diff --git a/.coveragerc b/.coveragerc
new file mode 100644
index 00000000000..ebf532a778c
--- /dev/null
+++ b/.coveragerc
@@ -0,0 +1,9 @@
+[run]
+omit =
+     */usr/local/lib*
+     */tools/test/*
+
+[report]
+omit =
+     */usr/local/lib*
+     */tools/test/*
\ No newline at end of file
diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md
index ca274f9b597..95211bb5116 100644
--- a/.github/pull_request_template.md
+++ b/.github/pull_request_template.md
@@ -1,22 +1,23 @@
 Notes:
-* Pull requests will not be accepted until the submitter has agreed to the [contributer agreement](https://github.com/ARMmbed/mbed-os/blob/master/CONTRIBUTING.md).
-* This is just a template, so feel free to use/remove the unnecessary things
+- Pull requests will not be accepted until the submitter has agreed to the [contributer agreement](https://github.com/ARMmbed/mbed-os/blob/master/CONTRIBUTING.md).
+- This is just a template, so feel free to use/remove the unnecessary things
 
 ## Description
-A few sentences describing the overall goals of the pull request's commits.
 
+A few sentences describing the overall goals of the pull request's commits.
 
 ## Status
-**READY/IN DEVELOPMENT/HOLD**
 
+**READY/IN DEVELOPMENT/HOLD**
 
 ## Migrations
+
 If this PR changes any APIs or behaviors, give a short description of what *API users* should do when this PR is merged.
 
 YES | NO
 
-
 ## Related PRs
+
 List related PRs against other branches:
 
 branch | PR
@@ -24,16 +25,15 @@ branch | PR
 other_pr_production | [link]()
 other_pr_master | [link]()
 
-
 ## Todos
+
 - [ ] Tests
 - [ ] Documentation
 
-
 ## Deploy notes
-Notes regarding the deployment of this PR. These should note any
-required changes in the build environment, tools, compilers, etc.
 
+Notes regarding the deployment of this PR. These should note any required changes in the build environment, tools, compilers and so on.
 
 ## Steps to test or reproduce
+
 Outline the steps to test or reproduce the PR here.
diff --git a/.travis.yml b/.travis.yml
index 0bd0e8a1855..3fecbafc4e9 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -1,6 +1,5 @@
 python:
   - "2.7"
-group: deprecated-2017Q3
 script:
   - mkdir BUILD
 # Assert that the Doxygen build produced no warnings.
@@ -36,10 +35,10 @@ before_install:
   - python --version
   - doxygen --version
 install:
-  - pip install -r requirements.txt
-  - pip install pytest
-  - pip install pylint
-  - pip install hypothesis
-  - pip install mock
-  - pip install coverage
-  - pip install coveralls
+  - pip install --user -r requirements.txt
+  - pip install --user pytest
+  - pip install --user pylint
+  - pip install --user hypothesis
+  - pip install --user mock
+  - pip install --user coverage
+  - pip install --user coveralls
diff --git a/TESTS/events/queue/main.cpp b/TESTS/events/queue/main.cpp
index f779ee0c24d..738fdd0d8dc 100644
--- a/TESTS/events/queue/main.cpp
+++ b/TESTS/events/queue/main.cpp
@@ -22,7 +22,10 @@
 
 using namespace utest::v1;
 
-#define TEST_EQUEUE_SIZE 1024
+// TEST_EQUEUE_SIZE was reduced below 1024B to fit this test to devices with small RAM (RAM <= 16kB)
+// additionally TEST_EQUEUE_SIZE was expressed in EVENTS_EVENT_SIZE to increase readability
+// (for more details about EVENTS_EVENT_SIZE see EventQueue constructor)
+#define TEST_EQUEUE_SIZE (18*EVENTS_EVENT_SIZE)
 
 // flag for called
 volatile bool touched = false;
diff --git a/TESTS/mbed_drivers/echo/main.cpp b/TESTS/mbed_drivers/echo/main.cpp
index 8e849c9dd04..6388299c401 100644
--- a/TESTS/mbed_drivers/echo/main.cpp
+++ b/TESTS/mbed_drivers/echo/main.cpp
@@ -26,13 +26,18 @@ using namespace utest::v1;
 // Echo server (echo payload to host)
 template<int N>
 void test_case_echo_server_x() {
-    char _key[10] = {};
+    char _key[11] = {};
     char _value[128] = {};
     const int echo_count = N;
+    const char _key_const[] = "echo_count";
+    int expected_key = 1;
 
+    greentea_send_kv(_key_const, echo_count);
     // Handshake with host
-    greentea_send_kv("echo_count", echo_count);
-    greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value));
+    do {
+        greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value));
+        expected_key = strcmp(_key_const, _key);
+    } while (expected_key);
     TEST_ASSERT_EQUAL_INT(echo_count, atoi(_value));
 
     for (int i=0; i < echo_count; ++i) {
@@ -48,12 +53,10 @@ utest::v1::status_t greentea_failure_handler(const Case *const source, const fai
 
 Case cases[] = {
     Case("Echo server: x16", test_case_echo_server_x<16>, greentea_failure_handler),
-    Case("Echo server: x32", test_case_echo_server_x<32>, greentea_failure_handler),
-    Case("Echo server: x64", test_case_echo_server_x<64>, greentea_failure_handler),
 };
 
 utest::v1::status_t greentea_test_setup(const size_t number_of_cases) {
-    GREENTEA_SETUP(180, "echo");
+    GREENTEA_SETUP(30, "echo");
     return greentea_test_setup_handler(number_of_cases);
 }
 
diff --git a/TESTS/mbed_drivers/lp_ticker/main.cpp b/TESTS/mbed_drivers/lp_ticker/main.cpp
new file mode 100644
index 00000000000..aeb36765f1a
--- /dev/null
+++ b/TESTS/mbed_drivers/lp_ticker/main.cpp
@@ -0,0 +1,221 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2013-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "utest/utest.h"
+#include "unity/unity.h"
+
+
+#if !DEVICE_LOWPOWERTIMER
+    #error [NOT_SUPPORTED] Low power ticker not supported for this target
+#endif
+
+using utest::v1::Case;
+
+static const int test_timeout = 10;
+
+#define TICKER_COUNT 16
+#define MULTI_TICKER_TIME_MS 100
+
+/* Due to poor accuracy of LowPowerTicker on many platforms
+   there is no sense to tune tolerance value as it was in Ticker tests.
+
+   Tolerance value is set to 2000us to cover this diversity */
+#define TOLERANCE_US 2000
+
+
+volatile uint32_t ticker_callback_flag;
+volatile uint32_t multi_counter;
+Timer gtimer;
+
+
+
+void sem_release(Semaphore *sem)
+{
+    sem->release();
+}
+
+
+void stop_gtimer_set_flag(void)
+{
+    gtimer.stop();
+    core_util_atomic_incr_u32((uint32_t*)&ticker_callback_flag, 1);
+}
+
+void increment_multi_counter(void)
+{
+    core_util_atomic_incr_u32((uint32_t*)&multi_counter, 1);;
+}
+
+/** Test many tickers run one after the other
+
+    Given many Tickers
+    When schedule them one after the other with the same time intervals
+    Then tickers properly execute callbacks
+    When schedule them one after the other with the different time intervals
+    Then tickers properly execute callbacks
+ */
+void test_multi_ticker(void)
+{
+    LowPowerTicker ticker[TICKER_COUNT];
+    const uint32_t extra_wait = 10; // extra 10ms wait time
+
+    multi_counter = 0;
+    for (int i = 0; i < TICKER_COUNT; i++) {
+        ticker[i].attach_us(callback(increment_multi_counter), MULTI_TICKER_TIME_MS * 1000);
+    }
+
+    Thread::wait(MULTI_TICKER_TIME_MS + extra_wait);
+    for (int i = 0; i < TICKER_COUNT; i++) {
+            ticker[i].detach();
+    }
+    TEST_ASSERT_EQUAL(TICKER_COUNT, multi_counter);
+
+    multi_counter = 0;
+    for (int i = 0; i < TICKER_COUNT; i++) {
+        ticker[i].attach_us(callback(increment_multi_counter), (MULTI_TICKER_TIME_MS + i) * 1000);
+    }
+
+    Thread::wait(MULTI_TICKER_TIME_MS + TICKER_COUNT + extra_wait);
+    for (int i = 0; i < TICKER_COUNT; i++) {
+        ticker[i].detach();
+    }
+    TEST_ASSERT_EQUAL(TICKER_COUNT, multi_counter);
+}
+
+/** Test multi callback time
+
+    Given a Ticker
+    When the callback is attached multiple times
+    Then ticker properly execute callback multiple times
+ */
+void test_multi_call_time(void)
+{
+    LowPowerTicker ticker;
+    int time_diff;
+    const int attach_count = 10;
+
+    for (int i = 0; i < attach_count; i++) {
+        ticker_callback_flag = 0;
+        gtimer.reset();
+
+        gtimer.start();
+        ticker.attach_us(callback(stop_gtimer_set_flag), MULTI_TICKER_TIME_MS * 1000);
+        while(!ticker_callback_flag);
+        time_diff = gtimer.read_us();
+
+        TEST_ASSERT_UINT32_WITHIN(TOLERANCE_US, MULTI_TICKER_TIME_MS * 1000, time_diff);
+    }
+}
+
+/** Test if detach cancel scheduled callback event
+
+    Given a Ticker with callback attached
+    When the callback is detached
+    Then the callback is not being called
+ */
+void test_detach(void)
+{
+    LowPowerTicker ticker;
+    int32_t ret;
+    const float ticker_time_s = 0.1f;
+    const uint32_t wait_time_ms = 500;
+    Semaphore sem(0, 1);
+
+    ticker.attach(callback(sem_release, &sem), ticker_time_s);
+
+    ret = sem.wait();
+    TEST_ASSERT_TRUE(ret > 0);
+
+    ret = sem.wait();
+    ticker.detach(); /* cancel */
+    TEST_ASSERT_TRUE(ret > 0);
+
+    ret = sem.wait(wait_time_ms);
+    TEST_ASSERT_EQUAL(0, ret);
+}
+
+/** Test single callback time via attach
+
+    Given a Ticker
+    When callback attached with time interval specified
+    Then ticker properly executes callback within a specified time interval
+ */
+template<us_timestamp_t DELAY_US>
+void test_attach_time(void)
+{
+    LowPowerTicker ticker;
+    ticker_callback_flag = 0;
+
+    gtimer.reset();
+    gtimer.start();
+    ticker.attach(callback(stop_gtimer_set_flag), ((float)DELAY_US) / 1000000.0f);
+    while(!ticker_callback_flag);
+    ticker.detach();
+    const int time_diff = gtimer.read_us();
+
+    TEST_ASSERT_UINT64_WITHIN(TOLERANCE_US, DELAY_US, time_diff);
+}
+
+/** Test single callback time via attach_us
+
+    Given a Ticker
+    When callback attached with time interval specified
+    Then ticker properly executes callback within a specified time interval
+ */
+template<us_timestamp_t DELAY_US>
+void test_attach_us_time(void)
+{
+    LowPowerTicker ticker;
+    ticker_callback_flag = 0;
+
+    gtimer.reset();
+    gtimer.start();
+    ticker.attach_us(callback(stop_gtimer_set_flag), DELAY_US);
+    while(!ticker_callback_flag);
+    ticker.detach();
+    const int time_diff = gtimer.read_us();
+
+    TEST_ASSERT_UINT64_WITHIN(TOLERANCE_US, DELAY_US, time_diff);
+}
+
+// Test cases
+Case cases[] = {
+    Case("Test attach for 0.001s and time measure", test_attach_time<1000>),
+    Case("Test attach_us for 1ms and time measure", test_attach_us_time<1000>),
+    Case("Test attach for 0.01s and time measure", test_attach_time<10000>),
+    Case("Test attach_us for 10ms and time measure", test_attach_us_time<10000>),
+    Case("Test attach for 0.1s and time measure", test_attach_time<100000>),
+    Case("Test attach_us for 100ms and time measure", test_attach_us_time<100000>),
+    Case("Test attach for 0.5s and time measure", test_attach_time<500000>),
+    Case("Test attach_us for 500ms and time measure", test_attach_us_time<500000>),
+    Case("Test detach", test_detach),
+    Case("Test multi call and time measure", test_multi_call_time),
+    Case("Test multi ticker", test_multi_ticker),
+};
+
+utest::v1::status_t greentea_test_setup(const size_t number_of_cases)
+{
+    GREENTEA_SETUP(test_timeout, "timing_drift_auto");
+    return utest::v1::greentea_test_setup_handler(number_of_cases);
+}
+
+utest::v1::Specification specification(greentea_test_setup, cases, utest::v1::greentea_test_teardown_handler);
+
+int main()
+{
+    utest::v1::Harness::run(specification);
+}
diff --git a/TESTS/mbed_drivers/lp_timeout/main.cpp b/TESTS/mbed_drivers/lp_timeout/main.cpp
index f3b5b63c6b7..9a16d6bdfbd 100644
--- a/TESTS/mbed_drivers/lp_timeout/main.cpp
+++ b/TESTS/mbed_drivers/lp_timeout/main.cpp
@@ -23,7 +23,6 @@
 #include "greentea-client/test_env.h"
 
 #include "mbed.h"
-#include "us_ticker_api.h"
 
 using namespace utest::v1;
 
@@ -42,6 +41,7 @@ void cb_done() {
 void lp_timeout_1s_deepsleep(void)
 {
     complete = false;
+    LowPowerTimer timer;
 
     /*
      * Since deepsleep() may shut down the UART peripheral, we wait for 10ms
@@ -54,33 +54,37 @@ void lp_timeout_1s_deepsleep(void)
     wait_ms(10);
 
     /*
-     * We use here lp_ticker_read() instead of us_ticker_read() for start and
+     * We use here the low power timer instead of microsecond timer for start and
      * end because the microseconds timer might be disable during deepsleep.
      */
-    timestamp_t start = lp_ticker_read();
+    timer.start();
     lpt.attach(&cb_done, 1);
-    deepsleep();
+    /* Make sure deepsleep is allowed, to go to deepsleep */
+    bool deep_sleep_allowed = sleep_manager_can_deep_sleep();
+    TEST_ASSERT_TRUE_MESSAGE(deep_sleep_allowed, "Deep sleep should be allowed");
+    sleep();
     while (!complete);
-    timestamp_t end = lp_ticker_read();
 
     /* It takes longer to wake up from deep sleep */
-    TEST_ASSERT_UINT32_WITHIN(LONG_TIMEOUT, 1000000, end - start);
+    TEST_ASSERT_UINT32_WITHIN(LONG_TIMEOUT, 1000000, timer.read_us());
     TEST_ASSERT_TRUE(complete);
 }
 
 void lp_timeout_1s_sleep(void)
 {
     complete = false;
+    Timer timer;
+    timer.start();
 
     sleep_manager_lock_deep_sleep();
-    timestamp_t start = us_ticker_read();
     lpt.attach(&cb_done, 1);
+    bool deep_sleep_allowed = sleep_manager_can_deep_sleep();
+    TEST_ASSERT_FALSE_MESSAGE(deep_sleep_allowed, "Deep sleep should be disallowed");
     sleep();
     while (!complete);
-    timestamp_t end = us_ticker_read();
     sleep_manager_unlock_deep_sleep();
 
-    TEST_ASSERT_UINT32_WITHIN(LONG_TIMEOUT, 1000000, end - start);
+    TEST_ASSERT_UINT32_WITHIN(LONG_TIMEOUT, 1000000, timer.read_us());
     TEST_ASSERT_TRUE(complete);
 }
 #endif /* DEVICE_SLEEP */
@@ -88,14 +92,14 @@ void lp_timeout_1s_sleep(void)
 void lp_timeout_us(uint32_t delay_us, uint32_t tolerance)
 {
     complete = false;
+    Timer timer;
+    timer.start();
 
-    timestamp_t start = us_ticker_read();
     lpt.attach_us(&cb_done, delay_us);
     while (!complete);
-    timestamp_t end = us_ticker_read();
 
     /* Using RTC which is less accurate */
-    TEST_ASSERT_UINT32_WITHIN(tolerance, delay_us, end - start);
+    TEST_ASSERT_UINT32_WITHIN(tolerance, delay_us, timer.read_us());
     TEST_ASSERT_TRUE(complete);
 }
 
diff --git a/TESTS/mbed_drivers/lp_timer/main.cpp b/TESTS/mbed_drivers/lp_timer/main.cpp
new file mode 100644
index 00000000000..bf3f09639e8
--- /dev/null
+++ b/TESTS/mbed_drivers/lp_timer/main.cpp
@@ -0,0 +1,348 @@
+/*
+ * Copyright (c) 2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "rtos.h"
+#include "hal/us_ticker_api.h"
+
+#if !DEVICE_LOWPOWERTIMER
+#error [NOT_SUPPORTED] test not supported
+#endif
+
+using namespace utest::v1;
+
+extern uint32_t SystemCoreClock;
+
+/* This test is created based on the test for Timer class.
+ * Since low power timer is less accurate than regular
+ * timer we need to adjust delta.
+ */
+
+/* Macro to define delta based on CPU clock frequency.
+ *
+ * Note that some extra time is counted by the timer.
+ * Additional time is caused by the function calls and
+ * additional operations performed by wait and
+ * stop functions before in fact timer is stopped. This may
+ * add additional time to the counted result.
+ *
+ * To take in to account this extra time we introduce DELTA
+ * value based on CPU clock (speed):
+ *   DELTA = TOLERANCE_FACTOR / SystemCoreClock * US_FACTOR
+ *
+ *   e.g.
+ *   For K64F          DELTA = (80000 / 120000000) * 1000000 = 666[us]
+ *   For NUCLEO_F070RB DELTA = (80000 /  48000000) * 1000000 = 1666[us]
+ *   For NRF51_DK      DELTA = (80000 /  16000000) * 1000000 = 5000[us]
+ */
+#define US_PER_SEC       1000000
+#define US_PER_MSEC      1000
+#define TOLERANCE_FACTOR 80000.0f
+#define US_FACTOR        1000000.0f
+
+static const int delta_sys_clk_us = ((int) (TOLERANCE_FACTOR / (float) SystemCoreClock * US_FACTOR));
+
+/* When test performs time measurement using Timer in sequence, then measurement error accumulates
+ * in the successive attempts. */
+ #define DELTA_US(i) (delta_sys_clk_us * i)
+ #define DELTA_S(i)  ((float)delta_sys_clk_us * i / US_PER_SEC)
+ #define DELTA_MS(i) (1 + ( (i * delta_sys_clk_us) / US_PER_MSEC))
+
+/* This test verifies if low power timer is stopped after
+ * creation.
+ *
+ * Given Timer has been successfully created.
+ * When read of timer elapsed time is requested.
+ * Then result is always 0.
+ */
+void test_lptimer_creation()
+{
+    LowPowerTimer lp_timer;
+
+    /* Check results. */
+    TEST_ASSERT_EQUAL_FLOAT(0, lp_timer.read());
+    TEST_ASSERT_EQUAL_INT32(0, lp_timer.read_ms());
+    TEST_ASSERT_EQUAL_INT32(0, lp_timer.read_us());
+    TEST_ASSERT_EQUAL_UINT64(0, lp_timer.read_high_resolution_us());
+
+    /* Wait 10 ms.
+     * After that operation timer read routines should still return 0. */
+    wait_ms(10);
+
+    /* Check results. */
+    TEST_ASSERT_EQUAL_FLOAT(0, lp_timer.read());
+    TEST_ASSERT_EQUAL_INT32(0, lp_timer.read_ms());
+    TEST_ASSERT_EQUAL_INT32(0, lp_timer.read_us());
+    TEST_ASSERT_EQUAL_UINT64(0, lp_timer.read_high_resolution_us());
+}
+
+/* This test verifies if read(), read_us(), read_ms(),
+ * read_high_resolution_us()
+ * functions return time accumulated between
+ * low power timer starts and stops.
+ *
+ * Given Timer has been successfully created and
+ * few times started and stopped after a specified period of time.
+ * When timer read request is performed.
+ * Then read functions return accumulated time elapsed between starts
+ * and stops.
+ */
+void test_lptimer_time_accumulation()
+{
+    LowPowerTimer lp_timer;
+
+    /* Start the timer. */
+    lp_timer.start();
+
+    /* Wait 10 ms. */
+    wait_ms(10);
+
+    /* Stop the timer. */
+    lp_timer.stop();
+
+    /* Check results - totally 10 ms have elapsed. */
+    TEST_ASSERT_FLOAT_WITHIN(DELTA_S(1), 0.010f, lp_timer.read());
+    TEST_ASSERT_INT32_WITHIN(DELTA_MS(1), 10, lp_timer.read_ms());
+    TEST_ASSERT_INT32_WITHIN(DELTA_US(1), 10000, lp_timer.read_us());
+    TEST_ASSERT_UINT64_WITHIN(DELTA_US(1), 10000, lp_timer.read_high_resolution_us());
+
+    /* Wait 50 ms - this is done to show that time elapsed when
+     * the timer is stopped does not have influence on the
+     * timer counted time. */
+    wait_ms(50);
+
+    /* ------ */
+
+    /* Start the timer. */
+    lp_timer.start();
+
+    /* Wait 20 ms. */
+    wait_ms(20);
+
+    /* Stop the timer. */
+    lp_timer.stop();
+
+    /* Check results - totally 30 ms have elapsed. */
+    TEST_ASSERT_FLOAT_WITHIN(DELTA_S(2), 0.030f, lp_timer.read());
+    TEST_ASSERT_INT32_WITHIN(DELTA_MS(2), 30, lp_timer.read_ms());
+    TEST_ASSERT_INT32_WITHIN(DELTA_US(2), 30000, lp_timer.read_us());
+    TEST_ASSERT_UINT64_WITHIN(DELTA_US(2), 30000, lp_timer.read_high_resolution_us());
+
+    /* Wait 50 ms - this is done to show that time elapsed when
+     * the timer is stopped does not have influence on the
+     * timer counted time. */
+
+    /* ------ */
+
+    /* Start the timer. */
+    lp_timer.start();
+
+    /* Wait 30 ms. */
+    wait_ms(30);
+
+    /* Stop the timer. */
+    lp_timer.stop();
+
+    /* Check results - totally 60 ms have elapsed. */
+    TEST_ASSERT_FLOAT_WITHIN(DELTA_S(3), 0.060f, lp_timer.read());
+    TEST_ASSERT_INT32_WITHIN(DELTA_MS(3), 60, lp_timer.read_ms());
+    TEST_ASSERT_INT32_WITHIN(DELTA_US(3), 60000, lp_timer.read_us());
+    TEST_ASSERT_UINT64_WITHIN(DELTA_US(3), 60000, lp_timer.read_high_resolution_us());
+
+    /* Wait 50 ms - this is done to show that time elapsed when
+     * the timer is stopped does not have influence on the
+     * timer time. */
+    wait_ms(50);
+
+    /* ------ */
+
+    /* Start the timer. */
+    lp_timer.start();
+
+    /* Wait 1 sec. */
+    wait_ms(1000);
+
+    /* Stop the timer. */
+    lp_timer.stop();
+
+    /* Check results - totally 1060 ms have elapsed. */
+    TEST_ASSERT_FLOAT_WITHIN(DELTA_S(4), 1.060f, lp_timer.read());
+    TEST_ASSERT_INT32_WITHIN(DELTA_MS(4), 1060, lp_timer.read_ms());
+    TEST_ASSERT_INT32_WITHIN(DELTA_US(4), 1060000, lp_timer.read_us());
+    TEST_ASSERT_UINT64_WITHIN(DELTA_US(4), 1060000, lp_timer.read_high_resolution_us());
+}
+
+/* This test verifies if reset() function resets the
+ * low power timer counted time.
+ *
+ * Given timer has been started and stopped once, then reset
+ * operation was performed.
+ * When timer is started and stopped next time.
+ * Then timer read functions returns only the the second
+ * measured time.
+ */
+void test_lptimer_reset()
+{
+    LowPowerTimer lp_timer;
+
+    /* First measure 10 ms delay. */
+    lp_timer.start();
+
+    /* Wait 10 ms. */
+    wait_ms(10);
+
+    /* Stop the timer. */
+    lp_timer.stop();
+
+    /* Check results - totally 10 ms elapsed. */
+    TEST_ASSERT_FLOAT_WITHIN(DELTA_S(1), 0.010f, lp_timer.read());
+    TEST_ASSERT_INT32_WITHIN(DELTA_MS(1), 10, lp_timer.read_ms());
+    TEST_ASSERT_INT32_WITHIN(DELTA_US(1), 10000, lp_timer.read_us());
+    TEST_ASSERT_UINT64_WITHIN(DELTA_US(1), 10000, lp_timer.read_high_resolution_us());
+
+    /* Reset the timer - previous measured time should be lost now. */
+    lp_timer.reset();
+
+    /* Now measure 20 ms delay. */
+    lp_timer.start();
+
+    /* Wait 20 ms. */
+    wait_ms(20);
+
+    /* Stop the timer. */
+    lp_timer.stop();
+
+    /* Check results - 20 ms elapsed since the reset. */
+    TEST_ASSERT_FLOAT_WITHIN(DELTA_S(1), 0.020f, lp_timer.read());
+    TEST_ASSERT_INT32_WITHIN(DELTA_MS(1), 20, lp_timer.read_ms());
+    TEST_ASSERT_INT32_WITHIN(DELTA_US(1), 20000, lp_timer.read_us());
+    TEST_ASSERT_UINT64_WITHIN(DELTA_US(1), 20000, lp_timer.read_high_resolution_us());
+}
+
+/* This test verifies if calling start() for already
+ * started low power timer does nothing.
+ *
+ * Given timer is already started.
+ * When timer is started again.
+ * Then second start operation is ignored.
+ */
+void test_lptimer_start_started_timer()
+{
+    LowPowerTimer lp_timer;
+
+    /* Start the timer. */
+    lp_timer.start();
+
+    /* Wait 10 ms. */
+    wait_ms(10);
+
+    /* Now start timer again. */
+    lp_timer.start();
+
+    /* Wait 20 ms. */
+    wait_ms(20);
+
+    /* Stop the timer. */
+    lp_timer.stop();
+
+    /* Check results - 30 ms have elapsed since the first start. */
+    TEST_ASSERT_FLOAT_WITHIN(DELTA_S(2), 0.030f, lp_timer.read());
+    TEST_ASSERT_INT32_WITHIN(DELTA_MS(2), 30, lp_timer.read_ms());
+    TEST_ASSERT_INT32_WITHIN(DELTA_US(2), 30000, lp_timer.read_us());
+    TEST_ASSERT_UINT64_WITHIN(DELTA_US(2), 30000, lp_timer.read_high_resolution_us());
+}
+
+/* This test verifies low power timer float operator.
+ *
+ * Given timer is created and a time period time is counted.
+ * When timer object is casted on float type.
+ * Then counted type in seconds is returned by means of
+ * read() function.
+ */
+void test_lptimer_float_operator()
+{
+    LowPowerTimer lp_timer;
+
+    /* Start the timer. */
+    lp_timer.start();
+
+    /* Wait 10 ms. */
+    wait_ms(10);
+
+    /* Stop the timer. */
+    lp_timer.stop();
+
+    /* Check result - 10 ms elapsed. */
+    TEST_ASSERT_FLOAT_WITHIN(DELTA_S(1), 0.010f, (float )(lp_timer));
+}
+
+/* This test verifies if time counted by the low power timer is
+ * valid.
+ *
+ * Given timer is created.
+ * When timer is used to measure 1ms/10ms/100ms/1s
+ * delays.
+ * Then the results are valid (within acceptable range).
+ */
+template<int wait_val_us>
+void test_lptimer_time_measurement()
+{
+    LowPowerTimer lp_timer;
+
+    /* Start the timer. */
+    lp_timer.start();
+
+    /* Wait <wait_val_us> us. */
+    wait_us(wait_val_us);
+
+    /* Stop the timer. */
+    lp_timer.stop();
+
+    /* Check results - wait_val_us us have elapsed. */
+    TEST_ASSERT_FLOAT_WITHIN(DELTA_S(1), (float )wait_val_us / 1000000, lp_timer.read());
+    TEST_ASSERT_INT32_WITHIN(DELTA_MS(1), wait_val_us / 1000, lp_timer.read_ms());
+    TEST_ASSERT_INT32_WITHIN(DELTA_US(1), wait_val_us, lp_timer.read_us());
+    TEST_ASSERT_UINT64_WITHIN(DELTA_US(1), wait_val_us, lp_timer.read_high_resolution_us());
+}
+
+utest::v1::status_t test_setup(const size_t number_of_cases)
+{
+    GREENTEA_SETUP(15, "default_auto");
+    return verbose_test_setup_handler(number_of_cases);
+}
+
+Case cases[] = {
+    Case("Test: LowPowerTimer - stopped after creation.", test_lptimer_creation),
+    Case("Test: LowPowerTimer - measure time accumulation.", test_lptimer_time_accumulation),
+    Case("Test: LowPowerTimer - reset.", test_lptimer_reset),
+    Case("Test: LowPowerTimer - start started timer.", test_lptimer_start_started_timer),
+    Case("Test: LowPowerTimer - float operator.", test_lptimer_float_operator),
+    Case("Test: LowPowerTimer - time measurement 1 ms.", test_lptimer_time_measurement<1000>),
+    Case("Test: LowPowerTimer - time measurement 10 ms.", test_lptimer_time_measurement<10000>),
+    Case("Test: LowPowerTimer - time measurement 100 ms.", test_lptimer_time_measurement<100000>),
+    Case("Test: LowPowerTimer - time measurement 1 s.", test_lptimer_time_measurement<1000000>)
+};
+
+Specification specification(test_setup, cases);
+
+int main()
+{
+    return !Harness::run(specification);
+}
diff --git a/TESTS/mbed_drivers/race_test/main.cpp b/TESTS/mbed_drivers/race_test/main.cpp
index c0a89ff8c5a..f4753f9bf40 100644
--- a/TESTS/mbed_drivers/race_test/main.cpp
+++ b/TESTS/mbed_drivers/race_test/main.cpp
@@ -68,21 +68,18 @@ static void main_class_race()
 void test_case_func_race()
 {
     Callback<void()> cb(main_func_race);
-    Thread *t1 = new Thread(osPriorityNormal, TEST_STACK_SIZE);
-    Thread *t2 = new Thread(osPriorityNormal, TEST_STACK_SIZE);
+    Thread t1(osPriorityNormal, TEST_STACK_SIZE);
+    Thread t2(osPriorityNormal, TEST_STACK_SIZE);
 
     // Start start first thread
-    t1->start(cb);
+    t1.start(cb);
     // Start second thread while the first is inside the constructor
     Thread::wait(250);
-    t2->start(cb);
+    t2.start(cb);
 
     // Wait for the threads to finish
-    t1->join();
-    t2->join();
-
-    delete t1;
-    delete t2;
+    t1.join();
+    t2.join();
 
     TEST_ASSERT_EQUAL_UINT32(1, instance_count);
 
@@ -93,21 +90,18 @@ void test_case_func_race()
 void test_case_class_race()
 {
     Callback<void()> cb(main_class_race);
-    Thread *t1 = new Thread(osPriorityNormal, TEST_STACK_SIZE);
-    Thread *t2 = new Thread(osPriorityNormal, TEST_STACK_SIZE);
+    Thread t1(osPriorityNormal, TEST_STACK_SIZE);
+    Thread t2(osPriorityNormal, TEST_STACK_SIZE);
 
     // Start start first thread
-    t1->start(cb);
+    t1.start(cb);
     // Start second thread while the first is inside the constructor
     Thread::wait(250);
-    t2->start(cb);
+    t2.start(cb);
 
     // Wait for the threads to finish
-    t1->join();
-    t2->join();
-
-    delete t1;
-    delete t2;
+    t1.join();
+    t2.join();
 
     TEST_ASSERT_EQUAL_UINT32(1, instance_count);
 
diff --git a/TESTS/mbed_drivers/sleep_lock/main.cpp b/TESTS/mbed_drivers/sleep_lock/main.cpp
new file mode 100644
index 00000000000..2e1bcbd80a2
--- /dev/null
+++ b/TESTS/mbed_drivers/sleep_lock/main.cpp
@@ -0,0 +1,132 @@
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if !DEVICE_SLEEP
+    #error [NOT_SUPPORTED] Sleep not supported for this target
+#endif
+
+#include "utest/utest.h"
+#include "unity/unity.h"
+#include "greentea-client/test_env.h"
+
+#include "mbed.h"
+
+using namespace utest::v1;
+
+void deep_sleep_lock_lock_test()
+{
+    TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep());
+    {
+        // Check basic usage works
+        DeepSleepLock lock;
+        TEST_ASSERT_EQUAL(false, sleep_manager_can_deep_sleep());
+    }
+
+    TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep());
+    {
+        // Check that unlock and lock change can deep sleep as expected
+        DeepSleepLock lock;
+        TEST_ASSERT_EQUAL(false, sleep_manager_can_deep_sleep());
+        lock.unlock();
+        TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep());
+        lock.lock();
+        TEST_ASSERT_EQUAL(false, sleep_manager_can_deep_sleep());
+    }
+
+    TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep());
+    {
+        // Check that unlock releases sleep based on count
+        DeepSleepLock lock;
+        lock.lock();
+        lock.lock();
+        lock.unlock();
+        TEST_ASSERT_EQUAL(false, sleep_manager_can_deep_sleep());
+    }
+
+    TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep());
+    {
+        // Check that unbalanced locks do not leave deep sleep locked
+        DeepSleepLock lock;
+        lock.lock();
+        TEST_ASSERT_EQUAL(false, sleep_manager_can_deep_sleep());
+    }
+    TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep());
+
+}
+
+void timer_lock_test()
+{
+    TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep());
+    {
+        // Just creating a timer object does not lock sleep
+        Timer timer;
+        TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep());
+    }
+
+    TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep());
+    {
+        // Starting a timer does lock sleep
+        Timer timer;
+        timer.start();
+        TEST_ASSERT_EQUAL(false, sleep_manager_can_deep_sleep());
+    }
+
+    TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep());
+    {
+        // Stopping a timer after starting it allows sleep
+        Timer timer;
+        timer.start();
+        timer.stop();
+        TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep());
+    }
+
+    TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep());
+    {
+        // Starting a timer multiple times still lets you sleep
+        Timer timer;
+        timer.start();
+        timer.start();
+    }
+    TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep());
+
+    TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep());
+    {
+        // Stopping a timer multiple times still lets you sleep
+        Timer timer;
+        timer.start();
+        timer.stop();
+        timer.stop();
+        TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep());
+    }
+    TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep());
+}
+
+Case cases[] = {
+    Case("DeepSleepLock lock test", deep_sleep_lock_lock_test),
+    Case("timer lock test", timer_lock_test),
+};
+
+utest::v1::status_t greentea_test_setup(const size_t number_of_cases) {
+    GREENTEA_SETUP(20, "default_auto");
+    return greentea_test_setup_handler(number_of_cases);
+}
+
+Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler);
+
+int main() {
+    Harness::run(specification);
+}
diff --git a/TESTS/mbed_drivers/stats/main.cpp b/TESTS/mbed_drivers/stats/main.cpp
index 2d5404d0d55..b99adead2f1 100644
--- a/TESTS/mbed_drivers/stats/main.cpp
+++ b/TESTS/mbed_drivers/stats/main.cpp
@@ -22,7 +22,7 @@
 #include <stdlib.h>
 #include <stdio.h>
 
-#if !defined(MBED_HEAP_STATS_ENABLED) || !MBED_HEAP_STATS_ENABLED || defined(__ICCARM__)
+#if !defined(MBED_HEAP_STATS_ENABLED)
   #error [NOT_SUPPORTED] test not supported
 #endif
 
diff --git a/TESTS/mbed_drivers/ticker/main.cpp b/TESTS/mbed_drivers/ticker/main.cpp
index b9ae733bf2d..abbcdb32eac 100644
--- a/TESTS/mbed_drivers/ticker/main.cpp
+++ b/TESTS/mbed_drivers/ticker/main.cpp
@@ -1,51 +1,46 @@
-/*
- * Copyright (c) 2013-2016, ARM Limited, All Rights Reserved
- * SPDX-License-Identifier: Apache-2.0
+/* mbed Microcontroller Library
+ * Copyright (c) 2013-2017 ARM Limited
  *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- * http://www.apache.org/licenses/LICENSE-2.0
+ *     http://www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
-
-
-/*
- * Tests is to measure the accuracy of Ticker over a period of time
- *
- *
- * 1) DUT would start to update callback_trigger_count every milli sec, in 2x callback we use 2 tickers
- *    to update the count alternatively.
- * 2) Host would query what is current count base_time, Device responds by the callback_trigger_count
- * 3) Host after waiting for measurement stretch. It will query for device time again final_time.
- * 4) Host computes the drift considering base_time, final_time, transport delay and measurement stretch
- * 5) Finally host send the results back to device pass/fail based on tolerance.
- * 6) More details on tests can be found in timing_drift_auto.py
- */
-
 #include "mbed.h"
 #include "greentea-client/test_env.h"
 #include "utest/utest.h"
 #include "unity/unity.h"
 
-using namespace utest::v1;
+
+using utest::v1::Case;
 
 #define ONE_MILLI_SEC 1000
+#define TICKER_COUNT 16
+#define MULTI_TICKER_TIME_MS 100
 volatile uint32_t callback_trigger_count = 0;
 static const int test_timeout = 240;
 static const int total_ticks = 10;
 
+
+/* Tolerance is quite arbitrary due to large number of boards with varying level of accuracy */
+#define TOLERANCE_US 1000
+
+volatile uint32_t ticker_callback_flag;
+volatile uint32_t multi_counter;
+
 DigitalOut led1(LED1);
 DigitalOut led2(LED2);
 
-Ticker *ticker1;
-Ticker *ticker2;
+Ticker *volatile ticker1;
+Ticker *volatile ticker2;
+Timer gtimer;
 
 volatile int ticker_count = 0;
 volatile bool print_tick = false;
@@ -53,50 +48,80 @@ volatile bool print_tick = false;
 void ticker_callback_1_switch_to_2(void);
 void ticker_callback_2_switch_to_1(void);
 
-void ticker_callback_0(void) {
+void increment_ticker_counter(void)
+{
     ++callback_trigger_count;
 }
 
-void ticker_callback_1_led(void) {
+void switch_led1_state(void)
+{
     led1 = !led1;
 }
 
-void ticker_callback_2_led(void) {
+void switch_led2_state(void)
+{
     led2 = !led2;
 }
 
-void ticker_callback_1_switch_to_2(void) {
+void ticker_callback_1_switch_to_2(void)
+{
     ++callback_trigger_count;
-    ticker1->detach();
-    ticker1->attach_us(ticker_callback_2_switch_to_1, ONE_MILLI_SEC);
-    ticker_callback_1_led();
+    // If ticker is NULL then it is being or has been deleted
+    if (ticker1) {
+        ticker1->detach();
+        ticker1->attach_us(ticker_callback_2_switch_to_1, ONE_MILLI_SEC);
+    }
+    switch_led1_state();
 }
 
-void ticker_callback_2_switch_to_1(void) {
+void ticker_callback_2_switch_to_1(void)
+{
     ++callback_trigger_count;
-    ticker2->detach();
-    ticker2->attach_us(ticker_callback_1_switch_to_2, ONE_MILLI_SEC);
-    ticker_callback_2_led();
+    // If ticker is NULL then it is being or has been deleted
+    if (ticker2) {
+        ticker2->detach();
+        ticker2->attach_us(ticker_callback_1_switch_to_2, ONE_MILLI_SEC);
+    }
+    switch_led2_state();
 }
 
-void wait_and_print() {
-    while (ticker_count <= total_ticks) {
-        if (print_tick) {
-            print_tick = false;
-            greentea_send_kv("tick", ticker_count++);
-        }
-    }
+
+void sem_release(Semaphore *sem)
+{
+    sem->release();
 }
 
-void test_case_1x_ticker() {
 
+void stop_gtimer_set_flag(void)
+{
+    gtimer.stop();
+    core_util_atomic_incr_u32((uint32_t*)&ticker_callback_flag, 1);
+}
+
+void increment_multi_counter(void)
+{
+    core_util_atomic_incr_u32((uint32_t*)&multi_counter, 1);
+}
+
+
+/* Tests is to measure the accuracy of Ticker over a period of time
+ *
+ * 1) DUT would start to update callback_trigger_count every milli sec, in 2x callback we use 2 tickers
+ *    to update the count alternatively.
+ * 2) Host would query what is current count base_time, Device responds by the callback_trigger_count
+ * 3) Host after waiting for measurement stretch. It will query for device time again final_time.
+ * 4) Host computes the drift considering base_time, final_time, transport delay and measurement stretch
+ * 5) Finally host send the results back to device pass/fail based on tolerance.
+ * 6) More details on tests can be found in timing_drift_auto.py
+ */
+void test_case_1x_ticker()
+{
     char _key[11] = { };
     char _value[128] = { };
-    uint8_t results_size = 0;
     int expected_key = 1;
 
     greentea_send_kv("timing_drift_check_start", 0);
-    ticker1->attach_us(&ticker_callback_0, ONE_MILLI_SEC);
+    ticker1->attach_us(&increment_ticker_counter, ONE_MILLI_SEC);
 
     // wait for 1st signal from host
     do {
@@ -113,13 +138,12 @@ void test_case_1x_ticker() {
     greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value));
 
     TEST_ASSERT_EQUAL_STRING_MESSAGE("pass", _key,"Host side script reported a fail...");
-
 }
 
-void test_case_2x_callbacks() {
+void test_case_2x_callbacks()
+{
     char _key[11] = { };
     char _value[128] = { };
-    uint8_t results_size = 0;
     int expected_key =  1;
 
     led1 = 0;
@@ -144,44 +168,198 @@ void test_case_2x_callbacks() {
     greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value));
 
     TEST_ASSERT_EQUAL_STRING_MESSAGE("pass", _key,"Host side script reported a fail...");
+}
+
+/** Test many tickers run one after the other
+
+    Given many Tickers
+    When schedule them one after the other with the same time intervals
+    Then tickers properly execute callbacks
+    When schedule them one after the other with the different time intervals
+    Then tickers properly execute callbacks
+ */
+void test_multi_ticker(void)
+{
+    Ticker ticker[TICKER_COUNT];
+    const uint32_t extra_wait = 5; // extra 5ms wait time
+
+    multi_counter = 0;
+    for (int i = 0; i < TICKER_COUNT; i++) {
+        ticker[i].attach_us(callback(increment_multi_counter), MULTI_TICKER_TIME_MS * 1000);
+    }
+
+    Thread::wait(MULTI_TICKER_TIME_MS + extra_wait);
+    for (int i = 0; i < TICKER_COUNT; i++) {
+            ticker[i].detach();
+    }
+    TEST_ASSERT_EQUAL(TICKER_COUNT, multi_counter);
+
+    multi_counter = 0;
+    for (int i = 0; i < TICKER_COUNT; i++) {
+        ticker[i].attach_us(callback(increment_multi_counter), (MULTI_TICKER_TIME_MS + i) * 1000);
+    }
 
+    Thread::wait(MULTI_TICKER_TIME_MS + TICKER_COUNT + extra_wait);
+    for (int i = 0; i < TICKER_COUNT; i++) {
+        ticker[i].detach();
+    }
+    TEST_ASSERT_EQUAL(TICKER_COUNT, multi_counter);
 }
 
-utest::v1::status_t one_ticker_case_setup_handler_t(const Case *const source, const size_t index_of_case) {
+/** Test multi callback time
+
+    Given a Ticker
+    When the callback is attached multiple times
+    Then ticker properly execute callback multiple times
+ */
+void test_multi_call_time(void)
+{
+    Ticker ticker;
+    int time_diff;
+    const int attach_count = 10;
+
+    for (int i = 0; i < attach_count; i++) {
+        ticker_callback_flag = 0;
+        gtimer.reset();
+
+        gtimer.start();
+        ticker.attach_us(callback(stop_gtimer_set_flag), MULTI_TICKER_TIME_MS * 1000);
+        while(!ticker_callback_flag);
+        time_diff = gtimer.read_us();
+
+        TEST_ASSERT_UINT32_WITHIN(TOLERANCE_US, MULTI_TICKER_TIME_MS * 1000, time_diff);
+    }
+}
+
+/** Test if detach cancel scheduled callback event
+
+    Given a Ticker with callback attached
+    When the callback is detached
+    Then the callback is not being called
+ */
+void test_detach(void)
+{
+    Ticker ticker;
+    int32_t ret;
+    const float ticker_time_s = 0.1f;
+    const uint32_t wait_time_ms = 500;
+    Semaphore sem(0, 1);
+
+    ticker.attach(callback(sem_release, &sem), ticker_time_s);
+
+    ret = sem.wait();
+    TEST_ASSERT_TRUE(ret > 0);
+
+    ret = sem.wait();
+    ticker.detach(); /* cancel */
+    TEST_ASSERT_TRUE(ret > 0);
+
+    ret = sem.wait(wait_time_ms);
+    TEST_ASSERT_EQUAL(0, ret);
+}
+
+/** Test single callback time via attach
+
+    Given a Ticker
+    When callback attached with time interval specified
+    Then ticker properly executes callback within a specified time interval
+ */
+template<us_timestamp_t DELAY_US>
+void test_attach_time(void)
+{
+    Ticker ticker;
+    ticker_callback_flag = 0;
+
+    gtimer.reset();
+    gtimer.start();
+    ticker.attach(callback(stop_gtimer_set_flag), ((float)DELAY_US) / 1000000.0f);
+    while(!ticker_callback_flag);
+    ticker.detach();
+    const int time_diff = gtimer.read_us();
+
+    TEST_ASSERT_UINT64_WITHIN(TOLERANCE_US, DELAY_US, time_diff);
+}
+
+/** Test single callback time via attach_us
+
+    Given a Ticker
+    When callback attached with time interval specified
+    Then ticker properly executes callback within a specified time interval
+ */
+template<us_timestamp_t DELAY_US>
+void test_attach_us_time(void)
+{
+    Ticker ticker;
+    ticker_callback_flag = 0;
+
+    gtimer.reset();
+    gtimer.start();
+    ticker.attach_us(callback(stop_gtimer_set_flag), DELAY_US);
+    while(!ticker_callback_flag);
+    ticker.detach();
+    const int time_diff = gtimer.read_us();
+
+    TEST_ASSERT_UINT64_WITHIN(TOLERANCE_US, DELAY_US, time_diff);
+}
+
+
+utest::v1::status_t one_ticker_case_setup_handler_t(const Case *const source, const size_t index_of_case)
+{
     ticker1 = new Ticker();
     return greentea_case_setup_handler(source, index_of_case);
 }
 
-utest::v1::status_t two_ticker_case_setup_handler_t(const Case *const source, const size_t index_of_case) {
+utest::v1::status_t two_ticker_case_setup_handler_t(const Case *const source, const size_t index_of_case)
+{
     ticker1 = new Ticker();
     ticker2 = new Ticker();
-    return greentea_case_setup_handler(source, index_of_case);
+    return utest::v1::greentea_case_setup_handler(source, index_of_case);
 }
 
-utest::v1::status_t one_ticker_case_teardown_handler_t(const Case *const source, const size_t passed, const size_t failed, const failure_t reason) {
-    delete ticker1;
-    return greentea_case_teardown_handler(source, passed, failed, reason);
+utest::v1::status_t one_ticker_case_teardown_handler_t(const Case *const source, const size_t passed, const size_t failed, const utest::v1::failure_t reason)
+{
+    Ticker *temp1 = ticker1;
+    ticker1 = NULL;
+    delete temp1;
+    return utest::v1::greentea_case_teardown_handler(source, passed, failed, reason);
 }
 
-utest::v1::status_t two_ticker_case_teardown_handler_t(const Case *const source, const size_t passed, const size_t failed, const failure_t reason) {
-    delete ticker1;
-    delete ticker2;
-    return greentea_case_teardown_handler(source, passed, failed, reason);
+utest::v1::status_t two_ticker_case_teardown_handler_t(const Case *const source, const size_t passed, const size_t failed, const utest::v1::failure_t reason)
+{
+    Ticker *temp1 = ticker1;
+    Ticker *temp2 = ticker2;
+    ticker1 = NULL;
+    ticker2 = NULL;
+    delete temp1;
+    delete temp2;
+    return utest::v1::greentea_case_teardown_handler(source, passed, failed, reason);
 }
 
+
 // Test cases
 Case cases[] = {
-    Case("Timers: 1x ticker", one_ticker_case_setup_handler_t,test_case_1x_ticker, one_ticker_case_teardown_handler_t),
-    Case("Timers: 2x callbacks", two_ticker_case_setup_handler_t,test_case_2x_callbacks, two_ticker_case_teardown_handler_t),
+    Case("Test attach for 0.01s and time measure", test_attach_time<10000>),
+    Case("Test attach_us for 10ms and time measure", test_attach_us_time<10000>),
+    Case("Test attach for 0.1s and time measure", test_attach_time<100000>),
+    Case("Test attach_us for 100ms and time measure", test_attach_us_time<100000>),
+    Case("Test attach for 0.5s and time measure", test_attach_time<500000>),
+    Case("Test attach_us for 500ms and time measure", test_attach_us_time<500000>),
+    Case("Test detach", test_detach),
+    Case("Test multi call and time measure", test_multi_call_time),
+    Case("Test multi ticker", test_multi_ticker),
+    Case("Test timers: 1x ticker", one_ticker_case_setup_handler_t,test_case_1x_ticker, one_ticker_case_teardown_handler_t),
+    Case("Test timers: 2x callbacks", two_ticker_case_setup_handler_t,test_case_2x_callbacks, two_ticker_case_teardown_handler_t)
 };
 
-utest::v1::status_t greentea_test_setup(const size_t number_of_cases) {
+utest::v1::status_t greentea_test_setup(const size_t number_of_cases)
+{
     GREENTEA_SETUP(test_timeout, "timing_drift_auto");
-    return greentea_test_setup_handler(number_of_cases);
+    return utest::v1::greentea_test_setup_handler(number_of_cases);
 }
 
-Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler);
+utest::v1::Specification specification(greentea_test_setup, cases, utest::v1::greentea_test_teardown_handler);
 
-int main() {
-    Harness::run(specification);
+int main()
+{
+    utest::v1::Harness::run(specification);
 }
diff --git a/TESTS/mbed_drivers/timer/main.cpp b/TESTS/mbed_drivers/timer/main.cpp
new file mode 100644
index 00000000000..4f58ed2ef20
--- /dev/null
+++ b/TESTS/mbed_drivers/timer/main.cpp
@@ -0,0 +1,757 @@
+/*
+ * Copyright (c) 2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "rtos.h"
+#include "hal/us_ticker_api.h"
+
+using namespace utest::v1;
+
+extern uint32_t SystemCoreClock;
+
+/* Macro to define delta based on CPU clock frequency.
+ *
+ * Note that some extra time is counted by the timer.
+ * Additional time is caused by the function calls and
+ * additional operations performed by wait and
+ * stop functions before in fact timer is stopped. This may
+ * add additional time to the counted result.
+ *
+ * To take in to account this extra time we introduce DELTA
+ * value based on CPU clock (speed):
+ *   DELTA = TOLERANCE_FACTOR / SystemCoreClock * US_FACTOR
+ *
+ *   e.g.
+ *   For K64F          DELTA = (30000 / 120000000) * 1000000 = 250[us]
+ *   For NUCLEO_F070RB DELTA = (30000 /  48000000) * 1000000 = 625[us]
+ *   For NRF51_DK      DELTA = (30000 /  16000000) * 1000000 = 1875[us]
+ */
+#define US_PER_SEC       1000000
+#define US_PER_MSEC      1000
+#define TOLERANCE_FACTOR 30000.0f
+#define US_FACTOR        1000000.0f
+
+static const int delta_sys_clk_us = ((int) (TOLERANCE_FACTOR / (float)SystemCoreClock * US_FACTOR));
+
+/* When test performs time measurement using Timer in sequence, then measurement error accumulates
+ * in the successive attempts. */
+ #define DELTA_US(i) (delta_sys_clk_us * i)
+ #define DELTA_S(i)  ((float)delta_sys_clk_us * i / US_PER_SEC)
+ #define DELTA_MS(i) (1 + ( (i * delta_sys_clk_us) / US_PER_MSEC))
+
+static Timer *p_timer = NULL;
+
+/* Global variable used to simulate passage of time
+ * in case when timer which uses user ticker is tested.
+ */
+static uint32_t curr_ticker_us_val;
+
+/* User ticker interface function. */
+static void stub_interface_init()
+{
+    /* do nothing. */
+}
+
+/* User ticker interface function - only this
+ * ticker interface function is used by Timer API. */
+static uint32_t stub_ticker_read(void)
+{
+    /* Simulate elapsed time. */
+    return curr_ticker_us_val;
+}
+
+/* User ticker interface function. */
+static void stub_disable_interrupt(void)
+{
+    /* do nothing. */
+}
+
+/* User ticker interface function. */
+static void stub_clear_interrupt(void)
+{
+    /* do nothing. */
+}
+
+/* User ticker interface function. */
+static void stub_set_interrupt(timestamp_t timestamp)
+{
+    /* do nothing. */
+}
+
+/* User ticker interface function. */
+static void stub_fire_interrupt(void)
+{
+    /* do nothing. */
+}
+
+/* User ticker event queue. */
+static ticker_event_queue_t my_events = { 0 };
+
+/* User ticker interface data. */
+static const ticker_interface_t us_interface = {
+    .init = stub_interface_init,
+    .read = stub_ticker_read, /* Only this function is used by the Timer. */
+    .disable_interrupt = stub_disable_interrupt,
+    .clear_interrupt = stub_clear_interrupt,
+    .set_interrupt = stub_set_interrupt,
+    .fire_interrupt = stub_fire_interrupt,
+};
+
+/* User ticker data structure. */
+static const ticker_data_t us_data = {
+    .interface = &us_interface,
+    .queue = &my_events
+};
+
+/* Function which returns user ticker data. */
+const ticker_data_t* get_user_ticker_data(void)
+{
+    return &us_data;
+}
+
+/* Initialisation of the Timer object which uses
+ * ticker data provided by the user.
+ *
+ * */
+utest::v1::status_t timer_user_ticker_setup_handler(const Case *const source, const size_t index_of_case)
+{
+    p_timer = new Timer(get_user_ticker_data());
+
+    /* Check if Timer object has been created. */
+    TEST_ASSERT_NOT_NULL(p_timer);
+
+    return greentea_case_setup_handler(source, index_of_case);
+}
+
+/* Initialisation of the Timer object which uses
+ * default os ticker data.
+ *
+ * */
+utest::v1::status_t timer_os_ticker_setup_handler(const Case *const source, const size_t index_of_case)
+{
+    p_timer = new Timer();
+
+    /* Check if Timer object has been created. */
+    TEST_ASSERT_NOT_NULL(p_timer);
+
+    return greentea_case_setup_handler(source, index_of_case);
+}
+
+/* Test finalisation.
+ *
+ * */
+utest::v1::status_t cleanup_handler(const Case *const source, const size_t passed, const size_t failed, const failure_t reason)
+{
+    delete p_timer;
+
+    p_timer = NULL;
+
+    return greentea_case_teardown_handler(source, passed, failed, reason);
+}
+
+/* This test verifies if timer is stopped after
+ * creation.
+ *
+ * Note: this function assumes that Timer uses os ticker.
+ *
+ * Given Timer has been successfully created.
+ * When read of timer elapsed time is requested.
+ * Then result is always 0.
+ */
+void test_timer_creation_os_ticker()
+{
+    /* Check results. */
+    TEST_ASSERT_EQUAL_FLOAT(0, p_timer->read());
+    TEST_ASSERT_EQUAL_INT32(0, p_timer->read_ms());
+    TEST_ASSERT_EQUAL_INT32(0, p_timer->read_us());
+    TEST_ASSERT_EQUAL_UINT64(0, p_timer->read_high_resolution_us());
+
+    /* Wait 10 ms.
+     * After that operation timer read routines should still return 0. */
+    wait_ms(10);
+
+    /* Check results. */
+    TEST_ASSERT_EQUAL_FLOAT(0, p_timer->read());
+    TEST_ASSERT_EQUAL_INT32(0, p_timer->read_ms());
+    TEST_ASSERT_EQUAL_INT32(0, p_timer->read_us());
+    TEST_ASSERT_EQUAL_UINT64(0, p_timer->read_high_resolution_us());
+}
+
+/* This test verifies if timer is stopped after
+ * creation.
+ *
+ * Note: this function assumes that Timer uses user/fake ticker
+ * which returns time value provided in curr_ticker_us_val
+ * global variable.
+ *
+ * Given Timer has been successfully created.
+ * When read of timer elapsed time is requested.
+ * Then result is always 0.
+ */
+void test_timer_creation_user_ticker()
+{
+    /* For timer which is using user ticker simulate timer
+     * creation time (irrelevant in case of os ticker). */
+    curr_ticker_us_val = 10000;
+
+    /* Check results. */
+    TEST_ASSERT_EQUAL_FLOAT(0, p_timer->read());
+    TEST_ASSERT_EQUAL_INT32(0, p_timer->read_ms());
+    TEST_ASSERT_EQUAL_INT32(0, p_timer->read_us());
+    TEST_ASSERT_EQUAL_UINT64(0, p_timer->read_high_resolution_us());
+
+    /* Simulate that 10 ms has elapsed.
+     * After that operation timer read routines should still return 0. */
+    curr_ticker_us_val += 10000;
+
+    /* Check results. */
+    TEST_ASSERT_EQUAL_FLOAT(0, p_timer->read());
+    TEST_ASSERT_EQUAL_INT32(0, p_timer->read_ms());
+    TEST_ASSERT_EQUAL_INT32(0, p_timer->read_us());
+    TEST_ASSERT_EQUAL_UINT64(0, p_timer->read_high_resolution_us());
+}
+
+/* This test verifies verifies if read(), read_us(), read_ms(),
+ * read_high_resolution_us() functions returns valid values.
+ *
+ * Note: this function assumes that Timer uses user/fake ticker
+ * which returns time value provided in curr_ticker_us_val
+ * global variable.
+ *
+ * Given Timer has been successfully created and
+ * few times started and stopped after a specified period of time.
+ * When timer read request is performed.
+ * Then read functions return accumulated time elapsed between starts
+ * and stops.
+ */
+void test_timer_time_accumulation_user_ticker()
+{
+    /* Simulate that current time is equal to 0 us. */
+    curr_ticker_us_val = 0;
+
+    /* Start the timer. */
+    p_timer->start();
+
+    /* -- Simulate that current time is equal to 1 us -- */
+    curr_ticker_us_val = 1;
+
+    /* Stop the timer. */
+    p_timer->stop();
+
+    /* Check results - 1 us has elapsed. */
+    TEST_ASSERT_EQUAL_FLOAT(0.000001f, p_timer->read());
+    TEST_ASSERT_EQUAL_INT32(0, p_timer->read_ms());
+    TEST_ASSERT_EQUAL_INT32(1, p_timer->read_us());
+    TEST_ASSERT_EQUAL_UINT64(1, p_timer->read_high_resolution_us());
+
+    /* Simulate that 100 us has elapsed between stop and start. */
+    curr_ticker_us_val = 101;
+
+    /* Start the timer. */
+    p_timer->start();
+
+    /* -- Simulate that current time is equal to 225 us -- */
+    curr_ticker_us_val = 225;
+
+    /* Stop the timer. */
+    p_timer->stop();
+
+    /* Check results - 125 us have elapsed. */
+    TEST_ASSERT_EQUAL_FLOAT(0.000125f, p_timer->read());
+    TEST_ASSERT_EQUAL_INT32(0, p_timer->read_ms());
+    TEST_ASSERT_EQUAL_INT32(125, p_timer->read_us());
+    TEST_ASSERT_EQUAL_UINT64(125, p_timer->read_high_resolution_us());
+
+    /* Simulate that 100 us has elapsed between stop and start. */
+    curr_ticker_us_val = 325;
+
+    /* Start the timer. */
+    p_timer->start();
+
+    /* -- Simulate that current time is equal to 1200 us -- */
+    curr_ticker_us_val = 1200;
+
+    /* Stop the timer. */
+    p_timer->stop();
+
+    /* Check results - 1 ms has elapsed. */
+    TEST_ASSERT_EQUAL_FLOAT(0.001000f, p_timer->read());
+    TEST_ASSERT_EQUAL_INT32(1, p_timer->read_ms());
+    TEST_ASSERT_EQUAL_INT32(1000, p_timer->read_us());
+    TEST_ASSERT_EQUAL_UINT64(1000, p_timer->read_high_resolution_us());
+
+    /* Simulate that 100 us has elapsed between stop and start. */
+    curr_ticker_us_val = 1300;
+
+    /* Start the timer. */
+    p_timer->start();
+
+    /* -- Simulate that current time is equal to 125300 us -- */
+    curr_ticker_us_val = 125300;
+
+    /* Stop the timer. */
+    p_timer->stop();
+
+    /* Check results - 125 ms have elapsed. */
+    TEST_ASSERT_EQUAL_FLOAT(0.125000f, p_timer->read());
+    TEST_ASSERT_EQUAL_INT32(125, p_timer->read_ms());
+    TEST_ASSERT_EQUAL_INT32(125000, p_timer->read_us());
+    TEST_ASSERT_EQUAL_UINT64(125000, p_timer->read_high_resolution_us());
+
+    /* Simulate that 100 us has elapsed between stop and start. */
+    curr_ticker_us_val = 125400;
+
+    /* Start the timer. */
+    p_timer->start();
+
+    /* -- Simulate that current time is equal to 1000400 us -- */
+    curr_ticker_us_val = 1000400;
+
+    /* Stop the timer. */
+    p_timer->stop();
+
+    /* Check results - 1 s has elapsed. */
+    TEST_ASSERT_EQUAL_FLOAT(1.000000f, p_timer->read());
+    TEST_ASSERT_EQUAL_INT32(1000, p_timer->read_ms());
+    TEST_ASSERT_EQUAL_INT32(1000000, p_timer->read_us());
+    TEST_ASSERT_EQUAL_UINT64(1000000, p_timer->read_high_resolution_us());
+
+    /* Simulate that 100 us has elapsed between stop and start. */
+    curr_ticker_us_val = 1000500;
+
+    /* Start the timer. */
+    p_timer->start();
+
+    /* -- Simulate that current time is equal to 125000500 us -- */
+    curr_ticker_us_val = 125000500;
+
+    /* Stop the timer. */
+    p_timer->stop();
+
+    /* Check results - 125 s have elapsed. */
+    TEST_ASSERT_EQUAL_FLOAT(125.000000f, p_timer->read());
+    TEST_ASSERT_EQUAL_INT32(125000, p_timer->read_ms());
+    TEST_ASSERT_EQUAL_INT32(125000000, p_timer->read_us());
+    TEST_ASSERT_EQUAL_UINT64(125000000, p_timer->read_high_resolution_us());
+
+    /* Simulate that 100 us has elapsed between stop and start. */
+    curr_ticker_us_val = 125000600;
+
+    /* Start the timer. */
+    p_timer->start();
+
+    /* -- Simulate that current time is equal to MAX_INT_32 us + 600 us (delays
+     *    between stops and starts) -- */
+
+    /* Note that ticker is based on unsigned 32-bit int microsecond counters
+     * while timers are based on 32-bit signed int microsecond counters,
+     * so timers can only count up to a maximum of 2^31-1 microseconds i.e.
+     * 2147483647 us (about 35 minutes). */
+    curr_ticker_us_val = 2147484247;
+
+    /* Stop the timer. */
+    p_timer->stop();
+
+    /* Check results - 2147483647 (MAX_INT_32) us have elapsed. */
+    TEST_ASSERT_EQUAL_FLOAT(2147.483647f, p_timer->read());
+    TEST_ASSERT_EQUAL_INT32(2147483, p_timer->read_ms());
+    TEST_ASSERT_EQUAL_INT32(2147483647, p_timer->read_us());
+    TEST_ASSERT_EQUAL_UINT64(2147483647, p_timer->read_high_resolution_us());
+}
+
+/* This test verifies if read(), read_us(), read_ms(),
+ * read_high_resolution_us()
+ * functions return time accumulated between
+ * timer starts and stops.
+ *
+ * Note this function assumes that Timer uses os ticker.
+ *
+ * Given Timer has been successfully created and
+ * few times started and stopped after a specified period of time.
+ * When timer read request is performed.
+ * Then read functions return accumulated time elapsed between starts
+ * and stops.
+ */
+void test_timer_time_accumulation_os_ticker()
+{
+    /* Start the timer. */
+    p_timer->start();
+
+    /* Wait 10 ms. */
+    wait_ms(10);
+
+    /* Stop the timer. */
+    p_timer->stop();
+
+    /* Check results - totally 10 ms have elapsed. */
+    TEST_ASSERT_FLOAT_WITHIN(DELTA_S(1), 0.010f, p_timer->read());
+    TEST_ASSERT_INT32_WITHIN(DELTA_MS(1), 10, p_timer->read_ms());
+    TEST_ASSERT_INT32_WITHIN(DELTA_US(1), 10000, p_timer->read_us());
+    TEST_ASSERT_UINT64_WITHIN(DELTA_US(1), 10000, p_timer->read_high_resolution_us());
+
+    /* Wait 50 ms - this is done to show that time elapsed when
+     * the timer is stopped does not have influence on the
+     * timer counted time. */
+    wait_ms(50);
+
+    /* ------ */
+
+    /* Start the timer. */
+    p_timer->start();
+
+    /* Wait 20 ms. */
+    wait_ms(20);
+
+    /* Stop the timer. */
+    p_timer->stop();
+
+    /* Check results - totally 30 ms have elapsed. */
+    TEST_ASSERT_FLOAT_WITHIN(DELTA_S(2), 0.030f, p_timer->read());
+    TEST_ASSERT_INT32_WITHIN(DELTA_MS(2), 30, p_timer->read_ms());
+    TEST_ASSERT_INT32_WITHIN(DELTA_US(2), 30000, p_timer->read_us());
+    TEST_ASSERT_UINT64_WITHIN(DELTA_US(2), 30000, p_timer->read_high_resolution_us());
+
+    /* Wait 50 ms - this is done to show that time elapsed when
+     * the timer is stopped does not have influence on the
+     * timer counted time. */
+
+    /* ------ */
+
+    /* Start the timer. */
+    p_timer->start();
+
+    /* Wait 30 ms. */
+    wait_ms(30);
+
+    /* Stop the timer. */
+    p_timer->stop();
+
+    /* Check results - totally 60 ms have elapsed. */
+    TEST_ASSERT_FLOAT_WITHIN(DELTA_S(3), 0.060f, p_timer->read());
+    TEST_ASSERT_INT32_WITHIN(DELTA_MS(3), 60, p_timer->read_ms());
+    TEST_ASSERT_INT32_WITHIN(DELTA_US(3), 60000, p_timer->read_us());
+    TEST_ASSERT_UINT64_WITHIN(DELTA_US(3), 60000, p_timer->read_high_resolution_us());
+
+    /* Wait 50 ms - this is done to show that time elapsed when
+     * the timer is stopped does not have influence on the
+     * timer time. */
+    wait_ms(50);
+
+    /* ------ */
+
+    /* Start the timer. */
+    p_timer->start();
+
+    /* Wait 1 sec. */
+    wait_ms(1000);
+
+    /* Stop the timer. */
+    p_timer->stop();
+
+    /* Check results - totally 1060 ms have elapsed. */
+    TEST_ASSERT_FLOAT_WITHIN(DELTA_S(4), 1.060f, p_timer->read());
+    TEST_ASSERT_INT32_WITHIN(DELTA_MS(4), 1060, p_timer->read_ms());
+    TEST_ASSERT_INT32_WITHIN(DELTA_US(4), 1060000, p_timer->read_us());
+    TEST_ASSERT_UINT64_WITHIN(DELTA_US(4), 1060000, p_timer->read_high_resolution_us());
+}
+
+/* This test verifies if reset() function resets the timer
+ * counted time.
+ *
+ * Note this function assumes that Timer uses os ticker.
+ *
+ * Given timer has been started and stopped once, then reset
+ * operation was performed.
+ * When timer is started and stopped next time.
+ * Then timer read functions returns only the the second
+ * measured time.
+ */
+void test_timer_reset_os_ticker()
+{
+    /* First measure 10 ms delay. */
+    p_timer->start();
+
+    /* Wait 10 ms. */
+    wait_ms(10);
+
+    /* Stop the timer. */
+    p_timer->stop();
+
+    /* Check results - totally 10 ms elapsed. */
+    TEST_ASSERT_FLOAT_WITHIN(DELTA_S(1), 0.010f, p_timer->read());
+    TEST_ASSERT_INT32_WITHIN(DELTA_MS(1), 10, p_timer->read_ms());
+    TEST_ASSERT_INT32_WITHIN(DELTA_US(1), 10000, p_timer->read_us());
+    TEST_ASSERT_UINT64_WITHIN(DELTA_US(1), 10000, p_timer->read_high_resolution_us());
+
+    /* Reset the timer - previous measured time should be lost now. */
+    p_timer->reset();
+
+    /* Now measure 20 ms delay. */
+    p_timer->start();
+
+    /* Wait 20 ms. */
+    wait_ms(20);
+
+    /* Stop the timer. */
+    p_timer->stop();
+
+    /* Check results - 20 ms elapsed since the reset. */
+    TEST_ASSERT_FLOAT_WITHIN(DELTA_S(1), 0.020f, p_timer->read());
+    TEST_ASSERT_INT32_WITHIN(DELTA_MS(1), 20, p_timer->read_ms());
+    TEST_ASSERT_INT32_WITHIN(DELTA_US(1), 20000, p_timer->read_us());
+    TEST_ASSERT_UINT64_WITHIN(DELTA_US(1), 20000, p_timer->read_high_resolution_us());
+}
+
+/* This test verifies if reset() function resets the timer
+ * counted time.
+ *
+ * Note this function assumes that Timer uses user ticker.
+ *
+ * Given timer has been started and stopped once, then reset
+ * operation was performed.
+ * When timer is started and stopped next time.
+ * Then timer read functions returns only the the second
+ * measured time.
+ */
+void test_timer_reset_user_ticker()
+{
+    /* For timer which is using user ticker simulate set current
+     * time (irrelevant in case of os ticker). */
+    curr_ticker_us_val = 0;
+
+    /* First measure 10 ms delay. */
+    p_timer->start();
+
+    /* Simulate that 10 ms have elapsed. */
+    curr_ticker_us_val = 10000;
+
+    /* Stop the timer. */
+    p_timer->stop();
+
+    /* Check results - totally 10 ms elapsed. */
+    TEST_ASSERT_EQUAL_FLOAT(0.010f, p_timer->read());
+    TEST_ASSERT_EQUAL_INT32(10, p_timer->read_ms());
+    TEST_ASSERT_EQUAL_INT32(10000, p_timer->read_us());
+    TEST_ASSERT_EQUAL_UINT64(10000, p_timer->read_high_resolution_us());
+
+    /* Reset the timer - previous measured time should be lost now. */
+    p_timer->reset();
+
+    /* Now measure 20 ms delay. */
+    p_timer->start();
+
+    /* Simulate that 20 ms have elapsed. */
+    curr_ticker_us_val = 30000;
+
+    /* Stop the timer. */
+    p_timer->stop();
+
+    /* Check results - 20 ms elapsed since the reset. */
+    TEST_ASSERT_EQUAL_FLOAT(0.020f, p_timer->read());
+    TEST_ASSERT_EQUAL_INT32(20, p_timer->read_ms());
+    TEST_ASSERT_EQUAL_INT32(20000, p_timer->read_us());
+    TEST_ASSERT_EQUAL_UINT64(20000, p_timer->read_high_resolution_us());
+}
+
+/* This test verifies if calling start() for already
+ * started timer does nothing.
+ *
+ * Note this function assumes that Timer uses os ticker.
+ *
+ * Given timer is already started.
+ * When timer is started again.
+ * Then second start operation is ignored.
+ */
+void test_timer_start_started_timer_os_ticker()
+{
+    /* Start the timer. */
+    p_timer->start();
+
+    /* Wait 10 ms. */
+    wait_ms(10);
+
+    /* Now start timer again. */
+    p_timer->start();
+
+    /* Wait 20 ms. */
+    wait_ms(20);
+
+    /* Stop the timer. */
+    p_timer->stop();
+
+    /* Check results - 30 ms have elapsed since the first start. */
+    TEST_ASSERT_FLOAT_WITHIN(DELTA_S(2), 0.030f, p_timer->read());
+    TEST_ASSERT_INT32_WITHIN(DELTA_MS(2), 30, p_timer->read_ms());
+    TEST_ASSERT_INT32_WITHIN(DELTA_US(2), 30000, p_timer->read_us());
+    TEST_ASSERT_UINT64_WITHIN(DELTA_US(2), 30000, p_timer->read_high_resolution_us());
+}
+
+/* This test verifies if calling start() for already
+ * started timer does nothing.
+ *
+ * Note this function assumes that Timer uses user ticker.
+ *
+ * Given timer is already started.
+ * When timer is started again.
+ * Then second start operation is ignored.
+ */
+void test_timer_start_started_timer_user_ticker()
+{
+    /* For timer which is using user ticker set current
+     * time (irrelevant in case of os ticker). */
+    curr_ticker_us_val = 0;
+
+    /* Start the timer. */
+    p_timer->start();
+
+    /* Simulate that 10 ms have elapsed. */
+    curr_ticker_us_val = 10000;
+
+    /* Now start timer again. */
+    p_timer->start();
+
+    /* Simulate that 20 ms have elapsed. */
+    curr_ticker_us_val = 30000;
+
+    /* Stop the timer. */
+    p_timer->stop();
+
+    /* Check results - 30 ms have elapsed since the first start. */
+    TEST_ASSERT_FLOAT_WITHIN(DELTA_S(2), 0.030f, p_timer->read());
+    TEST_ASSERT_INT32_WITHIN(DELTA_MS(2), 30, p_timer->read_ms());
+    TEST_ASSERT_INT32_WITHIN(DELTA_US(2), 30000, p_timer->read_us());
+    TEST_ASSERT_UINT64_WITHIN(DELTA_US(2), 30000, p_timer->read_high_resolution_us());
+}
+
+/* This test verifies Timer float operator.
+ *
+ * Note this function assumes that Timer uses os ticker.
+ *
+ * Given timer is created and a time period time is counted.
+ * When timer object is casted on float type.
+ * Then counted type in seconds is returned by means of
+ * read() function.
+ */
+void test_timer_float_operator_os_ticker()
+{
+    /* Start the timer. */
+    p_timer->start();
+
+    /* Wait 10 ms. */
+    wait_ms(10);
+
+    /* Stop the timer. */
+    p_timer->stop();
+
+    /* Check result - 10 ms elapsed. */
+    TEST_ASSERT_FLOAT_WITHIN(DELTA_S(1), 0.010f, (float)(*p_timer));
+}
+
+/* This test verifies Timer float operator.
+ *
+ * Note this function assumes that Timer uses user ticker.
+ *
+ * Given timer is created and a time period time is counted.
+ * When timer object is casted on float type.
+ * Then counted type in seconds is returned by means of
+ * read() function.
+ */
+void test_timer_float_operator_user_ticker()
+{
+    /* For timer which is using user ticker set current
+     * time (irrelevant in case of os ticker). */
+    curr_ticker_us_val = 0;
+
+    /* Start the timer. */
+    p_timer->start();
+
+    /* Simulate that 10 ms have elapsed. */
+    curr_ticker_us_val = 10000;
+
+    /* Stop the timer. */
+    p_timer->stop();
+
+    /* Check result - 10 ms elapsed. */
+    TEST_ASSERT_EQUAL_FLOAT(0.010f, (float)(*p_timer));
+}
+
+/* This test verifies if time counted by the timer is
+ * valid.
+ *
+ * For this test Timer which uses os ticker
+ * must be used.
+ *
+ * Given timer is created.
+ * When timer is used to measure 1ms/10ms/100ms/1s
+ * delays.
+ * Then the results are valid (within acceptable range).
+ */
+template<int wait_val_us>
+void test_timer_time_measurement()
+{
+    /* Start the timer. */
+    p_timer->start();
+
+    /* Wait <wait_val_us> us. */
+    wait_us(wait_val_us);
+
+    /* Stop the timer. */
+    p_timer->stop();
+
+    /* Check results. */
+    TEST_ASSERT_FLOAT_WITHIN(DELTA_S(1), (float)wait_val_us / 1000000, p_timer->read());
+    TEST_ASSERT_INT32_WITHIN(DELTA_MS(1), wait_val_us / 1000, p_timer->read_ms());
+    TEST_ASSERT_INT32_WITHIN(DELTA_US(1), wait_val_us, p_timer->read_us());
+    TEST_ASSERT_UINT64_WITHIN(DELTA_US(1), wait_val_us, p_timer->read_high_resolution_us());
+}
+
+utest::v1::status_t test_setup(const size_t number_of_cases) {
+    GREENTEA_SETUP(15, "default_auto");
+    return verbose_test_setup_handler(number_of_cases);
+}
+
+Case cases[] = {
+    Case("Test: Timer (based on os ticker) is stopped after creation.", timer_os_ticker_setup_handler, test_timer_creation_os_ticker, cleanup_handler),
+    Case("Test: Timer (based on user ticker) is stopped after creation.", timer_user_ticker_setup_handler, test_timer_creation_user_ticker, cleanup_handler),
+
+    Case("Test: Timer (based on os ticker) - measured time accumulation.", timer_os_ticker_setup_handler, test_timer_time_accumulation_os_ticker, cleanup_handler),
+    Case("Test: Timer (based on user ticker) measured time accumulation.", timer_user_ticker_setup_handler, test_timer_time_accumulation_user_ticker, cleanup_handler),
+
+    Case("Test: Timer (based on os ticker) - reset.", timer_os_ticker_setup_handler, test_timer_reset_os_ticker, cleanup_handler),
+    Case("Test: Timer (based on user ticker) - reset.", timer_user_ticker_setup_handler, test_timer_reset_user_ticker, cleanup_handler),
+
+    Case("Test: Timer (based on os ticker) - start started timer.", timer_os_ticker_setup_handler, test_timer_start_started_timer_os_ticker, cleanup_handler),
+    Case("Test: Timer (based on user ticker) - start started timer.", timer_user_ticker_setup_handler, test_timer_start_started_timer_user_ticker, cleanup_handler),
+
+    Case("Test: Timer (based on os ticker) - float operator.", timer_os_ticker_setup_handler, test_timer_float_operator_os_ticker, cleanup_handler),
+    Case("Test: Timer (based on user ticker) - float operator.", timer_user_ticker_setup_handler, test_timer_float_operator_user_ticker, cleanup_handler),
+
+    Case("Test: Timer - time measurement 1 ms.", timer_os_ticker_setup_handler, test_timer_time_measurement<1000>, cleanup_handler),
+    Case("Test: Timer - time measurement 10 ms.", timer_os_ticker_setup_handler, test_timer_time_measurement<10000>, cleanup_handler),
+    Case("Test: Timer - time measurement 100 ms.", timer_os_ticker_setup_handler, test_timer_time_measurement<100000>, cleanup_handler),
+    Case("Test: Timer - time measurement 1 s.", timer_os_ticker_setup_handler, test_timer_time_measurement<1000000>, cleanup_handler),
+};
+
+Specification specification(test_setup, cases);
+
+int main() {
+    return !Harness::run(specification);
+}
+
diff --git a/TESTS/mbed_hal/lp_ticker/main.cpp b/TESTS/mbed_hal/lp_ticker/main.cpp
index 05d497fa937..5802644c580 100644
--- a/TESTS/mbed_hal/lp_ticker/main.cpp
+++ b/TESTS/mbed_hal/lp_ticker/main.cpp
@@ -23,17 +23,16 @@
 #include "greentea-client/test_env.h"
 
 #include "mbed.h"
-#include "us_ticker_api.h"
 #include "lp_ticker_api.h"
-#include "TimerEvent.h"
 
 using namespace utest::v1;
 
 static volatile bool complete;
-static volatile timestamp_t complete_timestamp;
+static volatile timestamp_t complete_time;
 static ticker_event_t delay_event;
 static const ticker_data_t *lp_ticker_data = get_lp_ticker_data();
-
+static Timer timer;
+static LowPowerTimer lp_timer;
 
 /* Timeouts are quite arbitrary due to large number of boards with varying level of accuracy */
 #define LONG_TIMEOUT (100000)
@@ -41,7 +40,7 @@ static const ticker_data_t *lp_ticker_data = get_lp_ticker_data();
 
 void cb_done(uint32_t id) {
     if ((uint32_t)&delay_event == id) {
-        complete_timestamp = us_ticker_read();
+        complete_time = timer.read_us();
         complete = true;
     } else {
         // Normal ticker handling
@@ -51,7 +50,7 @@ void cb_done(uint32_t id) {
 
 void cb_done_deepsleep(uint32_t id) {
     if ((uint32_t)&delay_event == id) {
-        complete_timestamp = lp_ticker_read();
+        complete_time = lp_timer.read_us();
         complete = true;
     } else {
         // Normal ticker handling
@@ -66,14 +65,15 @@ void lp_ticker_delay_us(uint32_t delay_us, uint32_t tolerance)
 
     ticker_set_handler(lp_ticker_data, cb_done);
     ticker_remove_event(lp_ticker_data, &delay_event);
-    delay_ts = lp_ticker_read() + delay_us;
+    delay_ts = ticker_read(lp_ticker_data) + delay_us;
 
-    timestamp_t start = us_ticker_read();
+    timer.reset();
+    timer.start();
     ticker_insert_event(lp_ticker_data, &delay_event, delay_ts, (uint32_t)&delay_event);
     while (!complete);
-    timestamp_t end = complete_timestamp;
+    timer.stop();
 
-    TEST_ASSERT_UINT32_WITHIN(tolerance, delay_us, end - start);
+    TEST_ASSERT_UINT32_WITHIN(tolerance, delay_us, complete_time);
     TEST_ASSERT_TRUE(complete);
 }
 
@@ -95,19 +95,23 @@ void lp_ticker_1s_deepsleep()
 
     ticker_set_handler(lp_ticker_data, cb_done_deepsleep);
     ticker_remove_event(lp_ticker_data, &delay_event);
-    delay_ts = lp_ticker_read() + 1000000;
+    delay_ts = ticker_read(lp_ticker_data) + 1000000;
 
     /*
-     * We use here lp_ticker_read() instead of us_ticker_read() for start and
+     * We use here the low power timer instead of microsecond timer for start and
      * end because the microseconds timer might be disable during deepsleep.
      */
-    timestamp_t start = lp_ticker_read();
+    lp_timer.reset();
+    lp_timer.start();
     ticker_insert_event(lp_ticker_data, &delay_event, delay_ts, (uint32_t)&delay_event);
-    deepsleep();
+    /* Make sure deepsleep is allowed, to go to deepsleep */
+    bool deep_sleep_allowed = sleep_manager_can_deep_sleep();
+    TEST_ASSERT_TRUE_MESSAGE(deep_sleep_allowed, "Deep sleep should be allowed");
+    sleep();
     while (!complete);
-    timestamp_t end = complete_timestamp;
+    lp_timer.stop();
 
-    TEST_ASSERT_UINT32_WITHIN(LONG_TIMEOUT, 1000000, end - start);
+    TEST_ASSERT_UINT32_WITHIN(LONG_TIMEOUT, 1000000, complete_time);
     TEST_ASSERT_TRUE(complete);
 }
 
@@ -118,17 +122,20 @@ void lp_ticker_1s_sleep()
 
     ticker_set_handler(lp_ticker_data, cb_done);
     ticker_remove_event(lp_ticker_data, &delay_event);
-    delay_ts = lp_ticker_read() + 1000000;
+    delay_ts = ticker_read(lp_ticker_data) + 1000000;
 
     sleep_manager_lock_deep_sleep();
-    timestamp_t start = us_ticker_read();
+    timer.reset();
+    timer.start();
+    bool deep_sleep_allowed = sleep_manager_can_deep_sleep();
+    TEST_ASSERT_FALSE_MESSAGE(deep_sleep_allowed, "Deep sleep should be disallowed");
     ticker_insert_event(lp_ticker_data, &delay_event, delay_ts, (uint32_t)&delay_event);
     sleep();
     while (!complete);
-    timestamp_t end = complete_timestamp;
+    timer.stop();
     sleep_manager_unlock_deep_sleep();
 
-    TEST_ASSERT_UINT32_WITHIN(LONG_TIMEOUT, 1000000, end - start);
+    TEST_ASSERT_UINT32_WITHIN(LONG_TIMEOUT, 1000000, complete_time);
     TEST_ASSERT_TRUE(complete);
 }
 #endif /* DEVICE_SLEEP */
diff --git a/TESTS/mbedmicro-rtos-mbed/MemoryPool/main.cpp b/TESTS/mbedmicro-rtos-mbed/MemoryPool/main.cpp
new file mode 100644
index 00000000000..1428d48e948
--- /dev/null
+++ b/TESTS/mbedmicro-rtos-mbed/MemoryPool/main.cpp
@@ -0,0 +1,623 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+
+using namespace utest::v1;
+
+/* Enum used to select block allocation method. */
+typedef enum
+{
+    ALLOC, CALLOC
+} AllocType;
+
+/* Structure for complex block type. */
+typedef struct
+{
+    int a;
+    char b;
+    int c;
+} COMPLEX_TYPE;
+
+/* Function to check if complex type object is cleared.*/
+bool comp_is_cleared(COMPLEX_TYPE *object)
+{
+    if (object->a == 0 && object->b == 0 && object->c == 0) {
+        return true;
+    }
+
+    return false;
+}
+
+/* Function to check if complex type object holds specified values.*/
+bool comp_is_equal(COMPLEX_TYPE *object, int a, char b, int c)
+{
+    if (object->a == a && object->b == b && object->c == c) {
+        return true;
+    }
+
+    return false;
+}
+
+/* Function to set complex type object fields.*/
+void comp_set(COMPLEX_TYPE *object, int a, char b, int c)
+{
+    object->a = a;
+    object->b = b;
+    object->c = c;
+}
+
+/* Template for functional tests for alloc(), calloc() functions
+ * of MemoryPool object.
+ *
+ * Given MemoryPool object of the specified type and queue size has
+ * been successfully created.
+ * When max number of blocks is allocated from the pool.
+ * Then all allocations are successful.
+ *
+ * */
+template<typename T, const uint32_t numOfEntries>
+void test_mem_pool_alloc_success(AllocType atype)
+{
+    MemoryPool<T, numOfEntries> mem_pool;
+    T * p_blocks[numOfEntries];
+    uint32_t i;
+
+    /* Test alloc()/calloc() methods - try to allocate max number of
+       blocks. All allocations should be successful. */
+    for (i = 0; i < numOfEntries; i++) {
+        /* Allocate memory block. */
+        if (atype == ALLOC) {
+            p_blocks[i] = mem_pool.alloc();
+        } else {
+            p_blocks[i] = mem_pool.calloc();
+        }
+
+        /* Show that memory pool block has been allocated. */
+        TEST_ASSERT_NOT_NULL(p_blocks[i]);
+
+        /* Check if Calloc clears the block. */
+        if (atype == CALLOC) {
+            TEST_ASSERT_EQUAL(0, *p_blocks[i]);
+        }
+
+        /* Init fields. */
+        *p_blocks[i] = (i + 5);
+    }
+
+    /* Check if blocks holds valid values. */
+    for (i = 0; i < numOfEntries; i++) {
+        TEST_ASSERT_EQUAL((i + 5), *p_blocks[i]);
+    }
+}
+
+/* Template for functional tests for alloc(), calloc() functions
+ * of MemoryPool object.
+ *
+ * Complex memory pool block type is used.
+ *
+ * Given MemoryPool object of the specified type and queue size has
+ * been successfully created.
+ * When max number of blocks is allocated from the pool.
+ * Then all allocations are successful.
+ *
+ * */
+template<typename T, const uint32_t numOfEntries>
+void test_mem_pool_alloc_success_complex(AllocType atype)
+{
+    MemoryPool<T, numOfEntries> mem_pool;
+    T * p_blocks[numOfEntries];
+    uint32_t i;
+
+    /* Test alloc()/calloc() methods - try to allocate max number of
+       blocks. All allocations should be successful. */
+    for (i = 0; i < numOfEntries; i++) {
+        /* Allocate memory block. */
+        if (atype == ALLOC) {
+            p_blocks[i] = mem_pool.alloc();
+        } else {
+            p_blocks[i] = mem_pool.calloc();
+        }
+
+        /* Show that memory pool block has been allocated. */
+        TEST_ASSERT_NOT_NULL(p_blocks[i]);
+
+        /* Check if Calloc clears the block. */
+        if (atype == CALLOC) {
+            TEST_ASSERT_EQUAL(true, comp_is_cleared(p_blocks[i]));
+        }
+
+        /* Init fields. */
+        comp_set(p_blocks[i], i + 1, i + 2, i + 3);
+    }
+
+    /* Check if blocks holds valid values. */
+    for (i = 0; i < numOfEntries; i++) {
+        TEST_ASSERT_EQUAL(true, comp_is_equal(p_blocks[i], i + 1, i + 2, i + 3));
+    }
+}
+
+/* Template for functional tests for alloc(), calloc() functions
+ * of MemoryPool object.
+ *
+ * Given MemoryPool has already max number of blocks allocated from the pool.
+ * When next block is allocated.
+ * Then allocation fails.
+ *
+ * */
+template<typename T, const uint32_t numOfEntries>
+void test_mem_pool_alloc_fail(AllocType atype)
+{
+    MemoryPool<T, numOfEntries> mem_pool;
+    T * p_blocks[numOfEntries];
+    T * p_extra_block;
+    uint32_t i;
+
+    /* Allocate all available blocks. */
+    for (i = 0; i < numOfEntries; i++) {
+        if (atype == ALLOC) {
+            p_blocks[i] = mem_pool.alloc();
+        } else {
+            p_blocks[i] = mem_pool.calloc();
+        }
+
+        /* Show that memory pool block has been allocated. */
+        TEST_ASSERT_NOT_NULL(p_blocks[i]);
+    }
+
+    /* There are no more blocks available. Try to allocate another block. */
+    if (atype == ALLOC) {
+        p_extra_block = mem_pool.alloc();
+    } else {
+        p_extra_block = mem_pool.calloc();
+    }
+
+    /* Show that memory pool block has NOT been allocated. */
+    TEST_ASSERT_NULL(p_extra_block);
+}
+
+/* Template for functional tests for free() function
+ * of MemoryPool object.
+ *
+ * Given MemoryPool has all blocks allocated.
+ * When free operation is executed on the each allocated block.
+ * Then each deallocation is successfully performed.
+ *
+ * */
+template<typename T, const uint32_t numOfEntries>
+void test_mem_pool_free_success(AllocType atype)
+{
+    MemoryPool<T, numOfEntries> mem_pool;
+    T * p_blocks[numOfEntries];
+    uint32_t i;
+    osStatus status;
+
+    /* Allocate all available blocks. */
+    for (i = 0; i < numOfEntries; i++) {
+        if (atype == ALLOC) {
+            p_blocks[i] = mem_pool.alloc();
+        } else {
+            p_blocks[i] = mem_pool.calloc();
+        }
+
+        /* Show that memory pool block has been allocated. */
+        TEST_ASSERT_NOT_NULL(p_blocks[i]);
+    }
+
+    /* Free all memory blocks. */
+    for (i = 0; i < numOfEntries; i++) {
+        status = mem_pool.free(p_blocks[i]);
+
+        /* Check operation status. */
+        TEST_ASSERT_EQUAL(osOK, status);
+    }
+}
+
+/* Template for functional tests for alloc(), calloc() functions
+ * of MemoryPool object.
+ *
+ * Basic memory pool block type is used.
+ *
+ * Given MemoryPool had all blocks allocated and one block has
+ * been freed (last).
+ * When next block is allocated.
+ * Then allocation is successful.
+ *
+ * */
+template<typename T, const uint32_t numOfEntries>
+void test_mem_pool_free_realloc_last(AllocType atype)
+{
+    MemoryPool<T, numOfEntries> mem_pool;
+    T * p_blocks[numOfEntries];
+    uint32_t i;
+    osStatus status;
+
+    /* Allocate all available blocks. */
+    for (i = 0; i < numOfEntries; i++) {
+        if (atype == ALLOC) {
+            p_blocks[i] = mem_pool.alloc();
+        } else {
+            p_blocks[i] = mem_pool.calloc();
+        }
+
+        /* Init block. */
+        *p_blocks[i] = 0xAB;
+
+        /* Show that memory pool block has been allocated. */
+        TEST_ASSERT_NOT_NULL(p_blocks[i]);
+    }
+
+    /* Free the last block. */
+    status = mem_pool.free(p_blocks[numOfEntries - 1]);
+
+    /* Check status. */
+    TEST_ASSERT_EQUAL(osOK, status);
+
+    /* Try to allocate another block (one block is now available). */
+    if (atype == ALLOC) {
+        p_blocks[numOfEntries - 1] = mem_pool.alloc();
+    } else {
+        p_blocks[numOfEntries - 1] = mem_pool.calloc();
+    }
+
+    /* Show that memory pool block has been now allocated. */
+    TEST_ASSERT_NOT_NULL(p_blocks[numOfEntries - 1]);
+
+    /* Check if Calloc clears the block. */
+    if (atype == CALLOC) {
+        TEST_ASSERT_EQUAL(0, *p_blocks[numOfEntries - 1]);
+    }
+}
+
+/* Template for functional tests for alloc(), calloc() functions
+ * of MemoryPool object.
+ *
+ * Complex memory pool block type is used.
+ *
+ * Given MemoryPool had all blocks allocated and one block has
+ * been freed (last).
+ * When next block is allocated.
+ * Then allocation is successful.
+ *
+ * */
+template<typename T, const uint32_t numOfEntries>
+void test_mem_pool_free_realloc_last_complex(AllocType atype)
+{
+    MemoryPool<T, numOfEntries> mem_pool;
+    T * p_blocks[numOfEntries];
+    uint32_t i;
+    osStatus status;
+
+    /* Allocate all available blocks. */
+    for (i = 0; i < numOfEntries; i++) {
+        if (atype == ALLOC) {
+            p_blocks[i] = mem_pool.alloc();
+        } else {
+            p_blocks[i] = mem_pool.calloc();
+        }
+
+        /* Init block. */
+        comp_set(p_blocks[i], i + 1, i + 2, i + 3);
+
+        /* Show that memory pool block has been allocated. */
+        TEST_ASSERT_NOT_NULL(p_blocks[i]);
+    }
+
+    /* Free the last block. */
+    status = mem_pool.free(p_blocks[numOfEntries - 1]);
+
+    /* Check status. */
+    TEST_ASSERT_EQUAL(osOK, status);
+
+    /* Try to allocate another block (one block is now available). */
+    if (atype == ALLOC) {
+        p_blocks[numOfEntries - 1] = mem_pool.alloc();
+    } else {
+        p_blocks[numOfEntries - 1] = mem_pool.calloc();
+    }
+
+    /* Show that memory pool block has been now allocated. */
+    TEST_ASSERT_NOT_NULL(p_blocks[numOfEntries - 1]);
+
+    /* Check if Calloc clears the block. */
+    if (atype == CALLOC) {
+        TEST_ASSERT_EQUAL(true, comp_is_cleared(p_blocks[numOfEntries - 1]));
+    }
+}
+
+/* Template for functional tests for alloc(), calloc() functions
+ * of MemoryPool object.
+ *
+ * Basic memory pool block type is used.
+ *
+ * Given MemoryPool had all blocks allocated and one block has
+ * been freed (first).
+ * When next block is allocated.
+ * Then allocation is successful.
+ *
+ * */
+template<typename T, const uint32_t numOfEntries>
+void test_mem_pool_free_realloc_first(AllocType atype)
+{
+    MemoryPool<T, numOfEntries> mem_pool;
+    T * p_blocks[numOfEntries];
+    uint32_t i;
+    osStatus status;
+
+    /* Allocate all available blocks. */
+    for (i = 0; i < numOfEntries; i++) {
+        if (atype == ALLOC) {
+            p_blocks[i] = mem_pool.alloc();
+        } else {
+            p_blocks[i] = mem_pool.calloc();
+        }
+
+        /* Init block. */
+        *p_blocks[i] = 0xAB;
+
+        /* Show that memory pool block has been allocated. */
+        TEST_ASSERT_NOT_NULL(p_blocks[i]);
+    }
+
+    /* Free the last block. */
+    status = mem_pool.free(p_blocks[0]);
+
+    /* Check status. */
+    TEST_ASSERT_EQUAL(osOK, status);
+
+    /* Try to allocate another block (one block is now available). */
+    if (atype == ALLOC) {
+        p_blocks[0] = mem_pool.alloc();
+    } else {
+        p_blocks[0] = mem_pool.calloc();
+    }
+
+    /* Show that memory pool block has been now allocated. */
+    TEST_ASSERT_NOT_NULL(p_blocks[0]);
+
+    /* Check if Calloc clears the block. */
+    if (atype == CALLOC) {
+        TEST_ASSERT_EQUAL(0, *p_blocks[0]);
+    }
+}
+
+/* Template for functional tests for alloc(), calloc() functions
+ * of MemoryPool object.
+ *
+ * Complex memory pool block type is used.
+ *
+ * Given MemoryPool had all blocks allocated and one block has
+ * been freed (first).
+ * When next block is allocated.
+ * Then allocation is successful.
+ *
+ * */
+template<typename T, const uint32_t numOfEntries>
+void test_mem_pool_free_realloc_first_complex(AllocType atype)
+{
+    MemoryPool<T, numOfEntries> mem_pool;
+    T * p_blocks[numOfEntries];
+    uint32_t i;
+    osStatus status;
+
+    /* Allocate all available blocks. */
+    for (i = 0; i < numOfEntries; i++) {
+        if (atype == ALLOC) {
+            p_blocks[i] = mem_pool.alloc();
+        } else {
+            p_blocks[i] = mem_pool.calloc();
+        }
+
+        /* Init block. */
+        comp_set(p_blocks[i], i + 1, i + 2, i + 3);
+
+        /* Show that memory pool block has been allocated. */
+        TEST_ASSERT_NOT_NULL(p_blocks[i]);
+    }
+
+    /* Free the last block. */
+    status = mem_pool.free(p_blocks[0]);
+
+    /* Check status. */
+    TEST_ASSERT_EQUAL(osOK, status);
+
+    /* Try to allocate another block (one block is now available). */
+    if (atype == ALLOC) {
+        p_blocks[0] = mem_pool.alloc();
+    } else {
+        p_blocks[0] = mem_pool.calloc();
+    }
+
+    /* Show that memory pool block has been now allocated. */
+    TEST_ASSERT_NOT_NULL(p_blocks[0]);
+
+    /* Check if Calloc clears the block. */
+    if (atype == CALLOC) {
+        TEST_ASSERT_EQUAL(true, comp_is_cleared(p_blocks[0]));
+    }
+}
+
+/* Robustness checks for free() function.
+ *
+ * Given block from the MemoryPool has been successfully deallocated.
+ * When free operation is executed on this block again.
+ * Then operation fails with osErrorResource status.
+ *
+ * */
+void test_mem_pool_free_on_freed_block()
+{
+    MemoryPool<int, 1> mem_pool;
+    int * p_block;
+    osStatus status;
+
+    /* Allocate memory block. */
+    p_block = mem_pool.alloc();
+
+    /* Show that memory pool block has been allocated. */
+    TEST_ASSERT_NOT_NULL(p_block);
+
+    /* Free memory block. */
+    status = mem_pool.free(p_block);
+
+    /* Check operation status. */
+    TEST_ASSERT_EQUAL(osOK, status);
+
+    /* Free memory block again. */
+    status = mem_pool.free(p_block);
+
+    /* Check operation status. */
+    TEST_ASSERT_EQUAL(osErrorResource, status);
+}
+
+/* Robustness checks for free() function.
+ * Function under test is called with invalid parameters.
+ *
+ * Given MemoryPool object has been successfully created.
+ * When free operation is performed on NULL address.
+ * Then deallocation fails with osErrorParameter error.
+ *
+ */
+void free_block_invalid_parameter_null()
+{
+    MemoryPool<int, 1> mem_pool;
+    osStatus status;
+
+    /* Try to free block passing invalid parameter (NULL). */
+    status = mem_pool.free(NULL);
+
+    /* Check operation status. */
+    TEST_ASSERT_EQUAL(osErrorParameter, status);
+}
+
+/* Robustness checks for free() function.
+ * Function under test is called with invalid parameters.
+ *
+ * Given MemoryPool object has been successfully created.
+ * When free operation is performed on invalid address.
+ * Then deallocation fails with osErrorParameter error.
+ *
+ */
+void free_block_invalid_parameter()
+{
+    MemoryPool<int, 1> mem_pool;
+    osStatus status;
+
+    /* Try to free block passing invalid parameter (variable address). */
+    status = mem_pool.free(reinterpret_cast<int*>(&status));
+
+    /* Check operation status. */
+    TEST_ASSERT_EQUAL(osErrorParameter, status);
+}
+
+/* Use wrapper functions to reduce memory usage. */
+
+template<typename T, const uint32_t numOfEntries>
+void test_mem_pool_alloc_success_wrapper()
+{
+    test_mem_pool_alloc_success<T, numOfEntries>(ALLOC);
+    test_mem_pool_alloc_success<T, numOfEntries>(CALLOC);
+}
+
+template<typename T, const uint32_t numOfEntries>
+void test_mem_pool_alloc_success_complex_wrapper()
+{
+    test_mem_pool_alloc_success_complex<T, numOfEntries>(ALLOC);
+    test_mem_pool_alloc_success_complex<T, numOfEntries>(CALLOC);
+}
+
+template<typename T, const uint32_t numOfEntries>
+void test_mem_pool_free_success_wrapper()
+{
+    test_mem_pool_free_success<T, numOfEntries>(ALLOC);
+    test_mem_pool_free_success<T, numOfEntries>(CALLOC);
+}
+
+template<typename T, const uint32_t numOfEntries>
+void test_mem_pool_free_realloc_last_wrapper()
+{
+    test_mem_pool_free_realloc_last<T, numOfEntries>(ALLOC);
+    test_mem_pool_free_realloc_last<T, numOfEntries>(CALLOC);
+
+}
+
+template<typename T, const uint32_t numOfEntries>
+void test_mem_pool_free_realloc_first_wrapper()
+{
+    test_mem_pool_free_realloc_first<T, numOfEntries>(ALLOC);
+    test_mem_pool_free_realloc_first<T, numOfEntries>(CALLOC);
+}
+
+template<typename T, const uint32_t numOfEntries>
+void test_mem_pool_free_realloc_first_complex_wrapper()
+{
+    test_mem_pool_free_realloc_first_complex<T, numOfEntries>(ALLOC);
+    test_mem_pool_free_realloc_first_complex<T, numOfEntries>(CALLOC);
+}
+
+template<typename T, const uint32_t numOfEntries>
+void test_mem_pool_free_realloc_last_complex_wrapper()
+{
+    test_mem_pool_free_realloc_last_complex<T, numOfEntries>(ALLOC);
+    test_mem_pool_free_realloc_last_complex<T, numOfEntries>(CALLOC);
+}
+
+template<typename T, const uint32_t numOfEntries>
+void test_mem_pool_alloc_fail_wrapper()
+{
+    test_mem_pool_alloc_fail<T, numOfEntries>(ALLOC);
+    test_mem_pool_alloc_fail<T, numOfEntries>(CALLOC);
+}
+
+Case cases[] = {
+    Case("Test: alloc()/calloc() - success, 4 bytes b_type, q_size equal to 1.", test_mem_pool_alloc_success_wrapper<int, 1>),
+    Case("Test: alloc()/calloc() - success, 4 bytes b_type, q_size equal to 3.", test_mem_pool_alloc_success_wrapper<int, 3>),
+    Case("Test: alloc()/calloc() - success, 1 bytes b_type, q_size equal to 1.", test_mem_pool_alloc_success_wrapper<char, 1>),
+    Case("Test: alloc()/calloc() - success, 1 bytes b_type, q_size equal to 3.", test_mem_pool_alloc_success_wrapper<char, 3>),
+    Case("Test: alloc()/calloc() - success, complex b_type, q_size equal to 1.", test_mem_pool_alloc_success_complex_wrapper<COMPLEX_TYPE, 1>),
+    Case("Test: alloc()/calloc() - success, complex b_type, q_size equal to 3.", test_mem_pool_alloc_success_complex_wrapper<COMPLEX_TYPE, 3>),
+
+    Case("Test: free() - success, 4 bytes b_type, q_size equal to 1.", test_mem_pool_free_success_wrapper<int, 1>),
+    Case("Test: free() - success, 4 bytes b_type, q_size equal to 3.", test_mem_pool_free_success_wrapper<int, 3>),
+    Case("Test: free() - success, complex b_type, q_size equal to 1.", test_mem_pool_free_success_wrapper<COMPLEX_TYPE, 1>),
+    Case("Test: free() - success, complex b_type, q_size equal to 3.", test_mem_pool_free_success_wrapper<COMPLEX_TYPE, 3>),
+
+    Case("Test: re-allocation of the last block, basic type.", test_mem_pool_free_realloc_last_wrapper<int, 3>),
+    Case("Test: re-allocation of the first block, basic type.", test_mem_pool_free_realloc_first_wrapper<int, 3>),
+    Case("Test: re-allocation of the first block, complex type.", test_mem_pool_free_realloc_first_complex_wrapper<COMPLEX_TYPE, 3>),
+    Case("Test: re-allocation of the last block, complex type.", test_mem_pool_free_realloc_last_complex_wrapper<COMPLEX_TYPE, 3>),
+
+    Case("Test: fail (out of free blocks).", test_mem_pool_alloc_fail_wrapper<int, 3>),
+
+    Case("Test: free() - robust (free block twice).", test_mem_pool_free_on_freed_block),
+    Case("Test: free() - robust (free called with invalid param - NULL).", free_block_invalid_parameter_null),
+    Case("Test: free() - robust (free called with invalid param).", free_block_invalid_parameter)
+};
+
+utest::v1::status_t greentea_test_setup(const size_t number_of_cases)
+{
+    GREENTEA_SETUP(20, "default_auto");
+    return greentea_test_setup_handler(number_of_cases);
+}
+
+Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler);
+
+int main()
+{
+    Harness::run(specification);
+}
+
diff --git a/TESTS/mbedmicro-rtos-mbed/basic/main.cpp b/TESTS/mbedmicro-rtos-mbed/basic/main.cpp
index dc066c9093f..87b1e6712f9 100644
--- a/TESTS/mbedmicro-rtos-mbed/basic/main.cpp
+++ b/TESTS/mbedmicro-rtos-mbed/basic/main.cpp
@@ -14,49 +14,57 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
-
-
-/*
- * Tests is to measure the accuracy of Thread::wait() over a period of time
- *
- *
- * 1) DUT would start to update callback_trigger_count every milli sec
- * 2) Host would query what is current count base_time, Device responds by the callback_trigger_count
- * 3) Host after waiting for measurement stretch. It will query for device time again final_time.
- * 4) Host computes the drift considering base_time, final_time, transport delay and measurement stretch
- * 5) Finally host send the results back to device pass/fail based on tolerance.
- * 6) More details on tests can be found in timing_drift_auto.py
- *
- */
-
 #include "mbed.h"
 #include "greentea-client/test_env.h"
-#include "rtos.h"
+#include "utest/utest.h"
 #include "unity/unity.h"
 
 #if defined(MBED_RTOS_SINGLE_THREAD)
 #error [NOT_SUPPORTED] test not supported
 #endif
 
-#define TEST_STACK_SIZE 1024
+using utest::v1::Case;
+
+#define TEST_STACK_SIZE 256
 #define ONE_MILLI_SEC 1000
 
-volatile uint32_t callback_trigger_count = 0;
+volatile uint32_t elapsed_time_ms = 0;
+static const int test_timeout = 40;
 
-static const int test_timeout = 240;
-bool test_result = false;
 
-void update_tick_thread() {
+void update_tick_thread(Mutex *mutex)
+{
     while (true) {
         Thread::wait(1);
-        ++callback_trigger_count;
+        mutex->lock();
+        ++elapsed_time_ms;
+        mutex->unlock();
     }
 }
 
-void gt_comm_wait_thread() {
+
+/** Tests is to measure the accuracy of Thread::wait() over a period of time
+
+    Given
+        a thread updating elapsed_time_ms every milli sec
+        and host script for time measurement accuracy check (More details on tests can be found in timing_drift_auto.py)
+    When host query what is current count base_time
+    Then Device responds by the elapsed_time_ms
+    When host query what is current count final_time
+    Then Device responds by the elapsed_time_ms
+    When host computes the drift considering base_time, final_time, transport delay and measurement stretch
+    Then host send the results back to device pass/fail based on tolerance
+ */
+void test(void)
+{
     char _key[11] = { };
     char _value[128] = { };
     int expected_key = 1;
+    Mutex mutex;
+    uint32_t elapsed_time;
+
+    Thread tick_thread(osPriorityHigh, TEST_STACK_SIZE);
+    tick_thread.start(callback(update_tick_thread, &mutex));
 
     greentea_send_kv("timing_drift_check_start", 0);
 
@@ -65,28 +73,41 @@ void gt_comm_wait_thread() {
         greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value));
         expected_key = strcmp(_key, "base_time");
     } while (expected_key);
-    greentea_send_kv(_key, callback_trigger_count * ONE_MILLI_SEC);
+
+    mutex.lock();
+    elapsed_time = elapsed_time_ms;
+    mutex.unlock();
+    // send base_time
+    greentea_send_kv(_key, elapsed_time * ONE_MILLI_SEC);
 
     // wait for 2nd signal from host
     greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value));
-    greentea_send_kv(_key, callback_trigger_count * ONE_MILLI_SEC);
+
+    mutex.lock();
+    elapsed_time = elapsed_time_ms;
+    mutex.unlock();
+    // send final_time
+    greentea_send_kv(_key, elapsed_time * ONE_MILLI_SEC);
 
     //get the results from host
     greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value));
 
-    if (strcmp("pass", _key) == 0) {
-        test_result = true;
-    }
+    TEST_ASSERT_EQUAL_STRING_MESSAGE("pass", _key,"Host side script reported a fail...");
 }
 
-int main() {
+Case cases[] = {
+    Case("Test Thread::wait accuracy", test)
+};
+
+utest::v1::status_t greentea_test_setup(const size_t number_of_cases)
+{
     GREENTEA_SETUP(test_timeout, "timing_drift_auto");
-    Thread tick_thread(osPriorityHigh, TEST_STACK_SIZE);
-    Thread gt_conn_thread(osPriorityNormal, TEST_STACK_SIZE);
+    return utest::v1::greentea_test_setup_handler(number_of_cases);
+}
 
-    tick_thread.start(update_tick_thread);
-    gt_conn_thread.start(gt_comm_wait_thread);
-    gt_conn_thread.join();
+utest::v1::Specification specification(greentea_test_setup, cases);
 
-    GREENTEA_TESTSUITE_RESULT(test_result);
+int main()
+{
+    utest::v1::Harness::run(specification);
 }
diff --git a/TESTS/mbedmicro-rtos-mbed/event_flags/main.cpp b/TESTS/mbedmicro-rtos-mbed/event_flags/main.cpp
index e9d0a269e40..7753a4521d9 100644
--- a/TESTS/mbedmicro-rtos-mbed/event_flags/main.cpp
+++ b/TESTS/mbedmicro-rtos-mbed/event_flags/main.cpp
@@ -17,47 +17,361 @@
 
 #include "mbed.h"
 #include "greentea-client/test_env.h"
-#include "rtos.h"
+#include "unity/unity.h"
+#include "utest/utest.h"
+
+using utest::v1::Case;
 
 #if defined(MBED_RTOS_SINGLE_THREAD)
   #error [NOT_SUPPORTED] test not supported
 #endif
 
-#define TEST_STACK_SIZE 512
+#define THREAD_STACK_SIZE   320 /* 512B stack on GCC_ARM compiler cause out of memory on some 16kB RAM boards e.g. NUCLEO_F070RB */
+
+#define MAX_FLAG_POS 30
+#define PROHIBITED_FLAG_POS 31
 
-#define   EVENT_SET_VALUE    0x01
-const int EVENT_TO_EMIT = 100;
-const int EVENT_HANDLE_DELAY = 25;
+/* flags */
+#define FLAG01          0x1FFF       /* 00000000000000000001111111111111 */
+#define FLAG02          0x3FFE000    /* 00000011111111111110000000000000 */
+#define FLAG03          0x7C000000   /* 01111100000000000000000000000000 */
+#define PROHIBITED_FLAG 0x80000000   /* 10000000000000000000000000000000 */
+#define NO_FLAGS 0x0
 
-DigitalOut led(LED1);
-EventFlags event_flags;
+Semaphore sync_sem(0, 1);
 
-int events_counter = 0;
+/* In order to successfully run this test suite when compiled with --profile=debug
+ * error() has to be redefined as noop.
+ *
+ * EventFlags calls RTX API which uses Event Recorder functionality. When compiled
+ * with MBED_TRAP_ERRORS_ENABLED=1 (set in debug profile) EvrRtxEventFlagsError() calls error()
+ * which aborts test program.
+ */
+#if defined(MBED_TRAP_ERRORS_ENABLED) && MBED_TRAP_ERRORS_ENABLED
+void error(const char* format, ...) {
+    (void) format;
+}
+#endif
 
-void led_thread() {
-    while (true) {
-        event_flags.wait_all(EVENT_SET_VALUE);
-        led = !led;
-        events_counter++;
+template<uint32_t flags, uint32_t wait_ms>
+void send_thread(EventFlags *ef)
+{
+    for (uint32_t i = 0; i <= MAX_FLAG_POS; i++) {
+        const uint32_t flag = flags & (1 << i);
+        if (flag) {
+            ef->set(flag);
+            Thread::wait(wait_ms);
+        }
     }
 }
 
-int main (void) {
-    GREENTEA_SETUP(10, "default_auto");
+template<uint32_t flags, uint32_t wait_ms>
+void send_thread_sync(EventFlags *ef)
+{
+    for (uint32_t i = 0; i <= MAX_FLAG_POS; i++) {
+        const uint32_t flag = flags & (1 << i);
+        if (flag) {
+            sync_sem.wait();
+            ef->set(flag);
+            Thread::wait(wait_ms);
+        }
+    }
+}
 
-    Thread thread(osPriorityNormal, TEST_STACK_SIZE);
-    thread.start(led_thread);
+template<uint32_t flags>
+void wait_thread_all(EventFlags *ef)
+{
+    uint32_t ret, flags_after_clear;
+    ret = ef->wait_all(flags);
+    flags_after_clear = ef->get();
+    TEST_ASSERT(flags | ret);
+    TEST_ASSERT(flags | ~flags_after_clear);
+}
 
-    bool result = false;
 
-    while (true) {
-        Thread::wait(2 * EVENT_HANDLE_DELAY);
-        event_flags.set(EVENT_SET_VALUE);
-        if (events_counter == EVENT_TO_EMIT) {
-            result = true;
-            break;
-        }
+/** Test if get on empty EventFlags object return NO_FLAGS
+
+    Given a empty EventFlags object
+    When call @a get
+    Then @a get return status is NO_FLAGS
+ */
+void test_empty_get(void)
+{
+    EventFlags ev;
+    uint32_t flags;
+
+    flags = ev.get();
+    TEST_ASSERT_EQUAL(NO_FLAGS, flags);
+}
+
+/** Test if clear on empty EventFlags object return NO_FLAGS
+
+    Given a empty EventFlags object
+    When call @a clear(NO_FLAGS)
+    Then @a clear return status is NO_FLAGS
+ */
+void test_empty_clear(void)
+{
+    EventFlags ev;
+    uint32_t flags;
+
+    flags = ev.clear(NO_FLAGS);
+    TEST_ASSERT_EQUAL(NO_FLAGS, flags);
+}
+
+/** Test if set on empty EventFlags object return NO_FLAGS
+
+    Given a empty EventFlags object
+    When call @a set(NO_FLAGS)
+    Then @a set return status is NO_FLAGS
+ */
+void test_empty_set(void)
+{
+    EventFlags ev;
+    uint32_t flags;
+
+    flags = ev.set(NO_FLAGS);
+    TEST_ASSERT_EQUAL(NO_FLAGS, flags);
+}
+
+/** Test if call of set/clean with PROHIBITED_FLAG doesn't invalidates object flags
+
+    Given a EventFlags object with all flags already set
+    When call @a clear(PROHIBITED_FLAG) with prohibited flag
+    Then @a clear return status is osFlagsErrorParameter and object flags stays unchanged
+    When call @a set(PROHIBITED_FLAG) with prohibited flag
+    Then @a set return status is osFlagsErrorParameter and object flags stays unchanged
+
+    @note Each signal has up to 31 event flags 0x1, 0x2, 0x4, 0x8, ...,  0x40000000
+          Most significant bit is reserved and thereby flag 0x80000000 is prohibited
+ */
+void test_prohibited(void)
+{
+    EventFlags ev;
+    uint32_t flags;
+
+    ev.set(FLAG01 | FLAG02 | FLAG03);
+
+    flags = ev.clear(PROHIBITED_FLAG);
+    TEST_ASSERT_EQUAL(osFlagsErrorParameter, flags);
+
+    flags = ev.get();
+    TEST_ASSERT_EQUAL(FLAG01 | FLAG02 | FLAG03, flags);
+
+    flags = ev.set(PROHIBITED_FLAG);
+    TEST_ASSERT_EQUAL(osFlagsErrorParameter, flags);
+
+    flags = ev.get();
+    TEST_ASSERT_EQUAL(FLAG01 | FLAG02 | FLAG03, flags);
+}
+
+/** Test set/get/clear for full flag range
+
+    Given a EventFlags object
+    When call @a clear
+    Then @a clear return status is already set flags
+    When call @a set with specified flag
+    Then @a set return status is flags after setting
+    When call @a get
+    Then @a get return status is set flags
+ */
+void test_set_get_clear_full_flag_range(void)
+{
+    EventFlags ev;
+    uint32_t flag, flags, ret;
+
+    flags = NO_FLAGS;
+    for (int i = 0; i <= MAX_FLAG_POS; i++) {
+        ret = ev.clear();
+        TEST_ASSERT_EQUAL(flags, ret);
+        flags = 1 << i;
+        ret = ev.set(flags);
+        TEST_ASSERT_EQUAL(flags, ret);
+        ret = ev.get();
+        TEST_ASSERT_EQUAL(flags, ret);
+    }
+
+    ev.clear();
+    flags = NO_FLAGS;
+    for (int i = 0; i <= MAX_FLAG_POS; i++) {
+        ret = ev.clear(NO_FLAGS);
+        TEST_ASSERT_EQUAL(flags, ret);
+        flag = 1 << i;
+        flags |= flag;
+        ret = ev.set(flag);
+        TEST_ASSERT_EQUAL(flags, ret);
+        ret = ev.get();
+        TEST_ASSERT_EQUAL(flags, ret);
+    }
+}
+
+/** Test if multi-threaded flag set cause wait_all to return
+
+    Given a EventFlags object and three threads are started in parallel
+    When threads set specified flags
+    Then main thread waits until receive all of them
+ */
+void test_multi_thread_all(void)
+{
+    EventFlags ef;
+    Thread thread1(osPriorityNormal, THREAD_STACK_SIZE);
+    Thread thread2(osPriorityNormal, THREAD_STACK_SIZE);
+    Thread thread3(osPriorityNormal, THREAD_STACK_SIZE);
+    thread1.start(callback(send_thread<FLAG01, 1>, &ef));
+    thread2.start(callback(send_thread<FLAG02, 2>, &ef));
+    thread3.start(callback(send_thread<FLAG03, 3>, &ef));
+
+    uint32_t ret = ef.wait_all(FLAG01 | FLAG02 | FLAG03);
+    TEST_ASSERT_EQUAL(FLAG01 | FLAG02 | FLAG03, ret);
+}
+
+/** Test if multi-threaded flag set cause wait_any to return
+
+    Given a EventFlags object and three threads are started in parallel
+    When threads set specified flags
+    Then main thread waits until receive all of them
+ */
+void test_multi_thread_any(void)
+{
+    EventFlags ef;
+    uint32_t ret;
+    Thread thread1(osPriorityNormal, THREAD_STACK_SIZE);
+    Thread thread2(osPriorityNormal, THREAD_STACK_SIZE);
+    Thread thread3(osPriorityNormal, THREAD_STACK_SIZE);
+    thread1.start(callback(send_thread<FLAG01, 1>, &ef));
+    thread2.start(callback(send_thread<FLAG02, 1>, &ef));
+    thread3.start(callback(send_thread<FLAG03, 1>, &ef));
+
+    for (int i = 0; i <= MAX_FLAG_POS; i++) {
+        uint32_t flag = 1 << i;
+        ret = ef.wait_any(flag);
+        TEST_ASSERT(flag | ret);
+    }
+    ret = ef.get();
+    TEST_ASSERT_EQUAL(NO_FLAGS, ret);
+}
+
+/** Test if multi-threaded flag set cause wait_any(with timeout) to return
+
+    Given a EventFlags object and thread is running
+    When main thread call @ wait_any with timeout
+    Then when timeout expires @ wait_any return status is osFlagsErrorTimeout
+    When main thread call @ wait_any with timeout and thread set specified flags
+    Then main thread waits until receive all of them and @ wait_any return status is wait flag
+ */
+void test_multi_thread_any_timeout(void)
+{
+    EventFlags ef;
+    uint32_t ret;
+    Thread thread(osPriorityNormal, THREAD_STACK_SIZE);
+    thread.start(callback(send_thread_sync<FLAG01 | FLAG02 | FLAG03, 1>, &ef));
+
+    for (int i = 0; i <= MAX_FLAG_POS; i++) {
+        uint32_t flag = 1 << i;
+
+        ret = ef.wait_any(flag, 10);
+        TEST_ASSERT_EQUAL(osFlagsErrorTimeout, ret);
+
+        sync_sem.release();
+        ret = ef.wait_any(flag, 10);
+        TEST_ASSERT_EQUAL(flag, ret);
+    }
+    ret = ef.get();
+    TEST_ASSERT_EQUAL(NO_FLAGS, ret);
+}
+
+/** Test if multi-threaded flag set cause wait_any(without clear) to return
+
+    Given a EventFlags object and three threads are started in parallel
+    When threads set specified flags
+    Then main thread waits until receive all of them
+ */
+void test_multi_thread_any_no_clear(void)
+{
+    EventFlags ef;
+    uint32_t ret;
+    Thread thread1(osPriorityNormal, THREAD_STACK_SIZE);
+    Thread thread2(osPriorityNormal, THREAD_STACK_SIZE);
+    Thread thread3(osPriorityNormal, THREAD_STACK_SIZE);
+    thread1.start(callback(send_thread<FLAG01, 1>, &ef));
+    thread2.start(callback(send_thread<FLAG02, 1>, &ef));
+    thread3.start(callback(send_thread<FLAG03, 1>, &ef));
+
+    for (int i = 0; i <= MAX_FLAG_POS; i++) {
+        uint32_t flag = 1 << i;
+        ret = ef.wait_any(flag, osWaitForever, false);
+        TEST_ASSERT(flag | ret);
+        ret = ef.clear(flag);
+        TEST_ASSERT(ret < osFlagsError);
+    }
+    ret = ef.get();
+    TEST_ASSERT_EQUAL(NO_FLAGS, ret);
+}
+
+/** Test multi-threaded wait_any
+
+    Given a EventFlags object and three threads are started in parallel
+    When flags are set in main thread
+    Then other threads waits until receive all of them
+ */
+void test_multi_thread_all_many_wait(void)
+{
+    EventFlags ef;
+    {
+        Thread thread1(osPriorityNormal, THREAD_STACK_SIZE);
+        Thread thread2(osPriorityNormal, THREAD_STACK_SIZE);
+        Thread thread3(osPriorityNormal, THREAD_STACK_SIZE);
+        thread1.start(callback(wait_thread_all<FLAG01>, &ef));
+        thread2.start(callback(wait_thread_all<FLAG02>, &ef));
+        thread3.start(callback(wait_thread_all<FLAG03>, &ef));
+
+        ef.set(FLAG01 | FLAG02 | FLAG03);
+        thread1.join();
+        thread2.join();
+        thread3.join();
+        TEST_ASSERT_EQUAL(NO_FLAGS, ef.get());
     }
-    GREENTEA_TESTSUITE_RESULT(result);
-    return 0;
+
+    {
+        Thread thread1(osPriorityNormal, THREAD_STACK_SIZE);
+        Thread thread2(osPriorityNormal, THREAD_STACK_SIZE);
+        Thread thread3(osPriorityNormal, THREAD_STACK_SIZE);
+        thread1.start(callback(wait_thread_all<FLAG01>, &ef));
+        thread2.start(callback(wait_thread_all<FLAG02>, &ef));
+        thread3.start(callback(wait_thread_all<FLAG03>, &ef));
+
+        ef.set(FLAG01);
+        thread1.join();
+        ef.set(FLAG02);
+        thread2.join();
+        ef.set(FLAG03);
+        thread3.join();
+        TEST_ASSERT_EQUAL(NO_FLAGS, ef.get());
+    }
+}
+
+utest::v1::status_t test_setup(const size_t number_of_cases)
+{
+    GREENTEA_SETUP(10, "default_auto");
+    return utest::v1::verbose_test_setup_handler(number_of_cases);
+}
+
+Case cases[] = {
+    Case("Test empty clear", test_empty_clear),
+    Case("Test empty get", test_empty_get),
+    Case("Test empty set", test_empty_set),
+    Case("Test clear/set with prohibited flag", test_prohibited),
+    Case("Test set/get/clear for full flag range", test_set_get_clear_full_flag_range),
+    Case("Test multi-threaded wait_all", test_multi_thread_all),
+    Case("Test multi-threaded wait_any", test_multi_thread_any),
+    Case("Test multi-threaded wait_all many wait", test_multi_thread_all_many_wait),
+    Case("Test multi-threaded wait_any timeout", test_multi_thread_any_timeout),
+    Case("Test multi-threaded wait_any no clear", test_multi_thread_any_no_clear)
+};
+
+utest::v1::Specification specification(test_setup, cases);
+
+int main()
+{
+    return !utest::v1::Harness::run(specification);
 }
diff --git a/rtos/TARGET_CORTEX/rtx5/TESTS/memory/heap_and_stack/main.cpp b/TESTS/mbedmicro-rtos-mbed/heap_and_stack/main.cpp
similarity index 100%
rename from rtos/TARGET_CORTEX/rtx5/TESTS/memory/heap_and_stack/main.cpp
rename to TESTS/mbedmicro-rtos-mbed/heap_and_stack/main.cpp
diff --git a/TESTS/mbedmicro-rtos-mbed/isr/main.cpp b/TESTS/mbedmicro-rtos-mbed/isr/main.cpp
deleted file mode 100644
index 1ba963f37d2..00000000000
--- a/TESTS/mbedmicro-rtos-mbed/isr/main.cpp
+++ /dev/null
@@ -1,77 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "mbed.h"
-#include "greentea-client/test_env.h"
-#include "rtos.h"
-
-#if defined(MBED_RTOS_SINGLE_THREAD)
-  #error [NOT_SUPPORTED] test not supported
-#endif
-
-#define QUEUE_SIZE              5
-#define THREAD_DELAY            250
-#define QUEUE_PUT_ISR_VALUE     128
-#define QUEUE_PUT_THREAD_VALUE  127
-
-#define TEST_STACK_SIZE 512
-
-Queue<uint32_t, QUEUE_SIZE> queue;
-
-DigitalOut myled(LED1);
-
-void queue_isr() {
-
-    queue.put((uint32_t*)QUEUE_PUT_ISR_VALUE);
-    myled = !myled;
-}
-
-void queue_thread() {
-    while (true) {
-        queue.put((uint32_t*)QUEUE_PUT_THREAD_VALUE);
-        Thread::wait(THREAD_DELAY);
-    }
-}
-
-int main (void) {
-    GREENTEA_SETUP(20, "default_auto");
-
-    Thread thread(osPriorityNormal, TEST_STACK_SIZE);
-    thread.start(queue_thread);
-    Ticker ticker;
-    ticker.attach(queue_isr, 1.0);
-    int isr_puts_counter = 0;
-    bool result = true;
-
-    while (true) {
-        osEvent evt = queue.get();
-        if (evt.status != osEventMessage) {
-            printf("QUEUE_GET: FAIL\r\n");
-            result = false;
-            break;
-        } else {
-            printf("QUEUE_GET: Value(%u) ... [OK]\r\n", evt.value.v);
-            if (evt.value.v == QUEUE_PUT_ISR_VALUE) {
-                isr_puts_counter++;
-            }
-            if (isr_puts_counter >= QUEUE_SIZE) {
-                break;
-            }
-        }
-    }
-
-    GREENTEA_TESTSUITE_RESULT(result);
-    return 0;
-}
diff --git a/TESTS/mbedmicro-rtos-mbed/mail/main.cpp b/TESTS/mbedmicro-rtos-mbed/mail/main.cpp
index 3332de41e10..ad006f8a942 100644
--- a/TESTS/mbedmicro-rtos-mbed/mail/main.cpp
+++ b/TESTS/mbedmicro-rtos-mbed/mail/main.cpp
@@ -25,7 +25,7 @@
 
 using namespace utest::v1;
 
-#define THREAD_STACK_SIZE   384 /* larger stack cause out of memory on some 16kB RAM boards in multi thread test*/
+#define THREAD_STACK_SIZE   320 /* larger stack cause out of heap memory on some 16kB RAM boards in multi thread test*/
 #define QUEUE_SIZE          16
 #define THREAD_1_ID         1
 #define THREAD_2_ID         2
diff --git a/TESTS/mbedmicro-rtos-mbed/malloc/main.cpp b/TESTS/mbedmicro-rtos-mbed/malloc/main.cpp
index 8c4cae324f3..e0fcd355e02 100644
--- a/TESTS/mbedmicro-rtos-mbed/malloc/main.cpp
+++ b/TESTS/mbedmicro-rtos-mbed/malloc/main.cpp
@@ -54,17 +54,22 @@ void task_using_malloc(void)
 
 int main()
 {
+    // static stack for threads to reduce heap usage on devices with small RAM
+    // and eliminate run out of heap memory problem
+    uint8_t stack[NUM_THREADS][THREAD_STACK_SIZE];
+
     Thread *thread_list[NUM_THREADS];
     int test_time = 15;
     GREENTEA_SETUP(20, "default_auto");
 
     // Allocate threads for the test
     for (int i = 0; i < NUM_THREADS; i++) {
-        thread_list[i] = new Thread(osPriorityNormal, THREAD_STACK_SIZE);
+        thread_list[i] = new Thread(osPriorityNormal, THREAD_STACK_SIZE, stack[i]);
         if (NULL == thread_list[i]) {
             allocation_failure = true;
+        } else {
+            thread_list[i]->start(task_using_malloc);
         }
-        thread_list[i]->start(task_using_malloc);
     }
 
     // Give the test time to run
diff --git a/TESTS/mbedmicro-rtos-mbed/mutex/main.cpp b/TESTS/mbedmicro-rtos-mbed/mutex/main.cpp
index a3aef568b09..0506a66dbd9 100644
--- a/TESTS/mbedmicro-rtos-mbed/mutex/main.cpp
+++ b/TESTS/mbedmicro-rtos-mbed/mutex/main.cpp
@@ -191,11 +191,12 @@ void test_dual_thread_lock_trylock_thread(Mutex *mutex)
 
 void test_dual_thread_lock_lock_thread(Mutex *mutex)
 {
-    uint32_t start = us_ticker_read();
+    Timer timer;
+    timer.start();
 
     osStatus stat = mutex->lock(TEST_DELAY);
     TEST_ASSERT_EQUAL(osErrorTimeout, stat);
-    TEST_ASSERT_UINT32_WITHIN(5000, TEST_DELAY*1000, us_ticker_read() - start);
+    TEST_ASSERT_UINT32_WITHIN(5000, TEST_DELAY*1000, timer.read_us());
 }
 
 /** Test dual thread lock
diff --git a/TESTS/mbedmicro-rtos-mbed/queue/main.cpp b/TESTS/mbedmicro-rtos-mbed/queue/main.cpp
index 374dc8662c6..d275784dbda 100644
--- a/TESTS/mbedmicro-rtos-mbed/queue/main.cpp
+++ b/TESTS/mbedmicro-rtos-mbed/queue/main.cpp
@@ -135,11 +135,12 @@ void test_get_empty_no_timeout()
 void test_get_empty_timeout()
 {
     Queue<uint32_t, 1> q;
-    uint32_t start = us_ticker_read();
+    Timer timer;
+    timer.start();
 
     osEvent evt = q.get(50);
     TEST_ASSERT_EQUAL(osEventTimeout, evt.status);
-    TEST_ASSERT_UINT32_WITHIN(5000, 50000, us_ticker_read() - start);
+    TEST_ASSERT_UINT32_WITHIN(5000, 50000, timer.read_us());
 }
 
 /** Test get empty wait forever
@@ -157,12 +158,13 @@ void test_get_empty_wait_forever()
 
     t.start(callback(thread_put_uint_msg<TEST_TIMEOUT>, &q));
 
-    uint32_t start = us_ticker_read();
+    Timer timer;
+    timer.start();
 
     osEvent evt = q.get();
     TEST_ASSERT_EQUAL(osEventMessage, evt.status);
     TEST_ASSERT_EQUAL(TEST_UINT_MSG, evt.value.v);
-    TEST_ASSERT_UINT32_WITHIN(TEST_TIMEOUT * 100, TEST_TIMEOUT * 1000, us_ticker_read() - start);
+    TEST_ASSERT_UINT32_WITHIN(TEST_TIMEOUT * 100, TEST_TIMEOUT * 1000, timer.read_us());
 }
 
 /** Test put full no timeout
@@ -195,11 +197,12 @@ void test_put_full_timeout()
     osStatus stat = q.put((uint32_t*) TEST_UINT_MSG, TEST_TIMEOUT);
     TEST_ASSERT_EQUAL(osOK, stat);
 
-    uint32_t start = us_ticker_read();
+    Timer timer;
+    timer.start();
 
     stat = q.put((uint32_t*) TEST_UINT_MSG, TEST_TIMEOUT);
     TEST_ASSERT_EQUAL(osErrorTimeout, stat);
-    TEST_ASSERT_UINT32_WITHIN(TEST_TIMEOUT * 100, TEST_TIMEOUT * 1000, us_ticker_read() - start);
+    TEST_ASSERT_UINT32_WITHIN(TEST_TIMEOUT * 100, TEST_TIMEOUT * 1000, timer.read_us());
 }
 
 /** Test put full wait forever
@@ -220,10 +223,11 @@ void test_put_full_waitforever()
     osStatus stat = q.put((uint32_t*) TEST_UINT_MSG);
     TEST_ASSERT_EQUAL(osOK, stat);
 
-    uint32_t start = us_ticker_read();
+    Timer timer;
+    timer.start();
     stat = q.put((uint32_t*) TEST_UINT_MSG, osWaitForever);
     TEST_ASSERT_EQUAL(osOK, stat);
-    TEST_ASSERT_UINT32_WITHIN(TEST_TIMEOUT * 100, TEST_TIMEOUT * 1000, us_ticker_read() - start);
+    TEST_ASSERT_UINT32_WITHIN(TEST_TIMEOUT * 100, TEST_TIMEOUT * 1000, timer.read_us());
 
     t.join();
 }
diff --git a/TESTS/mbedmicro-rtos-mbed/rtostimer/main.cpp b/TESTS/mbedmicro-rtos-mbed/rtostimer/main.cpp
new file mode 100644
index 00000000000..694ea04bf3a
--- /dev/null
+++ b/TESTS/mbedmicro-rtos-mbed/rtostimer/main.cpp
@@ -0,0 +1,349 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "rtos.h"
+
+using namespace utest::v1;
+
+#define DELAY_MS 50
+#define DELTA_MS 5
+#define RESTART_DELAY_MS 10
+#define DELAY2_MS 30
+
+#if RESTART_DELAY_MS >= DELAY_MS
+#error invalid RESTART_DELAY_MS value
+#endif
+
+class Stopwatch: public Timer {
+private:
+    Semaphore _sem;
+
+public:
+    Stopwatch() :
+            Timer(), _sem(1)
+    {
+    }
+
+    ~Stopwatch()
+    {
+    }
+
+    void start(void)
+    {
+        _sem.wait(0);
+        Timer::start();
+    }
+
+    void stop(void)
+    {
+        Timer::stop();
+        _sem.release();
+    }
+
+    int32_t wait_until_stopped(uint32_t millisec = osWaitForever)
+    {
+        core_util_critical_section_enter();
+        int running = _running;
+        core_util_critical_section_exit();
+        if (!running) {
+            return 1;
+        }
+        return _sem.wait(millisec);
+    }
+};
+
+void sem_callback(Semaphore *sem)
+{
+    sem->release();
+}
+
+/* In order to successfully run this test suite when compiled with --profile=debug
+ * error() has to be redefined as noop.
+ *
+ * RtosTimer calls RTX API which uses Event Recorder functionality. When compiled
+ * with MBED_TRAP_ERRORS_ENABLED=1 (set in debug profile) EvrRtxTimerError() calls error()
+ * which aborts test program.
+ */
+#if defined(MBED_TRAP_ERRORS_ENABLED) && MBED_TRAP_ERRORS_ENABLED
+void error(const char* format, ...)
+{
+    (void) format;
+}
+#endif
+
+/** Test one-shot not restarted when elapsed
+ *
+ * Given a one-shot RtosTimer
+ * When the timer is started
+ *     and given time elapses
+ * Then timer stops
+ *     and elapsed time matches given delay
+ *     and timer stays stopped
+ */
+void test_oneshot_not_restarted()
+{
+    Stopwatch stopwatch;
+    RtosTimer rtostimer(mbed::callback(&stopwatch, &Stopwatch::stop), osTimerOnce);
+
+    stopwatch.start();
+    osStatus status = rtostimer.start(DELAY_MS);
+    TEST_ASSERT_EQUAL(osOK, status);
+
+    int32_t slots = stopwatch.wait_until_stopped();
+    TEST_ASSERT_EQUAL(1, slots);
+    TEST_ASSERT_INT_WITHIN(DELTA_MS, DELAY_MS, stopwatch.read_ms());
+    stopwatch.start();
+
+    slots = stopwatch.wait_until_stopped(DELAY_MS + DELTA_MS);
+    TEST_ASSERT_EQUAL(0, slots);
+    status = rtostimer.stop();
+    TEST_ASSERT_EQUAL(osErrorResource, status);
+}
+
+/** Test periodic repeats continuously
+ *
+ * Given a periodic RtosTimer
+ * When timer is started
+ *     and given time elapses
+ * Then timer repeats its operation
+ * When timer is stopped
+ * Then timer stops operation
+ */
+void test_periodic_repeats()
+{
+    Stopwatch stopwatch;
+    RtosTimer rtostimer(mbed::callback(&stopwatch, &Stopwatch::stop), osTimerPeriodic);
+
+    stopwatch.start();
+    osStatus status = rtostimer.start(DELAY_MS);
+    TEST_ASSERT_EQUAL(osOK, status);
+
+    int32_t slots = stopwatch.wait_until_stopped();
+    int t1 = stopwatch.read_ms();
+    stopwatch.reset();
+    stopwatch.start();
+    TEST_ASSERT_EQUAL(1, slots);
+    TEST_ASSERT_INT_WITHIN(DELTA_MS, DELAY_MS, t1);
+
+    slots = stopwatch.wait_until_stopped();
+    TEST_ASSERT_EQUAL(1, slots);
+    TEST_ASSERT_INT_WITHIN(DELTA_MS, DELAY_MS, stopwatch.read_ms());
+    stopwatch.start();
+
+    status = rtostimer.stop();
+    TEST_ASSERT_EQUAL(osOK, status);
+
+    slots = stopwatch.wait_until_stopped(DELAY_MS + DELTA_MS);
+    TEST_ASSERT_EQUAL(0, slots);
+    status = rtostimer.stop();
+    TEST_ASSERT_EQUAL(osErrorResource, status);
+}
+
+/** Test timer can be started again
+ *
+ * Given a one-shot Rtosimer
+ * When the timer is started
+ *     and given time elapses
+ * Then timer stops
+ * When the timer is started again
+ *     and given time elapses
+ * Then timer stops again
+ */
+void test_start_again()
+{
+    Semaphore sem(0, 1);
+    RtosTimer rtostimer(mbed::callback(sem_callback, &sem), osTimerOnce);
+
+    osStatus status = rtostimer.start(DELAY_MS);
+    TEST_ASSERT_EQUAL(osOK, status);
+
+    int32_t slots = sem.wait(DELAY_MS + DELTA_MS);
+    TEST_ASSERT_EQUAL(1, slots);
+
+    status = rtostimer.stop();
+    TEST_ASSERT_EQUAL(osErrorResource, status);
+
+    status = rtostimer.start(DELAY_MS);
+    TEST_ASSERT_EQUAL(osOK, status);
+
+    slots = sem.wait(DELAY_MS + DELTA_MS);
+    TEST_ASSERT_EQUAL(1, slots);
+
+    status = rtostimer.stop();
+    TEST_ASSERT_EQUAL(osErrorResource, status);
+}
+
+/** Test timer restart updates delay
+ *
+ * Given a one-shot RtosTimer
+ * When the timer is started
+ *     and @a start is called again with a different delay before given time elapses
+ *     and updated delay elapses
+ * Then timer stops
+ *     and time elapsed since the second @a start call matches updated delay
+ */
+void test_restart_updates_delay()
+{
+    Stopwatch stopwatch;
+    RtosTimer rtostimer(mbed::callback(&stopwatch, &Stopwatch::stop), osTimerOnce);
+
+    stopwatch.start();
+    osStatus status = rtostimer.start(DELAY_MS);
+    TEST_ASSERT_EQUAL(osOK, status);
+
+    int32_t slots = stopwatch.wait_until_stopped(RESTART_DELAY_MS);
+    TEST_ASSERT_EQUAL(0, slots);
+
+    stopwatch.reset();
+    stopwatch.start();
+    status = rtostimer.start(DELAY2_MS);
+    TEST_ASSERT_EQUAL(osOK, status);
+
+    slots = stopwatch.wait_until_stopped();
+    TEST_ASSERT_EQUAL(1, slots);
+    TEST_ASSERT_INT_WITHIN(DELTA_MS, DELAY2_MS, stopwatch.read_ms());
+
+    status = rtostimer.stop();
+    TEST_ASSERT_EQUAL(osErrorResource, status);
+}
+
+/** Test timer is created in stopped state
+ *
+ * Given a one-shot RtosTimer
+ * When the timer has not been started
+ * Then the timer is stopped
+ */
+void test_created_stopped()
+{
+    RtosTimer rtostimer(mbed::callback(sem_callback, (Semaphore *) NULL), osTimerOnce);
+    osStatus status = rtostimer.stop();
+    TEST_ASSERT_EQUAL(osErrorResource, status);
+}
+
+/** Test one-shot can be stopped
+ *
+ * Given a one-shot RtosTimer
+ * When the timer is started
+ *     and timer is stopped while still running
+ * Then timer stops operation
+ */
+void test_stop()
+{
+    Semaphore sem(0, 1);
+    RtosTimer rtostimer(mbed::callback(sem_callback, &sem), osTimerOnce);
+
+    osStatus status = rtostimer.start(DELAY_MS);
+    TEST_ASSERT_EQUAL(osOK, status);
+
+    int32_t slots = sem.wait(RESTART_DELAY_MS);
+    TEST_ASSERT_EQUAL(0, slots);
+
+    status = rtostimer.stop();
+    TEST_ASSERT_EQUAL(osOK, status);
+
+    slots = sem.wait(DELAY_MS + DELTA_MS);
+    TEST_ASSERT_EQUAL(0, slots);
+
+    status = rtostimer.stop();
+    TEST_ASSERT_EQUAL(osErrorResource, status);
+}
+
+/** Test timer started with infinite delay
+ *
+ * Given a one-shot RtosTimer
+ * When the timer is started with @a osWaitForever delay
+ * Then @a start return status is @a osOK
+ */
+void test_wait_forever()
+{
+    RtosTimer rtostimer(mbed::callback(sem_callback, (Semaphore *) NULL), osTimerOnce);
+
+    osStatus status = rtostimer.start(osWaitForever);
+    TEST_ASSERT_EQUAL(osOK, status);
+
+    status = rtostimer.stop();
+    TEST_ASSERT_EQUAL(osOK, status);
+}
+
+/** Test timer started with zero delay
+ *
+ * Given a one-shot RtosTimer
+ * When the timer is started with 0 delay
+ * Then @a start return status is @a osErrorParameter
+ */
+void test_no_wait()
+{
+    RtosTimer rtostimer(mbed::callback(sem_callback, (Semaphore *) NULL), osTimerOnce);
+
+    osStatus status = rtostimer.start(0);
+    TEST_ASSERT_EQUAL(osErrorParameter, status);
+
+    status = rtostimer.stop();
+    TEST_ASSERT_EQUAL(osErrorResource, status);
+}
+
+void rtostimer_isr_call(RtosTimer *rtostimer)
+{
+    osStatus status = rtostimer->start(DELAY_MS);
+    TEST_ASSERT_EQUAL(osErrorISR, status);
+
+    status = rtostimer->stop();
+    TEST_ASSERT_EQUAL(osErrorISR, status);
+}
+
+/** Test timer method calls from an ISR fail
+ *
+ * Given a one-shot RtosTimer
+ * When a timer method is called from an ISR
+ * Then method return status is @a osErrorISR
+ */
+void test_isr_calls_fail()
+{
+    RtosTimer rtostimer(mbed::callback(sem_callback, (Semaphore *) NULL), osTimerOnce);
+
+    Ticker ticker;
+    ticker.attach(mbed::callback(rtostimer_isr_call, &rtostimer), (float) DELAY_MS / 1000.0);
+
+    wait_ms(DELAY_MS + DELTA_MS);
+}
+
+utest::v1::status_t test_setup(const size_t number_of_cases)
+{
+    GREENTEA_SETUP(5, "default_auto");
+    return verbose_test_setup_handler(number_of_cases);
+}
+
+Case cases[] = {
+    Case("One-shot not restarted when elapsed", test_oneshot_not_restarted),
+    Case("Periodic repeats continuously", test_periodic_repeats),
+    Case("Stopped timer can be started again", test_start_again),
+    Case("Restart changes timeout", test_restart_updates_delay),
+    Case("Timer can be stopped", test_stop),
+    Case("Timer is created in stopped state", test_created_stopped),
+    Case("Timer started with infinite delay", test_wait_forever),
+    Case("Timer started with zero delay", test_no_wait),
+    Case("Calls from ISR fail", test_isr_calls_fail)
+};
+
+Specification specification(test_setup, cases);
+
+int main()
+{
+    return !Harness::run(specification);
+}
diff --git a/TESTS/mbedmicro-rtos-mbed/semaphore/main.cpp b/TESTS/mbedmicro-rtos-mbed/semaphore/main.cpp
index 33f50204c9f..ce211752080 100644
--- a/TESTS/mbedmicro-rtos-mbed/semaphore/main.cpp
+++ b/TESTS/mbedmicro-rtos-mbed/semaphore/main.cpp
@@ -30,7 +30,7 @@ using namespace utest::v1;
 #define SEM_CHANGES      100
 #define SHORT_WAIT       5
 
-#define THREAD_STACK_SIZE 512
+#define THREAD_STACK_SIZE 320 /* larger stack cause out of heap memory on some 16kB RAM boards in multi thread test*/
 
 Semaphore two_slots(SEMAPHORE_SLOTS);
 
@@ -152,7 +152,8 @@ void test_timeout()
     Semaphore sem(0);
     osStatus res;
 
-    uint32_t start = us_ticker_read();
+    Timer timer;
+    timer.start();
     res = t.start(callback(timeout_thread, &sem));
     TEST_ASSERT_EQUAL(osOK, res);
     Thread::wait(SHORT_WAIT);
@@ -160,7 +161,7 @@ void test_timeout()
     TEST_ASSERT_EQUAL(Thread::WaitingSemaphore, t.get_state());
 
     t.join();
-    TEST_ASSERT_UINT32_WITHIN(5000, 30000, us_ticker_read() - start);
+    TEST_ASSERT_UINT32_WITHIN(5000, 30000, timer.read_us());
 }
 
 /** Test no timeouts
@@ -180,12 +181,13 @@ void test_no_timeout()
 {
     Semaphore sem(T);
 
-    uint32_t start = us_ticker_read();
+    Timer timer;
+    timer.start();
 
     int32_t cnt = sem.wait(0);
     TEST_ASSERT_EQUAL(T, cnt);
 
-    TEST_ASSERT_UINT32_WITHIN(5000, 0, us_ticker_read() - start);
+    TEST_ASSERT_UINT32_WITHIN(5000, 0, timer.read_us());
 }
 
 /** Test multiple tokens wait
diff --git a/TESTS/mbedmicro-rtos-mbed/threads/main.cpp b/TESTS/mbedmicro-rtos-mbed/threads/main.cpp
index 1ece21524df..931d14d941b 100644
--- a/TESTS/mbedmicro-rtos-mbed/threads/main.cpp
+++ b/TESTS/mbedmicro-rtos-mbed/threads/main.cpp
@@ -377,11 +377,12 @@ void test_thread_stack_info() {
     then the thread sleeps for given amount of time
  */
 void test_thread_wait() {
-    uint32_t start = us_ticker_read();
+    Timer timer;
+    timer.start();
 
     Thread::wait(150);
 
-    TEST_ASSERT_UINT32_WITHIN(50000, 150000, us_ticker_read() - start);
+    TEST_ASSERT_UINT32_WITHIN(50000, 150000, timer.read_us());
 }
 
 /** Testing thread name
@@ -656,7 +657,7 @@ void test_thread_prio() {
 }
 
 utest::v1::status_t test_setup(const size_t number_of_cases) {
-    GREENTEA_SETUP(15, "default_auto");
+    GREENTEA_SETUP(20, "default_auto");
     return verbose_test_setup_handler(number_of_cases);
 }
 
diff --git a/features/FEATURE_LWIP/TESTS/mbedmicro-net/connectivity/main.cpp b/TESTS/netsocket/connectivity/main.cpp
similarity index 59%
rename from features/FEATURE_LWIP/TESTS/mbedmicro-net/connectivity/main.cpp
rename to TESTS/netsocket/connectivity/main.cpp
index 67119ea20fb..3330d2bbc37 100644
--- a/features/FEATURE_LWIP/TESTS/mbedmicro-net/connectivity/main.cpp
+++ b/TESTS/netsocket/connectivity/main.cpp
@@ -1,64 +1,57 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
+/*
+ * Copyright (c) 2013-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
-#if !FEATURE_LWIP
-    #error [NOT_SUPPORTED] LWIP not supported for this target
-#endif
-#if DEVICE_EMAC
-    #error [NOT_SUPPORTED] Not supported for WiFi targets
-#endif
+
+ #ifndef MBED_CONF_APP_CONNECT_STATEMENT
+     #error [NOT_SUPPORTED] No network configuration found for this target.
+ #endif
 
 #include "mbed.h"
 #include "greentea-client/test_env.h"
 #include "unity.h"
 #include "utest.h"
-
-#include "EthernetInterface.h"
+#include MBED_CONF_APP_HEADER_FILE
 
 using namespace utest::v1;
 
-
 // Bringing the network up and down
 template <int COUNT>
 void test_bring_up_down() {
-    EthernetInterface eth;
+    NetworkInterface* net = MBED_CONF_APP_OBJECT_CONSTRUCTION;
 
     for (int i = 0; i < COUNT; i++) {
-        int err = eth.connect();
+        int err = MBED_CONF_APP_CONNECT_STATEMENT;
         TEST_ASSERT_EQUAL(0, err);
 
-        printf("MBED: IP Address %s\r\n", eth.get_ip_address());
-        printf("MBED: Netmask %s\r\n", eth.get_netmask());
-        printf("MBED: Gateway %s\r\n", eth.get_gateway());
-        TEST_ASSERT(eth.get_ip_address());
-        TEST_ASSERT(eth.get_netmask());
-        TEST_ASSERT(eth.get_gateway());
+        printf("MBED: IP Address %s\r\n", net->get_ip_address());
+        TEST_ASSERT(net->get_ip_address());
 
         UDPSocket udp;
-        err = udp.open(&eth);
+        err = udp.open(net);
         TEST_ASSERT_EQUAL(0, err);
         err = udp.close();
         TEST_ASSERT_EQUAL(0, err);
 
         TCPSocket tcp;
-        err = tcp.open(&eth);
+        err = tcp.open(net);
         TEST_ASSERT_EQUAL(0, err);
         err = tcp.close();
         TEST_ASSERT_EQUAL(0, err);
 
-        err = eth.disconnect();
+        err = net->disconnect();
         TEST_ASSERT_EQUAL(0, err);
     }
 }
diff --git a/features/FEATURE_LWIP/TESTS/mbedmicro-net/gethostbyname/main.cpp b/TESTS/netsocket/gethostbyname/main.cpp
similarity index 75%
rename from features/FEATURE_LWIP/TESTS/mbedmicro-net/gethostbyname/main.cpp
rename to TESTS/netsocket/gethostbyname/main.cpp
index b0a5d4eb7b7..23eabc9be33 100644
--- a/features/FEATURE_LWIP/TESTS/mbedmicro-net/gethostbyname/main.cpp
+++ b/TESTS/netsocket/gethostbyname/main.cpp
@@ -1,30 +1,29 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
+/*
+ * Copyright (c) 2013-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
-#if !FEATURE_LWIP
-    #error [NOT_SUPPORTED] LWIP not supported for this target
-#endif
-#if DEVICE_EMAC
-    #error [NOT_SUPPORTED] Not supported for WiFi targets
-#endif
+
+ #ifndef MBED_CONF_APP_CONNECT_STATEMENT
+     #error [NOT_SUPPORTED] No network configuration found for this target.
+ #endif
 
 #include "mbed.h"
 #include "greentea-client/test_env.h"
 #include "unity.h"
 #include "utest.h"
-#include "EthernetInterface.h"
+#include MBED_CONF_APP_HEADER_FILE
 
 using namespace utest::v1;
 
@@ -34,20 +33,23 @@ using namespace utest::v1;
 #define MBED_DNS_TEST_HOST "connector.mbed.com"
 #endif
 
+
 // Address info from stack
 const char *ip_literal;
 nsapi_version_t ip_pref;
 const char *ip_pref_repr;
 
 // Network setup
-EthernetInterface net;
+NetworkInterface *net;
+
 void net_bringup() {
-    int err = net.connect();
+    net = MBED_CONF_APP_OBJECT_CONSTRUCTION;
+    int err =  MBED_CONF_APP_CONNECT_STATEMENT;
     TEST_ASSERT_EQUAL(0, err);
     printf("MBED: Connected to network\n");
-    printf("MBED: IP Address: %s\n", net.get_ip_address());
+    printf("MBED: IP Address: %s\n", net->get_ip_address());
 
-    ip_literal = net.get_ip_address();
+    ip_literal = net->get_ip_address();
     ip_pref = SocketAddress(ip_literal).get_ip_version();
     ip_pref_repr = (ip_pref == NSAPI_IPv4) ? "ipv4" :
                    (ip_pref == NSAPI_IPv6) ? "ipv6" : "unspec";
@@ -57,7 +59,7 @@ void net_bringup() {
 // DNS tests
 void test_dns_query() {
     SocketAddress addr;
-    int err = net.gethostbyname(MBED_DNS_TEST_HOST, &addr);
+    int err = net->gethostbyname(MBED_DNS_TEST_HOST, &addr);
     printf("DNS: query \"%s\" => \"%s\"\n",
             MBED_DNS_TEST_HOST, addr.get_ip_address());
 
@@ -68,7 +70,7 @@ void test_dns_query() {
 
 void test_dns_query_pref() {
     SocketAddress addr;
-    int err = net.gethostbyname(MBED_DNS_TEST_HOST, &addr, ip_pref);
+    int err = net->gethostbyname(MBED_DNS_TEST_HOST, &addr, ip_pref);
     printf("DNS: query %s \"%s\" => \"%s\"\n",
             ip_pref_repr, MBED_DNS_TEST_HOST, addr.get_ip_address());
 
@@ -80,7 +82,7 @@ void test_dns_query_pref() {
 
 void test_dns_literal() {
     SocketAddress addr;
-    int err = net.gethostbyname(ip_literal, &addr);
+    int err = net->gethostbyname(ip_literal, &addr);
     printf("DNS: literal \"%s\" => \"%s\"\n",
             ip_literal, addr.get_ip_address());
 
@@ -92,7 +94,7 @@ void test_dns_literal() {
 
 void test_dns_literal_pref() {
     SocketAddress addr;
-    int err = net.gethostbyname(ip_literal, &addr, ip_pref);
+    int err = net->gethostbyname(ip_literal, &addr, ip_pref);
     printf("DNS: literal %s \"%s\" => \"%s\"\n",
             ip_pref_repr, ip_literal, addr.get_ip_address());
 
diff --git a/features/FEATURE_LWIP/TESTS/mbedmicro-net/host_tests/tcp_echo.py b/TESTS/netsocket/host_tests/tcp_echo.py
similarity index 100%
rename from features/FEATURE_LWIP/TESTS/mbedmicro-net/host_tests/tcp_echo.py
rename to TESTS/netsocket/host_tests/tcp_echo.py
diff --git a/features/FEATURE_LWIP/TESTS/mbedmicro-net/host_tests/udp_echo.py b/TESTS/netsocket/host_tests/udp_echo.py
similarity index 100%
rename from features/FEATURE_LWIP/TESTS/mbedmicro-net/host_tests/udp_echo.py
rename to TESTS/netsocket/host_tests/udp_echo.py
diff --git a/features/FEATURE_LWIP/TESTS/mbedmicro-net/host_tests/udp_shotgun.py b/TESTS/netsocket/host_tests/udp_shotgun.py
similarity index 100%
rename from features/FEATURE_LWIP/TESTS/mbedmicro-net/host_tests/udp_shotgun.py
rename to TESTS/netsocket/host_tests/udp_shotgun.py
diff --git a/TESTS/netsocket/ip_parsing/main.cpp b/TESTS/netsocket/ip_parsing/main.cpp
index 6d00816256f..1ffe8058987 100644
--- a/TESTS/netsocket/ip_parsing/main.cpp
+++ b/TESTS/netsocket/ip_parsing/main.cpp
@@ -1,18 +1,24 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
+/*
+ * Copyright (c) 2013-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
+
+ #ifndef MBED_CONF_APP_CONNECT_STATEMENT
+     #error [NOT_SUPPORTED] No network configuration found for this target.
+ #endif
+
 #include "mbed.h"
 #include "greentea-client/test_env.h"
 #include "unity.h"
diff --git a/TESTS/netsocket/socket_sigio/main.cpp b/TESTS/netsocket/socket_sigio/main.cpp
new file mode 100644
index 00000000000..6c357abd4a6
--- /dev/null
+++ b/TESTS/netsocket/socket_sigio/main.cpp
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2013-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ #ifndef MBED_CONF_APP_CONNECT_STATEMENT
+     #error [NOT_SUPPORTED] No network configuration found for this target.
+ #endif
+
+#include <algorithm>
+#include "mbed.h"
+#include MBED_CONF_APP_HEADER_FILE
+#include "TCPSocket.h"
+#include "greentea-client/test_env.h"
+#include "unity/unity.h"
+#include "utest.h"
+
+using namespace utest::v1;
+
+
+namespace {
+    // Test connection information
+    const char *HTTP_SERVER_NAME = "os.mbed.com";
+    const char *HTTP_SERVER_FILE_PATH = "/media/uploads/mbed_official/hello.txt";
+    const int HTTP_SERVER_PORT = 80;
+#if defined(TARGET_VK_RZ_A1H)
+    const int RECV_BUFFER_SIZE = 300;
+#else
+    const int RECV_BUFFER_SIZE = 512;
+#endif
+    // Test related data
+    const char *HTTP_OK_STR = "200 OK";
+    const char *HTTP_HELLO_STR = "Hello world!";
+
+    // Test buffers
+    char buffer[RECV_BUFFER_SIZE] = {0};
+
+    Semaphore recvd;
+    NetworkInterface *net;
+}
+
+void net_bringup() {
+    net = MBED_CONF_APP_OBJECT_CONSTRUCTION;
+    int err =  MBED_CONF_APP_CONNECT_STATEMENT;
+    TEST_ASSERT_EQUAL(0, err);
+}
+
+bool find_substring(const char *first, const char *last, const char *s_first, const char *s_last) {
+    const char *f = std::search(first, last, s_first, s_last);
+    return (f != last);
+}
+
+void get_data(TCPSocket* sock){
+    bool result = false;
+    // Server will respond with HTTP GET's success code
+    const int ret = sock->recv(buffer, sizeof(buffer) - 1);
+    if(ret <= 0)
+        return;
+
+    buffer[ret] = '\0';
+
+    // Find 200 OK HTTP status in reply
+    bool found_200_ok = find_substring(buffer, buffer + ret, HTTP_OK_STR, HTTP_OK_STR + strlen(HTTP_OK_STR));
+    // Find "Hello World!" string in reply
+    bool found_hello = find_substring(buffer, buffer + ret, HTTP_HELLO_STR, HTTP_HELLO_STR + strlen(HTTP_HELLO_STR));
+
+    TEST_ASSERT_TRUE(found_200_ok);
+    TEST_ASSERT_TRUE(found_hello);
+
+    if (found_200_ok && found_hello) result = true;
+
+    TEST_ASSERT_EQUAL(result, true);
+
+    printf("HTTP: Received %d chars from server\r\n", ret);
+    printf("HTTP: Received 200 OK status ... %s\r\n", found_200_ok ? "[OK]" : "[FAIL]");
+    printf("HTTP: Received '%s' status ... %s\r\n", HTTP_HELLO_STR, found_hello ? "[OK]" : "[FAIL]");
+    printf("HTTP: Received message:\r\n");
+    printf("%s", buffer);
+    // Signal that we have recvd
+    recvd.release();
+}
+
+void prep_buffer() {
+    memset(buffer, 0, sizeof(buffer));
+    // We are constructing GET command like this:
+    // GET http://developer.mbed.org/media/uploads/mbed_official/hello.txt HTTP/1.0\n\n
+    strcpy(buffer, "GET http://");
+    strcat(buffer, HTTP_SERVER_NAME);
+    strcat(buffer, HTTP_SERVER_FILE_PATH);
+    strcat(buffer, " HTTP/1.0\n\n");
+}
+
+void test_socket_attach() {
+    // Dispatch event queue
+    Thread eventThread;
+    EventQueue queue(4*EVENTS_EVENT_SIZE);
+    eventThread.start(callback(&queue, &EventQueue::dispatch_forever));
+
+    printf("TCP client IP Address is %s\r\n", net->get_ip_address());
+
+    TCPSocket sock(net);
+    printf("HTTP: Connection to %s:%d\r\n", HTTP_SERVER_NAME, HTTP_SERVER_PORT);
+    if (sock.connect(HTTP_SERVER_NAME, HTTP_SERVER_PORT) == 0) {
+        printf("HTTP: OK\r\n");
+
+        prep_buffer();
+        // Attach a sigio function that adds function to event queue
+        sock.sigio(queue.event(get_data, &sock));
+        // Send GET command
+        sock.send(buffer, strlen(buffer));
+        // wait for recv data
+        recvd.wait();
+    } else {
+        printf("HTTP: ERROR\r\n");
+    }
+    sock.close();
+}
+
+void cb_fail() {
+    TEST_ASSERT(false);
+}
+
+void cb_pass() {
+    recvd.release();
+}
+
+void test_socket_detach() {
+    // Dispatch event queue
+    Thread eventThread;
+    EventQueue queue(4*EVENTS_EVENT_SIZE);
+    eventThread.start(callback(&queue, &EventQueue::dispatch_forever));
+
+    printf("TCP client IP Address is %s\r\n", net->get_ip_address());
+
+    TCPSocket sock(net);
+    printf("HTTP: Connection to %s:%d\r\n", HTTP_SERVER_NAME, HTTP_SERVER_PORT);
+    if (sock.connect(HTTP_SERVER_NAME, HTTP_SERVER_PORT) == 0) {
+        printf("HTTP: OK\r\n");
+
+        prep_buffer();
+        // Attach a sigio function that adds function to event queue
+        sock.sigio(queue.event(cb_fail));
+        // Detach function
+        sock.sigio(NULL);
+        // Send GET command
+        sock.send(buffer, strlen(buffer));
+        wait(5);
+    } else {
+        printf("HTTP: ERROR\r\n");
+    }
+    sock.close();
+}
+
+void test_socket_reattach() {
+    // Dispatch event queue
+    Thread eventThread;
+    EventQueue queue(4*EVENTS_EVENT_SIZE);
+    eventThread.start(callback(&queue, &EventQueue::dispatch_forever));
+
+    printf("TCP client IP Address is %s\r\n", net->get_ip_address());
+
+    TCPSocket sock(net);
+    printf("HTTP: Connection to %s:%d\r\n", HTTP_SERVER_NAME, HTTP_SERVER_PORT);
+    if (sock.connect(HTTP_SERVER_NAME, HTTP_SERVER_PORT) == 0) {
+        printf("HTTP: OK\r\n");
+
+        prep_buffer();
+        // Attach a sigio function that adds function to event queue
+        sock.sigio(queue.event(cb_fail));
+        // Override previous attach
+        sock.sigio(queue.event(cb_pass));
+        // Send GET command
+        sock.send(buffer, strlen(buffer));
+        recvd.wait();
+        TEST_ASSERT(true);
+    } else {
+        printf("HTTP: ERROR\r\n");
+    }
+    sock.close();
+}
+
+
+// Test setup
+utest::v1::status_t test_setup(const size_t number_of_cases) {
+    GREENTEA_SETUP(120, "default_auto");
+    net_bringup();
+    return verbose_test_setup_handler(number_of_cases);
+}
+
+Case cases[] = {
+    Case("Socket Attach Test", test_socket_attach),
+    Case("Socket Detach Test", test_socket_detach),
+    Case("Socket Reattach Test", test_socket_reattach),
+};
+
+Specification specification(test_setup, cases);
+
+int main() {
+    return !Harness::run(specification);
+}
diff --git a/features/FEATURE_LWIP/TESTS/mbedmicro-net/tcp_echo/main.cpp b/TESTS/netsocket/tcp_echo/main.cpp
similarity index 50%
rename from features/FEATURE_LWIP/TESTS/mbedmicro-net/tcp_echo/main.cpp
rename to TESTS/netsocket/tcp_echo/main.cpp
index 6324e6d1043..90124a28711 100644
--- a/features/FEATURE_LWIP/TESTS/mbedmicro-net/tcp_echo/main.cpp
+++ b/TESTS/netsocket/tcp_echo/main.cpp
@@ -1,27 +1,26 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
+/*
+ * Copyright (c) 2013-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
-#if !FEATURE_LWIP
-    #error [NOT_SUPPORTED] LWIP not supported for this target
-#endif
-#if DEVICE_EMAC
-    #error [NOT_SUPPORTED] Not supported for WiFi targets
-#endif
+
+ #ifndef MBED_CONF_APP_CONNECT_STATEMENT
+     #error [NOT_SUPPORTED] No network configuration found for this target.
+ #endif
 
 #include "mbed.h"
-#include "EthernetInterface.h"
+#include MBED_CONF_APP_HEADER_FILE
 #include "TCPSocket.h"
 #include "greentea-client/test_env.h"
 #include "unity/unity.h"
@@ -29,7 +28,6 @@
 
 using namespace utest::v1;
 
-
 #ifndef MBED_CFG_TCP_CLIENT_ECHO_BUFFER_SIZE
 #define MBED_CFG_TCP_CLIENT_ECHO_BUFFER_SIZE 256
 #endif
@@ -47,63 +45,67 @@ void prep_buffer(char *tx_buffer, size_t tx_size) {
 }
 
 void test_tcp_echo() {
-    EthernetInterface eth;
-    int err = eth.connect();
+
+    NetworkInterface* net = MBED_CONF_APP_OBJECT_CONSTRUCTION;
+    int err =  MBED_CONF_APP_CONNECT_STATEMENT;
 
     if (err) {
         printf("MBED: failed to connect with an error of %d\r\n", err);
         TEST_ASSERT_EQUAL(0, err);
     }
 
-    printf("MBED: TCPClient IP address is '%s'\n", eth.get_ip_address());
-    printf("MBED: TCPClient waiting for server IP and port...\n");
-
-    greentea_send_kv("target_ip", eth.get_ip_address());
+    printf("MBED: TCPClient IP address is '%s'\n", net->get_ip_address());
 
     bool result = false;
 
-    char recv_key[] = "host_port";
-    char ipbuf[60] = {0};
-    char portbuf[16] = {0};
-    unsigned int port = 0;
+    TCPSocket sock(net);
 
-    greentea_send_kv("host_ip", " ");
-    greentea_parse_kv(recv_key, ipbuf, sizeof(recv_key), sizeof(ipbuf));
+    SocketAddress tcp_addr(MBED_CONF_APP_ECHO_SERVER_ADDR, MBED_CONF_APP_ECHO_SERVER_PORT);
 
-    greentea_send_kv("host_port", " ");
-    greentea_parse_kv(recv_key, portbuf, sizeof(recv_key), sizeof(ipbuf));
-    sscanf(portbuf, "%u", &port);
-
-    printf("MBED: Server IP address received: %s:%d \n", ipbuf, port);
-
-    TCPSocket sock(&eth);
-    SocketAddress tcp_addr(ipbuf, port);
     if (sock.connect(tcp_addr) == 0) {
-        printf("HTTP: Connected to %s:%d\r\n", ipbuf, port);
+        printf("HTTP: Connected to %s:%d\r\n", MBED_CONF_APP_ECHO_SERVER_ADDR, MBED_CONF_APP_ECHO_SERVER_PORT);
         printf("tx_buffer buffer size: %u\r\n", sizeof(tx_buffer));
         printf("rx_buffer buffer size: %u\r\n", sizeof(rx_buffer));
 
         prep_buffer(tx_buffer, sizeof(tx_buffer));
-        sock.send(tx_buffer, sizeof(tx_buffer));
-        printf("MBED: Finished sending\r\n");
-        // Server will respond with HTTP GET's success code
-        const int ret = sock.recv(rx_buffer, sizeof(rx_buffer));
-        printf("MBED: Finished receiving\r\n");
+        sock.recv(rx_buffer, sizeof(MBED_CONF_APP_TCP_ECHO_PREFIX));
+        const int ret = sock.send(tx_buffer, sizeof(tx_buffer));
+        if (ret >= 0) {
+            printf("sent %d bytes - %.*s  \n", ret, ret, tx_buffer);
+        } else {
+            printf("Network error %d\n", ret);
+        }
+
+        int n = sock.recv(rx_buffer, sizeof(rx_buffer));
+        if (n >= 0) {
+            printf("recv %d bytes - %.*s  \n", n, n, rx_buffer);
+        } else {
+            printf("Network error %d\n", n);
+        }
 
         result = !memcmp(tx_buffer, rx_buffer, sizeof(tx_buffer));
         TEST_ASSERT_EQUAL(ret, sizeof(rx_buffer));
-        TEST_ASSERT(result);
+        TEST_ASSERT_EQUAL(true, result);
     }
 
     sock.close();
-    eth.disconnect();
-    TEST_ASSERT(result);
+    net->disconnect();
+    TEST_ASSERT_EQUAL(true, result);
 }
 
 
 // Test setup
 utest::v1::status_t test_setup(const size_t number_of_cases) {
-    GREENTEA_SETUP(120, "tcp_echo");
+    char uuid[48] = {0};
+    GREENTEA_SETUP(240, "tcp_echo");
+
+    // create mac address based on uuid
+    uint64_t mac = 0;
+    for (int i = 0; i < sizeof(uuid); i++) {
+        mac += uuid[i];
+    }
+    //mbed_set_mac_address((const char*)mac, /*coerce control bits*/ 1);
+
     return verbose_test_setup_handler(number_of_cases);
 }
 
diff --git a/features/FEATURE_LWIP/TESTS/mbedmicro-net/tcp_echo_parallel/main.cpp b/TESTS/netsocket/tcp_echo_parallel/main.cpp
similarity index 70%
rename from features/FEATURE_LWIP/TESTS/mbedmicro-net/tcp_echo_parallel/main.cpp
rename to TESTS/netsocket/tcp_echo_parallel/main.cpp
index 377a4229b66..c5b6ca0b63b 100644
--- a/features/FEATURE_LWIP/TESTS/mbedmicro-net/tcp_echo_parallel/main.cpp
+++ b/TESTS/netsocket/tcp_echo_parallel/main.cpp
@@ -1,27 +1,30 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
+/*
+ * Copyright (c) 2013-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
-#if !FEATURE_LWIP
-    #error [NOT_SUPPORTED] LWIP not supported for this target
-#endif
-#if DEVICE_EMAC
-    #error [NOT_SUPPORTED] Not supported for WiFi targets
+
+ #ifndef MBED_CONF_APP_CONNECT_STATEMENT
+     #error [NOT_SUPPORTED] No network configuration found for this target.
+ #endif
+
+#ifndef MBED_EXTENDED_TESTS
+    #error [NOT_SUPPORTED] Parallel tests are not supported by default
 #endif
 
 #include "mbed.h"
-#include "EthernetInterface.h"
+#include MBED_CONF_APP_HEADER_FILE
 #include "TCPSocket.h"
 #include "greentea-client/test_env.h"
 #include "unity/unity.h"
@@ -38,8 +41,11 @@ using namespace utest::v1;
 #define MBED_CFG_TCP_CLIENT_ECHO_THREADS 3
 #endif
 
+#define STRINGIZE(x) STRINGIZE2(x)
+#define STRINGIZE2(x) #x
 
-EthernetInterface net;
+
+NetworkInterface* net;
 SocketAddress tcp_addr;
 Mutex iomutex;
 
@@ -75,12 +81,16 @@ class Echo {
     }
 
     void echo() {
-        int err = sock.open(&net);
+        int err = sock.open(net);
         TEST_ASSERT_EQUAL(0, err);
 
         err = sock.connect(tcp_addr);
         TEST_ASSERT_EQUAL(0, err);
 
+        //recv connection prefix message
+        sock.recv(rx_buffer, sizeof(MBED_CONF_APP_TCP_ECHO_PREFIX));
+        memset(rx_buffer, 0, sizeof(rx_buffer));
+
         iomutex.lock();
         printf("HTTP: Connected to %s:%d\r\n",
                 tcp_addr.get_ip_address(), tcp_addr.get_port());
@@ -95,7 +105,7 @@ class Echo {
         const int ret = sock.recv(rx_buffer, sizeof(rx_buffer));
         bool result = !memcmp(tx_buffer, rx_buffer, sizeof(tx_buffer));
         TEST_ASSERT_EQUAL(ret, sizeof(rx_buffer));
-        TEST_ASSERT(result);
+        TEST_ASSERT_EQUAL(true, result);
 
         err = sock.close();
         TEST_ASSERT_EQUAL(0, err);
@@ -104,30 +114,16 @@ class Echo {
 
 Echo *echoers[MBED_CFG_TCP_CLIENT_ECHO_THREADS];
 
+
 void test_tcp_echo_parallel() {
-    int err = net.connect();
+    net = MBED_CONF_APP_OBJECT_CONSTRUCTION;
+    int err =  MBED_CONF_APP_CONNECT_STATEMENT;
     TEST_ASSERT_EQUAL(0, err);
 
-    printf("MBED: TCPClient IP address is '%s'\n", net.get_ip_address());
-    printf("MBED: TCPClient waiting for server IP and port...\n");
-
-    greentea_send_kv("target_ip", net.get_ip_address());
-
-    char recv_key[] = "host_port";
-    char ipbuf[60] = {0};
-    char portbuf[16] = {0};
-    unsigned int port = 0;
-
-    greentea_send_kv("host_ip", " ");
-    greentea_parse_kv(recv_key, ipbuf, sizeof(recv_key), sizeof(ipbuf));
-
-    greentea_send_kv("host_port", " ");
-    greentea_parse_kv(recv_key, portbuf, sizeof(recv_key), sizeof(ipbuf));
-    sscanf(portbuf, "%u", &port);
+    printf("MBED: TCPClient IP address is '%s'\n", net->get_ip_address());
 
-    printf("MBED: Server IP address received: %s:%d \n", ipbuf, port);
-    tcp_addr.set_ip_address(ipbuf);
-    tcp_addr.set_port(port);
+    tcp_addr.set_ip_address(MBED_CONF_APP_ECHO_SERVER_ADDR);
+    tcp_addr.set_port(MBED_CONF_APP_ECHO_SERVER_PORT);
 
     // Startup echo threads in parallel
     for (int i = 0; i < MBED_CFG_TCP_CLIENT_ECHO_THREADS; i++) {
@@ -140,7 +136,7 @@ void test_tcp_echo_parallel() {
         delete echoers[i];
     }
 
-    net.disconnect();
+    net->disconnect();
 }
 
 // Test setup
diff --git a/features/FEATURE_LWIP/TESTS/mbedmicro-net/tcp_hello_world/main.cpp b/TESTS/netsocket/tcp_hello_world/main.cpp
similarity index 78%
rename from features/FEATURE_LWIP/TESTS/mbedmicro-net/tcp_hello_world/main.cpp
rename to TESTS/netsocket/tcp_hello_world/main.cpp
index f5a0b0b9a98..9e42e21c046 100644
--- a/features/FEATURE_LWIP/TESTS/mbedmicro-net/tcp_hello_world/main.cpp
+++ b/TESTS/netsocket/tcp_hello_world/main.cpp
@@ -1,28 +1,27 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
+/*
+ * Copyright (c) 2013-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
-#if !FEATURE_LWIP
-    #error [NOT_SUPPORTED] LWIP not supported for this target
-#endif
-#if DEVICE_EMAC
-    #error [NOT_SUPPORTED] Not supported for WiFi targets
-#endif
+
+ #ifndef MBED_CONF_APP_CONNECT_STATEMENT
+     #error [NOT_SUPPORTED] No network configuration found for this target.
+ #endif
 
 #include <algorithm>
 #include "mbed.h"
-#include "EthernetInterface.h"
+#include MBED_CONF_APP_HEADER_FILE
 #include "TCPSocket.h"
 #include "greentea-client/test_env.h"
 #include "unity/unity.h"
@@ -33,7 +32,7 @@ using namespace utest::v1;
 
 namespace {
     // Test connection information
-    const char *HTTP_SERVER_NAME = "developer.mbed.org";
+    const char *HTTP_SERVER_NAME = "os.mbed.com";
     const char *HTTP_SERVER_FILE_PATH = "/media/uploads/mbed_official/hello.txt";
     const int HTTP_SERVER_PORT = 80;
 #if defined(TARGET_VK_RZ_A1H)
@@ -56,12 +55,11 @@ bool find_substring(const char *first, const char *last, const char *s_first, co
 
 void test_tcp_hello_world() {
     bool result = false;
-    EthernetInterface eth;
-    //eth.init(); //Use DHCP
-    eth.connect();
-    printf("TCP client IP Address is %s\r\n", eth.get_ip_address());
+    NetworkInterface* net = MBED_CONF_APP_OBJECT_CONSTRUCTION;
+    MBED_CONF_APP_CONNECT_STATEMENT;
+    printf("TCP client IP Address is %s\r\n", net->get_ip_address());
 
-    TCPSocket sock(&eth);
+    TCPSocket sock(net);
     printf("HTTP: Connection to %s:%d\r\n", HTTP_SERVER_NAME, HTTP_SERVER_PORT);
     if (sock.connect(HTTP_SERVER_NAME, HTTP_SERVER_PORT) == 0) {
         printf("HTTP: OK\r\n");
@@ -84,8 +82,8 @@ void test_tcp_hello_world() {
         // Find "Hello World!" string in reply
         bool found_hello = find_substring(buffer, buffer + ret, HTTP_HELLO_STR, HTTP_HELLO_STR + strlen(HTTP_HELLO_STR));
 
-        TEST_ASSERT(found_200_ok);
-        TEST_ASSERT(found_hello);
+        TEST_ASSERT_TRUE(found_200_ok);
+        TEST_ASSERT_TRUE(found_hello);
 
         if (found_200_ok && found_hello) result = true;
 
@@ -99,8 +97,8 @@ void test_tcp_hello_world() {
         printf("HTTP: ERROR\r\n");
     }
 
-    eth.disconnect();
-    TEST_ASSERT(result);
+    net->disconnect();
+    TEST_ASSERT_EQUAL(true, result);
 }
 
 
diff --git a/features/FEATURE_LWIP/TESTS/mbedmicro-net/tcp_packet_pressure/main.cpp b/TESTS/netsocket/tcp_packet_pressure/main.cpp
similarity index 82%
rename from features/FEATURE_LWIP/TESTS/mbedmicro-net/tcp_packet_pressure/main.cpp
rename to TESTS/netsocket/tcp_packet_pressure/main.cpp
index ec0731c9c78..48980bcf68c 100644
--- a/features/FEATURE_LWIP/TESTS/mbedmicro-net/tcp_packet_pressure/main.cpp
+++ b/TESTS/netsocket/tcp_packet_pressure/main.cpp
@@ -1,30 +1,30 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
+/*
+ * Copyright (c) 2013-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
-#if !FEATURE_LWIP
-    #error [NOT_SUPPORTED] LWIP not supported for this target
-#endif
-#if DEVICE_EMAC
-    #error [NOT_SUPPORTED] Not supported for WiFi targets
-#endif
+
+ #ifndef MBED_CONF_APP_CONNECT_STATEMENT
+     #error [NOT_SUPPORTED] No network configuration found for this target.
+ #endif
+
 #ifndef MBED_EXTENDED_TESTS
     #error [NOT_SUPPORTED] Pressure tests are not supported by default
 #endif
 
 #include "mbed.h"
-#include "EthernetInterface.h"
+#include MBED_CONF_APP_HEADER_FILE
 #include "TCPSocket.h"
 #include "greentea-client/test_env.h"
 #include "unity/unity.h"
@@ -49,6 +49,9 @@ using namespace utest::v1;
 #define MBED_CFG_TCP_CLIENT_PACKET_PRESSURE_DEBUG false
 #endif
 
+#define STRINGIZE(x) STRINGIZE2(x)
+#define STRINGIZE2(x) #x
+
 
 // Simple xorshift pseudorandom number generator
 class RandSeq {
@@ -131,31 +134,14 @@ void test_tcp_packet_pressure() {
         MBED_CFG_TCP_CLIENT_PACKET_PRESSURE_MAX);
     printf("MBED: Generated buffer %d\r\n", buffer_size);
 
-    EthernetInterface eth;
-    int err = eth.connect();
+    NetworkInterface* net = MBED_CONF_APP_OBJECT_CONSTRUCTION;
+    int err =  MBED_CONF_APP_CONNECT_STATEMENT;
     TEST_ASSERT_EQUAL(0, err);
 
-    printf("MBED: TCPClient IP address is '%s'\n", eth.get_ip_address());
-    printf("MBED: TCPClient waiting for server IP and port...\n");
-
-    greentea_send_kv("target_ip", eth.get_ip_address());
-
-    char recv_key[] = "host_port";
-    char ipbuf[60] = {0};
-    char portbuf[16] = {0};
-    unsigned int port = 0;
-
-    greentea_send_kv("host_ip", " ");
-    greentea_parse_kv(recv_key, ipbuf, sizeof(recv_key), sizeof(ipbuf));
-
-    greentea_send_kv("host_port", " ");
-    greentea_parse_kv(recv_key, portbuf, sizeof(recv_key), sizeof(ipbuf));
-    sscanf(portbuf, "%u", &port);
-
-    printf("MBED: Server IP address received: %s:%d \n", ipbuf, port);
+    printf("MBED: TCPClient IP address is '%s'\n", net->get_ip_address());
 
     TCPSocket sock;
-    SocketAddress tcp_addr(ipbuf, port);
+    SocketAddress tcp_addr(MBED_CONF_APP_ECHO_SERVER_ADDR, MBED_CONF_APP_ECHO_SERVER_PORT);
 
     Timer timer;
     timer.start();
@@ -164,11 +150,16 @@ void test_tcp_packet_pressure() {
     for (size_t size = MBED_CFG_TCP_CLIENT_PACKET_PRESSURE_MIN;
          size < MBED_CFG_TCP_CLIENT_PACKET_PRESSURE_MAX;
          size *= 2) {
-        err = sock.open(&eth);
+        err = sock.open(net);
         TEST_ASSERT_EQUAL(0, err);
         err = sock.connect(tcp_addr);
         TEST_ASSERT_EQUAL(0, err);
-        printf("TCP: %s:%d streaming %d bytes\r\n", ipbuf, port, size);
+        printf("TCP: %s:%d streaming %d bytes\r\n",
+            tcp_addr.get_ip_address(), tcp_addr.get_port(), size);
+
+        //recv connection prefix message
+        sock.recv(buffer, sizeof(MBED_CONF_APP_TCP_ECHO_PREFIX));
+        memset(buffer, 0, sizeof(buffer));
 
         sock.set_blocking(false);
 
@@ -237,7 +228,7 @@ void test_tcp_packet_pressure() {
             8*(2*MBED_CFG_TCP_CLIENT_PACKET_PRESSURE_MAX -
             MBED_CFG_TCP_CLIENT_PACKET_PRESSURE_MIN) / (1000*timer.read()));
 
-    eth.disconnect();
+    net->disconnect();
 }
 
 
diff --git a/features/FEATURE_LWIP/TESTS/mbedmicro-net/tcp_packet_pressure_parallel/main.cpp b/TESTS/netsocket/tcp_packet_pressure_parallel/main.cpp
similarity index 86%
rename from features/FEATURE_LWIP/TESTS/mbedmicro-net/tcp_packet_pressure_parallel/main.cpp
rename to TESTS/netsocket/tcp_packet_pressure_parallel/main.cpp
index 847e40ae15d..2c438a92d6f 100644
--- a/features/FEATURE_LWIP/TESTS/mbedmicro-net/tcp_packet_pressure_parallel/main.cpp
+++ b/TESTS/netsocket/tcp_packet_pressure_parallel/main.cpp
@@ -1,30 +1,30 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
+/*
+ * Copyright (c) 2013-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
-#if !FEATURE_LWIP
-    #error [NOT_SUPPORTED] LWIP not supported for this target
-#endif
-#if DEVICE_EMAC
-    #error [NOT_SUPPORTED] Not supported for WiFi targets
-#endif
+
+ #ifndef MBED_CONF_APP_CONNECT_STATEMENT
+     #error [NOT_SUPPORTED] No network configuration found for this target.
+ #endif
+
 #ifndef MBED_EXTENDED_TESTS
     #error [NOT_SUPPORTED] Parallel pressure tests are not supported by default
 #endif
 
 #include "mbed.h"
-#include "EthernetInterface.h"
+#include MBED_CONF_APP_HEADER_FILE
 #include "TCPSocket.h"
 #include "greentea-client/test_env.h"
 #include "unity/unity.h"
@@ -53,6 +53,9 @@ using namespace utest::v1;
 #define MBED_CFG_TCP_CLIENT_PACKET_PRESSURE_DEBUG false
 #endif
 
+#define STRINGIZE(x) STRINGIZE2(x)
+#define STRINGIZE2(x) #x
+
 
 // Simple xorshift pseudorandom number generator
 class RandSeq {
@@ -127,7 +130,7 @@ void generate_buffer(uint8_t **buffer, size_t *size, size_t min, size_t max) {
 
 
 // Global variables shared between pressure tests
-EthernetInterface net;
+NetworkInterface* net;
 SocketAddress tcp_addr;
 Timer timer;
 Mutex iomutex;
@@ -161,10 +164,12 @@ class PressureTest {
         for (size_t size = MBED_CFG_TCP_CLIENT_PACKET_PRESSURE_MIN;
              size < MBED_CFG_TCP_CLIENT_PACKET_PRESSURE_MAX;
              size *= 2) {
-            int err = sock.open(&net);
+            int err = sock.open(net);
             TEST_ASSERT_EQUAL(0, err);
             err = sock.connect(tcp_addr);
             TEST_ASSERT_EQUAL(0, err);
+            sock.recv(buffer, sizeof(MBED_CONF_APP_TCP_ECHO_PREFIX));
+
             iomutex.lock();
             printf("TCP: %s:%d streaming %d bytes\r\n",
                 tcp_addr.get_ip_address(), tcp_addr.get_port(), size);
@@ -255,29 +260,14 @@ void test_tcp_packet_pressure_parallel() {
             MBED_CFG_TCP_CLIENT_PACKET_PRESSURE_THREADS,
             buffer_subsize);
 
-    int err = net.connect();
+    net = MBED_CONF_APP_OBJECT_CONSTRUCTION;
+    int err =  MBED_CONF_APP_CONNECT_STATEMENT;
     TEST_ASSERT_EQUAL(0, err);
 
-    printf("MBED: TCPClient IP address is '%s'\n", net.get_ip_address());
-    printf("MBED: TCPClient waiting for server IP and port...\n");
-
-    greentea_send_kv("target_ip", net.get_ip_address());
-
-    char recv_key[] = "host_port";
-    char ipbuf[60] = {0};
-    char portbuf[16] = {0};
-    unsigned int port = 0;
-
-    greentea_send_kv("host_ip", " ");
-    greentea_parse_kv(recv_key, ipbuf, sizeof(recv_key), sizeof(ipbuf));
-
-    greentea_send_kv("host_port", " ");
-    greentea_parse_kv(recv_key, portbuf, sizeof(recv_key), sizeof(ipbuf));
-    sscanf(portbuf, "%u", &port);
+    printf("MBED: TCPClient IP address is '%s'\n", net->get_ip_address());
 
-    printf("MBED: Server IP address received: %s:%d \n", ipbuf, port);
-    tcp_addr.set_ip_address(ipbuf);
-    tcp_addr.set_port(port);
+    tcp_addr.set_ip_address(MBED_CONF_APP_ECHO_SERVER_ADDR);
+    tcp_addr.set_port(MBED_CONF_APP_ECHO_SERVER_PORT);
 
     timer.start();
 
@@ -299,7 +289,7 @@ void test_tcp_packet_pressure_parallel() {
             8*(2*MBED_CFG_TCP_CLIENT_PACKET_PRESSURE_MAX -
             MBED_CFG_TCP_CLIENT_PACKET_PRESSURE_MIN) / (1000*timer.read()));
 
-    net.disconnect();
+    net->disconnect();
 }
 
 
diff --git a/features/FEATURE_LWIP/TESTS/mbedmicro-net/udp_dtls_handshake/main.cpp b/TESTS/netsocket/udp_dtls_handshake/main.cpp
similarity index 83%
rename from features/FEATURE_LWIP/TESTS/mbedmicro-net/udp_dtls_handshake/main.cpp
rename to TESTS/netsocket/udp_dtls_handshake/main.cpp
index 2563bc2dfae..b36191fa3fd 100644
--- a/features/FEATURE_LWIP/TESTS/mbedmicro-net/udp_dtls_handshake/main.cpp
+++ b/TESTS/netsocket/udp_dtls_handshake/main.cpp
@@ -1,27 +1,26 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
+/*
+ * Copyright (c) 2013-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
-#if !FEATURE_LWIP
-    #error [NOT_SUPPORTED] LWIP not supported for this target
-#endif
-#if DEVICE_EMAC
-    #error [NOT_SUPPORTED] Not supported for WiFi targets
-#endif
+
+ #ifndef MBED_CONF_APP_CONNECT_STATEMENT
+     #error [NOT_SUPPORTED] No network configuration found for this target.
+ #endif
 
 #include "mbed.h"
-#include "EthernetInterface.h"
+#include MBED_CONF_APP_HEADER_FILE
 #include "UDPSocket.h"
 #include "greentea-client/test_env.h"
 #include "unity/unity.h"
@@ -46,19 +45,20 @@ using namespace utest::v1;
 #define MBED_CFG_UDP_DTLS_HANDSHAKE_TIMEOUT 1500
 #endif
 
+
 uint8_t buffer[MBED_CFG_UDP_DTLS_HANDSHAKE_BUFFER_SIZE] = {0};
 int udp_dtls_handshake_pattern[] = {MBED_CFG_UDP_DTLS_HANDSHAKE_PATTERN};
 const int udp_dtls_handshake_count = sizeof(udp_dtls_handshake_pattern) / sizeof(int);
 
 void test_udp_dtls_handshake() {
-    EthernetInterface eth;
-    int err = eth.connect();
+    NetworkInterface* net = MBED_CONF_APP_OBJECT_CONSTRUCTION;
+    int err =  MBED_CONF_APP_CONNECT_STATEMENT;
     TEST_ASSERT_EQUAL(0, err);
 
-    printf("MBED: UDPClient IP address is '%s'\n", eth.get_ip_address());
+    printf("MBED: UDPClient IP address is '%s'\n", net->get_ip_address());
     printf("MBED: UDPClient waiting for server IP and port...\n");
 
-    greentea_send_kv("target_ip", eth.get_ip_address());
+    greentea_send_kv("target_ip", net->get_ip_address());
 
     bool result = false;
 
@@ -95,7 +95,7 @@ void test_udp_dtls_handshake() {
     sock.set_timeout(MBED_CFG_UDP_DTLS_HANDSHAKE_TIMEOUT);
 
     for (int attempt = 0; attempt < MBED_CFG_UDP_DTLS_HANDSHAKE_RETRIES; attempt++) {
-        err = sock.open(&eth);
+        err = sock.open(net);
         TEST_ASSERT_EQUAL(0, err);
 
         for (int i = 0; i < udp_dtls_handshake_count; i++) {
@@ -143,8 +143,8 @@ void test_udp_dtls_handshake() {
         }
     }
 
-    eth.disconnect();
-    TEST_ASSERT(result);
+    net->disconnect();
+    TEST_ASSERT_EQUAL(true, result);
 }
 
 
diff --git a/features/FEATURE_LWIP/TESTS/mbedmicro-net/udp_echo/main.cpp b/TESTS/netsocket/udp_echo/main.cpp
similarity index 50%
rename from features/FEATURE_LWIP/TESTS/mbedmicro-net/udp_echo/main.cpp
rename to TESTS/netsocket/udp_echo/main.cpp
index ab07f52f038..a5ab9bef4df 100644
--- a/features/FEATURE_LWIP/TESTS/mbedmicro-net/udp_echo/main.cpp
+++ b/TESTS/netsocket/udp_echo/main.cpp
@@ -1,27 +1,26 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
+/*
+ * Copyright (c) 2013-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
-#if !FEATURE_LWIP
-    #error [NOT_SUPPORTED] LWIP not supported for this target
-#endif
-#if DEVICE_EMAC
-    #error [NOT_SUPPORTED] Not supported for WiFi targets
+
+#ifndef MBED_CONF_APP_CONNECT_STATEMENT
+    #error [NOT_SUPPORTED] No network configuration found for this target.
 #endif
 
 #include "mbed.h"
-#include "EthernetInterface.h"
+#include MBED_CONF_APP_HEADER_FILE
 #include "UDPSocket.h"
 #include "greentea-client/test_env.h"
 #include "unity/unity.h"
@@ -38,22 +37,14 @@ using namespace utest::v1;
 #define MBED_CFG_UDP_CLIENT_ECHO_TIMEOUT 500
 #endif
 
-
 namespace {
     char tx_buffer[MBED_CFG_UDP_CLIENT_ECHO_BUFFER_SIZE] = {0};
     char rx_buffer[MBED_CFG_UDP_CLIENT_ECHO_BUFFER_SIZE] = {0};
     const char ASCII_MAX = '~' - ' ';
     const int ECHO_LOOPS = 16;
-    char uuid[GREENTEA_UUID_LENGTH] = {0};
+    char uuid[48] = {0};
 }
 
-// Creates a buffer that contains the test's UUID in the first part of the contents
-// so the output can be associated with individual test runs. The rest of the
-// buffer is filled with random data so it is unique within the CURRENT test run.
-//
-// Ex. A test with UUID of `33e5002c-9722-4685-817a-709cc69c4701` would have a
-// buffer filled with something like `33e5002c-9722-4685-817a-709cc69c4701 12594387`
-// where `33e5002c-9722-4685-817a-709cc69c4701` is the UUID and `12594387` is the random data
 void prep_buffer(char *uuid, char *tx_buffer, size_t tx_size) {
     size_t i = 0;
 
@@ -68,60 +59,51 @@ void prep_buffer(char *uuid, char *tx_buffer, size_t tx_size) {
 }
 
 void test_udp_echo() {
-    EthernetInterface eth;
 
-    int err = eth.connect();
-    TEST_ASSERT_EQUAL(0, err);
+    NetworkInterface* net = MBED_CONF_APP_OBJECT_CONSTRUCTION;
+    int err =  MBED_CONF_APP_CONNECT_STATEMENT;
 
-    printf("UDP client IP Address is %s\n", eth.get_ip_address());
+    TEST_ASSERT_EQUAL(0, err);
 
-    greentea_send_kv("target_ip", eth.get_ip_address());
+    if (err) {
+        printf("MBED: failed to connect with an error of %d\r\n", err);
+        TEST_ASSERT_EQUAL(0, err);
+    }
 
-    char recv_key[] = "host_port";
-    char ipbuf[60] = {0};
-    char portbuf[16] = {0};
-    unsigned int port = 0;
+    printf("UDP client IP Address is %s\n", net->get_ip_address());
 
     UDPSocket sock;
-    sock.open(&eth);
+    sock.open(net);
     sock.set_timeout(MBED_CFG_UDP_CLIENT_ECHO_TIMEOUT);
 
-    greentea_send_kv("host_ip", " ");
-    greentea_parse_kv(recv_key, ipbuf, sizeof(recv_key), sizeof(ipbuf));
-
-    greentea_send_kv("host_port", " ");
-    greentea_parse_kv(recv_key, portbuf, sizeof(recv_key), sizeof(ipbuf));
-    sscanf(portbuf, "%u", &port);
-
-    printf("MBED: UDP Server IP address received: %s:%d \n", ipbuf, port);
-    SocketAddress udp_addr(ipbuf, port);
+    SocketAddress udp_addr(MBED_CONF_APP_ECHO_SERVER_ADDR, MBED_CONF_APP_ECHO_SERVER_PORT);
 
     int success = 0;
-    for (unsigned int i = 0; success < ECHO_LOOPS; i++) {
+    for (int i = 0; success < ECHO_LOOPS; i++) {
         prep_buffer(uuid, tx_buffer, sizeof(tx_buffer));
-        int ret = sock.sendto(udp_addr, tx_buffer, sizeof(tx_buffer));
+        const int ret = sock.sendto(udp_addr, tx_buffer, sizeof(tx_buffer));
         if (ret >= 0) {
-            printf("[%02u] sent %d bytes - %.*s  \n", i, ret, ret, tx_buffer);
+            printf("[%02d] sent %d bytes - %.*s  \n", i, ret, ret, tx_buffer);
         } else {
-            printf("[%02u] Network error %d\n", i, ret);
+            printf("[%02d] Network error %d\n", i, ret);
             continue;
         }
 
         SocketAddress temp_addr;
-        ret = sock.recvfrom(&temp_addr, rx_buffer, sizeof(rx_buffer));
-        if (ret >= 0) {
-            printf("[%02u] recv %d bytes - %.*s  \n", i, ret, ret, tx_buffer);
+        const int n = sock.recvfrom(&temp_addr, rx_buffer, sizeof(rx_buffer));
+        if (n >= 0) {
+            printf("[%02d] recv %d bytes - %.*s  \n", i, n, n, rx_buffer);
         } else {
-            printf("[%02u] Network error %d\n", i, ret);
+            printf("[%02d] Network error %d\n", i, n);
             continue;
         }
 
         if ((temp_addr == udp_addr &&
-             ret == sizeof(tx_buffer) &&
+             n == sizeof(tx_buffer) &&
              memcmp(rx_buffer, tx_buffer, sizeof(rx_buffer)) == 0)) {
             success += 1;
 
-            printf("[%02u] success #%d\n", i, success);
+            printf("[%02d] success #%d\n", i, success);
             continue;
         }
 
@@ -137,14 +119,22 @@ void test_udp_echo() {
     }
 
     sock.close();
-    eth.disconnect();
+    net->disconnect();
     TEST_ASSERT_EQUAL(ECHO_LOOPS, success);
 }
 
 
 // Test setup
 utest::v1::status_t test_setup(const size_t number_of_cases) {
-    GREENTEA_SETUP_UUID(120, "udp_echo", uuid, GREENTEA_UUID_LENGTH);
+    GREENTEA_SETUP(240, "udp_echo");
+
+    // create mac address based on uuid
+    uint64_t mac = 0;
+    for (int i = 0; i < sizeof(uuid); i++) {
+        mac += uuid[i];
+    }
+    //mbed_set_mac_address((const char*)mac, /*coerce control bits*/ 1);
+
     return verbose_test_setup_handler(number_of_cases);
 }
 
diff --git a/TESTS/netsocket/udp_echo_parallel/main.cpp b/TESTS/netsocket/udp_echo_parallel/main.cpp
new file mode 100644
index 00000000000..2a47f5b9658
--- /dev/null
+++ b/TESTS/netsocket/udp_echo_parallel/main.cpp
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2013-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ #ifndef MBED_CONF_APP_CONNECT_STATEMENT
+     #error [NOT_SUPPORTED] No network configuration found for this target.
+ #endif
+
+#ifndef MBED_EXTENDED_TESTS
+    #error [NOT_SUPPORTED] Parallel tests are not supported by default
+#endif
+
+#include "mbed.h"
+#include MBED_CONF_APP_HEADER_FILE
+#include "UDPSocket.h"
+#include "greentea-client/test_env.h"
+#include "unity/unity.h"
+#include "utest.h"
+
+using namespace utest::v1;
+
+
+#ifndef MBED_CFG_UDP_CLIENT_ECHO_BUFFER_SIZE
+#define MBED_CFG_UDP_CLIENT_ECHO_BUFFER_SIZE 64
+#endif
+
+#ifndef MBED_CFG_UDP_CLIENT_ECHO_TIMEOUT
+#define MBED_CFG_UDP_CLIENT_ECHO_TIMEOUT 500
+#endif
+
+#ifndef MBED_CFG_UDP_CLIENT_ECHO_THREADS
+#define MBED_CFG_UDP_CLIENT_ECHO_THREADS 3
+#endif
+
+#define STRINGIZE(x) STRINGIZE2(x)
+#define STRINGIZE2(x) #x
+
+
+const int ECHO_LOOPS = 16;
+NetworkInterface* net;
+SocketAddress udp_addr;
+Mutex iomutex;
+char uuid[48] = {0};
+
+// NOTE: assuming that "id" stays in the single digits
+void prep_buffer(int id, char *uuid, char *tx_buffer, size_t tx_size) {
+    size_t i = 0;
+
+    tx_buffer[i++] = '0' + id;
+    tx_buffer[i++] = ' ';
+
+    memcpy(tx_buffer+i, uuid, strlen(uuid));
+    i += strlen(uuid);
+
+    tx_buffer[i++] = ' ';
+
+    for (; i<tx_size; ++i) {
+        tx_buffer[i] = (rand() % 10) + '0';
+    }
+}
+
+
+// Each echo class is in charge of one parallel transaction
+class Echo {
+private:
+    char tx_buffer[MBED_CFG_UDP_CLIENT_ECHO_BUFFER_SIZE];
+    char rx_buffer[MBED_CFG_UDP_CLIENT_ECHO_BUFFER_SIZE];
+
+    UDPSocket sock;
+    Thread thread;
+    bool result;
+    int id;
+    char *uuid;
+
+public:
+    // Limiting stack size to 1k
+    Echo(): thread(osPriorityNormal, 1024), result(false) {
+    }
+
+    void start(int id, char *uuid) {
+        this->id = id;
+        this->uuid = uuid;
+        osStatus status = thread.start(callback(this, &Echo::echo));
+    }
+
+    void join() {
+        osStatus status = thread.join();
+        TEST_ASSERT_EQUAL(osOK, status);
+    }
+
+    void echo() {
+        int success = 0;
+
+        int err = sock.open(net);
+        TEST_ASSERT_EQUAL(0, err);
+
+        sock.set_timeout(MBED_CFG_UDP_CLIENT_ECHO_TIMEOUT);
+
+        for (int i = 0; success < ECHO_LOOPS; i++) {
+            prep_buffer(id, uuid, tx_buffer, sizeof(tx_buffer));
+            const int ret = sock.sendto(udp_addr, tx_buffer, sizeof(tx_buffer));
+            if (ret >= 0) {
+                iomutex.lock();
+                printf("[ID:%01d][%02d] sent %d bytes - %.*s  \n", id, i, ret, ret, tx_buffer);
+                iomutex.unlock();
+            } else {
+                iomutex.lock();
+                printf("[ID:%01d][%02d] Network error %d\n", id, i, ret);
+                iomutex.unlock();
+                continue;
+            }
+
+            SocketAddress temp_addr;
+            const int n = sock.recvfrom(&temp_addr, rx_buffer, sizeof(rx_buffer));
+            if (n >= 0) {
+                iomutex.lock();
+                printf("[ID:%01d][%02d] recv %d bytes - %.*s  \n", id, i, n, n, tx_buffer);
+                iomutex.unlock();
+            } else {
+                iomutex.lock();
+                printf("[ID:%01d][%02d] Network error %d\n", id, i, n);
+                iomutex.unlock();
+                continue;
+            }
+
+            if ((temp_addr == udp_addr &&
+                 n == sizeof(tx_buffer) &&
+                 memcmp(rx_buffer, tx_buffer, sizeof(rx_buffer)) == 0)) {
+                success += 1;
+                iomutex.lock();
+                printf("[ID:%01d][%02d] success #%d\n", id, i, success);
+                iomutex.unlock();
+                continue;
+            }
+
+            // failed, clean out any remaining bad packets
+            sock.set_timeout(0);
+            while (true) {
+                err = sock.recvfrom(NULL, NULL, 0);
+                if (err == NSAPI_ERROR_WOULD_BLOCK) {
+                    break;
+                }
+            }
+            sock.set_timeout(MBED_CFG_UDP_CLIENT_ECHO_TIMEOUT);
+        }
+
+        result = success == ECHO_LOOPS;
+
+        err = sock.close();
+        TEST_ASSERT_EQUAL(0, err);
+        if (err) {
+            result = false;
+        }
+    }
+
+    bool get_result() {
+        return result;
+    }
+};
+
+Echo *echoers[MBED_CFG_UDP_CLIENT_ECHO_THREADS];
+
+
+void test_udp_echo_parallel() {
+    net = MBED_CONF_APP_OBJECT_CONSTRUCTION;
+    int err =  MBED_CONF_APP_CONNECT_STATEMENT;
+    TEST_ASSERT_EQUAL(0, err);
+
+    if (err) {
+        printf("MBED: failed to connect with an error of %d\r\n", err);
+        GREENTEA_TESTSUITE_RESULT(false);
+    } else {
+        printf("UDP client IP Address is %s\n", net->get_ip_address());
+
+        udp_addr.set_ip_address(MBED_CONF_APP_ECHO_SERVER_ADDR);
+        udp_addr.set_port(MBED_CONF_APP_ECHO_SERVER_PORT);
+
+        // Startup echo threads in parallel
+        for (int i = 0; i < MBED_CFG_UDP_CLIENT_ECHO_THREADS; i++) {
+            echoers[i] = new Echo;
+            echoers[i]->start(i, uuid);
+        }
+
+        bool result = true;
+
+        for (int i = 0; i < MBED_CFG_UDP_CLIENT_ECHO_THREADS; i++) {
+            echoers[i]->join();
+            result = result && echoers[i]->get_result();
+            delete echoers[i];
+        }
+
+        net->disconnect();
+        TEST_ASSERT_EQUAL(true, result);
+    }
+}
+
+
+// Test setup
+utest::v1::status_t test_setup(const size_t number_of_cases) {
+    GREENTEA_SETUP(120, "udp_echo");
+    return verbose_test_setup_handler(number_of_cases);
+}
+
+Case cases[] = {
+    Case("UDP echo parallel", test_udp_echo_parallel),
+};
+
+Specification specification(test_setup, cases);
+
+int main() {
+    return !Harness::run(specification);
+}
diff --git a/features/FEATURE_LWIP/TESTS/mbedmicro-net/udp_packet_pressure/main.cpp b/TESTS/netsocket/udp_packet_pressure/main.cpp
similarity index 84%
rename from features/FEATURE_LWIP/TESTS/mbedmicro-net/udp_packet_pressure/main.cpp
rename to TESTS/netsocket/udp_packet_pressure/main.cpp
index 3faa23b4669..f3c72b959da 100644
--- a/features/FEATURE_LWIP/TESTS/mbedmicro-net/udp_packet_pressure/main.cpp
+++ b/TESTS/netsocket/udp_packet_pressure/main.cpp
@@ -1,30 +1,30 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
+/*
+ * Copyright (c) 2013-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
-#if !FEATURE_LWIP
-    #error [NOT_SUPPORTED] LWIP not supported for this target
-#endif
-#if DEVICE_EMAC
-    #error [NOT_SUPPORTED] Not supported for WiFi targets
-#endif
+
+ #ifndef MBED_CONF_APP_CONNECT_STATEMENT
+     #error [NOT_SUPPORTED] No network configuration found for this target.
+ #endif
+
 #ifndef MBED_EXTENDED_TESTS
     #error [NOT_SUPPORTED] Pressure tests are not supported by default
 #endif
 
 #include "mbed.h"
-#include "EthernetInterface.h"
+#include MBED_CONF_APP_HEADER_FILE
 #include "UDPSocket.h"
 #include "greentea-client/test_env.h"
 #include "unity/unity.h"
@@ -53,6 +53,9 @@ using namespace utest::v1;
 #define MBED_CFG_UDP_CLIENT_PACKET_PRESSURE_DEBUG false
 #endif
 
+#define STRINGIZE(x) STRINGIZE2(x)
+#define STRINGIZE2(x) #x
+
 
 // Simple xorshift pseudorandom number generator
 class RandSeq {
@@ -134,31 +137,14 @@ void test_udp_packet_pressure() {
         MBED_CFG_UDP_CLIENT_PACKET_PRESSURE_MAX);
     printf("MBED: Generated buffer %d\r\n", buffer_size);
 
-    EthernetInterface eth;
-    int err = eth.connect();
+    NetworkInterface* net = MBED_CONF_APP_OBJECT_CONSTRUCTION;
+    int err =  MBED_CONF_APP_CONNECT_STATEMENT;
     TEST_ASSERT_EQUAL(0, err);
 
-    printf("MBED: UDPClient IP address is '%s'\n", eth.get_ip_address());
-    printf("MBED: UDPClient waiting for server IP and port...\n");
-
-    greentea_send_kv("target_ip", eth.get_ip_address());
-
-    char recv_key[] = "host_port";
-    char ipbuf[60] = {0};
-    char portbuf[16] = {0};
-    unsigned int port = 0;
-
-    greentea_send_kv("host_ip", " ");
-    greentea_parse_kv(recv_key, ipbuf, sizeof(recv_key), sizeof(ipbuf));
-
-    greentea_send_kv("host_port", " ");
-    greentea_parse_kv(recv_key, portbuf, sizeof(recv_key), sizeof(ipbuf));
-    sscanf(portbuf, "%u", &port);
-
-    printf("MBED: Server IP address received: %s:%d \n", ipbuf, port);
+    printf("MBED: UDPClient IP address is '%s'\n", net->get_ip_address());
 
     UDPSocket sock;
-    SocketAddress udp_addr(ipbuf, port);
+    SocketAddress udp_addr(MBED_CONF_APP_ECHO_SERVER_ADDR, MBED_CONF_APP_ECHO_SERVER_PORT);
 
     Timer timer;
     timer.start();
@@ -167,9 +153,10 @@ void test_udp_packet_pressure() {
     for (size_t size = MBED_CFG_UDP_CLIENT_PACKET_PRESSURE_MIN;
          size < MBED_CFG_UDP_CLIENT_PACKET_PRESSURE_MAX;
          size *= 2) {
-        err = sock.open(&eth);
+        err = sock.open(net);
         TEST_ASSERT_EQUAL(0, err);
-        printf("UDP: %s:%d streaming %d bytes\r\n", ipbuf, port, size);
+        printf("UDP: %s:%d streaming %d bytes\r\n",
+            udp_addr.get_ip_address(), udp_addr.get_port(), size);
 
         sock.set_blocking(false);
 
@@ -260,7 +247,7 @@ void test_udp_packet_pressure() {
             8*(2*MBED_CFG_UDP_CLIENT_PACKET_PRESSURE_MAX -
             MBED_CFG_UDP_CLIENT_PACKET_PRESSURE_MIN) / (1000*timer.read()));
 
-    eth.disconnect();
+    net->disconnect();
 }
 
 
diff --git a/features/FEATURE_LWIP/TESTS/mbedmicro-net/udp_packet_pressure_parallel/main.cpp b/TESTS/netsocket/udp_packet_pressure_parallel/main.cpp
similarity index 88%
rename from features/FEATURE_LWIP/TESTS/mbedmicro-net/udp_packet_pressure_parallel/main.cpp
rename to TESTS/netsocket/udp_packet_pressure_parallel/main.cpp
index acb543b4bb3..e26b8d53fee 100644
--- a/features/FEATURE_LWIP/TESTS/mbedmicro-net/udp_packet_pressure_parallel/main.cpp
+++ b/TESTS/netsocket/udp_packet_pressure_parallel/main.cpp
@@ -1,30 +1,30 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
+/*
+ * Copyright (c) 2013-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
-#if !FEATURE_LWIP
-    #error [NOT_SUPPORTED] LWIP not supported for this target
-#endif
-#if DEVICE_EMAC
-    #error [NOT_SUPPORTED] Not supported for WiFi targets
-#endif
+
+ #ifndef MBED_CONF_APP_CONNECT_STATEMENT
+     #error [NOT_SUPPORTED] No network configuration found for this target.
+ #endif
+
 #ifndef MBED_EXTENDED_TESTS
     #error [NOT_SUPPORTED] Parallel pressure tests are not supported by default
 #endif
 
 #include "mbed.h"
-#include "EthernetInterface.h"
+#include MBED_CONF_APP_HEADER_FILE
 #include "UDPSocket.h"
 #include "greentea-client/test_env.h"
 #include "unity/unity.h"
@@ -57,6 +57,9 @@ using namespace utest::v1;
 #define MBED_CFG_UDP_CLIENT_PACKET_PRESSURE_DEBUG false
 #endif
 
+#define STRINGIZE(x) STRINGIZE2(x)
+#define STRINGIZE2(x) #x
+
 
 // Simple xorshift pseudorandom number generator
 class RandSeq {
@@ -130,7 +133,7 @@ void generate_buffer(uint8_t **buffer, size_t *size, size_t min, size_t max) {
 
 
 // Global variables shared between pressure tests
-EthernetInterface net;
+NetworkInterface* net;
 SocketAddress udp_addr;
 Timer timer;
 Mutex iomutex;
@@ -164,7 +167,7 @@ class PressureTest {
         for (size_t size = MBED_CFG_UDP_CLIENT_PACKET_PRESSURE_MIN;
              size < MBED_CFG_UDP_CLIENT_PACKET_PRESSURE_MAX;
              size *= 2) {
-            int err = sock.open(&net);
+            int err = sock.open(net);
             TEST_ASSERT_EQUAL(0, err);
             iomutex.lock();
             printf("UDP: %s:%d streaming %d bytes\r\n",
@@ -280,29 +283,14 @@ void test_udp_packet_pressure_parallel() {
             MBED_CFG_UDP_CLIENT_PACKET_PRESSURE_THREADS,
             buffer_subsize);
 
-    int err = net.connect();
+    net = MBED_CONF_APP_OBJECT_CONSTRUCTION;
+    int err =  MBED_CONF_APP_CONNECT_STATEMENT;
     TEST_ASSERT_EQUAL(0, err);
 
-    printf("MBED: UDPClient IP address is '%s'\n", net.get_ip_address());
-    printf("MBED: UDPClient waiting for server IP and port...\n");
-
-    greentea_send_kv("target_ip", net.get_ip_address());
-
-    char recv_key[] = "host_port";
-    char ipbuf[60] = {0};
-    char portbuf[16] = {0};
-    unsigned int port = 0;
-
-    greentea_send_kv("host_ip", " ");
-    greentea_parse_kv(recv_key, ipbuf, sizeof(recv_key), sizeof(ipbuf));
-
-    greentea_send_kv("host_port", " ");
-    greentea_parse_kv(recv_key, portbuf, sizeof(recv_key), sizeof(ipbuf));
-    sscanf(portbuf, "%u", &port);
+    printf("MBED: UDPClient IP address is '%s'\n", net->get_ip_address());
 
-    printf("MBED: Server IP address received: %s:%d \n", ipbuf, port);
-    udp_addr.set_ip_address(ipbuf);
-    udp_addr.set_port(port);
+    udp_addr.set_ip_address(MBED_CONF_APP_ECHO_SERVER_ADDR);
+    udp_addr.set_port(MBED_CONF_APP_ECHO_SERVER_PORT);
 
     timer.start();
 
@@ -324,7 +312,7 @@ void test_udp_packet_pressure_parallel() {
             8*(2*MBED_CFG_UDP_CLIENT_PACKET_PRESSURE_MAX -
             MBED_CFG_UDP_CLIENT_PACKET_PRESSURE_MIN) / (1000*timer.read()));
 
-    net.disconnect();
+    net->disconnect();
 }
 
 
diff --git a/TESTS/network/wifi/get_interface.cpp b/TESTS/network/wifi/get_interface.cpp
new file mode 100644
index 00000000000..9bafab9b588
--- /dev/null
+++ b/TESTS/network/wifi/get_interface.cpp
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+
+// Pick the correct driver based on mbed_app.json
+#define INTERNAL            1
+#define WIFI_ESP8266        2
+#define X_NUCLEO_IDW01M1    3
+
+#if MBED_CONF_APP_WIFI_DRIVER == INTERNAL
+
+#if TARGET_UBLOX_EVK_ODIN_W2
+#include "OdinWiFiInterface.h"
+#define DRIVER OdinWiFiInterface
+
+#elif TARGET_REALTEK_RTL8195AM
+#include "RTWInterface.h"
+#define DRIVER RTWInterface
+#else
+#error [NOT_SUPPORTED] Unsupported Wifi driver
+#endif
+
+#elif MBED_CONF_APP_WIFI_DRIVER == WIFI_ESP8266
+#include "ESP8266Interface.h"
+#define DRIVER ESP8266Interface
+
+#elif MBED_CONF_APP_WIFI_DRIVER == X_NUCLEO_IDW01M1
+#include "SpwfSAInterface.h"
+#define DRIVER SpwfSAInterface
+#else
+#error [NOT_SUPPORTED] Unsupported Wifi driver
+#endif
+
+WiFiInterface *get_interface()
+{
+    static WiFiInterface *interface = NULL;
+
+    if (interface)
+        delete interface;
+
+#if MBED_CONF_APP_WIFI_DRIVER == INTERNAL
+    interface = new DRIVER();
+#else
+    interface = new DRIVER(MBED_CONF_APP_WIFI_TX, MBED_CONF_APP_WIFI_RX);
+#endif
+    return interface;
+}
diff --git a/TESTS/network/wifi/main.cpp b/TESTS/network/wifi/main.cpp
index c242a8c291f..1245b11e2dd 100644
--- a/TESTS/network/wifi/main.cpp
+++ b/TESTS/network/wifi/main.cpp
@@ -1,196 +1,71 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2016 ARM Limited
+/*
+ * Copyright (c) 2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
 
-#include "utest/utest.h"
-#include "unity/unity.h"
-#include "greentea-client/test_env.h"
-
 #include "mbed.h"
-
-#if TARGET_UBLOX_EVK_ODIN_W2
-#include "OdinWiFiInterface.h"
-#else
-#error [NOT_SUPPORTED] Only built in WiFi modules are supported at this time.
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "wifi_tests.h"
+
+// Test for parameters
+#if !defined(MBED_CONF_APP_AP_MAC_SECURE)      || \
+    !defined(MBED_CONF_APP_AP_MAC_UNSECURE)    || \
+    !defined(MBED_CONF_APP_MAX_SCAN_SIZE)      || \
+    !defined(MBED_CONF_APP_WIFI_CH_SECURE)     || \
+    !defined(MBED_CONF_APP_WIFI_CH_UNSECURE)   || \
+    !defined(MBED_CONF_APP_WIFI_DRIVER)        || \
+    !defined(MBED_CONF_APP_WIFI_PASSWORD)      || \
+    !defined(MBED_CONF_APP_WIFI_RX)            || \
+    !defined(MBED_CONF_APP_WIFI_SECURE_SSID)   || \
+    !defined(MBED_CONF_APP_WIFI_TX)            || \
+    !defined(MBED_CONF_APP_WIFI_UNSECURE_SSID)
+#error [NOT_SUPPORTED] Requires parameters from mbed_app.json
 #endif
 
 using namespace utest::v1;
 
-/**
- * WiFi tests require following macros to be defined:
- * - MBED_CONF_APP_WIFI_SSID - SSID of a network the test will try connecting to
- * - MBED_CONF_APP_WIFI_PASSWORD - Passphrase that will be used to connecting to the network
- * - WIFI_TEST_NETWORKS - List of network that presence will be asserted e.g. "net1", "net2", "net3"
- */
-#if !defined(MBED_CONF_APP_WIFI_SSID) || !defined(MBED_CONF_APP_WIFI_PASSWORD) || !defined(MBED_CONF_APP_WIFI_NETWORKS)
-#error [NOT_SUPPORTED] MBED_CONF_APP_WIFI_SSID, MBED_CONF_APP_WIFI_PASSWORD and MBED_CONF_APP_WIFI_NETWORKS have to be defined for this test.
-#endif
-
-const char *networks[] = {MBED_CONF_APP_WIFI_NETWORKS, NULL};
-
-WiFiInterface *wifi;
-
-/* In normal circumstances the WiFi object could be global, but the delay introduced by WiFi initialization is an issue
-   for the tests. It causes Greentea to timeout on syncing with the board. To solve it we defer the actual object
-   creation till we actually need it.
- */
-WiFiInterface *get_wifi()
-{
-    if (wifi == NULL) {
-        /* We don't really care about freeing this, as its lifetime is through the full test suit run. */
-#if TARGET_UBLOX_EVK_ODIN_W2
-        wifi = new OdinWiFiInterface;
-#endif
-    }
-
-    return wifi;
-}
-
-void check_wifi(const char *ssid, bool *net_stat)
-{
-    int i = 0;
-    while(networks[i]) {
-        if (strcmp(networks[i], ssid) == 0) {
-            net_stat[i] = true;
-            break;
-        }
-        i++;
-    }
-}
-
-void wifi_scan()
-{
-    int count;
-    WiFiAccessPoint *aps;
-    const int net_len = sizeof(networks)/sizeof(networks[0]);
-    bool net_stat[net_len - 1];
-
-    memset(net_stat, 0, sizeof(net_stat));
-
-    count = get_wifi()->scan(NULL, 0);
-    TEST_ASSERT_MESSAGE(count >= 0, "WiFi interface returned error");
-    TEST_ASSERT_MESSAGE(count > 0, "Scan result empty");
-
-    aps = new WiFiAccessPoint[count];
-    count = get_wifi()->scan(aps, count);
-    for(int i = 0; i < count; i++) {
-        check_wifi(aps[i].get_ssid(), net_stat);
-    }
-
-    delete[] aps;
-
-    for (unsigned i = 0; i < sizeof(net_stat); i++) {
-        TEST_ASSERT_MESSAGE(net_stat[i] == true, "Not all required WiFi network detected");
-    }
-}
-
-void wifi_connect()
-{
-    int ret;
-
-    ret = get_wifi()->connect(MBED_CONF_APP_WIFI_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA_WPA2);
-    TEST_ASSERT_MESSAGE(ret == 0, "Connect failed");
-
-    ret = get_wifi()->disconnect();
-    TEST_ASSERT_MESSAGE(ret == 0, "Disconnect failed");
-}
-
-void wifi_connect_scan()
-{
-    int ret;
-    int count;
-    WiFiAccessPoint *aps;
-    const int net_len = sizeof(networks)/sizeof(networks[0]);
-    bool net_stat[net_len - 1];
-
-    memset(net_stat, 0, sizeof(net_stat));
-
-    ret = get_wifi()->connect(MBED_CONF_APP_WIFI_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA_WPA2);
-    TEST_ASSERT_MESSAGE(ret == 0, "Connect failed");
-
-    count = get_wifi()->scan(NULL, 0);
-    TEST_ASSERT_MESSAGE(count >= 0, "WiFi interface returned error");
-    TEST_ASSERT_MESSAGE(count > 0, "Scan result empty");
-
-    aps = new WiFiAccessPoint[count];
-    count = get_wifi()->scan(aps, count);
-    for(int i = 0; i < count; i++) {
-        check_wifi(aps[i].get_ssid(), net_stat);
-    }
-
-    delete[] aps;
-
-    ret = get_wifi()->disconnect();
-    TEST_ASSERT_MESSAGE(ret == 0, "Disconnect failed");
-
-    for (unsigned i = 0; i < sizeof(net_stat); i++) {
-        TEST_ASSERT_MESSAGE(net_stat[i] == true, "Not all required WiFi network detected");
-    }
-}
-
-void wifi_http()
-{
-    TCPSocket socket;
-    int ret;
-
-    ret = get_wifi()->connect(MBED_CONF_APP_WIFI_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA_WPA2);
-    TEST_ASSERT_MESSAGE(ret == 0, "Connect failed");
-
-    // Open a socket on the network interface, and create a TCP connection to www.arm.com
-    ret = socket.open(get_wifi());
-    TEST_ASSERT_MESSAGE(ret == 0, "Socket open failed");
-    ret = socket.connect("www.arm.com", 80);
-    TEST_ASSERT_MESSAGE(ret == 0, "Socket connect failed");
-
-    // Send a simple http request
-    char sbuffer[] = "GET / HTTP/1.1\r\nHost: www.arm.com\r\n\r\n";
-    int scount = socket.send(sbuffer, sizeof sbuffer);
-    TEST_ASSERT_MESSAGE(scount >= 0, "Socket send failed");
-
-    // Recieve a simple http response and check if it's not empty
-    char rbuffer[64];
-    int rcount = socket.recv(rbuffer, sizeof rbuffer);
-    TEST_ASSERT_MESSAGE(rcount >= 0, "Socket recv error");
-    TEST_ASSERT_MESSAGE(rcount > 0, "No data received");
-
-    ret = socket.close();
-    TEST_ASSERT_MESSAGE(ret == 0, "Socket close failed");
-
-    ret = get_wifi()->disconnect();
-    TEST_ASSERT_MESSAGE(ret == 0, "Disconnect failed");
-}
-
-status_t greentea_failure_handler(const Case *const source, const failure_t reason) {
-    greentea_case_failure_abort_handler(source, reason);
-    return STATUS_CONTINUE;
+utest::v1::status_t test_setup(const size_t number_of_cases) {
+    GREENTEA_SETUP(240, "default_auto");
+    return verbose_test_setup_handler(number_of_cases);
 }
 
+// Test cases
 Case cases[] = {
-    Case("Scan test", wifi_scan, greentea_failure_handler),
-    Case("Connect test", wifi_connect, greentea_failure_handler),
-    Case("Scan while connected test", wifi_connect_scan, greentea_failure_handler),
-    Case("HTTP test", wifi_http, greentea_failure_handler),
+    Case("WIFI-CONSTRUCTOR", wifi_constructor),
+    Case("WIFI-SET-CREDENTIAL", wifi_set_credential),
+    Case("WIFI-SET-CHANNEL", wifi_set_channel),
+    Case("WIFI-GET-RSSI", wifi_get_rssi),
+    Case("WIFI-CONNECT-PARAMS-NULL", wifi_connect_params_null),
+    Case("WIFI-CONNECT-PARAMS-VALID-UNSECURE", wifi_connect_params_valid_unsecure),
+    Case("WIFI-CONNECT-PARAMS-VALID-SECURE", wifi_connect_params_valid_secure),
+    Case("WIFI-CONNECT-PARAMS-CHANNEL", wifi_connect_params_channel),
+    Case("WIFI-CONNECT-PARAMS-CHANNEL-FAIL", wifi_connect_params_channel_fail),
+    Case("WIFI-CONNECT-NOCREDENTIALS", wifi_connect_nocredentials),
+    Case("WIFI-CONNECT", wifi_connect),
+    Case("WIFI-CONNECT-SECURE", wifi_connect_secure),
+    Case("WIFI-CONNECT-SECURE-FAIL", wifi_connect_secure_fail),
+    Case("WIFI-CONNECT-DISCONNECT-REPEAT", wifi_connect_disconnect_repeat),
+    Case("WIFI-SCAN-NULL", wifi_scan_null),
+    Case("WIFI-SCAN", wifi_scan),
 };
 
-status_t greentea_test_setup(const size_t number_of_cases) {
-    GREENTEA_SETUP(90, "default_auto");
-    return greentea_test_setup_handler(number_of_cases);
-}
-
+Specification specification(test_setup, cases);
 
+// Entry point into the tests
 int main() {
-    Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler);
-    Harness::run(specification);
+    return !Harness::run(specification);
 }
diff --git a/TESTS/network/wifi/template_mbed_app.txt b/TESTS/network/wifi/template_mbed_app.txt
index 77a7af0cf95..ddab934545a 100644
--- a/TESTS/network/wifi/template_mbed_app.txt
+++ b/TESTS/network/wifi/template_mbed_app.txt
@@ -1,21 +1,48 @@
 {
     "config": {
-        "wifi-ssid": {
-            "help": "WiFi SSID",
-            "value": "\"SSID\""
+        "wifi-secure-ssid": {
+            "help": "WiFi SSID for WPA2 secured network",
+            "value": "\"SSID-SECURE\""
+        },
+        "wifi-unsecure-ssid": {
+            "help": "WiFi SSID for unsecure netwrok",
+            "value": "\"SSID-UNSECURE\""
         },
         "wifi-password": {
             "help": "WiFi Password",
-            "value": "\"PASS\""
+            "value": "\"PASSWORD\""
         },
-        "wifi-networks": {
-            "help": "WiFi SSIDs which presence will be asserted in the test",
-            "value": "\"SSID1\",\"SSID2\",\"SSID3\""
-        }
-    },
-    "target_overrides": {
-        "UBLOX_EVK_ODIN_W2": {
-            "target.device_has": ["EMAC"]
+        "wifi-ch-secure": {
+            "help": "Channel number of secure SSID",
+            "value": 1
+        },
+        "wifi-ch-unsecure": {
+            "help": "Channel number of unsecure SSID",
+            "value": 2
+        },
+        "wifi-driver": {
+            "help": "Wifi driver to use, valid values are INTERNAL, WIFI_ESP8266 and X_NUCLEO_IDW01M1",
+            "value": "INTERNAL"
+        },
+        "wifi-tx": {
+            "help": "TX pin for serial connection to external device",
+            "value": "D1"
+        },
+        "wifi-rx": {
+            "help": "RX pin for serial connection to external device",
+            "value": "D0"
+        },
+        "ap-mac-secure": {
+            "help": "BSSID of secure AP in form of AA:BB:CC:DD:EE:FF",
+            "value": "\"AA:AA:AA:AA:AA:AA\""
+        },
+        "ap-mac-unsecure": {
+            "help": "BSSID of unsecure AP in form of \"AA:BB:CC:DD:EE:FF\"",
+            "value": "\"BB:BB:BB:BB:BB:BB\""
+        },
+        "max-scan-size": {
+            "help": "How many networks may appear in Wifi scan result",
+            "value": 10
         }
     }
 }
diff --git a/TESTS/network/wifi/wifi-constructor.cpp b/TESTS/network/wifi/wifi-constructor.cpp
new file mode 100644
index 00000000000..3fa80ff5cbb
--- /dev/null
+++ b/TESTS/network/wifi/wifi-constructor.cpp
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "wifi_tests.h"
+
+using namespace utest::v1;
+
+void wifi_constructor() {
+    WiFiInterface *wifi = get_interface();
+    TEST_ASSERT(wifi);
+}
diff --git a/TESTS/network/wifi/wifi_connect.cpp b/TESTS/network/wifi/wifi_connect.cpp
new file mode 100644
index 00000000000..c244e0247fc
--- /dev/null
+++ b/TESTS/network/wifi/wifi_connect.cpp
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "wifi_tests.h"
+
+using namespace utest::v1;
+
+void wifi_connect(void)
+{
+    WiFiInterface *wifi = get_interface();
+
+    TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->set_credentials(MBED_CONF_APP_WIFI_UNSECURE_SSID, NULL));
+
+    TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->connect());
+}
diff --git a/TESTS/network/wifi/wifi_connect_disconnect_repeat.cpp b/TESTS/network/wifi/wifi_connect_disconnect_repeat.cpp
new file mode 100644
index 00000000000..9ee73fc5587
--- /dev/null
+++ b/TESTS/network/wifi/wifi_connect_disconnect_repeat.cpp
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "wifi_tests.h"
+
+using namespace utest::v1;
+
+void wifi_connect_disconnect_repeat(void)
+{
+    WiFiInterface *wifi = get_interface();
+    nsapi_error_t error;
+
+    error = wifi->set_credentials(MBED_CONF_APP_WIFI_UNSECURE_SSID, NULL);
+    TEST_ASSERT(error == NSAPI_ERROR_OK);
+
+    for(int i=0; i<10; i++) {
+        error = wifi->connect();
+        TEST_ASSERT(error == NSAPI_ERROR_OK);
+        error = wifi->disconnect();
+        TEST_ASSERT(error == NSAPI_ERROR_OK);
+    }
+}
diff --git a/TESTS/network/wifi/wifi_connect_nocredentials.cpp b/TESTS/network/wifi/wifi_connect_nocredentials.cpp
new file mode 100644
index 00000000000..c930d7d0a95
--- /dev/null
+++ b/TESTS/network/wifi/wifi_connect_nocredentials.cpp
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "wifi_tests.h"
+
+using namespace utest::v1;
+
+void wifi_connect_nocredentials(void)
+{
+    WiFiInterface *wifi = get_interface();
+    nsapi_error_t error;
+    error = wifi->connect();
+    wifi->disconnect();
+    TEST_ASSERT(error == NSAPI_ERROR_PARAMETER);
+}
diff --git a/TESTS/network/wifi/wifi_connect_params_channel.cpp b/TESTS/network/wifi/wifi_connect_params_channel.cpp
new file mode 100644
index 00000000000..08c34a9c541
--- /dev/null
+++ b/TESTS/network/wifi/wifi_connect_params_channel.cpp
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "wifi_tests.h"
+
+using namespace utest::v1;
+
+void wifi_connect_params_channel(void)
+{
+    WiFiInterface *wifi = get_interface();
+
+    if (wifi->set_channel(1) == NSAPI_ERROR_UNSUPPORTED && wifi->set_channel(36) == NSAPI_ERROR_UNSUPPORTED) {
+        TEST_IGNORE_MESSAGE("set_channel() not supported");
+        return;
+    }
+
+    nsapi_error_t error = wifi->connect(MBED_CONF_APP_WIFI_SECURE_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA2, MBED_CONF_APP_WIFI_CH_SECURE);
+    TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, error);
+}
+
diff --git a/TESTS/network/wifi/wifi_connect_params_channel_fail.cpp b/TESTS/network/wifi/wifi_connect_params_channel_fail.cpp
new file mode 100644
index 00000000000..f1d56d22496
--- /dev/null
+++ b/TESTS/network/wifi/wifi_connect_params_channel_fail.cpp
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "wifi_tests.h"
+
+using namespace utest::v1;
+
+void wifi_connect_params_channel_fail(void)
+{
+    WiFiInterface *wifi = get_interface();
+
+    if (wifi->set_channel(1) == NSAPI_ERROR_UNSUPPORTED && wifi->set_channel(36) == NSAPI_ERROR_UNSUPPORTED) {
+        TEST_IGNORE_MESSAGE("set_channel() not supported");
+        return;
+    }
+
+    nsapi_error_t error = wifi->connect(MBED_CONF_APP_WIFI_SECURE_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA2, MBED_CONF_APP_WIFI_CH_UNSECURE);
+    TEST_ASSERT(error==NSAPI_ERROR_CONNECTION_TIMEOUT || error==NSAPI_ERROR_NO_CONNECTION);
+}
+
diff --git a/TESTS/network/wifi/wifi_connect_params_null.cpp b/TESTS/network/wifi/wifi_connect_params_null.cpp
new file mode 100644
index 00000000000..6a471bd6049
--- /dev/null
+++ b/TESTS/network/wifi/wifi_connect_params_null.cpp
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "wifi_tests.h"
+
+using namespace utest::v1;
+
+void wifi_connect_params_null(void)
+{
+    WiFiInterface *wifi = get_interface();
+    TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_PARAMETER, wifi->connect(NULL, NULL));
+}
diff --git a/TESTS/network/wifi/wifi_connect_params_valid_secure.cpp b/TESTS/network/wifi/wifi_connect_params_valid_secure.cpp
new file mode 100644
index 00000000000..0da25c67927
--- /dev/null
+++ b/TESTS/network/wifi/wifi_connect_params_valid_secure.cpp
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "wifi_tests.h"
+
+using namespace utest::v1;
+
+void wifi_connect_params_valid_secure(void)
+{
+    WiFiInterface *wifi = get_interface();
+    TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->connect(MBED_CONF_APP_WIFI_SECURE_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA2));
+}
diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/debug.h b/TESTS/network/wifi/wifi_connect_params_valid_unsecure.cpp
similarity index 60%
rename from features/FEATURE_UVISOR/includes/uvisor/api/inc/debug.h
rename to TESTS/network/wifi/wifi_connect_params_valid_unsecure.cpp
index 22e4a24e001..e1540b24a8d 100644
--- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/debug.h
+++ b/TESTS/network/wifi/wifi_connect_params_valid_unsecure.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited, All Rights Reserved
+ * Copyright (c) 2017, ARM Limited, All Rights Reserved
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
@@ -14,19 +14,18 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
-#ifndef __UVISOR_API_DEBUG_H__
-#define __UVISOR_API_DEBUG_H__
 
-#include "api/inc/debug_exports.h"
-#include "api/inc/uvisor_exports.h"
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "wifi_tests.h"
 
-UVISOR_EXTERN_C_BEGIN
+using namespace utest::v1;
 
-static UVISOR_FORCEINLINE void uvisor_debug_init(const TUvisorDebugDriver * const driver)
+void wifi_connect_params_valid_unsecure(void)
 {
-    uvisor_api.debug_init(driver);
+    WiFiInterface *wifi = get_interface();
+    TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->connect(MBED_CONF_APP_WIFI_UNSECURE_SSID, NULL));
 }
 
-UVISOR_EXTERN_C_END
-
-#endif /* __UVISOR_API_DEBUG_H__ */
diff --git a/TESTS/network/wifi/wifi_connect_secure.cpp b/TESTS/network/wifi/wifi_connect_secure.cpp
new file mode 100644
index 00000000000..dce86f969fd
--- /dev/null
+++ b/TESTS/network/wifi/wifi_connect_secure.cpp
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "wifi_tests.h"
+
+using namespace utest::v1;
+
+void wifi_connect_secure(void)
+{
+    WiFiInterface *wifi = get_interface();
+
+    TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->set_credentials(MBED_CONF_APP_WIFI_SECURE_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA2));
+
+    TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->connect());
+}
+
diff --git a/TESTS/network/wifi/wifi_connect_secure_fail.cpp b/TESTS/network/wifi/wifi_connect_secure_fail.cpp
new file mode 100644
index 00000000000..7e55a290a87
--- /dev/null
+++ b/TESTS/network/wifi/wifi_connect_secure_fail.cpp
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "wifi_tests.h"
+
+using namespace utest::v1;
+
+void wifi_connect_secure_fail(void)
+{
+    WiFiInterface *wifi = get_interface();
+
+    TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->set_credentials(MBED_CONF_APP_WIFI_SECURE_SSID, "aaaaaaaa", NSAPI_SECURITY_WPA2));
+
+    TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_AUTH_FAILURE, wifi->connect());
+}
+
diff --git a/TESTS/network/wifi/wifi_get_rssi.cpp b/TESTS/network/wifi/wifi_get_rssi.cpp
new file mode 100644
index 00000000000..ac4338ff934
--- /dev/null
+++ b/TESTS/network/wifi/wifi_get_rssi.cpp
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "wifi_tests.h"
+
+using namespace utest::v1;
+
+void wifi_get_rssi(void)
+{
+    WiFiInterface *wifi = get_interface();
+
+    TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->set_credentials(MBED_CONF_APP_WIFI_UNSECURE_SSID, NULL));
+
+    TEST_ASSERT_EQUAL_INT8(0, wifi->get_rssi());
+
+    TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->connect());
+
+    TEST_ASSERT_INT8_WITHIN(-35, -65, wifi->get_rssi()); // -30 ... -100
+}
+
diff --git a/TESTS/network/wifi/wifi_scan.cpp b/TESTS/network/wifi/wifi_scan.cpp
new file mode 100644
index 00000000000..d4722dd0d08
--- /dev/null
+++ b/TESTS/network/wifi/wifi_scan.cpp
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "wifi_tests.h"
+#include <stdbool.h>
+
+using namespace utest::v1;
+
+void wifi_scan(void)
+{
+    WiFiInterface *wifi = get_interface();
+
+    WiFiAccessPoint ap[MBED_CONF_APP_MAX_SCAN_SIZE];
+
+    int size = wifi->scan(ap, MBED_CONF_APP_MAX_SCAN_SIZE);
+    TEST_ASSERT(size >= 2);
+
+    bool secure_found = false;
+    bool unsecure_found = false;
+
+    char secure_bssid[6];
+    char unsecure_bssid[6];
+    const char *coversion_string = "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx";
+    TEST_ASSERT_EQUAL_INT_MESSAGE(6, sscanf(MBED_CONF_APP_AP_MAC_SECURE, coversion_string, &secure_bssid[0], &secure_bssid[1], &secure_bssid[2], &secure_bssid[3], &secure_bssid[4], &secure_bssid[5]), "Failed to convert ap-mac-secure from mbed_app.json");
+    TEST_ASSERT_EQUAL_INT_MESSAGE(6, sscanf(MBED_CONF_APP_AP_MAC_UNSECURE, coversion_string, &unsecure_bssid[0], &unsecure_bssid[1], &unsecure_bssid[2], &unsecure_bssid[3], &unsecure_bssid[4], &unsecure_bssid[5]), "Failed to convert ap-mac-unsecure from mbed_app.json");
+
+    for (int i=0; i<size; i++) {
+        const char *ssid = ap[i].get_ssid();
+        const uint8_t *bssid = ap[i].get_bssid();
+        nsapi_security_t security = ap[i].get_security();
+        int8_t rssi = ap[i].get_rssi();
+        uint8_t ch = ap[i].get_channel();
+        TEST_ASSERT_NOT_EQUAL(0, strlen(ssid));
+        TEST_ASSERT_INT8_WITHIN(-35, -65, rssi);
+        if (strcmp(MBED_CONF_APP_WIFI_SECURE_SSID, ssid) == 0) {
+            secure_found = true;
+            TEST_ASSERT_EQUAL_INT(NSAPI_SECURITY_WPA2, security);
+            TEST_ASSERT_EQUAL_INT(MBED_CONF_APP_WIFI_CH_SECURE, ch);
+        }
+        if (strcmp(MBED_CONF_APP_WIFI_UNSECURE_SSID, ssid) == 0) {
+            unsecure_found = true;
+            TEST_ASSERT_EQUAL_INT(NSAPI_SECURITY_NONE, security);
+            TEST_ASSERT_EQUAL_INT(MBED_CONF_APP_WIFI_CH_UNSECURE, ch);
+        }
+    }
+    TEST_ASSERT_TRUE(secure_found);
+    TEST_ASSERT_TRUE(unsecure_found);
+}
+
diff --git a/TESTS/network/wifi/wifi_scan_null.cpp b/TESTS/network/wifi/wifi_scan_null.cpp
new file mode 100644
index 00000000000..784d91b8969
--- /dev/null
+++ b/TESTS/network/wifi/wifi_scan_null.cpp
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "wifi_tests.h"
+
+using namespace utest::v1;
+
+void wifi_scan_null(void)
+{
+    WiFiInterface *wifi = get_interface();
+    TEST_ASSERT(wifi->scan(NULL, 0) >= 2);
+}
+
diff --git a/TESTS/network/wifi/wifi_set_channel.cpp b/TESTS/network/wifi/wifi_set_channel.cpp
new file mode 100644
index 00000000000..ecb79150042
--- /dev/null
+++ b/TESTS/network/wifi/wifi_set_channel.cpp
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "wifi_tests.h"
+#include <stdbool.h>
+
+using namespace utest::v1;
+
+void wifi_set_channel(void)
+{
+    bool is_2Ghz = false;
+    bool is_5Ghz = false;
+
+    WiFiInterface *wifi = get_interface();
+
+    if (wifi->set_channel(1) == NSAPI_ERROR_UNSUPPORTED && wifi->set_channel(36) == NSAPI_ERROR_UNSUPPORTED) {
+        TEST_IGNORE_MESSAGE("set_channel() not supported");
+        return;
+    }
+
+    nsapi_error_t error;
+    error = wifi->set_channel(1);
+    if (error == NSAPI_ERROR_OK) {
+        is_2Ghz = true;
+    }
+
+    error = wifi->set_channel(30);
+    if (error == NSAPI_ERROR_OK) {
+        is_5Ghz = true;
+    }
+
+    TEST_ASSERT(is_2Ghz || is_5Ghz);
+
+    if (is_2Ghz) {
+        error = wifi->set_channel(0);
+        TEST_ASSERT(error == NSAPI_ERROR_PARAMETER);
+        error = wifi->set_channel(1);
+        TEST_ASSERT(error == NSAPI_ERROR_OK);
+        error = wifi->set_channel(13);
+        TEST_ASSERT(error == NSAPI_ERROR_OK || error == NSAPI_ERROR_PARAMETER);
+        error = wifi->set_channel(15);
+        TEST_ASSERT(error == NSAPI_ERROR_PARAMETER);
+    }
+
+    if (is_5Ghz) {
+        error = wifi->set_channel(30);
+        TEST_ASSERT(error == NSAPI_ERROR_PARAMETER);
+        error = wifi->set_channel(36);
+        TEST_ASSERT(error == NSAPI_ERROR_OK);
+        error = wifi->set_channel(169);
+        TEST_ASSERT(error == NSAPI_ERROR_PARAMETER);
+    }
+
+}
+
diff --git a/TESTS/network/wifi/wifi_set_credential.cpp b/TESTS/network/wifi/wifi_set_credential.cpp
new file mode 100644
index 00000000000..78f5d604270
--- /dev/null
+++ b/TESTS/network/wifi/wifi_set_credential.cpp
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+#include "greentea-client/test_env.h"
+#include "unity.h"
+#include "utest.h"
+#include "wifi_tests.h"
+
+using namespace utest::v1;
+
+void wifi_set_credential(void)
+{
+    WiFiInterface *iface = get_interface();
+    nsapi_error_t error;
+
+    error = iface->set_credentials(NULL, NULL, NSAPI_SECURITY_NONE);
+    TEST_ASSERT(error == NSAPI_ERROR_PARAMETER);
+
+    error = iface->set_credentials("OK", NULL, NSAPI_SECURITY_NONE);
+    TEST_ASSERT(error == NSAPI_ERROR_OK);
+
+    error = iface->set_credentials("OK", NULL, NSAPI_SECURITY_WEP);
+    TEST_ASSERT(error == NSAPI_ERROR_PARAMETER);
+
+    error = iface->set_credentials("OK", NULL, NSAPI_SECURITY_WPA_WPA2);
+    TEST_ASSERT(error == NSAPI_ERROR_PARAMETER);
+
+    error = iface->set_credentials("OK", "12345678", NSAPI_SECURITY_WPA);
+    TEST_ASSERT(error == NSAPI_ERROR_OK);
+
+    error = iface->set_credentials("OK", "12345678", NSAPI_SECURITY_WPA2);
+    TEST_ASSERT(error == NSAPI_ERROR_OK);
+
+    error = iface->set_credentials("OK", "12345678", NSAPI_SECURITY_WPA_WPA2);
+    TEST_ASSERT(error == NSAPI_ERROR_OK);
+
+    error = iface->set_credentials("OK", "kUjd0PHHeAqaDoyfcDDEOvbyiVbYMpUHDukGoR6EJZnO5iLzWsfwiM9JQqOngni82", NSAPI_SECURITY_WPA2);
+    TEST_ASSERT(error == NSAPI_ERROR_PARAMETER);
+}
diff --git a/TESTS/network/wifi/wifi_tests.h b/TESTS/network/wifi/wifi_tests.h
new file mode 100644
index 00000000000..1ef40ccc2de
--- /dev/null
+++ b/TESTS/network/wifi/wifi_tests.h
@@ -0,0 +1,63 @@
+#ifndef WIFI_TESTS_H
+#define WIFI_TESTS_H
+
+#include "WiFiInterface.h"
+
+/** Get WiFiInterface based on provided
+ * app_json. */
+WiFiInterface *get_interface(void);
+
+/*
+ * Test cases
+ */
+
+/** Test that constructor of the driver works. */
+void wifi_constructor(void);
+
+/** This test case is to test whether the driver accepts valid credentials and reject ones that are not valid. */
+void wifi_set_credential(void);
+
+/** Test validity of WiFiInterface::set_channel(). */
+void wifi_set_channel(void);
+
+/** Test WiFiInterface::get_rssi() API.
+ * When connected, it should return valid RSSI value. When unconnected it should return 0. */
+void wifi_get_rssi(void);
+
+/** Test WiFiInterface::connect(ssid, pass, security, channel) with NULL parameters */
+void wifi_connect_params_null(void);
+
+/** Test WiFiInterface::connect(ssid, pass, security) with valid parameters for unsecure network */
+void wifi_connect_params_valid_unsecure(void);
+
+/** Test WiFiInterface::connect(ssid, pass, security) with valid parameters for secure network */
+void wifi_connect_params_valid_secure(void);
+
+/** Test WiFiInterface::connect(ssid, pass, security, channel) with valid parameters for secure network using channel specified. */
+void wifi_connect_params_channel(void);
+
+/** Test WiFiInterface::connect(ssid, pass, security, channel) with valid parameters for secure network using wrong channel number. */
+void wifi_connect_params_channel_fail(void);
+
+/** Test WiFiInterface::connect() without parameters. Use set_credentials() for setting parameters. */
+void wifi_connect(void);
+
+/** Test WiFiInterface::connect() without parameters. Don't set parameters with set_credentials() */
+void wifi_connect_nocredentials(void);
+
+/** Test WiFiInterface::connect() without parameters. Use secure settings for set_credentials. */
+void wifi_connect_secure(void);
+
+/** Test WiFiInterface::connect() failing with wrong password. */
+void wifi_connect_secure_fail(void);
+
+/** Test WiFiInterface::connect() - disconnect() repeatition works. */
+void wifi_connect_disconnect_repeat(void);
+
+/** Call WiFiInterface::scan() with null parameters to get number of networks available. */
+void wifi_scan_null(void);
+
+/** Call WiFiInterface::scan() with valid accesspoint list allocated */
+void wifi_scan(void);
+
+#endif //WIFI_TESTS_H
diff --git a/doxyfile_options b/doxyfile_options
index 33eb3a2478d..4ee6b29a87d 100644
--- a/doxyfile_options
+++ b/doxyfile_options
@@ -32,7 +32,7 @@ DOXYFILE_ENCODING      = UTF-8
 # title of most generated pages and in a few other places.
 # The default value is: My Project.
 
-PROJECT_NAME           = "My Project"
+PROJECT_NAME           = "Mbed OS Reference"
 
 # The PROJECT_NUMBER tag can be used to enter a project or revision number. This
 # could be handy for archiving the generated documentation or if some version
@@ -846,7 +846,6 @@ EXCLUDE_PATTERNS       = */tools/* \
                          */features/mbedtls/* \
                          */features/storage/* \
                          */features/unsupported/* \
-                         */features/filesystem/* \
 
 # The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names
 # (namespaces, classes, functions, etc.) that should be excluded from the
diff --git a/doxygen_options.json b/doxygen_options.json
index 37433da2e86..834cac9270d 100644
--- a/doxygen_options.json
+++ b/doxygen_options.json
@@ -1,4 +1,5 @@
 {
+    "PROJECT_NAME": "Mbed OS Reference",
     "ENABLE_PREPROCESSING": "YES",
     "MACRO_EXPANSION": "YES",
     "EXPAND_ONLY_PREDEF": "NO",
@@ -8,5 +9,5 @@
     "PREDEFINED": "DOXYGEN_ONLY DEVICE_ANALOGIN DEVICE_ANALOGOUT DEVICE_CAN DEVICE_ETHERNET DEVICE_EMAC DEVICE_FLASH  DEVICE_I2C DEVICE_I2CSLAVE DEVICE_I2C_ASYNCH DEVICE_INTERRUPTIN DEVICE_LOWPOWERTIMER DEVICE_PORTIN DEVICE_PORTINOUT DEVICE_PORTOUT DEVICE_PWMOUT DEVICE_RTC DEVICE_TRNG DEVICE_SERIAL DEVICE_SERIAL_ASYNCH DEVICE_SERIAL_FC DEVICE_SLEEP DEVICE_SPI DEVICE_SPI_ASYNCH DEVICE_SPISLAVE DEVICE_STORAGE \"MBED_DEPRECATED_SINCE(f, g)=\" \"MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, M)=\"",
     "EXPAND_AS_DEFINED": "", 
     "SKIP_FUNCTION_MACROS": "NO",
-    "EXCLUDE_PATTERNS": "*/tools/* */TESTS/* */targets/* */FEATURE_*/* */features/mbedtls/* */features/storage/* */features/unsupported/* */features/filesystem/* */BUILD/* */rtos/TARGET_CORTEX/rtx*/* */cmsis/* */features/FEATURES_*"
+    "EXCLUDE_PATTERNS": "*/tools/* */TESTS/* */targets/* */FEATURE_*/* */features/mbedtls/* */features/storage/* */features/unsupported/* */BUILD/* */rtos/TARGET_CORTEX/rtx*/* */cmsis/* */features/FEATURES_*"
 }
diff --git a/drivers/CAN.cpp b/drivers/CAN.cpp
index e49b7adfcb7..b84d6082cee 100644
--- a/drivers/CAN.cpp
+++ b/drivers/CAN.cpp
@@ -46,6 +46,11 @@ CAN::CAN(PinName rd, PinName td, int hz) : _can(), _irq() {
 
 CAN::~CAN() {
     // No lock needed in destructor
+
+    // Detaching interrupts releases the sleep lock if it was locked
+    for (int irq = 0; irq < IrqCnt; irq++) {
+        attach(NULL, (IrqType)irq);
+    }
     can_irq_free(&_can);
     can_free(&_can);
 }
diff --git a/drivers/FlashIAP.h b/drivers/FlashIAP.h
index dd7b167e846..a6acc1bed90 100644
--- a/drivers/FlashIAP.h
+++ b/drivers/FlashIAP.h
@@ -112,6 +112,7 @@ class FlashIAP : private NonCopyable<FlashIAP> {
 
     /** Get the program page size
      *
+     *  The page size defines the writable page size
      *  @return Size of a program page in bytes
      */
     uint32_t get_page_size() const;
diff --git a/drivers/InterruptIn.cpp b/drivers/InterruptIn.cpp
index f555d4bdf8d..34f32104c31 100644
--- a/drivers/InterruptIn.cpp
+++ b/drivers/InterruptIn.cpp
@@ -19,17 +19,12 @@
 
 namespace mbed {
 
-static void donothing() {}
-
 InterruptIn::InterruptIn(PinName pin) : gpio(),
                                         gpio_irq(),
-                                        _rise(),
-                                        _fall() {
+                                        _rise(NULL),
+                                        _fall(NULL) {
     // No lock needed in the constructor
 
-    _rise = donothing;
-    _fall = donothing;
-
     gpio_irq_init(&gpio_irq, pin, (&InterruptIn::_irq_handler), (uint32_t)this);
     gpio_init_in(&gpio, pin);
 }
@@ -56,7 +51,7 @@ void InterruptIn::rise(Callback<void()> func) {
         _rise = func;
         gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
     } else {
-        _rise = donothing;
+        _rise = NULL;
         gpio_irq_set(&gpio_irq, IRQ_RISE, 0);
     }
     core_util_critical_section_exit();
@@ -68,7 +63,7 @@ void InterruptIn::fall(Callback<void()> func) {
         _fall = func;
         gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
     } else {
-        _fall = donothing;
+        _fall = NULL;
         gpio_irq_set(&gpio_irq, IRQ_FALL, 0);
     }
     core_util_critical_section_exit();
@@ -77,8 +72,16 @@ void InterruptIn::fall(Callback<void()> func) {
 void InterruptIn::_irq_handler(uint32_t id, gpio_irq_event event) {
     InterruptIn *handler = (InterruptIn*)id;
     switch (event) {
-        case IRQ_RISE: handler->_rise(); break;
-        case IRQ_FALL: handler->_fall(); break;
+        case IRQ_RISE: 
+            if (handler->_rise) {
+                handler->_rise();
+            }
+            break;
+        case IRQ_FALL: 
+            if (handler->_fall) {
+                handler->_fall(); 
+            }
+            break;
         case IRQ_NONE: break;
     }
 }
diff --git a/drivers/PwmOut.h b/drivers/PwmOut.h
index 1a90c3576ac..c94b8584fdd 100644
--- a/drivers/PwmOut.h
+++ b/drivers/PwmOut.h
@@ -21,6 +21,7 @@
 #if defined (DEVICE_PWMOUT) || defined(DOXYGEN_ONLY)
 #include "hal/pwmout_api.h"
 #include "platform/mbed_critical.h"
+#include "platform/mbed_sleep.h"
 
 namespace mbed {
 /** \addtogroup drivers */
@@ -56,12 +57,18 @@ class PwmOut {
      *
      *  @param pin PwmOut pin to connect to
      */
-    PwmOut(PinName pin) {
+    PwmOut(PinName pin) : _deep_sleep_locked(false) {
         core_util_critical_section_enter();
         pwmout_init(&_pwm, pin);
         core_util_critical_section_exit();
     }
 
+    ~PwmOut() {
+        core_util_critical_section_enter();
+        unlock_deep_sleep();
+        core_util_critical_section_exit();
+    }
+
     /** Set the ouput duty-cycle, specified as a percentage (float)
      *
      *  @param value A floating-point value representing the output duty-cycle,
@@ -71,6 +78,7 @@ class PwmOut {
      */
     void write(float value) {
         core_util_critical_section_enter();
+        lock_deep_sleep();
         pwmout_write(&_pwm, value);
         core_util_critical_section_exit();
     }
@@ -177,7 +185,24 @@ class PwmOut {
     }
 
 protected:
+    /** Lock deep sleep only if it is not yet locked */
+    void lock_deep_sleep() {
+        if (_deep_sleep_locked == false) {
+            sleep_manager_lock_deep_sleep();
+            _deep_sleep_locked = true;
+        }
+    }
+
+    /** Unlock deep sleep in case it is locked */
+    void unlock_deep_sleep() {
+        if (_deep_sleep_locked == true) {
+            sleep_manager_unlock_deep_sleep();
+            _deep_sleep_locked = false;
+        }
+    }
+
     pwmout_t _pwm;
+    bool _deep_sleep_locked;
 };
 
 } // namespace mbed
diff --git a/drivers/SerialBase.cpp b/drivers/SerialBase.cpp
index e07a44149dd..5ec47ff83a6 100644
--- a/drivers/SerialBase.cpp
+++ b/drivers/SerialBase.cpp
@@ -133,6 +133,16 @@ void SerialBase:: unlock() {
     // Stub
 }
 
+SerialBase::~SerialBase()
+{
+    // No lock needed in destructor
+
+    // Detaching interrupts releases the sleep lock if it was locked
+    for (int irq = 0; irq < IrqCnt; irq++) {
+        attach(NULL, (IrqType)irq);
+    }
+}
+
 #if DEVICE_SERIAL_FC
 void SerialBase::set_flow_control(Flow type, PinName flow1, PinName flow2) {
     lock();
diff --git a/drivers/SerialBase.h b/drivers/SerialBase.h
index 835e1a33b18..faf29a06998 100644
--- a/drivers/SerialBase.h
+++ b/drivers/SerialBase.h
@@ -241,8 +241,7 @@ class SerialBase : private NonCopyable<SerialBase> {
 
 protected:
     SerialBase(PinName tx, PinName rx, int baud);
-    virtual ~SerialBase() {
-    }
+    virtual ~SerialBase();
 
     int _base_getc();
     int _base_putc(int c);
diff --git a/drivers/Ticker.cpp b/drivers/Ticker.cpp
index 35c2ee43dd3..c2589c0d808 100644
--- a/drivers/Ticker.cpp
+++ b/drivers/Ticker.cpp
@@ -25,10 +25,11 @@ namespace mbed {
 void Ticker::detach() {
     core_util_critical_section_enter();
     remove();
-    // unlocked only if we were attached (we locked it)
-    if (_function) {
+    // unlocked only if we were attached (we locked it) and this is not low power ticker
+    if(_function && _lock_deepsleep) {
         sleep_manager_unlock_deep_sleep();
     }
+
     _function = 0;
     core_util_critical_section_exit();
 }
diff --git a/drivers/Ticker.h b/drivers/Ticker.h
index 66b38490519..c8f1f9deb33 100644
--- a/drivers/Ticker.h
+++ b/drivers/Ticker.h
@@ -21,13 +21,15 @@
 #include "platform/mbed_toolchain.h"
 #include "platform/NonCopyable.h"
 #include "platform/mbed_sleep.h"
+#include "hal/lp_ticker_api.h"
+#include "platform/mbed_critical.h"
 
 namespace mbed {
 /** \addtogroup drivers */
 
 /** A Ticker is used to call a function at a recurring interval
  *
- *  You can use as many seperate Ticker objects as you require.
+ *  You can use as many separate Ticker objects as you require.
  *
  * @note Synchronization level: Interrupt safe
  *
@@ -64,14 +66,18 @@ namespace mbed {
 class Ticker : public TimerEvent, private NonCopyable<Ticker> {
 
 public:
-    Ticker() : TimerEvent(), _function(0) {
+    Ticker() : TimerEvent(), _function(0), _lock_deepsleep(true) {
     }
 
-    Ticker(const ticker_data_t *data) : TimerEvent(data), _function(0) {
+    // When low power ticker is in use, then do not disable deep-sleep.
+    Ticker(const ticker_data_t *data) : TimerEvent(data), _function(0), _lock_deepsleep(true)  {
         data->interface->init();
+#if DEVICE_LOWPOWERTIMER
+        _lock_deepsleep = (data != get_lp_ticker_data());
+#endif
     }
 
-    /** Attach a function to be called by the Ticker, specifiying the interval in seconds
+    /** Attach a function to be called by the Ticker, specifying the interval in seconds
      *
      *  @param func pointer to the function to be called
      *  @param t the time between calls in seconds
@@ -80,7 +86,7 @@ class Ticker : public TimerEvent, private NonCopyable<Ticker> {
         attach_us(func, t * 1000000.0f);
     }
 
-    /** Attach a member function to be called by the Ticker, specifiying the interval in seconds
+    /** Attach a member function to be called by the Ticker, specifying the interval in seconds
      *
      *  @param obj pointer to the object to call the member function on
      *  @param method pointer to the member function to be called
@@ -97,21 +103,28 @@ class Ticker : public TimerEvent, private NonCopyable<Ticker> {
         attach(callback(obj, method), t);
     }
 
-    /** Attach a function to be called by the Ticker, specifiying the interval in micro-seconds
+    /** Attach a function to be called by the Ticker, specifying the interval in micro-seconds
      *
      *  @param func pointer to the function to be called
      *  @param t the time between calls in micro-seconds
+     *
+     *  @note setting @a t to a value shorter that it takes to process the ticker callback
+     *  will cause the system to hang. Ticker callback will be called constantly with no time
+     *  for threads scheduling.
+     *
      */
     void attach_us(Callback<void()> func, us_timestamp_t t) {
-        // lock only for the initial callback setup
-        if (!_function) {
+        core_util_critical_section_enter();
+        // lock only for the initial callback setup and this is not low power ticker
+        if(!_function && _lock_deepsleep) {
             sleep_manager_lock_deep_sleep();
         }
         _function = func;
         setup(t);
+        core_util_critical_section_exit();
     }
 
-    /** Attach a member function to be called by the Ticker, specifiying the interval in micro-seconds
+    /** Attach a member function to be called by the Ticker, specifying the interval in micro-seconds
      *
      *  @param obj pointer to the object to call the member function on
      *  @param method pointer to the member function to be called
@@ -143,6 +156,7 @@ class Ticker : public TimerEvent, private NonCopyable<Ticker> {
 protected:
     us_timestamp_t         _delay;  /**< Time delay (in microseconds) for re-setting the multi-shot callback. */
     Callback<void()>    _function;  /**< Callback. */
+    bool          _lock_deepsleep;  /**< Flag which indicates if deep-sleep should be disabled. */
 };
 
 } // namespace mbed
diff --git a/drivers/Timer.cpp b/drivers/Timer.cpp
index 12f9737ca46..f523974e6b4 100644
--- a/drivers/Timer.cpp
+++ b/drivers/Timer.cpp
@@ -17,21 +17,38 @@
 #include "hal/ticker_api.h"
 #include "hal/us_ticker_api.h"
 #include "platform/mbed_critical.h"
+#include "hal/lp_ticker_api.h"
 
 namespace mbed {
 
-Timer::Timer() : _running(), _start(), _time(), _ticker_data(get_us_ticker_data()) {
+Timer::Timer() : _running(), _start(), _time(), _ticker_data(get_us_ticker_data()), _lock_deepsleep(true) {
     reset();
 }
 
-Timer::Timer(const ticker_data_t *data) : _running(), _start(), _time(), _ticker_data(data) {
+Timer::Timer(const ticker_data_t *data) : _running(), _start(), _time(), _ticker_data(data), _lock_deepsleep(true) {
     reset();
+#if DEVICE_LOWPOWERTIMER
+    _lock_deepsleep = (data != get_lp_ticker_data());
+#endif
+}
+
+Timer::~Timer() {
+    core_util_critical_section_enter();
+    if (_running) {
+        if(_lock_deepsleep) {
+            sleep_manager_unlock_deep_sleep();
+        }
+    }
+    _running = 0;
+    core_util_critical_section_exit();
 }
 
 void Timer::start() {
     core_util_critical_section_enter();
     if (!_running) {
-        sleep_manager_lock_deep_sleep();
+        if(_lock_deepsleep) {
+            sleep_manager_lock_deep_sleep();
+        }
         _start = ticker_read_us(_ticker_data);
         _running = 1;
     }
@@ -42,7 +59,9 @@ void Timer::stop() {
     core_util_critical_section_enter();
     _time += slicetime();
     if (_running) {
-        sleep_manager_unlock_deep_sleep();
+        if(_lock_deepsleep) {
+            sleep_manager_unlock_deep_sleep();
+        }
     }
     _running = 0;
     core_util_critical_section_exit();
diff --git a/drivers/Timer.h b/drivers/Timer.h
index e353720b966..a8758005d45 100644
--- a/drivers/Timer.h
+++ b/drivers/Timer.h
@@ -53,6 +53,7 @@ class Timer : private NonCopyable<Timer> {
 public:
     Timer();
     Timer(const ticker_data_t *data);
+    ~Timer();
 
     /** Start the timer
      */
@@ -100,6 +101,7 @@ class Timer : private NonCopyable<Timer> {
     us_timestamp_t _start;   // the start time of the latest slice
     us_timestamp_t _time;    // any accumulated time from previous slices
     const ticker_data_t *_ticker_data;
+    bool _lock_deepsleep;    // flag which indicates if deep-sleep should be disabled
 };
 
 } // namespace mbed
diff --git a/drivers/UARTSerial.cpp b/drivers/UARTSerial.cpp
index 96cdc831d84..5cad4ffc827 100644
--- a/drivers/UARTSerial.cpp
+++ b/drivers/UARTSerial.cpp
@@ -19,7 +19,12 @@
 #include <errno.h>
 #include "UARTSerial.h"
 #include "platform/mbed_poll.h"
+
+#if MBED_CONF_RTOS_PRESENT
+#include "rtos/Thread.h"
+#else
 #include "platform/mbed_wait_api.h"
+#endif
 
 namespace mbed {
 
@@ -277,6 +282,17 @@ void UARTSerial::tx_irq(void)
     }
 }
 
+void UARTSerial::wait_ms(uint32_t millisec)
+{
+    /* wait_ms implementation for RTOS spins until exact microseconds - we
+     * want to just sleep until next tick.
+     */
+#if MBED_CONF_RTOS_PRESENT
+    rtos::Thread::wait(millisec);
+#else
+    ::wait_ms(millisec);
+#endif
+}
 } //namespace mbed
 
 #endif //(DEVICE_SERIAL && DEVICE_INTERRUPTIN)
diff --git a/drivers/UARTSerial.h b/drivers/UARTSerial.h
index ebb5779c1c7..f6ff523f8f6 100644
--- a/drivers/UARTSerial.h
+++ b/drivers/UARTSerial.h
@@ -39,6 +39,13 @@
 
 namespace mbed {
 
+/** \addtogroup drivers */
+
+/** Class providing buffered UART communication functionality using separate circular buffer for send and receive channels
+ *  
+ * @ingroup drivers
+ */
+
 class UARTSerial : private SerialBase, public FileHandle, private NonCopyable<UARTSerial> {
 
 public:
@@ -56,6 +63,12 @@ class UARTSerial : private SerialBase, public FileHandle, private NonCopyable<UA
      */
     virtual short poll(short events) const;
 
+    /* Resolve ambiguities versus our private SerialBase
+     * (for writable, spelling differs, but just in case)
+     */
+    using FileHandle::readable;
+    using FileHandle::writable;
+
     /** Write the contents of a buffer to a file
      *
      *  @param buffer   The buffer to write from
@@ -160,6 +173,8 @@ class UARTSerial : private SerialBase, public FileHandle, private NonCopyable<UA
 
 private:
 
+    void wait_ms(uint32_t millisec);
+
     /** SerialBase lock override */
     virtual void lock(void);
 
diff --git a/features/FEATURE_BLE/ble/GattService.h b/features/FEATURE_BLE/ble/GattService.h
index d638b3c9167..bfc7c211dd3 100644
--- a/features/FEATURE_BLE/ble/GattService.h
+++ b/features/FEATURE_BLE/ble/GattService.h
@@ -46,8 +46,7 @@ class GattService {
 
 public:
     /**
-     *  @brief  Creates a new GattService using the specified 16-bit
-     *          UUID, value length, and properties.
+     *  @brief  Creates a new GattService using the specified UUID and characteristics.
      *
      *  @note   The UUID value must be unique and is normally >1.
      *
diff --git a/features/FEATURE_BLE/ble/services/BatteryService.h b/features/FEATURE_BLE/ble/services/BatteryService.h
index 5aa419a4690..e6025af5152 100644
--- a/features/FEATURE_BLE/ble/services/BatteryService.h
+++ b/features/FEATURE_BLE/ble/services/BatteryService.h
@@ -14,64 +14,119 @@
  * limitations under the License.
  */
 
-#ifndef __BLE_BATTERY_SERVICE_H__
-#define __BLE_BATTERY_SERVICE_H__
+#ifndef MBED_BLE_BATTERY_SERVICE_H__
+#define MBED_BLE_BATTERY_SERVICE_H__
 
+#include "platform/mbed_assert.h"
 #include "ble/BLE.h"
 
 /**
-* @class BatteryService
-* @brief BLE Battery Service. This service displays the battery level from 0% to 100%, represented as an 8bit number.
-* Service:  https://developer.bluetooth.org/gatt/services/Pages/ServiceViewer.aspx?u=org.bluetooth.service.battery_service.xml
-* Battery Level Char:  https://developer.bluetooth.org/gatt/characteristics/Pages/CharacteristicViewer.aspx?u=org.bluetooth.characteristic.battery_level.xml
-*/
+ * BLE Battery service.
+ *
+ * @par purpose
+ *
+ * The battery service exposes the charge level of the battery of the device.
+ * This information is exposed as a percentage from 0% to 100%; a value of 0%
+ * represents a fully discharged battery, and a value of 100% represents a
+ * fully charged battery.
+ *
+ * Clients can read the current charge level and subscribe to server initiated
+ * updates of the charge level. The server delivers these updates to the subscribed
+ * client in a notification packet.
+ *
+ * The subscription mechanism is useful to save power; it avoids unecessary data
+ * traffic between the client and the server, which may be induced by polling the
+ * battery level characteristic value.
+ *
+ * @par usage
+ *
+ * When this class is instantiated, it adds a battery service in the GattServer.
+ *
+ * The application code can use the function updateBatteryLevel() to update the
+ * charge level that the service exposes and to notify the subscribed client that the
+ * value changed.
+ *
+ * @note You can find specification of the battery service here:
+ * https://www.bluetooth.com/specifications/gatt
+ *
+ * @important Multiple instances of this battery service are not supported.
+ */
 class BatteryService {
 public:
     /**
-     * @param[in] _ble
-     *               BLE object for the underlying controller.
-     * @param[in] level
-     *               8bit batterly level. Usually used to represent percentage of batterly charge remaining.
+     * Instantiate a battery service.
+     *
+     * The construction of a BatteryService adds a GATT battery service in @p
+     * _ble GattServer and sets the initial charge level of the battery to @p
+     * level.
+     *
+     * @param[in] _ble BLE device which will host the battery service.
+     * @param[in] level Initial charge level of the battery. It is a percentage
+     * where 0% means that the battery is fully discharged and 100% means that
+     * the battery is fully charged.
      */
     BatteryService(BLE &_ble, uint8_t level = 100) :
         ble(_ble),
         batteryLevel(level),
-        batteryLevelCharacteristic(GattCharacteristic::UUID_BATTERY_LEVEL_CHAR, &batteryLevel, GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_NOTIFY) {
-
-        GattCharacteristic *charTable[] = {&batteryLevelCharacteristic};
-        GattService         batteryService(GattService::UUID_BATTERY_SERVICE, charTable, sizeof(charTable) / sizeof(GattCharacteristic *));
+        batteryLevelCharacteristic(
+            GattCharacteristic::UUID_BATTERY_LEVEL_CHAR,
+            &batteryLevel,
+            GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_NOTIFY
+        )
+    {
+        MBED_ASSERT(level <= 100);
+        GattCharacteristic *charTable[] = { &batteryLevelCharacteristic };
+        GattService batteryService(
+            GattService::UUID_BATTERY_SERVICE,
+            charTable,
+            sizeof(charTable) / sizeof(GattCharacteristic *)
+        );
 
         ble.addService(batteryService);
     }
 
     /**
-     * @brief Update the battery level with a new value. Valid values lie between 0 and 100,
-     * anything outside this range will be ignored.
+     * Update the battery charge level that the service exposes.
      *
-     * @param newLevel
-     *              Update to battery level.
+     * The server sends a notification of the new value to clients that have
+     * subscribed to the battery level characteristic updates, and clients
+     * reading the charge level after the update obtain the updated value.
+     *
+     * @param newLevel Charge level of the battery. It is a percentage of the
+     * remaining charge between 0% and 100%.
+     *
+     * @important This function must be called in the execution context of the
+     * BLE stack.
      */
-    void updateBatteryLevel(uint8_t newLevel) {
+    void updateBatteryLevel(uint8_t newLevel)
+    {
+        MBED_ASSERT(newLevel <= 100);
         batteryLevel = newLevel;
-        ble.gattServer().write(batteryLevelCharacteristic.getValueHandle(), &batteryLevel, 1);
+        ble.gattServer().write(
+            batteryLevelCharacteristic.getValueHandle(),
+            &batteryLevel,
+            1
+        );
     }
 
 protected:
     /**
-     * A reference to the underlying BLE instance that this object is attached to.
-     * The services and characteristics will be registered in this BLE instance.
+     * Reference to the underlying BLE instance that this object is attached to.
+     *
+     * The services and characteristics are registered in the GattServer of
+     * this BLE instance.
      */
     BLE &ble;
 
     /**
      * The current battery level represented as an integer from 0% to 100%.
      */
-    uint8_t    batteryLevel;
+    uint8_t batteryLevel;
+
     /**
-     * A ReadOnlyGattCharacteristic that allows access to the peer device to the
-     * batteryLevel value through BLE.
+     * The GATT characteristic, which exposes the charge level.
      */
     ReadOnlyGattCharacteristic<uint8_t> batteryLevelCharacteristic;
 };
 
-#endif /* #ifndef __BLE_BATTERY_SERVICE_H__*/
+#endif /* #ifndef MBED_BLE_BATTERY_SERVICE_H__*/
diff --git a/features/FEATURE_BLE/ble/services/UARTService.h b/features/FEATURE_BLE/ble/services/UARTService.h
index 1043ddbf465..e8701ab155f 100644
--- a/features/FEATURE_BLE/ble/services/UARTService.h
+++ b/features/FEATURE_BLE/ble/services/UARTService.h
@@ -140,6 +140,19 @@ class UARTService {
         return write(str, strlen(str));
     }
 
+    /**
+     * Flush sendBuffer, i.e., forcefully write its contents to the UART RX
+     * characteristic even if the buffer is not full.
+     */
+    void flush() {
+        if (ble.getGapState().connected) {
+            if (sendBufferIndex != 0) {
+                ble.gattServer().write(getRXCharacteristicHandle(), static_cast<const uint8_t *>(sendBuffer), sendBufferIndex);
+                sendBufferIndex = 0;
+            }
+        }
+    }
+
     /**
      * Override for Stream::_putc().
      * @param  c
diff --git a/features/FEATURE_BLE/ble/services/iBeacon.h b/features/FEATURE_BLE/ble/services/iBeacon.h
index 0bdaf4dc657..bc520d3a0ae 100644
--- a/features/FEATURE_BLE/ble/services/iBeacon.h
+++ b/features/FEATURE_BLE/ble/services/iBeacon.h
@@ -13,63 +13,230 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
-#ifndef __BLE_IBEACON_H__
-#define __BLE_IBEACON_H__
+#ifndef MBED_BLE_IBEACON_H__
+#define MBED_BLE_IBEACON_H__
 
 #include "cmsis_compiler.h"
 #include "ble/BLE.h"
 
 /**
-* @class iBeacon
-* @brief iBeacon Service. This sets up a device to broadcast advertising packets to mimic an iBeacon.
-*/
+ * iBeacon Service.
+ *
+ * @par Purpose
+ *
+ * iBeacons are Bluetooth Low Energy (BLE) devices advertising an identification
+ * number generally used to determine the location of devices or physical objects
+ * near a mobile phone user.
+ *
+ * iOS scans for iBeacon devices in a background task and notifies Apps
+ * subscribed to a specific region when the area is entered or left. Apps may
+ * use this information to display context-aware content to users.
+ *
+ * As an example, a museum can deploy an app that informs the user when one of
+ * its exhibitions is entered and then displays specific information about exposed
+ * pieces of art when the user is sufficiently close to them.
+ *
+ * @par Positioning
+ *
+ * Location information is hierarchically structured. A UUID specific to the
+ * application and its deployment is used to identify a region. That region
+ * usually identifies an organization. The region is divided into subregions
+ * identified by a major ID. The subregion contains related points of interest
+ * which a minor ID distinguishes.
+ *
+ * As an example, a city willing to improve tourist's experience can deploy a fleet
+ * of iBeacons in relevant touristic locations it operates. The UUID may
+ * identify a place managed by the city. The major ID would identify the place;
+ * it can be a museum, a historic monument, a metro station and so on. The minor ID
+ * would locate a specific spot within a specific city place. It can be a
+ * piece of art, a ticket dispenser or a relevant point of interest.
+ *
+ * Each iBeacon device is physically attached to the spot it locates and
+ * advertises the triplet UUID, major ID and minor ID.
+ *
+ * @par Proximity
+ *
+ * The beacon advertises the signal strength measured by an iOS device at a
+ * distance of one meter. iOS uses this information to approximate the
+ * proximity to a given beacon:
+ *   - Immediate: The beacon is less than one meter away from the user.
+ *   - Near: The beacon is one to three meters away from the user.
+ *   - Far: The user is not near the beacon; the distance highly depends on
+ *     the physical environment.
+ *
+ * Ideally, beacons should be calibrated at their deployment location because the
+ * surrounding environment affects the strength of the advertised signal.
+ *
+ * @par Usage
+ *
+ * Mbed OS applications can use this class to configure a device to broadcast
+ * advertising packets mimicking an iBeacon. The construction automatically
+ * creates the payload identifying the beacon and registers it as part of the
+ * advertising payload of the device.
+ *
+ * Beacon configuration and advertising commencement is left to the user.
+ *
+ * @important If you are interested in manufacturing iBeacons, you must obtain a
+ * license from Apple. More information at https://developer.apple.com/ibeacon/.
+ * The licence also grant access to the iBeacons technical specification.
+ *
+ * @note More information at https://developer.apple.com/ibeacon/Getting-Started-with-iBeacon.pdf
+ */
 class iBeacon
 {
 public:
+    /**
+     * Data buffer of a location UUID.
+     */
     typedef const uint8_t LocationUUID_t[16];
 
+    /**
+     * iBeacon payload builder.
+     *
+     * This data structure contains the payload of an iBeacon. The payload is
+     * built at construction time and application code can set up an iBeacon by
+     * injecting the raw field into the GAP advertising payload as a
+     * GapAdvertisingData::MANUFACTURER_SPECIFIC_DATA.
+     */
     union Payload {
+        /**
+         * Raw data of the payload.
+         */
         uint8_t raw[25];
         struct {
+            /**
+             * Beacon manufacturer identifier.
+             */
             uint16_t companyID;
+
+            /**
+             * Packet ID; Equal to 2 for an iBeacon.
+             */
             uint8_t ID;
+
+            /**
+             * Length of the remaining data presents in the payload.
+             */
             uint8_t len;
+
+            /**
+             * Beacon UUID.
+             */
             uint8_t proximityUUID[16];
+
+            /**
+             * Beacon Major group ID.
+             */
             uint16_t majorNumber;
+
+            /**
+             * Beacon minor ID.
+             */
             uint16_t minorNumber;
+
+            /**
+             * Tx power received at 1 meter; in dBm.
+             */
             uint8_t txPower;
         };
 
-        Payload(LocationUUID_t uuid, uint16_t majNum, uint16_t minNum, uint8_t transmitPower, uint16_t companyIDIn) :
-            companyID(companyIDIn), ID(0x02), len(0x15), majorNumber(__REV16(majNum)), minorNumber(__REV16(minNum)), txPower(transmitPower)
+        /**
+         * Assemble an iBeacon payload.
+         *
+         * @param[in] uuid Beacon network ID. iBeacon operators use this value
+         * to group their iBeacons into a single network, a single region and
+         * identify their organization among others.
+         *
+         * @param[in] majNum Beacon major group ID. iBeacon exploitants may use
+         * this field to divide the region into subregions, their network into
+         * subnetworks.
+         *
+         * @param[in] minNum Identifier of the Beacon in its subregion.
+         *
+         * @param[in] transmitPower Measured transmit power of the beacon at 1
+         * meter. Scanners use this parameter to approximate the distance
+         * to the beacon.
+         *
+         * @param[in] companyIDIn ID of the beacon manufacturer.
+         */
+        Payload(
+            LocationUUID_t uuid,
+            uint16_t majNum,
+            uint16_t minNum,
+            uint8_t transmitPower,
+            uint16_t companyIDIn
+        ) : companyID(companyIDIn),
+            ID(0x02),
+            len(0x15),
+            majorNumber(__REV16(majNum)),
+            minorNumber(__REV16(minNum)),
+            txPower(transmitPower)
         {
             memcpy(proximityUUID, uuid, sizeof(LocationUUID_t));
         }
     };
 
 public:
-    iBeacon(BLE            &_ble,
-            LocationUUID_t  uuid,
-            uint16_t        majNum,
-            uint16_t        minNum,
-            uint8_t         txP    = 0xC8,
-            uint16_t        compID = 0x004C) :
-        ble(_ble), data(uuid, majNum, minNum, txP, compID)
+    /**
+     * Construct an iBeacon::Payload and register it into Gap.
+     *
+     * @param[in] _ble The BLE interface to configure with the iBeacon payload.
+     *
+     * @param[in] uuid Beacon network ID. iBeacon operators use this value
+     * to group their iBeacons into a single network, a single region and
+     * identify their organization among others.
+     *
+     * @param[in] majNum Beacon major group ID. iBeacon exploitants may use
+     * this field to divide the region into subregions, their network into
+     * subnetworks.
+     *
+     * @param[in] minNum Identifier of the Beacon in its subregion.
+     *
+     * @param[in] txP Measured transmit power of the beacon at 1
+     * meter. Scanners use this parameter to approximate the distance
+     * to the beacon.
+     *
+     * @param[in] compID ID of the beacon manufacturer.
+     */
+    iBeacon(
+        BLE &_ble,
+        LocationUUID_t uuid,
+        uint16_t majNum,
+        uint16_t minNum,
+        uint8_t txP = 0xC8,
+        uint16_t compID = 0x004C
+    ) : ble(_ble),
+        data(uuid, majNum, minNum, txP, compID)
     {
         // Generate the 0x020106 part of the iBeacon Prefix.
-        ble.accumulateAdvertisingPayload(GapAdvertisingData::BREDR_NOT_SUPPORTED | GapAdvertisingData::LE_GENERAL_DISCOVERABLE );
+        ble.accumulateAdvertisingPayload(
+            GapAdvertisingData::BREDR_NOT_SUPPORTED |
+            GapAdvertisingData::LE_GENERAL_DISCOVERABLE
+        );
         // Generate the 0x1AFF part of the iBeacon Prefix.
-        ble.accumulateAdvertisingPayload(GapAdvertisingData::MANUFACTURER_SPECIFIC_DATA, data.raw, sizeof(data.raw));
+        ble.accumulateAdvertisingPayload(
+            GapAdvertisingData::MANUFACTURER_SPECIFIC_DATA,
+            data.raw,
+            sizeof(data.raw)
+        );
 
         // Set advertising type.
-        ble.setAdvertisingType(GapAdvertisingParams::ADV_NON_CONNECTABLE_UNDIRECTED);
+        ble.setAdvertisingType(
+            GapAdvertisingParams::ADV_NON_CONNECTABLE_UNDIRECTED
+        );
     }
 
 protected:
-    BLE     &ble;
-    Payload  data;
+    BLE &ble;
+    Payload data;
 };
 
-typedef iBeacon iBeaconService; /* This type-alias is deprecated. Please use iBeacon directly. This alias may be dropped from a future release. */
+/**
+ * iBeacon alias.
+ *
+ * @deprecated Please use iBeacon directly. This alias may be dropped from a
+ * future release.
+ */
+typedef iBeacon iBeaconService;
 
-#endif //__BLE_IBEACON_H__
+#endif //MBED_BLE_IBEACON_H__
diff --git a/features/FEATURE_BLE/targets/TARGET_ARM_SSG/TARGET_BEETLE/source/ArmGattServer.cpp b/features/FEATURE_BLE/targets/TARGET_ARM_SSG/TARGET_BEETLE/source/ArmGattServer.cpp
index 299b029f4ec..ee90a156a28 100644
--- a/features/FEATURE_BLE/targets/TARGET_ARM_SSG/TARGET_BEETLE/source/ArmGattServer.cpp
+++ b/features/FEATURE_BLE/targets/TARGET_ARM_SSG/TARGET_BEETLE/source/ArmGattServer.cpp
@@ -130,6 +130,9 @@ ble_error_t ArmGattServer::addService(GattService &service)
         currAtt->pLen = p_char->getValueAttribute().getLengthPtr();
         currAtt->maxLen = p_char->getValueAttribute().getMaxLength();
         currAtt->settings = ATTS_SET_WRITE_CBACK | ATTS_SET_READ_CBACK;
+        if (p_char->getValueAttribute().hasVariableLength()) {
+            currAtt->settings |= ATTS_SET_VARIABLE_LEN;
+        }
         if (p_char->getValueAttribute().getUUID().shortOrLong() == UUID::UUID_TYPE_LONG) {
             currAtt->settings |= ATTS_SET_UUID_128;
         }
diff --git a/features/FEATURE_LWIP/TESTS/mbedmicro-net/.mbedignore b/features/FEATURE_LWIP/TESTS/mbedmicro-net/.mbedignore
deleted file mode 100644
index 709fc036051..00000000000
--- a/features/FEATURE_LWIP/TESTS/mbedmicro-net/.mbedignore
+++ /dev/null
@@ -1 +0,0 @@
-host_tests/*
\ No newline at end of file
diff --git a/features/FEATURE_LWIP/TESTS/mbedmicro-net/udp_echo_parallel/main.cpp b/features/FEATURE_LWIP/TESTS/mbedmicro-net/udp_echo_parallel/main.cpp
deleted file mode 100644
index 8e8c19ccf11..00000000000
--- a/features/FEATURE_LWIP/TESTS/mbedmicro-net/udp_echo_parallel/main.cpp
+++ /dev/null
@@ -1,242 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#if !FEATURE_LWIP
-    #error [NOT_SUPPORTED] LWIP not supported for this target
-#endif
-#if DEVICE_EMAC
-    #error [NOT_SUPPORTED] Not supported for WiFi targets
-#endif
-
-#include "mbed.h"
-#include "EthernetInterface.h"
-#include "UDPSocket.h"
-#include "greentea-client/test_env.h"
-#include "unity/unity.h"
-#include "utest.h"
-
-using namespace utest::v1;
-
-
-#ifndef MBED_CFG_UDP_CLIENT_ECHO_BUFFER_SIZE
-#define MBED_CFG_UDP_CLIENT_ECHO_BUFFER_SIZE 64
-#endif
-
-#ifndef MBED_CFG_UDP_CLIENT_ECHO_TIMEOUT
-#define MBED_CFG_UDP_CLIENT_ECHO_TIMEOUT 500
-#endif
-
-#ifndef MBED_CFG_UDP_CLIENT_ECHO_THREADS
-#define MBED_CFG_UDP_CLIENT_ECHO_THREADS 3
-#endif
-
-
-const int ECHO_LOOPS = 16;
-EthernetInterface net;
-SocketAddress udp_addr;
-Mutex iomutex;
-char uuid[GREENTEA_UUID_LENGTH] = {0};
-
-// Thread safe printf macro
-#define TS_PRINTF(...) {\
-    iomutex.lock();\
-    printf(__VA_ARGS__);\
-    iomutex.unlock();\
-}
-
-// NOTE: assuming that "id" stays in the single digits
-//
-// Creates a buffer that first contains the thread's id.
-//
-// The second part of the buffer contains the test's UUID so the output can be
-// associated with individual test runs.
-//
-// The rest of the buffer is filled with random data so it is unique within the
-// CURRENT test run.
-//
-// Ex. A thread with id "2" and a test with UUID of `33e5002c-9722-4685-817a-709cc69c4701`
-// would have a buffer filled with something like `2 33e5002c-9722-4685-817a-709cc69c4701 12594387`
-// where `2` is the thread id, `33e5002c-9722-4685-817a-709cc69c4701` is the UUID
-// and `12594387` is the random data
-void prep_buffer(unsigned int id, char *uuid, char *tx_buffer, size_t tx_size) {
-    size_t i = 0;
-
-    tx_buffer[i++] = '0' + id;
-    tx_buffer[i++] = ' ';
-
-    memcpy(tx_buffer+i, uuid, strlen(uuid));
-    i += strlen(uuid);
-
-    tx_buffer[i++] = ' ';
-
-    for (; i<tx_size; ++i) {
-        tx_buffer[i] = (rand() % 10) + '0';
-    }
-}
-
-// Each echo class is in charge of one parallel transaction
-class Echo {
-private:
-    char tx_buffer[MBED_CFG_UDP_CLIENT_ECHO_BUFFER_SIZE];
-    char rx_buffer[MBED_CFG_UDP_CLIENT_ECHO_BUFFER_SIZE];
-
-    UDPSocket sock;
-    Thread thread;
-    bool result;
-    unsigned int id;
-    char *uuid;
-
-public:
-    // Limiting stack size to 1k
-    Echo(): thread(osPriorityNormal, 1024), result(false) {
-    }
-
-    void start(unsigned int id, char *uuid) {
-        this->id = id;
-        this->uuid = uuid;
-        osStatus status = thread.start(callback(this, &Echo::echo));
-    }
-
-    void join() {
-        osStatus status = thread.join();
-        TEST_ASSERT_EQUAL(osOK, status);
-    }
-
-    void echo() {
-        int success = 0;
-
-        int err = sock.open(&net);
-        TEST_ASSERT_EQUAL(0, err);
-
-        sock.set_timeout(MBED_CFG_UDP_CLIENT_ECHO_TIMEOUT);
-
-        for (unsigned int i = 0; success < ECHO_LOOPS; i++) {
-            prep_buffer(id, uuid, tx_buffer, sizeof(tx_buffer));
-            int ret = sock.sendto(udp_addr, tx_buffer, sizeof(tx_buffer));
-            if (ret >= 0) {
-                TS_PRINTF("[ID:%01u][%02u] sent %d bytes - %.*s  \n", id, i, ret, ret, tx_buffer);
-            } else {
-                TS_PRINTF("[ID:%01u][%02u] Network error %d\n", id, i, ret);
-                continue;
-            }
-
-            SocketAddress temp_addr;
-            ret = sock.recvfrom(&temp_addr, rx_buffer, sizeof(rx_buffer));
-            if (ret >= 0) {
-                TS_PRINTF("[ID:%01u][%02u] recv %d bytes - %.*s  \n", id, i, ret, ret, tx_buffer);
-            } else {
-                TS_PRINTF("[ID:%01u][%02u] Network error %d\n", id, i, ret);
-                continue;
-            }
-
-            if ((temp_addr == udp_addr &&
-                 ret == sizeof(tx_buffer) &&
-                 memcmp(rx_buffer, tx_buffer, sizeof(rx_buffer)) == 0)) {
-                success += 1;
-                TS_PRINTF("[ID:%01u][%02u] success #%d\n", id, i, success);
-                continue;
-            }
-
-            // failed, clean out any remaining bad packets
-            sock.set_timeout(0);
-            while (true) {
-                err = sock.recvfrom(NULL, NULL, 0);
-                if (err == NSAPI_ERROR_WOULD_BLOCK) {
-                    break;
-                }
-            }
-            sock.set_timeout(MBED_CFG_UDP_CLIENT_ECHO_TIMEOUT);
-        }
-
-        result = success == ECHO_LOOPS;
-
-        if (result) {
-            TS_PRINTF("[ID:%01u] Succeeded all %d times!\n", id, success);
-        } else {
-            TS_PRINTF("[ID:%01u] Only succeeded %d times out of a required %d.\n", id, success, ECHO_LOOPS);
-        }
-
-        err = sock.close();
-        if (err) {
-            TS_PRINTF("[ID:%01u] Failed to close socket!\n", id);
-            result = false;
-        }
-    }
-
-    bool get_result() {
-        return result;
-    }
-};
-
-Echo *echoers[MBED_CFG_UDP_CLIENT_ECHO_THREADS];
-
-void test_udp_echo_parallel() {
-    int err = net.connect();
-    TEST_ASSERT_EQUAL(0, err);
-
-    printf("UDP client IP Address is %s\n", net.get_ip_address());
-
-    greentea_send_kv("target_ip", net.get_ip_address());
-
-    char recv_key[] = "host_port";
-    char ipbuf[60] = {0};
-    char portbuf[16] = {0};
-    unsigned int port = 0;
-
-    greentea_send_kv("host_ip", " ");
-    greentea_parse_kv(recv_key, ipbuf, sizeof(recv_key), sizeof(ipbuf));
-
-    greentea_send_kv("host_port", " ");
-    greentea_parse_kv(recv_key, portbuf, sizeof(recv_key), sizeof(ipbuf));
-    sscanf(portbuf, "%u", &port);
-
-    printf("MBED: UDP Server IP address received: %s:%d \n", ipbuf, port);
-    udp_addr.set_ip_address(ipbuf);
-    udp_addr.set_port(port);
-
-    // Startup echo threads in parallel
-    for (unsigned int i = 0; i < MBED_CFG_UDP_CLIENT_ECHO_THREADS; i++) {
-        echoers[i] = new Echo;
-        echoers[i]->start(i, uuid);
-    }
-
-    bool result = true;
-
-    for (unsigned int i = 0; i < MBED_CFG_UDP_CLIENT_ECHO_THREADS; i++) {
-        echoers[i]->join();
-        result = result && echoers[i]->get_result();
-        delete echoers[i];
-    }
-
-    net.disconnect();
-    TEST_ASSERT(result);
-}
-
-
-// Test setup
-utest::v1::status_t test_setup(const size_t number_of_cases) {
-    GREENTEA_SETUP_UUID(120, "udp_echo", uuid, GREENTEA_UUID_LENGTH);
-    return verbose_test_setup_handler(number_of_cases);
-}
-
-Case cases[] = {
-    Case("UDP echo parallel", test_udp_echo_parallel),
-};
-
-Specification specification(test_setup, cases);
-
-int main() {
-    return !Harness::run(specification);
-}
diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_Freescale/hardware_init_MK64F12.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_Freescale/TARGET_K64F/hardware_init_MK64F12.c
similarity index 100%
rename from features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_Freescale/hardware_init_MK64F12.c
rename to features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_Freescale/TARGET_K64F/hardware_init_MK64F12.c
diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_Freescale/hardware_init_MK66F18.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_Freescale/TARGET_K66F/hardware_init_MK66F18.c
similarity index 98%
rename from features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_Freescale/hardware_init_MK66F18.c
rename to features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_Freescale/TARGET_K66F/hardware_init_MK66F18.c
index 6ff6dc2614a..222a3173ee3 100644
--- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_Freescale/hardware_init_MK66F18.c
+++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_Freescale/TARGET_K66F/hardware_init_MK66F18.c
@@ -39,7 +39,7 @@ void k66f_init_eth_hardware(void)
 
 #ifndef FEATURE_UVISOR
     /* Disable MPU only when uVisor is not around. */
-    MPU->CESR &= ~MPU_CESR_VLD_MASK;
+    SYSMPU->CESR &= ~SYSMPU_CESR_VLD_MASK;
 #endif/*FEATURE_UVISOR*/
 
     /* Ungate the port clock */
diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_M480/m480_eth.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_M480/m480_eth.c
index 32918059f61..2e747a60ef5 100644
--- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_M480/m480_eth.c
+++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_M480/m480_eth.c
@@ -215,10 +215,15 @@ static void __eth_clk_pin_init()
     /* Init I/O Multi-function                                                                                 */
     /*---------------------------------------------------------------------------------------------------------*/
     // Configure RMII pins
-    SYS->GPA_MFPL = SYS_GPA_MFPL_PA6MFP_EMAC_RMII_RXERR | SYS_GPA_MFPL_PA7MFP_EMAC_RMII_CRSDV;
-    SYS->GPC_MFPL = SYS_GPC_MFPL_PC6MFP_EMAC_RMII_RXD1 | SYS_GPC_MFPL_PC7MFP_EMAC_RMII_RXD0;
-    SYS->GPC_MFPH = SYS_GPC_MFPH_PC8MFP_EMAC_RMII_REFCLK;
-    SYS->GPE_MFPH = SYS_GPE_MFPH_PE8MFP_EMAC_RMII_MDC |
+    SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA6MFP_Msk | SYS_GPA_MFPL_PA7MFP_Msk);
+    SYS->GPA_MFPL |= SYS_GPA_MFPL_PA6MFP_EMAC_RMII_RXERR | SYS_GPA_MFPL_PA7MFP_EMAC_RMII_CRSDV;
+    SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC6MFP_Msk | SYS_GPC_MFPL_PC7MFP_Msk);
+    SYS->GPC_MFPL |= SYS_GPC_MFPL_PC6MFP_EMAC_RMII_RXD1 | SYS_GPC_MFPL_PC7MFP_EMAC_RMII_RXD0;
+    SYS->GPC_MFPH &= ~SYS_GPC_MFPH_PC8MFP_Msk;
+    SYS->GPC_MFPH |= SYS_GPC_MFPH_PC8MFP_EMAC_RMII_REFCLK;
+    SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE8MFP_Msk | SYS_GPE_MFPH_PE9MFP_Msk | SYS_GPE_MFPH_PE10MFP_Msk |
+                       SYS_GPE_MFPH_PE11MFP_Msk | SYS_GPE_MFPH_PE12MFP_Msk);
+    SYS->GPE_MFPH |= SYS_GPE_MFPH_PE8MFP_EMAC_RMII_MDC |
                     SYS_GPE_MFPH_PE9MFP_EMAC_RMII_MDIO |
                     SYS_GPE_MFPH_PE10MFP_EMAC_RMII_TXD0 |
                     SYS_GPE_MFPH_PE11MFP_EMAC_RMII_TXD1 |
diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_eth.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_eth.c
index 1101f5b1e50..6c22b03bb57 100644
--- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_eth.c
+++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_eth.c
@@ -207,6 +207,9 @@ static void __eth_clk_pin_init()
     /* Init I/O Multi-function                                                                                 */
     /*---------------------------------------------------------------------------------------------------------*/
     // Configure RMII pins
+    SYS->GPC_MFPL &= ~( SYS_GPC_MFPL_PC0MFP_Msk | SYS_GPC_MFPL_PC1MFP_Msk |
+                    SYS_GPC_MFPL_PC2MFP_Msk | SYS_GPC_MFPL_PC3MFP_Msk |
+                    SYS_GPC_MFPL_PC4MFP_Msk | SYS_GPC_MFPL_PC6MFP_Msk | SYS_GPC_MFPL_PC7MFP_Msk ); 
     SYS->GPC_MFPL |= SYS_GPC_MFPL_PC0MFP_EMAC_REFCLK |
                     SYS_GPC_MFPL_PC1MFP_EMAC_MII_RXERR |
                     SYS_GPC_MFPL_PC2MFP_EMAC_MII_RXDV |
@@ -215,12 +218,13 @@ static void __eth_clk_pin_init()
                     SYS_GPC_MFPL_PC6MFP_EMAC_MII_TXD0 |
                     SYS_GPC_MFPL_PC7MFP_EMAC_MII_TXD1;
 
-
+    SYS->GPC_MFPH &= ~SYS_GPC_MFPH_PC8MFP_Msk;
     SYS->GPC_MFPH |= SYS_GPC_MFPH_PC8MFP_EMAC_MII_TXEN;
     // Enable high slew rate on all RMII pins
     PC->SLEWCTL |= 0x1DF;
 
     // Configure MDC, MDIO at PB14 & PB15
+    SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB14MFP_Msk | SYS_GPB_MFPH_PB15MFP_Msk);
     SYS->GPB_MFPH |= SYS_GPB_MFPH_PB14MFP_EMAC_MII_MDC | SYS_GPB_MFPH_PB15MFP_EMAC_MII_MDIO;
 
 }
diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/lpc17_emac.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/lpc17_emac.c
index a9aef9a524c..5b3b326435a 100644
--- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/lpc17_emac.c
+++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/lpc17_emac.c
@@ -63,6 +63,12 @@
  * @{
  */
 
+#if defined(TARGET_LPC1768) || defined(TARGET_LPC1769)
+/** \brief Group LPC17xx processors into one definition
+ */
+#define TARGET_LPC17XX
+#endif
+
 #if NO_SYS == 0
 /** \brief  Driver transmit and receive thread priorities
  *
@@ -146,8 +152,8 @@ struct lpc_enetdata {
 #  else
 #     define ETHMEM_SECTION __attribute__((section("AHBSRAM1"),aligned))
 #  endif
-#elif defined(TARGET_LPC1768)
-#  if defined(TOOLCHAIN_GCC_ARM)
+#elif defined(TARGET_LPC17XX)
+#  if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_ARM)
 #     define ETHMEM_SECTION __attribute__((section("AHBSRAM1"),aligned))
 #  endif
 #endif
@@ -370,7 +376,7 @@ static struct pbuf *lpc_low_level_input(struct netif *netif)
     			LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
                     ("lpc_low_level_input: Packet index %"U32_F" dropped for OOM\n",
     				idx));
-			
+
 #ifdef LOCK_RX_THREAD
 #if NO_SYS == 0
         		sys_mutex_unlock(&lpc_enetif->TXLockMutex);
@@ -428,7 +434,7 @@ void lpc_enetif_input(struct netif *netif)
  */
 static s32_t lpc_packet_addr_notsafe(void *addr) {
 	/* Check for legal address ranges */
-#if defined(TARGET_LPC1768)
+#if defined(TARGET_LPC17XX)
 	if ((((u32_t) addr >= 0x2007C000) && ((u32_t) addr < 0x20083FFF))) {
 #elif defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
 	if ((((u32_t) addr >= 0x20000000) && ((u32_t) addr < 0x20007FFF))) {
@@ -790,7 +796,7 @@ static err_t low_level_init(struct netif *netif)
 	/* Enable MII clocking */
 	LPC_SC->PCONP |= CLKPWR_PCONP_PCENET;
 
-#if defined(TARGET_LPC1768)
+#if defined(TARGET_LPC17XX)
 	LPC_PINCON->PINSEL2 = 0x50150105;                  /* Enable P1 Ethernet Pins. */
 	LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
 #elif defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MBED_CONNECT_ODIN/stm32f4_eth_conf.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MBED_CONNECT_ODIN/stm32f4_eth_conf.c
new file mode 100644
index 00000000000..56f754a4f4c
--- /dev/null
+++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MBED_CONNECT_ODIN/stm32f4_eth_conf.c
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "stm32f4xx_hal.h"
+
+void _eth_config_mac(ETH_HandleTypeDef *heth)
+{
+    ETH_MACInitTypeDef macconf =
+    {
+        .Watchdog = ETH_WATCHDOG_ENABLE,
+        .Jabber = ETH_JABBER_ENABLE,
+        .InterFrameGap = ETH_INTERFRAMEGAP_96BIT,
+        .CarrierSense = ETH_CARRIERSENCE_ENABLE,
+        .ReceiveOwn = ETH_RECEIVEOWN_ENABLE,
+        .LoopbackMode = ETH_LOOPBACKMODE_DISABLE,
+        .ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE,
+        .RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE,
+        .AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE,
+        .BackOffLimit = ETH_BACKOFFLIMIT_10,
+        .DeferralCheck = ETH_DEFFERRALCHECK_DISABLE,
+        .ReceiveAll = ETH_RECEIVEAll_DISABLE,
+        .SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE,
+        .PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL,
+        .BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE,
+        .DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL,
+        .PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE,
+        .MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_NONE, // Disable multicast filter
+        .UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT,
+        .HashTableHigh = 0x0U,
+        .HashTableLow = 0x0U,
+        .PauseTime = 0x0U,
+        .ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE,
+        .PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4,
+        .UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE,
+        .ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE,
+        .TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE,
+        .VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT,
+        .VLANTagIdentifier = 0x0U
+    };
+
+    if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) {
+        macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
+    } else {
+        macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
+    }
+
+    (void) HAL_ETH_ConfigMAC(heth, &macconf);
+}
diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MBED_CONNECT_ODIN/stm32f4_eth_init.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MBED_CONNECT_ODIN/stm32f4_eth_init.c
new file mode 100644
index 00000000000..f9ee0771e7a
--- /dev/null
+++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MBED_CONNECT_ODIN/stm32f4_eth_init.c
@@ -0,0 +1,143 @@
+#include <string.h>
+#include "stm32f4xx_hal.h"
+#include "mbed_toolchain.h"
+
+#define C029_OTP_START_ADDRESS           (0x1FFF7800U)
+#define C029_OTP_END_ADDRESS             (C029_OTP_START_ADDRESS + (16*32))
+#define C029_MAC_ETHERNET_ID             (3)
+
+typedef MBED_PACKED(struct) C029_OTP_Header {
+    uint8_t id;
+    uint8_t len;
+    uint8_t data[];
+} C029_OTP_Header;
+
+static int _macRetrieved = 0;
+static char _macAddr[6] = { 0x02, 0x02, 0xF7, 0xF0, 0x00, 0x00 };
+
+static C029_OTP_Header *increment(C029_OTP_Header *pTemp)
+{
+    uint8_t len = 0;
+    uint8_t id = 0;
+    uint8_t *p = (uint8_t*)pTemp;
+
+    memcpy((void*)&id, (void*)pTemp, 1);
+
+    if (id == 0xFF){
+        p++;
+    } else {
+        p++;
+        memcpy((void*)&len, (void*)p++, 1);
+        p += len;
+    }
+    return (C029_OTP_Header*)p;
+}
+
+/**
+ * Override HAL Eth Init function
+ */
+void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
+{
+    GPIO_InitTypeDef GPIO_InitStructure;
+    if (heth->Instance == ETH) {
+
+        /* Enable GPIOs clocks */
+        __HAL_RCC_GPIOA_CLK_ENABLE();
+        __HAL_RCC_GPIOB_CLK_ENABLE();
+        __HAL_RCC_GPIOC_CLK_ENABLE();
+
+        /** ETH GPIO Configuration
+          RMII_REF_CLK ----------------------> PA1
+          RMII_MDIO -------------------------> PA2
+          RMII_MDC --------------------------> PC1
+          RMII_MII_CRS_DV -------------------> PA7
+          RMII_MII_RXD0 ---------------------> PC4
+          RMII_MII_RXD1 ---------------------> PC5
+          RMII_MII_RXER ---------------------> PG2
+          RMII_MII_TX_EN --------------------> PB11
+          RMII_MII_TXD0 ---------------------> PB12
+          RMII_MII_TXD1 ---------------------> PB13
+         */
+        /* Configure PA1, PA2 and PA7 */
+        GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
+        GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
+        GPIO_InitStructure.Pull = GPIO_PULLUP;
+        GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_7;
+        GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
+        HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+        GPIO_InitStructure.Pull = GPIO_NOPULL;
+        GPIO_InitStructure.Pin = GPIO_PIN_1;
+        HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+        /* Configure PB13 */
+        GPIO_InitStructure.Pin = GPIO_PIN_13 | GPIO_PIN_11 | GPIO_PIN_12;
+        HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+        /* Configure PC1, PC4 and PC5 */
+        GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
+        HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+        /* Enable the Ethernet global Interrupt */
+        HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
+        HAL_NVIC_EnableIRQ(ETH_IRQn);
+
+        /* Enable ETHERNET clock  */
+        __HAL_RCC_ETH_CLK_ENABLE();
+    }
+}
+
+/**
+ * Override HAL Eth DeInit function
+ */
+void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
+{
+    if (heth->Instance == ETH) {
+        /* Peripheral clock disable */
+        __HAL_RCC_ETH_CLK_DISABLE();
+
+        /** ETH GPIO Configuration
+          RMII_REF_CLK ----------------------> PA1
+          RMII_MDIO -------------------------> PA2
+          RMII_MDC --------------------------> PC1
+          RMII_MII_CRS_DV -------------------> PA7
+          RMII_MII_RXD0 ---------------------> PC4
+          RMII_MII_RXD1 ---------------------> PC5
+          RMII_MII_RXER ---------------------> PG2
+          RMII_MII_TX_EN --------------------> PB11
+          RMII_MII_TXD0 ---------------------> PB12
+          RMII_MII_TXD1 ---------------------> PB13
+         */
+        HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
+        HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13 | GPIO_PIN_11 | GPIO_PIN_12);
+        HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
+
+        /* Disable the Ethernet global Interrupt */
+        NVIC_DisableIRQ(ETH_IRQn);
+    }
+}
+
+uint8_t mbed_otp_mac_address(char *mac)
+{
+    C029_OTP_Header *pFound = NULL;
+    C029_OTP_Header *pTemp = (C029_OTP_Header*)C029_OTP_START_ADDRESS;
+    C029_OTP_Header temp;
+
+    if (_macRetrieved == 0) {
+        while ((pTemp >= (C029_OTP_Header*)C029_OTP_START_ADDRESS) && (pTemp < (C029_OTP_Header*)C029_OTP_END_ADDRESS)){
+            memcpy((void*)&temp, (void*)pTemp, sizeof(temp));
+            if (temp.id == C029_MAC_ETHERNET_ID){
+                pFound = pTemp;
+                break;
+            }
+            pTemp = increment(pTemp);
+        }
+        if (pFound != NULL) {
+            memcpy(_macAddr, pFound->data, 6);
+            _macRetrieved = 1;
+        }
+    }
+    memcpy(mac, _macAddr, 6);
+
+    return 1;
+}
diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_conf.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_conf.c
index 7325f42caf3..56f754a4f4c 100644
--- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_conf.c
+++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_conf.c
@@ -19,7 +19,7 @@
 void _eth_config_mac(ETH_HandleTypeDef *heth)
 {
     ETH_MACInitTypeDef macconf =
-        {
+    {
         .Watchdog = ETH_WATCHDOG_ENABLE,
         .Jabber = ETH_JABBER_ENABLE,
         .InterFrameGap = ETH_INTERFRAMEGAP_96BIT,
@@ -48,8 +48,8 @@ void _eth_config_mac(ETH_HandleTypeDef *heth)
         .ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE,
         .TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE,
         .VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT,
-        .VLANTagIdentifier = 0x0U,
-        };
+        .VLANTagIdentifier = 0x0U
+    };
 
     if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) {
         macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_init.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_init.c
index 89fd896139d..f9ee0771e7a 100644
--- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_init.c
+++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_init.c
@@ -25,8 +25,7 @@ static C029_OTP_Header *increment(C029_OTP_Header *pTemp)
 
     if (id == 0xFF){
         p++;
-    }
-    else {
+    } else {
         p++;
         memcpy((void*)&len, (void*)p++, 1);
         p += len;
@@ -59,31 +58,30 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
           RMII_MII_TXD0 ---------------------> PB12
           RMII_MII_TXD1 ---------------------> PB13
          */
-        /* Configure PA1, PA2 and PA7 */       
+        /* Configure PA1, PA2 and PA7 */
         GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
         GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
         GPIO_InitStructure.Pull = GPIO_PULLUP;
         GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_7;
         GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
         HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
-        
+
         GPIO_InitStructure.Pull = GPIO_NOPULL;
         GPIO_InitStructure.Pin = GPIO_PIN_1;
         HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
 
         /* Configure PB13 */
-	    GPIO_InitStructure.Pin = GPIO_PIN_13 | GPIO_PIN_11 | GPIO_PIN_12;
+        GPIO_InitStructure.Pin = GPIO_PIN_13 | GPIO_PIN_11 | GPIO_PIN_12;
         HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
 
         /* Configure PC1, PC4 and PC5 */
         GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
-	    HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
-
+        HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
 
         /* Enable the Ethernet global Interrupt */
         HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
         HAL_NVIC_EnableIRQ(ETH_IRQn);
-        
+
         /* Enable ETHERNET clock  */
         __HAL_RCC_ETH_CLK_ENABLE();
     }
diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/stm32xx_emac.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/stm32xx_emac.c
index 5d3319e446c..134cea811d8 100644
--- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/stm32xx_emac.c
+++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/stm32xx_emac.c
@@ -46,6 +46,10 @@ static sys_mutex_t tx_lock_mutex;
 /* function */
 static void _eth_arch_rx_task(void *arg);
 static void _eth_arch_phy_task(void *arg);
+#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx)\
+    || defined (STM32F779xx)
+static void _rmii_watchdog(void *arg);
+#endif
 
 #if LWIP_IPV4
 static err_t _eth_arch_netif_output_ipv4(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr);
@@ -95,9 +99,6 @@ void ETH_IRQHandler(void)
  */
 static void _eth_arch_low_level_init(struct netif *netif)
 {
-    uint32_t regvalue = 0;
-    HAL_StatusTypeDef hal_eth_init_status;
-
     /* Init ETH */
     uint8_t MACAddr[6];
     EthHandle.Instance = ETH;
@@ -119,7 +120,7 @@ static void _eth_arch_low_level_init(struct netif *netif)
     EthHandle.Init.RxMode = ETH_RXINTERRUPT_MODE;
     EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
     EthHandle.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
-    hal_eth_init_status = HAL_ETH_Init(&EthHandle);
+    HAL_ETH_Init(&EthHandle);
 
     /* Initialize Tx Descriptors list: Chain Mode */
     HAL_ETH_DMATxDescListInit(&EthHandle, DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
@@ -375,6 +376,36 @@ static void _eth_arch_phy_task(void *arg)
     }
 }
 
+#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx)\
+    || defined (STM32F779xx)
+/**
+ * workaround for the ETH RMII bug in STM32F76x and STM32F77x revA
+ *
+ * \param[in] netif the lwip network interface structure
+ */
+static void _rmii_watchdog(void *arg)
+{
+    while(1) {
+        /* some good packets are received */
+        if (EthHandle.Instance->MMCRGUFCR > 0) {
+            /* RMII Init is OK - would need service to terminate or suspend
+             * the thread */
+            while(1) {
+                /*  don't do anything anymore */
+                osDelay(0xFFFFFFFF);
+            }
+        } else if (EthHandle.Instance->MMCRFCECR > 10) {
+            /* ETH received too many packets with CRC errors, resetting RMII */
+            SYSCFG->PMC &= ~SYSCFG_PMC_MII_RMII_SEL;
+            SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL;
+            EthHandle.Instance->MMCCR |= ETH_MMCCR_CR;
+        } else {
+            osDelay(100);
+        }
+    }
+}
+#endif
+
 /**
  * This function is the ethernet IPv4 packet send function. It calls
  * etharp_output after checking link status.
@@ -468,6 +499,11 @@ err_t eth_arch_enetif_init(struct netif *netif)
     /* initialize the hardware */
     _eth_arch_low_level_init(netif);
 
+#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx)\
+    || defined (STM32F779xx)
+    sys_thread_new("stm32_rmii_watchdog", _rmii_watchdog, netif, DEFAULT_THREAD_STACKSIZE, osPriorityLow);
+#endif
+
     return ERR_OK;
 }
 
diff --git a/features/FEATURE_LWIP/lwip-interface/lwip/src/core/lwip_tcp.c b/features/FEATURE_LWIP/lwip-interface/lwip/src/core/lwip_tcp.c
index ec2e1f92cef..17b681e5901 100644
--- a/features/FEATURE_LWIP/lwip-interface/lwip/src/core/lwip_tcp.c
+++ b/features/FEATURE_LWIP/lwip-interface/lwip/src/core/lwip_tcp.c
@@ -358,7 +358,6 @@ tcp_close_shutdown_fin(struct tcp_pcb *pcb)
   default:
     /* Has already been closed, do nothing. */
     return ERR_OK;
-    break;
   }
 
   if (err == ERR_OK) {
diff --git a/features/FEATURE_LWIP/lwip-interface/lwip_stack.c b/features/FEATURE_LWIP/lwip-interface/lwip_stack.c
index 8175a7c62ac..513c3830e55 100644
--- a/features/FEATURE_LWIP/lwip-interface/lwip_stack.c
+++ b/features/FEATURE_LWIP/lwip-interface/lwip_stack.c
@@ -293,7 +293,9 @@ static int get_ip_addr_type(const ip_addr_t *ip_addr)
         return IPADDR_TYPE_V4;
     }
 #endif
+#if LWIP_IPV6 && LWIP_IPV4
     return IPADDR_TYPE_ANY;
+#endif
 }
 
 void add_dns_addr(struct netif *lwip_netif)
@@ -658,7 +660,7 @@ nsapi_error_t mbed_lwip_bringup_2(bool dhcp, bool ppp, const char *ip, const cha
     if (!netif_is_link_up(&lwip_netif)) {
         if (sys_arch_sem_wait(&lwip_netif_linked, 15000) == SYS_ARCH_TIMEOUT) {
             if (ppp) {
-                ppp_lwip_disconnect();
+                (void) ppp_lwip_disconnect();
             }
             return NSAPI_ERROR_NO_CONNECTION;
         }
@@ -686,7 +688,7 @@ nsapi_error_t mbed_lwip_bringup_2(bool dhcp, bool ppp, const char *ip, const cha
     if (!mbed_lwip_get_ip_addr(true, &lwip_netif)) {
         if (sys_arch_sem_wait(&lwip_netif_has_any_addr, DHCP_TIMEOUT * 1000) == SYS_ARCH_TIMEOUT) {
             if (ppp) {
-                ppp_lwip_disconnect();
+                (void) ppp_lwip_disconnect();
             }
             return NSAPI_ERROR_DHCP_FAILURE;
         }
@@ -790,6 +792,7 @@ static nsapi_error_t mbed_lwip_err_remap(err_t err) {
         case ERR_CLSD:
             return 0;
         case ERR_MEM:
+        case ERR_BUF:
             return NSAPI_ERROR_NO_MEMORY;
         case ERR_CONN:
         case ERR_RST:
diff --git a/features/FEATURE_LWIP/lwip-interface/lwipopts.h b/features/FEATURE_LWIP/lwip-interface/lwipopts.h
index 0b422627c9f..608cc994e78 100644
--- a/features/FEATURE_LWIP/lwip-interface/lwipopts.h
+++ b/features/FEATURE_LWIP/lwip-interface/lwipopts.h
@@ -137,10 +137,25 @@
 #define LWIP_RAM_HEAP_POINTER       lwip_ram_heap
 
 // Number of pool pbufs.
-// Each requires 684 bytes of RAM.
+// Each requires 684 bytes of RAM (if MSS=536 and PBUF_POOL_BUFSIZE defaulting to be based on MSS)
+#ifdef MBED_CONF_LWIP_PBUF_POOL_SIZE
+#undef PBUF_POOL_SIZE
+#define PBUF_POOL_SIZE              MBED_CONF_LWIP_PBUF_POOL_SIZE
+#else
 #ifndef PBUF_POOL_SIZE
 #define PBUF_POOL_SIZE              5
 #endif
+#endif
+
+#ifdef MBED_CONF_LWIP_PBUF_POOL_BUFSIZE
+#undef PBUF_POOL_BUFSIZE
+#define PBUF_POOL_BUFSIZE           MBED_CONF_LWIP_PBUF_POOL_BUFSIZE
+#endif
+
+#ifdef MBED_CONF_LWIP_MEM_SIZE
+#undef MEM_SIZE
+#define MEM_SIZE                    MBED_CONF_LWIP_MEM_SIZE
+#endif
 
 // One tcp_pcb_listen is needed for each TCPServer.
 // Each requires 72 bytes of RAM.
diff --git a/features/FEATURE_LWIP/lwip-interface/mbed_lib.json b/features/FEATURE_LWIP/lwip-interface/mbed_lib.json
index ef77cf81069..6d9def2aa17 100644
--- a/features/FEATURE_LWIP/lwip-interface/mbed_lib.json
+++ b/features/FEATURE_LWIP/lwip-interface/mbed_lib.json
@@ -72,6 +72,18 @@
             "help": "Maximum number of open UDPSocket instances allowed, including one used internally for DNS.  Each requires 84 bytes of pre-allocated RAM",
             "value": 4
         },
+        "pbuf-pool-size": {
+            "help": "Number of pbufs in pool - usually used for received packets, so this determines how much data can be buffered between reception and the application reading. If a driver uses PBUF_RAM for reception, less pool may be needed. Current default (used if null here) is set to 5 in lwipopts.h, unless overridden by target Ethernet drivers.",
+            "value": null
+        },
+        "pbuf-pool-bufsize": {
+            "help": "Size of pbufs in pool. If set to null, lwIP will base the size on the TCP MSS, which is 536 unless overridden by the target",
+            "value": null
+        },
+        "mem-size": {
+            "help": "Size of heap (bytes) - used for outgoing packets, and also used by some drivers for reception. Current default (used if null here) is set to 1600 in opt.h, unless overridden by target Ethernet drivers.",
+            "value": null
+        },
         "tcpip-thread-stacksize": {
             "help": "Stack size for lwip TCPIP thread",
             "value": 1200
@@ -84,5 +96,10 @@
             "help": "Thread stack size for PPP",
             "value": 768
         }
+    },
+    "target_overrides": {
+        "REALTEK_RTL8195AM": {
+            "tcpip-thread-stacksize": 1600
+        }
     }
 }
diff --git a/features/FEATURE_UVISOR/AUTHORS.txt b/features/FEATURE_UVISOR/AUTHORS.txt
index b736cbbd739..e4a33f3291b 100644
--- a/features/FEATURE_UVISOR/AUTHORS.txt
+++ b/features/FEATURE_UVISOR/AUTHORS.txt
@@ -1,25 +1,26 @@
    600	Alessandro Angelino
    592	Milosch Meriac
-   190	Jaeden Amero
+   213	Jaeden Amero
     89	Niklas Hauser
-    10	Fangyi Zhou
-     6	Michael Schwarcz
-     5	Irit Arkin
-     5	Alexander Zilberkant
-     4	Amir Cohen
-     3	Hugo Vincent
+    27	Fangyi Zhou
+    14	Michael Schwarcz
+     8	Alexander Zilberkant
+     7	Irit Arkin
+     6	Amir Cohen
+     6	Roman Kuznetsov
+     4	Amanda Butler
+     4	Oren Cohen
      3	AnotherButler
-     3	Roman Kuznetsov
+     3	Danny Shavit
+     3	Hugo Vincent
+     3	Jan Jongboom
      3	JaredCJR
      3	Jim Huang
-     2	tonyyanxuan
-     2	Amanda Butler
-     2	Jan Jongboom
+     2	Jethro Hsu
      2	Nathan Chong
-     2	Oren Cohen
      2	Vincenzo Frascino
      2	ccli8
-     1	Russ Butler
-     1	Jethro Hsu
+     2	tonyyanxuan
      1	Aksel Skauge Mellbye
-     1	Danny Shavit
+     1	Michael Bartling
+     1	Russ Butler
diff --git a/features/FEATURE_UVISOR/README.md b/features/FEATURE_UVISOR/README.md
index d4531ba5b94..f458f244be6 100644
--- a/features/FEATURE_UVISOR/README.md
+++ b/features/FEATURE_UVISOR/README.md
@@ -248,7 +248,7 @@ static void private_button_on_press(void)
         for (int i = 0; i < PRIVATE_BUTTON_BUFFER_COUNT; ++i) {
             uvisor_ctx->pc->printf("%lu ", uvisor_ctx->buffer[i]);
         }
-        uvisor_ctx->pc->printf("\r\n");
+        uvisor_ctx->pc->printf("\n");
     }
 
 }
@@ -265,7 +265,7 @@ static void private_button_main_thread(const void *)
     /* Create the buffer and cache its pointer to the private static memory. */
     uvisor_ctx->buffer = (uint32_t *) malloc(PRIVATE_BUTTON_BUFFER_COUNT * sizeof(uint32_t));
     if (uvisor_ctx->buffer == NULL) {
-        uvisor_ctx->pc->printf("ERROR: Failed to allocate memory for the button buffer\r\n");
+        uvisor_ctx->pc->printf("ERROR: Failed to allocate memory for the button buffer\n");
         mbed_die();
     }
     uvisor_ctx->index = 0;
@@ -408,7 +408,7 @@ int main(void)
 {
     while (true) {
         led = !led;
-        printf("Secure index is %d\r\n", secure_get_index());
+        printf("Secure index is %d\n", secure_get_index());
         Thread::wait(500);
     }
 }
@@ -482,5 +482,6 @@ Repeat the process multiple times until all ACLs have been added to the list. Wh
 
 - [uVisor API documentation](API.md).
 - [Debugging uVisor on mbed OS](DEBUGGING.md).
+- [Using nonvolatile storage from uVisor on mbed OS](manual/Flash.md).
 
 If you found any bug or inconsistency in this guide, please [raise an issue](https://github.com/ARMmbed/uvisor/issues/new).
diff --git a/features/FEATURE_UVISOR/VERSION.txt b/features/FEATURE_UVISOR/VERSION.txt
index 9388ecbd52f..7021025f318 100644
--- a/features/FEATURE_UVISOR/VERSION.txt
+++ b/features/FEATURE_UVISOR/VERSION.txt
@@ -1 +1 @@
-v0.30.0
+v0.31.0
diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/api.h b/features/FEATURE_UVISOR/includes/uvisor/api/inc/api.h
index de3b2644a24..46c29c3e255 100644
--- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/api.h
+++ b/features/FEATURE_UVISOR/includes/uvisor/api/inc/api.h
@@ -65,7 +65,6 @@ typedef struct {
     int (*box_namespace)(int box_id, char *box_namespace, size_t length);
     int (*box_id_for_namespace)(int * const box_id, const char * const box_namespace);
 
-    void (*debug_init)(const TUvisorDebugDriver * const driver);
     void (*error)(THaltUserError reason);
     void (*start)(void);
     void (*vmpu_mem_invalidate)(void);
@@ -74,8 +73,8 @@ typedef struct {
     int                (*pool_queue_init)(uvisor_pool_queue_t *, uvisor_pool_t *, void *, size_t, size_t);
     uvisor_pool_slot_t (*pool_allocate)(uvisor_pool_t *);
     uvisor_pool_slot_t (*pool_try_allocate)(uvisor_pool_t *);
-    void               (*pool_queue_enqueue)(uvisor_pool_queue_t *, uvisor_pool_slot_t);
-    int                (*pool_queue_try_enqueue)(uvisor_pool_queue_t *, uvisor_pool_slot_t);
+    uvisor_pool_slot_t (*pool_queue_enqueue)(uvisor_pool_queue_t *, uvisor_pool_slot_t);
+    uvisor_pool_slot_t (*pool_queue_try_enqueue)(uvisor_pool_queue_t *, uvisor_pool_slot_t);
     uvisor_pool_slot_t (*pool_free)(uvisor_pool_t *, uvisor_pool_slot_t);
     uvisor_pool_slot_t (*pool_try_free)(uvisor_pool_t *, uvisor_pool_slot_t);
     uvisor_pool_slot_t (*pool_queue_dequeue)(uvisor_pool_queue_t *, uvisor_pool_slot_t);
diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/box_config.h b/features/FEATURE_UVISOR/includes/uvisor/api/inc/box_config.h
index a75ba03cfc9..1f21d6554f3 100644
--- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/box_config.h
+++ b/features/FEATURE_UVISOR/includes/uvisor/api/inc/box_config.h
@@ -18,6 +18,7 @@
 #define __UVISOR_API_BOX_CONFIG_H__
 
 #include "api/inc/uvisor_exports.h"
+#include "api/inc/debug_exports.h"
 #include "api/inc/page_allocator_exports.h"
 #include "api/inc/rpc_exports.h"
 #include <stddef.h>
@@ -169,4 +170,22 @@ UVISOR_EXTERN void const * const public_box_cfg_ptr;
 
 #define __uvisor_ctx (((UvisorBoxIndex *) __uvisor_ps)->bss.address_of.context)
 
+
+/* Use this macro after calling the box configuration macro, in order to register your box as a debug box.
+ * It will create a valid debug driver struct with the halt_error_func parameter as its halt_error() function */
+#define UVISOR_DEBUG_DRIVER(box_name, halt_error_func) \
+        UVISOR_EXTERN TUvisorDebugDriver const __uvisor_debug_driver; \
+        TUvisorDebugDriver const __uvisor_debug_driver = { \
+            UVISOR_DEBUG_BOX_MAGIC, \
+            UVISOR_DEBUG_BOX_VERSION, \
+            &box_name ## _cfg, \
+            halt_error_func \
+        };
+
+/* Use this macro after calling the box configuration macro, in order to
+ * register the public box as a debug box. */
+#define UVISOR_PUBLIC_BOX_DEBUG_DRIVER(halt_error_func) \
+        UVISOR_DEBUG_DRIVER(public_box, halt_error_func)
+
+
 #endif /* __UVISOR_API_BOX_CONFIG_H__ */
diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/debug_exports.h b/features/FEATURE_UVISOR/includes/uvisor/api/inc/debug_exports.h
index a269ba32087..2c8fc3395e0 100644
--- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/debug_exports.h
+++ b/features/FEATURE_UVISOR/includes/uvisor/api/inc/debug_exports.h
@@ -19,12 +19,19 @@
 
 #include "api/inc/halt_exports.h"
 #include <stdint.h>
+#include "api/inc/vmpu_exports.h"
 
-/* Debug box driver -- Version 0
+
+#define UVISOR_DEBUG_BOX_VERSION    (1)
+
+
+/* Debug box driver
  * A constant instance of this struct must be instantiated by the unprivileged
  * code to setup a debug box.*/
 typedef struct TUvisorDebugDriver {
-    uint32_t (*get_version)(void);
+    const uint32_t magic;
+    const uint32_t version;
+    const UvisorBoxConfig * const box_cfg_ptr;
     void (*halt_error)(THaltError, const THaltInfo *);
 } TUvisorDebugDriver;
 
diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/halt_exports.h b/features/FEATURE_UVISOR/includes/uvisor/api/inc/halt_exports.h
index 5ea9d4f6742..ab173ea8efd 100644
--- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/halt_exports.h
+++ b/features/FEATURE_UVISOR/includes/uvisor/api/inc/halt_exports.h
@@ -17,6 +17,8 @@
 #ifndef __UVISOR_API_HALT_EXPORTS_H__
 #define __UVISOR_API_HALT_EXPORTS_H__
 
+#include "uvisor_exports.h"
+
 #define UVISOR_ERROR_INVALID_BOX_ID             (-2)
 #define UVISOR_ERROR_BUFFER_TOO_SMALL           (-3)
 #define UVISOR_ERROR_BOX_NAMESPACE_ANONYMOUS    (-4)
diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/ipc.h b/features/FEATURE_UVISOR/includes/uvisor/api/inc/ipc.h
index 19a737a2b50..4186df4c5a3 100644
--- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/ipc.h
+++ b/features/FEATURE_UVISOR/includes/uvisor/api/inc/ipc.h
@@ -51,10 +51,12 @@ UVISOR_EXTERN int ipc_waitforall(uint32_t wait_tokens, uint32_t * done_tokens, u
 
 /** Asynchronously send an IPC message
  *
- * @note The memory used for sending the message (pointed to by msg) must be
- * valid until after the send is complete.
+ * @note The memory used for receiving the message (pointed to by msg) and the
+ * IPC descriptor (pointed to by desc) must be valid until after the send is
+ * complete. In addition, each IPC message should use its own IPC descriptor.
+ * Reusing an IPC descriptor will lead to unpredictable behaviours.
  *
- * @param[in]  desc   an IPC descriptor for the message
+ * @param[inout]  desc   an IPC descriptor for the message
  * @param[in]  msg    the message to send
  *
  * @return     0 on success, non-zero error code otherwise
@@ -63,8 +65,10 @@ UVISOR_EXTERN int ipc_send(uvisor_ipc_desc_t * desc, const void * msg);
 
 /** Asynchronously receive an IPC message
  *
- * @note The memory used for receiving the message (pointed to by msg) must be
- * valid until after the receive is complete.
+ * @note The memory used for receiving the message (pointed to by msg) and the
+ * IPC descriptor (pointed to by desc) must be valid until after the receive is
+ * complete. In addition, each IPC message should use its own IPC descriptor.
+ * Reusing an IPC descriptor will lead to unpredictable behaviours.
  *
  * @param[inout] desc   an IPC descriptor for the message
  * @param[out]   msg    the memory to copy the message to
diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/magic_exports.h b/features/FEATURE_UVISOR/includes/uvisor/api/inc/magic_exports.h
index ff8bd38e558..7ebe8579e8d 100644
--- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/magic_exports.h
+++ b/features/FEATURE_UVISOR/includes/uvisor/api/inc/magic_exports.h
@@ -37,6 +37,7 @@
 #define UVISOR_RPC_GATEWAY_MAGIC_SYNC  UDF_OPCODE(0x07C3)
 #define UVISOR_POOL_MAGIC              UDF_OPCODE(0x07C4)
 #define UVISOR_POOL_QUEUE_MAGIC        UDF_OPCODE(0x07C5)
+#define UVISOR_DEBUG_BOX_MAGIC         UDF_OPCODE(0x07C6)
 #else
 #error "Unsupported instruction set. The ARM Thumb-2 instruction set must be supported."
 #endif /* __thumb__ && __thumb2__ */
diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/pool_queue_exports.h b/features/FEATURE_UVISOR/includes/uvisor/api/inc/pool_queue_exports.h
index 7175e81d1df..d9764fb3f3d 100644
--- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/pool_queue_exports.h
+++ b/features/FEATURE_UVISOR/includes/uvisor/api/inc/pool_queue_exports.h
@@ -19,7 +19,6 @@
 
 #include "api/inc/magic_exports.h"
 #include "api/inc/uvisor_exports.h"
-#include "api/inc/uvisor_semaphore_exports.h"
 #include "api/inc/uvisor_spinlock_exports.h"
 #include <stdint.h>
 #include <stddef.h>
@@ -115,8 +114,8 @@ UVISOR_EXTERN uvisor_pool_slot_t uvisor_pool_allocate(uvisor_pool_t * pool);
 UVISOR_EXTERN uvisor_pool_slot_t uvisor_pool_try_allocate(uvisor_pool_t * pool);
 
 /* Enqueue the specified slot into the queue. */
-UVISOR_EXTERN void uvisor_pool_queue_enqueue(uvisor_pool_queue_t * pool_queue, uvisor_pool_slot_t slot);
-UVISOR_EXTERN int uvisor_pool_queue_try_enqueue(uvisor_pool_queue_t * pool_queue, uvisor_pool_slot_t slot);
+UVISOR_EXTERN uvisor_pool_slot_t uvisor_pool_queue_enqueue(uvisor_pool_queue_t * pool_queue, uvisor_pool_slot_t slot);
+UVISOR_EXTERN uvisor_pool_slot_t uvisor_pool_queue_try_enqueue(uvisor_pool_queue_t * pool_queue, uvisor_pool_slot_t slot);
 
 /* Free the specified slot back into the pool. Invalid slots are ignored.
  * Return the slot that was freed, or UVISOR_POOL_SLOT_IS_FREE if the slot was
diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/uvisor-lib.h b/features/FEATURE_UVISOR/includes/uvisor/api/inc/uvisor-lib.h
index 4cfbd950549..ab42ba24700 100644
--- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/uvisor-lib.h
+++ b/features/FEATURE_UVISOR/includes/uvisor/api/inc/uvisor-lib.h
@@ -28,7 +28,6 @@
 #include "api/inc/api.h"
 #include "api/inc/box_config.h"
 #include "api/inc/box_id.h"
-#include "api/inc/debug.h"
 #include "api/inc/disabled.h"
 #include "api/inc/error.h"
 #include "api/inc/interrupts.h"
diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/uvisor_exports.h b/features/FEATURE_UVISOR/includes/uvisor/api/inc/uvisor_exports.h
index 996db28fde0..3723c4d0998 100644
--- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/uvisor_exports.h
+++ b/features/FEATURE_UVISOR/includes/uvisor/api/inc/uvisor_exports.h
@@ -133,6 +133,12 @@
 #define UVISOR_MACRO_REGS_RETVAL(type, name) \
     register type name asm("r0");
 
+UVISOR_FORCEINLINE void uvisor_noreturn(void)
+{
+    volatile int var = 1;
+    while(var);
+}
+
 /* declare callee-saved input/output operands for gcc-style inline asm */
 /* note: this macro requires that a C variable having the same name of the
  *       corresponding callee-saved register is declared; these operands follow
diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/vmpu_exports.h b/features/FEATURE_UVISOR/includes/uvisor/api/inc/vmpu_exports.h
index af94dd94fe5..a241c01a457 100644
--- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/vmpu_exports.h
+++ b/features/FEATURE_UVISOR/includes/uvisor/api/inc/vmpu_exports.h
@@ -18,7 +18,6 @@
 #define __UVISOR_API_VMPU_EXPORTS_H__
 
 #include "api/inc/uvisor_exports.h"
-#include "api/inc/pool_queue_exports.h"
 #include <stdint.h>
 
 /* The maximum box namespace length is 37 so that it is exactly big enough for
diff --git a/features/FEATURE_UVISOR/source/page_allocator.c_inc b/features/FEATURE_UVISOR/source/page_allocator.c_inc
index 7957567ed2d..e432710432c 100644
--- a/features/FEATURE_UVISOR/source/page_allocator.c_inc
+++ b/features/FEATURE_UVISOR/source/page_allocator.c_inc
@@ -138,7 +138,7 @@ void page_allocator_init(void * const heap_start, void * const heap_end, const u
     g_page_map_shift -= (g_page_head_end_rounded - (uint32_t) g_page_heap_end) / g_page_size;
 
     DPRINTF(
-        "page heap: [0x%08x, 0x%08x] %ukB -> %u %ukB pages\r\n",
+        "page heap: [0x%08x, 0x%08x] %ukB -> %u %ukB pages\n",
             (unsigned int) g_page_heap_start,
             (unsigned int) g_page_heap_end,
             (unsigned int) (g_page_count_free * g_page_size / 1024),
diff --git a/features/FEATURE_UVISOR/targets/TARGET_UVISOR_SUPPORTED/TARGET_ARM_BEETLE_SOC/TARGET_DEBUG/TARGET_M3/libconfiguration_beetle_cortex_m3_0x20000000_0x140.a b/features/FEATURE_UVISOR/targets/TARGET_UVISOR_SUPPORTED/TARGET_ARM_BEETLE_SOC/TARGET_DEBUG/TARGET_M3/libconfiguration_beetle_cortex_m3_0x20000000_0x140.a
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index 34d1acd830c..a2965f62298 100644
Binary files a/features/FEATURE_UVISOR/targets/TARGET_UVISOR_SUPPORTED/TARGET_STM32F4/TARGET_RELEASE/TARGET_M4/libconfiguration_stm32_cortex_m4_0x10000000_0x0.a and b/features/FEATURE_UVISOR/targets/TARGET_UVISOR_SUPPORTED/TARGET_STM32F4/TARGET_RELEASE/TARGET_M4/libconfiguration_stm32_cortex_m4_0x10000000_0x0.a differ
diff --git a/features/FEATURE_UVISOR/uvisor-tests.txt b/features/FEATURE_UVISOR/uvisor-tests.txt
index ed2bf8e0e43..241f957279e 100644
--- a/features/FEATURE_UVISOR/uvisor-tests.txt
+++ b/features/FEATURE_UVISOR/uvisor-tests.txt
@@ -1 +1 @@
-e3b1385c7facc7fdab472440293c4c87ed2b2999
+36664e60639dda2b364e6e8b5ecf9a23116d280a
diff --git a/features/filesystem/Dir.cpp b/features/filesystem/Dir.cpp
index 867105b96ae..17014e3bae5 100644
--- a/features/filesystem/Dir.cpp
+++ b/features/filesystem/Dir.cpp
@@ -43,8 +43,12 @@ int Dir::open(FileSystem *fs, const char *path)
         return -EINVAL;
     }
 
-    _fs = fs;
-    return _fs->dir_open(&_dir, path);
+    int err = fs->dir_open(&_dir, path);
+    if (!err) {
+        _fs = fs;
+    }
+
+    return err;
 }
 
 int Dir::close()
diff --git a/features/filesystem/FileSystem.cpp b/features/filesystem/FileSystem.cpp
index 4fea36f1a0a..b356b0a0378 100644
--- a/features/filesystem/FileSystem.cpp
+++ b/features/filesystem/FileSystem.cpp
@@ -15,6 +15,8 @@
  */
 
 #include "mbed.h"
+#include "filesystem/Dir.h"
+#include "filesystem/File.h"
 #include "filesystem/FileSystem.h"
 #include <errno.h>
 
diff --git a/features/filesystem/bd/BlockDevice.h b/features/filesystem/bd/BlockDevice.h
index a45dfee2985..da46c7b7278 100644
--- a/features/filesystem/bd/BlockDevice.h
+++ b/features/filesystem/bd/BlockDevice.h
@@ -91,7 +91,26 @@ class BlockDevice
      *  @param size     Size to erase in bytes, must be a multiple of erase block size
      *  @return         0 on success, negative error code on failure
      */
-    virtual int erase(bd_addr_t addr, bd_size_t size) = 0;
+    virtual int erase(bd_addr_t addr, bd_size_t size)
+    {
+        return 0;
+    }
+
+    /** Mark blocks as no longer in use
+     *
+     *  This function provides a hint to the underlying block device that a region of blocks
+     *  is no longer in use and may be erased without side effects. Erase must still be called
+     *  before programming, but trimming allows flash-translation-layers to schedule erases when
+     *  the device is not busy.
+     *
+     *  @param addr     Address of block to mark as unused
+     *  @param size     Size to mark as unused in bytes, must be a multiple of erase block size
+     *  @return         0 on success, negative error code on failure
+     */
+    virtual int trim(bd_addr_t addr, bd_size_t size)
+    {
+        return 0;
+    }
 
     /** Get the size of a readable block
      *
@@ -111,7 +130,10 @@ class BlockDevice
      *  @return         Size of a eraseable block in bytes
      *  @note Must be a multiple of the program size
      */
-    virtual bd_size_t get_erase_size() const = 0;
+    virtual bd_size_t get_erase_size() const
+    {
+        return get_program_size();
+    }
 
     /** Get the total size of the underlying device
      *
diff --git a/features/filesystem/bd/ChainingBlockDevice.cpp b/features/filesystem/bd/ChainingBlockDevice.cpp
index 9dcfbae562a..f9f5c9a29f9 100644
--- a/features/filesystem/bd/ChainingBlockDevice.cpp
+++ b/features/filesystem/bd/ChainingBlockDevice.cpp
@@ -109,7 +109,7 @@ int ChainingBlockDevice::read(void *b, bd_addr_t addr, bd_size_t size)
             size -= read;
         }
 
-        addr -= size;
+        addr -= bdsize;
     }
 
     return 0;
@@ -140,7 +140,7 @@ int ChainingBlockDevice::program(const void *b, bd_addr_t addr, bd_size_t size)
             size -= program;
         }
 
-        addr -= size;
+        addr -= bdsize;
     }
 
     return 0;
@@ -169,7 +169,7 @@ int ChainingBlockDevice::erase(bd_addr_t addr, bd_size_t size)
             size -= erase;
         }
 
-        addr -= size;
+        addr -= bdsize;
     }
 
     return 0;
diff --git a/features/filesystem/bd/HeapBlockDevice.h b/features/filesystem/bd/HeapBlockDevice.h
index 1844bdddf38..afdaeef7440 100644
--- a/features/filesystem/bd/HeapBlockDevice.h
+++ b/features/filesystem/bd/HeapBlockDevice.h
@@ -34,13 +34,16 @@
  * #include "mbed.h"
  * #include "HeapBlockDevice.h"
  *
- * HeapBlockDevice bd(2048, 512); // 2048 bytes with a block size of 512 bytes
- * uint8_t block[512] = "Hello World!\n";
+ * #define BLOCK_SIZE 512
+ *
+ * HeapBlockDevice bd(2048, BLOCK_SIZE); // 2048 bytes with a block size of 512 bytes
+ * uint8_t block[BLOCK_SIZE] = "Hello World!\n";
  *
  * int main() {
  *     bd.init();
- *     bd.program(block, 0);
- *     bd.read(block, 0);
+ *     bd.erase(0, BLOCK_SIZE);
+ *     bd.program(block, 0, BLOCK_SIZE);
+ *     bd.read(block, 0, BLOCK_SIZE);
  *     printf("%s", block);
  *     bd.deinit();
  * }
@@ -53,7 +56,8 @@ class HeapBlockDevice : public BlockDevice
     /** Lifetime of the memory block device
      *
      * @param size      Size of the Block Device in bytes
-     * @param block     Block size in bytes
+     * @param block     Block size in bytes. Minimum read, program, and erase sizes are
+     *                  configured to this value
      */
     HeapBlockDevice(bd_size_t size, bd_size_t block=512);
     /** Lifetime of the memory block device
diff --git a/features/filesystem/bd/ProfilingBlockDevice.h b/features/filesystem/bd/ProfilingBlockDevice.h
index 9bfa08d33c6..c019fa7300d 100644
--- a/features/filesystem/bd/ProfilingBlockDevice.h
+++ b/features/filesystem/bd/ProfilingBlockDevice.h
@@ -42,6 +42,7 @@
  *  printf("read count: %lld\n", profiler.get_read_count());
  *  printf("program count: %lld\n", profiler.get_program_count());
  *  printf("erase count: %lld\n", profiler.get_erase_count());
+ *  @endcode
  */
 class ProfilingBlockDevice : public BlockDevice
 {
diff --git a/features/filesystem/fat/ChaN/ffconf.h b/features/filesystem/fat/ChaN/ffconf.h
index 9d461c1e260..cab80cf21be 100644
--- a/features/filesystem/fat/ChaN/ffconf.h
+++ b/features/filesystem/fat/ChaN/ffconf.h
@@ -171,7 +171,7 @@
 /  disk_ioctl() function. */
 
 
-#define	_USE_TRIM	0
+#define	_USE_TRIM	1
 /* This option switches ATA-TRIM feature. (0:Disable or 1:Enable)
 /  To enable Trim feature, also CTRL_TRIM command should be implemented to the
 /  disk_ioctl() function. */
diff --git a/features/filesystem/fat/FATFileSystem.cpp b/features/filesystem/fat/FATFileSystem.cpp
index 20e981099e0..1829bbda8e4 100644
--- a/features/filesystem/fat/FATFileSystem.cpp
+++ b/features/filesystem/fat/FATFileSystem.cpp
@@ -244,6 +244,15 @@ DRESULT disk_ioctl(BYTE pdrv, BYTE cmd, void *buff)
         case GET_BLOCK_SIZE:
             *((DWORD*)buff) = 1; // default when not known
             return RES_OK;
+        case CTRL_TRIM:
+            if (_ffs[pdrv] == NULL) {
+                return RES_NOTRDY;
+            } else {
+                DWORD *sectors = (DWORD*)buff;
+                DWORD ssize = disk_get_sector_size(pdrv);
+                int err = _ffs[pdrv]->trim(sectors[0]*ssize, (sectors[1]-sectors[0]+1)*ssize);
+                return err ? RES_PARERR : RES_OK;
+            }
     }
 
     return RES_PARERR;
diff --git a/features/mbedtls/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/mbedtls_device.h b/features/mbedtls/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/mbedtls_device.h
new file mode 100644
index 00000000000..dfbc82055ef
--- /dev/null
+++ b/features/mbedtls/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/mbedtls_device.h
@@ -0,0 +1,31 @@
+/*
+ *  mbedtls_device.h
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ */
+#ifndef MBEDTLS_DEVICE_H
+#define MBEDTLS_DEVICE_H
+
+#define MBEDTLS_AES_ALT
+
+#define MBEDTLS_SHA256_ALT
+
+#define MBEDTLS_SHA1_ALT
+
+#define MBEDTLS_MD5_ALT
+
+#endif /* MBEDTLS_DEVICE_H */
diff --git a/features/mbedtls/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/mbedtls_device.h b/features/mbedtls/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/mbedtls_device.h
index 90213bea118..03ddf8f8ac8 100644
--- a/features/mbedtls/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/mbedtls_device.h
+++ b/features/mbedtls/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/mbedtls_device.h
@@ -20,14 +20,14 @@
 #ifndef MBEDTLS_DEVICE_H
 #define MBEDTLS_DEVICE_H
 
-/* FIXME: Don't enable AES hardware acceleration until issue #4928 is fixed.
- * (https://github.com/ARMmbed/mbed-os/issues/4928) */
-/* #define MBEDTLS_AES_ALT */
+#define MBEDTLS_AES_ALT
 
-#define MBEDTLS_SHA256_ALT
+/* FIXME: Don't enable SHA1, SHA256 and MD5 hardware acceleration until issue
+ * #5079 is fixed. (https://github.com/ARMmbed/mbed-os/issues/5079) */
+/* #define MBEDTLS_SHA256_ALT */
 
-#define MBEDTLS_SHA1_ALT
+/* #define MBEDTLS_SHA1_ALT */
 
-#define MBEDTLS_MD5_ALT
+/* #define MBEDTLS_MD5_ALT */
 
 #endif /* MBEDTLS_DEVICE_H */
diff --git a/features/mbedtls/targets/TARGET_STM/aes_alt.c b/features/mbedtls/targets/TARGET_STM/aes_alt.c
index 8736d7ee474..15e57eb095e 100644
--- a/features/mbedtls/targets/TARGET_STM/aes_alt.c
+++ b/features/mbedtls/targets/TARGET_STM/aes_alt.c
@@ -1,5 +1,5 @@
 /*
- *  Hardware aes collector for the STM32F4 family
+ *  Hardware aes implementation for STM32F4 STM32F7 and STM32L4 families
  *******************************************************************************
  * Copyright (c) 2017, STMicroelectronics
  *  SPDX-License-Identifier: Apache-2.0
@@ -129,15 +129,18 @@ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
 
     /* allow multi-instance of CRYP use: restore context for CRYP hw module */
     ctx->hcryp_aes.Instance->CR = ctx->ctx_save_cr;
+    ctx->hcryp_aes.Phase = HAL_CRYP_PHASE_READY;
+    ctx->hcryp_aes.Init.DataType = CRYP_DATATYPE_8B;
+    ctx->hcryp_aes.Init.pKey = ctx->aes_key;
 
     if(mode == MBEDTLS_AES_DECRYPT) { /* AES decryption */
-        ctx->hcryp_aes.Init.DataType = CRYP_DATATYPE_8B;
-        ctx->hcryp_aes.Init.pKey = ctx->aes_key;
-        mbedtls_aes_decrypt( ctx, input, output );
+        if (mbedtls_internal_aes_decrypt( ctx, input, output )){
+            return ST_ERR_AES_BUSY;
+        }
     } else { /* AES encryption */
-        ctx->hcryp_aes.Init.DataType = CRYP_DATATYPE_8B;
-        ctx->hcryp_aes.Init.pKey = ctx->aes_key;
-        mbedtls_aes_encrypt( ctx, input, output );
+        if (mbedtls_internal_aes_encrypt( ctx, input, output )) {
+            return ST_ERR_AES_BUSY;
+        }
     }
     /* allow multi-instance of CRYP use: save context for CRYP HW module CR */
     ctx->ctx_save_cr = ctx->hcryp_aes.Instance->CR;
@@ -147,29 +150,50 @@ int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
 
 #if defined(MBEDTLS_CIPHER_MODE_CBC)
 #if defined (TARGET_STM32L486xG)
+static int st_cbc_restore_context(mbedtls_aes_context *ctx){
+    uint32_t tickstart;
+    tickstart = HAL_GetTick();
+    while((ctx->hcryp_aes.Instance->SR & AES_SR_BUSY) != 0){
+        if ((HAL_GetTick() - tickstart) > ST_AES_TIMEOUT) {
+            return ST_ERR_AES_BUSY; // timeout: CRYP processor is busy
+        }
+    }
+    /* allow multi-instance of CRYP use: restore context for CRYP hw module */
+    ctx->hcryp_aes.Instance->CR = ctx->ctx_save_cr;
+    return 0;
+}
+
 static int st_hal_cryp_cbc( mbedtls_aes_context *ctx, uint32_t opmode, size_t length, 
                             unsigned char iv[16], uint8_t *input, uint8_t *output) 
 {
-    int status = 0;
     ctx->hcryp_aes.Init.pInitVect = &iv[0]; // used in process, not in the init
-    if ((ctx->hcryp_aes.Init.OperatingMode != opmode) || \
-         (ctx->hcryp_aes.Init.ChainingMode != CRYP_CHAINMODE_AES_CBC) || \
-         (ctx->hcryp_aes.Init.KeyWriteFlag != CRYP_KEY_WRITE_ENABLE)) {
-
-        /* Re-initialize AES IP with proper parameters */
-        if (HAL_CRYP_DeInit(&ctx->hcryp_aes) != HAL_OK)
-            return HAL_ERROR;
-        ctx->hcryp_aes.Init.OperatingMode = opmode;
-        ctx->hcryp_aes.Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
-        ctx->hcryp_aes.Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
-        if (HAL_CRYP_Init(&ctx->hcryp_aes) != HAL_OK)
-            return HAL_ERROR;
-    }
-
-    status =  HAL_CRYPEx_AES(&ctx->hcryp_aes, input, length, output, 10);
+    /* At this moment only, we know we have CBC mode: Re-initialize AES
+        IP with proper parameters and apply key and IV for multi context usecase */
+    if (HAL_CRYP_DeInit(&ctx->hcryp_aes) != HAL_OK)
+        return ST_ERR_AES_BUSY;
+    ctx->hcryp_aes.Init.OperatingMode = opmode;
+    ctx->hcryp_aes.Init.ChainingMode = CRYP_CHAINMODE_AES_CBC;
+    ctx->hcryp_aes.Init.KeyWriteFlag = CRYP_KEY_WRITE_ENABLE;
+    if (HAL_CRYP_Init(&ctx->hcryp_aes) != HAL_OK)
+        return ST_ERR_AES_BUSY;
 
-    return status;
+    if(HAL_CRYPEx_AES(&ctx->hcryp_aes, input, length, output, 10) != 0)
+        return ST_ERR_AES_BUSY;
+    return 0;
+}
+#else /* STM32F4 and STM32F7 */
+static int st_cbc_restore_context(mbedtls_aes_context *ctx){
+    /* allow multi-instance of CRYP use: restore context for CRYP hw module */
+    ctx->hcryp_aes.Instance->CR = ctx->ctx_save_cr;
+    /* Re-initialize AES processor with proper parameters
+       and (re-)apply key and IV for multi context usecases */
+    if (HAL_CRYP_DeInit(&ctx->hcryp_aes) != HAL_OK)
+        return ST_ERR_AES_BUSY;
+    if (HAL_CRYP_Init(&ctx->hcryp_aes) != HAL_OK)
+        return ST_ERR_AES_BUSY;
+    return 0;
 }
+
 #endif /* TARGET_STM32L486xG */
 
 int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
@@ -179,25 +203,66 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
                     const unsigned char *input,
                     unsigned char *output )
 {
-    int status = 0;
+    uint32_t tickstart;
+    uint32_t *iv_ptr = (uint32_t *)&iv[0];
     if( length % 16 )
         return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH );
+    ctx->hcryp_aes.Init.pInitVect = &iv[0];
+    if (st_cbc_restore_context(ctx) != 0)
+        return (ST_ERR_AES_BUSY);
+
 #if defined (TARGET_STM32L486xG)
+
     if( mode == MBEDTLS_AES_DECRYPT ) {
-        status = st_hal_cryp_cbc(ctx, CRYP_ALGOMODE_KEYDERIVATION_DECRYPT, length, iv, (uint8_t *)input, (uint8_t *)output);
+        if (st_hal_cryp_cbc(ctx, CRYP_ALGOMODE_KEYDERIVATION_DECRYPT, length, iv, (uint8_t *)input, (uint8_t *)output) != 0)
+            return ST_ERR_AES_BUSY;
+        /* Save the internal IV vector for multi context purpose */
+        tickstart = HAL_GetTick();
+        while((ctx->hcryp_aes.Instance->SR & AES_SR_BUSY) != 0){
+            if ((HAL_GetTick() - tickstart) > ST_AES_TIMEOUT) {
+                return ST_ERR_AES_BUSY; // timeout: CRYP processor is busy
+            }
+        }
+        ctx->ctx_save_cr = ctx->hcryp_aes.Instance->CR; // save here before overwritten
+        ctx->hcryp_aes.Instance->CR &= ~AES_CR_EN;
+        *iv_ptr++ = ctx->hcryp_aes.Instance->IVR3;
+        *iv_ptr++ = ctx->hcryp_aes.Instance->IVR2;
+        *iv_ptr++ = ctx->hcryp_aes.Instance->IVR1;
+        *iv_ptr++ = ctx->hcryp_aes.Instance->IVR0;
     } else {
-        status = st_hal_cryp_cbc(ctx, CRYP_ALGOMODE_ENCRYPT, length, iv, (uint8_t *)input, (uint8_t *)output);
+        if (st_hal_cryp_cbc(ctx, CRYP_ALGOMODE_ENCRYPT, length, iv, (uint8_t *)input, (uint8_t *)output) != 0)
+            return ST_ERR_AES_BUSY;
+        memcpy( iv, output, 16 ); /* current output is the IV vector for the next call */
+        ctx->ctx_save_cr = ctx->hcryp_aes.Instance->CR;
     }
+
 #else
-    ctx->hcryp_aes.Init.pInitVect = &iv[0];
-    
+
     if( mode == MBEDTLS_AES_DECRYPT ) {
-        status = HAL_CRYP_AESCBC_Decrypt(&ctx->hcryp_aes, (uint8_t *)input, length, (uint8_t *)output, 10);
+        if (HAL_CRYP_AESCBC_Decrypt(&ctx->hcryp_aes, (uint8_t *)input, length, (uint8_t *)output, 10) != HAL_OK)
+            return ST_ERR_AES_BUSY;
+        /* Save the internal IV vector for multi context purpose */
+        tickstart = HAL_GetTick();
+        while((ctx->hcryp_aes.Instance->SR & (CRYP_SR_IFEM | CRYP_SR_OFNE | CRYP_SR_BUSY)) != CRYP_SR_IFEM){
+            if ((HAL_GetTick() - tickstart) > ST_AES_TIMEOUT) {
+                return ST_ERR_AES_BUSY; // timeout: CRYP processor is busy
+            }
+        }
+        ctx->ctx_save_cr = ctx->hcryp_aes.Instance->CR; // save here before overwritten
+        ctx->hcryp_aes.Instance->CR &= ~CRYP_CR_CRYPEN;
+        *iv_ptr++ = ctx->hcryp_aes.Instance->IV0LR;
+        *iv_ptr++ = ctx->hcryp_aes.Instance->IV0RR;
+        *iv_ptr++ = ctx->hcryp_aes.Instance->IV1LR;
+        *iv_ptr++ = ctx->hcryp_aes.Instance->IV1RR;
     } else {
-        status = HAL_CRYP_AESCBC_Encrypt(&ctx->hcryp_aes, (uint8_t *)input, length, (uint8_t *)output, 10);
+        if (HAL_CRYP_AESCBC_Encrypt(&ctx->hcryp_aes, (uint8_t *)input, length, (uint8_t *)output, 10) != HAL_OK)
+            return ST_ERR_AES_BUSY;
+        memcpy( iv, output, 16 ); /* current output is the IV vector for the next call */
+        ctx->ctx_save_cr = ctx->hcryp_aes.Instance->CR;
     }
+
 #endif
-    return( status );
+    return 0;
 }
 #endif /* MBEDTLS_CIPHER_MODE_CBC */
 
@@ -216,7 +281,8 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
     if( mode == MBEDTLS_AES_DECRYPT ) {
         while( length-- ) {
             if( n == 0 )
-                mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
+                if (mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ) != 0)
+                    return ST_ERR_AES_BUSY;
 
             c = *input++;
             *output++ = (unsigned char)( c ^ iv[n] );
@@ -227,7 +293,8 @@ int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
     } else {
         while( length-- ) {
             if( n == 0 )
-                mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
+                if (mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ) != 0)
+                    return ST_ERR_AES_BUSY;
 
             iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ );
 
@@ -253,7 +320,8 @@ int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx,
 
     while( length-- ) {
         memcpy( ov, iv, 16 );
-        mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
+        if (mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ) != 0)
+            return ST_ERR_AES_BUSY;
 
         if( mode == MBEDTLS_AES_DECRYPT )
             ov[16] = *input;
@@ -286,7 +354,8 @@ int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx,
     while( length-- )
     {
         if( n == 0 ) {
-            mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block );
+            if (mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block ) != 0)
+                return ST_ERR_AES_BUSY;
 
             for( i = 16; i > 0; i-- )
                 if( ++nonce_counter[i - 1] != 0 )
@@ -304,26 +373,42 @@ int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx,
 }
 #endif /* MBEDTLS_CIPHER_MODE_CTR */
 
-void mbedtls_aes_encrypt( mbedtls_aes_context *ctx,
+int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx,
                           const unsigned char input[16],
                           unsigned char output[16] )
 {
-    
-    if (HAL_CRYP_AESECB_Encrypt(&ctx->hcryp_aes, (uint8_t *)input, 16, (uint8_t *)output, 10) !=0) {
-        // error found to be returned
+    if (HAL_CRYP_AESECB_Encrypt(&ctx->hcryp_aes, (uint8_t *)input, 16, (uint8_t *)output, 10) != HAL_OK) {
+        // error found
+        return ST_ERR_AES_BUSY;
     }
+    return 0;
 
 }
 
-void mbedtls_aes_decrypt( mbedtls_aes_context *ctx,
-                          const unsigned char input[16],
-                          unsigned char output[16] )
+int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx,
+                                  const unsigned char input[16],
+                                  unsigned char output[16] )
 {
-
-    if(HAL_CRYP_AESECB_Decrypt(&ctx->hcryp_aes, (uint8_t *)input, 16, (uint8_t *)output, 10)) {
-        // error found to be returned
+    if(HAL_CRYP_AESECB_Decrypt(&ctx->hcryp_aes, (uint8_t *)input, 16, (uint8_t *)output, 10) != HAL_OK) {
+        // error found
+        return ST_ERR_AES_BUSY;
     }
+    return 0;
 }
 
+#if !defined(MBEDTLS_DEPRECATED_REMOVED)
+void mbedtls_aes_encrypt( mbedtls_aes_context *ctx,
+                          const unsigned char input[16],
+                          unsigned char output[16] )
+{
+    mbedtls_internal_aes_encrypt( ctx, input, output );
+}
 
+void mbedtls_aes_decrypt( mbedtls_aes_context *ctx,
+                          const unsigned char input[16],
+                          unsigned char output[16] )
+{
+    mbedtls_internal_aes_decrypt( ctx, input, output );
+}
+#endif /* MBEDTLS_DEPRECATED_REMOVED */
 #endif /*MBEDTLS_AES_ALT*/
diff --git a/features/mbedtls/targets/TARGET_STM/aes_alt.h b/features/mbedtls/targets/TARGET_STM/aes_alt.h
index dbe4fdeec30..120c9af5f17 100644
--- a/features/mbedtls/targets/TARGET_STM/aes_alt.h
+++ b/features/mbedtls/targets/TARGET_STM/aes_alt.h
@@ -1,7 +1,7 @@
 /*
  *  aes_alt.h AES block cipher
  *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
+ * Copyright (c) 2017, STMicroelectronics
  *  SPDX-License-Identifier: Apache-2.0
  *
  *  Licensed under the Apache License, Version 2.0 (the "License"); you may
@@ -30,6 +30,9 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
+
+#define ST_AES_TIMEOUT    ((uint32_t) 0xFF) /* 255 ms timeout for the crypto processor */
+#define ST_ERR_AES_BUSY   (-0x0023)      /* Crypto processor is busy, timeout occured */
 /**
  * \brief          AES context structure
  *
@@ -236,10 +239,12 @@ int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx,
  * \param ctx       AES context
  * \param input     Plaintext block
  * \param output    Output (ciphertext) block
+ *
+ * \return          0 if successful
  */
-void mbedtls_aes_encrypt( mbedtls_aes_context *ctx,
-                          const unsigned char input[16],
-                          unsigned char output[16] );
+int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx,
+                                  const unsigned char input[16],
+                                  unsigned char output[16] );
 
 /**
  * \brief           Internal AES block decryption function
@@ -249,10 +254,49 @@ void mbedtls_aes_encrypt( mbedtls_aes_context *ctx,
  * \param ctx       AES context
  * \param input     Ciphertext block
  * \param output    Output (plaintext) block
+ *
+ * \return          0 if successful
  */
-void mbedtls_aes_decrypt( mbedtls_aes_context *ctx,
-                          const unsigned char input[16],
-                          unsigned char output[16] );
+int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx,
+                                  const unsigned char input[16],
+                                  unsigned char output[16] );
+
+#if !defined(MBEDTLS_DEPRECATED_REMOVED)
+#if defined(MBEDTLS_DEPRECATED_WARNING)
+#define MBEDTLS_DEPRECATED      __attribute__((deprecated))
+#else
+#define MBEDTLS_DEPRECATED
+#endif
+/**
+ * \brief           Deprecated internal AES block encryption function
+ *                  without return value.
+ *
+ * \deprecated      Superseded by mbedtls_aes_encrypt_ext() in 2.5.0
+ *
+ * \param ctx       AES context
+ * \param input     Plaintext block
+ * \param output    Output (ciphertext) block
+ */
+MBEDTLS_DEPRECATED void mbedtls_aes_encrypt( mbedtls_aes_context *ctx,
+                                             const unsigned char input[16],
+                                             unsigned char output[16] );
+
+/**
+ * \brief           Deprecated internal AES block decryption function
+ *                  without return value.
+ *
+ * \deprecated      Superseded by mbedtls_aes_decrypt_ext() in 2.5.0
+ *
+ * \param ctx       AES context
+ * \param input     Ciphertext block
+ * \param output    Output (plaintext) block
+ */
+MBEDTLS_DEPRECATED void mbedtls_aes_decrypt( mbedtls_aes_context *ctx,
+                                             const unsigned char input[16],
+                                             unsigned char output[16] );
+
+#undef MBEDTLS_DEPRECATED
+#endif /* !MBEDTLS_DEPRECATED_REMOVED */
 
 #ifdef __cplusplus
 }
diff --git a/features/mbedtls/targets/TARGET_Silicon_Labs/aes_aes.c b/features/mbedtls/targets/TARGET_Silicon_Labs/aes_aes.c
new file mode 100644
index 00000000000..822c7e6f468
--- /dev/null
+++ b/features/mbedtls/targets/TARGET_Silicon_Labs/aes_aes.c
@@ -0,0 +1,466 @@
+/*
+ *  Hardware-accelerated AES implementation for Silicon Labs devices
+ *  containing an AES peripheral.
+ *
+ *  Copyright 2017, Silicon Laboratories, Inc.
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ */
+
+#include "mbedtls/aes.h"
+#include "em_device.h"
+
+#if defined(AES_PRESENT) && (AES_COUNT == 1)
+#if defined(MBEDTLS_AES_C)
+#if defined(MBEDTLS_AES_ALT)
+#include "em_aes.h"
+#include "em_cmu.h"
+#include "em_bus.h"
+#include <string.h>
+
+#if defined(MBEDTLS_THREADING_C)
+#include "mbedtls/threading.h"
+#include "em_core.h"
+/* Mutex for protecting access to the AES instance */
+static mbedtls_threading_mutex_t aes_mutex;
+static volatile bool aes_mutex_inited = false;
+#endif
+
+static void aes_lock( void )
+{
+#if defined(MBEDTLS_THREADING_C)
+    if ( !aes_mutex_inited ) {
+        /* Turn off interrupts that can cause preemption */
+        CORE_irqState_t critical_irq_state = CORE_EnterCritical();
+        if ( !aes_mutex_inited ) {
+            mbedtls_mutex_init(&aes_mutex);
+            aes_mutex_inited = true;
+        }
+        CORE_ExitCritical(critical_irq_state);
+    }
+    mbedtls_mutex_lock(&aes_mutex);
+#endif
+    BUS_RegBitWrite(&(CMU->HFCORECLKEN0), _CMU_HFCORECLKEN0_AES_SHIFT, 1);
+    return;
+}
+
+static void aes_unlock( void )
+{
+#if defined(MBEDTLS_THREADING_C)
+    if ( aes_mutex_inited ) {
+        mbedtls_mutex_unlock(&aes_mutex);
+    }
+#endif
+    BUS_RegBitWrite(&(CMU->HFCORECLKEN0), _CMU_HFCORECLKEN0_AES_SHIFT, 0);
+    return;
+}
+
+/*
+ * Initialize AES context
+ */
+void mbedtls_aes_init( mbedtls_aes_context *ctx )
+{
+    if( ctx == NULL )
+        return;
+
+    memset( ctx, 0, sizeof( mbedtls_aes_context ) );
+}
+
+/*
+ * Clear AES context
+ */
+void mbedtls_aes_free( mbedtls_aes_context *ctx )
+{
+    if( ctx == NULL )
+        return;
+
+    memset( ctx, 0, sizeof( mbedtls_aes_context ) );
+}
+
+/*
+ * AES key schedule (encryption)
+ */
+int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx,
+                            const unsigned char *key,
+                            unsigned int keybits )
+{
+    if ( ( 128 != keybits ) && ( 256 != keybits ) )
+    {
+        /* Unsupported key size */
+        return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH );
+    }
+
+    ctx->keybits = keybits;
+    memcpy( ctx->key, key, keybits/8 );
+
+    return 0;
+}
+
+/*
+ * AES key schedule (decryption)
+ */
+int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx,
+                            const unsigned char *key,
+                            unsigned int keybits )
+{
+    if ( ( 128 != keybits ) && ( 256 != keybits ) )
+        /* Unsupported key size */
+        return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH );
+
+    ctx->keybits = keybits;
+    switch (keybits)
+    {
+        case 128:
+            aes_lock();
+            AES_DecryptKey128( ctx->key, key );
+            aes_unlock();
+            break;
+        case 256:
+            aes_lock();
+            AES_DecryptKey256( ctx->key, key );
+            aes_unlock();
+            break;
+        default:
+            return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH );
+    }
+
+    return 0;
+}
+
+/*
+ * AES-ECB block encryption
+ */
+int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx,
+                                   const unsigned char input[16],
+                                   unsigned char output[16] )
+{
+    return mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, input, output);
+}
+
+/*
+ * AES-ECB block decryption
+ */
+int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx,
+                                   const unsigned char input[16],
+                                   unsigned char output[16] )
+{
+    return mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_DECRYPT, input, output);
+}
+
+/*
+ * AES-ECB block encryption/decryption
+ */
+int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
+                           int mode,
+                           const unsigned char input[16],
+                           unsigned char output[16] )
+{
+    switch ( ctx->keybits )
+    {
+        case 128:
+            aes_lock();
+            AES_ECB128( output,
+                        input,
+                        16,
+                        ctx->key,
+                        mode == MBEDTLS_AES_ENCRYPT ? true : false );
+            aes_unlock();
+            break;
+        case 256:
+            aes_lock();
+            AES_ECB256( output,
+                        input,
+                        16,
+                        ctx->key,
+                        mode == MBEDTLS_AES_ENCRYPT ? true : false );
+            aes_unlock();
+            break;
+        default:
+           return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH );
+    }
+
+    return( 0 );
+}
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+/*
+ * AES-CBC buffer encryption/decryption
+ */
+int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
+                           int mode,
+                           size_t length,
+                           unsigned char iv[16],
+                           const unsigned char *input,
+                           unsigned char *output )
+{
+    uint8_t tmpIv[16];
+
+    if( length % 16 )
+    {
+        return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH );
+    }
+
+    if ( mode == MBEDTLS_AES_DECRYPT )
+    {
+        if ( length >= 16 )
+            memcpy( tmpIv, &input[length-16], 16 );
+    }
+
+    switch ( ctx->keybits )
+    {
+        case 128:
+            aes_lock();
+            AES_CBC128( output,
+                        input,
+                        length,
+                        ctx->key,
+                        iv,
+                        mode == MBEDTLS_AES_ENCRYPT ? true : false );
+            aes_unlock();
+            break;
+        case 256:
+            aes_lock();
+            AES_CBC256( output,
+                        input,
+                        length,
+                        ctx->key,
+                        iv,
+                        mode == MBEDTLS_AES_ENCRYPT ? true : false );
+            aes_unlock();
+            break;
+        default:
+           return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH );
+    }
+
+    if ( length >= 16 )
+    {
+        if ( mode == MBEDTLS_AES_ENCRYPT )
+            memcpy( iv, &output[length-16], 16 );
+        else
+            memcpy( iv, tmpIv, 16 );
+    }
+
+    return( 0 );
+}
+#endif /* MBEDTLS_CIPHER_MODE_CBC */
+
+#if defined(MBEDTLS_CIPHER_MODE_CFB)
+/*
+ * AES-CFB128 buffer encryption/decryption
+ */
+int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
+                              int mode,
+                              size_t length,
+                              size_t *iv_off,
+                              unsigned char iv[16],
+                              const unsigned char *input,
+                              unsigned char *output )
+{
+    size_t n = ( iv_off != NULL ) ? *iv_off : 0;
+
+    if ( ( n > 0 ) || ( length & 0xf ) )
+    {
+        // IV offset or length not aligned to block size
+        int c;
+
+        if( mode == MBEDTLS_AES_DECRYPT )
+        {
+            while( length-- )
+            {
+                if( n == 0 )
+                    mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
+
+                c = *input++;
+                *output++ = (unsigned char)( c ^ iv[n] );
+                iv[n] = (unsigned char) c;
+
+                n = ( n + 1 ) & 0x0F;
+            }
+        }
+        else
+        {
+            while( length-- )
+            {
+                if( n == 0 )
+                    mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
+
+                iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ );
+
+                n = ( n + 1 ) & 0x0F;
+            }
+        }
+
+        if (iv_off)
+        {
+            *iv_off = n;
+        }
+        return( 0 );
+    }
+    else
+    {
+        switch( ctx->keybits )
+        {
+        case 128:
+            aes_lock();
+            AES_CFB128(output,
+                       input,
+                       length,
+                       ctx->key,
+                       iv,
+                       mode == MBEDTLS_AES_ENCRYPT ? true : false );
+            aes_unlock();
+            break;
+
+        case 256:
+            aes_lock();
+            AES_CFB256(output,
+                       input,
+                       length,
+                       ctx->key,
+                       iv,
+                       mode == MBEDTLS_AES_ENCRYPT ? true : false );
+            aes_unlock();
+            break;
+
+        default:
+            return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH );
+        }
+
+        return( 0 );
+    }
+}
+
+/*
+ * AES-CFB8 buffer encryption/decryption
+ */
+int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx,
+                       int mode,
+                       size_t length,
+                       unsigned char iv[16],
+                       const unsigned char *input,
+                       unsigned char *output )
+{
+    unsigned char c;
+    unsigned char ov[17];
+
+    while( length-- )
+    {
+        memcpy( ov, iv, 16 );
+        mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
+
+        if( mode == MBEDTLS_AES_DECRYPT )
+            ov[16] = *input;
+
+        c = *output++ = (unsigned char)( iv[0] ^ *input++ );
+
+        if( mode == MBEDTLS_AES_ENCRYPT )
+            ov[16] = c;
+
+        memcpy( iv, ov + 1, 16 );
+    }
+
+    return( 0 );
+}
+#endif /*MBEDTLS_CIPHER_MODE_CFB */
+
+#if defined(MBEDTLS_CIPHER_MODE_CTR)
+/*
+ * AES-CTR Nonce update function
+ */
+static void aes_ctr_update_nonce( uint8_t *nonce_counter )
+{
+    for( size_t i = 16; i > 0; i-- )
+        if( ++nonce_counter[i - 1] != 0 )
+            break;
+}
+
+/*
+ * AES-CTR buffer encryption/decryption
+ */
+int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx,
+                           size_t length,
+                           size_t *nc_off,
+                           unsigned char nonce_counter[16],
+                           unsigned char stream_block[16],
+                           const unsigned char *input,
+                           unsigned char *output )
+{
+    size_t n = ( nc_off != NULL ) ? *nc_off : 0;
+
+    if ( ( n > 0 ) || ( length & 0xf ) )
+    {
+        // IV offset or length not aligned to block size
+        int c, i;
+
+        while( length-- )
+        {
+            if( n == 0 )
+            {
+                mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block );
+
+                for( i = 16; i > 0; i-- )
+                    if( ++nonce_counter[i - 1] != 0 )
+                        break;
+            }
+            c = *input++;
+            *output++ = (unsigned char)( c ^ stream_block[n] );
+
+            n = ( n + 1 ) & 0x0F;
+        }
+
+        if (nc_off)
+        {
+            *nc_off = n;
+        }
+        return( 0 );
+    }
+    else
+    {
+        switch( ctx->keybits )
+        {
+        case 128:
+            aes_lock();
+            AES_CTR128( output,
+                        input,
+                        length,
+                        ctx->key,
+                        nonce_counter,
+                        &aes_ctr_update_nonce );
+            aes_unlock();
+        break;
+
+        case 256:
+            aes_lock();
+            AES_CTR256( output,
+                        input,
+                        length,
+                        ctx->key,
+                        nonce_counter,
+                        &aes_ctr_update_nonce );
+            aes_unlock();
+            break;
+
+        default:
+            return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH );
+            break;
+        }
+
+        return( 0 );
+    }
+}
+#endif /* MBEDTLS_CIPHER_MODE_CTR */
+
+#endif /* MBEDTLS_AES_ALT */
+#endif /* MBEDTLS_AES_C */
+#endif /* AES_PRESENT && (AES_COUNT == 1) */
diff --git a/features/mbedtls/targets/TARGET_Silicon_Labs/aes_alt.h b/features/mbedtls/targets/TARGET_Silicon_Labs/aes_alt.h
new file mode 100644
index 00000000000..6b18a334e64
--- /dev/null
+++ b/features/mbedtls/targets/TARGET_Silicon_Labs/aes_alt.h
@@ -0,0 +1,318 @@
+/*
+ * AES block cipher
+ *
+ *  Copyright (C) 2015-2017, Silicon Labs, http://www.silabs.com
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ */
+#ifndef MBEDTLS_AES_ALT_H
+#define MBEDTLS_AES_ALT_H
+
+/***************************************************************************//**
+ * \addtogroup sl_crypto
+ * \{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * \addtogroup sl_crypto_aes AES block cipher
+ * \brief Hardware accelerated AES block cipher.
+ * \{
+ ******************************************************************************/
+
+#if defined(MBEDTLS_AES_ALT)
+/* SiliconLabs CRYPTO hardware acceleration implementation */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          AES context structure
+ */
+typedef struct
+{
+    unsigned int                    keybits;   /*!<  size of key */
+    unsigned char                   key[32];   /*!<  AES key 128 or 256 bits */
+}
+mbedtls_aes_context;
+
+/**
+ * \brief          Initialize AES context
+ *
+ * \param ctx      AES context to be initialized
+ */
+void mbedtls_aes_init( mbedtls_aes_context *ctx );
+
+/**
+ * \brief          Clear AES context
+ *
+ * \param ctx      AES context to be cleared
+ */
+void mbedtls_aes_free( mbedtls_aes_context *ctx );
+
+/**
+ * \brief          AES key schedule (encryption)
+ *
+ * \param ctx      AES context to be initialized
+ * \param key      encryption key
+ * \param keybits  must be 128 or 256
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH
+ */
+int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key,
+                    unsigned int keybits );
+
+/**
+ * \brief          AES key schedule (decryption)
+ *
+ * \param ctx      AES context to be initialized
+ * \param key      decryption key
+ * \param keybits  must be 128 or 256
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH
+ */
+int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key,
+                    unsigned int keybits );
+
+/**
+ * \brief          AES-ECB block encryption/decryption
+ *
+ * \param ctx      AES context
+ * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
+ * \param input    16-byte input block
+ * \param output   16-byte output block
+ *
+ * \return         0 if successful
+ */
+int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
+                    int mode,
+                    const unsigned char input[16],
+                    unsigned char output[16] );
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+/**
+ * \brief          AES-CBC buffer encryption/decryption
+ *                 Length should be a multiple of the block
+ *                 size (16 bytes)
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the same function again on the following block(s) of
+ *                 data and get the same result as if it was encrypted in one
+ *                 call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      AES context
+ * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
+ * \param length   length of the input data
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful, or MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH
+ */
+int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
+                    int mode,
+                    size_t length,
+                    unsigned char iv[16],
+                    const unsigned char *input,
+                    unsigned char *output );
+#endif /* MBEDTLS_CIPHER_MODE_CBC */
+
+#if defined(MBEDTLS_CIPHER_MODE_CFB)
+/**
+ * \brief          AES-CFB128 buffer encryption/decryption.
+ *
+ * Note: Due to the nature of CFB you should use the same key schedule for
+ * both encryption and decryption. So a context initialized with
+ * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT.
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      AES context
+ * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
+ * \param length   length of the input data
+ * \param iv_off   offset in IV (updated after use)
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful
+ */
+int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
+                       int mode,
+                       size_t length,
+                       size_t *iv_off,
+                       unsigned char iv[16],
+                       const unsigned char *input,
+                       unsigned char *output );
+
+/**
+ * \brief          AES-CFB8 buffer encryption/decryption.
+ *
+ * Note: Due to the nature of CFB you should use the same key schedule for
+ * both encryption and decryption. So a context initialized with
+ * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT.
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      AES context
+ * \param mode     MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
+ * \param length   length of the input data
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful
+ */
+int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx,
+                    int mode,
+                    size_t length,
+                    unsigned char iv[16],
+                    const unsigned char *input,
+                    unsigned char *output );
+#endif /*MBEDTLS_CIPHER_MODE_CFB */
+
+#if defined(MBEDTLS_CIPHER_MODE_CTR)
+/**
+ * \brief               AES-CTR buffer encryption/decryption
+ *
+ * Warning: You have to keep the maximum use of your counter in mind!
+ *
+ * Note: Due to the nature of CTR you should use the same key schedule for
+ * both encryption and decryption. So a context initialized with
+ * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT.
+ *
+ * \param ctx           AES context
+ * \param length        The length of the data
+ * \param nc_off        The offset in the current stream_block (for resuming
+ *                      within current cipher stream). The offset pointer to
+ *                      should be 0 at the start of a stream.
+ * \param nonce_counter The 128-bit nonce and counter.
+ * \param stream_block  The saved stream-block for resuming. Is overwritten
+ *                      by the function.
+ * \param input         The input data stream
+ * \param output        The output data stream
+ *
+ * \return         0 if successful
+ */
+int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx,
+                       size_t length,
+                       size_t *nc_off,
+                       unsigned char nonce_counter[16],
+                       unsigned char stream_block[16],
+                       const unsigned char *input,
+                       unsigned char *output );
+#endif /* MBEDTLS_CIPHER_MODE_CTR */
+
+/**
+ * \brief           Internal AES block encryption function
+ *                  (Only exposed to allow overriding it,
+ *                  see MBEDTLS_AES_ENCRYPT_ALT)
+ *
+ * \param ctx       AES context
+ * \param input     Plaintext block
+ * \param output    Output (ciphertext) block
+ *
+ * \return          0 if successful
+ */
+int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx,
+                                  const unsigned char input[16],
+                                  unsigned char output[16] );
+
+/**
+ * \brief           Internal AES block decryption function
+ *                  (Only exposed to allow overriding it,
+ *                  see MBEDTLS_AES_DECRYPT_ALT)
+ *
+ * \param ctx       AES context
+ * \param input     Ciphertext block
+ * \param output    Output (plaintext) block
+ *
+ * \return          0 if successful
+ */
+int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx,
+                                  const unsigned char input[16],
+                                  unsigned char output[16] );
+
+#if !defined(MBEDTLS_DEPRECATED_REMOVED)
+#if defined(MBEDTLS_DEPRECATED_WARNING)
+#define MBEDTLS_DEPRECATED      __attribute__((deprecated))
+#else
+#define MBEDTLS_DEPRECATED
+#endif
+/**
+ * \brief           Internal AES block encryption function
+ *                  (Only exposed to allow overriding it,
+ *                  see MBEDTLS_AES_ENCRYPT_ALT)
+ *
+ * \deprecated      Superseded by mbedtls_aes_encrypt_ext() in 2.5.0
+ *
+ * \param ctx       AES context
+ * \param input     Plaintext block
+ * \param output    Output (ciphertext) block
+ */
+MBEDTLS_DEPRECATED static inline void mbedtls_aes_encrypt(
+                                                mbedtls_aes_context *ctx,
+                                                const unsigned char input[16],
+                                                unsigned char output[16] )
+{
+    mbedtls_internal_aes_encrypt( ctx, input, output );
+}
+
+/**
+ * \brief           Internal AES block decryption function
+ *                  (Only exposed to allow overriding it,
+ *                  see MBEDTLS_AES_DECRYPT_ALT)
+ *
+ * \deprecated      Superseded by mbedtls_aes_decrypt_ext() in 2.5.0
+ *
+ * \param ctx       AES context
+ * \param input     Ciphertext block
+ * \param output    Output (plaintext) block
+ */
+MBEDTLS_DEPRECATED static inline void mbedtls_aes_decrypt(
+                                                mbedtls_aes_context *ctx,
+                                                const unsigned char input[16],
+                                                unsigned char output[16] )
+{
+    mbedtls_internal_aes_decrypt( ctx, input, output );
+}
+
+#undef MBEDTLS_DEPRECATED
+#endif /* !MBEDTLS_DEPRECATED_REMOVED */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBEDTLS_AES_ALT */
+
+/** \} (end addtogroup sl_crypto_aes) */
+/** \} (end addtogroup sl_crypto) */
+
+#endif /* MBEDTLS_AES_ALT_H */
diff --git a/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_aes.c b/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_aes.c
new file mode 100644
index 00000000000..8b3c75aba58
--- /dev/null
+++ b/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_aes.c
@@ -0,0 +1,557 @@
+/*
+ *  FIPS-197 compliant AES implementation
+ *
+ *  Copyright (C) 2017, Silicon Labs, http://www.silabs.com
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ */
+
+/*
+ * This file includes alternative plugin implementations of various
+ * functions in aes.c using the CRYPTO hardware accelerator incorporated
+ * in MCU devices from Silicon Laboratories.
+ */
+
+/*
+ *  The AES block cipher was designed by Vincent Rijmen and Joan Daemen.
+ *
+ *  http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf
+ *  http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
+ */
+
+#include "mbedtls/aes.h"
+#include "em_device.h"
+
+#if defined(CRYPTO_PRESENT)
+#if defined(MBEDTLS_AES_C)
+#if defined(MBEDTLS_AES_ALT)
+
+#include "crypto_management.h"
+#include "em_crypto.h"
+#include "em_core.h"
+#include <string.h>
+
+__STATIC_INLINE void CRYPTO_DataReadUnaligned(volatile uint32_t * reg,
+                                              uint8_t * const val)
+{
+  /* Check data is 32bit aligned, if not, read into temporary buffer and
+     then move to user buffer. */
+  if ((uint32_t)val & 0x3)
+  {
+    uint32_t temp[4];
+    CRYPTO_DataRead(reg, temp);
+    memcpy(val, temp, 16);
+  }
+  else
+  {
+    CRYPTO_DataRead(reg, (uint32_t* const)val);
+  }
+}
+
+__STATIC_INLINE void CRYPTO_DataWriteUnaligned(volatile uint32_t * reg,
+                                               uint8_t * const val)
+{
+  /* Check data is 32bit aligned, if not move to temporary buffer before
+     writing.*/
+  if ((uint32_t)val & 0x3)
+  {
+    uint32_t temp[4];
+    memcpy(temp, val, 16);
+    CRYPTO_DataWrite(reg, temp);
+  }
+  else
+  {
+    CRYPTO_DataWrite(reg, (uint32_t* const)val);
+  }
+}
+
+/*
+ * Initialize AES context
+ */
+void mbedtls_aes_init( mbedtls_aes_context *ctx )
+{
+    if( ctx == NULL ) {
+        return;
+    }
+
+    memset( ctx, 0, sizeof( mbedtls_aes_context ) );
+}
+
+/*
+ * Clear AES context
+ */
+void mbedtls_aes_free( mbedtls_aes_context *ctx )
+{
+    if( ctx == NULL ) {
+        return;
+    }
+
+    memset( ctx, 0, sizeof( mbedtls_aes_context ) );
+}
+
+/*
+ * AES key schedule (encryption)
+ */
+int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx,
+                            const unsigned char *key,
+                            unsigned int keybits )
+{
+    if( ctx == NULL || key == NULL ) {
+        return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH );
+    }
+
+    if ( ( 128UL != keybits ) && ( 256UL != keybits ) ) {
+        /* Unsupported key size */
+        return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH );
+    }
+
+    ctx->keybits = keybits;
+    memcpy(ctx->key, key, keybits/8);
+
+    return 0;
+}
+
+/*
+ * AES key schedule (decryption)
+ */
+int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx,
+                            const unsigned char *key,
+                            unsigned int keybits )
+{
+    CORE_DECLARE_IRQ_STATE;
+
+    if( ctx == NULL || key == NULL ) {
+        return ( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH );
+    }
+
+    if ( ( 128UL != keybits ) && ( 256UL != keybits ) ) {
+        /* Unsupported key size */
+        return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH );
+    }
+
+    ctx->keybits = keybits;
+
+    CRYPTO_TypeDef *device = crypto_management_acquire();
+    device->WAC = 0;
+    device->CTRL = 0;
+
+    CORE_ENTER_CRITICAL();
+    CRYPTO_KeyBufWrite(device, (uint32_t*)key, (keybits == 128) ? cryptoKey128Bits : cryptoKey256Bits);
+    CORE_EXIT_CRITICAL();
+
+    /* Busy-wait here to allow context-switching to occur */
+    device->CMD = CRYPTO_CMD_INSTR_AESENC;
+    while ((device->STATUS & CRYPTO_STATUS_INSTRRUNNING) != 0);
+
+    CORE_ENTER_CRITICAL();
+    CRYPTO_KeyRead(device, (uint32_t*)ctx->key, (keybits == 128) ? cryptoKey128Bits : cryptoKey256Bits);
+    CORE_EXIT_CRITICAL();
+
+    crypto_management_release(device);
+
+    return 0;
+}
+
+/* TODO: underneath these, we should swap out the em_crypto-provided library
+ * functions with in-place implemented functions, to get much shorter
+ * critical sections */
+
+/*
+ * AES-ECB block encryption
+ */
+int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx,
+                                   const unsigned char input[16],
+                                   unsigned char output[16] )
+{
+    return mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, input, output);
+}
+
+/*
+ * AES-ECB block decryption
+ */
+int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx,
+                                   const unsigned char input[16],
+                                   unsigned char output[16] )
+{
+    return mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_DECRYPT, input, output);
+}
+
+/*
+ * AES-ECB block encryption/decryption
+ */
+int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
+                           int mode,
+                           const unsigned char input[16],
+                           unsigned char output[16] )
+{
+    int ret = 0;
+    CORE_DECLARE_IRQ_STATE;
+
+    if( ctx == NULL || input == NULL || output == NULL ) {
+        return ( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH );
+    }
+
+    if ( ctx->keybits != 128UL && ctx->keybits != 256UL) {
+        return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH;
+    }
+
+    CRYPTO_TypeDef *device = crypto_management_acquire();
+    device->WAC = 0;
+    device->CTRL = 0;
+
+    CORE_ENTER_CRITICAL();
+    CRYPTO_KeyBufWrite(device, (uint32_t*)ctx->key, (ctx->keybits == 128UL) ? cryptoKey128Bits : cryptoKey256Bits);
+    CRYPTO_DataWriteUnaligned(&device->DATA0, (uint8_t *)input);
+    CORE_EXIT_CRITICAL();
+
+    if ( mode == MBEDTLS_AES_ENCRYPT ) {
+        device->CMD = CRYPTO_CMD_INSTR_AESENC;
+    } else {
+        device->CMD = CRYPTO_CMD_INSTR_AESDEC;
+    }
+    while ((device->STATUS & CRYPTO_STATUS_INSTRRUNNING) != 0);
+
+    CORE_ENTER_CRITICAL();
+    CRYPTO_DataReadUnaligned(&device->DATA0, (uint8_t *)output);
+    CORE_EXIT_CRITICAL();
+
+    crypto_management_release(device);
+
+    return ret;
+}
+
+#if defined(MBEDTLS_CIPHER_MODE_CBC)
+
+/*
+ * AES-CBC buffer encryption/decryption
+ */
+int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
+                           int mode,
+                           size_t length,
+                           unsigned char iv[16],
+                           const unsigned char *input,
+                           unsigned char *output )
+{
+    int ret = 0;
+    CORE_DECLARE_IRQ_STATE;
+    size_t processed = 0;
+
+    if( ctx == NULL || input == NULL || output == NULL || iv == NULL ) {
+        return ( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH );
+    }
+
+    /* Input length must be a multiple of 16 bytes which is the AES block
+       length. */
+    if( length & 0xf ) {
+        return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH );
+    }
+
+    if ( ctx->keybits != 128UL && ctx->keybits != 256UL) {
+        return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH;
+    }
+
+    CRYPTO_TypeDef *device = crypto_management_acquire();
+    device->WAC = 0;
+    device->CTRL = 0;
+
+    CORE_ENTER_CRITICAL();
+    CRYPTO_KeyBufWrite(device, (uint32_t*)ctx->key, (ctx->keybits == 128UL) ? cryptoKey128Bits : cryptoKey256Bits);
+    if ( mode == MBEDTLS_AES_ENCRYPT ) {
+        CRYPTO_DataWriteUnaligned(&device->DATA0, (uint8_t *)iv);
+    } else {
+        CRYPTO_DataWriteUnaligned(&device->DATA2, (uint8_t *)iv);
+    }
+    CORE_EXIT_CRITICAL();
+
+    while ( processed < length ) {
+        if ( mode == MBEDTLS_AES_ENCRYPT ) {
+            CORE_ENTER_CRITICAL();
+            CRYPTO_DataWriteUnaligned(&device->DATA0XOR, (uint8_t *)(&input[processed]));
+            device->CMD = CRYPTO_CMD_INSTR_AESENC;
+            CRYPTO_DataReadUnaligned(&device->DATA0, (uint8_t *)(&output[processed]));
+            CORE_EXIT_CRITICAL();
+        } else {
+            /* Decrypt input block, XOR IV to decrypted text, set ciphertext as next IV */
+            CORE_ENTER_CRITICAL();
+            CRYPTO_DataWriteUnaligned(&device->DATA0, (uint8_t *)(&input[processed]));
+            CRYPTO_EXECUTE_4( device,
+                              CRYPTO_CMD_INSTR_DATA0TODATA1,
+                              CRYPTO_CMD_INSTR_AESDEC,
+                              CRYPTO_CMD_INSTR_DATA2TODATA0XOR,
+                              CRYPTO_CMD_INSTR_DATA1TODATA2);
+            CRYPTO_DataReadUnaligned(&device->DATA0, (uint8_t *)(&output[processed]));
+            CORE_EXIT_CRITICAL();
+        }
+        processed += 16;
+    }
+
+    if ( processed >= 16 ) {
+        if ( mode == MBEDTLS_AES_ENCRYPT ) {
+            memcpy(iv, &output[processed-16], 16);
+        } else {
+            CORE_ENTER_CRITICAL();
+            CRYPTO_DataReadUnaligned(&device->DATA2, (uint8_t *)(iv));
+            CORE_EXIT_CRITICAL();
+        }
+    }
+
+    crypto_management_release(device);
+
+    return ret;
+}
+#endif /* MBEDTLS_CIPHER_MODE_CBC */
+
+#if defined(MBEDTLS_CIPHER_MODE_CFB)
+/*
+ * AES-CFB128 buffer encryption/decryption
+ */
+int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
+                              int mode,
+                              size_t length,
+                              size_t *iv_off,
+                              unsigned char iv[16],
+                              const unsigned char *input,
+                              unsigned char *output )
+{
+    size_t n = iv_off ? *iv_off : 0;
+    size_t processed = 0;
+    int ret = 0;
+    CORE_DECLARE_IRQ_STATE;
+
+    if( ctx == NULL || input == NULL || output == NULL || iv == NULL ) {
+        return ( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH );
+    }
+
+    if ( ctx->keybits != 128UL && ctx->keybits != 256UL) {
+        return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH;
+    }
+
+    while ( processed < length ) {
+        if ( n > 0 ) {
+            /* start by filling up the IV */
+            if( mode == MBEDTLS_AES_ENCRYPT ) {
+                iv[n] = output[processed] = (unsigned char)( iv[n] ^ input[processed] );
+            } else {
+                int c = input[processed];
+                output[processed] = (unsigned char)( c ^ iv[n] );
+                iv[n] = (unsigned char) c;
+            }
+            n = ( n + 1 ) & 0x0F;
+            processed++;
+            continue;
+        } else {
+            /* process one ore more blocks of data */
+            CRYPTO_TypeDef *device = crypto_management_acquire();
+            device->WAC = 0;
+            device->CTRL = 0;
+
+            CORE_ENTER_CRITICAL();
+            CRYPTO_KeyBufWrite(device, (uint32_t*)ctx->key, (ctx->keybits == 128UL) ? cryptoKey128Bits : cryptoKey256Bits);
+            CRYPTO_DataWriteUnaligned(&device->DATA0, (uint8_t *)iv);
+            CORE_EXIT_CRITICAL();
+
+            /* Encryption: encrypt IV, encIV xor input -> output and IV */
+            /* Decryption: encrypt IV, encIV xor input -> output, input -> IV */
+            size_t iterations = (length - processed) / 16;
+            for (size_t i = 0; i < iterations; i++ ) {
+                device->CMD = CRYPTO_CMD_INSTR_AESENC;
+                while ((device->STATUS & CRYPTO_STATUS_INSTRRUNNING) != 0);
+
+                CORE_ENTER_CRITICAL();
+                if ( mode == MBEDTLS_AES_ENCRYPT ) {
+                    CRYPTO_DataWriteUnaligned(&device->DATA0XOR, (uint8_t *)(&input[processed]));
+                    CRYPTO_DataReadUnaligned(&device->DATA0, (uint8_t *)(&output[processed]));
+                } else {
+                    CRYPTO_DataWriteUnaligned(&device->DATA1, (uint8_t *)(&input[processed]));
+                    device->CMD = CRYPTO_CMD_INSTR_DATA1TODATA0XOR;
+                    CRYPTO_DataReadUnaligned(&device->DATA0, (uint8_t *)(&output[processed]));
+                    device->CMD = CRYPTO_CMD_INSTR_DATA1TODATA0;
+                }
+                CORE_EXIT_CRITICAL();
+                processed += 16;
+            }
+
+            CORE_ENTER_CRITICAL();
+            CRYPTO_DataReadUnaligned(&device->DATA0, (uint8_t *)iv);
+            CORE_EXIT_CRITICAL();
+
+            while ( length - processed > 0 ) {
+                if ( n == 0 ) {
+                    device->CMD = CRYPTO_CMD_INSTR_AESENC;
+                    while ((device->STATUS & CRYPTO_STATUS_INSTRRUNNING) != 0);
+                    CORE_ENTER_CRITICAL();
+                    CRYPTO_DataReadUnaligned(&device->DATA0, (uint8_t *)iv);
+                    CORE_EXIT_CRITICAL();
+                }
+                /* Save remainder to iv */
+                if( mode == MBEDTLS_AES_ENCRYPT ) {
+                    iv[n] = output[processed] = (unsigned char)( iv[n] ^ input[processed] );
+                } else {
+                    int c = input[processed];
+                    output[processed] = (unsigned char)( c ^ iv[n] );
+                    iv[n] = (unsigned char) c;
+                }
+                n = ( n + 1 ) & 0x0F;
+                processed++;
+            }
+
+            crypto_management_release(device);
+        }
+    }
+
+    if ( iv_off ) {
+        *iv_off = n;
+    }
+
+    return ret;
+}
+
+/*
+ * AES-CFB8 buffer encryption/decryption
+ */
+int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx,
+                            int mode,
+                            size_t length,
+                            unsigned char iv[16],
+                            const unsigned char *input,
+                            unsigned char *output )
+{
+    unsigned char c;
+    unsigned char ov[17];
+    int ret = 0;
+
+    if( ctx == NULL || input == NULL || output == NULL || iv == NULL ) {
+        return ( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH );
+    }
+
+    if ( ctx->keybits != 128UL && ctx->keybits != 256UL) {
+        return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH;
+    }
+
+    while( length-- )
+    {
+        memcpy( ov, iv, 16 );
+        if ( (ret = mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ) ) != 0 ) {
+            return ret;
+        }
+
+        if( mode == MBEDTLS_AES_DECRYPT )
+            ov[16] = *input;
+
+        c = *output++ = (unsigned char)( iv[0] ^ *input++ );
+
+        if( mode == MBEDTLS_AES_ENCRYPT )
+            ov[16] = c;
+
+        memcpy( iv, ov + 1, 16 );
+    }
+
+    return ret;
+}
+#endif /*MBEDTLS_CIPHER_MODE_CFB */
+
+#if defined(MBEDTLS_CIPHER_MODE_CTR)
+/*
+ * AES-CTR buffer encryption/decryption
+ */
+int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx,
+                           size_t length,
+                           size_t *nc_off,
+                           unsigned char nonce_counter[16],
+                           unsigned char stream_block[16],
+                           const unsigned char *input,
+                           unsigned char *output )
+{
+    size_t n = nc_off ? *nc_off : 0;
+    size_t processed = 0;
+    int ret = 0;
+    CORE_DECLARE_IRQ_STATE;
+
+    if( ctx == NULL || input == NULL || output == NULL || nonce_counter == NULL || stream_block == NULL ) {
+        return ( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH );
+    }
+
+    if ( ctx->keybits != 128UL && ctx->keybits != 256UL) {
+        return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH;
+    }
+
+    while ( processed < length ) {
+        if ( n > 0 ) {
+            /* start by filling up the IV */
+            output[processed] = (unsigned char)( input[processed] ^ stream_block[n] );
+            n = ( n + 1 ) & 0x0F;
+            processed++;
+            continue;
+        } else {
+            /* process one ore more blocks of data */
+            CRYPTO_TypeDef *device = crypto_management_acquire();
+            device->WAC = 0;
+            device->CTRL = CRYPTO_CTRL_INCWIDTH_INCWIDTH4;
+
+            CORE_ENTER_CRITICAL();
+            CRYPTO_KeyBufWrite(device, (uint32_t*)ctx->key, (ctx->keybits == 128UL) ? cryptoKey128Bits : cryptoKey256Bits);
+            CRYPTO_DataWriteUnaligned(&device->DATA1, (uint8_t *)nonce_counter);
+            CORE_EXIT_CRITICAL();
+
+            /* strategy: encrypt nonce, encNonce xor input -> output, inc(nonce) */
+            size_t iterations = (length - processed) / 16;
+            for (size_t i = 0; i < iterations; i++ ) {
+                device->CMD = CRYPTO_CMD_INSTR_DATA1TODATA0;
+                device->CMD = CRYPTO_CMD_INSTR_AESENC;
+                while ((device->STATUS & CRYPTO_STATUS_INSTRRUNNING) != 0);
+                device->CMD = CRYPTO_CMD_INSTR_DATA1INC;
+
+                CORE_ENTER_CRITICAL();
+                CRYPTO_DataWriteUnaligned(&device->DATA0XOR, (uint8_t *)(&input[processed]));
+                CRYPTO_DataReadUnaligned(&device->DATA0, (uint8_t *)(&output[processed]));
+                CORE_EXIT_CRITICAL();
+                processed += 16;
+            }
+
+            while ( length - processed > 0 ) {
+                if ( n == 0 ) {
+                    device->CMD = CRYPTO_CMD_INSTR_DATA1TODATA0;
+                    device->CMD = CRYPTO_CMD_INSTR_AESENC;
+                    while ((device->STATUS & CRYPTO_STATUS_INSTRRUNNING) != 0);
+                    device->CMD = CRYPTO_CMD_INSTR_DATA1INC;
+
+                    CORE_ENTER_CRITICAL();
+                    CRYPTO_DataReadUnaligned(&device->DATA0, (uint8_t *)stream_block);
+                    CORE_EXIT_CRITICAL();
+                }
+                /* Save remainder to iv */
+                output[processed] = (unsigned char)( input[processed] ^ stream_block[n] );
+                n = ( n + 1 ) & 0x0F;
+                processed++;
+            }
+
+            CORE_ENTER_CRITICAL();
+            CRYPTO_DataReadUnaligned(&device->DATA1, (uint8_t *)nonce_counter);
+            CORE_EXIT_CRITICAL();
+
+            crypto_management_release(device);
+        }
+    }
+
+    if ( nc_off ) {
+        *nc_off = n;
+    }
+
+    return ret;
+}
+#endif /* MBEDTLS_CIPHER_MODE_CTR */
+
+#endif /* MBEDTLS_AES_ALT */
+#endif /* MBEDTLS_AES_C */
+#endif /* CRYPTO_PRESENT */
diff --git a/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_ecp.c b/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_ecp.c
new file mode 100644
index 00000000000..48fe271e8fc
--- /dev/null
+++ b/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_ecp.c
@@ -0,0 +1,1725 @@
+/*
+ *  Elliptic curves over GF(p): CRYPTO hw acceleration functions
+ *
+ *  Copyright (C) 2016, Silicon Labs, http://www.silabs.com
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ */
+/*
+ * This file includes alternative plugin implementations of various
+ * functions in ecp.c using the CRYPTO hardware accelerator incorporated
+ * in MCU devices from Silicon Laboratories.
+ */
+/*
+ * References:
+ *
+ * SEC1 http://www.secg.org/index.php?action=secg,docs_secg
+ * GECC = Guide to Elliptic Curve Cryptography - Hankerson, Menezes, Vanstone
+ * FIPS 186-3 http://csrc.nist.gov/publications/fips/fips186-3/fips_186-3.pdf
+ * RFC 4492 for the related TLS structures and constants
+ *
+ * [Curve25519] http://cr.yp.to/ecdh/curve25519-20060209.pdf
+ *
+ * [2] CORON, Jean-S'ebastien. Resistance against differential power analysis
+ *     for elliptic curve cryptosystems. In : Cryptographic Hardware and
+ *     Embedded Systems. Springer Berlin Heidelberg, 1999. p. 292-302.
+ *     <http://link.springer.com/chapter/10.1007/3-540-48059-5_25>
+ *
+ * [3] HEDABOU, Mustapha, PINEL, Pierre, et B'EN'ETEAU, Lucien. A comb method to
+ *     render ECC resistant against Side Channel Attacks. IACR Cryptology
+ *     ePrint Archive, 2004, vol. 2004, p. 342.
+ *     <http://eprint.iacr.org/2004/342.pdf>
+ */
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "mbedtls/config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include "em_device.h"
+
+#if defined( CRYPTO_PRESENT )
+
+#if defined( MBEDTLS_ECP_C )
+#if defined( MBEDTLS_ECP_INTERNAL_ALT )
+
+#include "mbedtls/ecp.h"
+#include "mbedtls/ecp_internal.h"
+#include "mbedtls/platform.h"
+#include "em_crypto.h"
+#include "em_core.h"
+#include "crypto_management.h"
+
+#include <stdbool.h>
+#include <string.h>
+
+/** ECC big integer type. */
+#define ECC_BIGINT_SIZE_IN_BITS        (256)
+#define ECC_BIGINT_SIZE_IN_BYTES       (ECC_BIGINT_SIZE_IN_BITS/8)
+#define ECC_BIGINT_SIZE_IN_32BIT_WORDS (ECC_BIGINT_SIZE_IN_BYTES/sizeof(uint32_t))
+#define EC_BIGINT_COPY(X, Y) memcpy((X), (Y), sizeof(ecc_bigint_t));
+typedef uint32_t ecc_bigint_t[ECC_BIGINT_SIZE_IN_32BIT_WORDS];
+
+#define SLCL_ECP_CHK(f) do { if( ( ret = (f) ) != 0 ) goto cleanup; } while( 0 )
+
+#if defined(MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT) || defined(MBEDTLS_ECP_NORMALIZE_JAC_ALT)
+#define MPI_TO_BIGINT(bigint, mpi) mpitobigint((bigint), (mpi));
+
+/***************************************************************************//**
+ * @brief
+ *   Convert an mpi number representation to a 32bit word array used by crypto.
+ ******************************************************************************/
+__STATIC_INLINE void mpitobigint( ecc_bigint_t bigint, const mbedtls_mpi* mpi )
+{
+    uint32_t* bi = bigint;
+
+    if ( mpi->n < ECC_BIGINT_SIZE_IN_32BIT_WORDS )
+    {
+      memcpy(bigint, mpi->p, mpi->n * sizeof(uint32_t));
+      memset(&bi[mpi->n],
+             0,
+             ECC_BIGINT_SIZE_IN_BYTES - ( mpi->n * sizeof(uint32_t) ) );
+    }
+    else
+    {
+      /* mpi has more room than bigint, so only store up to sizeof(bigint) */
+      memcpy(bigint, mpi->p, ECC_BIGINT_SIZE_IN_BYTES);
+    }
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Returns true if the value of the DDATA0 register is equal to zero.
+ ******************************************************************************/
+__STATIC_INLINE bool crypto_ddata0_is_zero(CRYPTO_TypeDef* crypto,
+                                           uint32_t*       status_reg)
+{
+  CORE_DECLARE_IRQ_STATE;
+  CORE_ENTER_CRITICAL();
+  CRYPTO_EXECUTE_3(crypto,
+                   CRYPTO_CMD_INSTR_CCLR,
+                   CRYPTO_CMD_INSTR_DEC,  /* Decrement by one which will set
+                                             carry bit if DDATA0 is zero. */
+                   CRYPTO_CMD_INSTR_INC   /* Increment in order to restore
+                                             original value. */
+                   );
+
+  *status_reg = crypto->DSTATUS;
+  CORE_EXIT_CRITICAL();
+
+  return (*status_reg & CRYPTO_DSTATUS_CARRY) == CRYPTO_DSTATUS_CARRY;
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Modular division using CRYPTO hardware acceleration.
+ *
+ * @details
+ *   This function computes R = X/Y mod(N) using CRYPTO hardware acceleration.
+ *   The implementation is not a direct replacement plugin, i.e. alternative
+ *   implementation, of an existing mbedtls function. This function is used
+ *   internally in other CRYPTO plugin functions indirectly replacing
+ *   mbedtls_mpi_inv_mod.
+ *
+ *  @param[in]  X        Dividend of modular division operation
+ *  @param[in]  Y        Divisor of  modular division operation
+ *  @param[in]  N        Modulus
+ *  @param[out] R        The destination of the result
+ *
+ * @return N/A
+ ******************************************************************************/
+static void crypto_mpi_div_mod(CRYPTO_TypeDef *crypto,
+                               ecc_bigint_t   X,
+                               ecc_bigint_t   Y,
+                               ecc_bigint_t   N,
+                               ecc_bigint_t   R)
+{
+    uint32_t            D[9];
+    uint32_t            status_reg;
+    uint8_t             rdata;
+    uint8_t             lsb_C;
+    uint8_t             lsb_D;
+    uint8_t             lsb_U;
+    int                 t;
+    int                 k;
+    CORE_DECLARE_IRQ_STATE;
+
+    /************** Initialize and organize data in crypto module **************/
+
+    /*
+    ** Register usage:
+    **
+    ** DDATA0 - holds temporary results and loads 260 bit variables in/out
+    ** DDATA1 - variable referred to as 'C' in the following algorithm
+    ** DDATA2 - variable referred to as 'U' in the following algorithm
+    ** DDATA3 - variable referred to as 'D' in the following algorithm
+    ** DDATA4 - variable referred to as 'W' in the following algorithm
+    */
+
+    EC_BIGINT_COPY(D, N);             /* D will hold the modulus (n) initially */
+    D[8]=0;                           /* Set MSWord of D to 0. */
+
+    CORE_ENTER_CRITICAL();
+    CRYPTO_DDataWrite(&crypto->DDATA1, Y);  /* Set C to Y (divisor) initially */
+    CRYPTO_DDataWrite(&crypto->DDATA2, X);  /* Set U to X (dividend)initially */
+    CRYPTO_DDataWrite(&crypto->DDATA3, N);  /* Set D to modulus p initially   */
+    CORE_EXIT_CRITICAL();
+
+    CRYPTO_EXECUTE_3(crypto,
+                     CRYPTO_CMD_INSTR_CLR,            /* DDATA0 = 0 */
+                     CRYPTO_CMD_INSTR_DDATA0TODDATA4, /* Set W to zero initially*/
+                     CRYPTO_CMD_INSTR_DDATA1TODDATA0);/* DDATA0 = C initially */
+
+    t     = 0;
+    k     = 1;
+
+    /******************* Run main loop while 'C' is non-zero ********************/
+
+    /* while (C != 1024'd0)  */
+    while ( !crypto_ddata0_is_zero(crypto, &status_reg) )
+    {
+
+        lsb_C = (status_reg & _CRYPTO_DSTATUS_DDATA0LSBS_MASK) >> _CRYPTO_DSTATUS_DDATA0LSBS_SHIFT;
+        if ((lsb_C & 0x1) == 0)
+        {
+            CRYPTO_EXECUTE_3(crypto,
+                             CRYPTO_CMD_INSTR_SELDDATA1DDATA1,
+                             CRYPTO_CMD_INSTR_SHRA,
+                             CRYPTO_CMD_INSTR_DDATA0TODDATA1
+                             );
+            t = t-1;
+        }
+        else
+        {
+            if (t<0)
+            {
+                CRYPTO_EXECUTE_6(crypto,
+                                 CRYPTO_CMD_INSTR_DDATA2TODDATA0,
+                                 CRYPTO_CMD_INSTR_DDATA4TODDATA2,
+                                 CRYPTO_CMD_INSTR_DDATA0TODDATA4,
+                                 CRYPTO_CMD_INSTR_DDATA1TODDATA0,
+                                 CRYPTO_CMD_INSTR_DDATA3TODDATA1,
+                                 CRYPTO_CMD_INSTR_DDATA0TODDATA3);
+                CORE_ENTER_CRITICAL();
+                CRYPTO_DDATA0_260_BITS_READ(crypto, D);
+                CORE_EXIT_CRITICAL();
+                t = -t;
+            }
+
+            k = 1;
+
+            CRYPTO_EXECUTE_2(crypto,
+                             CRYPTO_CMD_INSTR_SELDDATA1DDATA3,
+                             CRYPTO_CMD_INSTR_ADD);
+
+            rdata = CRYPTO_DData0_4LSBitsRead(crypto);
+
+            if((rdata & 0x3) != 0x0)
+              k = -1;
+            else
+              t = t-1;
+
+            /*  R1 = C >> 1  */
+            crypto->CMD = CRYPTO_CMD_INSTR_DDATA1TODDATA0; /* to get the lsb of C */
+
+            lsb_C = CRYPTO_DData0_4LSBitsRead(crypto);
+            CRYPTO_EXECUTE_4(crypto,
+                             CRYPTO_CMD_INSTR_SELDDATA1DDATA1,
+                             CRYPTO_CMD_INSTR_SHRA,
+                             CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+                             CRYPTO_CMD_INSTR_DDATA3TODDATA0); /* to get the lsb of D(R3) */
+
+            /*  R3 = D >> 1  */
+            lsb_D = CRYPTO_DData0_4LSBitsRead(crypto);
+
+            CRYPTO_EXECUTE_2(crypto,
+                             CRYPTO_CMD_INSTR_SELDDATA3DDATA3,
+                             CRYPTO_CMD_INSTR_SHRA);
+
+            if(k == 1)
+            {
+                if (((lsb_C & 0x1)==0x1) && ((lsb_D & 0x1)==0x1))
+                {
+                    CRYPTO_EXECUTE_7(crypto,
+                                     /*  C = R1+R3+1  */
+                                     CRYPTO_CMD_INSTR_SELDDATA0DDATA1,
+                                     CRYPTO_CMD_INSTR_CSET,
+                                     CRYPTO_CMD_INSTR_ADDC,
+                                     CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+                                     /*  U = mod(R2+R4,n)  */
+                                     CRYPTO_CMD_INSTR_SELDDATA2DDATA4,
+                                     CRYPTO_CMD_INSTR_MADD,
+                                     CRYPTO_CMD_INSTR_DDATA0TODDATA2
+                                     );
+                }
+                else
+                {
+                    CRYPTO_EXECUTE_6(crypto,
+                                     /*  C = R1+R3  */
+                                     CRYPTO_CMD_INSTR_SELDDATA0DDATA1,
+                                     CRYPTO_CMD_INSTR_ADD,
+                                     CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+                                     /*  U = mod(R2+R4,n)  */
+                                     CRYPTO_CMD_INSTR_SELDDATA2DDATA4,
+                                     CRYPTO_CMD_INSTR_MADD,
+                                     CRYPTO_CMD_INSTR_DDATA0TODDATA2
+                                     );
+                }
+            }
+            else
+            {
+                if (k == -1)
+                {
+                    if (((lsb_C & 0x1)==0x0) && ((lsb_D & 0x1)==0x1))
+                    {
+                        CRYPTO_EXECUTE_8(crypto,
+                                         /*  C = R1-R3-1  */
+                                         CRYPTO_CMD_INSTR_DDATA0TODDATA3,
+                                         CRYPTO_CMD_INSTR_SELDDATA1DDATA3,
+                                         CRYPTO_CMD_INSTR_CSET,
+                                         CRYPTO_CMD_INSTR_SUBC,
+                                         CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+                                         /*  U = mod(R2-R4,p)  */
+                                         CRYPTO_CMD_INSTR_SELDDATA2DDATA4,
+                                         CRYPTO_CMD_INSTR_MSUB,
+                                         CRYPTO_CMD_INSTR_DDATA0TODDATA2
+                                         );
+                    }
+                    else
+                    {
+                        CRYPTO_EXECUTE_7(crypto,
+                                         /*  C = R1+R3  */
+                                         CRYPTO_CMD_INSTR_DDATA0TODDATA3,
+                                         CRYPTO_CMD_INSTR_SELDDATA1DDATA3,
+                                         CRYPTO_CMD_INSTR_SUB,
+                                         CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+                                         /*  U = mod(R2-R4,p)  */
+                                         CRYPTO_CMD_INSTR_SELDDATA2DDATA4,
+                                         CRYPTO_CMD_INSTR_MSUB,
+                                         CRYPTO_CMD_INSTR_DDATA0TODDATA2
+                                         );
+                    }
+
+                    CRYPTO_DDATA0_260_BITS_WRITE(crypto, D);
+                    crypto->CMD = CRYPTO_CMD_INSTR_DDATA0TODDATA3;
+
+                } /* if (k == -1) */
+            }
+        } /* else: !if((C[31:0] & 0x1) == 0x0) */
+
+        crypto->CMD = CRYPTO_CMD_INSTR_DDATA2TODDATA0;
+
+        lsb_U = CRYPTO_DData0_4LSBitsRead(crypto);
+
+        /* if ((U[31:0] & 0x1) == 0x1) */
+        if((lsb_U & 0x1) == 0x1)
+        {
+            CRYPTO_EXECUTE_3( crypto,
+                              CRYPTO_CMD_INSTR_SELDDATA2DDATA2,
+                              CRYPTO_CMD_INSTR_SHRA,
+                              CRYPTO_CMD_INSTR_DDATA0TODDATA2);
+
+            CORE_ENTER_CRITICAL();
+            CRYPTO_DDataWrite(&crypto->DDATA0, N);
+            CORE_EXIT_CRITICAL();
+
+            CRYPTO_EXECUTE_6( crypto,
+                              CRYPTO_CMD_INSTR_SELDDATA0DDATA0,
+                              CRYPTO_CMD_INSTR_SHR,
+                              CRYPTO_CMD_INSTR_SELDDATA0DDATA2,
+                              CRYPTO_CMD_INSTR_CSET,
+                              CRYPTO_CMD_INSTR_ADDC,
+                              CRYPTO_CMD_INSTR_DDATA0TODDATA2);
+        }
+        else
+        {
+            CRYPTO_EXECUTE_3(crypto,
+                             CRYPTO_CMD_INSTR_SELDDATA2DDATA2,
+                             CRYPTO_CMD_INSTR_SHRA,
+                             CRYPTO_CMD_INSTR_DDATA0TODDATA2);
+        }
+
+        /* DDATA0 = C */
+        crypto->CMD = CRYPTO_CMD_INSTR_DDATA1TODDATA0;
+
+    } /* End of main loop:  while (C != 0)  */
+
+    /* if (D == 1): */
+    /* Decrement D by 1 and test if zero. */
+    CRYPTO_EXECUTE_2(crypto,
+                     CRYPTO_CMD_INSTR_DDATA3TODDATA0,
+                     CRYPTO_CMD_INSTR_DEC);
+
+    if (crypto_ddata0_is_zero(crypto, &status_reg))
+    {
+        CORE_ENTER_CRITICAL();
+        CRYPTO_DDataRead(&crypto->DDATA4, R);
+        CORE_EXIT_CRITICAL();
+    }
+    else
+    {
+        CORE_ENTER_CRITICAL();
+        CRYPTO_DDataWrite(&crypto->DDATA0, N);
+        CORE_EXIT_CRITICAL();
+
+        CRYPTO_EXECUTE_2(crypto,
+                         CRYPTO_CMD_INSTR_SELDDATA0DDATA4,
+                         CRYPTO_CMD_INSTR_SUB
+                         );
+
+        CORE_ENTER_CRITICAL();
+        CRYPTO_DDataRead(&crypto->DDATA0, R);
+        CORE_EXIT_CRITICAL();
+    }
+    return;
+} /* crypto_mpi_div_mod  */
+#endif /* MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT || MBEDTLS_ECP_NORMALIZE_JAC_ALT */
+
+/***************************************************************************//**
+ * @brief
+ *   Enable CRYPTO by setting up control registers for given ecc curve.
+ ******************************************************************************/
+static int crypto_device_init( CRYPTO_TypeDef *device, const mbedtls_ecp_group *grp)
+{
+    int             ret = 0;
+
+    /* Setup CRYPTO registers for ECC operation */
+    device->CTRL     = 0;
+    device->SEQCTRL  = CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES | 32;
+    device->SEQCTRLB = 0;
+
+    switch( grp->id )
+    {
+#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED)
+        case MBEDTLS_ECP_DP_SECP192R1:
+            CRYPTO_ModulusSet( device, cryptoModulusEccP192 );
+            CRYPTO_MulOperandWidthSet( device, cryptoMulOperandModulusBits );
+            CRYPTO_ResultWidthSet( device, cryptoResult256Bits );
+        break;
+#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */
+
+#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED)
+        case MBEDTLS_ECP_DP_SECP224R1:
+            CRYPTO_ModulusSet( device, cryptoModulusEccP224 );
+            CRYPTO_MulOperandWidthSet( device, cryptoMulOperandModulusBits );
+            CRYPTO_ResultWidthSet( device, cryptoResult256Bits );
+        break;
+#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */
+
+#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED)
+        case MBEDTLS_ECP_DP_SECP256R1:
+            CRYPTO_ModulusSet( device, cryptoModulusEccP256 );
+            CRYPTO_MulOperandWidthSet( device, cryptoMulOperandModulusBits );
+            CRYPTO_ResultWidthSet( device, cryptoResult260Bits );
+        break;
+#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */
+
+        default:
+            ret = MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE;
+        break;
+    }
+
+    return( ret );
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Write 256 bits of data to a DDATAX register in the CRYPTO module.
+ *
+ * @details
+ *   Write 256 bits of data into a DDATAX (Double Data) register in the crypto
+ *   module.
+ *
+ *  @param[in]  ddataReg   Data register identifier
+ *  @param[in]  val        Value of the data to write to the DDATA register.
+ ******************************************************************************/
+__STATIC_INLINE void ecp_crypto_ddata_write(CRYPTO_DDataReg_TypeDef  ddataReg,
+                                            const mbedtls_mpi*       mpi)
+{
+  uint32_t volatile* regPtr = (volatile uint32_t *) ddataReg;
+  uint32_t* pVal = mpi->p;
+  register uint32_t v0;
+  register uint32_t v1;
+  register uint32_t v2;
+  register uint32_t v3;
+  int      i;
+
+  if (mpi->n <4)
+  {
+    /* Non optimal write of data. */
+    for (i=0; i<(int)mpi->n; i++)
+      *regPtr = *pVal++;
+    for (; i<8; i++)
+      *regPtr = 0;
+  }
+  else
+  {
+    if (mpi->n < 8)
+    {
+      /* Optimal write of first 4 words. */
+      v0 = *pVal++;
+      v1 = *pVal++;
+      v2 = *pVal++;
+      v3 = *pVal++;
+      *regPtr = v0;
+      *regPtr = v1;
+      *regPtr = v2;
+      *regPtr = v3;
+
+      /* Non optimal write of remaining words */
+      for (i=4; i<(int)mpi->n; i++)
+        *regPtr = *pVal++;
+      for (; i<8; i++)
+        *regPtr = 0;
+    }
+    else
+    {
+      /* Optimal write of all data. */
+      v0 = *pVal++;
+      v1 = *pVal++;
+      v2 = *pVal++;
+      v3 = *pVal++;
+      *regPtr = v0;
+      *regPtr = v1;
+      *regPtr = v2;
+      *regPtr = v3;
+
+      v0 = *pVal++;
+      v1 = *pVal++;
+      v2 = *pVal++;
+      v3 = *pVal++;
+      *regPtr = v0;
+      *regPtr = v1;
+      *regPtr = v2;
+      *regPtr = v3;
+    }
+  }
+}
+
+/***************************************************************************//**
+ * @brief
+ *   Read 256 bits of data from a DDATAX register in the CRYPTO module.
+ *
+ * @details
+ *   Read 256 bits of data from a DDATAX (Double Data) register in the crypto
+ *   module.
+ *
+ *  @param[in]  ddataReg   Data register identifier
+ *  @param[out] val        Location where to store the value in memory.
+ ******************************************************************************/
+
+__STATIC_INLINE int ecp_crypto_ddata_read(CRYPTO_DDataReg_TypeDef  ddataReg,
+                                          mbedtls_mpi*             mpi)
+{
+  CRYPTO_DData_TypeDef  ddata;
+  uint32_t              val32;
+  int                   i;
+  int                   used;
+  int                   ret = 0;
+  CORE_DECLARE_IRQ_STATE;
+
+  if (mpi->n == 8)
+  {
+    CORE_ENTER_CRITICAL();
+    CRYPTO_DDataRead(ddataReg, mpi->p);
+    CORE_EXIT_CRITICAL();
+  }
+  else
+  {
+    if (mpi->n > 8)
+    {
+      CORE_ENTER_CRITICAL();
+      CRYPTO_DDataRead(ddataReg, mpi->p);
+      CORE_EXIT_CRITICAL();
+      memset(&mpi->p[8], 0, sizeof(uint32_t)*(mpi->n-8));
+    }
+    else
+    {
+      uint32_t volatile* regPtr = (volatile uint32_t*) ddataReg;
+      used = 0;
+      for (i=0; i<8; i++)
+      {
+        ddata[i] = val32 = *regPtr;
+        if (val32)
+          used = i+1;
+      }
+      if (used > (int)mpi->n)
+      {
+        SLCL_ECP_CHK( mbedtls_mpi_grow(mpi, used) );
+        memcpy(mpi->p, ddata, used*sizeof(uint32_t));
+        mpi->s = 1;
+      }
+      else
+      {
+        memcpy(mpi->p, ddata, mpi->n*sizeof(uint32_t));
+      }
+    }
+  }
+ cleanup:
+  return( ret );
+}
+
+/**
+ * \brief           Indicate if the Elliptic Curve Point module extension can
+ *                  handle the group.
+ *
+ * \param grp       The pointer to the elliptic curve group that will be the
+ *                  basis of the cryptographic computations.
+ *
+ * \return          Non-zero if successful.
+ */
+unsigned char mbedtls_internal_ecp_grp_capable( const mbedtls_ecp_group *grp )
+{
+    switch( grp->id )
+    {
+#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED)
+        case MBEDTLS_ECP_DP_SECP192R1:
+            return( true );
+#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */
+
+#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED)
+        case MBEDTLS_ECP_DP_SECP224R1:
+            return( true );
+#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */
+
+#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED)
+        case MBEDTLS_ECP_DP_SECP256R1:
+            return( true );
+#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */
+
+        default:
+            return( false );
+    }
+}
+
+/**
+ * \brief           Initialise the Elliptic Curve Point module extension.
+ *
+ *                  If mbedtls_internal_ecp_grp_capable returns true for a
+ *                  group, this function has to be able to initialise the
+ *                  module for it.
+ *
+ *                  This module can be a driver to a crypto hardware
+ *                  accelerator, for which this could be an initialise function.
+ *
+ * \param grp       The pointer to the group the module needs to be
+ *                  initialised for.
+ *
+ * \return          0 if successful.
+ */
+int mbedtls_internal_ecp_init( const mbedtls_ecp_group *grp )
+{
+    /* Crypto operations are atomic, so no need to setup any context here */
+    (void) grp;
+    return 0;
+}
+
+/**
+ * \brief           Frees and deallocates the Elliptic Curve Point module
+ *                  extension.
+ *
+ * \param grp       The pointer to the group the module was initialised for.
+ */
+void mbedtls_internal_ecp_free( const mbedtls_ecp_group *grp )
+{
+    /* Crypto operations are atomic, so no need to free any context here */
+    (void) grp;
+}
+
+#if defined(MBEDTLS_ECP_RANDOMIZE_JAC_ALT)
+/**
+ * \brief           Randomize jacobian coordinates:
+ *                  (X, Y, Z) -> (l^2 X, l^3 Y, l Z) for random l.
+ *
+ * \param grp       Pointer to the group representing the curve.
+ *
+ * \param pt        The point on the curve to be randomised, given with Jacobian
+ *                  coordinates.
+ *
+ * \param f_rng     A function pointer to the random number generator.
+ *
+ * \param p_rng     A pointer to the random number generator state.
+ *
+ * \return          0 if successful.
+ */
+int mbedtls_internal_ecp_randomize_jac( const mbedtls_ecp_group *grp,
+                                        mbedtls_ecp_point *pt,
+                                        int (*f_rng)(void *, unsigned char *, size_t),
+                                        void *p_rng )
+{
+    int ret;
+    ecc_bigint_t l;
+    CORE_DECLARE_IRQ_STATE;
+    CRYPTO_TypeDef *crypto;
+
+    /* Strategy:
+     *  1) Generate l such that 1 < l < p
+     *  2) Z = l (R1) * Z (R4)
+     *  3) ll (R1) = l (R4) * l
+     *  4) X = ll (R1) * X (R2)
+     *  5) lll (R1) = ll (R1) * l (R4)
+     *  6) Y = lll (R1) * Y (R3)
+     */
+
+    /* Acquire entropy before grabbing crypto, since the entropy function might use crypto */
+    /* Generate l such that 1 < l < p */
+    ret = f_rng(p_rng, (unsigned char *)l, sizeof(l));
+    if ( ret != 0 ) {
+        return( ret );
+    }
+
+    crypto = crypto_management_acquire();
+    crypto_device_init(crypto, grp);
+
+    CORE_ENTER_CRITICAL();
+    CRYPTO_DDataWrite(&crypto->DDATA1, l);
+    ecp_crypto_ddata_write(&crypto->DDATA2, &pt->X);
+    ecp_crypto_ddata_write(&crypto->DDATA3, &pt->Y);
+    ecp_crypto_ddata_write(&crypto->DDATA4, &pt->Z);
+    CORE_EXIT_CRITICAL();
+
+    /* Z = l * Z */
+    CRYPTO_EXECUTE_2 (  crypto,
+                        CRYPTO_CMD_INSTR_SELDDATA1DDATA4,
+                        CRYPTO_CMD_INSTR_MMUL );
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    MBEDTLS_MPI_CHK( ecp_crypto_ddata_read(&crypto->DDATA0, &pt->Z) );
+
+    /* X = l^2 * X */
+    CRYPTO_EXECUTE_6 (  crypto,
+                        CRYPTO_CMD_INSTR_DDATA1TODDATA4,
+                        CRYPTO_CMD_INSTR_SELDDATA1DDATA4,
+                        CRYPTO_CMD_INSTR_MMUL,
+                        CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+                        CRYPTO_CMD_INSTR_SELDDATA1DDATA2,
+                        CRYPTO_CMD_INSTR_MMUL );
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    MBEDTLS_MPI_CHK( ecp_crypto_ddata_read(&crypto->DDATA0, &pt->X) );
+
+    /* Y = l^3 * Y */
+    CRYPTO_EXECUTE_5 (  crypto,
+                        CRYPTO_CMD_INSTR_SELDDATA1DDATA4,
+                        CRYPTO_CMD_INSTR_MMUL,
+                        CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+                        CRYPTO_CMD_INSTR_SELDDATA1DDATA3,
+                        CRYPTO_CMD_INSTR_MMUL );
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    MBEDTLS_MPI_CHK( ecp_crypto_ddata_read(&crypto->DDATA0, &pt->Y) );
+
+cleanup:
+    crypto_management_release( crypto );
+    return( ret );
+}
+#endif
+
+#if defined(MBEDTLS_ECP_ADD_MIXED_ALT)
+/**
+ * \brief           Addition: R = P + Q, mixed affine-Jacobian coordinates.
+ *
+ *                  The coordinates of Q must be normalized (= affine),
+ *                  but those of P don't need to. R is not normalized.
+ *
+ *                  This function is used only as a subrutine of
+ *                  ecp_mul_comb().
+ *
+ *                  Special cases: (1) P or Q is zero, (2) R is zero,
+ *                      (3) P == Q.
+ *                  None of these cases can happen as intermediate step in
+ *                  ecp_mul_comb():
+ *                      - at each step, P, Q and R are multiples of the base
+ *                      point, the factor being less than its order, so none of
+ *                      them is zero;
+ *                      - Q is an odd multiple of the base point, P an even
+ *                      multiple, due to the choice of precomputed points in the
+ *                      modified comb method.
+ *                  So branches for these cases do not leak secret information.
+ *
+ *                  We accept Q->Z being unset (saving memory in tables) as
+ *                  meaning 1.
+ *
+ *                  Cost in field operations if done by [5] 3.22:
+ *                      1A := 8M + 3S
+ *
+ * \param grp       Pointer to the group representing the curve.
+ *
+ * \param R         Pointer to a point structure to hold the result.
+ *
+ * \param P         Pointer to the first summand, given with Jacobian
+ *                  coordinates
+ *
+ * \param Q         Pointer to the second summand, given with affine
+ *                  coordinates.
+ *
+ * \return          0 if successful.
+ */
+int mbedtls_internal_ecp_add_mixed( const mbedtls_ecp_group *grp,
+                                    mbedtls_ecp_point *R,
+                                    const mbedtls_ecp_point *P,
+                                    const mbedtls_ecp_point *Q )
+{
+    int             ret;
+    CORE_DECLARE_IRQ_STATE;
+    CRYPTO_TypeDef *crypto = crypto_management_acquire();
+
+    crypto_device_init(crypto, grp);
+
+    /*
+      STEP 1:
+
+      Goals:
+      A = Qx*Pz^2
+      B = Qy*Pz^3
+
+      Write Operations:
+
+      R0 = Pz
+      R0 = Qx
+      R0 = Qy
+
+      Instructions to be executed:
+
+      1. R0 = DMA = Pz
+      2. R1 = R0 = Pz
+      3. R2 = R0 = Pz
+      4. Select R1, R2
+      5. R0 = R1 * R2 = Pz^2
+      6. R1 = R0 = Pz^2
+
+      7.  R0 = DMA = Qx
+      8.  R3 = R0 = Qx
+      9.  Select R1, R3
+      10. R0 = R1 * R3 = Qx * Pz^2
+      11. R3 = R0 = Qx * Pz^2
+
+      12. Select R1, R2
+      13. R0 = R1 * R2 = Pz^3
+      14. R1 = R0 = Pz^3
+
+      15. R0 = DMA = Qy
+      16. R4 = R0 = Qx
+      17. Select R1, R4
+      18. R0 = R1 * R4 = Qy * Pz^3
+      19. Select R0, R1  (for MSUB in step 2)
+
+      Output State:
+      R0   = B
+      R1   = FREE
+      R2   = FREE
+      R3   = A
+      R4   = Pz
+
+      STEP 1:
+    */
+    CORE_ENTER_CRITICAL();
+    ecp_crypto_ddata_write(&crypto->DDATA0, &P->Z);
+    CORE_EXIT_CRITICAL();
+
+    CRYPTO_EXECUTE_5(crypto,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA4,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA4,
+                      CRYPTO_CMD_INSTR_MMUL,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA1);
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    CORE_ENTER_CRITICAL();
+    ecp_crypto_ddata_write(&crypto->DDATA0, &Q->X);
+    CORE_EXIT_CRITICAL();
+
+    CRYPTO_EXECUTE_4 (crypto,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA3,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA3,
+                      CRYPTO_CMD_INSTR_MMUL,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA3);
+    CRYPTO_InstructionSequenceWait(crypto);
+    CRYPTO_EXECUTE_3 (crypto,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA4,
+                      CRYPTO_CMD_INSTR_MMUL,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA1);
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    CORE_ENTER_CRITICAL();
+    ecp_crypto_ddata_write(&crypto->DDATA0, &Q->Y);
+    CORE_EXIT_CRITICAL();
+
+    CRYPTO_EXECUTE_3 (crypto,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA2,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA2,
+                      CRYPTO_CMD_INSTR_MMUL
+                      );
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    /*
+      STEP 2:
+
+      Goals:
+      C  = A - Px
+      D  = B - Py
+      R->Z = Pz * C
+
+      Write Operations:
+
+      R1 = Py
+      R0 = Px (via DMA)
+
+      Input State:
+      R0   = B
+      R1   = Py
+      R2   = FREE
+      R3   = A
+      R4   = Pz
+
+      Instructions to be executed:
+
+      0. Select R0, R1
+      1. R0 = R0 - R1 = B - Py = D
+      2. R2 = R0 = D
+      3. R1 = R3 = A
+      4. R0 = DMA = Px
+      5. R3 = R0 = Px
+      6. Select R1, R3
+      7. R0 = R1 - R3 = A - Px = C
+      8. R1 = R0 = C
+      9. Select R1, R4
+      10. R0 = R1 * R4 = Pz * C = R->Z
+
+      Read Operations:
+
+      R->Z = R0 = Pz * C
+
+      Output State:
+      R0   = FREE
+      R1   = C
+      R2   = D
+      R3   = Px
+      R4   = FREE
+
+      STEP 2:
+    */
+
+    CORE_ENTER_CRITICAL();
+    ecp_crypto_ddata_write(&crypto->DDATA1, &P->Y);
+    CORE_EXIT_CRITICAL();
+
+    CRYPTO_EXECUTE_3 (crypto,
+                      CRYPTO_CMD_INSTR_SELDDATA0DDATA1,
+                      CRYPTO_CMD_INSTR_MSUB,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA2); /* R2 = D */
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    CORE_ENTER_CRITICAL();
+    ecp_crypto_ddata_write(&crypto->DDATA0, &P->X);
+    CORE_EXIT_CRITICAL();
+
+    CRYPTO_EXECUTE_7 (crypto,
+                      CRYPTO_CMD_INSTR_DDATA3TODDATA1,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA3,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA3,
+                      CRYPTO_CMD_INSTR_MSUB,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA1,  /* R1 = C */
+
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA4,
+                      CRYPTO_CMD_INSTR_MMUL
+                      );
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    ret = ecp_crypto_ddata_read(&crypto->DDATA0, &R->Z);
+
+    if (ret != 0) goto cleanup;
+
+    /*
+      STEP 3:
+
+      Goals:
+      X1C2  = Px * C^2
+      C3    = C^3
+      D2    = D^2
+
+      Input State:
+      R0   = FREE
+      R1   = C
+      R2   = D
+      R3   = Px
+      R4   = FREE
+
+      Instructions to be executed:
+
+      1. R4 = R1 = C
+      2. Select R1, R4
+      3. R0 = R1 * R4 = C^2
+      4. R1 = R0 = C^2
+      5. R0 = R1 * R4 = C^3
+      6. R4 = R0 = C^3
+      7. Select R1, R3
+      8. R0 = R1 * R3 = Px * C^2
+      9. R3 = R0 = Px * C^2
+      10. R1 = R2 = D
+      11. Select R1, R1
+      12. R0 = R1 * R1 = D^2
+      13. Select R0, R4
+      14. R0 = R0 - R4 = D2 - C3
+
+      Output state:
+
+      R0 = D2 - C3
+      R1 = FREE
+      R2 = D
+      R3 = X1C2 = Px * C^2
+      R4 = C3   = C^3
+
+      STEP 3:
+    */
+    CRYPTO_EXECUTE_3 (crypto,
+                      CRYPTO_CMD_INSTR_DDATA1TODDATA4,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA4,
+                      CRYPTO_CMD_INSTR_MMUL);
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    CRYPTO_EXECUTE_3 (crypto,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+                      CRYPTO_CMD_INSTR_MMUL,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA4);
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    CRYPTO_EXECUTE_3 (crypto,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA3,
+                      CRYPTO_CMD_INSTR_MMUL,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA3);
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    CRYPTO_EXECUTE_5 (crypto,
+                      CRYPTO_CMD_INSTR_DDATA2TODDATA1,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA2,
+                      CRYPTO_CMD_INSTR_MMUL,
+                      CRYPTO_CMD_INSTR_SELDDATA0DDATA4,
+                      CRYPTO_CMD_INSTR_MSUB
+                      );
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    /*
+      STEP 3:
+
+      Goals:
+      R->X   = D2 - (C3 + 2 * X1C2) = D2 - C3 - X1C2- X1C2
+      Y1C3 = Py * C3
+      R->Y = D * (X1C2 - R->X) - Y1C3
+
+      Write Operations:
+      R1 = Py
+
+      Input State:
+      R0 = D2 - C3
+      R1 = FREE
+      R2 = D
+      R3 = X1C2
+      R4 = C3
+
+      Instructions to be executed:
+
+      1.  Select R0, R3
+      2.  R0 = R0 - R3 = D2 - C3 - X1C2
+      3.  R0 = R0 - R3 = D2 - C3 - X1C2 - X1C2 = R->X
+      4.  DMA = R0 = R->X
+      5.  R1 = R0 = R->X
+
+      6.  Select R3, R1
+      7.  R0 = R3 - R1 = X1C2 - R->X
+      8.  R1 = R0 = X1C2 - R->X
+      9.  Select R1, R2
+      10. R0 = R1 * R2 = D *(X1C2 - R->X)
+      11. R2 = R0
+
+      12. R0 = DMA = Py
+      13. R1 = R0 = Py
+      14. Select R1, R4
+      15. R0 = R1 * R4 = Py * C3 = Y1C3
+      16. R4 = R0 = Y1C3
+
+      17. Select R2, R4
+      18. R0 = R2 - R4
+
+      Read Operations:
+
+      R->X = R2 = D2 - (C3 + 2 * X1C2)
+      R->Y = R0 = D * (X1C2 - R->X) - Y1C3
+
+      STEP 4:
+    */
+
+    CRYPTO_EXECUTE_3 (crypto,
+                      CRYPTO_CMD_INSTR_SELDDATA0DDATA3,
+                      CRYPTO_CMD_INSTR_MSUB,
+                      CRYPTO_CMD_INSTR_MSUB);
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    ret = ecp_crypto_ddata_read(&crypto->DDATA0, &R->X);
+    if ( ret != 0 ) goto cleanup;
+
+    CRYPTO_EXECUTE_7 (crypto,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+
+                      CRYPTO_CMD_INSTR_SELDDATA3DDATA1,
+                      CRYPTO_CMD_INSTR_MSUB,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA2,
+                      CRYPTO_CMD_INSTR_MMUL,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA2);
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    CORE_ENTER_CRITICAL();
+    ecp_crypto_ddata_write(&crypto->DDATA0, &P->Y);
+    CORE_EXIT_CRITICAL();
+
+    CRYPTO_EXECUTE_6 (crypto,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA4,
+                      CRYPTO_CMD_INSTR_MMUL,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA4,
+
+                      CRYPTO_CMD_INSTR_SELDDATA2DDATA4,
+                      CRYPTO_CMD_INSTR_MSUB
+                      );
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    ret = ecp_crypto_ddata_read(&crypto->DDATA0, &R->Y);
+    if ( ret != 0 ) goto cleanup;
+
+ cleanup:
+    crypto_management_release( crypto );
+    return ( ret );
+}
+#endif
+
+/**
+ * \brief           Point doubling R = 2 P, Jacobian coordinates.
+ *
+ *                  Cost:   1D := 3M + 4S    (A ==  0)
+ *                          4M + 4S          (A == -3)
+ *                          3M + 6S + 1a     otherwise
+ *                  when the implementation is based on the "dbl-1998-cmo-2"
+ *                  doubling formulas in [8] and standard optimizations are
+ *                  applied when curve parameter A is one of { 0, -3 }.
+ *
+ * \param grp       Pointer to the group representing the curve.
+ *
+ * \param R         Pointer to a point structure to hold the result.
+ *
+ * \param P         Pointer to the point that has to be doubled, given with
+ *                  Jacobian coordinates.
+ *
+ * \return          0 if successful.
+ */
+#if defined(MBEDTLS_ECP_DOUBLE_JAC_ALT)
+int mbedtls_internal_ecp_double_jac( const mbedtls_ecp_group *grp,
+                                     mbedtls_ecp_point *R,
+                                     const mbedtls_ecp_point *P )
+{
+    int             ret;
+    CORE_DECLARE_IRQ_STATE;
+    CRYPTO_TypeDef *crypto = crypto_management_acquire();
+
+    crypto_device_init(crypto, grp);
+
+    ecc_bigint_t _2YY;
+    /*
+      STEP 1:
+
+      Goals:
+      ZZ   = Z^2
+      R->Z = 2 * Y * Z
+      YY   = Y^2
+      4YY  = 4 * Y^2
+
+      Write Operations:
+
+      R2 = Y
+      R3 = Z
+
+      Instructions to be executed:
+
+      1.  R0 = DMA = Z
+      2.  R1 = R0 = Z
+      3.  R2 = R0 = Z
+      4.  Select R1, R2
+      5.  R0 = R1 * R2 = Z^2 = ZZ
+      6.  R3 = R0 = ZZ
+
+      7.  R0 = DMA = Y
+      8.  R2 = R0 = Y
+      9.  R0 = R1 * R2 = Y * Z
+      10. Select R0, R0
+      11. R0 = R0 + R0 = 2 * Y * Z = R->Z
+
+      12. DMA = R0 = R->Z
+
+      13. R1 = R2 = Y
+      14. Select R1, R2
+      15. R0 = R1 * R2 = Y^2 = YY
+      16.  Select R0, R0
+      17.  R0 = R0 + R0 = 2YY
+
+      Read Operations:
+
+      R->Z = R0 = 2 * Y * Z
+      2YY  = R0
+
+      Output State:
+      R0 = 2YY
+      R1 = FREE
+      R2 = FREE
+      R3 = ZZ
+      R4 = FREE
+
+      STEP 1:
+    */
+    CORE_ENTER_CRITICAL();
+    ecp_crypto_ddata_write(&crypto->DDATA0, &P->Z);
+    CORE_EXIT_CRITICAL();
+
+    CRYPTO_EXECUTE_5 (crypto,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA2,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA2,
+                      CRYPTO_CMD_INSTR_MMUL,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA3);
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    CORE_ENTER_CRITICAL();
+    ecp_crypto_ddata_write(&crypto->DDATA0, &P->Y);
+    CORE_EXIT_CRITICAL();
+
+    CRYPTO_EXECUTE_4 (crypto,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA2,
+                      CRYPTO_CMD_INSTR_MMUL,
+                      CRYPTO_CMD_INSTR_SELDDATA0DDATA0,
+                      CRYPTO_CMD_INSTR_MADD);
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    ret = ecp_crypto_ddata_read(&crypto->DDATA0, &R->Z);
+    if ( ret != 0 ) goto cleanup;
+
+    CRYPTO_EXECUTE_5 (crypto,
+                      CRYPTO_CMD_INSTR_DDATA2TODDATA1,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA2,
+                      CRYPTO_CMD_INSTR_MMUL,
+                      CRYPTO_CMD_INSTR_SELDDATA0DDATA0,
+                      CRYPTO_CMD_INSTR_MADD
+                      );
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    CORE_ENTER_CRITICAL();
+    ecp_crypto_ddata_write(&crypto->DDATA4, &P->X);
+    CRYPTO_DDataRead(&crypto->DDATA0, _2YY);
+    CORE_EXIT_CRITICAL();
+
+    /*
+      STEP 2:
+
+      Goals:
+      A   = 4YY * X
+      C   = 3(X - ZZ)(X + ZZ)
+
+      Write Operations:
+
+      R4 = X
+
+      Input State:
+      R0 = 2YY
+      R1 = FREE
+      R2 = FREE
+      R3 = ZZ
+      R4 = X
+
+      Instructions to be executed:
+
+      1.  R0 = R0 + R0 = 4YY
+      2.  R1 = R0 = 4YY
+      3.  Select R1, R4
+      4.  R0 = R1 * R4 = 4YY * X = A
+      5.  R2 = R0 = A
+      6.  Select R4, R3
+      7.  R0 = R4 + R3 = X + ZZ
+      8.  R1 = R0 = X + ZZ
+      9.  R0 = R4 - R3 = X - ZZ
+      0.  R2 = R0 = X - ZZ
+      11. Select R1, R2
+      12. R0 = R1 * R2 = (X + ZZ)(X - ZZ)
+      13. R1 = R0 = (X + ZZ)(X - ZZ)
+      14. Select R0, R1
+      15. R0 = R0 + R1 = 2(X + ZZ)(X - ZZ)
+      16. R0 = R0 + R1 = 3(X + ZZ)(X - ZZ) = C
+      17. R1 = R0 = C
+
+      Output State:
+      R0 = FREE
+      R1 = C
+      R2 = A
+      R3 = FREE
+      R4 = FREE
+
+      STEP 2:
+    */
+    CRYPTO_EXECUTE_11(crypto,
+                      CRYPTO_CMD_INSTR_SELDDATA0DDATA0,
+                      CRYPTO_CMD_INSTR_MADD,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA4,
+                      CRYPTO_CMD_INSTR_MMUL,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA2,
+                      CRYPTO_CMD_INSTR_SELDDATA4DDATA3,
+                      CRYPTO_CMD_INSTR_MADD,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+                      CRYPTO_CMD_INSTR_MSUB,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA4);
+    CRYPTO_InstructionSequenceWait(crypto);
+    CRYPTO_EXECUTE_7 (crypto,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA4,
+                      CRYPTO_CMD_INSTR_MMUL,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+                      CRYPTO_CMD_INSTR_SELDDATA0DDATA1,
+                      CRYPTO_CMD_INSTR_MADD,
+                      CRYPTO_CMD_INSTR_MADD,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA1
+                      );
+    CRYPTO_InstructionSequenceWait(crypto);
+    /*
+      STEP 3:
+
+      Goals:
+      R->X = C^2 - 2A
+      D = C(A - R->X)
+
+      Input State:
+      R0 = FREE
+      R1 = C
+      R2 = A
+      R3 = FREE
+      R4 = FREE
+
+      Instructions to be executed:
+
+      1.  R4 = R1 = C
+      2.  Select R1, R4
+      3.  R0 = R1 * R4 = C^2
+      4.  Select R0, R2
+      5.  R0 = R0 - R2 = C^2 - 2A = R->X
+      6.  R4 = R0 = R->X
+      7.  Select R3, R4
+      8.  R0 = R3 - R4 = A - R->X
+      9.  R2 = R0 = A - R->X
+      10  Select R1, R2
+      11. R0 = R1 * R2 = C(A - R->X) = D
+
+      Read Operations:
+
+      R->X = R4 = C^2 - 2A
+
+      Output State:
+      R0   = FREE
+      R1   = FREE
+      R2   = FREE
+      R3   = D
+      R4   = FREE
+
+      STEP 3:
+    */
+
+    CRYPTO_EXECUTE_8 (crypto,
+                      CRYPTO_CMD_INSTR_SELDDATA2DDATA2,
+                      CRYPTO_CMD_INSTR_MADD,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA4,
+
+                      CRYPTO_CMD_INSTR_DDATA1TODDATA3,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA3,
+                      CRYPTO_CMD_INSTR_MMUL,
+
+                      CRYPTO_CMD_INSTR_SELDDATA0DDATA4,
+                      CRYPTO_CMD_INSTR_MSUB);
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    ret = ecp_crypto_ddata_read(&crypto->DDATA0, &R->X);
+    if ( ret != 0 ) goto cleanup;
+
+    CRYPTO_EXECUTE_7 (crypto,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA4,
+
+                      CRYPTO_CMD_INSTR_SELDDATA2DDATA4,
+                      CRYPTO_CMD_INSTR_MSUB,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA2,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA2,
+                      CRYPTO_CMD_INSTR_MMUL,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA3
+                      );
+    CRYPTO_InstructionSequenceWait(crypto);
+
+
+    /*
+      STEP 4:
+
+      Goals:
+      B    = 8 * Y^4
+      R->Y = D - B
+
+      Write Operations:
+
+      R1 = YY
+
+      Input State:
+      R0   = FREE
+      R1   = YY
+      R2   = FREE
+      R3   = D
+      R4   = FREE
+
+      Instructions to be executed:
+
+      2. R0 = DMA0
+      3. R1 = R0 = Y^2
+      4. R2 = R0 = Y^2
+      5. Select R1, R2
+      6. R0 = R1 * R2 = Y^4
+      7. Select R0, R0
+      8. R0 = R0 + R0 = 2 * Y^4
+      9. R0 = R0 + R0 = 4 * Y^4
+      10. R0 = R0 + R0 = 8 * Y^4
+      11. R2 = R0
+      12. Select R3, R2
+      13. R0 = R3 - R2 = D - B = R->Y
+
+      Read Operations:
+
+      R->Y = R0 = D - B
+
+      STEP 4:
+    */
+    CORE_ENTER_CRITICAL();
+    CRYPTO_DDataWrite(&crypto->DDATA0, _2YY);
+    CORE_EXIT_CRITICAL();
+
+    CRYPTO_EXECUTE_9 (crypto,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA2,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA2,
+                      CRYPTO_CMD_INSTR_MMUL,
+
+                      CRYPTO_CMD_INSTR_SELDDATA0DDATA0,
+                      CRYPTO_CMD_INSTR_MADD,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA2,
+
+                      CRYPTO_CMD_INSTR_SELDDATA3DDATA2,
+                      CRYPTO_CMD_INSTR_MSUB
+                      );
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    ret = ecp_crypto_ddata_read(&crypto->DDATA0, &R->Y);
+    if ( ret != 0 ) goto cleanup;
+
+ cleanup:
+    crypto_management_release( crypto );
+
+    return ( ret );
+}
+#endif
+
+/**
+ * \brief           Normalize jacobian coordinates of an array of (pointers to)
+ *                  points.
+ *
+ *                  Using Montgomery's trick to perform only one inversion mod P
+ *                  the cost is:
+ *                      1N(t) := 1I + (6t - 3)M + 1S
+ *                  (See for example Algorithm 10.3.4. in [9])
+ *
+ *                  This function is used only as a subrutine of
+ *                  ecp_mul_comb().
+ *
+ *                  Warning: fails (returning an error) if one of the points is
+ *                  zero!
+ *                  This should never happen, see choice of w in ecp_mul_comb().
+ *
+ * \param grp       Pointer to the group representing the curve.
+ *
+ * \param T         Array of pointers to the points to normalise.
+ *
+ * \param t_len     Number of elements in the array.
+ *
+ * \return          0 if successful,
+ *                      an error if one of the points is zero.
+ */
+#if defined(MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT)
+int mbedtls_internal_ecp_normalize_jac_many( const mbedtls_ecp_group *grp,
+                                             mbedtls_ecp_point *T[],
+                                             size_t t_len )
+{
+    int ret = 0;
+    size_t i;
+    ecc_bigint_t*   cc;
+    ecc_bigint_t    uu;
+    ecc_bigint_t    one;
+    ecc_bigint_t    modulus;
+    CORE_DECLARE_IRQ_STATE;
+
+    if( t_len < 2 )
+        return( mbedtls_internal_ecp_normalize_jac( grp, *T ) );
+
+    if( ( cc = mbedtls_calloc( t_len, sizeof( ecc_bigint_t ) ) ) == NULL )
+        return( MBEDTLS_ERR_ECP_ALLOC_FAILED );
+
+    /*
+     * c[i] = Z_0 * ... * Z_i
+     */
+    MPI_TO_BIGINT( cc[0], &T[0]->Z );
+
+    CRYPTO_TypeDef *crypto = crypto_management_acquire();
+    crypto_device_init(crypto, grp);
+
+    for( i = 1; i < t_len; i++ )
+    {
+        CORE_ENTER_CRITICAL();
+        ecp_crypto_ddata_write( &crypto->DDATA1, &T[i]->Z );
+        CRYPTO_DDataWrite( &crypto->DDATA2, cc[i-1] );
+        CORE_EXIT_CRITICAL();
+
+        CRYPTO_EXECUTE_2(crypto,
+                         CRYPTO_CMD_INSTR_SELDDATA1DDATA2,
+                         CRYPTO_CMD_INSTR_MMUL);
+        CRYPTO_InstructionSequenceWait(crypto);
+
+        CORE_ENTER_CRITICAL();
+        CRYPTO_DDataRead( &crypto->DDATA0, cc[i] );
+        CORE_EXIT_CRITICAL();
+    }
+
+    memset(one, 0, sizeof(one));
+    one[0]=1;
+    MPI_TO_BIGINT( modulus, &grp->P );
+
+    /*
+     * u = 1 / (Z_0 * ... * Z_n) mod P
+     */
+    crypto_mpi_div_mod(crypto, one, cc[t_len-1], modulus, uu);
+
+    for( i = t_len - 1; ; i-- )
+    {
+        /*
+         * Zi = 1 / Z_i mod p
+         * u = 1 / (Z_0 * ... * Z_i) mod P
+         */
+        if( i == 0 )
+        {
+            /* Z_inv (DDATA2) = uu */
+            CORE_ENTER_CRITICAL();
+            CRYPTO_DDataWrite(&crypto->DDATA2, uu);
+            CORE_EXIT_CRITICAL();
+        }
+        else
+        {
+            /* Z_inv (DDATA1) = uu x cc[i-1] modulo p */
+            /* uu = uu x T[i]->Z modulo p */
+            CORE_ENTER_CRITICAL();
+            CRYPTO_DDataWrite(&crypto->DDATA1, uu);
+            CRYPTO_DDataWrite(&crypto->DDATA2, cc[i-1]);
+            ecp_crypto_ddata_write( &crypto->DDATA3, &T[i]->Z );
+            CORE_EXIT_CRITICAL();
+
+            CRYPTO_EXECUTE_3(crypto,
+                             CRYPTO_CMD_INSTR_SELDDATA1DDATA2,
+                             CRYPTO_CMD_INSTR_MMUL,
+                             CRYPTO_CMD_INSTR_DDATA0TODDATA2); /* Z_inv (DDATA2) */
+            CRYPTO_InstructionSequenceWait(crypto);
+            CRYPTO_EXECUTE_2(crypto,
+                             CRYPTO_CMD_INSTR_SELDDATA1DDATA3,
+                             CRYPTO_CMD_INSTR_MMUL);
+            CRYPTO_InstructionSequenceWait(crypto);
+
+            CORE_ENTER_CRITICAL();
+            CRYPTO_DDataRead(&crypto->DDATA0, uu);
+            CORE_EXIT_CRITICAL();
+        }
+
+        /*
+         * proceed as in normalize()
+         */
+        CORE_ENTER_CRITICAL();
+        ecp_crypto_ddata_write(&crypto->DDATA3, &T[i]->X);
+        ecp_crypto_ddata_write(&crypto->DDATA4, &T[i]->Y);
+        CORE_EXIT_CRITICAL();
+
+        /* Z_inv  already in DDATA2 */
+        CRYPTO_EXECUTE_3 (crypto,
+                          CRYPTO_CMD_INSTR_DDATA2TODDATA1,
+                          CRYPTO_CMD_INSTR_SELDDATA1DDATA2,
+                          CRYPTO_CMD_INSTR_MMUL);
+        CRYPTO_InstructionSequenceWait(crypto);
+        CRYPTO_EXECUTE_3 (crypto,
+                          CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+                          CRYPTO_CMD_INSTR_SELDDATA1DDATA3,
+                          CRYPTO_CMD_INSTR_MMUL);
+        CRYPTO_InstructionSequenceWait(crypto);
+        CRYPTO_EXECUTE_3 (crypto,
+                          CRYPTO_CMD_INSTR_DDATA0TODDATA3,
+                          CRYPTO_CMD_INSTR_SELDDATA1DDATA2,
+                          CRYPTO_CMD_INSTR_MMUL);
+        CRYPTO_InstructionSequenceWait(crypto);
+        CRYPTO_EXECUTE_3 (crypto,
+                          CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+                          CRYPTO_CMD_INSTR_SELDDATA1DDATA4,
+                          CRYPTO_CMD_INSTR_MMUL);
+        CRYPTO_InstructionSequenceWait(crypto);
+
+        ecp_crypto_ddata_read(&crypto->DDATA0, &T[i]->Y);
+        ecp_crypto_ddata_read(&crypto->DDATA3, &T[i]->X);
+
+        /*
+         * Post-precessing: reclaim some memory by shrinking coordinates
+         * - not storing Z (always 1)
+         * - shrinking other coordinates, but still keeping the same number of
+         *   limbs as P, as otherwise it will too likely be regrown too fast.
+         */
+        SLCL_ECP_CHK( mbedtls_mpi_shrink( &T[i]->X, grp->P.n ) );
+        SLCL_ECP_CHK( mbedtls_mpi_shrink( &T[i]->Y, grp->P.n ) );
+        mbedtls_mpi_free( &T[i]->Z );
+
+        if( i == 0 )
+            break;
+    }
+
+ cleanup:
+    crypto_management_release( crypto );
+    mbedtls_free( cc );
+
+    return( ret );
+}
+#endif
+
+/**
+ * \brief           Normalize jacobian coordinates so that Z == 0 || Z == 1.
+ *
+ *                  Cost in field operations if done by [5] 3.2.1:
+ *                      1N := 1I + 3M + 1S
+ *
+ * \param grp       Pointer to the group representing the curve.
+ *
+ * \param pt        pointer to the point to be normalised. This is an
+ *                  input/output parameter.
+ *
+ * \return          0 if successful.
+ */
+#if defined(MBEDTLS_ECP_NORMALIZE_JAC_ALT)
+int mbedtls_internal_ecp_normalize_jac( const mbedtls_ecp_group *grp,
+                                        mbedtls_ecp_point *pt )
+{
+    int             ret      = 0;
+    CORE_DECLARE_IRQ_STATE;
+    CRYPTO_TypeDef *crypto = crypto_management_acquire();
+
+    crypto_device_init(crypto, grp);
+
+    ecc_bigint_t    one;
+    ecc_bigint_t    Z;
+    ecc_bigint_t    modulus;
+    ecc_bigint_t    Z_inv;
+
+    memset(one, 0, sizeof(one));
+    one[0]=1;
+
+    MPI_TO_BIGINT( Z, &pt->Z );
+    MPI_TO_BIGINT( modulus, &grp->P );
+
+    crypto_mpi_div_mod(crypto, one, Z, modulus, Z_inv);
+
+    /*
+
+    Goals:
+    R->X = P->X * Z_inv ^2
+    R->Y = P->Y * Z_inv ^3
+
+    Write Operations:
+
+    R1 = Z_inv
+    R3 = P->X
+    R4 = P->Y
+
+    Instructions to be executed:
+
+    1.  R2 = R1 = Z_inv
+    2.  Select R1, R2
+    3.  R0 = R1 * R2 = Z_inv^2
+    4.  R1 = R0 = Z_inv^2
+    5.  Select R1, R3
+    6.  R0 = R1 * R3 = P->X * Z_inv^2 = R->X
+    7.  R3 = R0
+    8.  Select R1, R2
+    9.  R0 = R1 * R2 = Z_inv^3
+    10. R1 = R0 = Z_inv^3
+    11. Select R1, R4
+    12. R0 = R1 * R4 = P->Y * Z_inv^3 = R->Y
+
+    Read Operations:
+
+    R->Y = R0 = P->Y * P->Z_inv^3
+    R->X = R3 = P->X * P->Z_inv^2
+
+    */
+    CORE_ENTER_CRITICAL();
+    CRYPTO_DDataWrite(&crypto->DDATA1, Z_inv);
+    ecp_crypto_ddata_write(&crypto->DDATA3, &pt->X);
+    ecp_crypto_ddata_write(&crypto->DDATA4, &pt->Y);
+    CORE_EXIT_CRITICAL();
+
+    CRYPTO_EXECUTE_3 (crypto,
+                      CRYPTO_CMD_INSTR_DDATA1TODDATA2,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA2,
+                      CRYPTO_CMD_INSTR_MMUL);
+    CRYPTO_InstructionSequenceWait(crypto);
+    CRYPTO_EXECUTE_3 (crypto,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA3,
+                      CRYPTO_CMD_INSTR_MMUL);
+    CRYPTO_InstructionSequenceWait(crypto);
+    CRYPTO_EXECUTE_3 (crypto,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA3,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA2,
+                      CRYPTO_CMD_INSTR_MMUL);
+    CRYPTO_InstructionSequenceWait(crypto);
+    CRYPTO_EXECUTE_3 (crypto,
+                      CRYPTO_CMD_INSTR_DDATA0TODDATA1,
+                      CRYPTO_CMD_INSTR_SELDDATA1DDATA4,
+                      CRYPTO_CMD_INSTR_MMUL);
+    CRYPTO_InstructionSequenceWait(crypto);
+
+    ecp_crypto_ddata_read(&crypto->DDATA0, &pt->Y);
+    ecp_crypto_ddata_read(&crypto->DDATA3, &pt->X);
+
+    crypto_management_release( crypto );
+
+    /*
+     * Z = 1
+     */
+    SLCL_ECP_CHK( mbedtls_mpi_lset( &pt->Z, 1 ) );
+
+ cleanup:
+    return( ret );
+}
+#endif
+
+#endif /* #if defined( MBEDTLS_ECP_INTERNAL_ALT ) */
+
+#endif /* #if defined( MBEDTLS_ECP_C ) */
+
+#endif /* #if defined( CRYPTO_PRESENT ) */
diff --git a/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_management.c b/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_management.c
new file mode 100644
index 00000000000..b49fe089313
--- /dev/null
+++ b/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_management.c
@@ -0,0 +1,403 @@
+/*
+ *  Silicon Labs CRYPTO device management interface.
+ *
+ *  Copyright (C) 2016, Silicon Labs, http://www.silabs.com
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ */
+
+#include "crypto_management.h"
+#include "em_core.h"
+#include "em_bus.h"
+
+#if defined( CRYPTO_PRESENT )
+
+/* Conversion macro for compatibility with the 5.3.x release of the Gecko SDK */
+#if defined( MBEDTLS_CRYPTO_DEVICE_PREEMPTION )
+#warning "MBEDTLS_CRYPTO_DEVICE_PREEMPTION is deprecated, please define " \
+         "CRYPTO_DEVICE_PREEMPTION instead."
+#endif
+
+#if defined( MBEDTLS_THREADING_C )
+#include "mbedtls/threading.h"
+static mbedtls_threading_mutex_t    crypto_locks[CRYPTO_COUNT];
+static volatile bool                crypto_locks_initialized = false;
+static unsigned int                 acquire_count = 0U;
+#endif /* MBEDTLS_THREADING_C */
+
+#if defined( CRYPTO_DEVICE_PREEMPTION )
+/** Preemptable context of CRYPTO hardware module. */
+typedef struct
+{
+    uint32_t CTRL;          /*!< Control Register  */
+    uint32_t WAC;           /*!< Wide Arithmetic Configuration  */
+    uint32_t SEQCTRL;       /*!< Sequence Control  */
+    uint32_t SEQCTRLB;      /*!< Sequence Control B  */
+    uint32_t IEN;           /*!< Interrupt Enable Register  */
+    uint32_t SEQ[5];        /*!< Instruction Sequence registers */
+    CRYPTO_Data260_TypeDef DDATA[5]; /*!< DDATA registers. Covers all data
+                                        registers
+                                        of CRYPTO, including DATA(128 bit),
+                                        DDATA (256bit/260bit),
+                                        QDATA (512bit) registers. */
+    uint32_t regmask;       /*!< Bitmask for which registers to save */
+    uint32_t operands;      /*!< Saving the currently selected operands */
+    bool carry;             /*!< Saving the status of the carry flag */
+} crypto_context_t;
+
+static crypto_context_t preemption_context;
+static bool             is_preempted = false;
+static CORE_DECLARE_IRQ_STATE;
+#endif /* CRYPTO_DEVICE_PREEMPTION */
+
+typedef enum
+{
+#if defined( CRYPTO0 )
+    CRYPTO0_ID = 0,
+#elif defined( CRYPTO )
+    CRYPTO_ID = 0,
+#endif
+#if defined( CRYPTO1 )
+    CRYPTO1_ID = 1,
+#endif
+} crypto_instance_number_t;
+
+typedef struct {
+    CRYPTO_TypeDef *device;
+    uint32_t clockMask;
+} crypto_device_t;
+
+static const crypto_device_t crypto_devices[CRYPTO_COUNT] =
+{
+#if defined( CRYPTO0 )
+    {
+        CRYPTO0,
+        _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT
+    },
+#elif defined( CRYPTO )
+    {
+        CRYPTO,
+        _CMU_HFBUSCLKEN0_CRYPTO_SHIFT
+    },
+#endif
+#if defined( CRYPTO1 )
+    {
+        CRYPTO1,
+        _CMU_HFBUSCLKEN0_CRYPTO1_SHIFT
+    },
+#endif
+};
+
+static inline int crypto_management_index_by_device( CRYPTO_TypeDef *device )
+{
+#if defined( CRYPTO0 )
+    if ( device == CRYPTO0 ) return 0;
+#elif defined( CRYPTO )
+    if ( device == CRYPTO ) return 0;
+#endif
+#if defined( CRYPTO1 )
+    if ( device == CRYPTO1 ) return 1;
+#endif
+    return -1;
+}
+
+/* Use bitband for clock enable/disable operations, such that they are atomic */
+#define CRYPTO_CLOCK_ENABLE(clk)  BUS_RegBitWrite(&(CMU->HFBUSCLKEN0), (clk), 1)
+#define CRYPTO_CLOCK_DISABLE(clk) BUS_RegBitWrite(&(CMU->HFBUSCLKEN0), (clk), 0)
+#define CRYPTO_CLOCK_ENABLED(clk) BUS_RegBitRead(&(CMU->HFBUSCLKEN0), (clk))
+
+/* Get ownership of an available crypto device */
+CRYPTO_TypeDef *crypto_management_acquire( void )
+{
+    CRYPTO_TypeDef *device = NULL;
+
+#if defined( MBEDTLS_THREADING_C )
+    /* Initialize mutexes if that hasn't happened yet */
+    CORE_DECLARE_IRQ_STATE;
+
+    if ( !crypto_locks_initialized ) {
+        CORE_ENTER_CRITICAL();
+        if ( !crypto_locks_initialized ) {
+            for ( int i = 0; i < CRYPTO_COUNT; i++ ) {
+                mbedtls_mutex_init(&crypto_locks[i]);
+            }
+            crypto_locks_initialized = true;
+        }
+        CORE_EXIT_CRITICAL();
+    }
+
+/* Wrapping this in SL_THREADING_ALT pending non-blocking mutex in official
+ * threading API. */
+#if defined( SL_THREADING_ALT )
+    /* Try to take an available crypto instance */
+    unsigned int devno = 0;
+    for ( ; devno < CRYPTO_COUNT; devno++ ) {
+        if ( 0 == THREADING_TakeMutexNonBlocking(&crypto_locks[devno]) ) {
+            device = crypto_devices[devno].device;
+            break;
+        }
+    }
+#endif // SL_THREADING_ALT
+
+    /* If no device immediately available, do naieve round-robin */
+    if ( device == NULL ) {
+        devno = acquire_count % CRYPTO_COUNT;
+        mbedtls_mutex_lock( &crypto_locks[devno] );
+        device = crypto_devices[devno].device;
+    }
+
+    /* Doing this outside of critical section is safe, since we own the lock
+     * and are using bitband to poke the clock enable bit */
+    CRYPTO_CLOCK_ENABLE( crypto_devices[devno].clockMask );
+
+    acquire_count++;
+#else // !MBEDTLS_THREADING_C
+    device = crypto_devices[0].device;
+    CRYPTO_CLOCK_ENABLE( crypto_devices[0].clockMask );
+#endif // MBEDTLS_THREADING_C
+
+    return device;
+}
+
+/* Get ownership of the default crypto device (CRYPTO0/CRYPTO) */
+CRYPTO_TypeDef *crypto_management_acquire_default( void )
+{
+    CRYPTO_TypeDef *device = NULL;
+
+#if defined( MBEDTLS_THREADING_C )
+    /* Initialize mutexes if that hasn't happened yet */
+    CORE_DECLARE_IRQ_STATE;
+
+    if ( !crypto_locks_initialized ) {
+        CORE_ENTER_CRITICAL();
+        if ( !crypto_locks_initialized ) {
+            for ( int i = 0; i < CRYPTO_COUNT; i++ ) {
+                mbedtls_mutex_init(&crypto_locks[i]);
+            }
+            crypto_locks_initialized = true;
+        }
+        CORE_EXIT_CRITICAL();
+    }
+
+    mbedtls_mutex_lock( &crypto_locks[0] );
+    device = crypto_devices[0].device;
+
+    /* Doing this outside of critical section is safe, since we own the lock
+     * and are using bitband to poke the clock enable bit */
+    CRYPTO_CLOCK_ENABLE( crypto_devices[0].clockMask );
+#else // !MBEDTLS_THREADING_C
+    device = crypto_devices[0].device;
+    CRYPTO_CLOCK_ENABLE( crypto_devices[0].clockMask );
+#endif // MBEDTLS_THREADING_C
+
+    return device;
+}
+
+/* Release ownership of an available crypto device */
+void crypto_management_release( CRYPTO_TypeDef *device )
+{
+    int devno = crypto_management_index_by_device( device );
+    if ( devno < 0 ) {
+        return;
+    }
+
+    /* Doing this outside of critical section is safe, since we still own the lock
+     * and are using bitband to poke the clock enable bit */
+    CRYPTO_CLOCK_DISABLE( crypto_devices[devno].clockMask );
+
+#if defined ( MBEDTLS_THREADING_C )
+    mbedtls_mutex_unlock( &crypto_locks[devno] );
+#endif
+}
+
+/* Acquire a device with preemption. NOT thread-safe! */
+CRYPTO_TypeDef *crypto_management_acquire_preemption( uint32_t regmask )
+{
+#if defined( CRYPTO_DEVICE_PREEMPTION )
+    CRYPTO_TypeDef *device = NULL;
+    /* Turn off interrupts */
+    CORE_ENTER_CRITICAL();
+
+    /* Check if there is an unused CRYPTO instance */
+    for ( int i = 0; i < CRYPTO_COUNT; i++ ) {
+        if ( !CRYPTO_CLOCK_ENABLED( crypto_devices[i].clockMask ) ) {
+            /* Found an unused device */
+            CRYPTO_CLOCK_ENABLE( crypto_devices[i].clockMask );
+            device = crypto_devices[i].device;
+            break;
+        }
+    }
+
+    /* If there is no unused instance, preempt the last one */
+    if ( device == NULL ) {
+        is_preempted = true;
+        device = crypto_devices[CRYPTO_COUNT - 1].device;
+
+        /* In case this instance is still working on anything */
+        CRYPTO_InstructionSequenceWait(device);
+
+        /* Store operational context */
+        preemption_context.regmask  = regmask;
+        preemption_context.WAC      = device->WAC;
+        preemption_context.CTRL     = device->CTRL;
+        preemption_context.SEQCTRL  = device->SEQCTRL;
+        preemption_context.SEQCTRLB = device->SEQCTRLB;
+        preemption_context.IEN      = device->IEN;
+        preemption_context.operands = device->CSTATUS;
+        preemption_context.carry    = (device->DSTATUS & CRYPTO_DSTATUS_CARRY) != 0;
+
+        if ( (preemption_context.WAC & _CRYPTO_WAC_RESULTWIDTH_MASK) == CRYPTO_WAC_RESULTWIDTH_260BIT)
+        {
+            CRYPTO_DData0Read260(device, preemption_context.DDATA[0]); /* Always save DDATA0 because it'll get clobbered in 260-bit mode*/
+
+            if ( (regmask & CRYPTO_MANAGEMENT_SAVE_DDATA1) != 0 ) {
+                device->CMD = CRYPTO_CMD_INSTR_DDATA1TODDATA0; /* Move DDATA1 to DDATA0
+                                                                  in order to read. */
+                CRYPTO_DData0Read260(device, preemption_context.DDATA[1]);
+            }
+            if ( (regmask & CRYPTO_MANAGEMENT_SAVE_DDATA2) != 0 ) {
+                device->CMD = CRYPTO_CMD_INSTR_DDATA2TODDATA0; /* Move DDATA2 to DDATA0
+                                                                  in order to read. */
+                CRYPTO_DData0Read260(device, preemption_context.DDATA[2]);
+            }
+            if ( (regmask & CRYPTO_MANAGEMENT_SAVE_DDATA3) != 0 ) {
+                device->CMD = CRYPTO_CMD_INSTR_DDATA3TODDATA0; /* Move DDATA3 to DDATA0
+                                                                  in order to read. */
+                CRYPTO_DData0Read260(device, preemption_context.DDATA[3]);
+            }
+            if ( (regmask & CRYPTO_MANAGEMENT_SAVE_DDATA4) != 0 ) {
+                device->CMD = CRYPTO_CMD_INSTR_DDATA4TODDATA0; /* Move DDATA4 to DDATA0
+                                                                  in order to read. */
+                CRYPTO_DData0Read260(device, preemption_context.DDATA[4]);
+            }
+        }
+        else
+        {
+            if ( (regmask & CRYPTO_MANAGEMENT_SAVE_DDATA0) != 0 )
+                CRYPTO_DDataRead(&device->DDATA0, preemption_context.DDATA[0]);
+            if ( (regmask & CRYPTO_MANAGEMENT_SAVE_DDATA1) != 0 )
+                CRYPTO_DDataRead(&device->DDATA1, preemption_context.DDATA[1]);
+            if ( (regmask & CRYPTO_MANAGEMENT_SAVE_DDATA2) != 0 )
+                CRYPTO_DDataRead(&device->DDATA2, preemption_context.DDATA[2]);
+            if ( (regmask & CRYPTO_MANAGEMENT_SAVE_DDATA3) != 0 )
+                CRYPTO_DDataRead(&device->DDATA3, preemption_context.DDATA[3]);
+            if ( (regmask & CRYPTO_MANAGEMENT_SAVE_DDATA4) != 0 )
+                CRYPTO_DDataRead(&device->DDATA4, preemption_context.DDATA[4]);
+        }
+
+        /* Search for possible EXEC commands and replace with END. */
+        for ( size_t j = 0; j < (regmask & 0x7U)*sizeof(uint32_t); j++ ) {
+            if ( (j & 0x03) == 0 ) {
+                preemption_context.SEQ[j / sizeof(uint32_t)] = *((&device->SEQ0) + (j / sizeof(uint32_t)));
+            }
+            if ( ((uint8_t*)preemption_context.SEQ)[j] == CRYPTO_CMD_INSTR_EXEC ) {
+                ((uint8_t*)preemption_context.SEQ)[j] = CRYPTO_CMD_INSTR_END;
+            }
+        }
+    }
+
+    return device;
+#else
+    (void) regmask;
+    return crypto_management_acquire();
+#endif
+}
+
+/* Release a device from preemption */
+void crypto_management_release_preemption( CRYPTO_TypeDef *device )
+{
+    if ( crypto_management_index_by_device( device ) < 0 ) {
+        return;
+    }
+#if defined( CRYPTO_DEVICE_PREEMPTION )
+
+    if ( is_preempted ) {
+        /* If we preempted something, put their context back */
+        device->WAC      = preemption_context.WAC;
+        device->CTRL     = preemption_context.CTRL;
+        device->SEQCTRL  = preemption_context.SEQCTRL;
+        device->SEQCTRLB = preemption_context.SEQCTRLB;
+        device->IEN      = preemption_context.IEN;
+
+        if ( (preemption_context.WAC & _CRYPTO_WAC_RESULTWIDTH_MASK) == CRYPTO_WAC_RESULTWIDTH_260BIT)
+        {
+            /* Start by writing the DDATA1 value to DDATA0 and move to DDATA1. */
+            if ( (preemption_context.regmask & CRYPTO_MANAGEMENT_SAVE_DDATA1) != 0 ) {
+                CRYPTO_DData0Write260(device, preemption_context.DDATA[1]);
+                device->CMD = CRYPTO_CMD_INSTR_DDATA0TODDATA1;
+            }
+
+            /* Write the DDATA2 value to DDATA0 and move to DDATA2. */
+            if ( (preemption_context.regmask & CRYPTO_MANAGEMENT_SAVE_DDATA2) != 0 ) {
+                CRYPTO_DData0Write260(device, preemption_context.DDATA[2]);
+                device->CMD = CRYPTO_CMD_INSTR_DDATA0TODDATA2;
+            }
+
+            /* Write the DDATA3 value to DDATA0 and move to DDATA3. */
+            if ( (preemption_context.regmask & CRYPTO_MANAGEMENT_SAVE_DDATA3) != 0 ) {
+                CRYPTO_DData0Write260(device, preemption_context.DDATA[3]);
+                device->CMD = CRYPTO_CMD_INSTR_DDATA0TODDATA3;
+            }
+
+            /* Write the DDATA4 value to DDATA0 and move to DDATA4. */
+            if ( (preemption_context.regmask & CRYPTO_MANAGEMENT_SAVE_DDATA4) != 0 ) {
+                CRYPTO_DData0Write260(device, preemption_context.DDATA[4]);
+                device->CMD = CRYPTO_CMD_INSTR_DDATA0TODDATA4;
+            }
+
+            /* Finally write DDATA0 */
+            CRYPTO_DData0Write260(device, preemption_context.DDATA[0]);
+        }
+        else
+        {
+            if ( (preemption_context.regmask & CRYPTO_MANAGEMENT_SAVE_DDATA0) != 0 )
+                CRYPTO_DDataWrite(&device->DDATA0, preemption_context.DDATA[0]);
+            if ( (preemption_context.regmask & CRYPTO_MANAGEMENT_SAVE_DDATA1) != 0 )
+                CRYPTO_DDataWrite(&device->DDATA1, preemption_context.DDATA[1]);
+            if ( (preemption_context.regmask & CRYPTO_MANAGEMENT_SAVE_DDATA2) != 0 )
+                CRYPTO_DDataWrite(&device->DDATA2, preemption_context.DDATA[2]);
+            if ( (preemption_context.regmask & CRYPTO_MANAGEMENT_SAVE_DDATA3) != 0 )
+                CRYPTO_DDataWrite(&device->DDATA3, preemption_context.DDATA[3]);
+            if ( (preemption_context.regmask & CRYPTO_MANAGEMENT_SAVE_DDATA4) != 0 )
+                CRYPTO_DDataWrite(&device->DDATA4, preemption_context.DDATA[4]);
+        }
+
+        if (preemption_context.carry) {
+            device->CMD = CRYPTO_CMD_INSTR_CSET;
+        } else {
+            device->CMD = CRYPTO_CMD_INSTR_CCLR;
+        }
+
+        device->CMD = (preemption_context.operands & 0x7U) |
+                      (((preemption_context.operands >> 8) & 0x7U) << 3) |
+                      0xC0;
+
+        for (size_t i = 0; i < (preemption_context.regmask & 0x7U); i++ ) {
+            *((&device->SEQ0) + i) = preemption_context.SEQ[i];
+        }
+
+        is_preempted = false;
+    } else {
+        /* If we didn't preempt anything, turn crypto clock back off */
+        CRYPTO_CLOCK_DISABLE( crypto_devices[crypto_management_index_by_device( device )].clockMask );
+    }
+
+    /* Turn interrupts back on */
+    CORE_EXIT_CRITICAL();
+#else
+    crypto_management_release(device);
+#endif
+}
+
+#endif /* CRYPTO_PRESENT */
diff --git a/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_management.h b/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_management.h
new file mode 100644
index 00000000000..b1a4e9f151f
--- /dev/null
+++ b/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_management.h
@@ -0,0 +1,128 @@
+/*
+ *  Silicon Labs CRYPTO device management interface.
+ *
+ *  Copyright (C) 2016, Silicon Labs, http://www.silabs.com
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ */
+
+#ifndef CRYPTO_MANAGEMENT_H
+#define CRYPTO_MANAGEMENT_H
+
+/***************************************************************************//**
+ * \addtogroup sl_crypto
+ * \{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * \addtogroup sl_crypto_management CRYPTO peripheral instance management
+ * \brief Management functions for CRYPTO peripherals. These functions take care
+ *        of not having two 'owners' simultaneously for the same peripheral,
+ *        potentially messing up the internal state of said peripheral.
+ * \{
+ ******************************************************************************/
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "mbedtls/config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include <stdlib.h>
+
+#include "em_device.h"
+
+#if defined( CRYPTO_PRESENT )
+#include "em_crypto.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Save DDATA0 register when preempting */
+#define CRYPTO_MANAGEMENT_SAVE_DDATA0 (0x1U << 3)
+/** Save DDATA1 register when preempting */
+#define CRYPTO_MANAGEMENT_SAVE_DDATA1 (0x1U << 4)
+/** Save DDATA2 register when preempting */
+#define CRYPTO_MANAGEMENT_SAVE_DDATA2 (0x1U << 5)
+/** Save DDATA3 register when preempting */
+#define CRYPTO_MANAGEMENT_SAVE_DDATA3 (0x1U << 6)
+/** Save DDATA4 register when preempting */
+#define CRYPTO_MANAGEMENT_SAVE_DDATA4 (0x1U << 7)
+/** Save SEQ0 register when preempting */
+#define CRYPTO_MANAGEMENT_SAVE_UPTO_SEQ0 (0x1U)
+/** Save SEQ0 through SEQ1 register when preempting */
+#define CRYPTO_MANAGEMENT_SAVE_UPTO_SEQ1 (0x2U)
+/** Save SEQ0 through SEQ2 register when preempting */
+#define CRYPTO_MANAGEMENT_SAVE_UPTO_SEQ2 (0x3U)
+/** Save SEQ0 through SEQ3 register when preempting */
+#define CRYPTO_MANAGEMENT_SAVE_UPTO_SEQ3 (0x4U)
+/** Save SEQ0 through SEQ4 register when preempting */
+#define CRYPTO_MANAGEMENT_SAVE_UPTO_SEQ4 (0x5U)
+
+/**
+ * \brief		   Get ownership of a CRYPTO peripheral
+ *
+ * \return         Handle of assigned CRYPTO peripheral
+ */
+CRYPTO_TypeDef *crypto_management_acquire( void );
+
+/**
+ * \brief		   Get ownership of the default CRYPTO peripheral
+ *
+ * \return         Handle of default CRYPTO peripheral
+ */
+CRYPTO_TypeDef *crypto_management_acquire_default( void );
+
+/**
+ * \brief          Release ownership of a CRYPTO peripheral
+ *
+ * \param device   Handle of CRYPTO peripheral to be released
+ */
+void crypto_management_release( CRYPTO_TypeDef *device );
+
+/**
+ * \brief          Acquire preempting ownership of a CRYPTO peripheral.
+ *                 NOTE: this function is not meant for general use, it
+ *                 is not thread-safe, and must be called form the
+ *                 highest priority thread/interrupt allowed to use mbed TLS.
+ *
+ * \param regmask  Bitmask of CRYPTO_MANAGEMENT_ defines instructing what
+ *                 parts of the device state will be clobbered during
+ *                 preemption.
+ *
+ * \return         Handle of assigned CRYPTO peripheral
+ */
+CRYPTO_TypeDef *crypto_management_acquire_preemption( uint32_t regmask );
+
+/**
+ * \brief          Releasing preempting ownership of a CRYPTO peripheral.
+ *                 NOTE: this function is not meant for general use, it
+ *                 is not thread-safe, and must be called form the
+ *                 highest priority thread/interrupt allowed to use mbed TLS.
+ *
+ * \param device   Handle of preempted CRYPTO peripheral to be released
+ */
+void crypto_management_release_preemption( CRYPTO_TypeDef *device );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CRYPTO_PRESENT */
+
+/** \} (end addtogroup sl_crypto_management) */
+/** \} (end addtogroup sl_crypto) */
+
+#endif /* CRYPTO_MANAGEMENT_H */
\ No newline at end of file
diff --git a/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_sha.c b/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_sha.c
new file mode 100644
index 00000000000..64d03989237
--- /dev/null
+++ b/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_sha.c
@@ -0,0 +1,467 @@
+/*
+ *  FIPS-180-2 compliant SHA-1 & SHA-256 implementation
+ *
+ *  Copyright (C) 2016, Silicon Labs, http://www.silabs.com
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ */
+/*
+ * This file includes an alternative implementation of the standard
+ * mbedtls/libary/sha[1][256].c using the CRYPTO hardware accelerator incorporated
+ * in MCU devices from Silicon Laboratories.
+ */
+/*
+ *  The SHA-1 standard was published by NIST in 1993.
+ *
+ *  http://www.itl.nist.gov/fipspubs/fip180-1.htm
+ *
+ *  The SHA-256 Secure Hash Standard was published by NIST in 2002.
+ *
+ *  http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf
+ */
+
+#if !defined(MBEDTLS_CONFIG_FILE)
+#include "mbedtls/config.h"
+#else
+#include MBEDTLS_CONFIG_FILE
+#endif
+
+#include "mbedtls/sha1.h"
+#include "mbedtls/sha256.h"
+
+#if ( defined(MBEDTLS_SHA256_ALT) && defined(MBEDTLS_SHA256_C) ) || ( defined(MBEDTLS_SHA1_ALT) && defined (MBEDTLS_SHA1_C) )
+
+#include "em_device.h"
+
+#if defined(CRYPTO_PRESENT)
+#include "em_crypto.h"
+#include "em_core.h"
+#include "crypto_management.h"
+#include "em_assert.h"
+#include <string.h>
+
+#define CRYPTO_SHA_BLOCK_SIZE (64)
+
+#if defined(MBEDTLS_SHA1_C)
+static const uint32_t init_state_sha1[8] =
+{
+    0x67452301UL,
+    0xEFCDAB89UL,
+    0x98BADCFEUL,
+    0x10325476UL,
+    0xC3D2E1F0UL,
+    0x0UL,
+    0x0UL,
+    0x0UL
+};
+#endif /* defined(MBEDTLS_SHA1_C) */
+
+#if defined(MBEDTLS_SHA256_C)
+static const uint32_t init_state_sha256[8] =
+{
+    0x6A09E667UL,
+    0xBB67AE85UL,
+    0x3C6EF372UL,
+    0xA54FF53AUL,
+    0x510E527FUL,
+    0x9B05688CUL,
+    0x1F83D9ABUL,
+    0x5BE0CD19UL
+};
+
+static const uint32_t init_state_sha224[8] =
+{
+    0xC1059ED8UL,
+    0x367CD507UL,
+    0x3070DD17UL,
+    0xF70E5939UL,
+    0xFFC00B31UL,
+    0x68581511UL,
+    0x64F98FA7UL,
+    0xBEFA4FA4UL
+};
+#endif /* defined(MBEDTLS_SHA256_C) */
+
+static const unsigned char sha_padding[64] =
+{
+ 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+typedef enum {
+#if defined(MBEDTLS_SHA1_C)
+    CRYPTO_SHA1,
+#endif /* defined(MBEDTLS_SHA1_C) */
+#if defined(MBEDTLS_SHA256_C)
+    CRYPTO_SHA2
+#endif /* defined(MBEDTLS_SHA256_C) */
+} crypto_sha_mode_t;
+
+/*
+ * 32-bit integer manipulation macros (big endian)
+ */
+#ifndef PUT_UINT32_BE
+#define PUT_UINT32_BE(n,b,i)                            \
+do {                                                    \
+    (b)[(i)    ] = (unsigned char) ( (n) >> 24 );       \
+    (b)[(i) + 1] = (unsigned char) ( (n) >> 16 );       \
+    (b)[(i) + 2] = (unsigned char) ( (n) >>  8 );       \
+    (b)[(i) + 3] = (unsigned char) ( (n)       );       \
+} while( 0 )
+#endif
+
+/**
+ * @brief unified SHA acceleration function.
+ *
+ * @param[inout] state  State context for SHA hashing
+ * @param[in] data      Input block(s). Must contain N blocks
+ *                      of SHA1/SHA256 block size (64 bytes)
+ * @param blocks        Amount of blocks pointed to by data
+ * @param mode          SHA operation mode
+ */
+static void crypto_sha_update_state( uint32_t state[8],
+                                     const unsigned char *data,
+                                     size_t blocks,
+                                     crypto_sha_mode_t mode )
+{
+    CORE_DECLARE_IRQ_STATE;
+    CRYPTO_TypeDef *crypto = crypto_management_acquire();
+
+    switch ( mode ) {
+#if defined(MBEDTLS_SHA1_C)
+        case CRYPTO_SHA1:
+            crypto->CTRL = CRYPTO_CTRL_SHA_SHA1;
+            break;
+#endif /* defined(MBEDTLS_SHA1_C) */
+#if defined(MBEDTLS_SHA256_C)
+        case CRYPTO_SHA2:
+            crypto->CTRL = CRYPTO_CTRL_SHA_SHA2;
+            break;
+#endif /* defined(MBEDTLS_SHA256_C) */
+    }
+
+    crypto->WAC      = 0;
+    crypto->IEN      = 0;
+
+    /* Set result width of MADD32 operation. */
+    CRYPTO_ResultWidthSet(crypto, cryptoResult256Bits);
+
+    /* Clear sequence control registers */
+    crypto->SEQCTRL  = 0;
+    crypto->SEQCTRLB = 0;
+
+    /* Put the state back */
+    CORE_ENTER_CRITICAL();
+    CRYPTO_DDataWrite(&crypto->DDATA1, state);
+    CORE_EXIT_CRITICAL();
+
+    CRYPTO_EXECUTE_3( crypto,
+                      CRYPTO_CMD_INSTR_DDATA1TODDATA0,
+                      CRYPTO_CMD_INSTR_DDATA1TODDATA2,
+                      CRYPTO_CMD_INSTR_SELDDATA0DDATA1 );
+
+    /* Load the data block(s) */
+    for ( size_t i = 0; i < blocks; i++ ) {
+        if ((uint32_t)(&data[i*CRYPTO_SHA_BLOCK_SIZE]) & 0x3)
+        {
+            uint32_t temp[CRYPTO_SHA_BLOCK_SIZE/sizeof(uint32_t)];
+            memcpy(temp, &data[i*CRYPTO_SHA_BLOCK_SIZE], CRYPTO_SHA_BLOCK_SIZE);
+            CORE_ENTER_CRITICAL();
+            CRYPTO_QDataWrite(&crypto->QDATA1BIG, temp);
+            CORE_EXIT_CRITICAL();
+        }
+        else
+        {
+            CORE_ENTER_CRITICAL();
+            CRYPTO_QDataWrite(&crypto->QDATA1BIG,
+                              (uint32_t*) &data[i*CRYPTO_SHA_BLOCK_SIZE]);
+            CORE_EXIT_CRITICAL();
+        }
+
+        /* Process the data block */
+        CRYPTO_EXECUTE_3(  crypto,
+                           CRYPTO_CMD_INSTR_SHA,
+                           CRYPTO_CMD_INSTR_MADD32,
+                           CRYPTO_CMD_INSTR_DDATA0TODDATA1 );
+    }
+    CORE_ENTER_CRITICAL();
+    CRYPTO_DDataRead(&crypto->DDATA0, state);
+    CORE_EXIT_CRITICAL();
+
+    crypto_management_release( crypto );
+}
+
+#if defined(MBEDTLS_SHA256_ALT) && defined(MBEDTLS_SHA256_C)
+void mbedtls_sha256_init( mbedtls_sha256_context *ctx )
+{
+    if( ctx == NULL ) {
+        return;
+    }
+
+    memset( ctx, 0, sizeof( mbedtls_sha256_context ) );
+}
+
+void mbedtls_sha256_free( mbedtls_sha256_context *ctx )
+{
+    if( ctx == NULL ) {
+        return;
+    }
+
+    memset( ctx, 0, sizeof( mbedtls_sha256_context ) );
+}
+
+void mbedtls_sha256_clone( mbedtls_sha256_context *dst,
+                           const mbedtls_sha256_context *src )
+{
+    if ( dst != NULL && src != NULL ) {
+        *dst = *src;
+    }
+}
+
+/*
+ * SHA-256 context setup
+ */
+void mbedtls_sha256_starts( mbedtls_sha256_context *ctx, int is224 )
+{
+    ctx->total[0] = 0;
+    ctx->total[1] = 0;
+
+    if ( is224 != 0 ) {
+        ctx->is224 = true;
+        memcpy(ctx->state, init_state_sha224, sizeof(ctx->state));
+    } else {
+        ctx->is224 = false;
+        memcpy(ctx->state, init_state_sha256, sizeof(ctx->state));
+    }
+}
+
+void mbedtls_sha256_process( mbedtls_sha256_context *ctx,
+                             const unsigned char data[64] )
+{
+    crypto_sha_update_state( ctx->state, data, 1, CRYPTO_SHA2 );
+}
+
+/*
+ * SHA-256 process buffer
+ */
+void mbedtls_sha256_update( mbedtls_sha256_context *ctx,
+                            const unsigned char *input,
+                            size_t ilen )
+{
+    size_t fill;
+    uint32_t left;
+
+    if( ilen == 0 ) {
+        return;
+    }
+
+    left = ctx->total[0] & 0x3F;
+    fill = 64 - left;
+
+    ctx->total[0] += (uint32_t) ilen;
+    ctx->total[0] &= 0xFFFFFFFF;
+
+    if( ctx->total[0] < (uint32_t) ilen ) {
+        ctx->total[1]++;
+    }
+
+    if( left && ilen >= fill ) {
+        memcpy( (void *) (ctx->buffer + left), input, fill );
+        mbedtls_sha256_process( ctx, ctx->buffer );
+        input += fill;
+        ilen  -= fill;
+        left = 0;
+    }
+
+    while( ilen >= 64 ) {
+        size_t blocks = ilen / 64;
+        crypto_sha_update_state( ctx->state, input, blocks, CRYPTO_SHA2 );
+        input += blocks * 64;
+        ilen  -= blocks * 64;
+    }
+
+    if( ilen > 0 ) {
+        memcpy( (void *) (ctx->buffer + left), input, ilen );
+    }
+}
+
+/*
+ * SHA-256 final digest
+ */
+void mbedtls_sha256_finish( mbedtls_sha256_context *ctx,
+                            unsigned char output[32] )
+{
+    uint32_t        last, padn;
+    uint32_t        high, low;
+    unsigned char   msglen[8];
+
+    high = ( ctx->total[0] >> 29 )
+         | ( ctx->total[1] <<  3 );
+    low  = ( ctx->total[0] <<  3 );
+
+    PUT_UINT32_BE( high, msglen, 0 );
+    PUT_UINT32_BE( low,  msglen, 4 );
+
+    last = ctx->total[0] & 0x3F;
+    padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last );
+
+    mbedtls_sha256_update( ctx, sha_padding, padn );
+    mbedtls_sha256_update( ctx, msglen, 8 );
+
+    for ( size_t i = 0; i < (ctx->is224 ? 28 : 32); i+=4) {
+        *((uint32_t*)(&output[i])) = __REV(ctx->state[i >> 2]);
+    }
+}
+#endif /* #if defined(MBEDTLS_SHA256_ALT) && defined(MBEDTLS_SHA256_C) */
+
+#if defined(MBEDTLS_SHA1_ALT) && defined(MBEDTLS_SHA1_C)
+
+/**
+ * \brief          Initialize SHA-1 context
+ */
+void mbedtls_sha1_init( mbedtls_sha1_context *ctx )
+{
+    if( ctx == NULL ) {
+        return;
+    }
+    memset( ctx, 0, sizeof( mbedtls_sha1_context ) );
+}
+
+/**
+ * \brief          Clear SHA-1 context
+ */
+void mbedtls_sha1_free( mbedtls_sha1_context *ctx )
+{
+    if( ctx == NULL ) {
+        return;
+    }
+    memset( ctx, 0, sizeof( mbedtls_sha1_context ) );
+}
+
+/**
+ * \brief          Clone (the state of) a SHA-1 context
+ */
+void mbedtls_sha1_clone( mbedtls_sha1_context *dst,
+                         const mbedtls_sha1_context *src )
+{
+    if ( dst != NULL && src != NULL ) {
+        *dst = *src;
+    }
+}
+
+/**
+ * \brief          SHA-1 context setup
+ *
+ * \param ctx      context to be initialized
+ */
+void mbedtls_sha1_starts( mbedtls_sha1_context *ctx )
+{
+    ctx->total[0] = 0;
+    ctx->total[1] = 0;
+    memcpy(ctx->state, init_state_sha1, 32);
+}
+
+/**
+ * \brief          SHA-1 process buffer
+ *
+ * \param ctx      SHA-1 context
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ */
+void mbedtls_sha1_update( mbedtls_sha1_context *ctx,
+                          const unsigned char *input,
+                          size_t ilen )
+{
+    size_t fill;
+    uint32_t left;
+
+    if( ilen == 0 ) {
+        return;
+    }
+
+    left = ctx->total[0] & 0x3F;
+    fill = 64 - left;
+
+    ctx->total[0] += (uint32_t) ilen;
+    ctx->total[0] &= 0xFFFFFFFF;
+
+    if( ctx->total[0] < (uint32_t) ilen ) {
+        ctx->total[1]++;
+    }
+
+    if( left && ilen >= fill ) {
+        memcpy( (void *) (ctx->buffer + left), input, fill );
+        mbedtls_sha1_process( ctx, ctx->buffer );
+        input += fill;
+        ilen  -= fill;
+        left = 0;
+    }
+
+    while( ilen >= 64 ) {
+        size_t blocks = ilen / 64;
+        crypto_sha_update_state( ctx->state, input, blocks, CRYPTO_SHA1 );
+        input += blocks * 64;
+        ilen  -= blocks * 64;
+    }
+
+    if( ilen > 0 ) {
+        memcpy( (void *) (ctx->buffer + left), input, ilen );
+    }
+}
+
+/**
+ * \brief          SHA-1 final digest
+ *
+ * \param ctx      SHA-1 context
+ * \param output   SHA-1 checksum result
+ */
+void mbedtls_sha1_finish( mbedtls_sha1_context *ctx,
+                          unsigned char output[20] )
+{
+    uint32_t last, padn;
+    uint32_t high, low;
+    unsigned char msglen[8];
+
+    high = ( ctx->total[0] >> 29 )
+         | ( ctx->total[1] <<  3 );
+    low  = ( ctx->total[0] <<  3 );
+
+    PUT_UINT32_BE( high, msglen, 0 );
+    PUT_UINT32_BE( low,  msglen, 4 );
+
+    last = ctx->total[0] & 0x3F;
+    padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last );
+
+    mbedtls_sha1_update( ctx, sha_padding, padn );
+    mbedtls_sha1_update( ctx, msglen, 8 );
+
+    for ( size_t i = 0; i < 20; i+=4) {
+        *((uint32_t*)(&output[i])) = __REV(ctx->state[i >> 2]);
+    }
+}
+
+/* Internal use */
+void mbedtls_sha1_process( mbedtls_sha1_context *ctx,
+                           const unsigned char data[64] )
+{
+    crypto_sha_update_state( ctx->state, data, 1, CRYPTO_SHA1 );
+}
+
+#endif /* defined(MBEDTLS_SHA1_ALT) && defined(MBEDTLS_SHA1_C) */
+
+#endif /* #if defined(CRYPTO_PRESENT) */
+
+#endif /* #if ( defined(MBEDTLS_SHA256_ALT) && defined(MBEDTLS_SHA256_C) ) || ( defined(MBEDTLS_SHA1_ALT) && defined (MBEDTLS_SHA1_C) ) */
diff --git a/features/mbedtls/targets/TARGET_Silicon_Labs/mbedtls_device.h b/features/mbedtls/targets/TARGET_Silicon_Labs/mbedtls_device.h
new file mode 100644
index 00000000000..d76aba13c6f
--- /dev/null
+++ b/features/mbedtls/targets/TARGET_Silicon_Labs/mbedtls_device.h
@@ -0,0 +1,42 @@
+/*
+ *  mbed OS configuration header for mbed TLS HW acceleration
+ *
+ *  Copyright (C) 2016, Silicon Labs, http://www.silabs.com
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ */
+#ifndef MBEDTLS_DEVICE_H
+#define MBEDTLS_DEVICE_H
+
+#include "em_device.h"
+
+#if defined ( AES_PRESENT )
+#define MBEDTLS_AES_ALT
+#endif
+
+#if defined ( CRYPTO_PRESENT )
+#define MBEDTLS_AES_ALT
+
+#define MBEDTLS_ECP_INTERNAL_ALT
+#define MBEDTLS_ECP_ADD_MIXED_ALT
+#define MBEDTLS_ECP_DOUBLE_JAC_ALT
+#define MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT
+#define MBEDTLS_ECP_NORMALIZE_JAC_ALT
+#define MBEDTLS_ECP_RANDOMIZE_JAC_ALT
+
+#define MBEDTLS_SHA1_ALT
+#define MBEDTLS_SHA256_ALT
+#endif
+
+#endif /* MBEDTLS_DEVICE_H */
diff --git a/features/mbedtls/targets/TARGET_Silicon_Labs/sha1_alt.h b/features/mbedtls/targets/TARGET_Silicon_Labs/sha1_alt.h
new file mode 100644
index 00000000000..891b0655c88
--- /dev/null
+++ b/features/mbedtls/targets/TARGET_Silicon_Labs/sha1_alt.h
@@ -0,0 +1,113 @@
+/**
+ * \file sha1_alt.h
+ *
+ * \brief SHA-1 cryptographic hash function
+ *
+ *  Copyright (C) 2015-2016, Silicon Labs, http://www.silabs.com
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ */
+#ifndef MBEDTLS_SHA1_ALT_H
+#define MBEDTLS_SHA1_ALT_H
+
+/***************************************************************************//**
+ * \addtogroup sl_crypto
+ * \{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * \addtogroup sl_crypto_sha1 SHA-1 cryptographic hash function
+ * \brief CRYPTO hardware accelerated SHA-1 cryptographic hash function.
+ * \{
+ ******************************************************************************/
+
+#if defined(MBEDTLS_SHA1_ALT)
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          SHA-1 context structure
+ */
+typedef struct
+{
+    uint32_t state[8];          /*!< intermediate digest state  */
+    uint32_t total[2];          /*!< number of bytes processed  */
+    unsigned char buffer[64];   /*!< data block being processed */
+}
+mbedtls_sha1_context;
+
+/**
+ * \brief          Initialize SHA-1 context
+ *
+ * \param ctx      SHA-1 context to be initialized
+ */
+void mbedtls_sha1_init( mbedtls_sha1_context *ctx );
+
+/**
+ * \brief          Clear SHA-1 context
+ *
+ * \param ctx      SHA-1 context to be cleared
+ */
+void mbedtls_sha1_free( mbedtls_sha1_context *ctx );
+
+/**
+ * \brief          Clone (the state of) a SHA-1 context
+ *
+ * \param dst      The destination context
+ * \param src      The context to be cloned
+ */
+void mbedtls_sha1_clone( mbedtls_sha1_context *dst,
+                         const mbedtls_sha1_context *src );
+
+/**
+ * \brief          SHA-1 context setup
+ *
+ * \param ctx      context to be initialized
+ */
+void mbedtls_sha1_starts( mbedtls_sha1_context *ctx );
+
+/**
+ * \brief          SHA-1 process buffer
+ *
+ * \param ctx      SHA-1 context
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ */
+void mbedtls_sha1_update( mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen );
+
+/**
+ * \brief          SHA-1 final digest
+ *
+ * \param ctx      SHA-1 context
+ * \param output   SHA-1 checksum result
+ */
+void mbedtls_sha1_finish( mbedtls_sha1_context *ctx, unsigned char output[20] );
+
+/* Internal use */
+void mbedtls_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[64] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if defined(MBEDTLS_SHA1_ALT) */
+
+/** \} (end addtogroup sl_crypto_sha1) */
+/** \} (end addtogroup sl_crypto) */
+
+#endif /* #ifndef MBEDTLS_SHA1_ALT_H */
diff --git a/features/mbedtls/targets/TARGET_Silicon_Labs/sha256_alt.h b/features/mbedtls/targets/TARGET_Silicon_Labs/sha256_alt.h
new file mode 100644
index 00000000000..5a7bf9a6766
--- /dev/null
+++ b/features/mbedtls/targets/TARGET_Silicon_Labs/sha256_alt.h
@@ -0,0 +1,120 @@
+/**
+ * \file sha256_alt.h
+ *
+ * \brief SHA-224 and SHA-256 cryptographic hash function
+ *
+ *  Copyright (C) 2015-2016, Silicon Labs, http://www.silabs.com
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ */
+#ifndef MBEDTLS_SHA256_ALT_H
+#define MBEDTLS_SHA256_ALT_H
+
+/***************************************************************************//**
+ * \addtogroup sl_crypto
+ * \{
+ ******************************************************************************/
+
+/***************************************************************************//**
+ * \addtogroup sl_crypto_sha256 SHA-224 and SHA-256 cryptographic hash function
+ * \brief CRYPTO hardware accelerated SHA-224 and SHA-256 cryptographic hash function.
+ * \{
+ ******************************************************************************/
+
+#if defined(MBEDTLS_SHA256_ALT)
+
+/* SiliconLabs CRYPTO hardware acceleration implementation */
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          SHA-256 context structure
+ */
+typedef struct
+{
+    uint32_t state[8];            /*!< intermediate digest state  */
+    uint32_t total[2];            /*!< number of bytes processed  */
+    unsigned char buffer[64];     /*!< data block being processed */
+    bool is224;                   /*!< false => SHA-256, else SHA-224 */
+}
+mbedtls_sha256_context;
+
+/**
+ * \brief          Initialize SHA-256 context
+ *
+ * \param ctx      SHA-256 context to be initialized
+ */
+void mbedtls_sha256_init( mbedtls_sha256_context *ctx );
+
+/**
+ * \brief          Clear SHA-256 context
+ *
+ * \param ctx      SHA-256 context to be cleared
+ */
+void mbedtls_sha256_free( mbedtls_sha256_context *ctx );
+
+/**
+ * \brief          Clone (the state of) a SHA-256 context
+ *
+ * \param dst      The destination context
+ * \param src      The context to be cloned
+ */
+void mbedtls_sha256_clone( mbedtls_sha256_context *dst,
+                           const mbedtls_sha256_context *src );
+
+/**
+ * \brief          SHA-256 context setup
+ *
+ * \param ctx      context to be initialized
+ * \param is224    0 = use SHA256, 1 = use SHA224
+ */
+void mbedtls_sha256_starts( mbedtls_sha256_context *ctx, int is224 );
+
+/**
+ * \brief          SHA-256 process buffer
+ *
+ * \param ctx      SHA-256 context
+ * \param input    buffer holding the  data
+ * \param ilen     length of the input data
+ */
+void mbedtls_sha256_update( mbedtls_sha256_context *ctx, const unsigned char *input,
+                    size_t ilen );
+
+/**
+ * \brief          SHA-256 final digest
+ *
+ * \param ctx      SHA-256 context
+ * \param output   SHA-224/256 checksum result
+ */
+void mbedtls_sha256_finish( mbedtls_sha256_context *ctx, unsigned char output[32] );
+
+/* Internal use */
+void mbedtls_sha256_process( mbedtls_sha256_context *ctx, const unsigned char data[64] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if defined(MBEDTLS_SHA256_ALT) */
+
+/** \} (end addtogroup sl_crypto_sha256) */
+/** \} (end addtogroup sl_crypto) */
+
+#endif /* #ifndef MBEDTLS_SHA256_ALT_H */
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diff --git a/features/nanostack/FEATURE_LOWPAN_ROUTER/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/libnanostack.a b/features/nanostack/FEATURE_LOWPAN_ROUTER/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/libnanostack.a
index 31b0ce5c865..321bfb8782b 100644
Binary files a/features/nanostack/FEATURE_LOWPAN_ROUTER/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/libnanostack.a and b/features/nanostack/FEATURE_LOWPAN_ROUTER/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/libnanostack.a differ
diff --git a/features/nanostack/FEATURE_NANOSTACK/coap-service/source/include/coap_security_handler.h b/features/nanostack/FEATURE_NANOSTACK/coap-service/source/include/coap_security_handler.h
index f02167e028e..4a1f11d0e0e 100644
--- a/features/nanostack/FEATURE_NANOSTACK/coap-service/source/include/coap_security_handler.h
+++ b/features/nanostack/FEATURE_NANOSTACK/coap-service/source/include/coap_security_handler.h
@@ -100,10 +100,21 @@ const void *coap_security_handler_keyblock(const coap_security_t *sec);
 NS_DUMMY_DEFINITIONS_OK
 
 /* Dummy definitions, including needed error codes */
+#ifndef MBEDTLS_ERR_SSL_TIMEOUT
 #define MBEDTLS_ERR_SSL_TIMEOUT (-1)
+#endif
+
+#ifndef MBEDTLS_ERR_SSL_WANT_READ
 #define MBEDTLS_ERR_SSL_WANT_READ (-2)
+#endif
+
+#ifndef MBEDTLS_ERR_SSL_WANT_WRITE
 #define MBEDTLS_ERR_SSL_WANT_WRITE (-3)
+#endif
+
+#ifndef MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE
 #define MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE (-4)
+#endif
 
 #define coap_security_create(socket_id, timer_id, handle, \
                              mode, send_cb, receive_cb, start_timer_cb, timer_status_cb) ((coap_security_t *) 0)
diff --git a/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/source/nd_tasklet.c b/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/source/nd_tasklet.c
index 5b589d8842c..e3eab47677e 100644
--- a/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/source/nd_tasklet.c
+++ b/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/source/nd_tasklet.c
@@ -23,6 +23,7 @@
 #include "include/nd_tasklet.h"
 #include "include/mesh_system.h"
 #include "ns_event_loop.h"
+#include "multicast_api.h"
 
 // For tracing we need to define flag, have include and define group
 #define HAVE_DEBUG 1
@@ -265,6 +266,13 @@ void nd_tasklet_configure_and_connect_to_network(void)
          tasklet_data_ptr->network_interface_id,
          MBED_CONF_MBED_MESH_API_6LOWPAN_ND_PANID_FILTER);
 
+    // Enable MPL by default
+    const uint8_t all_mpl_forwarders[16] = {0xff, 0x03, [15]=0xfc};
+    multicast_mpl_domain_subscribe(tasklet_data_ptr->network_interface_id,
+                                      all_mpl_forwarders,
+                                      MULTICAST_MPL_SEED_ID_DEFAULT,
+                                      NULL);
+
     status = arm_nwk_interface_up(tasklet_data_ptr->network_interface_id);
     if (status >= 0) {
         tasklet_data_ptr->tasklet_state = TASKLET_STATE_BOOTSTRAP_STARTED;
diff --git a/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/nanostack/net_test_api.h b/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/nanostack/net_test_api.h
index b0c0375bc34..8a7c84c05be 100644
--- a/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/nanostack/net_test_api.h
+++ b/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/nanostack/net_test_api.h
@@ -23,7 +23,7 @@
 #include "ns_types.h"
 
 /**
- * \brief Makes TCP protocol drop given number of packets from a particular state (TX side, tcp_down()).
+ * \brief Makes TCP protocol drop given number of packets from a particular state (TX side).
  *
  * Testing API for TCP retransmission mechanism after a packet is dropped in a particular state.
  *
@@ -35,7 +35,7 @@
 int8_t arm_nwk_test_tcp_drop_tx(int state, uint8_t count);
 
 /**
- * \brief Makes TCP protocol drop given number of packets from a particular state (RX side, tcp_up()).
+ * \brief Makes TCP protocol drop given number of packets from a particular state (RX side).
  *
  * Testing API for TCP to drop  received packets.
  *
diff --git a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp
index 875abbb48a7..3b91b01aa66 100644
--- a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp
+++ b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp
@@ -14,15 +14,66 @@
  * limitations under the License.
  */
 #include "NanostackRfPhyEfr32.h"
+
+#include <string.h>
+
+#include "mbed.h"
 #include "ns_types.h"
 #include "platform/arm_hal_interrupt.h"
 #include "nanostack/platform/arm_hal_phy.h"
 #include "mbed_toolchain.h"
-#include <string.h>
 
 #include "mbed-trace/mbed_trace.h"
 #define  TRACE_GROUP  "SLRF"
 
+/* Enable debug printing with SL_RADIO_DEBUG, override debug printer with SL_DEBUG_PRINT. */
+#ifdef SL_RADIO_DEBUG
+#ifndef SL_DEBUG_PRINT
+#define SL_DEBUG_PRINT(...) tr_debug(__VA_ARGS__)
+#endif
+#else
+#define SL_DEBUG_PRINT(...) 
+#endif
+
+/* RF_THREAD_STACK_SIZE defines tack size for the RF adaptor thread */
+#ifndef RF_THREAD_STACK_SIZE
+#define RF_THREAD_STACK_SIZE 1024
+#endif
+
+/* RF_QUEUE_SIZE defines queue size for incoming messages */
+#ifndef RF_QUEUE_SIZE
+#define RF_QUEUE_SIZE  8
+#endif
+
+
+/* RFThreadSignal used to signal from interrupts to the adaptor thread */
+enum RFThreadSignal {
+    SL_RX_DONE          = (1 << 1),
+    SL_TX_DONE          = (1 << 2),
+    SL_TX_ERR           = (1 << 3),
+    SL_TX_TIMEOUT       = (1 << 4),
+    SL_ACK_RECV         = (1 << 5),    
+    SL_ACK_TIMEOUT      = (1 << 6),
+    SL_TXFIFO_ERR       = (1 << 7),
+    SL_RXFIFO_ERR       = (1 << 8),
+    SL_CAL_REQ          = (1 << 9),
+    SL_RSSI_DONE        = (1 << 10),
+    SL_QUEUE_FULL       = (1 << 11),
+
+    // ACK pend flag can be signalled in addition to RX_DONE
+    SL_ACK_PEND         = (1 << 31),
+};
+
+/*  Adaptor thread definitions */
+static void rf_thread_loop(const void *arg);
+static osThreadDef(rf_thread_loop, osPriorityRealtime, RF_THREAD_STACK_SIZE);
+static osThreadId rf_thread_id;
+
+/* Queue for passing messages from interrupt to adaptor thread */
+static volatile void* rx_queue[8];
+static volatile size_t rx_queue_head;
+static volatile size_t rx_queue_tail;
+
 /* Silicon Labs headers */
 extern "C" {
     #include "rail/rail.h"
@@ -64,10 +115,11 @@ typedef enum {
 
 static const RAIL_CsmaConfig_t csma_config = RAIL_CSMA_CONFIG_802_15_4_2003_2p4_GHz_OQPSK_CSMA;
 
-#if defined(TARGET_EFR32MG1)
+#if defined(TARGET_EFR32MG1) || defined(TARGET_EFR32FG1)
 #include "ieee802154_subg_efr32xg1_configurator_out.h"
 #include "ieee802154_efr32xg1_configurator_out.h"
-#elif defined(TARGET_EFR32MG12)
+#elif defined(TARGET_EFR32MG12) || defined(TARGET_EFR32FG12)
+#include "ieee802154_efr32xg12_configurator_out.h"
 #include "ieee802154_efr32xg12_configurator_out.h"
 #else
 #error "Not a valid target."
@@ -152,6 +204,75 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h
 /* Local function prototypes */
 static bool rail_checkAndSwitchChannel(uint8_t channel);
 
+static void rf_thread_loop(const void *arg)
+{
+    SL_DEBUG_PRINT("rf_thread_loop: starting (id: %d)\n", rf_thread_id);
+    for (;;) {
+        osEvent event = osSignalWait(0, osWaitForever);
+
+        if (event.status != osEventSignal) {
+            continue;
+        }
+
+        platform_enter_critical();
+
+        if (event.value.signals & SL_RX_DONE) {
+            while(rx_queue_tail != rx_queue_head) {
+                void* handle = (void*) rx_queue[rx_queue_tail];
+                RAIL_RxPacketInfo_t* info = (RAIL_RxPacketInfo_t*) memoryPtrFromHandle(handle);
+                device_driver.phy_rx_cb(
+                        info->dataPtr + 1,
+                        info->dataLength - 1, 
+                        info->appendedInfo.lqi, 
+                        info->appendedInfo.rssiLatch, 
+                        rf_radio_driver_id);
+
+                memoryFree(handle);
+                rx_queue[rx_queue_tail] = NULL;
+                rx_queue_tail = (rx_queue_tail + 1) % RF_QUEUE_SIZE;
+            }
+
+        } else if (event.value.signals & SL_TX_DONE) {
+            device_driver.phy_tx_done_cb(rf_radio_driver_id,
+                    current_tx_handle,
+                    PHY_LINK_TX_SUCCESS,
+                    1,
+                    1);
+        } else if (event.value.signals & SL_ACK_RECV) {
+            device_driver.phy_tx_done_cb( rf_radio_driver_id,
+                    current_tx_handle,
+                    (event.value.signals & SL_ACK_PEND) ? PHY_LINK_TX_DONE_PENDING : PHY_LINK_TX_DONE,
+                    1,
+                    1);
+        } else if (event.value.signals & SL_ACK_TIMEOUT) {
+            waiting_for_ack = false;
+            device_driver.phy_tx_done_cb(rf_radio_driver_id,
+                    current_tx_handle,
+                    PHY_LINK_TX_FAIL,
+                    1,
+                    1);
+        } else if(event.value.signals & SL_TX_ERR) {
+            device_driver.phy_tx_done_cb( rf_radio_driver_id,
+                    current_tx_handle,
+                    PHY_LINK_CCA_FAIL,
+                    8,
+                    1);
+        } else if(event.value.signals & SL_CAL_REQ) {
+            SL_DEBUG_PRINT("rf_thread_loop: SL_CAL_REQ signal received (unhandled)\n");
+        } else if(event.value.signals & SL_RXFIFO_ERR) {
+            SL_DEBUG_PRINT("rf_thread_loop: SL_RXFIFO_ERR signal received (unhandled)\n");
+        } else if(event.value.signals & SL_TXFIFO_ERR) {
+            SL_DEBUG_PRINT("rf_thread_loop: SL_TXFIFO_ERR signal received (unhandled)\n");
+        } else if(event.value.signals & SL_QUEUE_FULL) {
+            SL_DEBUG_PRINT("rf_thread_loop: SL_QUEUE_FULL signal received (packet dropped)\n");
+        } else {
+            SL_DEBUG_PRINT("rf_thread_loop unhandled event status: %d value: %d\n", event.status, event.value.signals);
+        }
+
+        platform_exit_critical();
+    }
+}
+
 /*============ CODE =========*/
 
 /*
@@ -168,6 +289,8 @@ static int8_t rf_device_register(void)
         return -1;
     }
 
+    SL_DEBUG_PRINT("rf_device_register: entry\n");
+
 #if MBED_CONF_SL_RAIL_BAND == 2400
     RADIO_PA_Init((RADIO_PAInit_t*)&paInit2p4);
 #elif (MBED_CONF_SL_RAIL_BAND == 915) || (MBED_CONF_SL_RAIL_BAND == 868)
@@ -254,6 +377,12 @@ static int8_t rf_device_register(void)
         radio_state = RADIO_INITING;
     }
 
+#ifdef MBED_CONF_RTOS_PRESENT
+    rx_queue_head = 0;
+    rx_queue_tail = 0;
+    rf_thread_id = osThreadCreate(osThread(rf_thread_loop), NULL);
+#endif
+
     return rf_radio_driver_id;
 }
 
@@ -288,29 +417,31 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h
 
     switch(radio_state) {
     case RADIO_UNINIT:
-        tr_debug("Radio uninit\n");
+        SL_DEBUG_PRINT("rf_start_cca: Radio uninit\n");
         return -1;
     case RADIO_INITING:
-        tr_debug("Radio initing\n");
+        SL_DEBUG_PRINT("rf_start_cca: Radio initing\n");
         return -1;
     case RADIO_CALIBRATION:
-        tr_debug("Radio calibrating\n");
+        SL_DEBUG_PRINT("rf_start_cca: Radio calibrating\n");
         return -1;
     case RADIO_TX:
-        tr_debug("Radio in TX mode\n");
+        SL_DEBUG_PRINT("rf_start_cca: Radio in TX mode\n");
         return -1;
     case RADIO_IDLE:
     case RADIO_RX:
         // If we're still waiting for an ACK, don't mess up the internal state
         if(waiting_for_ack || RAIL_RfStateGet() == RAIL_RF_STATE_TX) {
             if((RAIL_GetTime() - last_tx) < 30000) {
-                tr_debug("Still waiting on previous ACK\n");
+                SL_DEBUG_PRINT("rf_start_cca: Still waiting on previous ACK\n");
                 return -1;
             } else {
-                tr_debug("TXerr\n");
+                SL_DEBUG_PRINT("rf_start_cca: TXerr\n");
             }
         }
 
+        platform_enter_critical();
+
         data_ptr[0] = data_length + 2;
         RAIL_RfIdleExt(RAIL_IDLE_ABORT , true);
         RAIL_TxDataLoad(&txData);
@@ -325,21 +456,24 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h
             txOpt.waitForAck = false;
         }
 
-        //tr_debug("Called TX, len %d, chan %d, ack %d\n", data_length, channel, waiting_for_ack ? 1 : 0);
+        SL_DEBUG_PRINT("rf_start_cca: Called TX, len %d, chan %d, ack %d\n", data_length, channel, waiting_for_ack ? 1 : 0);
 
         if(RAIL_TxStartWithOptions(channel, &txOpt, &RAIL_CcaCsma, (RAIL_CsmaConfig_t*) &csma_config) == 0) {
           //Save packet number and sequence
           current_tx_handle = tx_handle;
           current_tx_sequence = data_ptr[3];
+          platform_exit_critical();
           return 0;
         } else {
           RAIL_RfIdle();
           RAIL_RxStart(channel);
           radio_state = RADIO_RX;
+          platform_exit_critical();
           return -1;
         }
     }
     //Should never get here...
+    platform_exit_critical();
     return -1;
 }
 
@@ -378,7 +512,7 @@ static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_
             break;
         /* Enable wireless interface ED scan mode */
         case PHY_INTERFACE_RX_ENERGY_STATE:
-            tr_debug("Energy det req\n");
+            SL_DEBUG_PRINT("rf_interface_state_control: Energy det req\n");
             // TODO: implement energy detection
             break;
         /* Enable RX in promiscuous mode (aka no address filtering) */
@@ -435,12 +569,15 @@ static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_pt
         /* Read status of the link */
         case PHY_EXTENSION_READ_LINK_STATUS:
             // TODO: return accurate value here
-            tr_debug("Trying to read link status\n");
+            SL_DEBUG_PRINT("rf_extension: Trying to read link status\n");
             break;
         /* Convert between LQI and RSSI */
         case PHY_EXTENSION_CONVERT_SIGNAL_INFO:
             // TODO: return accurate value here
-            tr_debug("Trying to read signal info\n");
+            SL_DEBUG_PRINT("rf_extension: Trying to read signal info\n");
+            break;
+        case PHY_EXTENSION_ACCEPT_ANY_BEACON:
+        SL_DEBUG_PRINT("rf_extension: Trying to accept any beacon\n");
             break;
     }
     return 0;
@@ -468,11 +605,11 @@ static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address
         case PHY_MAC_64BIT:
             /* Store MAC in MSB order */
             memcpy(MAC_address, address_ptr, 8);
-            tr_debug("MACw ");
+            SL_DEBUG_PRINT("rf_address_write: MACw ");
             for(unsigned int i = 0; i < sizeof(MAC_address); i ++) {
-                tr_debug("%02x:", MAC_address[i]);
+                SL_DEBUG_PRINT("%02x:", MAC_address[i]);
             }
-            tr_debug("\n");
+            SL_DEBUG_PRINT("\n");
             /* Pass MAC to the RF driver in LSB order */
             uint8_t MAC_reversed[8];
             for(unsigned int i = 0; i < sizeof(MAC_address); i ++) {
@@ -483,13 +620,11 @@ static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address
         /*Set 16-bit address*/
         case PHY_MAC_16BIT:
             short_address = address_ptr[0] << 8 | address_ptr[1];
-            tr_debug("Filter EUI16 %04x\n", short_address);
             RAIL_IEEE802154_SetShortAddress(short_address);
             break;
         /*Set PAN Id*/
         case PHY_MAC_PANID:
             PAN_address = address_ptr[0] << 8 | address_ptr[1];
-            tr_debug("Filter PAN %04x\n", PAN_address);
             RAIL_IEEE802154_SetPanId(PAN_address);
             break;
     }
@@ -618,14 +753,19 @@ void RAILCb_TxRadioStatus(uint8_t status) {
        status == RAIL_TX_CONFIG_TX_ABORTED ||
        status == RAIL_TX_CONFIG_TX_BLOCKED) {
         waiting_for_ack = false;
-        device_driver.phy_tx_done_cb( rf_radio_driver_id,
+#ifdef MBED_CONF_RTOS_PRESENT
+        osSignalSet(rf_thread_id, SL_TX_ERR);
+    }
+#else
+        device_driver.phy_tx_done_cb(rf_radio_driver_id,
                                       current_tx_handle,
                                       PHY_LINK_CCA_FAIL,
                                       8,
                                       1);
     } else {
-        tr_debug("Packet TX error %d\n", status);
+        SL_DEBUG_PRINT("Packet TX error %d\n", status);
     }
+#endif
   }
   radio_state = RADIO_RX;
 }
@@ -648,7 +788,6 @@ void RAILCb_RxRadioStatus(uint8_t status) {
         case RAIL_RX_CONFIG_ADDRESS_FILTERED:
             break;
         default:
-            tr_debug("RXE %d\n", status);
             break;
     }
 }
@@ -663,7 +802,11 @@ void RAILCb_RxRadioStatus(uint8_t status) {
  */
 void RAILCb_CalNeeded(void) {
   // TODO: Implement on-the-fly recalibration
-  tr_debug("!!!! Calling for calibration\n");
+#ifdef MBED_CONF_RTOS_PRESENT
+  osSignalSet(rf_thread_id, SL_CAL_REQ);
+#else
+  SL_DEBUG_PRINT("!!!! Calling for calibration\n");
+#endif
 }
 
 /**
@@ -691,6 +834,9 @@ void RAILCb_TimerExpired(void) {
  * callback.
  */
 void RAILCb_TxPacketSent(RAIL_TxPacketInfo_t *txPacketInfo) {
+#ifdef MBED_CONF_RTOS_PRESENT
+    osSignalSet(rf_thread_id, SL_TX_DONE);
+#else
   if(device_driver.phy_tx_done_cb != NULL) {
     device_driver.phy_tx_done_cb( rf_radio_driver_id,
                                   current_tx_handle,
@@ -700,6 +846,7 @@ void RAILCb_TxPacketSent(RAIL_TxPacketInfo_t *txPacketInfo) {
                                   1,
                                   1);
   }
+#endif
   last_tx = RAIL_GetTime();
   radio_state = RADIO_RX;
 }
@@ -731,12 +878,16 @@ void RAILCb_RxPacketReceived(void *rxPacketHandle) {
             /* Save the pending bit */
             last_ack_pending_bit = (rxPacketInfo->dataPtr[1] & (1 << 4)) != 0;
             /* Tell the stack we got an ACK */
-            //tr_debug("rACK\n");
+#ifdef MBED_CONF_RTOS_PRESENT
+            osSignalSet(rf_thread_id, SL_ACK_RECV | SL_ACK_PEND);
+#else
+            SL_DEBUG_PRINT("rACK\n");
             device_driver.phy_tx_done_cb( rf_radio_driver_id,
                                           current_tx_handle,
                                           last_ack_pending_bit ? PHY_LINK_TX_DONE_PENDING : PHY_LINK_TX_DONE,
                                           1,
                                           1);
+#endif
         } else {
             /* Figure out whether we want to not ACK this packet */
 
@@ -752,14 +903,24 @@ void RAILCb_RxPacketReceived(void *rxPacketHandle) {
                 RAIL_AutoAckCancelAck();
             }
 
-            //tr_debug("rPKT %d\n", rxPacketInfo->dataLength);
             /* Feed the received packet into the stack */
+#ifdef MBED_CONF_RTOS_PRESENT
+            if (((rx_queue_head + 1) % RF_QUEUE_SIZE) != rx_queue_tail) {
+                memoryTakeReference(rxPacketHandle);
+                rx_queue[rx_queue_head] = rxPacketHandle;
+                rx_queue_head = (rx_queue_head + 1) % RF_QUEUE_SIZE;
+                osSignalSet(rf_thread_id, SL_RX_DONE);
+            } else {
+                osSignalSet(rf_thread_id, SL_QUEUE_FULL);
+            }
+#else
+            SL_DEBUG_PRINT("rPKT %d\n", rxPacketInfo->dataLength);
             device_driver.phy_rx_cb(rxPacketInfo->dataPtr + 1, 
                                     rxPacketInfo->dataLength - 1, 
-                                    //TODO: take a new RAIL release that exposes LQI, or have LQI as function of RSSI
-                                    255, 
+                                    rxPacketInfo->appendedInfo.lqi, 
                                     rxPacketInfo->appendedInfo.rssiLatch, 
                                     rf_radio_driver_id);
+#endif
         }
     }
 }
@@ -792,13 +953,16 @@ void RAILCb_IEEE802154_DataRequestCommand(RAIL_IEEE802154_Address_t *address) {
  */
 void RAILCb_RxAckTimeout(void) {
     if(waiting_for_ack) {
-        tr_debug("nACK\n");
         waiting_for_ack = false;
+#ifdef MBED_CONF_RTOS_PRESENT
+        osSignalSet(rf_thread_id, SL_ACK_TIMEOUT);
+#else
         device_driver.phy_tx_done_cb( rf_radio_driver_id,
                                       current_tx_handle,
                                       PHY_LINK_TX_FAIL,
                                       1,
                                       1);
+#endif
     }
 }
 
@@ -849,7 +1013,11 @@ static bool rail_checkAndSwitchChannel(uint8_t newChannel) {
  * time of the callback dispatch.
  */
 void RAILCb_RxFifoAlmostFull(uint16_t bytesAvailable) {
-    tr_debug("RX near full (%d)\n", bytesAvailable);
+#ifdef MBED_CONF_RTOS_PRESENT
+    osSignalSet(rf_thread_id, SL_RXFIFO_ERR);
+#else
+    SL_DEBUG_PRINT("RX near full (%d)\n", bytesAvailable);
+#endif
 }
 
 /**
@@ -871,7 +1039,11 @@ void RAILCb_RxFifoAlmostFull(uint16_t bytesAvailable) {
  * callback dispatch.
  */
 void RAILCb_TxFifoAlmostEmpty(uint16_t spaceAvailable) {
-    tr_debug("TX near empty (%d)\n", spaceAvailable);
+#ifdef MBED_CONF_RTOS_PRESENT
+    osSignalSet(rf_thread_id, SL_TXFIFO_ERR);
+#else
+    SL_DEBUG_PRINT("TX near empty (%d)\n", spaceAvailable);
+#endif
 }
 
 /**
@@ -886,5 +1058,9 @@ void RAILCb_TxFifoAlmostEmpty(uint16_t spaceAvailable) {
  * get the result.
  */
 void RAILCb_RssiAverageDone(int16_t avgRssi) {
-    tr_debug("RSSI done (%d)\n", avgRssi);
+#ifdef MBED_CONF_RTOS_PRESENT
+    osSignalSet(rf_thread_id, SL_RSSI_DONE);
+#else
+    SL_DEBUG_PRINT("RSSI done (%d)\n", avgRssi);
+#endif
 }
\ No newline at end of file
diff --git a/features/nanostack/FEATURE_NANOSTACK_FULL/TOOLCHAIN_ARM/TARGET_LIKE_CORTEX_M0/libnanostack.ar b/features/nanostack/FEATURE_NANOSTACK_FULL/TOOLCHAIN_ARM/TARGET_LIKE_CORTEX_M0/libnanostack.ar
index f86e07432fc..c6ba1183041 100644
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diff --git a/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp b/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp
index 06c0de8299e..22d9a193205 100644
--- a/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp
+++ b/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp
@@ -141,7 +141,7 @@ static void CMT_URC(ATCmdParser *at)
 
 static bool set_atd(ATCmdParser *at)
 {
-    bool success = at->send("ATD*99***" CTX"#") && at->recv("CONNECT");
+    bool success = at->send("ATD*99***" CTX "#") && at->recv("CONNECT");
 
     return success;
 }
@@ -469,7 +469,7 @@ nsapi_error_t PPPCellularInterface::setup_context_and_credentials()
 #endif
     success = _at->send("AT"
                           "+FCLASS=0;" // set to connection (ATD) to data mode
-                          "+CGDCONT=" CTX",\"%s\",\"%s%s\"",
+                          "+CGDCONT=" CTX ",\"%s\",\"%s%s\"",
                           pdp_type, auth, _apn
                          )
                    && _at->recv("OK");
@@ -558,18 +558,12 @@ nsapi_error_t PPPCellularInterface::connect()
     nsapi_error_t retcode;
     bool success;
     bool did_init = false;
+    const char *apn_config = NULL;
 
     if (dev_info.ppp_connection_up) {
         return NSAPI_ERROR_IS_CONNECTED;
     }
 
-    const char *apn_config = NULL;
-#if MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP
-    if (!set_credentials_api_used) {
-        apn_config = apnconfig(dev_info.imsi);
-    }
-#endif
-
     do {
         retry_init:
 
@@ -604,6 +598,12 @@ nsapi_error_t PPPCellularInterface::connect()
                 return NSAPI_ERROR_NO_CONNECTION;
             }
 
+#if MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP
+            if (!apn_config) {
+                apn_config = apnconfig(dev_info.imsi);
+            }
+#endif
+
             /* Check if user want skip SIM pin checking on boot up */
             if (set_sim_pin_check_request) {
                 retcode = do_sim_pin_check(_at, _pin);
@@ -629,6 +629,7 @@ nsapi_error_t PPPCellularInterface::connect()
                 _apn = _APN_GET(apn_config);
                 _uname = _APN_GET(apn_config);
                 _pwd = _APN_GET(apn_config);
+                tr_info("Looked up APN %s.", _apn);
             }
 #endif
 
diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32F103RB.h b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_DEVICE.h
similarity index 53%
rename from features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32F103RB.h
rename to features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_DEVICE.h
index 271610b217b..d7cfc5b35c1 100644
--- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32F103RB.h
+++ b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_DEVICE.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2016 mbed.org, MIT License
+/* Copyright (c) 2017 mbed.org, MIT License
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
 * and associated documentation files (the "Software"), to deal in the Software without
@@ -15,16 +15,29 @@
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
-#ifndef USBHAL_STM32F103RB
-#define USBHAL_STM32F103RB
+#ifndef USBHAL_IP_DEVICE_H
+#define USBHAL_IP_DEVICE_H
 
+#if defined(TARGET_NUCLEO_F303ZE)
+#define USBHAL_IRQn  USB_LP_CAN_RX0_IRQn
+
+#elif defined(TARGET_NUCLEO_F103RB)
 #define USBHAL_IRQn  USB_LP_CAN1_RX0_IRQn
 
+#elif defined(TARGET_DISCO_L072CZ_LRWAN1) || \
+      defined(TARGET_DISCO_L053C8)
+#define USBHAL_IRQn  USB_IRQn
+
+#else
+#error "USB IRQ is not configured !"
+#endif
+
+#define NB_ENDPOINT  8 // Must be a multiple of 4 bytes
 
-#define NB_ENDPOINT  8
-/*  must be multiple of 4 bytes */
 #define MAXTRANSFER_SIZE  0x200
-#define FIFO_USB_RAM_SIZE (MAXTRANSFER_SIZE+MAX_PACKET_SIZE_EP0+MAX_PACKET_SIZE_EP1+MAX_PACKET_SIZE_EP2+MAX_PACKET_SIZE_EP3)
+
+#define FIFO_USB_RAM_SIZE (MAXTRANSFER_SIZE + MAX_PACKET_SIZE_EP0 + MAX_PACKET_SIZE_EP1 + MAX_PACKET_SIZE_EP2 + MAX_PACKET_SIZE_EP3)
+
 #if (FIFO_USB_RAM_SIZE > 0x500)
 #error "FIFO dimensioning incorrect"
 #endif
@@ -32,34 +45,33 @@
 typedef struct
 {
     USBHAL *inst;
+
     void (USBHAL::*bus_reset)(void);
     void (USBHAL::*sof)(int frame);
-    void (USBHAL::*connect_change)(unsigned int  connected);
+    void (USBHAL::*connect_change)(unsigned int connected);
     void (USBHAL::*suspend_change)(unsigned int suspended);
     void (USBHAL::*ep0_setup)(void);
     void (USBHAL::*ep0_in)(void);
     void (USBHAL::*ep0_out)(void);
     void (USBHAL::*ep0_read)(void);
     bool (USBHAL::*ep_realise)(uint8_t endpoint, uint32_t maxPacket, uint32_t flags);
-    bool (USBHAL::*epCallback[2*NB_ENDPOINT-2])(void);
-    uint8_t epComplete[8];
-    /*  memorize dummy buffer used for reception */
-    uint32_t pBufRx[MAXTRANSFER_SIZE>>2];
-    uint32_t pBufRx0[MAX_PACKET_SIZE_EP0>>2];
-    gpio_t usb_switch;
-}USBHAL_Private_t;
+    bool (USBHAL::*epCallback[(2 * NB_ENDPOINT) - 2])(void);
 
-void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
-{
-    USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
-    gpio_write(&(priv->usb_switch),!state);
-}
+    uint8_t epComplete[2 * NB_ENDPOINT];
+
+    /* Memorize dummy buffer used for reception */
+    uint32_t pBufRx[MAXTRANSFER_SIZE >> 2];
+    uint32_t pBufRx0[MAX_PACKET_SIZE_EP0 >> 2];
+
+    gpio_t usb_switch;
+} USBHAL_Private_t;
 
 uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo)
 {
     return 1024;
 }
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) 
 {
     USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
     USBHAL *obj= priv->inst;
@@ -68,24 +80,31 @@ void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
     (obj->*func)(sofnum);
 }
 
-USBHAL * USBHAL::instance;
-
-USBHAL::USBHAL(void)
+void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
 {
-    /*  init parameter  */
+    USBHAL_Private_t *priv = ((USBHAL_Private_t *)(hpcd->pData));
+#if defined(TARGET_NUCLEO_F103RB)
+    gpio_write(&(priv->usb_switch), !state);
+#else
+    gpio_write(&(priv->usb_switch), state);
+#endif
+}
+
+USBHAL *USBHAL::instance;
+
+USBHAL::USBHAL(void) {
     USBHAL_Private_t *HALPriv = new(USBHAL_Private_t);
-    /*  initialized all field of init including 0 field  */
-    /*  constructor does not fill with zero */
+
     hpcd.Instance = USB;
-    /*  initialized all field of init including 0 field  */
-    /*  constructor does not fill with zero */
+
     memset(&hpcd.Init, 0, sizeof(hpcd.Init));
     hpcd.Init.dev_endpoints = NB_ENDPOINT;
-    hpcd.Init.ep0_mps =   MAX_PACKET_SIZE_EP0;
+    hpcd.Init.ep0_mps = MAX_PACKET_SIZE_EP0;
     hpcd.Init.phy_itface = PCD_PHY_EMBEDDED;
     hpcd.Init.Sof_enable = 1;
     hpcd.Init.speed = PCD_SPEED_FULL;
-    /*  pass instance for usage inside call back */
+
+    // Pass instance for usage inside call back
     HALPriv->inst = this;
     HALPriv->bus_reset = &USBHAL::busReset;
     HALPriv->suspend_change = &USBHAL::suspendStateChanged;
@@ -96,7 +115,6 @@ USBHAL::USBHAL(void)
     HALPriv->ep0_in = &USBHAL::EP0in;
     HALPriv->ep0_out = &USBHAL::EP0out;
     HALPriv->ep0_read = &USBHAL::EP0read;
-    hpcd.pData = (void*)HALPriv;
     HALPriv->epCallback[0] = &USBHAL::EP1_OUT_callback;
     HALPriv->epCallback[1] = &USBHAL::EP1_IN_callback;
     HALPriv->epCallback[2] = &USBHAL::EP2_OUT_callback;
@@ -105,43 +123,56 @@ USBHAL::USBHAL(void)
     HALPriv->epCallback[5] = &USBHAL::EP3_IN_callback;
     instance = this;
 
+    // Configure USB pins and other clocks
+#if defined(TARGET_NUCLEO_F303ZE)
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_USB)); // DM
+    pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_USB)); // DP
+    __HAL_RCC_GPIOG_CLK_ENABLE();
+    gpio_init_out(&HALPriv->usb_switch, PG_6);
+
+#elif defined(TARGET_NUCLEO_F103RB)
+    // Make sure to connect a 1.5K resistor between USB-DP PA12 pin and +3.3V
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_MODE_AF_INPUT)); // DM
+    pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_MODE_AF_INPUT)); // DP
+
+#elif defined(TARGET_DISCO_L072CZ_LRWAN1) || \
+      defined(TARGET_DISCO_L053C8)
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_USB)); // DM
+    pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_USB)); // DP
 
-    /* Configure USB VBUS GPIO */
-    gpio_init_out(&HALPriv->usb_switch,PB_14);
-    gpio_mode(&HALPriv->usb_switch,OpenDrain);
-    /* Configure USB FS GPIOs */
-
-    /* Configure DM DP Pins
-     *   - USB-DP (D+ of the USB connector) <======> PA12 (Nucleo board)
-     *   Make sure to connect a 1.5KOhm pull up to USB-DP PA12 pin
-     *   (permanent pull-up)
-     - USB-DM (D- of the USB connector) <======> PA11 (Nucleo board)
-     */
-
-    pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_MODE_AF_INPUT));
-    pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_MODE_AF_INPUT));
+#else
+#error "USB pins are not configured !"
+#endif
 
     __HAL_RCC_USB_CLK_ENABLE();
+    __HAL_RCC_SYSCFG_CLK_ENABLE();
 
+    // Configure PCD and FIFOs
+    hpcd.pData = (void*)HALPriv;
     hpcd.State = HAL_PCD_STATE_RESET;
-
     HAL_PCD_Init(&hpcd);
-    /* hardcoded size of FIFO according definition*/
-    HAL_PCDEx_PMAConfig(&hpcd , 0x00 , PCD_SNG_BUF, 0x30);
-    HAL_PCDEx_PMAConfig(&hpcd , 0x80 , PCD_SNG_BUF, 0x70);
-    HAL_PCDEx_PMAConfig(&hpcd , 0x01 , PCD_SNG_BUF, 0x90);
-    HAL_PCDEx_PMAConfig(&hpcd , 0x81 , PCD_SNG_BUF, 0xb0);
-#if 0
-    HAL_PCDEx_PMAConfig(&hpcd , 0x2, PCD_DBL_BUF, 0x018000b0);
-#else
-    HAL_PCDEx_PMAConfig(&hpcd , 0x2, PCD_SNG_BUF, 0x100);
-#endif
-    HAL_PCDEx_PMAConfig(&hpcd , 0x82, PCD_SNG_BUF, 0x120);
 
-    NVIC_SetVector(USBHAL_IRQn,(uint32_t)&_usbisr);
-    NVIC_SetPriority( USBHAL_IRQn, 1);
+    // EP0
+    HAL_PCDEx_PMAConfig(&hpcd, 0x00, PCD_SNG_BUF, 0x30);
+    HAL_PCDEx_PMAConfig(&hpcd, 0x80, PCD_SNG_BUF, 0x70);
+    // EP1
+    HAL_PCDEx_PMAConfig(&hpcd, 0x01, PCD_SNG_BUF, 0x90);
+    HAL_PCDEx_PMAConfig(&hpcd, 0x81, PCD_SNG_BUF, 0xb0);
+    // EP2
+    HAL_PCDEx_PMAConfig(&hpcd, 0x02, PCD_SNG_BUF, 0x100);
+    HAL_PCDEx_PMAConfig(&hpcd, 0x82, PCD_SNG_BUF, 0x120);
+    // EP3
+    HAL_PCDEx_PMAConfig(&hpcd, 0x03, PCD_DBL_BUF, 0x018000b0);
+    HAL_PCDEx_PMAConfig(&hpcd, 0x83, PCD_SNG_BUF, 0xb0);
+
+    // Configure interrupt vector
+    NVIC_SetVector(USBHAL_IRQn, (uint32_t)&_usbisr);
+    NVIC_SetPriority(USBHAL_IRQn, 1);
 
     HAL_PCD_Start(&hpcd);
 }
 
-#endif
+#endif // USBHAL_IP_DEVICE_H
diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32F769NI.h b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h
similarity index 55%
rename from features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32F769NI.h
rename to features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h
index f2bfa7a1025..e79e01be476 100644
--- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32F769NI.h
+++ b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2016 mbed.org, MIT License
+/* Copyright (c) 2017 mbed.org, MIT License
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
 * and associated documentation files (the "Software"), to deal in the Software without
@@ -15,13 +15,31 @@
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
-#ifndef USBHAL_STM32F769NI_H
-#define USBHAL_STM32F769NI_H
+#ifndef USBHAL_IP_OTGFSHS_H
+#define USBHAL_IP_OTGFSHS_H
+
+//==================================================================
+// This board has both USB OTG FS and HS connectors.
+// Select one line only.
+//==================================================================
+#if defined(TARGET_DISCO_F746NG)
+//#define TARGET_DISCO_F746NG_OTG_FS
+#define TARGET_DISCO_F746NG_OTG_HS
+#endif
+
+#if defined(TARGET_DISCO_F769NI) || \
+    defined(TARGET_DISCO_F746NG_OTG_HS)
 #define USBHAL_IRQn  OTG_HS_IRQn
-/*  must be multiple of 4 bytes */
-#define NB_ENDPOINT 4
+#else
+#define USBHAL_IRQn  OTG_FS_IRQn
+#endif
+
+#define NB_ENDPOINT  4 // Must be a multiple of 4 bytes
+
 #define MAXTRANSFER_SIZE  0x200
-#define FIFO_USB_RAM_SIZE (MAXTRANSFER_SIZE+MAX_PACKET_SIZE_EP0+MAX_PACKET_SIZE_EP1+MAX_PACKET_SIZE_EP2+MAX_PACKET_SIZE_EP3)
+
+#define FIFO_USB_RAM_SIZE (MAXTRANSFER_SIZE + MAX_PACKET_SIZE_EP0 + MAX_PACKET_SIZE_EP1 + MAX_PACKET_SIZE_EP2 + MAX_PACKET_SIZE_EP3)
+
 #if (FIFO_USB_RAM_SIZE > 0x500)
 #error "FIFO dimensioning incorrect"
 #endif
@@ -29,30 +47,37 @@
 typedef struct
 {
     USBHAL *inst;
+
     void (USBHAL::*bus_reset)(void);
     void (USBHAL::*sof)(int frame);
-    void (USBHAL::*connect_change)(unsigned int  connected);
+    void (USBHAL::*connect_change)(unsigned int connected);
     void (USBHAL::*suspend_change)(unsigned int suspended);
     void (USBHAL::*ep0_setup)(void);
     void (USBHAL::*ep0_in)(void);
     void (USBHAL::*ep0_out)(void);
     void (USBHAL::*ep0_read)(void);
     bool (USBHAL::*ep_realise)(uint8_t endpoint, uint32_t maxPacket, uint32_t flags);
-    bool (USBHAL::*epCallback[2*NB_ENDPOINT-2])(void);
-    /*  memorize dummy buffer used for reception */
-    uint32_t pBufRx[MAXTRANSFER_SIZE>>2];
-    uint32_t pBufRx0[MAX_PACKET_SIZE_EP0>>2];
-    uint8_t epComplete[2*NB_ENDPOINT];
-}USBHAL_Private_t;
+    bool (USBHAL::*epCallback[(2 * NB_ENDPOINT) - 2])(void);
+
+    uint8_t epComplete[2 * NB_ENDPOINT];
+
+    /* Memorize dummy buffer used for reception */
+    uint32_t pBufRx[MAXTRANSFER_SIZE >> 2];
+    uint32_t pBufRx0[MAX_PACKET_SIZE_EP0 >> 2];
+} USBHAL_Private_t;
 
 uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo)
 {
     uint32_t len;
-    if (fifo == 0) len = hpcd->Instance->DIEPTXF0_HNPTXFSIZ>>16;
-    else
+    if (fifo == 0) {
+        len = hpcd->Instance->DIEPTXF0_HNPTXFSIZ >> 16;
+    }
+    else {
         len =  hpcd->Instance->DIEPTXF[fifo - 1] >> 16;
-    return len*4;
+    }
+    return len * 4;
 }
+
 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) 
 {
     USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
@@ -60,27 +85,32 @@ void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
     USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
     uint32_t sofnum = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF) >> 8;
     void (USBHAL::*func)(int frame) = priv->sof;
-    /* fix me  call with same frame number */
     (obj->*func)(sofnum);
 }
 
-
-USBHAL * USBHAL::instance;
+USBHAL *USBHAL::instance;
 
 USBHAL::USBHAL(void) {
-    /*  init parameter  */
     USBHAL_Private_t *HALPriv = new(USBHAL_Private_t);
-    hpcd.Instance = USB_OTG_HS;
+
     memset(&hpcd.Init, 0, sizeof(hpcd.Init));
-    hpcd.Init.dev_endpoints = NB_ENDPOINT;
-    hpcd.Init.ep0_mps =   MAX_PACKET_SIZE_EP0;
+
+#if defined(TARGET_DISCO_F769NI) || \
+    defined(TARGET_DISCO_F746NG_OTG_HS)
+    hpcd.Instance = USB_OTG_HS;
     hpcd.Init.phy_itface = PCD_PHY_ULPI;
     hpcd.Init.Sof_enable = 0;
-
     hpcd.Init.speed = PCD_SPEED_HIGH;
-    //hpcd.Init.vbus_sensing_enable = 0;
-    //hpcd.Init.lpm_enable = 0;
-    /*  pass instance for usage inside call back */
+#else
+    hpcd.Instance = USB_OTG_FS;
+    hpcd.Init.phy_itface = PCD_PHY_EMBEDDED;
+    hpcd.Init.Sof_enable = 1;
+    hpcd.Init.speed = PCD_SPEED_FULL;
+#endif
+    hpcd.Init.dev_endpoints = NB_ENDPOINT;
+    hpcd.Init.ep0_mps = MAX_PACKET_SIZE_EP0;
+
+    // Pass instance for usage inside call back
     HALPriv->inst = this;
     HALPriv->bus_reset = &USBHAL::busReset;
     HALPriv->suspend_change = &USBHAL::suspendStateChanged;
@@ -91,7 +121,6 @@ USBHAL::USBHAL(void) {
     HALPriv->ep0_in = &USBHAL::EP0in;
     HALPriv->ep0_out = &USBHAL::EP0out;
     HALPriv->ep0_read = &USBHAL::EP0read;
-    hpcd.pData = (void*)HALPriv;
     HALPriv->epCallback[0] = &USBHAL::EP1_OUT_callback;
     HALPriv->epCallback[1] = &USBHAL::EP1_IN_callback;
     HALPriv->epCallback[2] = &USBHAL::EP2_OUT_callback;
@@ -99,16 +128,49 @@ USBHAL::USBHAL(void) {
     HALPriv->epCallback[4] = &USBHAL::EP3_OUT_callback;
     HALPriv->epCallback[5] = &USBHAL::EP3_IN_callback;
     instance = this;
-    /* Enable power and clocking */
+
+    // Configure USB pins and other clocks
+
+#if defined(TARGET_NUCLEO_F207ZG) || \
+    defined(TARGET_NUCLEO_F401RE) || \
+    defined(TARGET_NUCLEO_F411RE) || \
+    defined(TARGET_NUCLEO_F412ZG) || \
+    defined(TARGET_NUCLEO_F429ZI) || \
+    defined(TARGET_NUCLEO_F446RE) || \
+    defined(TARGET_NUCLEO_F446ZE) || \
+    defined(TARGET_NUCLEO_F767ZI) || \
+    defined(TARGET_NUCLEO_F746ZG) || \
+    defined(TARGET_DISCO_F407VG) || \
+    defined(TARGET_DISCO_F469NI) || \
+    defined(TARGET_DISCO_F746NG_OTG_FS)
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DM
+    pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DP
+    pin_function(PA_9, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF10_OTG_FS));  // VBUS
+    pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)); // ID
+    pin_function(PA_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));  // SOF
+    __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+
+#elif defined(TARGET_DISCO_L475VG_IOT01A) || \
+      defined(TARGET_DISCO_L476VG)
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DM
+    pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DP
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    pin_function(PC_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // VBUS
+    __HAL_RCC_PWR_CLK_ENABLE();
+    HAL_PWREx_EnableVddUSB();
+    __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+
+#elif defined(TARGET_DISCO_F769NI) || \
+      defined(TARGET_DISCO_F746NG_OTG_HS)
     __HAL_RCC_GPIOA_CLK_ENABLE();
     __HAL_RCC_GPIOB_CLK_ENABLE();
     __HAL_RCC_GPIOC_CLK_ENABLE();
     __HAL_RCC_GPIOH_CLK_ENABLE();
     __HAL_RCC_GPIOI_CLK_ENABLE();
-
     pin_function(PA_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // CLK
     pin_function(PA_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D0
-
     pin_function(PB_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D1
     pin_function(PB_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D2
     pin_function(PB_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D3
@@ -116,32 +178,46 @@ USBHAL::USBHAL(void) {
     pin_function(PB_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D5
     pin_function(PB_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D6
     pin_function(PB_13, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // D7
-
     pin_function(PC_0, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // STP
     pin_function(PH_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // NXT
+#if defined(TARGET_DISCO_F769NI)
     pin_function(PI_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // DIR
-
+#else // TARGET_DISCO_F746NG
+    pin_function(PC_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_HS)); // DIR
+#endif
     __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();
     __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
 
+#else
+#error "USB pins are not configured !"
+#endif
+
     __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+    // Configure PCD and FIFOs
+    hpcd.pData = (void*)HALPriv;
     hpcd.State = HAL_PCD_STATE_RESET;
     HAL_PCD_Init(&hpcd);
-    /* 1.25kbytes */
+
+    /* 1.25 kbytes */
     /* min value 16 (= 16 x 4 bytes) */
-    /*  max value 256 (= 1K bytes ) */
-    /*  maximum sum is 0x140 */
-    HAL_PCDEx_SetRxFiFo(&hpcd, (MAXTRANSFER_SIZE/4));
-    /*  bulk/int 64 bytes in FS  */
-    HAL_PCDEx_SetTxFiFo(&hpcd, 0, (MAX_PACKET_SIZE_EP0/4)+1);
-    /*  bulk/int bytes in FS */
-    HAL_PCDEx_SetTxFiFo(&hpcd, 1, (MAX_PACKET_SIZE_EP1/4)+1);
-    HAL_PCDEx_SetTxFiFo(&hpcd, 2, (MAX_PACKET_SIZE_EP2/4));
-    /* ISOchronous */
-    HAL_PCDEx_SetTxFiFo(&hpcd, 3, (MAX_PACKET_SIZE_EP3/4));
+    /* max value 256 (= 1K bytes ) */
+    /* maximum sum is 0x140 */
+    HAL_PCDEx_SetRxFiFo(&hpcd, (MAXTRANSFER_SIZE / 4));
+    // EP0 = Bulk/Int 64 bytes in FS
+    HAL_PCDEx_SetTxFiFo(&hpcd, 0, (MAX_PACKET_SIZE_EP0 / 4) + 1);
+    // EP1 = Bulk/Int bytes in FS
+    HAL_PCDEx_SetTxFiFo(&hpcd, 1, (MAX_PACKET_SIZE_EP1 / 4) + 1);
+    // EP2
+    HAL_PCDEx_SetTxFiFo(&hpcd, 2, (MAX_PACKET_SIZE_EP2 / 4));
+    // EP3 = ISOchronous
+    HAL_PCDEx_SetTxFiFo(&hpcd, 3, (MAX_PACKET_SIZE_EP3 / 4));
+
+    // Configure interrupt vector
     NVIC_SetVector(USBHAL_IRQn, (uint32_t)&_usbisr);
     NVIC_SetPriority(USBHAL_IRQn, 1);
+
     HAL_PCD_Start(&hpcd);
 }
-#endif
 
+#endif // USBHAL_IP_OTGFSHS_H
diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.cpp b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.cpp
index 36c0caf3590..6953f4a0783 100644
--- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.cpp
+++ b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.cpp
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2011 mbed.org, MIT License
+/* Copyright (c) 2017 mbed.org, MIT License
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
 * and associated documentation files (the "Software"), to deal in the Software without
@@ -15,11 +15,13 @@
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
+
 /* TARGET NOT STM does not support this HAL */
 #ifndef TARGET_STM
 #define USBSTM_HAL_UNSUPPORTED
 #endif
-/* F4 famlily wihtout USB_STM_HAL use another HAL*/
+
+/* STM32F4 family without USB_STM_HAL use another HAL */
 #if defined(TARGET_STM) && defined(TARGET_STM32F4) && !defined(USB_STM_HAL)
 #define USBSTM_HAL_UNSUPPORTED
 #endif
@@ -27,15 +29,15 @@
 #ifndef USBSTM_HAL_UNSUPPORTED
 #include "USBHAL.h"
 #include "pinmap.h"
-/* mbed endpoint definition to hal definition   */
+
+#include "USBHAL_STM32.h"
+
+/* mbed endpoint definition to hal definition */
 #define EP_ADDR(ep) (((ep) >> 1)|((ep) & 1) << 7)
+
 /* from hal definition to mbed definition */
 #define ADDR_EPIN(ep) (((ep) << 1) | 1)
 #define ADDR_EPOUT(ep) (((ep) << 1))
-/* id to detect if rx buffer is used or not  */
-
-#include "USBHAL_STM_TARGET.h"
-
 
 /*  this call at device reception completion on a Out Enpoint  */
 void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
@@ -318,15 +320,12 @@ bool USBHAL::getEndpointStallState(uint8_t endpoint) {
 void USBHAL::remoteWakeup(void) {
 }
 
-
 void USBHAL::_usbisr(void) {
     instance->usbisr();
 }
 
-
 void USBHAL::usbisr(void) {
-
     HAL_PCD_IRQHandler(&instance->hpcd);
 }
-#endif
 
+#endif
diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM_TARGET.h b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.h
similarity index 54%
rename from features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM_TARGET.h
rename to features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.h
index b380ba85945..1ed92bad54d 100644
--- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM_TARGET.h
+++ b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.h
@@ -15,29 +15,35 @@
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
+#ifndef USBHAL_STM32_H
+#define USBHAL_STM32_H
+
+#if defined(TARGET_NUCLEO_F207ZG) || \
+    defined(TARGET_NUCLEO_F401RE) || \
+    defined(TARGET_NUCLEO_F411RE) || \
+    defined(TARGET_NUCLEO_F412ZG) || \
+    defined(TARGET_NUCLEO_F429ZI) || \
+    defined(TARGET_NUCLEO_F446RE) || \
+    defined(TARGET_NUCLEO_F446ZE) || \
+    defined(TARGET_NUCLEO_F767ZI) || \
+    defined(TARGET_NUCLEO_F746ZG) || \
+    defined(TARGET_DISCO_F407VG) || \
+    defined(TARGET_DISCO_F469NI) || \
+    defined(TARGET_DISCO_F746NG) || \
+    defined(TARGET_DISCO_F769NI) || \
+    defined(TARGET_DISCO_L475VG_IOT01A) || \
+    defined(TARGET_DISCO_L476VG)
+#include "USBHAL_IP_OTGFSHS.h"
+
+#elif defined(TARGET_NUCLEO_F103RB) || \
+      defined(TARGET_NUCLEO_F303ZE) || \
+      defined(TARGET_DISCO_L053C8) || \
+      defined(TARGET_DISCO_L072CZ_LRWAN1)
+#include "USBHAL_IP_DEVICE.h"
+
+#else
+#error "Target not supported !"
 
-#if defined(TARGET_DISCO_L476VG)
-#include "USBHAL_STM32L476VG.h"
-
-#elif defined(TARGET_DISCO_L475VG_IOT01A)
-#include "USBHAL_STM32L475VG.h"
-
-#elif defined(TARGET_DISCO_L072CZ_LRWAN1)
-#include "USBHAL_STM32L072CZ.h"
-
-#elif defined(TARGET_NUCLEO_F303ZE)
-#include "USBHAL_STM32F303ZE.h"
-
-#elif defined(TARGET_NUCLEO_F103RB)
-#include "USBHAL_STM32F103RB.h"
-
-#elif defined(TARGET_DISCO_F769NI)
-#include "USBHAL_STM32F769NI.h"
-
-#elif defined(TARGET_DISCO_L053C8)
-#include "USBHAL_STM32L053C8.h"
-
-#else /* default configuration */
-#include "USBHAL_STM_144_64pins.h"
-  		  
 #endif
+
+#endif // USBHAL_STM32_H
diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32F303ZE.h b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32F303ZE.h
deleted file mode 100644
index fa49ba280a7..00000000000
--- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32F303ZE.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/* Copyright (c) 2016 mbed.org, MIT License
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
-* and associated documentation files (the "Software"), to deal in the Software without
-* restriction, including without limitation the rights to use, copy, modify, merge, publish,
-* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
-* Software is furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in all copies or
-* substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
-* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
-* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-#ifndef USBHAL_STM32F303ZE_H
-#define USBHAL_STM32F303ZE_H
-#define USBHAL_IRQn  USB_LP_CAN_RX0_IRQn
-/*  must be multiple of 4 bytes */
-#define NB_ENDPOINT 8
-#define MAXTRANSFER_SIZE  0x200
-#define FIFO_USB_RAM_SIZE (MAXTRANSFER_SIZE+MAX_PACKET_SIZE_EP0+MAX_PACKET_SIZE_EP1+MAX_PACKET_SIZE_EP2+MAX_PACKET_SIZE_EP3)
-#if (FIFO_USB_RAM_SIZE > 0x500)
-#error "FIFO dimensioning incorrect"
-#endif
-
-typedef struct
-{
-	USBHAL *inst;
-	void (USBHAL::*bus_reset)(void);
-	void (USBHAL::*sof)(int frame);
-	void (USBHAL::*connect_change)(unsigned int  connected);
-	void (USBHAL::*suspend_change)(unsigned int suspended);
-	void (USBHAL::*ep0_setup)(void);
-	void (USBHAL::*ep0_in)(void);
-	void (USBHAL::*ep0_out)(void);
-	void (USBHAL::*ep0_read)(void);
-	bool (USBHAL::*ep_realise)(uint8_t endpoint, uint32_t maxPacket, uint32_t flags);
-	bool (USBHAL::*epCallback[6])(void);
-	uint8_t epComplete[2*NB_ENDPOINT];
-	/*  memorize dummy buffer used for reception */
-	uint32_t pBufRx[MAXTRANSFER_SIZE>>2];
-	uint32_t pBufRx0[MAX_PACKET_SIZE_EP0>>2];
-    gpio_t usb_switch;
-}USBHAL_Private_t;
-
-uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo)
-{
-        return 1024;
-}
-
-void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state){
-    USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
-    gpio_write(&(priv->usb_switch),state);
-}
-
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) {
-    USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
-    USBHAL *obj= priv->inst;
-    uint32_t sofnum = (hpcd->Instance->FNR) & USB_FNR_FN;
-    void (USBHAL::*func)(int frame) = priv->sof;
-    (obj->*func)(sofnum);
-}
-
-USBHAL * USBHAL::instance;
-
-USBHAL::USBHAL(void) {
-    /*  init parameter  */
-    USBHAL_Private_t *HALPriv = new(USBHAL_Private_t);
-    hpcd.Instance = USB;
-    /*  initialized Init to zero (constructor does not zero initialized the
-     *  area */
-    /*  initialized all field of init including 0 field  */
-    /*  constructor does not fill with zero */
-    memset(&hpcd.Init, 0, sizeof(hpcd.Init));
-    hpcd.Init.dev_endpoints = NB_ENDPOINT;
-    hpcd.Init.ep0_mps =   MAX_PACKET_SIZE_EP0;
-    hpcd.Init.phy_itface = PCD_PHY_EMBEDDED;
-    hpcd.Init.Sof_enable = 1;
-    hpcd.Init.speed = PCD_SPEED_FULL;
-    /*  pass instance for usage inside call back */
-    HALPriv->inst = this;
-    HALPriv->bus_reset = &USBHAL::busReset;
-    HALPriv->suspend_change = &USBHAL::suspendStateChanged;
-    HALPriv->connect_change = &USBHAL::connectStateChanged;
-    HALPriv->sof = &USBHAL::SOF;
-    HALPriv->ep0_setup = &USBHAL::EP0setupCallback;
-    HALPriv->ep_realise = &USBHAL::realiseEndpoint;
-    HALPriv->ep0_in = &USBHAL::EP0in;
-    HALPriv->ep0_out = &USBHAL::EP0out;
-    HALPriv->ep0_read = &USBHAL::EP0read;
-    hpcd.pData = (void*)HALPriv;
-    HALPriv->epCallback[0] = &USBHAL::EP1_OUT_callback;
-    HALPriv->epCallback[1] = &USBHAL::EP1_IN_callback;
-    HALPriv->epCallback[2] = &USBHAL::EP2_OUT_callback;
-    HALPriv->epCallback[3] = &USBHAL::EP2_IN_callback;
-    HALPriv->epCallback[4] = &USBHAL::EP3_OUT_callback;
-    HALPriv->epCallback[5] = &USBHAL::EP3_IN_callback;
-    instance = this;
-    __HAL_RCC_GPIOA_CLK_ENABLE();
-    /* Configure USB DM pin. This is optional, and maintained only for user guidance. */
-    pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_USB));
-    pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_USB));
-    __HAL_RCC_GPIOG_CLK_ENABLE();
-    gpio_init_out(&HALPriv->usb_switch,PG_6);
-    /* Enable USB Clock */
-    __HAL_RCC_USB_CLK_ENABLE();
-    /* Enable SYSCFG Clock */
-    __HAL_RCC_SYSCFG_CLK_ENABLE();
-    hpcd.State = HAL_PCD_STATE_RESET;
-    HAL_PCD_Init(&hpcd);
-    /* hardcoded size of FIFO according definition*/
-    HAL_PCDEx_PMAConfig(&hpcd , 0x00 , PCD_SNG_BUF, 0x30);
-    HAL_PCDEx_PMAConfig(&hpcd , 0x80 , PCD_SNG_BUF, 0x70);
-#if 1
-    HAL_PCDEx_PMAConfig(&hpcd , 0x3, PCD_DBL_BUF, 0x018000b0);
-#else
-    HAL_PCDEx_PMAConfig(&hpcd , 0x3, PCD_SNG_BUF, 0x180);
-#endif
-    HAL_PCDEx_PMAConfig(&hpcd , 0x83, PCD_SNG_BUF, 0xb0);
-    NVIC_SetVector(USBHAL_IRQn,(uint32_t)&_usbisr);
-    NVIC_SetPriority(USBHAL_IRQn, 1);
-    HAL_PCD_Start(&hpcd);
-}
-#endif
diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32L053C8.h b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32L053C8.h
deleted file mode 100644
index 69b6b8196cb..00000000000
--- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32L053C8.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/* Copyright (c) 2016 mbed.org, MIT License
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
-* and associated documentation files (the "Software"), to deal in the Software without
-* restriction, including without limitation the rights to use, copy, modify, merge, publish,
-* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
-* Software is furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in all copies or
-* substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
-* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
-* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-#ifndef USBHAL_STM32L053C8_H
-#define USBHAL_STM32L053C8_H
-
-#define USBHAL_IRQn  USB_IRQn
-
-/*  must be multiple of 4 bytes */
-#define NB_ENDPOINT 8
-#define MAXTRANSFER_SIZE  0x200
-#define FIFO_USB_RAM_SIZE (MAXTRANSFER_SIZE+MAX_PACKET_SIZE_EP0+MAX_PACKET_SIZE_EP1+MAX_PACKET_SIZE_EP2+MAX_PACKET_SIZE_EP3)
-#if (FIFO_USB_RAM_SIZE > 0x500)
-#error "FIFO dimensioning incorrect"
-#endif
-
-typedef struct
-{
-	USBHAL *inst;
-	void (USBHAL::*bus_reset)(void);
-	void (USBHAL::*sof)(int frame);
-	void (USBHAL::*connect_change)(unsigned int  connected);
-	void (USBHAL::*suspend_change)(unsigned int suspended);
-	void (USBHAL::*ep0_setup)(void);
-	void (USBHAL::*ep0_in)(void);
-	void (USBHAL::*ep0_out)(void);
-	void (USBHAL::*ep0_read)(void);
-	bool (USBHAL::*ep_realise)(uint8_t endpoint, uint32_t maxPacket, uint32_t flags);
-	bool (USBHAL::*epCallback[6])(void);
-	uint8_t epComplete[2*NB_ENDPOINT];
-	/*  memorize dummy buffer used for reception */
-	uint32_t pBufRx[MAXTRANSFER_SIZE>>2];
-	uint32_t pBufRx0[MAX_PACKET_SIZE_EP0>>2];
-    gpio_t usb_switch;
-}USBHAL_Private_t;
-
-uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo)
-{
-        return 1024;
-}
-
-void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
-{
-    USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
-    gpio_write(&(priv->usb_switch),state);
-}
-
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
-{
-    USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
-    USBHAL *obj= priv->inst;
-    uint32_t sofnum = (hpcd->Instance->FNR) & USB_FNR_FN;
-    void (USBHAL::*func)(int frame) = priv->sof;
-    (obj->*func)(sofnum);
-}
-
-USBHAL * USBHAL::instance;
-
-USBHAL::USBHAL(void)
-{
-    /*  init parameter  */
-    USBHAL_Private_t *HALPriv = new(USBHAL_Private_t);
-    hpcd.Instance = USB;
-    /*  initialized Init to zero (constructor does not zero initialized the
-     *  area */
-    /*  initialized all field of init including 0 field  */
-    /*  constructor does not fill with zero */
-    memset(&hpcd.Init, 0, sizeof(hpcd.Init));
-    hpcd.Init.dev_endpoints = NB_ENDPOINT;
-    hpcd.Init.ep0_mps =   MAX_PACKET_SIZE_EP0;
-    hpcd.Init.phy_itface = PCD_PHY_EMBEDDED;
-    hpcd.Init.Sof_enable = 1;
-    hpcd.Init.speed = PCD_SPEED_FULL;
-    /*  pass instance for usage inside call back */
-    HALPriv->inst = this;
-    HALPriv->bus_reset = &USBHAL::busReset;
-    HALPriv->suspend_change = &USBHAL::suspendStateChanged;
-    HALPriv->connect_change = &USBHAL::connectStateChanged;
-    HALPriv->sof = &USBHAL::SOF;
-    HALPriv->ep0_setup = &USBHAL::EP0setupCallback;
-    HALPriv->ep_realise = &USBHAL::realiseEndpoint;
-    HALPriv->ep0_in = &USBHAL::EP0in;
-    HALPriv->ep0_out = &USBHAL::EP0out;
-    HALPriv->ep0_read = &USBHAL::EP0read;
-    hpcd.pData = (void*)HALPriv;
-    HALPriv->epCallback[0] = &USBHAL::EP1_OUT_callback;
-    HALPriv->epCallback[1] = &USBHAL::EP1_IN_callback;
-    HALPriv->epCallback[2] = &USBHAL::EP2_OUT_callback;
-    HALPriv->epCallback[3] = &USBHAL::EP2_IN_callback;
-    HALPriv->epCallback[4] = &USBHAL::EP3_OUT_callback;
-    HALPriv->epCallback[5] = &USBHAL::EP3_IN_callback;
-    instance = this;
-    
-    /* Configure USB DM pin. This is optional, and maintained only for user guidance. */
-    __HAL_RCC_GPIOA_CLK_ENABLE();
-    pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_USB));
-    pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_USB));
-    
-    /* Enable USB Clock */
-    __HAL_RCC_USB_CLK_ENABLE();
-    
-    /* Enable SYSCFG Clock */
-    __HAL_RCC_SYSCFG_CLK_ENABLE();
-    hpcd.State = HAL_PCD_STATE_RESET;
-    HAL_PCD_Init(&hpcd);
-    
-    /* hardcoded size of FIFO according definition*/
-    HAL_PCDEx_PMAConfig(&hpcd , 0x00 , PCD_SNG_BUF, 0x30);
-    HAL_PCDEx_PMAConfig(&hpcd , 0x80 , PCD_SNG_BUF, 0x70);
-#if 1
-    HAL_PCDEx_PMAConfig(&hpcd , 0x3, PCD_DBL_BUF, 0x018000b0);
-#else
-    HAL_PCDEx_PMAConfig(&hpcd , 0x3, PCD_SNG_BUF, 0x180);
-#endif
-    HAL_PCDEx_PMAConfig(&hpcd , 0x83, PCD_SNG_BUF, 0xb0);
-    NVIC_SetVector(USBHAL_IRQn,(uint32_t)&_usbisr);
-    NVIC_SetPriority(USBHAL_IRQn, 1);
-    HAL_PCD_Start(&hpcd);
-}
-#endif
diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32L072CZ.h b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32L072CZ.h
deleted file mode 100644
index 628701af4bb..00000000000
--- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32L072CZ.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/* Copyright (c) 2016 mbed.org, MIT License
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
-* and associated documentation files (the "Software"), to deal in the Software without
-* restriction, including without limitation the rights to use, copy, modify, merge, publish,
-* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
-* Software is furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in all copies or
-* substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
-* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
-* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-#ifndef USBHAL_STM32L072CZ_H
-#define USBHAL_STM32L072CZ_H
-
-#define USBHAL_IRQn  USB_IRQn
-
-/*  must be multiple of 4 bytes */
-#define NB_ENDPOINT 8
-#define MAXTRANSFER_SIZE  0x200
-#define FIFO_USB_RAM_SIZE (MAXTRANSFER_SIZE+MAX_PACKET_SIZE_EP0+MAX_PACKET_SIZE_EP1+MAX_PACKET_SIZE_EP2+MAX_PACKET_SIZE_EP3)
-#if (FIFO_USB_RAM_SIZE > 0x500)
-#error "FIFO dimensioning incorrect"
-#endif
-
-typedef struct
-{
-	USBHAL *inst;
-	void (USBHAL::*bus_reset)(void);
-	void (USBHAL::*sof)(int frame);
-	void (USBHAL::*connect_change)(unsigned int  connected);
-	void (USBHAL::*suspend_change)(unsigned int suspended);
-	void (USBHAL::*ep0_setup)(void);
-	void (USBHAL::*ep0_in)(void);
-	void (USBHAL::*ep0_out)(void);
-	void (USBHAL::*ep0_read)(void);
-	bool (USBHAL::*ep_realise)(uint8_t endpoint, uint32_t maxPacket, uint32_t flags);
-	bool (USBHAL::*epCallback[6])(void);
-	uint8_t epComplete[2*NB_ENDPOINT];
-	/*  memorize dummy buffer used for reception */
-	uint32_t pBufRx[MAXTRANSFER_SIZE>>2];
-	uint32_t pBufRx0[MAX_PACKET_SIZE_EP0>>2];
-    gpio_t usb_switch;
-}USBHAL_Private_t;
-
-uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo)
-{
-        return 1024;
-}
-
-void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
-{
-    USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
-    gpio_write(&(priv->usb_switch),state);
-}
-
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
-{
-    USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
-    USBHAL *obj= priv->inst;
-    uint32_t sofnum = (hpcd->Instance->FNR) & USB_FNR_FN;
-    void (USBHAL::*func)(int frame) = priv->sof;
-    (obj->*func)(sofnum);
-}
-
-USBHAL * USBHAL::instance;
-
-USBHAL::USBHAL(void)
-{
-    /*  init parameter  */
-    USBHAL_Private_t *HALPriv = new(USBHAL_Private_t);
-    hpcd.Instance = USB;
-    /*  initialized Init to zero (constructor does not zero initialized the
-     *  area */
-    /*  initialized all field of init including 0 field  */
-    /*  constructor does not fill with zero */
-    memset(&hpcd.Init, 0, sizeof(hpcd.Init));
-    hpcd.Init.dev_endpoints = NB_ENDPOINT;
-    hpcd.Init.ep0_mps =   MAX_PACKET_SIZE_EP0;
-    hpcd.Init.phy_itface = PCD_PHY_EMBEDDED;
-    hpcd.Init.Sof_enable = 1;
-    hpcd.Init.speed = PCD_SPEED_FULL;
-    /*  pass instance for usage inside call back */
-    HALPriv->inst = this;
-    HALPriv->bus_reset = &USBHAL::busReset;
-    HALPriv->suspend_change = &USBHAL::suspendStateChanged;
-    HALPriv->connect_change = &USBHAL::connectStateChanged;
-    HALPriv->sof = &USBHAL::SOF;
-    HALPriv->ep0_setup = &USBHAL::EP0setupCallback;
-    HALPriv->ep_realise = &USBHAL::realiseEndpoint;
-    HALPriv->ep0_in = &USBHAL::EP0in;
-    HALPriv->ep0_out = &USBHAL::EP0out;
-    HALPriv->ep0_read = &USBHAL::EP0read;
-    hpcd.pData = (void*)HALPriv;
-    HALPriv->epCallback[0] = &USBHAL::EP1_OUT_callback;
-    HALPriv->epCallback[1] = &USBHAL::EP1_IN_callback;
-    HALPriv->epCallback[2] = &USBHAL::EP2_OUT_callback;
-    HALPriv->epCallback[3] = &USBHAL::EP2_IN_callback;
-    HALPriv->epCallback[4] = &USBHAL::EP3_OUT_callback;
-    HALPriv->epCallback[5] = &USBHAL::EP3_IN_callback;
-    instance = this;
-    
-    /* Configure USB DM pin. This is optional, and maintained only for user guidance. */
-    __HAL_RCC_GPIOA_CLK_ENABLE();
-    pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_USB));
-    pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_USB));
-    
-    /* Enable USB Clock */
-    __HAL_RCC_USB_CLK_ENABLE();
-    
-    /* Enable SYSCFG Clock */
-    __HAL_RCC_SYSCFG_CLK_ENABLE();
-    hpcd.State = HAL_PCD_STATE_RESET;
-    HAL_PCD_Init(&hpcd);
-    
-    /* hardcoded size of FIFO according definition*/
-    HAL_PCDEx_PMAConfig(&hpcd , 0x00 , PCD_SNG_BUF, 0x30);
-    HAL_PCDEx_PMAConfig(&hpcd , 0x80 , PCD_SNG_BUF, 0x70);
-    HAL_PCDEx_PMAConfig(&hpcd , 0x3, PCD_DBL_BUF, 0x018000b0);
-    HAL_PCDEx_PMAConfig(&hpcd , 0x83, PCD_SNG_BUF, 0xb0);
-
-    NVIC_SetVector(USBHAL_IRQn,(uint32_t)&_usbisr);
-    NVIC_SetPriority(USBHAL_IRQn, 1);
-    HAL_PCD_Start(&hpcd);
-}
-#endif
diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32L475VG.h b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32L475VG.h
deleted file mode 100644
index 39a9df449c1..00000000000
--- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32L475VG.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/* Copyright (c) 2016 mbed.org, MIT License
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
-* and associated documentation files (the "Software"), to deal in the Software without
-* restriction, including without limitation the rights to use, copy, modify, merge, publish,
-* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
-* Software is furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in all copies or
-* substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
-* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
-* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-#ifndef USBHAL_STM32L475VG
-#define USBHAL_STM32L475VG
-
-#define USBHAL_IRQn  OTG_FS_IRQn
-
-
-#define NB_ENDPOINT  4
-/*  must be multiple of 4 bytes */
-#define MAXTRANSFER_SIZE  0x200
-#define FIFO_USB_RAM_SIZE (MAXTRANSFER_SIZE+MAX_PACKET_SIZE_EP0+MAX_PACKET_SIZE_EP1+MAX_PACKET_SIZE_EP2+MAX_PACKET_SIZE_EP3)
-#if (FIFO_USB_RAM_SIZE > 0x500)
-#error "FIFO dimensioning incorrect"
-#endif
-
-typedef struct
-{
-    USBHAL *inst;
-    void (USBHAL::*bus_reset)(void);
-    void (USBHAL::*sof)(int frame);
-    void (USBHAL::*connect_change)(unsigned int  connected);
-    void (USBHAL::*suspend_change)(unsigned int suspended);
-    void (USBHAL::*ep0_setup)(void);
-    void (USBHAL::*ep0_in)(void);
-    void (USBHAL::*ep0_out)(void);
-    void (USBHAL::*ep0_read)(void);
-    bool (USBHAL::*ep_realise)(uint8_t endpoint, uint32_t maxPacket, uint32_t flags);
-    bool (USBHAL::*epCallback[2*NB_ENDPOINT-2])(void);
-    uint8_t epComplete[8];
-    /*  memorize dummy buffer used for reception */
-    uint32_t pBufRx[MAXTRANSFER_SIZE>>2];
-    uint32_t pBufRx0[MAX_PACKET_SIZE_EP0>>2];
-}USBHAL_Private_t;
-
-uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo)
-{
-    uint32_t len;
-    if (fifo == 0) len = hpcd->Instance->DIEPTXF0_HNPTXFSIZ>>16;
-    else
-        len =  hpcd->Instance->DIEPTXF[fifo - 1] >> 16;
-    return len*4;
-}
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) {
-    USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
-    USBHAL *obj= priv->inst;
-    USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-    uint32_t sofnum = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF) >> 8;
-    void (USBHAL::*func)(int frame) = priv->sof;
-    /* fix me  call with same frame number */
-    (obj->*func)(sofnum);
-}
-
-USBHAL * USBHAL::instance;
-
-USBHAL::USBHAL(void) {
-    /*  init parameter  */
-    USBHAL_Private_t *HALPriv = new(USBHAL_Private_t);
-    /*  initialized all field of init including 0 field  */
-    /*  constructor does not fill with zero */
-    hpcd.Instance = USB_OTG_FS;
-    /*  initialized all field of init including 0 field  */
-    /*  constructor does not fill with zero */
-    memset(&hpcd.Init, 0, sizeof(hpcd.Init));
-    hpcd.Init.dev_endpoints = NB_ENDPOINT;
-    hpcd.Init.ep0_mps =   MAX_PACKET_SIZE_EP0;
-    hpcd.Init.phy_itface = PCD_PHY_EMBEDDED;
-    hpcd.Init.Sof_enable = 1;
-    hpcd.Init.speed = PCD_SPEED_FULL;
-    /*  pass instance for usage inside call back */
-    HALPriv->inst = this;
-    HALPriv->bus_reset = &USBHAL::busReset;
-    HALPriv->suspend_change = &USBHAL::suspendStateChanged;
-    HALPriv->connect_change = &USBHAL::connectStateChanged;
-    HALPriv->sof = &USBHAL::SOF;
-    HALPriv->ep0_setup = &USBHAL::EP0setupCallback;
-    HALPriv->ep_realise = &USBHAL::realiseEndpoint;
-    HALPriv->ep0_in = &USBHAL::EP0in;
-    HALPriv->ep0_out = &USBHAL::EP0out;
-    HALPriv->ep0_read = &USBHAL::EP0read;
-    hpcd.pData = (void*)HALPriv;
-    HALPriv->epCallback[0] = &USBHAL::EP1_OUT_callback;
-    HALPriv->epCallback[1] = &USBHAL::EP1_IN_callback;
-    HALPriv->epCallback[2] = &USBHAL::EP2_OUT_callback;
-    HALPriv->epCallback[3] = &USBHAL::EP2_IN_callback;
-    HALPriv->epCallback[4] = &USBHAL::EP3_OUT_callback;
-    HALPriv->epCallback[5] = &USBHAL::EP3_IN_callback;
-    instance = this;
-
-    __HAL_RCC_PWR_CLK_ENABLE();
-
-    HAL_PWREx_EnableVddUSB(); 
-    /* Configure USB VBUS GPIO */
-    __HAL_RCC_GPIOC_CLK_ENABLE();
-
-    /* Configure USB FS GPIOs */
-    __HAL_RCC_GPIOA_CLK_ENABLE();
-
-    /* Configure DM DP Pins */
-    pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
-    pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
-
-    /* Configure VBUS Pin */
-    pin_function(PC_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
-
-    __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
-
-    hpcd.State = HAL_PCD_STATE_RESET;
-
-    HAL_PCD_Init(&hpcd);
-    /* 1.25kbytes */
-    /* min value 16 (= 16 x 4 bytes) */
-    /*  max value 256 (= 1K bytes ) */
-    /*  maximum sum is 0x140 */
-    HAL_PCDEx_SetRxFiFo(&hpcd, (MAXTRANSFER_SIZE/4));
-    /*  bulk/int 64 bytes in FS  */
-    HAL_PCDEx_SetTxFiFo(&hpcd, 0, (MAX_PACKET_SIZE_EP0/4)+1);
-    /*  bulk/int bytes in FS */
-    HAL_PCDEx_SetTxFiFo(&hpcd, 1, (MAX_PACKET_SIZE_EP1/4)+1);
-    HAL_PCDEx_SetTxFiFo(&hpcd, 2, (MAX_PACKET_SIZE_EP2/4));
-    /* ISOchronous */
-    HAL_PCDEx_SetTxFiFo(&hpcd, 3, (MAX_PACKET_SIZE_EP3/4));
-
-    NVIC_SetVector(USBHAL_IRQn,(uint32_t)&_usbisr);
-    NVIC_SetPriority( USBHAL_IRQn, 1);
-
-    HAL_PCD_Start(&hpcd);
-}
-
-#endif
diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32L476VG.h b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32L476VG.h
deleted file mode 100644
index b08bce8b40a..00000000000
--- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32L476VG.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/* Copyright (c) 2016 mbed.org, MIT License
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
-* and associated documentation files (the "Software"), to deal in the Software without
-* restriction, including without limitation the rights to use, copy, modify, merge, publish,
-* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
-* Software is furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in all copies or
-* substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
-* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
-* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-#ifndef USBHAL_STM32L476VG
-#define USBHAL_STM32L476VG
-
-#define USBHAL_IRQn  OTG_FS_IRQn
-
-
-#define NB_ENDPOINT  4
-/*  must be multiple of 4 bytes */
-#define MAXTRANSFER_SIZE  0x200
-#define FIFO_USB_RAM_SIZE (MAXTRANSFER_SIZE+MAX_PACKET_SIZE_EP0+MAX_PACKET_SIZE_EP1+MAX_PACKET_SIZE_EP2+MAX_PACKET_SIZE_EP3)
-#if (FIFO_USB_RAM_SIZE > 0x500)
-#error "FIFO dimensioning incorrect"
-#endif
-
-typedef struct
-{
-    USBHAL *inst;
-    void (USBHAL::*bus_reset)(void);
-    void (USBHAL::*sof)(int frame);
-    void (USBHAL::*connect_change)(unsigned int  connected);
-    void (USBHAL::*suspend_change)(unsigned int suspended);
-    void (USBHAL::*ep0_setup)(void);
-    void (USBHAL::*ep0_in)(void);
-    void (USBHAL::*ep0_out)(void);
-    void (USBHAL::*ep0_read)(void);
-    bool (USBHAL::*ep_realise)(uint8_t endpoint, uint32_t maxPacket, uint32_t flags);
-    bool (USBHAL::*epCallback[2*NB_ENDPOINT-2])(void);
-    uint8_t epComplete[8];
-    /*  memorize dummy buffer used for reception */
-    uint32_t pBufRx[MAXTRANSFER_SIZE>>2];
-    uint32_t pBufRx0[MAX_PACKET_SIZE_EP0>>2];
-}USBHAL_Private_t;
-
-uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo)
-{
-    uint32_t len;
-    if (fifo == 0) len = hpcd->Instance->DIEPTXF0_HNPTXFSIZ>>16;
-    else
-        len =  hpcd->Instance->DIEPTXF[fifo - 1] >> 16;
-    return len*4;
-}
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) {
-    USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
-    USBHAL *obj= priv->inst;
-    USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-    uint32_t sofnum = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF) >> 8;
-    void (USBHAL::*func)(int frame) = priv->sof;
-    /* fix me  call with same frame number */
-    (obj->*func)(sofnum);
-}
-
-USBHAL * USBHAL::instance;
-
-USBHAL::USBHAL(void) {
-    /*  init parameter  */
-    USBHAL_Private_t *HALPriv = new(USBHAL_Private_t);
-    /*  initialized all field of init including 0 field  */
-    /*  constructor does not fill with zero */
-    hpcd.Instance = USB_OTG_FS;
-    /*  initialized all field of init including 0 field  */
-    /*  constructor does not fill with zero */
-    memset(&hpcd.Init, 0, sizeof(hpcd.Init));
-    hpcd.Init.dev_endpoints = NB_ENDPOINT;
-    hpcd.Init.ep0_mps =   MAX_PACKET_SIZE_EP0;
-    hpcd.Init.phy_itface = PCD_PHY_EMBEDDED;
-    hpcd.Init.Sof_enable = 1;
-    hpcd.Init.speed = PCD_SPEED_FULL;
-    /*  pass instance for usage inside call back */
-    HALPriv->inst = this;
-    HALPriv->bus_reset = &USBHAL::busReset;
-    HALPriv->suspend_change = &USBHAL::suspendStateChanged;
-    HALPriv->connect_change = &USBHAL::connectStateChanged;
-    HALPriv->sof = &USBHAL::SOF;
-    HALPriv->ep0_setup = &USBHAL::EP0setupCallback;
-    HALPriv->ep_realise = &USBHAL::realiseEndpoint;
-    HALPriv->ep0_in = &USBHAL::EP0in;
-    HALPriv->ep0_out = &USBHAL::EP0out;
-    HALPriv->ep0_read = &USBHAL::EP0read;
-    hpcd.pData = (void*)HALPriv;
-    HALPriv->epCallback[0] = &USBHAL::EP1_OUT_callback;
-    HALPriv->epCallback[1] = &USBHAL::EP1_IN_callback;
-    HALPriv->epCallback[2] = &USBHAL::EP2_OUT_callback;
-    HALPriv->epCallback[3] = &USBHAL::EP2_IN_callback;
-    HALPriv->epCallback[4] = &USBHAL::EP3_OUT_callback;
-    HALPriv->epCallback[5] = &USBHAL::EP3_IN_callback;
-    instance = this;
-
-    __HAL_RCC_PWR_CLK_ENABLE();
-
-    HAL_PWREx_EnableVddUSB(); 
-    /* Configure USB VBUS GPIO */
-    __HAL_RCC_GPIOC_CLK_ENABLE();
-
-    /* Configure USB FS GPIOs */
-    __HAL_RCC_GPIOA_CLK_ENABLE();
-
-    /* Configure DM DP Pins */
-    pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
-    pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
-
-    /* Configure VBUS Pin */
-    pin_function(PC_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
-
-    __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
-
-    hpcd.State = HAL_PCD_STATE_RESET;
-
-    HAL_PCD_Init(&hpcd);
-    /* 1.25kbytes */
-    /* min value 16 (= 16 x 4 bytes) */
-    /*  max value 256 (= 1K bytes ) */
-    /*  maximum sum is 0x140 */
-    HAL_PCDEx_SetRxFiFo(&hpcd, (MAXTRANSFER_SIZE/4));
-    /*  bulk/int 64 bytes in FS  */
-    HAL_PCDEx_SetTxFiFo(&hpcd, 0, (MAX_PACKET_SIZE_EP0/4)+1);
-    /*  bulk/int bytes in FS */
-    HAL_PCDEx_SetTxFiFo(&hpcd, 1, (MAX_PACKET_SIZE_EP1/4)+1);
-    HAL_PCDEx_SetTxFiFo(&hpcd, 2, (MAX_PACKET_SIZE_EP2/4));
-    /* ISOchronous */
-    HAL_PCDEx_SetTxFiFo(&hpcd, 3, (MAX_PACKET_SIZE_EP3/4));
-
-    NVIC_SetVector(USBHAL_IRQn,(uint32_t)&_usbisr);
-    NVIC_SetPriority( USBHAL_IRQn, 1);
-
-    HAL_PCD_Start(&hpcd);
-}
-
-#endif
diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM_144_64pins.h b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM_144_64pins.h
deleted file mode 100644
index 200369d8dc2..00000000000
--- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM_144_64pins.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* Copyright (c) 2016 mbed.org, MIT License
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
-* and associated documentation files (the "Software"), to deal in the Software without
-* restriction, including without limitation the rights to use, copy, modify, merge, publish,
-* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
-* Software is furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in all copies or
-* substantial portions of the Software.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
-* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
-* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-#ifndef USBHAL_STM32_144_64
-#define USBHAL_STM32_144_64
-
-#define USBHAL_IRQn  OTG_FS_IRQn
-/*  must be multiple of 4 bytes */
-#define NB_ENDPOINT 4
-#define MAXTRANSFER_SIZE  0x200
-#define FIFO_USB_RAM_SIZE (MAXTRANSFER_SIZE+MAX_PACKET_SIZE_EP0+MAX_PACKET_SIZE_EP1+MAX_PACKET_SIZE_EP2+MAX_PACKET_SIZE_EP3)
-#if (FIFO_USB_RAM_SIZE > 0x500)
-#error "FIFO dimensioning incorrect"
-#endif
-
-typedef struct
-{
-    USBHAL *inst;
-    void (USBHAL::*bus_reset)(void);
-    void (USBHAL::*sof)(int frame);
-    void (USBHAL::*connect_change)(unsigned int  connected);
-    void (USBHAL::*suspend_change)(unsigned int suspended);
-    void (USBHAL::*ep0_setup)(void);
-    void (USBHAL::*ep0_in)(void);
-    void (USBHAL::*ep0_out)(void);
-    void (USBHAL::*ep0_read)(void);
-    bool (USBHAL::*ep_realise)(uint8_t endpoint, uint32_t maxPacket, uint32_t flags);
-    bool (USBHAL::*epCallback[2*NB_ENDPOINT-2])(void);
-    /*  memorize dummy buffer used for reception */
-    uint32_t pBufRx[MAXTRANSFER_SIZE>>2];
-    uint32_t pBufRx0[MAX_PACKET_SIZE_EP0>>2];
-    uint8_t epComplete[2*NB_ENDPOINT];
-}USBHAL_Private_t;
-
-uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo)
-{
-    uint32_t len;
-    if (fifo == 0) len = hpcd->Instance->DIEPTXF0_HNPTXFSIZ>>16;
-    else
-        len =  hpcd->Instance->DIEPTXF[fifo - 1] >> 16;
-    return len*4;
-}
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) 
-{
-    USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
-    USBHAL *obj= priv->inst;
-    USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-    uint32_t sofnum = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF) >> 8;
-    void (USBHAL::*func)(int frame) = priv->sof;
-    (obj->*func)(sofnum);
-}
-
-
-USBHAL * USBHAL::instance;
-
-USBHAL::USBHAL(void) {
-    /*  init parameter  */
-    USBHAL_Private_t *HALPriv = new(USBHAL_Private_t);
-    hpcd.Instance = USB_OTG_FS;
-    memset(&hpcd.Init, 0, sizeof(hpcd.Init));
-    hpcd.Init.dev_endpoints = NB_ENDPOINT;
-    hpcd.Init.ep0_mps =   MAX_PACKET_SIZE_EP0;
-    hpcd.Init.phy_itface = PCD_PHY_EMBEDDED;
-    hpcd.Init.Sof_enable = 1;
-
-    hpcd.Init.speed = PCD_SPEED_FULL;
-    //hpcd.Init.vbus_sensing_enable = 0;
-    //hpcd.Init.lpm_enable = 0;
-    /*  pass instance for usage inside call back */
-    HALPriv->inst = this;
-    HALPriv->bus_reset = &USBHAL::busReset;
-    HALPriv->suspend_change = &USBHAL::suspendStateChanged;
-    HALPriv->connect_change = &USBHAL::connectStateChanged;
-    HALPriv->sof = &USBHAL::SOF;
-    HALPriv->ep0_setup = &USBHAL::EP0setupCallback;
-    HALPriv->ep_realise = &USBHAL::realiseEndpoint;
-    HALPriv->ep0_in = &USBHAL::EP0in;
-    HALPriv->ep0_out = &USBHAL::EP0out;
-    HALPriv->ep0_read = &USBHAL::EP0read;
-    hpcd.pData = (void*)HALPriv;
-    HALPriv->epCallback[0] = &USBHAL::EP1_OUT_callback;
-    HALPriv->epCallback[1] = &USBHAL::EP1_IN_callback;
-    HALPriv->epCallback[2] = &USBHAL::EP2_OUT_callback;
-    HALPriv->epCallback[3] = &USBHAL::EP2_IN_callback;
-    HALPriv->epCallback[4] = &USBHAL::EP3_OUT_callback;
-    HALPriv->epCallback[5] = &USBHAL::EP3_IN_callback;
-    instance = this;
-    // Enable power and clocking
-    /*  board 144 pin all similar  */
-    __HAL_RCC_GPIOA_CLK_ENABLE();
-    pin_function(PA_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));  /* OTG_FS_SOF */
-    pin_function(PA_9, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF10_OTG_FS));  /* OTG_FS_VBUS */
-    pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)); /* OTG_FS_ID */
-    pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); /* OTG_FS_DM */
-    pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); /* OTG_FS_DP */
-
-    __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
-    __HAL_RCC_SYSCFG_CLK_ENABLE();
-    hpcd.State = HAL_PCD_STATE_RESET;
-    HAL_PCD_Init(&hpcd);
-    /* 1.25kbytes */
-    /* min value 16 (= 16 x 4 bytes) */
-    /*  max value 256 (= 1K bytes ) */
-    /*  maximum sum is 0x140 */
-    HAL_PCDEx_SetRxFiFo(&hpcd, (MAXTRANSFER_SIZE/4));
-    /*  bulk/int 64 bytes in FS  */
-    HAL_PCDEx_SetTxFiFo(&hpcd, 0, (MAX_PACKET_SIZE_EP0/4)+1);
-    /*  bulk/int bytes in FS */
-    HAL_PCDEx_SetTxFiFo(&hpcd, 1, (MAX_PACKET_SIZE_EP1/4)+1);
-    HAL_PCDEx_SetTxFiFo(&hpcd, 2, (MAX_PACKET_SIZE_EP2/4));
-    /* ISOchronous */
-    HAL_PCDEx_SetTxFiFo(&hpcd, 3, (MAX_PACKET_SIZE_EP3/4));
-    NVIC_SetVector(USBHAL_IRQn, (uint32_t)&_usbisr);
-    NVIC_SetPriority(USBHAL_IRQn, 1);
-    HAL_PCD_Start(&hpcd);
-}
-#endif
-
diff --git a/hal/flash_api.h b/hal/flash_api.h
index 1804250fd87..4231c083bac 100644
--- a/hal/flash_api.h
+++ b/hal/flash_api.h
@@ -75,9 +75,9 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address);
  */
 int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size);
 
-/** Program one page starting at defined address
+/** Program pages starting at defined address
  *
- * The page should be at page boundary, should not cross multiple sectors.
+ * The pages should not cross multiple sectors.
  * This function does not do any check for address alignments or if size is aligned to a page size.
  * @param obj The flash object
  * @param address The sector starting address
@@ -97,6 +97,7 @@ uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address);
 
 /** Get page size
  *
+ * The page size defines the writable page size
  * @param obj The flash object
  * @return The size of a page
  */
diff --git a/hal/mbed_ticker_api.c b/hal/mbed_ticker_api.c
index f4f8cfe7cc6..18ee36d9862 100644
--- a/hal/mbed_ticker_api.c
+++ b/hal/mbed_ticker_api.c
@@ -263,6 +263,7 @@ timestamp_t ticker_read(const ticker_data_t *const ticker)
 
 us_timestamp_t ticker_read_us(const ticker_data_t *const ticker)
 {
+    initialize(ticker);
     update_present_time(ticker);
     return ticker->queue->present_time;
 }
diff --git a/hal/ticker_api.h b/hal/ticker_api.h
index fceba2db87e..aaa063dd2b2 100644
--- a/hal/ticker_api.h
+++ b/hal/ticker_api.h
@@ -132,8 +132,9 @@ void ticker_insert_event(const ticker_data_t *const ticker, ticker_event_t *obj,
  *
  * The event will be executed in timestamp - ticker_read_us() us.
  *
- * @warning If an event is inserted with a timestamp less than the current
- * timestamp then the event will **not** be inserted.
+ * @note If an event is inserted with a timestamp less than the current
+ * timestamp then the event will be scheduled immediately resulting in
+ * an instant call to event handler.
  *
  * @param ticker    The ticker object.
  * @param obj       The event object to be inserted to the queue
diff --git a/mbed.h b/mbed.h
index 1e56e636401..b1cb710bcb1 100644
--- a/mbed.h
+++ b/mbed.h
@@ -16,6 +16,24 @@
 #ifndef MBED_H
 #define MBED_H
 
+#define MBED_LIBRARY_VERSION 156
+
+#if MBED_CONF_RTOS_PRESENT
+// RTOS present, this is valid only for mbed OS 5
+#define MBED_MAJOR_VERSION 5
+#define MBED_MINOR_VERSION 6
+#define MBED_PATCH_VERSION 5
+
+#else
+// mbed 2
+#define MBED_MAJOR_VERSION 2
+#define MBED_MINOR_VERSION 0
+#define MBED_PATCH_VERSION MBED_LIBRARY_VERSION
+#endif
+
+#define MBED_ENCODE_VERSION(major, minor, patch) ((major)*10000 + (minor)*100 + (patch))
+#define MBED_VERSION MBED_ENCODE_VERSION(MBED_MAJOR_VERSION, MBED_MINOR_VERSION, MBED_PATCH_VERSION)
+
 #if MBED_CONF_RTOS_PRESENT
 #include "rtos/rtos.h"
 #endif
diff --git a/platform/ATCmdParser.cpp b/platform/ATCmdParser.cpp
index 6200f1fa4b6..a787b58b2a2 100644
--- a/platform/ATCmdParser.cpp
+++ b/platform/ATCmdParser.cpp
@@ -380,3 +380,44 @@ void ATCmdParser::abort()
 {
     _aborted = true;
 }
+
+bool ATCmdParser::process_oob()
+{
+    if (!_fh->readable()) {
+        return false;
+    }
+
+    int i = 0;
+    while (true) {
+        // Receive next character
+        int c = getc();
+        if (c < 0) {
+            return false;
+        }
+        _buffer[i++] = c;
+        _buffer[i] = 0;
+
+        // Check for oob data
+        struct oob *oob = _oobs;
+        while (oob) {
+            if (i == (int)oob->len && memcmp(
+                    oob->prefix, _buffer, oob->len) == 0) {
+                debug_if(_dbg_on, "AT! %s\r\n", oob->prefix);
+                oob->cb();
+                return true;
+            }
+            oob = oob->next;
+        }
+        
+        // Clear the buffer when we hit a newline or ran out of space
+        // running out of space usually means we ran into binary data
+        if (i+1 >= _buffer_size ||
+            strcmp(&_buffer[i-_output_delim_size], _output_delimiter) == 0) {
+
+            debug_if(_dbg_on, "AT< %s", _buffer);
+            i = 0;
+        }
+    }
+}
+
+
diff --git a/platform/ATCmdParser.h b/platform/ATCmdParser.h
index 03b1ef6b2ac..c8fb0406340 100644
--- a/platform/ATCmdParser.h
+++ b/platform/ATCmdParser.h
@@ -24,6 +24,15 @@
 #include <cstdarg>
 #include "Callback.h"
 
+namespace mbed {
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_ATCmdParser ATCmdParser class
+ * @{
+ */
+
 /**
  * Parser class for parsing AT commands
  *
@@ -43,8 +52,6 @@
  * @endcode
  */
 
-namespace mbed {
-
 class ATCmdParser : private NonCopyable<ATCmdParser>
 {
 private:
@@ -288,7 +295,22 @@ class ATCmdParser : private NonCopyable<ATCmdParser>
      * recv operation.
      */
     void abort();
+    
+    /**
+    * Process out-of-band data
+    *
+    * Process out-of-band data in the receive buffer. This function
+    * returns immediately if there is no data to process.
+    *
+    * @return true if oob data processed, false otherwise
+    */
+    bool process_oob(void);
 };
+
+/**@}*/
+
+/**@}*/
+
 } //namespace mbed
 
 #endif //MBED_ATCMDPARSER_H
diff --git a/platform/CThunk.h b/platform/CThunk.h
index 90e150b6a9c..73c3aba1389 100644
--- a/platform/CThunk.h
+++ b/platform/CThunk.h
@@ -1,6 +1,10 @@
 
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_CThunk CThunk class
+ * @{
+ */
 /* General C++ Object Thunking class
  *
  * - allows direct callbacks to non-static C++ class functions
@@ -73,13 +77,11 @@
 
 /* IRQ/Exception compatible thunk entry function */
 typedef void (*CThunkEntry)(void);
-/** @}*/
 
 /**
  * Class for created a pointer with data bound to it
  *
  * @note Synchronization level: Not protected
- * @ingroup platform
  */
 template<class T>
 class CThunk
@@ -243,5 +245,9 @@ class CThunk
         }
 };
 
+/**@}*/
+
+/**@}*/
+
 #endif/*__CTHUNK_H__*/
 
diff --git a/platform/CallChain.h b/platform/CallChain.h
index 42e97e6d288..ffb786d2c2a 100644
--- a/platform/CallChain.h
+++ b/platform/CallChain.h
@@ -22,7 +22,17 @@
 #include <string.h>
 
 namespace mbed {
+
+
+typedef Callback<void()> *pFunctionPointer_t;
+class CallChainLink;
+
 /** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_CallChain CallChain class
+ * @{
+ */
 
 /** Group one or more functions in an instance of a CallChain, then call them in
  * sequence using CallChain::call(). Used mostly by the interrupt chaining code,
@@ -60,12 +70,7 @@ namespace mbed {
  *     chain.call();
  * }
  * @endcode
- * @ingroup platform
  */
-
-typedef Callback<void()> *pFunctionPointer_t;
-class CallChainLink;
-
 class CallChain : private NonCopyable<CallChain> {
 public:
     /** Create an empty chain
@@ -183,6 +188,10 @@ class CallChain : private NonCopyable<CallChain> {
     CallChainLink *_chain;
 };
 
+/**@}*/
+
+/**@}*/
+
 } // namespace mbed
 
 #endif
diff --git a/platform/Callback.h b/platform/Callback.h
index b9fd21e90aa..b300afefadc 100644
--- a/platform/Callback.h
+++ b/platform/Callback.h
@@ -24,12 +24,15 @@
 
 namespace mbed {
 /** \addtogroup platform */
-
+/** @{*/
+/**
+ * \defgroup platform_Callback Callback class
+ * @{
+ */
 
 /** Callback class based on template specialization
  *
  * @note Synchronization level: Not protected
- * @ingroup platform
  */
 template <typename F>
 class Callback;
@@ -67,7 +70,6 @@ namespace detail {
 /** Callback class based on template specialization
  *
  * @note Synchronization level: Not protected
- * @ingroup platform
  */
 template <typename R>
 class Callback<R()> {
@@ -77,7 +79,7 @@ class Callback<R()> {
      */
     Callback(R (*func)() = 0) {
         if (!func) {
-            _ops = 0;
+            memset(this, 0, sizeof(Callback));
         } else {
             generate(func);
         }
@@ -590,6 +592,7 @@ class Callback<R()> {
 
         MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
                 "Type F must not exceed the size of the Callback class");
+        memset(this, 0, sizeof(Callback));
         new (this) F(f);
         _ops = &ops;
     }
@@ -641,7 +644,6 @@ class Callback<R()> {
 /** Callback class based on template specialization
  *
  * @note Synchronization level: Not protected
- * @ingroup platform
  */
 template <typename R, typename A0>
 class Callback<R(A0)> {
@@ -651,7 +653,7 @@ class Callback<R(A0)> {
      */
     Callback(R (*func)(A0) = 0) {
         if (!func) {
-            _ops = 0;
+            memset(this, 0, sizeof(Callback));
         } else {
             generate(func);
         }
@@ -1165,6 +1167,7 @@ class Callback<R(A0)> {
 
         MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
                 "Type F must not exceed the size of the Callback class");
+        memset(this, 0, sizeof(Callback));
         new (this) F(f);
         _ops = &ops;
     }
@@ -1216,7 +1219,6 @@ class Callback<R(A0)> {
 /** Callback class based on template specialization
  *
  * @note Synchronization level: Not protected
- * @ingroup platform
  */
 template <typename R, typename A0, typename A1>
 class Callback<R(A0, A1)> {
@@ -1226,7 +1228,7 @@ class Callback<R(A0, A1)> {
      */
     Callback(R (*func)(A0, A1) = 0) {
         if (!func) {
-            _ops = 0;
+            memset(this, 0, sizeof(Callback));
         } else {
             generate(func);
         }
@@ -1741,6 +1743,7 @@ class Callback<R(A0, A1)> {
 
         MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
                 "Type F must not exceed the size of the Callback class");
+        memset(this, 0, sizeof(Callback));
         new (this) F(f);
         _ops = &ops;
     }
@@ -1792,7 +1795,6 @@ class Callback<R(A0, A1)> {
 /** Callback class based on template specialization
  *
  * @note Synchronization level: Not protected
- * @ingroup platform
  */
 template <typename R, typename A0, typename A1, typename A2>
 class Callback<R(A0, A1, A2)> {
@@ -1802,7 +1804,7 @@ class Callback<R(A0, A1, A2)> {
      */
     Callback(R (*func)(A0, A1, A2) = 0) {
         if (!func) {
-            _ops = 0;
+            memset(this, 0, sizeof(Callback));
         } else {
             generate(func);
         }
@@ -2318,6 +2320,7 @@ class Callback<R(A0, A1, A2)> {
 
         MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
                 "Type F must not exceed the size of the Callback class");
+        memset(this, 0, sizeof(Callback));
         new (this) F(f);
         _ops = &ops;
     }
@@ -2369,7 +2372,6 @@ class Callback<R(A0, A1, A2)> {
 /** Callback class based on template specialization
  *
  * @note Synchronization level: Not protected
- * @ingroup platform
  */
 template <typename R, typename A0, typename A1, typename A2, typename A3>
 class Callback<R(A0, A1, A2, A3)> {
@@ -2379,7 +2381,7 @@ class Callback<R(A0, A1, A2, A3)> {
      */
     Callback(R (*func)(A0, A1, A2, A3) = 0) {
         if (!func) {
-            _ops = 0;
+            memset(this, 0, sizeof(Callback));
         } else {
             generate(func);
         }
@@ -2896,6 +2898,7 @@ class Callback<R(A0, A1, A2, A3)> {
 
         MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
                 "Type F must not exceed the size of the Callback class");
+        memset(this, 0, sizeof(Callback));
         new (this) F(f);
         _ops = &ops;
     }
@@ -2947,7 +2950,6 @@ class Callback<R(A0, A1, A2, A3)> {
 /** Callback class based on template specialization
  *
  * @note Synchronization level: Not protected
- * @ingroup platform
  */
 template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
 class Callback<R(A0, A1, A2, A3, A4)> {
@@ -2957,7 +2959,7 @@ class Callback<R(A0, A1, A2, A3, A4)> {
      */
     Callback(R (*func)(A0, A1, A2, A3, A4) = 0) {
         if (!func) {
-            _ops = 0;
+            memset(this, 0, sizeof(Callback));
         } else {
             generate(func);
         }
@@ -3475,6 +3477,7 @@ class Callback<R(A0, A1, A2, A3, A4)> {
 
         MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
                 "Type F must not exceed the size of the Callback class");
+        memset(this, 0, sizeof(Callback));
         new (this) F(f);
         _ops = &ops;
     }
@@ -4540,6 +4543,9 @@ Callback<R(A0, A1, A2, A3, A4)> callback(const volatile U *obj, R (*func)(const
     return Callback<R(A0, A1, A2, A3, A4)>(func, obj);
 }
 
+/**@}*/
+
+/**@}*/
 
 } // namespace mbed
 
diff --git a/platform/CircularBuffer.h b/platform/CircularBuffer.h
index bb7fd38c547..b721791b810 100644
--- a/platform/CircularBuffer.h
+++ b/platform/CircularBuffer.h
@@ -20,11 +20,15 @@
 
 namespace mbed {
 /** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_CircularBuffer CircularBuffer functions
+ * @{
+ */
 
 /** Templated Circular buffer class
  *
  *  @note Synchronization level: Interrupt safe
- *  @ingroup platform
  */
 template<typename T, uint32_t BufferSize, typename CounterType = uint32_t>
 class CircularBuffer {
@@ -112,6 +116,10 @@ class CircularBuffer {
     volatile bool _full;
 };
 
+/**@}*/
+
+/**@}*/
+
 }
 
 #endif
diff --git a/platform/CriticalSectionLock.h b/platform/CriticalSectionLock.h
index 5199fbaf691..cb619769c8e 100644
--- a/platform/CriticalSectionLock.h
+++ b/platform/CriticalSectionLock.h
@@ -22,6 +22,13 @@
 
 namespace mbed {
 
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_CriticalSectionLock CriticalSectionLock functions
+ * @{
+ */
+
 /** RAII object for disabling, then restoring, interrupt state
   * Usage:
   * @code
@@ -65,6 +72,9 @@ class CriticalSectionLock {
     }
 };
 
+/**@}*/
+
+/**@}*/
 
 } // namespace mbed
 
diff --git a/platform/DeepSleepLock.h b/platform/DeepSleepLock.h
index ff5149d2e37..6b64022fc06 100644
--- a/platform/DeepSleepLock.h
+++ b/platform/DeepSleepLock.h
@@ -16,10 +16,18 @@
 #ifndef MBED_DEEPSLEEPLOCK_H
 #define MBED_DEEPSLEEPLOCK_H
 
+#include <limits.h>
 #include "platform/mbed_sleep.h"
+#include "platform/mbed_critical.h"
 
 namespace mbed {
 
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_DeepSleepLock DeepSleepLock functions
+ * @{
+ */
 
 /** RAII object for disabling, then restoring the deep sleep mode
   * Usage:
@@ -36,32 +44,55 @@ namespace mbed {
   * @endcode
   */
 class DeepSleepLock {
+private:
+    uint16_t _lock_count;
+
 public:
-    DeepSleepLock()
+    DeepSleepLock(): _lock_count(1)
     {
         sleep_manager_lock_deep_sleep();
     }
 
     ~DeepSleepLock()
     {
-        sleep_manager_unlock_deep_sleep();
+        if (_lock_count) {
+            sleep_manager_unlock_deep_sleep();
+        }
     }
 
     /** Mark the start of a locked deep sleep section
      */
     void lock()
     {
-        sleep_manager_lock_deep_sleep();
+        uint16_t count = core_util_atomic_incr_u16(&_lock_count, 1);
+        if (1 == count) {
+            sleep_manager_lock_deep_sleep();
+        }
+        if (0 == count) {
+            error("DeepSleepLock overflow (> USHRT_MAX)");
+        }
     }
 
     /** Mark the end of a locked deep sleep section
      */
     void unlock()
     {
-        sleep_manager_unlock_deep_sleep();
+        uint16_t count = core_util_atomic_decr_u16(&_lock_count, 1);
+        if (count == 0) {
+            sleep_manager_unlock_deep_sleep();
+        }
+        if (count == USHRT_MAX) {
+            core_util_critical_section_exit();
+            error("DeepSleepLock underflow (< 0)");
+        }
     }
 };
 
+/**@}*/
+
+/**@}*/
+
+
 }
 
 #endif
diff --git a/platform/DirHandle.h b/platform/DirHandle.h
index b1dcfe2b1f0..116ebf581dc 100644
--- a/platform/DirHandle.h
+++ b/platform/DirHandle.h
@@ -23,6 +23,11 @@
 
 namespace mbed {
 /** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_DirHandle DirHandle functions
+ * @{
+ */
 
 
 /** Represents a directory stream. Objects of this type are returned
@@ -40,7 +45,6 @@ namespace mbed {
  *
  *  @note to create a directory, @see Dir
  *  @note Synchronization level: Set by subclass
- *  @ingroup platform
  */
 class DirHandle : private NonCopyable<DirHandle> {
 public:
@@ -142,7 +146,9 @@ class DirHandle : private NonCopyable<DirHandle> {
     virtual void seekdir(off_t location) { seek(location); }
 };
 
+/**@}*/
 
+/**@}*/
 } // namespace mbed
 
 #endif /* MBED_DIRHANDLE_H */
diff --git a/platform/FileBase.h b/platform/FileBase.h
index 5df9ef8550d..4f6371923b2 100644
--- a/platform/FileBase.h
+++ b/platform/FileBase.h
@@ -27,19 +27,22 @@ typedef int FILEHANDLE;
 #include "platform/NonCopyable.h"
 
 namespace mbed {
-/** \addtogroup platform */
-/** @{*/
-
+    
 typedef enum {
     FilePathType,
     FileSystemPathType
 } PathType;
-/** @}*/
 
+/** \addtogroup platform */
+/** @{*/
 /**
- * @class FileBase
- * @ingroup platform
+ * \defgroup platform_FileBase FileBase class
+ * @{
  */
+/** Class FileBase
+ *
+ */
+ 
 class FileBase : private NonCopyable<FileBase> {
 public:
     FileBase(const char *name, PathType t);
@@ -62,6 +65,10 @@ class FileBase : private NonCopyable<FileBase> {
     const PathType _path_type;
 };
 
+/**@}*/
+
+/**@}*/
+
 } // namespace mbed
 
 #endif
diff --git a/platform/FileHandle.h b/platform/FileHandle.h
index a6b306b3fa6..6a769b4b8f2 100644
--- a/platform/FileHandle.h
+++ b/platform/FileHandle.h
@@ -26,6 +26,11 @@ typedef int FILEHANDLE;
 
 namespace mbed {
 /** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_FileHandle FileHandle functions
+ * @{
+ */
 
 
 /** Class FileHandle
@@ -36,7 +41,6 @@ namespace mbed {
  *
  *  @note to create a file, @see File
  *  @note Synchronization level: Set by subclass
- *  @ingroup platform
  */
 class FileHandle : private NonCopyable<FileHandle> {
 public:
@@ -254,6 +258,11 @@ class FileHandle : private NonCopyable<FileHandle> {
 
 std::FILE *fdopen(FileHandle *fh, const char *mode);
 
+/**@}*/
+
+/**@}*/
+
+
 } // namespace mbed
 
 #endif
diff --git a/platform/FileLike.h b/platform/FileLike.h
index 91a3f304d09..e75be50bfd3 100644
--- a/platform/FileLike.h
+++ b/platform/FileLike.h
@@ -23,14 +23,17 @@
 
 namespace mbed {
 /** \addtogroup platform */
-
-
-/* Class FileLike
+/** @{*/
+/**
+ * \defgroup platform_FileLike FileLike class
+ * @{
+ */
+/** Class FileLike
+ *
  *  A file-like object is one that can be opened with fopen by
  *  fopen("/name", mode).
  *
  *  @note Synchronization level: Set by subclass
- *  @ingroup platform
  */
 class FileLike : public FileHandle, public FileBase, private NonCopyable<FileLike> {
 public:
@@ -42,6 +45,9 @@ class FileLike : public FileHandle, public FileBase, private NonCopyable<FileLik
     virtual ~FileLike() {}
 };
 
+/**@}*/
+
+/**@}*/
 
 } // namespace mbed
 
diff --git a/platform/FilePath.h b/platform/FilePath.h
index 4c4dc65e15c..d380041ca05 100644
--- a/platform/FilePath.h
+++ b/platform/FilePath.h
@@ -23,15 +23,23 @@
 
 namespace mbed {
 /** \addtogroup platform */
-
+/** @{*/
 /**
- * @class FileSystem
- * @ingroup platform
+ * \defgroup platform_FilePath FilePath class
+ * @{
  */
-class FileSystem;
 
+class FileSystem;
+/** Class FilePath
+ *
+ */
+ 
 class FilePath {
 public:
+    /** Constructor FilePath
+     *
+     *  @param file_path     The path of file.
+     */ 
     FilePath(const char* file_path);
 
     const char* fileName(void);
@@ -48,6 +56,10 @@ class FilePath {
     FileBase* fb;
 };
 
+/**@}*/
+
+/**@}*/
+
 } // namespace mbed
 
 #endif
diff --git a/platform/FileSystemHandle.h b/platform/FileSystemHandle.h
index dda1f6f271d..713d6e5d7a2 100644
--- a/platform/FileSystemHandle.h
+++ b/platform/FileSystemHandle.h
@@ -24,8 +24,12 @@
 #include "platform/NonCopyable.h"
 
 namespace mbed {
-/** \addtogroup drivers */
+/** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_FileSystemHandle FileSystemHandle functions
+ * @{
+ */
 
 
 /** A filesystem-like object is one that can be used to open file-like
@@ -91,7 +95,9 @@ class FileSystemHandle : private NonCopyable<FileSystemHandle> {
      */
     virtual int mkdir(const char *path, mode_t mode);
 };
+/**@}*/
 
+/**@}*/
 
 } // namespace mbed
 
diff --git a/platform/FileSystemLike.h b/platform/FileSystemLike.h
index d8923391d6a..aef7913cf67 100644
--- a/platform/FileSystemLike.h
+++ b/platform/FileSystemLike.h
@@ -25,6 +25,11 @@
 
 namespace mbed {
 /** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_FileSystemLike FileSystemLike functions
+ * @{
+ */
 
 
 /** A filesystem-like object is one that can be used to open file-like
@@ -34,7 +39,6 @@ namespace mbed {
  *  of the rest of the functions just return error values).
  *
  * @note Synchronization level: Set by subclass
- * @ingroup platform
  */
 class FileSystemLike : public FileSystemHandle, public FileBase, private NonCopyable<FileSystemLike> {
 public:
@@ -79,6 +83,9 @@ class FileSystemLike : public FileSystemHandle, public FileBase, private NonCopy
     }
 };
 
+/**@}*/
+
+/**@}*/
 
 } // namespace mbed
 
diff --git a/platform/FunctionPointer.h b/platform/FunctionPointer.h
index a57195f7a83..18c34c2106e 100644
--- a/platform/FunctionPointer.h
+++ b/platform/FunctionPointer.h
@@ -23,13 +23,14 @@
 
 namespace mbed {
 /** \addtogroup platform */
-
+/** @{*/
+/**
+ * \defgroup platform_FunctionPointer FunctionPointer class
+ * @{
+ */
 
 // Declarations for backwards compatibility
 // To be foward compatible, code should adopt the Callback class
-/**
- * @ingroup platform
- */
 template <typename R, typename A1>
 class FunctionPointerArg1 : public Callback<R(A1)> {
 public:
@@ -61,9 +62,6 @@ class FunctionPointerArg1 : public Callback<R(A1)> {
     }
 };
 
-/**
- * @ingroup platform
- */
 template <typename R>
 class FunctionPointerArg1<R, void> : public Callback<R()> {
 public:
@@ -97,6 +95,10 @@ class FunctionPointerArg1<R, void> : public Callback<R()> {
 
 typedef FunctionPointerArg1<void, void> FunctionPointer;
 
+/**@}*/
+
+/**@}*/
+
 
 } // namespace mbed
 
diff --git a/platform/LocalFileSystem.h b/platform/LocalFileSystem.h
index 3bd64d8377e..ce0baafaf07 100644
--- a/platform/LocalFileSystem.h
+++ b/platform/LocalFileSystem.h
@@ -27,9 +27,12 @@
 namespace mbed {
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_LocalFileSystem LocalFileSystem functions
+ * @{
+ */
 
 FILEHANDLE local_file_open(const char* name, int flags);
-/** @}*/
 
 /**
  * @class LocalFileHandle
@@ -112,6 +115,10 @@ class LocalFileSystem : public FileSystemLike, private NonCopyable<LocalFileSyst
     virtual int remove(const char *filename);
 };
 
+/**@}*/
+
+/**@}*/
+
 } // namespace mbed
 
 #endif
diff --git a/platform/PlatformMutex.h b/platform/PlatformMutex.h
index 517fd3ad050..dc3b82bee6a 100644
--- a/platform/PlatformMutex.h
+++ b/platform/PlatformMutex.h
@@ -1,5 +1,10 @@
 
 /** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_PlatformMutex PlatformMutex class
+ * @{
+ */
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
  *
@@ -25,7 +30,6 @@
 typedef rtos::Mutex PlatformMutex;
 #else
 /** A stub mutex for when an RTOS is not present
- * @ingroup platform
 */
 class PlatformMutex : private mbed::NonCopyable<PlatformMutex> {
 public:
@@ -50,3 +54,6 @@ class PlatformMutex : private mbed::NonCopyable<PlatformMutex> {
 
 #endif
 
+/**@}*/
+
+/**@}*/
diff --git a/platform/SingletonPtr.h b/platform/SingletonPtr.h
index 369d6dbe2f1..848fd099f46 100644
--- a/platform/SingletonPtr.h
+++ b/platform/SingletonPtr.h
@@ -1,6 +1,10 @@
 
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_SingletonPtr SingletonPtr class
+ * @{
+ */
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
  *
@@ -55,7 +59,6 @@ inline static void singleton_unlock(void)
     osMutexRelease (singleton_mutex_id);
 #endif
 }
-/** @}*/
 
 /** Utility class for creating an using a singleton
  *
@@ -68,7 +71,6 @@ inline static void singleton_unlock(void)
  * @note: This class is lazily initialized on first use.
  * This class is a POD type so if it is not used it will
  * be garbage collected.
- * @ingroup platform
  */
 template <class T>
 struct SingletonPtr {
@@ -108,4 +110,6 @@ struct SingletonPtr {
 };
 
 #endif
+/**@}*/
 
+/**@}*/
diff --git a/platform/Stream.h b/platform/Stream.h
index fd74b0520f1..20b7e44afcb 100644
--- a/platform/Stream.h
+++ b/platform/Stream.h
@@ -26,16 +26,18 @@
 namespace mbed {
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_Stream Stream class
+ * @{
+ */
 
 extern void mbed_set_unbuffered_stream(std::FILE *_file);
 extern int mbed_getc(std::FILE *_file);
 extern char* mbed_gets(char *s, int size, std::FILE *_file);
-/** @}*/
 
 /** File stream
  *
  * @note Synchronization level: Set by subclass
- * @ingroup platform
  */
 class Stream : public FileLike, private NonCopyable<Stream> {
 
@@ -82,7 +84,9 @@ class Stream : public FileLike, private NonCopyable<Stream> {
         // Stub
     }
 };
+/**@}*/
 
+/**@}*/
 } // namespace mbed
 
 #endif
diff --git a/platform/Transaction.h b/platform/Transaction.h
index 8e262368800..23f03e07f22 100644
--- a/platform/Transaction.h
+++ b/platform/Transaction.h
@@ -21,9 +21,13 @@
 
 namespace mbed {
 /** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_Transaction Transaction class
+ * @{
+ */
 
 /** Transaction structure
- * @ingroup platform
  */
 typedef struct {
     void *tx_buffer;           /**< Tx buffer */
@@ -38,7 +42,6 @@ typedef struct {
 /** Transaction class defines a transaction.
  *
  * @note Synchronization level: Not protected
- * @ingroup platform
  */
 template<typename Class>
 class Transaction {
@@ -72,7 +75,9 @@ class Transaction {
     Class* _obj;
     transaction_t _data;
 };
+/**@}*/
 
+/**@}*/
 }
 
 #endif
diff --git a/platform/mbed_alloc_wrappers.cpp b/platform/mbed_alloc_wrappers.cpp
index 200ce2e5632..94318114726 100644
--- a/platform/mbed_alloc_wrappers.cpp
+++ b/platform/mbed_alloc_wrappers.cpp
@@ -207,26 +207,46 @@ extern "C" void * __wrap__memalign_r(struct _reent * r, size_t alignment, size_t
 
 
 /******************************************************************************/
-/* ARMCC memory allocation wrappers                                           */
+/* ARMCC / IAR memory allocation wrappers                                     */
 /******************************************************************************/
 
-#elif defined(TOOLCHAIN_ARM) // #if defined(TOOLCHAIN_GCC)
+#elif defined(TOOLCHAIN_ARM) || defined(__ICCARM__)
+
+#if defined(TOOLCHAIN_ARM)
+#define SUPER_MALLOC    $Super$$malloc
+#define SUB_MALLOC      $Sub$$malloc
+#define SUPER_REALLOC   $Super$$realloc
+#define SUB_REALLOC     $Sub$$realloc
+#define SUPER_CALLOC    $Super$$calloc
+#define SUB_CALLOC      $Sub$$calloc
+#define SUPER_FREE      $Super$$free
+#define SUB_FREE        $Sub$$free
+#elif defined(__ICCARM__)
+#define SUPER_MALLOC    $Super$$__iar_dlmalloc
+#define SUB_MALLOC      $Sub$$__iar_dlmalloc
+#define SUPER_REALLOC   $Super$$__iar_dlrealloc
+#define SUB_REALLOC     $Sub$$__iar_dlrealloc
+#define SUPER_CALLOC    $Super$$__iar_dlcalloc
+#define SUB_CALLOC      $Sub$$__iar_dlcalloc
+#define SUPER_FREE      $Super$$__iar_dlfree
+#define SUB_FREE        $Sub$$__iar_dlfree
+#endif
 
 /* Enable hooking of memory function only if tracing is also enabled */
 #if defined(MBED_MEM_TRACING_ENABLED) || defined(MBED_HEAP_STATS_ENABLED)
 
 extern "C" {
-    void *$Super$$malloc(size_t size);
-    void *$Super$$realloc(void *ptr, size_t size);
-    void *$Super$$calloc(size_t nmemb, size_t size);
-    void $Super$$free(void *ptr);
+    void *SUPER_MALLOC(size_t size);
+    void *SUPER_REALLOC(void *ptr, size_t size);
+    void *SUPER_CALLOC(size_t nmemb, size_t size);
+    void SUPER_FREE(void *ptr);
 }
 
-extern "C" void* $Sub$$malloc(size_t size) {
+extern "C" void* SUB_MALLOC(size_t size) {
     void *ptr = NULL;
 #ifdef MBED_HEAP_STATS_ENABLED
     malloc_stats_mutex->lock();
-    alloc_info_t *alloc_info = (alloc_info_t*)$Super$$malloc(size + sizeof(alloc_info_t));
+    alloc_info_t *alloc_info = (alloc_info_t*)SUPER_MALLOC(size + sizeof(alloc_info_t));
     if (alloc_info != NULL) {
         alloc_info->size = size;
         ptr = (void*)(alloc_info + 1);
@@ -241,7 +261,7 @@ extern "C" void* $Sub$$malloc(size_t size) {
     }
     malloc_stats_mutex->unlock();
 #else // #ifdef MBED_HEAP_STATS_ENABLED
-    ptr = $Super$$malloc(size);
+    ptr = SUPER_MALLOC(size);
 #endif // #ifdef MBED_HEAP_STATS_ENABLED
 #ifdef MBED_MEM_TRACING_ENABLED
     mem_trace_mutex->lock();
@@ -251,7 +271,7 @@ extern "C" void* $Sub$$malloc(size_t size) {
     return ptr;
 }
 
-extern "C" void* $Sub$$realloc(void *ptr, size_t size) {
+extern "C" void* SUB_REALLOC(void *ptr, size_t size) {
     void *new_ptr = NULL;
 #ifdef MBED_HEAP_STATS_ENABLED
     // Note - no lock needed since malloc and free are thread safe
@@ -276,7 +296,7 @@ extern "C" void* $Sub$$realloc(void *ptr, size_t size) {
         free(ptr);
     }
 #else // #ifdef MBED_HEAP_STATS_ENABLED
-    new_ptr = $Super$$realloc(ptr, size);
+    new_ptr = SUPER_REALLOC(ptr, size);
 #endif // #ifdef MBED_HEAP_STATS_ENABLED
 #ifdef MBED_MEM_TRACING_ENABLED
     mem_trace_mutex->lock();
@@ -286,7 +306,7 @@ extern "C" void* $Sub$$realloc(void *ptr, size_t size) {
     return new_ptr;
 }
 
-extern "C" void *$Sub$$calloc(size_t nmemb, size_t size) {
+extern "C" void *SUB_CALLOC(size_t nmemb, size_t size) {
     void *ptr = NULL;
 #ifdef MBED_HEAP_STATS_ENABLED
     // Note - no lock needed since malloc is thread safe
@@ -295,7 +315,7 @@ extern "C" void *$Sub$$calloc(size_t nmemb, size_t size) {
         memset(ptr, 0, nmemb * size);
     }
 #else // #ifdef MBED_HEAP_STATS_ENABLED
-    ptr = $Super$$calloc(nmemb, size);
+    ptr = SUPER_CALLOC(nmemb, size);
 #endif // #ifdef MBED_HEAP_STATS_ENABLED
 #ifdef MBED_MEM_TRACING_ENABLED
     mem_trace_mutex->lock();
@@ -305,7 +325,7 @@ extern "C" void *$Sub$$calloc(size_t nmemb, size_t size) {
     return ptr;
 }
 
-extern "C" void $Sub$$free(void *ptr) {
+extern "C" void SUB_FREE(void *ptr) {
 #ifdef MBED_HEAP_STATS_ENABLED
     malloc_stats_mutex->lock();
     alloc_info_t *alloc_info = NULL;
@@ -314,10 +334,10 @@ extern "C" void $Sub$$free(void *ptr) {
         heap_stats.current_size -= alloc_info->size;
         heap_stats.alloc_cnt -= 1;
     }
-    $Super$$free((void*)alloc_info);
+    SUPER_FREE((void*)alloc_info);
     malloc_stats_mutex->unlock();
 #else // #ifdef MBED_HEAP_STATS_ENABLED
-    $Super$$free(ptr);
+    SUPER_FREE(ptr);
 #endif // #ifdef MBED_HEAP_STATS_ENABLED
 #ifdef MBED_MEM_TRACING_ENABLED
     mem_trace_mutex->lock();
@@ -332,15 +352,14 @@ extern "C" void $Sub$$free(void *ptr) {
 /* Allocation wrappers for other toolchains are not supported yet             */
 /******************************************************************************/
 
-#else // #if defined(TOOLCHAIN_GCC)
+#else
 
 #ifdef MBED_MEM_TRACING_ENABLED
-#warning Memory tracing is not supported with the current toolchain.
+#error Memory tracing is not supported with the current toolchain.
 #endif
 
 #ifdef MBED_HEAP_STATS_ENABLED
-#warning Heap statistics are not supported with the current toolchain.
+#error Heap statistics are not supported with the current toolchain.
 #endif
 
 #endif // #if defined(TOOLCHAIN_GCC)
-
diff --git a/platform/mbed_application.h b/platform/mbed_application.h
index 633b6a8572e..43b4813f755 100644
--- a/platform/mbed_application.h
+++ b/platform/mbed_application.h
@@ -1,6 +1,3 @@
-
-/** \addtogroup platform */
-/** @{*/
 /* mbed Microcontroller Library
  * Copyright (c) 2017-2017 ARM Limited
  *
@@ -16,6 +13,7 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
+
 #ifndef MBED_APPLICATION_H
 #define MBED_APPLICATION_H
 
@@ -52,4 +50,3 @@ void mbed_start_application(uintptr_t address);
 
 #endif
 
-/** @}*/
diff --git a/platform/mbed_assert.h b/platform/mbed_assert.h
index bd86983fc8b..8aecdcc3fa8 100644
--- a/platform/mbed_assert.h
+++ b/platform/mbed_assert.h
@@ -1,6 +1,10 @@
 
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_Assert Assert macros
+ * @{
+ */
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
  *
@@ -39,6 +43,19 @@ void mbed_assert_internal(const char *expr, const char *file, int line);
 }
 #endif
 
+/** MBED_ASSERT
+ *  Declare runtime assertions: results in runtime error if condition is false
+ *
+ *  @note
+ *  Use of MBED_ASSERT is limited to Debug and Develop builds.
+ *
+ *  @code
+ *
+ *  int Configure(serial_t *obj) {
+ *      MBED_ASSERT(obj);
+ *  }
+ *  @endcode
+ */
 #ifdef NDEBUG
 #define MBED_ASSERT(expr) ((void)0)
 
@@ -110,4 +127,7 @@ do {                                                     \
 
 #endif
 
-/** @}*/
+/**@}*/
+
+/**@}*/
+
diff --git a/platform/mbed_critical.h b/platform/mbed_critical.h
index 8aa314a8e99..0b7cb2a8b1a 100644
--- a/platform/mbed_critical.h
+++ b/platform/mbed_critical.h
@@ -1,6 +1,4 @@
 
-/** \addtogroup platform */
-/** @{*/
 /*
  * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
  * SPDX-License-Identifier: Apache-2.0
@@ -29,6 +27,12 @@
 extern "C" {
 #endif
 
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_critical critical section function
+ * @{
+ */
 
 /** Determine the current interrupts enabled state
   *
@@ -363,8 +367,11 @@ void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta);
 #ifdef __cplusplus
 } // extern "C"
 #endif
+/**@}*/
 
+/**@}*/
 
 #endif // __MBED_UTIL_CRITICAL_H__
 
-/** @}*/
+
+
diff --git a/platform/mbed_debug.h b/platform/mbed_debug.h
index 761c1eb99f6..5f9a19805d6 100644
--- a/platform/mbed_debug.h
+++ b/platform/mbed_debug.h
@@ -1,6 +1,11 @@
 
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_debug Debug functions
+ * @{
+ */
+ 
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
  *
@@ -68,4 +73,7 @@ static inline void debug_if(int condition, const char *format, ...) {
 
 #endif
 
-/** @}*/
+/**@}*/
+
+/**@}*/
+
diff --git a/platform/mbed_error.h b/platform/mbed_error.h
index 1da55135b9e..8f5cd9baff1 100644
--- a/platform/mbed_error.h
+++ b/platform/mbed_error.h
@@ -1,6 +1,10 @@
 
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_error Error functions
+ * @{
+ */
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
  *
@@ -75,3 +79,4 @@ void error(const char* format, ...);
 #endif
 
 /** @}*/
+/** @}*/
diff --git a/platform/mbed_interface.h b/platform/mbed_interface.h
index 538a6a7cbfd..94baa34f775 100644
--- a/platform/mbed_interface.h
+++ b/platform/mbed_interface.h
@@ -1,6 +1,11 @@
 
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_interface Network interface and other utility functions
+ * @{
+ */
+
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
  *
@@ -42,6 +47,11 @@ extern "C" {
 
 #if DEVICE_SEMIHOST
 
+/**
+ * \defgroup platform_interface interface functions
+ * @{
+ */
+
 /** Functions to control the mbed interface
  *
  * mbed Microcontrollers have a built-in interface to provide functionality such as
@@ -137,6 +147,7 @@ void mbed_error_printf(const char* format, ...);
  *
  */
 void mbed_error_vfprintf(const char * format, va_list arg);
+/** @}*/
 
 #ifdef __cplusplus
 }
diff --git a/platform/mbed_mem_trace.h b/platform/mbed_mem_trace.h
index 0267255ba78..59da721e2fe 100644
--- a/platform/mbed_mem_trace.h
+++ b/platform/mbed_mem_trace.h
@@ -1,6 +1,7 @@
 
 /** \addtogroup platform */
 /** @{*/
+
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2016 ARM Limited
  *
@@ -35,6 +36,11 @@ enum {
     MBED_MEM_TRACE_FREE
 };
 
+/**
+ * \defgroup platform_mem_trace mem_trace functions
+ * @{
+ */
+
 /* Prefix for the output of the default tracer */
 #define MBED_MEM_DEFAULT_TRACER_PREFIX  "#"
 
@@ -133,6 +139,8 @@ void mbed_mem_trace_free(void *ptr, void *caller);
  */
 void mbed_mem_trace_default_callback(uint8_t op, void *res, void *caller, ...);
 
+/** @}*/
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/platform/mbed_mktime.h b/platform/mbed_mktime.h
index b28525224c4..dd302702e40 100644
--- a/platform/mbed_mktime.h
+++ b/platform/mbed_mktime.h
@@ -28,6 +28,11 @@
 extern "C" {
 #endif
 
+/**
+ * \defgroup platform_mktime mktime functions
+ * @{
+ */
+
 /** Compute if a year is a leap year or not.
  *
  * @param year The year to test it shall be in the range [70:138]. Year 0 is
@@ -89,6 +94,8 @@ time_t _rtc_mktime(const struct tm* calendar_time);
  */
 bool _rtc_localtime(time_t timestamp, struct tm* calendar_time);
 
+/** @}*/
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/platform/mbed_poll.cpp b/platform/mbed_poll.cpp
index 28492010d42..c2a08fa3ddb 100644
--- a/platform/mbed_poll.cpp
+++ b/platform/mbed_poll.cpp
@@ -66,7 +66,7 @@ int poll(pollfh fhs[], unsigned nfhs, int timeout)
 #ifdef MBED_CONF_RTOS_PRESENT
         // TODO - proper blocking
         // wait for condition variable, wait queue whatever here
-        rtos::Thread::yield();
+        rtos::Thread::wait(1);
 #endif
     }
     return count;
diff --git a/platform/mbed_poll.h b/platform/mbed_poll.h
index 635733bb98f..f9c894c21f6 100644
--- a/platform/mbed_poll.h
+++ b/platform/mbed_poll.h
@@ -27,7 +27,11 @@ namespace mbed {
 class FileHandle;
 
 /** \addtogroup platform */
-
+/** @{*/
+/**
+ * \defgroup platform_poll poll functions
+ * @{
+ */
 
 struct pollfh {
     FileHandle *fh;
@@ -47,6 +51,10 @@ struct pollfh {
  */
 int poll(pollfh fhs[], unsigned nfhs, int timeout);
 
+/**@}*/
+
+/**@}*/
+
 } // namespace mbed
 
 #endif //MBED_POLL_H
diff --git a/platform/mbed_preprocessor.h b/platform/mbed_preprocessor.h
index 5e72d99f873..63312e8b13b 100644
--- a/platform/mbed_preprocessor.h
+++ b/platform/mbed_preprocessor.h
@@ -1,5 +1,10 @@
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_preprocessor preprocessor macros
+ * @{
+ */
+
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
  *
@@ -51,3 +56,4 @@
 #endif
 
 /** @}*/
+/** @}*/
diff --git a/platform/mbed_retarget.cpp b/platform/mbed_retarget.cpp
index e9f6d3c67c4..04660eda1e0 100644
--- a/platform/mbed_retarget.cpp
+++ b/platform/mbed_retarget.cpp
@@ -13,9 +13,11 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
+#include <time.h>
 #include "platform/platform.h"
 #include "platform/FilePath.h"
 #include "hal/serial_api.h"
+#include "hal/us_ticker_api.h"
 #include "platform/mbed_toolchain.h"
 #include "platform/mbed_semihost_api.h"
 #include "platform/mbed_interface.h"
@@ -24,6 +26,7 @@
 #include "platform/mbed_error.h"
 #include "platform/mbed_stats.h"
 #include "platform/mbed_critical.h"
+#include "platform/PlatformMutex.h"
 #include <stdlib.h>
 #include <string.h>
 #include <limits.h>
@@ -33,6 +36,8 @@
 #include <errno.h>
 #include "platform/mbed_retarget.h"
 
+static SingletonPtr<PlatformMutex> _mutex;
+
 #if defined(__ARMCC_VERSION)
 #   if __ARMCC_VERSION >= 6010050
 #      include <arm_compat.h>
@@ -247,7 +252,7 @@ extern "C" FILEHANDLE PREFIX(_open)(const char* name, int openmode) {
             /* The first part of the filename (between first 2 '/') is not a
              * registered mount point in the namespace.
              */
-            return handle_open_errors(-ENOENT, fh_i);
+            return handle_open_errors(-ENODEV, fh_i);
         }
 
         if (path.isFile()) {
@@ -255,7 +260,7 @@ extern "C" FILEHANDLE PREFIX(_open)(const char* name, int openmode) {
         } else {
             FileSystemHandle *fs = path.fileSystem();
             if (fs == NULL) {
-                return handle_open_errors(-ENOENT, fh_i);
+                return handle_open_errors(-ENODEV, fh_i);
             }
             int posix_mode = openmode_to_posix(openmode);
             int err = fs->open(&res, path.fileName(), posix_mode);
@@ -446,6 +451,7 @@ int _lseek(FILEHANDLE fh, int offset, int whence)
 #if defined(__ARMCC_VERSION)
     int whence = SEEK_SET;
 #endif
+
     if (fh < 3) {
         errno = ESPIPE;
         return -1;
@@ -536,13 +542,21 @@ extern "C" __value_in_regs struct __initial_stackheap __user_setup_stackheap(uin
 
 
 #if !defined(__ARMCC_VERSION) && !defined(__ICCARM__)
-extern "C" int _fstat(int fd, struct stat *st) {
-    if (fd < 3) {
+extern "C" int _fstat(int fh, struct stat *st) {
+    if (fh < 3) {
         st->st_mode = S_IFCHR;
         return  0;
     }
-    errno = EBADF;
-    return -1;
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) {
+        errno = EBADF;
+        return -1;
+    }
+
+    st->st_mode = fhc->isatty() ? S_IFCHR : S_IFREG;
+    st->st_size = fhc->size();
+    return 0;
 }
 #endif
 
@@ -551,7 +565,7 @@ extern "C" int remove(const char *path) {
     FilePath fp(path);
     FileSystemHandle *fs = fp.fileSystem();
     if (fs == NULL) {
-        errno = ENOENT;
+        errno = ENODEV;
         return -1;
     }
 
@@ -571,7 +585,7 @@ extern "C" int rename(const char *oldname, const char *newname) {
     FileSystemHandle *fsNew = fpNew.fileSystem();
 
     if (fsOld == NULL) {
-        errno = ENOENT;
+        errno = ENODEV;
         return -1;
     }
 
@@ -611,7 +625,7 @@ extern "C" DIR *opendir(const char *path) {
     FilePath fp(path);
     FileSystemHandle* fs = fp.fileSystem();
     if (fs == NULL) {
-        errno = ENOENT;
+        errno = ENODEV;
         return NULL;
     }
 
@@ -663,7 +677,10 @@ extern "C" void seekdir(DIR *dir, off_t off) {
 extern "C" int mkdir(const char *path, mode_t mode) {
     FilePath fp(path);
     FileSystemHandle *fs = fp.fileSystem();
-    if (fs == NULL) return -1;
+    if (fs == NULL) {
+        errno = ENODEV;
+        return -1;
+    }
 
     int err = fs->mkdir(fp.fileName(), mode);
     if (err < 0) {
@@ -677,7 +694,10 @@ extern "C" int mkdir(const char *path, mode_t mode) {
 extern "C" int stat(const char *path, struct stat *st) {
     FilePath fp(path);
     FileSystemHandle *fs = fp.fileSystem();
-    if (fs == NULL) return -1;
+    if (fs == NULL) {
+        errno = ENODEV;
+        return -1;
+    }
 
     int err = fs->stat(fp.fileName(), st);
     if (err < 0) {
@@ -1008,6 +1028,16 @@ void *operator new[](std::size_t count)
     return buffer;
 }
 
+void *operator new(std::size_t count, const std::nothrow_t& tag)
+{
+    return malloc(count);
+}
+
+void *operator new[](std::size_t count, const std::nothrow_t& tag)
+{
+    return malloc(count);
+}
+
 void operator delete(void *ptr)
 {
     if (ptr != NULL) {
@@ -1020,3 +1050,22 @@ void operator delete[](void *ptr)
         free(ptr);
     }
 }
+
+/* @brief   standard c library clock() function.
+ *
+ * This function returns the number of clock ticks elapsed since the start of the program.
+ *
+ * @note Synchronization level: Thread safe
+ *
+ * @return
+ *  the number of clock ticks elapsed since the start of the program.
+ *
+ * */
+extern "C" clock_t clock()
+{
+    _mutex->lock();
+    clock_t t = ticker_read(get_us_ticker_data());
+    t /= 1000000 / CLOCKS_PER_SEC; // convert to processor time
+    _mutex->unlock();
+    return t;
+}
diff --git a/platform/mbed_retarget.h b/platform/mbed_retarget.h
index 90d19fb0943..0f3e30b5e5c 100644
--- a/platform/mbed_retarget.h
+++ b/platform/mbed_retarget.h
@@ -29,32 +29,50 @@
  * need to define the types ourselves for the other compilers that normally
  * target embedded systems */
 #if defined(__ARMCC_VERSION) || defined(__ICCARM__)
-typedef int ssize_t;    ///< Signed size type, usually encodes negative errors
-typedef long off_t;     ///< Offset in a data stream
-typedef int mode_t;     ///< Mode for opening files
-
-#define O_RDONLY 0
-#define O_WRONLY 1
-#define O_RDWR   2
-#define O_CREAT  0x0200
-#define O_TRUNC  0x0400
-#define O_APPEND 0x0008
+typedef signed   int  ssize_t;  ///< Signed size type, usually encodes negative errors
+typedef signed   long off_t;    ///< Offset in a data stream
+typedef unsigned int  mode_t;   ///< Mode for opening files
+typedef unsigned int  dev_t;    ///< Device ID type
+typedef unsigned long ino_t;    ///< File serial number
+typedef unsigned int  nlink_t;  ///< Number of links to a file
+typedef unsigned int  uid_t;    ///< User ID
+typedef unsigned int  gid_t;    ///< Group ID
+
+#define O_RDONLY 0      ///< Open for reading
+#define O_WRONLY 1      ///< Open for writing
+#define O_RDWR   2      ///< Open for reading and writing
+#define O_CREAT  0x0200 ///< Create file if it does not exist
+#define O_TRUNC  0x0400 ///< Truncate file to zero length
+#define O_EXCL   0x0800 ///< Fail if file exists
+#define O_APPEND 0x0008 ///< Set file offset to end of file prior to each write
 
 #define NAME_MAX 255    ///< Maximum size of a name in a file path
 
+#include <time.h>
+
 #else
+
 #include <sys/fcntl.h>
 #include <sys/types.h>
 #include <sys/syslimits.h>
+
 #endif
 
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_retarget Retarget functions
+ * @{
+ */
 
 /* DIR declarations must also be here */
 #if __cplusplus
 namespace mbed {
+    
 class FileHandle;
 class DirHandle;
 std::FILE *mbed_fdopen(FileHandle *fh, const char *mode);
+
 }
 typedef mbed::DirHandle DIR;
 #else
@@ -83,107 +101,353 @@ extern "C" {
  * symbol definitions used by the POSIX filesystem API to return errno codes.
  * Note also that ARMCC errno.h defines some symbol values differently from
  * the GCC_ARM/IAR/standard POSIX definitions. The definitions guard against
- * this and future changes by changing the symbol definition as shown below. */
-#undef ENOENT
-#define ENOENT      2       /* No such file or directory. */
-
-#undef EIO
-#define EIO         5       /* I/O error */
-
-#undef ENXIO
-#define ENXIO       6       /* No such device or address */
-
-#undef ENOEXEC
-#define ENOEXEC     8       /* Exec format error */
-
-#undef EBADF
-#define EBADF       9       /* Bad file number */
-
-#undef EAGAIN
-#define EAGAIN      11      /* Resource unavailable, try again */
-
-#undef EWOULDBLOCK
-#define EWOULDBLOCK EAGAIN  /* Operation would block */
-
-#undef ENOMEM
-#define ENOMEM      12      /* Not enough space */
-
-#undef EACCES
-#define EACCES      13      /* Permission denied */
-
-#undef EFAULT
-#define EFAULT      14      /* Bad address */
-
-#undef EEXIST
-#define EEXIST      17      /* File exists */
-
-#undef EXDEV
-#define EXDEV       18      /* Cross-device link */
-
-#undef ENODEV
-#define ENODEV      19
-
-#undef EINVAL
-#define EINVAL      22      /* Invalid argument */
-
-#undef ENFILE
-#define ENFILE      23      /* Too many open files in system */
-
-#undef EMFILE
-#define EMFILE      24      /* File descriptor value too large */
-
-#undef ESPIPE
-#define ESPIPE      29      /* Invalid seek */
-
-#undef ENOSYS
-#define ENOSYS      38      /* Function not implemented */
-
-#undef EOVERFLOW
-#define EOVERFLOW   75      /* Value too large to be stored in data type */
+ * this and future changes by changing the symbol definition as shown below.
+ */
+#undef  EPERM
+#define EPERM           1       /* Operation not permitted */
+#undef  ENOENT
+#define ENOENT          2       /* No such file or directory */
+#undef  ESRCH
+#define ESRCH           3       /* No such process */
+#undef  EINTR
+#define EINTR           4       /* Interrupted system call */
+#undef  EIO
+#define EIO             5       /* I/O error */
+#undef  ENXIO
+#define ENXIO           6       /* No such device or address */
+#undef  E2BIG
+#define E2BIG           7       /* Argument list too long */
+#undef  ENOEXEC
+#define ENOEXEC         8       /* Exec format error */
+#undef  EBADF
+#define EBADF           9       /* Bad file number */
+#undef  ECHILD
+#define ECHILD          10      /* No child processes */
+#undef  EAGAIN
+#define EAGAIN          11      /* Try again */
+#undef  ENOMEM
+#define ENOMEM          12      /* Out of memory */
+#undef  EACCES
+#define EACCES          13      /* Permission denied */
+#undef  EFAULT
+#define EFAULT          14      /* Bad address */
+#undef  ENOTBLK
+#define ENOTBLK         15      /* Block device required */
+#undef  EBUSY
+#define EBUSY           16      /* Device or resource busy */
+#undef  EEXIST
+#define EEXIST          17      /* File exists */
+#undef  EXDEV
+#define EXDEV           18      /* Cross-device link */
+#undef  ENODEV
+#define ENODEV          19      /* No such device */
+#undef  ENOTDIR
+#define ENOTDIR         20      /* Not a directory */
+#undef  EISDIR
+#define EISDIR          21      /* Is a directory */
+#undef  EINVAL
+#define EINVAL          22      /* Invalid argument */
+#undef  ENFILE
+#define ENFILE          23      /* File table overflow */
+#undef  EMFILE
+#define EMFILE          24      /* Too many open files */
+#undef  ENOTTY
+#define ENOTTY          25      /* Not a typewriter */
+#undef  ETXTBSY
+#define ETXTBSY         26      /* Text file busy */
+#undef  EFBIG
+#define EFBIG           27      /* File too large */
+#undef  ENOSPC
+#define ENOSPC          28      /* No space left on device */
+#undef  ESPIPE
+#define ESPIPE          29      /* Illegal seek */
+#undef  EROFS
+#define EROFS           30      /* Read-only file system */
+#undef  EMLINK
+#define EMLINK          31      /* Too many links */
+#undef  EPIPE
+#define EPIPE           32      /* Broken pipe */
+#undef  EDOM
+#define EDOM            33      /* Math argument out of domain of func */
+#undef  ERANGE
+#define ERANGE          34      /* Math result not representable */
+#undef  EDEADLK
+#define EDEADLK         35      /* Resource deadlock would occur */
+#undef  ENAMETOOLONG
+#define ENAMETOOLONG    36      /* File name too long */
+#undef  ENOLCK
+#define ENOLCK          37      /* No record locks available */
+#undef  ENOSYS
+#define ENOSYS          38      /* Function not implemented */
+#undef  ENOTEMPTY
+#define ENOTEMPTY       39      /* Directory not empty */
+#undef  ELOOP
+#define ELOOP           40      /* Too many symbolic links encountered */
+#undef  EWOULDBLOCK
+#define EWOULDBLOCK     EAGAIN  /* Operation would block */
+#undef  ENOMSG
+#define ENOMSG          42      /* No message of desired type */
+#undef  EIDRM
+#define EIDRM           43      /* Identifier removed */
+#undef  ECHRNG
+#define ECHRNG          44      /* Channel number out of range */
+#undef  EL2NSYNC
+#define EL2NSYNC        45      /* Level 2 not synchronized */
+#undef  EL3HLT
+#define EL3HLT          46      /* Level 3 halted */
+#undef  EL3RST
+#define EL3RST          47      /* Level 3 reset */
+#undef  ELNRNG
+#define ELNRNG          48      /* Link number out of range */
+#undef  EUNATCH
+#define EUNATCH         49      /* Protocol driver not attached */
+#undef  ENOCSI
+#define ENOCSI          50      /* No CSI structure available */
+#undef  EL2HLT
+#define EL2HLT          51      /* Level 2 halted */
+#undef  EBADE
+#define EBADE           52      /* Invalid exchange */
+#undef  EBADR
+#define EBADR           53      /* Invalid request descriptor */
+#undef  EXFULL
+#define EXFULL          54      /* Exchange full */
+#undef  ENOANO
+#define ENOANO          55      /* No anode */
+#undef  EBADRQC
+#define EBADRQC         56      /* Invalid request code */
+#undef  EBADSLT
+#define EBADSLT         57      /* Invalid slot */
+#undef  EDEADLOCK
+#define EDEADLOCK       EDEADLK /* Resource deadlock would occur */
+#undef  EBFONT
+#define EBFONT          59      /* Bad font file format */
+#undef  ENOSTR
+#define ENOSTR          60      /* Device not a stream */
+#undef  ENODATA
+#define ENODATA         61      /* No data available */
+#undef  ETIME
+#define ETIME           62      /* Timer expired */
+#undef  ENOSR
+#define ENOSR           63      /* Out of streams resources */
+#undef  ENONET
+#define ENONET          64      /* Machine is not on the network */
+#undef  ENOPKG
+#define ENOPKG          65      /* Package not installed */
+#undef  EREMOTE
+#define EREMOTE         66      /* Object is remote */
+#undef  ENOLINK
+#define ENOLINK         67      /* Link has been severed */
+#undef  EADV
+#define EADV            68      /* Advertise error */
+#undef  ESRMNT
+#define ESRMNT          69      /* Srmount error */
+#undef  ECOMM
+#define ECOMM           70      /* Communication error on send */
+#undef  EPROTO
+#define EPROTO          71      /* Protocol error */
+#undef  EMULTIHOP
+#define EMULTIHOP       72      /* Multihop attempted */
+#undef  EDOTDOT
+#define EDOTDOT         73      /* RFS specific error */
+#undef  EBADMSG
+#define EBADMSG         74      /* Not a data message */
+#undef  EOVERFLOW
+#define EOVERFLOW       75      /* Value too large for defined data type */
+#undef  ENOTUNIQ
+#define ENOTUNIQ        76      /* Name not unique on network */
+#undef  EBADFD
+#define EBADFD          77      /* File descriptor in bad state */
+#undef  EREMCHG
+#define EREMCHG         78      /* Remote address changed */
+#undef  ELIBACC
+#define ELIBACC         79      /* Can not access a needed shared library */
+#undef  ELIBBAD
+#define ELIBBAD         80      /* Accessing a corrupted shared library */
+#undef  ELIBSCN
+#define ELIBSCN         81      /* .lib section in a.out corrupted */
+#undef  ELIBMAX
+#define ELIBMAX         82      /* Attempting to link in too many shared libraries */
+#undef  ELIBEXEC
+#define ELIBEXEC        83      /* Cannot exec a shared library directly */
+#undef  EILSEQ
+#define EILSEQ          84      /* Illegal byte sequence */
+#undef  ERESTART
+#define ERESTART        85      /* Interrupted system call should be restarted */
+#undef  ESTRPIPE
+#define ESTRPIPE        86      /* Streams pipe error */
+#undef  EUSERS
+#define EUSERS          87      /* Too many users */
+#undef  ENOTSOCK
+#define ENOTSOCK        88      /* Socket operation on non-socket */
+#undef  EDESTADDRREQ
+#define EDESTADDRREQ    89      /* Destination address required */
+#undef  EMSGSIZE
+#define EMSGSIZE        90      /* Message too long */
+#undef  EPROTOTYPE
+#define EPROTOTYPE      91      /* Protocol wrong type for socket */
+#undef  ENOPROTOOPT
+#define ENOPROTOOPT     92      /* Protocol not available */
+#undef  EPROTONOSUPPORT
+#define EPROTONOSUPPORT 93      /* Protocol not supported */
+#undef  ESOCKTNOSUPPORT
+#define ESOCKTNOSUPPORT 94      /* Socket type not supported */
+#undef  EOPNOTSUPP
+#define EOPNOTSUPP      95      /* Operation not supported on transport endpoint */
+#undef  EPFNOSUPPORT
+#define EPFNOSUPPORT    96      /* Protocol family not supported */
+#undef  EAFNOSUPPORT
+#define EAFNOSUPPORT    97      /* Address family not supported by protocol */
+#undef  EADDRINUSE
+#define EADDRINUSE      98      /* Address already in use */
+#undef  EADDRNOTAVAIL
+#define EADDRNOTAVAIL   99      /* Cannot assign requested address */
+#undef  ENETDOWN
+#define ENETDOWN        100     /* Network is down */
+#undef  ENETUNREACH
+#define ENETUNREACH     101     /* Network is unreachable */
+#undef  ENETRESET
+#define ENETRESET       102     /* Network dropped connection because of reset */
+#undef  ECONNABORTED
+#define ECONNABORTED    103     /* Software caused connection abort */
+#undef  ECONNRESET
+#define ECONNRESET      104     /* Connection reset by peer */
+#undef  ENOBUFS
+#define ENOBUFS         105     /* No buffer space available */
+#undef  EISCONN
+#define EISCONN         106     /* Transport endpoint is already connected */
+#undef  ENOTCONN
+#define ENOTCONN        107     /* Transport endpoint is not connected */
+#undef  ESHUTDOWN
+#define ESHUTDOWN       108     /* Cannot send after transport endpoint shutdown */
+#undef  ETOOMANYREFS
+#define ETOOMANYREFS    109     /* Too many references: cannot splice */
+#undef  ETIMEDOUT
+#define ETIMEDOUT       110     /* Connection timed out */
+#undef  ECONNREFUSED
+#define ECONNREFUSED    111     /* Connection refused */
+#undef  EHOSTDOWN
+#define EHOSTDOWN       112     /* Host is down */
+#undef  EHOSTUNREACH
+#define EHOSTUNREACH    113     /* No route to host */
+#undef  EALREADY
+#define EALREADY        114     /* Operation already in progress */
+#undef  EINPROGRESS
+#define EINPROGRESS     115     /* Operation now in progress */
+#undef  ESTALE
+#define ESTALE          116     /* Stale NFS file handle */
+#undef  EUCLEAN
+#define EUCLEAN         117     /* Structure needs cleaning */
+#undef  ENOTNAM
+#define ENOTNAM         118     /* Not a XENIX named type file */
+#undef  ENAVAIL
+#define ENAVAIL         119     /* No XENIX semaphores available */
+#undef  EISNAM
+#define EISNAM          120     /* Is a named type file */
+#undef  EREMOTEIO
+#define EREMOTEIO       121     /* Remote I/O error */
+#undef  EDQUOT
+#define EDQUOT          122     /* Quota exceeded */
+#undef  ENOMEDIUM
+#define ENOMEDIUM       123     /* No medium found */
+#undef  EMEDIUMTYPE
+#define EMEDIUMTYPE     124     /* Wrong medium type */
+#undef  ECANCELED
+#define ECANCELED       125     /* Operation Canceled */
+#undef  ENOKEY
+#define ENOKEY          126     /* Required key not available */
+#undef  EKEYEXPIRED
+#define EKEYEXPIRED     127     /* Key has expired */
+#undef  EKEYREVOKED
+#define EKEYREVOKED     128     /* Key has been revoked */
+#undef  EKEYREJECTED
+#define EKEYREJECTED    129     /* Key was rejected by service */
+#undef  EOWNERDEAD
+#define EOWNERDEAD      130     /* Owner died */
+#undef  ENOTRECOVERABLE
+#define ENOTRECOVERABLE 131     /* State not recoverable */
+#endif
 
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
 /* Missing stat.h defines.
  * The following are sys/stat.h definitions not currently present in the ARMCC
  * errno.h. Note, ARMCC errno.h defines some symbol values differing from
  * GCC_ARM/IAR/standard POSIX definitions. Guard against this and future
- * changes by changing the symbol definition for filesystem use. */
-#define     _IFDIR  0040000 /* directory */
-#define     _IFREG  0100000 /* regular */
-
-#define S_IFDIR     _IFDIR
-#define S_IFREG     _IFREG
+ * changes by changing the symbol definition for filesystem use.
+ */
+#define     _IFMT   0170000 //< type of file
+#define     _IFSOCK 0140000 //< socket
+#define     _IFLNK  0120000 //< symbolic link
+#define     _IFREG  0100000 //< regular
+#define     _IFBLK  0060000 //< block special
+#define     _IFDIR  0040000 //< directory
+#define     _IFCHR  0020000 //< character special
+#define     _IFIFO  0010000 //< fifo special
+
+#define S_IFMT      _IFMT   //< type of file
+#define S_IFSOCK    _IFSOCK //< socket
+#define S_IFLNK     _IFLNK  //< symbolic link
+#define S_IFREG     _IFREG  //< regular
+#define S_IFBLK     _IFBLK  //< block special
+#define S_IFDIR     _IFDIR  //< directory
+#define S_IFCHR     _IFCHR  //< character special
+#define S_IFIFO     _IFIFO  //< fifo special
 
 #define S_IRWXU     (S_IRUSR | S_IWUSR | S_IXUSR)
-#define     S_IRUSR 0000400 /* read permission, owner */
-#define     S_IWUSR 0000200 /* write permission, owner */
-#define     S_IXUSR 0000100/* execute/search permission, owner */
+#define     S_IRUSR 0000400 ///< read permission, owner
+#define     S_IWUSR 0000200 ///< write permission, owner
+#define     S_IXUSR 0000100 ///< execute/search permission, owner
 #define S_IRWXG     (S_IRGRP | S_IWGRP | S_IXGRP)
-#define     S_IRGRP 0000040 /* read permission, group */
-#define     S_IWGRP 0000020 /* write permission, grougroup */
-#define     S_IXGRP 0000010/* execute/search permission, group */
+#define     S_IRGRP 0000040 ///< read permission, group
+#define     S_IWGRP 0000020 ///< write permission, grougroup
+#define     S_IXGRP 0000010 ///< execute/search permission, group
 #define S_IRWXO     (S_IROTH | S_IWOTH | S_IXOTH)
-#define     S_IROTH 0000004 /* read permission, other */
-#define     S_IWOTH 0000002 /* write permission, other */
-#define     S_IXOTH 0000001/* execute/search permission, other */
+#define     S_IROTH 0000004 ///< read permission, other
+#define     S_IWOTH 0000002 ///< write permission, other
+#define     S_IXOTH 0000001 ///< execute/search permission, other
+
+/* Refer to sys/stat standard
+ * Note: Not all fields may be supported by the underlying filesystem
+ */
+struct stat {
+    dev_t     st_dev;     ///< Device ID containing file
+    ino_t     st_ino;     ///< File serial number
+    mode_t    st_mode;    ///< Mode of file
+    nlink_t   st_nlink;   ///< Number of links to file
+
+    uid_t     st_uid;     ///< User ID
+    gid_t     st_gid;     ///< Group ID
+
+    off_t     st_size;    ///< Size of file in bytes
+
+    time_t    st_atime;   ///< Time of last access
+    time_t    st_mtime;   ///< Time of last data modification
+    time_t    st_ctime;   ///< Time of last status change
+};
 
 #endif /* defined(__ARMCC_VERSION) || defined(__ICCARM__) */
 
 
 /* The following are dirent.h definitions are declared here to garuntee
- * consistency where structure may be different with different toolchains */
+ * consistency where structure may be different with different toolchains
+ */
 struct dirent {
-    char d_name[NAME_MAX+1];
-    uint8_t d_type;
+    char d_name[NAME_MAX+1]; ///< Name of file
+    uint8_t d_type;          ///< Type of file
 };
 
 enum {
-    DT_UNKNOWN, // The file type could not be determined.
-    DT_FIFO,    // This is a named pipe (FIFO).
-    DT_CHR,     // This is a character device.
-    DT_DIR,     // This is a directory.
-    DT_BLK,     // This is a block device.
-    DT_REG,     // This is a regular file.
-    DT_LNK,     // This is a symbolic link.
-    DT_SOCK,    // This is a UNIX domain socket.
+    DT_UNKNOWN, ///< The file type could not be determined.
+    DT_FIFO,    ///< This is a named pipe (FIFO).
+    DT_CHR,     ///< This is a character device.
+    DT_DIR,     ///< This is a directory.
+    DT_BLK,     ///< This is a block device.
+    DT_REG,     ///< This is a regular file.
+    DT_LNK,     ///< This is a symbolic link.
+    DT_SOCK,    ///< This is a UNIX domain socket.
 };
 
+/**@}*/
+
+/**@}*/
+
 #endif /* RETARGET_H */
diff --git a/platform/mbed_rtc_time.cpp b/platform/mbed_rtc_time.cpp
index 7a0ef488343..b77e2efa54b 100644
--- a/platform/mbed_rtc_time.cpp
+++ b/platform/mbed_rtc_time.cpp
@@ -15,10 +15,8 @@
  */
 #include "hal/rtc_api.h"
 
-#include <time.h>
 #include "platform/mbed_critical.h"
 #include "platform/mbed_rtc_time.h"
-#include "hal/us_ticker_api.h"
 #include "platform/SingletonPtr.h"
 #include "platform/PlatformMutex.h"
 
@@ -76,14 +74,6 @@ void set_time(time_t t) {
     _mutex->unlock();
 }
 
-clock_t clock() {
-    _mutex->lock();
-    clock_t t = us_ticker_read();
-    t /= 1000000 / CLOCKS_PER_SEC; // convert to processor time
-    _mutex->unlock();
-    return t;
-}
-
 void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void)) {
     _mutex->lock();
     _rtc_read = read_rtc;
diff --git a/platform/mbed_rtc_time.h b/platform/mbed_rtc_time.h
index 84a3739ec32..ee3e7ec7a1e 100644
--- a/platform/mbed_rtc_time.h
+++ b/platform/mbed_rtc_time.h
@@ -1,6 +1,10 @@
 
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_rtc_time rtc_time functions
+ * @{
+ */
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
  *
@@ -90,3 +94,4 @@ void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init
 #endif
 
 /** @}*/
+/** @}*/
diff --git a/platform/mbed_semihost_api.h b/platform/mbed_semihost_api.h
index 9127c5ff006..611cce69c07 100644
--- a/platform/mbed_semihost_api.h
+++ b/platform/mbed_semihost_api.h
@@ -1,6 +1,4 @@
 
-/** \addtogroup platform */
-/** @{*/
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
  *
@@ -95,4 +93,4 @@ int semihost_disabledebug(void);
 
 #endif
 
-/** @}*/
+
diff --git a/platform/mbed_sleep.h b/platform/mbed_sleep.h
index a7dfb37d2c1..23fa5150f42 100644
--- a/platform/mbed_sleep.h
+++ b/platform/mbed_sleep.h
@@ -1,6 +1,11 @@
 
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_sleep Sleep functions
+ * @{
+ */
+ 
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2017 ARM Limited
  *
@@ -62,13 +67,13 @@ extern "C" {
 
 /** Lock the deep sleep mode
  *
- * This locks the automatic deep mode selection. 
+ * This locks the automatic deep mode selection.
  * sleep_manager_sleep_auto() will ignore deepsleep mode if
  * this function is invoked at least once (the internal counter is non-zero)
  *
  * Use this locking mechanism for interrupt driven API that are
  * running in the background and deepsleep could affect their functionality
- * 
+ *
  * The lock is a counter, can be locked up to USHRT_MAX
  * This function is IRQ and thread safe
  */
@@ -76,8 +81,8 @@ void sleep_manager_lock_deep_sleep(void);
 
 /** Unlock the deep sleep mode
  *
- * Use unlocking in pair with sleep_manager_lock_deep_sleep(). 
- * 
+ * Use unlocking in pair with sleep_manager_lock_deep_sleep().
+ *
  * The lock is a counter, should be equally unlocked as locked
  * This function is IRQ and thread safe
  */
@@ -97,7 +102,7 @@ bool sleep_manager_can_deep_sleep(void);
  * @note
  * If MBED_DEBUG is defined, only hal_sleep is allowed. This ensures the debugger
  * to be active for debug modes.
- * 
+ *
  */
 void sleep_manager_sleep_auto(void);
 
@@ -106,6 +111,10 @@ void sleep_manager_sleep_auto(void);
  * @note This function can be a noop if not implemented by the platform.
  * @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined).
  * @note This function will be a noop while uVisor is in use.
+ * @note This function will be a noop if the following conditions are met:
+ *   - The RTOS is present
+ *   - The processor turn off the Systick clock during sleep
+ *   - The target does not implement tickless mode
  *
  * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
  * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
@@ -123,7 +132,9 @@ __INLINE static void sleep(void)
 {
 #if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
 #if DEVICE_SLEEP
+#if (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_STCLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS)
     sleep_manager_sleep_auto();
+#endif /* (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_STCLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS) */
 #endif /* DEVICE_SLEEP */
 #endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */
 }
@@ -163,3 +174,4 @@ __INLINE static void deepsleep(void)
 #endif
 
 /** @}*/
+/** @}*/
diff --git a/platform/mbed_stats.h b/platform/mbed_stats.h
index 99662af4142..c997baefab2 100644
--- a/platform/mbed_stats.h
+++ b/platform/mbed_stats.h
@@ -1,6 +1,10 @@
 
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_stats stats functions
+ * @{
+ */
 /* mbed Microcontroller Library
  * Copyright (c) 2016-2016 ARM Limited
  *
@@ -25,6 +29,9 @@
 extern "C" {
 #endif
 
+/**
+ * struct mbed_stats_heap_t definition
+ */
 typedef struct {
     uint32_t current_size;      /**< Bytes allocated currently. */
     uint32_t max_size;          /**< Max bytes allocated at a given time. */
@@ -41,6 +48,9 @@ typedef struct {
  */
 void mbed_stats_heap_get(mbed_stats_heap_t *stats);
 
+/**
+ * struct mbed_stats_stack_t definition
+ */
 typedef struct {
     uint32_t thread_id;         /**< Identifier for thread that owns the stack or 0 if multiple threads. */
     uint32_t max_size;          /**< Maximum number of bytes used on the stack. */
@@ -73,3 +83,5 @@ size_t mbed_stats_stack_get_each(mbed_stats_stack_t *stats, size_t count);
 #endif
 
 /** @}*/
+
+/** @}*/
diff --git a/platform/mbed_toolchain.h b/platform/mbed_toolchain.h
index c5bec189bcd..a911e9c9974 100644
--- a/platform/mbed_toolchain.h
+++ b/platform/mbed_toolchain.h
@@ -1,6 +1,11 @@
 
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_toolchain Toolchain functions
+ * @{
+ */
+ 
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
  *
@@ -92,6 +97,26 @@
 #endif
 #endif
 
+/** MBED_USED
+ *  Inform the compiler that a static variable is to be retained in the object file, even if it is unreferenced.
+ *
+ *  @code
+ *  #include "mbed_toolchain.h"
+ *
+ *  MBED_USED int foo;
+ *
+ *  @endcode
+ */
+#ifndef MBED_USED
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_USED __attribute__((used))
+#elif defined(__ICCARM__)
+#define MBED_USED __root
+#else
+#define MBED_USED
+#endif
+#endif
+
 /** MBED_WEAK
  *  Mark a function as being weak.
  *
@@ -362,3 +387,4 @@ typedef int FILEHANDLE;
 #endif
 
 /** @}*/
+/** @}*/
diff --git a/platform/mbed_wait_api.h b/platform/mbed_wait_api.h
index 91619def4ac..a58509f741a 100644
--- a/platform/mbed_wait_api.h
+++ b/platform/mbed_wait_api.h
@@ -1,6 +1,11 @@
 
 /** \addtogroup platform */
 /** @{*/
+/**
+ * \defgroup platform_wait_api wait_api functions
+ * @{
+ */
+ 
 /* mbed Microcontroller Library
  * Copyright (c) 2006-2013 ARM Limited
  *
@@ -70,3 +75,4 @@ void wait_us(int us);
 #endif
 
 /** @}*/
+/** @}*/
diff --git a/platform/mbed_wait_api_no_rtos.c b/platform/mbed_wait_api_no_rtos.c
index 55820a4b99a..a78dd8bc799 100644
--- a/platform/mbed_wait_api_no_rtos.c
+++ b/platform/mbed_wait_api_no_rtos.c
@@ -30,8 +30,9 @@ void wait_ms(int ms) {
 }
 
 void wait_us(int us) {
-    uint32_t start = us_ticker_read();
-    while ((us_ticker_read() - start) < (uint32_t)us);
+    const ticker_data_t *const ticker = get_us_ticker_data();
+    uint32_t start = ticker_read(ticker);
+    while ((ticker_read(ticker) - start) < (uint32_t)us);
 }
 
 #endif // #ifndef MBED_CONF_RTOS_PRESENT
diff --git a/platform/mbed_wait_api_rtos.cpp b/platform/mbed_wait_api_rtos.cpp
index 7ed609a1439..d89b139cf2b 100644
--- a/platform/mbed_wait_api_rtos.cpp
+++ b/platform/mbed_wait_api_rtos.cpp
@@ -22,6 +22,7 @@
 #include "hal/us_ticker_api.h"
 #include "rtos/rtos.h"
 #include "platform/mbed_critical.h"
+#include "platform/mbed_sleep.h"
 
 void wait(float s) {
     wait_us(s * 1000000.0f);
@@ -32,15 +33,19 @@ void wait_ms(int ms) {
 }
 
 void wait_us(int us) {
-    uint32_t start = us_ticker_read();
+    const ticker_data_t *const ticker = get_us_ticker_data();
+
+    uint32_t start = ticker_read(ticker);
     // Use the RTOS to wait for millisecond delays if possible
     int ms = us / 1000;
     if ((ms > 0) && core_util_are_interrupts_enabled()) {
+        sleep_manager_lock_deep_sleep();
         Thread::wait((uint32_t)ms);
+        sleep_manager_unlock_deep_sleep();
     }
     // Use busy waiting for sub-millisecond delays, or for the whole
     // interval if interrupts are not enabled
-    while ((us_ticker_read() - start) < (uint32_t)us);
+    while ((ticker_read(ticker) - start) < (uint32_t)us);
 }
 
 #endif // #if MBED_CONF_RTOS_PRESENT
diff --git a/rtos/EventFlags.cpp b/rtos/EventFlags.cpp
index abd88a1142e..3d6b79321f1 100644
--- a/rtos/EventFlags.cpp
+++ b/rtos/EventFlags.cpp
@@ -39,11 +39,11 @@ EventFlags::EventFlags(const char *name)
 void EventFlags::constructor(const char *name)
 {
     memset(&_obj_mem, 0, sizeof(_obj_mem));
-    memset(&_attr, 0, sizeof(_attr));
-    _attr.name = name ? name : "application_unnamed_event_flags";
-    _attr.cb_mem = &_obj_mem;
-    _attr.cb_size = sizeof(_obj_mem);
-    _id = osEventFlagsNew(&_attr);
+    osEventFlagsAttr_t attr;
+    attr.name = name ? name : "application_unnamed_event_flags";
+    attr.cb_mem = &_obj_mem;
+    attr.cb_size = sizeof(_obj_mem);
+    _id = osEventFlagsNew(&attr);
     MBED_ASSERT(_id);
 }
 
diff --git a/rtos/EventFlags.h b/rtos/EventFlags.h
index 8f0e2b20ed2..5beb5e5ef17 100644
--- a/rtos/EventFlags.h
+++ b/rtos/EventFlags.h
@@ -32,7 +32,11 @@
 namespace rtos {
 /** \addtogroup rtos */
 /** @{*/
-
+/**
+ * \defgroup rtos_EventFlags EventFlags class
+ * @{
+ */
+ 
 /** The EventFlags class is used to signal or wait for an arbitrary event or events.
  @note 
  EventFlags support 31 flags so the MSB flag is ignored, it is used to return an error code (@a osFlagsError)
@@ -90,11 +94,12 @@ class EventFlags : private mbed::NonCopyable<EventFlags> {
     void constructor(const char *name = NULL);
     uint32_t wait(uint32_t flags, uint32_t opt, uint32_t timeout, bool clear);
     osEventFlagsId_t                _id;
-    osEventFlagsAttr_t              _attr;
     mbed_rtos_storage_event_flags_t _obj_mem;
 };
 
+/** @}*/
+/** @}*/
+
 }
 #endif
 
-/** @}*/
diff --git a/rtos/Mail.h b/rtos/Mail.h
index 602907e34e3..83a3a246569 100644
--- a/rtos/Mail.h
+++ b/rtos/Mail.h
@@ -38,7 +38,11 @@ using namespace rtos;
 namespace rtos {
 /** \addtogroup rtos */
 /** @{*/
-
+/**
+ * \defgroup rtos_Mail Mail class
+ * @{
+ */
+ 
 /** The Mail class allow to control, send, receive, or wait for mail.
  A mail is a memory block that is send to a thread or interrupt service routine.
   @tparam  T         data type of a single message element.
@@ -103,9 +107,12 @@ class Mail : private mbed::NonCopyable<Mail<T, queue_sz> > {
     MemoryPool<T, queue_sz> _pool;
 };
 
+/** @}*/
+/** @}*/
+
 }
 
 #endif
 
 
-/** @}*/
+
diff --git a/rtos/MemoryPool.h b/rtos/MemoryPool.h
index 361ae6518fa..d76a99e794f 100644
--- a/rtos/MemoryPool.h
+++ b/rtos/MemoryPool.h
@@ -33,7 +33,11 @@
 namespace rtos {
 /** \addtogroup rtos */
 /** @{*/
-
+/**
+ * \defgroup rtos_MemoryPool MemoryPool class
+ * @{
+ */
+ 
 /** Define and manage fixed-size memory pools of objects of a given type.
   @tparam  T         data type of a single object (element).
   @tparam  queue_sz  maximum number of objects (elements) in the memory pool.
@@ -50,12 +54,12 @@ class MemoryPool : private mbed::NonCopyable<MemoryPool<T, pool_sz> > {
     MemoryPool() {
         memset(_pool_mem, 0, sizeof(_pool_mem));
         memset(&_obj_mem, 0, sizeof(_obj_mem));
-        memset(&_attr, 0, sizeof(_attr));
-        _attr.mp_mem = _pool_mem;
-        _attr.mp_size = sizeof(_pool_mem);
-        _attr.cb_mem = &_obj_mem;
-        _attr.cb_size = sizeof(_obj_mem);
-        _id = osMemoryPoolNew(pool_sz, sizeof(T), &_attr);
+        osMemoryPoolAttr_t attr = { 0 };
+        attr.mp_mem = _pool_mem;
+        attr.mp_size = sizeof(_pool_mem);
+        attr.cb_mem = &_obj_mem;
+        attr.cb_size = sizeof(_obj_mem);
+        _id = osMemoryPoolNew(pool_sz, sizeof(T), &attr);
         MBED_ASSERT(_id);
     }
 
@@ -95,13 +99,14 @@ class MemoryPool : private mbed::NonCopyable<MemoryPool<T, pool_sz> > {
 
 private:
     osMemoryPoolId_t             _id;
-    osMemoryPoolAttr_t           _attr;
     /* osMemoryPoolNew requires that pool block size is a multiple of 4 bytes. */
     char                         _pool_mem[((sizeof(T) + 3) & ~3) * pool_sz];
     mbed_rtos_storage_mem_pool_t _obj_mem;
 };
+/** @}*/
+/** @}*/
 
 }
 #endif
 
-/** @}*/
+
diff --git a/rtos/Mutex.cpp b/rtos/Mutex.cpp
index 359af105368..874af4608cc 100644
--- a/rtos/Mutex.cpp
+++ b/rtos/Mutex.cpp
@@ -40,12 +40,12 @@ Mutex::Mutex(const char *name)
 void Mutex::constructor(const char *name)
 {
     memset(&_obj_mem, 0, sizeof(_obj_mem));
-    memset(&_attr, 0, sizeof(_attr));
-    _attr.name = name ? name : "aplication_unnamed_mutex";
-    _attr.cb_mem = &_obj_mem;
-    _attr.cb_size = sizeof(_obj_mem);
-    _attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust;
-    _id = osMutexNew(&_attr);
+    osMutexAttr_t attr = { 0 };
+    attr.name = name ? name : "aplication_unnamed_mutex";
+    attr.cb_mem = &_obj_mem;
+    attr.cb_size = sizeof(_obj_mem);
+    attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust;
+    _id = osMutexNew(&attr);
     MBED_ASSERT(_id);
 }
 
diff --git a/rtos/Mutex.h b/rtos/Mutex.h
index 4f1ed8a6aae..e84631e64f0 100644
--- a/rtos/Mutex.h
+++ b/rtos/Mutex.h
@@ -32,7 +32,11 @@
 namespace rtos {
 /** \addtogroup rtos */
 /** @{*/
-
+/**
+ * \defgroup rtos_Mutex Mutex class
+ * @{
+ */
+ 
 /** The Mutex class is used to synchronize the execution of threads.
  This is for example used to protect access to a shared resource.
 
@@ -82,11 +86,11 @@ class Mutex : private mbed::NonCopyable<Mutex> {
     void constructor(const char *name = NULL);
 
     osMutexId_t               _id;
-    osMutexAttr_t             _attr;
     mbed_rtos_storage_mutex_t _obj_mem;
 };
-
+/** @}*/
+/** @}*/
 }
 #endif
 
-/** @}*/
+
diff --git a/rtos/Queue.h b/rtos/Queue.h
index 56739522ae9..556c9b8f0d9 100644
--- a/rtos/Queue.h
+++ b/rtos/Queue.h
@@ -34,7 +34,11 @@
 namespace rtos {
 /** \addtogroup rtos */
 /** @{*/
-
+/**
+ * \defgroup rtos_EventFlags EventFlags class
+ * @{
+ */
+ 
 /** The Queue class allow to control, send, receive, or wait for messages.
  A message can be a integer or pointer value  to a certain type T that is send
  to a thread or interrupt service routine.
@@ -51,12 +55,12 @@ class Queue : private mbed::NonCopyable<Queue<T, queue_sz> > {
     /** Create and initialize a message Queue. */
     Queue() {
         memset(&_obj_mem, 0, sizeof(_obj_mem));
-        memset(&_attr, 0, sizeof(_attr));
-        _attr.mq_mem = _queue_mem;
-        _attr.mq_size = sizeof(_queue_mem);
-        _attr.cb_mem = &_obj_mem;
-        _attr.cb_size = sizeof(_obj_mem);
-        _id = osMessageQueueNew(queue_sz, sizeof(T*), &_attr);
+        osMessageQueueAttr_t attr = { 0 };
+        attr.mq_mem = _queue_mem;
+        attr.mq_size = sizeof(_queue_mem);
+        attr.cb_mem = &_obj_mem;
+        attr.cb_size = sizeof(_obj_mem);
+        _id = osMessageQueueNew(queue_sz, sizeof(T*), &attr);
         MBED_ASSERT(_id);
     }
 
@@ -115,12 +119,12 @@ class Queue : private mbed::NonCopyable<Queue<T, queue_sz> > {
 
 private:
     osMessageQueueId_t            _id;
-    osMessageQueueAttr_t          _attr;
     char                          _queue_mem[queue_sz * (sizeof(T*) + sizeof(mbed_rtos_storage_message_t))];
     mbed_rtos_storage_msg_queue_t _obj_mem;
 };
+/** @}*/
+/** @}*/
 
 }
 #endif
 
-/** @}*/
diff --git a/rtos/RtosTimer.cpp b/rtos/RtosTimer.cpp
index acec84ed98c..3e6c19718be 100644
--- a/rtos/RtosTimer.cpp
+++ b/rtos/RtosTimer.cpp
@@ -31,10 +31,10 @@ namespace rtos {
 void RtosTimer::constructor(mbed::Callback<void()> func, os_timer_type type) {
     _function = func;
     memset(&_obj_mem, 0, sizeof(_obj_mem));
-    memset(&_attr, 0, sizeof(_attr));
-    _attr.cb_mem = &_obj_mem;
-    _attr.cb_size = sizeof(_obj_mem);
-    _id = osTimerNew((void (*)(void *))Callback<void()>::thunk, type, &_function, &_attr);
+    osTimerAttr_t attr = { 0 };
+    attr.cb_mem = &_obj_mem;
+    attr.cb_size = sizeof(_obj_mem);
+    _id = osTimerNew((void (*)(void *))Callback<void()>::thunk, type, &_function, &attr);
     MBED_ASSERT(_id);
 }
 
diff --git a/rtos/RtosTimer.h b/rtos/RtosTimer.h
index 3abef47c942..c5e6276468b 100644
--- a/rtos/RtosTimer.h
+++ b/rtos/RtosTimer.h
@@ -33,7 +33,11 @@
 namespace rtos {
 /** \addtogroup rtos */
 /** @{*/
-
+/**
+ * \defgroup rtos_RtosTimer RtosTimer class
+ * @{
+ */
+ 
 /** The RtosTimer class allow creating and and controlling of timer functions in the system.
  A timer function is called when a time period expires whereby both on-shot and
  periodic timers are possible. A timer can be started, restarted, or stopped.
@@ -131,13 +135,21 @@ class RtosTimer : private mbed::NonCopyable<RtosTimer> {
     }
 
     /** Stop the timer.
-      @return  status code that indicates the execution status of the function.
+      @return  status code that indicates the execution status of the function:
+          @a osOK the timer has been stopped.
+          @a osErrorISR @a stop cannot be called from interrupt service routines.
+          @a osErrorParameter internal error.
+          @a osErrorResource the timer is not running.
     */
     osStatus stop(void);
 
-    /** Start the timer.
-      @param   millisec  time delay value of the timer.
-      @return  status code that indicates the execution status of the function.
+    /** Start or restart the timer.
+      @param   millisec  non-zero value of the timer.
+      @return  status code that indicates the execution status of the function:
+          @a osOK the timer has been started or restarted.
+          @a osErrorISR @a start cannot be called from interrupt service routines.
+          @a osErrorParameter internal error or incorrect parameter value.
+          @a osErrorResource internal error (the timer is in an invalid timer state).
     */
     osStatus start(uint32_t millisec);
 
@@ -149,13 +161,14 @@ class RtosTimer : private mbed::NonCopyable<RtosTimer> {
     void constructor(mbed::Callback<void()> func, os_timer_type type);
 
     osTimerId_t _id;
-    osTimerAttr_t _attr;
     mbed_rtos_storage_timer_t _obj_mem;
     mbed::Callback<void()> _function;
 };
+/** @}*/
+/** @}*/
 
 }
 
 #endif
 
-/** @}*/
+
diff --git a/rtos/Semaphore.cpp b/rtos/Semaphore.cpp
index 107dccb33fc..fb082d3c449 100644
--- a/rtos/Semaphore.cpp
+++ b/rtos/Semaphore.cpp
@@ -36,10 +36,10 @@ Semaphore::Semaphore(int32_t count, uint16_t max_count) {
 
 void Semaphore::constructor(int32_t count, uint16_t max_count) {
     memset(&_obj_mem, 0, sizeof(_obj_mem));
-    memset(&_attr, 0, sizeof(_attr));
-    _attr.cb_mem = &_obj_mem;
-    _attr.cb_size = sizeof(_obj_mem);
-    _id = osSemaphoreNew(max_count, count, &_attr);
+    osSemaphoreAttr_t attr = { 0 };
+    attr.cb_mem = &_obj_mem;
+    attr.cb_size = sizeof(_obj_mem);
+    _id = osSemaphoreNew(max_count, count, &attr);
     MBED_ASSERT(_id != NULL);
 }
 
diff --git a/rtos/Semaphore.h b/rtos/Semaphore.h
index 80dc928ede4..88b479c5e4f 100644
--- a/rtos/Semaphore.h
+++ b/rtos/Semaphore.h
@@ -31,6 +31,10 @@
 namespace rtos {
 /** \addtogroup rtos */
 /** @{*/
+/**
+ * \defgroup rtos_Semaphore Semaphore class
+ * @{
+ */
 
 /** The Semaphore class is used to manage and protect access to a set of shared resources.
  *
@@ -71,11 +75,11 @@ class Semaphore : private mbed::NonCopyable<Semaphore> {
     void constructor(int32_t count, uint16_t max_count);
 
     osSemaphoreId_t               _id;
-    osSemaphoreAttr_t             _attr;
     mbed_rtos_storage_semaphore_t _obj_mem;
 };
-
+/** @}*/
+/** @}*/
 }
 #endif
 
-/** @}*/
+
diff --git a/rtos/TARGET_CORTEX/mbed_rtx_conf.h b/rtos/TARGET_CORTEX/mbed_rtx_conf.h
index 48a4456340c..a6cd655d9f3 100644
--- a/rtos/TARGET_CORTEX/mbed_rtx_conf.h
+++ b/rtos/TARGET_CORTEX/mbed_rtx_conf.h
@@ -41,6 +41,10 @@
 
 #define OS_DYNAMIC_MEM_SIZE         0
 
+#if defined(OS_TICK_FREQ) && (OS_TICK_FREQ != 1000)
+#error "OS Tickrate must be 1000 for system timing"
+#endif
+
 #if defined (__CC_ARM) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
 /* ARM toolchain uses up to 8 static mutexes, any further mutexes will be allocated on the heap. */
 #define OS_MUTEX_OBJ_MEM            1
diff --git a/rtos/TARGET_CORTEX/mbed_rtx_handlers.c b/rtos/TARGET_CORTEX/mbed_rtx_handlers.c
index e5dcabaa790..882d4636af6 100644
--- a/rtos/TARGET_CORTEX/mbed_rtx_handlers.c
+++ b/rtos/TARGET_CORTEX/mbed_rtx_handlers.c
@@ -19,8 +19,17 @@
 #include "rtx_evr.h"
 #include "mbed_rtx.h"
 #include "mbed_error.h"
+#include "RTX_Config.h"
+
+#ifdef RTE_Compiler_EventRecorder
+#include "EventRecorder.h"              // Keil::Compiler:Event Recorder
+// Used from rtx_evr.c
+#define EvtRtxThreadExit               EventID(EventLevelAPI, 0xF2U, 0x19U)
+#define EvtRtxThreadTerminate          EventID(EventLevelAPI, 0xF2U, 0x1AU)
+#endif
 
 extern void rtos_idle_loop(void);
+extern void thread_terminate_hook(osThreadId_t id);
 
 __NO_RETURN void osRtxIdleThread (void *argument)
 {
@@ -136,3 +145,21 @@ void EvrRtxMessageQueueError (osMessageQueueId_t mq_id, int32_t status)
 }
 
 #endif
+
+// RTX hook which gets called when a thread terminates, using the event function to call hook
+void EvrRtxThreadExit (void)
+{
+    osThreadId_t thread_id = osThreadGetId();
+    thread_terminate_hook(thread_id);
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_EXIT_DISABLE) && defined(RTE_Compiler_EventRecorder))
+    EventRecord2(EvtRtxThreadExit, 0U, 0U);
+#endif
+}
+
+void EvrRtxThreadTerminate (osThreadId_t thread_id)
+{
+    thread_terminate_hook(thread_id);
+#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_TERMINATE_DISABLE) && defined(RTE_Compiler_EventRecorder))
+    EventRecord2(EvtRtxThreadTerminate, (uint32_t)thread_id, 0U);
+#endif
+}
diff --git a/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp b/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp
index 121229460ec..1ea59c5b793 100644
--- a/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp
+++ b/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp
@@ -195,6 +195,14 @@ static void default_idle_hook(void)
     core_util_critical_section_exit();
 }
 
+#elif defined(FEATURE_UVISOR)
+
+static void default_idle_hook(void)
+{
+    /* uVisor can't sleep. See <https://github.com/ARMmbed/uvisor/issues/420>
+     * for details. */
+}
+
 #else
 
 static void default_idle_hook(void)
diff --git a/rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_ARM/irq_armv8mbl.S b/rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_ARM/irq_armv8mbl.S
new file mode 100644
index 00000000000..41e4beb713f
--- /dev/null
+++ b/rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_ARM/irq_armv8mbl.S
@@ -0,0 +1,298 @@
+;/*
+; * Copyright (c) 2016-2017 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project:     CMSIS-RTOS RTX
+; * Title:       ARMv8M Baseline Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+I_T_RUN_OFS     EQU      28                     ; osInfo.thread.run offset
+TCB_SM_OFS      EQU      48                     ; TCB.stack_mem offset
+TCB_SP_OFS      EQU      56                     ; TCB.SP offset
+TCB_SF_OFS      EQU      34                     ; TCB.stack_frame offset
+TCB_TZM_OFS     EQU      64                     ; TCB.tz_memory offset
+
+
+                PRESERVE8
+                THUMB
+
+
+                AREA     |.constdata|, DATA, READONLY
+                EXPORT   irqRtxLib
+irqRtxLib       DCB      0                      ; Non weak library reference
+
+
+                AREA     |.text|, CODE, READONLY
+
+
+SVC_Handler     PROC
+                EXPORT   SVC_Handler
+                IMPORT   osRtxUserSVC
+                IMPORT   osRtxInfo
+#ifdef __DOMAIN_NS
+                IMPORT   TZ_LoadContext_S
+                IMPORT   TZ_StoreContext_S
+#endif
+
+                MRS      R0,PSP                 ; Get PSP
+                LDR      R1,[R0,#24]            ; Load saved PC from stack
+                SUBS     R1,R1,#2               ; Point to SVC instruction
+                LDRB     R1,[R1]                ; Load SVC number
+                CMP      R1,#0
+                BNE      SVC_User               ; Branch if not SVC 0
+
+                PUSH     {R0,LR}                ; Save PSP and EXC_RETURN
+                LDM      R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R7                     ; Call service function
+                POP      {R2,R3}                ; Restore PSP and EXC_RETURN
+                STMIA    R2!,{R0-R1}            ; Store function return values
+                MOV      LR,R3                  ; Set EXC_RETURN
+
+SVC_Context
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDMIA    R3!,{R1,R2}            ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BEQ      SVC_Exit               ; Branch when threads are the same
+
+                CBZ      R1,SVC_ContextSwitch   ; Branch if running thread is deleted
+
+SVC_ContextSave
+#ifdef __DOMAIN_NS
+                LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,SVC_ContextSave1    ; Branch if there is no secure context
+                PUSH     {R1,R2,R3,R7}          ; Save registers
+                MOV      R7,LR                  ; Get EXC_RETURN
+                BL       TZ_StoreContext_S      ; Store secure context
+                MOV      LR,R7                  ; Set EXC_RETURN
+                POP      {R1,R2,R3,R7}          ; Restore registers
+#endif
+
+SVC_ContextSave1
+                MRS      R0,PSP                 ; Get PSP
+                SUBS     R0,R0,#32              ; Adjust PSP
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                STMIA    R0!,{R4-R7}            ; Save R4..R7
+                MOV      R4,R8
+                MOV      R5,R9
+                MOV      R6,R10
+                MOV      R7,R11
+                STMIA    R0!,{R4-R7}            ; Save R8..R11
+
+SVC_ContextSave2
+                MOV      R0,LR                  ; Get EXC_RETURN
+                ADDS     R1,R1,#TCB_SF_OFS      ; Adjust address
+                STRB     R0,[R1]                ; Store stack frame information
+
+SVC_ContextSwitch
+                SUBS     R3,R3,#8               ; Adjust address
+                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore
+#ifdef __DOMAIN_NS
+                LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,SVC_ContextRestore1 ; Branch if there is no secure context
+                PUSH     {R2,R3}                ; Save registers
+                BL       TZ_LoadContext_S       ; Load secure context
+                POP      {R2,R3}                ; Restore registers
+#endif
+
+SVC_ContextRestore1
+                MOV      R1,R2
+                ADDS     R1,R1,#TCB_SF_OFS      ; Adjust address
+                LDRB     R0,[R1]                ; Load stack frame information
+                MOVS     R1,#0xFF
+                MVNS     R1,R1                  ; R1=0xFFFFFF00
+                ORRS     R0,R1
+                MOV      LR,R0                  ; Set EXC_RETURN
+
+#ifdef __DOMAIN_NS
+                LSLS     R0,R0,#25              ; Check domain of interrupted thread
+                BPL      SVC_ContextRestore2    ; Branch if non-secure
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                MSR      PSP,R0                 ; Set PSP
+                BX       LR                     ; Exit from handler
+#else
+                LDR      R0,[R2,#TCB_SM_OFS]    ; Load stack memory base
+                MSR      PSPLIM,R0              ; Set PSPLIM
+#endif
+
+SVC_ContextRestore2
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ADDS     R0,R0,#16              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R8..R11
+                MOV      R8,R4
+                MOV      R9,R5
+                MOV      R10,R6
+                MOV      R11,R7
+                MSR      PSP,R0                 ; Set PSP
+                SUBS     R0,R0,#32              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R4..R7
+
+SVC_Exit
+                BX       LR                     ; Exit from handler
+
+SVC_User
+                PUSH     {R4,LR}                ; Save registers
+                LDR      R2,=osRtxUserSVC       ; Load address of SVC table
+                LDR      R3,[R2]                ; Load SVC maximum number
+                CMP      R1,R3                  ; Check SVC number range
+                BHI      SVC_Done               ; Branch if out of range
+
+                LSLS     R1,R1,#2
+                LDR      R4,[R2,R1]             ; Load address of SVC function
+
+                LDM      R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R4                     ; Call service function
+                MRS      R4,PSP                 ; Get PSP
+                STR      R0,[R4]                ; Store function return value
+
+SVC_Done
+                POP      {R4,PC}                ; Return from handler
+
+                ALIGN
+                ENDP
+
+
+PendSV_Handler  PROC
+                EXPORT   PendSV_Handler
+                IMPORT   osRtxPendSV_Handler
+
+                PUSH     {R0,LR}                ; Save EXC_RETURN
+                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler
+                POP      {R0,R1}                ; Restore EXC_RETURN
+                MOV      LR,R1                  ; Set EXC_RETURN
+                B        Sys_Context
+
+                ALIGN
+                ENDP
+
+
+SysTick_Handler PROC
+                EXPORT   SysTick_Handler
+                IMPORT   osRtxTick_Handler
+
+                PUSH     {R0,LR}                ; Save EXC_RETURN
+                BL       osRtxTick_Handler      ; Call osRtxTick_Handler
+                POP      {R0,R1}                ; Restore EXC_RETURN
+                MOV      LR,R1                  ; Set EXC_RETURN
+                B        Sys_Context
+
+                ALIGN
+                ENDP
+
+
+Sys_Context     PROC
+                EXPORT   Sys_Context
+                IMPORT   osRtxInfo
+#ifdef __DOMAIN_NS
+                IMPORT   TZ_LoadContext_S
+                IMPORT   TZ_StoreContext_S
+#endif
+
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDM      R3!,{R1,R2}            ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BEQ      Sys_ContextExit        ; Branch when threads are the same
+
+Sys_ContextSave
+#ifdef __DOMAIN_NS
+                LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,Sys_ContextSave1    ; Branch if there is no secure context
+                PUSH     {R1,R2,R3,R7}          ; Save registers
+                MOV      R7,LR                  ; Get EXC_RETURN
+                BL       TZ_StoreContext_S      ; Store secure context
+                MOV      LR,R7                  ; Set EXC_RETURN
+                POP      {R1,R2,R3,R7}          ; Restore registers
+                LSLS     R7,R7,#25              ; Check domain of interrupted thread
+                BMI      Sys_ContextSave1       ; Branch if secure
+                MRS      R0,PSP                 ; Get PSP
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                B        Sys_ContextSave2
+#endif
+
+Sys_ContextSave1
+                MRS      R0,PSP                 ; Get PSP
+                SUBS     R0,R0,#32              ; Adjust address
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                STMIA    R0!,{R4-R7}            ; Save R4..R7
+                MOV      R4,R8
+                MOV      R5,R9
+                MOV      R6,R10
+                MOV      R7,R11
+                STMIA    R0!,{R4-R7}            ; Save R8..R11
+
+Sys_ContextSave2
+                MOV      R0,LR                  ; Get EXC_RETURN
+                ADDS     R1,R1,#TCB_SF_OFS      ; Adjust address
+                STRB     R0,[R1]                ; Store stack frame information
+
+Sys_ContextSwitch
+                SUBS     R3,R3,#8               ; Adjust address
+                STR      R2,[R3]                ; osRtxInfo.run: curr = next
+
+Sys_ContextRestore
+#ifdef __DOMAIN_NS
+                LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,Sys_ContextRestore1 ; Branch if there is no secure context
+                PUSH     {R2,R3}                ; Save registers
+                BL       TZ_LoadContext_S       ; Load secure context
+                POP      {R2,R3}                ; Restore registers
+#endif
+
+Sys_ContextRestore1
+                MOV      R1,R2
+                ADDS     R1,R1,#TCB_SF_OFS      ; Adjust offset
+                LDRB     R0,[R1]                ; Load stack frame information
+                MOVS     R1,#0xFF
+                MVNS     R1,R1                  ; R1=0xFFFFFF00
+                ORRS     R0,R1
+                MOV      LR,R0                  ; Set EXC_RETURN
+
+#ifdef __DOMAIN_NS
+                LSLS     R0,R0,#25              ; Check domain of interrupted thread
+                BPL      Sys_ContextRestore2    ; Branch if non-secure
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                MSR      PSP,R0                 ; Set PSP
+                BX       LR                     ; Exit from handler
+#else
+                LDR      R0,[R2,#TCB_SM_OFS]    ; Load stack memory base
+                MSR      PSPLIM,R0              ; Set PSPLIM
+#endif
+
+Sys_ContextRestore2
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ADDS     R0,R0,#16              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R8..R11
+                MOV      R8,R4
+                MOV      R9,R5
+                MOV      R10,R6
+                MOV      R11,R7
+                MSR      PSP,R0                 ; Set PSP
+                SUBS     R0,R0,#32              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R4..R7
+
+Sys_ContextExit
+                BX       LR                     ; Exit from handler
+
+                ALIGN
+                ENDP
+
+
+                END
\ No newline at end of file
diff --git a/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_ARM/irq_armv8mml.S b/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_ARM/irq_armv8mml.S
new file mode 100644
index 00000000000..1adeffa5570
--- /dev/null
+++ b/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_ARM/irq_armv8mml.S
@@ -0,0 +1,267 @@
+;/*
+; * Copyright (c) 2016-2017 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project:     CMSIS-RTOS RTX
+; * Title:       ARMv8M Mainline Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+
+I_T_RUN_OFS     EQU      28                     ; osRtxInfo.thread.run offset
+TCB_SM_OFS      EQU      48                     ; TCB.stack_mem offset
+TCB_SP_OFS      EQU      56                     ; TCB.SP offset
+TCB_SF_OFS      EQU      34                     ; TCB.stack_frame offset
+TCB_TZM_OFS     EQU      64                     ; TCB.tz_memory offset
+
+
+                PRESERVE8
+                THUMB
+
+
+                AREA     |.constdata|, DATA, READONLY
+                EXPORT   irqRtxLib
+irqRtxLib       DCB      0                      ; Non weak library reference
+
+
+                AREA     |.text|, CODE, READONLY
+
+
+SVC_Handler     PROC
+                EXPORT   SVC_Handler
+                IMPORT   osRtxUserSVC
+                IMPORT   osRtxInfo
+#ifdef __DOMAIN_NS
+                IMPORT   TZ_LoadContext_S
+                IMPORT   TZ_StoreContext_S
+#endif
+
+                MRS      R0,PSP                 ; Get PSP
+                LDR      R1,[R0,#24]            ; Load saved PC from stack
+                LDRB     R1,[R1,#-2]            ; Load SVC number
+                CMP      R1,#0
+                BNE      SVC_User               ; Branch if not SVC 0
+
+                PUSH     {R0,LR}                ; Save PSP and EXC_RETURN
+                LDM      R0,{R0-R3,R12}         ; Load function parameters and address from stack
+                BLX      R12                    ; Call service function
+                POP      {R12,LR}               ; Restore PSP and EXC_RETURN
+                STM      R12,{R0-R1}            ; Store function return values
+
+SVC_Context
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDM      R3,{R1,R2}             ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BXEQ     LR                     ; Exit when threads are the same
+
+#ifdef __FPU_USED
+                CBNZ     R1,SVC_ContextSave     ; Branch if running thread is not deleted
+                TST      LR,#0x10               ; Check if extended stack frame
+                BNE      SVC_ContextSwitch
+                LDR      R1,=0xE000EF34         ; FPCCR Address
+                LDR      R0,[R1]                ; Load FPCCR
+                BIC      R0,#1                  ; Clear LSPACT (Lazy state)
+                STR      R0,[R1]                ; Store FPCCR
+                B        SVC_ContextSwitch
+#else
+                CBZ      R1,SVC_ContextSwitch   ; Branch if running thread is deleted
+#endif
+
+SVC_ContextSave
+#ifdef __DOMAIN_NS
+                LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,SVC_ContextSave1    ; Branch if there is no secure context
+                PUSH     {R1,R2,R3,LR}          ; Save registers and EXC_RETURN
+                BL       TZ_StoreContext_S      ; Store secure context
+                POP      {R1,R2,R3,LR}          ; Restore registers and EXC_RETURN
+#endif
+
+SVC_ContextSave1
+                MRS      R0,PSP                 ; Get PSP
+                STMDB    R0!,{R4-R11}           ; Save R4..R11
+#ifdef __FPU_USED
+                TST      LR,#0x10               ; Check if extended stack frame
+                VSTMDBEQ R0!,{S16-S31}          ;  Save VFP S16.S31
+#endif
+
+SVC_ContextSave2
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                STRB     LR,[R1,#TCB_SF_OFS]    ; Store stack frame information
+
+SVC_ContextSwitch
+                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore
+#ifdef __DOMAIN_NS
+                LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,SVC_ContextRestore1 ; Branch if there is no secure context
+                PUSH     {R2,R3}                ; Save registers
+                BL       TZ_LoadContext_S       ; Load secure context
+                POP      {R2,R3}                ; Restore registers
+#endif
+
+SVC_ContextRestore1
+                LDR      R0,[R2,#TCB_SM_OFS]    ; Load stack memory base
+                LDRB     R1,[R2,#TCB_SF_OFS]    ; Load stack frame information
+                MSR      PSPLIM,R0              ; Set PSPLIM
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ORR      LR,R1,#0xFFFFFF00      ; Set EXC_RETURN
+
+#ifdef __DOMAIN_NS
+                TST      LR,#0x40               ; Check domain of interrupted thread
+                BNE      SVC_ContextRestore2    ; Branch if secure
+#endif
+
+#ifdef __FPU_USED
+                TST      LR,#0x10               ; Check if extended stack frame
+                VLDMIAEQ R0!,{S16-S31}          ;  Restore VFP S16..S31
+#endif
+                LDMIA    R0!,{R4-R11}           ; Restore R4..R11
+
+SVC_ContextRestore2
+                MSR      PSP,R0                 ; Set PSP
+
+SVC_Exit
+                BX       LR                     ; Exit from handler
+
+SVC_User
+                PUSH     {R4,LR}                ; Save registers
+                LDR      R2,=osRtxUserSVC       ; Load address of SVC table
+                LDR      R3,[R2]                ; Load SVC maximum number
+                CMP      R1,R3                  ; Check SVC number range
+                BHI      SVC_Done               ; Branch if out of range
+
+                LDR      R4,[R2,R1,LSL #2]      ; Load address of SVC function
+
+                LDM      R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R4                     ; Call service function
+                MRS      R4,PSP                 ; Get PSP
+                STR      R0,[R4]                ; Store function return value
+
+SVC_Done
+                POP      {R4,PC}                ; Return from handler
+
+                ALIGN
+                ENDP
+
+
+PendSV_Handler  PROC
+                EXPORT   PendSV_Handler
+                IMPORT   osRtxPendSV_Handler
+
+                PUSH     {R4,LR}                ; Save EXC_RETURN
+                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler
+                POP      {R4,LR}                ; Restore EXC_RETURN
+                B        Sys_Context
+
+                ALIGN
+                ENDP
+
+
+SysTick_Handler PROC
+                EXPORT   SysTick_Handler
+                IMPORT   osRtxTick_Handler
+
+                PUSH     {R4,LR}                ; Save EXC_RETURN
+                BL       osRtxTick_Handler      ; Call osRtxTick_Handler
+                POP      {R4,LR}                ; Restore EXC_RETURN
+                B        Sys_Context
+
+                ALIGN
+                ENDP
+
+
+Sys_Context     PROC
+                EXPORT   Sys_Context
+                IMPORT   osRtxInfo
+#ifdef __DOMAIN_NS
+                IMPORT   TZ_LoadContext_S
+                IMPORT   TZ_StoreContext_S
+#endif
+
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDM      R3,{R1,R2}             ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BXEQ     LR                     ; Exit when threads are the same
+
+Sys_ContextSave
+#ifdef __DOMAIN_NS
+                LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,Sys_ContextSave1    ; Branch if there is no secure context
+                PUSH     {R1,R2,R3,LR}          ; Save registers and EXC_RETURN
+                BL       TZ_StoreContext_S      ; Store secure context
+                POP      {R1,R2,R3,LR}          ; Restore registers and EXC_RETURN
+                TST      LR,#0x40               ; Check domain of interrupted thread
+                MRSNE    R0,PSP                 ; Get PSP
+                BNE      Sys_ContextSave2       ; Branch if secure
+#endif
+
+Sys_ContextSave1
+                MRS      R0,PSP                 ; Get PSP
+                STMDB    R0!,{R4-R11}           ; Save R4..R11
+#ifdef __FPU_USED
+                TST      LR,#0x10               ; Check if extended stack frame
+                VSTMDBEQ R0!,{S16-S31}          ;  Save VFP S16.S31
+#endif
+
+Sys_ContextSave2
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                STRB     LR,[R1,#TCB_SF_OFS]    ; Store stack frame information
+
+Sys_ContextSwitch
+                STR      R2,[R3]                ; osRtxInfo.run: curr = next
+
+Sys_ContextRestore
+#ifdef __DOMAIN_NS
+                LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,Sys_ContextRestore1 ; Branch if there is no secure context
+                PUSH     {R2,R3}                ; Save registers
+                BL       TZ_LoadContext_S       ; Load secure context
+                POP      {R2,R3}                ; Restore registers
+#endif
+
+Sys_ContextRestore1
+                LDR      R0,[R2,#TCB_SM_OFS]    ; Load stack memory base
+                LDRB     R1,[R2,#TCB_SF_OFS]    ; Load stack frame information
+                MSR      PSPLIM,R0              ; Set PSPLIM
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ORR      LR,R1,#0xFFFFFF00      ; Set EXC_RETURN
+
+#ifdef __DOMAIN_NS
+                TST      LR,#0x40               ; Check domain of interrupted thread
+                BNE      Sys_ContextRestore2    ; Branch if secure
+#endif
+
+#ifdef __FPU_USED
+                TST      LR,#0x10               ; Check if extended stack frame
+                VLDMIAEQ R0!,{S16-S31}          ;  Restore VFP S16..S31
+#endif
+                LDMIA    R0!,{R4-R11}           ; Restore R4..R11
+
+Sys_ContextRestore2
+                MSR      PSP,R0                 ; Set PSP
+
+Sys_ContextExit
+                BX       LR                     ; Exit from handler
+
+                ALIGN
+                ENDP
+
+
+                END
\ No newline at end of file
diff --git a/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_GCC/irq_armv8mml.S b/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_GCC/irq_armv8mml.S
index c01721b1521..49f80cf9b13 100644
--- a/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_GCC/irq_armv8mml.S
+++ b/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_GCC/irq_armv8mml.S
@@ -27,14 +27,6 @@
         .file    "irq_armv8mml.S"
         .syntax  unified
 
-        .ifndef  __DOMAIN_NS
-        .equ     __DOMAIN_NS, 0
-        .endif
-
-        .ifndef  __FPU_USED
-        .equ     __FPU_USED,  0
-        .endif
-
         .equ     I_T_RUN_OFS, 28        // osRtxInfo.thread.run offset
         .equ     TCB_SM_OFS,  48        // TCB.stack_mem offset
         .equ     TCB_SP_OFS,  56        // TCB.SP offset
@@ -78,7 +70,7 @@ SVC_Context:
         IT       EQ
         BXEQ     LR                     // Exit when threads are the same
 
-        .if      __FPU_USED == 1
+#ifdef __FPU_USED
         CBNZ     R1,SVC_ContextSave     // Branch if running thread is not deleted
         TST      LR,#0x10               // Check if extended stack frame
         BNE      SVC_ContextSwitch
@@ -87,27 +79,27 @@ SVC_Context:
         BIC      R0,#1                  // Clear LSPACT (Lazy state)
         STR      R0,[R1]                // Store FPCCR
         B        SVC_ContextSwitch
-        .else
+#else
         CBZ      R1,SVC_ContextSwitch   // Branch if running thread is deleted
-        .endif
+#endif
 
 SVC_ContextSave:
-        .if      __DOMAIN_NS == 1
+#ifdef __DOMAIN_NS
         LDR      R0,[R1,#TCB_TZM_OFS]   // Load TrustZone memory identifier
         CBZ      R0,SVC_ContextSave1    // Branch if there is no secure context
         PUSH     {R1,R2,R3,LR}          // Save registers and EXC_RETURN
         BL       TZ_StoreContext_S      // Store secure context
         POP      {R1,R2,R3,LR}          // Restore registers and EXC_RETURN
-        .endif
+#endif
 
 SVC_ContextSave1:
         MRS      R0,PSP                 // Get PSP
         STMDB    R0!,{R4-R11}           // Save R4..R11
-        .if      __FPU_USED == 1
+#ifdef __FPU_USED
         TST      LR,#0x10               // Check if extended stack frame
         IT       EQ
         VSTMDBEQ R0!,{S16-S31}          //  Save VFP S16.S31
-        .endif
+#endif
 
 SVC_ContextSave2:
         STR      R0,[R1,#TCB_SP_OFS]    // Store SP
@@ -117,13 +109,13 @@ SVC_ContextSwitch:
         STR      R2,[R3]                // osRtxInfo.thread.run: curr = next
 
 SVC_ContextRestore:
-        .if      __DOMAIN_NS == 1
+#ifdef __DOMAIN_NS
         LDR      R0,[R2,#TCB_TZM_OFS]   // Load TrustZone memory identifier
         CBZ      R0,SVC_ContextRestore1 // Branch if there is no secure context
         PUSH     {R2,R3}                // Save registers
         BL       TZ_LoadContext_S       // Load secure context
         POP      {R2,R3}                // Restore registers
-        .endif
+#endif
 
 SVC_ContextRestore1:
         LDR      R0,[R2,#TCB_SM_OFS]    // Load stack memory base
@@ -132,16 +124,16 @@ SVC_ContextRestore1:
         LDR      R0,[R2,#TCB_SP_OFS]    // Load SP
         ORR      LR,R1,#0xFFFFFF00      // Set EXC_RETURN
 
-        .if      __DOMAIN_NS == 1
+#ifdef __DOMAIN_NS
         TST      LR,#0x40               // Check domain of interrupted thread
         BNE      SVC_ContextRestore2    // Branch if secure
-        .endif
+#endif
 
-        .if      __FPU_USED == 1
+#ifdef __FPU_USED
         TST      LR,#0x10               // Check if extended stack frame
         IT       EQ
         VLDMIAEQ R0!,{S16-S31}          //  Restore VFP S16..S31
-        .endif
+#endif
         LDMIA    R0!,{R4-R11}           // Restore R4..R11
 
 SVC_ContextRestore2:
@@ -217,7 +209,7 @@ Sys_Context:
         BXEQ     LR                     // Exit when threads are the same
 
 Sys_ContextSave:
-        .if      __DOMAIN_NS == 1
+#ifdef __DOMAIN_NS
         LDR      R0,[R1,#TCB_TZM_OFS]   // Load TrustZone memory identifier
         CBZ      R0,Sys_ContextSave1    // Branch if there is no secure context
         PUSH     {R1,R2,R3,LR}          // Save registers and EXC_RETURN
@@ -227,16 +219,16 @@ Sys_ContextSave:
         IT       NE
         MRSNE    R0,PSP                 // Get PSP
         BNE      Sys_ContextSave2       // Branch if secure
-        .endif
+#endif
 
 Sys_ContextSave1:
         MRS      R0,PSP                 // Get PSP
         STMDB    R0!,{R4-R11}           // Save R4..R11
-        .if      __FPU_USED == 1
+#ifdef __FPU_USED
         TST      LR,#0x10               // Check if extended stack frame
         IT       EQ
         VSTMDBEQ R0!,{S16-S31}          //  Save VFP S16.S31
-        .endif
+#endif
 
 Sys_ContextSave2:
         STR      R0,[R1,#TCB_SP_OFS]    // Store SP
@@ -246,13 +238,13 @@ Sys_ContextSwitch:
         STR      R2,[R3]                // osRtxInfo.run: curr = next
 
 Sys_ContextRestore:
-        .if      __DOMAIN_NS == 1
+#ifdef __DOMAIN_NS
         LDR      R0,[R2,#TCB_TZM_OFS]   // Load TrustZone memory identifier
         CBZ      R0,Sys_ContextRestore1 // Branch if there is no secure context
         PUSH     {R2,R3}                // Save registers
         BL       TZ_LoadContext_S       // Load secure context
         POP      {R2,R3}                // Restore registers
-        .endif
+#endif
 
 Sys_ContextRestore1:
         LDR      R0,[R2,#TCB_SM_OFS]    // Load stack memory base
@@ -261,16 +253,16 @@ Sys_ContextRestore1:
         LDR      R0,[R2,#TCB_SP_OFS]    // Load SP
         ORR      LR,R1,#0xFFFFFF00      // Set EXC_RETURN
 
-        .if      __DOMAIN_NS == 1
+#ifdef __DOMAIN_NS
         TST      LR,#0x40               // Check domain of interrupted thread
         BNE      Sys_ContextRestore2    // Branch if secure
-        .endif
+#endif
 
-        .if      __FPU_USED == 1
+#ifdef __FPU_USED
         TST      LR,#0x10               // Check if extended stack frame
         IT       EQ
         VLDMIAEQ R0!,{S16-S31}          //  Restore VFP S16..S31
-        .endif
+#endif
         LDMIA    R0!,{R4-R11}           // Restore R4..R11
 
 Sys_ContextRestore2:
diff --git a/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_IAR/irq_armv8mml.S b/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_IAR/irq_armv8mml.S
new file mode 100644
index 00000000000..20c041119f1
--- /dev/null
+++ b/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_IAR/irq_armv8mml.S
@@ -0,0 +1,253 @@
+;/*
+; * Copyright (c) 2016-2017 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project:     CMSIS-RTOS RTX
+; * Title:       ARMv8M Mainline Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+                NAME    irq_armv8mml.S
+
+I_T_RUN_OFS     EQU      28                     ; osRtxInfo.thread.run offset
+TCB_SM_OFS      EQU      48                     ; TCB.stack_mem offset
+TCB_SP_OFS      EQU      56                     ; TCB.SP offset
+TCB_SF_OFS      EQU      34                     ; TCB.stack_frame offset
+TCB_TZM_OFS     EQU      64                     ; TCB.tz_memory offset
+
+
+                PRESERVE8
+                SECTION .rodata:DATA:NOROOT(2)
+
+                EXPORT   irqRtxLib
+irqRtxLib       DCB      0                      ; Non weak library reference
+
+                THUMB
+                SECTION .text:CODE:NOROOT(2)
+
+
+SVC_Handler
+                EXPORT   SVC_Handler
+                IMPORT   osRtxUserSVC
+                IMPORT   osRtxInfo
+#ifdef __DOMAIN_NS
+                IMPORT   TZ_LoadContext_S
+                IMPORT   TZ_StoreContext_S
+#endif
+
+                MRS      R0,PSP                 ; Get PSP
+                LDR      R1,[R0,#24]            ; Load saved PC from stack
+                LDRB     R1,[R1,#-2]            ; Load SVC number
+                CMP      R1,#0
+                BNE      SVC_User               ; Branch if not SVC 0
+
+                PUSH     {R0,LR}                ; Save PSP and EXC_RETURN
+                LDM      R0,{R0-R3,R12}         ; Load function parameters and address from stack
+                BLX      R12                    ; Call service function
+                POP      {R12,LR}               ; Restore PSP and EXC_RETURN
+                STM      R12,{R0-R1}            ; Store function return values
+
+SVC_Context
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDM      R3,{R1,R2}             ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BXEQ     LR                     ; Exit when threads are the same
+
+#ifdef __FPU_USED
+                CBNZ     R1,SVC_ContextSave     ; Branch if running thread is not deleted
+                TST      LR,#0x10               ; Check if extended stack frame
+                BNE      SVC_ContextSwitch
+                LDR      R1,=0xE000EF34         ; FPCCR Address
+                LDR      R0,[R1]                ; Load FPCCR
+                BIC      R0,#1                  ; Clear LSPACT (Lazy state)
+                STR      R0,[R1]                ; Store FPCCR
+                B        SVC_ContextSwitch
+#else
+                CBZ      R1,SVC_ContextSwitch   ; Branch if running thread is deleted
+#endif
+
+SVC_ContextSave
+#ifdef __DOMAIN_NS
+                LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,SVC_ContextSave1    ; Branch if there is no secure context
+                PUSH     {R1,R2,R3,LR}          ; Save registers and EXC_RETURN
+                BL       TZ_StoreContext_S      ; Store secure context
+                POP      {R1,R2,R3,LR}          ; Restore registers and EXC_RETURN
+#endif
+
+SVC_ContextSave1
+                MRS      R0,PSP                 ; Get PSP
+                STMDB    R0!,{R4-R11}           ; Save R4..R11
+#ifdef __FPU_USED
+                TST      LR,#0x10               ; Check if extended stack frame
+                VSTMDBEQ R0!,{S16-S31}          ;  Save VFP S16.S31
+#endif
+
+SVC_ContextSave2
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                STRB     LR,[R1,#TCB_SF_OFS]    ; Store stack frame information
+
+SVC_ContextSwitch
+                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore
+#ifdef __DOMAIN_NS
+                LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,SVC_ContextRestore1 ; Branch if there is no secure context
+                PUSH     {R2,R3}                ; Save registers
+                BL       TZ_LoadContext_S       ; Load secure context
+                POP      {R2,R3}                ; Restore registers
+#endif
+
+SVC_ContextRestore1
+                LDR      R0,[R2,#TCB_SM_OFS]    ; Load stack memory base
+                LDRB     R1,[R2,#TCB_SF_OFS]    ; Load stack frame information
+                MSR      PSPLIM,R0              ; Set PSPLIM
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ORR      LR,R1,#0xFFFFFF00      ; Set EXC_RETURN
+
+#ifdef __DOMAIN_NS
+                TST      LR,#0x40               ; Check domain of interrupted thread
+                BNE      SVC_ContextRestore2    ; Branch if secure
+#endif
+
+#ifdef __FPU_USED
+                TST      LR,#0x10               ; Check if extended stack frame
+                VLDMIAEQ R0!,{S16-S31}          ;  Restore VFP S16..S31
+#endif
+                LDMIA    R0!,{R4-R11}           ; Restore R4..R11
+
+SVC_ContextRestore2
+                MSR      PSP,R0                 ; Set PSP
+
+SVC_Exit
+                BX       LR                     ; Exit from handler
+
+SVC_User
+                PUSH     {R4,LR}                ; Save registers
+                LDR      R2,=osRtxUserSVC       ; Load address of SVC table
+                LDR      R3,[R2]                ; Load SVC maximum number
+                CMP      R1,R3                  ; Check SVC number range
+                BHI      SVC_Done               ; Branch if out of range
+
+                LDR      R4,[R2,R1,LSL #2]      ; Load address of SVC function
+
+                LDM      R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R4                     ; Call service function
+                MRS      R4,PSP                 ; Get PSP
+                STR      R0,[R4]                ; Store function return value
+
+SVC_Done
+                POP      {R4,PC}                ; Return from handler
+
+
+PendSV_Handler
+                EXPORT   PendSV_Handler
+                IMPORT   osRtxPendSV_Handler
+
+                PUSH     {R4,LR}                ; Save EXC_RETURN
+                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler
+                POP      {R4,LR}                ; Restore EXC_RETURN
+                B        Sys_Context
+
+
+SysTick_Handler
+                EXPORT   SysTick_Handler
+                IMPORT   osRtxTick_Handler
+
+                PUSH     {R4,LR}                ; Save EXC_RETURN
+                BL       osRtxTick_Handler      ; Call osRtxTick_Handler
+                POP      {R4,LR}                ; Restore EXC_RETURN
+                B        Sys_Context
+
+
+Sys_Context
+                EXPORT   Sys_Context
+                IMPORT   osRtxInfo
+#ifdef __DOMAIN_NS
+                IMPORT   TZ_LoadContext_S
+                IMPORT   TZ_StoreContext_S
+#endif
+
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDM      R3,{R1,R2}             ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BXEQ     LR                     ; Exit when threads are the same
+
+Sys_ContextSave
+#ifdef __DOMAIN_NS
+                LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,Sys_ContextSave1    ; Branch if there is no secure context
+                PUSH     {R1,R2,R3,LR}          ; Save registers and EXC_RETURN
+                BL       TZ_StoreContext_S      ; Store secure context
+                POP      {R1,R2,R3,LR}          ; Restore registers and EXC_RETURN
+                TST      LR,#0x40               ; Check domain of interrupted thread
+                MRSNE    R0,PSP                 ; Get PSP
+                BNE      Sys_ContextSave2       ; Branch if secure
+#endif
+
+Sys_ContextSave1
+                MRS      R0,PSP                 ; Get PSP
+                STMDB    R0!,{R4-R11}           ; Save R4..R11
+#ifdef __FPU_USED
+                TST      LR,#0x10               ; Check if extended stack frame
+                VSTMDBEQ R0!,{S16-S31}          ;  Save VFP S16.S31
+#endif
+
+Sys_ContextSave2
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                STRB     LR,[R1,#TCB_SF_OFS]    ; Store stack frame information
+
+Sys_ContextSwitch
+                STR      R2,[R3]                ; osRtxInfo.run: curr = next
+
+Sys_ContextRestore
+#ifdef __DOMAIN_NS
+                LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,Sys_ContextRestore1 ; Branch if there is no secure context
+                PUSH     {R2,R3}                ; Save registers
+                BL       TZ_LoadContext_S       ; Load secure context
+                POP      {R2,R3}                ; Restore registers
+#endif
+
+Sys_ContextRestore1
+                LDR      R0,[R2,#TCB_SM_OFS]    ; Load stack memory base
+                LDRB     R1,[R2,#TCB_SF_OFS]    ; Load stack frame information
+                MSR      PSPLIM,R0              ; Set PSPLIM
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ORR      LR,R1,#0xFFFFFF00      ; Set EXC_RETURN
+
+#ifdef __DOMAIN_NS
+                TST      LR,#0x40               ; Check domain of interrupted thread
+                BNE      Sys_ContextRestore2    ; Branch if secure
+#endif
+
+#ifdef __FPU_USED
+                TST      LR,#0x10               ; Check if extended stack frame
+                VLDMIAEQ R0!,{S16-S31}          ;  Restore VFP S16..S31
+#endif
+                LDMIA    R0!,{R4-R11}           ; Restore R4..R11
+
+Sys_ContextRestore2
+                MSR      PSP,R0                 ; Set PSP
+
+Sys_ContextExit
+                BX       LR                     ; Exit from handler
+
+                END
\ No newline at end of file
diff --git a/rtos/TARGET_CORTEX/rtx5/rtx_kernel.c b/rtos/TARGET_CORTEX/rtx5/rtx_kernel.c
index d9b9a7a7a59..1f9a91f7d14 100644
--- a/rtos/TARGET_CORTEX/rtx5/rtx_kernel.c
+++ b/rtos/TARGET_CORTEX/rtx5/rtx_kernel.c
@@ -607,8 +607,7 @@ void osKernelResume (uint32_t sleep_ticks) {
 /// Get the RTOS kernel tick count.
 uint64_t osKernelGetTickCount (void) {
   if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
-    EvrRtxKernelGetTickCount(0U);
-    return  0U;
+    return svcRtxKernelGetTickCount();
   } else {
     return  __svcKernelGetTickCount();
   }
@@ -617,8 +616,7 @@ uint64_t osKernelGetTickCount (void) {
 /// Get the RTOS kernel tick frequency.
 uint32_t osKernelGetTickFreq (void) {
   if (IS_IRQ_MODE() || IS_IRQ_MASKED()) {
-    EvrRtxKernelGetTickFreq(0U);
-    return  0U;
+    return svcRtxKernelGetTickFreq();
   } else {
     return  __svcKernelGetTickFreq();
   }
diff --git a/rtos/Thread.cpp b/rtos/Thread.cpp
index f01f1b1502d..20c1a083de6 100644
--- a/rtos/Thread.cpp
+++ b/rtos/Thread.cpp
@@ -23,6 +23,15 @@
 
 #include "mbed.h"
 #include "rtos/rtos_idle.h"
+#include "mbed_assert.h"
+
+#define ALIGN_UP(pos, align) ((pos) % (align) ? (pos) +  ((align) - (pos) % (align)) : (pos))
+MBED_STATIC_ASSERT(ALIGN_UP(0, 8) == 0, "ALIGN_UP macro error");
+MBED_STATIC_ASSERT(ALIGN_UP(1, 8) == 8, "ALIGN_UP macro error");
+
+#define ALIGN_DOWN(pos, align) ((pos) - ((pos) % (align)))
+MBED_STATIC_ASSERT(ALIGN_DOWN(7, 8) == 0, "ALIGN_DOWN macro error");
+MBED_STATIC_ASSERT(ALIGN_DOWN(8, 8) == 8, "ALIGN_DOWN macro error");
 
 static void (*terminate_hook)(osThreadId_t id) = 0;
 extern "C" void thread_terminate_hook(osThreadId_t id)
@@ -36,15 +45,21 @@ namespace rtos {
 
 void Thread::constructor(osPriority priority,
         uint32_t stack_size, unsigned char *stack_mem, const char *name) {
+
+    const uintptr_t unaligned_mem = reinterpret_cast<uintptr_t>(stack_mem);
+    const uintptr_t aligned_mem = ALIGN_UP(unaligned_mem, 8);
+    const uint32_t offset = aligned_mem - unaligned_mem;
+    const uint32_t aligned_size = ALIGN_DOWN(stack_size - offset, 8);
+
     _tid = 0;
     _dynamic_stack = (stack_mem == NULL);
     _finished = false;
     memset(&_obj_mem, 0, sizeof(_obj_mem));
     memset(&_attr, 0, sizeof(_attr));
     _attr.priority = priority;
-    _attr.stack_size = stack_size;
+    _attr.stack_size = aligned_size;
     _attr.name = name ? name : "application_unnamed_thread";
-    _attr.stack_mem = (uint32_t*)stack_mem;
+    _attr.stack_mem = reinterpret_cast<uint32_t*>(aligned_mem);
 }
 
 void Thread::constructor(Callback<void()> task,
diff --git a/rtos/Thread.h b/rtos/Thread.h
index 7aa4faa2762..d67ad3acf81 100644
--- a/rtos/Thread.h
+++ b/rtos/Thread.h
@@ -35,6 +35,10 @@
 namespace rtos {
 /** \addtogroup rtos */
 /** @{*/
+/**
+ * \defgroup rtos_Thread Thread class
+ * @{
+ */
 
 /** The Thread class allow defining, creating, and controlling thread functions in the system.
  *
@@ -246,7 +250,7 @@ class Thread : private mbed::NonCopyable<Thread> {
 
     /** Set the specified Thread Flags for the thread.
       @param   signals  specifies the signal flags of the thread that should be set.
-      @return  previous signal flags of the specified thread or osFlagsError in case of incorrect parameters.
+      @return  signal flags after setting or osFlagsError in case of incorrect parameters.
     */
     int32_t signal_set(int32_t signals);
 
@@ -305,7 +309,7 @@ class Thread : private mbed::NonCopyable<Thread> {
 
     /** Clears the specified Thread Flags of the currently running thread.
       @param   signals  specifies the signal flags of the thread that should be cleared.
-      @return  resultant signal flags of the specified thread or osFlagsError in case of incorrect parameters.
+      @return  signal flags before clearing or osFlagsError in case of incorrect parameters.
     */
     static int32_t signal_clr(int32_t signals);
 
@@ -370,8 +374,9 @@ class Thread : private mbed::NonCopyable<Thread> {
     mbed_rtos_storage_thread_t _obj_mem;
     bool                       _finished;
 };
-
+/** @}*/
+/** @}*/
 }
 #endif
 
-/** @}*/
+
diff --git a/rtos/rtos_idle.h b/rtos/rtos_idle.h
index 5fa9fb776c0..c2894c23e30 100644
--- a/rtos/rtos_idle.h
+++ b/rtos/rtos_idle.h
@@ -31,7 +31,17 @@
 extern "C" {
 #endif
 
+/**
+ * \defgroup rtos_Idle Idle hook function
+ * @{
+ */
+/** 
+ @note
+ Sets the hook function called by idle task
+ @param fptr Hook function pointer.
+ */
 void rtos_attach_idle_hook(void (*fptr)(void));
+/** @}*/
 
 #ifdef __cplusplus
 }
@@ -40,3 +50,4 @@ void rtos_attach_idle_hook(void (*fptr)(void));
 #endif
 
 /** @}*/
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/PinNames.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/PinNames.h
new file mode 100755
index 00000000000..032050d1176
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/PinNames.h
@@ -0,0 +1,206 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#include "adi_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+//update
+
+#define GPIO_PORT_SHIFT 12
+
+
+typedef enum {
+    P0_00  = (0 << GPIO_PORT_SHIFT | 0 ),
+    P0_01  = (0 << GPIO_PORT_SHIFT | 1 ),
+    P0_02  = (0 << GPIO_PORT_SHIFT | 2 ),
+    P0_03  = (0 << GPIO_PORT_SHIFT | 3 ),
+    P0_04  = (0 << GPIO_PORT_SHIFT | 4 ),
+    P0_05  = (0 << GPIO_PORT_SHIFT | 5 ),
+    P0_06  = (0 << GPIO_PORT_SHIFT | 6 ),
+    P0_07  = (0 << GPIO_PORT_SHIFT | 7 ),
+    P0_08  = (0 << GPIO_PORT_SHIFT | 8 ),
+    P0_09  = (0 << GPIO_PORT_SHIFT | 9 ),
+    P0_10 = (0 << GPIO_PORT_SHIFT | 10),
+    P0_11 = (0 << GPIO_PORT_SHIFT | 11),
+    P0_12 = (0 << GPIO_PORT_SHIFT | 12),
+    P0_13 = (0 << GPIO_PORT_SHIFT | 13),
+    P0_14 = (0 << GPIO_PORT_SHIFT | 14),
+    P0_15 = (0 << GPIO_PORT_SHIFT | 15),
+    P1_00  = (1 << GPIO_PORT_SHIFT | 0 ),
+    P1_01  = (1 << GPIO_PORT_SHIFT | 1 ),
+    P1_02  = (1 << GPIO_PORT_SHIFT | 2 ),
+    P1_03  = (1 << GPIO_PORT_SHIFT | 3 ),
+    P1_04  = (1 << GPIO_PORT_SHIFT | 4 ),
+    P1_05  = (1 << GPIO_PORT_SHIFT | 5 ),
+    P1_06  = (1 << GPIO_PORT_SHIFT | 6 ),
+    P1_07  = (1 << GPIO_PORT_SHIFT | 7 ),
+    P1_08  = (1 << GPIO_PORT_SHIFT | 8 ),
+    P1_09  = (1 << GPIO_PORT_SHIFT | 9 ),
+    P1_10 = (1 << GPIO_PORT_SHIFT | 10),
+    P1_11 = (1 << GPIO_PORT_SHIFT | 11),
+    P1_12 = (1 << GPIO_PORT_SHIFT | 12),
+    P1_13 = (1 << GPIO_PORT_SHIFT | 13),
+    P1_14 = (1 << GPIO_PORT_SHIFT | 14),
+    P1_15 = (1 << GPIO_PORT_SHIFT | 15),
+    P2_00  = (2 << GPIO_PORT_SHIFT | 0 ),
+    P2_01  = (2 << GPIO_PORT_SHIFT | 1 ),
+    P2_02  = (2 << GPIO_PORT_SHIFT | 2 ),
+    P2_03  = (2 << GPIO_PORT_SHIFT | 3 ),
+    P2_04  = (2 << GPIO_PORT_SHIFT | 4 ),
+    P2_05  = (2 << GPIO_PORT_SHIFT | 5 ),
+    P2_06  = (2 << GPIO_PORT_SHIFT | 6 ),
+    P2_07  = (2 << GPIO_PORT_SHIFT | 7 ),
+    P2_08  = (2 << GPIO_PORT_SHIFT | 8 ),
+    P2_09  = (2 << GPIO_PORT_SHIFT | 9 ),
+    P2_10 = (2 << GPIO_PORT_SHIFT | 10),
+    P2_11 = (2 << GPIO_PORT_SHIFT | 11),
+
+    // USB Pins
+    USBTX = P0_10,
+    USBRX = P0_11,
+    USBTX1 = P1_15,
+    USBRX1 = P2_00,
+
+    // mbed original LED naming
+    LED1 = P2_02,
+    LED2 = P2_10,
+    LED3 = LED2,
+    LED4 = LED1,
+
+    //Push buttons
+    PB0 = P1_00,        // BTN1
+    PB1 = P0_09,        // BTN2
+    BOOT = P1_01,
+    WAKE0 = P0_15,      // JP15 to select
+    WAKE1 = P1_00,      // JP8 (BTN1 jumper) to select
+    WAKE2 = P0_13,      // JP4 to select
+    WAKE3 = P2_01,      // JP15 to select
+
+    // SPI Pins
+    SPI0_SCLK = P0_00,
+    SPI0_MOSI = P0_01,
+    SPI0_MISO = P0_02,
+    SPI0_CS0 = P0_03,
+    SPI0_CS1 = P1_10,
+    SPI0_CS2 = P2_08,
+    SPI0_CS3 = P2_09,
+
+    SPI1_SCLK = P1_06,
+    SPI1_MOSI = P1_07,
+    SPI1_MISO = P1_08,
+    SPI1_CS0 = P1_09,
+    SPI1_CS1 = P2_11,
+    SPI1_CS2 = P2_02,
+    SPI1_CS3 = P1_10,
+
+    SPI2_SCLK = P1_02,
+    SPI2_MOSI = P1_03,
+    SPI2_MISO = P1_04,
+    SPI2_CS0 = P1_05,
+    SPI2_CS1 = P0_09,
+    SPI2_CS2 = P2_10,
+    SPI2_CS3 = P2_07,
+
+    // ADC Pins
+    ADC_VIN0 = P2_03,
+    ADC_VIN1 = P2_04,
+    ADC_VIN2 = P2_05,
+    ADC_VIN3 = P2_06,
+    ADC_VIN4 = P2_07,
+    ADC_VIN5 = P2_08,
+    ADC_VIN6 = P2_09,
+    ADC_VIN7 = P2_10,
+
+    // Arduino Headers
+    D0 = P0_10,        // UART0_TXD
+    D1 = P0_11,        // UART0_RXD
+    D2 = P0_15,        // INT_WAKE0
+    D3 = P0_13,        // EXT_INT_WAKE2
+    D4 = P0_09,        // EXT_SPI2_CS1
+    D5 = P2_01,        // INT_WAKE3 or EXT_RTC1_SS1 via JP8
+    D6 = P1_11,        // GPIO_27
+    D7 = P0_12,        // GPIO_08 or GPIO_12 via JP7
+
+    D8 = P1_12,         // GPIO_28
+    D9 = P1_14,         // GPIO_30
+    D10 = SPI0_CS2,     // P2_08
+    D11 = SPI0_MOSI,    // P0_01
+    D12 = SPI0_MISO,    // P0_02
+    D13 = SPI0_SCLK,    // P0_00
+    I2C_SCL = P0_04,    // I2C_SCL
+    I2C_SDA = P0_05,    // I2C_SDA
+
+    A0 = P2_03,         // ADC0
+    A1 = P2_04,         // EXT_ADC1
+    A2 = P2_05,         // EXT_ADC2
+    A3 = P2_06,         // ADC3
+    A4 = P2_07,         // SPI2_CS3/ADC_VIN4
+    A5 = P2_10,         // EXT_GPIO42/ADC_VIN7
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+
+typedef enum {
+    PullNone = 0,
+    PullDown = 1,
+    PullUp   = 2,
+    PullDefault = PullNone
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.c
new file mode 100755
index 00000000000..7593a5ae04e
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.c
@@ -0,0 +1,272 @@
+/*!
+ *****************************************************************************
+ * @file:    startup_ADuCM3029.c
+ * @brief:   Interrupt table and default handlers for ADuCM302x
+ * @version: $Revision: $
+ * @date:    $Date: $
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2010-2017 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+#include <stdint.h>
+#ifdef __ARMCC_VERSION
+#include <rt_misc.h>
+#endif
+#include <cmsis.h>
+#include <startup_ADuCM3029.h>
+#include <mbed_rtx.h>
+
+
+/*----------------------------------------------------------------------------
+  External function Declaration
+ *----------------------------------------------------------------------------*/
+extern void SramInit(void);
+
+/*----------------------------------------------------------------------------
+  Checksum options
+ *----------------------------------------------------------------------------*/
+#if defined (__ARMCC_VERSION)
+__attribute__((section(".ARM.__at_0x000001A0")))
+#elif defined( __ICCARM__)
+__root
+#endif /* __ICCARM__ */
+const uint32_t SECTION_PLACE(blank_checksum[],".checksum") =
+{
+    BLANKX60,BLANKX600
+};
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+WEAK_FUNCTION( NMI_Handler                 )
+WEAK_FUNCTION( HardFault_Handler           )
+WEAK_FUNCTION( MemManage_Handler           )
+WEAK_FUNCTION( BusFault_Handler            )
+WEAK_FUNCTION( UsageFault_Handler          )
+WEAK_FUNCTION( SVC_Handler                 )
+WEAK_FUNCTION( DebugMon_Handler            )
+WEAK_FUNCTION( PendSV_Handler              )
+WEAK_FUNCTION( SysTick_Handler             )
+WEAK_FUNCTION( RTC1_Int_Handler            )
+WEAK_FUNCTION( Ext_Int0_Handler            )
+WEAK_FUNCTION( Ext_Int1_Handler            )
+WEAK_FUNCTION( Ext_Int2_Handler            )
+WEAK_FUNCTION( Ext_Int3_Handler            )
+WEAK_FUNCTION( WDog_Tmr_Int_Handler        )
+WEAK_FUNCTION( Vreg_over_Int_Handler       )
+WEAK_FUNCTION( Battery_Voltage_Int_Handler )
+WEAK_FUNCTION( RTC0_Int_Handler            )
+WEAK_FUNCTION( GPIO_A_Int_Handler          )
+WEAK_FUNCTION( GPIO_B_Int_Handler          )
+WEAK_FUNCTION( GP_Tmr0_Int_Handler         )
+WEAK_FUNCTION( GP_Tmr1_Int_Handler         )
+WEAK_FUNCTION( Flash0_Int_Handler          )
+WEAK_FUNCTION( UART_Int_Handler            )
+WEAK_FUNCTION( SPI0_Int_Handler            )
+WEAK_FUNCTION( SPI2_Int_Handler            )
+WEAK_FUNCTION( I2C0_Slave_Int_Handler      )
+WEAK_FUNCTION( I2C0_Master_Int_Handler     )
+WEAK_FUNCTION( DMA_Err_Int_Handler         )
+WEAK_FUNCTION( DMA_SPI2_TX_Int_Handler     )
+WEAK_FUNCTION( DMA_SPI2_RX_Int_Handler     )
+WEAK_FUNCTION( DMA_SPORT0A_Int_Handler     )
+WEAK_FUNCTION( DMA_SPORT0B_Int_Handler     )
+WEAK_FUNCTION( DMA_SPI0_TX_Int_Handler     )
+WEAK_FUNCTION( DMA_SPI0_RX_Int_Handler     )
+WEAK_FUNCTION( DMA_SPI1_TX_Int_Handler     )
+WEAK_FUNCTION( DMA_SPI1_RX_Int_Handler     )
+WEAK_FUNCTION( DMA_UART_TX_Int_Handler     )
+WEAK_FUNCTION( DMA_UART_RX_Int_Handler     )
+WEAK_FUNCTION( DMA_I2C0_STX_Int_Handler    )
+WEAK_FUNCTION( DMA_I2C0_SRX_Int_Handler    )
+WEAK_FUNCTION( DMA_I2C0_MX_Int_Handler     )
+WEAK_FUNCTION( DMA_AES0_IN_Int_Handler     )
+WEAK_FUNCTION( DMA_AES0_OUT_Int_Handler    )
+WEAK_FUNCTION( DMA_FLASH0_Int_Handler      )
+WEAK_FUNCTION( SPORT0A_Int_Handler         )
+WEAK_FUNCTION( SPORT0B_Int_Handler         )
+WEAK_FUNCTION( Crypto_Int_Handler          )
+WEAK_FUNCTION( DMA_ADC0_Int_Handler        )
+WEAK_FUNCTION( GP_Tmr2_Int_Handler         )
+WEAK_FUNCTION( Crystal_osc_Int_Handler     )
+WEAK_FUNCTION( SPI1_Int_Handler            )
+WEAK_FUNCTION( PLL_Int_Handler             )
+WEAK_FUNCTION( RNG_Int_Handler             )
+WEAK_FUNCTION( Beep_Int_Handler            )
+WEAK_FUNCTION( ADC_Int_Handler             )
+WEAK_FUNCTION( DMA_SIP0_Int_Handler        )
+WEAK_FUNCTION( DMA_SIP1_Int_Handler        )
+WEAK_FUNCTION( DMA_SIP2_Int_Handler        )
+WEAK_FUNCTION( DMA_SIP3_Int_Handler        )
+WEAK_FUNCTION( DMA_SIP4_Int_Handler        )
+WEAK_FUNCTION( DMA_SIP5_Int_Handler        )
+WEAK_FUNCTION( DMA_SIP6_Int_Handler        )
+WEAK_FUNCTION( DMA_SIP7_Int_Handler        )
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+const pFunc SECTION_PLACE(IVT_NAME[104],VECTOR_SECTION) =
+{
+    (pFunc) INITIAL_SP,    /* Initial Stack Pointer */
+    ADUCM3029_VECTORS
+};
+
+/*----------------------------------------------------------------------------
+* Initialize .bss and .data for GNU
+*----------------------------------------------------------------------------*/
+#if defined( __GNUC__) && !defined (__ARMCC_VERSION)
+void zero_bss(void)
+{
+    uint32_t *pSrc, *pDest;
+    uint32_t *pTable __attribute__((unused));
+#ifdef __STARTUP_COPY_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of triplets, each of which specify:
+ *    offset 0: LMA of start of a section to copy from
+ *    offset 4: VMA of start of a section to copy to
+ *    offset 8: size of the section to copy. Must be multiply of 4
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    pTable = &__copy_table_start__;
+
+    for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
+        pSrc  = (uint32_t*)*(pTable + 0);
+        pDest = (uint32_t*)*(pTable + 1);
+        for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+      *pDest++ = *pSrc++;
+        }
+    }
+#else
+/*  Single section scheme.
+ *
+ *  The ranges of copy from/to are specified by following symbols
+ *    __etext: LMA of start of the section to copy from. Usually end of text
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    pSrc  = (uint32_t*)(&__etext);
+    pDest = (uint32_t*)(&__data_start__);
+
+    for ( ; pDest < (uint32_t*)(&__data_end__) ; ) {
+        *pDest++ = *pSrc++;
+    }
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/*  This part of work usually is done in C library startup code. Otherwise,
+ *  define this macro to enable it in this startup.
+ *
+ *  There are two schemes too. One can clear multiple BSS sections. Another
+ *  can only clear one section. The former is more size expensive than the
+ *  latter.
+ *
+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of tuples specifying:
+ *    offset 0: Start of a BSS section
+ *    offset 4: Size of this BSS section. Must be multiply of 4
+ */
+    pTable = (uint32_t*)(&__zero_table_start__);
+
+    for (; pTable < (uint32_t*)(&__zero_table_end__); pTable = pTable + 2) {
+        pDest = (uint32_t*)*(pTable + 0);
+        for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+            *pDest++ = 0;
+        }
+    }
+#elif defined (__STARTUP_CLEAR_BSS)
+/*  Single BSS section scheme.
+ *
+ *  The BSS section is specified by following symbols
+ *    __bss_start__: start of the BSS section.
+ *    __bss_end__: end of the BSS section.
+ *
+ *  Both addresses must be aligned to 4 bytes boundary.
+ */
+    pDest = &__bss_start__;
+
+    for ( ; pDest < &__bss_end__ ; ) {
+        *pDest++ = 0ul;
+    }
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+}
+#endif
+
+/*----------------------------------------------------------------------------
+* Function    : Reset_Handler (-15)
+* Description : Reset event handler
+*----------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+    /* Configure the SRAM first. This is done first because the bss section
+       may reside in DSRAM bank B. */
+    SramInit();
+
+#if defined(__GNUC__) && !defined (__ARMCC_VERSION)
+    /* Clear the bss section for GCC build only */
+    zero_bss();
+#endif
+
+    /* initialize system */
+    SystemInit();
+
+    /* branch to other initialization routines before main */
+    RESET_EXCPT_HNDLR();
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+#if defined(__ARMCC_VERSION) || defined (__GNUC__)
+void Default_Handler(void)
+{
+    while(1);
+}
+#endif
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.h
new file mode 100755
index 00000000000..768bae88f92
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.h
@@ -0,0 +1,208 @@
+/*!
+*****************************************************************************
+ * @file:    startup_ADuCM3029.h
+ * @brief:   CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
+ *           ADI ADuCxxx Device Series
+ * @version: $Revision: $
+ * @date:    $Date: $
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2010-2017 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/*
+WEAK_FUNC(func)
+   If this is available for a compiler, apply whatever attributes are needed
+   to a function definition ("func") to flag that the function is a "weak" one.
+VECTOR_SECTION
+   A particular setup may have a requirement that the vector table be placed
+   in a particular section. This specifies the name of that section
+RESET_EXCPT_HNDLR
+   A particular setup may have a requirement for a different reset handler.
+   This specifies the name of that handler.
+*/
+
+#ifndef __STARTUP_H__
+#define __STARTUP_H__
+
+#define VECTOR_SECTION                 ".vectors"
+
+#ifdef __ARMCC_VERSION
+void Default_Handler(void);
+#define SECTION_NAME(sectionname)      __attribute__((section(sectionname)))
+#define SECTION_PLACE(def,sectionname) def __attribute__((section(sectionname)))
+#define IVT_NAME                       __Vectors
+#define RESET_EXCPT_HNDLR              __main
+#define COMPILER_NAME                  "ARMCC"
+#define WEAK_FUNCTION(x)               void x (void) __attribute__((weak, alias("Default_Handler")));
+
+#elif defined(__ICCARM__)
+#pragma diag_suppress=Pm093,Pm140
+#define SECTION_PLACE(def,sectionname) def @ sectionname
+#define IVT_NAME                       __vector_table
+#define WEAK_FUNC(func)                __weak func
+#define RESET_EXCPT_HNDLR              __iar_program_start
+#define COMPILER_NAME                  "ICCARM"
+#define WEAK_FUNCTION(x)    WEAK_FUNC  ( void x (void)) { while(1){} }
+
+#elif defined(__GNUC__)
+extern unsigned __etext;
+extern unsigned __data_start__;
+extern unsigned __data_end__;
+extern unsigned __copy_table_start__;
+extern unsigned __copy_table_end__;
+extern unsigned __zero_table_start__;
+extern unsigned __zero_table_end__;
+extern unsigned __bss_start__;
+extern unsigned __bss_end__;
+extern unsigned __StackTop;
+void Default_Handler(void);
+#ifndef __START
+extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
+#define RESET_EXCPT_HNDLR              _start
+#else
+extern int  __START(void) __attribute__((noreturn));    /* main entry point */
+#define RESET_EXCPT_HNDLR              __START
+#endif
+#define SECTION_NAME(sectionname)      __attribute__ ((section(sectionname)))
+#define SECTION_PLACE(def,sectionname) def __attribute__ ((section(sectionname)))
+#define IVT_NAME                       __Vectors
+#define COMPILER_NAME                  "GNUC"
+#define WEAK_FUNCTION(x)               void x (void) __attribute__ ((weak, alias("Default_Handler")));
+#define __STARTUP_CLEAR_BSS_MULTIPLE
+#endif // __GNUC__
+#define LASTCRCPAGE                    0
+#define BLANKX4   0xFFFFFFFF
+#define BLANKX20  BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4
+#define BLANKX100 BLANKX20,BLANKX20,BLANKX20,BLANKX20,BLANKX20,BLANKX20,BLANKX20,BLANKX20
+#define BLANKX600 BLANKX100,BLANKX100,BLANKX100,BLANKX100,BLANKX100,BLANKX100
+#define BLANKX60  BLANKX20,BLANKX20,BLANKX20
+void RESET_EXCPT_HNDLR(void);
+void Reset_Handler(void);
+/* IVT typedefs. */
+typedef void( *pFunc )( void );
+
+#define ADUCM3029_VECTORS           /* Cortex-M3 Exceptions Handler */ \
+    Reset_Handler,                            /* -15 */                \
+    NMI_Handler,                              /* -14 */                \
+    HardFault_Handler,                        /* -13 */                \
+    MemManage_Handler,                        /* -12 */                \
+    BusFault_Handler,                         /* -11 */                \
+    UsageFault_Handler,                       /* -10 */                \
+    0,                                        /* -9  */                \
+    0,                                        /* -8  */                \
+    0,                                        /* -7  */                \
+    0,                                        /* -6  */                \
+    SVC_Handler,                              /* -5  */                \
+    DebugMon_Handler,                         /* -4  */                \
+    0,                                        /* -3  */                \
+    PendSV_Handler,                           /* -2  */                \
+    SysTick_Handler,                          /* -1  */                \
+    /* External interrupts */                                          \
+    RTC1_Int_Handler,                         /* 0  */                 \
+    Ext_Int0_Handler,                         /* 1  */                 \
+    Ext_Int1_Handler,                         /* 2  */                 \
+    Ext_Int2_Handler,                         /* 3  */                 \
+    Ext_Int3_Handler,                         /* 4  */                 \
+    WDog_Tmr_Int_Handler,                     /* 5  */                 \
+    Vreg_over_Int_Handler,                    /* 6  */                 \
+    Battery_Voltage_Int_Handler,              /* 7  */                 \
+    RTC0_Int_Handler,                         /* 8  */                 \
+    GPIO_A_Int_Handler,                       /* 9  */                 \
+    GPIO_B_Int_Handler,                       /* 10 */                 \
+    GP_Tmr0_Int_Handler,                      /* 11 */                 \
+    GP_Tmr1_Int_Handler,                      /* 12 */                 \
+    Flash0_Int_Handler,                       /* 13 */                 \
+    UART_Int_Handler,                         /* 14 */                 \
+    SPI0_Int_Handler,                         /* 15 */                 \
+    SPI2_Int_Handler,                         /* 16 */                 \
+    I2C0_Slave_Int_Handler,                   /* 17 */                 \
+    I2C0_Master_Int_Handler,                  /* 18 */                 \
+    DMA_Err_Int_Handler,                      /* 19 */                 \
+    DMA_SPI2_TX_Int_Handler,                  /* 20 */                 \
+    DMA_SPI2_RX_Int_Handler,                  /* 21 */                 \
+    DMA_SPORT0A_Int_Handler,                  /* 22 */                 \
+    DMA_SPORT0B_Int_Handler,                  /* 23 */                 \
+    DMA_SPI0_TX_Int_Handler,                  /* 24 */                 \
+    DMA_SPI0_RX_Int_Handler,                  /* 25 */                 \
+    DMA_SPI1_TX_Int_Handler,                  /* 26 */                 \
+    DMA_SPI1_RX_Int_Handler,                  /* 27 */                 \
+    DMA_UART_TX_Int_Handler,                  /* 28 */                 \
+    DMA_UART_RX_Int_Handler,                  /* 29 */                 \
+    DMA_I2C0_STX_Int_Handler,                 /* 30 */                 \
+    DMA_I2C0_SRX_Int_Handler,                 /* 31 */                 \
+    DMA_I2C0_MX_Int_Handler,                  /* 32 */                 \
+    DMA_AES0_IN_Int_Handler,                  /* 33 */                 \
+    DMA_AES0_OUT_Int_Handler,                 /* 34 */                 \
+    DMA_FLASH0_Int_Handler,                   /* 35 */                 \
+    SPORT0A_Int_Handler,                      /* 36 */                 \
+    SPORT0B_Int_Handler,                      /* 37 */                 \
+    Crypto_Int_Handler,                       /* 38 */                 \
+    DMA_ADC0_Int_Handler,                     /* 39 */                 \
+    GP_Tmr2_Int_Handler,                      /* 40 */                 \
+    Crystal_osc_Int_Handler,                  /* 41 */                 \
+    SPI1_Int_Handler,                         /* 42 */                 \
+    PLL_Int_Handler,                          /* 43 */                 \
+    RNG_Int_Handler,                          /* 44 */                 \
+    Beep_Int_Handler,                         /* 45 */                 \
+    ADC_Int_Handler,                          /* 46 */                 \
+    0,                                        /* 47 */                 \
+    0,                                        /* 48 */                 \
+    0,                                        /* 49 */                 \
+    0,                                        /* 50 */                 \
+    0,                                        /* 51 */                 \
+    0,                                        /* 52 */                 \
+    0,                                        /* 53 */                 \
+    0,                                        /* 54 */                 \
+    0,                                        /* 55 */                 \
+    DMA_SIP0_Int_Handler,                     /* 56 */                 \
+    DMA_SIP1_Int_Handler,                     /* 57 */                 \
+    DMA_SIP2_Int_Handler,                     /* 58 */                 \
+    DMA_SIP3_Int_Handler,                     /* 59 */                 \
+    DMA_SIP4_Int_Handler,                     /* 60 */                 \
+    DMA_SIP5_Int_Handler,                     /* 61 */                 \
+    DMA_SIP6_Int_Handler,                     /* 62 */                 \
+    DMA_SIP7_Int_Handler,                     /* 63 */                 \
+    0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,          /* 64 - 79 */            \
+    (pFunc)BLANKX4, (pFunc)BLANKX4,           /* security_options */   \
+    (pFunc)BLANKX4, (pFunc)BLANKX4,                                    \
+    (pFunc)0xA79C3203u, (pFunc)LASTCRCPAGE,                            \
+    (pFunc)BLANKX4, (pFunc)BLANKX4            /* 80 - 87 */
+
+#endif /* __STARTUP_H__ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/system_ADuCM3029.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/system_ADuCM3029.c
new file mode 100755
index 00000000000..0bfbdfc5eb4
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/system_ADuCM3029.c
@@ -0,0 +1,286 @@
+/******************************************************************************
+ * @file     system_ADuCM3029.c
+ * @brief    CMSIS Cortex-M3 Device Peripheral Access Layer Source File for
+ *           Device ADuCM3029
+ * @version  V3.10
+ * @date     23. November 2012
+ *
+ ******************************************************************************/
+/* Copyright (c) 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+
+   Portions Copyright (c) 2016 - 2017 Analog Devices, Inc.
+   ---------------------------------------------------------------------------*/
+#include <cmsis.h>
+#include <adi_pwr.h>
+#include <adi_gpio.h>
+#include <startup_ADuCM3029.h>
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#ifdef ADI_DEBUG
+/* only needed in debug mode */
+uint32_t lfClock = 0u;    /* "lf_clk" coming out of LF mux             */
+#endif
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/* Note that these variables will be re-initialized to the value set here by the
+   LIBC startup code, so if other clock values are required, make sure set them
+   here.
+*/
+uint32_t hfClock = __HFOSC;         /* "root_clk" output of HF mux              */
+uint32_t gpioClock = 0;             /* external GPIO clock                      */
+uint32_t SystemCoreClock = __HFOSC; /*!< System Clock Frequency (Core Clock)    */
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+
+/*!
+ * Update the clock.
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the variable SystemCoreClock and must be called whenever
+ *         the core clock is changed during program execution.
+ */
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+    uint32_t    val;
+    uint16_t    div2;
+    float       mul2, nDivisor, nMulfactor;
+
+#ifdef ADI_DEBUG
+    /* "lfclock" is only used during debug checks... */
+    /* LF clock is always 32k, whether osc or xtal */
+    lfClock = __LFCLK;  /* for beep, wdt and lcd */
+    if( lfClock == 0 )
+    {
+      while( 1 );
+    }
+#endif
+
+    /* Update Core Clock sources */
+    /* update the HF clock */
+    switch( pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_CLKMUX ) {
+
+        case HFMUX_INTERNAL_OSC_VAL:
+          hfClock = __HFOSC;
+          break;
+
+        case HFMUX_EXTERNAL_XTAL_VAL:
+          hfClock = __HFXTAL;
+          break;
+
+        case HFMUX_SYSTEM_SPLL_VAL:
+            /* Calculate System PLL output frequency */
+            if( pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_SPLLIPSEL )
+            {
+                /* PLL input from HFXTAL */
+                val = __HFXTAL;
+            }
+            else
+            {
+                /* PLL input from HFOSC */
+                val = __HFOSC;
+            }
+
+            /* PLL NSEL multiplier */
+            nMulfactor = ( ( pADI_CLKG0_CLK->CTL3 &BITM_CLKG_CLK_CTL3_SPLLNSEL ) >> BITP_CLKG_CLK_CTL3_SPLLNSEL );
+
+            /* PLL MSEL divider */
+            nDivisor = ( ( pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLMSEL ) >> BITP_CLKG_CLK_CTL3_SPLLMSEL );
+
+            /* PLL NSEL multiplier */
+            div2 = ( ( pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLDIV2 ) >> BITP_CLKG_CLK_CTL3_SPLLDIV2 );
+
+            /* PLL MSEL divider */
+            mul2 = ( ( pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLMUL2 ) >> BITP_CLKG_CLK_CTL3_SPLLMUL2 );
+
+            val = ( ( (uint32_t)( ( nMulfactor * ( mul2 + 1.0 ) * (float) val ) / nDivisor ) ) >> div2 );
+
+            hfClock = val;
+            break;
+
+        case HFMUX_GPIO_VAL:
+          hfClock = gpioClock;
+          break;
+
+        default:
+          return;
+    } /* end switch */
+
+    SystemCoreClock = hfClock;
+}
+
+
+/*!
+ * Configure the SRAM banks
+ *
+ * @return none
+ *
+ * @brief  Setup the SRAM banks.
+ *         Initialize the SRAM configuration and retention.
+ */
+void SramInit(void)
+{
+    /* SRAM Bank1 and Banck2 are hibernate-preserved */
+    adi_system_EnableRetention(ADI_SRAM_BANK_1, true);
+    adi_system_EnableRetention(ADI_SRAM_BANK_2, true);
+    /* To disable the instruction SRAM and entire 64K of SRAM is used as DSRAM */
+    adi_system_EnableISRAM(false);
+    /* To disable the instruction cache  */
+    adi_system_EnableCache(false);
+}
+
+
+/*!
+ * Initialize the system
+ *
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the relocate vector table.
+ */
+void SystemInit (void)
+{
+    uint32_t IntStatus;
+
+    /* Turn off Tile 3029 LED */
+    pADI_GPIO1->OEN |= ADI_GPIO_PIN_10;
+    pADI_GPIO2->OEN |= ADI_GPIO_PIN_2;
+    pADI_GPIO1->SET  = ADI_GPIO_PIN_10;
+    pADI_GPIO2->SET  = ADI_GPIO_PIN_2;
+
+    IntStatus = __get_PRIMASK();
+    __disable_irq();
+
+    /* Set boot ROM IVT. */
+    SCB->VTOR = (uint32_t)NVIC_FLASH_VECTOR_ADDRESS;
+
+    /* Set all three (USGFAULTENA, BUSFAULTENA, and MEMFAULTENA) fault enable bits
+     * in the System Control Block, System Handler Control and State Register
+     * otherwise these faults are handled as hard faults.
+     */
+    SCB->SHCSR = SCB_SHCSR_USGFAULTENA_Msk |
+                 SCB_SHCSR_BUSFAULTENA_Msk |
+                 SCB_SHCSR_MEMFAULTENA_Msk ;
+    adi_pwr_Init();
+    adi_pwr_SetClockDivider(ADI_CLOCK_HCLK,1);
+    adi_pwr_SetClockDivider(ADI_CLOCK_PCLK,1);
+
+    /* Set up the LF clock source */
+    adi_pwr_SetLFClockMux(ADI_CLOCK_MUX_LFCLK_LFXTAL);
+    adi_pwr_EnableClockSource(ADI_CLOCK_SOURCE_LFXTAL,true);
+
+    __set_PRIMASK(IntStatus);
+}
+
+/*!
+ * @brief  This enables or disables  the cache.
+ * \n @param  bEnable : To specify whether to enable/disable cache.
+ * \n              true : To enable cache.
+ * \n
+ * \n              false : To disable cache.
+ * \n
+ * @return none
+ *
+ */
+void adi_system_EnableCache(bool bEnable)
+{
+    pADI_FLCC0_CACHE->KEY = CACHE_CONTROLLER_KEY;
+    if(bEnable)
+    {
+        pADI_FLCC0_CACHE->SETUP |= BITM_FLCC_CACHE_SETUP_ICEN;
+    }
+    else
+    {
+        pADI_FLCC0_CACHE->SETUP &= ~BITM_FLCC_CACHE_SETUP_ICEN;
+    }
+}
+
+/*!
+ * @brief  This enables or disables instruction SRAM
+ *
+ * @param bEnable: To enable/disable the instruction SRAM.
+ * \n              true : To enable cache.
+ * \n
+ * \n              false : To disable cache.
+ * \n
+ * @return none
+ * @note:  Please note that respective linker file need to support the configuration.
+ */
+void adi_system_EnableISRAM(bool bEnable)
+{
+
+    if(bEnable)
+    {
+        pADI_PMG0_TST->SRAM_CTL |= BITM_PMG_TST_SRAM_CTL_INSTREN;
+    }
+    else
+    {
+        pADI_PMG0_TST->SRAM_CTL &= ~BITM_PMG_TST_SRAM_CTL_INSTREN;
+    }
+}
+
+/*!
+ * @brief  This enables/disable SRAM retention during the hibernation.
+ * @param eBank:   Specify which SRAM bank. Only BANK1 and BANK2 are valid.
+ * @param bEnable: To enable/disable the  retention for specified  SRAM bank.
+ * \n              true : To enable retention during the hibernation.
+ * \n
+ * \n              false :To disable retention during the hibernation.
+ * \n
+ * @return : SUCCESS : Configured successfully.
+ *           FAILURE :  For invalid bank.
+ * @note: Please note that respective linker file need to support the configuration. Only BANK-1 and
+          BANK-2 of SRAM is valid.
+ */
+uint32_t adi_system_EnableRetention(ADI_SRAM_BANK eBank,bool bEnable)
+{
+#ifdef ADI_DEBUG
+    if((eBank != ADI_SRAM_BANK_1) && (eBank != ADI_SRAM_BANK_2))
+    {
+        return FAILURE;
+    }
+#endif
+    pADI_PMG0->PWRKEY = PWRKEY_VALUE_KEY;
+    if(bEnable)
+    {
+        pADI_PMG0->SRAMRET |= (uint32_t)eBank>>1;
+    }
+    else
+    {
+        pADI_PMG0->SRAMRET &= ~((uint32_t)eBank >> 1);
+    }
+
+    return SUCCESS;
+}
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_ARM_STD/ADuCM3029.sct b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_ARM_STD/ADuCM3029.sct
new file mode 100755
index 00000000000..f7087cac097
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_ARM_STD/ADuCM3029.sct
@@ -0,0 +1,65 @@
+;******************************************************************************
+;  File: ADuCM3029.sct
+;  Scatter loading file for Analog Devices ADuCM3029 processor
+;
+;  Copyright (c) 2011 - 2014 ARM LIMITED
+;  Copyright (c) 2016 - 2017 Analog Devices, Inc.
+;
+;  All rights reserved.
+;  Redistribution and use in source and binary forms, with or without
+;  modification, are permitted provided that the following conditions are met:
+;  - Redistributions of source code must retain the above copyright
+;    notice, this list of conditions and the following disclaimer.
+;  - Redistributions in binary form must reproduce the above copyright
+;    notice, this list of conditions and the following disclaimer in the
+;    documentation and/or other materials provided with the distribution.
+;  - Neither the name of ARM nor the names of its contributors may be used
+;    to endorse or promote products derived from this software without
+;    specific prior written permission.
+;
+;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+;  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;  POSSIBILITY OF SUCH DAMAGE.
+;
+;  Portions Copyright (c) 2017 Analog Devices, Inc.
+;
+;******************************************************************************
+
+LR_IROM1 0x00000000 0x00040000 {
+    ADUCM_IROM1 0x00000000 0x00040000 {  ; romflash start address
+        *(.vectors, +First)
+        *(.checksum)
+        *(InRoot$$Sections)
+        .ANY (+RO)
+    }
+
+    RW_IRAM1 0x20000200 { ; data section
+        .ANY (+RW)
+    }
+
+    ADUCM_HEAP AlignExpr(+0, 16) EMPTY
+        (0x20003000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; heap
+    }
+
+    ADUCM_STACK AlignExpr(+0, 16) EMPTY 0x1000 { ; stack
+    }
+
+    ADUCM_IRAM2 0x20004000 0x4000 { ; bss section
+        .ANY (+RW +ZI)
+    }
+
+    ADUCM_IRAM3 0x20040000 0x8000 { ; non-retainable memory region
+         .ANY (+RW +ZI)
+    }
+}
+
+ScatterAssert(ImageLimit(RW_IRAM1)    <= 0x20002000)
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_GCC_ARM/ADuCM3029.ld b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_GCC_ARM/ADuCM3029.ld
new file mode 100755
index 00000000000..23208ce7cd7
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_GCC_ARM/ADuCM3029.ld
@@ -0,0 +1,225 @@
+/*
+ * Portions Copyright (c) 2016 - 2017 Analog Devices, Inc.
+ *
+ * Based on Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld file in
+ * ARM.CMSIS.4.5.0.pack.
+ */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  /* Flash bank0 */
+  FLASH0 (rx) : ORIGIN = 0x00000000, LENGTH = 0x800
+  /* Flash bank0 - bank127*/
+  FLASH (rx) : ORIGIN = 0x00000800, LENGTH = 256k - 0x800
+  /* SRAM bank 0+1 */
+  DSRAM_V (rwx) : ORIGIN = 0x20000000, LENGTH = 0x200
+  DSRAM_A (rwx) : ORIGIN = 0x20000200, LENGTH = 16k - 0x200
+  DSRAM_C (rwx) : ORIGIN = 0x20004000, LENGTH = 16k
+  /* SRAM bank 3 */
+  DSRAM_B (rwx) : ORIGIN = 0x20040000, LENGTH = 32k
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+/* Custom stack and heap sizes */
+__stack_size__ = 0x1000;
+__heap_size__ = 0x2000;
+
+/* select custom or default sizes for stack and heap */
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0C00;
+
+/* Linker script to place sections and symbol values.
+ * It references the following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines the following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .vectors :
+    {
+        KEEP(*(.vectors))
+        __Vectors_End = .;
+        __Vectors_Size = __Vectors_End - __Vectors;
+        __end__ = .;
+        KEEP(*(.checksum))
+    } > FLASH0
+
+    .text :
+    {
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (__etext2)
+        LONG (__data2_start__)
+        LONG (__data2_end__ - __data2_start__)
+        __copy_table_end__ = .;
+    } > FLASH
+    */
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (__bss2_start__)
+        LONG (__bss2_end__ - __bss2_start__)
+        __zero_table_end__ = .;
+    } > FLASH
+
+
+    __etext = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > DSRAM_A
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        KEEP(*(.bss.gChannelControlDataArray))
+        KEEP(*(.bss.thread_stack_main))
+        KEEP(*(.bss.UartDeviceMem))
+        KEEP(*(.bss.os_thread_def_stack_event_loop_thread))
+        *(COMMON)
+        *(.bss)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > DSRAM_C
+
+    .bss2 :
+    {
+        . = ALIGN(4);
+        __bss2_start__ = .;
+        *(.bss*)
+        . = ALIGN(4);
+        __bss2_end__ = .;
+    } > DSRAM_B
+
+    .heap (COPY):
+    {
+        __HeapBase = .;
+        __end__ = .;
+        end = __end__;
+        . += HEAP_SIZE;
+        __HeapLimit = .;
+    } > DSRAM_A
+
+    /* Set stack top to end of DSRAM_A, and move stack limit down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(DSRAM_C);
+    __StackLimit = __StackTop - STACK_SIZE;
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds DSRAM_A limit when they are both in DSRAM_A
+    ASSERT(__StackLimit >= __HeapLimit, "region DSRAM_A overflowed with stack") */
+}
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_IAR/ADuCM3029.icf b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_IAR/ADuCM3029.icf
new file mode 100755
index 00000000000..8c15cd0b5c3
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_IAR/ADuCM3029.icf
@@ -0,0 +1,49 @@
+/******************************************************************************
+*  File: ADuCM3029.icf
+*  ILINK Configuration File for Analog Devices ADuCM3029 processor
+*
+*  Copyright (c) 2011 - 2014 ARM LIMITED
+*  Copyright (c) 2016 - 2017 Analog Devices, Inc.
+*
+*  All rights reserved.
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions are met:
+*  - Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*  - Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the distribution.
+*  - Neither the name of ARM nor the names of its contributors may be used
+*    to endorse or promote products derived from this software without
+*    specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+*  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+*  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+*  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+*  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+*  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+*  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+*  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+*  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+*  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+*  POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************/
+define memory mem with size               = 4G;
+define region ROM_PAGE0_INTVEC            = mem:[from 0x00000000 size 0x000001A0];
+define region ROM_PAGE0_CHECKSUM          = mem:[from 0x000001A0 size 0x00000660];
+define region ROM_REGION                  = mem:[from 0x00000800 size 254K];
+define region RAM_bank1_region            = mem:[from 0x20000200 size 0x00003E00];
+define region RAM_bank2_region            = mem:[from 0x20004000 size 0x00004000]
+                                          | mem:[from 0x20040000 size 0x00008000];
+define block CSTACK   with alignment = 16, size = 0x1000 { };
+define block HEAP     with alignment = 16, size = 0x2000 { };
+do not initialize                         { section .noinit };
+initialize by copy                        { rw };
+place at start of ROM_PAGE0_INTVEC        { ro section .vectors };
+place in          ROM_PAGE0_CHECKSUM      { ro section .checksum };
+place in          ROM_REGION              { ro };
+place at end of   RAM_bank1_region        { block CSTACK };
+place in          RAM_bank1_region        { rw section .data };
+place in          RAM_bank1_region        { block HEAP };
+place in          RAM_bank2_region        { rw };
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/PeripheralNames.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/PeripheralNames.h
new file mode 100755
index 00000000000..c1cfd6c14ae
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/PeripheralNames.h
@@ -0,0 +1,136 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    OSC32KCLK = 0,
+} RTCName;
+
+typedef enum {
+    UART_0 = 0,
+    UART_1 = 1,
+    UART_2 = 2,
+    UART_3 = 3,
+    UART_4 = 4,
+} UARTName;
+
+#define STDIO_UART_TX     USBTX
+#define STDIO_UART_RX     USBRX
+#define STDIO_UART        UART_0
+
+typedef enum {
+    I2C_0 = 0,
+    I2C_1 = 1,
+    I2C_2 = 2,
+} I2CName;
+
+#define TPM_SHIFT   8
+typedef enum {
+    PWM_1  = (0 << TPM_SHIFT) | (0),  // FTM0 CH0
+    PWM_2  = (0 << TPM_SHIFT) | (1),  // FTM0 CH1
+    PWM_3  = (0 << TPM_SHIFT) | (2),  // FTM0 CH2
+    PWM_4  = (0 << TPM_SHIFT) | (3),  // FTM0 CH3
+    PWM_5  = (0 << TPM_SHIFT) | (4),  // FTM0 CH4
+    PWM_6  = (0 << TPM_SHIFT) | (5),  // FTM0 CH5
+    PWM_7  = (0 << TPM_SHIFT) | (6),  // FTM0 CH6
+    PWM_8  = (0 << TPM_SHIFT) | (7),  // FTM0 CH7
+    PWM_9  = (1 << TPM_SHIFT) | (0),  // FTM1 CH0
+    PWM_10 = (1 << TPM_SHIFT) | (1),  // FTM1 CH1
+    PWM_11 = (1 << TPM_SHIFT) | (2),  // FTM1 CH2
+    PWM_12 = (1 << TPM_SHIFT) | (3),  // FTM1 CH3
+    PWM_13 = (1 << TPM_SHIFT) | (4),  // FTM1 CH4
+    PWM_14 = (1 << TPM_SHIFT) | (5),  // FTM1 CH5
+    PWM_15 = (1 << TPM_SHIFT) | (6),  // FTM1 CH6
+    PWM_16 = (1 << TPM_SHIFT) | (7),  // FTM1 CH7
+    PWM_17 = (2 << TPM_SHIFT) | (0),  // FTM2 CH0
+    PWM_18 = (2 << TPM_SHIFT) | (1),  // FTM2 CH1
+    PWM_19 = (2 << TPM_SHIFT) | (2),  // FTM2 CH2
+    PWM_20 = (2 << TPM_SHIFT) | (3),  // FTM2 CH3
+    PWM_21 = (2 << TPM_SHIFT) | (4),  // FTM2 CH4
+    PWM_22 = (2 << TPM_SHIFT) | (5),  // FTM2 CH5
+    PWM_23 = (2 << TPM_SHIFT) | (6),  // FTM2 CH6
+    PWM_24 = (2 << TPM_SHIFT) | (7),  // FTM2 CH7
+    // could be 4 or could be 3... not sure what register
+    //  this is for... too much abstraction
+    PWM_25 = (3 << TPM_SHIFT) | (0),  // FTM3 CH0
+    PWM_26 = (3 << TPM_SHIFT) | (1),  // FTM3 CH1
+    PWM_27 = (3 << TPM_SHIFT) | (2),  // FTM3 CH2
+    PWM_28 = (3 << TPM_SHIFT) | (3),  // FTM3 CH3
+    PWM_29 = (3 << TPM_SHIFT) | (4),  // FTM3 CH4
+    PWM_30 = (3 << TPM_SHIFT) | (5),  // FTM3 CH5
+    PWM_31 = (3 << TPM_SHIFT) | (6),  // FTM3 CH6
+    PWM_32 = (3 << TPM_SHIFT) | (7),  // FTM3 CH7
+} PWMName;
+
+typedef enum {
+    ADC0_VIN0 = 0,
+    ADC0_VIN1 = 1,
+    ADC0_VIN2 = 2,
+    ADC0_VIN3 = 3,
+    ADC0_VIN4 = 4,
+    ADC0_VIN5 = 5,
+    ADC0_VIN6 = 6,
+    ADC0_VIN7 = 7
+} ADCName;
+
+typedef enum {
+    DAC_0 = 0
+} DACName;
+
+
+typedef enum {
+    SPI_0 = 0,
+    SPI_1 = 1,
+    SPI_2 = 2,
+} SPIName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/PeripheralPins.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/PeripheralPins.c
new file mode 100755
index 00000000000..80df8caa617
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/PeripheralPins.c
@@ -0,0 +1,111 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include "PeripheralPins.h"
+
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+    {P0_10, UART_0, 1},
+    {NC,  NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {P0_11, UART_0, 1},
+    {NC,  NC, 0}
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+    {P0_00, SPI_0, 1},
+    {P1_06, SPI_1, 1},
+    {P1_02, SPI_2, 1},
+    {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {P0_01, SPI_0, 1},
+    {P1_07, SPI_1, 1},
+    {P1_03, SPI_2, 1},
+    {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {P0_02, SPI_0, 1},
+    {P1_08, SPI_1, 1},
+    {P1_04, SPI_2, 1},
+    {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {P0_03, SPI_0, 1},
+    {P1_09, SPI_1, 1},
+    {P2_10, SPI_2, 1},
+    {NC, NC, 0}
+};
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+    {P2_03, ADC0_VIN0, 1},
+    {P2_04, ADC0_VIN1, 1},
+    {P2_05, ADC0_VIN2, 1},
+    {P2_06, ADC0_VIN3, 1},
+    {P2_07, ADC0_VIN4, 1},
+    {P2_08, ADC0_VIN5, 1},
+    {P2_09, ADC0_VIN6, 1},
+    {P2_10, ADC0_VIN7, 1},
+    {NC, NC, 0}
+};
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+    {P0_05, I2C_0, 1},
+    {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {P0_04, I2C_0, 1},
+    {NC, NC, 0}
+};
+
+/************RTC***************/
+const PinMap PinMap_RTC[] = {
+    {NC, OSC32KCLK, 0},
+};
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/PeripheralPins.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/PeripheralPins.h
new file mode 100755
index 00000000000..40ef7f85b12
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/PeripheralPins.h
@@ -0,0 +1,67 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifndef MBED_PERIPHERALPINS_H
+#define MBED_PERIPHERALPINS_H
+
+#include "pinmap.h"
+#include "PeripheralNames.h"
+
+/************RTC***************/
+extern const PinMap PinMap_RTC[];
+
+/************ADC***************/
+extern const PinMap PinMap_ADC[];
+
+/************I2C***************/
+extern const PinMap PinMap_I2C_SDA[];
+extern const PinMap PinMap_I2C_SCL[];
+
+/************UART***************/
+extern const PinMap PinMap_UART_TX[];
+extern const PinMap PinMap_UART_RX[];
+
+/************SPI***************/
+extern const PinMap PinMap_SPI_SCLK[];
+extern const PinMap PinMap_SPI_MOSI[];
+extern const PinMap PinMap_SPI_MISO[];
+extern const PinMap PinMap_SPI_SSEL[];
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/analogin_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/analogin_api.c
new file mode 100755
index 00000000000..91905d61bd5
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/analogin_api.c
@@ -0,0 +1,227 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "adi_adc_def.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ADC Device number */
+#define ADC_DEV_NUM                (0u)
+
+/* Memory Required for adc driver */
+static uint32_t DeviceMemory[(ADI_ADC_MEMORY_SIZE+3)/4];
+/* Active channel */
+static uint32_t adi_pin2channel(PinName pin);
+
+/**
+ * \defgroup hal_analogin Analogin hal functions
+ * @{
+ */
+
+/** Initialize the analogin peripheral
+ *
+ * Configures the pin used by analogin.
+ * @param obj The analogin object to initialize
+ * @param pin The analogin pin name
+ */
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    ADI_ADC_HANDLE hDevice;
+    bool bCalibrationDone = false;
+    bool bReady = false;
+
+    ADCName peripheral;
+    uint32_t function, channel;
+
+    peripheral = (ADCName)pinmap_peripheral(pin, &PinMap_ADC[0]);	// gives peripheral
+    MBED_ASSERT(peripheral != (ADCName)NC);
+
+    /* verify read function */
+    function = pinmap_function(pin, &PinMap_ADC[0]);
+    MBED_ASSERT(function == 1);
+
+    /* Configure PORT2_MUX registers */
+    pin_function(pin, function);
+
+    /* Configure active channel */
+    channel = adi_pin2channel(pin);
+    MBED_ASSERT(channel != 0xFFFFFFFF);
+    obj->UserBuffer.nChannels = channel;
+
+    /* Set ACLK to CCLK/16 */
+    adi_pwr_SetClockDivider(ADI_CLOCK_ACLK,16);
+
+    /* Set default values for conversion and delay cycles. This sets up a sampling rate of
+       16kHz. The sampling frequency is worked out from the following:
+
+       if delay time > 0:
+            Fs = ACLK / [((14 + sampling time) * oversample factor) + (delay time + 2)]
+       if delay time = 0:
+            Fs = ACLK / ((14 + sampling time) * oversample factor)
+
+       The sampling (or acquisition) and delay times are in number of ACLK clock cycles.
+    */
+    obj->DelayCycles = 0;
+    obj->SampleCycles = 88;
+
+    /* Open the ADC device */
+    adi_adc_Open(ADC_DEV_NUM, DeviceMemory, sizeof(DeviceMemory), &hDevice);
+    obj->hDevice = hDevice;
+
+    /* Power up ADC */
+    adi_adc_PowerUp(hDevice, true);
+
+    /* Set ADC reference */
+    adi_adc_SetVrefSource(hDevice, ADI_ADC_VREF_SRC_INT_2_50_V);
+
+    /* Enable ADC sub system */
+    adi_adc_EnableADCSubSystem(hDevice, true);
+
+    /* Wait untilthe ADC is ready for sampling */
+    while(bReady == false) {
+        adi_adc_IsReady(hDevice, &bReady);
+    }
+
+    /* Start calibration */
+    adi_adc_StartCalibration(hDevice);
+
+    /* Wait until calibration is done */
+    while (!bCalibrationDone) {
+        adi_adc_IsCalibrationDone(hDevice, &bCalibrationDone);
+    }
+
+    /* Set the delay time */
+    adi_adc_SetDelayTime(hDevice, obj->DelayCycles);
+
+    /* Set the acquisition time. (Application need to change it based on the impedence) */
+    adi_adc_SetAcquisitionTime(hDevice, obj->SampleCycles);
+}
+
+/** Read the input voltage, represented as a float in the range [0.0, 1.0]
+ *
+ * @param obj The analogin object
+ * @return A floating value representing the current input voltage
+ */
+float analogin_read(analogin_t *obj)
+{
+    float fl32 = (float)analogin_read_u16(obj)/(float)4095.0;
+
+    return(fl32);
+}
+
+/** Read the value from analogin pin, represented as an unsigned 16bit value
+ *
+ * @param obj The analogin object
+ * @return An unsigned 16bit value representing the current input voltage
+ */
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+    ADI_ADC_HANDLE  hDevice = obj->hDevice;
+    ADI_ADC_BUFFER  *pAdcBuffer;
+
+    /* Submit the buffer to the driver */
+    adi_adc_SubmitBuffer(hDevice, &obj->UserBuffer);
+
+    /* Enable the ADC */
+    adi_adc_Enable(hDevice, true);
+
+    adi_adc_GetBuffer(hDevice, &pAdcBuffer);
+    MBED_ASSERT(pAdcBuffer == &obj->UserBuffer);
+
+    return( (uint16_t)( ((uint16_t *)pAdcBuffer->pDataBuffer)[(pAdcBuffer->nNumConversionPasses) - 1]) );
+}
+
+/* Retrieve te active channel correspondoing to the input pin */
+static uint32_t adi_pin2channel(PinName pin) {
+
+    uint32_t activech;
+
+    switch(pin) {
+        case ADC_VIN0:
+            activech = ADI_ADC_CHANNEL_0;
+            break;
+        case ADC_VIN1:
+            activech = ADI_ADC_CHANNEL_1;
+            break;
+        case ADC_VIN2:
+            activech = ADI_ADC_CHANNEL_2;
+            break;
+        case ADC_VIN3:
+            activech = ADI_ADC_CHANNEL_3;
+            break;
+        case ADC_VIN4:
+            activech = ADI_ADC_CHANNEL_4;
+            break;
+        case ADC_VIN5:
+            activech = ADI_ADC_CHANNEL_5;
+            break;
+        case ADC_VIN6:
+            activech = ADI_ADC_CHANNEL_6;
+            break;
+        case ADC_VIN7:
+            activech = ADI_ADC_CHANNEL_7;
+            break;
+        default:
+            activech = (uint32_t) 0xFFFFFFFF;
+            break;
+    }
+
+    return ((uint32_t)activech);
+}
+
+
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // #if DEVICE_ANALOGIN
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/cmsis.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/cmsis.h
new file mode 100755
index 00000000000..b0439b1db09
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/cmsis.h
@@ -0,0 +1,47 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+#define     __C
+#include "adi_processor.h"
+#include "cmsis_nvic.h"
+#undef      __C
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/cmsis_nvic.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/cmsis_nvic.h
new file mode 100755
index 00000000000..8310b5fbbea
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/cmsis_nvic.h
@@ -0,0 +1,78 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_USER_IRQ_OFFSET 16
+#define NVIC_USER_IRQ_NUMBER 64
+#define NVIC_NUM_VECTORS     (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
+
+#define NVIC_RAM_VECTOR_ADDRESS   0x20000000
+#define NVIC_FLASH_VECTOR_ADDRESS 0x0
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Set the ISR for IRQn
+ *
+ * Sets an Interrupt Service Routine vector for IRQn; if the feature is available, the vector table is relocated to SRAM
+ * the first time this function is called
+ * @param[in] IRQn   The Interrupt Request number for which a vector will be registered
+ * @param[in] vector The ISR vector to register for IRQn
+ */
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+
+/** Get the ISR registered for IRQn
+ *
+ * Reads the Interrupt Service Routine currently registered for IRQn
+ * @param[in] IRQn   The Interrupt Request number the vector of which will be read
+ * @return           Returns the ISR registered for IRQn
+ */
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/device.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/device.h
new file mode 100755
index 00000000000..0d46738ec1a
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/device.h
@@ -0,0 +1,48 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_ID_LENGTH       24
+
+#include "objects.h"
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/flash_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/flash_api.c
new file mode 100755
index 00000000000..feae0e3d982
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/flash_api.c
@@ -0,0 +1,91 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifdef DEVICE_FLASH
+#include "flash_api.h"
+#include "flash_data.h"
+#include "mbed_critical.h"
+
+// This file is automagically generated
+
+// This is a flash algo binary blob. It is PIC (position independent code) that should be stored in RAM
+
+static unsigned FLASH_ALGO[] = {
+    0x2000B508,0x4A5B1E41,0x495B6011,0x21076211,0xBF006091,0x68094957,0x99009100,0x0104F001,
+    0xD0F72900,0xF0019900,0xB1010130,0x21002001,0x62114A50,0xB5F0BD08,0x460F4606,0x4D4D4614,
+    0x20013554,0x20007028,0x6048494A,0xD1072C01,0x6D004608,0x0001F000,0xF7FFB110,0xBDF0FFD1,
+    0xE7FC2000,0x20004601,0x62104A42,0xB5084770,0x20004601,0x4B3F1E42,0x461A601A,0x4A3E6191,
+    0x2206621A,0xBF00609A,0x68124A3A,0x9A009200,0x0204F002,0xD0F72A00,0xF0029A00,0xB1020230,
+    0x22002001,0x621A4B33,0xB5FEBD08,0x460B4604,0x46252600,0x48304611,0x62384F2E,0xF04FE052,
+    0x4F2C30FF,0x2B086038,0x6808D304,0x68486138,0xE02F6178,0x3CFFF04F,0xC000F8CD,0xC004F8CD,
+    0x2B084668,0xE8DFD21A,0x1619F003,0x0A0D1013,0x798F0407,0xBF007187,0x7147794F,0x790FBF00,
+    0xBF007107,0x70C778CF,0x788FBF00,0xBF007087,0x7047784F,0x780FBF00,0xE0007007,0xBF00BF00,
+    0xC050F8DF,0xF8CC9F00,0x9F017010,0x7014F8CC,0xBF002308,0x60C5480F,0x4F0E2004,0x463860B8,
+    0xF0006800,0xB1080030,0xE00D2601,0x4809BF00,0x90026800,0xF0009802,0x28000004,0x3B08D0F7,
+    0x35083108,0xD1AA2B00,0x2000BF00,0x62384F01,0xBDFE4630,0x40018000,0x676C7565,0
+};
+
+static const flash_algo_t flash_algo_config = {
+    .init         = 0x00000037,
+    .uninit       = 0x00000065,
+    .erase_sector = 0x0000006F,
+    .program_page = 0x000000AB,
+    .static_base  = 0x0000017C,
+    .algo_blob    = FLASH_ALGO
+};
+
+static const sector_info_t sectors_info[] = {
+    {0x0, 0x800},
+};
+
+static const flash_target_config_t flash_target_config = {
+    .page_size   = 0x800,
+    .flash_start = 0x0,
+    .flash_size  = 0x00040000,
+    .sectors     = sectors_info,
+    .sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t)
+};
+
+void flash_set_target_config(flash_t *obj)
+{
+    obj->flash_algo = &flash_algo_config;
+    obj->target_config = &flash_target_config;
+}
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_api.c
new file mode 100755
index 00000000000..fdaa7d603c2
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_api.c
@@ -0,0 +1,147 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include "mbed_assert.h"
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "adi_gpio.h"
+
+
+#define MUX_FUNC_0 0x0
+#define NUM_GPIO_PORTS 4
+
+extern uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE];
+extern uint8_t gpio_initialized;
+
+static uint16_t gpio_oen[NUM_GPIO_PORTS] = {0};
+static uint16_t gpio_output_val[NUM_GPIO_PORTS] = {0};
+
+
+/******************************************************************************
+   Function definitions
+ *****************************************************************************/
+uint32_t gpio_set(PinName pin)
+{
+    MBED_ASSERT(pin != (PinName)NC);
+    uint32_t pin_num = pin & 0xFF;
+
+    pin_function(pin, MUX_FUNC_0);
+
+    return (1 << pin_num);
+}
+
+void gpio_init(gpio_t *obj, PinName pin)
+{
+    obj->pin = pin;
+
+    if (pin == (PinName)NC) {
+        return;
+    }
+
+    // Initialize the GPIO driver. This function
+    // initializes the GPIO driver only once globally.
+    if (!gpio_initialized) {
+        adi_gpio_Init(gpioMemory, ADI_GPIO_MEMORY_SIZE);
+    }
+
+    pin_function(pin, MUX_FUNC_0);
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+    uint32_t pin = obj->pin;
+
+    pin_mode((PinName)pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    uint32_t port = obj->pin >> GPIO_PORT_SHIFT;
+    uint32_t pin_num = obj->pin & 0xFF;
+
+    if (direction ==  PIN_OUTPUT) {
+        adi_gpio_OutputEnable(port, 1 << pin_num, true);
+        // save the input/output configuration
+        gpio_oen[port] |= (1 << pin_num);
+    } else {
+        adi_gpio_InputEnable(port, 1 << pin_num, true);
+        // save the input/output configuration
+        gpio_oen[port] &= (~(1 << pin_num));
+    }
+}
+
+void gpio_write(gpio_t *obj, int value)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    uint32_t port = obj->pin >> GPIO_PORT_SHIFT;
+    uint32_t pin_num = obj->pin & 0xFF;
+
+    if (value & 1) {
+        adi_gpio_SetHigh(port, (1 << pin_num));
+
+        // save the output port value
+        gpio_output_val[port] |= ((value & 1) << pin_num);
+    } else {
+        adi_gpio_SetLow(port, (1 << pin_num));
+
+        // save the output port value
+        gpio_output_val[port] &= (~(1 << pin_num));
+    }
+}
+
+
+int gpio_read(gpio_t *obj)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    uint32_t port = obj->pin >> GPIO_PORT_SHIFT;
+    uint32_t pin_num = obj->pin & 0xFF;
+    uint16_t Data;
+
+    // check whether the pin is configured as input or output
+    if ((gpio_oen[port] >> pin_num) & 1) {
+        Data = gpio_output_val[port] & (1 << pin_num);
+    } else {
+        // otherwise call GetData
+        adi_gpio_GetData(port, (1 << pin_num), &Data);
+    }
+
+    return ((((uint32_t)Data) >> pin_num) & 1);
+}
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_dev_mem.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_dev_mem.c
new file mode 100755
index 00000000000..5e0d99ad8b0
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_dev_mem.c
@@ -0,0 +1,47 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include <drivers/gpio/adi_gpio.h>
+
+// ADI GPIO device driver state memory. Only one state memory is required globally.
+uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE];
+
+// Flag to indicate whether the GPIO driver has been initialized
+uint8_t gpio_initialized = 0;
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_irq_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_irq_api.c
new file mode 100755
index 00000000000..ea62c3d3bae
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_irq_api.c
@@ -0,0 +1,327 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include "gpio_irq_api.h"
+#include "adi_gpio.h"
+#include "adi_gpio_def.h"
+#include "ADuCM302x_device.h"
+
+#ifdef DEVICE_INTERRUPTIN
+
+#define MAX_GPIO_LINES    16
+#define MAX_GPIO_PORTS    ADI_GPIO_NUM_PORTS
+
+typedef struct {
+    unsigned int id;
+    gpio_irq_event event;
+    uint8_t int_enable;
+} gpio_chan_info_t;
+
+extern uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE];
+extern uint8_t gpio_initialized;
+static gpio_chan_info_t channel_ids[MAX_GPIO_PORTS][MAX_GPIO_LINES];
+static gpio_irq_handler irq_handler = NULL;
+
+
+/** Local interrupt callback routine.
+ */
+static void gpio_irq_callback(void *pCBParam, uint32_t Event, void *pArg)
+{
+    uint16_t pin = *(ADI_GPIO_DATA*)pArg;
+    int index = 0;
+
+    // determine the index of the pin that caused the interrupt
+    while (pin) {
+        if (pin & 0x01) {
+            // call the user ISR. The argument Event is the port number of the GPIO line.
+            if (irq_handler != NULL)
+                irq_handler((uint32_t)channel_ids[Event][index].id, channel_ids[Event][index].event);
+        }
+        index++;
+        pin >>= 1;
+    }
+}
+
+
+/** Function to get the IENA and IENB register values.
+ *  Added here temporarily until these are available in the BSP
+ */
+static ADI_GPIO_RESULT adi_gpio_GetGroupInterruptPins(const ADI_GPIO_PORT Port, const IRQn_Type eIrq,
+        const ADI_GPIO_DATA Pins, uint16_t* const pValue)
+{
+    ADI_GPIO_TypeDef 	*pReg[MAX_GPIO_PORTS] = {pADI_GPIO0, pADI_GPIO1, pADI_GPIO2};
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+    uint16_t            Value = 0u;
+
+    pPort = pReg[Port];
+
+    switch (eIrq) {
+        case SYS_GPIO_INTA_IRQn:
+            Value = pPort->IENA;
+            break;
+        case SYS_GPIO_INTB_IRQn:
+            Value = pPort->IENB;
+            break;
+        default:
+            break; /* This shall never reach */
+    }
+
+    *pValue = (Value & Pins);
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/** Function to get the interrupt polarity register content.
+ *  Added here temporarily until these are available in the BSP
+ */
+static ADI_GPIO_RESULT adi_gpio_GetGroupInterruptPolarity(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins,
+        uint16_t* const pValue)
+{
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+    ADI_GPIO_TypeDef 	*pReg[MAX_GPIO_PORTS] = {pADI_GPIO0, pADI_GPIO1, pADI_GPIO2};
+
+    pPort = pReg[Port];
+
+    *pValue = (pPort->POL & Pins);
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/** Function to clear the relevant interrupt enable bits in both the IENA and IENB registers
+ *  for the given GPIO pin.
+ */
+static void disable_pin_interrupt(ADI_GPIO_PORT port, uint32_t pin_number)
+{
+    uint16_t int_reg_val;
+
+    // Read the current content of the IENA register
+    adi_gpio_GetGroupInterruptPins(port, SYS_GPIO_INTA_IRQn, 1 << pin_number, &int_reg_val);
+
+    // clear the bit for the pin
+    int_reg_val &= ~(1 << pin_number);
+
+    // write the interrupt register
+    adi_gpio_SetGroupInterruptPins(port, SYS_GPIO_INTA_IRQn, int_reg_val);
+
+    // Do the same to IENB
+    adi_gpio_GetGroupInterruptPins(port, SYS_GPIO_INTB_IRQn, 1 << pin_number, &int_reg_val);
+
+    // clear the bit for the pin
+    int_reg_val &= ~(1 << pin_number);
+
+    // write the interrupt register
+    adi_gpio_SetGroupInterruptPins(port, SYS_GPIO_INTB_IRQn, int_reg_val);
+}
+
+
+/** Function to set the relevant interrupt enable bits in either the IENA and IENB registers
+ *  for the given GPIO pin.
+ */
+static void enable_pin_interrupt(ADI_GPIO_PORT port, uint32_t pin_number, IRQn_Type eIrq)
+{
+    uint16_t int_reg_val;
+
+    // Read the current interrupt enable register content
+    adi_gpio_GetGroupInterruptPins(port, eIrq, 1 << pin_number, &int_reg_val);
+
+    // set the bit for the pin
+    int_reg_val |= (1 << pin_number);
+
+    // write the interrupt register
+    adi_gpio_SetGroupInterruptPins(port, eIrq, int_reg_val);
+}
+
+
+/** Initialize the GPIO IRQ pin
+ *
+ * @param obj     The GPIO object to initialize
+ * @param pin     The GPIO pin name
+ * @param handler The handler to be attached to GPIO IRQ
+ * @param id      The object ID (id != 0, 0 is reserved)
+ * @return -1 if pin is NC, 0 otherwise
+ */
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
+    uint32_t port = pin >> GPIO_PORT_SHIFT;
+    uint32_t pin_num = pin & 0xFF;
+
+    // check for valid pin and ID
+    if ((pin == NC) || (id == 0)) {
+        return -1;
+    }
+
+    // make sure gpio driver has been initialized
+    if (!gpio_initialized) {
+        adi_gpio_Init(gpioMemory,ADI_GPIO_MEMORY_SIZE);
+        gpio_initialized = 1;
+    }
+
+    // save the handler
+    if (handler) {
+        irq_handler = handler;
+    }
+
+    // disable the interrupt for the given pin
+    disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num);
+
+    // set the port pin as input
+    adi_gpio_InputEnable(port, 1 << pin_num, true);
+
+    // save the ID for future reference
+    channel_ids[port][pin_num].id = (uint32_t)id;
+    channel_ids[port][pin_num].event = IRQ_NONE;
+    channel_ids[port][pin_num].int_enable = 0;
+    obj->id = id;
+    obj->pinname = pin;
+
+    return 0;
+}
+
+/** Release the GPIO IRQ PIN
+ *
+ * @param obj The gpio object
+ */
+void gpio_irq_free(gpio_irq_t *obj)
+{
+    uint32_t port = obj->pinname >> GPIO_PORT_SHIFT;
+    uint32_t pin_num = obj->pinname & 0xFF;
+
+    // disable interrupt for the given pin
+    gpio_irq_disable(obj);
+
+    // clear the status table
+    channel_ids[port][pin_num].id = (uint32_t)0;
+    channel_ids[port][pin_num].event = IRQ_NONE;
+    channel_ids[port][pin_num].int_enable = 0;
+}
+
+/** Enable/disable pin IRQ event
+ *
+ * @param obj    The GPIO object
+ * @param event  The GPIO IRQ event
+ * @param enable The enable flag
+ */
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+    uint16_t int_polarity_reg;
+    uint32_t port = obj->pinname >> GPIO_PORT_SHIFT;
+    uint32_t pin_num = obj->pinname & 0xFF;
+
+    if (event == IRQ_NONE) {
+        return;
+    }
+
+    // read the current polarity register
+    adi_gpio_GetGroupInterruptPolarity((ADI_GPIO_PORT)port,	1 << pin_num, &int_polarity_reg);
+
+    if (event == IRQ_RISE) {
+        int_polarity_reg |= (1 << pin_num);
+    } else {
+        int_polarity_reg &= ~(1 << pin_num);
+    }
+
+    // set the polarity register
+    adi_gpio_SetGroupInterruptPolarity((ADI_GPIO_PORT)port, int_polarity_reg);
+
+    channel_ids[port][pin_num].event = event;
+
+    // enable interrupt for this pin if enable flag is set
+    if (enable) {
+        gpio_irq_enable(obj);
+    } else {
+        gpio_irq_disable(obj);
+    }
+}
+
+/** Enable GPIO IRQ
+ *
+ * This is target dependent, as it might enable the entire port or just a pin
+ * @param obj The GPIO object
+ */
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+    uint32_t port = obj->pinname >> GPIO_PORT_SHIFT;
+    uint32_t pin_num = obj->pinname & 0xFF;
+
+    if (channel_ids[port][pin_num].event == IRQ_NONE) {
+        return;
+    }
+
+    // Group all RISE interrupts in INTA and FALL interrupts in INTB
+    if (channel_ids[port][pin_num].event == IRQ_RISE) {
+        // set the callback routine
+        adi_gpio_RegisterCallback(SYS_GPIO_INTA_IRQn, gpio_irq_callback, obj);
+        enable_pin_interrupt((ADI_GPIO_PORT)port, pin_num, SYS_GPIO_INTA_IRQn);
+    } else if (channel_ids[port][pin_num].event == IRQ_FALL) {
+        // set the callback routine
+        adi_gpio_RegisterCallback(SYS_GPIO_INTB_IRQn, gpio_irq_callback, obj);
+        enable_pin_interrupt((ADI_GPIO_PORT)port, pin_num, SYS_GPIO_INTB_IRQn);
+    }
+
+    channel_ids[port][pin_num].int_enable = 1;
+}
+
+/** Disable GPIO IRQ
+ *
+ * This is target dependent, as it might disable the entire port or just a pin
+ * @param obj The GPIO object
+ */
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+    uint32_t port = obj->pinname >> GPIO_PORT_SHIFT;
+    uint32_t pin_num = obj->pinname & 0xFF;
+
+    if (channel_ids[port][pin_num].event == IRQ_NONE) {
+        return;
+    }
+
+    // Group all RISE interrupts in INTA and FALL interrupts in INTB
+    if (channel_ids[port][pin_num].event == IRQ_RISE) {
+        disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num);
+    }
+    else if (channel_ids[port][pin_num].event == IRQ_FALL) {
+        disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num);
+    }
+
+    channel_ids[port][pin_num].int_enable = 0;
+}
+
+#endif 	// #ifdef DEVICE_INTERRUPTIN
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_object.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_object.h
new file mode 100755
index 00000000000..8d59616b7f7
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_object.h
@@ -0,0 +1,61 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName pin;
+} gpio_t;
+
+static inline int gpio_is_connected(const gpio_t *obj)
+{
+    return obj->pin != (PinName)NC;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/i2c_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/i2c_api.c
new file mode 100755
index 00000000000..7f0b1c09837
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/i2c_api.c
@@ -0,0 +1,220 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include "mbed_assert.h"
+#include "i2c_api.h"
+
+#if DEVICE_I2C
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+#include "drivers/i2c/adi_i2c.h"
+
+
+
+#if defined(BUILD_I2C_MI_DYNAMIC)
+#if defined(ADI_DEBUG)
+#warning "BUILD_I2C_MI_DYNAMIC is defined.  Memory allocation for I2C will be dynamic"
+int adi_i2c_memtype = 0;
+#endif
+#else
+static uint8_t          i2c_Mem[ADI_I2C_MEMORY_SIZE];
+static ADI_I2C_HANDLE   i2c_Handle;
+#if defined(ADI_DEBUG)
+#warning "BUILD_I2C_MI_DYNAMIC is NOT defined.  Memory allocation for I2C will be static"
+int adi_i2c_memtype = 1;
+#endif
+#endif
+
+
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
+    uint32_t        i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
+    uint32_t        i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL);
+    ADI_I2C_HANDLE  *pI2C_Handle;
+    uint8_t         *I2C_Mem;
+    ADI_I2C_RESULT  I2C_Return = ADI_I2C_SUCCESS;
+    uint32_t        I2C_DevNum = I2C_0;     /* ADuCM3029 only has 1 I2C port */
+
+
+#if defined(BUILD_I2C_MI_DYNAMIC)
+    I2C_DevNum = I2C_0;
+    pI2C_Handle = &obj->I2C_Handle;
+    obj->pI2C_Handle = pI2C_Handle;
+    I2C_Mem = obj->I2C_Mem;
+#else
+    I2C_DevNum = I2C_0;
+    pI2C_Handle = &i2c_Handle;
+    obj->pI2C_Handle = pI2C_Handle;
+    I2C_Mem = &i2c_Mem[0];
+#endif
+
+
+    obj->instance = pinmap_merge(i2c_sda, i2c_scl);
+    MBED_ASSERT((int)obj->instance != NC);
+    pinmap_pinout(sda, PinMap_I2C_SDA);
+    pinmap_pinout(scl, PinMap_I2C_SCL);
+    SystemCoreClockUpdate();
+    I2C_Return = adi_i2c_Open(I2C_DevNum, I2C_Mem, ADI_I2C_MEMORY_SIZE, pI2C_Handle);
+    if (I2C_Return) {
+        obj->error = I2C_EVENT_ERROR;
+        return;
+    }
+    I2C_Return = adi_i2c_Reset(*pI2C_Handle);
+    if (I2C_Return) {
+        obj->error = I2C_EVENT_ERROR;
+        return;
+    }
+}
+
+
+int i2c_start(i2c_t *obj)
+{
+    /* The Hardware does not support this feature. */
+    return -1;
+}
+
+
+int i2c_stop(i2c_t *obj)
+{
+    /* The Hardware does not support this feature. */
+    return -1;
+}
+
+
+void i2c_frequency(i2c_t *obj, int hz)
+{
+    ADI_I2C_HANDLE  I2C_Handle;
+    ADI_I2C_RESULT  I2C_Return = ADI_I2C_SUCCESS;
+
+
+    I2C_Handle = *obj->pI2C_Handle;
+    I2C_Return = adi_i2c_SetBitRate(I2C_Handle, (uint32_t) hz);
+    if (I2C_Return) {
+        obj->error = I2C_EVENT_ERROR;
+        return;
+    }
+}
+
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
+    ADI_I2C_RESULT      I2C_Return;
+    ADI_I2C_TRANSACTION I2C_inst;
+    uint8_t             I2C_PrologueData = 0x00;
+    uint32_t            I2C_Errors;                 /* HW Error result */
+    ADI_I2C_HANDLE      I2C_Handle;
+
+
+    I2C_Handle = *obj->pI2C_Handle;
+    I2C_Return = adi_i2c_SetSlaveAddress(I2C_Handle, (address & 0x0000FFFF));
+    I2C_inst.pPrologue     = &I2C_PrologueData;
+    I2C_inst.nPrologueSize = 0;
+    I2C_inst.pData         = (uint8_t*) data;
+    I2C_inst.nDataSize     = length;
+    I2C_inst.bReadNotWrite = true;
+    I2C_inst.bRepeatStart  = stop;
+    I2C_Return = adi_i2c_ReadWrite(I2C_Handle, &I2C_inst, &I2C_Errors);
+    if (I2C_Return) {
+        obj->error = I2C_EVENT_ERROR;
+        return -1;
+    } else {
+        return length;
+    }
+}
+
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
+    ADI_I2C_RESULT      I2C_Return = ADI_I2C_SUCCESS;
+    ADI_I2C_TRANSACTION I2C_inst;
+    uint8_t             I2C_PrologueData = 0x00;
+    uint32_t            I2C_Errors;                 /* HW Error result */
+    ADI_I2C_HANDLE      I2C_Handle;
+
+
+    I2C_Handle = *obj->pI2C_Handle;
+    I2C_Return = adi_i2c_SetSlaveAddress(I2C_Handle, (address & 0x0000FFFF));
+    I2C_inst.pPrologue      = &I2C_PrologueData;
+    I2C_inst.nPrologueSize  = 0;
+    I2C_inst.pData          = (uint8_t*) data;
+    I2C_inst.nDataSize      = length;
+    I2C_inst.bReadNotWrite  = false;
+    I2C_inst.bRepeatStart   = stop;
+    I2C_Return = adi_i2c_ReadWrite(I2C_Handle, &I2C_inst, &I2C_Errors);
+    if (I2C_Return) {
+        obj->error = I2C_EVENT_ERROR;
+        return -1;
+    } else {
+        return length;
+    }
+}
+
+
+void i2c_reset(i2c_t *obj)
+{
+    ADI_I2C_RESULT      I2C_Return;
+    ADI_I2C_HANDLE      I2C_Handle = *obj->pI2C_Handle;
+
+    I2C_Return = adi_i2c_Reset(I2C_Handle);
+    if (I2C_Return) {
+        obj->error = I2C_EVENT_ERROR;
+        return;
+    }
+}
+
+
+int i2c_byte_read(i2c_t *obj, int last)
+{
+    /* The Hardware does not support this feature. */
+    return -1;
+}
+
+
+int i2c_byte_write(i2c_t *obj, int data)
+{
+    /* The Hardware does not support this feature. */
+    return -1;
+}
+
+#endif  // #if DEVICE_I2C
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/objects.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/objects.h
new file mode 100755
index 00000000000..d57a3b21ded
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/objects.h
@@ -0,0 +1,111 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+#include "gpio_object.h"
+#include "adi_adc.h"
+#include "adi_rng.h"
+
+#include "adi_i2c.h"
+#include "adi_spi.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Add your custom header content here */
+struct gpio_irq_s {
+    unsigned int id;
+    PinName pinname;
+};
+
+struct sleep_s {
+    int temp;
+};
+
+struct serial_s {
+    int index;
+};
+
+struct trng_s {
+    ADI_RNG_HANDLE  RNGhDevice;
+};
+
+#define BUILD_I2C_MI_DYNAMIC
+struct i2c_s {
+    uint32_t        instance;
+    uint32_t        error;
+    ADI_I2C_HANDLE  *pI2C_Handle;
+#if defined(BUILD_I2C_MI_DYNAMIC)
+    ADI_I2C_HANDLE  I2C_Handle;
+    uint8_t         I2C_Mem[ADI_I2C_MEMORY_SIZE];
+#endif
+};
+
+#define BUILD_SPI_MI_DYNAMIC
+struct spi_s {
+    uint32_t        instance;
+    uint32_t        error;
+    ADI_SPI_HANDLE  *pSPI_Handle;
+#if defined(BUILD_SPI_MI_DYNAMIC)
+    ADI_SPI_HANDLE  SPI_Handle;
+    uint8_t         SPI_Mem[ADI_SPI_MEMORY_SIZE];
+#endif
+};
+
+struct analogin_s {
+    ADI_ADC_HANDLE  hDevice;
+    ADI_ADC_BUFFER  UserBuffer;
+    uint8_t         DelayCycles;
+    uint8_t         SampleCycles;
+};
+
+#include "gpio_object.h"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/pinmap.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/pinmap.c
new file mode 100755
index 00000000000..eed31f176e7
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/pinmap.c
@@ -0,0 +1,105 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+#include "PinNames.h"
+#include "adi_gpio.h"
+
+void pin_function(PinName pin, int function)
+{
+    // pin is composed of port and pin
+    // function is the function number (the mux selection number shifted by the pin value
+    // and written to pin mux register, each pin mux takes 2 bits hence multiplying by 2)
+
+    MBED_ASSERT(pin != (PinName)NC);
+
+    uint8_t port = pin >> GPIO_PORT_SHIFT;
+    uint32_t cfg_reg, mask;
+    volatile uint32_t *pGPIO_CFG;
+
+    switch (port) {
+        case 0:
+            pGPIO_CFG = (volatile uint32_t *)REG_GPIO0_CFG;
+            break;
+        case 1:
+            pGPIO_CFG = (volatile uint32_t *)REG_GPIO1_CFG;
+            break;
+        case 2:
+            pGPIO_CFG = (volatile uint32_t *)REG_GPIO2_CFG;
+            break;
+
+        default:
+            return;
+    }
+
+    cfg_reg = *pGPIO_CFG;
+    // clear the corresponding 2 bit field first before writing the function
+    // bits
+    mask = ~(3 << (pin * 2));
+    cfg_reg = (cfg_reg & mask) | (function << (pin*2));
+    *pGPIO_CFG = cfg_reg;
+}
+
+void pin_mode(PinName pin, PinMode mode)
+{
+    MBED_ASSERT(pin != (PinName)NC);
+
+    uint8_t port = pin >> GPIO_PORT_SHIFT;
+    uint32_t pin_reg_value = 2 ^ (0xFF & pin);
+
+    switch (mode) {
+        case PullNone:
+            adi_gpio_PullUpEnable((ADI_GPIO_PORT)port, (ADI_GPIO_DATA)pin_reg_value,false);
+            break;
+
+        case PullDown:
+        case PullUp:
+            adi_gpio_PullUpEnable((ADI_GPIO_PORT)port, (ADI_GPIO_DATA)pin_reg_value,true);
+            break;
+
+        default:
+            break;
+
+    }
+
+}
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/rtc_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/rtc_api.c
new file mode 100755
index 00000000000..a1d6c95243c
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/rtc_api.c
@@ -0,0 +1,93 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include "rtc_api.h"
+
+#if DEVICE_RTC
+
+#include "adi_rtc.h"
+#include "adi_pwr.h"
+
+#define RTC_DEVICE_NUM    0
+static uint8_t aRtcDevMem0[ADI_RTC_MEMORY_SIZE];
+static ADI_RTC_HANDLE hDevice0 = NULL;
+
+
+void rtc_init(void)
+{
+    /* initialize driver */
+    adi_rtc_Open(RTC_DEVICE_NUM,aRtcDevMem0,ADI_RTC_MEMORY_SIZE,&hDevice0);
+
+    adi_rtc_Enable(hDevice0, true);
+}
+
+void rtc_free(void)
+{
+    adi_rtc_Close(hDevice0);
+}
+
+/*
+ * Little check routine to see if the RTC has been enabled
+ * 0 = Disabled, 1 = Enabled
+ */
+int rtc_isenabled(void)
+{
+    uint32_t ControlReg;
+
+    adi_rtc_GetControl (hDevice0, ADI_RTC_CONTROL_REGISTER_0,&ControlReg);
+
+    return((int) (ControlReg & BITM_RTC_CR0_CNTEN));
+}
+
+time_t rtc_read(void)
+{
+    time_t currentCount;
+
+    adi_rtc_GetCount(hDevice0, (uint32_t *)(&currentCount));
+
+    return(currentCount);
+}
+
+void rtc_write(time_t t)
+{
+    adi_rtc_SetCount (hDevice0, t);
+}
+
+#endif //  #if DEVICE_RTC
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/serial_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/serial_api.c
new file mode 100755
index 00000000000..f54b390f713
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/serial_api.c
@@ -0,0 +1,295 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include "serial_api.h"
+
+#if DEVICE_SERIAL
+
+// math.h required for floating point operations for baud rate calculation
+#include <math.h>
+#include "mbed_assert.h"
+
+#include <string.h>
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "drivers/uart/adi_uart.h"
+
+#define ADI_UART_MEMORY_SIZE   (ADI_UART_BIDIR_MEMORY_SIZE)
+
+static ADI_UART_HANDLE          hDevice;
+static uint32_t UartDeviceMem[(ADI_UART_MEMORY_SIZE + 3)/4];
+static uint32_t serial_irq_ids[2] = {0};
+static uart_irq_handler irq_handler = NULL;
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+static int rxbuffer[1];
+static int txbuffer[1];
+
+static void uart_callback(void *pCBParam, uint32_t Event, void *pArg)
+{
+    MBED_ASSERT(irq_handler);
+
+    if (Event == ADI_UART_EVENT_TX_BUFFER_PROCESSED)
+        irq_handler(serial_irq_ids[0], TxIrq);
+    else if (Event == ADI_UART_EVENT_RX_BUFFER_PROCESSED)
+        irq_handler(serial_irq_ids[0], RxIrq);
+}
+
+
+void serial_free(serial_t *obj)
+{
+    adi_uart_Close(hDevice);
+}
+
+void serial_baud(serial_t *obj, int baudrate)
+{
+    uint32_t uartdivc,uartdivm,uartdivn,uartosr;
+    switch (baudrate) {
+        default:
+        case    9600:
+            uartdivc= 22;
+            uartdivm= 3;
+            uartdivn= 1734;
+            uartosr= 3;
+            break;
+        case   19200:
+            uartdivc= 11;
+            uartdivm= 3;
+            uartdivn= 1735;
+            uartosr= 3;
+            break;
+        case   38400:
+            uartdivc= 17;
+            uartdivm= 1;
+            uartdivn= 0501;
+            uartosr= 3;
+            break;
+        case   57600:
+            uartdivc= 07;
+            uartdivm= 2;
+            uartdivn= 0031;
+            uartosr= 3;
+            break;
+        case  115200:
+            uartdivc= 07;
+            uartdivm= 2;
+            uartdivn= 0031;
+            uartosr= 2;
+            break;
+        case  230400:
+            uartdivc= 07;
+            uartdivm= 2;
+            uartdivn= 0031;
+            uartosr= 1;
+            break;
+        case  460800:
+            uartdivc= 07;
+            uartdivm= 2;
+            uartdivn= 0031;
+            uartosr= 0;
+            break;
+        case  921600:
+            uartdivc= 01;
+            uartdivm= 1;
+            uartdivn= 1563;
+            uartosr= 2;
+            break;
+        case 1000000:
+            uartdivc= 01;
+            uartdivm= 1;
+            uartdivn= 1280;
+            uartosr= 2;
+            break;
+        case 1500000:
+            uartdivc= 01;
+            uartdivm= 2;
+            uartdivn= 0341;
+            uartosr= 1;
+            break;
+        case 3000000:
+            uartdivc= 01;
+            uartdivm= 2;
+            uartdivn= 0341;
+            uartosr= 0;
+            break;
+        case 4000000:
+            uartdivc= 01;
+            uartdivm= 1;
+            uartdivn= 1280;
+            uartosr= 0;
+            break;
+        case 5000000:
+            uartdivc= 01;
+            uartdivm= 1;
+            uartdivn= 0614;
+            uartosr= 0;
+            break;
+        case 6000000:
+            uartdivc= 01;
+            uartdivm= 1;
+            uartdivn= 0171;
+            uartosr= 0;
+            break;
+        case 6500000:
+            uartdivc= 01;
+            uartdivm= 1;
+            uartdivn= 0000;
+            uartosr= 0;
+            break;
+    }
+    adi_uart_ConfigBaudRate(hDevice,uartdivc,uartdivm,uartdivn,uartosr);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
+    int convertedparity   = ADI_UART_NO_PARITY;
+    int convertedstopbits = ADI_UART_ONE_STOPBIT;
+
+    if (stop_bits)
+        convertedstopbits = ADI_UART_ONE_AND_HALF_TWO_STOPBITS;
+
+    if (parity == ParityOdd)
+        convertedparity = ADI_UART_ODD_PARITY;
+    else if (parity == ParityEven)
+        convertedparity = ADI_UART_EVEN_PARITY;
+    else if (parity == ParityForced1)
+        convertedparity = ADI_UART_ODD_PARITY_STICKY;
+    else if (parity == ParityForced0)
+        convertedparity = ADI_UART_EVEN_PARITY_STICKY;
+
+    adi_uart_SetConfiguration(hDevice,convertedparity,convertedstopbits, (data_bits - 5));
+}
+
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
+    uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
+    uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
+
+    obj->index = pinmap_merge(uart_tx, uart_rx);
+    MBED_ASSERT((int)obj->index != NC);
+
+    adi_uart_Open(0,ADI_UART_DIR_BIDIRECTION,UartDeviceMem,ADI_UART_MEMORY_SIZE,&hDevice);
+
+    serial_baud(obj, 9600);
+    serial_format(obj, 8, ParityNone, 1);
+
+    pinmap_pinout(tx, PinMap_UART_TX);
+    pinmap_pinout(rx, PinMap_UART_RX);
+
+    if (tx != NC) {
+        pin_mode(tx, PullUp);
+    }
+    if (rx != NC) {
+        pin_mode(rx, PullUp);
+    }
+    if (obj->index == STDIO_UART) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+}
+
+int serial_getc(serial_t *obj)
+{
+    void *pBuff;
+    uint32_t hw_error;
+
+    adi_uart_SubmitRxBuffer(hDevice, rxbuffer, 1, true);
+    adi_uart_GetRxBuffer(hDevice, &pBuff, &hw_error);
+    return rxbuffer[0];
+}
+
+void serial_putc(serial_t *obj, int c)
+{
+    void *pBuff;
+    uint32_t hw_error;
+
+    txbuffer[0] = c;
+    adi_uart_SubmitTxBuffer(hDevice,txbuffer, 1, true);
+    adi_uart_GetTxBuffer(hDevice, &pBuff, &hw_error);
+    return;
+}
+
+int serial_readable(serial_t *obj)
+{
+    bool bAvailable = false;
+    adi_uart_IsRxBufferAvailable(hDevice, &bAvailable);
+    return bAvailable;
+}
+
+int serial_writable(serial_t *obj)
+{
+    bool bAvailable = false;
+    adi_uart_IsTxBufferAvailable(hDevice, &bAvailable);
+    return bAvailable;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+    MBED_ASSERT(obj);
+
+    adi_uart_RegisterCallback(hDevice, &uart_callback, obj);
+}
+
+void serial_pinout_tx(PinName tx)
+{
+    pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj)
+{
+    adi_uart_ForceTxBreak(hDevice, true);
+}
+
+void serial_break_clear(serial_t *obj)
+{
+    adi_uart_ForceTxBreak(hDevice, false);
+}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+
+    MBED_ASSERT(obj);
+
+    irq_handler = handler;
+    serial_irq_ids[0] = id;
+}
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/sleep.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/sleep.c
new file mode 100755
index 00000000000..daf5e06738c
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/sleep.c
@@ -0,0 +1,221 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include "sleep_api.h"
+
+#ifdef DEVICE_SLEEP
+
+#include "adi_pwr.h"
+#include "adi_pwr_def.h"
+#include "adi_rtos_map.h"
+#include "ADuCM3029_device.h"
+#include "sleep.h"
+
+/**
+ * Function to put processor into sleep (FLEXI mode only).
+ */
+static void go_into_WFI(const ADI_PWR_POWER_MODE PowerMode)
+{
+    uint32_t savedPriority;
+    uint16_t savedWDT;
+    uint32_t scrSetBits = 0u;
+    uint32_t scrClrBits = 0u;
+    ADI_INT_STATUS_ALLOC();
+
+    /* pre-calculate the sleep-on-exit set/clear bits, FLEXI mode only */
+    scrSetBits |= SCB_SCR_SLEEPONEXIT_Msk;
+
+    /* wfi without deepsleep or sleep-on-exit */
+    scrClrBits |= (uint32_t)(BITM_NVIC_INTCON0_SLEEPDEEP | BITM_NVIC_INTCON0_SLEEPONEXIT);
+
+    /* put all the power mode and system control mods inside a critical section */
+    ADI_ENTER_CRITICAL_REGION();
+
+    { /* these three lines must be in a success-checking loop if they are not inside critical section */
+        /* Uninterruptable unlock sequence */
+        pADI_PMG0->PWRKEY = ADI_PMG_KEY;
+
+        /* Clear the previous mode and set new mode */
+        pADI_PMG0->PWRMOD =(uint32_t) ( ( pADI_PMG0->PWRMOD & (uint32_t) (~BITM_PMG_PWRMOD_MODE) ) | PowerMode );
+    }
+
+    /* Update the SCR (sleepdeep and sleep-on-exit bits) */
+    SCB->SCR = ((SCB->SCR | scrSetBits) & ~scrClrBits);
+
+    /* save current Base Priority Level */
+    savedPriority = __get_BASEPRI();
+
+    /* NOTE: the watchdog timer (WDT) of the GlueMicro (ADuCM302x) is reset
+       by the core hardware with every exit from low-power mode.  Therefore,
+       even though we may have disabled it during startup, it will reset
+       itself on exit from every hibernation state.  Therefore, to avoid
+       unintended system resets every 30 seconds because of unexpected WDT
+       timeouts, we save/restore the WDT control register around
+       hibernation entry and exit.
+    */
+
+    /* save WDT control register */
+    savedWDT = pADI_WDT0->CTL;
+
+    /* Set caller's priority threshold (left-justified) */
+    __set_BASEPRI(0);
+
+    /* bus sync to insure register writes from interrupt handlers are always complete before WFI */
+    __DSB();
+
+    /* Wait for interrupt */
+    __WFI();
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    ADI_ENTER_CRITICAL_REGION();
+
+    /* Restore previous base priority */
+    __set_BASEPRI(savedPriority);
+
+    /* restore WDT control register */
+    pADI_WDT0->CTL = savedWDT;
+
+    /* clear sleep-on-exit bit to avoid sleeping on exception return to thread level */
+    SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
+
+    __DSB(); /* bus sync before re-enabling interrupts */
+
+    ADI_EXIT_CRITICAL_REGION();
+}
+
+
+/**
+ * Function to enable/disable clock gating for the available clocks.
+ * PCLK overrides all the other clocks.
+ */
+void set_clock_gating(peripheral_clk_t eClk, int enable)
+{
+    uint32_t flag;
+
+    switch (eClk) {
+        case PCLK:
+            flag = 1 << BITP_CLKG_CLK_CTL5_PERCLKOFF;
+            break;
+        case I2C_CLOCK:
+            flag = 1 << BITP_CLKG_CLK_CTL5_UCLKI2COFF;
+            break;
+        case GPIO_CLOCK:
+            flag = 1 << BITP_CLKG_CLK_CTL5_GPIOCLKOFF;
+            break;
+        case GPT0_CLOCK:
+            flag = 1 << BITP_CLKG_CLK_CTL5_GPTCLK0OFF;
+            break;
+        case GPT1_CLOCK:
+            flag = 1 << BITP_CLKG_CLK_CTL5_GPTCLK1OFF;
+            break;
+        case GPT2_CLOCK:
+            flag = 1 << BITP_CLKG_CLK_CTL5_GPTCLK2OFF;
+            break;
+        default:
+            return;
+    }
+
+    // if enable, set the bit otherwise clear the bit
+    if (enable) {
+        pADI_CLKG0_CLK->CTL5 |= flag;
+    } else {
+        pADI_CLKG0_CLK->CTL5 &= (~flag);
+    }
+}
+
+
+
+/** Send the microcontroller to sleep
+ *
+ * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
+ * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
+ * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
+ * memory state are maintained, and the peripherals continue to work and can generate interrupts.
+ *
+ * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
+ *
+ * @note
+ * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ *
+ * This mode puts the processor into FLEXI mode however the peripheral clocks are not gated
+ * hence they are still active.
+ */
+void hal_sleep(void)
+{
+    // set to go into the FLEXI mode where the processor is asleep and all peripherals are
+    // still active
+    go_into_WFI(ADI_PWR_MODE_FLEXI);
+}
+
+
+/** Send the microcontroller to deep sleep
+ *
+ * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
+ * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
+ * is still maintained.
+ *
+ * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
+ *
+ * @note
+ *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ *
+ * This mode puts the processor into FLEXI mode and all the peripheral clocks are clock gated
+ * hence they are inactive until interrupts are generated in which case the processor is awaken
+ * from sleep.
+ */
+void hal_deepsleep(void)
+{
+    // set clock gating to all the peripheral clocks
+    set_clock_gating(PCLK, 1);
+
+    // set to go into the FLEXI mode with peripheral clocks gated.
+    go_into_WFI(ADI_PWR_MODE_FLEXI);
+
+    // when exiting, clear all peripheral clock gating bits. This is done to enable clocks that aren't
+    // automatically re-enabled out of sleep such as the GPIO clock.
+    pADI_CLKG0_CLK->CTL5 = 0;
+}
+
+#endif  // #ifdef DEVICE_SLEEP
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/sleep.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/sleep.h
new file mode 100755
index 00000000000..6d379a78009
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/sleep.h
@@ -0,0 +1,68 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifndef __SLEEP__H__
+#define __SLEEP__H__
+
+
+/* Enumeration to specify peripheral clock types:
+   General purpose timer clocks 0-2,
+   I2C clock,
+   GPIO clock,
+   RGB timer clock.
+   Peripheral clock (PCLK) controls all the peripheral clocks, including
+   all the clocks mentioned previously
+*/
+typedef enum {
+    GPT0_CLOCK = 0,
+    GPT1_CLOCK,
+    GPT2_CLOCK,
+    I2C_CLOCK,
+    GPIO_CLOCK,
+    PCLK
+} peripheral_clk_t;
+
+
+/* Function to enable/disable clock gating for the available clocks.
+   PCLK overrides all the other clocks.
+*/
+void set_clock_gating(peripheral_clk_t eClk, int enable);
+
+#endif  // #ifndef __SLEEP_H__
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c
new file mode 100755
index 00000000000..f5ef0bc4157
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c
@@ -0,0 +1,366 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include <math.h>
+#include "mbed_assert.h"
+
+#include "spi_api.h"
+
+#if DEVICE_SPI
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+#include "drivers/spi/adi_spi.h"
+
+
+
+#if defined(BUILD_SPI_MI_DYNAMIC)
+#if defined(ADI_DEBUG)
+#warning "BUILD_SPI_MI_DYNAMIC is defined.  Memory allocation for SPI will be dynamic"
+int adi_spi_memtype = 0;
+#endif
+#else
+ADI_SPI_HANDLE      spi_Handle0;
+uint8_t             spi_Mem0[ADI_SPI_MEMORY_SIZE];
+ADI_SPI_HANDLE      spi_Handle1;
+uint8_t             spi_Mem1[ADI_SPI_MEMORY_SIZE];
+ADI_SPI_HANDLE      spi_Handle2;
+uint8_t             spi_Mem2[ADI_SPI_MEMORY_SIZE];
+#if defined(ADI_DEBUG)
+#warning "BUILD_SPI_MI_DYNAMIC is NOT defined.  Memory allocation for SPI will be static"
+int adi_spi_memtype = 1;
+#endif
+#endif
+
+
+
+/** Initialize the SPI peripheral
+ *
+ * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
+ * @param[out] obj  The SPI object to initialize
+ * @param[in]  mosi The pin to use for MOSI
+ * @param[in]  miso The pin to use for MISO
+ * @param[in]  sclk The pin to use for SCLK
+ * @param[in]  ssel The pin to use for SSEL
+ */
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
+    // determine the SPI to use
+    uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
+    uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+    uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
+    uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
+    ADI_SPI_HANDLE      *pSPI_Handle;
+    uint8_t             *SPI_Mem;
+    ADI_SPI_RESULT      SPI_Return = ADI_SPI_SUCCESS;
+    uint32_t            nDeviceNum = 0;
+    ADI_SPI_CHIP_SELECT spi_cs = ADI_SPI_CS_NONE;
+
+
+#if defined(BUILD_SPI_MI_DYNAMIC)
+    if (mosi == SPI0_MOSI) {
+        nDeviceNum = SPI_0;
+    } else if (mosi == SPI1_MOSI) {
+        nDeviceNum = SPI_1;
+    } else if (mosi == SPI2_MOSI) {
+        nDeviceNum = SPI_2;
+    }
+    pSPI_Handle = &obj->SPI_Handle;
+    obj->pSPI_Handle = pSPI_Handle;
+    SPI_Mem = obj->SPI_Mem;
+#else
+    if (mosi == SPI0_MOSI) {
+        nDeviceNum = SPI_0;
+        pSPI_Handle = &spi_Handle0;
+        SPI_Mem = &spi_Mem0[0];
+    } else if (mosi == SPI1_MOSI) {
+        nDeviceNum = SPI_1;
+        pSPI_Handle = &spi_Handle1;
+        SPI_Mem = &spi_Mem1[0];
+    } else if (mosi == SPI2_MOSI) {
+        nDeviceNum = SPI_2;
+        pSPI_Handle = &spi_Handle2;
+        SPI_Mem = &spi_Mem2[0];
+    }
+    obj->pSPI_Handle    = pSPI_Handle;
+#endif
+
+
+    obj->instance = pinmap_merge(spi_data, spi_cntl);
+    MBED_ASSERT((int)obj->instance != NC);
+
+    // pin out the spi pins
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+    if (ssel != NC) {
+        pinmap_pinout(ssel, PinMap_SPI_SSEL);
+    }
+
+    SystemCoreClockUpdate();
+    SPI_Return = adi_spi_Open(nDeviceNum, SPI_Mem, ADI_SPI_MEMORY_SIZE, pSPI_Handle);
+    if (SPI_Return) {
+        obj->error = SPI_EVENT_ERROR;
+        return;
+    }
+
+    if (ssel != NC) {
+        if ( (ssel == SPI0_CS0) || (ssel == SPI1_CS0) || (ssel == SPI2_CS0)) {
+            spi_cs = ADI_SPI_CS0;
+        } else if ( (ssel == SPI0_CS1) || (ssel == SPI1_CS1) || (ssel == SPI2_CS1)) {
+            spi_cs = ADI_SPI_CS1;
+        } else if ( (ssel == SPI0_CS2) || (ssel == SPI1_CS2) || (ssel == SPI2_CS2)) {
+            spi_cs = ADI_SPI_CS2;
+        } else if ( (ssel == SPI0_CS3) || (ssel == SPI1_CS3) || (ssel == SPI2_CS3)) {
+            spi_cs = ADI_SPI_CS3;
+        }
+
+        SPI_Return = adi_spi_SetChipSelect(*pSPI_Handle, spi_cs);
+        if (SPI_Return) {
+            obj->error = SPI_EVENT_ERROR;
+            return;
+        }
+    }
+}
+
+
+/** Release a SPI object
+ *
+ * TODO: spi_free is currently unimplemented
+ * This will require reference counting at the C++ level to be safe
+ *
+ * Return the pins owned by the SPI object to their reset state
+ * Disable the SPI peripheral
+ * Disable the SPI clock
+ * @param[in] obj The SPI object to deinitialize
+ */
+void spi_free(spi_t *obj)
+{
+    ADI_SPI_HANDLE  SPI_Handle;
+    ADI_SPI_RESULT  SPI_Return = ADI_SPI_SUCCESS;
+
+    SPI_Handle = *obj->pSPI_Handle;
+    SPI_Return = adi_spi_Close(SPI_Handle);
+    if (SPI_Return) {
+        obj->error = SPI_EVENT_ERROR;
+        return;
+    }
+}
+
+
+/** Configure the SPI format
+ *
+ * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
+ * The default bit order is MSB.
+ * @param[in,out] obj   The SPI object to configure
+ * @param[in]     bits  The number of bits per frame
+ * @param[in]     mode  The SPI mode (clock polarity, phase, and shift direction)
+ * @param[in]     slave Zero for master mode or non-zero for slave mode
+ *
+ ** Configure the data transmission format
+ *
+ *  @param bits Number of bits per SPI frame (4 - 16)
+ *  @param mode Clock polarity and phase mode (0 - 3)
+ *
+ * @code
+ * mode | POL PHA
+ * -----+--------
+ *   0  |  0   0
+ *   1  |  0   1
+ *   2  |  1   0
+ *   3  |  1   1
+ * @endcode
+
+    bool          phase;
+        true  : trailing-edge
+        false : leading-edge
+
+    bool          polarity;
+        true  : CPOL=1 (idle high) polarity
+        false : CPOL=0 (idle-low) polarity
+ */
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+    ADI_SPI_HANDLE  SPI_Handle;
+    ADI_SPI_RESULT  SPI_Return = ADI_SPI_SUCCESS;
+    bool          phase;
+    bool          polarity;
+    bool          master;
+
+
+    SPI_Handle = *obj->pSPI_Handle;
+
+    if ((uint32_t)mode & 0x1) {
+        phase = true;
+    }
+    else {
+        phase = false;
+    }
+    SPI_Return = adi_spi_SetClockPhase(SPI_Handle, phase);
+    if (SPI_Return) {
+        obj->error = SPI_EVENT_ERROR;
+        return;
+    }
+
+    if ((uint32_t)mode & 0x2) {
+        polarity = true;
+    }
+    else {
+        polarity = false;
+    }
+    SPI_Return = adi_spi_SetClockPolarity(SPI_Handle, polarity);
+    if (SPI_Return) {
+        obj->error = SPI_EVENT_ERROR;
+        return;
+    }
+
+    master = !((bool)slave);
+    SPI_Return = adi_spi_SetMasterMode(SPI_Handle, master);
+    if (SPI_Return) {
+        obj->error = SPI_EVENT_ERROR;
+        return;
+    }
+}
+
+
+/** Set the SPI baud rate
+ *
+ * Actual frequency may differ from the desired frequency due to available dividers and bus clock
+ * Configures the SPI peripheral's baud rate
+ * @param[in,out] obj The SPI object to configure
+ * @param[in]     hz  The baud rate in Hz
+ */
+void spi_frequency(spi_t *obj, int hz)
+{
+    ADI_SPI_HANDLE  SPI_Handle;
+    ADI_SPI_RESULT  SPI_Return = ADI_SPI_SUCCESS;
+
+    SPI_Handle = *obj->pSPI_Handle;
+    SPI_Return = adi_spi_SetBitrate(SPI_Handle, (uint32_t) hz);
+    if (SPI_Return) {
+        obj->error = SPI_EVENT_ERROR;
+        return;
+    }
+}
+
+
+/** Write a byte out in master mode and receive a value
+ *
+ * @param[in] obj   The SPI peripheral to use for sending
+ * @param[in] value The value to send
+ * @return Returns the value received during send
+ */
+int spi_master_write(spi_t *obj, int value)
+{
+    ADI_SPI_TRANSCEIVER transceive;
+    uint8_t         TxBuf;
+    uint8_t         RxBuf;
+    ADI_SPI_HANDLE  SPI_Handle;
+    ADI_SPI_RESULT  SPI_Return = ADI_SPI_SUCCESS;
+
+    TxBuf = (uint8_t)value;
+
+    transceive.pReceiver        = &RxBuf;
+    transceive.ReceiverBytes    = 1;        /* link transceive data size to the remaining count */
+    transceive.nRxIncrement     = 1;        /* auto increment buffer */
+    transceive.pTransmitter     = &TxBuf;   /* initialize data attributes */
+    transceive.TransmitterBytes = 1;        /* link transceive data size to the remaining count */
+    transceive.nTxIncrement     = 1;        /* auto increment buffer */
+
+    transceive.bDMA = false;
+    transceive.bRD_CTL = false;
+    SPI_Handle = *obj->pSPI_Handle;
+    SPI_Return = adi_spi_MasterReadWrite(SPI_Handle, &transceive);
+    if (SPI_Return) {
+        obj->error = SPI_EVENT_ERROR;
+        return 1;
+    }
+
+    return((int)RxBuf);
+}
+
+
+/** Write a block out in master mode and receive a value
+ *
+ *  The total number of bytes sent and recieved will be the maximum of
+ *  tx_length and rx_length. The bytes written will be padded with the
+ *  value 0xff.
+ *
+ * @param[in] obj        The SPI peripheral to use for sending
+ * @param[in] tx_buffer  Pointer to the byte-array of data to write to the device
+ * @param[in] tx_length  Number of bytes to write, may be zero
+ * @param[in] rx_buffer  Pointer to the byte-array of data to read from the device
+ * @param[in] rx_length  Number of bytes to read, may be zero
+ * @param[in] write_fill Default data transmitted while performing a read
+ * @returns
+ *      The number of bytes written and read from the device. This is
+ *      maximum of tx_length and rx_length.
+ */
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill)
+{
+    ADI_SPI_TRANSCEIVER transceive;
+    ADI_SPI_HANDLE  SPI_Handle;
+    ADI_SPI_RESULT  SPI_Return = ADI_SPI_SUCCESS;
+
+    transceive.pReceiver        = (uint8_t*)rx_buffer;
+    transceive.ReceiverBytes    = rx_length;            /* link transceive data size to the remaining count */
+    transceive.nRxIncrement     = 1;                    /* auto increment buffer */
+    transceive.pTransmitter     = (uint8_t*)tx_buffer;  /* initialize data attributes */
+    transceive.TransmitterBytes = tx_length;            /* link transceive data size to the remaining count */
+    transceive.nTxIncrement     = 1;                    /* auto increment buffer */
+
+    transceive.bDMA = false;
+    transceive.bRD_CTL = false;
+    SPI_Handle = *obj->pSPI_Handle;
+    SPI_Return = adi_spi_MasterReadWrite(SPI_Handle, &transceive);
+    if (SPI_Return) {
+        obj->error = SPI_EVENT_ERROR;
+        return -1;
+    }
+    else {
+        return((int)tx_length);
+    }
+}
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/trng_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/trng_api.c
new file mode 100755
index 00000000000..24dadb02f29
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/trng_api.c
@@ -0,0 +1,136 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#if defined(DEVICE_TRNG)
+
+#include <stdlib.h>
+#include <drivers/rng/adi_rng.h>
+#include <drivers/pwr/adi_pwr.h>
+#include "adi_rng_def.h"
+#include "cmsis.h"
+#include "trng_api.h"
+#include "objects.h"
+
+// Sampling counter values
+// Prescaler: 0 - 10
+// LenReload: 0 - 4095
+#define TRNG_CNT_VAL    4095
+#define TRNG_PRESCALER  2
+
+/* RNG Device memory */
+static uint32_t RngDevMem[(ADI_RNG_MEMORY_SIZE + 3)/4];
+
+void trng_init(trng_t *obj)
+{
+    ADI_RNG_HANDLE RNGhDevice;
+
+    // Open the device
+    adi_rng_Open(0,RngDevMem,sizeof(RngDevMem),&RNGhDevice);
+
+    // Set sample length for the H/W RN accumulator
+    adi_rng_SetSampleLen(RNGhDevice, TRNG_PRESCALER, TRNG_CNT_VAL);
+
+    // Disable buffering - single byte generation only
+    adi_rng_EnableBuffering(RNGhDevice, false);
+
+    // Enable the TRNG
+    adi_rng_Enable(RNGhDevice, true);
+
+    // Save device handle
+    obj->RNGhDevice = RNGhDevice;
+}
+
+void trng_free(trng_t *obj)
+{
+    ADI_RNG_HANDLE RNGhDevice = obj->RNGhDevice;
+
+    adi_rng_Enable(RNGhDevice, false);
+    adi_rng_Close(RNGhDevice);
+}
+
+int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
+{
+    ADI_RNG_HANDLE RNGhDevice = obj->RNGhDevice;
+    bool bRNGRdy, bStuck;
+    uint32_t i;
+    volatile uint32_t nRandomNum;
+    ADI_RNG_RESULT result;
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)RNGhDevice;
+
+    for (i = 0; i < length; i++) {
+        // Loop until the device has data to be read
+        do {
+            result = adi_rng_GetRdyStatus(RNGhDevice, &bRNGRdy);
+            if (result != ADI_RNG_SUCCESS) {
+                return -1;
+            }
+        } while (!bRNGRdy);
+
+        // Check the STUCK bit to make sure the oscillator output isn't stuck
+        result = adi_rng_GetStuckStatus(RNGhDevice, &bStuck);
+
+        // If the stuck bit is set, this means there may be a problem with RNG hardware,
+        // exit with an error
+        if ( (result != ADI_RNG_SUCCESS) || ((result == ADI_RNG_SUCCESS) && (bStuck)) ) {
+            // Clear the STUCK bit by writing a 1 to it
+            pDevice->pRNG->STAT |= BITM_RNG_STAT_STUCK;
+            return -1;
+        }
+
+        // Read the RNG
+        result = adi_rng_GetRngData(RNGhDevice, (uint32_t*)(&nRandomNum));
+
+        if (result != ADI_RNG_SUCCESS) {
+            return -1;
+        }
+
+        // Save the output
+        output[i] = (uint8_t)(nRandomNum & 0xFF);
+    }
+
+    *output_length = length;
+
+    // Clear nRandomNum on the stack before exiting
+    nRandomNum = 0;
+
+    return 0;
+}
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/us_ticker.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/us_ticker.c
new file mode 100755
index 00000000000..82ca488f5f5
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/us_ticker.c
@@ -0,0 +1,348 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include <stdint.h>
+#include <stdio.h>
+#include <drivers/tmr/adi_tmr.h>
+#include <drivers/pwr/adi_pwr.h>
+#include <drivers/gpio/adi_gpio.h>
+
+#ifndef BITM_TMR_RGB_CTL_EN
+#define BITM_TMR_RGB_CTL_EN BITM_TMR_CTL_EN
+#endif
+
+typedef uint32_t timestamp_t;
+
+// defined in mbed_us_ticker_api.c which calls the ticker_irq_handler() routine
+// defined in mbed_ticker_api.c
+void us_ticker_irq_handler(void);
+
+static int us_ticker_inited = 0;
+
+static ADI_TMR_CONFIG tmrConfig, tmr2Config;
+
+static volatile uint32_t Upper_count = 0, largecnt = 0;
+
+static ADI_TMR_TypeDef * adi_tmr_registers[ADI_TMR_DEVICE_NUM] = {pADI_TMR0, pADI_TMR1, pADI_TMR2};
+
+#if defined(__ADUCM302x__)
+    static const IRQn_Type adi_tmr_interrupt[ADI_TMR_DEVICE_NUM] = {TMR0_EVT_IRQn, TMR1_EVT_IRQn, TMR2_EVT_IRQn};
+#elif defined(__ADUCM4x50__)
+    static const IRQn_Type adi_tmr_interrupt[ADI_TMR_DEVICE_NUM] = {TMR0_EVT_IRQn, TMR1_EVT_IRQn, TMR2_EVT_IRQn, TMR_RGB_EVT_IRQn};
+#else
+#error TMR is not ported for this processor
+#endif
+
+
+/*---------------------------------------------------------------------------*
+   Local functions
+ *---------------------------------------------------------------------------*/
+static void GP1CallbackFunction(void *pCBParam, uint32_t Event, void  * pArg)
+{
+    Upper_count++;
+}
+
+
+static uint32_t get_current_time(void)
+{
+    uint16_t tmrcnt0, tmrcnt1;
+    uint32_t totaltmr0, totaltmr1;
+    uint32_t uc1, tmrpend0, tmrpend1;
+
+    do {
+        volatile uint32_t *ucptr = &Upper_count;
+
+        /*
+         * Carefully coded to prevent race conditions.  Do not make changes unless you understand all the
+         * implications.
+         *
+         * Note this function can be called with interrupts globally disabled or enabled.  It has been coded to work in both cases.
+         *
+         * TMR0 and TMR1 both run from the same synchronous clock. TMR0 runs at 26MHz and TMR1 runs at 26/256MHz.
+         * TMR1 generates an interrupt every time it overflows its 16 bit counter.  TMR0 runs faster and provides
+         * the lowest 8 bits of the current time count.  When TMR0 and TMR1 are combined, they provide 24 bits of
+         * timer precision. i.e. (TMR0.CURCNT & 0xff) + (TMR1.CURCNT << 8)
+         *
+         * There are several race conditions protected against:
+         * 1. TMR0 and TMR1 are both read at the same time, however, on rare occasions, one will have incremented before the other.
+         * Therefore we read both timer counters, and check if the middle 8 bits match, if they don't then read the counts again
+         * until they do.  This ensures that one or the other counters are stable with respect to each other.
+         *
+         * 2. TMR1.CURCNT and Upper_count racing. Prevent this by disabling the TMR1 interrupt, which stops Upper_count increment interrupt (GP1CallbackFunction).
+         * Then check pending bit of TMR1 to see if we missed Upper_count interrupt, and add it manually later.
+         *
+         * 3. Race between the TMR1 pend, and the TMR1.CURCNT read.  Even with TMR1 interrupt disabled, the pend bit
+         * may be set while TMR1.CURCNT is being read.  We don't know if the pend bit matches the TMR1 state.
+         * To prevent this, the pending bit is read twice, and we see if it matches; if it doesn't, loop around again.
+         *
+         * Note the TMR1 interrupt is enabled on each iteration of the loop to flush out any pending TMR1 interrupt,
+         * thereby clearing any TMR1 pend's.  This have no effect if this routine is called with interrupts globally disabled.
+         */
+
+        NVIC_DisableIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]);     // Prevent Upper_count increment
+        tmrpend0 = NVIC_GetPendingIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]);
+                                                                    // Check if there is a pending interrupt for timer 1
+
+        __DMB();                                                    // memory barrier: read GP0 before GP1
+
+        tmrcnt0 = adi_tmr_registers[ADI_TMR_DEVICE_GP0]->CURCNT;    // to minimize skew, read both timers manually
+
+        __DMB();                                                    // memory barrier: read GP0 before GP1
+
+        tmrcnt1 = adi_tmr_registers[ADI_TMR_DEVICE_GP1]->CURCNT;    // read both timers manually
+
+        totaltmr0 = tmrcnt0;                                        // expand to u32 bits
+        totaltmr1 = tmrcnt1;                                        // expand to u32 bits
+
+        tmrcnt0 &= 0xff00u;
+        tmrcnt1 <<= 8;
+
+        __DMB();
+
+        uc1 = *ucptr;                                               // Read Upper_count
+
+        tmrpend1 = NVIC_GetPendingIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]);
+                    // Check for a pending interrupt again.  Only leave loop if they match
+
+        NVIC_EnableIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]);      // enable interrupt on every loop to allow TMR1 interrupt to run
+    } while ((tmrcnt0 != tmrcnt1) || (tmrpend0 != tmrpend1));
+
+    totaltmr1 <<= 8;                 // Timer1 runs 256x slower
+    totaltmr1 += totaltmr0 & 0xffu;  // Use last 8 bits of Timer0 as it runs faster
+                                     // totaltmr1 now contain 24 bits of significance
+
+    if (tmrpend0) {                  // If an interrupt is pending, then increment local copy of upper count
+        uc1++;
+    }
+
+    uint64_t Uc = totaltmr1;         // expand out to 64 bits unsigned
+    Uc += ((uint64_t) uc1) << 24;    // Add on the upper count to get the full precision count
+
+                                     // Divide Uc by 26 (26MHz converted to 1MHz) todo scale for other clock freqs
+
+    Uc *= 1290555u;                  // Divide total(1/26) << 25
+    Uc >>= 25;                       // shift back.  Fixed point avoid use of floating point divide.
+                                     // Compiler does this inline using shifts and adds.
+
+    return Uc;
+}
+
+
+static void calc_event_counts(uint32_t timestamp)
+{
+    uint32_t calc_time, blocks, offset;
+    uint64_t aa;
+
+    calc_time = get_current_time();
+    offset = timestamp - calc_time; // offset in useconds
+
+    if (offset > 0xf0000000u)       // if offset is a really big number, assume that timer has already expired (i.e. negative)
+        offset = 0u;
+
+    if (offset > 10u) {             // it takes 10us to user timer routine after interrupt.  Offset timer to account for that.
+        offset -= 10u;
+    } else
+        offset = 0u;
+
+    aa = (uint64_t) offset;
+    aa *= 26u;                      // convert from 1MHz to 26MHz clock. todo scale for other clock freqs
+
+    blocks = aa >> 7;
+    blocks++;                       // round
+
+    largecnt = blocks>>1;           // communicate to event_timer() routine
+}
+
+static void event_timer()
+{
+    if (largecnt) {
+        uint32_t cnt = largecnt;
+
+        if (cnt > 65535u) {
+            cnt = 0u;
+        } else {
+            cnt = 65536u - cnt;
+        }
+
+        tmr2Config.nLoad        = cnt;
+        tmr2Config.nAsyncLoad   = cnt;
+        adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP2, &tmr2Config);
+        adi_tmr_Enable(ADI_TMR_DEVICE_GP2, true);
+    } else {
+        us_ticker_irq_handler();
+    }
+}
+
+
+/*
+ * Interrupt routine for timer 2
+ *
+ * largecnt counts how many timer ticks should be counted to reach timer event.
+ * Each interrupt happens every 65536 timer ticks, unless there are less than 65536 ticks to count.
+ * In that case do the remaining timers ticks.
+ *
+ * largecnt is a global that is used to communicate between event_timer and the interrupt routine
+ * On entry, largecnt will be any value larger than 0.
+ */
+static void GP2CallbackFunction(void *pCBParam, uint32_t Event, void  * pArg)
+{
+    if (largecnt >= 65536u) {
+        largecnt -= 65536u;
+    } else {
+        largecnt = 0;
+    }
+
+    if (largecnt < 65536u) {
+        adi_tmr_Enable(ADI_TMR_DEVICE_GP2, false);
+        event_timer();
+    }
+}
+
+
+/*---------------------------------------------------------------------------*
+   us_ticker HAL APIs
+ *---------------------------------------------------------------------------*/
+void us_ticker_init(void)
+{
+    if (us_ticker_inited) {
+        return;
+    }
+
+    us_ticker_inited = 1;
+
+    /*--------------------- GP TIMER INITIALIZATION --------------------------*/
+
+    /* Set up GP0 callback function */
+    adi_tmr_Init(ADI_TMR_DEVICE_GP0, NULL, NULL, false);
+
+    /* Set up GP1 callback function */
+    adi_tmr_Init(ADI_TMR_DEVICE_GP1, GP1CallbackFunction, NULL, true);
+
+    /* Set up GP1 callback function */
+    adi_tmr_Init(ADI_TMR_DEVICE_GP2, GP2CallbackFunction, NULL, true);
+
+    /* Configure GP0 to run at 26MHz */
+    tmrConfig.bCountingUp  = true;
+    tmrConfig.bPeriodic    = true;
+    tmrConfig.ePrescaler   = ADI_TMR_PRESCALER_1;     // TMR0 at 26MHz
+    tmrConfig.eClockSource = ADI_TMR_CLOCK_PCLK;      // TMR source is PCLK (most examples use HFOSC)
+    tmrConfig.nLoad        = 0;
+    tmrConfig.nAsyncLoad   = 0;
+    tmrConfig.bReloading   = false;
+    tmrConfig.bSyncBypass  = true;                    // Allow x1 prescale: requires PCLK as a clk
+    adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP0, &tmrConfig);
+
+    /* Configure GP1 to have a period 256 times longer than GP0 */
+    tmrConfig.nLoad        = 0;
+    tmrConfig.nAsyncLoad   = 0;
+    tmrConfig.ePrescaler   = ADI_TMR_PRESCALER_256;    // TMR1 = 26MHz/256
+    adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP1, &tmrConfig);
+
+    /* Configure GP2 for doing event counts */
+    tmr2Config.bCountingUp  = true;
+    tmr2Config.bPeriodic    = true;
+    tmr2Config.ePrescaler   = ADI_TMR_PRESCALER_256;   // TMR2 at 26MHz/256
+    tmr2Config.eClockSource = ADI_TMR_CLOCK_PCLK;      // TMR source is PCLK (most examples use HFOSC)
+    tmr2Config.nLoad        = 0;
+    tmr2Config.nAsyncLoad   = 0;
+    tmr2Config.bReloading   = false;
+    tmr2Config.bSyncBypass  = true;                    // Allow x1 prescale
+    adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP2, &tmr2Config);
+
+
+    /*------------------------- GP TIMER ENABLE ------------------------------*/
+
+    /* Manually enable both timers to get them started at the same time
+     *
+     */
+    adi_tmr_registers[ADI_TMR_DEVICE_GP0]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_EN;
+    adi_tmr_registers[ADI_TMR_DEVICE_GP1]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_EN;
+}
+
+uint32_t us_ticker_read()
+{
+    uint32_t curr_time;
+
+    if (!us_ticker_inited) {
+        us_ticker_init();
+    }
+
+    curr_time = get_current_time();
+
+    return curr_time;
+}
+
+void us_ticker_disable_interrupt(void)
+{
+    adi_tmr_Enable(ADI_TMR_DEVICE_GP2, false);
+}
+
+void us_ticker_clear_interrupt(void)
+{
+    NVIC_ClearPendingIRQ(TMR2_EVT_IRQn);
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+
+    /* timestamp is when interrupt should fire.
+     *
+     * This MUST not be called if another timer event is currently enabled.
+     *
+     */
+    calc_event_counts(timestamp);             // use timestamp to calculate largecnt to control number of timer interrupts
+    event_timer();                            // uses largecnt to initiate timer interrupts
+}
+
+/** Set pending interrupt that should be fired right away.
+ *
+ * The ticker should be initialized prior calling this function.
+ *
+ * This MUST not be called if another timer event is currently enabled.
+ */
+void us_ticker_fire_interrupt(void)
+{
+    NVIC_SetPendingIRQ(TMR2_EVT_IRQn);
+}
+
+
+/*
+** EOF
+*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029.h
new file mode 100755
index 00000000000..df6d8c7ee6e
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029.h
@@ -0,0 +1,61 @@
+/**************************************************************************//**
+ * @file     ADuCM3029.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
+ *           Device ADuCM3029
+ * @version  V3.10
+ * @date     23. November 2012
+ *
+ * @note     Modified 14. November 2016 Analog Devices
+ *
+ ******************************************************************************/
+/* Copyright (c) 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   
+   Portions Copyright (c) 2016 Analog Devices, Inc.
+   ---------------------------------------------------------------------------*/
+
+#ifndef ADUCM3029_H
+#define ADUCM3029_H
+
+#ifndef __ADUCM30xx__
+#define __ADUCM30xx__ /*!< PreProcessor feature macro */
+#endif
+
+#include <ADuCM3029_cdef.h>
+#include <ADuCM3029_device.h>
+
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __CM3_REV                 0x0201u   /*!< Core Revision r2p1                               */
+#define __NVIC_PRIO_BITS          3u        /*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
+#define __MPU_PRESENT             1u        /*!< MPU present                                      */
+#define __FPU_PRESENT             0u        /*!< FPU not present                                  */
+
+#include <core_cm3.h>                       /* Cortex-M3 processor and core peripherals           */
+
+#include "system_ADuCM3029.h"
+
+#endif  /* ADUCM3029_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_cdef.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_cdef.h
new file mode 100755
index 00000000000..44595e97e08
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_cdef.h
@@ -0,0 +1,112 @@
+/*!
+*****************************************************************************
+ * @file:    ADuCM3029_cdef.h
+ * @brief:   ADuCM3029 C MMR Pointer Definitions
+ * @version: $Revision: 36179 $
+ * @date:    $Date: 2017-02-10 09:56:54 -0500 (Fri, 10 Feb 2017) $
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2015-2017 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef _WRAP_ADUCM3029_CDEF_H
+#define _WRAP_ADUCM3029_CDEF_H
+
+#include <ADuCM3029_def.h>
+
+#include <stdint.h>
+
+#ifdef __ICCARM__
+/* IAR MISRA C 2004 error suppressions:
+ *
+ * Pm081 (rule 19.6): #undef should not be used
+ *   Needed to work around incorrect definitions in sys/ADuCM302x_cdef.h.
+ */
+#pragma diag_suppress=Pm081
+#endif /* __ICCARM__ */
+
+#include <sys/adi_cio_macros.h>
+#include <sys/ADuCM302x_cdef.h>
+
+
+/* Backward compatibility shims for renamed UART registers. */
+
+#define pREG_UART0_COMRX   (pREG_UART0_RX)
+#define pREG_UART0_COMTX   (pREG_UART0_TX)
+#define pREG_UART0_COMIEN  (pREG_UART0_IEN)
+#define pREG_UART0_COMIIR  (pREG_UART0_IIR)
+#define pREG_UART0_COMLCR  (pREG_UART0_LCR)
+#define pREG_UART0_COMMCR  (pREG_UART0_MCR)
+#define pREG_UART0_COMLSR  (pREG_UART0_LSR)
+#define pREG_UART0_COMMSR  (pREG_UART0_MSR)
+#define pREG_UART0_COMSCR  (pREG_UART0_SCR)
+#define pREG_UART0_COMFCR  (pREG_UART0_FCR)
+#define pREG_UART0_COMFBR  (pREG_UART0_FBR)
+#define pREG_UART0_COMDIV  (pREG_UART0_DIV)
+#define pREG_UART0_COMLCR2 (pREG_UART0_LCR2)
+#define pREG_UART0_COMCTL  (pREG_UART0_CTL)
+#define pREG_UART0_COMRFC  (pREG_UART0_RFC)
+#define pREG_UART0_COMTFC  (pREG_UART0_TFC)
+#define pREG_UART0_COMRSC  (pREG_UART0_RSC)
+#define pREG_UART0_COMACR  (pREG_UART0_ACR)
+#define pREG_UART0_COMASRL (pREG_UART0_ASRL)
+#define pREG_UART0_COMASRH (pREG_UART0_ASRH)
+
+
+/* Backward compatibility shim for renamed RTC registers and fields. */
+
+#define pREG_RTC0_CR3OC  (pREG_RTC0_CR3SS)
+#define pREG_RTC0_CR4OC  (pREG_RTC0_CR4SS)
+#define pREG_RTC0_OCMSK  (pREG_RTC0_SSMSK)
+#define pREG_RTC0_OC1ARL (pREG_RTC0_SS1ARL)
+#define pREG_RTC0_OC1    (pREG_RTC0_SS1)
+#define pREG_RTC0_OC1TGT (pREG_RTC0_SS1TGT)
+#define pREG_RTC1_CR3OC  (pREG_RTC1_CR3SS)
+#define pREG_RTC1_CR4OC  (pREG_RTC1_CR4SS)
+#define pREG_RTC1_OCMSK  (pREG_RTC1_SSMSK)
+#define pREG_RTC1_OC1ARL (pREG_RTC1_SS1ARL)
+#define pREG_RTC1_OC1    (pREG_RTC1_SS1)
+#define pREG_RTC1_OC1TGT (pREG_RTC1_SS1TGT)
+
+
+#ifdef __ICCARM__
+#pragma diag_default=Pm081
+#endif /* __ICCARM__ */
+
+#endif /* _WRAP_ADUCM3029_CDEF_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_def.h
new file mode 100755
index 00000000000..dd19873c3a0
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_def.h
@@ -0,0 +1,370 @@
+/*!
+*****************************************************************************
+ * @file:    ADuCM3029_def.h
+ * @brief:   ADuCM3029 MMR addresses and fields
+ * @version: $Revision: 36179 $
+ * @date:    $Date: 2017-02-10 09:56:54 -0500 (Fri, 10 Feb 2017) $
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2015-2017 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef _WRAP_ADUCM3029_DEF_H
+#define _WRAP_ADUCM3029_DEF_H
+
+#ifdef __ICCARM__
+/* IAR MISRA C 2004 error suppressions:
+ *
+ * Pm008 (rule 2.4): sections of code should not be 'commented out'.
+ *   Some comments are wrongly identified as code.
+ *
+ * Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters.
+ *   The sys/ADuCM302x.h header relies on more. The IAR compiler supports that.
+ */
+#pragma diag_suppress=Pm008,Pm009
+#endif /* __ICCARM__ */
+
+#ifdef __IASMARM__
+/* Define masks to plain numeric literal for IAR assembler. */
+#define _ADI_MSK_3( mask, smask, type ) (mask)
+#endif /* __IASMARM__ */
+
+#include <sys/ADuCM302x.h>
+
+/* Backward compatibility shims for renamed UART registers. */
+
+#define REG_UART0_COMRX   (REG_UART0_RX)
+#define REG_UART0_COMTX   (REG_UART0_TX)
+#define REG_UART0_COMIEN  (REG_UART0_IEN)
+#define REG_UART0_COMIIR  (REG_UART0_IIR)
+#define REG_UART0_COMLCR  (REG_UART0_LCR)
+#define REG_UART0_COMMCR  (REG_UART0_MCR)
+#define REG_UART0_COMLSR  (REG_UART0_LSR)
+#define REG_UART0_COMMSR  (REG_UART0_MSR)
+#define REG_UART0_COMSCR  (REG_UART0_SCR)
+#define REG_UART0_COMFCR  (REG_UART0_FCR)
+#define REG_UART0_COMFBR  (REG_UART0_FBR)
+#define REG_UART0_COMDIV  (REG_UART0_DIV)
+#define REG_UART0_COMLCR2 (REG_UART0_LCR2)
+#define REG_UART0_COMCTL  (REG_UART0_CTL)
+#define REG_UART0_COMRFC  (REG_UART0_RFC)
+#define REG_UART0_COMTFC  (REG_UART0_TFC)
+#define REG_UART0_COMRSC  (REG_UART0_RSC)
+#define REG_UART0_COMACR  (REG_UART0_ACR)
+#define REG_UART0_COMASRL (REG_UART0_ASRL)
+#define REG_UART0_COMASRH (REG_UART0_ASRH)
+
+#define BITP_UART_COMRX_RBR         (BITP_UART_RX_RBR)
+#define BITP_UART_COMTX_THR         (BITP_UART_TX_THR)
+#define BITP_UART_COMIEN_EDMAR      (BITP_UART_IEN_EDMAR)
+#define BITP_UART_COMIEN_EDMAT      (BITP_UART_IEN_EDMAT)
+#define BITP_UART_COMIEN_EDSSI      (BITP_UART_IEN_EDSSI)
+#define BITP_UART_COMIEN_ELSI       (BITP_UART_IEN_ELSI)
+#define BITP_UART_COMIEN_ETBEI      (BITP_UART_IEN_ETBEI)
+#define BITP_UART_COMIEN_ERBFI      (BITP_UART_IEN_ERBFI)
+#define BITP_UART_COMIIR_FEND       (BITP_UART_IIR_FEND)
+#define BITP_UART_COMIIR_STA        (BITP_UART_IIR_STAT)
+#define BITP_UART_COMIIR_NIRQ       (BITP_UART_IIR_NIRQ)
+#define BITP_UART_COMLCR_BRK        (BITP_UART_LCR_BRK)
+#define BITP_UART_COMLCR_SP         (BITP_UART_LCR_SP)
+#define BITP_UART_COMLCR_EPS        (BITP_UART_LCR_EPS)
+#define BITP_UART_COMLCR_PEN        (BITP_UART_LCR_PEN)
+#define BITP_UART_COMLCR_STOP       (BITP_UART_LCR_STOP)
+#define BITP_UART_COMLCR_WLS        (BITP_UART_LCR_WLS)
+#define BITP_UART_COMMCR_LOOPBACK   (BITP_UART_MCR_LOOPBACK)
+#define BITP_UART_COMMCR_OUT2       (BITP_UART_MCR_OUT2)
+#define BITP_UART_COMMCR_OUT1       (BITP_UART_MCR_OUT1)
+#define BITP_UART_COMMCR_RTS        (BITP_UART_MCR_RTS)
+#define BITP_UART_COMMCR_DTR        (BITP_UART_MCR_DTR)
+#define BITP_UART_COMLSR_FIFOERR    (BITP_UART_LSR_FIFOERR)
+#define BITP_UART_COMLSR_TEMT       (BITP_UART_LSR_TEMT)
+#define BITP_UART_COMLSR_THRE       (BITP_UART_LSR_THRE)
+#define BITP_UART_COMLSR_BI         (BITP_UART_LSR_BI)
+#define BITP_UART_COMLSR_FE         (BITP_UART_LSR_FE)
+#define BITP_UART_COMLSR_PE         (BITP_UART_LSR_PE)
+#define BITP_UART_COMLSR_OE         (BITP_UART_LSR_OE)
+#define BITP_UART_COMLSR_DR         (BITP_UART_LSR_DR)
+#define BITP_UART_COMMSR_DCD        (BITP_UART_MSR_DCD)
+#define BITP_UART_COMMSR_RI         (BITP_UART_MSR_RI)
+#define BITP_UART_COMMSR_DSR        (BITP_UART_MSR_DSR)
+#define BITP_UART_COMMSR_CTS        (BITP_UART_MSR_CTS)
+#define BITP_UART_COMMSR_DDCD       (BITP_UART_MSR_DDCD)
+#define BITP_UART_COMMSR_TERI       (BITP_UART_MSR_TERI)
+#define BITP_UART_COMMSR_DDSR       (BITP_UART_MSR_DDSR)
+#define BITP_UART_COMMSR_DCTS       (BITP_UART_MSR_DCTS)
+#define BITP_UART_COMSCR_SCR        (BITP_UART_SCR_SCR)
+#define BITP_UART_COMFCR_RFTRIG     (BITP_UART_FCR_RFTRIG)
+#define BITP_UART_COMFCR_FDMAMD     (BITP_UART_FCR_FDMAMD)
+#define BITP_UART_COMFCR_TFCLR      (BITP_UART_FCR_TFCLR)
+#define BITP_UART_COMFCR_RFCLR      (BITP_UART_FCR_RFCLR)
+#define BITP_UART_COMFCR_FIFOEN     (BITP_UART_FCR_FIFOEN)
+#define BITP_UART_COMFBR_FBEN       (BITP_UART_FBR_FBEN)
+#define BITP_UART_COMFBR_DIVM       (BITP_UART_FBR_DIVM)
+#define BITP_UART_COMFBR_DIVN       (BITP_UART_FBR_DIVN)
+#define BITP_UART_COMDIV_DIV        (BITP_UART_DIV_DIV)
+#define BITP_UART_COMLCR2_OSR       (BITP_UART_LCR2_OSR)
+#define BITP_UART_COMCTL_REV        (BITP_UART_CTL_REV)
+#define BITP_UART_COMCTL_RXINV      (BITP_UART_CTL_RXINV)
+#define BITP_UART_COMCTL_FORCECLKON (BITP_UART_CTL_FORCECLK)
+#define BITP_UART_COMRFC_RFC        (BITP_UART_RFC_RFC)
+#define BITP_UART_COMTFC_TFC        (BITP_UART_TFC_TFC)
+#define BITP_UART_COMRSC_DISTX      (BITP_UART_RSC_DISTX)
+#define BITP_UART_COMRSC_DISRX      (BITP_UART_RSC_DISRX)
+#define BITP_UART_COMRSC_OENSP      (BITP_UART_RSC_OENSP)
+#define BITP_UART_COMRSC_OENP       (BITP_UART_RSC_OENP)
+#define BITP_UART_COMACR_EEC        (BITP_UART_ACR_EEC)
+#define BITP_UART_COMACR_SEC        (BITP_UART_ACR_SEC)
+#define BITP_UART_COMACR_TOIEN      (BITP_UART_ACR_TOIEN)
+#define BITP_UART_COMACR_DNIEN      (BITP_UART_ACR_DNIEN)
+#define BITP_UART_COMACR_ABE        (BITP_UART_ACR_ABE)
+#define BITP_UART_COMASRL_CNT       (BITP_UART_ASRL_CNT)
+#define BITP_UART_COMASRL_NEETO     (BITP_UART_ASRL_NEETO)
+#define BITP_UART_COMASRL_NSETO     (BITP_UART_ASRL_NSETO)
+#define BITP_UART_COMASRL_BRKTO     (BITP_UART_ASRL_BRKTO)
+#define BITP_UART_COMASRL_DONE      (BITP_UART_ASRL_DONE)
+#define BITP_UART_COMASRH_CNT       (BITP_UART_ASRH_CNT)
+
+#define BITM_UART_COMRX_RBR         (BITM_UART_RX_RBR)
+#define BITM_UART_COMTX_THR         (BITM_UART_TX_THR)
+#define BITM_UART_COMIEN_EDMAR      (BITM_UART_IEN_EDMAR)
+#define BITM_UART_COMIEN_EDMAT      (BITM_UART_IEN_EDMAT)
+#define BITM_UART_COMIEN_EDSSI      (BITM_UART_IEN_EDSSI)
+#define BITM_UART_COMIEN_ELSI       (BITM_UART_IEN_ELSI)
+#define BITM_UART_COMIEN_ETBEI      (BITM_UART_IEN_ETBEI)
+#define BITM_UART_COMIEN_ERBFI      (BITM_UART_IEN_ERBFI)
+#define BITM_UART_COMIIR_FEND       (BITM_UART_IIR_FEND)
+#define BITM_UART_COMIIR_STA        (BITM_UART_IIR_STAT)
+#define BITM_UART_COMIIR_NIRQ       (BITM_UART_IIR_NIRQ)
+#define BITM_UART_COMLCR_BRK        (BITM_UART_LCR_BRK)
+#define BITM_UART_COMLCR_SP         (BITM_UART_LCR_SP)
+#define BITM_UART_COMLCR_EPS        (BITM_UART_LCR_EPS)
+#define BITM_UART_COMLCR_PEN        (BITM_UART_LCR_PEN)
+#define BITM_UART_COMLCR_STOP       (BITM_UART_LCR_STOP)
+#define BITM_UART_COMLCR_WLS        (BITM_UART_LCR_WLS)
+#define BITM_UART_COMMCR_LOOPBACK   (BITM_UART_MCR_LOOPBACK)
+#define BITM_UART_COMMCR_OUT2       (BITM_UART_MCR_OUT2)
+#define BITM_UART_COMMCR_OUT1       (BITM_UART_MCR_OUT1)
+#define BITM_UART_COMMCR_RTS        (BITM_UART_MCR_RTS)
+#define BITM_UART_COMMCR_DTR        (BITM_UART_MCR_DTR)
+#define BITM_UART_COMLSR_FIFOERR    (BITM_UART_LSR_FIFOERR)
+#define BITM_UART_COMLSR_TEMT       (BITM_UART_LSR_TEMT)
+#define BITM_UART_COMLSR_THRE       (BITM_UART_LSR_THRE)
+#define BITM_UART_COMLSR_BI         (BITM_UART_LSR_BI)
+#define BITM_UART_COMLSR_FE         (BITM_UART_LSR_FE)
+#define BITM_UART_COMLSR_PE         (BITM_UART_LSR_PE)
+#define BITM_UART_COMLSR_OE         (BITM_UART_LSR_OE)
+#define BITM_UART_COMLSR_DR         (BITM_UART_LSR_DR)
+#define BITM_UART_COMMSR_DCD        (BITM_UART_MSR_DCD)
+#define BITM_UART_COMMSR_RI         (BITM_UART_MSR_RI)
+#define BITM_UART_COMMSR_DSR        (BITM_UART_MSR_DSR)
+#define BITM_UART_COMMSR_CTS        (BITM_UART_MSR_CTS)
+#define BITM_UART_COMMSR_DDCD       (BITM_UART_MSR_DDCD)
+#define BITM_UART_COMMSR_TERI       (BITM_UART_MSR_TERI)
+#define BITM_UART_COMMSR_DDSR       (BITM_UART_MSR_DDSR)
+#define BITM_UART_COMMSR_DCTS       (BITM_UART_MSR_DCTS)
+#define BITM_UART_COMSCR_SCR        (BITM_UART_SCR_SCR)
+#define BITM_UART_COMFCR_RFTRIG     (BITM_UART_FCR_RFTRIG)
+#define BITM_UART_COMFCR_FDMAMD     (BITM_UART_FCR_FDMAMD)
+#define BITM_UART_COMFCR_TFCLR      (BITM_UART_FCR_TFCLR)
+#define BITM_UART_COMFCR_RFCLR      (BITM_UART_FCR_RFCLR)
+#define BITM_UART_COMFCR_FIFOEN     (BITM_UART_FCR_FIFOEN)
+#define BITM_UART_COMFBR_FBEN       (BITM_UART_FBR_FBEN)
+#define BITM_UART_COMFBR_DIVM       (BITM_UART_FBR_DIVM)
+#define BITM_UART_COMFBR_DIVN       (BITM_UART_FBR_DIVN)
+#define BITM_UART_COMDIV_DIV        (BITM_UART_DIV_DIV)
+#define BITM_UART_COMLCR2_OSR       (BITM_UART_LCR2_OSR)
+#define BITM_UART_COMCTL_REV        (BITM_UART_CTL_REV)
+#define BITM_UART_COMCTL_RXINV      (BITM_UART_CTL_RXINV)
+#define BITM_UART_COMCTL_FORCECLKON (BITM_UART_CTL_FORCECLK)
+#define BITM_UART_COMRFC_RFC        (BITM_UART_RFC_RFC)
+#define BITM_UART_COMTFC_TFC        (BITM_UART_TFC_TFC)
+#define BITM_UART_COMRSC_DISTX      (BITM_UART_RSC_DISTX)
+#define BITM_UART_COMRSC_DISRX      (BITM_UART_RSC_DISRX)
+#define BITM_UART_COMRSC_OENSP      (BITM_UART_RSC_OENSP)
+#define BITM_UART_COMRSC_OENP       (BITM_UART_RSC_OENP)
+#define BITM_UART_COMACR_EEC        (BITM_UART_ACR_EEC)
+#define BITM_UART_COMACR_SEC        (BITM_UART_ACR_SEC)
+#define BITM_UART_COMACR_TOIEN      (BITM_UART_ACR_TOIEN)
+#define BITM_UART_COMACR_DNIEN      (BITM_UART_ACR_DNIEN)
+#define BITM_UART_COMACR_ABE        (BITM_UART_ACR_ABE)
+#define BITM_UART_COMASRL_CNT       (BITM_UART_ASRL_CNT)
+#define BITM_UART_COMASRL_NEETO     (BITM_UART_ASRL_NEETO)
+#define BITM_UART_COMASRL_NSETO     (BITM_UART_ASRL_NSETO)
+#define BITM_UART_COMASRL_BRKTO     (BITM_UART_ASRL_BRKTO)
+#define BITM_UART_COMASRL_DONE      (BITM_UART_ASRL_DONE)
+#define BITM_UART_COMASRH_CNT       (BITM_UART_ASRH_CNT)
+
+
+/* Backward compatibility shim for corrected RTC_SR5.WPENDSR3 bit name. */
+
+#define BITP_RTC_SR5_WPNDSR0        (BITP_RTC_SR5_WPENDSR3)
+#define BITM_RTC_SR5_WPNDSR0        (BITM_RTC_SR5_WPENDSR3)
+
+
+/* Backward compatibility shim for renamed RTC registers and fields. */
+
+#define REG_RTC0_CR3OC  (REG_RTC0_CR3SS)
+#define REG_RTC0_CR4OC  (REG_RTC0_CR4SS)
+#define REG_RTC0_OCMSK  (REG_RTC0_SSMSK)
+#define REG_RTC0_OC1ARL (REG_RTC0_SS1ARL)
+#define REG_RTC0_OC1    (REG_RTC0_SS1)
+#define REG_RTC0_OC1TGT (REG_RTC0_SS1TGT)
+#define REG_RTC1_CR3OC  (REG_RTC1_CR3SS)
+#define REG_RTC1_CR4OC  (REG_RTC1_CR4SS)
+#define REG_RTC1_OCMSK  (REG_RTC1_SSMSK)
+#define REG_RTC1_OC1ARL (REG_RTC1_SS1ARL)
+#define REG_RTC1_OC1    (REG_RTC1_SS1)
+#define REG_RTC1_OC1TGT (REG_RTC1_SS1TGT)
+
+#define BITP_RTC_CR1_RTCTRMINTEN   (BITP_RTC_CR1_TRMINTEN)
+#define BITP_RTC_SR3_RTCOC1IRQ     (BITP_RTC_SR3_SS1IRQ)
+#define BITP_RTC_SR3_RTCIC4IRQ     (BITP_RTC_SR3_IC4IRQ)
+#define BITP_RTC_SR3_RTCIC3IRQ     (BITP_RTC_SR3_IC3IRQ)
+#define BITP_RTC_SR3_RTCIC2IRQ     (BITP_RTC_SR3_IC2IRQ)
+#define BITP_RTC_SR3_RTCIC0IRQ     (BITP_RTC_SR3_IC0IRQ)
+#define BITP_RTC_CR2IC_RTCICOWUSEN (BITP_RTC_CR2IC_ICOWUSEN)
+#define BITP_RTC_CR2IC_RTCIC4IRQEN (BITP_RTC_CR2IC_IC4IRQEN)
+#define BITP_RTC_CR2IC_RTCIC3IRQEN (BITP_RTC_CR2IC_IC3IRQEN)
+#define BITP_RTC_CR2IC_RTCIC2IRQEN (BITP_RTC_CR2IC_IC2IRQEN)
+#define BITP_RTC_CR2IC_RTCIC0IRQEN (BITP_RTC_CR2IC_IC0IRQEN)
+#define BITP_RTC_CR2IC_RTCIC4LH    (BITP_RTC_CR2IC_IC4LH)
+#define BITP_RTC_CR2IC_RTCIC3LH    (BITP_RTC_CR2IC_IC3LH)
+#define BITP_RTC_CR2IC_RTCIC2LH    (BITP_RTC_CR2IC_IC2LH)
+#define BITP_RTC_CR2IC_RTCIC0LH    (BITP_RTC_CR2IC_IC0LH)
+#define BITP_RTC_CR2IC_RTCIC4EN    (BITP_RTC_CR2IC_IC4EN)
+#define BITP_RTC_CR2IC_RTCIC3EN    (BITP_RTC_CR2IC_IC3EN)
+#define BITP_RTC_CR2IC_RTCIC2EN    (BITP_RTC_CR2IC_IC2EN)
+#define BITP_RTC_CR2IC_RTCIC0EN    (BITP_RTC_CR2IC_IC0EN)
+#define BITP_RTC_CR3OC_RTCOC1IRQEN (BITP_RTC_CR3SS_SS1IRQEN)
+#define BITP_RTC_CR3OC_RTCOC1EN    (BITP_RTC_CR3SS_SS1EN)
+#define BITP_RTC_CR4OC_RTCOC1ARLEN (BITP_RTC_CR4SS_SS1ARLEN)
+#define BITP_RTC_CR4OC_RTCOC1MSKEN (BITP_RTC_CR4SS_SS1MSKEN)
+#define BITP_RTC_OCMSK_RTCOCMSK    (BITP_RTC_SSMSK_SSMSK)
+#define BITP_RTC_OC1ARL_RTCOC1ARL  (BITP_RTC_SS1ARL_SS1ARL)
+#define BITP_RTC_IC2_RTCIC2        (BITP_RTC_IC2_IC2)
+#define BITP_RTC_IC3_RTCIC3        (BITP_RTC_IC3_IC3)
+#define BITP_RTC_IC4_RTCIC4        (BITP_RTC_IC4_IC4)
+#define BITP_RTC_OC1_RTCOC1        (BITP_RTC_SS1_SS1)
+#define BITP_RTC_SR4_WSYNCOC1      (BITP_RTC_SR4_WSYNCSS1)
+#define BITP_RTC_SR4_WSYNCOC1ARL   (BITP_RTC_SR4_WSYNCSS1ARL)
+#define BITP_RTC_SR4_WSYNCOCMSK    (BITP_RTC_SR4_WSYNCSSMSK)
+#define BITP_RTC_SR4_WSYNCCR4OC    (BITP_RTC_SR4_WSYNCCR4SS)
+#define BITP_RTC_SR4_WSYNCCR3OC    (BITP_RTC_SR4_WSYNCCR3SS)
+#define BITP_RTC_SR5_WPENDOC1      (BITP_RTC_SR5_WPENDSS1)
+#define BITP_RTC_SR5_WPENDOC1ARL   (BITP_RTC_SR5_WPENDSS1ARL)
+#define BITP_RTC_SR5_WPENDOCMSK    (BITP_RTC_SR5_WPENDSSMSK)
+#define BITP_RTC_SR5_WPENDCR4OC    (BITP_RTC_SR5_WPENDCR4SS)
+#define BITP_RTC_SR5_WPENDCR3OC    (BITP_RTC_SR5_WPENDCR3SS)
+#define BITP_RTC_SR6_RTCFRZCNTPTR  (BITP_RTC_SR6_FRZCNTPTR)
+#define BITP_RTC_SR6_RTCIC0SNAP    (BITP_RTC_SR6_IC0SNAP)
+#define BITP_RTC_SR6_RTCIC4UNR     (BITP_RTC_SR6_IC4UNR)
+#define BITP_RTC_SR6_RTCIC3UNR     (BITP_RTC_SR6_IC3UNR)
+#define BITP_RTC_SR6_RTCIC2UNR     (BITP_RTC_SR6_IC2UNR)
+#define BITP_RTC_SR6_RTCIC0UNR     (BITP_RTC_SR6_IC0UNR)
+#define BITP_RTC_OC1TGT_RTCOC1TGT  (BITP_RTC_SS1TGT_SS1TGT)
+#define BITP_RTC_FRZCNT_RTCFRZCNT  (BITP_RTC_FRZCNT_FRZCNT)
+
+#define BITM_RTC_CR1_RTCTRMINTEN   (BITM_RTC_CR1_TRMINTEN)
+#define BITM_RTC_SR3_RTCOC1IRQ     (BITM_RTC_SR3_SS1IRQ)
+#define BITM_RTC_SR3_RTCIC4IRQ     (BITM_RTC_SR3_IC4IRQ)
+#define BITM_RTC_SR3_RTCIC3IRQ     (BITM_RTC_SR3_IC3IRQ)
+#define BITM_RTC_SR3_RTCIC2IRQ     (BITM_RTC_SR3_IC2IRQ)
+#define BITM_RTC_SR3_RTCIC0IRQ     (BITM_RTC_SR3_IC0IRQ)
+#define BITM_RTC_CR2IC_RTCICOWUSEN (BITM_RTC_CR2IC_ICOWUSEN)
+#define BITM_RTC_CR2IC_RTCIC4IRQEN (BITM_RTC_CR2IC_IC4IRQEN)
+#define BITM_RTC_CR2IC_RTCIC3IRQEN (BITM_RTC_CR2IC_IC3IRQEN)
+#define BITM_RTC_CR2IC_RTCIC2IRQEN (BITM_RTC_CR2IC_IC2IRQEN)
+#define BITM_RTC_CR2IC_RTCIC0IRQEN (BITM_RTC_CR2IC_IC0IRQEN)
+#define BITM_RTC_CR2IC_RTCIC4LH    (BITM_RTC_CR2IC_IC4LH)
+#define BITM_RTC_CR2IC_RTCIC3LH    (BITM_RTC_CR2IC_IC3LH)
+#define BITM_RTC_CR2IC_RTCIC2LH    (BITM_RTC_CR2IC_IC2LH)
+#define BITM_RTC_CR2IC_RTCIC0LH    (BITM_RTC_CR2IC_IC0LH)
+#define BITM_RTC_CR2IC_RTCIC4EN    (BITM_RTC_CR2IC_IC4EN)
+#define BITM_RTC_CR2IC_RTCIC3EN    (BITM_RTC_CR2IC_IC3EN)
+#define BITM_RTC_CR2IC_RTCIC2EN    (BITM_RTC_CR2IC_IC2EN)
+#define BITM_RTC_CR2IC_RTCIC0EN    (BITM_RTC_CR2IC_IC0EN)
+#define BITM_RTC_CR3OC_RTCOC1IRQEN (BITM_RTC_CR3SS_SS1IRQEN)
+#define BITM_RTC_CR3OC_RTCOC1EN    (BITM_RTC_CR3SS_SS1EN)
+#define BITM_RTC_CR4OC_RTCOC1ARLEN (BITM_RTC_CR4SS_SS1ARLEN)
+#define BITM_RTC_CR4OC_RTCOC1MSKEN (BITM_RTC_CR4SS_SS1MSKEN)
+#define BITM_RTC_OCMSK_RTCOCMSK    (BITM_RTC_SSMSK_SSMSK)
+#define BITM_RTC_OC1ARL_RTCOC1ARL  (BITM_RTC_SS1ARL_SS1ARL)
+#define BITM_RTC_IC2_RTCIC2        (BITM_RTC_IC2_IC2)
+#define BITM_RTC_IC3_RTCIC3        (BITM_RTC_IC3_IC3)
+#define BITM_RTC_IC4_RTCIC4        (BITM_RTC_IC4_IC4)
+#define BITM_RTC_OC1_RTCOC1        (BITM_RTC_SS1_SS1)
+#define BITM_RTC_SR4_WSYNCOC1      (BITM_RTC_SR4_WSYNCSS1)
+#define BITM_RTC_SR4_WSYNCOC1ARL   (BITM_RTC_SR4_WSYNCSS1ARL)
+#define BITM_RTC_SR4_WSYNCOCMSK    (BITM_RTC_SR4_WSYNCSSMSK)
+#define BITM_RTC_SR4_WSYNCCR4OC    (BITM_RTC_SR4_WSYNCCR4SS)
+#define BITM_RTC_SR4_WSYNCCR3OC    (BITM_RTC_SR4_WSYNCCR3SS)
+#define BITM_RTC_SR5_WPENDOC1      (BITM_RTC_SR5_WPENDSS1)
+#define BITM_RTC_SR5_WPENDOC1ARL   (BITM_RTC_SR5_WPENDSS1ARL)
+#define BITM_RTC_SR5_WPENDOCMSK    (BITM_RTC_SR5_WPENDSSMSK)
+#define BITM_RTC_SR5_WPENDCR4OC    (BITM_RTC_SR5_WPENDCR4SS)
+#define BITM_RTC_SR5_WPENDCR3OC    (BITM_RTC_SR5_WPENDCR3SS)
+#define BITM_RTC_SR6_RTCFRZCNTPTR  (BITM_RTC_SR6_FRZCNTPTR)
+#define BITM_RTC_SR6_RTCIC0SNAP    (BITM_RTC_SR6_IC0SNAP)
+#define BITM_RTC_SR6_RTCIC4UNR     (BITM_RTC_SR6_IC4UNR)
+#define BITM_RTC_SR6_RTCIC3UNR     (BITM_RTC_SR6_IC3UNR)
+#define BITM_RTC_SR6_RTCIC2UNR     (BITM_RTC_SR6_IC2UNR)
+#define BITM_RTC_SR6_RTCIC0UNR     (BITM_RTC_SR6_IC0UNR)
+#define BITM_RTC_OC1TGT_RTCOC1TGT  (BITM_RTC_SS1TGT_SS1TGT)
+#define BITM_RTC_FRZCNT_RTCFRZCNT  (BITM_RTC_FRZCNT_FRZCNT)
+
+#define ENUM_RTC_CR4OC_NO_MSK      (ENUM_RTC_CR4SS_NO_MSK)
+#define ENUM_RTC_CR4OC_THERM_MSK   (ENUM_RTC_CR4SS_THERM_MSK)
+
+/* Backward compatibility shim for renamed crypto registers. */
+
+#define BITP_CRYPT_CFG_KEYLEN (BITP_CRYPT_CFG_AESKEYLEN)
+#define BITP_CRYPT_CFG_ENDIAN (BITP_CRYPT_CFG_AES_BYTESWAP)
+
+#define BITM_CRYPT_CFG_KEYLEN (BITM_CRYPT_CFG_AESKEYLEN)
+#define BITM_CRYPT_CFG_ENDIAN (BITM_CRYPT_CFG_AES_BYTESWAP)
+
+#define ENUM_CRYPT_CFG_LITTLE_ENDIAN (_ADI_MSK_3(0x00000000, 0x00000000UL, uint32_t))
+#define ENUM_CRYPT_CFG_BIG_ENDIAN    (_ADI_MSK_3(0x00000040, 0x00000040UL, uint32_t))
+
+
+#ifdef __ICCARM__
+#pragma diag_default=Pm008,Pm009
+#endif /* __ICCARM__ */
+
+#endif /* _WRAP_ADUCM3029_DEF_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_device.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_device.h
new file mode 100755
index 00000000000..75b5f887967
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_device.h
@@ -0,0 +1,261 @@
+/*!
+*****************************************************************************
+ * @file:    ADuCM3029_device.h
+ * @brief:   ADuCM3029 C Register Definitions
+ * @version: $Revision: 36179 $
+ * @date:    $Date: 2017-02-10 09:56:54 -0500 (Fri, 10 Feb 2017) $
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2015-2017 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef _WRAP_ADUCM3029_DEVICE_H
+#define _WRAP_ADUCM3029_DEVICE_H
+
+#include <ADuCM3029_typedefs.h>
+#include <sys/adi_cio_macros.h>
+
+#ifdef __ICCARM__
+/* IAR MISRA C 2004 error suppressions:
+ *
+ * Pm093 (rule 18.4): use of union - overlapping storage shall not be used.
+ *    Unions are required by sys/ADUCM302x_device.h.
+ */
+#pragma diag_suppress=Pm093
+#endif /* __ICCARM__ */
+
+/* UART and RTC structs need to be redefined with backward compatibility names. */
+#define __ADI_NO_DECL_STRUCT_ADI_UART_TypeDef__
+#define __ADI_NO_DECL_STRUCT_ADI_RTC_TypeDef__
+
+/* The generated header. */
+#include <sys/ADuCM302x_device.h>
+
+typedef struct _ADI_UART_TypeDef
+{
+    union {
+    __I __C  uint16_t RX;                            /*!< Receive Buffer Register */
+    __I __C  uint16_t COMRX;
+    __O      uint16_t TX;                            /*!< Transmit Holding Register */
+    __O      uint16_t COMTX;
+    };
+    __I __C  uint8_t  RESERVED0[2];
+    union {
+    __IO     uint16_t IEN;                           /*!< Interrupt Enable */
+    __IO     uint16_t COMIEN;
+    };
+    __I __C  uint8_t  RESERVED1[2];
+    union {
+    __I __C  uint16_t IIR;                           /*!< Interrupt ID */
+    __I __C  uint16_t COMIIR;
+    };
+    __I __C  uint8_t  RESERVED2[2];
+    union {
+    __IO     uint16_t LCR;                           /*!< Line Control */
+    __IO     uint16_t COMLCR;
+    };
+    __I __C  uint8_t  RESERVED3[2];
+    union {
+    __IO     uint16_t MCR;                           /*!< Modem Control */
+    __IO     uint16_t COMMCR;
+    };
+    __I __C  uint8_t  RESERVED4[2];
+    union {
+    __I __C  uint16_t LSR;                           /*!< Line Status */
+    __I __C  uint16_t COMLSR;
+    };
+    __I __C  uint8_t  RESERVED5[2];
+    union {
+    __I __C  uint16_t MSR;                           /*!< Modem Status */
+    __I __C  uint16_t COMMSR;
+    };
+    __I __C  uint8_t  RESERVED6[2];
+    union {
+    __IO     uint16_t SCR;                           /*!< Scratch buffer */
+    __IO     uint16_t COMSCR;
+    };
+    __I __C  uint8_t  RESERVED7[2];
+    union {
+    __IO     uint16_t FCR;                           /*!< FIFO Control */
+    __IO     uint16_t COMFCR;
+    };
+    __I __C  uint8_t  RESERVED8[2];
+    union {
+    __IO     uint16_t FBR;                           /*!< Fractional Baud Rate */
+    __IO     uint16_t COMFBR;
+    };
+    __I __C  uint8_t  RESERVED9[2];
+    union {
+    __IO     uint16_t DIV;                           /*!< Baudrate divider */
+    __IO     uint16_t COMDIV;
+    };
+    __I __C  uint8_t  RESERVED10[2];
+    union {
+    __IO     uint16_t LCR2;                          /*!< second Line Control */
+    __IO     uint16_t COMLCR2;
+    };
+    __I __C  uint8_t  RESERVED11[2];
+    union {
+    __IO     uint16_t CTL;                           /*!< UART control register */
+    __IO     uint16_t COMCTL;
+    };
+    __I __C  uint8_t  RESERVED12[2];
+    union {
+    __I __C  uint16_t RFC;                           /*!< RX FIFO byte count */
+    __I __C  uint16_t COMRFC;
+    };
+    __I __C  uint8_t  RESERVED13[2];
+    union {
+    __I __C  uint16_t TFC;                           /*!< TX FIFO byte count */
+    __I __C  uint16_t COMTFC;
+    };
+    __I __C  uint8_t  RESERVED14[2];
+    union {
+    __IO     uint16_t RSC;                           /*!< RS485 half-duplex Control */
+    __IO     uint16_t COMRSC;
+    };
+    __I __C  uint8_t  RESERVED15[2];
+    union {
+    __IO     uint16_t ACR;                           /*!< Auto Baud Control */
+    __IO     uint16_t COMACR;
+    };
+    __I __C  uint8_t  RESERVED16[2];
+    union {
+    __I __C  uint16_t ASRL;                          /*!< Auto Baud Status (Low) */
+    __I __C  uint16_t COMASRL;
+    };
+    __I __C  uint8_t  RESERVED17[2];
+    union {
+    __I __C  uint16_t ASRH;                          /*!< Auto Baud Status (High) */
+    __I __C  uint16_t COMASRH;
+    };
+} ADI_UART_TypeDef;
+
+
+typedef struct _ADI_RTC_TypeDef
+{
+    __IO     uint16_t   CR0;                           /*!< RTC Control 0 */
+    __I __C  uint8_t  RESERVED0[2];
+    __IO     uint16_t   SR0;                           /*!< RTC Status 0 */
+    __I __C  uint8_t  RESERVED1[2];
+    __I __C  uint16_t   SR1;                           /*!< RTC Status 1 */
+    __I __C  uint8_t  RESERVED2[2];
+    __IO     uint16_t   CNT0;                          /*!< RTC Count 0 */
+    __I __C  uint8_t  RESERVED3[2];
+    __IO     uint16_t   CNT1;                          /*!< RTC Count 1 */
+    __I __C  uint8_t  RESERVED4[2];
+    __IO     uint16_t   ALM0;                          /*!< RTC Alarm 0 */
+    __I __C  uint8_t  RESERVED5[2];
+    __IO     uint16_t   ALM1;                          /*!< RTC Alarm 1 */
+    __I __C  uint8_t  RESERVED6[2];
+    __IO     uint16_t   TRM;                           /*!< RTC Trim */
+    __I __C  uint8_t  RESERVED7[2];
+    __O      uint16_t   GWY;                           /*!< RTC Gateway */
+    __I __C  uint8_t  RESERVED8[6];
+    __IO     uint16_t   CR1;                           /*!< RTC Control 1 */
+    __I __C  uint8_t  RESERVED9[2];
+    __IO     uint16_t   SR2;                           /*!< RTC Status 2 */
+    __I __C  uint8_t  RESERVED10[2];
+    __I __C  uint16_t   SNAP0;                         /*!< RTC Snapshot 0 */
+    __I __C  uint8_t  RESERVED11[2];
+    __I __C  uint16_t   SNAP1;                         /*!< RTC Snapshot 1 */
+    __I __C  uint8_t  RESERVED12[2];
+    __I __C  uint16_t   SNAP2;                         /*!< RTC Snapshot 2 */
+    __I __C  uint8_t  RESERVED13[2];
+    __I __C  uint16_t   MOD;                           /*!< RTC Modulo */
+    __I __C  uint8_t  RESERVED14[2];
+    __I __C  uint16_t   CNT2;                          /*!< RTC Count 2 */
+    __I __C  uint8_t  RESERVED15[2];
+    __IO     uint16_t   ALM2;                          /*!< RTC Alarm 2 */
+    __I __C  uint8_t  RESERVED16[2];
+    __IO     uint16_t   SR3;                           /*!< RTC Status 3 */
+    __I __C  uint8_t  RESERVED17[2];
+    __IO     uint16_t   CR2IC;                         /*!< RTC Control 2 for Configuring Input Capture Channels */
+    __I __C  uint8_t  RESERVED18[2];
+    union {
+    __IO     uint16_t   CR3SS;                         /*!< RTC Control 3 for Configuring SensorStrobe Channel */
+    __IO     uint16_t   CR3OC;
+    };
+    __I __C  uint8_t  RESERVED19[2];
+    union {
+    __IO     uint16_t   CR4SS;                         /*!< RTC Control 4 for Configuring SensorStrobe Channel */
+    __IO     uint16_t   CR4OC;
+    };
+    __I __C  uint8_t  RESERVED20[2];
+    union {
+    __IO     uint16_t   SSMSK;                         /*!< RTC Mask for SensorStrobe Channel */
+    __IO     uint16_t   OCMSK;
+    };
+    __I __C  uint8_t  RESERVED21[2];
+    union {
+    __IO     uint16_t   SS1ARL;                        /*!< RTC Auto-Reload for SensorStrobe Channel 1 */
+    __IO     uint16_t   OC1ARL;
+    };
+    __I __C  uint8_t  RESERVED22[6];
+    __I __C  uint16_t   IC2;                           /*!< RTC Input Capture Channel 2 */
+    __I __C  uint8_t  RESERVED23[2];
+    __I __C  uint16_t   IC3;                           /*!< RTC Input Capture Channel 3 */
+    __I __C  uint8_t  RESERVED24[2];
+    __I __C  uint16_t   IC4;                           /*!< RTC Input Capture Channel 4 */
+    __I __C  uint8_t  RESERVED25[2];
+    union {
+    __IO     uint16_t   SS1;                           /*!< RTC SensorStrobe Channel 1 */
+    __IO     uint16_t   OC1;
+    };
+    __I __C  uint8_t  RESERVED26[14];
+    __I __C  uint16_t   SR4;                           /*!< RTC Status 4 */
+    __I __C  uint8_t  RESERVED27[2];
+    __I __C  uint16_t   SR5;                           /*!< RTC Status 5 */
+    __I __C  uint8_t  RESERVED28[2];
+    __I __C  uint16_t   SR6;                           /*!< RTC Status 6 */
+    __I __C  uint8_t  RESERVED29[2];
+    union {
+    __I __C  uint16_t   SS1TGT;                        /*!< RTC SensorStrobe Channel 1 Target */
+    __I __C  uint16_t   OC1TGT;
+    };
+    __I __C  uint8_t  RESERVED30[2];
+    __I __C  uint16_t   FRZCNT;                        /*!< RTC Freeze Count */
+} ADI_RTC_TypeDef;
+
+
+#ifdef __ICCARM__
+#pragma diag_default=Pm093
+#endif /* __ICCARM__ */
+
+#endif /* _WRAP_ADUCM3029_DEVICE_H__ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_typedefs.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_typedefs.h
new file mode 100755
index 00000000000..8e2f650cb15
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_typedefs.h
@@ -0,0 +1,118 @@
+/*!
+ *****************************************************************************
+ * @file:    ADuCM3029_typedefs.h
+ * @brief:   ADuCM3029 C Register Structures
+ * @version: $Revision: 36131 $
+ * @date:    $Date: 2017-01-09 10:00:32 -0500 (Mon, 09 Jan 2017) $
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2015-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef _WRAP_ADUCM3029_TYPEDEFS_H
+#define _WRAP_ADUCM3029_TYPEDEFS_H
+
+#include <stdint.h>
+
+#ifdef __ICCARM__
+/* IAR MISRA C 2004 error suppressions:
+ *
+ * Pm008 (rule 2.4): sections of code should not be 'commented out'.
+ *   Some comments are wrongly identified as code.
+ *
+ * Pm093 (rule 18.4): use of union - overlapping storage shall not be used.
+ *    Unions are required by sys/ADUCM302x_typedefs.h.
+ */
+#pragma diag_suppress=Pm008,Pm093
+#endif /* __ICCARM__ */
+
+#define __ADI_NO_DECL_STRUCT_ADI_CRYPT_CFG_t__
+
+#include <sys/ADuCM302x_typedefs.h>
+
+
+/* Redefine ADI_CRYPT_CFG_t with backward compatibility names. */
+
+typedef struct _ADI_CRYPT_CFG_t {
+  union {
+    struct {
+      unsigned int BLKEN      :  1;  /**< Enable BIT for the Crypto Block */
+      unsigned int ENCR       :  1;  /**< Encrypt or Decrypt */
+      unsigned int INDMAEN    :  1;  /**< Enable DMA for Input Buffer */
+      unsigned int OUTDMAEN   :  1;  /**< Enable DMA for Output Buffer */
+      unsigned int INFLUSH    :  1;  /**< Input Buffer Flush */
+      unsigned int OUTFLUSH   :  1;  /**< Output Buffer Flush */
+      union {
+        unsigned int AES_BYTESWAP :  1;  /**< Byte Swap 32 Bit AES Input Data */
+        unsigned int ENDIAN       :  1;
+      };
+      unsigned int reserved7    :  1;
+      union {
+        unsigned int AESKEYLEN    :  2;  /**< Select Key Length for AES Cipher */
+        unsigned int KEYLEN       :  2;  /**< Select Key Length for AES Cipher */
+      };
+      unsigned int reserved10   :  6;
+      unsigned int ECBEN        :  1;  /**< Enable ECB Mode Operation */
+      unsigned int CTREN        :  1;  /**< Enable CTR Mode Operation */
+      unsigned int CBCEN        :  1;  /**< Enable CBC Mode Operation */
+      unsigned int CCMEN        :  1;  /**< Enable CCM/CCM* Mode Operation */
+      unsigned int CMACEN       :  1;  /**< Enable CMAC Mode Operation */
+      unsigned int reserved21   :  1;
+      unsigned int RES          :  3;  /**< Reserved */
+      unsigned int SHA256EN     :  1;  /**< Enable SHA-256 Operation */
+      unsigned int SHAINIT      :  1;  /**< Restarts SHA Computation */
+      unsigned int reserved27   :  1;
+      unsigned int RevID        :  4;  /**< Rev ID for Crypto */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_CFG_t;
+
+typedef enum
+{
+  CRYPT_CFG_LITTLE_ENDIAN = 0,
+  CRYPT_CFG_BIG_ENDIAN    = 1
+} ADI_CRYPT_CFG_ENDIAN;
+
+
+#ifdef __ICCARM__
+#pragma diag_default=Pm008,Pm093
+#endif /* __ICCARM__ */
+
+#endif /* _WRAP_ADUCM3029_TYPEDEFS_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adc/adi_adc.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adc/adi_adc.c
new file mode 100755
index 00000000000..094e53d0485
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adc/adi_adc.c
@@ -0,0 +1,2385 @@
+/*! *****************************************************************************
+ * @file:    adi_adc.c
+ * @brief:   ADC device driver global file.
+ * @details: This file contain the ADC device driver implementation.
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+/** @addtogroup  ADC_Driver ADC Driver
+ *  @{
+ *  @brief ADC Driver
+ *  @details The ADC driver manages all instances of the ADC peripheral.
+ *  @note - The application must include drivers/adc/adi_adc.h to use this driver.
+ *  @note - This driver also requires the DMA driver.  The application must include
+            the DMA driver sources to avoid link errors.    
+ */
+
+#ifndef ADI_ADC_C
+/*! \cond PRIVATE */
+#define ADI_ADC_C
+
+/*=============  I N C L U D E S   =============*/
+
+
+/* Header file with definitions specific to ADC driver implementation */
+
+/*=============  A D C    I M P L E M E N T A T I O N    S O U R C E    F I L E S  =============*/
+#include <drivers/adc/adi_adc.h>
+#include <adi_processor.h>
+#include <assert.h>
+#include <string.h>
+#include <drivers/pwr/adi_pwr.h>
+#include <adi_adc_config.h>
+#include <rtos_map/adi_rtos_map.h>
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
+*   This isn't a header as such.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+*
+* Pm050 (rule 14.2): a null statement shall only occur on a line by itself
+*   Needed for null expansion of ADI_INSTALL_HANDLER and others.
+*
+* Pm088 (rule 17.4): pointer arithmetic should not be used.
+*   Relying on pointer arithmetic for buffer handling.
+*
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   The rule makes an exception for memory-mapped register accesses.
+*
+* Pm152: (MISRA C 2004 rule 17.4) array indexing shall only be applied to objects defined as an array type
+*   Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors
+
+*/
+#pragma diag_suppress=Pm123,Pm073,Pm143,Pm050,Pm088,Pm140,Pm152
+#endif /* __ICCARM__ */
+
+#include "adi_adc_def.h"
+#include "adi_adc_data.c"
+
+/*==============  D E F I N E S  ===============*/
+#ifdef ADI_DEBUG
+#define ADI_ADC_INVALID_HANDLE(h)   (AdcDevInfo[0].hDevice != (h))
+#endif
+
+/* Specify the maximum acquisition time, based on the width of the SAMPTIME field. */
+#define ADI_MAX_ACQUISITION_TIME (((uint32_t)BITM_ADC_CNV_TIME_SAMPTIME << BITP_ADC_CNV_TIME_SAMPTIME) + 1u)
+
+/* The 12bit maximum sample value */
+#define ADI_ADC_SAMPLE_MAX ((uint16_t)(4095u))
+
+/*=============  C O D E  =============*/
+
+/*=============  D E B U G    F U N C T I O N    P R O T O T Y P E S  =============*/
+
+/* Override "weak" default binding in startup_*.c */
+/*! \cond PRIVATE */
+#if defined(__ADUCM302x__) 
+extern void ADC_Int_Handler(void);
+#else
+extern void ADC0_Int_Handler(void);
+#endif
+
+/* macro definition for ADuCM3029 */
+#if defined(__ADUCM302x__)
+#define BITM_ADC_CFG_VREFVBAT                (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  VRef VBAT */
+#endif
+
+extern void DMA_ADC0_Int_Handler (void);
+                                  
+/*! \endcond */
+
+/* Prototypes for static functions (required by MISRA-C:2004 Rule 8.1)  */
+/*=============  L O C A L   F U N C T I O N S   P R O T O T Y P E S =============*/
+static uint16_t ReadOutReg(uint32_t nChannelNum);
+
+/* ADC management functions, based on transfer method */
+#if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1
+static ADI_ADC_RESULT DmaFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode);
+#else
+static ADI_ADC_RESULT InterruptFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode);
+#endif
+
+/* Channel helper functions */
+static uint32_t GetNumChannels(uint32_t nChannels);
+static int32_t  nGetChannelNumber(ADI_ADC_CHANNEL eChannel);
+
+/* Buffer management functions */
+static void ManageFifoCompletion(ADI_ADC_DEVICE *pDevice);
+static bool InitBufferProcessing(ADI_ADC_DEVICE *pDevice);
+static void FlushFifo(ADI_ADC_DEVICE *pDevice, uint32_t nChannels);
+
+/* Internal configuration functions */
+static void EnableComparator(ADI_ADC_DEVICE *pDevice, bool bEnable);
+static void StaticConfiguration(ADI_ADC_DEVICE *pDevice);
+
+/*! \endcond */
+
+/*=============  P U B L I C   F U N C T I O N S =============*/
+
+/**
+ * @brief    Opens an ADC device instance.
+ *
+ * @param [in]  nDeviceNum   Device number to open
+ * @param [in]  pMemory      Pointer to a #ADI_ADC_MEMORY_SIZE sized buffer to manage the device
+ *                           instance.
+ * @param [in]  nMemorySize  Size of the buffer to which "pMemory" points
+ * @param [out] phDevice     Pointer to a location where ADC device handle is to be written.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Call completed successfully
+ *           - #ADI_ADC_INVALID_DEVICE_NUM      [D] Invalid Device Number
+ *           - #ADI_ADC_INSUFFICIENT_MEMORY     [D] Memory passed is not sufficient
+ *           - #ADI_ADC_IN_USE                  [D] ADC driver was already opened
+ */
+ADI_ADC_RESULT adi_adc_Open (
+    uint32_t       nDeviceNum,
+    void           *pMemory,
+    uint32_t       nMemorySize,
+    ADI_ADC_HANDLE *phDevice)
+{
+    ADI_INT_STATUS_ALLOC();
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)pMemory;
+    
+#ifdef ADI_DEBUG
+    if (nDeviceNum > (sizeof (AdcDevInfo)/sizeof(AdcDevInfo[0])))
+    {
+        return ADI_ADC_INVALID_DEVICE_NUM;
+    }
+
+    if (nMemorySize < ADI_ADC_MEMORY_SIZE)
+    {
+        return ADI_ADC_INSUFFICIENT_MEMORY;
+    }
+
+    if (AdcDevInfo[nDeviceNum].hDevice != NULL)
+    {
+        return ADI_ADC_IN_USE;
+    }
+    
+    assert (ADI_ADC_MEMORY_SIZE >= sizeof (ADI_ADC_DEVICE));
+#endif /* ADI_DEBUG */
+    
+    memset (pMemory, 0, nMemorySize);
+    
+    ADI_ENTER_CRITICAL_REGION();
+    AdcDevInfo[nDeviceNum].hDevice = (ADI_ADC_HANDLE)pDevice;
+    pDevice->pReg = AdcDevInfo[nDeviceNum].pReg;
+    ADI_EXIT_CRITICAL_REGION();
+    
+    /* Reset the ADC */
+    pDevice->pReg->CFG = BITM_ADC_CFG_RST;
+    
+    /* Enable the IRQs */ 
+    NVIC_ClearPendingIRQ(ADC0_EVT_IRQn);
+    NVIC_EnableIRQ(ADC0_EVT_IRQn);
+    
+    /* Initialize the registers to known value */
+    pDevice->pReg->IRQ_EN =   BITM_ADC_IRQ_EN_RDY | BITM_ADC_IRQ_EN_ALERT | BITM_ADC_IRQ_EN_OVF | BITM_ADC_IRQ_EN_CALDONE | BITM_ADC_IRQ_EN_CNVDONE;
+    
+    /* Do the static configuration */
+    StaticConfiguration(pDevice);
+
+    /* Create a semaphore for buffer management */
+    SEM_CREATE(pDevice, "ADC Sem", ADI_ADC_ERR_RTOS);
+
+    /* Set the default FIFO Manage function */
+#if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1
+    pDevice->pfManageFifo = DmaFIFOManage;
+    /* Make sure the DMA controller and its SRAM based descriptors are initialized */
+    adi_dma_Init();
+#else    
+    pDevice->pfManageFifo = InterruptFIFOManage;
+#endif 
+
+    /* Return the device handle back to the application */
+    *phDevice = AdcDevInfo[nDeviceNum].hDevice;
+
+    return ADI_ADC_SUCCESS;
+}
+    
+    
+/**
+ * @brief    Close the given device instance
+ *
+ * @param [in]  hDevice  Handle to the device instance
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully closed the device
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle based to the function
+ */
+ADI_ADC_RESULT adi_adc_Close (ADI_ADC_HANDLE hDevice)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    ADI_ADC_RESULT eResult;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+#endif /* ADI_DEBUG */	
+
+    /* Power down the device */
+    if ((eResult = adi_adc_PowerUp (hDevice, false)) != ADI_ADC_SUCCESS) {
+        return eResult;
+    }
+
+      /* Disable the IRQ */
+      pDevice->pReg->IRQ_EN = 0u;
+
+      /* Clear the conversion cfg register to stop any transaction */
+      pDevice->pReg->CNV_CFG = 0u;
+
+#if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1
+      /* Close the DMA if configured */
+      NVIC_DisableIRQ(DMA0_CH24_DONE_IRQn);
+#endif /* ADI_ADC_ENABLE_MULTI_ACQUIRE == 1 */
+        
+    /* Disable the ADC interrupt */
+    NVIC_DisableIRQ(ADC0_EVT_IRQn);
+    
+    /* Destroy the semaphore */
+    SEM_DELETE(pDevice, ADI_ADC_ERR_RTOS);
+
+    /* Finally, zero the device */
+    AdcDevInfo[0].hDevice = (NULL);
+
+    return ADI_ADC_SUCCESS;
+}
+
+
+/**
+ * @brief   Power up ADC
+ *
+ * @param [in]  hDevice     Handle to the device instance
+ *
+ * @param [in]  bPowerUp    'true' to power up and 'false' to power down the ADC.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully closed the device
+ *           - #ADI_ADC_BAD_SYS_CLOCK               Unable to obtain PCLK which is needed to calculate
+ *                                                  powerup values.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the function
+ */
+ADI_ADC_RESULT adi_adc_PowerUp (ADI_ADC_HANDLE hDevice, bool bPowerUp)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    uint32_t nClock = 0u;
+    uint16_t nCount = 0u;
+    ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS;
+    
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+#endif /* ADI_DEBUG */
+
+    if (bPowerUp == true)
+    {
+        if (IS_NOT_IN_ANY_STATE(ADC_STATUS_POWERED_UP))
+        {
+            if(adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &nClock) == ADI_PWR_SUCCESS)
+            {
+              /* We need the cycles equivelent of 20us entered here, based on the PCLK
+               * clock. nClock is the frequency of the PCLK, 50000 is the equivalent frequency of 20us
+               * e.g. 26,000,000Hz, 0.00002s produces 520 cycles.*/
+              nCount =  (uint16_t)(nClock / 50000u); 
+              
+              /* Powering up ADC */
+              pDevice->pReg->CFG |= BITM_ADC_CFG_PWRUP;
+
+              /* Set ADC_PWRUP.WAIT bits for the new count */
+              pDevice->pReg->PWRUP = (uint16_t)(((uint32_t)nCount << BITP_ADC_PWRUP_WAIT) &  BITM_ADC_PWRUP_WAIT);
+              
+              SET_STATE(ADC_STATUS_POWERED_UP);
+            }
+            else
+            {
+              eResult = ADI_ADC_BAD_SYS_CLOCK;
+            }
+        }
+    }
+    else
+    {
+        if (IS_IN_STATE(ADC_STATUS_POWERED_UP))
+        {
+            /* If the ADC system is up then disable the ADC subsystem */
+            if (  IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN) )
+            {
+                eResult = adi_adc_EnableADCSubSystem (hDevice, false);
+                if (eResult != ADI_ADC_SUCCESS)
+                {
+                    return eResult;
+                }                
+            }
+            
+            /* Powering down ADC */
+            pDevice->pReg->CFG &= (uint16_t)(~(BITM_ADC_CFG_PWRUP));
+            CLR_STATE(ADC_STATUS_POWERED_UP);
+        }
+    }
+
+    return eResult;
+}
+
+            
+/**
+ * @brief   Registering a callback function
+ *
+ * @param [in]  hDevice     Handle to the device instance
+ * @param [in]  pfCallback  Function pointer to callback function. Passing a NULL pointer will
+ *                          unregister the call back function.
+ * @param [in]  pCBParam    Call back function parameter
+ *
+ * @details  This function registers a call back function. Registered function will be called when
+ *           the given computation is over. It will also be called when the digital comparitor is being
+ *           used and a limit has been broken.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS              Successfully registerd the callback
+ *           - #ADI_ADC_INVALID_SEQUENCE      [D] Callback cannot be registered when ADC is enabled for sampling.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the function
+ */            
+ADI_ADC_RESULT adi_adc_RegisterCallback (
+    ADI_ADC_HANDLE hDevice,
+    ADI_CALLBACK   pfCallback,
+    void           *pCBParam)
+{
+    ADI_INT_STATUS_ALLOC();
+    
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+
+    if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) 
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+
+#endif /* ADI_DEBUG */
+
+    ADI_ENTER_CRITICAL_REGION();
+    pDevice->pfCallback = pfCallback;
+    pDevice->pCBParam = pCBParam;
+    ADI_EXIT_CRITICAL_REGION();
+    
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Enable/Disables the ADC Subsystem
+ *
+ * @param [in]  hDevice      Handle to the device instance
+ *
+ * @param [in]  bEnable      'true' to Enable and 'false' to Disable`
+ *
+ * @details  Enables/Disables the ADC Subsystem. The ADC subsystem need to be enabled before using the ADC
+ *           for sampling the signal. The driver should check whether the ADC is ready by calling adi_adc_IsReady
+ *           API before continuing. If internal reference buffer is used as voltage reference then application
+ *           has to wait at least 3.5ms after enabling irrespective of whether adi_adc_IsReady returns ready or not.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS              Successfully enabled/disabled the ADC subsystem
+ *           - #ADI_ADC_INVALID_SEQUENCE     [D] Can only be called if the ADC is powered up, 
+ *                                               and cannot be disabled when sampling or using
+ *                                               the camparator.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the function
+ */
+ADI_ADC_RESULT adi_adc_EnableADCSubSystem (
+    ADI_ADC_HANDLE hDevice,
+    bool         bEnable)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    
+    if (IS_NOT_IN_STATE(ADC_STATUS_POWERED_UP))
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+    
+    if (bEnable == true) {
+        if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) {
+            return ADI_ADC_INVALID_SEQUENCE;
+        }
+    } else {
+        if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) {
+            return ADI_ADC_INVALID_SEQUENCE;
+        }
+    }
+#endif /* ADI_DEBUG */
+
+    if (bEnable == true)
+    {
+        pDevice->pReg->CFG |= BITM_ADC_CFG_EN;
+        SET_STATE(ADC_STATUS_SUB_SYSTEM_EN);
+    }
+    else
+    {
+        pDevice->pReg->CFG &= (uint16_t)(~BITM_ADC_CFG_EN);
+        CLR_STATE(ADC_STATUS_SUB_SYSTEM_EN | ADC_STATUS_SUB_SYSTEM_READY);
+    }
+
+    return ADI_ADC_SUCCESS;
+}
+
+                
+/**
+  * @brief    Returns whether the ADC Subsystem is ready
+  *
+  * @param [in]  hDevice      Handle to the device instance
+  *
+
+* @param [in]  pbReady      Pointer to a bool variable. The variable will be set to 'true' if the ADC is ready else 'false'
+  *
+  * @details  Returns whether the ADC is ready for sampling. This API should be called after enabling the ADC sub-system using
+  *           adi_adc_EnableADCSubSystem API. If internal reference buffer is used as voltage reference then application
+  *           has to wait at least 3.5ms after enabling irrespective of whether adi_adc_IsReady returns ready or not.
+  *
+  * @return   Status
+  *           - #ADI_ADC_SUCCESS              Successfully returned the ready status
+  *           - #ADI_ADC_INVALID_SEQUENCE     [D] Cannot be called if the subsystem is not enabled.
+  *           - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the function
+  *           - #ADI_ADC_NULL_POINTER            [D] pbReady is NULL
+  */
+               
+ADI_ADC_RESULT adi_adc_IsReady (
+    ADI_ADC_HANDLE  hDevice,
+    bool         *pbReady
+)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+
+    if (pbReady == NULL)
+    {
+        return ADI_ADC_NULL_POINTER;
+    }
+    
+    if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN))
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+#endif /* ADI_DEBUG */
+
+    if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_READY))
+    {
+        *pbReady = true;
+    }
+    else
+    {
+        *pbReady = false;
+    }
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Set the Voltage Reference source
+ *
+ * @param [in] hDevice      Handle to the device instance
+ *
+ * @param [in] eVrefSrc     Voltage Reference source to be used
+ *
+ * @details  The API can be used to select the voltage reference to be used by the ADC. This option need to be
+ *           set before enabling the ADC subsystem.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Succesfully set the Vref source
+ *           - #ADI_ADC_INVALID_PARAMETER           Vref source enum passed is invalid.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle based to the function.
+ *           - #ADI_ADC_INVALID_SEQUENCE        [D] VREF cannot be changed once the ADC subsystem is enabled.
+ */
+
+ADI_ADC_RESULT adi_adc_SetVrefSource (
+    ADI_ADC_HANDLE   hDevice,
+    ADI_ADC_VREF_SRC eVrefSrc)
+{
+    ADI_ADC_RESULT eResult  = ADI_ADC_SUCCESS;
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    
+    if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) 
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+#endif /* ADI_DEBUG */
+
+    pDevice->pReg->CFG &= (uint16_t)(~(BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL | BITM_ADC_CFG_VREFVBAT));
+
+    switch (eVrefSrc)
+    {
+    case ADI_ADC_VREF_SRC_INT_1_25_V:
+        pDevice->pReg->CFG |= BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL;
+        break;
+
+    case ADI_ADC_VREF_SRC_INT_2_50_V:
+        pDevice->pReg->CFG |= BITM_ADC_CFG_REFBUFEN;
+        break;
+        
+    case ADI_ADC_VREF_SRC_VBAT:
+        pDevice->pReg->CFG |= BITM_ADC_CFG_VREFVBAT;
+        break;        
+
+    case ADI_ADC_VREF_SRC_EXT:
+        break;
+
+    default:
+        eResult = ADI_ADC_INVALID_PARAMETER;
+        break;
+    }
+
+    return eResult;
+}
+
+
+/**
+ * @brief    Enable/Disable Current Sink
+ *
+ * @param [in] hDevice      Handle to the device instance
+ *
+ * @param [in] bEnable      'true' to Enable and 'false' to Disable current sink
+ *
+ * @details  If the volatage reference is required to sink current then this option need to be enabled.
+ *           The ADC subsystem has the capability to sink upto 50uA at Vref of 1.25V and 100uA at Vref of 2.5V
+
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully enabled sink
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API
+ */
+                
+ADI_ADC_RESULT adi_adc_SinkEnable (
+    ADI_ADC_HANDLE hDevice,
+    bool         bEnable)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+#endif /* ADI_DEBUG */
+
+    if (bEnable == true)
+    {
+        pDevice->pReg->CFG |= BITM_ADC_CFG_SINKEN;
+    }
+    else
+    {
+        pDevice->pReg->CFG &= (uint16_t)~(BITM_ADC_CFG_SINKEN);
+    }
+
+    return ADI_ADC_SUCCESS;
+}
+
+
+/**
+ * @brief    Start the ADC calibration
+ *
+ * @param [in] hDevice      Handle to the device instance
+ *
+ * @details  The call to this function initiate calibration of the ADC. The user is recommended to do calibration of the ADC after
+ *           enabling the ADC subsystem. The status of the calibration can be checked using adi_adc_IsCalibrationDone API.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully initiated calibration of ADC
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_SEQUENCE        [D] Sampling cannot be enabled if the ADC is enabled.
+ */
+ADI_ADC_RESULT  adi_adc_StartCalibration(ADI_ADC_HANDLE hDevice)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+
+    /* Calibration cannot be done when ADC is processing the buffers */
+    if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN)) 
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+        
+#endif /* ADI_DEBUG */
+
+    /* Clear the calibration done state */
+    CLR_STATE(ADC_STATUS_CALIBRATION_DONE);
+
+    /* Clear ADC_STAT.CALDONE */
+    pDevice->pReg->STAT = BITM_ADC_STAT_CALDONE;
+    
+    /* Set the state as calibration enabled. This state will be cleared when we get the
+       calibration done interrupt. */
+    SET_STATE(ADC_STATUS_CALIBRATION_EN);
+    
+    /* Start ADC calibration */
+    pDevice->pReg->CFG |= BITM_ADC_CFG_STARTCAL;
+    
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Returns the status of the calibration which was initiated.
+ *
+ * @param [in]  hDevice              Handle to the device instance
+ *
+ * @param [out] pbCalibrationDone    Pointer to the location to which the status of calibration is written.
+ *                                   'true' if the calibration started by call to  is done else 'false'
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully retrieved the status of ADC calibration.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_NULL_POINTER            [D] pbCalibrationDone is NULL
+ */
+
+ADI_ADC_RESULT adi_adc_IsCalibrationDone (
+    ADI_ADC_HANDLE hDevice,
+    bool         *pbCalibrationDone)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+
+    if (pbCalibrationDone == NULL)
+    {
+        return ADI_ADC_NULL_POINTER;
+    }
+#endif /* ADI_DEBUG */
+
+    /* The driver will check whether the driver is set to calibration done state. This state will 
+     * be set in the driver when the calibration done interrupt is received by the driver
+     */
+    if (IS_IN_STATE(ADC_STATUS_CALIBRATION_DONE))
+    {
+        *pbCalibrationDone = true;
+    }
+    else
+    {
+        *pbCalibrationDone = false;
+    }
+
+    return ADI_ADC_SUCCESS;
+}
+
+
+
+/**
+ * @brief    Set the acquisition time of ADC in ADC clock cycles
+ *
+ * @param [in]  hDevice              Handle to the device instance
+ *
+ * @param [in] nAcqTimeInAClkCycles  Acquisition time in ADC clock cycles.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully set the acquisition time of ADC
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_SEQUENCE        [D] Acquisition time cannot be set when the ADC is enabled for sampling
+ *           - #ADI_ADC_INVALID_PARAMETER       [D] nAcqTimeInAClkCycles is not in the valid range
+ */
+ADI_ADC_RESULT adi_adc_SetAcquisitionTime (
+    ADI_ADC_HANDLE hDevice,
+    uint32_t       nAcqTimeInAClkCycles
+    )
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    uint16_t nCnvTime;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+
+    if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN))
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+ 
+    /* A valid range is 1u to the width of the SAMPTIME field + 1. */
+    if ((nAcqTimeInAClkCycles == 0u) || (nAcqTimeInAClkCycles > (ADI_MAX_ACQUISITION_TIME)))
+    {
+        return ADI_ADC_INVALID_PARAMETER;
+    }
+
+#endif /* ADI_DEBUG */
+
+    /* Acquisition phase is (ADC_CNV_TIME.SAMPTIME + 1) ACLK cycles */
+    nCnvTime = pDevice->pReg->CNV_TIME;
+    nCnvTime &= (uint16_t)(~BITM_ADC_CNV_TIME_SAMPTIME);
+    nCnvTime |= (uint16_t)((nAcqTimeInAClkCycles - ((uint32_t)1u)) << BITP_ADC_CNV_TIME_SAMPTIME);
+    pDevice->pReg->CNV_TIME = nCnvTime;
+
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Set the delay time of ADC in ADC cycles for multi iteration mode.
+ *
+ * @param [in]  hDevice              Handle to the device instance
+ *
+ * @param [in] nDelayInAClkCycles    Delay time in ADC clock cycles.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully set delay time
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_PARAMETER       [D] nDelayInAClkCycles is not in the valid range
+ */
+ADI_ADC_RESULT adi_adc_SetDelayTime (
+    ADI_ADC_HANDLE hDevice,
+    uint32_t nDelayInAClkCycles)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    uint16_t nCnvTime;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+
+    if (nDelayInAClkCycles > (BITM_ADC_CNV_TIME_DLY >> BITP_ADC_CNV_TIME_DLY))
+    {
+        return ADI_ADC_INVALID_PARAMETER;
+    }
+#endif /* ADI_DEBUG */
+
+    nCnvTime = pDevice->pReg->CNV_TIME;
+    nCnvTime &= (uint16_t)(~BITM_ADC_CNV_TIME_DLY);
+    nCnvTime |= (uint16_t)(nDelayInAClkCycles << BITP_ADC_CNV_TIME_DLY);
+    pDevice->pReg->CNV_TIME = nCnvTime;
+
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Set the resolution of ADC. he default resolution of ADC is 12-bit and the ADC increases the resolution
+ *           by oversampling. Averaging will be disabled when the resolution is more than 12-bits.
+ *
+ * @param [in]  hDevice       Handle to the device instance
+ *
+ * @param [in] eResolution    Enum of ADC resolution
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully set the resolution of the ADC.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API
+ *           - #ADI_ADC_INVALID_SEQUENCE        [D] Resolution cannot be changed when the ADC is enabled for sampling
+ *           - #ADI_ADC_INVALID_STATE           [D] Resolution cannot be changed from 12-bit if averaging is enabled
+ *           - #ADI_ADC_INVALID_PARAMETER           eResolution parameter passed is invalid.
+ */
+ADI_ADC_RESULT adi_adc_SetResolution (
+    ADI_ADC_HANDLE hDevice,
+    ADI_ADC_RESOLUTION eResolution)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    uint16_t nFactor;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) 
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+    if (IS_IN_ANY_STATE(ADC_STATUS_AVGERAGING_EN) && (eResolution != ADI_ADC_RESOLUTION_12_BIT)) 
+    {
+        return ADI_ADC_INVALID_STATE;
+    }
+#endif /* ADI_DEBUG */
+
+    switch (eResolution)
+    {
+    case ADI_ADC_RESOLUTION_12_BIT:
+        pDevice->pReg->AVG_CFG &= (uint16_t)(~BITM_ADC_AVG_CFG_OS);
+        if (IS_NOT_IN_STATE(ADC_STATUS_AVGERAGING_EN)) {
+          pDevice->pReg->AVG_CFG = 0u;
+        }
+        CLR_STATE(ADC_STATUS_OVERSAMPLING_EN);
+        break;
+
+    case ADI_ADC_RESOLUTION_13_BIT:
+    case ADI_ADC_RESOLUTION_14_BIT:
+    case ADI_ADC_RESOLUTION_15_BIT:
+    case ADI_ADC_RESOLUTION_16_BIT:
+        /* factor = 0x02 for 13-bit
+                    0x08 for 14-bit
+                    0x20 for 15-bit
+                    0x80 for 16-bit */
+        nFactor = (uint16_t)1u << (((uint16_t)eResolution * 2u) - ((uint16_t)1u));
+        pDevice->pReg->AVG_CFG =  BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN
+                                | (uint16_t)(nFactor << BITP_ADC_AVG_CFG_FACTOR);
+        SET_STATE(ADC_STATUS_OVERSAMPLING_EN);
+                                
+        break;
+
+    default:
+        return ADI_ADC_INVALID_PARAMETER;
+    }
+
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Enable Averaging for all ADC channels.
+ *
+ * @param [in] hDevice            Handle to the device instance
+ *
+ * @param [in] nAveragingSamples  Specifies the number of samples used for averaging. The valid value is between 1-256, in the steps of power of 2. 1 is for disabling averaging.
+ *                                The averaging require that the resolution of ADC is 12-bit.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully enabled averaging.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API  
+ *           - #ADI_ADC_INVALID_STATE           [D] Averaging cannot be enabled if the resolution is above 12bits
+ *           - #ADI_ADC_INVALID_PARAMETER       [D] nAveragingSamples parameter passed is invalid. 
+ */
+ADI_ADC_RESULT adi_adc_EnableAveraging (
+    ADI_ADC_HANDLE hDevice,
+    uint16_t        nAveragingSamples
+    )
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    uint16_t nFactor;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+
+    if ((nAveragingSamples == 0u) || (nAveragingSamples > 256u)
+        /* Or nAveragingSamples is not a power of 2 */
+        || ((nAveragingSamples & (nAveragingSamples - 1u)) != 0u))
+    {
+        return ADI_ADC_INVALID_PARAMETER;
+    }
+    if (IS_IN_STATE(ADC_STATUS_OVERSAMPLING_EN)) 
+    {
+        return ADI_ADC_INVALID_STATE;
+    }
+#endif /* ADI_DEBUG */
+
+    /* Disable averaging */
+    if (nAveragingSamples == 1u)
+    {
+        pDevice->pReg->AVG_CFG &= (uint16_t)(~BITM_ADC_AVG_CFG_EN);
+        CLR_STATE(ADC_STATUS_AVGERAGING_EN);
+    }
+    else
+    {
+        nFactor = nAveragingSamples >> 1;
+        pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_EN | (uint16_t)(nFactor << BITP_ADC_AVG_CFG_FACTOR);
+        SET_STATE(ADC_STATUS_AVGERAGING_EN);
+    }
+
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Configure low limit for an ADC channel when it is used as a digital comparator.
+ *
+ * @param [in] hDevice              Handle to the device instance
+ *
+ * @param [in] eChannel             The ADC channel for which to configure the comparator
+ *
+ * @param [in] bEnable              Enable or disable the low limit of the digital comparator
+ *
+ * @param [in] nLowLimit            The low limit of the digital comparator. If bEnable is false, this paramter is omitted.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully configured set the low limit.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_PARAMETER       [D] Parameters passed is not valid.
+ */
+ADI_ADC_RESULT adi_adc_SetLowLimit (
+    ADI_ADC_HANDLE   hDevice,
+    ADI_ADC_CHANNEL  eChannel,
+    bool             bEnable,
+    uint16_t         nLowLimit
+    )
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    static volatile uint16_t* pRegister[4] = {
+        pREG_ADC0_LIM0_LO, pREG_ADC0_LIM1_LO, pREG_ADC0_LIM2_LO, pREG_ADC0_LIM3_LO
+    };
+    int32_t nChannelNum = 0;
+    
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if ((nLowLimit > (BITM_ADC_LIM0_LO_VALUE >> BITP_ADC_LIM0_LO_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3))
+    {
+        return ADI_ADC_INVALID_PARAMETER;
+    }
+#endif /* ADI_DEBUG */
+        
+    nChannelNum = nGetChannelNumber(eChannel);
+    
+    if((nChannelNum >= 0) && (nChannelNum <= 3)) {
+      if (bEnable == true) {
+        
+        *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_LIM0_LO_VALUE)) | 
+          (uint16_t)(nLowLimit << BITP_ADC_LIM0_LO_VALUE);
+        
+        /* Now enable this channel comparitor - unused until the comparitor is enabled */   
+        pDevice->ComparitorLo |= (1u << nChannelNum);
+      }
+      else {
+        pDevice->ComparitorLo &= ~(1u << nChannelNum);
+      }
+    }
+
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Configure high limit for an ADC channel when it's used as a digital comparator.
+ *
+ * @param [in] hDevice              Handle to the device instance
+ *
+ * @param [in] eChannel             The ADC channel for which to configure the comparator
+ *
+ * @param [in] bEnable              Enable or disable the high limit of the digital comparator
+ *
+ * @param [in] nHighLimit           The high limit of the digital comparator. If bEnable is false, this paramter is omitted.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully set the high limit
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_PARAMETER       [D] Parameters passed is not valid.
+ */
+ADI_ADC_RESULT adi_adc_SetHighLimit (
+    ADI_ADC_HANDLE   hDevice,
+    ADI_ADC_CHANNEL  eChannel,
+    bool             bEnable,
+    uint16_t         nHighLimit)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    static volatile uint16_t* pRegister[4] = {
+        pREG_ADC0_LIM0_HI, pREG_ADC0_LIM1_HI, pREG_ADC0_LIM2_HI, pREG_ADC0_LIM3_HI
+    };
+    int32_t nChannelNum = 0;
+    
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if ((nHighLimit > (BITM_ADC_LIM0_HI_VALUE >> BITP_ADC_LIM0_HI_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3))
+    {
+        return ADI_ADC_INVALID_PARAMETER;
+    }
+#endif /* ADI_DEBUG */
+        
+    nChannelNum = nGetChannelNumber(eChannel);
+    
+    if((nChannelNum >= 0) && (nChannelNum <= 3)) {
+      if (bEnable == true) {
+        /* Set the given high value - only relevant if the limit is enabled. */
+        *pRegister[nChannelNum] =    (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_LIM0_HI_VALUE))
+          | (uint16_t)(nHighLimit << BITP_ADC_LIM0_HI_VALUE);
+        
+        /* Now enable this channel comparitor - unused until the comparitor is enabled */   
+        pDevice->ComparitorHi |= (1u << nChannelNum);
+      }
+      else {
+        pDevice->ComparitorHi &= ~(1u << nChannelNum);
+      }
+    }
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Configure hysteresis for an ADC channel when it's used as a digital comparator.
+ *
+ * @param [in] hDevice              Handle to the device instance
+ *
+ * @param [in] eChannel             The ADC channel for which to configure the comparator
+ *
+ * @param [in] bEnable              Enable or disable the hysteresis of the digital comparator
+ *
+ * @param [in] nHysteresis          The hysteresis to be used. If bEnable is false, this paramter is omitted.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully configured the comparator
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_PARAMETER       [D] Parameters passed is not valid.
+ */
+ADI_ADC_RESULT adi_adc_SetHysteresis (
+    ADI_ADC_HANDLE   hDevice,
+    ADI_ADC_CHANNEL  eChannel,
+    bool             bEnable,
+    uint16_t         nHysteresis)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    static volatile uint16_t* pRegister[4] = {
+        pREG_ADC0_HYS0, pREG_ADC0_HYS1, pREG_ADC0_HYS2, pREG_ADC0_HYS3
+    };
+    int32_t nChannelNum = 0;
+    
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if ((nHysteresis > (BITM_ADC_HYS0_VALUE >> BITP_ADC_HYS0_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3))
+    {
+        return ADI_ADC_INVALID_PARAMETER;
+    }
+#endif /* ADI_DEBUG */
+        
+    nChannelNum = nGetChannelNumber(eChannel);
+    
+    if((nChannelNum >= 0) && (nChannelNum <= 3)) {
+        if (bEnable == true) {
+          *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_HYS0_VALUE))
+                                  | (uint16_t)(nHysteresis << BITP_ADC_HYS0_VALUE);
+          
+          /* Now enable this channel hysteresis - unused until the comparitor is enabled */   
+          pDevice->ComparitorHys |= (1u << nChannelNum);
+        }
+        else {
+          pDevice->ComparitorHys &= ~(1u << nChannelNum);
+        }
+    }    
+
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Configure number of monitor cycles for an ADC channel when it's used as a digital comparator.
+ *
+ * @param [in] hDevice              Handle to the device instance
+ *
+ * @param [in] eChannel             The ADC channel for which to configure the comparator
+ *
+ * @param [in] nNumMonitorCycles    Number of Monitor cycles before giving interrupt
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully configured the comparator
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_PARAMETER       [D] Parameters passed is not valid.
+ */
+ADI_ADC_RESULT adi_adc_SetNumMonitorCycles(
+    ADI_ADC_HANDLE   hDevice,
+    ADI_ADC_CHANNEL  eChannel,
+    uint32_t         nNumMonitorCycles)
+{
+ #ifdef ADI_DEBUG
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+#endif /* ADI_DEBUG */
+    
+    static volatile uint16_t* pRegister[4] = {
+        pREG_ADC0_HYS0, pREG_ADC0_HYS1, pREG_ADC0_HYS2, pREG_ADC0_HYS3
+    };
+    int32_t nChannelNum = 0;
+    
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if ((nNumMonitorCycles > (BITM_ADC_HYS0_MONCYC >> BITP_ADC_HYS0_MONCYC)) || (nChannelNum < 0) || (nChannelNum > 3))
+    {
+        return ADI_ADC_INVALID_PARAMETER;
+    }
+#endif /* ADI_DEBUG */
+    
+    nChannelNum = nGetChannelNumber(eChannel);
+      
+    if((nChannelNum >= 0) && (nChannelNum <= 3)) {
+      *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_HYS0_MONCYC))
+        | (uint16_t)(nNumMonitorCycles << BITP_ADC_HYS0_MONCYC);
+    }
+    return ADI_ADC_SUCCESS;
+}
+
+
+
+/**
+ * @brief    Enable/Disable digital comparator for the given channel(s)
+ *
+ * @param [in] hDevice              Handle to the device instance
+ *
+ * @param [in] bEnableComparator    'true' to Enable and 'false' to disable
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully enabled/disabled digital comparator for the given channels
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_STATE           [D] Digital comparator cannot be enabled if sampling resolution is more than 12-bit or
+ *                                                  averaging is enabled. Comparator for a given channel cannot be enbaled if none of the limits
+ *                                                  are enabled for the given channel.
+ *           - #ADI_ADC_INVALID_SEQUENCE        [D] Comparator cannot be enabled when ADC is enabled for sampling.
+ *           - #ADI_ADC_INVALID_OPERATION       [D] Comparator require callback to be registered.
+ */
+ADI_ADC_RESULT adi_adc_EnableDigitalComparator (
+    ADI_ADC_HANDLE hDevice,
+    bool         bEnableComparator
+)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    
+    if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN)) 
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+    
+    if (IS_IN_ANY_STATE(ADC_STATUS_AVGERAGING_EN | ADC_STATUS_OVERSAMPLING_EN)) 
+    {
+        return ADI_ADC_INVALID_STATE;
+    }
+    
+    if (pDevice->pfCallback == NULL) {
+        return ADI_ADC_INVALID_OPERATION;
+    }
+    
+    if (bEnableComparator == true) {
+      if((pDevice->ComparitorHi | pDevice->ComparitorLo) == 0u) {
+        return ADI_ADC_INVALID_STATE;
+      }
+    }
+#endif /* ADI_DEBUG */
+    
+    EnableComparator(pDevice, bEnableComparator);
+    
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Submit the ADC buffer for processing to the ADC Module
+ *
+ * @param [in]  hDevice   Handle to the device instance.
+ * @param [in]  pBuffer   Pointer to the #ADI_ADC_BUFFER structure which contains details
+ *                        of the buffers required by the driver.
+ *
+ * @return  Status
+ *           - #ADI_ADC_SUCCESS                     Successfully submitted the buffer
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_NULL_POINTER            [D] pBuffer is NULL
+ *           - #ADI_ADC_INVALID_BUFFER          [D] Buffer parameters are invalid.
+ *
+ * @note    The driver will take ownership of the ADI_ADC_BUFFER structure passed to the driver.
+ *          The application has to make sure the structure is not used and it's scope is valid till
+ *          the structure is returned back to the application.
+ */
+ADI_ADC_RESULT adi_adc_SubmitBuffer (
+    ADI_ADC_HANDLE hDevice,
+    ADI_ADC_BUFFER*     pBuffer
+)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    uint32_t nNumChannels = 0u;
+
+    ADC_INT_BUFFER* pIntBuffer;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if (pBuffer == NULL) {
+        return ADI_ADC_NULL_POINTER;
+    }
+    if ((pBuffer->nChannels == 0u) || (pBuffer->pDataBuffer == NULL) || (pBuffer->nNumConversionPasses == 0u))
+    {
+        return ADI_ADC_INVALID_BUFFER;
+    }
+#endif /* ADI_DEBUG */
+
+    nNumChannels = GetNumChannels(pBuffer->nChannels);
+
+    pIntBuffer = &pDevice->s_Buffer;
+
+    pIntBuffer->nConfig = ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN;
+    pIntBuffer->nStatus = ADC_BUFFER_STATUS_OK;
+    if (pBuffer->nNumConversionPasses == 1u) 
+    {
+        pIntBuffer->nConfig |= ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN;
+    }
+    pIntBuffer->pUserBuffer = pBuffer;
+    pIntBuffer->pCurDataBuffer = pBuffer->pDataBuffer;
+    pIntBuffer->nNumSamplesRemaining = nNumChannels * pBuffer->nNumConversionPasses;
+    pIntBuffer->nChannels = pBuffer->nChannels;
+    
+    pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INIT);
+    
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Get a processed buffer from the ADC Driver. This function is a blocking call and will only return
+ *           once it has the buffer or if any error occurred. If a callback is registered then any call to this
+ *           function will fail.
+ *
+ * @param [in]  hDevice    Handle to the device instance.
+ * @param [out] ppBuffer   Pointer to a pointer to ADI_ADC_BUFFER structure. The returned pointer
+ *                         to ADI_ADC_BUFFER is written here.
+ *
+ * @return  Status
+ *           - #ADI_ADC_SUCCESS                     Successfully returned the buffer
+ *           - #ADI_ADC_INVALID_STATE               adi_adc_GetBuffer cannot be called when no buffer is given to the driver for processing.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_OPERATION       [D] adi_adc_GetBuffer cannot be used when callback is registered.
+ *           - #ADI_ADC_NULL_POINTER            [D] ppBuffer is NULL
+ *           - #ADI_ADC_INVALID_SEQUENCE        [D] adi_adc_GetBuffer cannot be used if non-blocking is not enabled.
+ *
+ */
+ADI_ADC_RESULT adi_adc_GetBuffer (
+    ADI_ADC_HANDLE hDevice,
+    ADI_ADC_BUFFER **ppBuffer)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    ADI_ADC_RESULT eADCresult = ADI_ADC_SUCCESS;
+    
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if (ppBuffer == NULL) {
+            return ADI_ADC_NULL_POINTER;
+    }
+    if (pDevice->pfCallback != NULL) {
+        return ADI_ADC_INVALID_OPERATION;
+    }
+    if (IS_NOT_IN_STATE(ADC_STATUS_NON_BLOCKING_EN)) {
+        return ADI_ADC_INVALID_SEQUENCE;
+    } 
+#endif /* ADI_DEBUG */
+
+    if (pDevice->s_Buffer.pUserBuffer == NULL) {
+      return ADI_ADC_INVALID_STATE;
+    }
+    
+    /* Wait for read completion */
+    SEM_PEND(pDevice, ADI_ADC_ERR_RTOS);
+    
+    if ((uint16_t)(pDevice->s_Buffer.nStatus & ADC_BUFFER_STATUS_OVERFLOW) != 0u) {
+        eADCresult =  ADI_ADC_BUFFER_OVERFLOW;
+    }
+    *ppBuffer = pDevice->s_Buffer.pUserBuffer;
+    pDevice->s_Buffer.pUserBuffer = NULL;
+    CLR_STATE(ADC_STATUS_NON_BLOCKING_EN);
+    
+    return eADCresult;
+}
+
+/**
+ * @brief   Enable/Disable ADC for sampling
+ *
+ * @param [in] hDevice    Handle to the device instance
+ *
+ * @param [in] bEnable    'true' to Enable and 'false' to disable
+ *
+ * @details
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Succesfully Enabled or disabled ADC for sampling
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_STATE           [D] Non-blocking cannot be enabled if comparator is enabled or any blocking API is in progress.
+ */
+ADI_ADC_RESULT adi_adc_Enable (
+    ADI_ADC_HANDLE hDevice,
+    bool         bEnable)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    
+    if (IS_IN_ANY_STATE(ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) {
+        return ADI_ADC_INVALID_STATE;
+    }
+#endif /* ADI_DEBUG */
+
+    if (bEnable == true) {
+        /* Set the driver to be in non-blocking mode */
+        SET_STATE(ADC_STATUS_NON_BLOCKING_EN);
+        
+        /* Enable the IRQs */
+        NVIC_EnableIRQ(ADC0_EVT_IRQn);
+   
+        /* Try to submit possible number of buffers */
+        InitBufferProcessing(pDevice);
+    } else {
+        /* Disble the IRQs */
+        NVIC_DisableIRQ(ADC0_EVT_IRQn);
+        
+        /* Abort any transaction if present */
+        pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_ABORT);
+        
+        CLR_STATE(ADC_STATUS_NON_BLOCKING_EN);
+    }
+
+    return ADI_ADC_SUCCESS;    
+}
+
+
+/**
+ * @brief    This function return whether a filled buffer is available to be returned to the user.
+ *           If this function return true, then a call to adi_adc_GetBuffer will not block
+ *
+ * @param [in]  hDevice               Handle to the device instance.
+ * @param [out] pbIsBufferAvailable   Pointer to a bool variable to which the availability of buffer will be written.
+ *                                    The variable will be set to 'true' if buffer is available else 'false'
+ *
+ * @return  Status
+ *           - #ADI_ADC_SUCCESS                     Successfully returned the status of the buffer availability
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_NULL_POINTER            [D] pbIsBufferAvailable is valid
+ *           - #ADI_ADC_INVALID_OPERATION       [D] adi_adc_IsBufferAvailable cannot be used when callback is registered.
+ *
+ */
+ADI_ADC_RESULT adi_adc_IsBufferAvailable (
+    ADI_ADC_HANDLE hDevice,
+    bool         *pbIsBufferAvailable)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if (pbIsBufferAvailable == NULL) 
+    {
+        return ADI_ADC_NULL_POINTER;
+    }
+    if (pDevice->pfCallback != NULL) {
+        return ADI_ADC_INVALID_OPERATION;
+    }
+#endif /* ADI_DEBUG */
+
+    if(IS_IN_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS))  
+    {
+        *pbIsBufferAvailable = false;
+    }
+    else
+    {
+        *pbIsBufferAvailable = true;
+    }
+
+    return ADI_ADC_SUCCESS;    
+}
+
+
+/**
+ * @brief   Sample the given channels for the given number of conversion passes and put it into the given buffer. This function only return after
+ *          the channels are sampled the given number of conversion times or if any error occurs. 
+ *
+ * @param [in] hDevice      Handle to the device instance
+ *
+ * @param [in] nChannels    Channels to sample. Should be an ORed value of ADI_ADC_CHANNEL types.
+ *
+ * @param [in] nNumConversionPasses  Number of conversion passes. In one conversion pass, the ADC will sample all the given channel(s) once.
+ *
+ * @param [in] pBuffer      Pointer to the buffer to which the sampled data is put.
+ *
+ * @param [in] nBuffLength  Length of the buffer. The length of the buffer should be at least
+ *                          2*(Num of Channels)*nNumConversionPasses bytes.
+ *
+ * @details Sample all the given channels for the given number of conversion passes and put the samples values into the given buffers. 
+ *          The channels will be sampled starting from the lower number. This function only return after
+ *          the channels are sampled the given number of conversion times or if any error occurs.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Succesfully Enabled or disabled ADC for sampling
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_PARAMETER       [D] Some parameter passed to the function is not valid
+ *           - #ADI_ADC_INVALID_SEQUENCE        [D] adi_adc_ReadChannels cannot be called if camparator is enabled or if 
+ *                                                  Non-blocking is enabled or if another blocking API is in progress.
+ */
+
+ADI_ADC_RESULT adi_adc_ReadChannels (
+    ADI_ADC_HANDLE hDevice,
+    uint32_t       nChannels,
+    uint32_t       nNumConversionPasses,
+    void           *pBuffer,
+    uint32_t       nBuffLength)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    uint32_t nNumChannels = 0u;
+    ADI_ADC_RESULT eADCresult = ADI_ADC_SUCCESS;
+
+    ADC_INT_BUFFER* pIntBuffer;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if ((nChannels == 0u) || (nNumConversionPasses == 0u) || (pBuffer == NULL)) 
+    {
+        return ADI_ADC_INVALID_PARAMETER;
+    }
+    if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) 
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+#endif /* ADI_DEBUG */
+
+    nNumChannels = GetNumChannels(nChannels);
+
+    if (nBuffLength < ((nNumChannels * sizeof(uint16_t)) * nNumConversionPasses))
+    {
+        return ADI_ADC_INSUFFICIENT_MEMORY;
+    }
+    
+    /* Clear ADC status */
+    pDevice->pReg->STAT = 0xFFFFu;
+
+    /* Set the driver to be in blocking mode */
+    SET_STATE(ADC_STATUS_BLOCKING_EN);
+
+    /* Get the buffer */
+    pIntBuffer = &pDevice->s_Buffer;    
+
+    pIntBuffer->nConfig = ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN;
+    if (nNumConversionPasses == 1u) {
+        pIntBuffer->nConfig |= ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN;
+    }
+    
+    pIntBuffer->nStatus = ADC_BUFFER_STATUS_OK;
+    pIntBuffer->pUserBuffer = NULL;
+    pIntBuffer->pCurDataBuffer = pBuffer;
+    pIntBuffer->nNumSamplesRemaining = nNumChannels * nNumConversionPasses;
+    pIntBuffer->nChannels = nChannels;
+    
+    pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INIT);
+    
+    InitBufferProcessing(pDevice);
+
+    /* Wait for read completion */
+    SEM_PEND(pDevice, ADI_ADC_ERR_RTOS);  
+    
+    if ((uint16_t)(pDevice->s_Buffer.nStatus & ADC_BUFFER_STATUS_OVERFLOW) != 0u) {
+        eADCresult =  ADI_ADC_BUFFER_OVERFLOW;
+    }
+
+    /* Driver is no longer in blocking mode */
+    CLR_STATE(ADC_STATUS_BLOCKING_EN);
+
+    /* Enable the IRQs */
+    NVIC_DisableIRQ(ADC0_EVT_IRQn);
+
+    return eADCresult;
+}
+
+
+/**
+ * @brief    Returns the battery voltage.
+ *
+ * @param [in]  hDevice        Handle to the device instance.
+ *
+ * @param [in]  nRefVoltage    Reference voltage in fixed point(16.16) format.
+ *
+ * @param [out] pnBatVoltage   Pointer to a variable to which the voltage of the battery will be written.
+ *                             The battery voltage will be in fixed point (16.16) format.
+ *
+ *
+ * @return  Status
+ *           - #ADI_ADC_SUCCESS                     Successfully retrieved the battery voltage.
+ *           - #ADI_ADC_BAD_SYS_CLOCK               Unable to obtain CLK which is needed to calculate
+ *                                                  voltage conversion timing values.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_NULL_POINTER            [D] pnBatVoltage is NULL
+ *           - #ADI_ADC_INVALID_SEQUENCE        [D] ADC sub system should be up and ADC should be free for getting the battery voltage.
+ */
+ADI_ADC_RESULT adi_adc_GetBatteryVoltage (
+    ADI_ADC_HANDLE hDevice,
+    uint32_t       nRefVoltage,
+    uint32_t       *pnBatVoltage)
+{
+    ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS;
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    uint16_t nConvTimeBackup;
+    uint16_t nAvgCfgBackup;
+    uint32_t nAdcValue = 0u;
+    uint32_t nClock = 0u;  
+    uint32_t nACLKDIVCNT;
+    
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if (pnBatVoltage == NULL) 
+    {
+        return ADI_ADC_NULL_POINTER;
+    }    
+    
+    if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+    
+    if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }    
+#endif /* ADI_DEBUG */
+
+    if(adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &nClock) == ADI_PWR_SUCCESS)
+    {
+        /* Take the backup of registers that need to be changed */
+        nConvTimeBackup = pDevice->pReg->CNV_TIME;
+        nAvgCfgBackup =  pDevice->pReg->AVG_CFG;
+        
+        /* Set the required value in the registers. */
+        nACLKDIVCNT = (*pREG_CLKG0_CLK_CTL1 & BITM_CLKG_CLK_CTL1_ACLKDIVCNT) >> BITP_CLKG_CLK_CTL1_ACLKDIVCNT;
+        
+        /* Calculate the number of cycles required for conversion. 
+         * The conversion time required is 500ns = 2000000Hz 
+         */
+        nClock = nClock/nACLKDIVCNT;  /* nClock = ACLK frequency Hz */
+        pDevice->pReg->CNV_TIME = (uint16_t)((nClock/2000000u) + ((uint16_t)1u)); 
+        pDevice->pReg->AVG_CFG = 0u;
+        
+        /* Clear the battery done status */
+        pDevice->pReg->STAT = BITM_ADC_STAT_BATDONE;
+        
+        /* Clear the battery done state */
+        CLR_STATE(ADC_STATUS_BATTERY_DONE);
+        
+        /* Set the registers */
+        pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_BAT);
+        
+        /* Wait for the Battery done status */
+        while (IS_NOT_IN_STATE(ADC_STATUS_BATTERY_DONE)) { ; }
+        
+        /* Clear the conversion register */
+        pDevice->pReg->CNV_CFG = 0u;
+        
+        /* Restore the changed registers */
+        pDevice->pReg->CNV_TIME = nConvTimeBackup;
+        pDevice->pReg->AVG_CFG = nAvgCfgBackup;
+        
+        /* Calculate the battery voltage */
+        
+        /* From HRM: converting ADC result to battery voltage, following calculations should be done: 
+         * VBAT = 4 * (adc_out) * Vref / (2^12 - 1) */
+         nAdcValue = pDevice->pReg->BAT_OUT;
+        *pnBatVoltage = (4u * nAdcValue * nRefVoltage) / ADI_ADC_SAMPLE_MAX;
+    }
+    else
+    {
+         eResult = ADI_ADC_BAD_SYS_CLOCK;
+    }
+        
+    return eResult;
+}
+/**
+ * @brief    Enable or disable the temperature sensor
+ *
+ * @param [in]  hDevice  Handle to the device instance.
+ *
+ * @param [in]  bEnable  'true' to enable and 'false' to disable the temperature sensor
+ *
+ *
+ * @return  Status
+ *           - #ADI_ADC_SUCCESS                     Successfully enabled/disabled the temperature sensor
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ */
+ADI_ADC_RESULT adi_adc_EnableTemperatureSensor (
+    ADI_ADC_HANDLE hDevice,
+    bool         bEnable)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+#endif /* ADI_DEBUG */
+
+    if (bEnable == true)
+    {
+        pDevice->pReg->CFG |= (uint16_t)BITM_ADC_CFG_TMPEN;
+        SET_STATE(ADC_STATUS_TEMP_SENSOR_EN);
+    }
+    else
+    {
+        pDevice->pReg->CFG &= (uint16_t)(~BITM_ADC_CFG_TMPEN);
+        CLR_STATE(ADC_STATUS_TEMP_SENSOR_EN);
+    }
+
+    return ADI_ADC_SUCCESS;
+}
+
+
+/**
+ * @brief    Return the temperature in fixed point format in degree Celcius.
+ *
+ * @param [in]  hDevice        Handle to the device instance.
+ *
+ * @param [in]  nRefVoltage    Reference voltage in fixed point(16.16) format.
+ *
+ * @param [out] pnTemperature  Pointer to a variable to which the ADC die temperature (in degree Celsius) will be written.
+ *                             The temperature will be in fixed point (16.16) format.
+ *
+ *
+ * @return  Status
+ *           - #ADI_ADC_SUCCESS                     Successfully retrieved the die temperature
+ *           - #ADI_ADC_BAD_SYS_CLOCK               Unable to obtain CLK which is needed to calculate
+ *                                                  temperature conversion timing values.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_NULL_POINTER            [D] pnBatVoltage is NULL
+ *           - #ADI_ADC_INVALID_SEQUENCE        [D] ADC sub system should be up and ADC should be free for getting the battery voltage. The Temperator
+ *                                                  sensor also need to be enabled.
+ *           - #ADI_ADC_INVALID_STATE           [D] Temperature sensor require an aquisition time of 65us and that cannot be set with the current
+ *                                                  ACLK since only ACLK of 255 can be stored to the sampling register. Decrease the ACLK clock to 
+ *                                                  rectify this.
+ */
+ADI_ADC_RESULT adi_adc_GetTemperature (
+    ADI_ADC_HANDLE  hDevice,
+    uint32_t        nRefVoltage,
+    int32_t*        pnTemperature
+    )
+{
+    ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS;
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    uint16_t nConvTimeBackup;
+    uint16_t nAvgCfgBackup;
+    uint32_t nAdcTmpValue = 0u;
+    uint32_t nAdcTmp2Value = 0u;
+    uint32_t nClock = 0u;  
+    uint32_t nACLKDIVCNT;
+    uint32_t nCnvTime;
+    
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if (pnTemperature == NULL) 
+    {
+        return ADI_ADC_NULL_POINTER;
+    } 
+    
+    if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN | ADC_STATUS_TEMP_SENSOR_EN))
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+        
+    if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN))
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }    
+#endif    
+    
+    
+    if(adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &nClock) == ADI_PWR_SUCCESS)
+    {    
+      /* Calculate the conversion time */
+      nACLKDIVCNT = (*pREG_CLKG0_CLK_CTL1 & BITM_CLKG_CLK_CTL1_ACLKDIVCNT) >> BITP_CLKG_CLK_CTL1_ACLKDIVCNT;
+      nCnvTime = ((nClock / nACLKDIVCNT) / (uint16_t)15385u) + 1u;   /* 65us acquisition time required = 15385Hz sample */
+      
+    #ifdef ADI_DEBUG
+      if (nCnvTime >= 256u) {
+          return ADI_ADC_INVALID_STATE;
+      }
+    #endif
+      /* Take the backup of registers that need to be changed */
+      nConvTimeBackup = pDevice->pReg->CNV_TIME;
+      nAvgCfgBackup =  pDevice->pReg->AVG_CFG;
+      
+      /* Set the required value in the registers. */
+      
+      pDevice->pReg->CNV_TIME = (uint16_t)((nCnvTime << BITP_ADC_CNV_TIME_SAMPTIME) & BITM_ADC_CNV_TIME_SAMPTIME);
+      pDevice->pReg->AVG_CFG = 0u;
+      
+      /* Clear the temperature done status */
+      pDevice->pReg->STAT =  BITM_ADC_STAT_TMPDONE | BITM_ADC_STAT_TMP2DONE;
+      
+      /* Clear the temperature done state */
+      CLR_STATE(ADC_STATUS_TMP_DONE | ADC_STATUS_TMP2_DONE);
+      
+      /* Sample Tmp register */
+      pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_TMP);
+      while (IS_NOT_IN_STATE(ADC_STATUS_TMP_DONE)) { ; }
+      nAdcTmpValue = pDevice->pReg->TMP_OUT;
+      pDevice->pReg->CNV_CFG = 0u;
+      
+      
+      /* Sample Tmp2 register */
+      pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_TMP2);
+      while (IS_NOT_IN_STATE(ADC_STATUS_TMP2_DONE)) { ; }
+      pDevice->pReg->CNV_CFG = 0u;
+      nAdcTmp2Value = pDevice->pReg->TMP2_OUT;
+
+      /* Restore the changed registers */
+      pDevice->pReg->CNV_TIME = nConvTimeBackup;
+      pDevice->pReg->AVG_CFG = nAvgCfgBackup;
+      
+      /* Calculate the temperature voltage.
+       * From the HRM: Temperature can be calculated as:
+       *
+       * T(^0 C)= code1/(code2+RG*code1)*Rvirtualreference/(ideal_sensitivity )-273.15
+       * 
+       * Some of these values are constants, and some have been read from registers.
+       * The above formula, when populated with variables and constants, would look like this:
+       * T(^0 C)= (nAdcTmpValue/(nAdcTmp2Value + nTempRG * nAdcTmpValue)) * (1.2256/1.2411e-3)) -273.15
+       */
+      {
+          uint32_t nRVirRefByIdealSensitivity = 2070960834u; /* 1.2256/1.2411e-3 in 11.21 format */
+          
+          uint32_t nTempRG = 19380u; /* 1.1829 in 2.14 format */
+          uint32_t nTmp2 = ((nAdcTmp2Value << 14u) + (nTempRG * nAdcTmpValue)); /* in 14.14 format */
+          
+          uint32_t nOffsetPart = (335544320u/nRefVoltage); /* (1.25 in 4.28 format / ReferenceVoltage(16.16)) = Result in format *.12 */
+          uint32_t nOffset = (161u * nOffsetPart);         /* 12.12 format */
+          
+          uint32_t nTmp3  = ((nAdcTmpValue << 12) - nOffset) << 8u;  /* Format 12.20 */
+          uint32_t nRatio = (nTmp3/(nTmp2 >> 10u));  /* nTmp2 resolution reduced by 10 to 14.4 and the result resolution is 0.16 */
+          uint32_t nTemp  = (nRatio * (nRVirRefByIdealSensitivity >> 16u)) >> 5u;  /* Temperature in degree kelvin in 16.16 format */
+          
+          int32_t  iTemp = (int32_t)nTemp - ((int32_t)17901158);   /* Subtract 273.15 (in 16.16) to get the temperature in degree celcius */
+          *pnTemperature = iTemp;
+      }
+    }
+    else
+    {
+       eResult = ADI_ADC_BAD_SYS_CLOCK;
+    }
+
+    return eResult;
+}
+
+
+/*! \cond PRIVATE */
+
+/*==========  S T A T I C    F U N C T I O N S  ==========*/
+/* Read the output register for the given channel number */
+static uint16_t ReadOutReg(uint32_t nChannelNum)
+{
+    const volatile uint16_t* pOutRegister = pREG_ADC0_CH0_OUT;
+    pOutRegister += nChannelNum*2u;
+    return *pOutRegister;
+}
+
+/* Init buffer processing */
+static bool InitBufferProcessing(ADI_ADC_DEVICE *pDevice)
+{
+    uint32_t nCnvReg = ((uint32_t)(pDevice->pReg->CNV_CFG) & BITM_ADC_CNV_CFG_DMAEN);
+    ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer;
+    
+    if (IS_NOT_IN_ANY_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS)) 
+    {
+        /* Clear conversion done flags */
+        pDevice->pReg->STAT = 0xFFFFu;
+        
+        /* Clear the overflow and alert register */
+        pDevice->pReg->OVF = 0xFFFFu;
+    }
+    
+    /* Calculate the conversion register value for the given configuration */
+    nCnvReg |= pIntBuffer->nChannels;
+    if ((uint16_t)(pIntBuffer->nConfig & ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN) != 0u) {
+        nCnvReg |= BITM_ADC_CNV_CFG_AUTOMODE;
+    }    
+    if ((pIntBuffer->nConfig & ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN) != 0u) {
+        nCnvReg |= BITM_ADC_CNV_CFG_SINGLE;
+    } else {
+        nCnvReg |= BITM_ADC_CNV_CFG_MULTI;
+    }    
+
+    SET_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS);
+
+    pDevice->pReg->CNV_CFG |= (uint16_t)nCnvReg;
+    
+    pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_ENABLED);
+
+    return true;
+}
+
+
+#if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1
+/* DMA Callback Handler */
+void DMA_ADC0_Int_Handler (void)
+{
+    ISR_PROLOG();
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *) AdcDevInfo[0].hDevice;
+    
+    DmaFIFOManage(pDevice, ADC_FIFO_MODE_DMA_BUFFER_PROCESS);
+    
+    ISR_EPILOG();
+}
+
+static ADI_ADC_RESULT DmaFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode)
+{
+    uint16_t nCount = 0u;
+    uint16_t chanNum = ADC0_CHANn;
+    uint16_t IRQ_Backup;
+    
+    ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer;
+    
+    if(pDevice->s_Buffer.pCurDataBuffer == NULL) {
+        /* If there is nothing active... */
+        if (eFifoMode == ADC_FIFO_MODE_INTERRUPT_PROCESS) {
+            /* ...it's something leftover, so cleanup. */
+            uint16_t nStat = pDevice->pReg->STAT & 0x00FFu;
+            FlushFifo(pDevice, (uint32_t)nStat);
+            pDevice->pReg->STAT = nStat;
+        }
+    }
+    else {
+        switch (eFifoMode)
+        {
+        case ADC_FIFO_MODE_INIT:
+
+              /* Enable the interrupt for the given DMA */
+              NVIC_EnableIRQ(DMA0_CH24_DONE_IRQn);
+              
+              pADI_DMA0->SRCADDR_CLR = 1U << chanNum;
+
+              /* Enable the channel */
+              pADI_DMA0->EN_SET = 1U << chanNum;
+              
+              /* Enables  peripheral to generate DMA requests. */
+              pADI_DMA0->RMSK_CLR = 1U << chanNum;
+
+              /* Set the primary as the current DMA descriptor */
+              pADI_DMA0->ALT_CLR = 1U << chanNum;  /* Should be default */
+                            
+              /* Setup the DMA registers */
+              nCount = (uint16_t)pIntBuffer->nNumSamplesRemaining;
+
+              /* Point to the end of the DMA source */
+              pPrimaryCCD[chanNum].DMASRCEND =   (uint32_t)(&(pDevice->pReg->DMA_OUT));
+              
+              /* Point to the end of the DMA write-to destination */ 
+              pPrimaryCCD[chanNum].DMADSTEND =   (uint32_t)((void*)pIntBuffer->pCurDataBuffer) + ((nCount * 2u) - 1u);
+              
+              /* Configure the DMA itself */
+              pPrimaryCCD[chanNum].DMACDC =         ((ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_DST_INC) |            /* Increment destination address */
+                                                    (ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) |               /* Don't increment the source address */
+                                                    ((uint32_t)ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) |           /* 16bit transfers */
+                                                    ((nCount - (uint32_t)1U)<< DMA_BITP_CTL_N_MINUS_1) |        /* Data size? */
+                                                    (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL) |  /*  Basic only */
+                                                    ((uint32_t)ADI_DMA_RPOWER_1 << DMA_BITP_CTL_R_POWER));                /* Arbitration */
+          
+              /* Enable DMA */
+              pDevice->pReg->CNV_CFG |= BITM_ADC_CNV_CFG_DMAEN;
+            break;
+
+        case ADC_FIFO_MODE_ENABLED:
+            break;
+
+        case ADC_FIFO_MODE_INTERRUPT_PROCESS:
+            /* Clear the status registers */
+            pDevice->pReg->STAT = (pDevice->pReg->STAT & 0x00FFu);
+            break;
+
+        case ADC_FIFO_MODE_INTERRUPT_OVERFLOW:
+            pIntBuffer->nStatus |= ADC_BUFFER_STATUS_OVERFLOW;
+            break;
+      
+        case ADC_FIFO_MODE_DMA_BUFFER_PROCESS:
+            pIntBuffer->nNumSamplesRemaining = 0u;
+            ManageFifoCompletion(pDevice);
+            break;
+            
+        case ADC_FIFO_MODE_ABORT:
+     
+            /* Take backup of IRQ */
+            IRQ_Backup = pDevice->pReg->IRQ_EN;
+
+            /* Disable the IRQ */
+            pDevice->pReg->IRQ_EN = 0u;
+
+            /* Clear the conversion cfg register to stop any transaction */
+            pDevice->pReg->CNV_CFG = 0u;
+            
+            /* Disable the DMA channel */
+            pADI_DMA0->EN_CLR = 1U << chanNum;
+              
+            /* Clear the status bits */
+            pDevice->pReg->STAT =  pDevice->pReg->STAT;
+      
+            /* Clear the sampling in progress state */
+            CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS);
+            
+            /* Read and flush all the buffers */
+            FlushFifo(pDevice, 0x00FFu);
+          
+            /* Restore the IRQ */
+            pDevice->pReg->IRQ_EN = IRQ_Backup;      
+          
+            break;
+
+        default:
+            break;
+        } 
+    }
+    
+    return ADI_ADC_SUCCESS;
+}
+#else /* else ADI_ADC_ENABLE_MULTI_ACQUIRE == 0 */
+
+static ADI_ADC_RESULT InterruptFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode)
+{
+    ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer;
+    
+    if(pDevice->s_Buffer.pCurDataBuffer == NULL) {
+        if (eFifoMode == ADC_FIFO_MODE_INTERRUPT_PROCESS) {
+            uint16_t nStat = pDevice->pReg->STAT & 0x00FFu;
+            FlushFifo(pDevice, (uint32_t)nStat);
+            pDevice->pReg->STAT = nStat;
+        }
+        return ADI_ADC_SUCCESS;
+    }
+
+    switch (eFifoMode)
+    {
+    case ADC_FIFO_MODE_INIT:
+        {
+            /* Enable the conversion done and overflow interrupt */
+            pDevice->ActData.nCurChannel = 0u;
+        }
+        break;
+
+    case ADC_FIFO_MODE_ENABLED:
+        break;
+
+    case ADC_FIFO_MODE_INTERRUPT_PROCESS:
+        {
+            while (pIntBuffer->nNumSamplesRemaining > 0u) {
+                uint32_t nConvStatus = ((uint32_t)pDevice->pReg->STAT & (uint32_t)0x00FFu);
+                if ((nConvStatus & 0x00FFu) == 0u)
+                {
+                    break;
+                }
+                
+                uint32_t nCurChannelBitM = ((uint32_t)1u << pDevice->ActData.nCurChannel);
+                while ((nCurChannelBitM & nConvStatus) == 0u) {
+                    pDevice->ActData.nCurChannel++;
+                    if (pDevice->ActData.nCurChannel >= NUM_ADC_CHANNELS) {
+                        pDevice->ActData.nCurChannel = 0u;
+                    }
+                    nCurChannelBitM = ((uint32_t)1u << pDevice->ActData.nCurChannel);
+                }
+                
+                assert ((pIntBuffer->nChannels & ((uint32_t)1u << pDevice->ActData.nCurChannel)) != 0u);
+                
+                *pIntBuffer->pCurDataBuffer = ReadOutReg( pDevice->ActData.nCurChannel);
+                pIntBuffer->pCurDataBuffer++;
+                
+                
+                pDevice->pReg->STAT = (uint16_t)nCurChannelBitM;
+                pIntBuffer->nNumSamplesRemaining -= 1u;
+
+                pDevice->ActData.nCurChannel += 1u;
+                if ( pDevice->ActData.nCurChannel >= NUM_ADC_CHANNELS) {
+                     pDevice->ActData.nCurChannel = 0u;
+                }
+            }
+
+            if (pIntBuffer->nNumSamplesRemaining == 0u) {
+                ManageFifoCompletion(pDevice);
+            }
+        }
+        break;
+        
+    case ADC_FIFO_MODE_INTERRUPT_OVERFLOW:
+        {
+            pIntBuffer->nStatus |= ADC_BUFFER_STATUS_OVERFLOW;
+        }
+        break;
+        
+    case ADC_FIFO_MODE_ABORT:
+        {
+          uint16_t IRQ_Backup;
+    
+          /* Take backup of IRQ */
+          IRQ_Backup = pDevice->pReg->IRQ_EN;
+
+          /* Disable the IRQ */
+          pDevice->pReg->IRQ_EN = 0u;
+
+          /* Clear the conversion cfg register to stop any transaction */
+          pDevice->pReg->CNV_CFG = 0u;
+          
+          /* Clear the status bits */
+          pDevice->pReg->STAT =  pDevice->pReg->STAT;
+    
+          /* Clear the sampling in progress state */
+          CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS);
+
+          /* Read and flush all the buffers */
+          FlushFifo(pDevice, 0x00FFu);
+        
+          /* Restore the IRQ */
+          pDevice->pReg->IRQ_EN = IRQ_Backup; 
+        }
+        break;
+
+    default:
+        break;
+    }
+    
+    return ADI_ADC_SUCCESS;
+}
+#endif 
+
+static void FlushFifo(ADI_ADC_DEVICE *pDevice, uint32_t nChannels)
+{
+    uint32_t x;
+    for (x = 0u; x < 8u; x++) {
+      if ((nChannels & ((uint32_t)1u << x)) != 0u) {
+          ReadOutReg(x);
+      }
+    }
+}
+
+
+/* Called when a transfer is complete */
+static void ManageFifoCompletion(ADI_ADC_DEVICE *pDevice)
+{   
+    /* Clear the conversion configuration */
+    pDevice->pReg->CNV_CFG = 0u;
+    CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS);
+    
+    SEM_POST(pDevice);
+}
+
+
+/* Internal function to extract the number of channels
+ * in a 32bit word.  */
+static uint32_t GetNumChannels(uint32_t nChannels)
+{
+    uint32_t n = nChannels & 0x000000FFu;
+
+    n = (n & 0x00000055u) + ((n >> 1u) & 0x00000055u);
+    n = (n & 0x00000033u) + ((n >> 2u) & 0x00000033u);
+    n = (n + (n >> 4u)) & (0x0000000Fu);
+
+    return n;
+}
+
+/* Returns the channel number based on the ADI_ADC_CHANNEL type.
+ *  i.e. ADI_ADC_CHANNEL1 returns 1. */
+static int32_t nGetChannelNumber(ADI_ADC_CHANNEL eChannel)
+{
+    int32_t retVal = 0;
+    uint32_t nChannel = (uint32_t)eChannel & 0x000000FFu;
+    
+    if ((nChannel & (nChannel - (uint32_t)1u)) != 0u) {
+        return -1;
+    }
+    if ((nChannel & 0x000000AAu) != 0u) { retVal += 1; }
+    if ((nChannel & 0x000000CCu) != 0u) { retVal += 2; }
+    if ((nChannel & 0x000000F0u) != 0u) { retVal += 4; }
+    
+    return retVal;
+}
+
+/* Internal function to set static configuration options. */
+static void StaticConfiguration(ADI_ADC_DEVICE *pDevice)
+{
+    uint16_t nCfgReg = 0u;
+
+    /* Configure the resolution */
+#if ADI_ADC_CFG_RESOLUTION == 12
+    pDevice->pReg->AVG_CFG = 0u; 
+#else    
+
+#if ADI_ADC_CFG_RESOLUTION == 13
+    pDevice->pReg->AVG_CFG =  BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0002u << BITP_ADC_AVG_CFG_FACTOR);
+#elif ADI_ADC_CFG_RESOLUTION == 14     
+    pDevice->pReg->AVG_CFG =  BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0008u << BITP_ADC_AVG_CFG_FACTOR);
+#elif ADI_ADC_CFG_RESOLUTION == 15
+    pDevice->pReg->AVG_CFG =  BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0020u << BITP_ADC_AVG_CFG_FACTOR);
+#elif ADI_ADC_CFG_RESOLUTION == 16     
+    pDevice->pReg->AVG_CFG =  BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0080u << BITP_ADC_AVG_CFG_FACTOR);
+#else
+#error "Invalid Resolution"    
+#endif
+
+    SET_STATE(ADC_STATUS_OVERSAMPLING_EN);    
+#endif
+
+    /* Configure the VREF */
+#if ADI_ADC_CFG_VREF == 0     /* 1.25V Internal Reference*/
+    nCfgReg |= BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL;
+#elif ADI_ADC_CFG_VREF == 1     /* 2.5V Internal Reference */    
+    nCfgReg |= BITM_ADC_CFG_REFBUFEN;
+#elif ADI_ADC_CFG_VREF == 2     /* Battery Voltage */    
+    nCfgReg |= BITM_ADC_CFG_VREFVBAT;
+#endif
+    
+    pDevice->pReg->CFG = nCfgReg;
+
+#if ADI_ADC_ENABLE_STATIC_COMPARATOR == 1
+    /* High limit registers */
+#if ADI_ADC_COMPARATOR_AIN0_HI_EN == 1
+    pDevice->pReg->LIM0_HI = ADI_ADC_COMPARATOR_AIN0_HI_VAL;
+    pDevice->ComparitorHi |= ADI_ADC_CHANNEL_0;
+#endif
+#if ADI_ADC_COMPARATOR_AIN1_HI_EN == 1
+    pDevice->pReg->LIM1_HI = ADI_ADC_COMPARATOR_AIN1_HI_VAL;
+    pDevice->ComparitorHi |= ADI_ADC_CHANNEL_1;
+#endif
+#if ADI_ADC_COMPARATOR_AIN2_HI_EN == 1
+    pDevice->pReg->LIM2_HI = ADI_ADC_COMPARATOR_AIN2_HI_VAL;
+    pDevice->ComparitorHi |= ADI_ADC_CHANNEL_2;
+#endif
+#if ADI_ADC_COMPARATOR_AIN3_HI_EN == 1
+    pDevice->pReg->LIM3_HI = ADI_ADC_COMPARATOR_AIN3_HI_VAL;
+    pDevice->ComparitorHi |= ADI_ADC_CHANNEL_3;
+#endif
+    /* Low limit registers */
+#if ADI_ADC_COMPARATOR_AIN0_LO_EN == 1
+    pDevice->pReg->LIM0_LO = (uint16_t)ADI_ADC_COMPARATOR_AIN0_LO_VAL;
+    pDevice->ComparitorLo |= ADI_ADC_CHANNEL_0;
+#endif
+#if ADI_ADC_COMPARATOR_AIN1_LO_EN == 1
+    pDevice->pReg->LIM1_LO = ADI_ADC_COMPARATOR_AIN1_LO_VAL;
+    pDevice->ComparitorLo |= ADI_ADC_CHANNEL_1;
+#endif
+#if ADI_ADC_COMPARATOR_AIN2_LO_EN == 1
+    pDevice->pReg->LIM2_LO = ADI_ADC_COMPARATOR_AIN2_LO_VAL;
+    pDevice->ComparitorLo |= ADI_ADC_CHANNEL_2;
+#endif
+#if ADI_ADC_COMPARATOR_AIN3_LO_EN == 1
+    pDevice->pReg->LIM3_LO = ADI_ADC_COMPARATOR_AIN3_LO_VAL;
+    pDevice->ComparitorLo |= ADI_ADC_CHANNEL_3;
+#endif
+    
+    /* Hysteresis registers */
+#if ADI_ADC_COMPARATOR_AIN0_HYS_EN == 1
+    pDevice->pReg->HYS0 = (uint16_t)(ADI_ADC_COMPARATOR_AIN0_HYS_VAL | (ADI_ADC_COMPARATOR_AIN0_HYS_CYC << BITP_ADC_HYS0_MONCYC));
+    pDevice->ComparitorHys |= ADI_ADC_CHANNEL_0;
+#endif
+#if ADI_ADC_COMPARATOR_AIN1_HYS_EN == 1
+    pDevice->pReg->HYS1 = (ADI_ADC_COMPARATOR_AIN1_HYS_VAL | (ADI_ADC_COMPARATOR_AIN1_HYS_CYC << BITP_ADC_HYS0_MONCYC));
+    pDevice->ComparitorHys |= ADI_ADC_CHANNEL_1;
+#endif
+#if ADI_ADC_COMPARATOR_AIN2_HYS_EN == 1
+    pDevice->pReg->HYS2 = (ADI_ADC_COMPARATOR_AIN2_HYS_VAL | (ADI_ADC_COMPARATOR_AIN2_HYS_CYC << BITP_ADC_HYS0_MONCYC));
+    pDevice->ComparitorHys |= ADI_ADC_CHANNEL_2;
+#endif
+#if ADI_ADC_COMPARATOR_AIN3_HYS_EN == 1
+    pDevice->pReg->HYS3 = (ADI_ADC_COMPARATOR_AIN3_HYS_VAL | (ADI_ADC_COMPARATOR_AIN3_HYS_CYC << BITP_ADC_HYS0_MONCYC));
+    pDevice->ComparitorHys |= ADI_ADC_CHANNEL_3;
+#endif
+#endif
+
+}
+
+/* Internal function to enable the comparitor for previously-configured channels
+ * Does not set the limits, only enables. 
+*/
+static void EnableComparator(ADI_ADC_DEVICE *pDevice, bool bEnable)
+{
+    uint32_t x;
+    uint16_t nCnvCfg = 0u;
+    volatile uint16_t* pLO_Register[4]  = {pREG_ADC0_LIM0_LO, pREG_ADC0_LIM1_LO, pREG_ADC0_LIM2_LO, pREG_ADC0_LIM3_LO};
+    volatile uint16_t* pHI_Register[4]  = {pREG_ADC0_LIM0_HI, pREG_ADC0_LIM1_HI, pREG_ADC0_LIM2_HI, pREG_ADC0_LIM3_HI};
+    volatile uint16_t* pHYS_Register[4] = {pREG_ADC0_HYS0,    pREG_ADC0_HYS1,    pREG_ADC0_HYS2,    pREG_ADC0_HYS3};
+    
+    if (bEnable == true)
+    {
+      /* Loop round all the channels enabling each part if required. */
+      for (x = 0u; x < NUM_ADC_COMPARATOR_CHANNELS; x++) {
+          if((pDevice->ComparitorHi & (1u << x)) > 0u) {
+            *pHI_Register[x] |= BITM_ADC_LIM0_HI_EN;
+          }
+          if((pDevice->ComparitorLo & (1u << x)) > 0u) {
+            *pLO_Register[x] |= BITM_ADC_LIM0_LO_EN;
+          }
+          if((pDevice->ComparitorHys & (1u << x)) > 0u) {
+            *pHYS_Register[x] |= BITM_ADC_HYS0_EN;
+          }
+      }      
+      nCnvCfg = (uint16_t)((uint16_t)pDevice->ComparitorHi | (uint16_t)pDevice->ComparitorLo);
+      
+      pDevice->pReg->IRQ_EN &= (uint16_t)(~BITM_ADC_IRQ_EN_CNVDONE);
+      pDevice->pReg->CNV_CFG = (uint16_t)nCnvCfg | (uint16_t)(BITM_ADC_CNV_CFG_MULTI | BITM_ADC_CNV_CFG_AUTOMODE);
+      SET_STATE(ADC_STATUS_COMPARATOR_EN);
+    }    
+    else {
+      /* Loop round disabling all. */
+      for (x = 0u; x < NUM_ADC_COMPARATOR_CHANNELS; x++) {
+            *pHI_Register[x]  &= (uint16_t)(~(BITM_ADC_LIM0_HI_EN));
+            *pLO_Register[x]  &= (uint16_t)(~(BITM_ADC_LIM0_LO_EN));
+            *pHYS_Register[x] &= (uint16_t)(~(BITM_ADC_HYS0_EN));
+        }
+        pDevice->pReg->CNV_CFG = 0u;
+        pDevice->pReg->STAT = pDevice->pReg->STAT & 0x00FFu;
+        CLR_STATE(ADC_STATUS_COMPARATOR_EN);
+        pDevice->pReg->IRQ_EN |= BITM_ADC_IRQ_EN_CNVDONE;
+    }
+}
+
+
+/* In Handler handles the following cases:
+ * ADI_ADC_EVENT_ADC_READY
+ * ADI_ADC_EVENT_CALIBRATION_DONE
+ * ADC_STATUS_BATTERY_DONE
+ * ADC_STATUS_TMP_DONE
+ * ADC_STATUS_TMP2_DONE
+ * ADI_ADC_EVENT_HIGH_LIMIT_CROSSED
+ * ADI_ADC_EVENT_LOW_LIMIT_CROSSED
+*/
+#if defined(__ADUCM302x__)
+void ADC_Int_Handler(void)
+#else
+void ADC0_Int_Handler(void)
+#endif
+{
+    ADI_ADC_DEVICE *pDevice;
+    ISR_PROLOG();
+    
+    pDevice = (ADI_ADC_DEVICE *) AdcDevInfo[0].hDevice;
+    
+    if ((pDevice->pReg->STAT & 0x00FFu) != 0u) {
+        if (IS_NOT_IN_STATE(ADC_STATUS_COMPARATOR_EN)) {
+            pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INTERRUPT_PROCESS);
+        } else {
+            pDevice->pReg->STAT = pDevice->pReg->STAT & (0x00FFu);
+        }
+    }
+    if ((uint16_t)(pDevice->pReg->STAT & 0xFF00u) != 0u) {
+        if ((pDevice->pReg->STAT & BITM_ADC_STAT_RDY) != 0u) {
+            SET_STATE(ADC_STATUS_SUB_SYSTEM_READY);
+            pDevice->pReg->STAT = BITM_ADC_STAT_RDY;
+            if (pDevice->pfCallback != NULL) {
+                pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_ADC_READY, NULL);
+            }
+        }
+        if ((pDevice->pReg->STAT & BITM_ADC_STAT_CALDONE) != 0u) {
+            SET_STATE(ADC_STATUS_CALIBRATION_DONE);
+            pDevice->pReg->STAT = BITM_ADC_STAT_CALDONE;
+            if (pDevice->pfCallback != NULL) {
+                pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_CALIBRATION_DONE, NULL);
+            }
+        }
+        if ((pDevice->pReg->STAT & BITM_ADC_STAT_BATDONE) != 0u) {
+            SET_STATE(ADC_STATUS_BATTERY_DONE);
+            pDevice->pReg->STAT = BITM_ADC_STAT_BATDONE;
+        }	
+        
+        if ((pDevice->pReg->STAT & BITM_ADC_STAT_TMPDONE) != 0u) {
+            SET_STATE(ADC_STATUS_TMP_DONE);
+            pDevice->pReg->STAT = BITM_ADC_STAT_TMPDONE;
+        }	
+        
+        if ((pDevice->pReg->STAT & BITM_ADC_STAT_TMP2DONE) != 0u) {
+            SET_STATE(ADC_STATUS_TMP2_DONE);
+            pDevice->pReg->STAT = BITM_ADC_STAT_TMP2DONE;
+        }	
+    }
+    if (pDevice->pReg->OVF) {
+        uint16_t nOvrFlowValue = pDevice->pReg->OVF;
+        if (IS_NOT_IN_STATE(ADC_STATUS_COMPARATOR_EN)) {
+            pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INTERRUPT_OVERFLOW);
+        }
+        pDevice->pReg->OVF = nOvrFlowValue;
+    }
+    if (pDevice->pReg->ALERT) {
+      uint32_t nAlertValue = pDevice->pReg->ALERT;
+      uint32_t channel;
+      if (IS_IN_STATE(ADC_STATUS_COMPARATOR_EN) && (pDevice->pfCallback != NULL)) {
+        for (channel = 0u; channel < (NUM_ADC_COMPARATOR_CHANNELS); channel++) {
+          /* Alert bit positions: hi limits are 0b01, 
+          *                      lo limit alerts are 0b10.
+          */
+          if((nAlertValue & (1u << (2u * channel))) > 0u) {
+            pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_HIGH_LIMIT_CROSSED, (void*)channel);
+          }
+          if((nAlertValue & (1u << ((2u * channel) + ((uint32_t)1u)))) > 0u)
+          {
+            pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_LOW_LIMIT_CROSSED, (void*)channel);
+          }
+        }
+      }
+      pDevice->pReg->ALERT = (uint16_t)nAlertValue;
+    }
+    ISR_EPILOG();     
+}
+
+
+/*! \endcond */
+
+#endif /* ADI_ADC_C */
+
+/*****/
+
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adc/adi_adc_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adc/adi_adc_data.c
new file mode 100755
index 00000000000..7157d9c0a27
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adc/adi_adc_data.c
@@ -0,0 +1,20 @@
+#ifndef ADI_ADC_DATA_C
+#define ADI_ADC_DATA_C
+
+#include <adi_processor.h>
+#include <drivers/adc/adi_adc.h>
+#include <drivers/dma/adi_dma.h>
+#include "adi_adc_def.h"
+
+/*! \cond PRIVATE */
+
+static ADI_ADC_INFO AdcDevInfo[] = {
+    {
+        NULL,
+        (ADI_ADC_TypeDef*)REG_ADC0_CFG
+    }
+};
+
+/*! \endcond */
+
+#endif /* ADI_ADC_DATA_C */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adc/adi_adc_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adc/adi_adc_def.h
new file mode 100755
index 00000000000..6568f6f277e
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adc/adi_adc_def.h
@@ -0,0 +1,120 @@
+/*! \cond PRIVATE */
+
+#ifndef ADI_ADC_DEF
+#define ADI_ADC_DEF
+
+#include <drivers/adc/adi_adc.h>
+#include <adi_processor.h>
+
+#if defined(__ECC__)
+#define ALIGN
+#define ALIGN4  _Pragma("align(4)")
+#elif defined(__ICCARM__)
+#define ALIGN   _Pragma("pack()")
+#define ALIGN4  _Pragma("pack(4)")
+#elif defined (__GNUC__)
+#define ALIGN   _Pragma("pack()")
+#define ALIGN4  _Pragma("pack(4)")
+#endif
+
+
+#define IS_IN_STATE(X)         ((pDevice->nDriverStatus & (uint32_t)(X)) == (uint32_t)(X))
+#define IS_NOT_IN_STATE(X)     ((pDevice->nDriverStatus & (uint32_t)(X)) == 0u)
+#define IS_IN_ALL_STATES(X)    ((pDevice->nDriverStatus & (uint32_t)(X)) == (uint32_t)(X))
+#define IS_IN_ANY_STATE(X)     ((pDevice->nDriverStatus & (uint32_t)(X)) != 0u)
+#define IS_NOT_IN_ANY_STATE(X) ((pDevice->nDriverStatus & (uint32_t)(X)) == 0u)
+
+#define SET_STATE(X)  (pDevice->nDriverStatus |= (uint32_t)(X))
+#define CLR_STATE(X)  (pDevice->nDriverStatus &= ~((uint32_t)(X)))
+
+#define NUM_ADC_CHANNELS      			(8u)
+#define NUM_ADC_COMPARATOR_CHANNELS             (4u)
+
+/* To keep state for the driver for error checking */
+typedef enum __ADC_STATUS {
+    ADC_STATUS_POWERED_UP            = (1u << 0),
+    ADC_STATUS_SUB_SYSTEM_EN         = (1u << 1),
+    ADC_STATUS_SUB_SYSTEM_READY      = (1u << 2),
+    
+    ADC_STATUS_NON_BLOCKING_EN       = (1u << 3),
+    ADC_STATUS_BLOCKING_EN           = (1u << 4), 
+    ADC_STATUS_COMPARATOR_EN         = (1u << 5),
+    
+    ADC_STATUS_SAMPLING_IN_PROGRESS  = (1u << 6),
+    ADC_STATUS_CALIBRATION_EN        = (1u << 7),
+    ADC_STATUS_CALIBRATION_DONE      = (1u << 8),
+    
+    ADC_STATUS_BATTERY_DONE          = (1u << 9),
+    
+    ADC_STATUS_OVERSAMPLING_EN       = (1u << 10),
+    ADC_STATUS_AVGERAGING_EN         = (1u << 11),
+    
+    ADC_STATUS_TEMP_SENSOR_EN        = (1u << 12),
+    
+    ADC_STATUS_TMP_DONE              = (1u << 13),
+    ADC_STATUS_TMP2_DONE             = (1u << 14),
+} ADC_STATUS;
+
+typedef enum __ADC_FIFO_MODE {
+    ADC_FIFO_MODE_INIT,
+    ADC_FIFO_MODE_ENABLED,
+    ADC_FIFO_MODE_INTERRUPT_PROCESS,
+    ADC_FIFO_MODE_INTERRUPT_OVERFLOW,
+    ADC_FIFO_MODE_DMA_BUFFER_PROCESS,
+    ADC_FIFO_MODE_DMA_INVALID_DESC,
+    ADC_FIFO_MODE_ABORT
+} ADC_FIFO_MODE;
+
+typedef enum __ADC_BUFFER_CONFIG {
+    ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN = ((uint32_t)1u << 1u),
+    ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN   = ((uint32_t)1u << 0u),
+} ADC_BUFFER_CONFIG;
+
+
+typedef enum __ADC_BUFFER_STATUS {
+    ADC_BUFFER_STATUS_OK        = ((uint32_t)1u << 0u),
+    ADC_BUFFER_STATUS_OVERFLOW  = ((uint32_t)1u << 1u)
+} ADC_BUFFER_STATUS;
+
+typedef struct __ADC_INT_BUFFER {
+    uint16_t                  nConfig;
+    uint16_t                  nStatus;
+    ADI_ADC_BUFFER           *pUserBuffer;
+    uint16_t*                 pCurDataBuffer;
+    uint32_t                  nNumSamplesRemaining;
+    uint32_t                  nChannels;
+} ADC_INT_BUFFER;
+
+typedef struct __ADC_ACTIVE_DATA {
+    uint32_t nCurChannel;
+} ADC_ACTIVE_DATA;
+
+typedef ADI_ADC_RESULT (*ADC_MANAGE_FIFO_FUNC)(struct __ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode);
+
+typedef struct __ADI_ADC_DEVICE
+{
+    volatile uint32_t    nDriverStatus;
+    ADI_ADC_TypeDef      *pReg;
+    void*                pCBParam;
+    ADI_CALLBACK         pfCallback;
+
+    ADC_ACTIVE_DATA      ActData;
+    ADC_MANAGE_FIFO_FUNC pfManageFifo;
+
+    ADC_INT_BUFFER       s_Buffer;
+    uint8_t              ComparitorHi;
+    uint8_t              ComparitorLo;
+    uint8_t              ComparitorHys;
+    
+    SEM_VAR_DECLR
+} ADI_ADC_DEVICE;
+
+typedef struct __ADI_ADC_INFO
+{
+    ADI_ADC_HANDLE     hDevice;
+    ADI_ADC_TypeDef*   pReg;
+} ADI_ADC_INFO;
+
+#endif /* ADI_ADC_DEF */
+
+/*! \endcond */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_callback.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_callback.h
new file mode 100755
index 00000000000..fd2e04f282b
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_callback.h
@@ -0,0 +1,60 @@
+/*!
+ *****************************************************************************
+   @file:    adi_callback.h
+   @brief:   callback APIs.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+/*****************************************************************************/
+
+#ifndef ADI_CALLBACK_H
+#define ADI_CALLBACK_H
+
+#include <stdint.h>
+
+/**
+ * @brief Device Drivers Callback function definition
+ */
+typedef void (* ADI_CALLBACK) (  /*!< Callback function pointer */
+    void      *pCBParam,         /*!< Client supplied callback param */
+    uint32_t   Event,            /*!< Event ID specific to the Driver/Service */
+    void      *pArg);            /*!< Pointer to the event specific argument */
+    
+#endif /* ADI_CALLBACK_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_cyclecount.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_cyclecount.h
new file mode 100755
index 00000000000..9e4a82aa2af
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_cyclecount.h
@@ -0,0 +1,139 @@
+/*
+ *******************************************************************************
+ * @brief:   Framework to preform cycle count measurements
+ *
+ * @details  this is a framework for monitoring the cycle counts
+ *           for ISRs and APIs. The framework uses systick.
+
+*******************************************************************************
+
+ Copyright(c) 2016 Analog Devices, Inc. All Rights Reserved.
+
+ This software is proprietary and confidential.  By using this software you agree
+ to the terms of the associated Analog Devices License Agreement.
+
+ ******************************************************************************/
+
+#ifndef ADI_CYCLECOUNT_H
+#define ADI_CYCLECOUNT_H
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <adi_cycle_counting_config.h>
+
+
+ /** @addtogroup  cyclecount_logging Cycle Counting Framework
+ *   @{
+ */
+
+/*!
+ * 64-bit integer to record cycle counts.
+ * Since UINT32_MAX = 4,294,967,296 cycles
+ * at 26 MHz this would allow us to record for 165 seconds
+ * before the system would wrap around.
+ * By moving to a 64-bit integer we can record for 11,248 years.
+ */
+typedef uint64_t  adi_cyclecount_t;
+
+
+/*!
+ * The systick timer is a 24-bit count down timer
+ * The initial value can, therefore,  be up to 0xFFFFFF
+ * The larger the value the fewer interrupts that will be taken
+ * and the less impact cycle counting will have on the system
+ */
+#define ADI_CYCLECOUNT_SYSTICKS        (0xFFFFFFu)
+
+/*!
+ * Cycle counting nesting is supported via a cycle counting stack. The initial
+ * value of the stack index is one less than the starting stack
+ * index (0)
+ */
+#define ADI_CYCLECOUNT_INITIAL_STACK_INDEX (-1)
+
+/*!
+ * Cycle Count API function return values.
+ */
+typedef enum {
+
+    ADI_CYCLECOUNT_SUCCESS,              /*!< API completed successfully */
+    ADI_CYCLECOUNT_ADD_ENTITY_FAILURE,   /*!< There is not enough space in the cycle counting entity array. Consider increasing the size via the #ADI_CYCLECOUNT_NUMBER_USER_DEFINED_APIS static configuration macro   */
+    ADI_CYCLECOUNT_INVALID_ID,           /*!< The API/ISR ID is invalid. */
+    ADI_CYCLECOUNT_FAILURE               /*!< API did not complete successfully. */
+} ADI_CYCLECOUNT_RESULT;
+
+
+/*!
+ * List of cycle counting IDs for the ISRs and APIs that can record cycle counts.
+ * Items enumerated here must be aligned with adi_cyclecounting_identifiers
+ *
+ * Note that the ID numbering starts at 1. ID==0 is not used.
+ * Note that the application can extend this list via static configuration (see adi_cycle_counting_config.h) and
+ * via the adi_cyclecount_addEntity() API.
+ */
+#define    ADI_CYCLECOUNT_ISR_EXT_3         1u      /*!< Cycle count ID for EXT3 Interrupt Handler. */
+#define    ADI_CYCLECOUNT_ISR_UART          2u      /*!< Cycle count ID for UART Interrupt Handler. */
+#define    ADI_CYCLECOUNT_ISR_DMA_UART_TX   3u      /*!< Cycle count ID for UART DMA TX Interrupt Handler. */
+#define    ADI_CYCLECOUNT_ISR_DMA_UART_RX   4u      /*!< Cycle count ID for UART DMA RX Interrupt Handler. */
+#define    ADI_CYCLECOUNT_ISR_TMR_COMMON    5u      /*!< Cycle count ID for Timer Interrupt Handler. */
+#define    ADI_CYCLECOUNT_ISR_RTC           6u      /*!< Cycle count ID for RTC Interrupt Handler.*/
+#define    ADI_CYCLECOUNT_ISR_SPI           7u      /*!< Cycle count ID for SPI Interrupt Handler. */
+#define    ADI_CYCLECOUNT_ISR_CRC           8u      /*!< Cycle count ID for CRC Interrupt Handler. */
+#define    ADI_CYCLECOUNT_ISR_SPORT         9u      /*!< Cycle count ID for SPORT Interrupt Handler. */
+#define    ADI_CYCLECOUNT_ID_COUNT         10u      /*!< Number of cycle count ISRs and APIs. Must be one greater than the last ID. */
+
+
+/*!
+ * The following are tracked when cycle counting
+ *    Maximum number of cycle counts
+ *    Minimum number of cycle counts
+ *    Average number of cycle counts
+ */
+typedef struct
+{
+  adi_cyclecount_t max_cycles_adjusted;         /*!< Tracks the adjusted max cycle count */
+  adi_cyclecount_t min_cycles_adjusted;         /*!< Tracks the adjusted min cycle count */
+  adi_cyclecount_t average_cycles_adjusted;     /*!< Tracks the adjusted average cycle count */
+
+  adi_cyclecount_t max_cycles_unadjusted;       /*!< Tracks the unadjusted max cycle count */
+  adi_cyclecount_t min_cycles_unadjusted;       /*!< Tracks the unadjusted min cycle count */
+  adi_cyclecount_t average_cycles_unadjusted;   /*!< Tracks the unadjusted average cycle count */
+
+  uint32_t         sample_count;                /*!< Number of cycle count samples recorded, used to compute the average */
+
+} ADI_CYCLECOUNT_LOG;
+
+/*!
+ * Cycle counting has to be enabled in the cycle counting configuration file
+ * If enabled then cycle counting related macros map to the cycle counting APIs.
+ * If not enabled, then the macros maps to a NOP
+ */
+#if defined(ADI_CYCLECOUNT_ENABLED) && (ADI_CYCLECOUNT_ENABLED == 1u)
+
+  #define ADI_CYCLECOUNT_INITIALIZE()       adi_cyclecount_init()      /*!< Initialize the cycle counting data structures */
+  #define ADI_CYCLECOUNT_STORE(id)          adi_cyclecount_store(id)    /*!< Record the number of cycles for the specified ISR or API */
+  #define ADI_CYCLECOUNT_REPORT()           adi_cyclecount_report()     /*!< Generate a cycle counting report */
+
+#else
+
+  #define ADI_CYCLECOUNT_INITIALIZE()       do{}while(0)      /*!< Initialize the cycle counting data structures */
+  #define ADI_CYCLECOUNT_STORE(id)          do{}while(0)      /*!< Record the number of cycles for the specified ISR or API */
+  #define ADI_CYCLECOUNT_REPORT()           do{}while(0)      /*!< Generate a cycle counting report */
+#endif
+
+
+/* Forward API declarations */
+extern ADI_CYCLECOUNT_RESULT  adi_cyclecount_start(void);
+extern ADI_CYCLECOUNT_RESULT  adi_cyclecount_stop(void);
+extern adi_cyclecount_t       adi_cyclecount_get(void);
+extern ADI_CYCLECOUNT_RESULT  adi_cyclecount_store(uint32_t id);
+extern void                   adi_cyclecount_init(void);
+extern void                   adi_cyclecount_report(void);
+extern ADI_CYCLECOUNT_RESULT  adi_cyclecount_addEntity(const char *EntityName, uint32_t *pid);
+
+//extern void SysTick_Handler(void);
+
+/**@}*/
+
+#endif /* ADI_CYCLECOUNT_H */
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_processor.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_processor.h
new file mode 100755
index 00000000000..46a40e01e7e
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_processor.h
@@ -0,0 +1,66 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_processor.h
+ * @brief:   Include appropriate CMSIS device header.
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef __ADI_PROCESSOR_H__
+#define __ADI_PROCESSOR_H__
+
+#if defined(__ADUCM3029__)
+#include <ADuCM3029.h>
+#define __ADUCM302x__
+#endif
+
+#if defined(__ADUCM3027__)
+#include <ADuCM3027.h>
+#define __ADUCM302x__
+#endif
+
+/* Include CMSIS device header for selected target processor. */
+
+#if defined(__ADUCM4050__)
+#include <ADuCM4050.h>
+#define __ADUCM4x50__
+#endif
+
+#endif /* __ADI_PROCESSOR_H__ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_version.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_version.h
new file mode 100755
index 00000000000..6dd08f49bb7
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_version.h
@@ -0,0 +1,63 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_version.h
+ * @brief:   Version macros for ADI ADuCMxxx Device Series
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+	THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+	EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+	TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+	NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+	INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+	(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+	PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+	OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+	THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+	NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+	EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef __ADI_VERSION_H__
+#define __ADI_VERSION_H__
+
+/* use a 32-bit versioning scheme that supports numerical compares */
+#define ADI_VERSION_MAJOR     1u     /* must be <= 255 */
+#define ADI_VERSION_MINOR     0u     /* must be <= 255 */
+#define ADI_VERSION_BUILD     0u     /* must be <= 255 */
+#define ADI_VERSION_PATCH     0u     /* must be <= 255 */
+
+#define ADI_CONSTRUCT_VERSION(a,b,c,d)  (((a) << 24u) | ((b) << 16u) | ((c) << 8u) | (d))
+
+/* known versions */
+#define ADI_VERSION_1_0_0_0   ADI_CONSTRUCT_VERSION(1u,0u,0u,0u)
+
+/* test current version against known predefines (see SystemInit() example in system.c) */
+#define ADI_VERSION_CURRENT   ADI_CONSTRUCT_VERSION(ADI_VERSION_MAJOR, ADI_VERSION_MINOR, ADI_VERSION_BUILD, ADI_VERSION_PATCH)
+
+#endif /* __ADI_VERSION_H__ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/beep/adi_beep.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/beep/adi_beep.c
new file mode 100755
index 00000000000..0d0054c432e
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/beep/adi_beep.c
@@ -0,0 +1,751 @@
+/*! *****************************************************************************
+ * @file:    adi_beep.c
+ * @brief:   BEEP device driver global file.
+ * @details: This a global file which includes a specific file based on the processor family.
+ *           This included file will be  containing  BEEP device driver functions.
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#include <adi_processor.h>
+
+#include <stddef.h>
+#include <assert.h>
+
+#include <drivers/beep/adi_beep.h>
+#include <rtos_map/adi_rtos_map.h>
+#include "adi_beep_def.h"
+
+/** @addtogroup BEEP_Driver BEEP Driver
+ *  @{
+ * @brief Beeper Driver
+ * @note The application must include drivers/beep/adi_beep.h to use this driver.
+ */
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
+*   This isn't a header as such.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit.
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function.
+*   Multiple returns are used for error handling.
+*
+* Pm050 (rule 14.2): a null statement shall only occur on a line by itself
+*   Needed for null expansion of ADI_INSTALL_HANDLER and others.
+*
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   Required for MMR addresses and callback parameters.
+*
+* Pm031: (MISRA C 2004 rule 12.7)  bitwise operations shall not be performed on signed integer types
+*    Required for MMR manipulations.
+* 
+* Pm152: (MISRA C 2004 rule 17.4)  array indexing shall only be applied to objects defined as an array type  
+*    Required for adi_beep_PlaySequence() to access the user-supplied array of notes.
+* 
+* Pm141: (MISRA C 2004 rule 11.4) a cast should not be performed between a pointer to object type and a 
+*     different pointer to object type, this casts from type.
+*    Required to store a an array of varying size in a device structure. 
+* 
+*    Required for adi_beep_PlaySequence() to access the user-supplied array of notes.
+*/
+#pragma diag_suppress=Pm123,Pm073,Pm143,Pm050,Pm140,Pm031,Pm152,Pm141
+#endif /* __ICCARM__ */
+
+/*==========  D A T A  ==========*/
+static ADI_BEEP_DRIVER adi_beep_Device[1];
+
+/*! \cond PRIVATE */
+/* Handler for the BEEP interrupt */
+void Beep_Int_Handler(void);
+
+/* debug handle checker */
+#ifdef ADI_DEBUG
+#define ADI_BEEP_INVALID_HANDLE(h) (&adi_beep_Device[0] != (h))
+#endif
+
+/* definition for the BEEP IRQ - there is only ever one instance of the 
+ * BEEP driver, so reducing space by using a #define rather than including
+ * it in the device structure. */
+#define BEEP_IRQ (BEEP_EVT_IRQn)
+
+#if ADI_BEEP_CFG_SEQUENCE_REPEAT_VALUE == 0
+/* A single note is requested.  Only enable the AEND int. */
+#define INTERRUPT_ON_SEQEND  (0)
+#define INTERRUPT_ON_AEND    (1)
+#else
+/* A two-tone sequence is requested.  Only enable the SEQEND int. */
+#define INTERRUPT_ON_SEQEND  (1)
+#define INTERRUPT_ON_AEND    (0)
+#endif
+
+/*! \endcond */
+
+static const ADI_BEEP_STATIC_INIT gBeeperStaticConfigData[ADI_BEEP_MAX_DEVID] = {
+	/* single instance of Beeper device */
+	{
+		/* configuration register */
+		( (INTERRUPT_ON_SEQEND                             << BITP_BEEP_CFG_SEQATENDIRQ)
+		| (INTERRUPT_ON_AEND                               << BITP_BEEP_CFG_AENDIRQ)
+		| (ADI_BEEP_CFG_SEQUENCE_REPEAT_VALUE              << BITP_BEEP_CFG_SEQREPEAT)
+		),
+
+		/* Status register (interrupt clears) */
+		(ADI_BEEP_ALL_INTERRUPTS),
+
+		/* ToneA control register */
+		( ((uint32_t)ADI_BEEP_TONEA_DISABLE                << BITP_BEEP_TONEA_DIS)
+		| ((uint32_t)ADI_BEEP_TONEA_FREQUENCY              << BITP_BEEP_TONEA_FREQ)
+		| ((uint32_t)ADI_BEEP_TONEA_DURATION               << BITP_BEEP_TONEA_DUR)
+		),
+
+		/* ToneB control register */
+		( ((uint32_t)ADI_BEEP_TONEB_DISABLE                << BITP_BEEP_TONEB_DIS)
+		| ((uint32_t)ADI_BEEP_TONEB_FREQUENCY              << BITP_BEEP_TONEB_FREQ)
+		| ((uint32_t)ADI_BEEP_TONEB_DURATION               << BITP_BEEP_TONEB_DUR)
+		)
+	}
+};
+
+/*! \endcond */
+
+
+/*!
+ *  @brief BEEP Initialization
+ *
+ *  @param[in] DeviceNum    Integer specifying the ID of Beeper to use.
+ *  @param[in] pMemory      Pointer to the memory to be used by the driver.
+ *                          Size of the memory should be at least #ADI_BEEP_MEMORY_SIZE bytes.
+ *  @param[in] MemorySize   Size of the memory passed in pMemory parameter.
+ *  @param[out] phDevice    Pointer to a location that the device data pointer
+ *                          will be written upon successful initialization.
+ *
+ *  @return    Status
+ *             - #ADI_BEEP_SUCCESS                  Success: BEEP device driver initialized successfully.
+ *             - #ADI_BEEP_SEMAPHORE_FAILED         The BEEP sempahore could not be created.
+ *             - #ADI_BEEP_ALREADY_INITIALIZED [D]  The BEEP is already initialized.
+ *             - #ADI_BEEP_NULL_PTR [D]              Null pointer.
+ *             - #ADI_BEEP_BAD_DEV_ID [D]           The device number is invalid.
+ *
+ *  Initialize the BEEP device for use.  The core NVIC BEEP interrupt is enabled.  This API
+ *  must preceed all other beeper API calls and the handle returned must be passed to all other beeper API
+ *  calls.
+ *
+ *
+ *  @note      The contents of \a phDevice will be set to NULL upon failure.\n\n
+ *
+ *  @note      The BEEP device driver will clear all pending interrupts and disable all beeper
+ *             interrupts during beeper device initialization.
+ *
+ *  @note      CALLBACKS: If a callback is registered, it will be called on 
+ *             completion of the note or sequence. The "Event" parameter will
+ *             contain which event occurred, either ADI_BEEP_INTERRUPT_SEQUENCE_END
+ *             or ADI_BEEP_INTERRUPT_NOTE_END.
+ *
+ *  @warning   This API will put the beeper in preconfigured mode as defined in 
+ *             adi_beep_config.h file.
+ *             Refer adi_beep_config.h file to see which all features can be preconfigured.
+ *
+ *  @sa    adi_beep_Close().
+ */
+ADI_BEEP_RESULT adi_beep_Open(ADI_BEEP_DEV_ID          const DeviceNum,
+                              void*                    const pMemory,
+                              uint32_t                 const MemorySize,
+                              ADI_BEEP_HANDLE*         const phDevice)
+{
+    ADI_BEEP_DRIVER    *pDevice;
+    ADI_BEEP_DEV_DATA  *pData;
+    /* store a bad handle in case of failure */
+    *phDevice = (ADI_BEEP_HANDLE) NULL;
+
+#ifdef ADI_DEBUG
+    if (DeviceNum >= ADI_BEEP_MAX_DEVID)
+    {
+        return ADI_BEEP_BAD_DEV_ID;
+    }
+
+    if (pMemory == NULL)
+    {
+        return ADI_BEEP_NULL_PTR;
+    }
+    
+    assert (MemorySize >= sizeof(ADI_BEEP_DRIVER));
+#endif
+
+    /* local pointer to instance data */
+    pDevice = &adi_beep_Device[DeviceNum];
+    pDevice->pReg = pADI_BEEP0;
+    pDevice->pData = (ADI_BEEP_DEV_DATA*)pMemory;
+    pData = pDevice->pData;
+
+#ifdef ADI_DEBUG
+    if (ADI_BEEP_STATE_UNINITIALIZED != adi_beep_Device[DeviceNum].pData->state)
+    {
+        return ADI_BEEP_ALREADY_INITIALIZED;
+    }
+#endif
+
+    pData->cbFunc  = NULL;
+    pData->cbParam = NULL;
+    SEM_CREATE(pDevice->pData, "BEEP_SEM", ADI_BEEP_SEMAPHORE_FAILED);
+    
+    /* set statically configured initialization data */
+    ADI_BEEP_STATIC_INIT const* pInitData = &gBeeperStaticConfigData[DeviceNum];
+    ADI_BEEP_TypeDef   *pReg = pDevice->pReg;
+
+    pReg->CFG   = pInitData->BEEP_CFG;
+    pReg->STAT  = pInitData->BEEP_STAT;
+    pReg->TONEA = pInitData->BEEP_TONEA;
+    pReg->TONEB = pInitData->BEEP_TONEB;
+
+    /* enable beeper interrupts in NVIC */
+    NVIC_EnableIRQ(BEEP_IRQ);
+
+    /* mark driver initialized */
+    pData->state = ADI_BEEP_STATE_INITIALIZED;
+
+    /* store handle at application handle pointer */
+    *phDevice = (ADI_BEEP_HANDLE)pDevice;
+            
+    return ADI_BEEP_SUCCESS;            /* initialized */
+}
+
+
+/*!
+ * @brief  Uninitialize and deallocate a BEEP device.
+ *
+* @param[in]   hDevice    Device handle obtained from #adi_beep_Open().
+ *
+ * @return      Status
+ *                - #ADI_BEEP_SUCCESS                Success: Call completed successfully.
+ *                - #ADI_BEEP_BAD_DEV_HANDLE [D]     Error: Invalid device handle parameter.
+ *                - #ADI_BEEP_NOT_INITIALIZED [D]    Error: Device has not been initialized for use, see #adi_beep_Open().
+ *
+ * Uninitialize and release an allocated BEEP device for other use.  The core NVIC BEEP interrupt is disabled.
+ *
+ * @sa        adi_beep_Open().
+ */
+ADI_BEEP_RESULT adi_beep_Close(ADI_BEEP_HANDLE const hDevice)
+{
+
+    ADI_BEEP_DRIVER    *pDevice;
+    ADI_BEEP_DEV_DATA  *pData;
+    ADI_BEEP_TypeDef   *pReg;
+
+    pDevice = (ADI_BEEP_DRIVER*)hDevice;
+    pData = pDevice->pData;
+    pReg =  pDevice->pReg;
+
+#ifdef ADI_DEBUG
+    if (ADI_BEEP_INVALID_HANDLE(hDevice))
+	{
+          return ADI_BEEP_BAD_DEV_HANDLE;
+	}
+    if (ADI_BEEP_STATE_UNINITIALIZED == pData->state)
+	{
+          return ADI_BEEP_NOT_INITIALIZED;
+	}
+#endif
+
+    /* uninitialize */
+    NVIC_DisableIRQ(BEEP_IRQ);
+
+    pData->state     = ADI_BEEP_STATE_UNINITIALIZED;
+    pData->cbFunc    = NULL;
+    pReg->CFG   = 0u;
+    pReg->STAT  = 0u;
+    pReg->TONEA = 0u;
+    pReg->TONEB = 0u;
+    SEM_DELETE(pDevice->pData, ADI_BEEP_SEMAPHORE_FAILED);
+    return ADI_BEEP_SUCCESS;
+}
+
+/*!
+ * @brief  Register a callback for the beeper driver.
+ *
+ * @param[in]  hDevice        Device handle obtained from #adi_beep_Open().
+ * @param[in]  pfCallback     The application supplied callback which will be called to notify device
+ *                            related events.  
+ * @param[in]  pCBParam       The application supplied callback parameter which can be passed back in
+ *                            the callback function.
+ *
+ * @return      Status
+ *                - #ADI_BEEP_SUCCESS                Call completed successfully.
+ *                - #ADI_BEEP_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_BEEP_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_beep_Open().
+ *
+ * Registers a callback for the beeper interrupts.  When an interrupt occurs, the 
+ * driver will handle any required interaction with the hardware and then call 
+ * the registered callback. 
+ *
+ * @sa        adi_beep_Open().
+ */
+ADI_BEEP_RESULT adi_beep_RegisterCallback(ADI_BEEP_HANDLE const hDevice, 
+                                          ADI_CALLBACK          pfCallback,
+                                          void* const           pCBParam)
+{
+    ADI_BEEP_DRIVER    *pDevice = (ADI_BEEP_DRIVER*)hDevice;
+        
+    ADI_INT_STATUS_ALLOC();   
+ 
+#ifdef ADI_DEBUG
+    if (ADI_BEEP_INVALID_HANDLE(hDevice)) {
+        return ADI_BEEP_BAD_DEV_HANDLE;
+    }
+    
+    if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) {
+        return ADI_BEEP_NOT_INITIALIZED;
+    }
+#endif
+    /* Assign the callback within a critical region. */
+    ADI_ENTER_CRITICAL_REGION();        
+    pDevice->pData->cbFunc  = pfCallback;
+    pDevice->pData->cbParam = pCBParam;    
+    ADI_EXIT_CRITICAL_REGION();
+    
+    return ADI_BEEP_SUCCESS; 
+}
+
+
+#if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1
+/*!
+ * @brief  Play a beeper tone sequence.
+ *
+ * @param[in]   hDevice       Device handle obtained from #adi_beep_Open().
+ * @param[in]   aSequence     The sequence of notes to be played by the beeper.
+ * @param[in]   count         The number of notes in the sequence, must be a multiple
+ *                            of two, and a maximum size of 254 notes.
+ *
+ * @return      Status
+ *                - #ADI_BEEP_SUCCESS                Success: Call completed successfully.
+ *                - #ADI_BEEP_INVALID_COUNT          Sequence count must be multiples of two.
+ *                - #ADI_BEEP_NULL_PTR [D]           Null pointer.
+ *                - #ADI_BEEP_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_BEEP_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_beep_Open().
+ *
+ * Programs the A/B tone pair to play a sequence of notes.  The sequnce can be 
+ * stopped by calling adi_beep_Enable(..., false).  The beeper will be enabled
+ * and disabled internally by the driver. This code, and supporting data, can
+ * be removed by setting ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 0 in the 
+ * adi_beep_config.h configuration file.
+ *
+ * @sa        adi_beep_Open().
+ * @sa        adi_beep_Enable()
+ */
+ADI_BEEP_RESULT adi_beep_PlaySequence(ADI_BEEP_HANDLE const hDevice, 
+                                      ADI_BEEP_NOTE aSequence[], 
+                                      uint8_t count)
+{
+    ADI_BEEP_DRIVER    *pDevice = (ADI_BEEP_DRIVER*)hDevice;
+    ADI_BEEP_TypeDef   *pReg    = pDevice->pReg;
+    uint16_t           nSeqCnt = 0u;
+    
+    ADI_INT_STATUS_ALLOC();
+    
+#ifdef ADI_DEBUG
+    if (ADI_BEEP_INVALID_HANDLE(hDevice)) {
+        return ADI_BEEP_BAD_DEV_HANDLE;
+    }
+    
+    if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) {
+        return ADI_BEEP_NOT_INITIALIZED;
+    }
+    
+    if (NULL == aSequence) {
+        return ADI_BEEP_NULL_PTR;
+    }
+    
+    /* The sequence count must be a multiple of two, be greater than 1 
+     * and must be a maximum of (127 * 2) notes in length.  The hardware supports a 
+     * sequence of up to 127, and there are two notes associated with that. */
+    if (((127u * 2u) < count) || 
+        ((count % 2u) != 0u)  ||
+        (count < 2u)) {
+        return ADI_BEEP_INVALID_COUNT;
+    }
+#endif
+
+    /* Two notes are loaded at a time, and the sequence count refers to 
+     * the number of times that both tone registers should be played. */
+    nSeqCnt = ((uint16_t)count) >> 1u;
+    
+    ADI_ENTER_CRITICAL_REGION();
+
+    /* make a hole, and disable the beeper */
+    pReg->CFG &= (uint16_t)~(BITM_BEEP_CFG_SEQREPEAT | BITM_BEEP_CFG_AENDIRQ | BITM_BEEP_CFG_EN);
+
+    pReg->TONEA =  (  (uint16_t)((uint16_t)aSequence[0].frequency << ADI_BEEP_TONE_FREQ_BITPOS)
+                   |(uint16_t)((uint16_t)aSequence[0].duration << ADI_BEEP_TONE_DUR_BITPOS)   );
+   
+    pReg->TONEB =  (  (uint16_t)((uint16_t)aSequence[1].frequency << ADI_BEEP_TONE_FREQ_BITPOS)
+                   |(uint16_t)((uint16_t)aSequence[1].duration << ADI_BEEP_TONE_DUR_BITPOS)   );
+    
+
+    /* program new sequence count, while preserving everything else */
+    pReg->CFG |= (BITM_BEEP_CFG_EN | 
+                  BITM_BEEP_CFG_BSTARTIRQ | 
+                  BITM_BEEP_CFG_SEQATENDIRQ | 
+                  (uint16_t)((uint16_t)(nSeqCnt) << BITP_BEEP_CFG_SEQREPEAT));
+
+    pDevice->pData->pSeqArray  = (ADI_BEEP_NOTE(*)[])aSequence; 
+    pDevice->pData->nSeqMax    = count;
+    pDevice->pData->nSeqIndex  = 2u;  
+    
+    /* We're now playing, but not blocked */
+    pDevice->pData->state |= (ADI_BEEP_STATE_PLAYING);
+    
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_BEEP_SUCCESS;
+}
+#endif
+
+/*!
+ * @brief  Play a single note/beep.
+ *
+* @param[in]   hDevice       Device handle obtained from #adi_beep_Open().
+ * @param[in]   note          The note to play.
+ *
+ * @return      Status
+ *                - #ADI_BEEP_SUCCESS                Success: Call completed successfully.
+ *                - #ADI_BEEP_BAD_DEV_HANDLE [D]     Error: Invalid device handle parameter.
+ *                - #ADI_BEEP_NOT_INITIALIZED [D]    Error: Device has not been initialized for use, see #adi_beep_Open().
+ *
+ * Programs the A tone to play a single note.
+ *
+ * @sa        adi_beep_Open().
+ */
+ADI_BEEP_RESULT adi_beep_PlayNote(ADI_BEEP_HANDLE const hDevice, 
+                                  ADI_BEEP_NOTE   note)
+{
+    ADI_BEEP_DRIVER    *pDevice;
+    ADI_BEEP_TypeDef   *pReg;
+    ADI_INT_STATUS_ALLOC();
+    
+    pDevice = (ADI_BEEP_DRIVER*)hDevice;
+    pReg = pDevice->pReg;
+
+#ifdef ADI_DEBUG
+    if (ADI_BEEP_INVALID_HANDLE(hDevice)) {
+        return ADI_BEEP_BAD_DEV_HANDLE;
+    }
+    
+    if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) {
+        return ADI_BEEP_NOT_INITIALIZED;
+    }
+#endif
+
+    ADI_ENTER_CRITICAL_REGION();
+
+    /* Clear any previous sequence setup, and disable the beeper */
+    pReg->CFG &= (uint16_t)~(BITM_BEEP_CFG_SEQREPEAT | BITM_BEEP_CFG_EN);
+
+    /* Set Tone A */
+    pReg->TONEA =  (  (uint16_t)((uint16_t)note.frequency << ADI_BEEP_TONE_FREQ_BITPOS)
+                   |(uint16_t)((uint16_t)note.duration << ADI_BEEP_TONE_DUR_BITPOS)   );
+
+    /* program new sequence count, while preserving everything else */
+    pReg->CFG |= (BITM_BEEP_CFG_EN | BITM_BEEP_CFG_AENDIRQ);
+    
+    /* We're now playing but not blocked */
+    pDevice->pData->state |= (ADI_BEEP_STATE_PLAYING);
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_BEEP_SUCCESS;
+}
+
+
+/*!
+ * @brief  Play a a repeating two-tone beep. Similar to an alarm.
+ *
+* @param[in]   hDevice       Device handle obtained from #adi_beep_Open().
+ * @param[in]   noteA         The note to play first.
+ * @param[in]   noteB         The note to play second.
+ * @param[in]   count         The number of times to repeat the two-note signal,
+ *                            maximum of 127.
+ * 
+ *
+ * @return      Status
+ *                - #ADI_BEEP_SUCCESS                Success: Call completed successfully.
+ *                - #ADI_BEEP_BAD_DEV_HANDLE [D]     Error: Invalid device handle parameter.
+ *                - #ADI_BEEP_NOT_INITIALIZED [D]    Error: Device has not been initialized for use, see #adi_beep_Open().
+ *
+ * Programs the beeper to play a repeating two-tone signal.
+ * The count argument refers to the number of iterations of both notes, not 
+ * just a single note.
+ *
+ * @sa        adi_beep_Open().
+ * @sa        adi_beep_PlayNote().
+ * @sa        adi_beep_PlayNSequence().
+ */
+ADI_BEEP_RESULT adi_beep_PlayTwoTone(ADI_BEEP_HANDLE const hDevice, 
+                                      ADI_BEEP_NOTE   noteA,
+                                      ADI_BEEP_NOTE   noteB,
+                                      uint8_t         count)
+{
+    ADI_BEEP_DRIVER    *pDevice;
+    ADI_BEEP_TypeDef   *pReg;
+    ADI_INT_STATUS_ALLOC();
+    
+    pDevice = (ADI_BEEP_DRIVER*)hDevice;
+    pReg = pDevice->pReg;
+
+#ifdef ADI_DEBUG
+    if (ADI_BEEP_INVALID_HANDLE(hDevice)) {
+        return ADI_BEEP_BAD_DEV_HANDLE;
+    }
+    
+    if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) {
+        return ADI_BEEP_NOT_INITIALIZED;
+    }
+#endif
+
+    ADI_ENTER_CRITICAL_REGION();
+
+    /* make a hole, and disable the beeper */
+    pReg->CFG &= (uint16_t)~(BITM_BEEP_CFG_SEQREPEAT | BITM_BEEP_CFG_AENDIRQ |BITM_BEEP_CFG_EN);
+
+    pReg->TONEA =  (  (uint16_t)((uint16_t)noteA.frequency << ADI_BEEP_TONE_FREQ_BITPOS)
+                   |(uint16_t)((uint16_t)noteA.duration << ADI_BEEP_TONE_DUR_BITPOS)   );
+
+    pReg->TONEB =  (  (uint16_t)((uint16_t)noteB.frequency << ADI_BEEP_TONE_FREQ_BITPOS)
+                   |(uint16_t)((uint16_t)noteB.duration << ADI_BEEP_TONE_DUR_BITPOS)   );
+    
+    /* program new sequence count, while preserving everything else */
+    pReg->CFG |= (BITM_BEEP_CFG_EN | BITM_BEEP_CFG_SEQATENDIRQ |(uint16_t)((uint16_t)count << BITP_BEEP_CFG_SEQREPEAT));
+
+    /* We're now playing but not blocked */
+    pDevice->pData->state |= (ADI_BEEP_STATE_PLAYING);
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_BEEP_SUCCESS;
+}
+
+/*!
+ * @brief  Enable or disable the beeper. Other APIs will automatically enable the beeper if required,
+ *         so this function is best used in the following situations:
+ *            - when only using static configuration, i.e. start playing the notes
+ *              set up in static adi_beep_config.h.  
+ *            - Otherwise, this can be used to stop the beeper during playback, 
+ *              when started from any other API.
+ *
+ * @param[in]   hDevice       Device handle obtained from #adi_beep_Open().
+ * @param[in]   bFlag         true to enable the device, false to stop playback.
+ *
+ * @return      Status
+ *                - #ADI_BEEP_SUCCESS                Success: Call completed successfully.
+ *                - #ADI_BEEP_BAD_DEV_HANDLE [D]     Error: Invalid device handle parameter.
+ *                - #ADI_BEEP_NOT_INITIALIZED [D]    Error: Device has not been initialized for use, see #adi_beep_Open().
+ *
+ * @sa        adi_beep_Open().
+ */
+ADI_BEEP_RESULT adi_beep_Enable(ADI_BEEP_HANDLE const hDevice, bool   const bFlag)
+{
+    ADI_BEEP_DRIVER    *pDevice;
+    ADI_BEEP_TypeDef   *pReg;
+    ADI_INT_STATUS_ALLOC();
+    
+    pDevice = (ADI_BEEP_DRIVER*)hDevice;
+    pReg = pDevice->pReg;
+
+#ifdef ADI_DEBUG
+    if (ADI_BEEP_INVALID_HANDLE(hDevice)) {
+        return ADI_BEEP_BAD_DEV_HANDLE;
+    }
+    
+    if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) {
+        return ADI_BEEP_NOT_INITIALIZED;
+    }
+#endif
+
+    ADI_ENTER_CRITICAL_REGION();
+
+    if (bFlag == true) {
+      /* All the registers should already be set - just enable the beep */
+      pReg->CFG |= BITM_BEEP_CFG_EN;
+      pDevice->pData->state |= (ADI_BEEP_STATE_PLAYING);
+    } 
+    else {
+      pReg->CFG &= (uint16_t)~(BITM_BEEP_CFG_EN);
+      pDevice->pData->state &= ~(ADI_BEEP_STATE_PLAYING);
+    }
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_BEEP_SUCCESS;
+}
+
+/*!
+ * @brief  Wait for the current playback to finish.  This is a blocking call,
+ *         that will not return until the current playback (if any) has finished.
+ *         If there is no current playback, it will return immediately.
+ *
+* @param[in]   hDevice       Device handle obtained from #adi_beep_Open().
+ *
+ * @return      Status
+ *                - #ADI_BEEP_SUCCESS                Success: Call completed successfully.
+ *                - #ADI_BEEP_FAILURE                Error: Semaphore failure.
+ *                - #ADI_BEEP_BAD_DEV_HANDLE [D]     Error: Invalid device handle parameter.
+ *                - #ADI_BEEP_NOT_INITIALIZED [D]    Error: Device has not been initialized for use, see #adi_beep_Open().
+ *
+ * @sa        adi_beep_Open().
+ */
+ADI_BEEP_RESULT adi_beep_Wait(ADI_BEEP_HANDLE const hDevice)
+{
+    ADI_BEEP_DRIVER    *pDevice;
+    bool               wait = false;
+    ADI_INT_STATUS_ALLOC();
+    
+    pDevice = (ADI_BEEP_DRIVER*)hDevice;
+
+#ifdef ADI_DEBUG
+    if (ADI_BEEP_INVALID_HANDLE(hDevice)) {
+        return ADI_BEEP_BAD_DEV_HANDLE;
+    }
+    
+    if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) {
+        return ADI_BEEP_NOT_INITIALIZED;
+    }
+#endif
+
+    ADI_ENTER_CRITICAL_REGION();
+    
+    if((pDevice->pData->state | ADI_BEEP_STATE_PLAYING) > 0u) {
+       /* We are going to pend on the semaphore, no matter what. */
+       pDevice->pData->state |= ADI_BEEP_STATE_BLOCKED;
+       wait = true;
+    }
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    if(wait == true) {
+       /* Wait for the completion interrupt to post */
+       SEM_PEND(pDevice->pData, ADI_BEEP_SEMAPHORE_FAILED);
+    }
+    
+    return ADI_BEEP_SUCCESS;
+}
+
+/*! \cond PRIVATE */
+
+/*! @brief  BEEP device driver interrupt handler.  Overrides weakly-bound 
+ *  default interrupt handler in the startup file. */
+void Beep_Int_Handler(void)
+{
+    ISR_PROLOG();    
+#if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1
+    ADI_BEEP_DEV_DATA  *pData;
+    ADI_BEEP_NOTE       noteA, noteB;
+#endif
+    ADI_BEEP_DRIVER *pDevice = &adi_beep_Device[ADI_BEEP_DEVID_0];  /* so far, there is only one BEEP, so this is safe */
+    ADI_BEEP_TypeDef *pReg = pDevice->pReg;
+    uint16_t          fired = ADI_BEEP_ALL_INTERRUPTS;
+    register uint16_t candidate;
+    
+    /* Make sure our driver is up and running. */
+    if (ADI_BEEP_STATE_UNINITIALIZED != pDevice->pData->state) {
+        
+        /* read both status and mask registers */
+        candidate = pReg->CFG & ADI_BEEP_ALL_INTERRUPTS;  /* Take the fired interrupts */
+        fired = candidate;                                /* ...and a copy. */
+        candidate = candidate & pReg->STAT;               /* ...and remove the unused set interrupt bits */
+        
+        /* From this driver's perspective, there are only two states
+         * to watch for - finished playing, or continuing the playing sequence.  
+         * Finished will be handled here. */
+        if((candidate & (BITM_BEEP_CFG_SEQATENDIRQ | BITM_BEEP_CFG_AENDIRQ)) > 0u) { 
+          
+          /* If we are blocked, unblock by posting the semaphore */
+          if((pDevice->pData->state | ADI_BEEP_STATE_BLOCKED) > 0u) {
+            SEM_POST(pDevice->pData);
+          }
+          
+          /* Reset the device playing status. */
+          pDevice->pData->state &= ~(ADI_BEEP_STATE_PLAYING | ADI_BEEP_STATE_BLOCKED);
+            
+          /* ...and disable the device. */
+          pReg->CFG &= (uint16_t)(~(BITM_BEEP_CFG_EN));
+          
+          /* forward the interrupt to the user if they are watching it and it has fired */
+          /* pass the interrupt as the event. */
+          if (pDevice->pData->cbFunc != NULL) {
+              pDevice->pData->cbFunc (pDevice->pData->cbParam, (uint32_t)candidate, NULL);
+          }
+        }
+            
+ #if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1
+        /* The second state is if we are playing a longer sequence, so this 
+         * interrupt may be to move the sequence along.  */
+        if ((BITM_BEEP_CFG_BSTARTIRQ & candidate) != 0u) {
+                
+               /* Get a local copy of data, to shorten the following code. */ 
+                pData = pDevice->pData;     
+                
+                /* If there's still data to play */
+                if(pData->nSeqIndex < pData->nSeqMax) {
+                  /* Move the sequence along.*/
+                  noteA = (*pData->pSeqArray)[pData->nSeqIndex];
+                  pData->nSeqIndex++;
+                  noteB = (*pData->pSeqArray)[pData->nSeqIndex];
+                  pData->nSeqIndex++;
+                  
+                  /* Any values written will not impact the current tones,
+                   * they will take effect after the current tone is completed */
+                  pReg->TONEA =  (  (uint16_t)((uint16_t)noteA.frequency << ADI_BEEP_TONE_FREQ_BITPOS)
+                                  | (uint16_t)((uint16_t)noteA.duration << ADI_BEEP_TONE_DUR_BITPOS)   );
+   
+                  pReg->TONEB =  (  (uint16_t)((uint16_t)noteB.frequency << ADI_BEEP_TONE_FREQ_BITPOS)
+                                  | (uint16_t)((uint16_t)noteB.duration << ADI_BEEP_TONE_DUR_BITPOS)   );
+                }
+        }
+#endif
+    }
+
+    /* clear the watched interrupt(s) that fired */
+    pReg->STAT |= (uint16_t)(fired & ADI_BEEP_ALL_INTERRUPTS);  /* only write allowed interrupt bits */
+    ISR_EPILOG();    
+}
+/*! \endcond */
+
+/*@}*/
+
+
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/beep/adi_beep_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/beep/adi_beep_def.h
new file mode 100755
index 00000000000..22e0b3a949c
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/beep/adi_beep_def.h
@@ -0,0 +1,128 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_beep_def.h
+ * @brief:   BEEP Device Driver definition
+ *-----------------------------------------------------------------------------
+ *
+ * Copyright (c) 2016 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright notice,
+ *   this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ *   this list of conditions and the following disclaimer in the documentation
+ *   and/or other materials provided with the distribution.
+ * - Modified versions of the software must be conspicuously marked as such.
+ * - This software is licensed solely and exclusively for use with processors
+ *   manufactured by or for Analog Devices, Inc.
+ * - This software may not be combined or merged with other code in any manner
+ *   that would cause the software to become subject to terms and conditions
+ *   which differ from those listed here.
+ * - Neither the name of Analog Devices, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ * - The use of this software may or may not infringe the patent rights of one
+ *   or more patent holders.  This license does not release you from the
+ *   requirement that you obtain separate licenses from these patent holders
+ *   to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+ * PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef _ADI_BEEP_DEF_H_
+#define _ADI_BEEP_DEF_H_
+
+/*! \cond PRIVATE */
+#include <drivers/beep/adi_beep.h>
+
+/*!
+ *****************************************************************************
+ * An interrupt mask covering all Beeper interrupts.
+ *****************************************************************************/
+#define ADI_BEEP_ALL_INTERRUPTS ( BITM_BEEP_CFG_SEQATENDIRQ         \
+                                | BITM_BEEP_CFG_SEQNEARENDIRQ    \
+                                | BITM_BEEP_CFG_BENDIRQ       \
+                                | BITM_BEEP_CFG_BSTARTIRQ     \
+                                | BITM_BEEP_CFG_AENDIRQ       \
+                                | BITM_BEEP_CFG_ASTARTIRQ)
+
+#define ADI_BEEP_TONE_DISABLE               (BITM_BEEP_TONEA_DIS)       /*!<  Beeper tone disable bit                          */
+
+#define ADI_BEEP_TONE_FREQ_BITPOS           (BITP_BEEP_TONEA_FREQ)      /*!<  Beeper tone frequency bitfield position          */
+#define ADI_BEEP_TONE_DUR_BITPOS            (BITP_BEEP_TONEA_DUR)       /*!<  Beeper tone duration bitfield position           */
+
+#define ADI_BEEP_TONE_FREQ_MASK             (BITM_BEEP_TONEA_FREQ)      /*!<  Beeper tone frequency bitfield mask              */
+#define ADI_BEEP_TONE_DUR_MASK              (BITM_BEEP_TONEA_DUR)       /*!<  Beeper tone duration bitfield mask               */
+
+/*!
+ *****************************************************************************
+ * ADI_BEEP_STATE
+ *
+ * BEEP driver state.  Used for internal tracking of the BEEP device initialization
+ * progress during the adi_beep_Open().  Also used to insure the BEEP device has been
+ * properly initialized as a prerequisite to using the balance of the BEEP API.
+ *
+ *****************************************************************************/
+typedef uint8_t ADI_BEEP_STATE;
+#define ADI_BEEP_STATE_UNINITIALIZED  0u               /*!< BEEP is not initialized.              */
+#define ADI_BEEP_STATE_INITIALIZED    (1u << 1u)       /*!< BEEP is initialized.                  */
+#define ADI_BEEP_STATE_PLAYING        (1u << 2u)       /*!< BEEP is currently playing.            */
+#define ADI_BEEP_STATE_BLOCKED        (1u << 3u)       /*!< BEEP has blocked, waiting completion. */
+
+/*!
+ * \struct ADI_BEEP_DEV_DATA
+ * Beeper device internal instance data structure.
+ */
+typedef struct _ADI_BEEP_DEV_DATA
+{
+    volatile ADI_BEEP_STATE   state;          /*!< Device state                */
+    ADI_CALLBACK              cbFunc;         /*!< Callback function           */
+    void                      *cbParam;       /*!< Callback parameter          */
+#if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1
+    ADI_BEEP_NOTE             (*pSeqArray)[];   /*!< Pointer to a user-allocated array of notes. */
+    volatile uint8_t            nSeqIndex;      /*!< Index for incrementing sequence */
+    uint8_t                     nSeqMax;        /*!< Size of the sequence */
+#endif
+    SEM_VAR_DECLR      
+} ADI_BEEP_DEV_DATA;
+
+
+/*! \struct ADI_BEEP_DRIVER_STRUCT
+ *  BEEP Device Structure
+ */
+typedef struct _ADI_BEEP_DRIVER_STRUCT
+{
+    ADI_BEEP_TypeDef   *pReg;          /*!< Pointer to register base           */
+    ADI_BEEP_DEV_DATA  *pData;         /*!< Pointer to device data structure   */  
+} ADI_BEEP_DRIVER_STRUCT;
+
+/*! \struct ADI_BEEP_STATIC_INIT
+ *  conditionally create static initialization data based on adi_beep_config.h settings
+ */
+typedef struct {
+	uint16_t BEEP_CFG;   /*!< Beeper configuration register */
+	uint16_t BEEP_STAT;  /*!< Beeper status register */
+	uint16_t BEEP_TONEA; /*!< Beeper ToneA register */
+	uint16_t BEEP_TONEB; /*!< Beeper ToneB register */
+} ADI_BEEP_STATIC_INIT;
+
+/* alias for the actual device structure */
+typedef ADI_BEEP_DRIVER_STRUCT      ADI_BEEP_DRIVER;
+
+/*! \endcond */
+
+#endif /* _ADI_BEEP_DEF_H_ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/common.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/common.h
new file mode 100755
index 00000000000..30eb56d97d1
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/common.h
@@ -0,0 +1,128 @@
+/*!
+ *****************************************************************************
+ * @file:    common.h
+ * @brief:   Common include file for all example 
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+
+#ifndef COMMON_H
+#define COMMON_H
+
+#ifdef __ICCARM__
+/*
+* Pm106 (rule 20.9): the input/output library <stdio.h> shall not be used in
+                     production code
+*   The purpose of this header is to provide I/O facilities based on stdio.
+*/
+#pragma diag_suppress=Pm106
+#endif /* __ICCARM__ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <string.h>
+
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm011 (rule 6.3): The basic types of char, int, short, long, float shall not be used.
+* Pm064 (rule 16.1): functions with variable number of arguments shall not be used.
+*/
+#pragma diag_suppress=Pm011,Pm064
+#endif /* __ICCARM__ */
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Enable REDIRECT_OUTPUT_TO_UART to send the output to UART terminal. 
+This requires the UART Driver(adi_uart.c) to be included in the project */
+/* #define REDIRECT_OUTPUT_TO_UART */  
+
+extern char aDebugString[150]; 
+
+#ifdef __ICCARM__
+/*
+* Pm154 (rule 19.10): in the definition of a function-like macro, each instance
+*                     of a parameter shall be enclosed in parentheses
+*   The __VA_ARGS__ macro cannot be enclosed in parentheses.
+*/
+#pragma diag_suppress=Pm154
+#endif /* __ICCARM__ */
+
+#define DEBUG_MESSAGE(...) \
+  do { \
+    sprintf(aDebugString,__VA_ARGS__); \
+    common_Perf(aDebugString); \
+  } while(0)
+
+#ifdef __ICCARM__
+#pragma diag_default=Pm154
+#endif /* __ICCARM__ */
+
+#define DEBUG_RESULT(s,result,expected_value) \
+  do { \
+    if ((result) != (expected_value)) { \
+      sprintf(aDebugString,"%s  %d", __FILE__,__LINE__); \
+      common_Fail(aDebugString); \
+      sprintf(aDebugString,"%s Error Code: 0x%08X\n\rFailed\n\r",(s),(result)); \
+      common_Perf(aDebugString); \
+      exit(0); \
+    } \
+  } while (0)
+
+/********************************************************************************
+* API function prototypes
+*********************************************************************************/
+void common_Init(void);
+void common_Pass(void);
+void common_Fail(char *FailureReason);
+void common_Perf(char *InfoString);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* COMMON_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_adc_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_adc_config.h
new file mode 100755
index 00000000000..527c172d706
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_adc_config.h
@@ -0,0 +1,342 @@
+/*!
+ *****************************************************************************
+   @file:    adi_adc_config.h
+   @brief:   Configuration options for ADC driver.
+             This is specific to the ADC driver and will be included by the driver.
+             It is not required for the application to include this header file.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_ADC_CONFIG_H
+#define ADI_ADC_CONFIG_H
+#include <adi_global_config.h>
+/** @defgroup ADC_Driver_Cfg Static Configuration
+ *  @ingroup ADC_Driver
+ */
+
+/** @addtogroup ADC_Driver_Cfg Static Configuration
+*  @{
+*/
+
+/************* ADC Driver configurations ***************/
+
+
+/*! Configure the default ADC configuration. Oversampling support must be enabled for resolution >12-bits.\n
+    Valid values are 12 to 16
+*/    
+#define ADI_ADC_CFG_RESOLUTION                               (12)
+
+/*! Configure the default Vref\n
+    3 - External Reference
+    2 - Battery Voltage
+    1 - 2.5V  Internal Reference\n
+    0 - 1.25V Internal Reference\n
+
+*/    
+#define ADI_ADC_CFG_VREF                                      (1)
+
+/*! Enable/Disable MULTI acquisitions of ADC data.
+    When enabled, DMA will be used for ADC readings which is
+    the preferred transfer method for multiple transactions.
+    Otherwise all will be interrupt driven. \n
+    1 - Enable MULTI (DMA) acquisitions \n
+    0 - Disable MULTI (use Interrupt) acquisitions \n
+*/ 
+#define ADI_ADC_ENABLE_MULTI_ACQUIRE              (1)
+
+/*! Enable/Disable HI/LO Digital Comparator limits \n
+    1 - Enable HI/LO Digital Comparator limits\n
+    0 - Disable HI/LO Digital Comparator limits\n
+*/    
+#define ADI_ADC_ENABLE_STATIC_COMPARATOR           (0)
+
+/*! Enable/Disable Channel0 limit comparator \n
+    1 - Enable HI Digital Comparator limit\n
+    0 - Disable HI Digital Comparator limit\n
+*/
+#define ADI_ADC_COMPARATOR_AIN0_HI_EN              (0)    /* 0 or 1 */
+
+/*! Set the Channel0 limit comparator value \n
+    Sets the HI limit value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN0_HI_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN0_HI_VAL             (4095) /* Range: 0 to 4095 */
+
+/*! Enable/Disable Channel0 limit comparator \n
+    1 - Enable LO Digital Comparator limit\n
+    0 - Disable LO Digital Comparator limit\n 
+*/
+#define ADI_ADC_COMPARATOR_AIN0_LO_EN              (0)    /* 0 or 1 */
+
+/*! Set the Channel0 limit comparator value. \n
+    Sets the LO limit value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN0_LO_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN0_LO_VAL             (0)    /* Range: 0 to 4095 */
+
+/*! Enable/Disable Channel0 hysteresis and monitor cycles \n
+    1 - Enable hysteresis and monitor cycles\n
+    0 - Disable hysteresis and monitor cycles\n 
+*/
+#define ADI_ADC_COMPARATOR_AIN0_HYS_EN             (0)   /* 0 or 1 */
+
+/*! Set the Channel0 limit comparator hysteresis value. \n
+    Sets the hysteresis value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN0_HYS_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN0_HYS_VAL            (0)   /* 9 bits, 0 to 511 */
+
+/*! Set the Channel0 limit comparator hysteresis monitor value. \n
+    Sets the monitor value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN0_HYS_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN0_HYS_CYC            (0)   /* 3 bits, 0 to 7 */
+
+/*! Enable/Disable Channel1 limit comparator \n
+    1 - Enable HI Digital Comparator limit\n
+    0 - Disable HI Digital Comparator limit\n
+*/
+#define ADI_ADC_COMPARATOR_AIN1_HI_EN              (0)    /* 0 or 1 */
+
+/*! Set the Channel1 limit comparator value \n
+    Sets the HI limit value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN1_HI_EN is set to 1. \n
+*/
+#define ADI_ADC_COMPARATOR_AIN1_HI_VAL             (4095) /* Range: 0 to 4095 */
+
+/*! Enable/Disable Channel1 limit comparator \n
+    1 - Enable LO Digital Comparator limit\n
+    0 - Disable LO Digital Comparator limit\n 
+*/
+#define ADI_ADC_COMPARATOR_AIN1_LO_EN              (0)    /* 0 or 1 */
+
+/*! Set the Channel1 limit comparator value. \n
+    Sets the LO limit value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN1_LO_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN1_LO_VAL             (0)    /* Range: 0 to 4095 */
+
+/*! Enable/Disable Channel1 hysteresis and monitor cycles \n
+    1 - Enable hysteresis and monitor cycles\n
+    0 - Disable hysteresis and monitor cycles\n 
+*/
+#define ADI_ADC_COMPARATOR_AIN1_HYS_EN             (0)    /* 0 or 1 */
+
+/*! Set the Channel1 limit comparator hysteresis value. \n
+    Sets the hysteresis value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN1_HYS_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN1_HYS_VAL            (0)    /* 9 bits, 0 to 511 */
+
+/*! Set the Channel1 limit comparator hysteresis monitor value. \n
+    Sets the monitor value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN1_HYS_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN1_HYS_CYC            (0)    /* 3 bits, 0 to 7 */
+
+/*! Enable/Disable Channel2 limit comparator \n
+    1 - Enable HI Digital Comparator limit\n
+    0 - Disable HI Digital Comparator limit\n
+*/
+#define ADI_ADC_COMPARATOR_AIN2_HI_EN              (0)    /* 0 or 1 */
+
+/*! Set the Channel2 limit comparator value \n
+    Sets the HI limit value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN2_HI_EN is set to 1. \n
+*/
+#define ADI_ADC_COMPARATOR_AIN2_HI_VAL             (4095) /* Range: 0 to 4095 */
+
+/*! Enable/Disable Channel2 limit comparator \n
+    1 - Enable LO Digital Comparator limit\n
+    0 - Disable LO Digital Comparator limit\n 
+*/
+#define ADI_ADC_COMPARATOR_AIN2_LO_EN              (0)    /* 0 or 1 */
+
+/*! Set the Channel2 limit comparator value. \n
+    Sets the LO limit value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN2_LO_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN2_LO_VAL             (0)    /* Range: 0 to 4095 */
+
+/*! Enable/Disable Channel2 hysteresis and monitor cycles \n
+    1 - Enable hysteresis and monitor cycles\n
+    0 - Disable hysteresis and monitor cycles\n 
+*/
+#define ADI_ADC_COMPARATOR_AIN2_HYS_EN             (0)    /* 0 or 1 */
+
+/*! Set the Channel2 limit comparator hysteresis value. \n
+    Sets the hysteresis value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN2_HYS_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN2_HYS_VAL            (0)    /* 9 bits, 0 to 511 */
+
+/*! Set the Channel2 limit comparator hysteresis monitor value. \n
+    Sets the monitor value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN2_HYS_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN2_HYS_CYC            (0)    /* 3 bits, 0 to 7 */
+
+/*! Enable/Disable Channel3 limit comparator \n
+    1 - Enable HI Digital Comparator limit\n
+    0 - Disable HI Digital Comparator limit\n
+*/
+#define ADI_ADC_COMPARATOR_AIN3_HI_EN              (0)    /* 0 or 1 */
+
+/*! Set the Channel3 limit comparator value \n
+    Sets the HI limit value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN3_HI_EN is set to 1. \n
+*/
+#define ADI_ADC_COMPARATOR_AIN3_HI_VAL             (4095) /* Range: 0 to 4095 */
+
+/*! Enable/Disable Channel3 limit comparator \n
+    1 - Enable LO Digital Comparator limit\n
+    0 - Disable LO Digital Comparator limit\n 
+*/
+#define ADI_ADC_COMPARATOR_AIN3_LO_EN              (0)   /* 0 or 1 */
+
+/*! Set the Channel3 limit comparator value. \n
+    Sets the LO limit value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN3_LO_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN3_LO_VAL             (0)   /* Range: 0 to 4095 */
+
+/*! Enable/Disable Channel3 hysteresis and monitor cycles \n
+    1 - Enable hysteresis and monitor cycles\n
+    0 - Disable hysteresis and monitor cycles\n 
+*/
+#define ADI_ADC_COMPARATOR_AIN3_HYS_EN             (0)   /* 0 or 1 */
+
+/*! Set the Channel3 limit comparator hysteresis value. \n
+    Sets the hysteresis value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN3_HYS_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN3_HYS_VAL            (0)   /* 9 bits, 0 to 511 */
+
+/*! Set the Channel3 limit comparator hysteresis monitor value. \n
+    Sets the monitor value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN3_HYS_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN3_HYS_CYC            (0)   /* 3 bits, 0 to 7 */
+   
+
+/************** Macro validation *****************************/
+
+#if (ADI_ADC_CFG_RESOLUTION < 12) || (ADI_ADC_CFG_RESOLUTION > 16)
+#error "ADI_ADC_CFG_RESOLUTION is invalid"
+#endif
+
+#if (ADI_ADC_CFG_VREF < 0) || (ADI_ADC_CFG_VREF > 3)
+#error "ADI_ADC_CFG_VREF is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN0_HI_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN0_HI_VAL > (4095))
+#error "ADI_ADC_COMPARATOR_AIN0_HI_VAL is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN1_HI_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN1_HI_VAL > (4095))
+#error "ADI_ADC_COMPARATOR_AIN1_HI_VAL is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN2_HI_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN2_HI_VAL > (4095))
+#error "ADI_ADC_COMPARATOR_AIN2_HI_VAL is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN3_HI_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN3_HI_VAL > (4095))
+#error "ADI_ADC_COMPARATOR_AIN3_HI_VAL is invalid"
+#endif
+
+
+#if (ADI_ADC_COMPARATOR_AIN0_LO_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN0_LO_VAL > (4095))
+#error "ADI_ADC_COMPARATOR_AIN0_LO_VAL is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN1_LO_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN1_LO_VAL > (4095))
+#error "ADI_ADC_COMPARATOR_AIN1_LO_VAL is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN2_LO_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN2_LO_VAL > (4095))
+#error "ADI_ADC_COMPARATOR_AIN2_LO_VAL is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN3_LO_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN3_LO_VAL > (4095))
+#error "ADI_ADC_COMPARATOR_AIN3_HI_VAL is invalid"
+#endif
+
+
+#if (ADI_ADC_COMPARATOR_AIN0_HYS_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN0_HYS_VAL > (511))
+#error "ADI_ADC_COMPARATOR_AIN0_HYS_VAL is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN1_HYS_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN1_HYS_VAL > (511))
+#error "ADI_ADC_COMPARATOR_AIN1_HYS_VAL is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN2_HYS_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN2_HYS_VAL > (511))
+#error "ADI_ADC_COMPARATOR_AIN2_HYS_VAL is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN3_HYS_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN3_HYS_VAL > (511))
+#error "ADI_ADC_COMPARATOR_AIN3_HYS_VAL is invalid"
+#endif
+
+
+#if (ADI_ADC_COMPARATOR_AIN0_HYS_CYC < (0)) || (ADI_ADC_COMPARATOR_AIN0_HYS_CYC > (7))
+#error "ADI_ADC_COMPARATOR_AIN0_HYS_CYC is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN1_HYS_CYC < (0)) || (ADI_ADC_COMPARATOR_AIN1_HYS_CYC > (7))
+#error "ADI_ADC_COMPARATOR_AIN1_HYS_CYC is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN2_HYS_CYC < (0)) || (ADI_ADC_COMPARATOR_AIN2_HYS_CYC > (7))
+#error "ADI_ADC_COMPARATOR_AIN2_HYS_CYC is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN3_HYS_CYC < (0)) || (ADI_ADC_COMPARATOR_AIN3_HYS_CYC > (7))
+#error "ADI_ADC_COMPARATOR_AIN3_HYS_CYC is invalid"
+#endif
+
+
+
+
+/*! @} */
+
+#endif /* ADI_ADC_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_beep_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_beep_config.h
new file mode 100755
index 00000000000..a78814b0c72
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_beep_config.h
@@ -0,0 +1,164 @@
+/*!
+ *****************************************************************************
+   @file:    adi_beep_config.h
+   @brief:   Configuration options for BEEP driver.
+             This is specific to the BEEP driver and will be included by the driver.
+             It is not required for the application to include this header file.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_BEEP_CONFIG_H
+#define ADI_BEEP_CONFIG_H
+#include <adi_global_config.h>
+
+#ifdef __ICCARM__
+/* IAR MISRA C 2004 error suppressions.
+ *
+ * Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters.
+ *   IAR compiler supports longer identifiers.
+ */
+#pragma diag_suppress=Pm009
+#endif /* __ICCARM__ */
+
+/** @addtogroup BEEP_Driver_Config Static Configuration
+ *  @ingroup BEEP_Driver
+ *  @{
+ */
+
+/************* BEEP Driver configurations ***************/
+/*! Enable the inclusion of adi_beep_PlaySequence().  This    \n
+    API requires more data in the device structures to manage \n
+    the longer playing sequences, along with extra code in    \n
+    the interrupt handler.                                    \n
+    0 -  adi_beep_PlaySequence() omitted.\n
+    1 -  adi_beep_PlaySequence() is included. */
+#define ADI_BEEP_INCLUDE_PLAY_SEQUENCE                         1
+   
+/************* BEEP controller static configurations ***************/
+
+/*! Configure beeper disable.\n
+    0 -  Beeper enabled.\n
+    1 -  Beeper disabled. */
+#define ADI_BEEP_CFG_BEEPER_DISABLE                            0
+
+/*! Configure beeper sequence, when using static configuration. \n
+    0     -  Single note (Tone A only).\n
+    1-255 -  Sequence mode repeat count (Tone A then B sequentially). */
+#define ADI_BEEP_CFG_SEQUENCE_REPEAT_VALUE                     5
+
+
+/* TONEA CONTROL REGISTER */
+
+/*! Initial ToneA Disable.\n
+    0 -  ToneA Enabled.\n
+    1 -  ToneA Disabled. */
+#define ADI_BEEP_TONEA_DISABLE                                 0
+
+/*! Initial ToneA Frequency.\n
+    0-3   -  Rest Tone (no oscillation).\n
+    4-127 -  Oscillate at 32kHz/freq Hz. */
+#define ADI_BEEP_TONEA_FREQUENCY                               20
+
+/*! Initial ToneA Duration.\n
+    0-254 -  Play for 4ms*duration.\n
+    255   -  Play for infinite duration. */
+#define ADI_BEEP_TONEA_DURATION                                2
+
+
+
+/* TONEB CONTROL REGISTER */
+
+/*! Initial ToneB Disable.\n
+    0 -  ToneB Enabled.\n
+    1 -  ToneB Disabled. */
+#define ADI_BEEP_TONEB_DISABLE                                 0
+
+/*! Initial ToneB Frequency. \n
+    0-3   -  Rest Tone (no oscillation).\n
+    4-127 -  Oscillate at 32kHz/freq Hz. */
+#define ADI_BEEP_TONEB_FREQUENCY                               50
+
+/*! Initial ToneB Duration.\n
+    0-254 -  Play for 4ms*duration.\n
+    255   -  Play for infinite duration. */
+#define ADI_BEEP_TONEB_DURATION                                2
+
+
+
+#ifdef __ICCARM__
+/*
+* Pm085 (rule 19.11): identifiers in pre-processor directives should be defined before use
+*   The macros in the the following #if directives are defined to enum constants by default.
+*/
+#pragma diag_suppress=Pm085
+#endif /* __ICCARM__ */
+
+#if (ADI_BEEP_TONEA_DISABLE > 1)
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_BEEP_TONEA_FREQUENCY  > 127 )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_BEEP_TONEA_DURATION > 255 )
+#error "Invalid configuration"
+#endif
+
+#if (ADI_BEEP_TONEB_DISABLE > 1)
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_BEEP_TONEB_FREQUENCY > 127 )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_BEEP_TONEB_DURATION  >  255 )
+#error "Invalid configuration"
+#endif
+
+#ifdef __ICCARM__
+#pragma diag_default=Pm009,Pm085
+#endif /* __ICCARM__ */
+
+/*! @} */
+
+#endif /* ADI_BEEP_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_crc_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_crc_config.h
new file mode 100755
index 00000000000..19737e3a883
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_crc_config.h
@@ -0,0 +1,100 @@
+/*!
+ *****************************************************************************
+   @file:    adi_crc_config.h
+   @brief:   Configuration options for CRC driver.
+             This is specific to the CRC driver and will be included by the driver.
+             It is not required for the application to include this header file.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders. This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_CRC_CONFIG_H
+#define ADI_CRC_CONFIG_H
+
+#include <adi_global_config.h>
+
+/** @defgroup CRC_Driver_Cfg Static Configuration
+ *  @ingroup CRC_Driver
+ */
+
+/** @addtogroup CRC_Driver_Cfg Static Configuration
+*  @{
+*/
+
+/************* CRC Driver configurations ***************/
+/*!
+   Enable DMA support in the driver code.\n
+   1 -  To have the DMA support code in the driver.\n
+   0 -  To eliminate the DMA support. Operates in core mode.\n
+*/
+#define ADI_CRC_CFG_ENABLE_DMA_SUPPORT         0
+
+/*!
+   Enable Byte mirroring option\n
+   1 -  To enable byte mirroring \n
+   0 -  To disable the byte mirroring.
+*/
+#define ADI_CFG_CRC_ENABLE_BYTE_MIRRORING      0
+/*!
+   Enable Bit mirroring option\n
+   1 -  To enable bit mirroring \n
+   0 -  To disable the bit mirroring.
+*/
+#define ADI_CFG_CRC_ENABLE_BIT_MIRRORING       0
+
+/*!
+   To specify the seed value for CRC computation
+*/
+
+#define ADI_CFG_CRC_SEED_VALUE                 (0xFFFFFFFFu)
+
+/*!
+   To specify the polynomial to be used for CRC computation
+*/
+#define ADI_CFG_CRC_POLYNOMIAL                 (0x04C11DB7u)
+
+/*!
+   To specify the Software DMA channel to be used for the CRC computation
+   0 -> DMA channel SIP0, ..., 7 -> DMA channel SIP7
+*/
+#define ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID     7
+
+#endif /* ADI_CRC_CONFIG_H */
+/*! @} */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_crypto_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_crypto_config.h
new file mode 100755
index 00000000000..c36d5ea4d36
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_crypto_config.h
@@ -0,0 +1,150 @@
+/*!
+ *****************************************************************************
+   @file:    adi_crypto_config.h
+   @brief:   Configuration options for Crypto driver.
+             This is specific to the Crypto driver and will be included by the driver.
+             It is not required for the application to include this header file.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2014-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef __ADI_CRYPTO_CONFIG_H__
+#define __ADI_CRYPTO_CONFIG_H__
+#include <adi_global_config.h>
+
+/** @addtogroup Crypto_Driver_Config Static Configuration
+ *  @ingroup Crypto_Driver
+ *  @{
+ */
+
+/************* Crypto Driver configurations ***************/
+
+/*! Enable/Disable ECB Support\n
+    1 - Enable ECB Support\n
+    0 - Disable ECB Support\n
+*/
+#define ADI_CRYPTO_ENABLE_ECB_SUPPORT            (1)
+
+/*! Enable/Disable CTR Support\n
+    1 - Enable CTR Support\n
+    0 - Disable CTR Support\n
+*/
+#define ADI_CRYPTO_ENABLE_CTR_SUPPORT            (1)
+
+/*! Enable/Disable CBC Support\n
+    1 - Enable CBC Support\n
+    0 - Disable CBC Support\n
+*/
+#define ADI_CRYPTO_ENABLE_CBC_SUPPORT            (1)
+
+/*! Enable/Disable CCM Support\n
+    1 - Enable CCM Support\n
+    0 - Disable CCM Support\n
+*/
+#define ADI_CRYPTO_ENABLE_CCM_SUPPORT            (1)
+
+/*! Enable/Disable CMAC Support\n
+    1 - Enable CMAC Support\n
+    0 - Disable CMAC Support\n
+*/
+#define ADI_CRYPTO_ENABLE_CMAC_SUPPORT           (1)
+
+/*! Enable/Disable HMAC Support\n
+    1 - Enable HMAC Support\n
+    0 - Disable HMAC Support\n
+*/
+#if defined (__ADUCM4x50__)
+#define ADI_CRYPTO_ENABLE_HMAC_SUPPORT           (1)
+#endif /*ADuCM4x50*/
+/*! Enable/Disable SHA Support\n
+    1 - Enable SHA Support\n
+    0 - Disable SHA Support\n
+*/
+#define ADI_CRYPTO_ENABLE_SHA_SUPPORT            (1)
+
+
+/*! Enable/Disable DMA Support\n
+    1 - Enable DMA Support\n
+    0 - Disable DMA Support
+*/
+#define ADI_CRYPTO_ENABLE_DMA_SUPPORT            (1)
+
+/*! Enable/Disable DMA Transfer by default\n
+    1 - Enable DMA \n
+    0 - Disable DMA
+*/
+#define ADI_CRYPTO_ENABLE_DMA                    (1)
+
+/*! SHA output format\n
+    1 - Big-Endian \n
+    0 - Little-Endian
+*/
+#define ADI_CRYPTO_SHA_OUTPUT_FORMAT             (1)
+
+
+/*! Enable/Disable PKSTOR Support\n
+    1 - Enable PKSTOR Support\n
+    0 - Disable PKSTOR Support\n
+*/
+#define ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT         (0)
+
+
+
+/************** Macro validation *****************************/
+
+#if ((ADI_CRYPTO_ENABLE_DMA_SUPPORT != 0) && (ADI_CRYPTO_ENABLE_DMA_SUPPORT != 1))
+#error "ADI_CRYPTO_ENABLE_DMA_SUPPORT is invalid"
+#endif
+
+#if ((ADI_CRYPTO_ENABLE_DMA != 0) && (ADI_CRYPTO_ENABLE_DMA != 1))
+#error "ADI_CRYPTO_ENABLE_DMA is invalid"
+#endif
+
+#if ((ADI_CRYPTO_ENABLE_DMA == 1) && (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 0))
+#error "DMA cannot be enabled if DMA support is disabled"
+#endif
+
+#if (!defined(__ADUCM4x50__) && (ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT == 1))
+#error "PKSTOR extensions only supported on ADuCM4x50 platform"
+#endif
+
+/*! @} */
+
+#endif /* __ADI_CRYPTO_CONFIG_H__ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_cycle_counting_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_cycle_counting_config.h
new file mode 100755
index 00000000000..4b83c46fd7b
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_cycle_counting_config.h
@@ -0,0 +1,105 @@
+/*! *****************************************************************************
+ * @file    adi_cycle_counting_config.h
+ * @brief   Cycle Counting Framework configuration
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+
+#ifndef ADI_CYCLE_COUNTING_CONFIG_H
+#define ADI_CYCLE_COUNTING_CONFIG_H
+
+/** @addtogroup CYCLE_COUNTING_Config Static Configuration
+ *  @ingroup cyclecount_logging
+ *  @{
+ */
+
+
+/************* Cycle Counting Configuration ***************/
+
+/*! Global enable. This must be enabled for any other functionality to work\n
+    0u disabled
+	1u enabled
+*/
+#define ADI_CYCLECOUNT_ENABLED                          (0u)
+
+/*! SPI Interrupt Mode ISR Cycle Counting Enabled\n
+   0 -  Disables the recording of SPI ISR cycle counting.
+   1 -  Enables the recording of SPI ISR cycle counting.
+*/
+#define ADI_CYCLECOUNT_SPI_ISR_ENABLED                  (0u)
+
+
+/*! CRC Interrupt Mode ISR Cycle Counting Enabled\n
+   0 -  Disables the recording of CRC ISR cycle counting.
+   1 -  Enables the recording of CRC ISR cycle counting.
+*/
+#define ADI_CYCLECOUNT_CRC_ISR_ENABLED                  (0u)
+
+
+/*! SPORT Interrupt Mode ISR Cycle Counting Enabled\n
+   0 -  Disables the recording of SPORT ISR cycle counting.
+   1 -  Enables the recording of SPORT ISR cycle counting.
+*/
+#define ADI_CYCLECOUNT_SPORT_ISR_ENABLED                (0u)
+
+/*! UART Interrupt Mode ISR Cycle Counting Enabled\n
+   0 -  Disables the recording of UART ISR cycle counting.
+   1 -  Enables the recording of UART ISR cycle counting.
+*/
+#define ADI_CYCLECOUNT_UART_ISR_ENABLED                 (0u)
+
+
+/*! A user application may desire/require cycle counting in an application defined API
+    or ISR. Set this macro to the number of required.
+*/
+#define ADI_CYCLECOUNT_NUMBER_USER_DEFINED_APIS         (0u)
+
+/*!
+ * Cycle count 'stack' nesting depth. Adjust as needed.
+ * This should map to the maximum number of nested interrupts an application might experience.
+ */
+#define ADI_CYCLECOUNT_STACK_SIZE 10
+
+/**
+ *  @}
+ */
+
+#endif /* ADI_CYCLE_COUNTING_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_flash_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_flash_config.h
new file mode 100755
index 00000000000..dcb2c82fb0f
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_flash_config.h
@@ -0,0 +1,307 @@
+/*!
+ *****************************************************************************
+   @file:    adi_flash_config.h
+   @brief:   Configuration options for flash driver.
+             This is specific to the flash driver and will be included by the driver.
+             It is not required for the application to include this header file.
+   @version: $Revision: 33205 $
+   @date:    $Date: 2016-01-11 05:46:07 -0500 (Mon, 11 Jan 2016) $
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_FLASH_CONFIG_H
+#define ADI_FLASH_CONFIG_H
+#include <adi_global_config.h>
+
+/** @addtogroup Flash_Driver_Config Static Configuration
+ *  @ingroup Flash_Driver
+ *  @{
+ */
+
+
+/****SETTINGS THAT LIVE IN FEE INTERRUPT ENABLE (IEN) REGISTER****/
+
+
+/*!
+ * Configure a response to the 2-bit ECC ERROR events (in IEN).
+ * - 0 Do not generate a response to ECC Error Events.
+ * - 1 Generate Bus Errors in response to ECC Error Events.
+ * - 2 Generate IRQs in response to ECC Error Events.
+ */
+#define ADI_FEE_CFG_ECC_ERROR_RESPONSE          (1u)
+/*!
+ * Configure a response to the 1-bit ECC CORRECTION events (in IEN).
+ * - 0 Do not generate a response to ECC correction Events.
+ * - 1 Generate Bus Errors in response to ECC correction Events.
+ * - 2 Generate IRQs in response to ECC correction Events.
+ */
+
+#if defined(__ADUCM4x50__)
+#define ADI_FEE_CFG_ECC_CORRECTION_RESPONSE     (2u)
+#endif
+
+
+/****SETTINGS THAT LIVE IN FEE TIME PARAMETER 0 (TIME_PARAM0) REGISTER****/
+
+
+/* It is recommended to NOT MODIFY flash timing parameters without keen insight and caution */
+/*!
+ * Configure flash non-volatile mass erase hold time.\n
+ * Upper 4-bits of 11-bit value.\n
+ * (Lower bits are hard-coded to 0x14.)\n
+ * Hardware default value is 0xb.
+ */
+#define ADI_FEE_CFG_PARAM0_TNVH1          (0xbu)
+
+/*!
+ * Configure flash erase time.\n
+ * Upper 4-bits of 19-bit value.\n
+ * (Lower bits are hard-coded to 0x7370.)\n
+ * Hardware default value is 0x8.
+ */
+#define ADI_FEE_CFG_PARAM0_TERASE          (0x8u)
+
+/*!
+ * Configure flash recovery time.\n
+ * Upper 4-bits of 8-bit value.\n
+ * (Lower bits are hard-coded to 0x2.)\n
+ * Hardware default value is 0x9.
+ */
+#define ADI_FEE_CFG_PARAM0_TRCV          (0x9u)
+
+/*!
+ * Configure flash non-volatile hold time.\n
+ * Upper 4-bits of 8-bit value.\n
+ * (Lower bits are hard-coded to 0x1.)\n
+ * Hardware default value is 0x5.
+ */
+#define ADI_FEE_CFG_PARAM0_TNVH          (0x5u)
+
+/*!
+ * Configure flash program time.\n
+ * Upper 4-bits of 10-bit value.\n
+ * (Lower bits are hard-coded to 0x7.)\n
+ * Hardware default value is 0x0.
+ */
+#if defined(__ADUCM302x__)
+#define ADI_FEE_CFG_PARAM0_TPROG          (0x5u)
+#elif defined(__ADUCM4x50__)
+#define ADI_FEE_CFG_PARAM0_TPROG          (0x0u)
+#else
+#error Flash Driver is not ported for this processor
+#endif
+/*!
+ * Configure flash NVSTR-to-program setup time.\n
+ * Upper 4-bits of 8-bit value.\n
+ * (Lower bits are hard-coded to 0x2.)\n
+ * Hardware default value is 0x9.
+ */
+#define ADI_FEE_CFG_PARAM0_TPGS          (0x9u)
+
+/*!
+ * Configure flash program/erase-to-NVSTR setup time.\n
+ * Upper 4-bits of 8-bit value.\n
+ * (Lower bits are hard-coded to 0x1.)\n
+ * Hardware default value is 0x5.
+ */
+#define ADI_FEE_CFG_PARAM0_TNVS          (0x5u)
+
+/*!
+ * Configure flash reference clock divide-by-2 setting.\n
+ * All timing parameters are referenced to this parameter.
+ * - 0 Reference clock is not divided.
+ * - 1 Reference clock is divided by 2.\n
+ * Hardware default value is 0x0.
+ */
+#define ADI_FEE_CFG_PARAM0_CLKDIV          (0x0u)
+
+
+
+/****SETTINGS THAT LIVE IN FEE TIME PARAMETER 1 (TIME_PARAM1) REGISTER****/
+
+
+/* It is recommended to NOT MODIFY flash timing parameters without keen insight and caution */
+/*!
+ * Configure flash read access wait states.\n
+ * Number of 3-bit read access wait states to use.\n
+ * Maximum allowed value is 0x4.\n
+ * Hardware default value is 0x0.
+ */
+#if defined (__ADUCM4x50__)
+#define ADI_FEE_CFG_PARAM1_WAITESTATES          (0x0u)
+#endif
+/*!
+ * Configure flash sleep mode wake-up time.\n
+ * Upper 4-bits of 8-bit value.\n
+ * (Lower bits are hard-coded to 0xb.)\n
+ * Hardware default value is 0x4.
+ */
+#define ADI_FEE_CFG_PARAM1_TWK          (0x4u)
+
+
+
+/****SETTINGS THAT LIVE IN FEE SYSTEM ABOUT ENABLE (ABOUT_EN_XX) REGISTERS****/
+
+
+/*!
+ * Configure lower (0-31) flash system interrupt abort enables.\n
+ * Allows system interrupts to abort an ongoing flash command.\n
+ * Only 64 system interrupts are supported.\n
+ * Lower interrupts (0-31) are encoded in ADI_FEE_CFG_ABORT_EN_LO,
+ * - 0 Corresponding interrupt is prevented from aborting flash command.
+ * - 1 Corresponding interrupt is allowed to abort flash command.\n
+ * Hardware default value is 0x0.
+ */
+#define ADI_FEE_CFG_ABORT_EN_LO          (0x0u)
+
+/*!
+ * Configure upper (32-63) flash system interrupt abort enables.\n
+ * Allows system interrupts to abort an ongoing flash command.\n
+ * Only 64 system interrupts are supported.\n
+ * Upper interrupts (32-63) are encoded in ADI_FEE_CFG_ABORT_EN_HI.
+ * - 0 Corresponding interrupt is prevented from aborting flash command.
+ * - 1 Corresponding interrupt is allowed to abort flash command.\n
+ * Hardware default value is 0x0.
+ */
+#define ADI_FEE_CFG_ABORT_EN_HI          (0x0u)
+
+
+
+/****SETTINGS THAT LIVE IN ECC CONFIG REGISTER (ECC_CFG) REGISTER****/
+
+
+/*!
+ * ECC Start Page Pointer (in ECC_CFG).
+ */
+#define ADI_FEE_CFG_ECC_START_PAGE              (0u)
+
+/*!
+ * Enable/Disable ECC for info space (in ECC_CFG).
+ * - 1 Enable Info Space.
+ * - 0 Disable Info Space.
+ */
+#define ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE   (0u)
+
+/*!
+ * Enable/Disable ECC (in ECC_CFG).
+ * - 1 Enable ECC.
+ * - 0 Disable ECC.
+ */
+#define ADI_FEE_CFG_ENABLE_ECC                  (0u)
+
+
+
+/************* Flash Driver Configuration Settings Checkers ***************/
+
+
+
+/* IEN CHECKS */
+#if ((ADI_FEE_CFG_ECC_ERROR_RESPONSE < 0u) || (ADI_FEE_CFG_ECC_ERROR_RESPONSE > 2u))
+#error "ADI_FEE_CFG_ECC_ERROR_RESPONSE should be in the range 0-2."
+#endif
+#if ((ADI_FEE_CFG_ECC_CORRECTION_RESPONSE < 0u) || (ADI_FEE_CFG_ECC_CORRECTION_RESPONSE > 2u))
+#error "ADI_FEE_CFG_ECC_CORRECTION_RESPONSE should be in the range 0-2."
+#endif
+
+
+
+/* PARAM0 CHECKS */
+#if ((ADI_FEE_CFG_PARAM0_TNVH1 < 0u) || (ADI_FEE_CFG_PARAM0_TNVH1 > 15u))
+#error "ADI_FEE_CFG_PARAM0_TNVH1 should be in the range 0-15."
+#endif
+#if ((ADI_FEE_CFG_PARAM0_TERASE < 0u) || (ADI_FEE_CFG_PARAM0_TERASE > 15u))
+#error "ADI_FEE_CFG_PARAM0_TERASE should be in the range 0-15."
+#endif
+#if ((ADI_FEE_CFG_PARAM0_TRCV < 0u) || (ADI_FEE_CFG_PARAM0_TRCV > 15u))
+#error "ADI_FEE_CFG_PARAM0_TRCV should be in the range 0-15."
+#endif
+#if ((ADI_FEE_CFG_PARAM0_TNVH1 < 0u) || (ADI_FEE_CFG_PARAM0_TNVH1 > 15u))
+#error "ADI_FEE_CFG_PARAM0_TNVH1 should be in the range 0-15."
+#endif
+#if ((ADI_FEE_CFG_PARAM0_TPROG < 0u) || (ADI_FEE_CFG_PARAM0_TPROG > 15u))
+#error "ADI_FEE_CFG_PARAM0_TPROG should be in the range 0-15."
+#endif
+#if ((ADI_FEE_CFG_PARAM0_TPGS < 0u) || (ADI_FEE_CFG_PARAM0_TPGS > 15u))
+#error "ADI_FEE_CFG_PARAM0_TPGS should be in the range 0-15."
+#endif
+#if ((ADI_FEE_CFG_PARAM0_TNVS < 0u) || (ADI_FEE_CFG_PARAM0_TNVS > 15u))
+#error "ADI_FEE_CFG_PARAM0_TNVS should be in the range 0-15."
+#endif
+#if ((ADI_FEE_CFG_PARAM0_CLKDIV < 0u) || (ADI_FEE_CFG_PARAM0_CLKDIV > 1u))
+#error "ADI_FEE_CFG_PARAM0_CLKDIV should be in the range 0-1."
+#endif
+
+
+
+/* PARAM1 CHECKS */
+#if ((ADI_FEE_CFG_PARAM1_WAITESTATES < 0u) || (ADI_FEE_CFG_PARAM1_WAITESTATES > 4u))
+#error "ADI_FEE_CFG_PARAM1_WAITESTATES should be in the range 0-4."
+#endif
+#if ((ADI_FEE_CFG_PARAM1_TWK < 0u) || (ADI_FEE_CFG_PARAM1_TWK > 15u))
+#error "ADI_FEE_CFG_PARAM1_TWK should be in the range 0-15."
+#endif
+
+
+
+/* ABORT_EN_XX CHECKS */
+#if ((ADI_FEE_CFG_ABORT_EN_LO < 0u) || (ADI_FEE_CFG_ABORT_EN_LO > 0XFFFFu))
+#error "ADI_FEE_CFG_ABORT_EN_LO should be in 32-bit range."
+#endif
+#if ((ADI_FEE_CFG_ABORT_EN_HI < 0u) || (ADI_FEE_CFG_ABORT_EN_HI > 0XFFFFu))
+#error "ADI_FEE_CFG_ABORT_EN_HI should be in 32-bit range."
+#endif
+
+
+
+/* ECC_CFG CHECKS */
+#if (((ADI_FEE_CFG_ECC_START_PAGE >> 8u) << 8) != ADI_FEE_CFG_ECC_START_PAGE)
+#error "ADI_FEE_CFG_ECC_START_PAGE has invalid  bits set in lower 8-bits."
+#endif
+#if ((ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE != 0u) && (ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE != 1u))
+#error "ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE should be 1 or 0."
+#endif
+#if ((ADI_FEE_CFG_ENABLE_ECC != 0u) && (ADI_FEE_CFG_ENABLE_ECC != 1u))
+#error "ADI_FEE_CFG_ENABLE_ECC should be 1 or 0."
+#endif
+
+/*! @} */
+
+#endif /* ADI_FLASH_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_global_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_global_config.h
new file mode 100755
index 00000000000..6d205577a3b
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_global_config.h
@@ -0,0 +1,131 @@
+/*!
+ *****************************************************************************
+   @file:    adi_global_config.h
+   @brief:   Configuration options for all the drivers.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_GLOBAL_CONFIG_H
+#define ADI_GLOBAL_CONFIG_H
+
+/** @addtogroup GLOBAL_Driver_Config Global Static Configuration
+ *  @brief   Configuration options for all the drivers.
+ *  @{
+ */
+
+/*! @name RTOS used
+ * In order to be used in a multi-threaded application, the device drivers
+ * may require the use of some RTOS-specific signals like semaphores or actions
+ * may be required when entering/exiting an interrupt. By specifying the RTOS
+ * that the application uses, the drivers can map their requirements to the
+ * specific RTOS, without requiring an OS abstraction layer.
+ * @note This macros do not add the RTOS sources to the application, users need
+ *       to set up the source and include paths in their application themselves
+ * @note If the RTOS specified is not in the list of supported RTOS the build
+ *       mechanism fails
+ */
+/**@{*/
+
+/*! @hideinitializer Indicates that no RTOS is used (bare-metal applications) */
+#define ADI_CFG_RTOS_NO_OS              (1)
+/*! @hideinitializer Indicates that Micrium uCOS-III is used  */
+#define ADI_CFG_RTOS_MICRIUM_III        (2)
+/*! @hideinitializer Indicates that Micrium FreeRTOS is used */
+#define ADI_CFG_RTOS_FREERTOS           (3)
+
+/*! Configure the RTOS required across the project.
+    It can be configured to one of the following macros:
+    - #ADI_CFG_RTOS_NO_OS
+    - #ADI_CFG_RTOS_MICRIUM_III
+    - #ADI_CFG_RTOS_FREERTOS
+ */
+#define ADI_CFG_RTOS    ADI_CFG_RTOS_NO_OS
+
+/**@}*/
+
+/*! @name Low power mode support
+    All applications may have to block when a buffer is being processed. In the
+    case of an RTOS application, when a task is blocked waiting for a buffer, a
+    different task can run. If no tasks are available then the idle task runs.
+    In many RTOS the idle task can be configured so it perform actions like
+    entering low power modes.
+
+    In the case of a bare-metal (no RTOS) application, since there are no other
+    tasks to be run, the driver can enter low power modes itself when it blocks.
+   */
+
+/*! Configures the drivers to enter low power mode (Flexi mode)
+    when waiting for a buffer to be processed. This macro is applicable
+    only when the drivers are operating in the bare metal mode (No RTOS).
+
+    The possible values it can be configured to are:
+
+    - 1 : Low power mode support required.
+    - 0 : Low power mode support not required.
+*/
+#define ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT      (1)
+/**@}*/
+
+
+
+/*
+** Verify the macro configuration
+*/
+#if ((ADI_CFG_RTOS != ADI_CFG_RTOS_NO_OS)       && \
+     (ADI_CFG_RTOS != ADI_CFG_RTOS_MICRIUM_III)  && \
+     (ADI_CFG_RTOS != ADI_CFG_RTOS_FREERTOS))
+#error "ADI_CFG_RTOS macro wrongly configured"
+#endif /* ADI_CFG_RTOS verification */
+
+#if ((ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT != 0) && \
+     (ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT != 1))
+#error "ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT macro is wrongly configured"
+#endif
+
+#if ((ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT == 1) && \
+     (ADI_CFG_RTOS != ADI_CFG_RTOS_NO_OS))
+#error "ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT cannot be set to 1 in multi-threaded applications"
+#endif
+/**
+ *  @}
+ */
+
+#endif /* ADI_GLOBAL_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_i2c_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_i2c_config.h
new file mode 100755
index 00000000000..0f6bbca875a
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_i2c_config.h
@@ -0,0 +1,226 @@
+/*!
+ *****************************************************************************
+   @file:    adi_i2c_config.h
+   @brief:   Configuration options for I2C driver.
+             This is specific to the I2C driver and will be included by the driver.
+             It is not required for the application to include this header file.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_I2C_CONFIG_H
+#define ADI_I2C_CONFIG_H
+#include <adi_global_config.h>
+
+/** @addtogroup I2C_Driver_Config Static Configuration
+ *  @ingroup I2C_Driver
+ *  @{
+ */
+
+/************* I2C Driver configurations ***************/
+
+/*! Master control register TX FIFO decrement control bit.\n
+    1 - Decrement master TX FIFO status when a byte has been fully serialized.\n
+    0 - Decrement master TX FIFO status when a byte is unloaded from the TX FIFO,
+        but not yet serialized on the bus. */
+#define ADI_I2C_CFG_MCTL_MXMITDEC               (0)
+
+/*! Master control register STOP condition interrupt enable.\n
+    1 - Enable completion interrupt when a STOP condition is detected.\n
+    0 - Disable completion interrupt when a STOP condition is detected. */
+#define ADI_I2C_CFG_MCTL_IENCMP                 (1)
+
+/*! Master control register NACK (NotACKnowledge) interrupt enable.\n
+    1 - Enable NACK interrupt when an acknowledge is not received.\n
+    0 - Disable NACK interrupt when an acknowledge is not received. */
+#define ADI_I2C_CFG_MCTL_IENACK                 (1)
+
+/*! Master control register ALOST (Arbitration LOST) interrupt enable.\n
+    1 - Enable ALOST interrupt when bus arbitration is lost.\n
+    0 - Disable ALOST interrupt when bus arbitration is lost. */
+#define ADI_I2C_CFG_MCTL_IENALOST               (1)
+
+/*! Master control register clock stretch enable.\n
+    1 - Enable clock stretch by slave device.\n
+    0 - Disable clock stretch by slave device. */
+#define ADI_I2C_CFG_MCTL_STRETCHSCL             (0)
+
+/*! Master control register internal loopback enable.\n
+    1 - Enable internal looping of SCL and SDA outputs onto their corresponding inputs.\n
+    0 - Disable internal looping of SCL and SDA outputs onto their corresponding inputs. */
+#define ADI_I2C_CFG_MCTL_LOOPBACK               (0)
+
+/*! Master control register start condition back-off disable.\n
+    1 - Enables controller to compete for bus ownership even if another device is driving a START condition.\n
+    0 - Disables controller to compete for bus ownership even if another device is driving a START condition. */
+#define ADI_I2C_CFG_MCTL_COMPLETE               (0)
+
+/*! Master control register device enable.\n
+    1 - Enable controller as a Master device.\n
+    0 - Disables controller as a Master device. */
+#define ADI_I2C_CFG_MCTL_MASEN                  (0)
+
+/*!
+ * Standard Clock divider Clock-HI settings.
+ * Assuming a 26 MHz core clock, the following settings
+ * will be useful:                                           \n
+ *     - For STANDARD (100 kHz) rate, use: HI= 25, LO= 31.   \n
+ *     - For FAST (400 kHz) rate, use:     HI=123, LO=129.   \n
+ *                                                           \n
+ * @note The clock high setting varies with pull-up loading,
+ * board layout, slew-rate, etc., so exact settings are somewhat
+ * empirical.  The clock high counter does not start until
+ * a logic high transition is sensed on the clock line, so
+ * variability in this logic transaction will alter the
+ * effective clock rate.  This results from the internal
+ * clock-stretch hardware feature supporting a slave slow device
+ * that may hold off the master by holding the clock line low.
+ *
+ * @sa ADI_I2C_CFG_DIV_LOW
+ */
+#define ADI_I2C_CFG_DIV_HIGH                    (25)
+
+/*! Standard Clock divider Clock-LO setting
+ *
+ * @sa ADI_I2C_CFG_DIV_HIGH
+ */
+#define ADI_I2C_CFG_DIV_LOW                     (31)
+
+/*! Shared control reset START/STOP detect circuit.\n
+    1 - Reset the SCL and SDA synchronizers, START/STOP detect logic, and LINEBUSY detect logic.\n
+    0 - Do nothing. */
+#define ADI_I2C_CFG_SHCTL_RST                   (0)
+
+/*! Timing control filter disable.\n
+    1 - Disable digital input clock filter.\n
+    0 - Enable digital input clock filter (1 PCLK). */
+#define ADI_I2C_CFG_TCTL_FILTEROFF              (0)
+
+/*! Timing control data input hold time requirement to recognize START/STOP condition (5-bit max).\n
+    Value - Minimum data input hold time count in units of PCLK period.  (Value = Thd/PCLK-period) */
+#define ADI_I2C_CFG_TCTL_THDATIN                (1)
+
+/*! Master automatic stretch mode duration (4-bit), e.g., (in binary):\n
+    - 0b0000 - No SCL clock stretching.\n
+    - 0b0001 - Timeout after hold SCL LOW 2^1 = 2 bit-times.\n
+    - 0b0010 - Timeout after hold SCL LOW 2^2 = 4 bit-times.\n
+    - ...\n
+    - 0b1110 - Timeout after hold SCL LOW 2^14 = 16,384 bit-times.\n
+    - 0b1111 - Hold SCL LOW with no timeout.\n
+\n
+    Where "bit-time" is computed by CLKDIV values and incoming UCLK (see HRM). */
+#define ADI_I2C_CFG_ASTRETCH_MST                (0)
+
+/*! Unformatted, 7-bit max width I2C "7-bit Addressing" slave device address value (unshifted and excluding R/W direction bit).\n
+    For example, the value:\n
+        0x50 - Is the "raw" (unencoded) slave address for the "Aardvark Activity Board" ATMEL AT24C02 I2C slave EEPROM device.\n
+            It is encoded (upshifted by one and ORed with R/W direction bit) on the I2C bus as:\n
+                - 0xA0 for write operations, or\n
+                - 0xA1 for read operations */
+#define ADI_I2C_CFG_SLAVE_ADDRESS              (0x50)
+
+
+/***********************************\
+|* Check for overflowing values... *|
+\***********************************/
+
+#if (ADI_I2C_CFG_MCTL_MXMITDEC >> 1)
+#error "Decrement TX FIFO status config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_MCTL_IENCMP >> 1)
+#error "Transaction complete (STOP) interrupt enable config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_MCTL_IENACK >> 1)
+#error "NACK interrupt enable config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_MCTL_IENALOST >> 1)
+#error "ALOST interrupt enable config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_MCTL_STRETCHSCL >> 1)
+#error "Clock stretch enable config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_MCTL_LOOPBACK >> 1)
+#error "Loopback enable config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_MCTL_COMPLETE >> 1)
+#error "Start back-off disable config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_MCTL_MASEN >> 1)
+#error "Master device enable config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_DIV_HIGH >> 8)
+#error "Clock HIGH time config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_DIV_LOW >> 8)
+#error "Clock LOW time config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_SHCTL_RST >> 1)
+#error "Shared control reset config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_TCTL_FILTEROFF >> 1)
+#error "Timing control filter-off config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_TCTL_THDATIN >> 5)
+#error "Timing control filter-off config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_ASTRETCH_MST >> 4)
+#error "Master clock stretch config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_SLAVE_ADDRESS >> 7)
+#error "Slave address config value too wide"
+#endif
+
+/*! @} */
+
+#endif /* ADI_I2C_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_pwr_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_pwr_config.h
new file mode 100755
index 00000000000..2eb5a38d17c
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_pwr_config.h
@@ -0,0 +1,668 @@
+/*
+ *****************************************************************************
+   @file:    adi_pwr_config.h
+   @brief:   Configuration options for PWR driver.
+             This is specific to the PWR driver and will be included by the source file.
+             It is not required for the application to include this header file.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_PWR_CONFIG_H
+#define ADI_PWR_CONFIG_H
+#include <adi_global_config.h>
+#ifdef __ICCARM__
+/* IAR MISRA C 2004 error suppressions.
+*
+* Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters.
+*   The YODA-generated headers rely on more. The IAR compiler supports that.
+*/
+#pragma diag_suppress=Pm009
+#endif /* __ICCARM__ */
+
+/** @addtogroup PWR_Driver_Config Static Configuration
+ *  @ingroup Power_Driver
+ *  @{
+ */
+
+/*! Enable the code to support input clock through the GPIO pin
+    0 - No support for input clock through the GPIO pin.
+    1 - Support for input clock through the GPIO pin.
+
+*/
+#define ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO                    0
+
+/*-------------------------------------------------------------------------------
+           Set of MACROs for configuring the clock
+--------------------------------------------------------------------------------*/
+/* Oscillator Control Register */
+
+/*!
+    32 KHz clock select mux.  This clock connects to beeper, RTC.\n
+   0 -  Internal 32 KHz oscillator is selected.\n
+   1 -  External 32 KHz crystal is selected..
+*/
+#define ADI_PWR_LF_CLOCK_MUX                                    0
+
+
+/*!
+    High frequency internal oscillator enable\n
+   0 -  The HFOSC oscillator is disabled and placed in a low power state\n
+   1 -  The HFOSC oscillator is enabled.
+*/
+#define ADI_PWR_HFOSC_CLOCK_ENABLE                              1
+
+/*!
+   Low  frequency external oscillator enable and placed in a low power state\n
+   0 -  The LFXTAL oscillator is disabled\n
+   1 -  The LFXTAL oscillator is enabled.
+
+*/
+#define ADI_PWR_LFXTAL_CLOCK_ENABLE                             0
+
+/*!
+    High frequency external  oscillator enable\n
+   0 -  The HFXTAL  oscillator is disabled and placed in a low power state\n
+   1 -  The HFXTAL  oscillator is enabled.
+*/
+#define ADI_PWR_HFXTAL_CLOCK_ENABLE                              0
+
+/*!
+   Low frequency external clock fail interrupt enable \n
+   0 -  The LFXTAL clock monitor and clock fail interrupt disabled \n
+   1 -  The LFXTAL clock monitor and clock fail interrupt enabled.\n
+                                                                  \n
+   Note: This feature is available only in ADuCM4x50 processor.
+*/
+#define ADI_PWR_LFXTAL_CLOCK_MON_ENABLE                         0
+
+/*!
+   Automatic switching of the LF Mux to LF Oscillator on LFXTAL failure.  \n
+   0 -  Disables Automatic switching of LF Mux to LF Oscillator on LFXTAL failure \n
+   1 -  Disables Automatic switching of LF Mux to LF Oscillator on LFXTAL failure.\n
+                                                                                  \n
+   Note: This feature is available only in ADuCM4x50 processor.
+*/
+#define ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE                  0
+
+/*!
+   Low frequency crystal Robust mode enable. The Robust mode enables the LFXTAL oscillator to work also when an
+   additional resistive load is placed between the crystal pins and GND. \n
+   0 -  Selects Normal mode \n
+   1 -  Selects Robust mode \n
+                            \n
+   Note: This feature is available only in ADuCM4x50 processor.
+*/
+#define ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE                       0
+
+/*!
+   Low frequency crystal Robust mode load select. The amount of loading tolerated when robust mode is enabled. \n
+   0 -  No Trim, and big resistive loads not tolerated. \n
+   1 -  20 Mohm load mode, greater than 20 Mohm load allowed. \n
+   2 -  10 Mohm load mode, greater than 10 Mohm load allowed. \n
+   3 -  5 Mohm load mode, 5 Mohm load allowed on both IO pins. \n
+                                                               \n
+   Note: This feature is available only in ADuCM4x50 processor.
+*/
+#define ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT                       0
+
+
+/*!
+   Root clock monitor and Clock Fail interrupt enable.
+   0 - Disable Root Clock Monitor and Clock Fail interrupt.   \n
+   1 - Enable Root Clock Monitor and Clock Fail interrupt.    \n
+                                                              \n
+   Note: This feature is available only in ADuCM4x50 processor.
+*/
+#define ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE                       0
+
+
+/*!
+   Enable Auto switch to High Frequency Oscillator (HFOSC) when Root Clock Fails.
+   0 - Disable Automatic switching of the Root Clock. \n
+   1 - Enable Automatic switching of the Root Clock.  \n
+                                                      \n
+*/
+#define ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE               0
+
+
+/********** Miscellaneous clock setting register CTL0 *************/
+
+/*!
+    Selecting the input clock for  Root Clock mux.  Determines which single shared clock source
+    is used by the PCLK,  and HCLK dividers. \n
+    0 -  HFOSC High frequency internal oscillator \n
+    1 -  HFXTAL High frequency external oscillator\n
+    2 -  SPLL  Output of System PLL is selected\n
+    3 -  External GPIO port is selected
+*/
+#define ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX                         0
+
+/*!
+    GPIO clock out select. Selects the clock to be routed to the GPIO clock out pin. \n
+    0  -  Root Clock (ROOT_CLK)\n
+    1  -  Low Frequency Clock (LF_CLK) \n
+    2  -  ADC Clock (ACLK) \n
+    3  -  HCLK_BUS \n
+    4  -  HCLK_CORE \n
+    5  -  Peripheral Clock (PCLK)
+    6  -  Reference Clock for Flash controller timer (RCLK)\n
+    7  -  Mux of HFOSC, HFXTAL clock (RHP_CLK)\n
+    8  -  GP Timer 0 clock (GPT0_CLK)\n
+    9  -  GP Timer 1 clock (GPT1_CLK)\n
+    10 -  Peripherals operating at HCLK (HCLK_P)\n
+    11 -  PLL Clock out (PCLK)\n
+    12 -  RTC0 Clock \n
+    13 -  HP Buck Clock (HPBUCK_CLK)\n
+    14 -  HP Buck Non overlap clock\n
+    15 -  RTC1 generated clock \n
+                               \n
+   Note: This feature is available only in ADuCM4x50 processor.
+*/
+#define ADI_PWR_GPIO_CLOCK_OUT_SELECT                           0
+
+/*!
+    Flash reference clock and HPBUCK clock source mux.  \n
+    0 -  sourcing from HFOSC (High frequency internal oscillator) \n
+    2 -  sourcing from external HFXTAL(  High frequency external oscillator 26M Hz )\n
+    3 -  sourcing from external HFXTAL(  High frequency external oscillator 16M Hz )
+
+*/
+#define ADI_PWR_INPUT_TO_RCLK_MUX                               0
+
+/*!
+    Selecting the input clock for the system PLL clock.  \n
+    0 -  sourcing from  HFOSC (High frequency internal oscillator) \n
+    1 -  sourcing from  HFXTAL(High frequency external oscillator) \n
+    2 -  GPIO Input clock. \n
+    3 -  GPIO Input clock.
+*/
+#define ADI_PWR_INPUT_TO_SPLL_MUX                               0
+
+/*!
+    External Low frequency crystal interrupt enable.\n
+    0 -  Disable the interrupt for LF clock \n
+    1 -  Enable the interrupt for LF clock
+*/
+#define ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE                   0
+
+/*!
+    External Hight frequency crystal interrupt enable.\n
+    0 -  Disable the interrupt for HFXTAL clock \n
+    1 -  Enable the interrupt for  HFXTAL clock
+*/
+#define ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE                    0
+
+
+
+/********** Clock divider register CTL1 ***************/
+
+/*!
+    HCLK divide count.Determines the HCLK rate based on the following equation: HCLK = ROOT_CLK/HCLKDIVCNT.
+    0 - 63 is valid range.
+*/
+#define ADI_PWR_HCLK_DIVIDE_COUNT                               4
+
+/*!
+    PCLK divide count.Determines the PCLK rate based on the following equation: PCLK = ROOT_CLK/PCLKDIVCNT.
+    0 - 63 is valid range.
+*/
+#define ADI_PWR_PCLK_DIVIDE_COUNT                               4
+
+/*!
+    ACLK divide count.Determines the ACLK rate based on the following equation: ACLK = ROOT_CLK/ACLKDIVCNT.
+    0 - 63 is valid range.
+*/
+#define ADI_PWR_ACLK_DIVIDE_COUNT                               16
+
+
+
+/************* HF Oscillator divide clock select register CTL2 ***********/
+
+/*!
+    HF Oscillator auto divide by one clock selection during wakeup from Flexi power mode.
+
+    When enabled enabled (Set to 1), the frequency undivided 26MHz HF oscillator clock itself will be used during the wake up.
+    The undivided HFOSC clock is selected automatically by clearing  the HFOSCDIVCLKSEL register content to 0, which selects the HFOSC/1 clock.This updated divided by 1 clock selection will remain same until the new divider value is written to this register.
+
+    When disabled (Set to 0), this fast wake up feature will be disabled and the HFOSCDIVCLKSEL register will remain unchanged
+    during the wakeup.
+
+    0 -  Auto select HFOSC/1 clock during wakeup from Flexi mode is disable. \n
+    1 -  Auto select HFOSC/1 clock during wakeup from Flexi mode is enabled. \n
+
+    Note: This feature is available only in ADuCM4x50 processor.
+*/
+#define ADI_PWR_HFOSC_AUTO_DIV_BY_1                              0
+
+/*!
+    HF Oscillator divide select.
+    0 -  HFOSC/1. \n
+    1 -  HFOSC/2. \n
+    2 -  HFOSC/4. \n
+    3 -  HFOSC/8. \n
+    4 -  HFOSC/16. \n
+    5 -  HFOSC/32. \n
+                   \n
+   Note: This feature is available only in ADuCM4x50 processor.
+*/
+#define ADI_PWR_HFOSC_DIVIDE_SELECT                              0
+
+
+
+/****** System PLL Register CTL3 *****/
+/*!
+    System PLL N multiplier(SPLL_NSEL).  Sets the N value used to obtain the multiplication
+    factor N/M of the PLL.
+    8 - 31 is valid range.
+*/
+#define ADI_PWR_SPLL_MUL_FACTOR                                 26
+
+/*!
+    System PLL division by 2.  Controls if an optional divide by two is placed on the PLL output.\n
+    0 -  The System PLL is not divided. Its output frequency equals that selected by the N/M ratio \n
+    1 -  The System PLL is divided by two. Its output frequency equals that selected by the N/M ratio
+         with an additional divide by 2
+*/
+#define ADI_PWR_SPLL_ENABLE_DIV2                                0
+
+/*!
+    System PLL enable.  Controls if the PLL should be enabled or placed in its low power state. \n
+    0 - The system PLL is disabled and is in its power down state\n
+    1 - The system  PLL is enabled.
+*/
+#define ADI_PWR_SPLL_ENABLE                                     0
+
+/*!
+    System PLL interrupt enable.Controls if the core should be interrupted on a PLL lock/PLL unlock or no interrupt generated.\n
+    0 - Disable the SPLL interrupt generation\n
+    1 - Enable the SPLL interrupt generation
+*/
+#define ADI_PWR_SPLL_INTERRUPT_ENABLE                           0
+
+/*!
+    System PLL M Divider(SPLL_MSEL).  Sets the M value used to obtain the multiplication
+    factor N/M of the PLL.
+    2 - 15 is valid range.
+*/
+#define ADI_PWR_SPLL_DIV_FACTOR                                 13
+
+/*!
+    system PLL multiply by 2.  This bit is used to configure if the VCO clock frequency should be multiplied by 2 or 1.\n
+    0 -  The System PLL is multiplied by 1.\n
+    1 -  The System PLL is multiplied by 2.
+*/
+#define ADI_PWR_SPLL_ENABLE_MUL2                                0
+
+
+/********** User Clock Gating Control CTL5 ********************/
+
+/*!
+    This can be  used to enable/disable clock to GPT0.  \n
+    0 - Disable  the clock to GPT0\n
+    1 - Enable the clock to GPT0
+*/
+#define ADI_PWR_GPT0_CLOCK_ENABLE                               1
+
+/*!
+    This can be  used to enable/disable clock to GPT1.  \n
+    0 - Disable  the clock to GPT1\n
+    1 - Enable the clock to   GPT1
+*/
+#define ADI_PWR_GPT1_CLOCK_ENABLE                               1
+/*!
+    This can be  used to enable/disable clock to GPT2.  \n
+    0 - Disable  the clock to GPT2\n
+    1 - Enable the clock to   GPT2
+*/
+#define ADI_PWR_GPT2_CLOCK_ENABLE                               1
+
+/*!
+    This can be  used to enable/disable clock to I2C.  \n
+    0 - Disable  the clock to I2C\n
+    1 - Enable the clock to   I2C\n
+                                 \n
+   Note: This feature is available only in ADuCM4x50 processor.
+*/
+#define ADI_PWR_I2C_CLOCK_ENABLE                                1
+
+/*!
+    This can be used to enable/disable clock to GPIO.  \n
+    0 - Disable the clock to GPIO\n
+    1 - Enable the clock to  GPIO \n
+
+    Note: This feature is available only in ADuCM4x50 processor.
+*/
+#define ADI_PWR_GPIO_CLOCK_ENABLE                               1
+
+
+/*!
+    This can be used to enable/disable all clocks connected to peripherals.  \n
+    0 - Disable  the Clock supply to  peripherals\n
+    1 - Enable the Clock supply to  peripherals \n
+                                                \n
+   Note: This feature is available only in ADuCM4x50 processor.
+*/
+#define ADI_PWR_PCLK_ENABLE                                     0
+
+/*!
+    This can be used to enable/disable clocks to Timer RGB.  \n
+    0 - Disable the Clock supply to Timer RGB \n
+    1 - Enable the Clock supply to Timer RGB \n
+                                             \n
+   Note: This feature is available only in ADuCM4x50 processor.
+*/
+#define ADI_PWR_TIMER_RGB_ENABLE                                 1
+
+/*-------------------------------------------------------------------------------
+           Set of macros for configuring the power management module
+--------------------------------------------------------------------------------*/
+
+/********* Interrupt enable register IEN ********/
+
+/*!
+    Enabling the interrupt if the  Battery  voltage falls below 1.8V.\n
+   0 -  Disable Battery voltage interrupt \n
+   1 -  Enable Battery voltage interrupt.
+*/
+#define ADI_PWR_ENABLE_VBAT_INTERRUPT                           0
+
+/*!
+    Enabling the interrupt for under VREG voltage (i.e less than 1V).\n
+   0 -  Disable VREG under voltage  interrupt \n
+   1 -  Enable VREG under voltage  interrupt.
+*/
+#define ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT             0
+
+/*!
+    Enabling the interrupt for over  VREG voltage (i.e above  than 1.32V).\n
+   0 -  Disable VREG over  voltage  interrupt \n
+   1 -  Enable VREG  over voltage  interrupt.
+*/
+#define ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT              0
+
+/*!
+    Enabling the interrupt for Battery range.\n
+   0 -  Disable battery voltage range  interrupt \n
+   1 -  Enable battery voltage range  interrupt
+*/
+#define ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT          0
+
+/*!
+    Battery voltage range for generating the interrupt.\n
+   0 - Configure to generate interrupt if VBAT > 2.75V \n
+   1 - Configure to generate interrupt if VBAT is between 2.75 and 1.6V  \n
+   2 - Configure to generate interrupt if VBAT is between 2.3V and 1.6V
+*/
+#define ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT             0
+
+/********* HP Buck control register CTL1 ********/
+/*!
+    Enable or disable HP Buck.\n
+    0 - Disable HP Buck.
+    1 - Enable HP Buck.
+*/
+#define ADI_PWR_HP_BUCK_ENABLE                                  0
+
+/*!
+    HP Buck Load mode.\n
+    0 - HP Buck low load mode. Can be set when the system is running at
+        less than 26 Mhz. \n
+    1 - HP Buck High load mode. Can be set when the system is running at
+        more than 26 Mh. \n
+                         \n
+   Note: This feature is available only in ADuCM4x50 processor.
+*/
+#define ADI_PWR_HP_BUCK_LOAD_MODE                               0
+
+/*!
+    HP Buck low power mode.\n
+    The HPBUCK Low Power mode can be selected, when the  Chip is in Flexi Power mode
+    and low power modules such as Timer, Beeper only are enabled
+
+    0 - HPBUCK Low power mode is disabled. \n
+    1 - HPBUCK Low power mode is enabled.  \n
+                                           \n
+    Note: This feature is available only in ADuCM4x50 processor.
+*/
+#define ADI_PWR_HP_BUCK_LOW_POWER_MODE                           0
+
+
+/********* Power mode register ********/
+
+/*!
+    Enable or disable monitoring battery voltage (VBAT) during HIBERNATE Mode. \n
+    0 - Battery voltage monitoring is enabled.
+    1 - Battery voltage monitoring is disabled.
+
+    By default battery voltage monitoring during hibernate is enabled.
+*/
+#define ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING                0
+
+
+/*******************************************************************************
+                        M A C R O   V A L I D A T I O N
+*******************************************************************************/
+
+#if ( ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO > 1 )
+#error "Invalid configuration set for ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO"
+#endif
+
+#if ( ADI_PWR_LF_CLOCK_MUX > 1 )
+#error "Invalid configuration set for ADI_PWR_LF_CLOCK_MUX"
+#endif
+
+#if ( ADI_PWR_HFOSC_CLOCK_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_HFOSC_CLOCK_ENABLE"
+#endif
+
+#if ( ADI_PWR_LFXTAL_CLOCK_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_LFXTAL_CLOCK_ENABLE"
+#endif
+
+#if ( ADI_PWR_HFXTAL_CLOCK_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_HFXTAL_CLOCK_ENABLE"
+#endif
+
+#if ( ADI_PWR_LFXTAL_CLOCK_MON_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_LFXTAL_CLOCK_MON_ENABLE"
+#endif
+
+#if ( ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE"
+#endif
+
+#if ( ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE"
+#endif
+
+#if ( ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT > 3 )
+#error "Invalid configuration set for ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT"
+#endif
+
+#if ( ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE"
+#endif
+
+#if ( ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE"
+#endif
+
+#if ( ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX > 3 )
+#error "Invalid configuration set for ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX"
+#endif
+
+#if ( ADI_PWR_GPIO_CLOCK_OUT_SELECT > 15 )
+#error "Invalid configuration set for ADI_PWR_GPIO_CLOCK_OUT_SELECT"
+#endif
+
+#if ( ADI_PWR_INPUT_TO_RCLK_MUX > 3 )
+#error "Invalid configuration set for ADI_PWR_INPUT_TO_RCLK_MUX"
+#endif
+
+#if ( ADI_PWR_INPUT_TO_SPLL_MUX > 3 )
+#error "Invalid configuration set for ADI_PWR_INPUT_TO_SPLL_MUX"
+#endif
+
+#if ( ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE"
+#endif
+
+#if ( ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE"
+#endif
+
+#if ( ADI_PWR_HCLK_DIVIDE_COUNT > 63 )
+#error "Invalid configuration set for ADI_PWR_HCLK_DIVIDE_COUNT"
+#endif
+
+#if ( ADI_PWR_PCLK_DIVIDE_COUNT > 63 )
+#error "Invalid configuration set for ADI_PWR_PCLK_DIVIDE_COUNT"
+#endif
+
+#if ( ADI_PWR_ACLK_DIVIDE_COUNT > 63 )
+#error "Invalid configuration set for ADI_PWR_ACLK_DIVIDE_COUNT"
+#endif
+
+#if ( ADI_PWR_HFOSC_AUTO_DIV_BY_1 > 1 )
+#error "Invalid configuration set for ADI_PWR_HFOSC_AUTO_DIV_BY_1"
+#endif
+
+#if ( ADI_PWR_HFOSC_DIVIDE_SELECT > 5 )
+#error "Invalid configuration set for ADI_PWR_HFOSC_DIVIDE_SELECT"
+#endif
+
+#if ( ADI_PWR_SPLL_MUL_FACTOR < 8 || ADI_PWR_SPLL_MUL_FACTOR > 31 )
+#error "Invalid configuration set for ADI_PWR_SPLL_MUL_FACTOR"
+#endif
+
+#if ( ADI_PWR_SPLL_ENABLE_DIV2 > 1 )
+#error "Invalid configuration set for ADI_PWR_SPLL_ENABLE_DIV2"
+#endif
+
+#if ( ADI_PWR_SPLL_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_SPLL_ENABLE"
+#endif
+
+#if ( ADI_PWR_SPLL_INTERRUPT_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_SPLL_INTERRUPT_ENABLE"
+#endif
+
+#if ( ADI_PWR_SPLL_DIV_FACTOR < 2 || ADI_PWR_SPLL_DIV_FACTOR > 15 )
+#error "Invalid configuration set for ADI_PWR_SPLL_DIV_FACTOR"
+#endif
+
+#if ( ADI_PWR_SPLL_ENABLE_MUL2 > 1 )
+#error "Invalid configuration set for ADI_PWR_SPLL_ENABLE_MUL2"
+#endif
+
+#if ( ADI_PWR_GPT0_CLOCK_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_GPT0_CLOCK_ENABLE"
+#endif
+
+#if ( ADI_PWR_GPT1_CLOCK_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_GPT1_CLOCK_ENABLE"
+#endif
+
+#if ( ADI_PWR_GPT2_CLOCK_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_GPT2_CLOCK_ENABLE"
+#endif
+
+#if ( ADI_PWR_I2C_CLOCK_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_I2C_CLOCK_ENABLE"
+#endif
+
+#if ( ADI_PWR_GPIO_CLOCK_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_GPIO_CLOCK_ENABLE"
+#endif
+
+#if ( ADI_PWR_PCLK_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_PCLK_ENABLE"
+#endif
+
+#if ( ADI_PWR_TIMER_RGB_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_TIMER_RGB_ENABLE"
+#endif
+
+#if ( ADI_PWR_ENABLE_VBAT_INTERRUPT > 1 )
+#error "Invalid configuration set for ADI_PWR_ENABLE_VBAT_INTERRUPT"
+#endif
+
+#if ( ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT > 1 )
+#error "Invalid configuration set for ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT"
+#endif
+
+#if ( ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT > 1 )
+#error "Invalid configuration set for ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT"
+#endif
+
+#if ( ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT > 1 )
+#error "Invalid configuration set for ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT"
+#endif
+
+#if ( ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT > 2 )
+#error "Invalid configuration set for ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT"
+#endif
+
+#if ( ADI_PWR_HP_BUCK_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_HP_BUCK_ENABLE"
+#endif
+
+#if ( ADI_PWR_HP_BUCK_LOAD_MODE > 1 )
+#error "Invalid configuration set for ADI_PWR_HP_BUCK_LOAD_MODE"
+#endif
+
+#if ( ADI_PWR_HP_BUCK_LOW_POWER_MODE > 1 )
+#error "Invalid configuration set for ADI_PWR_HP_BUCK_LOW_POWER_MODE"
+#endif
+
+#if ( ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING > 1 )
+#error "Invalid configuration set for ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING"
+#endif
+
+
+
+/*! @} */
+
+#ifdef __ICCARM__
+#pragma diag_default=Pm009
+#endif /* __ICCARM__ */
+
+#endif /* ADI_PWR_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_rng_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_rng_config.h
new file mode 100755
index 00000000000..76afe147cfb
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_rng_config.h
@@ -0,0 +1,106 @@
+/*!
+ *****************************************************************************
+   @file:    adi_rng_config.h
+   @brief:   Configuration options for RNG driver.
+             This is specific to the RNG driver and will be included by the driver.
+             It is not required for the application to include this header file.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2012-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_RNG_CONFIG_H__
+#define ADI_RNG_CONFIG_H__
+#include <adi_global_config.h>
+/** @defgroup RNG_Driver_Cfg RNG Driver Configuration
+ *  @ingroup RNG_Driver
+
+ */
+
+/*! \addtogroup  RNG_Driver_Cfg RNG Driver Configuration
+ *  @{
+ */
+
+/************* RNG Driver configurations ***************/
+
+/************* RNG controller configurations ***************/
+
+/*! RNG Control Register, bit 3\n
+    Enable only 8-bit generation\n
+    0 -  Generate 32-bit random number\n
+    1 -  Generate only 8-bit random number
+*/
+#define RNG0_CFG_ONLY_8_BIT                             1
+
+/*! RNG Sample Length Register, bits [11:0]\n
+    The register defines the number of samples to accumulate in the
+    CRC register when generating a random number.\n
+
+    Bits [11:0] contains the reload value of the sample counter
+
+    */
+#define RNG0_CFG_LENGTH_RELOAD                          256u
+
+/*! RNG Sample Length Register, bits [15:12]\n
+    The register defines the number of samples to accumulate in the
+    CRC register when generating a random number. The number of values
+    accumulated in the counter reload value is scaled by 2^prescaler.\n
+
+    Bits [15:12] contains the prescaler for the sample counter
+
+    */
+#define RNG0_CFG_LENGTH_PRESCALER                       0u
+
+/************** Macro validation *****************************/
+
+#if ( RNG0_CFG_ONLY_8_BIT > 1 )
+#error "Invalid configuration"
+#endif
+
+#if ( RNG0_CFG_LENGTH_RELOAD > 4095u )
+#error "Invalid value for reload"
+#endif
+
+#if ( RNG0_CFG_LENGTH_PRESCALER > 10u )
+#error "Invalid value for prescaler"
+#endif
+
+/*! @} */
+
+#endif /* __ADI_RNG_CONFIG_H__ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_rtc_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_rtc_config.h
new file mode 100755
index 00000000000..ef97a3b0a48
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_rtc_config.h
@@ -0,0 +1,397 @@
+/*!
+ *****************************************************************************
+   @file:    adi_rtc_config.h
+   @brief:   Configuration options for Real Time Clock  device  driver.
+             This is specific to the RTC driver and will be included by the driver.
+             It is not required for the application to include this header file.
+   @version: $Revision: 33005 $
+   @date:    $Date: 2015-12-12 10:43:13 -0500 (Sat, 12 Dec 2015) $
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2012-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_RTC_CONFIG_H__
+#define ADI_RTC_CONFIG_H__
+#include <adi_global_config.h>
+
+/** @addtogroup RTC_Driver_Config Static Configuration
+ *  @ingroup RTC_Driver
+ *  @{
+ */
+
+/*!
+ * The safe write mode insures any pending writes that have not yet synchronized between the faster core clock
+ * domain and the internal RTC 32kHz clock domain are reconciled before multiple writes to the same RTC register
+ * are allowed
+*/
+
+#define ADI_RTC_CFG_ENABLE_SAFE_WRITE 1    
+
+
+/** @addtogroup RTC_Driver_Config_RTC0 RTC0 Static Configuration
+ *  @ingroup RTC_Driver_Config
+ *  @{
+ */
+
+/*
+===================================================================
+ ------------------------RTC-0 CONFIGURATION MACRO-----------------
+===================================================================
+*/
+/*! Enable the Alarm */
+#define RTC0_CFG_ENABLE_ALARM                  0     
+
+/*! Enable the Alarm interrupt*/
+#define RTC0_CFG_ENABLE_ALARM_INTERRUPT        0     
+
+/*! Enable the Trim */
+#define RTC0_CFG_ENABLE_TRIM                    0     
+
+/*! Enable the PENDERROR interrupt*/
+#define RTC0_CFG_ENABLE_PENDERROR_INTERRUPT     0     
+
+/*! Enable the write sync  interrupt*/
+#define RTC0_CFG_ENABLE_WSYNC_INTERRUPT         0     
+
+/*! Enable the pend write interrupt*/
+#define RTC0_CFG_ENABLE_WRITEPEND_INTERRUPT     0     
+
+/*! Initial the count Value*/
+#define RTC0_CFG_COUNT_VALUE                    0     
+
+/*! Initial the count Value-0*/
+#define RTC0_CFG_COUNT_VALUE_0                  0     
+
+/*! Initial the count Value-1*/
+#define RTC0_CFG_COUNT_VALUE_1                  0     
+
+/*! Alarm-0  Value*/
+#define RTC0_CFG_ALARM_VALUE_0                  0     
+
+/*! Alarm-1  Value*/
+#define RTC0_CFG_ALARM_VALUE_1                  0     
+
+/*! Trim interval*/
+#define RTC0_CFG_TRIM_INTERVAL                  0     
+
+/*! Trim interval with power of 2*/
+#define RTC0_CFG_POW2_TRIM_INTERVAL             0     
+
+/*! Trim operation to be performed for RTC0*/
+#define RTC0_CFG_TRIM_OPERATION                 0     
+
+/*! Trim  Value for RTC-0*/
+#define RTC0_CFG_TRIM_VALUE                     0     
+
+/*! GPIO Sample around Rising Edge of Sensor Strobe Channel 3. 
+ * Enables sampling of Sensor Strobe GPIO inputs around rising edge of Sensor Strobe Channel 3 pulse.
+ *
+ *  0 No sampling of input around rising edge.
+ *  1 Input sampled one clock cycle before rising edge of Sensor Strobe.
+ * 10 Input sampled at rising edge of Sensor Strobe.
+ * 11 Input sampled one clock cycle after rising edge of Sensor Strobe.
+ */
+#define RTC0_SS3_SMPONRE                          0
+
+/*! GPIO Sample around Falling Edge of Sensor Strobe Channel 3. 
+ *  Enables sampling of Sensor Strobe GPIO inputs around falling edge of Sensor Strobe Channel 3 pulse. 
+ *
+ *  0	No sampling of input around rising edge.		
+ *  1	Input sampled one clock cycle before rising edge of Sensor Strobe.		
+ * 10	Input sampled at rising edge of Sensor Strobe.
+ * 11	Input sampled one clock cycle after rising edge of Sensor Strobe.		
+ */
+#define RTC0_SS3_SMPONFE                          0
+/*! GPIO Sample around Falling Edge of Sensor Strobe Channel 2.  */
+#define RTC0_SS2_SMPONFE                          0
+/*! GPIO Sample around Rising Edge of Sensor Strobe Channel 1.   */ 
+#define RTC0_SS1_SMPONRE                          0
+/*! GPIO Sample around Falling Edge of Sensor Strobe Channel 1.  */
+#define RTC0_SS1_SMPONFE                          0
+
+
+/*! Sensor Strobe's GP Input Sampling Mux
+ *  SS 2 GPIO Pin 1
+ *
+ * GPMUX0/1.SSxGPINySEL	3�b000	3�b001	3�b010	3�b011	3�b100	3�b101	3�b110	3�b111
+ * RTCSSxGPIny           p0[12] p2[0]    p0[9]  p0[8]   p1[13]   p1[2]   p2[7]   p2[9]
+ */
+#define RTC0_SS2_GPIN1SEL                       0x4
+/*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 0*/
+#define RTC0_SS2_GPIN0SEL                       0x3
+/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 2*/
+#define RTC0_SS1_GPIN2SEL                       0x2
+/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 1*/
+#define RTC0_SS1_GPIN1SEL                       0x1
+/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 0*/
+#define RTC0_SS1_GPIN0SEL                       0x0
+/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 2*/
+#define RTC0_SS3_GPIN2SEL                       0x0
+/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 1*/
+#define RTC0_SS3_GPIN1SEL                       0x7
+/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 0*/
+#define RTC0_SS3_GPIN0SEL                       0x6
+/*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 2*/
+#define RTC0_SS2_GPIN2SEL                       0x5
+
+/*! Differential output option for Sensor Strobe channel 3.
+ *  Sensor Strobe channel3 is used as differential signal, actual RTC_SS3 out 
+ *  for this channel is available in corresponding GPIO. 
+ *  RTC_SS4 of Sensor Strobe channel 4 is used to provided inverted signal of RTC_SS3.
+ */
+#define RTC0_SS3_DIFFOUT                           0
+/*! Differential output option for Sensor Strobe channel 1.
+ *  Sensor Strobe channel 1 is used as differential signal, actual RTC_SS1 out 
+ *  for this channel is available in corresponding GPIO. 
+ *  RTC_SS1 of Sensor Strobe channel 2 is used to provided inverted signal of RTC_SS1.
+ */
+#define RTC0_SS1_DIFFOUT                           0
+
+
+
+/*! @} */
+
+/*
+===================================================================
+ ------------------------RTC-1 CONFIGURATION MACRO-----------------
+===================================================================
+*/
+
+/** @addtogroup RTC_Driver_Config_RTC1 RTC1 Static Configuration
+ *  @ingroup RTC_Driver_Config
+ *  @{
+ */
+
+
+   
+/*! Enable the Alarm */
+#define RTC1_CFG_ENABLE_ALARM                       0     
+
+/*! Enable the Alarm interrupt*/
+#define RTC1_CFG_ENABLE_ALARM_INTERRUPT             0     
+
+/*! Enable the Trim */
+#define RTC1_CFG_ENABLE_TRIM                        0     
+
+/*! Enable the mod-60 Alarm */
+#define RTC1_CFG_ENABLE_MOD60_ALARM                 0     
+
+/*! Enable the mod-60 Alarm  period*/
+#define RTC1_CFG_ENABLE_MOD60_ALARM_PERIOD          0     
+
+/*! Enable the Alarm interrupt*/
+#define RTC1_CFG_ENABLE_MOD60_ALARM_INTERRUPT       0     
+
+/*! Enable the ISOINT interrupt*/
+#define RTC1_CFG_ENABLE_ISO_INTERRUPT               0     
+
+/*! Enable the PENDERROR interrupt*/
+#define RTC1_CFG_ENABLE_PENDERROR_INTERRUPT         0     
+
+/*! Enable the write sync  interrupt*/
+#define RTC1_CFG_ENABLE_WSYNC_INTERRUPT             0     
+
+/*! Enable the pend write interrupt*/
+#define RTC1_CFG_ENABLE_WRITEPEND_INTERRUPT         0     
+
+/*! Enable the RTC count interrupt*/
+#define RTC1_CFG_ENABLE_COUNT_INTERRUPT             0     
+
+/*! Enable the prescaled modulo-1 interrupt*/
+#define RTC1_CFG_ENABLE_MOD1_COUNT_INTERRUPT        0     
+
+/*! Enable the Trim interrupt*/
+#define RTC1_CFG_ENABLE_TRIM_INTERRUPT              0     
+
+/*! Enable the Mod60 roll over  interrupt*/
+#define RTC1_CFG_CNT_MOD60_ROLLLOVER_INTERRUPT      0     
+
+/*! Prescale value for the RTC1*/
+#define RTC1_CFG_PRESCALE                           0     
+
+/*! Enable the counter roll over  interrupt*/
+#define RTC1_CFG_CNT_ROLLLOVER_INTERRUPT            0     
+
+/*! Initial the count Value-0*/
+#define RTC1_CFG_COUNT_VALUE_0                      0     
+
+/*! Initial the count Value-1*/
+#define RTC1_CFG_COUNT_VALUE_1                      0     
+
+/*! Alarm  Value-0*/
+#define RTC1_CFG_ALARM_VALUE_0                      0     
+
+/*! Alarm  Value-1*/
+#define RTC1_CFG_ALARM_VALUE_1                      0     
+
+/*! Alarm  Value-2*/
+#define RTC1_CFG_ALARM_VALUE_2                      0     
+
+/*! Trim interval*/
+#define RTC1_CFG_TRIM_INTERVAL                      0     
+
+/*! Trim interval with power of 2*/
+#define RTC1_CFG_POW2_TRIM_INTERVAL                 0     
+
+/*! Trim operation to be performed for RTC1*/
+#define RTC1_CFG_TRIM_OPERATION                     0     
+
+/*! Trim  Value for RTC-1*/
+#define RTC1_CFG_TRIM_VALUE                         0     
+
+/*! Enable the input capture channel-0*/
+#define RTC1_CFG_IC0_ENABLE                         0     
+
+/*! Enable the input capture channel-2*/
+#define RTC1_CFG_IC2_ENABLE                         0     
+
+/*! Enable the input capture channel-3*/
+#define RTC1_CFG_IC3_ENABLE                         0     
+
+/*! Enable the input capture channel-4*/
+#define RTC1_CFG_IC4_ENABLE                         0     
+
+/*! Enable the Sensor Strobe channel-1*/
+#define RTC1_CFG_SS1_ENABLE                         0     
+/*! Enable the Sensor Strobe channel-2*/
+#define RTC1_CFG_SS2_ENABLE                         0     
+/*! Enable the Sensor Strobe channel-3*/
+#define RTC1_CFG_SS3_ENABLE                         0     
+/*! Enable the Sensor Strobe channel-4*/
+#define RTC1_CFG_SS4_ENABLE                         0     
+
+/*! Enable the interrupt for input capture channel-0*/
+#define RTC1_CFG_IC0_INT_ENABLE                     0     
+
+/*! Enable the interrupt for input capture channel-2*/
+#define RTC1_CFG_IC2_INT_ENABLE                     0     
+
+/*! Enable the interrupt for input capture channel-3*/
+#define RTC1_CFG_IC3_INT_ENABLE                     0     
+
+/*! Enable the interrupt for input capture channel-4*/
+#define RTC1_CFG_IC4_INT_ENABLE                     0     
+
+/*! Enable the over write input capture channels*/
+#define RTC1_CFG_IC_OVER_WRITE_ENABLE               0    
+
+/*! Polarity for  input capture channel-0*/
+#define RTC1_CFG_IC0_EDGE_POLARITY                  0     
+
+/*! Polarity for  input capture channel-2*/
+#define RTC1_CFG_IC2_EDGE_POLARITY                  0     
+
+/*! Polarity for  input capture channel-3*/
+#define RTC1_CFG_IC3_EDGE_POLARITY                  0     
+
+/*! Polarity for  input capture channel-4*/
+#define RTC1_CFG_IC4_EDGE_POLARITY                  0     
+
+/*! Enable the interrupt for Sensor Strobe channel-1*/
+#define RTC1_CFG_SS1_INT_ENABLE                     0     
+/*! Enable the interrupt for Sensor Strobe channel-2*/
+#define RTC1_CFG_SS2_INT_ENABLE                     0     
+/*! Enable the interrupt for Sensor Strobe channel-3*/
+#define RTC1_CFG_SS3_INT_ENABLE                     0     
+/*! Enable the interrupt for Sensor Strobe channel-4*/
+#define RTC1_CFG_SS4_INT_ENABLE                     0    
+
+/*! Enable the masking for Sensor Strobe channel-1*/
+#define RTC1_CFG_SS1_MASK_ENABLE                    0     
+/*! Enable the masking for Sensor Strobe channel-2*/
+#define RTC1_CFG_SS2_MASK_ENABLE                    0     
+/*! Enable the masking for Sensor Strobe channel-3*/
+#define RTC1_CFG_SS3_MASK_ENABLE                    0     
+/*! Enable the masking for Sensor Strobe channel-4*/
+#define RTC1_CFG_SS4_MASK_ENABLE                    0     
+
+/*! Enable the auto-reloading for Sensor Strobe channel-0*/
+#define RTC1_CFG_SS1_AUTO_RELOADING_ENABLE          0     
+
+/*! Mask for Sensor Strobe channel-0 */
+#define RTC1_CFG_SS1_MASK_VALUE                     0     
+
+
+/*! Auto reload value  for Sensor Strobe channel-0 */
+#define RTC1_CFG_SS1_AUTO_RELOAD_VALUE              32768/2
+
+
+/*! Sensor Strobe GP Input Sampling Mux
+ *  SS2 GPIO Pin 1
+ *
+ * GPMUX0/1.SSxGPINySEL	3�b000	3�b001	3�b010	3�b011	3�b100	3�b101	3�b110	3�b111
+ * RTCSSxGPIny           p0[12] p2[0]    p0[9]  p0[8]   p1[13]   p1[2]   p2[7]   p2[9]
+ */
+#define RTC1_SS2_GPIN1SEL                       0x4
+/*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 0*/
+#define RTC1_SS2_GPIN0SEL                       0x3
+/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 2*/
+#define RTC1_SS1_GPIN2SEL                       0x2
+/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 1*/
+#define RTC1_SS1_GPIN1SEL                       0x1
+/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 0*/
+#define RTC1_SS1_GPIN0SEL                       0x0
+/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 2*/
+#define RTC1_SS3_GPIN2SEL                       0x0
+/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 1*/
+#define RTC1_SS3_GPIN1SEL                       0x7
+/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 0*/
+#define RTC1_SS3_GPIN0SEL                       0x6
+/*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 2*/
+#define RTC1_SS2_GPIN2SEL                       0x5
+
+/*! Differential output option for Sensor Strobe channel 3.
+ *  Sensor Strobe channel3 is used as differential signal, actual RTC_SS3 out 
+ *  for this channel is available in corresponding GPIO. 
+ *  RTC_SS4 of Sensor Strobe channel 4 is used to provided inverted signal of RTC_SS3.
+ */
+#define RTC1_SS3_DIFFOUT                           0
+/*! Differential output option for Sensor Strobe channel 1.
+ *  Sensor Strobe channel 1 is used as differential signal, actual RTC_SS1 out 
+ *  for this channel is available in corresponding GPIO. 
+ *  RTC_SS1 of Sensor Strobe channel 2 is used to provided inverted signal of RTC_SS1.
+ */
+#define RTC1_SS1_DIFFOUT                           0
+
+
+/*! @} */
+
+/*! @} */
+#endif /* ADI_RTC_CONFIG_H__ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_spi_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_spi_config.h
new file mode 100755
index 00000000000..e2a8ccd572b
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_spi_config.h
@@ -0,0 +1,592 @@
+/*!
+ *****************************************************************************
+   @file:    adi_spi_config.h
+   @brief:   Configuration options for SPI driver.
+             This is specific to the SPI driver and will be included by the driver.
+             It is not required for the application to include this header file.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_SPI_CONFIG_H__
+#define ADI_SPI_CONFIG_H__
+#include <adi_global_config.h>
+/** @addtogroup SPI_Driver_Config Static Configuration
+ *  @ingroup SPI_Driver
+ *  @{
+ */
+
+
+/*! Set this macro to the system clock frequency in hertz*/
+#define ADI_CFG_SYSTEM_CLOCK_HZ                    (26000000u)
+
+/************* SPI controller configurations ***************/
+
+/* There are three SPI instances SPI0, SPI1 and SPI2       */
+/* Each SPI has its own configuration macros                */
+
+
+/*----------------------------------------------------------*/
+/* -------------------- SPI0 -------------------------------*/
+/*----------------------------------------------------------*/
+
+/** @addtogroup SPI_Driver_Config_SPI0 SPI0 Static Configuration
+ *  @ingroup SPI_Driver_Config
+ *  @{
+ */
+
+ /*! If using SPI0 in master mode set this macro to 1. For slave mode set this macro to 0. */
+#define ADI_SPI0_MASTER_MODE               (1u)
+
+
+/*! Set this macro to the SPI0 bit rate in hertz */
+#define ADI_SPI0_CFG_BIT_RATE               (2000000u)
+
+/*! SPI0 enable\n
+    SPI configuration register: Bit[0]\n
+    1 -  Enable SPI\n
+    0 -  Disable SPI */
+#define ADI_SPI0_CFG_ENABLE                         (0u)
+
+/*! SPI0 clock phase mode\n
+    SPI configuration register: Bit[2]\n
+    1 - Serial clock pulses at the beginning of each serial bit transfer.\n
+    0 - Serial clock pulses at the end of each serial bit transfer. */
+#define ADI_SPI0_CFG_CLK_PHASE                      (0u)
+
+
+
+
+
+/*! SPI0 clock polarity\n
+    SPI configuration register: Bit[3]\n
+    1 - Serial clock idles high.\n
+    0 - Serial clock idles low. */
+#define ADI_SPI0_CFG_CLK_POLARITY                   (0u)
+
+
+/*! SPI0 wired OR mode\n
+    SPI configuration register: Bit[4]\n
+    1 - Enables open circuit output enable.\n
+    0 - Normal output levels. */
+#define ADI_SPI0_CFG_WIRED_OR                       (0u)
+
+
+/*! SPI0 LSB/MSB\n
+    SPI configuration register: Bit[5]\n
+    1 - MSB transmitted first.\n
+    0 - LSB transmitted first. */
+#define ADI_SPI0_CFG_LSB_MSB                        (0u)
+
+
+/*! SPI0 transfer initiate\n
+    SPI configuration register: Bit[6]\n
+    1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n
+    0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/
+#define ADI_SPI0_CFG_TRANSFER_INITIATE              (0u)
+
+
+/*! SPI0 Tx FIFO transfers zeros or last bit upon underflow\n
+    SPI configuration register: Bit[7]\n
+    1 - Tx FIFO sends zeros upon underflow.\n
+    0 - Tx FIFO repeats last bit upon underflow. */
+#define ADI_SPI0_CFG_TX_UNDERFLOW                   (0u)
+
+
+/*! SPI0 Rx FIFO overflows with received data or data is discarded\n
+    SPI configuration register: Bit[8]\n
+    1 - Rx FIFO receives data upon overflow.\n
+    0 - Rx FIFO discards received data upon overflow. */
+#define ADI_SPI0_CFG_RX_OVERFLOW                    (0u)
+
+
+/*! SPI0 slave mode MISO enable\n
+    SPI configuration register: Bit[9]\n
+    1 - MISO operates as normal in slave mode.\n
+    0 - MISO is disabled in slave mode. */
+#define ADI_SPI0_CFG_MISO_ENABLE                    (0u)
+
+
+/*! SPI0 internal loopback enable\n
+    SPI configuration register: Bit[10]\n
+    1 - MISO and MOSI is loopbacked internally.\n
+    0 - MISO and MOSI operates normally. */
+#define ADI_SPI0_CFG_LOOPBACK                       (0u)
+
+/*! SPI0 transfer and interrupt mode\n
+    SPI configuration register: Bit[11]\n
+    1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n
+    0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/
+#define ADI_SPI0_CFG_CONTINUOUS                     (0u)
+
+/*! SPI0 Rx FIFO flush enable\n
+    SPI configuration register: Bit[12]\n
+    1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n
+    0 - Rx FIFO flush is disabled. */
+#define ADI_SPI0_CFG_RX_FLUSH                       (0u)
+
+
+/*! SPI0 Tx FIFO flush enable\n
+    SPI configuration register: Bit[13]\n
+    1 - Tx FIFO is flushed.\n
+    0 - Tx FIFO flush is disabled. */
+#define ADI_SPI0_CFG_TX_FLUSH                       (0u)
+
+
+/*! Reset Mode for CSERR.       \n
+    SPI0 configuration register: Bit[14]\n
+    0 -  To  continue from where it stopped. SPI can receive the remaining bits
+         when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n
+    1 -  To enable resetting the bit counter and  reset if there is  a
+         CS error condition and the Cortex is expected to clear the SPI_EN bit.
+*/
+#define ADI_SPI0_CFG_CSERR_RESET                       (0u)
+
+
+/*! SPI0 clock divide\n
+    SPI baud rate selection register: Bit[0:5]\n
+    Value between 0-63 that is used to divide the UCLK to generate
+    the SPI serial clock. */
+#define ADI_SPI0_CFG_CLK_DIV                        (0u)
+
+
+/*! SPI0 high frequency mode\n
+    SPI baud rate selection register: Bit[6]\n
+    1 - High frequency mode enabled.\n
+    0 - High frequency mode disabled. */
+#define ADI_SPI0_CFG_HFM                            (0u)
+
+
+/*! SPI0 reset mode for CSERR\n
+    SPI baud rate selection register: Bit[7]\n
+    1 - clear bit counter on CS error.\n
+    0 - do not clear bit counter on CS error. */
+#define ADI_SPI0_CFG_CS_ERR                         (0u)
+
+
+/*! SPI0 CS interrupt\n
+    SPI baud rate selection register: Bit[8]\n
+    1 - In continuous mode, generate interrupt on CS.\n
+    0 - In continuous mode, do not generate interrupt on CS. */
+#define ADI_SPI0_CFG_CS_IRQ                         (0u)
+
+
+/*! @} */
+
+/*----------------------------------------------------------*/
+/* -------------------- SPI1 -------------------------------*/
+/*----------------------------------------------------------*/
+
+/** @addtogroup SPI_Driver_Config_SPI1 SPI1 Static Configuration
+ *  @ingroup SPI_Driver_Config
+ *  @{
+ */
+
+ /*! If using SPI1 in master mode set this macro to 1. For slave mode set this macro to 0. */
+#define ADI_SPI1_MASTER_MODE               (1u)
+ 
+/*! Set this macro to the SPI1 bit rate in hertz */
+#define ADI_SPI1_CFG_BIT_RATE               (2000000u)
+
+/*! SPI1 enable\n
+    SPI configuration register: Bit[0]\n
+    1 -  Enable SPI\n
+    0 -  Disable SPI */
+#define ADI_SPI1_CFG_ENABLE                         (0u)
+
+/*! SPI1 clock phase mode\n
+    SPI configuration register: Bit[2]\n
+    1 - Serial clock pulses at the beginning of each serial bit transfer.\n
+    0 - Serial clock pulses at the end of each serial bit transfer. */
+#define ADI_SPI1_CFG_CLK_PHASE                      (0u)
+
+
+
+
+
+/*! SPI1 clock polarity\n
+    SPI configuration register: Bit[3]\n
+    1 - Serial clock idles high.\n
+    0 - Serial clock idles low. */
+#define ADI_SPI1_CFG_CLK_POLARITY                   (0u)
+
+
+/*! SPI1 wired OR mode\n
+    SPI configuration register: Bit[4]\n
+    1 - Enables open circuit output enable.\n
+    0 - Normal output levels. */
+#define ADI_SPI1_CFG_WIRED_OR                       (0u)
+
+
+/*! SPI1 LSB/MSB\n
+    SPI configuration register: Bit[5]\n
+    1 - MSB transmitted first.\n
+    0 - LSB transmitted first. */
+#define ADI_SPI1_CFG_LSB_MSB                        (0u)
+
+
+/*! SPI1 transfer initiate\n
+    SPI configuration register: Bit[6]\n
+    1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n
+    0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/
+#define ADI_SPI1_CFG_TRANSFER_INITIATE              (0u)
+
+
+/*! SPI1 Tx FIFO transfers zeros or last bit upon underflow\n
+    SPI configuration register: Bit[7]\n
+    1 - Tx FIFO sends zeros upon underflow.\n
+    0 - Tx FIFO repeats last bit upon underflow. */
+#define ADI_SPI1_CFG_TX_UNDERFLOW                   (0u)
+
+
+/*! SPI1 Rx FIFO overflows with received data or data is discarded\n
+    SPI configuration register: Bit[8]\n
+    1 - Rx FIFO receives data upon overflow.\n
+    0 - Rx FIFO discards received data upon overflow. */
+#define ADI_SPI1_CFG_RX_OVERFLOW                    (0u)
+
+
+/*! SPI1 slave mode MISO enable\n
+    SPI configuration register: Bit[9]\n
+    1 - MISO operates as normal in slave mode.\n
+    0 - MISO is disabled in slave mode. */
+#define ADI_SPI1_CFG_MISO_ENABLE                    (0u)
+
+
+/*! SPI1 internal loopback enable\n
+    SPI configuration register: Bit[10]\n
+    1 - MISO and MOSI is loopbacked internally.\n
+    0 - MISO and MOSI operates normally. */
+#define ADI_SPI1_CFG_LOOPBACK                       (0u)
+
+/*! SPI1 transfer and interrupt mode\n
+    SPI configuration register: Bit[11]\n
+    1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n
+    0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/
+#define ADI_SPI1_CFG_CONTINUOUS                     (0u)
+
+/*! SPI1 Rx FIFO flush enable\n
+    SPI configuration register: Bit[12]\n
+    1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n
+    0 - Rx FIFO flush is disabled. */
+#define ADI_SPI1_CFG_RX_FLUSH                       (0u)
+
+
+/*! SPI1 Tx FIFO flush enable\n
+    SPI configuration register: Bit[13]\n
+    1 - Tx FIFO is flushed.\n
+    0 - Tx FIFO flush is disabled. */
+#define ADI_SPI1_CFG_TX_FLUSH                       (0u)
+
+
+/*! Reset Mode for CSERR.       \n
+    SPI1 configuration register: Bit[14]\n
+    0 -  To  continue from where it stopped. SPI can receive the remaining bits
+         when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n
+    1 -  To enable resetting the bit counter and  reset if there is  a
+         CS error condition and the Cortex is expected to clear the SPI_EN bit.
+*/
+#define ADI_SPI1_CFG_CSERR_RESET                       (0u)
+
+
+/*! SPI1 clock divide\n
+    SPI baud rate selection register: Bit[0:5]\n
+    Value between 0-63 that is used to divide the UCLK to generate
+    the SPI serial clock. */
+#define ADI_SPI1_CFG_CLK_DIV                        (0u)
+
+
+/*! SPI1 high frequency mode\n
+    SPI baud rate selection register: Bit[6]\n
+    1 - High frequency mode enabled.\n
+    0 - High frequency mode disabled. */
+#define ADI_SPI1_CFG_HFM                            (0u)
+
+
+/*! SPI1 reset mode for CSERR\n
+    SPI baud rate selection register: Bit[7]\n
+    1 - clear bit counter on CS error.\n
+    0 - do not clear bit counter on CS error. */
+#define ADI_SPI1_CFG_CS_ERR                         (0u)
+
+
+/*! SPI1 CS interrupt\n
+    SPI baud rate selection register: Bit[8]\n
+    1 - In continuous mode, generate interrupt on CS.\n
+    0 - In continuous mode, do not generate interrupt on CS. */
+#define ADI_SPI1_CFG_CS_IRQ  
+
+/*! @} */
+
+/*----------------------------------------------------------*/
+/* -------------------- SPI2 -------------------------------*/
+/*----------------------------------------------------------*/
+
+/** @addtogroup SPI_Driver_Config_SPI2 SPI2 Static Configuration
+ *  @ingroup SP2_Driver_Config
+ *  @{
+ */
+
+/*! If using SPI2 in master mode set this macro to 1. For slave mode set this macro to 0. */
+#define ADI_SPI2_MASTER_MODE               (1u)
+
+/*! Set this macro to the SPI2 bit rate in hertz */
+#define ADI_SPI2_CFG_BIT_RATE               (2000000u)
+
+/*! SPI2 enable\n
+    SPI configuration register: Bit[0]\n
+    1 -  Enable SPI\n
+    0 -  Disable SPI */
+#define ADI_SPI2_CFG_ENABLE                         (0u)
+
+/*! SPI2 clock phase mode\n
+    SPI configuration register: Bit[2]\n
+    1 - Serial clock pulses at the beginning of each serial bit transfer.\n
+    0 - Serial clock pulses at the end of each serial bit transfer. */
+#define ADI_SPI2_CFG_CLK_PHASE                      (0u)
+
+
+
+
+
+/*! SPI2 clock polarity\n
+    SPI configuration register: Bit[3]\n
+    1 - Serial clock idles high.\n
+    0 - Serial clock idles low. */
+#define ADI_SPI2_CFG_CLK_POLARITY                   (0u)
+
+
+/*! SPI2 wired OR mode\n
+    SPI configuration register: Bit[4]\n
+    1 - Enables open circuit output enable.\n
+    0 - Normal output levels. */
+#define ADI_SPI2_CFG_WIRED_OR                       (0u)
+
+
+/*! SPI2 LSB/MSB\n
+    SPI configuration register: Bit[5]\n
+    1 - MSB transmitted first.\n
+    0 - LSB transmitted first. */
+#define ADI_SPI2_CFG_LSB_MSB                        (0u)
+
+
+/*! SPI2 transfer initiate\n
+    SPI configuration register: Bit[6]\n
+    1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n
+    0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/
+#define ADI_SPI2_CFG_TRANSFER_INITIATE              (0u)
+
+
+/*! SPI2 Tx FIFO transfers zeros or last bit upon underflow\n
+    SPI configuration register: Bit[7]\n
+    1 - Tx FIFO sends zeros upon underflow.\n
+    0 - Tx FIFO repeats last bit upon underflow. */
+#define ADI_SPI2_CFG_TX_UNDERFLOW                   (0u)
+
+
+/*! SPI2 Rx FIFO overflows with received data or data is discarded\n
+    SPI configuration register: Bit[8]\n
+    1 - Rx FIFO receives data upon overflow.\n
+    0 - Rx FIFO discards received data upon overflow. */
+#define ADI_SPI2_CFG_RX_OVERFLOW                    (0u)
+
+
+/*! SPI2 slave mode MISO enable\n
+    SPI configuration register: Bit[9]\n
+    1 - MISO operates as normal in slave mode.\n
+    0 - MISO is disabled in slave mode. */
+#define ADI_SPI2_CFG_MISO_ENABLE                    (0u)
+
+
+/*! SPI2 internal loopback enable\n
+    SPI configuration register: Bit[10]\n
+    1 - MISO and MOSI is loopbacked internally.\n
+    0 - MISO and MOSI operates normally. */
+#define ADI_SPI2_CFG_LOOPBACK                       (0u)
+
+/*! SPI2 transfer and interrupt mode\n
+    SPI configuration register: Bit[11]\n
+    1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n
+    0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/
+#define ADI_SPI2_CFG_CONTINUOUS                     (0u)
+
+/*! SPI2 Rx FIFO flush enable\n
+    SPI configuration register: Bit[12]\n
+    1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n
+    0 - Rx FIFO flush is disabled. */
+#define ADI_SPI2_CFG_RX_FLUSH                       (0u)
+
+
+/*! SPI2 Tx FIFO flush enable\n
+    SPI configuration register: Bit[13]\n
+    1 - Tx FIFO is flushed.\n
+    0 - Tx FIFO flush is disabled. */
+#define ADI_SPI2_CFG_TX_FLUSH                       (0u)
+
+
+/*! Reset Mode for CSERR.       \n
+    SPI2 configuration register: Bit[14]\n
+    0 -  To  continue from where it stopped. SPI can receive the remaining bits
+         when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n
+    1 -  To enable resetting the bit counter and  reset if there is  a
+         CS error condition and the Cortex is expected to clear the SPI_EN bit.
+*/
+#define ADI_SPI2_CFG_CSERR_RESET                       (0u)
+
+
+/*! SPI2 clock divide\n
+    SPI baud rate selection register: Bit[0:5]\n
+    Value between 0-63 that is used to divide the UCLK to generate
+    the SPI serial clock. */
+#define ADI_SPI2_CFG_CLK_DIV                        (0u)
+
+
+/*! SPI2 high frequency mode\n
+    SPI baud rate selection register: Bit[6]\n
+    1 - High frequency mode enabled.\n
+    0 - High frequency mode disabled. */
+#define ADI_SPI2_CFG_HFM                            (0u)
+
+
+/*! SPI2 reset mode for CSERR\n
+    SPI baud rate selection register: Bit[7]\n
+    1 - clear bit counter on CS error.\n
+    0 - do not clear bit counter on CS error. */
+#define ADI_SPI2_CFG_CS_ERR                         (0u)
+
+
+/*! SPI2 CS interrupt\n
+    SPI baud rate selection register: Bit[8]\n
+    1 - In continuous mode, generate interrupt on CS.\n
+    0 - In continuous mode, do not generate interrupt on CS. */
+#define ADI_SPI2_CFG_CS_IRQ  
+
+/*! @} */
+
+/************** Macro validation *****************************/
+
+#if ( ADI_SPI0_CFG_BIT_RATE > (13000000u) ) || \
+    ( ADI_SPI0_CFG_BIT_RATE > (13000000u) ) || \
+    ( ADI_SPI0_CFG_BIT_RATE > (13000000u) )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_ENABLE > 1u ) || \
+    ( ADI_SPI1_CFG_ENABLE > 1u ) || \
+    ( ADI_SPI2_CFG_ENABLE > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_CLK_PHASE > 1u ) || \
+    ( ADI_SPI1_CFG_CLK_PHASE > 1u ) || \
+    ( ADI_SPI2_CFG_CLK_PHASE > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_CLK_POLARITY > 1u ) || \
+    ( ADI_SPI1_CFG_CLK_POLARITY > 1u ) || \
+    ( ADI_SPI2_CFG_CLK_POLARITY > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_WIRED_OR > 1u ) || \
+    ( ADI_SPI1_CFG_WIRED_OR > 1u ) || \
+    ( ADI_SPI2_CFG_WIRED_OR > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_LSB_MSB > 1u ) || \
+    ( ADI_SPI1_CFG_LSB_MSB > 1u ) || \
+    ( ADI_SPI2_CFG_LSB_MSB > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_TRANSFER_INITIATE > 1u ) || \
+    ( ADI_SPI1_CFG_TRANSFER_INITIATE > 1u ) || \
+    ( ADI_SPI2_CFG_TRANSFER_INITIATE > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_TX_UNDERFLOW > 1u ) || \
+    ( ADI_SPI1_CFG_TX_UNDERFLOW > 1u ) || \
+    ( ADI_SPI2_CFG_TX_UNDERFLOW > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_RX_OVERFLOW > 1u ) || \
+    ( ADI_SPI1_CFG_RX_OVERFLOW > 1u ) || \
+    ( ADI_SPI2_CFG_RX_OVERFLOW > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_MISO_ENABLE > 1u ) || \
+    ( ADI_SPI1_CFG_MISO_ENABLE > 1u ) || \
+    ( ADI_SPI2_CFG_MISO_ENABLE > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_LOOPBACK > 1u ) || \
+    ( ADI_SPI1_CFG_LOOPBACK > 1u ) || \
+    ( ADI_SPI2_CFG_LOOPBACK > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_CONTINUOUS > 1u ) || \
+    ( ADI_SPI1_CFG_CONTINUOUS > 1u ) || \
+    ( ADI_SPI2_CFG_CONTINUOUS > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_RX_FLUSH > 1u ) || \
+    ( ADI_SPI1_CFG_RX_FLUSH > 1u ) || \
+    ( ADI_SPI2_CFG_RX_FLUSH > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_TX_FLUSH > 1u ) || \
+    ( ADI_SPI1_CFG_TX_FLUSH > 1u ) || \
+    ( ADI_SPI2_CFG_TX_FLUSH > 1u )
+#error "Invalid configuration"
+#endif
+
+
+/*! @} */
+
+#endif /* ADI_SPI_CONFIG_H__ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_sport_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_sport_config.h
new file mode 100755
index 00000000000..db0fdb6636a
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_sport_config.h
@@ -0,0 +1,355 @@
+/*! ****************************************************************************
+ * @file    adi_sport_config.h
+ * @brief   Configuration options for SPORT driver.
+ * @details This is specific to the SPORT driver and will be included by the
+ *          driver. It is not required for the application to include this
+ *          header file.
+  -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef ADI_SPORT_CONFIG_H
+#define ADI_SPORT_CONFIG_H
+#include <adi_global_config.h>
+
+/** @addtogroup SPORT_Driver_Config Static Configuration
+ *  @ingroup SPORT_Driver
+ *  @{
+ */
+
+/************* SPORT Driver configurations FOR SPORT-0-A ***************/
+/*!
+   Frame Sync Multiplexer Select.\n
+   0 - Disable frame sync multiplexing\n
+   1 - Enable frame sync multiplexing.
+*/
+#define ADI_CFG_SPORT0A_ENABLE_FSMUXSEL             (0u)
+
+/*!
+   Clock Multiplexer Select.\n
+   0 - Disable serial clock multiplexing\n
+   1 - Enable serial clock multiplexing.
+*/
+#define ADI_CFG_SPORT0A_ENABLE_CKMUXSEL             (1u)
+
+/*!
+   Least-Significant Bit First.\n
+   0 - MSB first sent/received.\n
+   1 - LSB first sent/received.
+*/
+#define ADI_CFG_SPORT0A_LSB_FIRST                   (0u)
+
+
+/*!
+   Serial Word Length in bits.\n
+   1 - 32 - SPORT word length
+*/
+#define ADI_CFG_SPORT0A_SERIAL_WLEN                 (32u)
+
+
+/*!
+   Internal Clock.\n
+   0 - External clock.\n
+   1 - Internal clock.
+*/
+#define ADI_CFG_SPORT0A_INTERNAL_CLK                (1u)
+
+/*!
+   Operation Mode\n
+   0 - DSP standard.\n
+   1 - Timer_enable mode.
+*/
+#define ADI_CFG_SPORT0A_OPERATION_MODE              (0u)
+
+
+/*!
+   Clock Rising Edge\n
+   0 - Clock falling edge\n
+   1 - Clock rising edge.
+*/
+#define ADI_CFG_SPORT0A_CLOCK_EDGE                  (0u)
+
+/*!
+   Frame Sync Required\n
+   0 - No frame sync required \n
+   1 - Frame sync required.
+*/
+#define ADI_CFG_SPORT0A_FS_REQUIRED                 (1u)
+
+/*!
+   Internal Frame Sync\n
+   0 - External frame sync\n
+   1 - Internal frame sync
+*/
+#define ADI_CFG_SPORT0A_INTERNAL_FS                 (0u)
+
+
+/*!
+   Data-Independent Frame Sync\n
+   0 - Data-dependent frame sync\n
+   1 - Data-independent frame 
+*/
+#define ADI_CFG_SPORT0A_DATA_INDEPENDENT_FS         (0u)
+
+/*!
+   Active-Low Frame Sync\n
+   0 - Active high frame sync\n
+   1 - Active low frame sync 
+*/
+#define ADI_CFG_SPORT0A_ACTIVE_LOW_FS               (0u)
+
+/*!
+   Late Frame Sync\n
+   0 - Early frame sync\n
+   1 - Late frame sync
+*/
+#define ADI_CFG_SPORT0A_LATE_FS                     (0u)
+
+/*!
+   Enable Packing \n
+   0 - Disable\n
+   1 - 8-bit packing enable\n
+   2 - 16-bit packing enable
+*/
+#define ADI_CFG_SPORT0A_ENABLE_PACKING              (0u)
+
+/*!
+   Frame Sync Error Operation
+   0 - Flag the Frame Sync error\n
+   1 - When frame Sync error occurs, discard the receive data
+*/
+#define ADI_CFG_SPORT0A_FS_ERROR_OPERATION          (1u)
+
+/*!
+   Enabling Gated Clock\n
+   0 - Disable Gated Clock\n
+   1 - Enable Gated Clock
+*/
+#define ADI_CFG_SPORT0A_GATED_CLOCK                 (0u)
+
+/*!
+   Serial Clock divisor.\n
+   0 - 65535 -   Serial Clock Divisor which  SPORT device use to  calculate the serial 
+                 clock (ACLK) from the processor system clock (PCLK).
+*/
+#define ADI_CFG_SPORT0A_CLOCK_DIVISOR               (2u)
+
+/*!
+   Frame Sync Divisor.\n
+   0 - 128 -    Frame Sync Divisor which select the number of transmit or receive clock
+                cycles that the half SPORT counts before generating a frame sync pulse.
+*/
+#define ADI_CFG_SPORT0A_FS_DIVISOR                  (0x40u)
+
+
+/*!
+   CONVT to FS duration.\n
+   0 - 128 -    Specify the value of the number of clocks which would be programmed 
+                corresponding to the desired time duration from assertion of CONVT 
+                signal to Frame sync signal
+*/
+#define ADI_CFG_SPORT0A_CONVT_FS_DURATION           (1u)
+
+/*!
+   Polarity of the Convt signal.\n
+   0 - Active High Polarity\n
+   1 - Active low Polarity
+*/
+#define ADI_CFG_SPORT0A_CONVT_POLARITY              (0u)
+
+/*!
+   CONVT signal width.\n
+   0 - 15 -     Specify the value of the number of serial clocks for which CONVT
+                signal should be active
+   
+*/
+#define ADI_CFG_SPORT0A_CONVT_WIDTH                 (1u)
+
+#if defined(ADI_CFG_SPORT0A_SERIAL_WLEN)
+#if (ADI_CFG_SPORT0A_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0A_SERIAL_WLEN > 32u)
+#error "Invalid word length : it must be between 4 and 32"
+#endif
+#else
+#error "ADI_CFG_SPORT0A_SERIAL_WLEN undefined!!! "
+#endif
+
+/************* SPORT Driver configurations FOR SPORT-0-B ***************/
+/*!
+   Least-Significant Bit First.\n
+   0 - MSB first sent/received.\n
+   1 - LSB first sent/received.
+*/
+#define ADI_CFG_SPORT0B_LSB_FIRST                   (0u)
+
+
+/*!
+   Serial Word Length in bits.\n
+   1 - 32 - SPORT word length
+*/
+#define ADI_CFG_SPORT0B_SERIAL_WLEN                 (32u)
+
+
+/*!
+   Internal Clock.\n
+   0 - External clock.\n
+   1 - Internal clock.
+*/
+#define ADI_CFG_SPORT0B_INTERNAL_CLK                (1u)
+
+/*!
+   Operation Mode\n
+   0 - DSP standard.\n
+   1 - Timer_enable mode.
+*/
+#define ADI_CFG_SPORT0B_OPERATION_MODE              (0u)
+
+
+/*!
+   Clock Rising Edge\n
+   0 - Clock falling edge\n
+   1 - Clock rising edge.
+*/
+#define ADI_CFG_SPORT0B_CLOCK_EDGE                  (0u)
+
+/*!
+   Frame Sync Required\n
+   0 - No frame sync required \n
+   1 - Frame sync required.
+*/
+#define ADI_CFG_SPORT0B_FS_REQUIRED                 (1u)
+
+/*!
+   Internal Frame Sync\n
+   0 - External frame sync\n
+   1 - Internal frame sync
+*/
+#define ADI_CFG_SPORT0B_INTERNAL_FS                 (1u)
+
+
+/*!
+   Data-Independent Frame Sync\n
+   0 - Data-dependent frame sync\n
+   1 - Data-independent frame 
+*/
+#define ADI_CFG_SPORT0B_DATA_INDEPENDENT_FS         (0u)
+
+/*!
+   Active-Low Frame Sync\n
+   0 - Active high frame sync\n
+   1 - Active low frame sync 
+*/
+#define ADI_CFG_SPORT0B_ACTIVE_LOW_FS               (0u)
+
+/*!
+   Late Frame Sync\n
+   0 - Early frame sync\n
+   1 - Late frame sync
+*/
+#define ADI_CFG_SPORT0B_LATE_FS                     (0u)
+
+/*!
+   Enable Packing \n
+   0 - Disable\n
+   1 - 8-bit packing enable\n
+   2 - 16-bit packing enable\n
+*/
+#define ADI_CFG_SPORT0B_ENABLE_PACKING              (0u)
+
+/*!
+   Frame Sync Error Operation\n
+   0 - Flag the Frame Sync error\n
+   1 - When frame Sync error occurs, discard the receive data
+*/
+#define ADI_CFG_SPORT0B_FS_ERROR_OPERATION          (1u)
+
+/*!
+   Enabling Gated Clock\n
+   0 - Disable Gated Clock\n
+   1 - Enable Gated Clock
+*/
+#define ADI_CFG_SPORT0B_GATED_CLOCK                 (0u)
+
+/*!
+   Serial Clock divisor.\n
+   0 - 65535 -   Serial Clock Divisor which SPORT device use to calculate the serial 
+                 clock (ACLK) from the processor system clock (PCLK).
+*/
+#define ADI_CFG_SPORT0B_CLOCK_DIVISOR               (2u)
+
+/*!
+   Frame Sync Divisor.\n
+   0 - 128 -    Frame Sync Divisor which select the number of transmit or receive clock
+                cycles that the half SPORT counts before generating a frame sync pulse.
+*/
+#define ADI_CFG_SPORT0B_FS_DIVISOR                  (0x40u)
+
+
+/*!
+   CONVT to FS duration.\n
+   0 - 128 -    Specify the value of the number of clocks which would be programmed 
+                corresponding to the desired time duration from assertion of CONVT 
+                signal to Frame sync signal
+*/
+#define ADI_CFG_SPORT0B_CONVT_FS_DURATION           (1u)
+
+/*!
+   Polarity of the Convt signal.\n
+   0 - Active High Polarity\n
+   1 - Active low Polarity
+*/
+#define ADI_CFG_SPORT0B_CONVT_POLARITY              (0u)
+
+/*!
+   CONVT signal width.\n
+   0-15 -       Specify the value of the number of serial clocks for which CONVT
+                signal should be active
+   
+*/
+#define ADI_CFG_SPORT0B_CONVT_WIDTH                 (1u)
+
+#if defined(ADI_CFG_SPORT0B_SERIAL_WLEN)
+#if (ADI_CFG_SPORT0B_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0B_SERIAL_WLEN > 32u)
+#error "Invalid word length : it must be between 4 and 32"
+#endif
+#else
+#error "ADI_CFG_SPORT0B_SERIAL_WLEN undefined!!! "
+#endif
+
+/*! @} */
+
+#endif /* ADI_SPORT_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_tmr_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_tmr_config.h
new file mode 100755
index 00000000000..f03ff59484f
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_tmr_config.h
@@ -0,0 +1,942 @@
+/*! *****************************************************************************
+ * @file    adi_tmr_config.h
+ * @brief   GP and RGB timer device driver configuration
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+
+#ifndef ADI_TMR_CONFIG_H
+#define ADI_TMR_CONFIG_H
+
+#include <adi_processor.h>
+#include <adi_global_config.h>
+
+/** @addtogroup TMR_Driver_Config Static Configuration
+ *  @ingroup TMR_Driver
+ *  @{
+ */
+
+
+/*! Static configuration allows all 3 GP timers and the RGB timer to be configured
+    with the parameters in this file by simply calling #adi_tmr_Init. The user can
+    then call any of the configuration API's to override the static configuration,
+    or simply call #adi_tmr_Enable to start the timer. Since all of these parameters
+    must be stored in arrays for abstraction, using static configuration will increase the 
+    data footprint. If the user doesn't call any of the runtime configuration API's, the
+    linker will throw them out and the code footprint will be reduced significantly. Using
+    static configuration also reduces cycle count and simplifies the user application. 
+    Static configuration should be used if the timers need to be configured once and do not 
+    need to be changed during the system lifetime.
+
+    0 - Disable static confiscation support. User must call #adi_tmr_ConfigTimer and other
+        configuration API's after calling #adi_tmr_Init and prior to calling #adi_tmr_Enable
+        in order to set up the timer.
+
+    1 - Enable static configuration support. The timer registers will be set based on the 
+        settings in this file when #adi_tmr_Init is called.
+*/
+
+
+/*************************************************************
+                        GP Timer 0 Configuration
+ *************************************************************/
+
+ /** @addtogroup GPTimer0_Driver_Config GP Timer 0 Static Configuration
+ *  @ingroup TMR_Driver_Config
+ *  @{
+ */
+
+ 
+/*! Count up or down. Used to control whether the timer increments (counts up)
+    or decrements (counts down) the Up/Down counter, it can be set to\n
+    0 -  Timer is set to count down.\n
+    1 -  Timer is set to count up.
+*/
+#define TMR0_CFG_COUNT_UP                               (0u)
+
+/*! Timer mode. Used to control whether the timer runs in periodic or
+    free running mode, it can be set to\n
+    0 -  Timer is in free running mode.\n
+    1 -  Timer is in periodic mode.
+*/
+#define TMR0_CFG_MODE                                   (1u)
+
+/*! Prescale factor. Controls the prescaler division factor
+    to the timer's selected clock. It can be set to\n
+
+    0 - source_clock/[1 or 4]\n
+    1 - source_clock/16\n
+    2 - source_clock/64\n
+    3 - source_clock/256
+*/
+#define TMR0_CFG_PRESCALE_FACTOR                        (0u)
+
+/*! Timer clock source. Used to select a timer clock from the four
+    available clock sources, it can be set to\n
+    0 - Select PCLK\n
+    1 - Select HFOSC\n
+    2 - Select LFOSC\n
+    3 - Select LFXTAL
+*/
+#define TMR0_CFG_CLOCK_SOURCE                           (0u)
+
+/*! Timer load value. The Up/Down counter is periodically loaded with this
+    value if periodic mode is selected. LOAD writes during Up/Down counter timeout events
+    are delayed until the event has passed. It can be set to any value from 0 to 65535.
+
+*/
+#define TMR0_CFG_LOAD_VALUE                             (0x8F9Cu)
+
+/*! Timer asynchrounous load value. The Up/Down counter is periodically loaded with
+    this value if periodic mode is selected. Writing Asynchronous Load value takes
+    advantage of having the timer run on PCLK by bypassing clock synchronization
+    logic otherwise required. It can be set to any value from 0 to 65535.
+
+*/
+#define TMR0_CFG_ASYNC_LOAD_VALUE                       (0x8F9Cu)
+
+/*! Reload control. This allows the user to select whether the Up/Down counter should be
+    reset only on a timeout event or also when interrupt is cleared. It can be set to\n
+    0 - Up/down counter is only reset on a time out event.\n
+    1 - Resets the up/down counter when the interrupt is cleared.
+*/
+#define TMR0_CFG_ENABLE_RELOADING                       (0u)
+
+/*! Enable or disable Synchronization bypass\n
+    0 - Disable Synchronization bypass.\n
+    1 - Enable Synchronization bypass.
+*/
+#define TMR0_CFG_ENABLE_SYNC_BYPASS                     (0u)
+
+/*************************************************************
+                        GP Timer 0 Event Configuration
+ *************************************************************/
+
+/*! Enable or disable event capture. It can be set to\n
+    0 - Disable event capturing.\n
+    1 - Enable event capturing.
+*/
+#define TMR0_CFG_ENABLE_EVENT_CAPTURE                   (1u)
+
+/*! Enable or disable prescale reset\n
+    0 - Disable rescale reset.\n
+    1 - Enable rescale reset.
+*/
+#define TMR0_CFG_ENABLE_PRESCALE_RESET                  (0u)    
+
+/*! Event to be captured. One of the selected 40 events associated
+    with a general purpose time can be captured. It can be set to
+    a value of 0 - 39. Please refer hardware reference manual to know
+    which events can be captured by a particular GP timer.
+*/
+#if defined(__ADUCM302x__)
+#define TMR0_CFG_EVENT_CAPTURE                          (9u)
+#elif defined(__ADUCM4x50__)
+#define TMR0_CFG_EVENT_CAPTURE                          (27u)
+#else
+#error TMR is not ported for this processor
+#endif
+
+/*************************************************************
+                        GP Timer 0 PWM0 Configuration
+ *************************************************************/
+
+/*! Timer PWM Enable Match. This will control PWM operation mode of the timer.
+    Toggle mode provides a 50% duty cycle and match mode provides a configurable
+    duty cycle by using the match value. This vlaue can be set to\n
+    0 - PWM in toggle mode.\n
+    1 - PWM in match mode.
+*/
+#define TMR0_CFG_ENABLE_PWM0_MATCH_MODE                 (1u)
+
+
+/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n
+    0 - PWM idles low.\n
+    1 - PWM idles high.
+*/
+#define TMR0_CFG_PWM0_IDLE_STATE                        (1u)
+
+
+/*! PWM Match value. The value is used when the PWM is operating in match mode.
+    The PWM output is asserted when the Up/Down counter is equal to this match value.
+    PWM output is deasserted again when a timeout event occurs.
+    If the match value is never reached, or occurs simultaneous to a timeout event,
+    the PWM output remains idle. It can be any value from 0 to 65535.
+*/
+#define TMR0_CFG_PWM0_MATCH_VALUE                       (0x0E5Cu)
+
+/*! @} */
+
+
+/*************************************************************
+                        GP Timer 1 Configuration
+ *************************************************************/
+
+ /** @addtogroup GPTimer1_Driver_Config GP Timer 1 Static Configuration
+ *  @ingroup TMR_Driver_Config
+ *  @{
+ */
+
+ 
+/*! Count up or down. Used to control whether the timer increments (counts up)
+    or decrements (counts down) the Up/Down counter, it can be set to\n
+    0 -  Timer is set to count down.\n
+    1 -  Timer is set to count up.
+*/
+#define TMR1_CFG_COUNT_UP                               (0u)
+
+/*! Timer mode. Used to control whether the timer runs in periodic or
+    free running mode, it can be set to\n
+    0 -  Timer is in free running mode.\n
+    1 -  Timer is in periodic mode.
+*/
+#define TMR1_CFG_MODE                                   (1u)
+
+/*! Prescale factor. Controls the prescaler division factor
+    to the timer's selected clock. It can be set to\n
+
+    0 - source_clock/[1 or 4]\n
+    1 - source_clock/16\n
+    2 - source_clock/64\n
+    3 - source_clock/256
+*/
+#define TMR1_CFG_PRESCALE_FACTOR                        (0u)
+
+/*! Timer clock source. Used to select a timer clock from the four
+    available clock sources, it can be set to\n
+    0 - Select PCLK\n
+    1 - Select HFOSC\n
+    2 - Select LFOSC\n
+    3 - Select LFXTAL
+*/
+#define TMR1_CFG_CLOCK_SOURCE                           (0u)
+
+/*! Timer load value. The Up/Down counter is periodically loaded with this
+    value if periodic mode is selected. LOAD writes during Up/Down counter timeout events
+    are delayed until the event has passed. It can be set to any value from 0 to 65535.
+
+*/
+#define TMR1_CFG_LOAD_VALUE                             (0x23E7u)
+
+/*! Timer asynchronous load value. The Up/Down counter is periodically loaded with
+    this value if periodic mode is selected. Writing Asynchronous Load value takes
+    advantage of having the timer run on PCLK by bypassing clock synchronization
+    logic otherwise required. It can be set to any value from 0 to 65535.
+
+*/
+#define TMR1_CFG_ASYNC_LOAD_VALUE                       (0x23E7u)
+
+/*! Reload control. This allows the user to select whether the Up/Down counter should be
+    reset only on a timeout event or also when interrupt is cleared. It can be set to\n
+    0 - Up/down counter is only reset on a time out event.\n
+    1 - Resets the up/down counter when the interrupt is cleared.
+*/
+#define TMR1_CFG_ENABLE_RELOADING                       (0u)
+
+/*! Enable or disable Synchronization bypass\n
+    0 - Disable Synchronization bypass.\n
+    1 - Enable Synchronization bypass.
+*/
+#define TMR1_CFG_ENABLE_SYNC_BYPASS                     (0u)
+
+
+/*************************************************************
+                        GP Timer 1 Event Configuration
+ *************************************************************/
+ 
+/*! Enable or disable event capture. It can be set to\n
+    0 - Disable event capturing.\n
+    1 - Enable event capturing.
+*/
+#define TMR1_CFG_ENABLE_EVENT_CAPTURE                   (1u)
+
+/*! Enable or disable prescale reset\n
+    0 - Disable rescale reset.\n
+    1 - Enable rescale reset.
+*/
+#define TMR1_CFG_ENABLE_PRESCALE_RESET                  (0u)
+
+/*! Event to be captured. One of the selected 40 events associated
+    with a general purpose time can be captured. It can be set to
+    a value of 0 - 39. Please refer hardware reference manual to know
+    which events can be captured by a particular GP timer.
+*/
+#if defined(__ADUCM302x__)
+#define TMR1_CFG_EVENT_CAPTURE                          (15u)
+#elif defined(__ADUCM4x50__)
+#define TMR1_CFG_EVENT_CAPTURE                          (28u)
+#else
+#error TMR is not ported for this processor
+#endif
+/*************************************************************
+                        GP Timer 1 PWM0 Configuration
+ *************************************************************/
+
+/*! Timer PWM Enable Match. This will control PWM operation mode of the timer.
+    Toggle mode provides a 50% duty cycle and match mode provides a configurable
+    duty cycle by using the match value. This value can be set to\n
+    0 - PWM in toggle mode.\n
+    1 - PWM in match mode.
+*/
+#define TMR1_CFG_ENABLE_PWM0_MATCH_MODE                 (1u)
+
+
+/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n
+    0 - PWM idles low.\n
+    1 - PWM idles high.
+*/
+#define TMR1_CFG_PWM0_IDLE_STATE                        (1u)
+
+
+/*! PWM Match value. The value is used when the PWM is operating in match mode.
+    The PWM output is asserted when the Up/Down counter is equal to this match value.
+    PWM output is deasserted again when a timeout event occurs.
+    If the match value is never reached, or occurs simultaneous to a timeout event,
+    the PWM output remains idle. It can be any value from 0 to 65535.
+*/
+#define TMR1_CFG_PWM0_MATCH_VALUE                       (0x08F9u)
+
+/*! @} */
+
+/*************************************************************
+                        GP Timer 2 Configuration
+ *************************************************************/
+
+ /** @addtogroup GPTimer2_Driver_Config GP Timer 2 Static Configuration
+ *  @ingroup TMR_Driver_Config
+ *  @{
+ */
+
+ 
+/*! Count up or down. Used to control whether the timer increments (counts up)
+    or decrements (counts down) the Up/Down counter, it can be set to\n
+    0 -  Timer is set to count down.\n
+    1 -  Timer is set to count up.
+*/
+#define TMR2_CFG_COUNT_UP                               (0u)
+
+/*! Timer mode. Used to control whether the timer runs in periodic or
+    free running mode, it can be set to\n
+    0 -  Timer is in free running mode.\n
+    1 -  Timer is in periodic mode.
+*/
+#define TMR2_CFG_MODE                                   (1u)
+
+/*! Prescale factor. Controls the prescaler division factor
+    to the timer's selected clock. It can be set to\n
+
+    0 - source_clock/[1 or 4]\n
+    1 - source_clock/16\n
+    2 - source_clock/64\n
+    3 - source_clock/256
+*/
+#define TMR2_CFG_PRESCALE_FACTOR                        (0u)
+
+/*! Timer clock source. Used to select a timer clock from the four
+    available clock sources, it can be set to\n
+    0 - Select PCLK\n
+    1 - Select HFOSC\n
+    2 - Select LFOSC\n
+    3 - Select LFXTAL
+*/
+#define TMR2_CFG_CLOCK_SOURCE                           (0u)
+
+/*! Timer load value. The Up/Down counter is periodically loaded with this
+    value if periodic mode is selected. LOAD writes during Up/Down counter timeout events
+    are delayed until the event has passed. It can be set to any value from 0 to 65535.
+
+*/
+#define TMR2_CFG_LOAD_VALUE                             (0x0E5Cu)
+
+/*! Timer asynchronous load value. The Up/Down counter is periodically loaded with
+    this value if periodic mode is selected. Writing Asynchronous Load value takes
+    advantage of having the timer run on PCLK by bypassing clock synchronization
+    logic otherwise required. It can be set to any value from 0 to 65535.
+
+*/
+#define TMR2_CFG_ASYNC_LOAD_VALUE                       (0x0E5Cu)
+
+/*! Reload control. This allows the user to select whether the Up/Down counter should be
+    reset only on a timeout event or also when interrupt is cleared. It can be set to\n
+    0 - Up/down counter is only reset on a time out event.\n
+    1 - Resets the up/down counter when the interrupt is cleared.
+*/
+#define TMR2_CFG_ENABLE_RELOADING                       (0u)
+
+/*! Enable or disable Synchronization bypass\n
+    0 - Disable Synchronization bypass.\n
+    1 - Enable Synchronization bypass.
+*/
+#define TMR2_CFG_ENABLE_SYNC_BYPASS                     (0u)
+
+/*************************************************************
+                        GP Timer 2 Event Configuration
+ *************************************************************/
+
+/*! Enable or disable event capture. It can be set to\n
+    0 - Disable event capturing.\n
+    1 - Enable event capturing.
+*/
+#define TMR2_CFG_ENABLE_EVENT_CAPTURE                   (1u)
+
+/*! Enable or disable prescale reset\n
+    0 - Disable rescale reset.\n
+    1 - Enable rescale reset.
+*/
+#define TMR2_CFG_ENABLE_PRESCALE_RESET                  (0u)
+
+/*! Event to be captured. One of the selected 40 events associated
+    with a general purpose time can be captured. It can be set to
+    a value of 0 - 39. Please refer hardware reference manual to know
+    which events can be captured by a particular GP timer.
+*/
+#if defined(__ADUCM302x__)
+#define TMR2_CFG_EVENT_CAPTURE                          (6u)
+#elif defined(__ADUCM4x50__)
+#define TMR2_CFG_EVENT_CAPTURE                          (27u)
+#else
+#error TMR is not ported for this processor
+#endif
+/*************************************************************
+                        GP Timer 2 PWM0 Configuration
+ *************************************************************/
+
+/*! Timer PWM Enable Match. This will control PWM operation mode of the timer.
+    Toggle mode provides a 50% duty cycle and match mode provides a configurable
+    duty cycle by using the match value. This value can be set to\n
+    0 - PWM in toggle mode.\n
+    1 - PWM in match mode.
+*/
+#define TMR2_CFG_ENABLE_PWM0_MATCH_MODE                 (1u)
+
+
+/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n
+    0 - PWM idles low.\n
+    1 - PWM idles high.
+*/
+#define TMR2_CFG_PWM0_IDLE_STATE                        (1u)
+
+
+/*! PWM Match value. The value is used when the PWM is operating in match mode.
+    The PWM output is asserted when the Up/Down counter is equal to this match value.
+    PWM output is deasserted again when a timeout event occurs.
+    If the match value is never reached, or occurs simultaneous to a timeout event,
+    the PWM output remains idle. It can be any value from 0 to 65535.
+*/
+#define TMR2_CFG_PWM0_MATCH_VALUE                       (0x02DFu)
+
+/*! @} */
+
+#if defined(__ADUCM4x50__)
+/*************************************************************
+                        RGB Timer Configuration
+ *************************************************************/
+
+/** @addtogroup RGBTimer_Driver_Config RGB Timer Static Configuration
+ *  @ingroup TMR_Driver_Config
+ *  @{
+ */
+
+ 
+/*! Count up or down. Used to control whether the timer increments (counts up)
+    or decrements (counts down) the Up/Down counter, it can be set to\n
+    0 -  Timer is set to count down.\n
+    1 -  Timer is set to count up.
+*/
+#define TMR3_CFG_COUNT_UP                               (0u)
+
+/*! Timer mode. Used to control whether the timer runs in periodic or
+    free running mode, it can be set to\n
+    0 -  Timer is in free running mode.\n
+    1 -  Timer is in periodic mode.
+*/
+#define TMR3_CFG_MODE                                   (1u)
+
+/*! Prescale factor. Controls the prescaler division factor
+    to the timer's selected clock. It can be set to\n
+
+    0 - source_clock/[1 or 4]\n
+    1 - source_clock/16\n
+    2 - source_clock/64\n
+    3 - source_clock/256
+*/
+#define TMR3_CFG_PRESCALE_FACTOR                        (0u)
+
+/*! Timer clock source. Used to select a timer clock from the four
+    available clock sources, it can be set to\n
+    0 - Select PCLK\n
+    1 - Select HFOSC\n
+    2 - Select LFOSC\n
+    3 - Select LFXTAL
+*/
+#define TMR3_CFG_CLOCK_SOURCE                           (0u)
+
+/*! Timer load value. The Up/Down counter is periodically loaded with this
+    value if periodic mode is selected. LOAD writes during Up/Down counter timeout events
+    are delayed until the event has passed. It can be set to any value from 0 to 65535.
+
+*/
+#define TMR3_CFG_LOAD_VALUE                             (0x47CEu)
+
+/*! Timer asynchronous load value. The Up/Down counter is periodically loaded with
+    this value if periodic mode is selected. Writing asynchronous Load value takes
+    advantage of having the timer run on PCLK by bypassing clock synchronization
+    logic otherwise required. It can be set to any value from 0 to 65535.
+
+*/
+#define TMR3_CFG_ASYNC_LOAD_VALUE                       (0x47CEu)
+
+/*! Reload control. This allows the user to select whether the Up/Down counter should be
+    reset only on a timeout event or also when interrupt is cleared. It can be set to\n
+    0 - Up/down counter is only reset on a time out event.\n
+    1 - Resets the up/down counter when the interrupt is cleared.
+*/
+#define TMR3_CFG_ENABLE_RELOADING                       (0u)
+
+/*! Enable or disable Synchronization bypass\n
+    0 - Disable Synchronization bypass.\n
+    1 - Enable Synchronization bypass.
+*/
+#define TMR3_CFG_ENABLE_SYNC_BYPASS                     (0u)
+
+/*************************************************************
+                        RGB Timer Event Configuration
+ *************************************************************/
+
+/*! Enable or disable event capture. It can be set to\n
+    0 - Disable event capturing.\n
+    1 - Enable event capturing.
+*/
+#define TMR3_CFG_ENABLE_EVENT_CAPTURE                   (1u)
+
+/*! Enable or disable prescale reset\n
+    0 - Disable rescale reset.\n
+    1 - Enable rescale reset.
+*/
+#define TMR3_CFG_ENABLE_PRESCALE_RESET                  (0u)
+
+/*! Event to be captured. One of the selected 40 events associated
+    with a general purpose time can be captured. It can be set to
+    a value of 0 - 39. Please refer hardware reference manual to know
+    which events can be captured by a particular GP timer.
+*/
+#define TMR3_CFG_EVENT_CAPTURE                          (28u)
+
+/*************************************************************
+                        RGB Timer PWM0 Configuration
+ *************************************************************/
+
+/*! Timer PWM Enable Match. This will control PWM operation mode of the timer.
+    Toggle mode provides a 50% duty cycle and match mode provides a configurable
+    duty cycle by using the match value. This value can be set to\n
+    0 - PWM in toggle mode.\n
+    1 - PWM in match mode.
+*/
+#define TMR3_CFG_ENABLE_PWM0_MATCH_MODE                 (1u)
+
+
+/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n
+    0 - PWM idles low.\n
+    1 - PWM idles high.
+*/
+#define TMR3_CFG_PWM0_IDLE_STATE                        (1u)
+
+
+/*! PWM Match value. The value is used when the PWM is operating in match mode.
+    The PWM output is asserted when the Up/Down counter is equal to this match value.
+    PWM output is deasserted again when a timeout event occurs.
+    If the match value is never reached, or occurs simultaneous to a timeout event,
+    the PWM output remains idle. It can be any value from 0 to 65535.
+*/
+#define TMR3_CFG_PWM0_MATCH_VALUE                       (0x23E7u)
+
+/*************************************************************
+                        RGB Timer PWM1 Configuration
+ *************************************************************/
+
+/*! Timer PWM Enable Match. This will control PWM operation mode of the timer.
+    Toggle mode provides a 50% duty cycle and match mode provides a configurable
+    duty cycle by using the match value. This value can be set to\n
+    0 - PWM in toggle mode.\n
+    1 - PWM in match mode.
+*/
+#define TMR3_CFG_ENABLE_PWM1_MATCH_MODE                 (0u)
+
+
+/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n
+    0 - PWM idles low.\n
+    1 - PWM idles high.
+*/
+#define TMR3_CFG_PWM1_IDLE_STATE                        (0u)
+
+
+/*! PWM Match value. The value is used when the PWM is operating in match mode.
+    The PWM output is asserted when the Up/Down counter is equal to this match value.
+    PWM output is deasserted again when a timeout event occurs.
+    If the match value is never reached, or occurs simultaneous to a timeout event,
+    the PWM output remains idle. It can be any value from 0 to 65535.
+*/
+#define TMR3_CFG_PWM1_MATCH_VALUE                       (0u)
+
+/*************************************************************
+                        RGB Timer PWM2 Configuration
+ *************************************************************/
+
+/*! Timer PWM Enable Match. This will control PWM operation mode of the timer.
+    Toggle mode provides a 50% duty cycle and match mode provides a configurable
+    duty cycle by using the match value. This value can be set to\n
+    0 - PWM in toggle mode.\n
+    1 - PWM in match mode.
+*/
+#define TMR3_CFG_ENABLE_PWM2_MATCH_MODE                 (0u)
+
+
+/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n
+    0 - PWM idles low.\n
+    1 - PWM idles high.
+*/
+#define TMR3_CFG_PWM2_IDLE_STATE                        (0u)
+
+
+/*! PWM Match value. The value is used when the PWM is operating in match mode.
+    The PWM output is asserted when the Up/Down counter is equal to this match value.
+    PWM output is deasserted again when a timeout event occurs.
+    If the match value is never reached, or occurs simultaneous to a timeout event,
+    the PWM output remains idle. It can be any value from 0 to 65535.
+*/
+#define TMR3_CFG_PWM2_MATCH_VALUE                       (0u)
+
+/*! @} */
+#endif
+
+/*************************************************************
+                        GP Timer 0 Macro Validation
+**************************************************************/
+
+#if TMR0_CFG_COUNT_UP > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR0_CFG_MODE > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR0_CFG_PRESCALE_FACTOR > 3u
+#error "Invalid configuration"
+#endif
+
+#if TMR0_CFG_CLOCK_SOURCE > 3u
+#error "Invalid configuration"
+#endif
+
+#if TMR0_CFG_LOAD_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif
+
+#if TMR0_CFG_ASYNC_LOAD_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif
+
+#if TMR0_CFG_ENABLE_RELOADING > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR0_CFG_ENABLE_SYNC_BYPASS > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR0_CFG_ENABLE_PRESCALE_RESET > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR0_CFG_ENABLE_EVENT_CAPTURE > 1u
+#error "Invalid configuration"
+#endif
+
+#if defined(__ADUCM302x__)
+#if TMR0_CFG_EVENT_CAPTURE > 15u
+#error "Invalid configuration"
+#endif
+#elif defined(__ADUCM4x50__)
+#if TMR0_CFG_EVENT_CAPTURE > 39u
+#error "Invalid configuration"
+#endif
+#else
+#error TMR is not ported for this processor
+#endif
+
+#if TMR0_CFG_ENABLE_PWM0_MATCH_MODE > 1u
+#error "Invalid configuration"
+#endif                   
+
+#if TMR0_CFG_PWM0_IDLE_STATE > 1u
+#error "Invalid configuration"
+#endif  
+
+#if TMR0_CFG_PWM0_MATCH_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif 
+
+/*************************************************************
+                        GP Timer 1 Macro Validation
+**************************************************************/
+
+#if TMR1_CFG_COUNT_UP > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR1_CFG_MODE > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR1_CFG_PRESCALE_FACTOR > 3u
+#error "Invalid configuration"
+#endif
+
+#if TMR1_CFG_CLOCK_SOURCE > 3u
+#error "Invalid configuration"
+#endif
+
+#if TMR1_CFG_LOAD_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif
+
+#if TMR1_CFG_ASYNC_LOAD_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif
+
+#if TMR1_CFG_ENABLE_RELOADING > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR1_CFG_ENABLE_SYNC_BYPASS > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR1_CFG_ENABLE_PRESCALE_RESET > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR1_CFG_ENABLE_EVENT_CAPTURE > 1u
+#error "Invalid configuration"
+#endif
+
+#if defined(__ADUCM302x__)
+#if TMR1_CFG_EVENT_CAPTURE > 15u
+#error "Invalid configuration"
+#endif
+#elif defined(__ADUCM4x50__)
+#if TMR1_CFG_EVENT_CAPTURE > 39u
+#error "Invalid configuration"
+#endif
+#else
+#error TMR is not ported for this processor
+#endif
+
+#if TMR1_CFG_ENABLE_PWM0_MATCH_MODE > 1u
+#error "Invalid configuration"
+#endif                   
+
+#if TMR1_CFG_PWM0_IDLE_STATE > 1u
+#error "Invalid configuration"
+#endif  
+
+#if TMR1_CFG_PWM0_MATCH_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif 
+
+/*************************************************************
+                        GP Timer 2 Macro Validation
+**************************************************************/
+
+#if TMR2_CFG_COUNT_UP > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR2_CFG_MODE > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR2_CFG_PRESCALE_FACTOR > 3u
+#error "Invalid configuration"
+#endif
+
+#if TMR2_CFG_CLOCK_SOURCE > 3u
+#error "Invalid configuration"
+#endif
+
+#if TMR2_CFG_LOAD_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif
+
+#if TMR2_CFG_ASYNC_LOAD_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif
+
+#if TMR2_CFG_ENABLE_RELOADING > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR2_CFG_ENABLE_SYNC_BYPASS > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR2_CFG_ENABLE_PRESCALE_RESET > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR2_CFG_ENABLE_EVENT_CAPTURE > 1u
+#error "Invalid configuration"
+#endif
+
+#if defined(__ADUCM302x__)
+#if TMR2_CFG_EVENT_CAPTURE > 15u
+#error "Invalid configuration"
+#endif
+#elif defined(__ADUCM4x50__)
+#if TMR2_CFG_EVENT_CAPTURE > 39u
+#error "Invalid configuration"
+#endif
+#else
+#error TMR is not ported for this processor
+#endif
+
+#if TMR2_CFG_ENABLE_PWM0_MATCH_MODE > 1u
+#error "Invalid configuration"
+#endif                   
+
+#if TMR2_CFG_PWM0_IDLE_STATE > 1u
+#error "Invalid configuration"
+#endif  
+
+#if TMR2_CFG_PWM0_MATCH_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif 
+
+#if defined(__ADUCM4x50__)
+/*************************************************************
+                        RGB Timer Macro Validation
+**************************************************************/
+#if TMR3_CFG_COUNT_UP > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_MODE > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_PRESCALE_FACTOR > 3u
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_CLOCK_SOURCE > 3u
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_LOAD_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_ASYNC_LOAD_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_ENABLE_RELOADING > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_ENABLE_SYNC_BYPASS > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_ENABLE_PRESCALE_RESET > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_ENABLE_EVENT_CAPTURE > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_EVENT_CAPTURE > 39u
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_ENABLE_PWM0_MATCH_MODE > 1u
+#error "Invalid configuration"
+#endif                   
+
+#if TMR3_CFG_PWM0_IDLE_STATE > 1u
+#error "Invalid configuration"
+#endif  
+
+#if TMR3_CFG_PWM0_MATCH_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif 
+
+#if TMR3_CFG_ENABLE_PWM1_MATCH_MODE > 1u
+#error "Invalid configuration"
+#endif                   
+
+#if TMR3_CFG_PWM1_IDLE_STATE > 1u
+#error "Invalid configuration"
+#endif  
+
+#if TMR3_CFG_PWM1_MATCH_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif 
+
+#if TMR3_CFG_ENABLE_PWM2_MATCH_MODE > 1u
+#error "Invalid configuration"
+#endif                   
+
+#if TMR3_CFG_PWM2_IDLE_STATE > 1u
+#error "Invalid configuration"
+#endif  
+
+#if TMR3_CFG_PWM2_MATCH_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif 
+
+#endif
+/*! @} */
+
+
+#endif /* ADI_TMR_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_uart_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_uart_config.h
new file mode 100755
index 00000000000..1cf72a4b91a
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_uart_config.h
@@ -0,0 +1,496 @@
+/*!
+ *****************************************************************************
+   @file:    adi_uart_config.h
+   @brief:   Configuration options for UART driver.
+             This is specific to the UART driver and will be included by the driver.
+             It is not required for the application to include this header file.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_UART_CONFIG_H
+#define ADI_UART_CONFIG_H
+
+/** @addtogroup UART_Driver_Config Static Configuration
+ *  @ingroup UART_Driver
+ *  @{
+ */
+
+
+#include <adi_global_config.h>
+
+/************** Common UART Driver configurations ************** */ 
+/*!
+   Enable the autobaud detection. \n
+   Range: 0 to 1.
+*/
+#define ADI_UART_CFG_ENABLE_AUTOBAUD                 1
+
+
+/** @addtogroup UART0_Driver_Config UART0 Static Configuration
+ *  @ingroup UART_Driver_Config
+ *  @{
+ */
+ 
+/************** UART Driver configurations FOR UART 0 ************** */
+/*!
+   Word length Select. \n
+   0 -  5 Bits word length. \n
+   1 -  6 Bits word length. \n
+   2 -  7 Bits word length. \n
+   3 -  8 Bits word length.
+*/
+#define ADI_UART0_CFG_WORD_LENGTH                  3
+
+
+/*!
+   Stop bit selection. \n
+   0 -  Send 1 stop bit regardless of the word length. \n
+   1 -  Send a number of stop bits based on the word length. \n
+        WORD-LENGTH 5 Bits       => 1.5 Stop Bits. \n
+        WORD-LENGTH (6/7/8) Bits => 2   Stop Bits.
+*/
+#define ADI_UART0_CFG_STOP_BIT                      1
+
+
+/*!
+   Parity Enable. Used to control the parity bit. \n
+   0 -  Parity will not be transmitted or checked. \n
+   1 -  Parity will be transmitted and checked.
+*/
+#define ADI_UART0_CFG_ENABLE_PARITY                 0
+
+
+/*!
+   Parity Select. This bit only has meaning if parity is enabled. \n
+   0 - Odd parity will be transmitted and checked. \n
+   1 - Even parity will be transmitted and checked.
+*/
+#define ADI_UART0_CFG_PARITY_SELECTION              0
+
+
+/*!
+   Stick Parity. Used to force parity to defined values. \n
+   0 -  Parity will not be forced. \n
+   1 -  Set parity based on the following bit settings: \n
+        EPS = 1 and PEN = 1, parity will be forced to 0. \n
+        EPS = 0 and PEN = 1, parity will be forced to 1. \n
+        EPS = 1/0 and PEN = 0, no parity will be transmitted.
+*/
+#define ADI_UART0_CFG_ENABLE_STICKY_PARITY          0
+
+
+/*
+  Table 21-2: Baud Rate Examples Based on 26 MHz PCLK
+  Baud Rate OSR COMDIV DIVM DIVN
+  9600        3 24     3    1078
+  19200       3 12     3    1078
+  38400       3 8      2    1321
+  57600       3 4      3    1078
+  115200      3 4      1    1563
+  230400      3 2      1    1563
+  460800      3 1      1    1563
+  921,600     2 1      1    1563
+  1,000,000   2 1      1    1280
+  1,500,000   2 1      1    171
+
+These are calculated with the UarDivCalculator tool.
+*/
+
+/*!
+   Fractional baud rate N divide value. \n
+   Range: 0 to 2047.
+*/
+#define ADI_UART0_CFG_DIVN                           1078
+
+
+/*!
+   Fractional baud rate M divide value. \n
+   Range: 1 to 3.
+*/
+#define ADI_UART0_CFG_DIVM                           3
+
+
+/*!
+   Fractional baud rate C divide value. \n
+   Range: 1 to 65535.
+*/
+#define ADI_UART0_CFG_DIVC                           24
+
+
+/*!
+   Over Sample Rate value. \n
+   Range: 0 to 3. \n
+   0 - Over sample by 4. \n
+   1 - Over sample by 8. \n
+   2 - Over sample by 16. \n
+   3 - Over sample by 32.
+
+*/
+#define ADI_UART0_CFG_OSR                            3
+
+
+/*!
+   Enable Internal FIFO. \n
+   Range: 0 to 1.
+*/
+#define ADI_UART0_CFG_ENABLE_FIFO                    1
+
+
+/*!
+   TRIG Level for  UART device. \n
+   Range: 0 to 3. \n
+   0 - 1 byte to trig RX interrupt. \n
+   1 - 4 bytes to trig RX interrupt. \n
+   2 - 8 bytes to trig RX interrupt. \n
+   3 - 14 bytes to trig RX interrupt.
+*/
+#define ADI_UART0_CFG_TRIG_LEVEL                     0
+
+
+/*!
+   Hold TX while RX is active.  \n
+   Range: 0 to 1.
+*/
+#define ADI_UART0_CFG_HOLD_TX                        0
+
+
+/*!
+   Disable RX when TX is active. \n
+   Range: 0 to 1. \n
+   0 - 1 byte to trig RX interrupt. \n
+   1 - 4 bytes to trig RX interrupt.
+*/
+#define ADI_UART0_CFG_DISABLE_RX                     0
+
+
+/*!
+   Configure the SOUT de-assertion earlier than full stop bit(s). \n
+   Range: 0 to 1. \n
+   0 - SOUT_EN de-assert same time as full stop bit(s). \n
+   1 - SOUT_EN de-assert half-bit earlier than full stop bit(s).
+*/
+#define ADI_UART0_CFG_DEASSERTION                     0
+
+
+/*!
+   Set the SOUT polarity low. \n
+   Range: 0 to 1. \n
+   0 - Active high. \n
+   1 - Active low.
+*/
+#define ADI_UART0_CFG_SOUT_POLARITY                   0
+
+/*!
+   Enable the RX status interrupt. \n
+   Range: 0 to 1.
+*/
+#define ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT      1
+
+
+/*!
+   Enable the Modem status interrupt. \n
+   Range: 0 to 1.
+*/
+#define ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT   0
+
+/*! @} */
+
+
+/***************  UART Driver configurations FOR UART 1 **************/
+
+/** @addtogroup UART1_Driver_Config UART1 Static Configuration
+ *  @ingroup UART_Driver_Config
+ *  @{
+ */
+
+/*!
+   Word length Select. \n
+   0 -  5 Bits word length. \n
+   1 -  6 Bits word length. \n
+   2 -  7 Bits word length. \n
+   3 -  8 Bits word length.
+*/
+#define ADI_UART1_CFG_WORD_LENGTH                     3
+
+
+/*!
+   Stop bit selection.\n
+   0 -  Send 1 stop bit regardless of the word length. \n
+   1 -  Send a number of stop bits based on the word length. \n
+        WORD-LENGTH 5 Bits       => 1.5 Stop Bits. \n
+        WORD-LENGTH (6/7/8) Bits => 2   Stop Bits.
+*/
+#define ADI_UART1_CFG_STOP_BIT                        1
+
+
+/*!
+   Parity Enable. Used to control the parity bit. \n
+   0 -  Parity will not be transmitted or checked. \n
+   1 -  Parity will be transmitted and checked.
+*/
+#define ADI_UART1_CFG_ENABLE_PARITY                   0
+
+
+/*!
+   Parity Select. This bit only has meaning if parity is enabled. \n
+   0 - Odd parity will be transmitted and checked. \n
+   1 - Even parity will be transmitted and checked.
+*/
+#define ADI_UART1_CFG_PARITY_SELECTION                0
+
+
+/*!
+   Stick Parity. Used to force parity to defined values. \n
+   0 -  Parity will not be forced. \n
+   1 -  Set parity based on the following bit settings: \n
+        EPS = 1 and PEN = 1, parity will be forced to 0. \n
+        EPS = 0 and PEN = 1, parity will be forced to 1. \n
+        EPS = 1/0 and PEN = 0, no parity will be transmitted.
+*/
+#define ADI_UART1_CFG_ENABLE_STICKY_PARITY            0
+
+
+/*
+  Table 21-2: Baud Rate Examples Based on 26 MHz PCLK
+  Baud Rate OSR COMDIV DIVM DIVN
+  9600        3 24     3    1078
+  19200       3 12     3    1078
+  38400       3 8      2    1321
+  57600       3 4      3    1078
+  115200      3 4      1    1563
+  230400      3 2      1    1563
+  460800      3 1      1    1563
+  921,600     2 1      1    1563
+  1,000,000   2 1      1    1280
+  1,500,000   2 1      1    171
+
+These are calculated with the UarDivCalculator tool.
+*/
+
+/*!
+   Fractional baud rate N divide value. \n
+   Range: 0 to 2047.
+*/
+#define ADI_UART1_CFG_DIVN                              1563
+
+
+/*!
+   Fractional baud rate M divide value. \n
+   Range: 1 to 3.
+*/
+#define ADI_UART1_CFG_DIVM                             1
+
+
+/*!
+   Fractional baud rate C divide value. \n
+   Range: 1 to 65535.
+*/
+#define ADI_UART1_CFG_DIVC                             1
+
+
+/*!
+   Over Sample Rate value. \n
+   Range: 0 to 3. \n
+   0 - Over sample by 4. \n
+   1 - Over sample by 8. \n
+   2 - Over sample by 16. \n
+   3 - Over sample by 32.
+
+*/
+#define ADI_UART1_CFG_OSR                              3
+
+
+/*!
+   Enable Internal FIFO. \n
+   Range: 0 to 1.
+*/
+#define ADI_UART1_CFG_ENABLE_FIFO                      1
+
+
+/*!
+   TRIG Level for  UART device. \n
+   Range: 0 to 3. \n
+   0 - 1 byte to trig RX interrupt. \n
+   1 - 4 bytes to trig RX interrupt. \n
+   2 - 8 bytes to trig RX interrupt. \n
+   3 - 14 bytes to trig RX interrupt.
+*/
+#define ADI_UART1_CFG_TRIG_LEVEL                       0
+
+
+/*!
+   Hold TX while RX is active.  \n
+   Range: 0 to 1.
+*/
+#define ADI_UART1_CFG_HOLD_TX                          0
+
+
+/*!
+   Disable RX when TX is active. \n
+   Range: 0 to 1. \n
+   0 - 1 byte to trig RX interrupt. \n
+   1 - 4 bytes to trig RX interrupt.
+*/
+#define ADI_UART1_CFG_DISABLE_RX                       0
+
+
+/*!
+   Configure the SOUT de-assertion earlier than full stop bit(s). \n
+   Range: 0 to 1. \n
+   0 - SOUT_EN de-assert same time as full stop bit(s). \n
+   1 - SOUT_EN de-assert half-bit earlier than full stop bit(s).
+*/
+#define ADI_UART1_CFG_DEASSERTION                     0
+
+
+/*!
+   Set the SOUT polarity low. \n
+   Range: 0 to 1. \n
+   0 - Active high. \n
+   1 - Active low.
+*/
+#define ADI_UART1_CFG_SOUT_POLARITY                   0
+
+/*!
+   Enable the RX status interrupt. \n
+   Range: 0 to 1.
+*/
+#define ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT       1
+
+
+/*!
+   Enable the Modem status interrupt. \n
+   Range: 0 to 1.
+*/
+#define ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT    0
+/*! @} */
+
+/*! @} */
+
+
+/***************  UART Driver Debug Checks ************** */
+
+/* Check word length */
+#if (((ADI_UART0_CFG_WORD_LENGTH < 0) || (ADI_UART0_CFG_WORD_LENGTH > 3))  || ((ADI_UART1_CFG_WORD_LENGTH < 0) || (ADI_UART1_CFG_WORD_LENGTH > 3)))
+#error "Word length needs to be between 0 and 3"
+#endif
+
+/* Check stop bit */
+#if (((ADI_UART0_CFG_STOP_BIT < 0) || (ADI_UART0_CFG_STOP_BIT > 1))  || ((ADI_UART1_CFG_STOP_BIT < 0) || (ADI_UART1_CFG_STOP_BIT > 1)))
+#error "Stop bit selection needs to be 0 or 1"
+#endif
+
+/* Check parity enable  */
+#if (((ADI_UART0_CFG_ENABLE_PARITY < 0) || (ADI_UART0_CFG_ENABLE_PARITY > 1))  || ((ADI_UART1_CFG_ENABLE_PARITY < 0) || (ADI_UART1_CFG_ENABLE_PARITY > 1)))
+#error "Parity Enable bit needs to be 0 or 1"
+#endif
+
+/* Check parity select */
+#if (((ADI_UART0_CFG_PARITY_SELECTION < 0) || (ADI_UART0_CFG_PARITY_SELECTION > 1))  || ((ADI_UART1_CFG_PARITY_SELECTION < 0) || (ADI_UART1_CFG_PARITY_SELECTION > 1)))
+#error "Parity bit selection needs to be 0 or 1"
+#endif
+
+/* Check enable sticky parity */
+#if (((ADI_UART0_CFG_ENABLE_STICKY_PARITY < 0) || (ADI_UART0_CFG_ENABLE_STICKY_PARITY > 1))  || ((ADI_UART1_CFG_ENABLE_STICKY_PARITY < 0) || (ADI_UART1_CFG_ENABLE_STICKY_PARITY > 1)))
+#error "Sticky parity enable needs to be 0 or 1"
+#endif
+
+/* Check fractional baudrate N divider value */
+#if (((ADI_UART0_CFG_DIVN < 0) || (ADI_UART0_CFG_DIVN > 2047))  || ((ADI_UART1_CFG_DIVN < 0) || (ADI_UART1_CFG_DIVN > 2047)))
+#error "Fractional baudrate N divider value needs to be between 0 and 2047"
+#endif
+
+/* Check fractional baudrate M divider value */
+#if (((ADI_UART0_CFG_DIVM < 1) || (ADI_UART0_CFG_DIVM > 3))  || ((ADI_UART1_CFG_DIVM < 1) || (ADI_UART1_CFG_DIVM > 3)))
+#error "Fractional baudrate M divider value needs to be between 1 and 3"
+#endif
+
+/* Check fractional baudrate C divider value */
+#if (((ADI_UART0_CFG_DIVC < 1) || (ADI_UART0_CFG_DIVC > 65535))  || ((ADI_UART1_CFG_DIVC < 1) || (ADI_UART1_CFG_DIVC > 65535)))
+#error "Fractional baudrate C divider value needs to be between 1 and 65535"
+#endif
+
+/* Check over same rate value */
+#if (((ADI_UART0_CFG_OSR < 0) || (ADI_UART0_CFG_OSR > 3))  || ((ADI_UART1_CFG_OSR < 0) || (ADI_UART1_CFG_OSR > 3)))
+#error "over sample rate value needs to be between 0 and 3"
+#endif
+
+/* Check enable internal FIFO */
+#if (((ADI_UART0_CFG_ENABLE_FIFO < 0) || (ADI_UART0_CFG_ENABLE_FIFO > 1))  || ((ADI_UART1_CFG_ENABLE_FIFO < 0) || (ADI_UART1_CFG_ENABLE_FIFO > 1)))
+#error "Enable internal FIFO needs to be 0 or 1"
+#endif
+
+/* Check UART trig level */
+#if (((ADI_UART0_CFG_TRIG_LEVEL < 0) || (ADI_UART0_CFG_TRIG_LEVEL > 3))  || ((ADI_UART1_CFG_TRIG_LEVEL < 0) || (ADI_UART1_CFG_TRIG_LEVEL > 3)))
+#error "Trig level for the UART device needs to be 0 or 1"
+#endif
+
+/* Check value for holding tx while rx is active */
+#if (((ADI_UART0_CFG_HOLD_TX < 0) || (ADI_UART0_CFG_HOLD_TX > 1))  || ((ADI_UART1_CFG_HOLD_TX < 0) || (ADI_UART1_CFG_HOLD_TX > 1)))
+#error "Value for holding Tx while Rx is active needs to be 0 or 1"
+#endif
+
+/* Check value de-assertion */
+#if (((ADI_UART0_CFG_DEASSERTION < 0) || (ADI_UART0_CFG_DEASSERTION > 1))  || ((ADI_UART1_CFG_DEASSERTION < 0) || (ADI_UART1_CFG_DEASSERTION > 1)))
+#error "Value for de-assertion needs to be 0 or 1"
+#endif
+
+/* Check value for SOUT polarity */
+#if (((ADI_UART0_CFG_SOUT_POLARITY < 0) || (ADI_UART0_CFG_SOUT_POLARITY > 1))  || ((ADI_UART1_CFG_SOUT_POLARITY < 0) || (ADI_UART1_CFG_SOUT_POLARITY > 1)))
+#error "Value for SOUT polarity needs to be 0 or 1"
+#endif
+
+/* Check value to enable autobaud detection */
+#if ((ADI_UART_CFG_ENABLE_AUTOBAUD < 0) || (ADI_UART_CFG_ENABLE_AUTOBAUD > 1))
+#error "Value for autobaud enable needs to be 0 or 1"
+#endif
+
+/* Check value to enable Rx status interrupt */
+#if (((ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT < 0) || (ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT > 1))  || ((ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT < 0) || (ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT > 1)))
+#error "Value to enable Rx status interrupt needs to be 0 or 1"
+#endif
+
+/* Check value to enable modem status interrupt */
+#if (((ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT < 0) || (ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT > 1))  || ((ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT < 0) || (ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT > 1)))
+#error "Value to enable modem status interrupt needs to be 0 or 1"
+#endif
+
+#endif /* ADI_UART_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_wdt_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_wdt_config.h
new file mode 100755
index 00000000000..25e47a78509
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_wdt_config.h
@@ -0,0 +1,119 @@
+/*! *****************************************************************************
+ * @file    adi_wdt_config.h
+ * @brief   WDT device driver configuration
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+
+#ifndef ADI_WDT_CONFIG_H
+#define ADI_WDT_CONFIG_H
+
+
+/** @addtogroup WDT_Driver_Config Static Configuration
+ *  @ingroup WDT_Driver
+ *  @{
+ */
+
+
+/************* WDT Static Configuration ***************/
+
+/*! WDT Timer Reload Value\n
+    Value used to reload the WDT count register after count expires.\n
+   0-65535 - WDT reload value (default is 0x0100).
+*/
+#define ADI_WDT_LOAD_VALUE                                  (0x1000u)
+
+/*! WDT Timer Mode\n
+   Selects WDT operating mode.\n
+   0 -  WDT operates in free-running mode.\n
+   1 -  WDT operates in periodic mode (default).
+*/
+#define ADI_WDT_CONTROL_TIMER_MODE                               (1u)
+
+/*! WDT Clock Prescaler\n
+   Controls WDT clock prescale.\n
+   0 -  WDT operates at (source clock)/1.\n
+   1 -  WDT operates at (source clock)/16.\n
+   2 -  WDT operates at (source clock)/256 (default).\n
+*/
+#define ADI_WDT_CONTROL_CLOCK_PRESCALER                          (2u)
+
+/*! WDT Timeout Mode\n
+   Controls WDT timeout behaviour.\n
+   0 -  WDT issues RESET on timeout (default).\n
+   1 -  WDT issues INTERRUPT on timeout.
+*/
+#define ADI_WDT_CONTROL_TIMEOUT_MODE                             (0u)
+
+/*! WDT Power Mode Disable\n
+   Controls WDT countdown in hibernate or halted mode.\n
+   0 -  WDT continues to count down when core is halted or in hibernate.\n
+   1 -  WDT pauses count down when core is halted or in hibernate (default).\n
+*/
+#define ADI_WDT_CONTROL_POWER_MODE                               (1u)
+
+/************** Macro Validation *****************************/
+
+#if ( ADI_WDT_LOAD_VALUE  > 65535u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_WDT_CONTROL_TIMER_MODE > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_WDT_CONTROL_CLOCK_PRESCALER > 2u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_WDT_CONTROL_TIMEOUT_MODE > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_WDT_CONTROL_POWER_MODE > 1u )
+#error "Invalid configuration"
+#endif
+
+/**
+ *  @}
+ */
+
+#endif /* ADI_WDT_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crc/adi_crc.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crc/adi_crc.c
new file mode 100755
index 00000000000..4ea2233205c
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crc/adi_crc.c
@@ -0,0 +1,1279 @@
+/*! ****************************************************************************
+ * @file:    adi_crc.c
+ * @brief:   CRC device driver global file.
+ * @details: This file contain the CRC device driver impelementation.
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders. This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#include <adi_processor.h>
+#include <rtos_map/adi_rtos_map.h>
+
+
+/** @addtogroup  CRC_Driver CRC Device Driver
+ *  @{
+
+@brief <b>Cyclic Redundancy Check (CRC) peripheral driver</b>
+@details
+
+The CRC peripheral is used to perform the Cyclic Redundancy Check (CRC) of the
+block of data that is presented to the peripheral. The peripheral provides a
+means to periodically verify the integrity of the system memory and it is based
+on a CRC32 engine that computes the signature of 32-bit data presented to the
+hardware engine. CRC operations can be core driven or DMA driven depending on
+static configuration.
+
+    - #ADI_CRC_CFG_ENABLE_DMA_SUPPORT set to 0 defines a core driven CRC driver
+    - #ADI_CRC_CFG_ENABLE_DMA_SUPPORT set to a non 0 value defines a DMA driven
+      CRC driver
+
+<b>Core driven CRC operations</b>
+
+The adi_crc_Compute function executes core driven CRC operations to calculate the
+CRC on the buffer input with the CRC parameters set in the driver. In this mode,
+data in the submitted buffer is transmitted to the CRC directly by the core.
+
+<b>Memory DMA driver CRC operations</b>
+
+The adi_crc_Compute function executes DMA driven CRC operations to calculate the
+CRC on the buffer input with the CRC parameters set in the driver. In this mode,
+data in the submitted buffer is transmitted to the CRC through DMA transfers.
+
+The software DMA channel reserved for the CRC driver is defined by a macro,
+ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID, which can take a value between 0 and 7.
+If this macro is not defined, e.g. in a configuration file, then its value
+is defaulted to 7: in this case, DMA channel SIP7 is used by the CRC driver
+and DMA_SIP7_Int_Handler becomes the interrupt used by the DMA when a transfer
+to the CRC is complete.
+
+<em><b>Computing CRC</b></em>
+
+The CRC engine performs a 32-bit CRC operation on the incoming data stream.
+
+Sequence of function calls for Computing CRC :\n
+    - #adi_crc_Open() to open CRC device and get a valid CRC handle.
+    - #adi_crc_SetPolynomialVal() to set the polynomial value to be used in CRC operations.
+    - #adi_crc_SetBitMirroring() to enable/disable bit mirroring
+    - #adi_crc_SetByteMirroring() to enable/disable byte mirroring
+    - #adi_crc_SetLSBFirst() to indicate if data is Big or Little Endian.
+    - #adi_crc_IsCrcInProgress() to poll the current status of CRC operation or
+      wait for callback event.
+    - #adi_crc_GetFinalCrcVal() to get the CRC value of the data stream if its
+      CRC value is unknown. (Note that #adi_crc_GetFinalCrcVal resets the CRC
+      seed to the #ADI_CFG_CRC_SEED_VALUE default value.)
+
+      Note that using statically configured parameters such as
+      #ADI_CFG_CRC_ENABLE_BYTE_MIRRORING, #ADI_CFG_CRC_ENABLE_BIT_MIRRORING,
+      #ADI_CFG_CRC_POLYNOMIAL and #ADI_CFG_CRC_SEED_VALUE, functions
+      #adi_crc_SetBitMirroring, #adi_crc_SetByteMirroring, #adi_crc_SetPolynomialVal
+      and #adi_crc_SetBitMirroring don't need to be called explicitly in your
+      application: the parameters will be assigned when opening the driver.
+
+  @note - The application must include drivers/crc/adi_crc.h to use this driver.
+  @note - This driver also requires the DMA driver.  The application must include
+          the DMA driver sources to avoid link errors.
+ */
+
+/*! \cond PRIVATE */
+/*=============  I N C L U D E S   =============*/
+
+#include <drivers/crc/adi_crc.h>
+#include <adi_cyclecount.h>
+#include "adi_crc_def.h"
+
+/*=============  M I S R A  =============*/
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
+*   This isn't a header as such.
+*
+* Pm088 (rule 17.4): pointer arithmetic should not be used.
+* Pm152 (rule 17.4): array indexing shall only be applied to objects defined as an array type
+*   Relying on pointer arithmetic for buffer handling.
+*
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   Casts from pointer to uint32_t needed to determine pointer alignment.
+*/
+#pragma diag_suppress=Pm123,Pm088,Pm152,Pm140
+#endif /* __ICCARM__ */
+
+/*==============  D E F I N E S  ===============*/
+
+/* CRC Peripheral specific information */
+#define ADI_CRC_NUM_DEVICES             (1u)
+
+/*! \endcond */
+
+#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT != 0)
+
+/**
+ * If a DMA channel has not been configured for the CRC driver,
+* then a default software DMA channel is assigned: SIP7.
+ */
+
+#ifndef ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID
+#define ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID 7
+#pragma message("ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID implicitly defaulted to 7!")
+#endif
+
+/**
+ * The following macros define
+ * - the Software DMA channel identifier to be used in CRC DMA driven operations
+ * - the ISR used by the CRC, which depends on the Software DMA channel
+ *   selected to drive the CRC in DMA driven CRC operations.
+ * - the interrupt identifier mapped to the software DMA channel; selected for
+ *   the CRC operations
+ */
+#if   (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 0)
+#define ADI_CFG_CRC_DMA_CHANNEL         SIP0_CHANn
+#define ADI_DMA_CRC_ISR                 DMA_SIP0_Int_Handler
+#define ADI_CRC_IRQ_ID                  DMA0_CH16_DONE_IRQn
+#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 1)
+#define ADI_CFG_CRC_DMA_CHANNEL         SIP1_CHANn
+#define ADI_DMA_CRC_ISR                 DMA_SIP1_Int_Handler
+#define ADI_CRC_IRQ_ID                  DMA0_CH17_DONE_IRQn
+#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 2)
+#define ADI_CFG_CRC_DMA_CHANNEL         SIP2_CHANn
+#define ADI_DMA_CRC_ISR                 DMA_SIP2_Int_Handler
+#define ADI_CRC_IRQ_ID                  DMA0_CH18_DONE_IRQn
+#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 3)
+#define ADI_CFG_CRC_DMA_CHANNEL         SIP3_CHANn
+#define ADI_DMA_CRC_ISR                 DMA_SIP3_Int_Handler
+#define ADI_CRC_IRQ_ID                  DMA0_CH19_DONE_IRQn
+#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 4)
+#define ADI_CFG_CRC_DMA_CHANNEL         SIP4_CHANn
+#define ADI_DMA_CRC_ISR                 DMA_SIP4_Int_Handler
+#define ADI_CRC_IRQ_ID                  DMA0_CH20_DONE_IRQn
+#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 5)
+#define ADI_CFG_CRC_DMA_CHANNEL         SIP5_CHANn
+#define ADI_DMA_CRC_ISR                 DMA_SIP5_Int_Handler
+#define ADI_CRC_IRQ_ID                  DMA0_CH21_DONE_IRQn
+#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 6)
+#define ADI_CFG_CRC_DMA_CHANNEL         SIP6_CHANn
+#define ADI_DMA_CRC_ISR                 DMA_SIP6_Int_Handler
+#define ADI_CRC_IRQ_ID                  DMA0_CH22_DONE_IRQn
+#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 7)
+#define ADI_CFG_CRC_DMA_CHANNEL         SIP7_CHANn
+#define ADI_DMA_CRC_ISR                 DMA_SIP7_Int_Handler
+#define ADI_CRC_IRQ_ID                  DMA0_CH23_DONE_IRQn
+#else
+#error "Invalid Software DMA channel identifier ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID: it must be between 0 and 7"
+#endif
+
+#endif  /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */
+
+/*! \cond PRIVATE */
+
+/** Check the validity of a CRC device identifier */
+#define ADI_CRC_VALID_DEVICE_ID(DEVNUM)         ((DEVNUM)<(ADI_CRC_NUM_DEVICES))
+
+/** Check that a CRC driver is in idle state */
+#define ADI_CRC_DEVICE_IS_IDLE(DEV)             (((DEV)->eCrcOpStatus == ADI_CRC_OP_IDLE) ? true : false)
+
+/*==============  D A T A  ===============*/
+
+/**
+ * Information for managing all the CRC devices available
+ */
+static ADI_CRC_INFO crc_device_info[ADI_CRC_NUM_DEVICES] =
+{
+   { pADI_CRC0,  NULL }      /* CRC  0 */
+};
+
+/*==============  M O R E   D E F I N E S  ===============*/
+
+/** Check the validity of a CRC handle for debug mode */
+#define ADI_CRC_INVALID_HANDLE(h)               ((NULL == (h)) || (crc_device_info[0].hDevice != (h)))
+
+/** Condition used to indicate if a CRC driver is already in use */
+#define ADI_CRC_DEVICE_IN_USE(DEVNUM)           ((NULL) != crc_device_info[(DEVNUM)].hDevice)
+
+#ifdef ADI_DEBUG
+#define HDL_TO_DEVICE_PTR(HDL) ((ADI_CRC_INVALID_HANDLE(HDL)) ? (NULL) : ((ADI_CRC_DEVICE*) (HDL)))
+#else
+#define HDL_TO_DEVICE_PTR(HDL) ((ADI_CRC_DEVICE*) (HDL))
+#endif
+
+/*=============  C O D E  =============*/
+
+#if (ADI_CRC_NUM_DEVICES!=1u)
+#error "!!! Current CRC driver implementation can deal with a unique CRC instance !!!"
+#endif
+
+/*=============  L O C A L   F U N C T I O N S =============*/
+
+/* Prototypes for static functions (required by MISRA-C:2004 Rule 8.1)  */
+
+static ADI_CRC_INFO *crc_DeviceInfo(ADI_CRC_HANDLE hDevice);
+
+static void crc_ResetRegisters (ADI_CRC_DEVICE *pDevice);
+
+#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT == 0)
+
+/* Functions specific to core driven CRC operations */
+
+static ADI_CRC_RESULT crc_ExecuteCoreDrivenOperation (ADI_CRC_DEVICE *pDevice, void *pCrcBuf, uint32_t NumBytes, uint32_t NumBits);
+
+#else
+
+/* Functions specific to DMA driven CRC operations */
+
+static ADI_CRC_RESULT crc_ExecuteDmaDrivenOperation(ADI_CRC_DEVICE *pDevice, void *pCrcBuf, uint32_t NumBytes, uint32_t NumBits);
+static void crc_CalculateCrcForRemaining(ADI_CRC_DEVICE *pDevice, uint8_t *pData, uint32_t NumBytes, uint32_t NumBits);
+static void CRC_Callback_For_DMA_Err_Int_Handler(void *pcbparam, uint32_t nEvent, void *pArg);
+void ADI_DMA_CRC_ISR(void);
+
+#endif  /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */
+
+
+/**
+ * @brief       return a pointer to the CRC device information mapped to the CRC
+ *              device identified by a handle
+ *
+ * @param [in]  hDevice         CRC device handle
+ *
+ * @return      pointer to CRC device information identified by hDevice
+ *              (NULL if the CRC device handle is invalid)
+ */
+static ADI_CRC_INFO *crc_DeviceInfo(ADI_CRC_HANDLE hDevice)
+{
+    ADI_CRC_INFO *pCrcInfo = (ADI_CRC_INVALID_HANDLE(hDevice))
+                           ? NULL
+                           : (&(crc_device_info[0]));
+    return pCrcInfo;
+}
+
+
+/**
+ * @brief       Reset CRC registers to default values
+ *
+ * @details     Reset CRC registers to default values as defined in configuration.
+ *
+ * @param [in]  pDevice         Pointer to CRC device
+ *
+ * @return      None
+ */
+static void crc_ResetRegisters(ADI_CRC_DEVICE *pDevice)
+{
+    /* Cast the values to be assigned to the targetted types */
+    const uint32_t byte_mirroring_val = (uint32_t) ADI_CFG_CRC_ENABLE_BYTE_MIRRORING;
+    const uint32_t byte_mirroring_pos = (uint32_t) BITP_CRC_CTL_BYTMIRR;
+    const uint32_t bit_mirroring_val  = (uint32_t) ADI_CFG_CRC_ENABLE_BIT_MIRRORING;
+    const uint32_t bit_mirroring_pos  = (uint32_t) BITP_CRC_CTL_BITMIRR;
+    const uint32_t seed_value = (uint32_t) ADI_CFG_CRC_SEED_VALUE;
+    const uint32_t polynomial = (uint32_t) ADI_CFG_CRC_POLYNOMIAL;
+
+    /* Set byte mirroring and bit mirroring in CTL register as configured */
+    pDevice->pReg->CTL = ( (byte_mirroring_val << byte_mirroring_pos)
+                         | (bit_mirroring_val << bit_mirroring_pos)
+                         );
+    pDevice->pReg->RESULT = seed_value;
+    pDevice->pReg->POLY   = polynomial;
+}
+
+#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT == 0)
+
+/*
+ * @brief       Starts core driven CRC operation.
+ *
+ * @param [in]  pDevice         Pointer to CRC device
+ * @param [in]  pCrcBuf         Address of data buffer.
+ * @param [in]  NumBytes        Number of bytes in data buffer.
+ * @param [in]  NumBits         Number of bits, 0 to 7, in the last partial byte
+ *                              in CRC data buffer
+ *
+ * @return      Status
+ *              - ADI_CRC_SUCCESS: Successfully set expected CRC result.
+ */
+static ADI_CRC_RESULT crc_ExecuteCoreDrivenOperation(
+    ADI_CRC_DEVICE      *pDevice,
+    void                *pCrcBuf,
+    uint32_t            NumBytes,
+    uint32_t            NumBits)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    uint8_t *pData = (uint8_t *)pCrcBuf;        /* initialize the pointer to data to the start of the data buffer */
+    uint32_t lsbFirst = pDevice->pReg->CTL & BITM_CRC_CTL_LSBFIRST;
+
+    pDevice->pReg->CTL |= (BITM_CRC_CTL_EN);    /*! enable CRC peripheral */
+
+    if (((uint32_t)pData & 0x3u) != 0u)         /* If the buffer is not 4-byte aligned */
+    {
+        /* feed the CRC byte per byte as long as there are data in the input buffer AND
+         * the data left in the buffer are not 4-byte aligned */
+        while ((NumBytes > 0u) && (((uint32_t)pData & 0x3u) != 0u))
+        {
+            pDevice->pReg->IPBYTE = *pData;     /* feed the CRC with the first byte in the buffer */
+            pData++;                            /* get the next byte to feed into CRC */
+            NumBytes--;                         /* decrease the number of bytes to be processed */
+        }
+    }
+
+    /* data left in the input buffer are now 4-byte aligned */
+
+    while (NumBytes >= 4u)                      /* if the number of bytes left is greater than 4 bytes */
+    {                                           /* feed CRC peripheral with 4-byte data */
+        uint32_t nData;                         /* 32-bit variable to be used to feed the CRC peripheral */
+
+        /*
+         * Here we assume memory is little endian. We need change the following
+         * code if we produce a Cortex-M processor with big endian memory.
+         */
+        if (lsbFirst != 0u)
+        {
+            nData = pData[3];
+            nData = (nData << 8) | pData[2];
+            nData = (nData << 8) | pData[1];
+            nData = (nData << 8) | pData[0];
+        }
+        else
+        {
+            nData = pData[0];
+            nData = (nData << 8) | pData[1];
+            nData = (nData << 8) | pData[2];
+            nData = (nData << 8) | pData[3];
+        }
+        pDevice->pReg->IPDATA = nData;          /* feed the CRC peripheral with 32-bit data input */
+        pData += 4;                             /* move the data pointer in the data buffer */
+        NumBytes -= 4u;                         /* decrease the number of data to be processed */
+    }
+
+    while (NumBytes > 0u)                       /* if the number of data left in the input buffer is smaller than 4 */
+    {
+        pDevice->pReg->IPBYTE = *pData;         /* feed the CRC peripheral with the remaining bytes */
+        pData++;                                /* move the pointer to the next byte in input data buffer */
+        NumBytes--;                             /* decrease the number of data to be fed into the CRC peripheral */
+    }
+
+    if (NumBits > 0u)                           /* if the last byte is a partial byte containing less than 8 bits */
+    {
+        pDevice->pReg->IPBITS[NumBits] = *pData;/* feed the CRC peripheral with the remaining bits (use IPBITS[N] to feed N bits) */
+    }
+
+    pDevice->pReg->CTL &= ~(BITM_CRC_CTL_EN);   /* All the data have been fed into the CRC peripheral : disable it */
+    pDevice->eCrcOpStatus = ADI_CRC_OP_IDLE;    /* CRC back in idle state */
+    return result;
+}
+
+#else   /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */
+
+/**
+ * @brief       Send a Memory DMA request to the CRC, which triggers a DMA driven
+ *              CRC operation.
+ *
+ * @param [in]  pDevice         Pointer to CRC device
+ * @param [in]  pCrcBuf         Address of data buffer.
+ * @param [in]  NumBytes        Number of whole bytes in data buffer.
+ * @param [in]  NumBits         Number of bits, 0 to 7, in the last partial byte
+ *                              in CRC data buffer
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Successfully set expected CRC result.
+ *              - #ADI_CRC_INVALID_DMA_CHANNEL: DMA channel cannot be used with CRC
+ */
+static ADI_CRC_RESULT crc_ExecuteDmaDrivenOperation(
+    ADI_CRC_DEVICE      *pDevice,
+    void                *pCrcBuf,
+    uint32_t            NumBytes,
+    uint32_t            NumBits)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    uint8_t *pData = (uint8_t *)pCrcBuf;
+    bool bUseDma = false;                               /* assume core driven CRC by default */
+
+#ifdef ADI_DEBUG
+    if (!ADI_CRC_VALID_DMA_CHANNEL(ADI_CFG_CRC_DMA_CHANNEL))
+    {
+        /* Report error as Memory DMA not open */
+        result = ADI_CRC_INVALID_DMA_CHANNEL;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        /* If LSBFIRST, it's easy. */
+        if ((pDevice->pReg->CTL & BITM_CRC_CTL_LSBFIRST) != 0u)
+        {
+            /* If the buffer is not 4-byte aligned */
+            if (((uint32_t)pData & 0x3u) != 0u)
+            {
+                /* process the first bytes until a 4-byte aligned data location is reached */
+                pDevice->pReg->CTL |= (BITM_CRC_CTL_EN);        /* enable CRC */
+                while ((NumBytes > 0u) && (((uint32_t)pData & 0x3u) != 0u))
+                {
+                    pDevice->pReg->IPBYTE = *pData;             /* feed byte into CRC */
+                    pData++;                                    /* get to the next byte */
+                    NumBytes--;                                 /* decrease the number of bytes still to be processed */
+                }
+                pDevice->pReg->CTL &= ~(BITM_CRC_CTL_EN);       /* disable CRC */
+            }
+
+            /* 4-byte aligned data transfer */
+            if (NumBytes >= 4u)
+            {
+                /* there are enough data for kicking off a DMA driven CRC operation */
+                const uint32_t channelId = (uint32_t) ADI_CFG_CRC_DMA_CHANNEL;
+                const uint32_t channelBit = 1ul << channelId;           /* get a value with the bit set at position identified by channelId */
+                const uint32_t numData = NumBytes / 4u;                 /* number of 4-byte data to be transferred */
+                const uint32_t src = (uint32_t) pData;                  /* DMA source address */
+                const uint32_t dst = (uint32_t) &pDevice->pReg->IPDATA; /* destination is CRC IPDATA 32-bit register */
+                const uint32_t numTransData = ( (numData > DMA_TRANSFER_LIMIT)
+                                              ? DMA_TRANSFER_LIMIT
+                                              : numData
+                                               );
+                const uint32_t numTransBytes = (numTransData << 2u);
+                const uint32_t lastDataPos = (numTransBytes - 4u);      /* position of last 32-bit data to be transferred in current DMA request */
+
+                pDevice->pReg->CTL |= ((uint32_t) BITM_CRC_CTL_EN);     /* enable CRC (leave other bits unmodified) */
+
+                pADI_DMA0->EN_SET = channelBit;                         /* Enable the channel */
+                pADI_DMA0->ALT_CLR = channelBit;                        /* Set the primary as the current DMA descriptor */
+                pADI_DMA0->SRCADDR_CLR = channelBit;                    /* Ensure decrement for source is cleared */
+                pADI_DMA0->DSTADDR_CLR = channelBit;                    /* Ensure decrement for destination is cleared */
+
+                pPrimaryCCD[channelId].DMADSTEND = dst;                 /* destination is CRC IPDATA 32-bit register */
+                pPrimaryCCD[channelId].DMASRCEND = src + lastDataPos;   /* source end address */
+
+                pPrimaryCCD[channelId].DMACDC =
+                    ( (((uint32_t) ADI_DMA_INCR_NONE)    << ((uint32_t) DMA_BITP_CTL_DST_INC))  /* destination address not incremented */
+                    | (((uint32_t) ADI_DMA_INCR_4_BYTE)  << ((uint32_t) DMA_BITP_CTL_SRC_INC))  /* source address incremented by 4 bytes */
+                    | (((uint32_t) ADI_DMA_WIDTH_4_BYTE) << ((uint32_t) DMA_BITP_CTL_SRC_SIZE)) /* source data size is 4-byte */
+                    | ((numTransData - 1u)               << ((uint32_t) DMA_BITP_CTL_N_MINUS_1))/* number of DMA transfers (minus 1) */
+                    | (DMA_ENUM_CTL_CYCLE_CTL_AUTO_REQ << DMA_BITP_CTL_CYCLE_CTL)               /* DMA Auto Request transmission */
+                    );
+                pDevice->pRemainingData = (void*)(src + numTransBytes); /* remaining data start address */
+                pDevice->RemainingBytes = NumBytes - numTransBytes;     /* remaining bytes that cannot be processed in this DMA batch */
+                pDevice->RemainingBits = NumBits;                       /* remaining bits if last byte is a partial byte */
+                bUseDma = true;                                         /* there are enough data to run 4-byte DMA transfers to CRC */
+            }
+        }
+        /*
+        * If ! LSBFIRST, we need the DMA controller support byte swap for fixed destination address.
+        * But we don't have such luck, although it supports byte swap for fixed source address.
+        * So we have to set DMA size to one byte, which is slower.
+        *
+        * Another option is using mirroring feature of CRC unit, which would be more complicated.
+        */
+        else
+        {
+            if (NumBytes > 0u)
+            {
+                /**
+                 * There are enough data for kicking off a DMA driven CRC operation.
+                 * DMA transfers are limited to 1024 bytes : if the buffer is larger
+                 * than 1024 then generate repeated DMA request through the CRC DMA
+                 * interrupt handler, i.e. the interrupt handler used by the software
+                 * DMA channel driving the CRC operations.
+                 */
+                const uint32_t channelId = (uint32_t) ADI_CFG_CRC_DMA_CHANNEL;
+                const uint32_t channelBit = 1ul << channelId;           /* get a value with the bit set at position identified by channelId */
+                const uint32_t src = (uint32_t) pData;                  /* DMA source address */
+                const uint32_t dst = (uint32_t) &pDevice->pReg->IPBYTE; /* destination is CRC IPBYTE 8-bit register */
+                const uint32_t numTransData = ( (NumBytes > DMA_TRANSFER_LIMIT)
+                                              ? DMA_TRANSFER_LIMIT
+                                              : NumBytes
+                                              );
+                const uint32_t lastDataPos = (numTransData - 1u);       /* position of last data to be transferred in buffer */
+
+                pDevice->pReg->CTL |= (BITM_CRC_CTL_EN);                /* enable CRC (leave other bits unmodified) */
+
+                pADI_DMA0->EN_SET = channelBit;                         /* Enable the channel */
+                pADI_DMA0->ALT_CLR = channelBit;                        /* Set the primary as the current DMA descriptor */
+                pADI_DMA0->SRCADDR_CLR = channelBit;                    /* Ensure decrement for source is cleared */
+                pADI_DMA0->DSTADDR_CLR = channelBit;                    /* Ensure decrement for destination is cleared */
+
+                pPrimaryCCD[channelId].DMADSTEND = dst;                 /* destination is CRC IPBYTE 8-bit register */
+                pPrimaryCCD[channelId].DMASRCEND = src + lastDataPos;   /* source end address */
+                pPrimaryCCD[channelId].DMACDC =
+                    ( (((uint32_t) ADI_DMA_INCR_NONE)    << ((uint32_t) DMA_BITP_CTL_DST_INC))  /* destination address not incremented */
+                    | (((uint32_t) ADI_DMA_INCR_1_BYTE)  << ((uint32_t) DMA_BITP_CTL_SRC_INC))  /* source address incremented by 1 byte */
+                    | (((uint32_t) ADI_DMA_WIDTH_1_BYTE) << ((uint32_t) DMA_BITP_CTL_SRC_SIZE)) /* source data size is 1-byte */
+                    | ((numTransData - 1u)               << ((uint32_t) DMA_BITP_CTL_N_MINUS_1))/* number of DMA transfers (minus 1) */
+                    | (DMA_ENUM_CTL_CYCLE_CTL_AUTO_REQ   << DMA_BITP_CTL_CYCLE_CTL)             /* DMA Auto Request transmission */
+                    );
+                pDevice->pRemainingData = (void*) (src + numTransData); /* remaining data start address */
+                pDevice->RemainingBytes = NumBytes - numTransData;      /* remaining bytes */
+                pDevice->RemainingBits = NumBits;                       /* remaining bits if last byte is a partial byte */
+                bUseDma = true;                                         /* there are enough data to run 4-byte DMA transfers to CRC */
+            }
+        }
+
+        /* if we are in a position to use the DMA to transfer data to the CRC */
+        if (bUseDma== true)
+        {
+            const uint32_t channelId = (uint32_t) ADI_CFG_CRC_DMA_CHANNEL;
+            const uint32_t channelBit = 1ul << channelId;       /* get a value with the bit set at position identified by channelId */
+            pADI_DMA0->SWREQ = channelBit;                      /* Issue a software DMA request */
+        }
+        else
+        {
+            pDevice->pReg->CTL |= (BITM_CRC_CTL_EN);
+            crc_CalculateCrcForRemaining(pDevice, pData, NumBytes, NumBits);
+            pDevice->pReg->CTL &= ~(BITM_CRC_CTL_EN);
+            if(pDevice->pfCallback != NULL)
+            {
+                pDevice->pfCallback(pDevice->pCBParam, (uint32_t) ADI_CRC_EVENT_BUFFER_PROCESSED, pData);
+            }
+            pDevice->eCrcOpStatus = ADI_CRC_OP_IDLE;            /* CRC calculation completed */
+        }
+    }
+    return result;
+}
+
+/**
+ * @brief       Completes a DMA driven CRC operation by dealing with remaining
+ *              data, usually when the number of bytes left is smaller than 4.
+ *
+ * @param [in]  pDevice         Pointer to CRC device
+ * @param [in]  pData           Address of data buffer.
+ * @param [in]  NumBytes        Number of whole bytes in data buffer.
+ * @param [in]  NumBits         Number of bits, 0 to 7, in the last partial byte
+ *                              in CRC data buffer
+ */
+static void crc_CalculateCrcForRemaining(ADI_CRC_DEVICE *pDevice, uint8_t *pData, uint32_t NumBytes, uint32_t NumBits)
+{
+    /* process the remaining bytes */
+    while (NumBytes > 0u)
+    {
+        pDevice->pReg->IPBYTE = *pData;
+        pData++;
+        NumBytes--;
+    }
+
+    /* process the remaining bits in the last byte if the number of bits is smaller than 8 */
+    if (NumBits > 0u)
+    {
+        pDevice->pReg->IPBITS[NumBits] = *pData;
+    }
+}
+
+/**
+ * @brief       Callback function used by the DMA when a DMA error occurs
+ *
+ * @details     Callback function used by the DMA when a DMA error must be reported
+ *              to the CRC driver because it affects the DMA channel driving the CRC.
+ */
+static void CRC_Callback_For_DMA_Err_Int_Handler(void *pcbparam, uint32_t nEvent, void *pArg)
+{
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(pcbparam);
+
+    if (NULL != pDevice)
+    {
+        /* DMA error detected */
+        pDevice->eCrcOpStatus = ADI_CRC_OP_IDLE;                /* mark the CRC peripheral as IDLE */
+        pDevice->pReg->CTL &= (uint32_t)(~(BITM_CRC_CTL_EN));   /* disable CRC peripheral */
+    }
+}
+
+/**
+ * @brief       interrupt handler used by the software DMA channel driving the CRC
+ *
+ * @details     interrupt handler used by the software DMA channel driving the CRC
+ *              ADI_DMA_CRC_ISR is a macro with the final interrupt handler name
+ *              being DMA_SIP0_Int_Handler, ..., DMA_SIP7_Int_Handler, depending
+ *              on the software DMA channel driving the CRC.
+ */
+void ADI_DMA_CRC_ISR(void)
+{
+    ISR_PROLOG();
+
+    if (ADI_CRC_DEVICE_IN_USE(0))
+    {
+        ADI_CRC_DEVICE * pDevice = HDL_TO_DEVICE_PTR(crc_device_info[0].hDevice);
+        if (NULL != pDevice)
+        {
+            uint8_t *pData = (uint8_t *)(pDevice->pRemainingData);
+            uint32_t NumBytes = pDevice->RemainingBytes;
+            uint32_t NumBits = pDevice->RemainingBits;
+            bool finishing = (NumBytes < 4u);
+
+            if (!finishing)
+            {
+                /* there's enough data left for another DMA transfer */
+                ADI_CRC_RESULT result = pDevice->pfSubmitBuffer(pDevice, pData, NumBytes, NumBits);
+                if (ADI_CRC_SUCCESS != result)
+                {
+                    /* buffer submission failed: complete the task through core driven operations */
+                    finishing = true;
+                }
+            }
+
+            if (finishing)
+            {
+                /* There are a very few bytes/bits left to be processed or
+                 * a DMA transfer request could not be sent */
+                crc_CalculateCrcForRemaining(pDevice, pData, NumBytes, NumBits);
+
+                /* if a callback function is registered with the interrupt handler
+                 * associated with the software DMA channel driving the CRC */
+                if(pDevice->pfCallback != NULL)
+                {
+                    pDevice->pfCallback(pDevice->pCBParam, (uint32_t) ADI_CRC_EVENT_BUFFER_PROCESSED, NULL);
+                }
+                pDevice->eCrcOpStatus = ADI_CRC_OP_IDLE;        /* CRC back in idle state */
+
+            }
+        }
+    }
+
+#if defined(ADI_CYCLECOUNT_CRC_ISR_ENABLED) && (ADI_CYCLECOUNT_CRC_ISR_ENABLED == 1u)
+    ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_CRC);    
+#endif
+
+    ISR_EPILOG();
+}
+
+#endif  /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */
+
+/*! \endcond */
+
+/*=============  P U B L I C   F U N C T I O N S =============*/
+
+/**
+ * @brief       Opens a CRC device instance.
+ *
+ * @param [in]  DeviceNum       Number identifying the CRC Device to open.
+ * @param [in]  pMemory         Pointer to a #ADI_CRC_MEMORY_SIZE.
+ *                              sized buffer to manage the device instance.
+ * @param [in]  MemorySize      Size of the buffer to which "pMemory" points.
+ * @param [out] phDevice        Pointer to a location where CRC device handle to be written.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Successfully opened a CRC device.
+ *              - #ADI_CRC_BAD_DEVICE_NUMBER [D]: Supplied CRC Device ID is invalid.
+ *              - #ADI_CRC_IN_USE [D]: Supplied CRC Device ID is already in use.
+ *              - #ADI_CRC_INSUFFICIENT_MEMORY [D]: Supplied memory is not sufficient to handle a CRC device instance.
+ *              - #ADI_CRC_FAILURE [D]: callback registration failed for CRC function used by DMA Error Interrupt Handler.
+ *
+ * @note        For the device memory should be of size #ADI_CRC_MEMORY_SIZE.
+ *
+ */
+ADI_CRC_RESULT adi_crc_Open(
+	uint32_t            DeviceNum,
+	void                *pMemory,
+	uint32_t            MemorySize,
+	ADI_CRC_HANDLE      *phDevice)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = (ADI_CRC_DEVICE*) pMemory;/* memory block to be used to manage a CRC driver instance */
+
+#ifdef ADI_DEBUG                                        /* IF (Debug information enabled) */
+    if (!ADI_CRC_VALID_DEVICE_ID(DeviceNum))            /* IF (This is not a valid CRC device number) */
+    {
+        result = ADI_CRC_BAD_DEVICE_NUMBER;             /* Report failure as bad device number */
+    }
+    else if (ADI_CRC_DEVICE_IN_USE(DeviceNum))          /* IF (The device is in use) */
+    {
+        result = ADI_CRC_IN_USE;                        /* return CRC Device in use error */
+    }
+    else if (  (MemorySize < ADI_CRC_MEMORY_SIZE)       /* IF (Supplied memory size is insufficient) */
+            || (ADI_CRC_MEMORY_SIZE < sizeof(ADI_CRC_DEVICE))
+            )
+    {
+        result = ADI_CRC_INSUFFICIENT_MEMORY;           /* Report failure as insufficient memory */
+    }
+    else
+#endif  /* ADI_DEBUG */
+    {
+        /* check that ADI_CRC_MEMORY_SIZE is accurately defined */
+        assert(ADI_CRC_MEMORY_SIZE == sizeof(ADI_CRC_DEVICE));
+
+        memset(pMemory, 0, MemorySize);                 /* Clear the given memory */
+
+        ADI_INT_STATUS_ALLOC();
+        ADI_ENTER_CRITICAL_REGION();                    /* Entering critical region, disable interrupts */
+
+            /* Save the supplied device memory address */
+            crc_device_info[DeviceNum].hDevice = (ADI_CRC_HANDLE)pDevice;
+            pDevice->pReg = crc_device_info[DeviceNum].pReg;
+
+        ADI_EXIT_CRITICAL_REGION();                     /* Re-enable interrupts */
+
+        crc_ResetRegisters(pDevice);                    /* Reset CRC registers */
+        *phDevice = crc_device_info[DeviceNum].hDevice; /* Pass a valid handle to this CRC device */
+
+#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT == 0)
+
+        pDevice->pfSubmitBuffer = &crc_ExecuteCoreDrivenOperation;
+
+#else   /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */
+
+        pDevice->pfSubmitBuffer = &crc_ExecuteDmaDrivenOperation;
+        adi_dma_Init();
+
+        /* Register CRC DMA callback */
+#ifdef ADI_DEBUG                                        /* IF (Debug information enabled) */
+        if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(ADI_CFG_CRC_DMA_CHANNEL,CRC_Callback_For_DMA_Err_Int_Handler,pDevice))
+        {
+            result = ADI_CRC_FAILURE;
+        }
+#else
+        adi_dma_RegisterCallback(ADI_CFG_CRC_DMA_CHANNEL,CRC_Callback_For_DMA_Err_Int_Handler,pDevice);
+#endif
+        NVIC_EnableIRQ(ADI_CRC_IRQ_ID);                 /* Enable the interrupt for the DMA channel used by CRC */
+#endif  /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */
+    }
+    return result;
+}
+
+/**
+ * @brief       Closes CRC device instance opened for use.
+ *
+ * @param [in]  hDevice         Handle to CRC Device instance to close.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Successfully closed CRC device.
+ *              - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid.
+ *              - #ADI_CRC_FAILURE [D]: callback un-registration failed for CRC function used by DMA Error Interrupt Handler.
+ */
+ADI_CRC_RESULT adi_crc_Close(ADI_CRC_HANDLE const hDevice)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_INFO *pCrcInfo = crc_DeviceInfo(hDevice);   /* get CRC info pointer from CRC handle */
+#ifdef ADI_DEBUG
+    if (NULL == pCrcInfo)
+    {
+        result = ADI_CRC_BAD_HANDLE;                    /* invalid CRC handle being used */
+    }
+    else
+#endif
+    {
+#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT != 0)
+        NVIC_DisableIRQ(ADI_CRC_IRQ_ID);                /* Disable the interrupt for the DMA channel used by CRC. */
+        /* Register CRC DMA callback */
+#ifdef ADI_DEBUG                                        /* IF (Debug information enabled) */
+        if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(ADI_CFG_CRC_DMA_CHANNEL,NULL,NULL))
+        {
+            result = ADI_CRC_FAILURE;
+        }
+#else
+        adi_dma_RegisterCallback(ADI_CFG_CRC_DMA_CHANNEL,NULL,NULL);
+#endif
+#endif
+        pCrcInfo->hDevice = NULL;                       /* Mark CRC driver as closed */
+    }
+    return result;
+}
+/*!
+ * @brief       Set the bit mirroring. This function should be called only when device is idle,
+ *              i.e. when no data are being processd by the CRC.
+ *
+ * @param[in]   hDevice     Device handle obtained from adi_crc_Open().
+ * @param[in]   bEnable     Boolean flag to enable/disable bit mirroring.
+ *                          true : To Enable bit mirroring.
+ *                          false :  To Disable bit mirroring.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Call completed successfully.
+ *              - #ADI_CRC_BAD_HANDLE [D] :Invalid device handle parameter.
+ *              - #ADI_CRC_FN_NOT_PERMITTED [D]: CRC is executing a request, its parameters cannot be altered.
+ *
+ * @sa          adi_crc_SetByteMirroring().
+ * @sa          adi_crc_SetWordSwap().
+ */
+ADI_CRC_RESULT adi_crc_SetBitMirroring(ADI_CRC_HANDLE const hDevice, const bool bEnable)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);       /* get CRC device pointer from CRC handle */
+
+#ifdef ADI_DEBUG
+    if (NULL == pDevice)                                        /* IF (CRC device handle is invalid) */
+    {
+        result = ADI_CRC_BAD_HANDLE;
+    }
+    else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice))                  /* IF (CRC in progress) */
+    {
+        result = ADI_CRC_FN_NOT_PERMITTED;                      /* Function not permitted when CRC operation is in progress */
+    }
+    else
+#endif
+    if(bEnable == true)
+    {
+        pDevice->pReg->CTL |= (BITM_CRC_CTL_BITMIRR);                   /* enable bit mirroring */
+    }
+    else
+    {
+        pDevice->pReg->CTL &= (uint32_t)(~(BITM_CRC_CTL_BITMIRR));      /* disable bit mirroring */
+    }
+    return result;
+}
+/*!
+ * @brief       Set the byte mirroring. This function should be called only when device is disabled.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_crc_Open().
+ * @param[in]   bEnable    Boolean flag to enable/disable byte mirroring.
+ *                         true  : To Enable byte mirroring.
+ *                         false : To Disable byte mirroring.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Call completed successfully.
+ *              - #ADI_CRC_BAD_HANDLE [D]: Invalid device handle parameter.
+ *              - #ADI_CRC_FN_NOT_PERMITTED [D]: CRC is executing a request, its parameters cannot be altered.
+ *
+ *
+ * @sa        adi_crc_EnableBitMirroring().
+ * @sa        adi_crc_EnableWordSwap().
+ */
+ADI_CRC_RESULT  adi_crc_SetByteMirroring(ADI_CRC_HANDLE const hDevice, const bool bEnable)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);       /* get CRC device pointer from CRC handle */
+
+#ifdef ADI_DEBUG
+    if (NULL == pDevice)                                        /* IF (CRC device handle is invalid) */
+    {
+        result = ADI_CRC_BAD_HANDLE;
+    }
+    else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice))                  /* IF (CRC in progress) */
+    {
+        result = ADI_CRC_FN_NOT_PERMITTED;                      /* Function not permitted when CRC operation is in progress */
+    }
+    else
+#endif
+    if(bEnable == true)
+    {
+       pDevice->pReg->CTL |= (BITM_CRC_CTL_BYTMIRR);                    /* enable byte mirroring */
+    }
+    else
+    {
+       pDevice->pReg->CTL &= (uint32_t)(~(BITM_CRC_CTL_BYTMIRR));       /* disable byte mirroring */
+    }
+    return result;
+}
+
+/*!
+ * @brief       Enable the LSB first.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_crc_Open().
+ * @param[in]   bEnable    Boolean flag which indicate whether LSB first OR MSB first for CRC calculation.
+ *                         true  : For LSB First CRC calculation
+ *                         false : For MSB First CRC calculation
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Call completed successfully.
+ *              - #ADI_CRC_BAD_HANDLE [D]: Invalid device handle parameter.
+ *              - #ADI_CRC_FN_NOT_PERMITTED [D]: CRC is executing a request, its parameters cannot be altered.
+ *
+ *
+ * @sa          adi_crc_EnableBitmirroring().
+ * @sa          adi_crc_EnableWordSwap().
+ */
+
+ADI_CRC_RESULT  adi_crc_SetLSBFirst(ADI_CRC_HANDLE const hDevice, const bool bEnable)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);       /* get CRC device pointer from CRC handle */
+
+#ifdef ADI_DEBUG
+    if (NULL == pDevice)                                        /* IF (CRC device handle is invalid) */
+    {
+        result =  ADI_CRC_BAD_HANDLE;
+    }
+    else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice))                  /* IF (CRC in progress) */
+    {
+        result = ADI_CRC_FN_NOT_PERMITTED;                      /* function not permitted when CRC operation is in progress */
+    }
+    else
+#endif
+    if(bEnable == true)
+    {
+       pDevice->pReg->CTL |= (BITM_CRC_CTL_LSBFIRST);           /* enable LSB first (MSB first disable) */
+    }
+    else
+    {
+       pDevice->pReg->CTL &= ~(BITM_CRC_CTL_LSBFIRST);          /* disable LSB first (MSB first enable) */
+    }
+    return result;
+}
+/*!
+ * @brief       To enable/disable the word Swap. This function should be called only when device is disabled.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_crc_Open().
+ * @param[in]   bEnable    Boolean flag to enable/disable word swap.
+ *                         true  : To Enable word swap.
+ *                         false : To Disable word swap.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Call completed successfully.
+ *              - #ADI_CRC_BAD_HANDLE [D]: Invalid device handle parameter.
+ *              - #ADI_CRC_FN_NOT_PERMITTED [D]: CRC is executing a request, its parameters cannot be altered.
+ *
+ *
+ * @sa          adi_crc_SetBitMirroring().
+ * @sa          adi_crc_SetByteMirroring().
+ */
+ADI_CRC_RESULT adi_crc_EnableWordSwap(ADI_CRC_HANDLE const hDevice, const bool bEnable)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);
+
+#ifdef ADI_DEBUG
+    if (NULL == pDevice)                                /* IF (CRC device handle is invalid) */
+    {
+        result = ADI_CRC_BAD_HANDLE;
+    }
+    else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice))          /* IF (CRC in progress) */
+    {
+        result = ADI_CRC_FN_NOT_PERMITTED;              /* function not permitted when CRC operation is in progress */
+    }
+    else
+#endif
+    if(bEnable == true)
+    {
+       pDevice->pReg->CTL |= BITM_CRC_CTL_W16SWP;       /* enable word swap */
+    }
+    else
+    {
+       pDevice->pReg->CTL &= ~BITM_CRC_CTL_W16SWP;      /* disable word swap */
+    }
+
+    return result;
+}
+/**
+ * @brief       Sets the initial seed value for the CRC operation that is about to take place.
+ *
+ * @param [in]  hDevice         Handle to CRC device instance to work on.
+ * @param [in]  CrcSeedVal      Initial seed value for the CRC operation that is about to take place.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Successfully set CRC seed value.
+ *              - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid.
+ *              - #ADI_CRC_FN_NOT_PERMITTED [D] : Function not permitted when CRC operation is in progress.
+ *
+ */
+ADI_CRC_RESULT adi_crc_SetCrcSeedVal(
+    ADI_CRC_HANDLE const    hDevice,
+    uint32_t                CrcSeedVal)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);
+
+#ifdef ADI_DEBUG
+    if (NULL == pDevice)                                /* IF (CRC device handle is invalid) */
+    {
+        result = ADI_CRC_BAD_HANDLE;
+    }
+    else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice))          /* IF (CRC in progress) */
+    {
+        result = ADI_CRC_FN_NOT_PERMITTED;              /* function not permitted when CRC operation is in progress */
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        pDevice->pReg->RESULT = CrcSeedVal;             /* Load the CRC seed value */
+    }
+    return result;
+}
+
+/**
+ * @brief       Sets the 32-bit polynomial for CRC operations.
+ *
+ * @param [in]  hDevice         Handle to CRC device instance to work on.
+ * @param [in]  PolynomialVal   32-bit CRC polynomial to use for CRC operation.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Successfully set polynomial value.
+ *              - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid.
+ *              - #ADI_CRC_FN_NOT_PERMITTED [D]: Function not permitted when CRC operation is in progress.
+ *
+ */
+ADI_CRC_RESULT adi_crc_SetPolynomialVal(
+    ADI_CRC_HANDLE const    hDevice,
+    uint32_t                PolynomialVal)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);
+
+#ifdef ADI_DEBUG
+    if (NULL == pDevice)                                /* IF (CRC device handle is invalid) */
+    {
+        result = ADI_CRC_BAD_HANDLE;
+    }
+    else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice))          /* IF (CRC in progress) */
+    {
+        result = ADI_CRC_FN_NOT_PERMITTED;              /* function not permitted when CRC operation is in progress */
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        pDevice->pReg->POLY = PolynomialVal;            /* Load Polynomial value */
+    }
+    return result;
+}
+
+/**
+ * @brief       Submits data buffer for CRC computation
+ *
+ * @details     This API can be used to submit data buffer for CRC computation.
+ *              If NumBits is in [0..7] then the number of bytes to be processed
+ *              is NumBytes plus one partial byte containing NumBits bits.
+ *              If DMA mode of operation is selected, buffer is processed using
+ *              the specified DMA channel.
+ *
+ * @param [in]  hDevice         Handle of CRC device
+ * @param [in]  pCrcBuf         Address of CRC data buffer
+ * @param [in]  NumBytes        Number of whole bytes in CRC data buffer
+ * @param [in]  NumBits         Number of bits, 0 to 7, in the last partial byte
+ *                              in CRC data buffer
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Successfully submitted data buffer.
+ *              - #ADI_CRC_INVALID_PARAMETER [D]: one of the parameter used is invalid.
+ *              - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid.
+ *              - #ADI_CRC_FN_NOT_SUPPORTED [D]: Function not supported by this CRC revision.
+ *              - #ADI_CRC_FN_NOT_PERMITTED [D]: Function not permitted when CRC operation is in progress.
+ *              - #ADI_CRC_INVALID_DMA_CHANNEL: DMA channel cannot be used with CRC (from crc_DmaDrivenOperation)
+ */
+ADI_CRC_RESULT adi_crc_Compute(
+    ADI_CRC_HANDLE const    hDevice,
+    void                    *pCrcBuf,
+    uint32_t                NumBytes,
+    uint32_t                NumBits)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);
+#ifdef ADI_DEBUG
+    if (NumBits >= 8u)
+    {
+        result = ADI_CRC_INVALID_PARAMETER;
+    }
+    else if (NULL == pDevice)
+    {
+        result = ADI_CRC_BAD_HANDLE;
+    }
+    else if (((pDevice->pReg->CTL & BITM_CRC_CTL_REVID) == 0u) && (NumBits != 0u))
+    {
+        result = ADI_CRC_FN_NOT_SUPPORTED;      /* Partial byte needs CRC unit revision 1 or up */
+    }
+    else
+    if (!ADI_CRC_DEVICE_IS_IDLE(pDevice))       /* IF (CRC in progress) */
+    {
+        result = ADI_CRC_FN_NOT_PERMITTED;      /* function not permitted when CRC operation is in progress */
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        pDevice->eCrcOpStatus = ADI_CRC_OP_IN_PROGRESS; /* mark the CRC as in progress */
+        result = pDevice->pfSubmitBuffer(pDevice, pCrcBuf, NumBytes, NumBits);
+
+        /* CRC returns in IDLE mode when it has processed all its data, not after submitting a request */
+    }
+    return result;
+}
+
+/**
+ * @brief       Gets the current CRC peripheral status.
+ *
+ * @param [in]  hDevice         Handle to CRC device instance to work on
+ * @param [in]  pbCrcInProgress Pointer to location to store the current status of CRC peripheral.
+ *                              'true' when CRC peripheral is in currently performing a CRC operation.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Successfully set expected CRC result.
+ *              - #ADI_CRC_BAD_HANDLE [D}: Supplied CRC handle is invalid.
+ *
+ * @note        This function is valid only when device is operating in DMA mode.
+ *
+ */
+ADI_CRC_RESULT adi_crc_IsCrcInProgress(
+    ADI_CRC_HANDLE const    hDevice,
+    bool                    *pbCrcInProgress)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);
+
+#ifdef ADI_DEBUG
+    if (NULL == pDevice)        /* IF (CRC device handle is invalid) */
+    {
+        result = ADI_CRC_BAD_HANDLE;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+
+      if ((pDevice)->eCrcOpStatus == ADI_CRC_OP_IN_PROGRESS) 
+      {
+                *pbCrcInProgress = true;
+
+      } 
+      else 
+      {
+                *pbCrcInProgress = false;
+
+      }
+    }
+    return result;
+}
+
+/**
+ * @brief       Gets the final CRC result computed for a data stream
+ *
+ * @details     This API gets the final CRC result computed for a data stream
+ *              and clears the current and final CRC results register.
+ *              The CRC Current result register holds the current or
+ *              intermediate CRC result. Whenever a CRC operation is initiated,
+ *              the CRC peripheral takes the CRC Current register value as
+ *              initial seed for CRC computation. This API clears both results
+ *              register to start a fresh CRC computation.
+ *              Use the adi_crc_GetCurrentCrcVal() API to get an intermediate
+ *              CRC result without clearing the results register.
+ *
+ * @param [in]  hDevice         Handle to CRC device instance to work on
+ * @param [out] pFinalCrcVal    Pointer to location where the final CRC result of
+ *                              a data stream to be processed will be written.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Successfully read final CRC result.
+ *              - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid.
+ */
+ADI_CRC_RESULT adi_crc_GetFinalCrcVal(
+    ADI_CRC_HANDLE const    hDevice,
+    uint32_t               *pFinalCrcVal)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);
+
+#ifdef ADI_DEBUG
+    if (NULL == pDevice)        /* IF (CRC device handle is invalid) */
+    {
+        result = ADI_CRC_BAD_HANDLE;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        const uint32_t seed_value = (uint32_t) ADI_CFG_CRC_SEED_VALUE;
+        *pFinalCrcVal = pDevice->pReg->RESULT;  /* Get the final CRC result */
+        pDevice->pReg->RESULT = seed_value;
+    }
+    return result;
+}
+
+/**
+ * @brief       Gets the current/intermediate CRC result computed for a data stream.
+ *
+ * @param [in]  hDevice           Handle to CRC device instance to work on
+ * @param [out] pCurrentCrcVal    Pointer to location where the intermediate CRC result of
+ *                                a data stream to be processed will be written.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Successfully read current CRC result.
+ *              - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid.
+ */
+ADI_CRC_RESULT adi_crc_GetCurrentCrcVal(
+    ADI_CRC_HANDLE const    hDevice,
+    uint32_t                *pCurrentCrcVal)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);
+
+#ifdef ADI_DEBUG
+    if (NULL == pDevice)                                /* IF (CRC device handle is invalid) */
+    {
+        result = ADI_CRC_BAD_HANDLE;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        *pCurrentCrcVal = pDevice->pReg->RESULT;        /* Get the current CRC result */
+    }
+
+    return result;
+}
+
+/**
+ * @brief       Registers or unregisters a callback with the CRC device
+ *
+ * @details     It is not required to register a callback for the operation of the
+ *              driver. Data compare or DMA error will be notified via the
+ *              adi_crc_IsCrcInProgress() API. But if an application requires the
+ *              errors/events to be notified immediately it can register a callback
+ *              with the driver which will be called to notify errors/events.
+ *
+ *              When a callback is registered the API adi_crc_IsCrcInProgress()
+ *              will not return error.
+ *
+ * @param  [in]  hDevice        Handle to CRC device instance to work on
+ * @param  [in]  pfCallback     Pointer to application callback function. The callback function
+ *                              has the prototype
+ *                              void callback(void *pCBParam, uint32_t nEvent, void *pArg)
+ *                              To unregister a callback pass the the pointer to the callback
+ *                              function as NULL.
+ * @param  [in]  pCBParam       Callback parameter which will be returned back to the
+ *                              application when the callback function is called.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Successfully registered callback.
+ *              - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid.
+ */
+ADI_CRC_RESULT adi_crc_RegisterCallback(
+    ADI_CRC_HANDLE const    hDevice,
+    ADI_CALLBACK            pfCallback,
+    void *const             pCBParam)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);
+
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();                /* Entering critical region, disable interrupts */
+
+#ifdef ADI_DEBUG
+    if (NULL == pDevice)                        /* IF (CRC device handle is invalid) */
+    {
+        result = ADI_CRC_BAD_HANDLE;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        /* Update CRC Callback information */
+        pDevice->pfCallback = pfCallback;
+        pDevice->pCBParam   = pCBParam;
+    }
+
+    ADI_EXIT_CRITICAL_REGION();                 /* Re-enable interrupts */
+
+    return result;
+}
+
+
+/*****/
+
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crc/adi_crc_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crc/adi_crc_def.h
new file mode 100755
index 00000000000..73cdd6c9e7e
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crc/adi_crc_def.h
@@ -0,0 +1,93 @@
+/*! *****************************************************************************
+ * @file:    adi_crc_def.h
+ * @brief:   Private header file for for CRC driver.
+ * @details
+ *           This is a private header file for the CRC driver,
+ *           which contains the API declarations, data and
+ *           constant definitions used in driver implementation
+ -----------------------------------------------------------------------------
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_CRC_DEF_H
+#define ADI_CRC_DEF_H
+
+/* CRC Driver includes */
+#include <drivers/crc/adi_crc.h>
+
+/*! \cond PRIVATE */
+
+typedef struct __ADI_CRC_DEVICE ADI_CRC_DEVICE;
+typedef ADI_CRC_RESULT (*CRC_BUFFER_SUBMIT) (ADI_CRC_DEVICE *pDevice, void *pBuffer, uint32_t NumBytes, uint32_t NumBits);
+
+/* Enumeration of CRC operation status */
+typedef enum
+{
+    ADI_CRC_OP_IDLE             = 0u,           /* CRC idle */
+    ADI_CRC_OP_IN_PROGRESS      = 0x01u,        /* CRC operation in progress */
+} ADI_CRC_OP_STATUS;
+
+#pragma pack(push)
+#pragma pack()
+
+/* Structure to handle CRC Peripheral instance */
+struct __ADI_CRC_DEVICE
+{
+    volatile ADI_CRC_TypeDef    *pReg;
+    CRC_BUFFER_SUBMIT           pfSubmitBuffer;         /* Function for submitting CRC data buffer for calculation */
+    ADI_CALLBACK                pfCallback;             /* Client supplied callback function */
+    void                        *pCBParam;              /* Client supplied callback parameter */
+    void                        *pRemainingData;        /* Pointer to the buffer containing remaining bytes */
+    uint32_t                    RemainingBytes;         /* Remaining bytes */
+    uint32_t                    RemainingBits;          /* Remaining bits */
+    ADI_CRC_OP_STATUS           eCrcOpStatus;           /* Current status of the CRC Operation */
+};
+
+/* Structure to hold CRC device specific information */
+typedef struct
+{
+    volatile ADI_CRC_TypeDef    *pReg;        /* CRC peripheral Registers */
+    ADI_CRC_HANDLE              hDevice;      /* CRC device handle */
+} ADI_CRC_INFO;
+
+#pragma pack(pop)
+/*! \endcond */
+
+#endif  /* ADI_CRC_DEF_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crypto/adi_crypto.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crypto/adi_crypto.c
new file mode 100755
index 00000000000..45bb0f6ebf4
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crypto/adi_crypto.c
@@ -0,0 +1,1624 @@
+/*! *****************************************************************************
+ * @file:    adi_crypto.c
+ * @brief:   CRYPTO device driver source file.
+ * @details: This is the Crypto driver implementation file.
+ -----------------------------------------------------------------------------
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+/*! \addtogroup Crypto_Driver Crypto Driver
+ *  @{
+ *
+ *  @brief <b>Crypto Driver</b>
+ *
+ *  @details
+ *
+ *  The Crypto controller provides hardware acceleration of various AES cryptographic
+ *  cipher modes, including: ECB, CBC, CTR, CMAC, CCM, SHA-256 and Keyed HMAC; as well
+ *  as Protected Key Storage (PKSTOR) operations for safely storing and using encrypted
+ *  keys.  The Crypto block works most efficiently in DMA mode due to the large about
+ *  of data I/O which would otherwise incur a lot of PIO-mode interrupt traffic to manually
+ *  pump data.
+ *
+ *  <b>Crypto Driver Static Configuration</b>
+ *
+ *  A number of Crypto cipher modes are able to be configured statically, such that
+ *  if particular mode(s) are not required, the resulting driver footprint can be reduced
+ *  internally by blocking out chunks of code that are not needed.
+ *
+ * @note - The application must include drivers/crypto/adi_crypto.h to use this driver.
+ * @note - This driver optionally uses the DMA driver if DMA is selected and active.
+ *         In this case, the application must include the DMA driver sources to resolve
+ *         DMA symbols.
+ */
+
+
+/*========  I N C L U D E  ========*/
+
+/*! \cond PRIVATE */
+#include <adi_processor.h>
+#include <assert.h>
+#include <string.h>
+
+/* main crypto include file */
+#include <drivers/crypto/adi_crypto.h>
+
+/* private crypto defines */
+#include "adi_crypto_def.h"
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+/* dma interface */
+#include <drivers/dma/adi_dma.h>
+#endif
+
+
+/*========  D E F I N E S   ========*/
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm123 (rule  8.5): there shall be no definition of objects or functions in a header file
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+* Pm050 (rule 14.2): a null statement shall only occur on a line by itself
+* Pm088 (rule 17.4): pointer arithmetic should not be used.
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+* Pm152 (rule 17.4): array indexing shall only be applied to objects defined as an array type
+*/
+#pragma diag_suppress=Pm123,Pm140,Pm050,Pm088,Pm073,Pm143,Pm152
+#endif /* __ICCARM__ */
+
+/* Utility Macros */
+#define CLR_BITS(REG,BITS)                        ((REG) &= ~(BITS))
+#define SET_BITS(REG,BITS)                        ((REG) |= (BITS))
+#define IS_ANY_BIT_SET(REG,BITS)                  (((REG) & (BITS)) != 0u)
+
+
+/* Number of crypto device for the given processor */
+#define NUM_DEVICES                               (1u)
+
+/* Compiler-specific mapping of assembly-level byte-swap instruction
+   IAR is "__REV", and we think Keil is "__rev", but lets see how that
+   goes when it is undefined for Keil.
+*/
+#if defined ( __ICCARM__ )
+#define __ADI_BYTE_SWAP(X)                        __REV(X)
+#elif defined (__GNUC__)
+#define __ADI_BYTE_SWAP(X)                        __builtin_bswap32(X)
+#elif defined (__ARMCC_VERSION)
+#define __ADI_BYTE_SWAP(X)                        __rev(X)
+#else
+#error "This toolchain is not supported"
+#endif
+
+
+/*========  L O C A L    F U N C    D E C L  ========*/
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+static void dmaCallback                      (void *pCBParam, uint32_t Event, void *pArg);
+#endif
+
+#ifdef ADI_DEBUG
+/* Validatation routines */
+static ADI_CRYPTO_RESULT ValidateHandle      (ADI_CRYPTO_HANDLE const hDevice);
+static ADI_CRYPTO_RESULT ValidateUserBuffer  (ADI_CRYPTO_TRANSACTION * const pBuffer);
+#endif
+
+/* Generate a uint32_t value from a pointer to a uint8_t buffer */
+static uint32_t u32FromU8p                   (uint8_t * const pFourBytes);
+
+/* load KEY registers with provided key */
+static void loadAesKey                       (uint8_t * const pKey, ADI_CRYPTO_AES_KEY_LEN const keyLen);
+
+/* Initialize the internal device handle object (user memory) */
+static void InitializeDevData                (ADI_CRYPTO_HANDLE const hDevice);
+
+/* Initiate the computation for a buffer */
+static void StartCompute                     (ADI_CRYPTO_HANDLE const hDevice);
+
+/* Stop the device */
+static void StopCompute                      (ADI_CRYPTO_HANDLE const hDevice);
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+static void programDMA                       (ADI_CRYPTO_HANDLE const hDevice);
+#endif
+
+/* PIO mode write input data */
+static void writePioInputData                (ADI_CRYPTO_HANDLE const hDevice, uint32_t const status);
+
+/* PIO mode read output data */
+static void readPioOutputData                (ADI_CRYPTO_HANDLE const hDevice, uint32_t const status);
+
+/* Flush the input and output buffers */
+static void FlushInputOutputRegisters        (ADI_CRYPTO_HANDLE const hDevice);
+
+
+/* pre-defined Crypto interrupt handler prototypes, as linked in IVT */
+void Crypto_Int_Handler(void);
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+void DMA_AES0_IN_Int_Handler (void);
+void DMA_AES0_OUT_Int_Handler (void);
+#endif
+
+
+/*========  D A T A  ========*/
+/* Internal device structure */
+
+static CRYPTO_INFO CryptoDevInfo[] = {
+    {pADI_CRYPT0,          /* physical device controller pointer */
+     NULL,                 /* hDevice */
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+     DMA0_CH13_DONE_IRQn,  /* DMA input interrupt number */
+     DMA0_CH14_DONE_IRQn,  /* DMA output interrupt number */
+     AES0_IN_CHANn,        /* DMA input channel */
+     AES0_OUT_CHANn,       /* DMA output channel */
+     ADI_CRYPTO_SUCCESS,   /* DMA error state */
+#endif
+    }
+};
+
+/*! \endcond */
+
+/*========  C O D E  ========*/
+
+
+/* include PKSTOR extensions into CRYPTO driver... */
+#if (1 == ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT)
+#include "adi_pkstor.c"
+#endif
+
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+
+/* Internal Crypto registered DMA Callback for receiving DMA
+   fault notifications from the shared DMA error handler */
+static void dmaCallback(void *pCBParam, uint32_t Event, void *pArg)
+{
+    /* recover device handle */
+    ADI_CRYPTO_HANDLE hDevice = CryptoDevInfo[0].hDevice;
+
+    /* recover failing channel number */
+    uint32_t failingChannel = (uint32_t)pCBParam;
+
+    /* save the DMA error */
+    switch (Event) {
+        case ADI_DMA_EVENT_ERR_BUS:
+            hDevice->dmaErrorCode = ADI_CRYPTO_ERR_DMA_BUS_FAULT;
+            break;
+        case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR:
+            hDevice->dmaErrorCode = ADI_CRYPTO_ERR_DMA_INVALID_DESCR;
+            break;
+        default:
+            hDevice->dmaErrorCode = ADI_CRYPTO_ERR_DMA_UNKNOWN_ERROR;
+            break;
+    }
+
+    /* transfer is toast... post semaphore to unblock any waiters */
+    SEM_POST(hDevice);
+
+    /* call user's callback */
+    if (0u != hDevice->pfCallback) {
+        hDevice->pfCallback (hDevice->pCBParam, (uint32_t)hDevice->dmaErrorCode, (void*)failingChannel);
+    }
+
+    /* game over... */
+    StopCompute(hDevice);
+}
+#endif
+
+
+#ifdef ADI_DEBUG
+/* Validate the given handle */
+static ADI_CRYPTO_RESULT ValidateHandle(ADI_CRYPTO_HANDLE const hDevice)
+{
+    ADI_CRYPTO_RESULT result = ADI_CRYPTO_ERR_BAD_DEV_HANDLE;
+    uint32_t x;
+
+    for (x = 0u; x < NUM_DEVICES; x++) {
+        if (CryptoDevInfo[x].hDevice == hDevice) {
+            result = ADI_CRYPTO_SUCCESS;
+            break;
+        }
+    }
+
+    return result;
+}
+#endif
+
+
+#ifdef ADI_DEBUG
+static ADI_CRYPTO_RESULT ValidateUserBuffer(ADI_CRYPTO_TRANSACTION * const pBuffer)
+{
+
+    /* null pointer and zero count checks */
+    if (
+           (pBuffer->pInputData     == NULL)
+        || (pBuffer->numInputBytes  == 0u)
+        || (pBuffer->pOutputData    == NULL)
+        || (pBuffer->numOutputBytes == 0u)
+        || (
+               (pBuffer->eAesByteSwap != ADI_CRYPTO_AES_LITTLE_ENDIAN)
+            && (pBuffer->eAesByteSwap != ADI_CRYPTO_AES_BIG_ENDIAN))
+            )
+    {
+        return ADI_CRYPTO_ERR_BAD_BUFFER;
+    }
+
+    /* check buffer pointers for 32-bit alignment */
+    if ( (0u != (3u & (uint32_t)pBuffer->pAuthData)) || (0u != (3u & (uint32_t)pBuffer->pInputData)) || (0u != (3u & (uint32_t)pBuffer->pOutputData)) ) {
+        return ADI_CRYPTO_ERR_BAD_BUFFER;
+    }
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+    /* check buffer sizes for max DMA size */
+    if ((MAX_CRYPTO_DMA_BYTES < pBuffer->numAuthBytes) || (MAX_CRYPTO_DMA_BYTES < pBuffer->numInputBytes) || (MAX_CRYPTO_DMA_BYTES < pBuffer->numOutputBytes)) {
+        return ADI_CRYPTO_ERR_BAD_BUFFER;
+    }
+#endif
+
+#if ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1
+    if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_SHA)
+    {
+        /* SHA output digest is 256-bit and hence the output buffer size should be at least 32 bytes */
+        if (pBuffer->numOutputBytes < SHA_OUTPUT_SIZE_IN_BYTES) {
+            return ADI_CRYPTO_ERR_BAD_BUFFER;
+        }
+    }
+    else
+#endif
+    {
+
+#if ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1
+        if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_CMAC) {
+            /* CMAC output is always a 128-bit block */
+            if (pBuffer->numOutputBytes < CRYPTO_INPUT_SIZE_IN_BYTES) {
+                return ADI_CRYPTO_ERR_BAD_BUFFER;
+            }
+        }
+        else
+#endif
+        {
+            if (
+                   (pBuffer->pKey == NULL)
+                || (   (pBuffer->eAesKeyLen  != ADI_CRYPTO_AES_KEY_LEN_128_BIT)
+                    && (pBuffer->eAesKeyLen  != ADI_CRYPTO_AES_KEY_LEN_256_BIT))
+                || (   (pBuffer->eCodingMode != ADI_CRYPTO_ENCODE)
+                    && (pBuffer->eCodingMode != ADI_CRYPTO_DECODE)))
+            {
+                return ADI_CRYPTO_ERR_BAD_CONFIG;
+            }
+
+#if ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1
+            if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_CTR)
+            {
+                if ((pBuffer->CounterInit & (0xFFF00000u)) != 0u) {
+                    return ADI_CRYPTO_ERR_BAD_BUFFER;
+                }
+            }
+#endif
+
+#if ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1
+            if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_CCM)
+            {
+                if ( ((pBuffer->CounterInit & (0xFFFF0000u)) != 0u)
+                    ||  (   (pBuffer->pAuthData != NULL)
+                                && (
+                                       (pBuffer->numAuthBytes == 0u)
+                                    || (pBuffer->numValidBytes == 0u)
+                                    || (pBuffer->numValidBytes > CRYPTO_INPUT_SIZE_IN_BYTES)
+                                    || (pBuffer->numOutputBytes < (pBuffer->numInputBytes + CRYPTO_INPUT_SIZE_IN_BYTES))
+                                    )
+                        )
+                 )
+                {
+                    return ADI_CRYPTO_ERR_BAD_BUFFER;
+                }
+            }
+            else
+#endif
+            {
+                if (pBuffer->numOutputBytes < pBuffer->numInputBytes)
+                {
+                    return ADI_CRYPTO_ERR_BAD_BUFFER;
+                }
+            }
+        }
+    }
+
+/* FIXME: Issue http://labrea.ad.analog.com/browse/MSKEW-299 describes missing support
+   for HMAC mode, so reject HMAC submits until support for this mode is implemented.
+   ***REMOVE THIS BLOCK WHEN HMAC SUPPORT IS ADDED***
+*/
+#if defined (__ADUCM4x50__)
+#if ADI_CRYPTO_ENABLE_HMAC_SUPPORT == 1
+	if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_HMAC)
+	{
+		return ADI_CRYPTO_ERR_BAD_BUFFER;
+	}
+#endif
+#endif /*ADUCM4x50__*/
+
+    return ADI_CRYPTO_SUCCESS;
+}
+#endif
+
+
+/**
+ * @brief    Opens a Crypto device instance.
+ *
+ * @param [in]  nDeviceNum   Device number to open.
+ * @param [in]  pMemory      Pointer to a #ADI_CRYPTO_MEMORY_SIZE sized buffer to manage the device
+ *                           instance.
+ * @param [in]  nMemorySize  Size of the buffer to which "pMemory" points.
+ * @param [out] phDevice     Pointer to a location where the Crypto device handle is to be written.
+ *
+ * @return   Status
+ *           - #ADI_CRYPTO_SUCCESS                      Call completed successfully.
+ *           - #ADI_CRYPTO_ERR_BAD_DEVICE_NUM       [D] Error: The device number is invalid.
+ *           - #ADI_CRYPTO_ERR_INVALID_PARAM        [D] Error: A parameter is invalid.
+ *           - #ADI_CRYPTO_ERR_INSUFFICIENT_MEM     [D] Error: The memory passed to the device is insufficient.
+ *           - #ADI_CRYPTO_ERR_ALREADY_INITIALIZED  [D] Error: The device is already opened.
+ *           - #ADI_CRYPTO_ERR_SEMAPHORE_FAILED         Error: Unable to create semaphore.
+ *           - #ADI_CRYPTO_ERR_DMA_REGISTER             Error: Unable to register DMA error callback function.
+ *
+ * @sa adi_crypto_Close().
+ */
+ADI_CRYPTO_RESULT adi_crypto_Open (uint32_t const nDeviceNum, void * const pMemory, uint32_t const nMemorySize, ADI_CRYPTO_HANDLE * const phDevice)
+{
+    ADI_CRYPTO_HANDLE hDevice = NULL;
+
+#ifdef ADI_DEBUG
+    if (nDeviceNum >= NUM_DEVICES) {
+        return ADI_CRYPTO_ERR_BAD_DEVICE_NUM;
+    }
+
+    if ((pMemory == NULL) || (phDevice == NULL)) {
+        return ADI_CRYPTO_ERR_INVALID_PARAM;
+    }
+
+    if (nMemorySize < ADI_CRYPTO_MEMORY_SIZE) {
+        return ADI_CRYPTO_ERR_INSUFFICIENT_MEM;
+    }
+
+    if (CryptoDevInfo[nDeviceNum].hDevice != NULL) {
+        return ADI_CRYPTO_ERR_ALREADY_INITIALIZED;
+    }
+
+    /* reality checks */
+    assert (ADI_CRYPTO_MEMORY_SIZE == sizeof(ADI_CRYPTO_DEV_DATA_TYPE));
+    assert (sizeof(ADI_CRYPTO_TRANSACTION) == sizeof(CRYPTO_COMPUTE));
+
+#endif /* ADI_DEBUG */
+
+    /* store a bad handle in case of failure */
+    *phDevice = NULL;
+
+    /* point local device handle to the user memory */
+    hDevice = (ADI_CRYPTO_HANDLE)pMemory;
+
+    /* link CRYPTO controller register set */
+    hDevice->pDev = CryptoDevInfo[nDeviceNum].pDev;
+
+    /* link device info */
+    hDevice->pDevInfo = CryptoDevInfo;
+
+    /* cross-link device handle into device info */
+    CryptoDevInfo[nDeviceNum].hDevice = hDevice;
+
+    /* Initialize the driver internals */
+    InitializeDevData(hDevice);
+
+    /* create the semaphore */
+    SEM_CREATE(hDevice, "crypto_sem", ADI_CRYPTO_ERR_SEMAPHORE_FAILED);
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+    /* initialize DMA core */
+    adi_dma_Init();
+
+    /* register DMA error callback for INPUT channel */
+    if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pDevInfo->dmaInputChanNum, dmaCallback, (void*)hDevice)) {
+        /* uninitialize crypto driver and fail */
+        adi_crypto_Close(hDevice);
+        return  ADI_CRYPTO_ERR_DMA_REGISTER;
+    }
+    /* register DMA error callback for OUTPUT channel */
+    if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pDevInfo->dmaOutputChanNum, dmaCallback, (void*)hDevice)) {
+        /* uninitialize crypto driver and fail */
+        adi_crypto_Close(hDevice);
+        return  ADI_CRYPTO_ERR_DMA_REGISTER;
+    }
+#endif
+
+    /* Give the handle back to the application */
+    *phDevice = hDevice;
+
+    /* Return success */
+    return ADI_CRYPTO_SUCCESS;
+}
+
+/**
+ * @brief    Close the given device instance.
+ *
+ * @param [in]  hDevice  Handle to the device instance.
+ *
+ * @return   Status
+ *           - #ADI_CRYPTO_SUCCESS                  Successfully closed the device.
+ *           - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE   [D] Error: Handle Passed is invalid.
+ *           - #ADI_CRYPTO_ERR_SEMAPHORE_FAILED     Error: Unable to delete semaphore.
+ *
+ * @sa adi_crypto_Open().
+ */
+ADI_CRYPTO_RESULT adi_crypto_Close (ADI_CRYPTO_HANDLE const hDevice)
+{
+    uint32_t x;
+    ADI_CRYPTO_RESULT result;
+
+#ifdef ADI_DEBUG
+    if ((result = ValidateHandle(hDevice)) != ADI_CRYPTO_SUCCESS) {
+        return result;
+    }
+#endif /* ADI_DEBUG */
+
+    /* IF (The device is enabled) */
+    if (hDevice->bDeviceEnabled) {
+        result = adi_crypto_Enable(hDevice, false);
+        if (result != ADI_CRYPTO_SUCCESS) {
+            return result;
+        }
+    }
+
+    /* Destroy the semaphore */
+    SEM_DELETE(hDevice, ADI_CRYPTO_ERR_SEMAPHORE_FAILED);
+
+    /* Close the device */
+    for (x=0u; x < NUM_DEVICES; x++) {
+        if (CryptoDevInfo[x].hDevice == hDevice) {
+            CryptoDevInfo[x].hDevice = NULL;
+            break;
+        }
+    }
+
+    return ADI_CRYPTO_SUCCESS;
+}
+
+
+/**
+ * @brief   Register a user callback function.
+ *
+ * @param [in]  hDevice     Handle to the device instance.
+ * @param [in]  pfCallback  Function pointer to user callback function. Passing a NULL pointer will
+ *                          unregister the callback function.
+ * @param [in]  pCBParam    Callback function parameter.
+ *
+ * @details  This function registers a user callback function.  The registered function will be called when
+ *           the given computation is over.  Registering an active user callback function implies use of the
+ *           (non-blocking) CALLBACK mode during which any subsequent calls to the (blocking-mode)
+ *           #adi_crypto_GetBuffer() API will be rejected.
+ *
+ *
+ * @return   Status
+ *           - #ADI_CRYPTO_SUCCESS                  Successfully registered the callback.
+ *           - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE   [D] Error: Handle Passed is invalid.
+ */
+ ADI_CRYPTO_RESULT adi_crypto_RegisterCallback (ADI_CRYPTO_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void * const pCBParam)
+{
+#ifdef ADI_DEBUG
+    ADI_CRYPTO_RESULT result;
+
+    if ((result = ValidateHandle(hDevice)) != ADI_CRYPTO_SUCCESS) {
+        return result;
+    }
+#endif /* ADI_DEBUG */
+
+    /* store user's callback values (critical section) */
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+		hDevice->pfCallback = pfCallback;
+		hDevice->pCBParam = pCBParam;
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_CRYPTO_SUCCESS;
+}
+
+
+/**
+ * @brief    Submit a Crypto transaction buffer for processing.
+ *
+ * @param [in]  hDevice   Handle to the device instance.
+ * @param [in]  pBuffer   Pointer to the #ADI_CRYPTO_TRANSACTION structure which contains details
+ *                        of the cipher-dependent buffer elements required by the driver.
+ *
+ * @return  Status
+ *           - #ADI_CRYPTO_SUCCESS                  Successfully submitted the buffer.
+ *           - #ADI_CRYPTO_ERR_COMPUTE_ACTIVE       Error: Buffer already submitted.
+ *           - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE   [D] Error: Handle Passed is invalid.
+ *           - #ADI_CRYPTO_ERR_BAD_BUFFER       [D] Error: The buffer passed to the device is invalid or unsupported.
+ *
+ * The buffer submitted is queued for eventual CRYPTO processing.  A single buffer may be submitted
+ * prior to initiating CRYPTO buffer processing.  Buffer processing is initiated with the
+ * #adi_crypto_Enable() call.  As buffer processing is completed, the buffer (and result info)
+ * is retrieved with the #adi_crypto_GetBuffer() API or through the user callback notification.
+ *
+ * @note    The driver takes ownership of the ADI_CRYPTO_TRANSACTION structure passed to the driver.
+ *          The application must insure the structure is not used and its scope is valid until
+ *          the structure is returned back to the application.
+ *
+ * @warning    The #ADI_CRYPTO_TRANSACTION buffer is a common superset of all possible cipher mode parameters.
+ *          As such, not all parameters pertain to each cipher mode.  It is recommended users clear unused
+ *          parameters prior to configuration for the particular cipher mode.  The example provided
+ *          illustrates this with a call to: "memset(&Buffer, 0, sizeof(ADI_CRYPTO_TRANSACTION));"
+ *          before configuring and then submitting each transaction.
+ *
+ * @sa adi_crypto_Enable().
+ * @sa adi_crypto_GetBuffer().
+ * @sa adi_crypto_IsBufferAvailable().
+ */
+ ADI_CRYPTO_RESULT adi_crypto_SubmitBuffer (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_TRANSACTION * const pBuffer)
+{
+    ADI_CRYPTO_RESULT result = ADI_CRYPTO_SUCCESS;
+
+    /* reject if we already have a user buffer */
+    if (NULL != hDevice->pUserBuffer) {
+        /* computation already active */
+        return ADI_CRYPTO_ERR_COMPUTE_ACTIVE;
+    }
+
+#ifdef ADI_DEBUG
+    if (ADI_CRYPTO_SUCCESS != (result = ValidateHandle(hDevice))) {
+        return result;
+    }
+
+    /* validate user Buffer */
+    if (ADI_CRYPTO_SUCCESS != (result = ValidateUserBuffer(pBuffer))) {
+        return result;
+    }
+#endif
+
+    /* store user buffer pointer to return later */
+    hDevice->pUserBuffer = pBuffer;
+
+    /* initialize internal compute state from user buffer */
+    memcpy(&hDevice->Computation, pBuffer, sizeof(ADI_CRYPTO_TRANSACTION));
+
+    /* don't initiate transaction until we get adi_crypto_Enable() */
+
+	/* reset dma error code */
+	hDevice->dmaErrorCode = ADI_CRYPTO_SUCCESS;
+
+    return result;
+}
+
+
+/**
+ * @brief   Get the submitted transaction buffer back from the driver.
+ *
+ * @param [in]  hDevice    Handle to the device instance.
+ * @param [out] ppBuffer   Pointer to a location to which the address of the buffer structure is written.
+ *
+ * @return   Status
+ *           - #ADI_CRYPTO_SUCCESS                      Successfully got a buffer.
+ *           - #ADI_CRYPTO_ERR_INVALID_PARAM        [D] Error: Pointer to the buffer is NULL.
+ *           - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE       [D] Error: Handle Passed is invalid.
+ *           - #ADI_CRYPTO_ERR_DMA_BUS_FAULT            Error: DMA bus fault was reported.
+ *           - #ADI_CRYPTO_ERR_DMA_INVALID_DESCR        Error: Invalid DMA descriptor was reported.
+ *           - #ADI_CRYPTO_ERR_DMA_UNKNOWN_ERROR        Error: An unexpected DMA error was reported.
+ *           - #ADI_CRYPTO_ERR_SEMAPHORE_FAILED         Error: Semaphore pend request failed.
+ *           - #ADI_CRYPTO_ERR_INVALID_STATE            Error: Invalid call when using callback mode.
+ *
+ *  This is a blocking call and will await transaction completion (if not already).
+ *  This function should not be called if a callback function is registered.
+ *
+ * @sa adi_crypto_SubmitBuffer().
+ * @sa adi_crypto_IsBufferAvailable().
+ */
+ADI_CRYPTO_RESULT adi_crypto_GetBuffer (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_TRANSACTION ** const ppBuffer)
+{
+    ADI_CRYPTO_RESULT result = ADI_CRYPTO_SUCCESS;
+
+#ifdef ADI_DEBUG
+
+    if (ppBuffer == NULL) {
+        return ADI_CRYPTO_ERR_INVALID_PARAM;
+    }
+    if (ADI_CRYPTO_SUCCESS != (result = ValidateHandle(hDevice))) {
+        return result;
+    }
+#endif /* ADI_DEBUG */
+
+	if (NULL != hDevice->pfCallback) {
+		return ADI_CRYPTO_ERR_INVALID_STATE;
+	}
+
+    /* pend on completion (even if already complete) */
+    SEM_PEND(hDevice, ADI_CRYPTO_ERR_SEMAPHORE_FAILED);
+
+    /* give back the user's buffer */
+    *ppBuffer = hDevice->pUserBuffer;
+
+    /* clear internal user buffer pointer */
+    hDevice->pUserBuffer = NULL;
+
+	/* if we had a DMA error, return that instead of success */
+	if (ADI_CRYPTO_SUCCESS != hDevice->dmaErrorCode) {
+		result = hDevice->dmaErrorCode;
+	}
+
+    return result;
+}
+
+
+/**
+ * @brief    Peek function to know whether a submitted transaction is complete.
+ *
+ * @param [in]  hDevice       Handle to the device instance.
+ * @param [in]  pbAvailable   Pointer to a Boolean variable. Set to "true" if there is a completed
+ *                            buffer and a call to adi_crypto_GetBuffer is ensured to be successful.
+ *                            Set to "false" if there is no completed buffer.
+ *
+ * @return   Status
+ *           - #ADI_CRYPTO_SUCCESS                  Successfully peeked for a buffer.
+ *           - #ADI_CRYPTO_ERR_INVALID_PARAM    [D] Error: The pointer passed is NULL.
+ *           - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE   [D] Error: Handle Passed is invalid.
+ *           - #ADI_CRYPTO_ERR_DMA_BUS_FAULT        Error: DMA bus fault was reported.
+ *           - #ADI_CRYPTO_ERR_DMA_INVALID_DESCR    Error: Invalid DMA descriptor was reported.
+ *           - #ADI_CRYPTO_ERR_DMA_UNKNOWN_ERROR    Error: An unexpected DMA error was reported.
+ *
+ * @sa adi_crypto_SubmitBuffer().
+ * @sa adi_crypto_GetBuffer().
+ */
+ADI_CRYPTO_RESULT adi_crypto_IsBufferAvailable (ADI_CRYPTO_HANDLE const hDevice, bool * const pbAvailable)
+{
+    ADI_CRYPTO_RESULT result = ADI_CRYPTO_SUCCESS;
+
+#ifdef ADI_DEBUG
+    if (pbAvailable == NULL)
+    {
+        return ADI_CRYPTO_ERR_INVALID_PARAM;
+    }
+    if (ADI_CRYPTO_SUCCESS != (result = ValidateHandle(hDevice))) {
+        return result;
+    }
+#endif /* ADI_DEBUG */
+
+    /* let the respective PIO/DMA interrupts drive completion... just return that state here */
+    *pbAvailable = hDevice->bCompletion;
+
+	/* if we had a DMA error, return that instead of success */
+	if (ADI_CRYPTO_SUCCESS != hDevice->dmaErrorCode) {
+		result = hDevice->dmaErrorCode;
+	}
+
+    return result;
+}
+
+
+/**
+ * @brief    Enable/Disable the device.  Enabling the device causes the submitted buffer to be processed.
+ *
+ * @param [in]  hDevice   Handle to the device instance.
+ * @param [in]  bEnable   'true' to enable and 'false' to disable the device.
+ *
+ * @return   Status
+ *           - #ADI_CRYPTO_SUCCESS                  Successfully enabled/disabled the device.
+ *           - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE   [D] Error: Handle Passed is invalid.
+ *           - #ADI_CRYPTO_ERR_INVALID_STATE    [D] Error: Calling enable when device is already enabled or
+ *                                                         disable when the device is already disabled.
+ *
+ */
+ADI_CRYPTO_RESULT adi_crypto_Enable (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable)
+{
+    ADI_CRYPTO_RESULT result = ADI_CRYPTO_SUCCESS;
+
+#ifdef ADI_DEBUG
+
+    if (ADI_CRYPTO_SUCCESS != (result = ValidateHandle(hDevice))) {
+        return result;
+    }
+    if (bEnable == hDevice->bDeviceEnabled) {
+        return ADI_CRYPTO_ERR_INVALID_STATE;
+    }
+#endif /* ADI_DEBUG */
+
+    if (true == bEnable) {
+
+        /* device enable */
+
+        /* Enable the IRQs */
+        NVIC_EnableIRQ(CRYPT_EVT_IRQn);
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+        /* Enable the DMA interrupts */
+        NVIC_EnableIRQ(hDevice->pDevInfo->dmaInputIrqNum);
+        NVIC_EnableIRQ(hDevice->pDevInfo->dmaOutputIrqNum);
+#endif
+
+        /* Mark the device as enabled */
+        hDevice->bDeviceEnabled = true;
+
+        /* Start processing buffer */
+        StartCompute(hDevice);
+
+    } else {
+
+        /* device disable */
+
+        /* Disable the IRQs */
+        NVIC_DisableIRQ(CRYPT_EVT_IRQn);
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+        /* Enable the DMA interrupts */
+        NVIC_DisableIRQ(hDevice->pDevInfo->dmaInputIrqNum);
+        NVIC_DisableIRQ(hDevice->pDevInfo->dmaOutputIrqNum);
+#endif
+
+        /* Stop the device */
+        StopCompute(hDevice);
+
+        /* if we had a DMA error, return that instead of success */
+        if (ADI_CRYPTO_SUCCESS != hDevice->dmaErrorCode) {
+			result = hDevice->dmaErrorCode;
+		}
+    }
+
+    /* Return success */
+    return result;
+}
+
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+/**
+ * @brief   Dynamically Enable/Disable DMA mode for the device.
+ *
+ * @param [in]  hDevice   Handle to the device instance.
+ * @param [in]  bEnable   'true' will enable DMA and 'false' disables the DMA.
+ *
+ * @return   Status
+ *           - #ADI_CRYPTO_SUCCESS                  Successfully enabled/disabled the DMA.
+ *           - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE   [D] Error: Handle Passed is invalid.
+ *           - #ADI_CRYPTO_ERR_INVALID_STATE    [D] Error: DMA cannot be enabled or disabled when the device is already enabled.
+ *
+ * Manage use of DMA mode dynamically.  Presupposes DMA support has been enabled statically
+ * in the static configuration files via the ADI_CRYPTO_ENABLE_DMA_SUPPORT macro.
+ *
+ * @note In addition to requiring that DMA support is enabled (see ADI_CRYPTO_ENABLE_DMA_SUPPORT static
+ * configuration macro) for #adi_crypto_EnableDmaMode() to be available, use of DMA mode may
+ * also be statically configured (see ADI_CRYPTO_ENABLE_DMA).  Both these macros may be set statically
+ * to both enable DMA support and to activate the DMA mode in a fully static manner, without need of
+ * calling adi_crypto_EnableDmaMode() at all (in which case, this function may be eliminated by the linker).
+ */
+ADI_CRYPTO_RESULT adi_crypto_EnableDmaMode (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable)
+{
+#ifdef ADI_DEBUG
+    ADI_CRYPTO_RESULT result;
+
+    if ((result = ValidateHandle(hDevice)) != ADI_CRYPTO_SUCCESS) {
+        return result;
+    }
+    if (hDevice->bDeviceEnabled) {
+        return ADI_CRYPTO_ERR_INVALID_STATE;
+    }
+#endif /* ADI_DEBUG */
+
+    if (bEnable)
+    {
+        /* Enable DMA and map data pump handler */
+        hDevice->bDmaEnabled = true;
+
+        /* Enable the DMA interrupts */
+        NVIC_EnableIRQ(hDevice->pDevInfo->dmaInputIrqNum);
+        NVIC_EnableIRQ(hDevice->pDevInfo->dmaOutputIrqNum);
+    }
+    else
+    {
+        /* Disable DMA and map data pump handler */
+        hDevice->bDmaEnabled = false;
+
+        /* Disable the DMA interrupts */
+        NVIC_DisableIRQ(hDevice->pDevInfo->dmaInputIrqNum);
+        NVIC_DisableIRQ(hDevice->pDevInfo->dmaOutputIrqNum);
+    }
+
+    /* Return success */
+    return ADI_CRYPTO_SUCCESS;
+}
+#endif
+
+
+
+/*! \cond PRIVATE */
+
+/*========  L O C A L    F U N C T I O N    D E F I N I T I O N S  ========*/
+
+
+/* Convert from a (4-byte) byte pointer to a u32 */
+static uint32_t u32FromU8p(uint8_t * const pFourBytes)
+{
+    return ( (pFourBytes[3] << 24) | (pFourBytes[2] << 16) | (pFourBytes[1] << 8) | (pFourBytes[0]) );
+}
+
+
+/* load KEY register set by length */
+static void loadAesKey(uint8_t * const pKey, ADI_CRYPTO_AES_KEY_LEN const keyLen)
+{
+	uint32_t volatile *pKeyReg = pREG_CRYPT0_AESKEY0;
+	uint8_t *pUserKey = pKey;
+	uint32_t numKeyWords;
+
+	/* set AES KEY length register */
+	CLR_BITS(*pREG_CRYPT0_CFG, BITM_CRYPT_CFG_AESKEYLEN);
+	SET_BITS(*pREG_CRYPT0_CFG, (uint32_t)keyLen);  /* pre-shifted */
+
+	/* Set the number of keywords to write to the 32-bit keyword registers */
+	switch (keyLen) {
+		case ADI_CRYPTO_AES_KEY_LEN_128_BIT:
+			numKeyWords = 4u;
+			break;
+		case ADI_CRYPTO_AES_KEY_LEN_256_BIT:
+			numKeyWords = 8u;
+			break;
+		default:
+			numKeyWords = 0u;  /* hardware only supports only 128-bit and 256-bit key length (no 192-bit) */
+			break;
+	}
+
+	/* load the key (key registers have write-no-read attribute) */
+	for (uint32_t count = 0u; count < numKeyWords; count++) {
+		*pKeyReg = u32FromU8p(pUserKey);
+		pKeyReg++;
+		pUserKey += sizeof(uint32_t);
+    }
+}
+
+
+/* Initialize the device structure */
+static void InitializeDevData (ADI_CRYPTO_HANDLE const hDevice)
+{
+    /* Clear the device structure */
+    memset(hDevice, 0, sizeof(ADI_CRYPTO_HANDLE));
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+    #if (ADI_CRYPTO_ENABLE_DMA == 1)
+        hDevice->bDmaEnabled = true;
+        NVIC_EnableIRQ(hDevice->pDevInfo->dmaInputIrqNum);
+        NVIC_EnableIRQ(hDevice->pDevInfo->dmaOutputIrqNum);
+    #else
+        hDevice->bDmaEnabled = false;
+        NVIC_DisableIRQ(hDevice->pDevInfo->dmaInputIrqNum);
+        NVIC_DisableIRQ(hDevice->pDevInfo->dmaOutputIrqNum);
+    #endif
+#else
+    /* no DMA support */
+    hDevice->bDmaEnabled = false;
+#endif
+}
+
+
+/* initiate buffer processing (called from crypto enable) */
+static void StartCompute(ADI_CRYPTO_HANDLE const hDevice)
+{
+    /* clear completion flag */
+    hDevice->bCompletion = false;
+
+    /* Get pointer to the compute buffer */
+    CRYPTO_COMPUTE* pCompute = &hDevice->Computation;
+
+    /* Clear any pending interrupts (all are R/W1C) */
+    hDevice->pDev->STAT = hDevice->pDev->STAT;
+
+    /* reset crypto config register */
+    hDevice->pDev->CFG = 0u;
+
+#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1)
+    /* reset SHA hardware machine state */
+    if (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) {
+        SET_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_SHAINIT);
+    }
+#endif
+
+    /* program main config register settings */
+    SET_BITS(hDevice->pDev->CFG,
+            ( (uint32_t)pCompute->eCipherMode   /* cipher mode    */
+#if defined (__ADUCM4x50__)
+            | (uint32_t)pCompute->eKeyByteSwap  /* KEY endianness */
+            | (uint32_t)pCompute->eShaByteSwap  /* SHA endianness */
+#endif /*ADUCM4x50*/
+            | (uint32_t)pCompute->eAesByteSwap  /* AES endianness */
+            | (uint32_t)pCompute->eAesKeyLen    /* AES key length */
+            | (uint32_t)pCompute->eCodingMode   /* encode mode    */
+            )
+        );
+
+#if (CRYPTO_SUPPORT_KEY_REQUIRED)
+
+#if (1 == ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT)
+
+	/* if PKSTOR extensions enabled... check is actually in use. */
+
+	/* load AES key indirectly from encrypted key in PKSTOR (no 512-bit keys allowed here) */
+	if ( (true == pCompute->bUsePKSTOR) && ((ADI_PK_KUW_LEN_128 == pCompute->pkKuwLen) || (ADI_PK_KUW_LEN_256 == pCompute->pkKuwLen)) )
+    {
+		/* retrieve and unwrap key from PKSTOR and "use" it (load it into AES register set) */
+        adi_crypto_pk_EnablePKSTOR    (hDevice, true);
+        adi_crypto_pk_SetKuwLen       (hDevice, pCompute->pkKuwLen);
+		adi_crypto_pk_LoadDeviceKey   (hDevice);
+		adi_crypto_pk_RetrieveKey     (hDevice, pCompute->pkIndex);
+		adi_crypto_pk_UnwrapKuwReg    (hDevice);
+		adi_crypto_pk_UseDecryptedKey (hDevice);
+        adi_crypto_pk_EnablePKSTOR    (hDevice, false);
+    }
+    else
+#endif /*ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT */
+    {
+		/* load AES key directly from compute block... */
+		if (NULL != pCompute->pKey) {
+            loadAesKey(pCompute->pKey, pCompute->eAesKeyLen);
+    	}
+	}  /* if PKSTOR / else */
+
+#endif  /* (CRYPTO_SUPPORT_KEY_REQUIRED) */
+
+#if (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1)
+    if (ADI_CRYPTO_MODE_CMAC == pCompute->eCipherMode) {
+        /* program CMAC-specific registers */
+        /* DATALEN in CMAC mode is number of 128 bit pages (or 16, 8 byte pages) */
+        hDevice->pDev->DATALEN             = pCompute->numInputBytesRemaining  / CRYPTO_INPUT_SIZE_IN_BYTES;
+    }
+#endif  /* (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) */
+
+#if (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1)
+    if (ADI_CRYPTO_MODE_CCM == pCompute->eCipherMode) {
+        /* program CMM-specific registers */
+        hDevice->pDev->PREFIXLEN           = pCompute->numAuthBytesRemaining / CRYPTO_INPUT_SIZE_IN_BYTES;
+        hDevice->pDev->DATALEN             = pCompute->numInputBytesRemaining  / CRYPTO_INPUT_SIZE_IN_BYTES;
+        hDevice->pDev->CCM_NUM_VALID_BYTES = pCompute->numValidBytes;
+    }
+#endif  /* (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) */
+
+#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1)
+
+    if ( (ADI_CRYPTO_MODE_CBC == pCompute->eCipherMode) || (ADI_CRYPTO_MODE_CCM == pCompute->eCipherMode) || (ADI_CRYPTO_MODE_CTR == pCompute->eCipherMode) )
+    {
+        /* program NONCE/IV for CBC, CCM and CTR modes */
+        assert (NULL != pCompute->pNonceIV);
+
+        /* Configure Counter Init and NONCE values */
+        hDevice->pDev->CNTRINIT = pCompute->CounterInit;
+
+        hDevice->pDev->NONCE0 = u32FromU8p(&pCompute->pNonceIV[0]);
+        hDevice->pDev->NONCE1 = u32FromU8p(&pCompute->pNonceIV[4]);
+        hDevice->pDev->NONCE2 = u32FromU8p(&pCompute->pNonceIV[8]);
+
+        hDevice->pDev->NONCE3 = ((uint32_t)pCompute->pNonceIV[12] <<  0u) | ((uint32_t)pCompute->pNonceIV[13] <<  8u);
+
+#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1)
+        if (ADI_CRYPTO_MODE_CBC == pCompute->eCipherMode) {
+
+            /* additionally, CBC mode requires remaining IV data */
+            hDevice->pDev->NONCE3 |= ( ((uint32_t)pCompute->pNonceIV[14] << 16u) | ((uint32_t)pCompute->pNonceIV[15] << 24u) );
+        }
+#endif    /* (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) */
+    }
+#endif    /* (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) */
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+
+    /* onle enable DMA for non-SHA mode or SHA mode with > 4 bytes of input... */
+    if ( ((true == hDevice->bDmaEnabled) && (ADI_CRYPTO_MODE_SHA != pCompute->eCipherMode))
+        || ((true == hDevice->bDmaEnabled) && (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) && (4u < pCompute->numInputBytesRemaining)) )
+    {
+
+        /* DMA startup... */
+        programDMA(hDevice);
+
+        /* mode-specific DMA interrupt enables */
+        switch (pCompute->eCipherMode) {
+#if defined (__ADUCM4x50__)
+            case ADI_CRYPTO_MODE_HMAC:
+                /* enable HMAC done and overrun interrupts (via PIO handler) */
+                SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_HMACDONEEN | BITM_CRYPT_INTEN_INOVREN));
+                break;
+#endif /*ADUCM4x50__*/
+            case ADI_CRYPTO_MODE_SHA:
+                /* enable SHA done and overrun interrupts */
+                SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_SHADONEN | BITM_CRYPT_INTEN_INOVREN));
+                SET_BITS(hDevice->pDev->CFG, (BITM_CRYPT_CFG_INDMAEN));
+                break;
+            default:
+                /* enable DMA I/O interrupts */
+                SET_BITS(hDevice->pDev->CFG, (BITM_CRYPT_CFG_OUTDMAEN | BITM_CRYPT_CFG_INDMAEN));
+                break;
+        }
+
+        /* crypto hardware enable */
+        SET_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_BLKEN);
+
+    } else
+#endif
+    {
+        /* mode-specific PIO interrupt enables */
+        switch (pCompute->eCipherMode) {
+#if defined (__ADUCM4x50__)
+                case ADI_CRYPTO_MODE_HMAC:
+                /* HMAC done interrupts via PIO handler (do NOT use INRDY in HMAC mode) */
+                SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_HMACDONEEN | BITM_CRYPT_INTEN_OUTRDYEN | BITM_CRYPT_INTEN_INOVREN));
+                break;
+#endif /*ADUCM4x50__*/
+            case ADI_CRYPTO_MODE_SHA:
+                /* SHA done interrupts via PIO handler (do NOT use INRDY in SHA mode) */
+                SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_SHADONEN | BITM_CRYPT_INTEN_INOVREN));
+                break;
+            default:
+                SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_INOVREN | BITM_CRYPT_INTEN_OUTRDYEN | BITM_CRYPT_INTEN_INRDYEN));
+                break;
+        }
+
+        /* crypto hardware enable */
+        SET_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_BLKEN);
+
+        /* manual write of 1st input data batch... (interrupt-driven hereafter...) */
+        writePioInputData(hDevice, hDevice->pDev->STAT);
+    }
+}
+
+
+/* halt computation */
+static void StopCompute (ADI_CRYPTO_HANDLE const hDevice)
+{
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+    /* disable Crypto DMA */
+    CLR_BITS(hDevice->pDev->CFG, (BITM_CRYPT_CFG_INDMAEN | BITM_CRYPT_CFG_OUTDMAEN));
+#endif
+
+    /* clear all interrupt enables */
+    hDevice->pDev->INTEN = 0u;
+
+    /* Flush the buffers */
+    FlushInputOutputRegisters(hDevice);
+
+    /* device disable */
+    CLR_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_BLKEN);
+
+    /* Mark the device as disabled */
+    hDevice->bDeviceEnabled = false;
+}
+
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+static void programDMA(ADI_CRYPTO_HANDLE const hDevice)
+{
+    CRYPTO_COMPUTE* pCompute = &hDevice->Computation;
+    ADI_DCC_TypeDef* pCCD;  /* pointer to DMA Control Data Descriptor */
+    uint32_t channelBit;
+    uint32_t num32BitWords;
+
+    /* start with INPUT channel */
+    channelBit = 1u << hDevice->pDevInfo->dmaInputChanNum;
+
+    /* disable various stuff */
+    pADI_DMA0->SRCADDR_CLR = channelBit;  /* disable src endpointer decrement mode */
+    pADI_DMA0->DSTADDR_CLR = channelBit;  /* disable dst endpointer decrement mode */
+    pADI_DMA0->EN_SET      = channelBit;  /* channel enable */
+    pADI_DMA0->RMSK_CLR    = channelBit;  /* allow Crypto to request DMA service */
+
+#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1)
+    /* program input descriptor(s) */
+    if (0u != pCompute->pNextAuthInput) {
+
+        /* schedule authentication data into primary descriptor (USING ping-pong mode) */
+
+        pADI_DMA0->ALT_CLR = channelBit;  /* activate PRIMARY descriptor */
+        pCCD = pPrimaryCCD + hDevice->pDevInfo->dmaInputChanNum;  /* point to primary INPUT descriptor */
+
+        /* setup the endpoints (point to input register & last 4 bytes of input array) */
+        pCCD->DMASRCEND = (uint32_t)pCompute->pNextAuthInput + sizeof(uint32_t) * (pCompute->numAuthBytesRemaining / FIFO_WIDTH_IN_BYTES - 1u);
+        pCCD->DMADSTEND = (uint32_t)&hDevice->pDev->INBUF;
+
+        /* program DMA Control Data Config register */
+        num32BitWords = pCompute->numAuthBytesRemaining / sizeof(uint32_t);
+        pCCD->DMACDC =
+            ( ((uint32_t)ADI_DMA_INCR_NONE                << DMA_BITP_CTL_DST_INC)
+            | ((uint32_t)ADI_DMA_INCR_4_BYTE              << DMA_BITP_CTL_SRC_INC)
+            | ((uint32_t)ADI_DMA_WIDTH_4_BYTE             << DMA_BITP_CTL_SRC_SIZE)
+            | ((uint32_t)ADI_DMA_RPOWER_4                 << DMA_BITP_CTL_R_POWER)
+            | (uint32_t)((num32BitWords - 1u)             << DMA_BITP_CTL_N_MINUS_1)
+            | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_PING_PONG << DMA_BITP_CTL_CYCLE_CTL) );
+
+
+        /* schedule input data into alternate descriptor (in basic mode) */
+        pADI_DMA0->PRI_CLR = channelBit;  /* activate ALTERNATE descriptor */
+        pCCD = pAlternateCCD + hDevice->pDevInfo->dmaInputChanNum;  /* point to alternate INPUT descriptor */
+
+        /* setup the endpoints (point to input register & last 4 bytes of input array) */
+        pCCD->DMASRCEND = (uint32_t)pCompute->pNextInput + sizeof(uint32_t) * (pCompute->numInputBytesRemaining / FIFO_WIDTH_IN_BYTES - 1u);
+        pCCD->DMADSTEND = (uint32_t)&hDevice->pDev->INBUF;
+
+        /* program DMA Control Data Config register */
+        num32BitWords = pCompute->numInputBytesRemaining / sizeof(uint32_t);
+        pCCD->DMACDC =
+            ( ((uint32_t)ADI_DMA_INCR_NONE                << DMA_BITP_CTL_DST_INC)
+            | ((uint32_t)ADI_DMA_INCR_4_BYTE              << DMA_BITP_CTL_SRC_INC)
+            | ((uint32_t)ADI_DMA_WIDTH_4_BYTE             << DMA_BITP_CTL_SRC_SIZE)
+            | ((uint32_t)ADI_DMA_RPOWER_4                 << DMA_BITP_CTL_R_POWER)
+            | (uint32_t)((num32BitWords - 1u)             << DMA_BITP_CTL_N_MINUS_1)
+            | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC     << DMA_BITP_CTL_CYCLE_CTL) );
+
+    } else
+#endif  /* #if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) */
+    {
+
+        /* no authentication data, just schedule input data into primary descriptor (in basic mode) */
+
+        pADI_DMA0->ALT_CLR = channelBit;  /* activate PRIMARY descriptor */
+        pCCD = pPrimaryCCD + hDevice->pDevInfo->dmaInputChanNum;  /* point to primary INPUT descriptor */
+
+        /* setup the endpoints (point to input register & last 4 bytes of input array) */
+#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1)
+        if (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) {
+
+            /* Stop SHA-mode input writes one short of last 32-bit word so the DMA input interrupt
+               can manually call PIO write function to handle SHA end flag and last write manually. */
+            pCCD->DMASRCEND = (uint32_t)pCompute->pNextInput + sizeof(uint32_t) * (pCompute->numInputBytesRemaining  / FIFO_WIDTH_IN_BYTES - 2u);
+            num32BitWords = (pCompute->numInputBytesRemaining - (pCompute->numInputBytesRemaining % sizeof(uint32_t))) / sizeof(uint32_t) - 1u;  /* count - 1 */
+        }
+        else
+#endif
+        {
+            /* stop at last write end */
+            pCCD->DMASRCEND = (uint32_t)pCompute->pNextInput + sizeof(uint32_t) * ( pCompute->numInputBytesRemaining / FIFO_WIDTH_IN_BYTES - 1u);
+            num32BitWords = pCompute->numInputBytesRemaining / sizeof(uint32_t); /* count */
+        }
+
+        pCCD->DMADSTEND = (uint32_t)&hDevice->pDev->INBUF;
+
+        /* program DMA Control Data Config register */
+        pCCD->DMACDC =
+            ( ((uint32_t)ADI_DMA_INCR_NONE                << DMA_BITP_CTL_DST_INC)
+            | ((uint32_t)ADI_DMA_INCR_4_BYTE              << DMA_BITP_CTL_SRC_INC)
+            | ((uint32_t)ADI_DMA_WIDTH_4_BYTE             << DMA_BITP_CTL_SRC_SIZE)
+            | ((uint32_t)ADI_DMA_RPOWER_4                 << DMA_BITP_CTL_R_POWER)
+            | (uint32_t)((num32BitWords - 1u)             << DMA_BITP_CTL_N_MINUS_1)
+            | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC     << DMA_BITP_CTL_CYCLE_CTL) );
+    }
+
+/* don't program output DMA in SHA mode... */
+#if CRYPTO_SUPPORT_MODE_ANY_NON_SHA
+
+    if (ADI_CRYPTO_MODE_SHA != pCompute->eCipherMode) {
+
+        /* switch to OUTPUT channel */
+        channelBit = 1u << hDevice->pDevInfo->dmaOutputChanNum;
+
+        /* disable various stuff */
+        pADI_DMA0->SRCADDR_CLR = channelBit;  /* disable src endpointer decrement mode */
+        pADI_DMA0->DSTADDR_CLR = channelBit;  /* disable dst endpointer decrement mode */
+        pADI_DMA0->EN_SET      = channelBit;  /* channel enable */
+        pADI_DMA0->RMSK_CLR    = channelBit;  /* allow Crypto to request DMA service */
+
+        pADI_DMA0->ALT_CLR = channelBit;  /* activate primary descriptor */
+        pCCD = pPrimaryCCD + hDevice->pDevInfo->dmaOutputChanNum;  /* point to crypto OUTPUT descriptor */
+
+
+        /* setup the endpoints (point to output register & last 4 bytes of output array) */
+        pCCD->DMASRCEND = (uint32_t)&hDevice->pDev->OUTBUF;
+        pCCD->DMADSTEND = (uint32_t)pCompute->pNextOutput + sizeof(uint32_t) * (pCompute->numOutputBytesRemaining / FIFO_WIDTH_IN_BYTES - 1u);
+
+        /* program DMA Control Data Config register */
+        num32BitWords = pCompute->numOutputBytesRemaining / sizeof(uint32_t);
+        pCCD->DMACDC =
+            ( ((uint32_t)ADI_DMA_INCR_4_BYTE           << DMA_BITP_CTL_DST_INC)
+            | ((uint32_t)ADI_DMA_INCR_NONE             << DMA_BITP_CTL_SRC_INC)
+            | ((uint32_t)ADI_DMA_WIDTH_4_BYTE          << DMA_BITP_CTL_SRC_SIZE)
+            | ((uint32_t)ADI_DMA_RPOWER_4              << DMA_BITP_CTL_R_POWER)
+            | (uint32_t)((num32BitWords - 1u)          << DMA_BITP_CTL_N_MINUS_1)
+            | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC  << DMA_BITP_CTL_CYCLE_CTL) );
+
+    }  /* end non-SHA mode */
+
+#endif  /* CRYPTO_SUPPORT_MODE_ANY_NON_SHA */
+}
+#endif  /* #if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) */
+
+
+static void writePioInputData(ADI_CRYPTO_HANDLE const hDevice, uint32_t const status)
+{
+    CRYPTO_COMPUTE* pCompute = &hDevice->Computation;
+    uint32_t numWritable = FIFO_DEPTH - ((status & BITM_CRYPT_STAT_INWORDS) >> BITP_CRYPT_STAT_INWORDS);
+
+#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1)
+    /* always send authentication data before input payload is sent */
+    if (0u != pCompute->numAuthBytesRemaining) {
+
+        /* fill input FIFO with 32-bit authentication data */
+        while ((0u != numWritable) && (0u != pCompute->numAuthBytesRemaining)) {
+            hDevice->pDev->INBUF = *pCompute->pNextAuthInput;
+            pCompute->pNextAuthInput++;
+            pCompute->numAuthBytesRemaining -= FIFO_WIDTH_IN_BYTES;
+            numWritable--;
+        }
+    } else
+#endif  /* #if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) */
+    {
+        /* no authentication data, process payload input data */
+
+#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1)
+        if (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) {
+
+            /* Drive up to a full "chunk" of SHA input message data.
+               Chunk size is limited to 512-bits (64-bytes) by AES
+               hardware compute block.
+            */
+
+            if (pCompute->numInputBytesRemaining >= SHA_CHUNK_MAX_BYTES)
+            {
+                /* This is the simple case, load up an entire chunk and let it go */
+                for (uint8_t i = 0u; i < SHA_CHUNK_MAX_WORDS; i++) {
+                    hDevice->pDev->INBUF = *pCompute->pNextInput;
+                    pCompute->pNextInput++;
+                }
+
+                pCompute->numShaBitsRemaining    -= SHA_CHUNK_MAX_BITS;
+                pCompute->numInputBytesRemaining -= SHA_CHUNK_MAX_BYTES;
+            }
+            else
+            {
+                /* The final case, we load up any bytes less than a full chunk and trigger the last word */
+                while (FIFO_WIDTH_IN_BITS <= pCompute->numShaBitsRemaining) {
+                    hDevice->pDev->INBUF = *pCompute->pNextInput;
+                    pCompute->pNextInput++;
+                    pCompute->numShaBitsRemaining -= FIFO_WIDTH_IN_BITS;
+                }
+
+                hDevice->pDev->SHA_LAST_WORD = (pCompute->numShaBitsRemaining << BITP_CRYPT_SHA_LAST_WORD_O_BITS_VALID) | BITM_CRYPT_SHA_LAST_WORD_O_LAST_WORD;
+
+                /* Last write is dummy or not, depending on remaining bit count */
+                if (0u == pCompute->numShaBitsRemaining) {
+                    /* dummy write */
+                    hDevice->pDev->INBUF = 0u;
+                } else {
+                    /* partial data (last remaining message data word) */
+                    hDevice->pDev->INBUF = *pCompute->pNextInput;
+                    pCompute->pNextInput++;
+                }
+
+                pCompute->numShaBitsRemaining     = 0u;
+                pCompute->numInputBytesRemaining  = 0u;
+
+                /* Use output bytes as a way of confirming that we are really done (can't use input bytes/bits) */
+                pCompute->numOutputBytesRemaining -= SHA_OUTPUT_SIZE_IN_BYTES;
+            }
+        }  /* end of SHA mode */
+        else
+#endif
+        {
+            /* full input FIFO with normal payload write (non-SHA) */
+            while ((0u != numWritable) && (0u != pCompute->numInputBytesRemaining)) {
+                hDevice->pDev->INBUF = *pCompute->pNextInput;
+                pCompute->pNextInput++;
+                pCompute->numInputBytesRemaining -= FIFO_WIDTH_IN_BYTES;
+                numWritable--;
+            }
+        }
+    }
+}
+
+
+static void readPioOutputData(ADI_CRYPTO_HANDLE const hDevice, uint32_t const status)
+{
+    CRYPTO_COMPUTE *pCompute = &hDevice->Computation;
+    uint32_t numReadable;
+
+#if  ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1
+    /* Copy the SHA output if enabled */
+    if (pCompute->eCipherMode == ADI_CRYPTO_MODE_SHA)
+    {
+        if (IS_ANY_BIT_SET(status, BITM_CRYPT_STAT_SHADONE)) {
+
+			/* Get 1 SHADONE per block + 1 SHADONE when we trigger the last word */
+			if (0u == pCompute->numOutputBytesRemaining) {
+#if ADI_CRYPTO_SHA_OUTPUT_FORMAT == 0 /* Little Endian */
+				pCompute->pNextOutput[0] = hDevice->pDev->SHAH7;
+				pCompute->pNextOutput[1] = hDevice->pDev->SHAH6;
+				pCompute->pNextOutput[2] = hDevice->pDev->SHAH5;
+				pCompute->pNextOutput[3] = hDevice->pDev->SHAH4;
+				pCompute->pNextOutput[4] = hDevice->pDev->SHAH3;
+				pCompute->pNextOutput[5] = hDevice->pDev->SHAH2;
+				pCompute->pNextOutput[6] = hDevice->pDev->SHAH1;
+				pCompute->pNextOutput[7] = hDevice->pDev->SHAH0;
+#else
+				pCompute->pNextOutput[0] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH0);
+				pCompute->pNextOutput[1] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH1);
+				pCompute->pNextOutput[2] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH2);
+				pCompute->pNextOutput[3] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH3);
+				pCompute->pNextOutput[4] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH4);
+				pCompute->pNextOutput[5] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH5);
+				pCompute->pNextOutput[6] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH6);
+				pCompute->pNextOutput[7] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH7);
+#endif
+			}
+        }
+    }
+    else
+#endif
+    {
+        /* read any ready non-SHA output from output FIFO */
+        if (IS_ANY_BIT_SET(status, BITM_CRYPT_STAT_OUTRDY)) {
+            numReadable = ((status & BITM_CRYPT_STAT_OUTWORDS) >> BITP_CRYPT_STAT_OUTWORDS);
+            while ((0u != numReadable) && (0u != pCompute->numOutputBytesRemaining)) {
+                *pCompute->pNextOutput = hDevice->pDev->OUTBUF;
+                pCompute->pNextOutput++;
+                pCompute->numOutputBytesRemaining -= FIFO_WIDTH_IN_BYTES;
+                numReadable--;
+            }
+        }
+    }
+
+    /* if output count has gone to zero, set completion flag */
+    if (0u == pCompute->numOutputBytesRemaining) {
+        hDevice->bCompletion = true;
+    }
+}
+
+
+/* Flush the Crypto input and output buffers */
+static void FlushInputOutputRegisters(ADI_CRYPTO_HANDLE const hDevice)
+{
+    /* Set and clear the flush bits to flush the input and output buffers */
+    SET_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_INFLUSH | BITM_CRYPT_CFG_OUTFLUSH);
+    CLR_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_INFLUSH | BITM_CRYPT_CFG_OUTFLUSH);
+}
+
+
+/*================ INTERRUPT HANDELING ==================*/
+
+/* native PIO-mode (non-DMA) interrupt handler */
+void Crypto_Int_Handler(void)
+{
+    ISR_PROLOG();
+
+    ADI_CRYPTO_HANDLE hDevice = CryptoDevInfo[0].hDevice;
+    CRYPTO_COMPUTE *pCompute  = &hDevice->Computation;
+    uint32_t status = hDevice->pDev->STAT;
+    uint32_t event;
+
+    /* clear status */
+    hDevice->pDev->STAT = status;
+
+    /* check for overflow */
+    if (IS_ANY_BIT_SET(status, BITM_CRYPT_STAT_INOVR)) {
+
+        /* call user's callback */
+        if (0u != hDevice->pfCallback) {
+            hDevice->pfCallback(hDevice->pCBParam, ADI_CRYPTO_EVENT_STATUS_INPUT_OVERFLOW, (void *)status);
+        }
+
+        /* stop */
+        StopCompute(hDevice);
+
+        /* post the semaphore */
+        SEM_POST(hDevice);
+
+        return;
+    }
+
+    /* pull outputs (updates completion flag) */
+    readPioOutputData(hDevice, status);
+
+    if (false == hDevice->bCompletion) {
+
+        /* push more inputs, but not in SHA DMA mode (except for when it�s perfectly aligned block) */
+        if ((pCompute->eCipherMode != ADI_CRYPTO_MODE_SHA) || (hDevice->bDmaEnabled == false) || (pCompute->numInputBytesRemaining == 0u))
+        {
+            writePioInputData(hDevice, status);
+        }
+
+    } else {
+
+        /* we're done */
+
+        /* dispatch to user callback if we have one */
+        if (0u != hDevice->pfCallback) {
+
+            /* check for overflow first */
+            if (0u != (BITM_CRYPT_STAT_INOVR & status)) {
+                event = ADI_CRYPTO_EVENT_STATUS_INPUT_OVERFLOW;
+            } else {
+                /* completion message depends on mode */
+                switch (hDevice->Computation.eCipherMode) {
+#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1)
+                    case ADI_CRYPTO_MODE_CBC:  event = ADI_CRYPTO_EVENT_STATUS_CBC_DONE;  break;
+#endif
+#if (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1)
+                    case ADI_CRYPTO_MODE_CCM:  event = ADI_CRYPTO_EVENT_STATUS_CCM_DONE;  break;
+#endif
+#if (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1)
+                    case ADI_CRYPTO_MODE_CMAC: event = ADI_CRYPTO_EVENT_STATUS_CMAC_DONE; break;
+#endif
+#if (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1)
+                    case ADI_CRYPTO_MODE_CTR:  event = ADI_CRYPTO_EVENT_STATUS_CTR_DONE;  break;
+#endif
+#if (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1)
+					case ADI_CRYPTO_MODE_ECB:  event = ADI_CRYPTO_EVENT_STATUS_ECB_DONE;  break;
+#endif
+#if defined (__ADUCM4x50__) /* HMAC support is provided only in ADuCM4x50*/
+#if (ADI_CRYPTO_ENABLE_HMAC_SUPPORT == 1)
+                    case ADI_CRYPTO_MODE_HMAC: event = ADI_CRYPTO_EVENT_STATUS_HMAC_DONE; break;
+#endif
+#endif /*__ADUCM4x50__*/
+#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1)
+                    case ADI_CRYPTO_MODE_SHA:  event = ADI_CRYPTO_EVENT_STATUS_SHA_DONE;  break;
+#endif
+                    default:                   event = ADI_CRYPTO_EVENT_STATUS_UNKNOWN;   break;
+                }
+            }
+
+            /* call user's callback and give back buffer pointer */
+            hDevice->pfCallback(hDevice->pCBParam, event, (void*)hDevice->pUserBuffer);
+
+            /* clear private copy of user buffer pointer */
+            /* (this is done in GetBuffer in non-Callback mode) */
+            hDevice->pUserBuffer = NULL;
+        }
+
+        /* disable interrupts */
+        hDevice->pDev->INTEN = 0u;
+
+        /* post the semaphore */
+        SEM_POST(hDevice);
+    }
+
+    ISR_EPILOG();
+}
+
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+/* native DMA input interrupt handler */
+void DMA_AES0_IN_Int_Handler (void)
+{
+    ISR_PROLOG();
+
+    ADI_CRYPTO_HANDLE hDevice = CryptoDevInfo[0].hDevice;
+    CRYPTO_COMPUTE *pCompute  = &hDevice->Computation;
+
+#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1)
+    if (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) {
+
+        /* Update the compute structure to reflect the "post DMA" state of the transaction */
+        uint32_t numTotalBytes            = pCompute->numInputBytesRemaining;
+        uint32_t num32BitWords            = (numTotalBytes - (numTotalBytes % sizeof(uint32_t))) / sizeof(uint32_t) - 1u;
+        pCompute->numInputBytesRemaining -= num32BitWords*4u;
+        pCompute->numShaBitsRemaining    -= num32BitWords*32u;
+        pCompute->pNextInput             += num32BitWords;
+
+        if ((numTotalBytes % SHA_CHUNK_MAX_BYTES) == 0u)
+        {
+            /* For perfect block sizes, need to write the last word WITHOUT triggering SHA_LAST_WORD */
+            hDevice->pDev->INBUF = *pCompute->pNextInput;
+
+            pCompute->numInputBytesRemaining = 0u;
+            pCompute->numShaBitsRemaining    = 0u;
+        }
+        else
+        {
+            /* Go ahead and write the remaining word, and it�s okay to trigger SHA_LAST_WORD */
+            writePioInputData(hDevice, hDevice->pDev->STAT);
+        }
+    }
+#endif
+
+    /* defer post to output interrupt... */
+
+    ISR_EPILOG();
+}
+#endif /* ADI_CRYPTO_ENABLE_DMA_SUPPORT */
+
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+/* native DMA output interrupt handler */
+void DMA_AES0_OUT_Int_Handler (void)
+{
+    ISR_PROLOG();
+    ADI_CRYPTO_HANDLE hDevice = CryptoDevInfo[0].hDevice;
+    uint32_t status = hDevice->pDev->STAT;
+    uint32_t event;
+
+    /* by the time we get here, everything should be complete */
+
+    /* dispatch to user callback if we have one */
+    if (0u != hDevice->pfCallback) {
+
+        /* check for overflow first */
+        if (0u != (BITM_CRYPT_STAT_INOVR & status)) {
+            event = ADI_CRYPTO_EVENT_STATUS_INPUT_OVERFLOW;
+        } else {
+            /* completion message depends on mode */
+            switch (hDevice->Computation.eCipherMode) {
+#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1)
+                case ADI_CRYPTO_MODE_CBC:  event = ADI_CRYPTO_EVENT_STATUS_CBC_DONE;  break;
+#endif
+#if (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1)
+                case ADI_CRYPTO_MODE_CCM:  event = ADI_CRYPTO_EVENT_STATUS_CCM_DONE;  break;
+#endif
+#if (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1)
+                case ADI_CRYPTO_MODE_CMAC: event = ADI_CRYPTO_EVENT_STATUS_CMAC_DONE; break;
+#endif
+#if (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1)
+                case ADI_CRYPTO_MODE_CTR:  event = ADI_CRYPTO_EVENT_STATUS_CTR_DONE;  break;
+#endif
+#if (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1)
+                case ADI_CRYPTO_MODE_ECB:  event = ADI_CRYPTO_EVENT_STATUS_ECB_DONE;  break;
+#endif
+#if defined (__ADUCM4x50__)
+#if (ADI_CRYPTO_ENABLE_HMAC_SUPPORT == 1)
+                case ADI_CRYPTO_MODE_HMAC: event = ADI_CRYPTO_EVENT_STATUS_HMAC_DONE; break;
+#endif
+#endif /*__ADUCM4x50__*/
+#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1)
+                case ADI_CRYPTO_MODE_SHA:  event = ADI_CRYPTO_EVENT_STATUS_SHA_DONE;  break;
+#endif
+                default:                   event = ADI_CRYPTO_EVENT_STATUS_UNKNOWN;   break;
+            }
+        }
+
+        /* call user's callback and give back buffer pointer */
+        hDevice->pfCallback(hDevice->pCBParam, event, (void*)hDevice->pUserBuffer);
+
+        /* clear private copy of user buffer pointer */
+          /* this is done in GetBuffer in non-Callback mode */
+        hDevice->pUserBuffer = NULL;
+    }
+
+    /* mark completion */
+    hDevice->bCompletion = true;
+
+    /* clear status */
+    hDevice->pDev->STAT = status;
+
+    /* post the semaphore */
+    SEM_POST(hDevice);
+
+    ISR_EPILOG();
+}
+#endif  /* ADI_CRYPTO_ENABLE_DMA_SUPPORT */
+
+/*! \endcond */
+
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crypto/adi_crypto_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crypto/adi_crypto_def.h
new file mode 100755
index 00000000000..da8f40eb8a7
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crypto/adi_crypto_def.h
@@ -0,0 +1,226 @@
+/*!
+ *****************************************************************************
+ @file:    adi_crypto_def.h
+ @brief:   Crypto Device Driver definitions for ADuCM4x50 processor
+ -----------------------------------------------------------------------------
+Copyright (c) 2012-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#ifndef ADI_CRYPTO_DEF_H
+#define ADI_CRYPTO_DEF_H
+
+/*! \cond PRIVATE */
+
+#include <drivers/dma/adi_dma.h>
+#include <adi_crypto_config.h>
+
+/* pick up compiler-specific alignment directives */
+#include <drivers/general/adi_drivers_general.h>
+#define ALIGN4 ALIGNED_PRAGMA(4)
+
+/* Support Check MACROS */
+#define CRYPTO_SUPPORT_KEY_REQUIRED  (                                                  \
+                                               (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1)    \
+                                            )
+
+#define CRYPTO_SUPPORT_MODE_CCM_ONLY       (                                             \
+                                               (ADI_CRYPTO_ENABLE_ECB_SUPPORT  != 1)     \
+                                            && (ADI_CRYPTO_ENABLE_CTR_SUPPORT  != 1)     \
+                                            && (ADI_CRYPTO_ENABLE_CBC_SUPPORT  != 1)     \
+                                            && (ADI_CRYPTO_ENABLE_CCM_SUPPORT  == 1)     \
+                                            && (ADI_CRYPTO_ENABLE_CMAC_SUPPORT != 1)     \
+                                            && (ADI_CRYPTO_ENABLE_SHA_SUPPORT  != 1)     \
+                                            )
+
+#define CRYPTO_SUPPORT_MODE_ANY_NON_CCM    (                                             \
+                                               (ADI_CRYPTO_ENABLE_ECB_SUPPORT  == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CTR_SUPPORT  == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CBC_SUPPORT  == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_SHA_SUPPORT  == 1)     \
+                                            )
+
+#define CRYPTO_SUPPORT_MODE_ANY_NON_SHA    (                                             \
+                                               (ADI_CRYPTO_ENABLE_ECB_SUPPORT  == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CTR_SUPPORT  == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CBC_SUPPORT  == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CCM_SUPPORT  == 1)     \
+                                            )
+
+
+/* PKSTOR config bits */
+#if (1 == ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT)
+#define PK_CONFIG_BITS (BITM_CRYPT_CFG_PRKSTOREN | BITM_CRYPT_CFG_BLKEN )
+#define NUM_PKSTOR_VAL_STRING_WORDS (2)
+#endif
+
+
+/* define local MIN/MAX macros, if not already... */
+#ifndef MIN
+#define MIN(a,b) (((a)<(b))?(a):(b))
+#endif
+#ifndef MAX
+#define MAX(a,b) (((a)>(b))?(a):(b))
+#endif
+
+/* various size macros */
+#define MAX_CRYPTO_DMA_BYTES        (DMA_TRANSFER_LIMIT * sizeof(uint32_t))
+
+/* SHA hardware max chunk size attributes */
+#define SHA_CHUNK_MAX_BYTES         (64u)
+#define SHA_CHUNK_MAX_BITS          (SHA_CHUNK_MAX_BYTES * 8U)
+#define SHA_CHUNK_MAX_WORDS         (16u)
+
+#define FIFO_WIDTH_IN_BITS          (32u)
+#define FIFO_WIDTH_IN_BYTES         (FIFO_WIDTH_IN_BITS/8u)
+#define FIFO_DEPTH                  (4u)
+
+#define CRYPTO_INPUT_SIZE_IN_BITS   (128u)
+#define CRYPTO_INPUT_SIZE_IN_BYTES  (CRYPTO_INPUT_SIZE_IN_BITS/8u)
+
+#define SHA_OUTPUT_SIZE_IN_BITS     (256u)
+#define SHA_OUTPUT_SIZE_IN_BYTES    (SHA_OUTPUT_SIZE_IN_BITS/8u)
+
+
+/* MAKE SURE THIS STRUCT REMAINS *******PERFECTLY ALIGNED******* WITH USER
+   ADI_CRYPTO_TRANSACTION BECAUSE WE USE BCOPY TO INITIALIZE EACH NEW SUBMIT!
+
+   Internal compute structure reflecting mostly, user ADI_CRYPTO_TRANSACTION,
+   except for moving data pointers and remaining counts.  Contents initialized
+   directly from from ADI_CRYPTO_TRANSACTION during buffer submit.
+*/
+typedef struct _CRYPTO_COMPUTE {
+	ADI_CRYPTO_CIPHER_MODE    eCipherMode;              /*!< Cipher mode to use */
+    ADI_CRYPTO_CODING_MODE    eCodingMode;              /*!< Coding Mode (Encryption or Decryption) */
+#if defined (__ADUCM4x50__)
+    ADI_CRYPTO_KEY_BYTE_SWAP  eKeyByteSwap;             /*!< KEY endianness */
+    ADI_CRYPTO_SHA_BYTE_SWAP  eShaByteSwap;             /*!< SHA endianness */
+#endif /*__ADUCM4x50__*/
+    ADI_CRYPTO_AES_BYTE_SWAP  eAesByteSwap;             /*!< AES endianness */
+
+    uint8_t                  *pKey;                     /*!< Pointer to the key data pre-formatted as a byte array, according to eAesKeyLen. */
+    ADI_CRYPTO_AES_KEY_LEN    eAesKeyLen;               /*!< The length of the key */
+
+    uint32_t                 *pNextAuthInput;           /* CCM mode: pointer to user prefix buffer */
+    uint32_t                  numAuthBytesRemaining;    /* Length of the prefix buffer in bytes (should be a multiple of 16 bytes) */
+
+    uint32_t                 *pNextInput;               /* Pointer to next user 32-bit input location */
+    uint32_t                  numInputBytesRemaining;   /* Number of input bytes remaining */
+
+    uint32_t                 *pNextOutput;              /* Pointer to next user 32-bit output location */
+    uint32_t                  numOutputBytesRemaining;  /* Number of output bytes remaining */
+
+    uint8_t                  *pNonceIV;                 /*!< Pointer to user 16-byte array containing one of three values, depending on cipher mode:
+                                                                 CTR mode = 108-bit NONCE
+                                                                 CCM mode = 112-bit NONCE
+                                                                 CBC mode = 128-bit IV (Initialization Vector)
+                                                             NONCE and IV assume little endian format, for example: CTR NONCE packing is:
+                                                                NONCE[0]            ->   7:0
+                                                                NONCE[1]            ->  15:8
+                                                                  ...
+                                                                NONCE[13]           -> 103:96
+                                                                NONCE[14](Bits 3:0) -> 107:104 */
+    uint32_t                  CounterInit;              /*!< CTR/CCM mode: Counter Initialization Value (CTR=20-bit, CCM=16-bit) */
+    uint32_t                  numValidBytes;            /*!< CCM mode: Number of valid bytes in the last (padding) block (1-16) */
+    uint32_t                  numShaBitsRemaining;      /*!< SHA mode: Number of bits remaining in the SHA payload, which may be odd-sized */
+
+#if defined (__ADUCM4x50__)
+    /* PKSTOR extensions used only in context of overriding above key info with protected keys stored in flash. */
+    /* Assumes previously wrapped keys have already been stored using adi_crypto_pk_Xxx APIs. */
+    bool                      bUsePKSTOR;               /* flag controlling use of PKSTOR key overrides */
+    ADI_CRYPTO_PK_KUW_LEN     pkKuwLen;                 /* overriding key size */
+    uint8_t                   pkIndex;                  /* PKSTOR flash index for key to use */
+#endif
+} CRYPTO_COMPUTE;
+
+
+/* Crypto device attributes */
+typedef struct _CRYPTO_INFO {
+    ADI_CRYPT_TypeDef          *pDev;				/* Pointer to physical Crypto controller */
+    ADI_CRYPTO_HANDLE           hDevice;			/* Device Handle */
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+    IRQn_Type                   dmaInputIrqNum;
+    IRQn_Type                   dmaOutputIrqNum;
+    DMA_CHANn_TypeDef           dmaInputChanNum;
+    DMA_CHANn_TypeDef           dmaOutputChanNum;
+    volatile ADI_CRYPTO_RESULT  dmaError;			/* DMA error collector. */
+#endif
+} CRYPTO_INFO;
+
+
+#ifdef __ICCARM__
+/*
+* Pm123 (RULE 8.5) there shall be no definition of objects or functions in a header file.
+* Exception is to allow the Crypto device data type and instance to be declared simultaniously.
+*/
+#pragma diag_suppress=Pm123
+#endif /* __ICCARM__ */
+
+/* Crypto driver internal data */
+struct __ADI_CRYPTO_DEV_DATA_TYPE {
+    bool                     bDeviceEnabled;         /* Boolean flag to signify whether the device is enable/disabled */
+    bool                     bDmaEnabled;            /* Boolean flag to signify whether the DMA is enable/disabled */
+    bool                     bCompletion;            /* Boolean flag to signify whether a transaction is complete */
+
+    ADI_CRYPT_TypeDef       *pDev;                   /* Pointer to physical Crypto controller */
+
+    CRYPTO_INFO             *pDevInfo;               /* access to device info */
+
+    CRYPTO_COMPUTE           Computation;            /* Active computation structure */
+
+    ADI_CRYPTO_TRANSACTION  *pUserBuffer;            /* saved user buffer pointer from submit */
+    ADI_CALLBACK             pfCallback;             /* User defined callback function */
+    void                    *pCBParam;               /* User defined callback param */
+    ADI_CRYPTO_RESULT        dmaErrorCode;           /* saved DMA error code to return via user API */
+
+
+    SEM_VAR_DECLR        /* Blocking object abstraction: "Semaphore" for rtos,  "bLowPowerExitFlag" for non-rtos, etc.    */
+} ADI_CRYPTO_DEV_DATA_TYPE;
+
+#ifdef __ICCARM__
+#pragma diag_default=Pm123
+#endif /* __ICCARM__ */
+
+/*! \endcond */
+
+#endif /* ADI_CRYPTO_DEF_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/dma/adi_dma.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/dma/adi_dma.c
new file mode 100755
index 00000000000..66474469ea6
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/dma/adi_dma.c
@@ -0,0 +1,346 @@
+/*! *****************************************************************************
+ * @file:    adi_dma.c
+ * @brief:   DMA manager global file.
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+
+
+/*! \addtogroup DMA_Driver DMA Driver
+ *  uDMA Device Driver.
+ *  @{
+ */
+
+/*=============  I N C L U D E S   =============*/
+#include <adi_processor.h>
+#include <drivers/dma/adi_dma.h>
+#include <adi_callback.h>
+#include <rtos_map/adi_rtos_map.h>
+#include <drivers/general/adi_drivers_general.h>
+
+/*! \cond PRIVATE */
+
+/*=============  M I S R A   =============*/
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm011 (rule 6.3): he basic types of char, int, short, long, float, and double should not be used
+*   Need to use bool.
+*
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   The rule makes an exception for memory-mapped register accesses.
+*/
+#pragma diag_suppress=Pm011,Pm140
+#endif /* __ICCARM__ */
+
+/*=============  D E F I N E S  =============*/
+
+/* CCD array allocation macros */
+#define CCD_ALIGN (0x400) /* Memory alignment required for CCD array */
+#define CCD_SIZE (32u)    /* Configure CCD allocation as an integral power of two,
+                            i.e., 24 channels is allocated as 32 */
+
+/*=============  R E G I S T E R    D E F I N E S  =============*/
+
+
+
+
+/*=============  T Y P E    D E F I N E S  =============*/
+
+/*! DMA Channel callback information structure */
+typedef struct _DMA_CHANNEL {
+    ADI_CALLBACK        pfCallback;             /*!< Pointer to the callback func */
+    void*               pCBParam;               /*!< Application Callback param */
+} DMA_CHANNEL_CALLBACK_INFO;
+
+/*! \struct ADI_DMA_DEV_DATA
+ * DMA Device instance data structure
+ *
+ * CallbackInfo[NUM_DMA_CHANNELSn]
+ * The semantics of indexes used to access CallbackInfo elements is defined by the semantics
+ * of the bits in registers DMA_ERRCHNL_CLR and DMA_INVALIDDESC_CLR. The position of these
+ * bits define the channel nodes of the peripheral they map to, e.g. bit N maps to channel
+ * node N.
+ */
+typedef struct {
+    bool                        Initialized;    /*!< track initialization state. See function adi_dma_Init) */
+    DMA_CHANNEL_CALLBACK_INFO   CallbackInfo[NUM_DMA_CHANNELSn];
+    uint32_t                    ChannelsInUse;  /*!< bits 0 to 26 record active channels */
+} ADI_DMA_DEV_DATA;
+
+
+/*=============  D A T A  =============*/
+
+/* DMA descriptor arrays must be contiguous */
+/* AND impose strict alignment requirements */
+/* Each compiler has different alignment directives */
+
+/* ALIGNED: DMA channel control data array declaration */
+ADI_ALIGNED_PRAGMA(CCD_ALIGN)
+static ADI_DCC_TypeDef gChannelControlDataArray[CCD_SIZE * 2u] ADI_ALIGNED_ATTRIBUTE(CCD_ALIGN)
+
+#ifdef ADI_DMA_DESCRIPTORS_IN_VOLATILE_MEMORY
+	/* conditional placement of DMA descriptor table to volatile memory */
+	@ "volatile_ram";
+#else
+	/* default placement to non-volatile memory (no override) */
+	;
+#endif
+
+
+/* pointer to the primary CCD array */
+ADI_DCC_TypeDef* const pPrimaryCCD = &gChannelControlDataArray[0];
+
+/* pointer to the alternate CCD array */
+ADI_DCC_TypeDef* const pAlternateCCD = &gChannelControlDataArray[CCD_SIZE];
+
+
+/*! DMA Device Driver Data instance
+ * 32 Channel Handles initialized to {0, 0}, i.e. call-back function pointer
+ * set to NULL and call-back function parameters set to NULL
+ */
+static ADI_DMA_DEV_DATA DMA_DevData = {
+
+    false,                      /*!< DMA device data not initialized. (See adi_dma_Init) */
+    {{0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0},
+     {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0},
+     {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0},
+     {0,0}, {0,0}, {0,0}},
+    0ul                         /*!< channels-in-use bitfield */
+};
+
+/*! pointer to the DMA Device Driver Data instance */
+static ADI_DMA_DEV_DATA* const pDMA_DevData = &DMA_DevData;
+
+/*=============  Local function declarations  =============*/
+
+/*==========  DMA HANDLERS  ==========*/
+
+/*! DMA Error Handler */
+void DMA_Err_Int_Handler(void);
+
+/*==========  U T I L I T Y    M A C R O S  ==========*/
+
+/*! \endcond*/
+/*=============  A P I    I M P L E M E N T A T I O N S  =============*/
+
+/*!
+ * @brief  Initialize the DMA peripheral
+ *
+ * @return         none
+ *
+ * The application must call this API once
+ *
+ */
+void adi_dma_Init(void)
+{
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+
+    if( false == pDMA_DevData->Initialized )
+    {
+        pDMA_DevData->Initialized = true;
+
+        /* Enable the DMA Controller */
+        pADI_DMA0->CFG |= BITM_DMA_CFG_MEN;
+
+        /* Set descriptor memory base pointer on DMA controller */
+        pADI_DMA0->PDBPTR = (uint32_t)pPrimaryCCD;
+
+        /* Enable the DMA Error Interrupt */
+        NVIC_EnableIRQ(DMA_CHAN_ERR_IRQn);
+
+        /* Reset per-channel, bitmapped control registers (W1C) */
+        const uint32_t w1r_value = (uint32_t) ((1 << NUM_DMA_CHANNELSn) - 1);
+        pADI_DMA0->RMSK_SET        = w1r_value;
+        pADI_DMA0->EN_CLR          = w1r_value;
+        pADI_DMA0->ALT_CLR         = w1r_value;
+        pADI_DMA0->PRI_CLR         = w1r_value;
+        pADI_DMA0->ERRCHNL_CLR     = w1r_value;
+        pADI_DMA0->ERR_CLR         = w1r_value;
+        pADI_DMA0->INVALIDDESC_CLR = w1r_value;
+    }
+
+    ADI_EXIT_CRITICAL_REGION();
+}
+
+/**
+ * @brief    Register a call-back function for a DMA channel.
+ *
+ * @param [in]  eChannelID    The ID of the DMA channel being assigned a call-back function.
+ * @param [in]  pfCallback    Pointer to the application callback function.
+ * @param [in]  pCBParam      Application callback parameter.
+ *
+ * @details  The function registers a call-back function for the DMA channel node
+ * identified by eChannelID and stores the extra parameters this call-back function
+ * may require. A NULL callback function pointer means "DMA channel unused".
+ *
+ * @return   Status
+ *              - #ADI_DMA_SUCCESS                      Successfully registered a call-back function for the given DMA channel node.
+ *              - #ADI_DMA_ERR_NOT_INITIALIZED          [D] adi_dma_Init must be called prior registering a call-back function.
+ *              - #ADI_DMA_ERR_INVALID_PARAMETER        [D] Some parameter(s) passed to the function is invalid.
+ */
+ADI_DMA_RESULT adi_dma_RegisterCallback (
+    DMA_CHANn_TypeDef   const eChannelID,
+    ADI_CALLBACK        const pfCallback,
+    void*               const pCBParam
+    )
+{
+    ADI_DMA_RESULT result = ADI_DMA_SUCCESS;
+
+#ifdef ADI_DEBUG
+    /* DMA must be initialized first */
+    if (false == pDMA_DevData->Initialized) {
+        result = ADI_DMA_ERR_NOT_INITIALIZED;
+    }else{
+        const size_t numChannelId = sizeof(pDMA_DevData->CallbackInfo) / sizeof(DMA_CHANNEL_CALLBACK_INFO);
+        if (numChannelId <= eChannelID)                 /*!< pDMA_DevData->CallbackInfo definition is invalid */
+        {
+            result = ADI_DMA_ERR_INVALID_PARAMETER;
+        }
+    }
+    if (ADI_DMA_SUCCESS == result)              /* if no errors previously detected */
+#endif
+    {
+        /* eChannelID cannot be out of range by definition (we use DMA_CHANn_TypeDef) */
+        DMA_CHANNEL_CALLBACK_INFO * pChannel = &pDMA_DevData->CallbackInfo[eChannelID];
+
+        /* Set the callback parameters */
+        pChannel->pfCallback = pfCallback;      /* assign the pointer to a callback function */
+        pChannel->pCBParam   = pCBParam;        /* store the parameters to be used with the callback function */
+
+        const uint32_t nChannelBit = (1u << eChannelID);
+        if (NULL != pfCallback) {
+            pDMA_DevData->ChannelsInUse |= nChannelBit;         /* set the bit to mark the channel as "being used" */
+        }else{
+            pDMA_DevData->ChannelsInUse &= (~nChannelBit);      /* clear the bit to mark the channel as "not being used" */
+        }
+    }
+    return result;
+}
+
+/*! \cond PRIVATE */
+
+
+#if defined(__ICCARM__)
+
+/* ARM Cortex-M3/M4, IAR compiler (CMSIS standard) */
+#define ADI_CLZ(X)     __CLZ(X)
+
+#elif defined(__GNUC__)
+
+/* ARM Cortex-M3/M4, GNU-ARM compiler */
+#define ADI_CLZ(X)     __builtin_clz(X)
+
+#elif defined(__ARMCC_VERSION)
+
+/* ARM Cortex-M3/M4, Keil compiler */
+#define ADI_CLZ(X)    __clz(X)
+
+#else
+
+#error "Macro ADI_CLZ undefined!!!"
+
+#endif
+
+/*! DMA Error Handler
+ *
+ * The DMA Error handler looks at the channels in use which are flagged in register ERRCHNL_CLR
+ * or INVALIDDESC_CLR and calls the associated call-back functions, if defined. If a call-back
+ * function is undefined (NULL pointer) then it means the associated driver ignores these errors.
+ *
+ * Then, all the bits set in ERRCHNL_CLR and INVALIDDESC_CLR at the time the handler is called
+ * are cleared.
+ */
+void DMA_Err_Int_Handler(void)
+{
+    ISR_PROLOG()
+
+    const uint32_t nErrClr = pADI_DMA0->ERR_CLR;                /* get all the bits set in ERR_CLR */
+    const uint32_t nErrChnClr = pADI_DMA0->ERRCHNL_CLR;         /* get all the bits set in ERRCHNL_CLR */
+    const uint32_t nInvdDescClr = pADI_DMA0->INVALIDDESC_CLR;   /* get all the bits set in INVALIDDESC_CLR */
+
+    /* if there are invalid channel descriptors or channel errors amongts the channels in use */
+    uint32_t functionsToBeCalled = pDMA_DevData->ChannelsInUse & (nErrChnClr | nInvdDescClr);
+
+    if (functionsToBeCalled > 0u)
+    {
+        const uint32_t numBits = sizeof(uint32_t) << 3; /* maximum number of bits to be considered */
+        uint32_t nlz;                                   /* number of leading zeroes in functionsToBeCalled */
+
+        /* For all the bits set in functionsToBeCalled, starting from the MSB */
+        for (nlz = (uint32_t) ADI_CLZ(functionsToBeCalled); nlz < numBits; nlz = (uint32_t) ADI_CLZ(functionsToBeCalled))
+        {
+            const uint32_t bitSet = numBits - nlz - 1u; /* bit position in functionsToBeCalled */
+            const uint32_t selected_bit = ((uint32_t)1u << bitSet);
+            DMA_CHANNEL_CALLBACK_INFO* pChannel = &pDMA_DevData->CallbackInfo[bitSet];
+
+            /* if there's a callback function to be called */
+            if (NULL != pChannel->pfCallback)
+            {
+                /* define the nature of the error: DMA bus error or else invalid descriptor */
+                uint32_t nEvent = ((nErrChnClr & selected_bit) != 0u)
+                                ? (uint32_t)ADI_DMA_EVENT_ERR_BUS
+                                : (uint32_t)ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR;
+
+                /* report the error to the peripheral through the callback function */
+                pChannel->pfCallback (pChannel->pCBParam, nEvent, NULL );
+            }
+
+            functionsToBeCalled &= ~selected_bit;       /* clear bit in functionsToBeCalled */
+        }
+    }
+
+    /* Clear the errors processed in the loop above */
+    pADI_DMA0->ERRCHNL_CLR = nErrChnClr;        /* W1C: clear only all the bits set in nErrChnClr */
+    pADI_DMA0->INVALIDDESC_CLR = nInvdDescClr;  /* W1C: clear only all the bits set in nInvdDescClr */
+    pADI_DMA0->ERR_CLR = nErrClr;               /* W1C: clear only all the bits set in nErrClr */
+
+    ISR_EPILOG()
+}
+
+/*! \endcond*/
+
+/**@}*/
+
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/adc/adi_adc.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/adc/adi_adc.h
new file mode 100755
index 00000000000..1794f4ab2c4
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/adc/adi_adc.h
@@ -0,0 +1,346 @@
+/*! *****************************************************************************
+ * @file    adi_adc.h
+ * @brief   Main include file for ADC Device driver definitions
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_ADC_H
+#define ADI_ADC_H
+
+#include <adi_processor.h>
+#include <adi_callback.h>
+#include <adi_adc_config.h>
+#include <rtos_map/adi_rtos_map.h>  /* for ADI_SEM_SIZE */
+
+/** @addtogroup  ADC_Driver ADC Driver
+*  @{
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! Amount of memory(In bytes) required by the ADC device driver for managing the operation
+ *  of a ADC controller. The memory is passed to the driver when the driver is opended.
+ * The memory is completely owned by the driver till the the driver is closed.
+ *
+ */
+#define ADI_ADC_MEMORY_SIZE (48u + ADI_SEM_SIZE)          /*!< Memory Size of the buffer required by the ADC driver */
+
+
+/*!
+ * \enum ADI_ADC_RESULT
+ * ADC API return codes
+ */
+typedef enum {
+    ADI_ADC_SUCCESS                  = 0,     /*!< No Error, API suceeded */
+    ADI_ADC_INVALID_DEVICE_NUM,               /*!< Invalid device number passed */
+    ADI_ADC_INVALID_DEVICE_HANDLE,            /*!< Invalid device handle passed */
+    ADI_ADC_INVALID_STATE,                    /*!< Invalid State */
+    ADI_ADC_INSUFFICIENT_MEMORY,              /*!< Insufficient memory passed to the driver */
+    ADI_ADC_IN_USE,                           /*!< ADC is alreaady in use */
+    ADI_ADC_INVALID_PARAMETER,                /*!< Invalid parameter passed to the driver */
+    ADI_ADC_NULL_POINTER,                     /*!< Null pointer passed when expecting a valid pointer */
+    ADI_ADC_FAILURE,                          /*!< General ADC Failure */
+    ADI_ADC_INVALID_SEQUENCE,                 /*!< Invalid sequence of API calls */
+    ADI_ADC_ERR_RTOS,                         /*!< RTOS error occurred */
+    ADI_ADC_INVALID_OPERATION,                /*!< API call is an invalid operation */
+    ADI_ADC_INVALID_BUFFER,                   /*!< Buffer passed to the application is invalid */
+    ADI_ADC_BUFFER_OVERFLOW,                  /*!< Buffer overflow occurred */
+    ADI_ADC_DMA_ERROR,			      /*!< DMA Error occurred */
+    ADI_ADC_BAD_SYS_CLOCK,                    /*!< Could not retrieve core clock value. */
+} ADI_ADC_RESULT;
+
+/*!
+ * \enum ADI_ADC_VREF_SRC
+ * Voltage Reference source selection.
+ */
+typedef enum {
+    ADI_ADC_VREF_SRC_INT_1_25_V,        /*!< 1.25V Internal Voltage Reference */
+    ADI_ADC_VREF_SRC_INT_2_50_V,        /*!< 2.50V Internal Voltage Reference */
+    ADI_ADC_VREF_SRC_EXT,               /*!< External Voltage Reference */
+    ADI_ADC_VREF_SRC_VBAT,              /*!< Battery Voltage as Voltage Reference source */
+} ADI_ADC_VREF_SRC;
+
+/*!
+ * \enum ADI_ADC_RESOLUTION
+ * Resolution of the ADC.
+ */
+typedef enum {
+    ADI_ADC_RESOLUTION_12_BIT,      /*!< 12-bit ADC Resolution */
+    ADI_ADC_RESOLUTION_13_BIT,      /*!< 13-bit ADC Resolution */
+    ADI_ADC_RESOLUTION_14_BIT,      /*!< 14-bit ADC Resolution */
+    ADI_ADC_RESOLUTION_15_BIT,      /*!< 15-bit ADC Resolution */
+    ADI_ADC_RESOLUTION_16_BIT       /*!< 16-bit ADC Resolution */
+} ADI_ADC_RESOLUTION;
+
+/*!
+ * \typedef ADI_ADC_CHANNEL
+ * Typedef for ADC Channels
+ */
+typedef uint32_t ADI_ADC_CHANNEL;
+
+/*!
+ * defines for ADC Channels
+ */
+#define    ADI_ADC_CHANNEL_0  (1u << 0u) /*!< ADC Channel 0 */
+#define    ADI_ADC_CHANNEL_1  (1u << 1u) /*!< ADC Channel 1 */
+#define    ADI_ADC_CHANNEL_2  (1u << 2u) /*!< ADC Channel 2 */
+#define    ADI_ADC_CHANNEL_3  (1u << 3u) /*!< ADC Channel 3 */
+#define    ADI_ADC_CHANNEL_4  (1u << 4u) /*!< ADC Channel 4 */
+#define    ADI_ADC_CHANNEL_5  (1u << 5u) /*!< ADC Channel 5 */
+#define    ADI_ADC_CHANNEL_6  (1u << 6u) /*!< ADC Channel 6 */
+#define    ADI_ADC_CHANNEL_7  (1u << 7u) /*!< ADC Channel 7 */
+
+/*!
+ * \enum ADI_ADC_EVENT
+ * Callback events from the ADC driver.
+ */
+typedef enum {
+    ADI_ADC_EVENT_CALIBRATION_DONE,         /*!< Calibration done event.   arg to the callback function will be NULL. */
+    ADI_ADC_EVENT_ADC_READY,	            /*!< ADC Ready event.          arg to the callback function will be null */
+    ADI_ADC_EVENT_OVERFLOW,                 /*!< Overflow event occurred.  The channel(#ADI_ADC_CHANNEL) for which the overflow occurred will be passed as arg to the callback function. */	
+    ADI_ADC_EVENT_HIGH_LIMIT_CROSSED,       /*!< High Limit crossed event. The channel(#ADI_ADC_CHANNEL) for which the limit is crossed will be passed as arg to the callback function. */
+    ADI_ADC_EVENT_LOW_LIMIT_CROSSED,        /*!< Low Limit crossed event.  The channel(#ADI_ADC_CHANNEL) for which the limit is crossed will be passed as arg to the callback function.  */
+} ADI_ADC_EVENT;
+
+/*! Structure which hold the details of the buffer and sampling details */
+typedef struct __ADI_ADC_BUFFER {
+    uint32_t  nChannels;                    /*!<    Channels to sample. Should be an ORed value of #ADI_ADC_CHANNEL enum */
+    void*     pDataBuffer;                  /*!<    Pointer to the Buffer to read the sample value into. If single channel(say Channel 0) is selected
+                                                    then the format of buffer will be <Chan0 conversion 0><Chan0 conversion 1><Chan0 conversion 2>.... but if
+                                                    multiple channels (say Channel 1 and Channel2) are selected then the format of buffer will be
+                                                    <Chan1 conversion 0><Chan2 conversion 0><Chan1 conversion 1><Chan2 conversion 1><Chan1 conversion 2><Chan2 conversion 2>....
+                                                    \n The pBuffer should be 2 byte aligned.
+                                                    \n
+                                                    \n If N is the number of channels selected then in single iteration mode the number of samples
+                                                       written to in the buffer will be N and for multiple iteration, the driver will try to fill the whole
+                                                       buffer with data and it is preferred that the nBuffSize be able to accommodate a multiple of N samples.
+                                              */
+    uint32_t  nNumConversionPasses; /*!< Num of conversion passes */
+    uint32_t  nBuffSize;            /*!< Size of the buffer supplied */
+} ADI_ADC_BUFFER;
+
+/* Type def for the ADC Handle. */
+typedef struct __ADI_ADC_DEVICE* ADI_ADC_HANDLE;  /*!< ADC Device Handler */
+
+
+/*=============  A P I   F U N C T I O N S    P R O T O T Y P E S  =============*/
+
+/* Opens an ADC device instance. */
+ADI_ADC_RESULT adi_adc_Open (
+        uint32_t        nDeviceNum,
+        void*           pMemory,
+        uint32_t        nMemorySize,
+        ADI_ADC_HANDLE* phDevice
+);
+
+/*  Close the given device instance */
+ADI_ADC_RESULT adi_adc_Close(ADI_ADC_HANDLE hDevice);
+
+/* Power up or power down the ADC */
+ADI_ADC_RESULT adi_adc_PowerUp (ADI_ADC_HANDLE hDevice, bool bPowerUp);
+
+/* Register the callback */
+ADI_ADC_RESULT adi_adc_RegisterCallback(
+    ADI_ADC_HANDLE     hDevice,
+    ADI_CALLBACK       pfCallback,
+    void              *pCBParam
+);
+
+/* Enables/Disables the ADC Subsystem */
+ ADI_ADC_RESULT adi_adc_EnableADCSubSystem (
+    ADI_ADC_HANDLE  hDevice,
+    bool            bEnable
+);
+
+/* Returns whether the ADC subsytem is ready */
+ADI_ADC_RESULT adi_adc_IsReady (
+     ADI_ADC_HANDLE  hDevice,
+     bool           *pbReady
+);
+
+/* Set the voltage reference source */
+ADI_ADC_RESULT adi_adc_SetVrefSource (
+    ADI_ADC_HANDLE    hDevice,
+    ADI_ADC_VREF_SRC  eVrefSrc
+);
+
+/* Enable/Disable current sink */
+ADI_ADC_RESULT adi_adc_SinkEnable (
+    ADI_ADC_HANDLE   hDevice,
+    bool             bEnable
+);
+
+/* Start the ADC Calibration */
+ADI_ADC_RESULT adi_adc_StartCalibration (
+    ADI_ADC_HANDLE hDevice
+);
+
+ ADI_ADC_RESULT adi_adc_IsCalibrationDone (
+     ADI_ADC_HANDLE hDevice,
+     bool*          pbCalibrationDone
+ );
+
+
+/* Set the acquisition time of ADC in ADC clock cycles */
+ADI_ADC_RESULT adi_adc_SetAcquisitionTime(
+    ADI_ADC_HANDLE hDevice,
+    uint32_t       nAcqTimeInAClkCycles
+);
+
+/* Set the delay time of ADC in ADC cycles for multi iteration mode */
+ADI_ADC_RESULT adi_adc_SetDelayTime(
+    ADI_ADC_HANDLE hDevice,
+    uint32_t       nDelayInAClkCycles
+);
+
+/* set the resolution of ADC. The default resolution of ADC is 12-bit and the ADC increases the resolution by oversampling */
+ADI_ADC_RESULT adi_adc_SetResolution (
+   ADI_ADC_HANDLE      hDevice,
+   ADI_ADC_RESOLUTION  eResolution
+);
+
+/* Enable Averaging for all ADC channels */
+ADI_ADC_RESULT adi_adc_EnableAveraging (
+    ADI_ADC_HANDLE  hDevice,
+    uint16_t        nAveragingSamples
+);
+
+/* Configure low limit for an ADC channel when it's used as a digital comparator. */
+ADI_ADC_RESULT adi_adc_SetLowLimit (
+    ADI_ADC_HANDLE   hDevice,
+    ADI_ADC_CHANNEL  eChannel,
+    bool             bEnable,
+    uint16_t         nLowLimit
+);
+
+/* Configure high limit for an ADC channel when it's used as a digital comparator. */
+ADI_ADC_RESULT adi_adc_SetHighLimit (
+    ADI_ADC_HANDLE   hDevice,
+    ADI_ADC_CHANNEL  eChannel,
+    bool             bEnable,
+    uint16_t         nHighLimit
+);
+
+
+/* Configure hysteresis for an ADC channel when it's used as a digital comparator. */
+ADI_ADC_RESULT adi_adc_SetHysteresis(
+    ADI_ADC_HANDLE   hDevice,
+    ADI_ADC_CHANNEL  eChannel,
+    bool             bEnable,
+    uint16_t         nHysteresis
+);
+
+/* Configure number of monitor cycles for an ADC channel when it's used as a digital comparator. */
+ADI_ADC_RESULT adi_adc_SetNumMonitorCycles(
+    ADI_ADC_HANDLE   hDevice,
+    ADI_ADC_CHANNEL  eChannel,
+    uint32_t         nNumMonitorCycles
+);
+
+/*  Enable/Disable digital comparator for the given channel(s) */
+ADI_ADC_RESULT adi_adc_EnableDigitalComparator (
+    ADI_ADC_HANDLE   hDevice,
+    bool             bEnableComparator
+);
+
+/* Submit buffer for sampling */
+ADI_ADC_RESULT adi_adc_SubmitBuffer (
+    ADI_ADC_HANDLE      hDevice,
+    ADI_ADC_BUFFER*     pBuffer
+);
+
+/* Get a completed buffer from the driver */
+ADI_ADC_RESULT adi_adc_GetBuffer(
+    ADI_ADC_HANDLE      hDevice,
+    ADI_ADC_BUFFER**    ppBuffer
+);
+
+/* Enable/Disable buffer processing */
+ADI_ADC_RESULT adi_adc_Enable (
+    ADI_ADC_HANDLE  hDevice,
+    bool            bEnable
+);
+
+/* Check whether a completed buffer is available in the driver */
+ADI_ADC_RESULT adi_adc_IsBufferAvailable(
+    ADI_ADC_HANDLE      hDevice,
+    bool*               pbIsBufferAvailable
+);
+
+/* Read the given channels. This will only return once the given amount of samples are collected */
+ADI_ADC_RESULT adi_adc_ReadChannels (
+    ADI_ADC_HANDLE   hDevice,
+    uint32_t         nChannels,
+    uint32_t         nNumConversionPasses,
+    void*            pBuffer,
+    uint32_t         nBuffLength
+);
+
+/* Get Battery Voltage */
+ADI_ADC_RESULT adi_adc_GetBatteryVoltage (
+    ADI_ADC_HANDLE  hDevice,
+    uint32_t        nRefVoltage,
+    uint32_t*       pnBatVoltage
+);
+
+/* Enable/Disable Temperature Sensor */
+ADI_ADC_RESULT adi_adc_EnableTemperatureSensor (
+    ADI_ADC_HANDLE hDevice,
+    bool           bEnable
+    );
+
+/* Get the Temperature Value */
+ADI_ADC_RESULT adi_adc_GetTemperature (
+    ADI_ADC_HANDLE  hDevice,
+    uint32_t        nRefVoltage,
+    int32_t*        pnTemperature
+    );
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+
+
+#endif /* ADI_ADC_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/beep/adi_beep.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/beep/adi_beep.h
new file mode 100755
index 00000000000..6fa441895ec
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/beep/adi_beep.h
@@ -0,0 +1,277 @@
+/*! *****************************************************************************
+ * @file    adi_beep.h
+ * @brief   Main include file for BEEP device driver definitions
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+/** @addtogroup BEEP_Driver BEEP Driver
+*  @{
+*/
+#ifndef ADI_BEEP_H
+#define ADI_BEEP_H
+
+#include "adi_processor.h"
+
+#include <adi_beep_config.h>
+#include <adi_callback.h>
+#include <rtos_map/adi_rtos_map.h> 
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+  
+/*! Amount of memory(In bytes) required by the Beep device driver for managing the operation.
+ * This memory is completely owned by the driver till the end of the operation.
+ */
+#if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1
+/*! @hideinitializer Indicates the size of the BEEP memory to be used */
+#define ADI_BEEP_MEMORY_SIZE        (20u + ADI_SEM_SIZE)
+#else
+/*! @hideinitializer Indicates the size of the BEEP memory to be used */
+#define ADI_BEEP_MEMORY_SIZE        (12u + ADI_SEM_SIZE)
+#endif
+   
+/*!
+ * \enum ADI_BEEP_RESULT
+ * Beeper API return codes
+ */
+typedef enum
+{
+    ADI_BEEP_SUCCESS = 0,            /*!<  No Error, API suceeded */
+
+    ADI_BEEP_FAILURE,                /*!<  An unknown error was detected */
+    ADI_BEEP_ALREADY_INITIALIZED,    /*!<  BEEP is already initialized */
+    ADI_BEEP_BAD_DEV_HANDLE,         /*!<  Invalid device handle passed */
+    ADI_BEEP_BAD_DEV_ID,             /*!<  Asking to initialize an unknown device num */
+    ADI_BEEP_NOT_INITIALIZED,        /*!<  BEEP not yet initialized */
+    ADI_BEEP_PARAM_OUT_OF_RANGE,     /*!<  Parameter is out of range. */
+    ADI_BEEP_INVALID_COUNT,          /*!<  Invalid count for supplied beep sequence */
+    ADI_BEEP_NULL_PTR,               /*!<  Null pointer supplied. */
+    ADI_BEEP_SEMAPHORE_FAILED,       /*!<  BEEP semaphore failure. */
+} ADI_BEEP_RESULT;
+
+
+/*!
+ * \enum ADI_BEEP_DEV_ID
+ *  @brief  Beeper Device IDs.
+ *  @details List of all Beeper Device IDs for the current part
+ */
+typedef enum
+{
+    ADI_BEEP_DEVID_0 = 0,       /*!<  BEEP Timer Device 0 */
+    ADI_BEEP_MAX_DEVID          /*!<  max number of BEEP devices */
+} ADI_BEEP_DEV_ID;
+
+/*!
+ * \enum ADI_BEEP_INTERRUPT
+ *  @brief  Beeper Interrupt Bits.
+ *  @details List of all Beeper interrupt (enables and status) bits.
+ */
+typedef enum
+{
+    ADI_BEEP_INTERRUPT_SEQUENCE_END            = BITM_BEEP_CFG_SEQATENDIRQ,   /*!<  Beeper sequence has finished      */
+    ADI_BEEP_INTERRUPT_NOTE_END                = BITM_BEEP_CFG_AENDIRQ,       /*!<  Beeper note has finished        */
+} ADI_BEEP_INTERRUPT;
+
+
+#define LFCLK_FREQ           32768.0f                                         /*!< Beeper main clock frequency.            */
+#define FREQUENCY_ENCODE(x) (uint8_t)(LFCLK_FREQ/(x) + 0.5f)                  /*!< Beeper tone frequency encoder macro     */
+
+/*!
+ * \enum ADI_BEEP_NOTE_FREQUENCY
+ *  @brief  Beeper tone frequency list.
+ *  @details List of possible Beeper tone frequencies.
+ */
+typedef enum {
+	/* Constants are pre-computed note frequencies (Hz).                 */
+	/* See http://www.phy.mtu.edu/~suits/notefreqs.html.                 */
+	/* Encodings are clock divider values for that note.                 */
+	/* Flats are the same as the lower sharp, so only sharps are listed. */
+	/* Even though octaves are simple frequency doublings/halvings       */
+	/* of adjuacient octaves, we pre-compute each constant (as opposed   */
+	/* to halving/doubling the encodings between octaves) to             */
+	/* minimize repeated doubling/halving errors across all octaves.     */
+	/* !!!ALL ENCODINGS MUST BE IN THE RANGE 4-127!!!                    */
+
+	ADI_BEEP_FREQ_REST = (0),                       /*!< silence */
+
+	ADI_BEEP_FREQ_C4  = FREQUENCY_ENCODE(261.63f),  /*!< Middle C (lowest representable frequency @ 32KHz) */
+	ADI_BEEP_FREQ_Cs4 = FREQUENCY_ENCODE(277.18f),
+	ADI_BEEP_FREQ_D4  = FREQUENCY_ENCODE(293.66f),
+	ADI_BEEP_FREQ_Ds4 = FREQUENCY_ENCODE(311.13f),
+	ADI_BEEP_FREQ_E4  = FREQUENCY_ENCODE(329.63f),
+	ADI_BEEP_FREQ_F4  = FREQUENCY_ENCODE(349.23f),
+	ADI_BEEP_FREQ_Fs4 = FREQUENCY_ENCODE(369.99f),
+	ADI_BEEP_FREQ_G4  = FREQUENCY_ENCODE(392.00f),
+	ADI_BEEP_FREQ_Gs4 = FREQUENCY_ENCODE(415.30f),
+	ADI_BEEP_FREQ_A4  = FREQUENCY_ENCODE(440.00f),
+	ADI_BEEP_FREQ_As4 = FREQUENCY_ENCODE(466.16f),
+	ADI_BEEP_FREQ_B4  = FREQUENCY_ENCODE(493.88f),
+
+	ADI_BEEP_FREQ_C5  = FREQUENCY_ENCODE(523.25f),
+	ADI_BEEP_FREQ_Cs5 = FREQUENCY_ENCODE(554.37f),
+	ADI_BEEP_FREQ_D5  = FREQUENCY_ENCODE(587.33f),
+	ADI_BEEP_FREQ_Ds5 = FREQUENCY_ENCODE(622.25f),
+	ADI_BEEP_FREQ_E5  = FREQUENCY_ENCODE(659.26f),
+	ADI_BEEP_FREQ_F5  = FREQUENCY_ENCODE(698.46f),
+	ADI_BEEP_FREQ_Fs5 = FREQUENCY_ENCODE(739.99f),
+	ADI_BEEP_FREQ_G5  = FREQUENCY_ENCODE(783.99f),
+	ADI_BEEP_FREQ_Gs5 = FREQUENCY_ENCODE(830.61f),
+	ADI_BEEP_FREQ_A5  = FREQUENCY_ENCODE(880.00f),
+	ADI_BEEP_FREQ_As5 = FREQUENCY_ENCODE(932.33f),
+	ADI_BEEP_FREQ_B5  = FREQUENCY_ENCODE(987.77f),
+
+	ADI_BEEP_FREQ_C6  = FREQUENCY_ENCODE(1046.50f),
+	ADI_BEEP_FREQ_Cs6 = FREQUENCY_ENCODE(1108.73f),
+	ADI_BEEP_FREQ_D6  = FREQUENCY_ENCODE(1174.66f),
+	ADI_BEEP_FREQ_Ds6 = FREQUENCY_ENCODE(1244.51f),
+	ADI_BEEP_FREQ_E6  = FREQUENCY_ENCODE(1318.51f),
+	ADI_BEEP_FREQ_F6  = FREQUENCY_ENCODE(1396.91f),
+	ADI_BEEP_FREQ_Fs6 = FREQUENCY_ENCODE(1479.98f),
+	ADI_BEEP_FREQ_G6  = FREQUENCY_ENCODE(1567.98f),
+	ADI_BEEP_FREQ_Gs6 = FREQUENCY_ENCODE(1661.22f),
+	ADI_BEEP_FREQ_A6  = FREQUENCY_ENCODE(1760.00f),
+	ADI_BEEP_FREQ_As6 = FREQUENCY_ENCODE(1864.66f),
+	ADI_BEEP_FREQ_B6  = FREQUENCY_ENCODE(1975.53f),
+
+	ADI_BEEP_FREQ_C7  = FREQUENCY_ENCODE(2093.00f),
+	ADI_BEEP_FREQ_Cs7 = FREQUENCY_ENCODE(2217.46f),
+	ADI_BEEP_FREQ_D7  = FREQUENCY_ENCODE(2349.32f),
+	ADI_BEEP_FREQ_Ds7 = FREQUENCY_ENCODE(2489.02f),
+	ADI_BEEP_FREQ_E7  = FREQUENCY_ENCODE(2637.02f),
+	ADI_BEEP_FREQ_F7  = FREQUENCY_ENCODE(2793.83f),
+	ADI_BEEP_FREQ_Fs7 = FREQUENCY_ENCODE(2959.96f),
+	ADI_BEEP_FREQ_G7  = FREQUENCY_ENCODE(3135.96f),
+	ADI_BEEP_FREQ_Gs7 = FREQUENCY_ENCODE(3322.44f),
+	ADI_BEEP_FREQ_A7  = FREQUENCY_ENCODE(3520.00f),
+	ADI_BEEP_FREQ_As7 = FREQUENCY_ENCODE(3729.31f),
+	ADI_BEEP_FREQ_B7  = FREQUENCY_ENCODE(3951.07f),
+
+	ADI_BEEP_FREQ_C8  = FREQUENCY_ENCODE(4186.01f),
+	ADI_BEEP_FREQ_Cs8 = FREQUENCY_ENCODE(4434.92f),
+	ADI_BEEP_FREQ_D8  = FREQUENCY_ENCODE(4698.64f),
+	ADI_BEEP_FREQ_Ds8 = FREQUENCY_ENCODE(4978.03f),
+	ADI_BEEP_FREQ_E8  = FREQUENCY_ENCODE(5274.04f),
+	ADI_BEEP_FREQ_F8  = FREQUENCY_ENCODE(5587.65f),
+	ADI_BEEP_FREQ_Fs8 = FREQUENCY_ENCODE(5919.91f),
+	ADI_BEEP_FREQ_G8  = FREQUENCY_ENCODE(6271.93f),
+} ADI_BEEP_NOTE_FREQUENCY;
+
+#define ADI_BEEP_DUR_ZERO      (0)                       /*!<  Beeper zero tone duration value          */
+#define ADI_BEEP_DUR_MIN       (1)                       /*!<  Beeper minimum tone duration value       */
+#define ADI_BEEP_DUR_MAX       (254)                     /*!<  Beeper maximum tone duration value       */
+#define ADI_BEEP_DUR_INFINITE  (255)                     /*!<  Beeper infinite tone duration value      */
+
+/*! A device handle used in all API functions to identify the BEEP device. */
+typedef void * ADI_BEEP_HANDLE;
+
+#define DURATION_ENCODE(x) (uint8_t)((float)ADI_BEEP_DUR_MAX/(float)(x) + 0.5f)    /*!<  Beeper tone duration encoder macro      */
+
+/*!
+ * \enum ADI_BEEP_NOTE_DURATION
+ *  @brief  Beeper tone duration list.
+ *  @details List of possible Beeper tone durations.
+ */
+typedef enum {
+	ADI_BEEP_DUR_0         = ADI_BEEP_DUR_ZERO,        /*!<  stop                       */
+	ADI_BEEP_DUR_32_32     = DURATION_ENCODE(1),       /*!<  whole note (1.016 seconds) */
+	ADI_BEEP_DUR_16_32     = DURATION_ENCODE(2),       /*!<  half note                  */
+	ADI_BEEP_DUR_12_32     = DURATION_ENCODE(8/3),     /*!<  three eights note          */
+	ADI_BEEP_DUR_8_32      = DURATION_ENCODE(4),       /*!<  one quarter note           */
+	ADI_BEEP_DUR_6_32      = DURATION_ENCODE(16/3),    /*!<  three sixteenth note       */
+	ADI_BEEP_DUR_4_32      = DURATION_ENCODE(8),       /*!<  one eighth note            */
+	ADI_BEEP_DUR_2_32      = DURATION_ENCODE(16),      /*!<  one sixteenth note         */
+	ADI_BEEP_DUR_1_32      = DURATION_ENCODE(32),      /*!<  one thirty-secondth note   */
+	ADI_BEEP_DUR_N         = ADI_BEEP_DUR_INFINITE,    /*!<  continuous play            */
+} ADI_BEEP_NOTE_DURATION;
+
+/*!
+ * \struct ADI_BEEP_NOTE
+ *  @brief  Beeper note structure.
+ *  @details Describes a note in terms of frequency and duration.
+ */
+typedef struct {
+   ADI_BEEP_NOTE_FREQUENCY frequency;  /*!<  Frequency of the note */
+   ADI_BEEP_NOTE_DURATION  duration;   /*!<  Duration of the note */
+} ADI_BEEP_NOTE;
+
+
+/*================ E X T E R N A L S ==================*/
+
+/*
+ * Beeper API
+ */
+
+ADI_BEEP_RESULT adi_beep_Open                   (ADI_BEEP_DEV_ID          const DeviceNum,
+                                                 void*                    const pMemory,
+                                                 uint32_t                 const MemorySize,
+                                                 ADI_BEEP_HANDLE*         const phDevice);
+
+ADI_BEEP_RESULT adi_beep_RegisterCallback       (ADI_BEEP_HANDLE const hDevice, 
+                                                 ADI_CALLBACK          pfCallback,
+                                                 void* const           pCBParam);
+
+ADI_BEEP_RESULT adi_beep_PlayNote               (ADI_BEEP_HANDLE          const hDevice,
+                                                 ADI_BEEP_NOTE            note);
+
+ADI_BEEP_RESULT adi_beep_PlayTwoTone            (ADI_BEEP_HANDLE          const hDevice, 
+                                                 ADI_BEEP_NOTE            noteA,
+                                                 ADI_BEEP_NOTE            noteB,
+                                                 uint8_t                  count);
+
+ADI_BEEP_RESULT adi_beep_PlaySequence           (ADI_BEEP_HANDLE const hDevice, 
+                                                 ADI_BEEP_NOTE aSequence[], 
+                                                 uint8_t count);
+
+ADI_BEEP_RESULT adi_beep_Enable                 (ADI_BEEP_HANDLE          const hDevice,
+                                                 bool                     const bFlag);
+
+ADI_BEEP_RESULT adi_beep_Wait                   (ADI_BEEP_HANDLE          const hDevice);
+
+ADI_BEEP_RESULT adi_beep_Close                  (ADI_BEEP_HANDLE          const hDevice);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* ADI_BEEP_H */
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/crc/adi_crc.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/crc/adi_crc.h
new file mode 100755
index 00000000000..9fddbc60858
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/crc/adi_crc.h
@@ -0,0 +1,236 @@
+/*! *****************************************************************************
+ * @file    adi_crc.h
+ * @brief   CRC (Cyclic Redundancy Check) Device driver global include file
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders. This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_CRC_H
+#define ADI_CRC_H
+
+/** @addtogroup CRC_Driver CRC Device Driver
+ *  @{
+ */
+
+#include <adi_processor.h>
+
+/*=============  I N C L U D E S   =============*/
+#include <string.h>
+/* Memory size check */
+#include <assert.h>
+
+/* DMA Manager includes */
+#include <drivers/dma/adi_dma.h>
+
+/* Include the config file for CRC */
+#include <adi_crc_config.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*==============  D E F I N E S  ===============*/
+
+#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT == 0)
+
+
+/**
+ * The size of types may vary between building tools (int, char, enumerator, etc.).
+ * This impacts the memory size required by a CRC driver.
+ * Consequently, ADI_CRC_MEMORY_SIZE is environment dependent.
+ */
+#if defined(__ICCARM__)
+/**
+ * The amount of application supplied memory required to operate a core driven CRC device
+ * using a CRC driver built in IAR environment.
+ */
+#define ADI_CRC_MEMORY_SIZE    (32u)
+#else
+/**
+ * The amount of application supplied memory required to operate a core driven CRC device
+ * using a CRC driver built in a generic built environment.
+ * Note: Create a new macro definition for your targetted development environment
+ *       if this generic value was not appropriate in your development environment.
+ */
+#define ADI_CRC_MEMORY_SIZE    (32u)
+#endif
+
+
+#else   /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */
+
+
+/**
+ * The size of types may vary between building tools (int, char, enumerator, etc.).
+ * This impacts the memory size required by a CRC driver.
+ * Consequently, ADI_CRC_MEMORY_SIZE is environment dependent.
+ */
+#if defined(__ICCARM__)
+/**
+ * The amount of application supplied memory required to operate a DMA driven CRC device
+ * using a CRC driver built in IAR environment.
+ */
+#define ADI_CRC_MEMORY_SIZE    (32u)
+#else
+/**
+ * The amount of application supplied memory required to operate a DMA driven CRC device
+ * using a CRC driver built in a generic built environment.
+ * Note: Create a new macro definition for your targetted development environment
+ *       if this generic value was not appropriate in your development environment.
+ */
+#define ADI_CRC_MEMORY_SIZE    (32u)
+#endif
+
+/** Check that a DMA channel can be used with CRC */
+#define ADI_CRC_VALID_DMA_CHANNEL(DMA_CHANNEL_ID) ((SIP0_CHANn<=(DMA_CHANNEL_ID)) && ((DMA_CHANNEL_ID)<=SIP7_CHANn))
+
+/**
+ * CRC events used in CRC callback functions to report
+ * - the completion of a DMA driven CRC request
+ * - errors detected when executing a DMA driven CRC request
+ */
+typedef enum __ADI_CRC_EVENT
+{
+    /*! DMA driven CRC peripheral has completed processing a request */
+    ADI_CRC_EVENT_BUFFER_PROCESSED = ADI_DMA_EVENT_BUFFER_PROCESSED,
+
+    /*! DMA driven CRC peripheral has encountered a problem when processing a request */
+    ADI_CRC_EVENT_ERROR
+} ADI_CRC_EVENT;
+
+#endif  /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */
+
+/**
+ * A device handle used in all API functions to identify a CRC device.
+ * This handle is obtained when opening a CRC driver using adi_crc_Open.
+ * It stops being valid after closing the CRC driver using adi_crc_Close.
+ */
+typedef struct __ADI_CRC_DEVICE*  ADI_CRC_HANDLE;
+
+/**
+ *  CRC driver return codes
+ */
+typedef enum
+{
+    ADI_CRC_SUCCESS = 0,                /*!< 0x00 - Generic success */
+    ADI_CRC_FAILURE,                    /*!< 0x01 - Generic failure */
+    ADI_CRC_IN_USE,                     /*!< 0x02 - Supplied CRC device number is already open and in use */
+    ADI_CRC_INSUFFICIENT_MEMORY,        /*!< 0x03 - Supplied memory is insufficient to operate the CRC device */
+    ADI_CRC_FN_NOT_SUPPORTED,           /*!< 0x04 - Function not supported */
+    ADI_CRC_FN_NOT_PERMITTED,           /*!< 0x05 - Function not permitted at current stage */
+    ADI_CRC_BAD_HANDLE,                 /*!< 0x06 - Bad CRC device handle (can be caused by a CRC device not opened)*/
+    ADI_CRC_BAD_DEVICE_NUMBER,          /*!< 0x07 - There is no CRC device identified by this number */
+    ADI_CRC_INVALID_DMA_CHANNEL,        /*!< 0x08 - Invalid DMA channel assigned to a CRC driver */
+    ADI_CRC_INVALID_PARAMETER,          /*!< 0x09 - Invalid parameter used in a CRC function */
+} ADI_CRC_RESULT;
+
+/*=======  P U B L I C   P R O T O T Y P E S  ========*/
+/*            (globally-scoped functions)             */
+
+/* Opens a CRC device instance */
+ADI_CRC_RESULT adi_crc_Open(
+    uint32_t                    DeviceNum,
+    void                        *pMemory,
+    uint32_t                    MemorySize,
+    ADI_CRC_HANDLE              *phDevice);
+
+/* Closes a CRC device instance */
+ADI_CRC_RESULT adi_crc_Close(
+    ADI_CRC_HANDLE const        hDevice);
+
+/* Registers or unregisters a callback, used by the CRC interrupt handler or with DMA driven operations, with the CRC device */
+ADI_CRC_RESULT adi_crc_RegisterCallback(
+    ADI_CRC_HANDLE const        hDevice,
+    ADI_CALLBACK                pfCallback,
+    void *const                 pCBParam);
+
+/* Sets the 32-bit polynomial for CRC operations */
+ADI_CRC_RESULT adi_crc_SetPolynomialVal(
+    ADI_CRC_HANDLE const        hDevice,
+    uint32_t                    PolynomialVal);
+
+/* Submits data buffer for CRC operation */
+ADI_CRC_RESULT adi_crc_Compute(
+    ADI_CRC_HANDLE const        hDevice,
+    void                        *pCrcBuf,
+    uint32_t                    NumBytes,
+    uint32_t                    NumBits);
+
+/* Gets the current CRC peripheral status */
+ADI_CRC_RESULT adi_crc_IsCrcInProgress(
+    ADI_CRC_HANDLE const        hDevice,
+    bool                        *pbCrcInProgress);
+
+/* Gets the final CRC result computed for a data stream */
+ADI_CRC_RESULT adi_crc_GetFinalCrcVal(
+    ADI_CRC_HANDLE const        hDevice,
+    uint32_t                    *pFinalCrcVal);
+
+/* Gets the current/intermediate CRC result computed for a data stream */
+ADI_CRC_RESULT adi_crc_GetCurrentCrcVal(
+    ADI_CRC_HANDLE const        hDevice,
+    uint32_t                    *pCurrentCrcVal);
+
+ADI_CRC_RESULT  adi_crc_SetBitMirroring(
+    ADI_CRC_HANDLE const        hDevice,
+    const bool                  bEnable);
+
+ADI_CRC_RESULT  adi_crc_SetByteMirroring(
+    ADI_CRC_HANDLE const        hDevice,
+    const bool                  bEnable);
+
+ADI_CRC_RESULT  adi_crc_EnableWordSwap(
+    ADI_CRC_HANDLE const        hDevice,
+    const bool                  bEnable);
+
+ADI_CRC_RESULT adi_crc_SetCrcSeedVal(
+    ADI_CRC_HANDLE const        hDevice,
+    uint32_t                    CrcSeedVal);
+
+ADI_CRC_RESULT  adi_crc_SetLSBFirst(
+    ADI_CRC_HANDLE const        hDevice,
+    const bool                  bEnable);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* ADI_CRC_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/crypto/adi_crypto.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/crypto/adi_crypto.h
new file mode 100755
index 00000000000..7b34cbcd9e3
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/crypto/adi_crypto.h
@@ -0,0 +1,326 @@
+/*! *****************************************************************************
+ * @file    adi_crypto.h
+ * @brief   Main include file for CRYPTO Device driver definitions
+ -----------------------------------------------------------------------------
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+
+/** @addtogroup Crypto_Driver Crypto Driver
+*  @{
+*/
+
+#ifndef ADI_CRYPTO_H
+#define ADI_CRYPTO_H
+
+ /*! \cond PRIVATE */
+#include <adi_processor.h>
+#include <adi_callback.h>
+#include <rtos_map/adi_rtos_map.h>  /* for ADI_SEM_SIZE */
+/*! \endcond */
+#include <adi_crypto_config.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/*!
+ * \enum ADI_CRYPTO_RESULT
+ * Crypto API return codes
+ */
+typedef enum
+{
+    ADI_CRYPTO_SUCCESS = 0,              /*!<  No Error, API suceeded.                                   */
+    ADI_CRYPTO_ERR_ALREADY_INITIALIZED,  /*!<  Crypto is already initialized.                            */
+    ADI_CRYPTO_ERR_BAD_BUFFER,           /*!<  Invalid buffer parameters.                                */
+    ADI_CRYPTO_ERR_BAD_CONFIG,           /*!<  Invalid device config parameters passed.                  */
+    ADI_CRYPTO_ERR_BAD_DEVICE_NUM,       /*!<  Invalid device instance number.                           */
+    ADI_CRYPTO_ERR_BAD_DEV_HANDLE,       /*!<  Invalid device handle passed.                             */
+    ADI_CRYPTO_ERR_COMPUTE_ACTIVE,       /*!<  Computation underway.                                     */
+    ADI_CRYPTO_ERR_DMA_BUS_FAULT,        /*!<  Runtime DMA bus fault detected.                           */
+    ADI_CRYPTO_ERR_DMA_INVALID_DESCR,    /*!<  Runtime DMA invalid descriptor detected.                  */
+    ADI_CRYPTO_ERR_DMA_REGISTER,         /*!<  Error registering DMA error callback function.            */
+    ADI_CRYPTO_ERR_DMA_UNKNOWN_ERROR,    /*!<  Unknown runtime DMA error detected.                       */
+    ADI_CRYPTO_ERR_INSUFFICIENT_MEM,     /*!<  Insufficient memory passed to the driver.                 */
+    ADI_CRYPTO_ERR_INVALID_PARAM,        /*!<  Invalid function parameter.                               */
+    ADI_CRYPTO_ERR_INVALID_STATE,        /*!<  Operation failed since the device is in an invalid state. */
+    ADI_CRYPTO_ERR_SEMAPHORE_FAILED,     /*!<  Failure in semaphore functions.                           */
+    ADI_CRYPTO_ERR_INVALID_KEY_SIZE,     /*!<  bad key size fault detected.                              */
+#if (1 == ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT)
+    ADI_CRYPTO_PK_ALREADY_ENABLED,       /*!<  PKSTOR is already enabled.                                */
+    ADI_CRYPTO_PK_ALREADY_DISABLED,      /*!<  PKSTOR is already disabled.                               */
+    ADI_CRYPTO_PK_NOT_ENABLED,           /*!<  PKSTOR operation attempted while PKSTOR is disabled.      */
+    ADI_CRYPTO_PK_INVALID_KUWLEN,        /*!<  Invalid KUW length parameter.                             */
+    ADI_CRYPTO_PK_INVALID_KEY_INDEX,     /*!<  PKSTOR key index overflow.                                */
+    ADI_CRYPTO_PK_CMD_BUSY,              /*!<  command busy bit set after PKSTOR command done.           */
+    ADI_CRYPTO_PK_CMD_FAULT,             /*!<  command fault bit set during PKSTOR command.              */
+    ADI_CRYPTO_PK_CMD_ECC_FAULT,         /*!<  ECC errors detected during PKSTOR command.                */
+#endif
+} ADI_CRYPTO_RESULT;
+
+/*!
+ * \enum ADI_CRYPTO_EVENT
+ * Crypto callback events
+ */
+typedef enum
+{
+    /* successful buffer completion events */
+    ADI_CRYPTO_EVENT_STATUS_CBC_DONE,        /*!<  CBC operation is complete.         */
+    ADI_CRYPTO_EVENT_STATUS_CCM_DONE,        /*!<  CCM operation is complete.         */
+    ADI_CRYPTO_EVENT_STATUS_CMAC_DONE,       /*!<  CMAC operation is complete.        */
+    ADI_CRYPTO_EVENT_STATUS_CTR_DONE,        /*!<  CTR operation is complete.         */
+    ADI_CRYPTO_EVENT_STATUS_ECB_DONE,        /*!<  ECB operation is complete.         */
+#if defined (__ADUCM4x50__)
+    ADI_CRYPTO_EVENT_STATUS_HMAC_DONE,       /*!<  HMAC operation is complete.        */
+#else
+    ADI_CRYPTO_RESERVED_EVENT,               /*!<  reserved: preserves ordering       */
+#endif /*__ADUCM4x50*/
+    ADI_CRYPTO_EVENT_STATUS_SHA_DONE,        /*!<  SHA operation is complete.         */
+
+    /* other events */
+    ADI_CRYPTO_EVENT_DMA_BUS_ERROR,          /*!<  DMA bus error encountered.         */
+    ADI_CRYPTO_EVENT_DMA_DESCRIPTOR_ERROR,   /*!<  DMA descriptor error encountered.  */
+    ADI_CRYPTO_EVENT_DMA_UNKNOWN_ERROR,      /*!<  DMA unknown error encountered.     */
+    ADI_CRYPTO_EVENT_STATUS_INPUT_OVERFLOW,  /*!<  Input overflow error encountered.  */
+    ADI_CRYPTO_EVENT_STATUS_UNKNOWN,         /*!<  Unknown error encountered.         */
+} ADI_CRYPTO_EVENT;
+
+/*! The amount of application supplied memory used by the CRYPTO driver to store internal state. */
+#if defined (__ADUCM4x50__)
+#define ADI_CRYPTO_MEMORY_SIZE          (96u + ADI_SEM_SIZE)  /*!< Required user memory size for ADuCM4x50 processor family. */
+#elif defined (__ADUCM302x__)
+#define ADI_CRYPTO_MEMORY_SIZE          (84u + ADI_SEM_SIZE)  /*!< Required user memory size for ADuCM302x processor family. */
+#else
+#error Crypto driver is not ported to this proccesor
+#endif
+
+/*! A device handle used in all API functions to identify the flash device. */
+typedef struct __ADI_CRYPTO_DEV_DATA_TYPE* ADI_CRYPTO_HANDLE;
+
+/*! Number of bytes to allocate for SHA256 hash outputs */
+#define ADI_CRYPTO_SHA_HASH_BYTES        (256u/8u)
+
+/*! Computation mode(Encryption/Decryption) for given buffers */
+typedef enum
+{
+    ADI_CRYPTO_DECODE = (0u << BITP_CRYPT_CFG_ENCR),    /*!< Encoding mode is decryption. */
+    ADI_CRYPTO_ENCODE = (1u << BITP_CRYPT_CFG_ENCR),    /*!< Encoding mode is encryption. */
+} ADI_CRYPTO_CODING_MODE;
+
+/*! Enum for the AES KEY Length */
+typedef enum
+{
+    ADI_CRYPTO_AES_KEY_LEN_128_BIT = (0u << BITP_CRYPT_CFG_AESKEYLEN),     /*!< KEY length is 128 bits. */
+    ADI_CRYPTO_AES_KEY_LEN_256_BIT = (2u << BITP_CRYPT_CFG_AESKEYLEN),     /*!< KEY length is 256 bits. */
+} ADI_CRYPTO_AES_KEY_LEN;
+
+#if defined (__ADUCM4x50__)
+/*! Enable byte swapping for KEY writes */
+typedef enum
+{
+    ADI_CRYPTO_KEY_LITTLE_ENDIAN = (0u << BITP_CRYPT_CFG_KEY_BYTESWAP),    /*!< Do not apply KEY write byte swaps. */
+    ADI_CRYPTO_KEY_BIG_ENDIAN    = (1u << BITP_CRYPT_CFG_KEY_BYTESWAP),    /*!< Apply KEY write byte swaps.        */
+} ADI_CRYPTO_KEY_BYTE_SWAP;
+#endif /*__ADUCM4x50__*/
+
+#if defined (__ADUCM4x50__)
+/*! Byte-swap the SHA Input Data */
+typedef enum
+{
+    ADI_CRYPTO_SHA_LITTLE_ENDIAN = (0u << BITP_CRYPT_CFG_SHA_BYTESWAP),    /*!< Do not apply SHA data write byte swaps. */
+    ADI_CRYPTO_SHA_BIG_ENDIAN    = (1u << BITP_CRYPT_CFG_SHA_BYTESWAP),    /*!< Apply SHA data write byte swaps. */
+} ADI_CRYPTO_SHA_BYTE_SWAP;
+#endif /*__ADUCM4x50__*/
+
+/*! Byte-swap the AES Input Data */
+typedef enum
+{
+    ADI_CRYPTO_AES_LITTLE_ENDIAN = (0u << BITP_CRYPT_CFG_AES_BYTESWAP),    /*!< Do not apply AES data write byte swaps. */
+    ADI_CRYPTO_AES_BIG_ENDIAN    = (1u << BITP_CRYPT_CFG_AES_BYTESWAP),    /*!< Apply AES data write byte swaps. */
+} ADI_CRYPTO_AES_BYTE_SWAP;
+
+/*!
+ * \enum ADI_CRYPTO_CIPHER_MODE
+ * Enum for the cipher modes.
+ */
+typedef enum {
+    ADI_CRYPTO_MODE_CBC  = BITM_CRYPT_CFG_CBCEN,     /*!< Select CBC cipher mode. */
+    ADI_CRYPTO_MODE_CCM  = BITM_CRYPT_CFG_CCMEN,     /*!< Select CCM cipher mode. */
+    ADI_CRYPTO_MODE_CMAC = BITM_CRYPT_CFG_CMACEN,    /*!< Select CMAC cipher mode. */
+    ADI_CRYPTO_MODE_CTR  = BITM_CRYPT_CFG_CTREN,     /*!< Select CTR cipher mode. */
+    ADI_CRYPTO_MODE_ECB  = BITM_CRYPT_CFG_ECBEN,     /*!< Select ECB cipher mode. */
+#if defined (__ADUCM4x50__)
+    ADI_CRYPTO_MODE_HMAC = BITM_CRYPT_CFG_HMACEN,    /*!< Select HMAC cipher mode. */
+#endif /*__ADUCM4x50__*/
+    ADI_CRYPTO_MODE_SHA  = BITM_CRYPT_CFG_SHA256EN,  /*!< Select SHA cipher mode. */
+} ADI_CRYPTO_CIPHER_MODE;
+
+
+#if (1 == ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT)
+/*! PKSTOR Key Wrap/Unwrap key lengths */
+typedef enum
+{
+	ADI_PK_KUW_LEN_128       = (1u << BITP_CRYPT_CFG_KUWKEYLEN),       /*!< key wrap/unwrap size is 128-bit. */
+	ADI_PK_KUW_LEN_256       = (2u << BITP_CRYPT_CFG_KUWKEYLEN),       /*!< key wrap/unwrap size is 256-bit. */
+	ADI_PK_KUW_LEN_512       = (3u << BITP_CRYPT_CFG_KUWKEYLEN),       /*!< key wrap/unwrap size is 512-bit (compute-only; not store). */
+} ADI_CRYPTO_PK_KUW_LEN;
+#endif /*ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT*/
+
+
+#if (1 == ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT)
+/*! PKSTOR commands */
+typedef enum
+{
+	ADI_PK_CMD_WRAP_KUW      = (0x1 << BITP_CRYPT_PRKSTORCFG_CMD),       /*!< KUW wrap command. */
+	ADI_PK_CMD_UNWRAP_KUW    = (0x2 << BITP_CRYPT_PRKSTORCFG_CMD),       /*!< KUW unwrap command. */
+	ADI_PK_CMD_RESET_KUW     = (0x3 << BITP_CRYPT_PRKSTORCFG_CMD),       /*!< clear all KUW registers command. */
+	ADI_PK_CMD_USE_KEY       = (0x4 << BITP_CRYPT_PRKSTORCFG_CMD),       /*!< load Key registers from KUW registers command. */
+	ADI_PK_CMD_USE_DEV_KEY   = (0x5 << BITP_CRYPT_PRKSTORCFG_CMD),       /*!< load Key registers with devide key command. */
+	/* gap */
+	ADI_PK_CMD_RETRIEVE_KEY  = (0x8 << BITP_CRYPT_PRKSTORCFG_CMD),       /*!< load KUW registers command. */
+	ADI_PK_CMD_STORE_KEY     = (0x9 << BITP_CRYPT_PRKSTORCFG_CMD),       /*!< program KUW registers into flash command. */
+	ADI_PK_CMD_ERASE_KEY     = (0xA << BITP_CRYPT_PRKSTORCFG_CMD),       /*!< erase single key set from flash command. */
+	ADI_PK_CMD_ERASE_PAGE    = (0xB << BITP_CRYPT_PRKSTORCFG_CMD),       /*!< erase entire key page command. */
+} ADI_CRYPTO_PK_CMD;
+#endif /*ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT*/
+
+
+/*! superset user Crypto transaction structure (different elements used for different modes) */
+typedef struct
+{
+    ADI_CRYPTO_CIPHER_MODE    eCipherMode;        /*!< Cipher mode to use */
+    ADI_CRYPTO_CODING_MODE    eCodingMode;        /*!< Coding Mode (Encryption or Decryption) */
+#if defined (__ADUCM4x50__)
+    ADI_CRYPTO_KEY_BYTE_SWAP  eKeyByteSwap;       /*!< KEY endianness */
+    ADI_CRYPTO_SHA_BYTE_SWAP  eShaByteSwap;       /*!< SHA endianness */
+#endif /*__ADUCM4x50__*/
+    ADI_CRYPTO_AES_BYTE_SWAP  eAesByteSwap;       /*!< AES endianness */
+
+    uint8_t                  *pKey;               /*!< Pointer to the KEY data: pre-formatted as a byte array, according to eAesKeyLen. */
+    ADI_CRYPTO_AES_KEY_LEN    eAesKeyLen;         /*!< The length of the AES KEY */
+
+    uint32_t                 *pAuthData;          /*!< CCM mode: pointer to user prefix buffer */
+    uint32_t                  numAuthBytes;       /*!< Length of the prefix buffer in bytes (should be a multiple of 16 bytes) */
+
+    uint32_t                 *pInputData;         /*!< Pointer to user input data buffer */
+    uint32_t                  numInputBytes;      /*!< Length of the data buffer in bytes (should be a multiple of 16bytes) */
+
+    uint32_t                 *pOutputData;        /*!< Pointer to user output buffer */
+    uint32_t                  numOutputBytes;     /*!< Length of the output buffer in bytes (should be a multiple of 16bytes) */
+
+    uint8_t                  *pNonceIV;           /*!< Pointer to user 16-byte array containing one of three values, depending on cipher mode:\n
+                                                       - CTR mode = 108-bit NONCE\n
+                                                       - CCM mode = 112-bit NONCE\n
+                                                       - CBC mode = 128-bit IV (Initialization Vector)\n\n
+                                                       NONCE and IV assume little endian format, for example: CTR NONCE packing is:\n
+                                                       - NONCE[0]            ->   7:0\n
+                                                       - NONCE[1]            ->  15:8\n
+                                                       -   ...\n
+                                                       - NONCE[13]           -> 103:96\n
+                                                       - NONCE[14](Bits 3:0) -> 107:104\n
+                                                   */
+    uint32_t                  CounterInit;        /*!< CTR/CCM mode: Counter Initialization Value (CTR=20-bit, CCM=16-bit) */
+    uint32_t                  numValidBytes;      /*!< CCM mode: Number of valid bytes in the last (padding) block (1-16) */
+    uint32_t                  numShaBits;         /*!< SHA mode: Number of bits in the SHA payload, which may be odd-sized */
+
+#if (1 == ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT)
+	/* PKSTOR extensions used only in context of overriding above key info with protected keys stored in flash. */
+    /* Assumes previously wrapped keys have already been stored using adi_crypto_pk_Xxx APIs. */
+    /* NOTE: Enabeling PKSTOR boolean results in explicit key loads being replaced with PKSTOR keys prior to all Crypto operations */
+    /* When enabled, the PKSTOR sequence is to RETRIEVE, UNWRAP and USE whichever key index and size is designated below. */
+
+    bool                      bUsePKSTOR;        /*!< Flag that controls use of PKSTOR key overrides. */
+    ADI_CRYPTO_PK_KUW_LEN     pkKuwLen;          /*!< KUW key size */
+    uint8_t                   pkIndex;           /*!< Flash index within PKSTOR for storing/rettrieving keys. */
+#endif
+} ADI_CRYPTO_TRANSACTION;
+
+
+/*================ PUBLIC API ==================*/
+
+
+ADI_CRYPTO_RESULT adi_crypto_Open                  (uint32_t const nDeviceNum, void * const pMemory, uint32_t const nMemorySize, ADI_CRYPTO_HANDLE * const phDevice);
+ADI_CRYPTO_RESULT adi_crypto_Close                 (ADI_CRYPTO_HANDLE const hDevice);
+ADI_CRYPTO_RESULT adi_crypto_RegisterCallback      (ADI_CRYPTO_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void * const pCBParam);
+ADI_CRYPTO_RESULT adi_crypto_Enable                (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable);
+
+ADI_CRYPTO_RESULT adi_crypto_SubmitBuffer          (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_TRANSACTION * const pBuffer);
+ADI_CRYPTO_RESULT adi_crypto_GetBuffer             (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_TRANSACTION ** const ppBuffer);
+ADI_CRYPTO_RESULT adi_crypto_IsBufferAvailable     (ADI_CRYPTO_HANDLE const hDevice, bool * const pbAvailable);
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+ADI_CRYPTO_RESULT adi_crypto_EnableDmaMode         (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable);
+#endif
+
+#if (1 == ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT)
+ADI_CRYPTO_RESULT adi_crypto_pk_EnablePKSTOR       (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable);
+
+ADI_CRYPTO_RESULT adi_crypto_pk_SetValString       (ADI_CRYPTO_HANDLE const hDevice, uint8_t * const pValStr);
+ADI_CRYPTO_RESULT adi_crypto_pk_GetValString       (ADI_CRYPTO_HANDLE const hDevice, uint8_t * const pValStr);
+
+ADI_CRYPTO_RESULT adi_crypto_pk_SetKuwLen          (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_PK_KUW_LEN const kuwDataLen);
+ADI_CRYPTO_RESULT adi_crypto_pk_SetKuwReg          (ADI_CRYPTO_HANDLE const hDevice, uint8_t * const pKuwData);
+ADI_CRYPTO_RESULT adi_crypto_pk_WrapKuwReg         (ADI_CRYPTO_HANDLE const hDevice);
+ADI_CRYPTO_RESULT adi_crypto_pk_UnwrapKuwReg       (ADI_CRYPTO_HANDLE const hDevice);
+ADI_CRYPTO_RESULT adi_crypto_pk_ResetKuwReg        (ADI_CRYPTO_HANDLE const hDevice);
+
+ADI_CRYPTO_RESULT adi_crypto_pk_UseDecryptedKey    (ADI_CRYPTO_HANDLE const hDevice);
+ADI_CRYPTO_RESULT adi_crypto_pk_LoadDeviceKey      (ADI_CRYPTO_HANDLE const hDevice);
+
+ADI_CRYPTO_RESULT adi_crypto_pk_RetrieveKey        (ADI_CRYPTO_HANDLE const hDevice, uint8_t const index);
+ADI_CRYPTO_RESULT adi_crypto_pk_StoreKey           (ADI_CRYPTO_HANDLE const hDevice, uint8_t const index);
+ADI_CRYPTO_RESULT adi_crypto_pk_DestroyKey         (ADI_CRYPTO_HANDLE const hDevice, uint8_t const index);
+ADI_CRYPTO_RESULT adi_crypto_pk_ErasePage          (ADI_CRYPTO_HANDLE const hDevice, uint8_t const index);
+#endif  /* ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* include guard */
+
+/*
+** EOF
+*/
+
+/*@}*/
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/dma/adi_dma.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/dma/adi_dma.h
new file mode 100755
index 00000000000..5b6adde5f86
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/dma/adi_dma.h
@@ -0,0 +1,276 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_dma.h
+ * @brief:   DMA Device Definitions for ADuCxxx
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ADI_DMA_MODE_PING_PONG
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/*! \addtogroup DMA_Driver DMA Driver
+ *  @{
+ *  @brief DMA Driver
+ *  @details This driver is intended to be used only by the device drivers and not by the application.
+ *  @note The device drivers must include drivers/dma/adi_dma.h to use this driver     
+ */
+
+#ifndef ADI_DMA__H__
+#define ADI_DMA__H__
+
+#include <adi_callback.h>
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*=============  D E F I N E S  =============*/
+/*! Amount of memory(In bytes) required by the DMA manager for managing the operation
+ *  This memory is completely owned by the driver till the end of the operation.
+ */
+
+/*============= D A T A T Y P E S =============*/
+
+
+/*!
+ * Dma Data Increments
+ */
+typedef enum
+{
+    ADI_DMA_INCR_1_BYTE    = 0x00u,     /*!< Byte increment */
+    ADI_DMA_INCR_2_BYTE    = 0x01u,     /*!< Half word increment */
+    ADI_DMA_INCR_4_BYTE    = 0x02u,     /*!< Word increment */
+    ADI_DMA_INCR_NONE      = 0x03u,     /*!< No increment */
+
+    ADI_DMA_DECR_1_BYTE    = 0x10u,     /*!< Byte decrement */
+    ADI_DMA_DECR_2_BYTE    = 0x11u,     /*!< Half word decrement */
+    ADI_DMA_DECR_4_BYTE    = 0x12u      /*!< Word decrement */
+
+} ADI_DMA_INCR_TYPE;
+
+/*!
+ *  DMA Callback Events
+ */
+typedef enum
+{
+    ADI_DMA_EVENT_BUFFER_PROCESSED,          /*!< Buffer processed event */
+    ADI_DMA_EVENT_ERR_BUS,                   /*!< Bus Error Occurred Event */
+    ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR     /*!< Invalid Descriptor Event */
+} ADI_DMA_EVENT;
+
+
+/*!
+ * Dma Data Widths
+ */
+typedef enum
+{
+    ADI_DMA_WIDTH_1_BYTE      = 0x0,      /*!<  8-bit */
+    ADI_DMA_WIDTH_2_BYTE      = 0x1,      /*!< 16-bit */
+    ADI_DMA_WIDTH_4_BYTE      = 0x2       /*!< 32-bit */
+} ADI_DMA_WIDTH_TYPE;
+
+
+/*!
+ * Dma Rearbitration Intervals (chunk size between bus arbitrations)
+ */
+typedef enum
+{
+    ADI_DMA_RPOWER_1 = 0,                       /*!< Rearbitrate after    1 transfer */
+    ADI_DMA_RPOWER_2,                           /*!< Rearbitrate after    2 transfers */
+    ADI_DMA_RPOWER_4,                           /*!< Rearbitrate after    4 transfers */
+    ADI_DMA_RPOWER_8,                           /*!< Rearbitrate after    8 transfers */
+    ADI_DMA_RPOWER_16,                          /*!< Rearbitrate after   16 transfers */
+    ADI_DMA_RPOWER_32,                          /*!< Rearbitrate after   32 transfers */
+    ADI_DMA_RPOWER_64,                          /*!< Rearbitrate after   64 transfers */
+    ADI_DMA_RPOWER_128,                         /*!< Rearbitrate after  128 transfers */
+    ADI_DMA_RPOWER_256,                         /*!< Rearbitrate after  256 transfers */
+    ADI_DMA_RPOWER_512,                         /*!< Rearbitrate after  512 transfers */
+    ADI_DMA_RPOWER_1024                         /*!< Rearbitrate after 1024 transfers */
+} ADI_DMA_RPOWER;
+
+
+/*!
+ * Dma Transfer Modes
+ */
+typedef enum
+{
+    ADI_DMA_MODE_BASIC,                         /*!< Basic mode */
+    ADI_DMA_MODE_AUTO,                          /*!< Auto request mode */
+    ADI_DMA_MODE_PING_PONG,                     /*!< Ping pong mode */
+    ADI_DMA_MODE_MSG,                           /*!< Memory Scatter gather mode (not valid as no Memory DMA support) */
+    ADI_DMA_MODE_PSG                            /*!< Peripheral Scatter mode */
+} ADI_DMA_MODE;
+
+
+/*!
+ * Dma Channel Priority Settings (only HIGH or DEFAULT priority supported)
+ */
+typedef enum
+{
+    ADI_DMA_PRIORITY_DEFAULT = 0,                       /*!< Use DEFAULT channel priority */
+    ADI_DMA_PRIORITY_HIGH                              /*!< Elevate channel to HIGH priority */
+} ADI_DMA_PRIORITY;
+
+
+/*!
+ * Result Event Type
+ */
+typedef enum {
+    ADI_DMA_SUCCESS,                    /*!< Successfully Completed */
+    ADI_DMA_ERR_NOT_INITIALIZED,        /*!< DMA not initialized */
+    ADI_DMA_ERR_INVALID_PARAMETER,      /*!< Input parameter to the function is invalid */
+} ADI_DMA_RESULT;
+
+/*! \cond PRIVATE*/
+/*!
+ * \enum DMA_CHANn_TypeDef
+ * DMA Channel Assignments
+ */
+typedef enum
+{
+    SPI2_TX_CHANn       =  0,  /*!< SPI2 Transmit DMA channel                */
+    SPI2_RX_CHANn       =  1,  /*!< SPI2 Receive DMA channel                 */
+    SPORT0A_CHANn       =  2,  /*!< SPORT0-A  DMA channel                    */
+    SPORT0B_CHANn       =  3,  /*!< SPORT0-B  DMA channel                    */
+    SPI0_TX_CHANn       =  4,  /*!< SPI0 Transmit DMA channel                */
+    SPI0_RX_CHANn       =  5,  /*!< SPI0 Receive DMA channel                 */
+    SPI1_TX_CHANn       =  6,  /*!< SPI1 Transmit DMA channel                */
+    SPI1_RX_CHANn       =  7,  /*!< SPI1 Receive DMA channel                 */
+    UART0_TX_CHANn      =  8,  /*!< UART0 Transmit DMA channel               */
+    UART0_RX_CHANn      =  9,  /*!< UART0 Receive DMA channel                */
+    I2CS_TX_CHANn       = 10,  /*!< I2C Slave Transmit DMA channel           */
+    I2CS_RX_CHANn       = 11,  /*!< I2C Slave Receive DMA channel            */
+    I2CM_CHANn          = 12,  /*!< I2C Master DMA channel                   */
+    AES0_IN_CHANn       = 13,  /*!< AES0-IN DMA channel                      */
+    AES0_OUT_CHANn      = 14,  /*!< AES0-OUT DMA channel                     */
+    FLASH_CHANn         = 15,  /*!< FLASH DMA channel                        */
+    SIP0_CHANn          = 16,  /*!< SIP-0 DMA channel                        */
+    SIP1_CHANn          = 17,  /*!< SIP-1 DMA channel                        */
+    SIP2_CHANn          = 18,  /*!< SIP-2 DMA channel                        */
+    SIP3_CHANn          = 19,  /*!< SIP-3 DMA channel                        */
+    SIP4_CHANn          = 20,  /*!< SIP-4 DMA channel                        */
+    SIP5_CHANn          = 21,  /*!< SIP-5 DMA channel                        */
+    SIP6_CHANn          = 22,  /*!< SIP-6 DMA channel                        */
+    SIP7_CHANn          = 23,  /*!< SIP-7 DMA channel                        */
+    ADC0_CHANn          = 24,  /*!< ADC0  DMA channel                        */
+#if defined(__ADUCM4x50__)    
+    UART1_TX_CHANn      = 25,  /*!< UART1 Transmit DMA channel               */
+    UART1_RX_CHANn      = 26,  /*!< UART1 Receive DMA channel                */
+#endif /* __ADUCM4x50__ */    
+    NUM_DMA_CHANNELSn   = 27   /*!< Total Number of DMA channels             */
+} DMA_CHANn_TypeDef;  /** typedef name for fixed DMA channel assignments */
+/*! \endcond */
+
+/*!
+ * \struct ADI_DCC_TypeDef
+ * DMA Channel Control MMR Access Template
+ */
+typedef struct
+{
+    __IO uint32_t DMASRCEND;      /*!< Source End Pointer                    */
+    __IO uint32_t DMADSTEND;      /*!< Destination End Pointer               */
+    __IO uint32_t DMACDC;         /*!< Channel Data Configuration            */
+         uint32_t RESERVED;       /*!< Address gap filler                    */
+} ADI_DCC_TypeDef;
+
+
+/*! \cond PRIVATE  */
+/* Bit Position for DMA Descriptor Control */
+#define DMA_BITP_CTL_DST_INC         (30u)
+#define DMA_BITP_CTL_SRC_INC         (26u)
+#define DMA_BITP_CTL_SRC_SIZE        (24u)
+#define DMA_BITP_CTL_R_POWER         (14u)
+#define DMA_BITP_CTL_N_MINUS_1        (4u)
+#define DMA_BITP_CTL_CYCLE_CTL        (0u)
+
+/* Bit Mask for DMA Descriptor Control */
+#define DMA_BITM_CTL_DST_INC         ((0x00000003u) << DMA_BITP_CTL_DST_INC)
+#define DMA_BITM_CTL_SRC_INC         ((0x00000003u) << DMA_BITP_CTL_SRC_INC)
+#define DMA_BITM_CTL_SRC_SIZE        ((0x00000003u) << DMA_BITP_CTL_SRC_SIZE)
+#define DMA_BITM_CTL_R_POWER         ((0x0000000Fu) << DMA_BITP_CTL_R_POWER)
+#define DMA_BITM_CTL_N_MINUS_1       ((0x000003FFu) << DMA_BITP_CTL_N_MINUS_1)
+#define DMA_BITM_CTL_CYCLE_CTL       ((0x00000007u) << DMA_BITP_CTL_CYCLE_CTL)
+
+/* Enum for the DMA Descriptor Cycle Control */
+#define DMA_ENUM_CTL_CYCLE_CTL_INVALID     (0u)
+#define DMA_ENUM_CTL_CYCLE_CTL_BASIC       (1u)
+#define DMA_ENUM_CTL_CYCLE_CTL_AUTO_REQ    (2u)
+#define DMA_ENUM_CTL_CYCLE_CTL_PING_PONG   (3u)
+#define DMA_ENUM_CTL_CYCLE_CTL_MSG_PRI     (4u)
+#define DMA_ENUM_CTL_CYCLE_CTL_MSG_ALT     (5u)
+#define DMA_ENUM_CTL_CYCLE_CTL_PSG_PRI     (6u)
+#define DMA_ENUM_CTL_CYCLE_CTL_PSG_ALT     (7u)
+
+
+#define DMA_BITM_INCR_TYPE_DECR            (0x10u)
+
+#define DMA_BITM_OCTL_SRC_DECR             (0x01u)
+#define DMA_BITM_OCTL_DST_DECR             (0x02u)
+
+#define DMA_BITM_OCTL_SRC_INCR             (0x04u)
+#define DMA_BITM_OCTL_DST_INCR             (0x08u)
+
+#define DMA_TRANSFER_LIMIT      (1024u) /*!< Maximum number of transfers handled by the DMA in one request */
+
+/* pointer to the primary CCD array */
+extern ADI_DCC_TypeDef* const pPrimaryCCD;
+/* pointer to the alternate CCD array */
+extern ADI_DCC_TypeDef* const pAlternateCCD;
+/*! \endcond  */
+/*==========  DMA API DECLARATIONS  ==========*/
+
+extern void adi_dma_Init(void);
+
+extern ADI_DMA_RESULT adi_dma_RegisterCallback (
+    DMA_CHANn_TypeDef   const eChannelID,
+    ADI_CALLBACK        const pfCallback,
+    void*               const pCBParam
+    );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* include guard */
+
+/*
+** EOF
+*/
+
+/**@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/flash/adi_flash.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/flash/adi_flash.h
new file mode 100755
index 00000000000..c72524e3e4d
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/flash/adi_flash.h
@@ -0,0 +1,185 @@
+/*!
+ *****************************************************************************
+ @file:    adi_flash.h
+ @brief:   Flash device driver definitions
+ @date:    $Date: 2016-07-05 00:49:46 -0400 (Tue, 05 Jul 2016) $
+ -----------------------------------------------------------------------------
+Copyright (c) 2012-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+/*! @addtogroup Flash_Driver Flash Driver
+ *  @{
+ */
+
+#ifndef ADI_FLASH_H
+#define ADI_FLASH_H
+
+ /*! \cond PRIVATE */
+#include <adi_processor.h>
+#include <adi_callback.h>
+#include <rtos_map/adi_rtos_map.h>  /* for ADI_SEM_SIZE */
+/*! \endcond */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * \enum ADI_FEE_RESULT
+ * Flash Controller return codes.
+ */
+ typedef enum {
+    ADI_FEE_SUCCESS = 0,                /*!< The function completed successfully.               */
+    ADI_FEE_ERR_ALIGNMENT,              /*!< The flash write source data pointer is misaligned. */
+    ADI_FEE_ERR_ALREADY_INITIALIZED,    /*!< The flash device driver is already initialized.    */
+    ADI_FEE_ERR_BAD_DEVICE_NUM,         /*!< Device number passed is invalid.                   */
+    ADI_FEE_ERR_BUFFER_ERR,             /*!< An error occurred while processing a write buffer. */
+    ADI_FEE_ERR_DEVICE_BUSY,            /*!< The device is busy.                                */
+    ADI_FEE_ERR_DMA_BUS_FAULT,          /*!< Runtime DMA bus fault detected.                    */
+    ADI_FEE_ERR_DMA_INVALID_DESCR,      /*!< Runtime DMA invalid descriptor detected.           */
+    ADI_FEE_ERR_DMA_REGISTER,           /*!< Error registering DMA error callback function.     */
+    ADI_FEE_ERR_DMA_UNKNOWN_ERROR,      /*!< Unknown runtime DMA error detected.                */
+    ADI_FEE_ERR_HW_ERROR_DETECTED,      /*!< An FEE hardware error occurred (pHwErrors param).  */
+    ADI_FEE_ERR_INSUFFICIENT_MEM,       /*!< The memory passed is undersized.                   */
+    ADI_FEE_ERR_INVALID_HANDLE,         /*!< Device Handle is invalid.                          */
+    ADI_FEE_ERR_INVALID_PARAM,          /*!< A function parameter is invalid.                   */
+    ADI_FEE_ERR_NO_DATA_TO_TRANSFER,    /*!< No transfer data detected.                         */
+    ADI_FEE_ERR_TRANSFER_IN_PROGRESS,   /*!< Operation already in progress.                     */
+    ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY, /*!< Unmatched read/write vs. submit/get API call.      */
+    ADI_FEE_ERR_SEMAPHORE_FAILED,       /*!< An semaphore operation failed.                     */
+ } ADI_FEE_RESULT;
+
+
+/*! A device handle used in all API functions to identify the flash device. */
+typedef struct __ADI_FEE_DEV_DATA_TYPE* ADI_FEE_HANDLE;
+
+
+/*! Applications use the "ADI_FEE_MEMORY_SIZE" macro to allocate
+    required flash driver memory.  This memory (and size) are passed
+    to the flash driver during the "adi_fee_Open()" driver initialization
+    call.  This memory is used to store internal flash driver state.
+*/
+#define ADI_FEE_MEMORY_SIZE            (44u + ADI_SEM_SIZE)
+
+
+/*!
+ * \enum ADI_FEE_CALLBACK_EVENT
+ * Enum for the callback events.
+ */
+typedef enum {
+     ADI_FEE_CALLBACK_EVENT_BUFFER_PROCESSED,    /*!< Buffer processed successfully event. */
+     ADI_FEE_CALLBACK_EVENT_DEVICE_ERROR,        /*!< Device error(s) detected during command. */
+} ADI_FEE_CALLBACK_EVENT;
+
+/*!
+ * \enum ADI_FEE_ECC_EVENT_TYPE
+ * Enum for the Error-Correction-Code event type.
+ */
+typedef enum {
+    ADI_FEE_ECC_EVENT_TYPE_ERROR,       /*!< ECC Error Event. */
+    ADI_FEE_ECC_EVENT_TYPE_CORRECT      /*!< ECC correction event. */
+} ADI_FEE_ECC_EVENT_TYPE;
+
+/*!
+ * \enum ADI_FEE_ECC_RESPONSE
+ * Error-Correction-Code configuration codes.
+ */
+typedef enum {
+    ADI_FEE_ECC_RESPONSE_NONE       = 0x0,      /*!< No Response. */
+    ADI_FEE_ECC_RESPONSE_BUS_ERROR  = 0x1,      /*!< Generate a Bus Error. */
+    ADI_FEE_ECC_RESPONSE_IRQ        = 0x2       /*!< Generate an IRQ. */
+} ADI_FEE_ECC_RESPONSE;
+
+
+/*!
+ * \struct ADI_FEE_TRANSACTION
+ * Flash write data transaction block.
+ */
+typedef struct {
+    uint32_t   *pWriteAddr;  /*!< Pointer to flash-space (destination) write location. */
+    uint32_t   *pWriteData;  /*!< Pointer to user-space (source) write Data.          */
+    uint32_t    nSize;       /*!< Write data size (in bytes).                          */
+    bool        bUseDma;     /*!< DMA flag controlling use of DMA or not.              */
+} ADI_FEE_TRANSACTION;
+
+
+/*================ E X T E R N A L S ==================*/
+/* Flash Controller API */
+
+ADI_FEE_RESULT adi_fee_Open              (uint32_t const nDeviceNum, void* const pMemory, uint32_t const nMemorySize, ADI_FEE_HANDLE* const phDevice);
+ADI_FEE_RESULT adi_fee_Close             (ADI_FEE_HANDLE const hDevice);
+ADI_FEE_RESULT adi_fee_RegisterCallback  (ADI_FEE_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void* const pCBParam);
+
+ADI_FEE_RESULT adi_fee_PageErase         (ADI_FEE_HANDLE const hDevice, uint32_t const nPageNumStart, uint32_t const nPageNumEnd, uint32_t* const pHwErrors);
+ADI_FEE_RESULT adi_fee_MassErase         (ADI_FEE_HANDLE const hDevice, uint32_t* const pHwErrors);
+
+ADI_FEE_RESULT adi_fee_Write             (ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION* const pTransaction, uint32_t* const pHwErrors);
+ADI_FEE_RESULT adi_fee_SubmitBuffer      (ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION* const pTransaction);
+
+ADI_FEE_RESULT adi_fee_IsBufferAvailable (ADI_FEE_HANDLE const hDevice, bool* const pbCompletionState);
+ADI_FEE_RESULT adi_fee_GetBuffer         (ADI_FEE_HANDLE const hDevice, uint32_t* const pHwErrors);
+
+ADI_FEE_RESULT adi_fee_GetPageNumber     (ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t* const pnPageNum);
+ADI_FEE_RESULT adi_fee_GetBlockNumber    (ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t* const pnBlockNum);
+
+ADI_FEE_RESULT adi_fee_VerifySignature   (ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, uint32_t const nEndPage, uint32_t* const pSigResult, uint32_t* const pHwErrors);
+ADI_FEE_RESULT adi_fee_WriteProtectBlock (ADI_FEE_HANDLE const hDevice, uint32_t const  nBlockNum);
+
+ADI_FEE_RESULT adi_fee_Sleep             (ADI_FEE_HANDLE const hDevice, bool const bSleep);
+ADI_FEE_RESULT adi_fee_Abort             (ADI_FEE_HANDLE const hDevice);
+ADI_FEE_RESULT adi_fee_GetAbortAddr      (ADI_FEE_HANDLE const hDevice, uint32_t* const pnAddress);
+
+ADI_FEE_RESULT adi_fee_ConfigECC         (ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, bool const bInfoECCEnable);
+ADI_FEE_RESULT adi_fee_EnableECC         (ADI_FEE_HANDLE const hDevice, bool const bEnable);
+ADI_FEE_RESULT adi_fee_ConfigECCEvents   (ADI_FEE_HANDLE const hDevice, ADI_FEE_ECC_EVENT_TYPE const eEvent, ADI_FEE_ECC_RESPONSE const eResponse);
+ADI_FEE_RESULT adi_fee_GetECCErrAddr     (ADI_FEE_HANDLE const hDevice, uint32_t* const pnAddress);
+ADI_FEE_RESULT adi_fee_GetECCCorrections (ADI_FEE_HANDLE const hDevice, uint32_t* const pnNumCorrections);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* include guard */
+
+/*
+** EOF
+*/
+
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/general/adi_data_transfer.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/general/adi_data_transfer.h
new file mode 100755
index 00000000000..89ab88d841e
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/general/adi_data_transfer.h
@@ -0,0 +1,127 @@
+/*! ****************************************************************************
+ * @file    adi_data_transfer.h
+ * @brief   General data transfer types for drivers
+ * @details General data transfer types for drivers
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef ADI_DATA_TRANSFER_H
+#define ADI_DATA_TRANSFER_H
+
+/*=============  I N C L U D E S   =============*/
+
+#include <stdint.h>                             /* defines types such as uint32_t*/
+#include <rtos_map/adi_rtos_map.h>              /* needed for SEM_VAR_DECLR declaration */
+
+/*! \cond PRIVATE */
+/** @addtogroup Data_Transfer Common Data Transfer Structures
+*  @{
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*==============  D E F I N E S  ===============*/
+
+#define ADI_DT_BUFNUM   (2u)                    /*!< Number of buffers available for data transfers in each communication channel */
+
+/*!
+ *******************************************************************************
+ * \struct ADI_DT_BUFF_INFO
+ *  Structure for managing buffers submitted to drivers.
+ ******************************************************************************/
+struct _ADI_DT_BUFF_INFO;
+
+/*!
+ *******************************************************************************
+ *  Structure for managing buffers submitted to drivers.
+ ******************************************************************************/
+typedef struct _ADI_DT_BUFF_INFO
+{
+    void *                      pStartAddress;  /*!< Address of buffer passed down a driver.            */
+    uint32_t                    nCount;         /*!< Size of buffer in bytes.                           */
+    uint32_t                    nIndex;         /*!< Position of first byte to be transmitted.          */
+    bool                        bInUse;         /*!< Buffer in use flag.                                */
+    bool                        bDMA;           /*!< Transaction is using the DMA flag.                 */
+    struct _ADI_DT_BUFF_INFO *  pNextBuffer;    /*!< Pointer to the next buffer in the list.            */
+} ADI_DT_BUFF_INFO;
+
+/*!
+ *******************************************************************************
+ *  Enumeration of different data transfer modes supported by drivers.
+ ******************************************************************************/
+typedef enum _ADI_DT_MODE
+{
+    ADI_DT_MODE_NONE,           /*!< Mode of data transfer is not selected. */ 
+    ADI_DT_MODE_BLOCKING,       /*!< Only calls to adi_xxx_Read or adi_xxx_Write are allowed for transferring data. */
+    ADI_DT_MODE_NONBLOCKING     /*!< Only calls to adi_xxx_SubmitBuffer are allowed for transferring data. */
+} ADI_DT_MODE;
+
+typedef void * ADI_DEVICE_HANDLE;               /*!< Generic device handle */
+
+/*!
+ *******************************************************************************
+ *  Structure for managing pool of buffers submitted to drivers.
+ ******************************************************************************/
+typedef struct
+{
+    ADI_DT_BUFF_INFO    BufInfo[ADI_DT_BUFNUM]; /*!< Ping Pong Buffers.                                             */
+    ADI_DT_BUFF_INFO *  pFreeBuffer;            /*!< Pointer to free buffer. (Next buffer to submit).               */
+    ADI_DT_BUFF_INFO *  pFillBuffer;            /*!< Pointer to the next buffer to be filled. (Needed for the case
+                                                     where many buffers are "submitted" before a "get" is called.)  */
+    ADI_DT_BUFF_INFO *  pActiveBuffer;          /*!< Pointer to active buffer. (Next buffer waiting for completion.)*/
+    ADI_DT_MODE         eDataTranferMode;       /*!< Data transfer mode (blocking or non-blockig).                  */
+
+    SEM_VAR_DECLR
+} ADI_DT_CHANNEL;
+
+
+/*=============  P U B L I C   F U N C T I O N S =============*/
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+/*! \endcond */
+
+#endif /* ADI_DATA_TRANSFER_H */
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/general/adi_drivers_general.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/general/adi_drivers_general.h
new file mode 100755
index 00000000000..e6f8571f1b4
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/general/adi_drivers_general.h
@@ -0,0 +1,98 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_drivers_general.h
+ * @brief:   Macros and types used in multiple drivers
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+#ifndef ADI_DRIVERS_GENERAL__H
+#define ADI_DRIVERS_GENERAL__H
+
+
+/* Macros related to alignment in the different toolchains supported */
+
+/* 
+ * These macros are designed to be used as follows:
+ * ADI_ALIGNED_PRAGMA(<required_alignment>)
+ * <variable_declaration> ADI_ALIGNED_ATTRIBUTE(<required_alignment>)
+ */
+
+#if defined ( __ICCARM__ )
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+*
+* Pm120 (rule 19.10): In the definition of a function-like macro each parameter
+*                     shall be enclosed in parenthesis. 
+*                     This is not possible in attributes and pragmas
+* Pm154 (rule 19.13): The # and ## preprocessor operators shall not be used.
+*                     We need to do this to abstract the macros for the 
+*                     different toolchains
+*/
+#pragma diag_suppress=Pm120,Pm154
+#endif
+
+#define PRAGMA(x) _Pragma(#x)
+#define ATTRIBUTE(x) __attribute__((x))
+
+#if defined (__GNUC__)
+  /* Gcc uses attributes */
+  #define ADI_ALIGNED_PRAGMA(num)
+  #define ADI_ALIGNED_ATTRIBUTE(num) ATTRIBUTE(aligned(num))
+  #define ADI_UNUSED_ATTRIBUTE ATTRIBUTE(unused)
+#elif defined ( __ICCARM__ )
+  /* IAR uses a pragma */
+  #define ADI_ALIGNED_ATTRIBUTE(num)
+  #define ADI_ALIGNED_PRAGMA(num) PRAGMA(data_alignment=num) 
+  #define ADI_UNUSED_ATTRIBUTE
+#elif defined (__ARMCC_VERSION)
+  /* Keil uses a decorator which is placed in the same position as pragmas */
+  #define ADI_ALIGNED_ATTRIBUTE(num)
+  #define ADI_ALIGNED_PRAGMA(num) __attribute__((aligned(num)))
+  #define ADI_UNUSED_ATTRIBUTE ATTRIBUTE(unused)
+#else
+#error "Toolchain not supported"
+#endif
+
+
+#if defined ( __ICCARM__ )
+#pragma diag_default=Pm120,Pm154
+#endif
+#endif /* ADI_DRIVERS_GENERAL__H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/gpio/adi_gpio.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/gpio/adi_gpio.h
new file mode 100755
index 00000000000..8a6042f88e0
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/gpio/adi_gpio.h
@@ -0,0 +1,178 @@
+/*
+ *****************************************************************************
+   @file:    adi_gpio.h
+   @brief:   GPIO definitions and API
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#ifndef ADI_GPIO_H
+#define ADI_GPIO_H
+
+#include <adi_processor.h>
+#include <adi_callback.h>
+
+#ifdef __ICCARM__
+/* IAR MISRA C 2004 error suppressions.
+ *
+ * Pm008 (rule 2.4): sections of code should not be 'commented out'.
+ *   Allow code example in doxygen comment.
+ * Pm011 (rule 6.3): The basic types of char, int, long, float cannot be used.
+ *   bool is used in the APIs as it is not affending the rule. Disabling this as IAR treats it as an error.
+ */
+#pragma diag_suppress=Pm008,Pm011
+#endif /* __ICCARM__ */
+
+/*! \addtogroup GPIO_Driver GPIO Driver
+ *  @{
+ */
+
+#ifdef __ICCARM__
+#pragma diag_default=Pm008
+#endif /* __ICCARM__ */
+
+/* C++ linkage */
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*! Amount of memory(in bytes) required by the GPIO device driver for its operation.
+ * This memory is completely owned by the driver till the end of the operation.
+ */
+#define ADI_GPIO_MEMORY_SIZE        (16u)
+
+/* typedefs for 16-bit Ports */
+typedef uint16_t ADI_GPIO_DATA;    /*!< pin data reg type */
+
+
+/*! GPIO API function return codes */
+typedef enum
+{
+    ADI_GPIO_SUCCESS = 0,                   /*!< No error detected. */
+    ADI_GPIO_FAILURE,                       /*!< The API call failed. */
+    ADI_GPIO_ALREADY_INITIALIZED,           /*!< GPIO device has already been initialized. */
+    ADI_GPIO_NOT_INITIALIZED,               /*!< GPIO device has not yet been initialized. */
+    ADI_GPIO_NULL_PARAMETER,                /*!< The given pointer is pointing to NULL. */
+    ADI_GPIO_INVALID_MEMORY_SIZE,           /*!< The given memory is not sufficient to operate the driver. */
+    ADI_GPIO_INVALID_PINS,                  /*!< Invalid pin combination. */
+    ADI_GPIO_INVALID_INTERRUPT,             /*!< Invalid interrupt number. */
+    ADI_GPIO_INVALID_TRIGGER,               /*!< Invalid trigger condition. */
+} ADI_GPIO_RESULT;
+
+
+/*! GPIO trigger condition enumerations */
+typedef enum {
+    ADI_GPIO_IRQ_RISING_EDGE    =(0x0),     /*!< Trigger an interrupt on a rising edge.    */
+    ADI_GPIO_IRQ_FALLING_EDGE   =(0x1),     /*!< Trigger an interrupt on a falling edge.   */
+    ADI_GPIO_IRQ_EITHER_EDGE    =(0x2),     /*!< Trigger an interrupt on either edge.      */
+    ADI_GPIO_IRQ_HIGH_LEVEL     =(0x3),     /*!< Trigger an interrupt on a high level.     */
+    ADI_GPIO_IRQ_LOW_LEVEL      =(0x4)      /*!< Trigger an interrupt on a low level.      */
+} ADI_GPIO_IRQ_TRIGGER_CONDITION;
+
+/*! GPIO IRQ enumeration */
+typedef enum {
+    ADI_GPIO_INTA_IRQ = SYS_GPIO_INTA_IRQn, /*!< GPIO Group Interrupt A.    */
+    ADI_GPIO_INTB_IRQ = SYS_GPIO_INTB_IRQn, /*!< GPIO Group Interrupt B.   */
+} ADI_GPIO_IRQ;
+
+
+/*! GPIO port enumerations */
+typedef enum {
+    ADI_GPIO_PORT0,      /*!< Port 0 */
+    ADI_GPIO_PORT1,      /*!< Port 1 */
+    ADI_GPIO_PORT2,      /*!< Port 2 */
+#if defined(__ADUCM4x50__)    
+    ADI_GPIO_PORT3,      /*!< Port 3 */
+#endif /* __ADUCM4x50__ */    
+    ADI_GPIO_NUM_PORTS   /*!< maximum number of ports */
+} ADI_GPIO_PORT;
+
+/* 16-bit port pin defs */
+#define ADI_GPIO_PIN_0      ((ADI_GPIO_DATA)(0x0001)) /*!< Pin 0 */
+#define ADI_GPIO_PIN_1      ((ADI_GPIO_DATA)(0x0002)) /*!< Pin 1 */
+#define ADI_GPIO_PIN_2      ((ADI_GPIO_DATA)(0x0004)) /*!< Pin 2 */
+#define ADI_GPIO_PIN_3      ((ADI_GPIO_DATA)(0x0008)) /*!< Pin 3 */
+#define ADI_GPIO_PIN_4      ((ADI_GPIO_DATA)(0x0010)) /*!< Pin 4 */
+#define ADI_GPIO_PIN_5      ((ADI_GPIO_DATA)(0x0020)) /*!< Pin 5 */
+#define ADI_GPIO_PIN_6      ((ADI_GPIO_DATA)(0x0040)) /*!< Pin 6 */
+#define ADI_GPIO_PIN_7      ((ADI_GPIO_DATA)(0x0080)) /*!< Pin 7 */
+#define ADI_GPIO_PIN_8      ((ADI_GPIO_DATA)(0x0100)) /*!< Pin 8 */
+#define ADI_GPIO_PIN_9      ((ADI_GPIO_DATA)(0x0200)) /*!< Pin 9 */
+#define ADI_GPIO_PIN_10     ((ADI_GPIO_DATA)(0x0400)) /*!< Pin 10 */
+#define ADI_GPIO_PIN_11     ((ADI_GPIO_DATA)(0x0800)) /*!< Pin 11 */
+#define ADI_GPIO_PIN_12     ((ADI_GPIO_DATA)(0x1000)) /*!< Pin 12 */
+#define ADI_GPIO_PIN_13     ((ADI_GPIO_DATA)(0x2000)) /*!< Pin 13 */
+#define ADI_GPIO_PIN_14     ((ADI_GPIO_DATA)(0x4000)) /*!< Pin 14 */
+#define ADI_GPIO_PIN_15     ((ADI_GPIO_DATA)(0x8000)) /*!< Pin 15 */
+
+/* GPIO port pins availability mask */
+#define ADI_GPIO_PORT0_PIN_AVL    (0xFFFFu)           /*!< Port 0 pin mask (16 pins)*/
+#define ADI_GPIO_PORT1_PIN_AVL    (0xFFFFu)           /*!< Port 1 pin mask (16 pins)*/
+#define ADI_GPIO_PORT2_PIN_AVL    (0xFFFFu)           /*!< Port 2 pin mask (16 pins)*/
+
+#if defined(__ADUCM4x50__)
+#define ADI_GPIO_PORT3_PIN_AVL    (0x000Fu)           /*!< Port 2 pin mask (4 pins) */
+#endif /* __ADUCM4x50__ */
+
+/* GPIO API functions */
+ADI_GPIO_RESULT  adi_gpio_Init                      (void* const pMemory, uint32_t const MemorySize);
+ADI_GPIO_RESULT  adi_gpio_UnInit                    (void);
+ADI_GPIO_RESULT  adi_gpio_RegisterCallback          (const ADI_GPIO_IRQ eIrq, ADI_CALLBACK const pfCallback, void *const pCBParam );
+ADI_GPIO_RESULT  adi_gpio_SetGroupInterruptPins     (const ADI_GPIO_PORT Port, const ADI_GPIO_IRQ eIrq, const ADI_GPIO_DATA Pins);
+ADI_GPIO_RESULT  adi_gpio_SetGroupInterruptPolarity (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins);
+ADI_GPIO_RESULT  adi_gpio_OutputEnable              (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag);
+ADI_GPIO_RESULT  adi_gpio_InputEnable               (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag);
+ADI_GPIO_RESULT  adi_gpio_PullUpEnable              (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag);
+ADI_GPIO_RESULT  adi_gpio_SetHigh                   (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins);
+ADI_GPIO_RESULT  adi_gpio_SetLow                    (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins);
+ADI_GPIO_RESULT  adi_gpio_Toggle                    (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins);
+ADI_GPIO_RESULT  adi_gpio_SetData                   (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins);
+ADI_GPIO_RESULT  adi_gpio_GetData                   (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, uint16_t* const pValue);
+
+#if defined (__ICCARM__)
+#pragma diag_default=Pm011
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+
+#endif /* ADI_GPIO_V1_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/i2c/adi_i2c.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/i2c/adi_i2c.h
new file mode 100755
index 00000000000..edd398f3f9b
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/i2c/adi_i2c.h
@@ -0,0 +1,243 @@
+/*!
+ *****************************************************************************
+ @file:    adi_i2c.h
+ @brief:   I2C device driver definitions
+ @details  This is the primary header file for the I2C driver, which contains the
+           API declarations, data and constant definitions used in the APIs.
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+
+#ifndef ADI_I2C_H
+#define ADI_I2C_H
+
+ /*! \cond PRIVATE */
+#include <adi_processor.h>
+#include <rtos_map/adi_rtos_map.h>  /* for ADI_SEM_SIZE */
+/*! \endcond */
+
+
+/** @addtogroup I2C_Driver I2C Driver
+ *  @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (__ICCARM__)
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm011 (rule 6.3): Types which specify sign and size should be used
+*   We use bool which is accepted by MISRA but the toolchain does not accept it
+*
+*/
+#pragma diag_suppress=Pm011
+
+#endif
+
+/*!
+ *****************************************************************************
+ * \enum ADI_I2C_RESULT
+ *
+ * I2C Device Error Codes.  #ADI_I2C_SUCCESS is always zero
+ * The return value of all I2C APIs returning #ADI_I2C_RESULT
+ * should always be tested at the application level for success or failure.
+ * Specific I2C bus error conditions are returned as elements of
+ * #ADI_I2C_RESULT.
+ *
+ *****************************************************************************/
+typedef enum
+{
+    ADI_I2C_SUCCESS = 0,                         /*!< The API call succeeded.                                  */
+    ADI_I2C_BAD_BITRATE,                         /*!< The bit rate is invalid.                                 */
+    ADI_I2C_BAD_DEVICE_HANDLE,                   /*!< The device handle is invalid.                            */
+    ADI_I2C_BAD_DEVICE_NUMBER,                   /*!< The device number is invalid.                            */
+    ADI_I2C_BAD_SYS_CLOCK,                       /*!< Unable to obtain system clock rate.                      */
+    ADI_I2C_DEVICE_IN_USE,                       /*!< The device is in use.                                    */
+    ADI_I2C_DEVICE_NOT_OPEN,                     /*!< The device is not open.                                  */
+    ADI_I2C_FAILURE,                             /*!< Generic API failure code.                                */
+    ADI_I2C_HW_ERROR_DETECTED,                   /*!< An I2C hardware error occurred.  See #ADI_I2C_HW_ERRORS. */
+    ADI_I2C_INSUFFICIENT_MEMORY,                 /*!< The application supplied memory size is insufficient.    */
+    ADI_I2C_INVALID_PARAMETER,                   /*!< An invalid parameter is passed to the function.          */
+    ADI_I2C_INVALID_SLAVE_ADDRESS,               /*!< The application supplied slave address is too wide.      */
+    ADI_I2C_INVALID_SUBMIT_API,                  /*!< Unmatched read/write vs. submit/get API call.            */
+    ADI_I2C_SEMAPHORE_FAILED                     /*!< Semaphore operation failed.                              */
+
+} ADI_I2C_RESULT;
+
+
+/*!
+ *****************************************************************************
+ * \enum ADI_I2C_HW_ERRORS
+ *
+ * I2C Device Hardware Error Codes.  Contains one or more hardware (I2C protocol)
+ * errors.  Use this enum to decode hardware errors when the main #ADI_I2C_RESULT
+ * return result value is #ADI_I2C_HW_ERROR_DETECTED.
+ *
+ *****************************************************************************/
+typedef enum
+{
+    ADI_I2C_HW_ERROR_NONE             = 0,         /*!< No hardware error.                                       */
+    ADI_I2C_HW_ERROR_NACK_ADDR        = 0x0001,    /*!< A no-acknowledgement occurred for the address.           */
+    ADI_I2C_HW_ERROR_NACK_DATA        = 0x0002,    /*!< A no-acknowledgement occurred for the data.              */
+    ADI_I2C_HW_ERROR_ARBITRATION_LOST = 0x0004,    /*!< I2C bus arbitration was Lost.                            */
+    ADI_I2C_HW_ERROR_UNEXPECTED_ERROR = 0x0008,    /*!< An unexpected error occurred.                            */
+
+} ADI_I2C_HW_ERRORS;
+
+
+/*! A device handle used in all API functions to identify the I2C device. */
+typedef struct __ADI_I2C_DEV_DATA_TYPE* ADI_I2C_HANDLE;
+
+/*! Use macro "ADI_I2C_MEMORY_SIZE" to know how much memory to
+   provide the i2c driver during the "adi_i2c_Open()" driver
+   initialization call.  This memory is used to store internal
+   driver state data.  Use map file to verify.
+*/
+#define ADI_I2C_MEMORY_SIZE (44u + ADI_SEM_SIZE)
+
+
+/*!
+  * \struct ADI_I2C_TRANSACTION
+  *****************************************************************************
+  * I2C Device Command/Data Transaction Structure.  This is the called-provided
+  * data structure used by the blocking #adi_i2c_ReadWrite() and non-blocking
+  * #adi_i2c_SubmitBuffer() calls to describe the caller's transaction parameters,
+  * consisting of prologue data and size (the addressing phase), transmit/receive
+  * data pointer and size (the data phase), and various transaction control parameters.
+  *
+  * Each transaction may optionally be prefaced with a prologue block, which may
+  * describe a read/write memory/register address, a slave-specific command, or
+  * some other slave-specific protocol that may precede the actual read/write
+  * data.  Set the prologue size to zero if no prologue is desired.
+  *
+  * Each call to #adi_i2c_ReadWrite or #adi_i2c_SubmitBuffer() must populate the
+  * following fields of the ADI_I2C_TRANSACTION block:
+  *
+  * @par pPrologue
+  * Byte pointer to an application-supplied prologue byte array. If the value is
+  * zero, prologue data is ignored.
+  *
+  * @par nPrologueSize
+  * The number of prologue bytes to be transmitted ahead of the data phase. If the
+  * value is zero, prologue data is ignored.
+  *
+  * @par pData
+  * Byte pointer to the application-supplied data byte array.  This buffer is
+  * either the source or destination address of the data being transmitted or
+  * received, respectively.
+  *
+  * @par nDataSize
+  * The number of data bytes to be transmitted or received during the data phase.
+  * If the value is zero, the data phase is ignored.
+  *
+  * @par bReadNotWrite
+  * Direction control for data phase.  If "true", data phase is a read (from
+  * the slave), if "false", data phase is a write (to the slave).  Pertains only
+  * to the data phase.  Any prologue data (addressing/command phase) is always
+  * transmitted (written to the slave) prior to the data phase.
+  *
+  * @par bRepeatStart
+  * Controls suppression of a Stop Condition between the addressing phase and the
+  * data phase of an I2C transaction.  After the prologue (if present), a
+  * unidirectional data stream (I2C is a half-duplex protocol) is either
+  * transmitted or received (depending on the transfer direction).  Frequently, a
+  * Repeat-Start Condition (in reality, just the absence of a Stop Condition
+  * following the prologue/addressing phase) is required between the addressing
+  * phase (prologue) and the data phase of a transaction to meet slave device
+  * protocol requirements.  The Repeat-Start requirement can be driven by the
+  * slave device communications protocol, or simply to just prevent any other
+  * I2C master from rearbitrating the bus between the prologue (addressing) and
+  * data phases of a so-called "COMBINED FORMAT" (write-followed-by-read).
+  * When bRepeatStart is set "true", the usual Stop Condition between the addressing
+  * phase and the data phase is suppressed and the I2C bus controller issues a
+  * second Start Condition (Repeat-Start) for the data phase.  Without
+  * Repeat-Start (bRepeatStart "false"), the addressing phase ends with a normal
+  * Stop Condition ahead of the data phase.  Repeat-Start conditions are used
+  * when "turning the bus around" as in writing a read address (for example),
+  * immediately followed by a data stream from that read address... without
+  * releasing bus arbitration.
+  *
+  *****************************************************************************/
+typedef struct {
+    uint8_t    *pPrologue;      /*!< Prologue pointer.                      */
+    uint16_t    nPrologueSize;  /*!< Prologue byte count.                   */
+    uint8_t    *pData;          /*!< Data pointer.                          */
+    uint16_t    nDataSize;      /*!< Data byte count.                       */
+    bool        bReadNotWrite;  /*!< Read/write flag.                       */
+    bool        bRepeatStart;   /*!< Repeat start flag.                     */
+} ADI_I2C_TRANSACTION;
+
+
+/*! Maximum supported bitrate is "FAST" mode (400 kHz). */
+#define ADI_I2C_MAX_RATE (400000u)
+
+/***************************************************************
+ * Eliminable user API that may be optimized out by the linker *
+ ***************************************************************/
+ADI_I2C_RESULT  adi_i2c_Open               (uint32_t const DeviceNum, void* const pMemory, uint32_t const MemorySize, ADI_I2C_HANDLE* const phDevice);
+ADI_I2C_RESULT  adi_i2c_Close              (ADI_I2C_HANDLE const hDevice);
+
+/* blocking calls... */
+ADI_I2C_RESULT  adi_i2c_ReadWrite          (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction, uint32_t* const pHwErrors);
+
+/* non-blocking calls... */
+ADI_I2C_RESULT  adi_i2c_SubmitBuffer       (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction);
+ADI_I2C_RESULT  adi_i2c_IsBufferAvailable  (ADI_I2C_HANDLE const hDevice, bool* const pbCompletionState);
+ADI_I2C_RESULT  adi_i2c_GetBuffer          (ADI_I2C_HANDLE const hDevice, uint32_t* const pHwErrors);
+
+/* other (blocking) calls... */
+ADI_I2C_RESULT  adi_i2c_Reset              (ADI_I2C_HANDLE const hDevice);
+ADI_I2C_RESULT  adi_i2c_SetBitRate         (ADI_I2C_HANDLE const hDevice, uint32_t const requestedBitRate32);
+ADI_I2C_RESULT  adi_i2c_SetSlaveAddress    (ADI_I2C_HANDLE const hDevice, uint16_t const SlaveAddress);
+ADI_I2C_RESULT  adi_i2c_IssueGeneralCall   (ADI_I2C_HANDLE const hDevice, uint8_t* const pData, uint8_t const nDataSize, uint32_t* const pHwErrors);
+
+
+#if defined (__ICCARM__)
+#pragma diag_default=Pm011
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+
+#endif /* ADI_I2C_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/pwr/adi_pwr.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/pwr/adi_pwr.h
new file mode 100755
index 00000000000..3175b7000cd
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/pwr/adi_pwr.h
@@ -0,0 +1,723 @@
+/*
+ *****************************************************************************
+ * @file:    adi_pwr.h
+ * @brief:   System clock and power management driver.
+ *-----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+
+/*! \addtogroup Power_Driver Power Driver
+ *  @{
+ */
+
+#ifndef ADI_PWR_H
+#define ADI_PWR_H
+
+#include <adi_callback.h>
+#include <adi_processor.h>
+#include <stdbool.h>
+
+#ifdef __ICCARM__
+/* IAR MISRA C 2004 error suppressions.
+ *
+ * Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters.
+ *   IAR compiler supports longer identifiers.
+ * Pm011 (rule 6.3): The basic types of char, int, long, float cannot be used.
+ *   bool is used in the APIs as it is not affending the rule. Disabling this as IAR treats it as an error. 
+ */
+#pragma diag_suppress=Pm009,Pm011
+#endif /* __ICCARM__ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+   
+/*! Enumeration of clock sources for various peripherals. */
+typedef enum {
+    /*! Source for all peripherals SPI, SPORT, SIP, CRC, AES, SIP interface, I2C, UART, optionally for timers. */  
+    ADI_CLOCK_PCLK,    
+    /*! Source for Core,Bus etc. */    
+    ADI_CLOCK_HCLK,
+    /*! Source for the ADC. */
+    ADI_CLOCK_ACLK
+    
+} ADI_CLOCK_ID;
+
+/*! Enumeration of input clock sources */
+typedef enum {
+   /*! Clock ID for 16 MHz or 26 MHz external crystal oscillator called  HFXTAL. */    
+    ADI_CLOCK_SOURCE_HFXTAL,
+   /*! Clock ID 32 kHz external crystal oscillator called  LFXTAL. */
+    ADI_CLOCK_SOURCE_LFXTAL,
+   /*! Clock ID for 26 MHz internal oscillator called  HFOSC. */
+    ADI_CLOCK_SOURCE_HFOSC,
+   /*! Clock ID 32 kHz a 32 kHz internal oscillator called  LFXTAL. */
+    ADI_CLOCK_SOURCE_LFOSC,
+   /*! Clock ID for output clock for System PLL. */
+    ADI_CLOCK_SOURCE_SPLL,
+   /*! Clock ID for external clock from GPIO. */               
+    ADI_CLOCK_SOURCE_GPIO
+} ADI_CLOCK_SOURCE_ID;
+
+
+/*! 
+ * Enumeration of clock sources for each clock multiplexer.
+ * The processor has the following clock multiplexers.
+ * - SPLL Mux (System PLL).
+ * - Reference clock Mux.
+ * - Root Clock Mux.
+ */
+typedef enum  {
+
+    /*! Input clock for  system PLL mux is HFOSC. */
+    ADI_CLOCK_MUX_SPLL_HFOSC, 
+    /*! Input clock for  system PLL mux is HFXTAL. */
+    ADI_CLOCK_MUX_SPLL_HFXTAL,
+
+#if defined(__ADUCM4x50__)
+    /*! Input clock for  system PLL mux is provided through GPIO. */
+    ADI_CLOCK_MUX_SPLL_GPIO,
+#endif
+    
+    /*! Input clock for  low frequency clock mux is LFOSC. */
+    ADI_CLOCK_MUX_LFCLK_LFOSC,
+    /*! Input clock for  low frequency clock mux is LFXTAL. */    
+    ADI_CLOCK_MUX_LFCLK_LFXTAL,
+
+    /*! Input clock to the multiplexer which provides reference clock for Flash 
+      and HPBUCK clock is HFOSC. */
+    ADI_CLOCK_MUX_REF_HFOSC_CLK,  
+    /*! Reserved. */
+    ADI_CLOCK_MUX_REF_RESERVED,    
+    /*! Input clock to the multiplexer which provides reference clock for Flash 
+      and HPBUCK clock is 26 MHz HFXTAL. */
+    ADI_CLOCK_MUX_REF_HFXTAL_26MHZ_CLK,
+    /*! Input clock to the multiplexer which provides reference clock for Flash 
+      and HPBUCK clock is 16 MHz HFXTAL. */
+    ADI_CLOCK_MUX_REF_HFXTAL_16MHZ_CLK,
+    
+    /*! Input clock to root multiplexer is HFOSC. */                                            
+    ADI_CLOCK_MUX_ROOT_HFOSC,
+    /*! Input clock to root multiplexer is HFXTAL. */                                                
+    ADI_CLOCK_MUX_ROOT_HFXTAL,
+    /*! Input clock to root multiplexer is SPLL. */                                                
+    ADI_CLOCK_MUX_ROOT_SPLL,
+    /*! Input clock to root multiplexer is from GPIO. */                                                
+    ADI_CLOCK_MUX_ROOT_GPIO
+    
+} ADI_CLOCK_MUX_ID;
+
+
+/*! 
+ * Enumeration of clock source status. 
+ */
+typedef enum {
+    /*! Specified clock source is disabled. */
+    ADI_CLOCK_SOURCE_DISABLED = 0,
+    /*! Specified clock source is not stable. */    
+    ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE,
+    /*! Specified clock source is enabled and  stable. */        
+    ADI_CLOCK_SOURCE_ENABLED_STABLE,
+    /*! Invalid clock ID. */
+    ADI_CLOCK_SOURCE_ID_NOT_VALID
+    
+} ADI_CLOCK_SOURCE_STATUS;
+
+/*! Clock output options through GPIO pin.
+    The GPIO clock output pin can be driven through one of these clocks.
+*/
+typedef enum
+{
+    /*! Root Clock (ROOT_CLK). */
+    ADI_CLOCK_OUTPUT_ROOT_CLK,
+    
+    /*! Low Frequency Clock (LF_CLK). */
+    ADI_CLOCK_OUTPUT_LF_CLK,
+    
+    /*! ADC Clock (ACLK). */
+    ADI_CLOCK_OUTPUT_ACLK,
+    
+    /*! HCLK_BUS. */
+    ADI_CLOCK_OUTPUT_HCLK_BUS,
+    
+    /*! HCLK_CORE. */
+    ADI_CLOCK_OUTPUT_HCLK_CORE,
+    
+    /*! Peripheral Clock (PCLK). */
+    ADI_CLOCK_OUTPUT_PCLK,
+    
+    /*! Reference Clock for Flash controller timer (RCLK). */
+    ADI_CLOCK_OUTPUT_RCLK,
+    
+    /*! Mux of HFOSC, HFXTAL clock (RHP_CLK). */
+    ADI_CLOCK_OUTPUT_RHP_CLK,
+    
+    /*! GP Timer 0 clock (GPT0_CLK). */
+    ADI_CLOCK_OUTPUT_GPT0_CLK,
+    
+    /*! GP Timer 1 clock (GPT1_CLK). */
+    ADI_CLOCK_OUTPUT_GPT1_CLK,
+    
+    /*! Peripherals operating at HCLK (HCLK_P). */
+    ADI_CLOCK_OUTPUT_HCLK_PERIPHERAL,
+    
+    /*! PLL Clock out. */
+    ADI_CLOCK_OUTPUT_PLL_OUTPUT,
+    
+    /*! RTC0 Clock. */
+    ADI_CLOCK_OUTPUT_RTC0_CLK,
+    
+    /*! HP Buck Clock (HPBUCK_CLK). */
+    ADI_CLOCK_OUTPUT_HPBUCK_CLK,
+    
+    /*! HP Buck Non overlap clock. */
+    ADI_CLOCK_OUTPUT_HPBUCK_NO_OVERLAP_CLK,
+    
+    /*! RTC1 generated clock. */
+    ADI_CLOCK_OUTPUT_RTC1_CLK
+    
+} ADI_CLOCK_OUTPUT_ID;
+ 
+
+/*! Enumeration of clock gates using which the clocks can be gated. */
+typedef enum {
+    /*! Clock Gate for the GP Timer-0. */    
+    ADI_CLOCK_GATE_GPT0_CLK     = 1 << BITP_CLKG_CLK_CTL5_GPTCLK0OFF,
+    /*! Clock Gate for the GP Timer-1. */        
+    ADI_CLOCK_GATE_GPT1_CLK     = 1 << BITP_CLKG_CLK_CTL5_GPTCLK1OFF,
+    /*! Clock Gate for the GP Timer-2. */        
+    ADI_CLOCK_GATE_GPT2_CLK     = 1 << BITP_CLKG_CLK_CTL5_GPTCLK2OFF,
+    /*! Clock Gate for the I2C. */        
+    ADI_CLOCK_GATE_I2C_CLK      = 1 << BITP_CLKG_CLK_CTL5_UCLKI2COFF,
+    /*! Clock Gate for the GPIO. */        
+    ADI_CLOCK_GATE_GPIO_CLK     = 1 << BITP_CLKG_CLK_CTL5_GPIOCLKOFF,    
+    /*! Clock Gate for the PCLK. */                
+    ADI_CLOCK_GATE_PCLK         = 1 << BITP_CLKG_CLK_CTL5_PERCLKOFF, 
+
+#if defined(__ADUCM4x50__)
+    /*! Clock Gate for the RGB Timer. */                
+    ADI_CLOCK_GATE_TMR_RGB_CLK  = 1 << BITP_CLKG_CLK_CTL5_TMRRGBCLKOFF 
+#endif
+
+} ADI_CLOCK_GATE;
+
+#if defined(__ADUCM4x50__)
+/*!
+ *  Enumeration of HF oscillator clock divide factor.
+ */
+typedef enum 
+{
+    /*! Divide by 1. */
+    ADI_PWR_HFOSC_DIV_BY_1,
+    /*! Divide by 2. */
+    ADI_PWR_HFOSC_DIV_BY_2,
+    /*! Divide by 4. */
+    ADI_PWR_HFOSC_DIV_BY_4,
+    /*! Divide by 8. */
+    ADI_PWR_HFOSC_DIV_BY_8,
+    /*! Divide by 16. */
+    ADI_PWR_HFOSC_DIV_BY_16,
+    /*! Divide by 32. */
+    ADI_PWR_HFOSC_DIV_BY_32
+
+} ADI_PWR_HFOSC_DIV;
+#endif /* __ADUCM4x50__ */
+
+ /*!
+ *****************************************************************************
+ * Power driver API return codes
+ *****************************************************************************/
+typedef enum
+{
+    /*! No error detected.                                    */  
+    ADI_PWR_SUCCESS = 0,              
+    /*! Generic unknown error occurred.                       */    
+    ADI_PWR_FAILURE,                  
+    /*! If the given pointer is pointing to NULL.             */    
+    ADI_PWR_NULL_POINTER,                  
+    /*! Requested divide value is out of range.               */    
+    ADI_PWR_INVALID_CLOCK_DIVIDER,    
+    /*! Invalid ADI_CLOCK_ID specified.                       */    
+    ADI_PWR_INVALID_CLOCK_ID,         
+    /*! PDIV:HDIV ratio must be integral.                     */    
+    ADI_PWR_INVALID_CLOCK_RATIO,      
+    /*! Invalid low-power mode requested.                     */    
+    ADI_PWR_INVALID_POWER_MODE,       
+    /*! Invalid clock speed.                                  */    
+    ADI_PWR_INVALID_CLOCK_SPEED,      
+    /*! Specified operation is not allowed.                   */    
+    ADI_PWR_OPERATION_NOT_ALLOWED,
+    /*! Parameter is out of range.                            */    
+    ADI_PWR_INVALID_PARAM,   
+    /*! System not initialized, call the API SystemInit.      */
+    ADI_PWR_SYSTEM_NOT_INITIALIZED
+    
+} ADI_PWR_RESULT;
+
+/*!
+ *   Enumeration of the power modes supported by the processor.
+ */
+typedef enum
+{
+    /*! Core Sleep power-down mode. */    
+    ADI_PWR_MODE_FLEXI          = 0 << BITP_PMG_PWRMOD_MODE,      
+    /*! Fully Active. (piggy-back on bitmode value "1", normally reserved) */    
+    ADI_PWR_MODE_ACTIVE         = 1 << BITP_PMG_PWRMOD_MODE,  
+    /*! Full Hibernate power-down mode. */    
+    ADI_PWR_MODE_HIBERNATE      = 2 << BITP_PMG_PWRMOD_MODE,        
+    /*! System Sleep power-down mode. */    
+    ADI_PWR_MODE_SHUTDOWN       = 3 << BITP_PMG_PWRMOD_MODE
+    
+} ADI_PWR_POWER_MODE;
+
+
+/*!
+ *   Enumeration of power management interrupts.
+ */
+typedef enum
+{
+    /*! Interrupt when battery voltage drops below 1.8V.*/    
+    ADI_PWR_LOW_BATTERY_VOLTAGE_IEN     = 1 << BITP_PMG_IEN_VBAT,       
+    /*! Interrupt when VREG under-voltage: below 1V. */    
+    ADI_PWR_UNDER_VOLATAGE_IEN          = 1 << BITP_PMG_IEN_VREGUNDR,   
+    /*! Interrupt when VREG over-voltage: over- 1.32V. */    
+    ADI_PWR_OVER_VOLATAGE_IEN           = 1 << BITP_PMG_IEN_VREGOVR,    
+    /*! Interrupt when battery voltage falls to the specified range.Please see #adi_pwr_SetVoltageRange.*/     
+    ADI_PWR_BATTERY_VOLTAGE_RANGE_IEN   = 1 << BITP_PMG_IEN_IENBAT
+    
+} ADI_PWR_PMG_IRQ;
+
+
+/*!
+ *   Enumeration of system clock module interrupts.
+ */
+typedef enum
+{
+#if defined(__ADUCM4x50__)
+    /*! Interrupt for root clock monitor and Clock Fail. */
+    ADI_PWR_ROOT_CLOCK_MON_IEN      = 1 << BITP_CLKG_OSC_CTL_ROOT_MON_EN,
+    /*! Interrupt for LFXTAL clock monitor and Clock Fail. */
+    ADI_PWR_LFXTAL_CLOCK_MON_IEN    = 1 << BITP_CLKG_OSC_CTL_LFX_MON_EN,
+    /*! Interrupt when LFXTAL clock becomes stable/unstable. */
+    ADI_PWR_LFXTAL_STATUS_IEN       = 1 << BITP_CLKG_CLK_CTL0_LFXTALIE,
+    /*! Interrupt when HFXTAL clock becomes stable/unstable. */     
+    ADI_PWR_HFXTAL_STATUS_IEN       = 1 << BITP_CLKG_CLK_CTL0_HFXTALIE,
+    /*! Interrupt when PLL-LOCK/PLL-UNLOCK.  */
+    ADI_PWR_PLL_STATUS_IEN          = 1 << BITP_CLKG_CLK_CTL3_SPLLIE
+#elif defined(__ADUCM302x__)
+    /*! Interrupt for LFXTAL clock monitor and Clock Fail. */
+    ADI_PWR_LFXTAL_CLOCK_MON_IEN    = 1 << BITP_CLKG_OSC_CTL_LFXTAL_MON_EN,   
+    /*! Interrupt when LFXTAL clock becomes stable/unstable. */
+    ADI_PWR_LFXTAL_STATUS_IEN       = 1 << BITP_CLKG_CLK_CTL0_LFXTALIE,
+    /*! Interrupt when HFXTAL clock becomes stable/unstable. */     
+    ADI_PWR_HFXTAL_STATUS_IEN       = 1 << BITP_CLKG_CLK_CTL0_HFXTALIE,
+    /*! Interrupt when PLL-LOCK/PLL-UNLOCK.  */
+    ADI_PWR_PLL_STATUS_IEN          = 1 << BITP_CLKG_CLK_CTL3_SPLLIE
+#endif
+     
+} ADI_PWR_CLOCK_IRQ;
+
+/**
+ * Enumeration of the power driver events notified through the callback.
+ */
+typedef enum 
+{
+    /*! Event for indicating Over voltage VREG  > 1.32v. */    
+    ADI_PWR_EVENT_VREG_OVER_VOLTAGE,            
+    /*! Event for indicating  under voltage VREG < 1V. */    
+    ADI_PWR_EVENT_VREG_UNDER_VOLTAGE,           
+    
+    /*! Event for indicating battery voltage below  1.8V. */
+    ADI_PWR_EVENT_BATTERY_VOLTAGE_LOW,
+
+#if defined(__ADUCM4x50__)
+    /*! Event for indicating battery voltage in specified range-1.VBAT range1 (> 2.75v). */ 
+    ADI_PWR_EVENT_BATTERY_VOLTAGE_RANGE_1,
+    /*! Event for indicating battery voltage in specified range-2.VBAT range2 (2.75v - 2.3v).   */    
+    ADI_PWR_EVENT_BATTERY_VOLTAGE_RANGE_2,
+    /*! Event for indicating battery voltage in specified range-3.VBAT range3 (2.3v - 1.6v).   */    
+    ADI_PWR_EVENT_BATTERY_VOLTAGE_RANGE_3,
+
+    /*! Event to indicate that LFXTAL failed and hardware automatically switched to LFOSC. */
+    ADI_PWR_EVENT_OSC_LFXTAL_AUTO_SWITCH,
+    /*! Event to indicate the LFXTAL clock is not stable. */
+    ADI_PWR_EVENT_OSC_LFXTAL_MON_FAIL,
+    /*! Event to indicate the Root clock is not stable. */
+    ADI_PWR_EVENT_OSC_ROOT_CLOCK_MON_FAIL,
+    /*! Event to indicate the Root clock failed and hardware automatically switched to HFOSC. */
+    ADI_PWR_EVENT_OSC_ROOT_CLOCK_FAIL_AUTO_SWITCH,
+#endif
+ 
+    /*! Event to indicate HF crystal stable. */    
+    ADI_PWR_EVENT_OSC_HFXTAL_CLOCK_OK,
+    /*! Event to indicate HF crystal is not stable. */    
+    ADI_PWR_EVENT_OSC_HFXTAL_CLOCK_NO_OK,
+    /*! Event to indicate LF crystal is  stable. */    
+    ADI_PWR_EVENT_OSC_LFXTAL_CLOCK_OK,
+    /*! Event to indicate LF crystal is not stable. */    
+    ADI_PWR_EVENT_OSC_LFXTAL_CLOCK_NO_OK,
+    /*! Event for indicating PLL is locked. */    
+
+    ADI_PWR_EVENT_PLLC_LOCK,
+    /*! Event for indicating PLL is unlocked.  */    
+    ADI_PWR_EVENT_PLLC_UNLOCK
+    
+} ADI_PWR_EVENT;
+
+
+/*!
+ *   Enumeration of processor wake up status. 
+*/
+typedef enum
+{
+    /*! Interrupt from External Interrupt 0. */    
+    ADI_PWR_INT_EXT0,    
+    /*! Interrupt from External Interrupt 1. */    
+    ADI_PWR_INT_EXT1,    
+    /*! Interrupt from External Interrupt 2. */        
+    ADI_PWR_INT_EXT2,   
+    /*! Interrupt from RTC. */
+    ADI_PWR_INT_RTC     
+      
+} ADI_PWR_WAKEUP_STATUS;
+
+/*!
+ *   Enumeration of the battery voltage ranges for voltage monitoring interrupt generation.
+*/
+typedef enum
+{
+    /*! Voltage range is in safe region.  */
+    ADI_PWR_BAT_VOLTAGE_RANGE_SAFE,     
+    /*! Battery voltage is in the range of 2.2 to 2.75 V. */    
+    ADI_PWR_VOLTAGE_RANGE_2_2_TO_2_75,  
+    /*! Battery voltage is in the range of 1.6 to 2.2 V.  */        
+    ADI_PWR_VOLTAGE_RANGE_1_6_TO_2_2    
+} ADI_PWR_VOLTAGE_RANGE;
+
+#if defined(__ADUCM4x50__)
+/*!
+ *  Enumeration of LFXTAL Robust Mode Load select. The amount of loading tolerated when 
+ *  LFXTAL robust mode is selected, that is when LFXTAL robust mode is enabled.
+ */
+typedef enum
+{
+    /*! No Trim, and big resistive loads not tolerated. */
+    ADI_PWR_LFXTAL_LOAD_NONE,
+    /*! 20 MOHM Load mode, greater than 20 MOHM load allowed. */
+    ADI_PWR_LFXTAL_LOAD_20MOHM,
+    /*! 10 MOHM Load mode, greater than 10 MOHM load allowed. */
+    ADI_PWR_LFXTAL_LOAD_10MOHM,
+    /*! 5 MOHM load resistance allowed on both IO pins, the user can scale the current 
+        down if the load is expected to be smaller than 5 MOHM. */
+    ADI_PWR_LFXTAL_LOAD_5MOHM
+    
+}ADI_PWR_LFXTAL_LOAD;
+
+/*!
+* Enumeration of HP Buck load modes. The modes can be used to choose the loading capability 
+* of the HPBUCK. The low load mode and high load mode are based on the loading in the system.
+*/
+typedef enum
+{
+    /*! HPBUCK Low load mode.  This mode can be set if the maximum system clock(HCLK) frequency 
+        is 26 MHz. */   
+    ADI_PWR_HPBUCK_LD_MODE_LOW,
+    
+    /*! HPBUCK High load mode. This mode can be set if the  system clock(HCLK) frequency is greater 
+        than 26 MHz. */
+    ADI_PWR_HPBUCK_LD_MODE_HIGH
+    
+}ADI_PWR_HPBUCK_LD_MODE;
+#endif /* __ADUCM4x50__ */
+
+/*  Related clock APIs */
+
+/* 
+ * Initialize the dynamic power management service 
+ */
+ADI_PWR_RESULT  adi_pwr_Init(void);
+
+/* 
+ * =================================================================
+ *  Clock Management related  APIs 
+ * =================================================================
+*/
+
+/*
+ *  Update the internal clock variable based on current configuration 
+ */
+ADI_PWR_RESULT adi_pwr_UpdateCoreClock(void);
+
+/* 
+ * Set the external clock frequency.
+ */
+ADI_PWR_RESULT adi_pwr_SetExtClkFreq(
+               const uint32_t ExtClkFreq
+               );
+
+/* 
+ * To Configure the root clock muxing 
+ */
+ADI_PWR_RESULT adi_pwr_SetRootClockMux(
+               const ADI_CLOCK_MUX_ID eClockID
+               );
+
+/*
+ * To Configure the root clock muxing 
+ */
+ADI_PWR_RESULT adi_pwr_SetPLLClockMux(
+               const ADI_CLOCK_MUX_ID eClockID
+               );
+
+/*
+ *  To Configure the root clock muxing 
+ */
+ADI_PWR_RESULT adi_pwr_SetLFClockMux(
+               const ADI_CLOCK_MUX_ID eClockID
+               );
+
+#if defined(__ADUCM4x50__)               
+/*
+ * To Enable/Disable the LFXTAL robust mode.
+ */
+ADI_PWR_RESULT adi_pwr_EnableLFXTALRobustMode(
+                const bool  bEnable
+                );
+
+/*
+ * To configure the LFXTAL robust mode load.
+ */
+ADI_PWR_RESULT adi_pwr_SetLFXTALRobustModeLoad(
+                const ADI_PWR_LFXTAL_LOAD eLoad
+                );
+
+
+/*
+ * To Enable/Disable the LFXTAL Fail Auto switch.
+ */
+ADI_PWR_RESULT adi_pwr_EnableLFXTALFailAutoSwitch(
+                const bool  bEnable
+                );                
+
+
+/*
+ *  To enable/disable auto switching of root clock to HFOSC upon detection
+ *  of Root clock failure.
+ */ 
+ADI_PWR_RESULT adi_pwr_EnableRootClockFailAutoSwitch(
+               const bool bEnable
+               );
+
+/*
+ *  To set the HF Oscillator divide factor
+ */ 
+ADI_PWR_RESULT adi_pwr_SetHFOscDivFactor(
+               const ADI_PWR_HFOSC_DIV    eDivFactor
+               );
+
+/*
+ *  To set the HF oscillator automatic divide by 1 during wakeup from Flexi mode
+ */ 
+ADI_PWR_RESULT adi_pwr_EnableHFOscAutoDivBy1(
+               const bool   bEnable
+               );
+               
+#endif /* __ADUCM4x50__ */
+
+
+               
+/* 
+ * To Configure the reference clock muxing 
+ */
+ADI_PWR_RESULT adi_pwr_SetRefClockMux(
+               const ADI_CLOCK_MUX_ID eClockID
+               );
+
+/*
+ *  Get external clock frequency. 
+ */
+ADI_PWR_RESULT adi_pwr_GetExtClkFreq(
+               uint32_t *pExtClock
+               );
+
+/* 
+ * Get current clock frequency. This API can be used to know PCLK, HCLK. 
+ */
+ADI_PWR_RESULT adi_pwr_GetClockFrequency(
+               const ADI_CLOCK_ID eClockId,
+               uint32_t *pClock
+               );
+/* 
+ * To enable/disable the specific clock. 
+ */
+ADI_PWR_RESULT adi_pwr_EnableClock(
+               const ADI_CLOCK_GATE eClockGate, 
+               const bool bEnable
+               );
+
+/* 
+ * To enable/disable the specific clock source. 
+ */
+ADI_PWR_RESULT adi_pwr_EnableClockSource(
+               const ADI_CLOCK_SOURCE_ID eClockSource, 
+               const bool bEnable
+               );
+/* 
+ * To set the specific clock divider. 
+*/
+ADI_PWR_RESULT adi_pwr_SetClockDivider(
+               const ADI_CLOCK_ID eClockId,
+               const uint16_t nDiv
+               );
+/* 
+ * To Get the clock status. 
+*/
+ADI_PWR_RESULT adi_pwr_GetClockStatus(
+               const ADI_CLOCK_SOURCE_ID eClockSource,
+               ADI_CLOCK_SOURCE_STATUS *peStatus
+               );
+/* 
+ * To configure the PLL to generate the SPLL
+*/
+ADI_PWR_RESULT adi_pwr_SetPll(
+                uint8_t  nDivFactor, 
+                const uint8_t  nMulFactor, 
+                const bool bDiv2,
+                const bool bMul2
+                );
+                
+/* To enable the interrupt for clock monitoring LFXTAL/HFXTAL/PLL.*/
+ADI_PWR_RESULT adi_pwr_EnableClockInterrupt(
+                const ADI_PWR_CLOCK_IRQ eIrq, 
+                const bool bEnable
+                );
+
+/* Enabling the LFXTAL bypass mode */
+ADI_PWR_RESULT  adi_pwr_EnableLFXTALBypass(
+                const bool bEnable
+                );
+
+               
+/* 
+ * =================================================================
+ *  Power Management related  APIs 
+ * =================================================================
+*/
+/* To enable the interrupt for voltage monitoring.*/
+ADI_PWR_RESULT adi_pwr_EnablePMGInterrupt(
+                const ADI_PWR_PMG_IRQ eIrq, 
+                const bool bEnable
+                );
+
+/*
+ * To know which is interrupt caused the processor to wake up from SHUTDOWN mode.
+ */
+ADI_PWR_RESULT adi_pwr_GetWakeUpStatus(
+               ADI_PWR_WAKEUP_STATUS *peStatus
+               );
+
+/*
+ * To select the voltage range of the battery for monitoring.
+*/
+ADI_PWR_RESULT adi_pwr_SetVoltageRange(
+               const ADI_PWR_VOLTAGE_RANGE eRange
+               );
+
+/*
+ *  For entering the low power mode.
+*/
+ADI_PWR_RESULT adi_pwr_EnterLowPowerMode(
+                const ADI_PWR_POWER_MODE PowerMode,
+                uint32_t volatile *        pnInterruptOccurred,
+                const uint8_t            PriorityMask
+                );
+
+/*
+ *  For exiting the low power mode.
+*/
+ADI_PWR_RESULT adi_pwr_ExitLowPowerMode(
+                uint32_t volatile *  pnInterruptOccurred
+                );
+
+/* To enable the HPBUCK */
+ADI_PWR_RESULT adi_pwr_EnableHPBuck(
+               const bool bEnable
+               );
+               
+#if defined(__ADUCM4x50__)
+
+/* Set the clock output through the GPIO */
+ADI_PWR_RESULT  adi_pwr_SetGPIOClockOutput(
+                const ADI_CLOCK_OUTPUT_ID eClockOutput
+                );
+
+                
+/* To enable the HPBUCK Low Power mode */
+ADI_PWR_RESULT adi_pwr_EnableHPBuckLowPowerMode(
+               const bool bEnable
+               );
+               
+/* To enable the HPBUCK Load mode */
+ADI_PWR_RESULT adi_pwr_SetHPBuckLoadMode(
+               const ADI_PWR_HPBUCK_LD_MODE   eLoadMode
+               );
+
+#endif /* __ADUCM4x50__ */               
+/* 
+ * For registering the call back function .
+*/
+ADI_PWR_RESULT adi_pwr_RegisterCallback(
+               const ADI_CALLBACK pfCallback,
+               void *pcbParam
+              );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ADI_PWR_H */
+
+
+/*@}*/
+
+/*
+** EOF
+*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/rng/adi_rng.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/rng/adi_rng.h
new file mode 100755
index 00000000000..a8375fba1db
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/rng/adi_rng.h
@@ -0,0 +1,204 @@
+/*!
+ *****************************************************************************
+ @file    adi_rng.h
+ @brief   Random Number Generator Driver
+ -----------------------------------------------------------------------------
+Copyright (c) 2012-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+/*! \addtogroup RNG_Driver RNG Driver
+ *  Random Number Generator Driver
+ *  @{
+ */
+
+#ifndef ADI_RNG_H
+#define ADI_RNG_H
+
+#include <adi_processor.h>
+#include <adi_callback.h>
+
+#if  !defined(__ADUCM4x50__) &&  !defined(__ADUCM302x__)
+#error "Unsupported processor"
+#endif
+
+#include <adi_rng_config.h>
+
+#ifdef __ICCARM__
+/* IAR MISRA C 2004 error suppressions.
+ *
+ * Pm011 (rule 6.3): The basic types of char, int, long, float cannot be used.
+ *   bool is used in the APIs as it is not affending the rule. Disabling this as IAR treats it as an error.
+ */
+#pragma diag_suppress=Pm011
+#endif /* __ICCARM__ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * \enum ADI_RNG_RESULT
+ * Random Number Generator API return codes
+ */
+typedef enum
+{
+    ADI_RNG_SUCCESS = 0,            /*!<  No Error, API suceeded */
+    ADI_RNG_UNKNOWN_ERROR,          /*!<  Unknown error detected */
+    ADI_RNG_ALREADY_INITIALIZED,    /*!<  RNG is already initialized */
+    ADI_RNG_INVALID_PARAM,          /*!<  Invalid function parameter */
+    ADI_RNG_BAD_DEV_HANDLE,         /*!<  Invalid device handle passed */
+    ADI_RNG_BAD_DEVICE_NUM,         /*!<  Invalid device instance */
+    ADI_RNG_NOT_INITIALIZED,        /*!<  RNG not yet initialized */
+    ADI_RNG_INVALID_STATE           /*!<  Device is in an invalid state */
+} ADI_RNG_RESULT;
+
+/*!
+ * \enum ADI_RNG_EVENT
+ * Random Number Generator callback events
+ */
+typedef enum
+{
+    ADI_RNG_EVENT_READY,               /*!< Random number ready event */
+    ADI_RNG_EVENT_STUCK                /*!< The ring oscillator got stuck event */
+} ADI_RNG_EVENT;
+
+
+/*! The amount of application supplied memory required by the RNG driver */
+#define ADI_RNG_MEMORY_SIZE        (12u)
+
+
+/*! RNG Device handle typedef */
+typedef void* ADI_RNG_HANDLE;
+
+/*================ E X T E R N A L S ==================*/
+
+/*
+ * RNG API
+ */
+
+/* Open a random number generator device */
+extern ADI_RNG_RESULT adi_rng_Open(
+                            uint32_t             const  nDeviceNum,
+                            void*                const  pMemory,
+                            uint32_t             const  MemorySize,
+                            ADI_RNG_HANDLE*      const  phDevice
+                            );
+
+/* Close the RNG Device */
+extern ADI_RNG_RESULT adi_rng_Close(ADI_RNG_HANDLE hDevice);
+
+/* Enable/Disable the device */
+extern ADI_RNG_RESULT adi_rng_Enable (
+                                      ADI_RNG_HANDLE const hDevice,
+                                      bool           const bFlag
+                                      );
+/* Enable/Disable buffering */
+extern ADI_RNG_RESULT adi_rng_EnableBuffering (
+                                               ADI_RNG_HANDLE const hDevice,
+                                               bool           const bFlag
+                                               );
+
+/* Set the sample length */
+extern ADI_RNG_RESULT adi_rng_SetSampleLen (
+                                            ADI_RNG_HANDLE const hDevice,
+                                            uint16_t       const nLenPrescaler,
+                                            uint16_t       const nLenReload
+                                            );
+
+/* Get whether the random number is ready */
+extern ADI_RNG_RESULT adi_rng_GetRdyStatus (
+                                            ADI_RNG_HANDLE const hDevice,
+                                            bool*          const pbFlag
+                                            );
+
+/* Get whether the ring oscillator output is stuck or not */
+extern ADI_RNG_RESULT adi_rng_GetStuckStatus (
+                                              ADI_RNG_HANDLE const hDevice,
+                                              bool*          const pbFlag
+                                              );
+
+/* Get the random number */
+extern ADI_RNG_RESULT adi_rng_GetRngData (
+                                          ADI_RNG_HANDLE const hDevice,
+                                          uint32_t*      const pRegData
+                                          );
+
+/* Get the oscillator count */
+extern ADI_RNG_RESULT adi_rng_GetOscCount (
+                                           ADI_RNG_HANDLE const hDevice,
+                                           uint32_t*      const pOscCount
+                                           );
+
+/* Get the oscillator count difference value */
+extern ADI_RNG_RESULT adi_rng_GetOscDiff (
+                                          ADI_RNG_HANDLE const hDevice,
+                                          uint32_t       const nIndex,
+                                          uint8_t*       const pOscDiff
+                                          );
+
+/* Register a callback */
+extern ADI_RNG_RESULT adi_rng_RegisterCallback (
+                                                ADI_RNG_HANDLE  hDevice,
+                                                ADI_CALLBACK    cbFunc,
+                                                void           *pCBParam
+                                                );
+
+/* Retrieve the current RNG sample length prescale and reload value configured in the device. */
+extern ADI_RNG_RESULT adi_rng_GetSampleLen (
+                                            ADI_RNG_HANDLE const hDevice,
+                                            uint16_t*      const pLenPrescaler,
+                                            uint16_t*      const pLenReload
+                                            );
+
+#ifdef __cplusplus
+}
+#endif
+
+#ifdef __ICCARM__
+#pragma diag_default=Pm011
+#endif /* __ICCARM__ */
+#endif /* include guard */
+
+/*
+** EOF
+*/
+
+/*@}*/
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/rtc/adi_rtc.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/rtc/adi_rtc.h
new file mode 100755
index 00000000000..4e235f70583
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/rtc/adi_rtc.h
@@ -0,0 +1,522 @@
+/*!
+ *****************************************************************************
+ @file    adi_rtc.h
+ @brief   Primary include file for Real Time Clock Services.
+ @version $Revision: 29004 $
+ @date    $Date: 2014-12-06 10:37:26 -0500 (Sat, 06 Dec 2014) $
+ -----------------------------------------------------------------------------
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#ifndef ADI_RTC_H__
+#define ADI_RTC_H__
+#include "adi_processor.h"
+
+#include <stdint.h>
+#include <adi_callback.h>
+#include <adi_rtc_config.h>
+
+/*! \addtogroup RTC_Driver RTC Driver
+ *  @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+
+/*! Amount of memory(In bytes) required by the RTC  device driver  for managing the operation.
+ * This memory is completely owned by the driver till the end of the operation.
+ */
+#define ADI_RTC_MEMORY_SIZE    (24u)
+
+/*! Emergency flush command to gatweay register */
+#define ADI_RTC_GATEWAY_FLUSH    0xa2c5
+
+/*! A device handle used in all API functions to identify the RTC device. */
+typedef void*   ADI_RTC_HANDLE;
+
+/*! Interrupt  bit position-1*/
+#define ADI_RTC_INTERRUPT_OFFSET                16
+
+/*! Interrupt  bit position-2*/
+#define ADI_RTC_INTERRUPT_OFFSET_IO_CAPTURE     21
+
+/*!
+ * RTC  API return codes
+ */
+typedef enum
+{
+    /*!  No Error, API succeeded */
+    ADI_RTC_SUCCESS,
+    /*!  Generic failure */
+    ADI_RTC_FAILURE,
+    /*!  RTC is in failsafe mode and not reliable */
+    ADI_RTC_CLOCK_FAILSAFE,
+    /*!  RTC is already initialized */
+    ADI_RTC_IN_USE,
+    /*!  Invalid device handle passed */
+    ADI_RTC_INVALID_HANDLE,
+    /*!  Asking to initialize an unknown instance */
+    ADI_RTC_INVALID_INSTANCE,
+    /*!  Parameter is out of range          */
+    ADI_RTC_INVALID_OPTION,
+    /*!  Specified operation not allowed */
+    ADI_RTC_OPERATION_NOT_ALLOWED,
+    /*!  One of the parameters is invalid */
+    ADI_RTC_INVALID_PARAM,
+    /*!  Input/SensorStrobe channel is invalid for the specified operation */
+    ADI_RTC_INVALID_CHANNEL
+    
+} ADI_RTC_RESULT;
+
+
+/*!
+ * RTC Interrupt Enable Bits.
+ */
+
+
+typedef uint32_t ADI_RTC_INT_TYPE;
+
+#define ADI_RTC_ALARM_INT                  0x00000001u    /*!< Alarm interrupt enable bit */
+#define ADI_RTC_MOD60ALM_INT               0x00000002u    /*!< modulo 60 Alarm interrupt enable */
+#define ADI_RTC_ISO_DONE_INT               0x00000004u    /*!< Power isolation done interrupt enable */
+#define ADI_RTC_WRITE_PENDERR_INT          0x00000008u    /*!< Write pend error interrupt enable */
+#define ADI_RTC_WRITE_SYNC_INT             0x00000010u    /*!< Write sync interrupt enable */
+#define ADI_RTC_WRITE_PEND_INT             0x00000020u    /*!< Write pend interrupt enable  */
+#define ADI_RTC_COUNT_INT                  0x00000040u    /*!< RTC count interrupt source enable */
+#define ADI_RTC_PSI_INT                    0x00000080u    /*!< Precaled Module 1 interrupt */
+#define ADI_RTC_TRIM_INT                   0x00000100u    /*!< Enable for the RTC trim interrupt source */
+#define ADI_RTC_COUNT_ROLLOVER_INT         0x00000200u    /*!< Enable for the RTC count roll-over interrupt source */
+#define ADI_RTC_MOD60_ROLLOVER_INT         0x00000400u    /*!< Enable for the RTC modulo-60 count roll-over interrupt source */
+#define ADI_RTC_SENSOR_STROBE_CH1_INT      0x00000800u    /*!< Enable interrupt for sensor strobe channel -1*/
+#define ADI_RTC_SENSOR_STROBE_CH2_INT      0x00001000u    /*!< Enable interrupt for sensor strobe channel -2*/
+#define ADI_RTC_SENSOR_STROBE_CH3_INT      0x00002000u    /*!< Enable interrupt for sensor strobe channel -3*/
+#define ADI_RTC_SENSOR_STROBE_CH4_INT      0x00004000u    /*!< Enable interrupt for sensor strobe channel -4*/
+#define ADI_RTC_INPUT_CAPTURE_CH0_INT      0x00008000u    /*!< Enable interrupt for input capture channel -0*/
+#define ADI_RTC_INPUT_CAPTURE_CH2_INT      0x00010000u    /*!< Enable interrupt for input capture channel -2*/
+#define ADI_RTC_INPUT_CAPTURE_CH3_INT      0x00020000u    /*!< Enable interrupt for input capture channel -3*/
+#define ADI_RTC_INPUT_CAPTURE_CH4_INT      0x00040000u    /*!< Enable interrupt for input capture channel -4*/
+#define ADI_RTC_LFXTL_FAILURE_INT          0x00080000u    /*!< Interrupt for LFXTL failure. LFXTL failure interrupt is mapped to RTC1 interrupt.*/
+#define ADI_RTC_RTCSS4_FE_INT              0x00100000u    /*!< Enable interrupt for Sensor Strobe channel 3*/
+#define ADI_RTC_RTCSS3_FE_INT              0x00200000u    /*!< Enable interrupt for Sensor Strobe channel 3*/
+#define ADI_RTC_RTCSS2_FE_INT              0x00400000u    /*!< Enable interrupt for Sensor Strobe channel 2*/
+#define ADI_RTC_RTCSS1_FE_INT              0x00800000u    /*!< Enable interrupt for Sensor Strobe channel 2*/
+#define ADI_RTC_RTCSS4MSKEN                0x01000000u    /*!< Enable interrupt for Sensor Strobe channel 4 Mask */
+#define ADI_RTC_RTCSS3MSKEN                0x02000000u    /*!< Enable interrupt for Sensor Strobe channel 3 Mask */
+#define ADI_RTC_RTCSS2MSKEN                0x04000000u    /*!< Enable interrupt for Sensor Strobe channel 2 Mask */
+#define ADI_RTC_RTCSS1MSKEN                0x08000000u    /*!< Enable interrupt for Sensor Strobe channel 1 Mask */
+#define ADI_RTC_CR5OCS_SS3SMPMTCHIRQEN     0x10000000u    /*!< Sample activity Interrupt enable for RTC Sensor Strobe Channel 3 */
+#define ADI_RTC_CR5OCS_SS2SMPMTCHIRQEN     0x20000000u    /*!< Sample activity Interrupt enable for RTC Sensor Strobe Channel 2 */
+#define ADI_RTC_CR5OCS_SS1SMPMTCHIRQEN     0x40000000u    /*!< Sample activity Interrupt enable for RTC Sensor Strobe Channel 1. */
+
+
+#define ADI_RTC_NUM_INTERRUPTS             31             /*!< Number of RTC interrupts. */
+
+
+/*!
+ * RTC Posted Write Status Bits.
+ */
+typedef enum
+{
+    /*!  Posted write control register-0 status bit */
+    ADI_RTC_WRITE_STATUS_CONTROL0      = 1 << BITP_RTC_SR0_WSYNCCR0,
+    /*!  Posted write status0 register status bit */
+    ADI_RTC_WRITE_STATUS_STATUS0       = 1 << BITP_RTC_SR0_WSYNCSR0,
+    /*!  Posted write count0 register status bit */
+    ADI_RTC_WRITE_STATUS_COUNT0        = 1 << BITP_RTC_SR0_WSYNCCNT0,
+    /*!  Posted write count1 register status bit */
+    ADI_RTC_WRITE_STATUS_COUNT1        = 1 << BITP_RTC_SR0_WSYNCCNT1,
+    /*!  Posted write alarm0 register status bit */
+    ADI_RTC_WRITE_STATUS_ALARM0        = 1 << BITP_RTC_SR0_WSYNCALM0,
+    /*!  Posted write alarm1 register status bit */
+    ADI_RTC_WRITE_STATUS_ALARM1        = 1 << BITP_RTC_SR0_WSYNCALM1,
+    /*!  Posted write trim register status bit */
+    ADI_RTC_WRITE_STATUS_TRIM          = 1 << BITP_RTC_SR0_WSYNCTRM
+} ADI_RTC_WRITE_STATUS;
+
+
+/*!
+ * RTC Trim intervals.
+ */
+typedef enum
+{
+    /*!  Trim interval is 2^2 seconds */
+    ADI_RTC_TRIM_INTERVAL_2           = (2 << BITP_RTC_TRM_IVL2EXPMIN    | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^3 seconds */
+    ADI_RTC_TRIM_INTERVAL_3           = (3 << BITP_RTC_TRM_IVL2EXPMIN    | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^4 seconds */
+    ADI_RTC_TRIM_INTERVAL_4           = (4 << BITP_RTC_TRM_IVL2EXPMIN    | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^5 seconds */
+    ADI_RTC_TRIM_INTERVAL_5           = (5 << BITP_RTC_TRM_IVL2EXPMIN    | 0x0 << BITP_RTC_TRM_IVL),
+      /*!  Trim interval is 2^6 seconds */
+    ADI_RTC_TRIM_INTERVAL_6           = (6 << BITP_RTC_TRM_IVL2EXPMIN    | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^7 seconds */
+    ADI_RTC_TRIM_INTERVAL_7           = (7 << BITP_RTC_TRM_IVL2EXPMIN    | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^8 seconds */
+    ADI_RTC_TRIM_INTERVAL_8           = (8 << BITP_RTC_TRM_IVL2EXPMIN    | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^9 seconds */
+    ADI_RTC_TRIM_INTERVAL_9           = (9 << BITP_RTC_TRM_IVL2EXPMIN    | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^10 seconds */
+    ADI_RTC_TRIM_INTERVAL_10           = (10 << BITP_RTC_TRM_IVL2EXPMIN  | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^11 seconds */
+    ADI_RTC_TRIM_INTERVAL_11           = (11 << BITP_RTC_TRM_IVL2EXPMIN  | 0x1 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^12 seconds */
+    ADI_RTC_TRIM_INTERVAL_12           = (12 << BITP_RTC_TRM_IVL2EXPMIN  | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^13 seconds */
+    ADI_RTC_TRIM_INTERVAL_13           = (13 << BITP_RTC_TRM_IVL2EXPMIN  | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^14 seconds */
+    ADI_RTC_TRIM_INTERVAL_14           = (14 << BITP_RTC_TRM_IVL2EXPMIN  | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^15 seconds */
+    ADI_RTC_TRIM_INTERVAL_15           = (14 << BITP_RTC_TRM_IVL2EXPMIN  | 0x1 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^16 seconds */
+    ADI_RTC_TRIM_INTERVAL_16           = (14 << BITP_RTC_TRM_IVL2EXPMIN  | 0x2 << BITP_RTC_TRM_IVL ),
+    /*!  Trim interval is 2^17 seconds */
+    ADI_RTC_TRIM_INTERVAL_17           = (14 << BITP_RTC_TRM_IVL2EXPMIN  | 0x3 << BITP_RTC_TRM_IVL)
+
+} ADI_RTC_TRIM_INTERVAL;
+
+/*!
+ * RTC input capture  channels.
+ */
+typedef enum
+{
+    /*!  Input capture channel-0  */
+    ADI_RTC_INPUT_CHANNEL_0           = 1 << BITP_RTC_CR2IC_IC0EN,
+    /*!  Input capture channel-2  */
+    ADI_RTC_INPUT_CHANNEL_2           = 1 << BITP_RTC_CR2IC_IC2EN,
+    /*!  Input capture channel-3  */
+    ADI_RTC_INPUT_CHANNEL_3           = 1 << BITP_RTC_CR2IC_IC3EN,
+    /*!  Input capture channel-4  */
+    ADI_RTC_INPUT_CHANNEL_4           = 1 << BITP_RTC_CR2IC_IC4EN
+
+}ADI_RTC_INPUT_CHANNEL;
+
+/*!
+ * RTC Sensor Strobe  channels.
+ */
+typedef enum
+{
+    /*!  Sensor Strobe channel-1  */
+    ADI_RTC_SS_CHANNEL_1               = 1 << BITP_RTC_CR3SS_SS1EN,
+#if defined(__ADUCM4x50__)    
+    /*!  Sensor Strobe channel-2  */
+    ADI_RTC_SS_CHANNEL_2               = 1 << BITP_RTC_CR3SS_SS2EN,
+    /*!  Sensor Strobe channel-3  */
+    ADI_RTC_SS_CHANNEL_3               = 1 << BITP_RTC_CR3SS_SS3EN,
+    /*!  Sensor Strobe channel-4  */
+    ADI_RTC_SS_CHANNEL_4               = 1 << BITP_RTC_CR3SS_SS4EN,
+#endif /* __ADUCM4x50__ */
+}ADI_RTC_SS_CHANNEL;
+
+/*!
+ * RTC Trim polarity.
+ */
+typedef enum
+{
+    /*!  Trim value is added every trim interval */
+    ADI_RTC_TRIM_ADD                   = (1 << BITP_RTC_TRM_ADD),
+    /*!  Trim value is subtracted every trim interval */
+    ADI_RTC_TRIM_SUB                   = (0 << BITP_RTC_TRM_ADD),
+} ADI_RTC_TRIM_POLARITY;
+
+/*!
+ * RTC Trim values.
+ */
+typedef enum
+{
+    /*!  Trim value is +/- 0 */
+    ADI_RTC_TRIM_0                     = (0 << BITP_RTC_TRM_VALUE),
+    /*!  Trim value is +/- 1 */
+    ADI_RTC_TRIM_1                     = (1 << BITP_RTC_TRM_VALUE),
+    /*!  Trim value is +/- 2 */
+    ADI_RTC_TRIM_2                     = (2 << BITP_RTC_TRM_VALUE),
+    /*!  Trim value is +/- 3 */
+    ADI_RTC_TRIM_3                     = (3 << BITP_RTC_TRM_VALUE),
+    /*!  Trim value is +/- 4 */
+    ADI_RTC_TRIM_4                     = (4 << BITP_RTC_TRM_VALUE),
+    /*!  Trim value is +/- 5 */
+    ADI_RTC_TRIM_5                     = (5 << BITP_RTC_TRM_VALUE),
+    /*!  Trim value is +/- 6 */
+    ADI_RTC_TRIM_6                     = (6 << BITP_RTC_TRM_VALUE),
+    /*!  Trim value is +/- 7 */
+    ADI_RTC_TRIM_7                     = (7 << BITP_RTC_TRM_VALUE)
+} ADI_RTC_TRIM_VALUE;
+
+/*!
+ * RTC control register set.
+ */
+typedef enum
+{
+  /*! Specify the RTC-Control register-0 */
+  ADI_RTC_CONTROL_REGISTER_0,
+  /*! Specify the RTC-Control register-1 */
+  ADI_RTC_CONTROL_REGISTER_1
+} ADI_RTC_CONTROL_REGISTER;
+
+/*================ E X T E R N A L S ==================*/
+
+/*
+ */
+
+/*************************************/
+/*    RTC API                       */
+/*************************************/
+ADI_RTC_RESULT adi_rtc_Open(
+               uint32_t         DeviceNumber,
+               void            *pDeviceMemory,
+               uint32_t         MemorySize,
+               ADI_RTC_HANDLE  *phDevice
+               );
+
+ADI_RTC_RESULT adi_rtc_Close(
+               ADI_RTC_HANDLE const hDevice
+               );
+
+/*************************************/
+/*    Enable APIs for RTC Device     */
+/*************************************/
+               
+ADI_RTC_RESULT adi_rtc_EnableAlarm(
+               ADI_RTC_HANDLE const hDevice,
+               bool bEnable
+               );
+
+ADI_RTC_RESULT adi_rtc_EnableMod60Alarm(
+               ADI_RTC_HANDLE const hDevice,
+               bool bEnable
+               );
+
+ADI_RTC_RESULT adi_rtc_Enable(
+               ADI_RTC_HANDLE const hDevice,
+               bool bEnable
+               );
+
+ADI_RTC_RESULT adi_rtc_EnableInterrupts(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_INT_TYPE Interrupts,
+               bool bEnable
+               );
+
+ADI_RTC_RESULT adi_rtc_EnableTrim(
+               ADI_RTC_HANDLE const hDevice,
+               bool bEnable
+               );
+               
+ADI_RTC_RESULT adi_rtc_EnableAutoReload(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_SS_CHANNEL   eSSChannel,
+               bool bEnable);
+
+ADI_RTC_RESULT adi_rtc_EnableSensorStrobeOutput (
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_SS_CHANNEL   eSSChannel, 
+               bool bEnable);
+
+ADI_RTC_RESULT adi_rtc_EnableInputCapture (
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_INPUT_CHANNEL eInpChannel,
+               bool bEnable);
+
+ADI_RTC_RESULT adi_rtc_EnableSensorStrobeChannelMask(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_SS_CHANNEL   eSSChannel, 
+               bool bEnable);
+               
+ADI_RTC_RESULT adi_rtc_EnableOverwriteSnapshot (
+               ADI_RTC_HANDLE const hDevice,
+               bool bEnable);
+               
+/*************************************/
+/*    Set APIs for RTC Device     */
+/*************************************/
+
+
+ADI_RTC_RESULT adi_rtc_SetMod60AlarmPeriod(
+               ADI_RTC_HANDLE const hDevice,
+               uint8_t nPeriod
+               );
+
+ADI_RTC_RESULT adi_rtc_SetAlarm(
+               ADI_RTC_HANDLE const hDevice,
+               uint32_t nAlarm
+               );
+
+ADI_RTC_RESULT adi_rtc_SetAlarmEx(
+               ADI_RTC_HANDLE const hDevice,
+               float  fAlarm
+               );
+
+
+ADI_RTC_RESULT adi_rtc_SetControlRegister(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_CONTROL_REGISTER eRegister,
+               uint32_t Control
+               );
+
+ADI_RTC_RESULT adi_rtc_SetCount(
+               ADI_RTC_HANDLE const hDevice,
+               uint32_t nCount
+               );
+
+ADI_RTC_RESULT adi_rtc_SetGateway(
+               ADI_RTC_HANDLE const hDevice,
+               uint16_t Command
+               );
+
+
+ADI_RTC_RESULT adi_rtc_SetPreScale(
+               ADI_RTC_HANDLE const hDevice,
+               uint8_t nPreScale
+               );
+
+ADI_RTC_RESULT adi_rtc_SetTrim(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_TRIM_INTERVAL eInterval,
+               ADI_RTC_TRIM_VALUE  eTrimValue,
+               ADI_RTC_TRIM_POLARITY eOperation
+               );
+               
+ADI_RTC_RESULT adi_rtc_SetSensorStrobeChannelMask(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_SS_CHANNEL   eSSChannel, 
+               uint8_t nMask);
+
+ADI_RTC_RESULT adi_rtc_SetAutoReloadValue(
+                ADI_RTC_HANDLE const hDevice,
+                ADI_RTC_SS_CHANNEL   eSSChannel, 
+                uint16_t nValue);
+                
+ADI_RTC_RESULT adi_rtc_SetInputCapturePolarity (
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_INPUT_CHANNEL eInpChannel,
+               bool bEnable);
+               
+ADI_RTC_RESULT adi_rtc_SetSensorStrobeValue(
+                ADI_RTC_HANDLE const hDevice,
+                ADI_RTC_SS_CHANNEL   eSSChannel, 
+                uint16_t nValue);
+
+/*************************************/
+/*    Get APIs for RTC Device     */
+/*************************************/
+
+ADI_RTC_RESULT adi_rtc_GetAlarm (
+               ADI_RTC_HANDLE hDevice,
+               uint32_t *pAlarm
+               );
+
+ADI_RTC_RESULT adi_rtc_GetAlarmEx (
+               ADI_RTC_HANDLE hDevice,
+               float *pAlarm);
+
+ADI_RTC_RESULT adi_rtc_GetControl (
+               ADI_RTC_HANDLE hDevice,
+               ADI_RTC_CONTROL_REGISTER eRegister ,
+               uint32_t *pControl);
+               
+ADI_RTC_RESULT adi_rtc_GetTrim(
+               ADI_RTC_HANDLE hDevice,
+               ADI_RTC_TRIM_VALUE *peTrim
+               );
+               
+ADI_RTC_RESULT adi_rtc_GetCount(
+               ADI_RTC_HANDLE const hDevice,
+               uint32_t *pCount
+               );
+
+ADI_RTC_RESULT adi_rtc_GetCountEx(
+               ADI_RTC_HANDLE const hDevice,
+               float *pfCount
+               );
+
+ADI_RTC_RESULT adi_rtc_GetSnapShot(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_INPUT_CHANNEL eChannel, 
+               uint32_t *pValue,
+               uint16_t *pFraction);
+
+ADI_RTC_RESULT adi_rtc_GetInputCaptureValue(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_INPUT_CHANNEL eChannel,
+               uint16_t *pValue);
+
+ADI_RTC_RESULT adi_rtc_GetWritePendStatus(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_WRITE_STATUS *pPendBits
+               );
+
+ADI_RTC_RESULT adi_rtc_GetWriteSyncStatus(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_WRITE_STATUS *pSyncBits
+               );
+               
+ADI_RTC_RESULT adi_rtc_GetSensorStrobeValue(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_SS_CHANNEL   eSSChannel, 
+               uint16_t *pValue);
+               
+ADI_RTC_RESULT adi_rtc_GetCountRegs(
+               ADI_RTC_HANDLE const hDevice, 
+               uint32_t *pnCount,
+               uint32_t *pfCount);        
+/************************************************/
+/*    RTC APIs for managing interrupt/sync     */
+/***********************************************/
+               
+ADI_RTC_RESULT adi_rtc_SynchronizeAllWrites(
+               ADI_RTC_HANDLE const hDevice
+               );
+
+ADI_RTC_RESULT adi_rtc_RegisterCallback(
+               ADI_RTC_HANDLE const  hDevice,
+               ADI_CALLBACK   const   pfCallback,
+               void        *const     pCBparam
+               );
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+
+#endif /* ADI_RTC_H__ */
+
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/spi/adi_spi.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/spi/adi_spi.h
new file mode 100755
index 00000000000..31e9b977d91
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/spi/adi_spi.h
@@ -0,0 +1,397 @@
+/*! *****************************************************************************
+ * @file    adi_spi.h
+ * @brief   Main include file for SPI Device driver definitions
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.ADI_SEM_SIZE
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+
+#ifndef ADI_SPI_H__
+#define ADI_SPI_H__
+
+#include <adi_processor.h>
+#include <rtos_map/adi_rtos_map.h>
+#include <adi_spi_config.h>
+
+/** @addtogroup SPI_Driver SPI Driver
+ *  @{
+ */
+
+
+#include <adi_spi_config.h>
+#include <adi_callback.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/*! Amount of memory(In bytes) required by the SPI device driver for managing the operation
+ *  of a SPI controller. The memory is passed to the driver when the driver is opened.
+ * The memory is completely owned by the driver till the the driver is closed.
+ *                                               
+ */
+   
+#define ADI_SPI_MEMORY_SIZE (40u + ADI_SEM_SIZE)
+        
+
+/*!
+ *****************************************************************************
+ * \enum ADI_SPI_RESULT
+ *
+ * SPI Device Error Codes.  #ADI_SPI_SUCCESS is always zero
+ * The return value of all SPI APIs returning #ADI_SPI_RESULT
+ * should always be tested at the application level for success or failure.
+ *
+ *****************************************************************************/
+typedef enum
+{
+    /*! Generic success.                    */
+    ADI_SPI_SUCCESS,
+    /*! Generic Failure.                      */
+    ADI_SPI_FAILURE,
+    /*! SPI device is already initialized.  */
+    ADI_SPI_IN_USE,
+    /*! Invalid device handle.              */
+    ADI_SPI_INVALID_HANDLE,
+    /*! Invalid device ID.                  */
+    ADI_SPI_INVALID_DEVICE_NUM,
+    /*! DMA configuration failure.          */
+    ADI_SPI_DMA_ERROR     ,
+    /*! NULL data pointer not allowed.      */
+    ADI_SPI_INVALID_POINTER,
+    /*! Parameter is out of range.          */
+    ADI_SPI_INVALID_PARAM,
+    /*! Unsupported mode of operation.      */
+    ADI_SPI_UNSUPPORTED_MODE,
+    /*! Semaphore in error           .      */
+    ADI_SPI_SEMAPHORE_FAILED,
+    /*! Invalid operation       */
+    ADI_SPI_INVALID_OPERATION,
+    /*! Buffer Not submitted */
+    ADI_SPI_BUFFER_NOT_SUBMITTED,
+    /*! Could not obtain the system clock */
+    ADI_SPI_BAD_SYS_CLOCK,
+    /*! Blocking PEND failed */
+    ADI_SPI_PEND_FAILED,
+    /*! DMA callback register failed */
+    ADI_SPI_DMA_REG_FAILED,
+    /*! Hardware error occurred */
+    ADI_SPI_HW_ERROR_OCCURRED
+} ADI_SPI_RESULT;
+
+/*!
+ *****************************************************************************
+ * \enum ADI_SPI_HW_ERRORS
+ *
+ * Enumeration of events notified in the application provided callback.
+ * More than one event can be recorded at a time so the enumerator symbols
+ * have to be assigned values of 2^N
+ *****************************************************************************/
+typedef enum
+{
+    /*!< The given buffer is processed. Application can use this event to submit
+         the next buffer to be transmitted. */
+    ADI_SPI_HW_ERROR_NONE                       = 0u,
+   /*!  Tx-underflow interrupt enable */
+    ADI_SPI_HW_ERROR_TX_UNDERFLOW               = 1u,
+    /*!  Rx-overflow interrupt enable */
+    ADI_SPI_HW_ERROR_RX_OVERFLOW                = 2u,
+    /*!  Rx DMA channel bus fault detected */
+    ADI_SPI_HW_ERROR_RX_CHAN_DMA_BUS_FAULT      = 4u,
+    /*!  Tx DMA channel bus fault detected */
+    ADI_SPI_HW_ERROR_TX_CHAN_DMA_BUS_FAULT      = 8u,
+    /*!  Rx DMA channel bus fault detected */
+    ADI_SPI_HW_ERROR_RX_CHAN_DMA_INVALID_DESCR  = 16u,
+    /*!  Tx DMA channel bus fault detected */
+    ADI_SPI_HW_ERROR_TX_CHAN_DMA_INVALID_DESCR  = 32u,
+    /*!  Rx DMA channel unkown error detected */
+    ADI_SPI_HW_ERROR_RX_CHAN_DMA_UNKNOWN_ERROR  = 64u,
+    /*!  Tx DMA channel unkown error detected */
+    ADI_SPI_HW_ERROR_TX_CHAN_DMA_UNKNOWN_ERROR  = 128u          
+
+} ADI_SPI_HW_ERRORS;
+
+/*!
+ *****************************************************************************
+ * \enum ADI_SPI_CHIP_SELECT
+ *
+ * SPI Device Chip Select Enumeration.  Allows designation of an external
+ * SPI slave device chip select pin to be driven by the SPI controller.
+ * Multiple external slave SPI devices may be present on a shared SPI bus,
+ * and the chip select pin allows each of them to be assigned dedicated selects.
+ * Use the #adi_spi_SetChipSelect() API to configure the active chip select.
+ * Note that SPI0 is an internal channel dedicated to the UHF controller and
+ * hence, has a dedicated SPI0 chip select pin that is not available externally.
+ *
+ *****************************************************************************/
+typedef enum
+{
+   /*! No  Slave Chip Select for SPI.               */
+    ADI_SPI_CS_NONE = 0,
+    /*! CS0 Slave Chip Select for SPI.               */
+    ADI_SPI_CS0 = 1,
+   /*! CS1 Slave Chip Select for SPI.               */
+    ADI_SPI_CS1 = 2,
+    /*! CS2 Slave Chip Select for SPI.               */
+    ADI_SPI_CS2 = 4,
+    /*! CS3 Slave Chip Select for SPI.               */
+    ADI_SPI_CS3 = 8
+} ADI_SPI_CHIP_SELECT;
+
+
+/*! SPI Device instance private data handle typedef. */
+typedef       struct __ADI_SPI_DEV_DATA_TYPE*  ADI_SPI_HANDLE;
+/*! SPI Device instance private data handle typedef. 'const' version */
+typedef const struct __ADI_SPI_DEV_DATA_TYPE*  ADI_SPI_CONST_HANDLE;
+
+
+/*!
+  * \struct ADI_SPI_TRANSCEIVER
+ *****************************************************************************
+ * SPI Device Command/Data Transceiver Structure.  Data structure used by
+ * the #adi_spi_MasterReadWrite(),#adi_spi_MasterSubmitBuffer()
+ * API to convey all parameters, consisting of
+ * prologue, transmit and receive data and size, and buffer increment flags.
+ * DMA and Half-Duplex operation are also specified in this structure as T/F.
+ *
+ * Each call to #adi_spi_MasterReadWrite or #adi_spi_MasterSubmitBuffer() must populate the following fields of the
+ * ADI_SPI_TRANSCEIVER block:
+ *
+ * @par TransmitterBytes
+ * The number of  bytes to be transmitted. If the value is zero, data will not be transmitted from the
+ * buffer pointed by pTransmitter.
+ *
+ * @par ReceiverBytes
+ * The number of  bytes to be received. If the value is zero, data will not be stored in the
+ * buffer pointed by pReceiver.
+ *
+ * @par pTransmitter
+ * Pointer to the application-defined transmit data buffer.  This is the data sent out
+ * over the SPI transmit wire (MOSI for Master-mode, MISO for Slave-mode) during the SPI transaction.
+ * For  SPI DMA mode (which is 16-bit based), the transmit buffer must be 16-bit aligned.
+ *
+ * @par pReceiver
+ * Pointer to the application-defined receive data buffer.  This is where the receive data
+ * will be stored from the SPI receive wire (MISO for Master-mode, MOSI for Slave-mode)
+ * during the SPI transaction.
+ * For SPI DMA mode (which is 16-bit based), the receive buffer must be 16-bit aligned.
+ *
+ * @par bTxIncrement
+ * Increment to be done for the transmit buffer after every transaction . The transmit data buffer
+ * pointer is advanced as each byte is sent.  If it is set to zero, the transmit data pointer is stationary.
+ * A stationary buffer pointer is useful for sending the same data to an external device or if
+ * the source data is from a fixed memory address.
+ *
+ * @par bRxIncrement
+ * Increment to be done for the receive buffer.   The transmit data buffer
+ * pointer is advanced as each byte is sent. If it is value is set to zero, the receive
+ * data pointer is stationary.  A stationary buffer pointer is useful for monitoring commands
+ * from an external device or if the receive data is going to a fixed memory address.
+ *
+ * @par bDMA
+ * Indicate whether the transaction is to use DMA (true) or not (false). If using DMA SPI
+ * transactions are limited to 2048 bytes. If more than 2048 bytes are needed then the application
+ * must use multiple transactions (DMA ping pong mode is not supported in the driver).
+ * For  SPI DMA mode (which is 16-bit based), TransmitterBytes/ReceiverBytes is rounded up to an
+ * even number by the SPI driver before submitting to DMA.
+ * Please align the buffer to 16 bit word boundary since the data transfer is 16bit.
+ *
+ *
+ * @par bRD_CTL
+ * Indicate whether the transaction should enable RD_CTL (true) or not (false).
+ * RD_CTL effectively provides half-duplex operation as outlined in the HRM.
+
+ *****************************************************************************/
+typedef struct
+{
+    /*! Pointer to transmit data.        */
+    uint8_t*    pTransmitter;
+    /*! Pointer to receive data.         */
+    uint8_t*    pReceiver;
+   /*! Data size  for TX(bytes).          */
+    uint16_t    TransmitterBytes;
+    /*! Data size  for RX(bytes).          */
+    uint16_t    ReceiverBytes;
+   /*!  Transmit pointer increment flag. */
+    uint8_t     nTxIncrement;
+   /*! Receive pointer increment flag.  */
+    uint8_t     nRxIncrement;
+    /*! DMA mode operation */
+    bool        bDMA;
+    /*! RD_CTL, half-duplex, operation */
+    bool        bRD_CTL;
+
+} ADI_SPI_TRANSCEIVER;
+
+
+
+/******************************************************************************
+ * SPI Device External API function prototypes
+ *****************************************************************************/
+
+/* Device Initialization and Uninitialization Interfaces */
+ADI_SPI_RESULT adi_spi_Open(
+               uint32_t nDeviceNum,
+               void *pDevMemory,
+               uint32_t nMemorySize,
+               ADI_SPI_HANDLE* const phDevice
+               );
+
+ADI_SPI_RESULT adi_spi_Close(
+               ADI_SPI_HANDLE const hDevice
+               );
+
+/******************************************************************
+ * Eliminatable functions that may be optimized out by the linker *
+ *****************************************************************/
+
+ADI_SPI_RESULT adi_spi_MasterReadWrite(
+               ADI_SPI_HANDLE const       hDevice,
+               const ADI_SPI_TRANSCEIVER* const pXfr
+               );
+
+
+ADI_SPI_RESULT adi_spi_SetMasterMode(
+               ADI_SPI_CONST_HANDLE const hDevice,
+               const bool bFlag
+               );
+
+/* Slave Mode APIs */
+ADI_SPI_RESULT adi_spi_SlaveReadWrite(
+               ADI_SPI_HANDLE const hDevice,
+               const ADI_SPI_TRANSCEIVER* const pXfr
+               );
+
+/* Command/Data transceiver API */
+ADI_SPI_RESULT adi_spi_MasterSubmitBuffer(
+              ADI_SPI_HANDLE const hDevice, 
+              const ADI_SPI_TRANSCEIVER* const pXfr
+                );
+
+ADI_SPI_RESULT adi_spi_SlaveSubmitBuffer(
+               ADI_SPI_HANDLE const hDevice, 
+               const ADI_SPI_TRANSCEIVER* 
+               const pXfr
+                 );
+
+ADI_SPI_RESULT adi_spi_RegisterCallback (
+               ADI_SPI_HANDLE const hDevice,  
+               ADI_CALLBACK const pfCallback, 
+               void *const pCBParam 
+                 );
+
+
+/* Turn a non-blocking call into a blocking call. Wait for the transaction to complete  */
+ADI_SPI_RESULT adi_spi_GetBuffer(
+               ADI_SPI_HANDLE const hDevice,
+               uint32_t * const pHWErrors
+               );
+
+/* Hardware Configuration Interface */
+ADI_SPI_RESULT adi_spi_SetClockPhase(
+               ADI_SPI_HANDLE const hDevice,
+               const bool bFlag
+               );
+
+ADI_SPI_RESULT adi_spi_SetClockPolarity(
+               ADI_SPI_HANDLE const hDevice,
+               const bool bFlag
+               );
+			   
+/* Query function for the data transfer completion  */
+ADI_SPI_RESULT adi_spi_isBufferAvailable(
+               ADI_SPI_CONST_HANDLE const hDevice,
+               bool* const bComplete
+               );
+
+
+
+ADI_SPI_RESULT adi_spi_SetContinuousMode(
+               ADI_SPI_CONST_HANDLE const hDevice,
+               const bool bFlag
+               );
+
+
+ADI_SPI_RESULT adi_spi_SetLoopback(
+               ADI_SPI_CONST_HANDLE const hDevice,
+               const bool bFlag
+               );
+
+ADI_SPI_RESULT adi_spi_SetIrqmode (
+               ADI_SPI_CONST_HANDLE const hDevice, 
+               const uint8_t nMode);
+
+ADI_SPI_RESULT adi_spi_SetReceiveOverflow(
+               ADI_SPI_CONST_HANDLE const hDevice,
+               const bool bFlag
+               );
+
+ADI_SPI_RESULT adi_spi_SetTransmitUnderflow(
+               ADI_SPI_CONST_HANDLE const hDevice,
+               const bool bFlag
+               );
+
+/* Mode Configuration Interface */
+ADI_SPI_RESULT adi_spi_SetBitrate(
+               ADI_SPI_CONST_HANDLE const hDevice,
+               const uint32_t Hertz
+               );
+ADI_SPI_RESULT adi_spi_SetChipSelect(
+               ADI_SPI_HANDLE const hDevice,
+               const ADI_SPI_CHIP_SELECT eChipSelect
+               );
+
+ADI_SPI_RESULT adi_spi_GetBitrate(
+               ADI_SPI_CONST_HANDLE const hDevice,
+               uint32_t* const pnBitrate
+               );
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/**@}*/
+
+
+#endif /* ADI_SPI_H__ */
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/sport/adi_sport.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/sport/adi_sport.h
new file mode 100755
index 00000000000..aaf32f2cb0a
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/sport/adi_sport.h
@@ -0,0 +1,236 @@
+/*! ****************************************************************************
+ * @file    adi_sport.h
+ * @brief   SPORT (Serial Port) Device driver definitions
+ * @details Header File for the SPORT driver API functions and definitions
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef ADI_SPORT_H
+#define ADI_SPORT_H
+
+/*=============  I N C L U D E S   =============*/
+
+#include <adi_processor.h>
+#include <rtos_map/adi_rtos_map.h>
+#include <drivers/dma/adi_dma.h>
+#include <adi_callback.h>
+
+/** @addtogroup SPORT_Driver SPORT Driver
+*  @{
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/*==============  D E F I N E S  ===============*/
+
+/**
+ * Amount of memory (bytes) required by the SPORT device driver for managing
+ * the operation in interrupt mode. This memory is completely owned by the
+ * driver till the end of the operation.
+ */
+#define ADI_SPORT_MEMORY_SIZE   (76u + ADI_SEM_SIZE)
+
+typedef void*  ADI_SPORT_HANDLE;        /*!< Handle to the SPORT Device */
+
+/**
+ * Enumeration of different channels of the SPORT
+ */
+typedef enum
+{
+    ADI_HALF_SPORT_A = 0,               /*!< First half SPORT */
+    ADI_HALF_SPORT_B = 1                /*!< Second half SPORT */
+} ADI_SPORT_CHANNEL;
+
+/**
+ * Enumeration for the direction of operation.
+ */
+typedef enum
+{
+    ADI_SPORT_DIR_RX,                   /*!< Sport in Rx mode */
+    ADI_SPORT_DIR_TX                    /*!< Sport in Tx mode */
+} ADI_SPORT_DIRECTION;
+
+/**
+ * Enumeration for enabling packing.
+ */
+typedef enum
+{
+    ADI_SPORT_NO_PACKING = 0,                                   /*!< No Packing */
+    ADI_SPORT_8BIT_PACKING = ENUM_SPORT_CTL_A_CTL_PACK_8BIT,    /*!< 8-bit packing */
+    ADI_SPORT_16BIT_PACKING = ENUM_SPORT_CTL_A_CTL_PACK_16BIT   /*!< 16-Bit packing */
+} ADI_SPORT_PACKING_MODE;
+
+/**
+ * Enumeration for Hardware Error encountered by the SPORT device.
+ */
+ typedef enum
+{
+    ADI_SPORT_HW_NO_ERR                  = 0x00,  /*!< No Hardware error */
+    ADI_SPORT_HW_ERR_RX_OVERFLOW         = 0x02,  /*!< Data overflow  for Rx (same value as Tx underflow) */
+    ADI_SPORT_HW_ERR_TX_UNDERFLOW        = 0x02,  /*!< Data underflow for Tx (same value as Rx overflow) */
+    ADI_SPORT_HW_ERR_FS                  = 0x04,  /*!< Frame sync error */
+    ADI_SPORT_HW_ERR_SYSDATAERR          = 0x10,  /*!< System Data Error */
+
+    ADI_SPORT_EVENT_RX_BUFFER_PROCESSED  = 0x20,  /*!< Processed the submitted RX buffer  */
+    ADI_SPORT_EVENT_TX_BUFFER_PROCESSED  = 0x40,  /*!< Processed the submitted TX buffer  */
+
+    ADI_SPORT_DMA_ERR_BUS                = 0x100, /*!< SPORT DMA bus error detected  */
+    ADI_SPORT_DMA_ERR_INVALID_DESCRIPTOR = 0x200  /*!< SPORT DMA invalid descriptor error detected  */
+}ADI_SPORT_EVENT;
+
+
+/**
+ *  Enumeration for result code returned from the SPORT device driver functions.
+ */
+typedef enum
+{
+    ADI_SPORT_SUCCESS,                  /*!< Success */
+    ADI_SPORT_FAILED,                   /*!< Generic Failure to indicate a call to SPORT driver function returned unsuccessful */
+    ADI_SPORT_INVALID_DEVICE_NUM ,      /*!< Invalid device number */
+    ADI_SPORT_INVALID_NULL_POINTER,     /*!< Specified pointer is invalid */
+    ADI_SPORT_INVALID_HANDLE,           /*!< The given handle is invalid */
+    ADI_SPORT_INVALID_PARAMETER,        /*!< Specified parameter is not valid */
+    ADI_SPORT_DMA_REGISTER_FAILED,      /*!< Registering DMA error handler failed */
+    ADI_SPORT_DEVICE_IN_USE,            /*!< The specified SPORT channel is already open and in use */
+    ADI_SPORT_INVALID_CONFIGURATION,    /*!< The SPORT configuration is invalid */
+    ADI_SPORT_BUFFERS_NOT_SUBMITTED,    /*!< Buffer submission failed */
+    ADI_SPORT_INVALID_WORD_LENGTH,      /*!< Invalid word size */
+    ADI_SPORT_OPERATION_NOT_ALLOWED,    /*!< Specified operation is not allowed when SPORT is transmitting/receiving data */
+    ADI_SPORT_HW_ERROR                  /*!< SPORT hardware or DMA reports an error  */
+} ADI_SPORT_RESULT;
+
+/*=============  P U B L I C   F U N C T I O N S =============*/
+
+/* Opens a SPORT device */
+ADI_SPORT_RESULT adi_sport_Open(
+    const uint32_t              nDevNum,
+    const ADI_SPORT_CHANNEL     eChannel,
+    const ADI_SPORT_DIRECTION   eDirection,
+    void                        *pMemory,
+    const uint32_t              nMemSize,
+    ADI_SPORT_HANDLE * const    phDevice
+    );
+
+/* Closes a SPORT device */
+ADI_SPORT_RESULT adi_sport_Close(
+    ADI_SPORT_HANDLE const      hDevice
+    );
+
+/* Submits a buffer to the driver */
+ADI_SPORT_RESULT adi_sport_SubmitBuffer(
+    ADI_SPORT_HANDLE const hDevice,
+    void *           const pBuffer,
+    uint32_t         const nNumBytes,
+    bool             const bDMA
+    );
+
+/* Get the processed buffer from the driver */
+ADI_SPORT_RESULT adi_sport_GetBuffer(
+    ADI_SPORT_HANDLE const      hDevice,
+    void ** const               ppBuffer,
+    uint32_t *                  pHwError
+    );
+
+/* Peek function to know whether an processed buffer is avilable */
+ADI_SPORT_RESULT adi_sport_IsBufferAvailable(
+    ADI_SPORT_HANDLE const      hDevice,
+    bool   * const              pbAvailable
+    );
+
+/* To register the callback function */
+ADI_SPORT_RESULT adi_sport_RegisterCallback(
+    ADI_SPORT_HANDLE const      hDevice,
+    const ADI_CALLBACK          pfCallback,
+    void * const                pCBparam
+    );
+
+/* Configure the data */
+ADI_SPORT_RESULT adi_sport_ConfigData(
+    ADI_SPORT_HANDLE  const             hDevice,
+    const uint8_t                       nWordLength,
+    const ADI_SPORT_PACKING_MODE        ePackMode,
+    const bool                          bLSBFirst
+    );
+
+/* Configure the clock */
+ADI_SPORT_RESULT adi_sport_ConfigClock(
+    ADI_SPORT_HANDLE const      hDevice,
+    const uint16_t              nClockRatio,
+    const bool                  bUseIntlClock,
+    const bool                  bRisingEdge,
+    const bool                  bGatedClk
+    );
+
+/* Configure the frame sync */
+ADI_SPORT_RESULT adi_sport_ConfigFrameSync(
+    ADI_SPORT_HANDLE const      hDevice,
+    const uint16_t              nFsDivisor,
+    const bool                  bFSRequired,
+    const bool                  bInternalFS,
+    const bool                  bDataFS,
+    const bool                  bActiveLowFS,
+    const bool                  bLateFS,
+    const bool                  bFSErrorOperation
+    );
+
+/* To mux the half-SPORT; this makes the device to use FS and Clock from other half-SPORT */
+ADI_SPORT_RESULT adi_sport_MultiplexSportSignal(
+    ADI_SPORT_HANDLE const      hDevice,
+    const bool                  bUseOtherFS,
+    const bool                  bUseOtherClk
+    );
+
+/* To configure the SPORT in timer mode */
+ADI_SPORT_RESULT adi_sport_ConfigTimerMode(
+    ADI_SPORT_HANDLE const      hDevice,
+    const uint8_t               nFSDuration,
+    const uint8_t               nWidth,
+    const bool                  bActiveLow
+    );
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* ADI_SPORT_H */
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/tmr/adi_tmr.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/tmr/adi_tmr.h
new file mode 100755
index 00000000000..33d00dece17
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/tmr/adi_tmr.h
@@ -0,0 +1,261 @@
+/*! *****************************************************************************
+ * @file    adi_tmr.h
+ * @brief   GP and RGB timer device driver public header file
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+
+#ifndef ADI_TMR_H
+#define ADI_TMR_H
+
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <adi_processor.h>
+#include <adi_callback.h>
+
+
+/** @addtogroup TMR_Driver Timer Driver
+ *  @{
+ */
+
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_TMR_RESULT
+ *   Enumeration for result code returned from the timer device driver functions.
+ *   The return value of all timer APIs returning #ADI_TMR_RESULT should always 
+ *   be tested at the application level for success or failure.
+ *****************************************************************************/
+typedef enum {
+    /*! Successful operation */
+    ADI_TMR_SUCCESS,
+    /*! Bad device number supplied by user */
+    ADI_TMR_BAD_DEVICE_NUM,
+    /*! Bad PWM output number supplied by user to #adi_tmr_ConfigPwm */
+    ADI_TMR_BAD_PWM_NUM,
+    /*! Bad event number supplied by user to #adi_tmr_ConfigEvent */
+    ADI_TMR_BAD_EVENT_ID,
+    /*! Bad timer configuration, reloading and free running are mutually exclusive options */
+    ADI_TMR_BAD_RELOAD_CONFIGURATION,
+    /*! Setup or enable function called while the timer is running */
+    ADI_TMR_OPERATION_NOT_ALLOWED,
+    /*! Timeout while waiting for busy bit to clear before writing control register */
+    ADI_TMR_DEVICE_BUSY,
+    /*! User attempts to reload the timer when reloading has not been enabled */
+    ADI_TMR_RELOAD_DISABLED,
+    /*! User attempts to read the current or captured count with a NULL pointer */
+    ADI_TMR_NULL_POINTER
+} ADI_TMR_RESULT;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_TMR_DEVICE
+ *   Enumeration for the hardware peripheral being used during the API call
+ *****************************************************************************/
+typedef enum {
+    /*! General purpose timer 0 */
+    ADI_TMR_DEVICE_GP0 = 0u,
+    /*! General purpose timer 1 */
+    ADI_TMR_DEVICE_GP1 = 1u,
+    /*! General purpose timer 2 */
+    ADI_TMR_DEVICE_GP2 = 2u,
+#if defined(__ADUCM302x__)
+    /*! Total number of devices (private) */
+    ADI_TMR_DEVICE_NUM = 3u,
+#elif defined(__ADUCM4x50__)
+    /*! RGB timer */
+    ADI_TMR_DEVICE_RGB = 3u,
+    /*! Total number of devices (private) */
+    ADI_TMR_DEVICE_NUM = 4u,
+#else 
+#error TMR is not ported for this processor
+#endif
+} ADI_TMR_DEVICE;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_TMR_EVENT
+ *   Enumeration of events notified in the application provided callback.
+ *****************************************************************************/
+typedef enum {
+  /*! Timeout event occurred */
+  ADI_TMR_EVENT_TIMEOUT = 0x01,  
+  /*! Event capture event occurred */
+  ADI_TMR_EVENT_CAPTURE = 0x02,
+} ADI_TMR_EVENT;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_TMR_PRESCALER
+ *   Prescale options when configuring the timer
+ *****************************************************************************/
+typedef enum {
+    /*! Count every 1 source clock periods */
+    ADI_TMR_PRESCALER_1   = 0u,
+    /*! Count every 16 source clock periods */
+    ADI_TMR_PRESCALER_16  = 1u, 
+    /*! Count every 64 source clock periods */
+    ADI_TMR_PRESCALER_64  = 2u,
+    /*! Count every 256 source clock periods */
+    ADI_TMR_PRESCALER_256 = 3u,
+} ADI_TMR_PRESCALER;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_TMR_CLOCK_SOURCE
+ *   Source clock options when configuring the timer
+ *****************************************************************************/
+typedef enum {
+    /*! Use periphreal clock (PCLK) */
+    ADI_TMR_CLOCK_PCLK  = 0u, 
+    /*! Use internal high frequency clock (HFOSC) */
+    ADI_TMR_CLOCK_HFOSC = 1u, 
+    /*! Use internal low frequency clock (LFOSC) */
+    ADI_TMR_CLOCK_LFOSC = 2u, 
+    /*! Use external low frequency clock (LFXTAL) */
+    ADI_TMR_CLOCK_LFXTAL = 3u,
+} ADI_TMR_CLOCK_SOURCE;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_TMR_PWM_OUTPUT
+ *   RGB PWM outputs, used to specify which PWM output to configure. For the GP
+ *   timers only #ADI_TMR_PWM_OUTPUT_0 is allowed. The RGB timer has all three 
+ *   outputs.
+ *****************************************************************************/
+typedef enum {
+    /*! PWM output 0 */
+    ADI_TMR_PWM_OUTPUT_0   = 0u,
+    /*! PWM output 1 */
+    ADI_TMR_PWM_OUTPUT_1   = 1u,
+    /*! PWM output 2 */
+    ADI_TMR_PWM_OUTPUT_2   = 2u,
+    /*! Total number of outputs (private) */
+    ADI_TMR_PWM_OUTPUT_NUM = 3u,
+} ADI_TMR_PWM_OUTPUT;
+
+/*!
+ *****************************************************************************
+ *  \struct ADI_TMR_CONFIG
+ *   Configuration structure to fill and pass to #adi_tmr_ConfigTimer when  
+ *   configuring the GP or RGB timer
+ *****************************************************************************/
+typedef struct {
+    /*! True to count up, false to count down */
+    bool                 bCountingUp;
+    /*! True for periodic (specific load value), false for free running (0xFFFF) */
+    bool                 bPeriodic;
+    /*! Prescaler */
+    ADI_TMR_PRESCALER    ePrescaler;
+    /*! Clock source */
+    ADI_TMR_CLOCK_SOURCE eClockSource;
+    /*! Load value (only relevant in periodic mode) */
+    uint16_t             nLoad;
+    /*! Asynchronous load value (only relevant in periodic mode, and when PCLK is used) */
+    uint16_t             nAsyncLoad;
+    /*! True to enable reloading, false to disable it (only relevant in periodic mode) */
+    bool                 bReloading;
+    /*! True to enable sync bypass, false to disable it */
+    bool                 bSyncBypass;
+} ADI_TMR_CONFIG;
+
+/*!
+ *****************************************************************************
+ *  \struct ADI_TMR_EVENT_CONFIG
+ *   Configuration structure to fill and pass to #adi_tmr_ConfigEvent when  
+ *   configuring event capture
+ *****************************************************************************/
+typedef struct {
+    /*! True to enable event capture, false to disable it */
+    bool    bEnable;
+    /*! True to reset the counter and prescaler when the selected event occurs, false to let it continue */
+    bool    bPrescaleReset;
+    /*! Event identifier, see hardware reference manual for details */
+    uint8_t nEventID;
+} ADI_TMR_EVENT_CONFIG;
+
+/*!
+ *****************************************************************************
+ *  \struct ADI_TMR_PWM_CONFIG
+ *   Configuration structure to fill and pass to #adi_tmr_ConfigPwm when  
+ *   configuring pulse width modulation output
+ *****************************************************************************/
+typedef struct {
+    /*! PWM output */
+    ADI_TMR_PWM_OUTPUT     eOutput;
+    /*! True if match mode (configurable duty cycle), false if toggle mode (50% duty cycle) */
+    bool                   bMatch;
+    /*! True for PWM idle high, false for PWM idle low */
+    bool                   bIdleHigh;
+    /*! Match value, only applicable if in match mode */
+    uint16_t               nMatchValue;
+} ADI_TMR_PWM_CONFIG;
+
+/******************************************************************************
+ * PUBLIC API
+ * 1.) Eliminate functions that may be optimized out by the linker
+ * 2.) Ordered by designed function call sequence
+ *****************************************************************************/
+
+/* Initialize timer driver */
+ADI_TMR_RESULT adi_tmr_Init            (ADI_TMR_DEVICE const eDevice, ADI_CALLBACK const pfCallback, void * const pCBParam, bool bEnableInt);
+
+/* Configuration interface functions */
+ADI_TMR_RESULT adi_tmr_ConfigTimer     (ADI_TMR_DEVICE const eDevice, ADI_TMR_CONFIG*       timerConfig);
+ADI_TMR_RESULT adi_tmr_ConfigEvent     (ADI_TMR_DEVICE const eDevice, ADI_TMR_EVENT_CONFIG* eventConfig);
+ADI_TMR_RESULT adi_tmr_ConfigPwm       (ADI_TMR_DEVICE const eDevice, ADI_TMR_PWM_CONFIG*   pwmConfig  );
+
+/* Timer start and stop */
+ADI_TMR_RESULT adi_tmr_Enable          (ADI_TMR_DEVICE const eDevice, bool bEnable);
+
+/* Read functions */
+ADI_TMR_RESULT adi_tmr_GetCurrentCount (ADI_TMR_DEVICE const eDevice, uint16_t *pCount);
+ADI_TMR_RESULT adi_tmr_GetCaptureCount (ADI_TMR_DEVICE const eDevice, uint16_t *pCount);
+
+/* Reload function */
+ADI_TMR_RESULT adi_tmr_Reload          (ADI_TMR_DEVICE const eDevice);
+
+
+/*! @} */
+
+
+#endif /* ADI_TMR_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/uart/adi_uart.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/uart/adi_uart.h
new file mode 100755
index 00000000000..abb0bf3109a
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/uart/adi_uart.h
@@ -0,0 +1,498 @@
+/*! *****************************************************************************
+ * @file    adi_uart.h
+ * @brief   UART device driver global include file.
+ * @details This a global file which includes a specific file based on the processor family.
+ *          This included file will be containing UART device driver functions.
+ -----------------------------------------------------------------------------
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#ifndef ADI_UART_H
+#define ADI_UART_H
+
+/** @addtogroup UART_Driver UART Driver
+*  @{
+*/
+
+/*! \cond PRIVATE */
+
+/*=============  I N C L U D E S   =============*/
+
+#include <stdint.h>
+#include <stddef.h>
+#include <string.h>
+#include <assert.h>
+#include <adi_processor.h>
+#include <adi_uart_config.h>
+#include <rtos_map/adi_rtos_map.h>
+#include <drivers/dma/adi_dma.h>
+#include <drivers/pwr/adi_pwr.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*! \endcond */
+
+/*! Amount of memory(bytes) required by the UART device driver for operating unidirectionally(Either RX or TX).
+ *  This memory is completely owned by the driver until the end of the operation.
+ */
+#define ADI_UART_UNIDIR_MEMORY_SIZE  (48u + (60u + ADI_SEM_SIZE))
+
+/*! Amount of memory(bytes) required by the UART device driver for operating bidirectionally(Both RX and TX).
+ *  This memory is completely owned by the driver until the end of the operation.
+ */
+#define ADI_UART_BIDIR_MEMORY_SIZE  (48u + (60u + ADI_SEM_SIZE)*2u)
+
+/*!
+ * Handle for managing the UART device typedef.
+ */
+typedef struct _ADI_UART_DEVICE* ADI_UART_HANDLE;
+
+/*!
+ * Handle for managing the UART device typedef 'const' version.
+ */
+typedef const struct _ADI_UART_DEVICE* ADI_UART_CONST_HANDLE;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_UART_DIRECTION
+ *   Enumeration for the UART direction.
+ *****************************************************************************/
+typedef enum
+{
+    ADI_UART_DIR_TRANSMIT,                              /*!< UART is only transmitting.   */
+
+    ADI_UART_DIR_RECEIVE,                               /*!< UART is only receiving.      */
+
+    ADI_UART_DIR_BIDIRECTION                            /*!< UART in bidirectional.       */
+
+} ADI_UART_DIRECTION;
+
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_UART_EVENT
+ *   Enumeration of events notified in the application provided callback.
+ *****************************************************************************/
+ typedef enum
+{
+    ADI_UART_EVENT_RX_BUFFER_PROCESSED,                 /*!< Rx buffer is processed.                                   */
+
+    ADI_UART_EVENT_TX_BUFFER_PROCESSED,                 /*!< Tx buffer is processed.                                   */
+
+    ADI_UART_EVENT_NO_RX_BUFFER_EVENT,                  /*!< No Rx buffer but data is in FIFO.                         */
+
+    ADI_UART_EVENT_AUTOBAUD_COMPLETE,                   /*!< Autobaud is complete.                                     */
+
+    ADI_UART_EVENT_HW_ERROR_DETECTED,                   /*!< Hardware error detected.                                  */
+    
+    ADI_UART_EVENT_AUTOBAUD_ERROR_DETECTED              /*!< Autobaud error detected.                                  */
+    
+}ADI_UART_EVENT;
+
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_UART_RESULT
+ *   Enumeration for result code returned from the UART device driver functions.
+ *   The return value of all UART APIs returning #ADI_UART_RESULT
+ *   should always be tested at the application level for success or failure.
+ *****************************************************************************/
+ typedef enum
+{
+
+    ADI_UART_SUCCESS,                           /*!< Generic success.                                               */
+
+    ADI_UART_FAILED,                            /*!< Generic failure.                                               */
+
+    ADI_UART_SEMAPHORE_FAILED,                  /*!< Semaphore error.                                               */
+
+    ADI_UART_INVALID_HANDLE,                    /*!< Invalid device handle.                                         */
+
+    ADI_UART_DEVICE_IN_USE,                     /*!< UART device in use.                                            */
+
+    ADI_UART_INVALID_DEVICE_NUM,                /*!< Invalid device number.                                         */
+
+    ADI_UART_INVALID_POINTER,                   /*!< NULL data pointer is not allowed.                              */
+
+    ADI_UART_INSUFFICIENT_MEMORY,               /*!< Insufficent memory.                                            */
+
+    ADI_UART_INVALID_DIR,                       /*!< Invalid UART direction.                                        */
+
+    ADI_UART_OPERATION_NOT_ALLOWED,             /*!< Invalid operation.                                             */
+
+    ADI_UART_INVALID_PARAMETER,                 /*!< Invalid parameter.                                             */
+
+    ADI_UART_BUFFER_NOT_SUBMITTED,              /*!< Buffer not submitted.                                          */
+
+    ADI_UART_INVALID_DATA_TRANSFER_MODE,        /*!< Invalid transfer mode.
+                                                     Adi_uart_Read()/adi_uart_Write() is used in nonblocking mode
+                                                     or adi_uart_SubmitRxBuffer()/adi_uart_SubmitTxBuffer()
+                                                     is used in blocking mode.                                      */
+
+    ADI_UART_HW_ERROR_DETECTED,                 /*!< Hardware error detected.                                       */
+
+    ADI_UART_AUTOBAUD_ERROR_DETECTED,           /*!< Autobaud error detected.                                       */
+      
+    ADI_UART_ERR_DMA_REGISTER,                  /*!< Error while registering the DMA callback.                      */
+      
+    ADI_UART_INVALID_DATA_SIZE                  /*!< Invalid transfer size. Must be less than 1025 bytes            */
+
+} ADI_UART_RESULT;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_UART_HW_ERRORS
+ *   Enumeration for UART hardware errors. If hardware error(s) occur in
+ *   either callback or interrupt mode, they are mapped to #ADI_UART_HW_ERRORS.
+ *   Interpretation of the break condition is application specific.
+ *****************************************************************************/
+typedef enum
+{
+    ADI_UART_NO_HW_ERROR                     = 0x00,   /*!< No hardware error.                                             */
+
+    ADI_UART_HW_ERR_FRAMING                  = 0x10,   /*!< Rx framing error.                                              */
+
+    ADI_UART_HW_ERR_PARITY                   = 0x20,   /*!< Rx parity error.                                               */
+
+    ADI_UART_HW_ERR_OVERRUN                  = 0x40,   /*!< Receive overrun.                                               */
+ 
+    ADI_UART_BREAK_INTERRUPT                 = 0x80,   /*!< Break condition.                                               */
+      
+    ADI_UART_HW_ERR_RX_CHAN_DMA_BUS_FAULT     = 0x100,  /*!< Rx DMA channel bus fault detected.                             */
+    
+    ADI_UART_HW_ERR_TX_CHAN_DMA_BUS_FAULT     = 0x200,  /*!< Tx DMA channel bus fault detected.                             */
+   
+    ADI_UART_HW_ERR_RX_CHAN_DMA_INVALID_DESCR = 0x400,  /*!< Rx DMA channel invalid descriptor detected.                    */
+    
+    ADI_UART_HW_ERR_TX_CHAN_DMA_INVALID_DESCR = 0x800,  /*!< Tx DMA channel invalid descriptor detected.                    */
+    
+    ADI_UART_HW_ERR_RX_CHAN_DMA_UNKNOWN_ERROR = 0x1000, /*!< Rx DMA channel unknown error detected.                         */
+  
+    ADI_UART_HW_ERR_TX_CHAN_DMA_UNKNOWN_ERROR = 0x2000, /*!< Tx DMA channel unknown error detected.                         */
+
+}ADI_UART_HW_ERRORS;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_UART_AUTOBAUD_ERRORS
+ *   Enumeration for UART autobaud errors. If autobaud related error(s) occur
+ *   they are mapped to #ADI_UART_AUTOBAUD_ERRORS.
+ *****************************************************************************/
+typedef enum
+{
+    ADI_UART_AUTOBAUD_NO_ERROR              = 0x000,  /*!< No autobaud error.                                           */
+
+    ADI_UART_AUTOBAUD_TIMEOUT_NO_START_EDGE = 0x100,  /*!< Timeout due to no valid start edge found during autobaud.    */
+
+    ADI_UART_AUTOBAUD_TIMEOUT_LONGBREAK     = 0x200,  /*!< Timeout due to break condition detected during autobaud.     */
+
+    ADI_UART_AUTOBAUD_TIMEOUT_NO_END_EDGE   = 0x400   /*!< Timeout due to no valid end edge found during autobaud.      */
+
+}ADI_UART_AUTOBAUD_ERRORS;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_UART_TRIG_LEVEL
+ *   Enumeration for the FIFO trigger level.
+ *****************************************************************************/
+typedef enum
+{
+
+    ADI_UART_RX_FIFO_TRIG_LEVEL_1BYTE   =  0 << BITP_UART_FCR_RFTRIG,  /*!< 1-byte to trigger RX interrupt.  */
+
+    ADI_UART_RX_FIFO_TRIG_LEVEL_4BYTE   =  1 << BITP_UART_FCR_RFTRIG,  /*!< 4-byte to trigger RX interrupt.  */
+    
+    ADI_UART_RX_FIFO_TRIG_LEVEL_8BYTE   =  2 << BITP_UART_FCR_RFTRIG,  /*!< 8-byte to trigger RX interrupt.  */
+    
+    ADI_UART_RX_FIFO_TRIG_LEVEL_14BYTE  =  3 << BITP_UART_FCR_RFTRIG   /*!< 14-byte to trigger RX interrupt. */
+
+}ADI_UART_TRIG_LEVEL;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_UART_WORDLEN
+ *   Enumeration for data width. 
+ *****************************************************************************/
+typedef enum
+{
+    ADI_UART_WORDLEN_5BITS,             /*!< 5 bits wide. */
+
+    ADI_UART_WORDLEN_6BITS,             /*!< 6 bits wide. */
+
+    ADI_UART_WORDLEN_7BITS,             /*!< 7 bits wide. */
+
+    ADI_UART_WORDLEN_8BITS              /*!< 8 bits wide. */
+
+} ADI_UART_WORDLEN;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_UART_PARITY
+ *   Enumeration for parity check.
+ *****************************************************************************/
+typedef enum
+{
+    ADI_UART_NO_PARITY          =  0x0,  /*!< No parity.          */
+
+    ADI_UART_ODD_PARITY         =  0x8,  /*!< Odd parity.         */
+
+    ADI_UART_EVEN_PARITY        =  0x18, /*!< Even Parity.        */
+
+    ADI_UART_ODD_PARITY_STICKY  =  0x28, /*!< Sticky odd parity.  */
+
+    ADI_UART_EVEN_PARITY_STICKY =  0x38  /*!< Sticky even parity. */
+      
+} ADI_UART_PARITY;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_UART_STOPBITS
+ *   Enumeration for the number of stop bits.
+ *****************************************************************************/
+typedef enum
+{
+    
+    ADI_UART_ONE_STOPBIT               = 0x00,          /*! One stop bit regardless of the word length                           */
+   
+    ADI_UART_ONE_AND_HALF_TWO_STOPBITS = 0x04           /*! Number of stop bits based on word length. 1.5 stop bits 
+                                                            for word length of 5 bits and 2 for rest( 6,7,8 bit word length)     */
+      
+} ADI_UART_STOPBITS;
+
+/*!
+ *****************************************************************************
+ * \enum  ADI_UART_TRANSFER_MODE
+ *  Enumeration for data transfer mode.
+ *****************************************************************************/
+typedef enum
+{
+    
+    ADI_UART_DATA_TRANSFER_MODE_NONE,       /*! Mode of data transfer is not selected.                             */ 
+    
+    ADI_UART_DATA_TRANSFER_MODE_BLOCKING,   /*! Blocking mode. Only calls to adi_uart_Read or adi_uart_write  
+                                                are allowed for sending or receiving data.                         */
+    
+    ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING /*! Non-Blocking mode. Only calls to adi_uart_SubmitRxBuffer or
+                                                adi_uart_SubmitTxBuffer are allowed for sending or receiving data. */
+
+} ADI_UART_TRANSFER_MODE;
+
+
+/******************************************************************************
+ * UART Device external API function prototypes
+ *****************************************************************************/
+
+/*
+ * Device initialization and uninitialization interfaces.
+*/
+ADI_UART_RESULT adi_uart_Open(
+                uint32_t           const nDeviceNum,
+                ADI_UART_DIRECTION const eDirection,
+                void                    *pMemory,
+                uint32_t           const nMemSize,
+                ADI_UART_HANDLE   *const phDevice
+);
+
+ADI_UART_RESULT adi_uart_Close(
+                ADI_UART_HANDLE  const   hDevice
+);
+
+
+/******************************************************************************
+ * Eliminatable functions that may be optimized out by the linker
+ *****************************************************************************/
+
+/*
+ * Non-blocking mode functions.
+*/
+
+ADI_UART_RESULT adi_uart_SubmitTxBuffer(
+                ADI_UART_HANDLE const    hDevice,
+                void           *const    pBuffer,
+                uint32_t        const    nBufSize,
+                bool            const    bDMA
+);
+
+ADI_UART_RESULT adi_uart_SubmitRxBuffer(
+                ADI_UART_HANDLE const    hDevice,
+                void           *const    pBuffer,
+                uint32_t        const    nBufSize,
+                bool            const    bDMA
+);
+
+ADI_UART_RESULT adi_uart_GetTxBuffer(
+                ADI_UART_HANDLE const    hDevice,
+                void          **const    ppBuffer,
+                uint32_t                *pHwError
+);
+
+ADI_UART_RESULT adi_uart_GetRxBuffer(
+                ADI_UART_HANDLE const    hDevice,
+                void          **const    ppBuffer,
+                uint32_t                *pHwError
+);
+ADI_UART_RESULT adi_uart_IsTxBufferAvailable(
+                ADI_UART_HANDLE const    hDevice,
+                bool           *const    pbAvailable
+);
+
+ADI_UART_RESULT adi_uart_IsRxBufferAvailable(
+                ADI_UART_HANDLE const    hDevice,
+                bool           *const    pbAvailable
+);
+
+/*
+ * Blocking mode functions.
+*/
+
+ADI_UART_RESULT adi_uart_Write(
+                ADI_UART_HANDLE const    hDevice,
+                void           *const    pBuffer,
+                uint32_t        const    nBufSize,
+                bool            const    bDMA,
+                uint32_t                *pHwError
+);
+
+ADI_UART_RESULT adi_uart_Read(
+                ADI_UART_HANDLE const    hDevice,
+                void           *const    pBuffer,
+                uint32_t        const    nBufSize,
+                bool            const    bDMA,
+                uint32_t                *pHwError
+);
+
+
+/*
+ * Configuration interface functions.
+*/
+
+ADI_UART_RESULT adi_uart_EnableLoopBack(
+                ADI_UART_HANDLE const     hDevice,
+                bool            const     bEnable
+);
+
+ADI_UART_RESULT adi_uart_EnableAutobaud(
+                ADI_UART_HANDLE const     hDevice,
+                bool            const     bEnable,
+                bool            const     bAutobaudCallbackMode
+);
+
+ADI_UART_RESULT adi_uart_SetRxFifoTriggerLevel(
+                ADI_UART_CONST_HANDLE     const hDevice,
+                ADI_UART_TRIG_LEVEL       const eTriglevel
+);
+
+ADI_UART_RESULT adi_uart_EnableFifo(
+                ADI_UART_HANDLE const     hDevice,
+                bool            const     bEnable
+);
+
+ADI_UART_RESULT adi_uart_GetBaudRate(
+                ADI_UART_HANDLE const     hDevice,
+                uint32_t                 *pnBaudRate,
+                uint32_t                 *pAutobaudError
+);
+
+ADI_UART_RESULT adi_uart_ForceTxBreak(
+                ADI_UART_HANDLE const     hDevice,
+                bool            const     bEnable
+);
+
+ADI_UART_RESULT adi_uart_SetConfiguration(
+                ADI_UART_HANDLE   const  hDevice,
+                ADI_UART_PARITY   const  eParity,
+                ADI_UART_STOPBITS const  eStopBits,
+                ADI_UART_WORDLEN  const  eWordLength
+);
+
+ADI_UART_RESULT adi_uart_ConfigBaudRate(
+                ADI_UART_HANDLE   const hDevice,
+                uint16_t          const nDivC,
+                uint8_t           const nDivM,
+                uint16_t          const nDivN,
+                uint8_t           const nOSR  
+);
+
+/*
+ * Channel data control functions.
+*/
+
+ADI_UART_RESULT adi_uart_FlushTxFifo(
+                ADI_UART_CONST_HANDLE const  hDevice
+);
+
+ADI_UART_RESULT adi_uart_FlushRxFifo(
+                ADI_UART_CONST_HANDLE const  hDevice
+);
+
+ADI_UART_RESULT adi_uart_FlushRxChannel(
+                ADI_UART_CONST_HANDLE const  hDevice
+);
+
+
+ADI_UART_RESULT adi_uart_FlushTxChannel(
+                ADI_UART_CONST_HANDLE const  hDevice
+);
+
+ADI_UART_RESULT adi_uart_IsTxComplete(
+                ADI_UART_HANDLE const hDevice,
+                bool           *const pbComplete
+);
+
+/*
+ * Callback functions.
+*/
+
+ADI_UART_RESULT adi_uart_RegisterCallback(
+                ADI_UART_HANDLE const    hDevice,
+                const ADI_CALLBACK       pfCallback,
+                void           *const    pCBParam
+);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+/*@}*/
+
+#endif /* ADI_UART_H */
+
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/wdt/adi_wdt.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/wdt/adi_wdt.h
new file mode 100755
index 00000000000..834afee018d
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/wdt/adi_wdt.h
@@ -0,0 +1,77 @@
+/*! *****************************************************************************
+ * @file    adi_wdt.h
+ * @brief   WDT device driver public header
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_WDT_H
+#define ADI_WDT_H
+
+#include <adi_callback.h>
+
+/** @addtogroup WDT_Driver WDT Driver
+ *  @{
+ */
+
+/*! \enum ADI_WDT_RESULT Watchdog Device Error Codes. */
+typedef enum
+{
+    /*! Generic success. */
+    ADI_WDT_SUCCESS,
+    /*! Timer is locked. */
+    ADI_WDT_FAILURE_LOCKED
+} ADI_WDT_RESULT;
+
+
+/******************************************************************************
+ * PUBLIC API
+ * 1.) Eliminatable functions that may be optimized out by the linker
+ * 2.) Ordered by designed function call sequence
+ *****************************************************************************/
+
+ADI_WDT_RESULT adi_wdt_Enable  (bool const bEnable, ADI_CALLBACK const pfCallback);
+void           adi_wdt_Kick    (void);
+void           adi_wdt_GetCount(uint16_t * const pCurCount);
+
+
+/*! @} */
+
+#endif /* ADI_WDT_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/xint/adi_xint.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/xint/adi_xint.h
new file mode 100755
index 00000000000..15269983940
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/xint/adi_xint.h
@@ -0,0 +1,121 @@
+/*
+ *****************************************************************************
+   @file:    adi_xint.h
+   @brief:   External interrupt driver definitions and API
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#ifndef ADI_XINT_H
+#define ADI_XINT_H
+
+/*! \addtogroup XINT_Driver External Interrupt Driver
+ *  @{
+ */
+
+#ifdef __ICCARM__
+#pragma diag_default=Pm008
+#endif /* __ICCARM__ */
+
+#include <adi_callback.h>
+#include <adi_processor.h>
+
+#if !defined(__ADUCM302x__) && !defined(__ADUCM4x50__)
+#error "Unknown processor family"
+#endif
+
+
+/* C++ linkage */
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*! Amount of memory(in bytes) required by the External Interrupt device driver for its operation.
+ * This memory is completely owned by the driver till the end of the operation.
+ */
+#define ADI_XINT_MEMORY_SIZE        (48u)
+
+/*! External Interrupt Driver API function return codes */
+typedef enum
+{
+    ADI_XINT_SUCCESS = 0,                       /*!< API successfully returned. */
+    ADI_XINT_FAILURE,                           /*!< The API call failed. */
+    ADI_XINT_ALREADY_INITIALIZED,               /*!< External interrupt driver has already been initialized. */
+    ADI_XINT_NOT_INITIALIZED,                   /*!< External interrupt driver has not yet been initialized. */
+    ADI_XINT_NULL_PARAMETER,                    /*!< The given pointer is pointing to NULL. */
+    ADI_XINT_INVALID_MEMORY_SIZE,               /*!< The given memory is not sufficient to operate the driver. */   
+    ADI_XINT_INVALID_INTERRUPT                  /*!< Invalid interrupt number. */
+} ADI_XINT_RESULT;
+
+
+/*! External interrupt trigger condition enumerations */
+typedef enum {
+    ADI_XINT_IRQ_RISING_EDGE    = 0x0,          /*!< Trigger an interrupt when a rising edge is detected.    */
+    ADI_XINT_IRQ_FALLING_EDGE   = 0x1,          /*!< Trigger an interrupt when on a falling edge is detected.   */
+    ADI_XINT_IRQ_EITHER_EDGE    = 0x2,          /*!< Trigger an interrupt on either falling or rising edge is detected. */
+    ADI_XINT_IRQ_HIGH_LEVEL     = 0x3,          /*!< Trigger an interrupt on a logic level high is detected.     */
+    ADI_XINT_IRQ_LOW_LEVEL      = 0x4           /*!< Trigger an interrupt on a logic level low is detected.  */
+} ADI_XINT_IRQ_MODE;
+
+/*! External interrupts. */
+typedef enum {
+    ADI_XINT_EVENT_INT0         = 0x0,          /*!< Event for external interrupt-0   */
+    ADI_XINT_EVENT_INT1         = 0x1,          /*!< Event for external interrupt-1   */
+    ADI_XINT_EVENT_INT2         = 0x2,          /*!< Event for external interrupt-2   */
+    ADI_XINT_EVENT_INT3         = 0x3,          /*!< Event for external interrupt-3   */
+    ADI_XINT_EVENT_RESERVED     = 0x4,          /*!< Event is reserved.   */
+    ADI_XINT_EVENT_UART_RX      = 0x5,          /*!< Event for UART Rx activity   */
+    ADI_XINT_EVENT_MAX          = 0x6           /*!< Number of external interrupt events */
+} ADI_XINT_EVENT;
+
+
+/* External Interrupt API functions */
+ADI_XINT_RESULT  adi_xint_Init                  (void* const pMemory, uint32_t const MemorySize);
+ADI_XINT_RESULT  adi_xint_UnInit                (void);
+ADI_XINT_RESULT  adi_xint_EnableIRQ             (const ADI_XINT_EVENT eEvent, const ADI_XINT_IRQ_MODE eMode);
+ADI_XINT_RESULT  adi_xint_DisableIRQ            (const ADI_XINT_EVENT eEvent); 
+ADI_XINT_RESULT  adi_xint_RegisterCallback      (const ADI_XINT_EVENT eEvent, ADI_CALLBACK const pfCallback, void *const pCBParam );
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+
+#endif /* ADI_XINT_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/flash/adi_flash.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/flash/adi_flash.c
new file mode 100755
index 00000000000..2488596cb6c
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/flash/adi_flash.c
@@ -0,0 +1,1815 @@
+/*!
+ *****************************************************************************
+ @file:    adi_flash.c
+ @brief:   Flash Device Driver Implementation
+ @date:    $Date: 2016-06-30 08:06:37 -0400 (Thu, 30 Jun 2016) $
+ -----------------------------------------------------------------------------
+Copyright (c) 2012-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+/** @addtogroup Flash_Driver Flash Driver
+ *  @{
+ *
+ *  @brief <b>Flash (FEE) Driver</b>
+ *
+ *  @details
+ *
+ *  The flash controller provides access to the embedded flash memory. The embedded
+ *  flash has a 72-bit wide data bus providing for two 32-bit words of data and
+ *  one corresponding 8-bit ECC byte per access.
+ *
+ *  <b>Flash Driver Hardware Errors</b>
+ *
+ * Many of the Flash Controller APIs can result in hardware errors.  Each such API has a
+ * a hardware error parameter (pHwErrors), which is a pointer to an application-defined
+ * variable into which the failing API will store the failing hardware error status.\n
+ *
+ * APIs failing with hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED
+ * return code.\n
+ *
+ * Hardware error details may be decoded according to the flash controller status register
+ * ("STAT") bit-map, documented in the Hardware Reference Manual (HRM).  Flash hardware
+ * errors are separate and distinct from DMA errors, which have separate and distinct
+ * return codes (#ADI_FEE_ERR_DMA_BUS_FAULT, #ADI_FEE_ERR_DMA_INVALID_DESCR, and
+ * #ADI_FEE_ERR_DMA_UNKNOWN_ERROR).
+ *
+ *  <b>Flash Driver Static Configuration</b>
+ *
+ * A number of flash driver APIs manage configurations that very likely do not require
+ * dynamic (run-time) management.  Such cases are documented with the respective APIs.
+ * In all such cases, the user is encouraged to consider using the static configuration
+ * equivalents (provided in the adi_flash_config.h file) in lieu of the dynamic APIs.
+ * In so doing, linker elimination may reduce the resulting code image footprint
+ * (provided the API is not called).
+ *
+ * @note - The application must include drivers/flash/adi_flash.h to use this driver.
+ * @note - This driver also requires the DMA driver.  The application must include
+ *         the DMA driver sources to avoid link errors.
+ */
+
+/*========  I N C L U D E  ========*/
+
+ /*! \cond PRIVATE */
+#include <adi_processor.h>
+#include <assert.h>
+#include <string.h>     /* for "memset" */
+/*! \endcond */
+
+#include <drivers/flash/adi_flash.h>
+
+/*=============  M I S R A   =============*/
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
+*   This isn't a header as such.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+*
+* Pm050 (rule 14.2): a null statement shall only occur on a line by itself
+*   Needed for null expansion of ADI_INSTALL_HANDLER and others.
+*
+* Pm088 (rule 17.4): pointer arithmetic should not be used.
+*   Relying on pointer arithmetic for buffer handling.
+*
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   Required for MMR accesses, determining pointer alignment, and a callback argument.
+*
+* Pm026 (rule 12.4): the right hand operand of an && or || operator shall not contain side effects
+*   Side effects being mis-reported due to added volatile storage class.
+*/
+#pragma diag_suppress=Pm123,Pm073,Pm143,Pm050,Pm088,Pm140,Pm026
+#endif /* __ICCARM__ */
+
+/* pull in internal data structures */
+#include "adi_flash_data.c"
+
+/*========  D E F I N E S   ========*/
+
+/*! \cond PRIVATE */
+
+#ifdef ADI_DEBUG
+#define ASSERT(X)   assert(X)
+#else
+#define ASSERT(X)
+#endif
+
+/* internal utility macros */
+#define CLR_BITS(REG, BITS) ((REG) &= ~(BITS))
+#define SET_BITS(REG, BITS) ((REG) |= (BITS))
+
+#ifdef ADI_DEBUG
+/* Validate Device Handle */
+static bool IsDeviceHandle (ADI_FEE_HANDLE const hDevice);
+static bool IsDeviceHandle (ADI_FEE_HANDLE const hDevice)
+{
+    if ( (fee_device_info[0].hDevice == (hDevice)) && ((hDevice)->pDevInfo->hDevice != NULL) ) {
+        return true;
+    } else {
+        return false;
+    }
+}
+#endif
+
+/* Wait for specified flash status to be clear */
+static void BusyWait (ADI_FEE_HANDLE const hDevice, uint32_t const status);
+static void BusyWait (ADI_FEE_HANDLE const hDevice, uint32_t const status)
+{
+    while ((hDevice->pDev->STAT & status) != 0u) {}
+}
+
+/* Internal DMA Callback for receiving DMA faults from common DMA error handler */
+static void dmaCallback(void *pCBParam, uint32_t Event, void *pArg);
+static void dmaCallback(void *pCBParam, uint32_t Event, void *pArg) {
+
+    /* recover the device handle */
+    ADI_FEE_HANDLE hDevice = (ADI_FEE_HANDLE)pCBParam;
+
+    /* save the DMA error */
+    switch (Event) {
+        case ADI_DMA_EVENT_ERR_BUS:
+            hDevice->dmaError = ADI_FEE_ERR_DMA_BUS_FAULT;
+            break;
+        case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR:
+            hDevice->dmaError = ADI_FEE_ERR_DMA_INVALID_DESCR;
+            break;
+        default:
+            hDevice->dmaError = ADI_FEE_ERR_DMA_UNKNOWN_ERROR;
+            break;
+    }
+
+    /* transfer is toast... post and callback any waiters */
+
+    SEM_POST(hDevice);
+
+    if (0u != hDevice->pfCallback) {
+        hDevice->pfCallback (hDevice->pCBParam, (uint32_t)hDevice->dmaError, (void*)NULL);
+    }
+}
+
+/*! \endcond */
+
+
+/*========  C O D E  ========*/
+/*
+ * API Implementation
+ */
+
+
+/**
+ * @brief    Open the flash controller.
+ *
+ * @param [in]     nDeviceNum    The zero-based device instance number of flash controller to be opened.
+ * @param [in]     pMemory       Application supplied memory space for use by the driver.
+ * @param [in]     nMemorySize   Size of the application supplied memory (in bytes).
+ * @param [in,out] phDevice      The caller's device handle pointer for storing the initialized
+ *                               device instance data pointer.
+ *
+ * @return  Status
+ *          - #ADI_FEE_SUCCESS                      The device is opened successfully.
+ *          - #ADI_FEE_ERR_BAD_DEVICE_NUM       [D] The device number passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Some pointer(s) passed to the function is NULL.
+ *          - #ADI_FEE_ERR_ALREADY_INITIALIZED  [D] The device is already initialized and hence cannot be opened.
+ *          - #ADI_FEE_ERR_INSUFFICIENT_MEM     [D] The memory passed to the driver is insufficient.
+ *          - #ADI_FEE_ERR_DMA_REGISTER             The required DMA common error handler registration failed.
+ *          - #ADI_FEE_ERR_SEMAPHORE_FAILED         The semaphore create operation failed.
+ *
+ * Initialize an instance of the flash device driver using default user configuration settings
+ * (from adi_flash_config.h) and allocate the device for use.
+ *
+ * No other flash APIs may be called until the device open function is called.  The returned
+ * device handle is required to be passed to all subsequent flash API calls to identify the
+ * physical device instance in use.  The user device handle (pointed to by phDevice) is set
+ * to NULL on failure.
+ *
+ * @note Currently, only a singular flash physical device instance (device ID "0") exists.
+ *
+ * @sa      adi_fee_Close().
+ */
+ADI_FEE_RESULT adi_fee_Open (uint32_t const nDeviceNum, void* const pMemory, uint32_t const nMemorySize, ADI_FEE_HANDLE* const phDevice)
+{
+    ADI_FEE_HANDLE hDevice = NULL;  /* initially */
+
+#ifdef ADI_DEBUG
+    if (nDeviceNum >= ADI_FEE_NUM_INSTANCES) {
+        return ADI_FEE_ERR_BAD_DEVICE_NUM;
+    }
+
+    /* verify device is not already open */
+    if (fee_device_info[nDeviceNum].hDevice != NULL) {
+        return ADI_FEE_ERR_ALREADY_INITIALIZED;
+    }
+
+    if ((pMemory == NULL) || (phDevice == NULL)) {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+
+    if (nMemorySize < ADI_FEE_MEMORY_SIZE) {
+        return ADI_FEE_ERR_INSUFFICIENT_MEM;
+    }
+
+    assert (ADI_FEE_MEMORY_SIZE == sizeof(ADI_FEE_DEV_DATA_TYPE));
+#endif
+
+    /* store a bad handle in case of failure */
+    *phDevice = NULL;
+
+    /* Link user memory (handle) into ADI_FEE_DEVICE_INFO data structure.
+     *
+     *       ADI_FEE_DEVICE_INFO  <==>   ADI_FEE_HANDLE
+     */
+    fee_device_info[nDeviceNum].hDevice = (ADI_FEE_DEV_DATA_TYPE *)pMemory;
+
+    /* Clear the ADI_FEE_HANDLE memory. This also sets all bool
+     * structure members to false so we do not need to waste cycles
+     * setting these explicitly (e.g. hDevice->bUseDma = false)
+     */
+    memset(pMemory, 0, nMemorySize);
+
+    /* initialize local device handle and link up device info for this device instance */
+    hDevice = (ADI_FEE_HANDLE)pMemory;
+    hDevice->pDevInfo = &fee_device_info[nDeviceNum];
+
+    /* Although the ADI_FEE_DEVICE_INFO struct has the physical device pointer
+     * for this instance, copying it to the ADI_FEE_HANDLE struct (in user memory)
+     * will minimize the runtime footprint and cycle count when accessing the FEE
+     * registers.
+     */
+    hDevice->pDev = fee_device_info[nDeviceNum].pDev;
+
+    /* store a pointer to user's static configuration settings for this device instance */
+    hDevice->pDevInfo->pConfig = (ADI_FEE_CONFIG*)&gConfigInfo[nDeviceNum];
+
+    /* create the semaphore */
+    SEM_CREATE(hDevice, "fee_sem", ADI_FEE_ERR_SEMAPHORE_FAILED);
+
+    /* grant keyed access */
+    hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
+
+        /* apply the static initializers */
+        hDevice->pDev->IEN         = hDevice->pDevInfo->pConfig->eccIrqEnables;
+        hDevice->pDev->TIME_PARAM0 = hDevice->pDevInfo->pConfig->param0;
+        hDevice->pDev->TIME_PARAM1 = hDevice->pDevInfo->pConfig->param1;
+        hDevice->pDev->ABORT_EN_LO = hDevice->pDevInfo->pConfig->abortEnableLo;
+        hDevice->pDev->ABORT_EN_HI = hDevice->pDevInfo->pConfig->abortEnableHi;
+        hDevice->pDev->ECC_CFG     = hDevice->pDevInfo->pConfig->eccConfig;
+
+        /* clear auto-increment and dma enable bits */
+        CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN));
+
+    /* close keyed access */
+    hDevice->pDev->KEY = 0u;
+
+    /* store device handle into user handle */
+    *phDevice = (ADI_FEE_HANDLE)hDevice;
+
+    /* initialize DMA service */
+    adi_dma_Init();
+
+    if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pDevInfo->dmaChanNum, dmaCallback, (void*)hDevice)) {
+        /* uninitialize flash driver and fail */
+        adi_fee_Close(hDevice);
+        return  ADI_FEE_ERR_DMA_REGISTER;
+    }
+
+    /* NVIC enables */
+    NVIC_EnableIRQ(hDevice->pDevInfo->pioIrqNum);
+    NVIC_EnableIRQ(hDevice->pDevInfo->dmaIrqNum);
+
+    /* return success */
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Close the flash controller.
+ *
+ * @param [in] hDevice   The handle to the flash controller device
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The device is closed successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_SEMAPHORE_FAILED         The semaphore delete operation failed.
+ *
+ * Uninitialize and release an allocated flash device, and memory associated with it
+ * for other use.
+ *
+ * @note The user memory is released from use by the flash driver, but is not freed.
+ *
+ * @sa  adi_fee_Open().
+ */
+ADI_FEE_RESULT adi_fee_Close (ADI_FEE_HANDLE const hDevice)
+{
+    uint32_t dev;
+
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+#endif
+
+    /* Destroy the semaphore */
+    SEM_DELETE(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED);
+
+    /* Remove the device handle from the list of possible device instances */
+    for (dev = 0u; dev < ADI_FEE_NUM_INSTANCES; dev++)
+    {
+        if (fee_device_info[dev].hDevice == hDevice)
+        {
+            fee_device_info[dev].hDevice = NULL;
+            break;
+        }
+    }
+
+    /* NVIC disables */
+    NVIC_DisableIRQ(hDevice->pDevInfo->pioIrqNum);
+    NVIC_DisableIRQ(hDevice->pDevInfo->dmaIrqNum);
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief   Register an application-defined callback function.
+ *
+ * @param [in]  hDevice     The handle to the flash controller device.
+ * @param [in]  pfCallback  A pointer to an application-supplied calllback function
+ *                          which is called to notify the application of device-related
+ *                          events.  A value of NULL disables driver callbacks.
+ * @param [in]  pCBParam    An application-supplied callback parameter which will be passed
+ *                          back to the callback function.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The callback is registered successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] A flash write operation is in progress and
+ *                                                  the callback registration is ignored.
+ *
+ * Links the user-provided callback function into the #adi_fee_SubmitBuffer() API such that
+ * rather than polling for buffer completion (with #adi_fee_IsBufferAvailable()) and eventually
+ * reacquiring the buffer (with #adi_fee_GetBuffer()), the user can simply register a callback
+ * function that will be called upon buffer completion with no further action needed.\n
+ *
+ * Error conditions are also passed to the callback, including DMA errors if DMA is active.  Make sure
+ * to always check the event value passed to the callback, just as the various API return codes should
+ * always be checked.\n
+ *
+ * However, callbacks are always made in context of an interrupt, so applications are strongly encouraged
+ * to exit the callback as quickly as possible so normal interrupt processing is disrupted as little as
+ * possible.  This is also an argument for not using callbacks at at all.
+ *
+ * @note When using callbacks to reacquire buffers, DO NOT use the #adi_fee_GetBuffer() API.  The two
+ * methods are mutually exclusive.
+ *
+ * @sa adi_fee_SubmitBuffer().
+ * @sa adi_fee_IsBufferAvailable().
+ * @sa adi_fee_GetBuffer().
+ */
+ADI_FEE_RESULT adi_fee_RegisterCallback (ADI_FEE_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void* const pCBParam)
+{
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+#endif
+
+    /* Set the callback function and param in the device */
+    hDevice->pfCallback = pfCallback;
+    hDevice->pCBParam   = pCBParam;
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Erase the given range of (2kB) page(s) within the flash user space memory.  This is a blocking call.
+ *
+ * @param [in]     hDevice         The handle to the flash controller device.
+ * @param [in]     nPageNumStart   Start page number.
+ * @param [in]     nPageNumEnd     End page number.
+ * @param [in,out] pHwErrors       Pointer to user location into which any flash hardware errors are reported.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The page(s) is(are) cleared successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] The page(s) number(s) is(are) incorrect.
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is in progress.
+ *          - #ADI_FEE_ERR_HW_ERROR_DETECTED        An internal flash controller hardware error was detected.
+ *          - #ADI_FEE_ERR_SEMAPHORE_FAILED         The semaphore pend operation failed.
+ *
+ * Erases entire page(s).  Callers are expected to save/restore any partial page data prior
+ * to erasure, as needed.  Translate literal flash addresses into flash start and end page
+ * numbers with #adi_fee_GetPageNumber().
+ *
+ * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code.
+ * Flash hardware error details are written to the location pointed to by the pHwErrors parameter.
+ * Hardware error details may be decoded according to the flash controller status register ("STAT")
+ * bit-map, documented in the Hardware Reference Manual (HRM).
+ *
+ * @sa adi_fee_GetPageNumber().
+ * @sa adi_fee_MassErase().
+ */
+ADI_FEE_RESULT adi_fee_PageErase (ADI_FEE_HANDLE const hDevice, uint32_t const nPageNumStart, uint32_t const nPageNumEnd, uint32_t* const pHwErrors)
+
+{
+    ADI_FEE_RESULT result = ADI_FEE_SUCCESS;
+
+    uint32_t page;
+
+#ifdef ADI_DEBUG
+
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+
+    uint32_t nRelAddrStart = (nPageNumStart << FEE_PAGE_SHIFT);
+    uint32_t nRelAddrStop  = (nPageNumEnd   << FEE_PAGE_SHIFT);
+
+    if (   (nPageNumStart > nPageNumEnd)
+        || (nRelAddrStart >= FEE_FLASH_SIZE)
+        || (nRelAddrStop  >= FEE_FLASH_SIZE))
+    {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif /* defined (ADI_DEBUG) */
+
+    for (page = nPageNumStart; page <= nPageNumEnd; page++)
+    {
+        /* Wait until not busy */
+        BusyWait(hDevice, (BITM_FLCC_STAT_CMDBUSY | BITM_FLCC_STAT_WRCLOSE));
+
+        /* Set the page address */
+        hDevice->pDev->PAGE_ADDR0 = (page << FEE_PAGE_SHIFT);
+
+        /* Issue a page erase command */
+        result = SendCommand (hDevice, ENUM_FLCC_CMD_ERASEPAGE);
+
+        /* block on command */
+        SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED);
+
+        if (result != ADI_FEE_SUCCESS) {
+            break;
+        }
+    }
+
+    /* copy out any hardware errors... */
+    *pHwErrors = hDevice->feeError;
+    if (0u != hDevice->feeError) {
+        /* return the HW error return code */
+        return ADI_FEE_ERR_HW_ERROR_DETECTED;
+    }
+
+    return result;
+}
+
+
+/**
+ * @brief    Erase the entire flash user space memory.  This is a blocking call.
+ *
+ * @param [in]     hDevice    The handle to the flash controller device.
+ * @param [in,out] pHwErrors  Pointer to user location into which any flash hardware errors are reported.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The flash is cleared successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is in progress.
+ *          - #ADI_FEE_ERR_HW_ERROR_DETECTED        An internal flash controller hardware error was detected.
+ *          - #ADI_FEE_ERR_SEMAPHORE_FAILED         The semaphore pend operation failed.
+ *
+ * @note Do not call mass erase on or from code that is running from flash.  Doing so will leave
+ * an indeterminate machine state.
+ *
+ * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code.
+ * Flash hardware error details are written to the location pointed to by the pHwErrors parameter.
+ * Hardware error details may be decoded according to the flash controller status register ("STAT")
+ * bit-map, documented in the Hardware Reference Manual (HRM).
+ *
+ * @sa adi_fee_PageErase().
+ */
+ADI_FEE_RESULT adi_fee_MassErase (ADI_FEE_HANDLE const hDevice, uint32_t* const pHwErrors)
+{
+    ADI_FEE_RESULT result = ADI_FEE_SUCCESS;
+
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+#endif
+
+    /* Call the mass erase command */
+    result = SendCommand (hDevice, ENUM_FLCC_CMD_MASSERASE);
+
+    /* block on command */
+    SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED);
+
+    /* copy out any hardware errors... */
+    *pHwErrors = hDevice->feeError;
+    if (0u != hDevice->feeError) {
+        /* return the HW error return code */
+        return ADI_FEE_ERR_HW_ERROR_DETECTED;
+    }
+
+    return result;
+}
+
+
+/**
+ * @brief     Perform a blocking flash data write operation.
+ *
+ * @param [in]  hDevice         The handle to the flash controller device.
+ * @param [in]  pTransaction    Pointer to a user-defined control block describing the data to be transferred, containing:
+ *                                - pWriteAddr; Pointer to a 64-bit-aligned destination address in flash.
+ *                                - pWriteData; Pointer to a 32-bit-aligned source data buffer in user memory.
+ *                                - nSize;      Number of bytes to write (must be an integral multiple of 8).
+ *                                - bUseDma;    Flag controlling use of DMA to perform the write.
+ * @param [in,out] pHwErrors    Pointer to user location into which any flash hardware errors are reported.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The buffer is successfully written to the flash.
+ *          - #ADI_FEE_ERR_ALIGNMENT            [D] The flash write source data pointer is misaligned.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Buffer size is not a multiple of 8-bytes (or too large for DMA).
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress.
+ *          - #ADI_FEE_ERR_BUFFER_ERR               Error occurred in processing the buffer.
+ *          - #ADI_FEE_ERR_DEVICE_BUSY              The flash controller is busy.
+ *          - #ADI_FEE_ERR_DMA_BUS_FAULT            A runtime DMA bus fault was detected.
+ *          - #ADI_FEE_ERR_DMA_INVALID_DESCR        A runtime DMA invalid descriptor was detected.
+ *          - #ADI_FEE_ERR_DMA_UNKNOWN_ERROR        An unknown runtime DMA error was detected.
+ *          - #ADI_FEE_ERR_HW_ERROR_DETECTED        An internal flash controller hardware error was detected.
+ *          - #ADI_FEE_ERR_NO_DATA_TO_TRANSFER      Transfer ran out of write data unexpectedly.
+ *          - #ADI_FEE_ERR_SEMAPHORE_FAILED         The semaphore pend operation failed.
+ *
+ * Perform a blocking flash data write operation.  This API does not return until the write operation is completed.
+ *
+ * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code.
+ * Flash hardware error details are written to the location pointed to by the pHwErrors parameter.
+ * Hardware error details may be decoded according to the flash controller status register ("STAT")
+ * bit-map, documented in the Hardware Reference Manual (HRM).  Flash hardware errors are separate
+ * and distinct from DMA errors, which have separate and distinct return codes, as described above.
+ */
+ADI_FEE_RESULT adi_fee_Write (ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION* const pTransaction, uint32_t* const pHwErrors)
+{
+    ADI_FEE_RESULT result = ADI_FEE_SUCCESS;
+
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+
+	/* check address is 64-bit aligned and data pointer is 32-bit aligned */
+    if ( (((uint32_t)pTransaction->pWriteAddr & 0x7u) != 0u) || ((((uint32_t)pTransaction->pWriteData) & 0x3u) != 0u) )
+    {
+        return ADI_FEE_ERR_ALIGNMENT;
+    }
+
+	/* make sure size is a multiple of 8 */
+    if ((pTransaction->nSize & 0x7u) != 0u) {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+
+    if (true == pTransaction->bUseDma) {
+        /* check for max DMA units (32-bit chunks, i.e., 4 bytes at a whack) */
+        if (DMA_TRANSFER_LIMIT < (pTransaction->nSize / sizeof(uint32_t))) {
+            return ADI_FEE_ERR_INVALID_PARAM;
+        }
+    }
+#endif
+
+    /* reset submit/get safeguard flag */
+    hDevice->bSubmitCalled = false;
+
+    /* Fill in the transfer params */
+    hDevice->pNextWriteAddress = pTransaction->pWriteAddr;
+    hDevice->pNextReadAddress  = pTransaction->pWriteData;
+    hDevice->nRemainingBytes   = pTransaction->nSize;
+    hDevice->bUseDma           = pTransaction->bUseDma;
+
+    /* Initiate a transfer */
+    result = InitiateTransfer (hDevice);
+
+    /* Wait for the completed transfer */
+    SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED);
+
+    /* issue any flash DMA error status codes... */
+    if (0u != hDevice->dmaError) {
+        return hDevice->dmaError;
+    }
+
+    /* copy out any hardware errors... */
+    *pHwErrors = hDevice->feeError;
+    if (0u != hDevice->feeError) {
+        /* return the HW error return code */
+        return ADI_FEE_ERR_HW_ERROR_DETECTED;
+    }
+
+    /* Check for errors in buffer write */
+    if (hDevice->nRemainingBytes != 0u) {
+        return ADI_FEE_ERR_BUFFER_ERR;
+    }
+
+    return result;
+}
+
+
+/**
+ * @brief     Submit a non-blocking flash data write operation for background processing.
+ *
+ * @param [in]  hDevice         The handle to the flash controller device.
+ * @param [in]  pTransaction    Pointer to a user-defined control block describing the data to be transferred, containing:
+ *                                - pWriteAddr; Pointer to a 64-bit-aligned destination address in flash.
+ *                                - pWriteData; Pointer to a 32-bit-aligned source data buffer in user memory.
+ *                                - nSize;      Number of bytes to write (must be an integral multiple of 8).
+ *                                - bUseDma;    Flag controlling use of DMA to perform the write.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The buffer is successfully written to the flash.
+ *          - #ADI_FEE_ERR_ALIGNMENT            [D] The flash write source data pointer is misaligned.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Buffer size is not a multiple of 8-bytes (or too large for DMA).
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress.
+ *          - #ADI_FEE_ERR_BUFFER_ERR               Error occurred in processing the buffer.
+ *          - #ADI_FEE_ERR_DEVICE_BUSY              The flash controller is busy.
+ *          - #ADI_FEE_ERR_NO_DATA_TO_TRANSFER      Transfer ran out of write data unexpectedly.
+ *
+ * Submit a flash data write transaction. This is a non-blocking function which returns immediately.
+ * The application may either: poll for transaction completion through the non-blocking #adi_fee_IsBufferAvailable()
+ * API, and/or await transaction completion through the blocking mode #adi_fee_GetBuffer() API.  If an application
+ * callback has been registered, the application is advised of completion status through the callback.
+ *
+ * @note If using callback mode, DO NOT USE the #adi_fee_GetBuffer() API, which are mutually exclusive protocols.
+ *
+ * @sa adi_fee_IsBufferAvailable().
+ * @sa adi_fee_GetBuffer().
+ */
+ADI_FEE_RESULT adi_fee_SubmitBuffer (ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION* const pTransaction)
+{
+    ADI_FEE_RESULT result = ADI_FEE_SUCCESS;
+
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+
+	/* check address is 64-bit aligned and data pointer is 32-bit aligned */
+    if ( (((uint32_t)pTransaction->pWriteAddr & 0x7u) != 0u) || ((((uint32_t)pTransaction->pWriteData) & 0x3u) != 0u) )
+    {
+        return ADI_FEE_ERR_ALIGNMENT;
+    }
+
+	/* make sure size is a multiple of 8 */
+    if ((pTransaction->nSize & 0x7u) != 0u) {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+
+    if (true == pTransaction->bUseDma) {
+        /* check for max DMA units (32-bit channel width means 4 bytes at a whack) */
+        if (DMA_TRANSFER_LIMIT < (pTransaction->nSize / sizeof(uint32_t))) {
+            return ADI_FEE_ERR_INVALID_PARAM;
+        }
+    }
+#endif
+
+    /* set submit/get safeguard flag */
+    hDevice->bSubmitCalled = true;
+
+    /* Fill in the transfer params */
+    hDevice->pNextWriteAddress = pTransaction->pWriteAddr;
+    hDevice->pNextReadAddress  = pTransaction->pWriteData;
+    hDevice->nRemainingBytes   = pTransaction->nSize;
+    hDevice->bUseDma           = pTransaction->bUseDma;
+
+    /* initiate a transfer */
+    result = InitiateTransfer (hDevice);
+
+    /* no pend here... just return */
+
+    return result;
+}
+
+
+/**
+ * @brief   Non-blocking check if a write transaction complete.
+ *
+ * @param [in]      hDevice           The handle to the flash controller device.
+ * @param [in,out]  pbCompletionState True if transfer is complete, false if not.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The status of buffer is returned successfully.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Pointer passed is NULL.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY   No matching buffer submit call found.
+ *
+ * Check if a non-blocking write transaction that was submitted via adi_fee_SubmitBuffer() is complete.
+ *
+ * @sa adi_fee_SubmitBuffer().
+ * @sa adi_fee_GetBuffer().
+ */
+ADI_FEE_RESULT adi_fee_IsBufferAvailable (ADI_FEE_HANDLE const hDevice, bool* const pbCompletionState)
+
+{
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    if (pbCompletionState == NULL) {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif
+
+    /* fail if not a submit-based transaction */
+    if (false == hDevice->bSubmitCalled) {
+        return ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY;
+    }
+
+    if (true == hDevice->bTransferInProgress) {
+        *pbCompletionState = false;
+    } else {
+        *pbCompletionState = true;
+    }
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Blocking mode call to await transaction completion.
+ *
+ * @param [in]     hDevice    The handle to the flash controller device.
+ * @param [in,out] pHwErrors  Pointer to user location into which any flash hardware errors are reported.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The buffer is successfully written to the flash.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_BUFFER_ERR               Error occurred in processing the buffer.
+ *          - #ADI_FEE_ERR_DMA_BUS_FAULT            A runtime DMA bus fault was detected.
+ *          - #ADI_FEE_ERR_DMA_INVALID_DESCR        A runtime DMA invalid descriptor was detected.
+ *          - #ADI_FEE_ERR_DMA_UNKNOWN_ERROR        An unknown runtime DMA error was detected.
+ *          - #ADI_FEE_ERR_HW_ERROR_DETECTED        An internal flash controller hardware error was detected.
+ *          - #ADI_FEE_ERR_SEMAPHORE_FAILED         The semaphore pend operation failed.
+ *          - #ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY   No matching buffer submit call found.
+ *
+ * This function blocks until a previously-submitted flash write operation has completed.
+ *
+ * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code.
+ * Flash hardware error details are written to the location pointed to by the pHwErrors parameter.
+ * Hardware error details may be decoded according to the flash controller status register ("STAT")
+ * bit-map, documented in the Hardware Reference Manual (HRM).
+ *
+ * @sa adi_fee_SubmitBuffer().
+ * @sa adi_fee_IsBufferAvailable().
+ */
+ADI_FEE_RESULT adi_fee_GetBuffer (ADI_FEE_HANDLE const hDevice, uint32_t* const pHwErrors)
+
+{
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+#endif
+
+    /* fail if not a submit-based transaction */
+    if (false == hDevice->bSubmitCalled) {
+        return ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY;
+    }
+
+    /* Pend for the semaphore */
+    SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED);
+
+    /* issue any flash DMA error status codes... */
+    if (0u != hDevice->dmaError) {
+        return hDevice->dmaError;
+    }
+
+    /* copy out any hardware errors... */
+    *pHwErrors = hDevice->feeError;
+    if (0u != hDevice->feeError) {
+        /* return the HW error return code */
+        return ADI_FEE_ERR_HW_ERROR_DETECTED;
+    }
+
+    /* Check for errors in buffer write or transfer still in progress */
+    if ((0u != hDevice->nRemainingBytes) || (true == hDevice->bTransferInProgress)) {
+        return ADI_FEE_ERR_BUFFER_ERR;
+    }
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief   Get the (2kB) page number within which a flash address resides.
+ *
+ * @param [in]      hDevice     The handle to the flash controller device.
+ * @param [in]      nAddress    The flash address for which the page number is required.
+ * @param [in,out]  pnPageNum   Pointer to a variable into which the page number corresponding
+ *                              to the provided flash address is written.
+ *
+ * @return  Status
+ *          - #ADI_FEE_SUCCESS                      The page number is returned successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Parameter(s) are invalid.
+ *
+ * Translates a literal flash address into a page number for use with various page-based flash operations.
+ *
+ * @sa adi_fee_PageErase().
+ * @sa adi_fee_VerifySignature().
+ * @sa adi_fee_ConfigECC().
+ * @sa adi_fee_GetBlockNumber().
+ *
+ */
+ADI_FEE_RESULT adi_fee_GetPageNumber (ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t* const pnPageNum)
+{
+#ifdef ADI_DEBUG
+
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    if (   (pnPageNum == NULL)
+        || (nAddress >= FEE_FLASH_SIZE))
+    {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif
+
+    /* Set the page number for the given flash address */
+    *pnPageNum = (nAddress >> FEE_PAGE_SHIFT);
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Get the (16kB) block number within which a flash address resides.
+ *
+ * @param [in]      hDevice     The handle to the flash controller device.
+ * @param [in]      nAddress    The flash address for which the block number is required.
+ * @param [in,out]  pnBlockNum  Pointer to a variable into which the block number corresponding
+ *                              to the provided flash address is written.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The block number is returned successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Parameter(s) are invalid.
+ *
+ * Translates a literal flash address into a block number for use with setting flash write protection on a block.
+ *
+ * @sa adi_fee_WriteProtectBlock().
+ * @sa adi_fee_GetPageNumber().
+ */
+ADI_FEE_RESULT adi_fee_GetBlockNumber (ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t* const pnBlockNum)
+{
+#ifdef ADI_DEBUG
+
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    if (   (pnBlockNum == NULL)
+        || (nAddress >= FEE_FLASH_SIZE))
+    {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif
+
+    /* Set the block number */
+    *pnBlockNum = (nAddress >> FEE_BLOCK_SHIFT);
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Generate the CRC signature for a range of flash data page(s).  This is a blocking call.
+ *
+ * @param [in]     hDevice      The handle to the flash controller device.
+ * @param [in]     nStartPage   The lower page number of the signature range.
+ * @param [in]     nEndPage     The upper page number of the signature range.
+ * @param [in,out] pSigResult   Pointer to a variable into which the computed signature is stored.
+ * @param [in,out] pHwErrors    Pointer to user location into which any flash hardware errors are reported.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The signature is verified successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM       [D] The page(s) number(s) is(are) incorrect.
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] A flash write operation is in progress.
+ *          - #ADI_FEE_ERR_HW_ERROR_DETECTED        An internal flash controller hardware error was detected.
+ *          - #ADI_FEE_ERR_SEMAPHORE_FAILED         The semaphore pend operation failed.
+ *
+ * Compute and return a CRC over a range of contiguous whole flash memory pages(s).  The computed CRC
+ * signature may subsequently be written into the most-significant word of the region over which the
+ * signature was calculated.  This is done in context of enabling bootloader enforcement of CRC signature
+ * verification during system startup.  See HRM for signature storage programming requirements and
+ * bootloader operation.
+ *
+ * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code.
+ * Flash hardware error details are written to the location pointed to by the pHwErrors parameter.
+ * Hardware error details may be decoded according to the flash controller status register ("STAT")
+ * bit-map, documented in the Hardware Reference Manual (HRM).
+ *
+ * @sa adi_fee_GetPageNumber().
+ */
+ADI_FEE_RESULT adi_fee_VerifySignature (ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, uint32_t const nEndPage, uint32_t* const pSigResult, uint32_t* const pHwErrors)
+
+{
+    ADI_FEE_RESULT result = ADI_FEE_SUCCESS;
+
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+
+    if (   (pSigResult == NULL)
+        || (nStartPage >  nEndPage)
+        || (nStartPage >= FEE_MAX_NUM_PAGES)
+        || (nEndPage >= FEE_MAX_NUM_PAGES)
+        )
+    {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif
+
+    /* Wait until not busy */
+    BusyWait (hDevice, (BITM_FLCC_STAT_CMDBUSY | BITM_FLCC_STAT_WRCLOSE));
+
+    /* Set the lower and upper page */
+    hDevice->pDev->PAGE_ADDR0 = nStartPage << FEE_PAGE_SHIFT;
+    hDevice->pDev->PAGE_ADDR1 = nEndPage << FEE_PAGE_SHIFT;
+
+    /* Do a SIGN command */
+    result = SendCommand(hDevice, ENUM_FLCC_CMD_SIGN);
+
+    /* block on command */
+    SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED);
+
+    /* Return the signature to the application */
+    if (ADI_FEE_SUCCESS == result) {
+        *pSigResult = hDevice->pDev->SIGNATURE;
+    } else {
+        *pSigResult = 0u;
+    }
+
+    /* copy out any hardware errors... */
+    *pHwErrors = hDevice->feeError;
+    if (0u != hDevice->feeError) {
+        /* return the HW error return code */
+        return ADI_FEE_ERR_HW_ERROR_DETECTED;
+    }
+
+    return result;
+}
+
+
+/**
+ * @brief    Set write protection on an (16kB) block.
+ *
+ * @param [in]  hDevice     The handle to the flash controller device.
+ * @param [in]  nBlockNum   The block number.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The block is write protected successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Block number is invalid.
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress.
+ *
+ * Assert memory write-protection for specified block.  Note that only entire blocks are protectable,
+ * with each block spanning 8 pages.
+ *
+ * @note Blocks may only be write-protected during user run-time code.  Unprotecting is only
+ * possible with a power-on-reset or a mass erase; write-protection is not otherwise clearable.
+ *
+ * @warning Flash-based code that write-protects blocks will cause the write-protection (and data at
+ * time of write-protect assertion) to apparently not clear... even after a mass erase or power-on-reset.
+ * This apparently "stuck" write-protection results from the flash-based write-protect code running
+ * after reset (as usual), but still prior to the debugger halting the target through the debug
+ * interrupt.  The debugger target halt occurs WELL AFTER the flash code has already run, thereby
+ * relocking the block and making it appear the write-protection was never reset.  This can be difficult
+ * Catch-22 situation to recover from, requiring repeated hardware resets and reflashing new code that
+ * does not assert the write-protection.
+ *
+ * @sa adi_fee_GetBlockNumber().
+ */
+ADI_FEE_RESULT adi_fee_WriteProtectBlock (ADI_FEE_HANDLE const hDevice, uint32_t const nBlockNum)
+
+{
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+
+    if (nBlockNum > FEE_MAX_NUM_BLOCKS) {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif
+
+    /* Set the write protection (by clearing the bit) for the given block */
+    hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
+    CLR_BITS (hDevice->pDev->WRPROT, 1u << nBlockNum);
+    hDevice->pDev->KEY = 0u;
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Sleep or awake the flash controller.  This is a blocking call.
+ *
+ * @param [in]  hDevice   The handle to the flash controller device.
+ * @param [in]  bSleep    'true' to enable to sleep the flash device
+ *                        and 'false' to wake up the device.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The flash controller is moved to sleep/wake
+ *                                                  up sate successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress.
+ *          - #ADI_FEE_ERR_SEMAPHORE_FAILED         The semaphore pend operation failed.
+ *
+ * Places the flash controller into a low-power sleep mode - see details in Hardware Reference Manual (HRM).
+ * Default wakeup time is approximately 5us, and is configurable with static configuration parameter
+ * ADI_FEE_CFG_PARAM1_TWK in adi_flash_config.h file.
+ */
+ADI_FEE_RESULT adi_fee_Sleep (ADI_FEE_HANDLE const hDevice, bool const bSleep)
+{
+    ADI_FEE_RESULT result = ADI_FEE_SUCCESS;
+
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+#endif
+
+    /* TODO: Check that IDLE can take the controller
+     *       out of sleep
+     */
+
+    if (true == bSleep) {
+        result = SendCommand (hDevice, ENUM_FLCC_CMD_SLEEP);
+    } else {
+        result = SendCommand (hDevice, ENUM_FLCC_CMD_IDLE);
+    }
+
+    /* block on command */
+    SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED);
+
+    return result;
+}
+
+
+/**
+ * @brief    Forcefully ABORT an ongoing flash operation.  This is a blocking call.
+ *
+ * @param [in]  hDevice   The handle to the flash controller device.
+ *
+ * @return   Statuus
+ *          - #ADI_FEE_SUCCESS                      The command is successfully aborted.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid
+ *          - #ADI_FEE_ERR_SEMAPHORE_FAILED         The semaphore pend operation failed.
+ *
+ * @warning Use this command sparingly and as a last resort to satisfy critical
+ * time-sensitive events.  Aborting any flash command results in prematurely ending the
+ * current flash access and may result in corrupted flash data.
+ *
+ * @sa adi_fee_GetAbortAddr().
+ */
+ADI_FEE_RESULT adi_fee_Abort (ADI_FEE_HANDLE const hDevice)
+
+{
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+#endif
+    /* Issue the command (abort is keyed) directly */
+    /* (avoid SendCommand() here, as it does a busy wait, which may not clear if we're in a recovery mode) */
+    hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
+    hDevice->pDev->CMD = ENUM_FLCC_CMD_ABORT;
+    hDevice->pDev->KEY = 0u;
+
+    SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED);
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Get the address of recently aborted write command.
+ *
+ * @param [in]     hDevice     The handle to the flash controller device.
+ * @param [in,out] pnAddress   Pointer to which the address is written.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The abort address is retrieved successfully
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Pointer passed is NULL
+ *
+ * Users may use this result to determine the flash location(s) affected by a write abort command.
+ * Subsequent flash commands invalidate the write abort address register.
+ *
+ *
+ * @sa adi_fee_Abort().
+ */
+ADI_FEE_RESULT adi_fee_GetAbortAddr (ADI_FEE_HANDLE const hDevice, uint32_t* const pnAddress)
+{
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    if (pnAddress == NULL) {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif
+
+    /* Write the address of the last write abort to the pointer
+     * supplied by the application
+     */
+    *pnAddress = hDevice->pDev->WR_ABORT_ADDR;
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Configure ECC start page and enablement.
+ *
+ * @param [in]  hDevice         The handle to the flash controller device.
+ * @param [in]  nStartPage      The start page for which ECC will be performed.
+ * @param [in]  bInfoECCEnable  Info space ECC enable:
+ *                                  - 'true' to enable info space ECC, or
+ *                                  - 'false' to disable info space ECC.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The ECC was configured successfully
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Start page is invalid
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress.
+ *
+ * @note The settings this API manages are very likely not needed to be modified dynamically (at run-time).
+ * If so, consider using the static configuration equivalents (see adi_flash_config.h) in lieu of
+ * this API... which will reduce the resulting code image footprint through linker elimination.
+ *
+ * @warning This API leaves user space ECC disabled.  Use #adi_fee_EnableECC() to manage ECC enable/disable.
+ *
+ * @sa adi_fee_EnableECC().
+ * @sa adi_fee_ConfigECCEvents().
+ * @sa adi_fee_GetECCErrAddr().
+ * @sa adi_fee_GetECCCorrections().
+ */
+ADI_FEE_RESULT adi_fee_ConfigECC (ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, bool const bInfoECCEnable)
+{
+    uint32_t nRelAddress = nStartPage << FEE_PAGE_SHIFT;
+
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+
+    if (nStartPage >= FEE_MAX_NUM_PAGES) {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif
+
+    /* Clear the ECC config bits */
+    CLR_BITS (hDevice->pDev->ECC_CFG, (BITM_FLCC_ECC_CFG_PTR | BITM_FLCC_ECC_CFG_INFOEN));
+
+    /* Set the start page address in the ECC Cfg register */
+    hDevice->pDev->ECC_CFG |= (nRelAddress & BITM_FLCC_ECC_CFG_PTR);
+
+    /* enable ECC on info space... if requested */
+    if (true == bInfoECCEnable) {
+        SET_BITS (hDevice->pDev->ECC_CFG, BITM_FLCC_ECC_CFG_INFOEN);
+    }
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Enable/Disable user space ECC for the device.
+ *
+ * @param [in]  hDevice  The handle to the flash controller device.
+ * @param [in]  bEnable  User space ECC enable:
+ *                           - 'true' to enable user space ECC, or
+ *                           - 'false' to disable user space ECC.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The ECC is enabled/disabled successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress.
+ *
+ * Manage enablement of user space ECC function.
+ *
+ * @note The settings this API manages are very likely not needed to be modified dynamically (at run-time).
+ * If so, consider using the static configuration equivalents (see adi_flash_config.h) in lieu of
+ * this API... which will reduce the resulting code image footprint through linker elimination.
+ *
+ * @sa adi_fee_ConfigECC().
+ * @sa adi_fee_ConfigECCEvents().
+ * @sa adi_fee_GetECCErrAddr().
+ * @sa adi_fee_GetECCCorrections().
+ */
+ADI_FEE_RESULT adi_fee_EnableECC (ADI_FEE_HANDLE const hDevice, bool const bEnable)
+{
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+#endif
+
+    /* manage flash ECC enable */
+    if (true == bEnable) {
+        SET_BITS(hDevice->pDev->ECC_CFG, BITM_FLCC_ECC_CFG_EN);
+    } else {
+        CLR_BITS(hDevice->pDev->ECC_CFG, BITM_FLCC_ECC_CFG_EN);
+    }
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Confifure ECC event response.
+ *
+ * @param [in]  hDevice     The handle to the flash controller device.
+ * @param [in]  eEvent      ECC event - Either error or correction event.
+ * @param [in]  eResponse   The response to the eEvent - One of none, bus error, or interrupt.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The ECC events are configured successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Parameters are invalid.
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress.
+ *
+ * Configures two major aspects of ECC event response:
+ *     - On ECC (2-bit) Error events, generate one of: no response, bus error, or flash interrupt.
+ *     - On ECC (1-bit) Correction events, generate one of: no response, bus error, or flash interrupt.
+ *
+ * @note The settings this API manages are very likely not needed to be modified dynamically (at run-time).
+ * If so, consider using the static configuration equivalents (see adi_flash_config.h) in lieu of
+ * this API... which will reduce the resulting code image footprint through linker elimination.
+ *
+ * @sa adi_fee_ConfigECC().
+ * @sa adi_fee_EnableECC().
+ * @sa adi_fee_GetECCErrAddr().
+ * @sa adi_fee_GetECCCorrections().
+ */
+ADI_FEE_RESULT adi_fee_ConfigECCEvents (ADI_FEE_HANDLE const hDevice, ADI_FEE_ECC_EVENT_TYPE const eEvent, ADI_FEE_ECC_RESPONSE const eResponse)
+
+{
+    uint32_t nBitMask;
+    int32_t nBitPos;
+
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+
+    /* Check the function parameters */
+    if (   (   (eEvent != ADI_FEE_ECC_EVENT_TYPE_ERROR)
+            && (eEvent != ADI_FEE_ECC_EVENT_TYPE_CORRECT))
+
+        || (   (eResponse != ADI_FEE_ECC_RESPONSE_NONE)
+            && (eResponse != ADI_FEE_ECC_RESPONSE_BUS_ERROR)
+            && (eResponse != ADI_FEE_ECC_RESPONSE_IRQ))
+        )
+    {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif
+
+    /* Select the correct bit mask and bit pos for the event type */
+    if (eEvent == ADI_FEE_ECC_EVENT_TYPE_ERROR) {
+        nBitMask = BITM_FLCC_IEN_ECC_ERROR;
+        nBitPos  = BITP_FLCC_IEN_ECC_ERROR;
+    }
+#if defined (__ADUCM4x50__)
+    else {
+        nBitMask = BITM_FLCC_IEN_ECC_CORRECT;
+        nBitPos  = BITP_FLCC_IEN_ECC_CORRECT;
+    }
+#endif    
+
+    /* clear the bits */
+    CLR_BITS (hDevice->pDev->IEN, nBitMask);
+
+    /* set the response */
+    SET_BITS (hDevice->pDev->IEN, ((uint32_t)eResponse) << nBitPos);
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * `@brief    Get the address for which the ECC event is detected.
+ *
+ * @param [in]      hDevice     The handle to the flash controller device.
+ * @param [in,out]  pnAddress   Pointer to which the address is written.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The ECC error address is retrieved successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Parameters are invalid.
+ *
+ * Returns the address of the first ECC error or correction event to generate an
+ * interrupt since the last time ECC status bits were cleared (or since reset).
+ *
+ * @sa adi_fee_ConfigECC().
+ * @sa adi_fee_EnableECC().
+ * @sa adi_fee_ConfigECCEvents().
+ * @sa adi_fee_GetECCCorrections().
+ */
+ADI_FEE_RESULT adi_fee_GetECCErrAddr (ADI_FEE_HANDLE const hDevice, uint32_t* const pnAddress)
+
+{
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    if (pnAddress == NULL) {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif
+
+    /* Write the address of the last ECC error/correction */
+    *pnAddress = hDevice->pDev->ECC_ADDR;
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Get the number of 1-bit error corrections.
+ *
+ * @param [in]      hDevice            The handle to the flash controller device.
+ * @param [in,out]  pnNumCorrections   Pointer to which the number of corrections are written.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The number of ECC corrections are successfully retrieved.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Parameters are invalid.
+ *
+ * See HRM for details on how current ECC configuration affects this reporting.
+ *
+ * @sa adi_fee_ConfigECC().
+ * @sa adi_fee_EnableECC().
+ * @sa adi_fee_ConfigECCEvents().
+ * @sa adi_fee_GetECCErrAddr().
+ */
+ADI_FEE_RESULT adi_fee_GetECCCorrections (ADI_FEE_HANDLE const hDevice, uint32_t* const pnNumCorrections)
+{
+
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    if (pnNumCorrections == NULL) {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif
+
+    /* Get the number of ECC Error corrections */
+    *pnNumCorrections = (hDevice->pDev->STAT & BITM_FLCC_STAT_ECCERRCNT) >> BITP_FLCC_STAT_ECCERRCNT;
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/*========  L O C A L    F U N C T I O N    D E F I N I T I O N S  ========*/
+
+
+/* Send a command to the flash controller... bot don't block on it...
+ */
+static ADI_FEE_RESULT SendCommand (ADI_FEE_HANDLE const hDevice, uint32_t const cmd)
+{
+    /* Wait for the flash to be free */
+    BusyWait (hDevice, (BITM_FLCC_STAT_CMDBUSY | BITM_FLCC_STAT_WRCLOSE));
+
+    /* Clear the command completion status bit
+     * by acknowledging it
+     */
+    hDevice->pDev->STAT = BITM_FLCC_STAT_CMDCOMP;
+
+    /* Enable command-complete and command-fail interrupt */
+    SET_BITS(hDevice->pDev->IEN, (BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL));
+
+    /* Issue the command (most commands are keyed) */
+    hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
+    hDevice->pDev->CMD = cmd;
+    hDevice->pDev->KEY = 0u;
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+static ADI_FEE_RESULT InitiatePioTransfer (ADI_FEE_HANDLE const hDevice)
+{
+
+    /* use PIO interrupt mode in non-burst-mode (burst-mode only spans 256-bytes).
+       Initiate the 1st write here, then let the interrupt handler feed
+       the remaining data as we process "almost-complete" interrupts.
+    */
+
+    /* write the 1st 64-bits of data */
+    if (0u != hDevice->nRemainingBytes) {
+
+        /* enable command interrupts */
+        SET_BITS (hDevice->pDev->IEN, (BITM_FLCC_IEN_WRALCMPLT | BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL));
+
+        /* set initial write address*/
+        hDevice->pDev->KH_ADDR = (uint32_t)hDevice->pNextWriteAddress;
+        hDevice->pNextWriteAddress += 2;
+
+        /* set key-hole data registers */
+        hDevice->pDev->KH_DATA0 = *hDevice->pNextReadAddress;
+        hDevice->pNextReadAddress++;
+        hDevice->pDev->KH_DATA1 = *hDevice->pNextReadAddress;
+        hDevice->pNextReadAddress++;
+        hDevice->nRemainingBytes -= sizeof(uint64_t);
+
+        /* write the command register which launches the burst write */
+        hDevice->pDev->CMD = ENUM_FLCC_CMD_WRITE;
+
+    } else {
+        return ADI_FEE_ERR_NO_DATA_TO_TRANSFER;
+    }
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/* DMA Transfer to FIFO */
+static ADI_FEE_RESULT InitiateDmaTransfer (ADI_FEE_HANDLE const hDevice)
+{
+    ADI_DCC_TypeDef* pCCD = pPrimaryCCD;  /* pointer to primary DMA descriptor array */
+
+    if (0u != hDevice->nRemainingBytes) {
+
+        /* local channel number */
+        uint16_t chan = hDevice->pDevInfo->dmaChanNum;
+
+        /* disable endpointer decrement modes */
+        pADI_DMA0->SRCADDR_CLR =  1u << chan;
+        pADI_DMA0->DSTADDR_CLR =  1u << chan;
+
+        /* enable the channel */
+        pADI_DMA0->EN_SET = 1u << chan;
+
+        /* allow flash to request DMA service */
+        pADI_DMA0->RMSK_CLR = 1u << chan;
+
+        /* activate primary descriptor */
+        pADI_DMA0->ALT_CLR = 1u << chan;
+
+        /* Note: DMA width is 32-bit for the flash controller, but flash writes require
+           64-bit writes at a whack.  Set DMA R_Power (bus rearbitration rate) to two so
+           we get two uninterrupted 32-bit DMA writes to the flash with each DMA transfer.
+        */
+
+        /* set DMA source endpoint */
+        pCCD += chan;  /* offset descriptor pointer to flash channel */
+        pCCD->DMASRCEND = (uint32_t)hDevice->pNextReadAddress + hDevice->nRemainingBytes - sizeof(uint32_t);
+
+        /* set DMA destination endpoint (no increment) */
+        pCCD->DMADSTEND = (uint32_t)&hDevice->pDev->KH_DATA1;
+
+        /* set the initial write address */
+        hDevice->pDev->KH_ADDR = (uint32_t)hDevice->pNextWriteAddress;
+
+        /* set the DMA Control Data Configuration register */
+        pCCD->DMACDC =
+            ( ((uint32_t)ADI_DMA_INCR_NONE                                << DMA_BITP_CTL_DST_INC)
+            | ((uint32_t)ADI_DMA_INCR_4_BYTE                              << DMA_BITP_CTL_SRC_INC)
+            | ((uint32_t)ADI_DMA_WIDTH_4_BYTE                             << DMA_BITP_CTL_SRC_SIZE)
+            | ((uint32_t)ADI_DMA_RPOWER_2                                 << DMA_BITP_CTL_R_POWER)
+            | (uint32_t)((hDevice->nRemainingBytes/sizeof(uint32_t) - 1u) << DMA_BITP_CTL_N_MINUS_1)
+            | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC                     << DMA_BITP_CTL_CYCLE_CTL) );
+
+        /* set auto-increment and DMA enable bits, launching transder */
+        hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
+        SET_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN));
+        hDevice->pDev->KEY = 0u;
+
+    } else {
+        return ADI_FEE_ERR_NO_DATA_TO_TRANSFER;
+    }
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/* Initiate transfer */
+static ADI_FEE_RESULT InitiateTransfer (ADI_FEE_HANDLE const hDevice)
+{
+    ADI_FEE_RESULT result = ADI_FEE_SUCCESS;
+
+    /* If a transfer is in progress or if the pending buffers are empty
+     * the return as there is nothing to be done now
+     */
+    if (true == hDevice->bTransferInProgress)
+    {
+        return ADI_FEE_ERR_DEVICE_BUSY;
+    }
+
+    /* Wait for the flash to not be busy */
+    BusyWait (hDevice, BITM_FLCC_STAT_CMDBUSY);
+
+    /* clear internal errors */
+    hDevice->feeError = 0u;
+    hDevice->dmaError = ADI_FEE_SUCCESS;
+
+    /* Set the bool variable to signify that a transfer is in progress */
+    hDevice->bTransferInProgress = true;
+
+    /* clear any command interrupt enables */
+    CLR_BITS(hDevice->pDev->IEN,  (BITM_FLCC_IEN_WRALCMPLT | BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL));
+
+    /* clear any dangeling command-related status */
+    hDevice->pDev->STAT = BITM_FLCC_STAT_WRALCOMP | BITM_FLCC_STAT_CMDCOMP | BITM_FLCC_STAT_CMDFAIL;
+
+    /* clear auto-increment and dma enable bits */
+    hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
+    CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN));
+    hDevice->pDev->KEY = 0u;
+
+    /* Call the corresponding Transfer functions */
+    if (true == hDevice->bUseDma) {
+        result = InitiateDmaTransfer(hDevice);
+    } else {
+        result = InitiatePioTransfer(hDevice);
+    }
+
+    return result;
+}
+
+
+/* hide the interrupt handlers from DoxyGen */
+/*! \cond PRIVATE */
+
+/* Flash PIO interrupt handler */
+void Flash0_Int_Handler(void)
+{
+    ISR_PROLOG();
+
+    /* post flag */
+    bool bPost = false;
+    bool bError = false;
+
+    /* recover the driver handle */
+    ADI_FEE_HANDLE hDevice = fee_device_info[0].hDevice;
+
+#ifdef ADI_DEBUG
+    /* Return if the device is not opened - spurious interrupts */
+    if (hDevice == NULL) {
+        return;
+    }
+#endif
+
+    /* update status cache and clear it right away on the controller */
+    hDevice->FlashStatusCopy = hDevice->pDev->STAT;
+    hDevice->pDev->STAT = hDevice->FlashStatusCopy;
+
+    /* check for flash device errors */
+    hDevice->feeError = (ADI_FEE_STATUS_ERROR_MASK & hDevice->FlashStatusCopy);
+    if (0u != hDevice->feeError) {
+        bError = true;
+    }
+
+    /* if no errors */
+    if (false == bError) {
+
+        if (0u != (BITM_FLCC_STAT_WRALCOMP & hDevice->FlashStatusCopy)) {
+
+            /* write-almost-complete */
+
+            /* if more data to write... */
+            if (0u != hDevice->nRemainingBytes) {
+
+                /* set next write the address */
+                hDevice->pDev->KH_ADDR = (uint32_t)hDevice->pNextWriteAddress;
+                hDevice->pNextWriteAddress += 2;
+
+                /* set next key-hole data */
+                hDevice->pDev->KH_DATA0 = *hDevice->pNextReadAddress;
+                hDevice->pNextReadAddress++;
+                hDevice->pDev->KH_DATA1 = *hDevice->pNextReadAddress;
+                hDevice->pNextReadAddress++;
+                hDevice->nRemainingBytes -= sizeof(uint64_t);
+
+                /* initiate next write */
+                hDevice->pDev->CMD = ENUM_FLCC_CMD_WRITE;
+
+            } else {
+
+                /* no more data to write...
+                   wait for current write-almost-complete status to transition to not busy */
+                BusyWait (hDevice, BITM_FLCC_STAT_CMDBUSY);
+
+                /* set post flag */
+                bPost = true;
+            }
+
+        } else if (0u != (BITM_FLCC_STAT_CMDCOMP & hDevice->FlashStatusCopy)) {
+
+            /* command-complete */
+
+            /* this path is for blocking-mode commands (erase, verify, abort, etc.) */
+
+            /* set post flag */
+            bPost = true;
+
+        } else {
+            /* no other interrupt types expected */
+        }
+    } else {
+        /* error(s) detected... set the post flag */
+        bPost = true;
+    }
+
+    /* singular post */
+    if (true == bPost) {
+
+        /* clear the command interrupt enables */
+        CLR_BITS(hDevice->pDev->IEN,  (BITM_FLCC_IEN_WRALCMPLT | BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL));
+
+        /* clear auto-increment and dma enable bits */
+        hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
+        CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN));
+        hDevice->pDev->KEY = 0u;
+
+        /* mark transfer complete */
+        hDevice->bTransferInProgress = false;
+
+        /* dispatch callback (if we have one...) */
+        if (0u != hDevice->pfCallback) {
+            if (false == bError) {
+                /* no error, pass success flag to callback */
+                hDevice->pfCallback (hDevice->pCBParam, (uint32_t)ADI_FEE_CALLBACK_EVENT_BUFFER_PROCESSED, (void*)NULL);
+            } else {
+                /* error condition, pass error flag and error status to callback */
+                hDevice->pfCallback (hDevice->pCBParam, (uint32_t)ADI_FEE_CALLBACK_EVENT_DEVICE_ERROR, (void*)hDevice->feeError);
+            }
+        }
+
+        /* post the semaphore */
+        SEM_POST(hDevice);
+    }
+
+    ISR_EPILOG();
+}
+
+
+/* Flash DMA interrupt handler */
+void DMA_FLASH0_Int_Handler (void)
+{
+    /* rtos prologue */
+    ISR_PROLOG()
+        ;
+
+    /* recover the driver handle */
+    ADI_FEE_HANDLE hDevice = fee_device_info[0].hDevice;
+
+    /* update status cache and clear it right away on the controller */
+    hDevice->FlashStatusCopy = hDevice->pDev->STAT;
+    hDevice->pDev->STAT = hDevice->FlashStatusCopy;
+
+    /* capture any hw error status */
+    hDevice->feeError = (ADI_FEE_STATUS_ERROR_MASK & hDevice->FlashStatusCopy);
+
+    /* clear auto-increment and dma enable bits */
+    hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
+    CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN));
+    hDevice->pDev->KEY = 0u;
+
+    /* clear the remaining count, as it should all have gone in one swoop */
+    hDevice->nRemainingBytes = 0u;
+
+    /* mark transfer complete */
+    hDevice->bTransferInProgress = false;
+
+    /* dispatch callback (if we have one...) */
+    if (0u != hDevice->pfCallback) {
+
+        /* no errors, notify success */
+        if ((0u == hDevice->feeError) && (0u == hDevice->dmaError)) {
+            hDevice->pfCallback (hDevice->pCBParam, (uint32_t)ADI_FEE_CALLBACK_EVENT_BUFFER_PROCESSED, (void*)NULL);
+
+        /* flash hardware error */
+        } else if (0u == hDevice->feeError) {
+            hDevice->pfCallback (hDevice->pCBParam, (uint32_t)ADI_FEE_CALLBACK_EVENT_DEVICE_ERROR, (void*)hDevice->feeError);
+
+        /* flash dma error */
+        } else if (0u == hDevice->dmaError) {
+            /* DMA error */
+            hDevice->pfCallback (hDevice->pCBParam, (uint32_t)hDevice->dmaError, NULL);
+        } else {
+            /* no other cases... */
+        }
+    }
+
+    /* post the semaphore */
+    SEM_POST(hDevice);
+
+    ISR_EPILOG();
+}
+
+/*! \endcond */
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/flash/adi_flash_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/flash/adi_flash_data.c
new file mode 100755
index 00000000000..7d419b11f02
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/flash/adi_flash_data.c
@@ -0,0 +1,129 @@
+/*
+ *****************************************************************************
+ * @file:    adi_flash_data.c
+ * @brief:   Data declaration for Flash Device Driver
+ * @date:    $Date$
+ *****************************************************************************
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be consciously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_FEE_DATA_C
+#define ADI_FEE_DATA_C
+
+ /*! \cond PRIVATE */
+
+#include <adi_processor.h>
+#include "adi_flash_def.h"
+#include "adi_flash_config.h"
+
+
+/* Stores the information about the specific device */
+static ADI_FEE_DEVICE_INFO fee_device_info [ADI_FEE_NUM_INSTANCES] =
+{
+    /* only one flash instance at this time */
+    {    pADI_FLCC0,            /* Flash controller pointer         */
+        FLCC_EVT_IRQn,          /* Flash PIO interrupt number       */
+        DMA0_CH15_DONE_IRQn,    /* Flash DMA interrupt number       */
+        FLASH_CHANn,            /* Flash DMA channel (15) number    */
+        NULL,                   /* Flash static config info         */
+        NULL                    /* Flash driver handle              */
+    },
+};
+
+
+/* build Flash Application configuration array */
+static ADI_FEE_CONFIG gConfigInfo[ADI_FEE_NUM_INSTANCES] =
+{
+    /* the one-and-only (so far) instance data for FEE0... */
+    {
+#if defined (__ADUCM4x50__)
+        /* ECC interrupt enable settings (IEN register) */
+        ( (ADI_FEE_CFG_ECC_ERROR_RESPONSE      << BITP_FLCC_IEN_ECC_ERROR)
+        | (ADI_FEE_CFG_ECC_CORRECTION_RESPONSE << BITP_FLCC_IEN_ECC_CORRECT)
+        ),
+
+#elif defined (__ADUCM302x__)
+
+        /* ECC interrupt enable settings (IEN register) */
+        ( (ADI_FEE_CFG_ECC_ERROR_RESPONSE      << BITP_FLCC_IEN_ECC_ERROR)),
+
+#endif
+        /* timing parameter settings (TIME_PARAM0 register) */
+        ( (ADI_FEE_CFG_PARAM0_TNVH1            << BITP_FLCC_TIME_PARAM0_TNVH1)
+        | (ADI_FEE_CFG_PARAM0_TERASE           << BITP_FLCC_TIME_PARAM0_TERASE)
+        | (ADI_FEE_CFG_PARAM0_TRCV             << BITP_FLCC_TIME_PARAM0_TRCV)
+        | (ADI_FEE_CFG_PARAM0_TNVH             << BITP_FLCC_TIME_PARAM0_TNVH)
+        | (ADI_FEE_CFG_PARAM0_TPROG            << BITP_FLCC_TIME_PARAM0_TPROG)
+        | (ADI_FEE_CFG_PARAM0_TPGS             << BITP_FLCC_TIME_PARAM0_TPGS)
+        | (ADI_FEE_CFG_PARAM0_TNVS             << BITP_FLCC_TIME_PARAM0_TNVS)
+        | (ADI_FEE_CFG_PARAM0_CLKDIV           << BITP_FLCC_TIME_PARAM0_DIVREFCLK)
+        ),
+#if defined (__ADUCM4x50__)
+            /* more timing parameter settings (TIME_PARAM1 register) */
+        ( (ADI_FEE_CFG_PARAM1_WAITESTATES      << BITP_FLCC_TIME_PARAM1_WAITSTATES)
+        | (ADI_FEE_CFG_PARAM1_TWK              << BITP_FLCC_TIME_PARAM1_TWK)
+        ),
+
+#elif defined (__ADUCM302x__)
+        /* more timing parameter settings (TIME_PARAM1 register) */
+        ((ADI_FEE_CFG_PARAM1_TWK              << BITP_FLCC_TIME_PARAM1_TWK)),
+
+#endif
+        /* system interrupt abort enables (ABORT_EN_XX registers) */
+        (ADI_FEE_CFG_ABORT_EN_LO),
+        (ADI_FEE_CFG_ABORT_EN_HI),
+
+        /* ECC configuration register settings (ECC_CFG register) */
+        (((ADI_FEE_CFG_ECC_START_PAGE          << FEE_PAGE_SHIFT) & BITM_FLCC_ECC_CFG_PTR)
+#if (ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE == 1u)
+        | (BITM_FLCC_ECC_CFG_INFOEN)
+#endif
+#if (ADI_FEE_CFG_ENABLE_ECC == 1u)
+        | (BITM_FLCC_ECC_CFG_EN)
+#endif
+        )
+    }  /* end device 0 settings */
+};
+
+/*! \endcond */
+
+
+#endif /* ADI_FEE_DATA_C */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/flash/adi_flash_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/flash/adi_flash_def.h
new file mode 100755
index 00000000000..13a58facae6
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/flash/adi_flash_def.h
@@ -0,0 +1,201 @@
+/*!
+ *****************************************************************************
+ @file:    adi_flash_def.h
+ @brief:   Internal Flash device driver definitions and macros
+ @date:    $Date: 2014-11-28 01:48:03 -0500 (Fri, 28 Nov 2014) $
+ -----------------------------------------------------------------------------
+Copyright (c) 2012-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_FLASH_DEF_H
+#define ADI_FLASH_DEF_H
+
+/*! \cond PRIVATE */
+
+#include <drivers/dma/adi_dma.h>
+#include <config/adi_flash_config.h>
+
+#include <drivers/flash/adi_flash.h>
+
+/* fixed number of flash controllers */
+#define ADI_FEE_NUM_INSTANCES       (1u)
+
+#if defined (__ADUCM4x50__)
+/* STATUS register error mask */
+#define ADI_FEE_STATUS_ERROR_MASK ( BITM_FLCC_STAT_ACCESS_MODE    \
+                                  | BITM_FLCC_STAT_CACHESRAMPERR  \
+                                  | BITM_FLCC_STAT_ECCDCODE       \
+                                  | BITM_FLCC_STAT_ECCINFOSIGN    \
+                                  | BITM_FLCC_STAT_SIGNERR        \
+                                  | BITM_FLCC_STAT_OVERLAP        \
+                                  | BITM_FLCC_STAT_ECCRDERR       \
+                                  | BITM_FLCC_STAT_ECCERRCMD      \
+                                  | BITM_FLCC_STAT_SLEEPING       \
+                                  | BITM_FLCC_STAT_CMDFAIL)
+#elif defined (__ADUCM302x__)
+#define ADI_FEE_STATUS_ERROR_MASK ( BITM_FLCC_STAT_CACHESRAMPERR  \
+                                  | BITM_FLCC_STAT_ECCDCODE       \
+                                  | BITM_FLCC_STAT_ECCINFOSIGN    \
+                                  | BITM_FLCC_STAT_SIGNERR        \
+                                  | BITM_FLCC_STAT_OVERLAP        \
+                                  | BITM_FLCC_STAT_ECCRDERR       \
+                                  | BITM_FLCC_STAT_ECCERRCMD      \
+                                  | BITM_FLCC_STAT_SLEEPING       \
+                                  | BITM_FLCC_STAT_CMDFAIL)
+#endif
+
+#if defined(__ECC__)
+#define ALIGN
+#define ALIGN4  _Pragma("align(4)")
+#elif defined(__ICCARM__)
+#define ALIGN   _Pragma("pack()")
+#define ALIGN4  _Pragma("pack(4)")
+#elif defined (__GNUC__)
+#define ALIGN   _Pragma("pack()")
+#define ALIGN4  _Pragma("pack(4)")
+#endif
+
+/* Flash Size and Page/Block macros:
+    512kB total user space, broken up as
+        256-pages, 2kB/page
+        32-blocks, 16kB/block
+        8 pages/block
+*/
+#if defined (__ADUCM4x50__)
+#define FEE_FLASH_SIZE     (0x80000u)                          /* 512kB total */
+#define FEE_BLOCK_SHIFT    (14u)                               /* 16kB block size */
+
+#elif defined (__ADUCM302x__)
+#define FEE_FLASH_SIZE     (0x40000u)                          /* 256kB total */
+#define FEE_BLOCK_SHIFT    (13u)                               /* 8kB block size */
+#else
+#error Flash driver is not ported to this processor
+#endif
+
+#define FEE_PAGE_SHIFT     (11u)                               /* 2kB page size */ 
+#define FEE_MAX_NUM_PAGES  (FEE_FLASH_SIZE >> FEE_PAGE_SHIFT)  /* max number of pages */
+#define FEE_MAX_NUM_BLOCKS (FEE_FLASH_SIZE >> FEE_BLOCK_SHIFT) /* max number of blocks (32) */
+
+#if (ADI_FEE_CFG_ECC_START_PAGE >= FEE_MAX_NUM_PAGES)
+#error "ADI_FEE_CFG_ECC_START_PAGE range is invalid"
+#endif
+
+
+/* INTERNAL DRIVER STATIC FUNCTION PROTOTYPES */
+
+/* Send a command to the flash controller, but does no pend on it... */
+static ADI_FEE_RESULT SendCommand (ADI_FEE_HANDLE const hDevice, uint32_t const cmd);
+
+/* generic transfer initiator... dispatches to InitiatePioTransfer() or InitiateDmaTransfer() */
+static ADI_FEE_RESULT InitiateTransfer (ADI_FEE_HANDLE const hDevice);
+
+/* PIO initiator */
+static ADI_FEE_RESULT InitiatePioTransfer (ADI_FEE_HANDLE const hDevice);
+
+/* DMA initiator */
+static ADI_FEE_RESULT InitiateDmaTransfer (ADI_FEE_HANDLE const hDevice);
+
+/* interrupt handlers */
+void Flash0_Int_Handler(void);
+void DMA_FLASH0_Int_Handler (void);
+
+/* INTERNAL DRIVER DATATYPES */
+
+/*
+ *****************************************************************************
+ * FEE Configuration structure.
+ *****************************************************************************/
+typedef struct __ADI_FEE_CONFIG {
+    uint32_t eccIrqEnables;     	/* ECC interrupt enables.                      */
+    uint32_t param0;            	/* TIME_PARAM0 register.                       */
+    uint32_t param1;            	/* TIME_PARAM1 register.                       */
+    uint32_t abortEnableLo;     	/* Lower interrupt abort enables (IRQs 0-31).  */
+    uint32_t abortEnableHi;     	/* Upper interrupt abort enables (IRQs 32-63.) */
+    uint32_t eccConfig;         	/* ECC_CFG register.                           */
+} ADI_FEE_CONFIG;
+
+
+/* Flash physical device instance data */
+typedef struct __ADI_FEE_DEVICE_INFO {
+
+   ADI_FLCC_TypeDef *pDev;       	/* Pointer to the physical controller.         */
+   IRQn_Type         pioIrqNum;  	/* The flash controller PIO interrupt number.  */
+   IRQn_Type         dmaIrqNum;  	/* The flash controller DMA interrupt number.  */
+   DMA_CHANn_TypeDef dmaChanNum;	/* The flash controller DMA channel number.    */
+   ADI_FEE_CONFIG   *pConfig;    	/* Pointer to user config info.                */
+   ADI_FEE_HANDLE    hDevice;    	/* Pointer the device memory (supplied by the application). */
+
+} ADI_FEE_DEVICE_INFO;
+
+
+/* Flash driver instance data structure */
+typedef struct __ADI_FEE_DEV_DATA_TYPE {
+
+    /* make sure to synchronize ANY size changes with ADI_FLASH_MEMORY_SIZE macro in adi_flash.h */
+
+    /* NOTE: "volatile" storage class on all interrupt-modified valuables */
+
+    /* device attributes */
+    ADI_FLCC_TypeDef           *pDev;					/* Pointer top physical flash controller.        */
+    ADI_FEE_DEVICE_INFO        *pDevInfo;				/* Pointer to hardware device attributes.        */
+
+    /* callback info */
+    ADI_CALLBACK                pfCallback;				/* Registered callback function address.         */
+    void                       *pCBParam;				/* Registered callback user parameter.           */
+
+    /* internal driver state variables */
+    bool                        bUseDma;				/* DMA control flag (from user).                 */
+    bool                        bSubmitCalled;			/* Flag to identify if a buffer was "submitted". */
+    volatile uint32_t           FlashStatusCopy;		/* Clop of latest flash status register.         */
+    volatile uint32_t           feeError;				/* Flash error collector.                        */
+    volatile ADI_FEE_RESULT     dmaError;				/* DMA error collector.                          */
+    volatile bool               bTransferInProgress;	/* Flag indicating if a transfer is in progress. */
+
+    /* data info */
+    volatile uint32_t          *pNextWriteAddress;      /* Pointer to next write data in flash space.    */
+    volatile uint32_t          *pNextReadAddress;       /* Pointer to next read data in user buffer.     */
+    volatile uint32_t           nRemainingBytes;        /* Number of remaining bytes still to transfer.  */
+
+    SEM_VAR_DECLR        /* Blocking object: "Semaphore" for rtos,  "bLowPowerExitFlag" for non-rtos.    */
+
+} ADI_FEE_DEV_DATA_TYPE;
+
+/*! \endcond */
+
+#endif /* ADI_FLASH_DEF_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/gpio/adi_gpio.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/gpio/adi_gpio.c
new file mode 100755
index 00000000000..a54c0b2b0be
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/gpio/adi_gpio.c
@@ -0,0 +1,989 @@
+/*
+ *****************************************************************************
+   @file:    adi_gpio.c
+   @brief:   GPIO device driver implementation.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+/*****************************************************************************/
+
+#include <stddef.h>
+#include <string.h>
+#include <assert.h>
+#include <drivers/gpio/adi_gpio.h>
+#include <rtos_map/adi_rtos_map.h>
+#include "adi_gpio_def.h"
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
+*   This isn't a header as such.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+*
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   The rule makes an exception for memory-mapped register accesses.
+*/
+#pragma diag_suppress=Pm123,Pm073,Pm143,Pm140
+#endif /* __ICCARM__ */
+
+/* Debug function declarations */
+#ifdef ADI_DEBUG
+static bool ArePinsValid      (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins);   /*!< tests for pins validity */
+#endif /* ADI_DEBUG */
+
+
+static void CommonInterruptHandler  (const ADI_GPIO_IRQ_INDEX index, const IRQn_Type eIrq);
+void GPIO_A_Int_Handler(void);
+void GPIO_B_Int_Handler(void);
+
+/*==========  D A T A  ==========*/
+static ADI_GPIO_DRIVER adi_gpio_Device =
+{
+    {
+       pADI_GPIO0,       /* port 0 base address */
+       pADI_GPIO1,       /* port 1 base address */
+       pADI_GPIO2,       /* port 2 base address */
+#if defined(__ADUCM4x50__)       
+	   pADI_GPIO3,		 /* port 3 base address */
+#endif /* __ADUCM4x50__ */       
+    },
+    
+    NULL
+};
+/*! \endcond */
+
+/*! \addtogroup GPIO_Driver GPIO Driver
+ *  @{
+
+  @brief    GPIO port and pin identifiers
+  @note The application must include drivers/gpio/adi_gpio.h to use this driver
+  @details  The documented macros can be passed to the following functions:
+      - adi_gpio_OutputEnable()
+      - adi_gpio_PullUpEnable()
+      - adi_gpio_SetHigh()
+      - adi_gpio_SetLow()
+      - adi_gpio_Toggle()
+      - adi_gpio_SetData()
+      - adi_gpio_GetData()
+
+      To control a single GPIO, these macros can be passed to the functions one
+      at a time. For example, to set the GPIO on port 2, pin 4 to a logical high
+      level, the following is used:
+
+      <pre>
+      adi_gpio_SetHigh(ADI_GPIO_PORT2, ADI_GPIO_PIN_4)
+      </pre>
+
+      Multiple GPIOs, so long as they reside on the same port, can be controlled
+      simultaneously. These macros can be OR-ed together and passed to the
+      functions. For example, to set the GPIOs on port 2, pins 3, 4 and 7 to
+      a logical low level, the following is used:
+
+      <pre>
+      adi_gpio_SetLow(ADI_GPIO_PORT2, ADI_GPIO_PIN_3 | ADI_GPIO_PIN_4 | ADI_GPIO_PIN_7)
+      </pre>
+
+      For the sensing, or adi_gpio_Getxxx, functions, the passed pValue parameter is written with
+      a packed value containing the status of the requested GPIO pins on the given port.
+
+      If information is required for a single pin, return value can be directly used
+      For example to see if pin 4 on port 2 has the pull up enabled, the following is used:
+      adi_gpio_GetData(ADI_GPIO_PORT2, ADI_GPIO_PIN_4, &pValue)
+      pValue will contain the required information.
+
+      If information is required for multiple pins, following method is required:
+      <pre>
+        adi_gpio_GetData(ADI_GPIO_PORT2, (ADI_GPIO_PIN_3 | ADI_GPIO_PIN_4 | ADI_GPIO_PIN_7), &pValue)
+      </pre>
+      To test if pin 4 on port 2 has pull up enabled, the following is used:
+      <pre>
+        if   (pValue & ADI_GPIO_PIN_4) {
+                    the pull up is enabled for pin 4 on port 2
+        } else {
+                    the pull up is disabled for pin 4 on port 2
+        }
+      </pre>
+
+ */
+
+/*!
+    @brief      Initializes the GPIO functions.
+
+    @details    This function initializes the GPIO driver. This function should be called before calling any of the GPIO
+                driver APIs.
+
+    @param[in] pMemory      Pointer to the memory required for the driver to operate.
+                            The size of the memory should be at least #ADI_GPIO_MEMORY_SIZE bytes.
+                            
+    @param[in] MemorySize   Size of the memory (in bytes) passed in pMemory parameter.
+
+    @return     Status
+                    - ADI_GPIO_SUCCESS                  If successfully initialized the GPIO driver.
+                    - ADI_GPIO_NULL_PARAMETER       [D] If the given pointer to the driver memory is pointing to NULL.
+                    - ADI_GPIO_INVALID_MEMORY_SIZE  [D] If the given memory size is not sufficient to operate the driver. 
+
+    @note       This function clears memory reserved for managing the callback function when it is called 
+                for the first time. It is expected from user to call "adi_gpio_UnInit" function when the GPIO service is no longer required.
+
+    @sa         adi_gpio_UnInit
+*/
+ADI_GPIO_RESULT adi_gpio_Init(
+    void*                const pMemory,
+    uint32_t             const MemorySize
+)
+{
+
+#ifdef ADI_DEBUG
+        /* Verify the given memory pointer */
+        if(NULL == pMemory)
+        {
+            return ADI_GPIO_NULL_PARAMETER;
+        }
+        /* Check if the memory size is sufficient to operate the driver */ 
+        if(MemorySize < ADI_GPIO_MEMORY_SIZE)
+        {
+            return ADI_GPIO_INVALID_MEMORY_SIZE;
+        }
+        assert(ADI_GPIO_MEMORY_SIZE == sizeof(ADI_GPIO_DEV_DATA));
+#endif
+
+    /* Only initialize on 1st init call, i.e., preserve callbacks on multiple inits */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        uint32_t i;
+
+        adi_gpio_Device.pData = (ADI_GPIO_DEV_DATA*)pMemory;
+
+        /* Initialize the callback table */
+        for (i = 0u; i < ADI_GPIO_NUM_INTERRUPTS; i++)
+        {
+            adi_gpio_Device.pData->CallbackTable[i].pfCallback = NULL;
+            adi_gpio_Device.pData->CallbackTable[i].pCBParam   = NULL;
+        }
+        
+        /* Enable the group interrupts */
+        NVIC_EnableIRQ(SYS_GPIO_INTA_IRQn);
+        NVIC_EnableIRQ(SYS_GPIO_INTB_IRQn);
+    }
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+    @brief      Un-initialize the GPIO driver.
+
+    @details    Terminates the GPIO functions, leaving everything unchanged.
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS if successfully uninitialized
+                    - #ADI_GPIO_NOT_INITIALIZED [D] if not yet initialized
+
+    @sa         adi_gpio_Init
+*/
+ADI_GPIO_RESULT adi_gpio_UnInit(void)
+{
+
+#ifdef ADI_DEBUG
+    /* IF (not initialized) */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        /* return error if not initialized */
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+#endif
+
+    /* Disable the group interrupts */
+    NVIC_DisableIRQ(SYS_GPIO_INTA_IRQn);
+    NVIC_DisableIRQ(SYS_GPIO_INTB_IRQn);
+
+    /* Clear the data pointer */
+    adi_gpio_Device.pData = NULL;
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+    @brief      Group the pins for the given group interrupt.
+
+    @details    Group the given pins for the Group A/B interrupt.
+                Applications can register/unregister a callback using the #adi_gpio_RegisterCallback API
+                to get a notification when the group interrupt occurs.
+
+    @param[in]  Port   GPIO port number to be operated on.
+    @param[in]  eIrq   Interrupt (Group A/B) to which the pin(s) are to be grouped.
+    @param[in]  Pins   The GPIO pins which needs to be grouped.
+                           Pin bits that are set enable the interrupt for the group A/B.
+                           Pin bits that are clear disable the interrupt for the group A/B.
+    @return     Status
+                    - #ADI_GPIO_SUCCESS                 If successfully grouped the given pins.
+                    - #ADI_GPIO_NOT_INITIALIZED     [D] If GPIO driver is not yet initialized.
+                    - #ADI_GPIO_INVALID_PINS        [D] The given pins are invalid.
+
+    @sa         adi_gpio_RegisterCallback
+    @sa         adi_gpio_SetGroupInterruptPolarity
+*/
+ADI_GPIO_RESULT adi_gpio_SetGroupInterruptPins(const ADI_GPIO_PORT Port, const ADI_GPIO_IRQ eIrq, const ADI_GPIO_DATA Pins)
+{
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+    ADI_INT_STATUS_ALLOC();
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+
+    /* validate the pins */
+    if (!ArePinsValid(Port, Pins))
+    {
+        return (ADI_GPIO_INVALID_PINS);
+    }
+#endif
+
+    pPort = adi_gpio_Device.pReg[Port];
+
+    ADI_ENTER_CRITICAL_REGION();
+    switch (eIrq)
+    {
+        case SYS_GPIO_INTA_IRQn:
+            pPort->IENA = Pins;
+            break;
+        case SYS_GPIO_INTB_IRQn:
+            pPort->IENB = Pins;
+            break;
+        default:
+            break; /* This shall never reach */
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+
+
+
+
+
+
+
+
+/*!
+    @brief      Set the interrupt polarity for the given pins.
+
+    @details    Sets the interrupt polarity for the given pins for the given port.
+                When the corresponding bit is set an interrupt is generated when the pin transitions from low-to-high. When the corresponding bit is cleared an interrupt is generated when the pin transitions from high-to-low.
+
+    @param[in]  Port   GPIO port number to be operated on.
+    @param[in]  Pins   Pins whose polarity to be set.
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS             If successfully set the polarity.
+                    - #ADI_GPIO_NOT_INITIALIZED [D] If not yet initialized.
+                    - #ADI_GPIO_INVALID_PINS    [D] If the given pins are invalid.
+
+    @sa         adi_gpio_RegisterCallback
+    @sa         adi_gpio_SetGroupInterruptPins
+*/
+ADI_GPIO_RESULT adi_gpio_SetGroupInterruptPolarity(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins)
+{
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+
+    /* validate the pins */
+    if (!ArePinsValid(Port, Pins))
+    {
+        return (ADI_GPIO_INVALID_PINS);
+    }
+#endif
+
+    pPort = adi_gpio_Device.pReg[Port];
+
+    pPort->POL = Pins;
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+    @brief      Enables/Disables the Output Drivers for GPIO Pin(s)
+
+    @details    Enables/disables the output drivers for the given GPIO pin(s) on
+                the given port.
+
+    @param[in]  Port    The GPIO port to be configured.
+    @param[in]  Pins    One or more GPIO pins to be configured. GPIO
+                        pins can be passed one at a time or in combination. To
+                        configure a single GPIO pin, a single GPIO value is
+                        passed for this parameter. For example, #ADI_GPIO_PIN_4.
+                        Alternatively, multiple GPIO pins can be configured
+                        simultaneously by OR-ing together GPIO pin values and
+                        passing the resulting value for this parameter. For
+                        example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6.
+    @param[in]  bFlag   Boolean value describing the action to be taken
+                            - true      enables the output driver
+                            - false     disables the output driver
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS             If successfully configured
+                    - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized.
+                    - #ADI_GPIO_INVALID_PINS    [D] If the given pins are invalid.
+*/
+ADI_GPIO_RESULT adi_gpio_OutputEnable(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag)
+{
+
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+    ADI_INT_STATUS_ALLOC();
+    
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+
+    /* validate the pins */
+    if (!ArePinsValid(Port, Pins))
+    {
+        return (ADI_GPIO_INVALID_PINS);
+    }
+#endif
+
+    pPort = adi_gpio_Device.pReg[Port];
+
+    ADI_ENTER_CRITICAL_REGION();
+    if (bFlag)
+    {
+        /* enable output */
+        pPort->OEN |= Pins;
+    } else
+    {
+        /* disable output */
+        pPort->OEN &= (uint16_t)~Pins;
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+    @brief      Enables/Disables the Input Drivers for GPIO Pin(s)
+
+    @details    Enables/disables the input drivers for the given GPIO pin(s) on
+                the given port.
+
+    @param[in]  Port    The GPIO port to be configured.
+    @param[in]  Pins    One or more GPIO pins to be configured. GPIO
+                        pins can be passed one at a time or in combination. To
+                        configure a single GPIO pin, a single GPIO value is
+                        passed for this parameter. For example, #ADI_GPIO_PIN_4.
+                        Alternatively, multiple GPIO pins can be configured
+                        simultaneously by OR-ing together GPIO pin values and
+                        passing the resulting value for this parameter. For
+                        example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6.
+
+    @param[in]  bFlag   Boolean value describing the action to be taken
+                            - true      enables the input driver
+                            - false     disables the input driver
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS             If successfully configured.
+                    - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized.
+                    - #ADI_GPIO_INVALID_PINS    [D] If the given pins are invalid.
+*/
+ADI_GPIO_RESULT adi_gpio_InputEnable(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag)
+{
+
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+    ADI_INT_STATUS_ALLOC();
+    
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData) {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+
+    /* validate the pins */
+    if (!ArePinsValid(Port, Pins)) {
+        return (ADI_GPIO_INVALID_PINS);
+    }
+#endif
+
+    pPort = adi_gpio_Device.pReg[Port];
+
+    ADI_ENTER_CRITICAL_REGION();
+    if (bFlag)
+    {
+        /* enable input */
+        pPort->IEN |= Pins;
+    } else
+    {
+        /* disable input */
+        pPort->IEN &= (uint16_t)~Pins;
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+    @brief      Enables/Disables the Pull-Up for GPIO Pin(s)
+
+    @details    Enables/disables the internal pull-up for the given GPIO pin(s) on
+                the given port.  API simply enables/disables whatever the hard-wired
+                pulls (up/down) are.
+
+    @param[in]  Port    The GPIO port to be configured.
+    @param[in]  Pins    One or more GPIO pins to be configured. GPIO
+                        pins can be passed one at a time or in combination. To
+                        configure a single GPIO pin, a single GPIO value is
+                        passed for this parameter. For example, #ADI_GPIO_PIN_4.
+                        Alternatively, multiple GPIO pins can be configured
+                        simultaneously by OR-ing together GPIO pin values and
+                        passing the resulting value for this parameter. For
+                        example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6.
+    @param[in]  bFlag   Boolean value describing the action to be taken
+                            - true      enables the pull-up
+                            - false     disables the pull-up
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS             If successfully configured.
+                    - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized.
+                    - #ADI_GPIO_INVALID_PINS    [D] If the given pins are invalid.
+*/
+ADI_GPIO_RESULT adi_gpio_PullUpEnable(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag)
+{
+
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+    ADI_INT_STATUS_ALLOC();
+    
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+
+    /* validate the pins */
+    if (!ArePinsValid(Port, Pins))
+    {
+        return (ADI_GPIO_INVALID_PINS);
+    }
+#endif
+
+    pPort = adi_gpio_Device.pReg[Port];
+
+    ADI_ENTER_CRITICAL_REGION();
+    if (bFlag)
+    {
+        pPort->PE |= Pins;
+    } else
+    {
+        pPort->PE &= (uint16_t)(~Pins);
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+/*!
+
+    @brief      Sets the Given GPIO pin(s) to a Logical High Level
+
+    @details    Sets the given GPIO pin(s) on the given port to a logical high
+                level.
+
+    @param[in]  Port    GPIO port whose pins need to be set to logical high level.
+    @param[in]  Pins    One or more GPIO pins to be set to logical high. GPIO
+                        pins can be passed one at a time or in combination. To
+                        configure a single GPIO pin, a single GPIO value is
+                        passed for this parameter. For example, #ADI_GPIO_PIN_4.
+                        Alternatively, multiple GPIO pins can be configured
+                        simultaneously by OR-ing together GPIO pin values and
+                        passing the resulting value for this parameter. For
+                        example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6.
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS             If successfully configured.
+                    - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized.
+                    - #ADI_GPIO_INVALID_PINS    [D] If the given pins are invalid.
+
+    @sa         adi_gpio_SetLow, adi_gpio_Toggle, adi_gpio_SetData, adi_gpio_GetData
+*/
+ADI_GPIO_RESULT adi_gpio_SetHigh(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins)
+{
+
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+
+    /* validate the pins */
+    if (!ArePinsValid(Port, Pins))
+    {
+        return (ADI_GPIO_INVALID_PINS);
+    }
+#endif
+
+    pPort = adi_gpio_Device.pReg[Port];
+
+    /* set the given GPIOs high */
+    pPort->SET = Pins;
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+
+    @brief      Sets the Given GPIO pin(s) to a Logical Low Level
+
+    @details    Sets the given GPIO pin(s) on the given port to a logical low
+                level.
+
+    @param[in]  Port    The GPIO port whose pins need to be set to logical low level.
+    @param[in]  Pins    One or more GPIO pins to be whose logic level to be set. GPIO
+                        pins can be passed one at a time or in combination. To
+                        configure a single GPIO pin, a single GPIO value is
+                        passed for this parameter. For example, #ADI_GPIO_PIN_4.
+                        Alternatively, multiple GPIO pins can be configured
+                        simultaneously by OR-ing together GPIO pin values and
+                        passing the resulting value for this parameter. For
+                        example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6.
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS             If successfully configured.
+                    - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized.
+                    - #ADI_GPIO_INVALID_PINS    [D] If the given pins are invalid.
+
+    @sa         adi_gpio_SetHigh, adi_gpio_Toggle, adi_gpio_SetData, adi_gpio_GetData
+*/
+ADI_GPIO_RESULT adi_gpio_SetLow(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins)
+{
+
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+
+    /* validate the pins */
+    if (!ArePinsValid(Port, Pins))
+    {
+        return (ADI_GPIO_INVALID_PINS);
+    }
+#endif
+
+    pPort = adi_gpio_Device.pReg[Port];
+
+    /* set the given GPIOs low */
+    pPort->CLR = Pins;
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+
+    @brief      Toggles the Logical Level of the Given GPIO pin(s)
+
+    @details    Toggles the logical level of the given GPIO pin(s) on the given port.
+                If a given GPIO pin is at a logical low level, this function will
+                change the level to a logical high value. If a given GPIO pin is
+                at a logical high level, this function will change the level to a
+                logical low value.
+
+    @param[in]  Port    The GPIO port whose pins to be toggled.
+    @param[in]  Pins    The GPIO pins whose logic level to be toggled. GPIO
+                        pins can be passed one at a time or in combination. To
+                        configure a single GPIO pin, a single GPIO value is
+                        passed for this parameter. For example, #ADI_GPIO_PIN_4.
+                        Alternatively, multiple GPIO pins can be configured
+                        simultaneously by OR-ing together GPIO pin values and
+                        passing the resulting value for this parameter. For
+                        example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6.
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS             If successfully configured.
+                    - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized.
+                    - #ADI_GPIO_INVALID_PINS    [D] If the given pins are invalid.
+
+    @sa         adi_gpio_SetHigh, adi_gpio_SetLow, adi_gpio_SetData, adi_gpio_GetData
+*/
+ADI_GPIO_RESULT adi_gpio_Toggle(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins)
+{
+
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+
+    /* validate the pins */
+    if (!ArePinsValid(Port, Pins))
+    {
+        return (ADI_GPIO_INVALID_PINS);
+    }
+#endif
+
+    pPort = adi_gpio_Device.pReg[Port];
+
+    /* toggle the given GPIOs */
+    pPort->TGL = Pins;
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+
+    @brief      Sets the logic level of all GPIO pins on the given port to
+                a given logic level.
+
+    @details    Sets the logic level of all the GPIO pins on the given port to the
+                given value.
+
+    @param[in]  Port    The GPIO port whose pins logic level to be set.
+    @param[in]  Pins    The GPIO pins whose logic level to be set high. All other 
+                        GPIO pins on the port will be set to a logical low level. 
+                        For example, to set pins 0 and 1 to a logical high level and 
+                        all other pins to a logical low level, this parameter should 
+                        be passed as #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_1.
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS             If successfully set the given data.
+                    - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized.
+                    - #ADI_GPIO_INVALID_PINS    [D] If the given pins are invalid.
+
+    @sa         adi_gpio_SetHigh, adi_gpio_SetLow, adi_gpio_Toggle, adi_gpio_GetData
+*/
+ADI_GPIO_RESULT adi_gpio_SetData(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins)
+{
+
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+
+    /* validate the pins */
+    if (!ArePinsValid(Port, Pins))
+    {
+        return (ADI_GPIO_INVALID_PINS);
+    }
+#endif
+
+    pPort = adi_gpio_Device.pReg[Port];
+
+    /* set the GPIOs as directed */
+    pPort->OUT = Pins;
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+    @brief      Gets/Senses the input level of all GPIO Pins on the given port.
+
+    @details    Gets the level of all GPIO input pins on the given port.
+
+    @param[in]  Port    The GPIO port whose input level to be sensed.
+    @param[in]  Pins    The GPIO pins to be sensed. To sense a single GPIO pin, a single 
+                        GPIO value is passed for this parameter. For example, #ADI_GPIO_PIN_4.
+                        Alternatively, multiple GPIO pins can be configured
+                        simultaneously by OR-ing together GPIO pin values and
+                        passing the resulting value for this parameter. For
+                        example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6.
+    @param[out] pValue  The passed pValue parameter is written with a packed value containing
+                        the status of all the requested GPIO pins on the given port.
+
+    To get the status of a single GPIO pin, return value can be directly used.
+    For example to see if pin 4 on port 2 is a logical high level, the following is used:
+    <pre>
+        adi_gpio_GetData(#ADI_GPIO_PORT2, #ADI_GPIO_PIN_4, &pValue)
+    </pre>
+    pValue will contain the required information.
+
+    If information is required for multiple pins, following method is required:
+    <pre>
+        adi_gpio_GetData(#ADI_GPIO_PORT2, (#ADI_GPIO_PIN_3 | #ADI_GPIO_PIN_4 | #ADI_GPIO_PIN_7), &pValue)
+    </pre>
+
+    To test if pin 4 on port 2 is a logical high level, the following is used:
+    <pre>
+        if  (pValue & ADI_GPIO_PIN_4) {
+            pin 4 on port 2 is a logical high value
+        } else {
+            pin 4 on port 2 is a logical low value
+        }
+    </pre>
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS             If successfully sensed the input pins.
+                    - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized.
+                    - #ADI_GPIO_INVALID_PINS    [D] If the given pins are invalid.
+
+    @sa         adi_gpio_SetHigh, adi_gpio_SetLow, adi_gpio_Toggle, adi_gpio_SetData
+*/
+ADI_GPIO_RESULT adi_gpio_GetData (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, uint16_t* const pValue)
+{
+
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+
+    /* validate the pins */
+    if (!ArePinsValid(Port, Pins))
+    {
+        return (ADI_GPIO_INVALID_PINS);
+    }
+#endif
+
+    pPort = adi_gpio_Device.pReg[Port];
+
+    /* return the status of the GPIOs */
+    *pValue = (pPort->IN) & Pins;
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+    @brief      Register or unregister an application callback function for group (A/B) interrupts.
+
+    @details    Applications may register a callback function that will be called when a
+                GPIO group (A/B) interrupt occurs. 
+                
+                The driver dispatches calls to registered callback functions when the
+                properly configured pin(s) latches an external interrupt input on the GPIO
+                pin(s).  The callback is dispatched with the following parameters, respectively:
+                    - application-provided callback parameter (\a pCBParam),
+                    - The GPIO Port,
+                    - The GPIO Pins.
+
+    @param[in]  eIrq            The interrupt for which the callback is being registered.
+    @param[in]  pfCallback      Pointer to the callback function. This can be passed as NULL to
+                                unregister the callback.
+    @param[in]  pCBParam        Callback parameter which will be passed back to the application
+                                when the callback is called..
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS if successfully registered the callback.
+                    - #ADI_GPIO_NOT_INITIALIZED [D] if not yet initialized
+                    - #ADI_GPIO_INVALID_INTERRUPT [D] if interrupt ID is invalid
+
+    @sa         adi_gpio_SetGroupInterruptPolarity
+*/
+ADI_GPIO_RESULT  adi_gpio_RegisterCallback (const ADI_GPIO_IRQ eIrq, ADI_CALLBACK const pfCallback, void *const pCBParam )
+{
+    uint16_t index = 0u;
+    ADI_INT_STATUS_ALLOC();
+    
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+#endif
+
+    index = (uint16_t)eIrq - (uint16_t)SYS_GPIO_INTA_IRQn + ADI_GPIO_IRQ_GROUPA_INDEX;
+
+    ADI_ENTER_CRITICAL_REGION();
+    
+    adi_gpio_Device.pData->CallbackTable[index].pfCallback = pfCallback;
+    adi_gpio_Device.pData->CallbackTable[index].pCBParam = pCBParam;
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* return the status */
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+
+/*@}*/
+
+/*! \cond PRIVATE */
+/* All of the following is excluded from the doxygen output... */
+
+/* Common group (A/B) interrupt handler */
+static void CommonInterruptHandler(const ADI_GPIO_IRQ_INDEX index, const IRQn_Type eIrq)
+{
+    ADI_GPIO_PORT Port;
+    ADI_GPIO_TypeDef *pPort;
+    ADI_GPIO_DATA Pins;
+    ADI_GPIO_DATA nIntEnabledPins;
+
+    ADI_GPIO_CALLBACK_INFO *pCallbackInfo = &adi_gpio_Device.pData->CallbackTable[index];
+
+    /* Loop over all the ports. */
+    for(Port=ADI_GPIO_PORT0; Port<ADI_GPIO_NUM_PORTS; Port++)
+    {
+        pPort = adi_gpio_Device.pReg[Port];
+
+        /* Is the interrupt is for GROUP A */
+        if(SYS_GPIO_INTA_IRQn == eIrq)
+        {
+            nIntEnabledPins =  pPort->IENA;
+        }
+        else  /* Is the interrupt is for GROUP B */
+        {
+            nIntEnabledPins =  pPort->IENB;
+        }
+
+        /* Clear only required interrupts */
+        Pins = ((pPort->INT) & nIntEnabledPins);
+        pPort->INT = Pins;
+
+        /* params list is: application-registered cbParam, Port number, and interrupt status */
+        if((pCallbackInfo->pfCallback != NULL) && (Pins != 0u))
+        {
+            pCallbackInfo->pfCallback (pCallbackInfo->pCBParam, (uint32_t)Port, &Pins);
+        }
+    }
+}
+
+/* Interrupt A handler */
+void GPIO_A_Int_Handler(void)
+{
+    ISR_PROLOG()
+    CommonInterruptHandler(ADI_GPIO_IRQ_GROUPA_INDEX, SYS_GPIO_INTA_IRQn);
+    ISR_EPILOG()
+}
+
+/* Interrupt B handler */
+void GPIO_B_Int_Handler (void)
+{
+    ISR_PROLOG()
+    CommonInterruptHandler(ADI_GPIO_IRQ_GROUPB_INDEX, SYS_GPIO_INTB_IRQn);
+    ISR_EPILOG()      
+}
+
+#ifdef ADI_DEBUG
+
+
+/*!
+    @brief      Tests a Pins Parameter for Validity
+
+    @details    A debug function that checks a Pins parameter for validity
+
+    @param[in]  Pins    Logical OR-ing of one or more ADI_GPIO_PIN_x values
+
+    @return     Status
+                    - true      the Pins value contains valid data
+                    - false     the Pins value contains invalid data
+*/
+static bool ArePinsValid(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins)
+{
+    uint32_t PinValid = 0u;
+
+    /* test for a valid pin */
+    switch (Port)
+    {
+        case ADI_GPIO_PORT0:
+            PinValid = ~ADI_GPIO_PORT0_PIN_AVL & Pins;
+            break;
+
+        case ADI_GPIO_PORT1:
+            PinValid = ~ADI_GPIO_PORT1_PIN_AVL & Pins;
+            break;
+
+        case ADI_GPIO_PORT2:
+            PinValid = ~ADI_GPIO_PORT2_PIN_AVL & Pins;
+            break;
+#if defined(__ADUCM4x50__)           
+        case ADI_GPIO_PORT3:
+            PinValid = ~ADI_GPIO_PORT3_PIN_AVL & Pins;
+            break;
+#endif /* __ADUCM4x50__ */            
+        default:
+            break;
+    }
+
+    if (PinValid == 0u)
+    {
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+}
+#endif /* ADI_DEBUG */
+
+/*! \endcond  */
+
+/*
+** EOF
+*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/gpio/adi_gpio_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/gpio/adi_gpio_def.h
new file mode 100755
index 00000000000..90282625df8
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/gpio/adi_gpio_def.h
@@ -0,0 +1,94 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_gpio_def.h
+ * @brief:   GPIO Device Driver definition
+ *****************************************************************************
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#ifndef ADI_GPIO_DEF_H
+#define ADI_GPIO_DEF_H
+/*! \cond PRIVATE */
+
+
+/*! local enum for callback table indexing */
+typedef enum
+{
+    /* Group interrupts */
+    ADI_GPIO_IRQ_GROUPA_INDEX     = (0x0),   /*!< GroupA interrupt index.   */
+    ADI_GPIO_IRQ_GROUPB_INDEX     = (0x1),   /*!< GroupB interrupt index.   */
+
+    ADI_GPIO_NUM_INTERRUPTS       = (0x2),   /*!< Number of GPIO interrupts */
+
+} ADI_GPIO_IRQ_INDEX;
+
+
+/*! Structure to hold callback function and parameter */
+typedef struct _ADI_GPIO_CALLBACK_INFO
+{
+    ADI_CALLBACK         pfCallback;    /*!< Callback function pointer */
+    void                 *pCBParam;      /*!< Callback parameter */
+} ADI_GPIO_CALLBACK_INFO;
+
+/*! Structure to hold callback function and parameter */
+typedef struct _ADI_GPIO_DEV_DATA
+{
+    ADI_GPIO_CALLBACK_INFO  CallbackTable[ADI_GPIO_NUM_INTERRUPTS];  /*!< Callback Info for External interrupts */
+} ADI_GPIO_DEV_DATA;
+
+/*! \struct ADI_GPIO_DEVICE
+
+    GPIO instance data
+
+    This structure contains the "state" information for the
+    instance of the device.  For GPIO there is only one
+    of these objects.
+*/
+typedef struct _ADI_GPIO_DRIVER_STRUCT
+{
+	ADI_GPIO_TypeDef            *pReg[ADI_GPIO_NUM_PORTS];          /*!< GPIO Ports Register base          */
+	ADI_GPIO_DEV_DATA           *pData;                             /*!< Pointer to device data            */
+} ADI_GPIO_DRIVER_STRUCT;
+
+
+/* alias for the actual device structure */
+typedef ADI_GPIO_DRIVER_STRUCT      ADI_GPIO_DRIVER;
+
+/*! \endcond */
+#endif /* ADI_GPIO_DEF_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/i2c/adi_i2c.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/i2c/adi_i2c.c
new file mode 100755
index 00000000000..6319177d18c
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/i2c/adi_i2c.c
@@ -0,0 +1,1192 @@
+/*! *****************************************************************************
+ * @file:    adi_i2c.c
+ * @brief:   I2C  device  driver global file.
+ * @details: This a global file which includes a specific file based on the processor family.
+ *           This file contains the I2C device driver functions.
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+/** @addtogroup I2C_Driver I2C Driver
+ *  @{
+ * @brief Inter-Integrated Circuit (I2C) Driver
+ * @details The I2C Master device driver manages the on-chip I2C hardware to
+ * control the external two-wire I2C Bus interface, allowing communication with
+ * multiple I2C slave devices through the I2C slave device addressing scheme.
+ * @note The application must include drivers/i2c/adi_i2c.h to use this driver
+ */
+
+ /*! \cond PRIVATE */
+#include <adi_processor.h>
+#include <assert.h>
+#include <string.h>     /* for "memset" */
+/*! \endcond */
+
+#include <drivers/general/adi_drivers_general.h>
+#include <drivers/i2c/adi_i2c.h>
+
+ /*! \cond PRIVATE */
+
+#include <drivers/pwr/adi_pwr.h>
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+*
+* Pm011 (rule 6.3): Types which specify sign and size should be used
+*   We use bool which is accepted by MISRA but the toolchain does not accept it
+*
+* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
+*   It is used in the _data.h file which isn't a header as such.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+*
+* Pm088 (rule 17.4): pointer arithmetic should not be used.
+*   Relying on pointer arithmetic for buffer handling.
+*
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   The rule makes an exception for memory-mapped register accesses.
+*/
+
+#pragma diag_suppress=Pm011,Pm123,Pm073,Pm143,Pm088,Pm140
+#endif /* __ICCARM__ */
+
+/* pull in internal data structures */
+#include "adi_i2c_data.c"
+
+
+/* handy type-safe zero */
+uint16_t uZero16 = 0u;
+
+/* central busy checker */
+#define I2C_BUSY (uZero16 != ((hDevice->pDev->MSTAT) & (uint16_t)(BITM_I2C_MSTAT_MBUSY | BITM_I2C_MSTAT_LINEBUSY)))
+
+/*!
+ * Read/write bit.
+ */
+ #define READ_NOT_WRITE (1u)
+
+/* Override "weak" default binding in startup.c */
+/*! \cond PRIVATE */
+extern void I2C0_Master_Int_Handler(void);
+
+/* DS4 and DS5 bits of GPIO Port 0 drive strength select register */
+#define I2C_GPIO_PORT0_DS4  ((uint16_t) ((uint16_t) 1<<4))
+#define I2C_GPIO_PORT0_DS5  ((uint16_t) ((uint16_t) 1<<5))
+
+#define ADI_ADUCM302X_CHIPID_SI_1_2             0x284u
+/*! \endcond */
+
+#if defined(ADI_DEBUG)
+/*
+ * Verifies a pointer to a driver points to one of the driver
+ * struct's internal to this file.
+ */
+static bool IsDeviceHandle(ADI_I2C_HANDLE const hDevice);
+static bool IsDeviceHandle(ADI_I2C_HANDLE const hDevice)
+{
+    if ((i2c_device_info[0].hDevice != (hDevice)) && ((hDevice)->pDevInfo->hDevice != NULL)) {
+        return true;
+    } else {
+        return false;
+    }
+}
+#endif
+
+#if defined(__ADUCM302x__)
+static ADI_SYS_REGISTERS  adi_sys_base = { pADI_SYS };
+#endif
+
+/*! \endcond */
+
+
+/**********************************************************************************\
+|**********************************USER INTERFACE**********************************|
+\**********************************************************************************/
+
+
+/*!
+ * @brief  Initialize and allocate an I2C device for use in Master Mode.
+ *
+ * @param[in]   DeviceNum    Zero-based device index designating the I2C device to initialize.
+ *
+ * @param [in]  pMemory      Pointer to a 32-bit aligned buffer of size ADI_I2C_MEMORY_SIZE
+ *                           required by the driver for the operation of specified I2C device.
+ *
+ * @param [in]  MemorySize   Size of the buffer to which "pMemory" points.
+ *
+ * @param[out]  phDevice     The caller's device handle pointer for storing the initialized
+ *                           device instance data pointer.
+ *
+ * @return            Status
+ *                    - #ADI_I2C_SUCCESS                    Call completed successfully.
+ *                    - #ADI_I2C_BAD_DEVICE_NUMBER [D]      Invalid device index.
+ *                    - #ADI_I2C_DEVICE_IN_USE [D]          Device is already opened.
+ *                    - #ADI_I2C_INSUFFICIENT_MEMORY [D]    Device memory is not sufficient.
+ *
+ * Initialize an I2C device using default user configuration settings (from adi_i2c_config.h)
+ * and allocate the device for use.  Device is opened in Master mode only.
+ *
+ * No other I2C APIs may be called until the device open function is called.  The returned
+ * device handle is required to be passed to all subsequent I2C API calls to identify the
+ * physical device instance to use.  The user device handle (pointed to by phDevice) is set
+ * to NULL on failure.
+ *
+ * @note Currently, only a singular I2C physical device instance (device ID "0") exists.
+ *
+ * @sa      adi_spi_Close().
+ */
+ADI_I2C_RESULT adi_i2c_Open (uint32_t const DeviceNum, void* const pMemory, uint32_t const MemorySize, ADI_I2C_HANDLE* const phDevice) {
+
+    /* make a device handle out of the user memory */
+    ADI_I2C_HANDLE hDevice = (ADI_I2C_HANDLE)pMemory;
+  #if defined(__ADUCM302x__)  
+     /*
+     * I2C fix for Silicon Version 1.2 
+     * Enable the drive strength of GPIO pins used for I2C communication. 
+     */
+  
+    /* Get the pointer to the internal structure for System registers*/
+    ADI_SYS_REGISTERS *sys =  &adi_sys_base;
+    
+    if( sys->pReg->CHIPID == ADI_ADUCM302X_CHIPID_SI_1_2 )
+    {
+      *((volatile uint32_t *)REG_GPIO0_DS)  |= ( I2C_GPIO_PORT0_DS4 | I2C_GPIO_PORT0_DS5 );
+    }
+
+   #endif 
+#if defined(ADI_DEBUG)
+    /* check requested device number */
+    if (DeviceNum >= (uint32_t)ADI_I2C_NUM_INSTANCES) {
+        return ADI_I2C_BAD_DEVICE_NUMBER;
+    }
+
+    /* verify device is not already open */
+    if (i2c_device_info[DeviceNum].hDevice != NULL) {
+        return ADI_I2C_DEVICE_IN_USE;
+    }
+
+    /* verify memory size macro value */
+    assert(ADI_I2C_MEMORY_SIZE == sizeof(ADI_I2C_DEV_DATA_TYPE));
+
+    /* verify user-provided memory meets requirement */
+    if ((NULL == pMemory) || (MemorySize < (uint32_t)ADI_I2C_MEMORY_SIZE)) {
+        return ADI_I2C_INSUFFICIENT_MEMORY;
+    }
+#endif
+    
+    /* store a bad handle in case of failure */
+    *phDevice = NULL;
+
+    /*
+     * Link user memory (handle) to ADI_I2C_DEVICE_INFO data structure.
+     *
+     *       ADI_I2C_DEVICE_INFO  <==>   ADI_I2C_HANDLE
+     *
+     * Clear the ADI_I2C_HANDLE memory. This also sets all bool
+     * structure members to false so we do not need to waste cycles
+     * setting these explicitly (e.g. hDevice->bRepearStart = false)
+     */
+    i2c_device_info[DeviceNum].hDevice = (ADI_I2C_DEV_DATA_TYPE *)pMemory;
+    memset(pMemory, 0, MemorySize);
+
+    /* also link device handle within __ADI_I2C_DEV_DATA_TYPE data structure */
+    hDevice->pDevInfo = &i2c_device_info[DeviceNum];
+    /*
+     * Although the ADI_I2C_DEVICE_INFO struct has the physical device pointer
+     * for this instance, copying it to the ADI_I2C_HANDLE struct (in user memory)
+     * will minimize the runtime footprint and cycle count when accessing the I2C
+     * registers.
+     */
+    hDevice->pDev = i2c_device_info[DeviceNum].pDev;
+
+    /* store a pointer to user's static configuration settings */
+    hDevice->pDevInfo->pConfig = (ADI_I2C_CONFIG*)&gConfigInfo[DeviceNum];
+
+    /* create the semaphore */
+    SEM_CREATE(hDevice, "i2c_sem", ADI_I2C_SEMAPHORE_FAILED)
+        ;
+
+    /* reset the driver and HW state */
+    ADI_I2C_RESULT ignore ADI_UNUSED_ATTRIBUTE = i2cReset(hDevice);
+
+    /* store device handle into user handle */
+    *phDevice = (ADI_I2C_HANDLE)hDevice;
+
+    return ADI_I2C_SUCCESS;
+}
+
+
+/*!
+ * @brief  Uninitialize and deallocate an I2C device.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_spi_Open().
+ *
+ * @return      Status
+ *                - #ADI_I2C_SUCCESS                Call completed successfully.
+ *                - #ADI_I2C_BAD_DEVICE_HANDLE [D]  Invalid device handle parameter.
+ *
+ * Uninitialize and release an allocated I2C device, and memory associated with it
+ * for other use.
+ *
+ * @note The user memory is released from use by the I2C driver, but is not freed.
+ *
+ * @sa  adi_spi_Open().
+ */
+ADI_I2C_RESULT adi_i2c_Close (ADI_I2C_HANDLE const hDevice) {
+
+#ifdef ADI_DEBUG
+    if (IsDeviceHandle(hDevice)) {
+        return ADI_I2C_BAD_DEVICE_HANDLE;
+    }
+#endif
+
+    /* destroy semaphore */
+    SEM_DELETE(hDevice,ADI_I2C_SEMAPHORE_FAILED)
+        ;
+
+    /* reset the driver and HW state */
+    ADI_I2C_RESULT ignore ADI_UNUSED_ATTRIBUTE = i2cReset(hDevice);
+
+    /* stub handle */
+    hDevice->pDevInfo->hDevice = NULL;
+
+    return ADI_I2C_SUCCESS;
+}
+
+
+/*!
+ * @brief  Blocking I2C Master-Mode data read/write API.
+ *
+ * @param[in]    hDevice        Device handle obtained from adi_spi_Open().
+ * @param[in]    pTransaction   Pointer to I2C transaction data struct.
+ * @param[out]   pHwErrors      Pointer to hardware error return variable.
+ *
+ * @return       Status
+ *                - #ADI_I2C_SUCCESS                Call completed successfully.
+ *                - #ADI_I2C_BAD_DEVICE_HANDLE [D]  Invalid device handle parameter.
+ *                - #ADI_I2C_DEVICE_IN_USE [D]      An I2C transaction is already underway.
+ *                - #ADI_I2C_INVALID_PARAMETER [D]  Invalid data pointer or count is detected.
+ *                - #ADI_I2C_HW_ERROR_DETECTED      A hardware error occurred, check \a pHwErrors.
+ *
+ * Request a blocking I2C data transfer (read or write, not both as I2C is unidirectional bus)
+ * with or without preceding prologue transmitted.  Control is not returned to the calling
+ * application until the transfer is complete.  Buffer allocations are made by the calling code
+ * (the application).
+ *
+ * The optional prologue (if present) and MANDATORY transaction data pointers are used to read or
+ * write data over the I2C serial bus according to the prologue and data pointers and corresponding
+ * size information contained in the \a pTransaction parameter block.  The most recently set slave
+ * target address (set statically with user configuration settings contained in adi_i2c_config.h file
+ * or set dynamically (at run-time) via the #adi_i2c_SetSlaveAddress() API) is used to address the
+ * specific destination slave device on the I2C bus.
+ *
+ * If present, the prologue (typically, an addressing phase conveying a memory/register address or
+ * slave device command) is transmitted prior to the data read or write phase, with or without
+ * an intervening I2C STOP condition.  The prologue data is entirely slave device dependent.
+ *
+ * In the case of a prologue followed by a data read operation, the I2C bus direction must be
+ * reversed following the prologue transmit.  In this case, The usual I2C STOP condition following
+ * the prologue (if present) transmit may be suppressed by setting the \a bRepeatStart transaction
+ * parameter "true".  In this case, a second (repeat) START condition is "transmitted" between the
+ * addressing phase (prologue transmit) and the data phase of the read sequence... \a without an
+ * intervening STOP condition.  This is commonly referred to as the "combined format" in which the
+ * I2C bus direction is reversed halfway through the transaction without releasing control of the
+ * I2C bus arbitration.  The REPEAT-START condition is a common I2C bus protocol required by many
+ * I2C slave devices.
+ *
+ * In the case of a prologue followed by a data write operation, there is no need to turn the bus
+ * around and so the \a bRepeatStart parameter is ignored.
+ *
+ * @note Application must check the return code to verify if any I2C Bus errors occurred.  Hardware
+ * errors (I2C Protocol errors) are indicated with the #ADI_I2C_HW_ERROR_DETECTED return code, and
+ * the set of hardware errors (enum #ADI_I2C_HW_ERRORS) that occurred (there may be multiple) are
+ * indicated in the value set to user variable pointed to by \a pHwErrors.
+ *
+ * @sa adi_i2c_SetSlaveAddress().
+ * @sa adi_i2c_SubmitBuffer().
+ * @sa adi_i2c_IsBufferAvailable().
+ * @sa adi_i2c_GetBuffer().
+ * @sa ADI_I2C_TRANSACTION.
+ * @sa ADI_I2C_HW_ERRORS.
+ */
+ADI_I2C_RESULT adi_i2c_ReadWrite (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction, uint32_t* const pHwErrors) {
+
+#ifdef ADI_DEBUG
+    if (IsDeviceHandle(hDevice)) {
+        return ADI_I2C_BAD_DEVICE_HANDLE;
+    }
+    if (I2C_BUSY) {
+        return ADI_I2C_DEVICE_IN_USE;
+    }
+    /* NULL transaction data pointer or zero transaction data count */
+    if ((NULL == pTransaction->pData) || (0u == pTransaction->nDataSize)) {
+        return ADI_I2C_INVALID_PARAMETER;
+    }
+#endif
+
+    /* reset submit/get safeguard flag */
+    hDevice->bSubmitCalled = false;
+
+    /* submit/commence the transaction */
+    submitTransaction(hDevice, pTransaction);
+
+    /* block on internal transaction completion/error semaphore */
+    if (ADI_I2C_SUCCESS == hDevice->result) {
+
+        SEM_PEND(hDevice, ADI_I2C_SEMAPHORE_FAILED);
+
+        /* completion interrupt comes as FIFO unloads, but serialization may not be complete yet... */
+        /* must also wait for hardware busy status to clear before giving back control */
+        /* i.e., allow any transmit serialization to complete after last FIFO unload */
+        while (I2C_BUSY) {
+            ;
+        }
+    }
+
+    /* copy out any hardware errors... */
+    *pHwErrors = hDevice->hwErrors;
+    if (0u != hDevice->hwErrors) {
+        /* set the HW error return code */
+        hDevice->result = ADI_I2C_HW_ERROR_DETECTED;
+    }
+
+    /* return transaction result code */
+    return hDevice->result;
+}
+
+
+/*!
+ * @brief  Non-Blocking I2C Master-Mode data read or data write API.
+ *
+ * @param[in]    hDevice        Device handle obtained from adi_spi_Open().
+ * @param[in]    pTransaction   Pointer to I2C transaction data struct.
+ *
+ * @return       Status
+ *                - #ADI_I2C_SUCCESS                Call completed successfully.
+ *                - #ADI_I2C_BAD_DEVICE_HANDLE [D]  Invalid device handle parameter.
+ *                - #ADI_I2C_DEVICE_IN_USE [D]      An I2C transaction is already underway.
+ *                - #ADI_I2C_INVALID_PARAMETER [D]  Invalid data pointer or count is detected.
+ *
+ * Request a non-blocking I2C data transfer (read or write) with or without preceding prologue
+ * transmitted.  Control is returned to the calling application immediately, allowing the application
+ * process other tasks.  The transaction result code is retrieved by #adi_i2c_GetBuffer().
+ *
+ * The application may optionally poll the I2C driver via the #adi_i2c_IsBufferAvailable() API while
+ * the transaction is underway to determine if and when the submitted transaction is complete.
+ * Eventually, the application \a MUST call the \a MANDATORY #adi_i2c_GetBuffer() API to obtain the
+ * transaction result and complete the transaction.  Buffer allocations are made by the calling
+ * code (the application).
+ *
+ * The #adi_i2c_GetBuffer() API may be called at any time, even if the transaction is incomplete;
+ * the #adi_i2c_GetBuffer() call will simply block in incomplete transactions until the
+ * transaction does complete... at which point #adi_i2c_GetBuffer() returns control with
+ * the transaction result code.  Submitting background transactions is useful if the application has
+ * housekeeping chores to perform when the I2C transaction is started, but later the application
+ * decides to just block until the transaction is complete.
+ *
+ * The prologue and data buffers are handled as they are in the blocking #adi_i2c_ReadWrite() call,
+ * it's just that the #adi_i2c_SubmitBuffer() API does not block on the data phase.
+ *
+ * @note The non-blocking #adi_i2c_SubmitBuffer() call \a REQUIRES a matching #adi_i2c_GetBuffer() call
+ * to obtain the final transaction result code and to inform the driver that the application wants to
+ * regain ownership of the buffers.  The application should be prepared to wait for this ownership
+ * until the current transaction completes.  The matching #adi_i2c_GetBuffer() call is required even if
+ * the transaction may have already completed.  The #adi_i2c_GetBuffer() call allows the driver to block
+ * on completion or error events and then synchronize its internal blocking object.  The intermediate
+ * #adi_i2c_IsBufferAvailable() API is optional.\n\n
+ *
+ * @note The #adi_i2c_SubmitBuffer() API is singular, i.e., only a single transaction may be submitted
+ * at a time.  Simultaneous submits (e.g., ping-pong mode) are not supported by the I2C driver.
+ *
+ * @sa adi_i2c_ReadWrite().
+ * @sa adi_i2c_SetSlaveAddress().
+ * @sa adi_i2c_IsBufferAvailable().
+ * @sa adi_i2c_GetBuffer().
+ * @sa ADI_I2C_TRANSACTION.
+ */
+ADI_I2C_RESULT adi_i2c_SubmitBuffer (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction) {
+
+#ifdef ADI_DEBUG
+    if (IsDeviceHandle(hDevice)) {
+        return ADI_I2C_BAD_DEVICE_HANDLE;
+    }
+    if (I2C_BUSY) {
+        return ADI_I2C_DEVICE_IN_USE;
+    }
+    /* NULL transaction data pointer or zero transaction data count */
+    if ((NULL == pTransaction->pData) || (0u == pTransaction->nDataSize)) {
+        return ADI_I2C_INVALID_PARAMETER;
+    }
+#endif
+
+    /* set submit/get safeguard flag */
+    hDevice->bSubmitCalled = true;
+
+    /* submit/commence the transaction */
+    submitTransaction(hDevice, pTransaction);
+
+    /* no blocking on submit... just return the submit result */
+    return hDevice->result;
+}
+
+
+/*!
+ * @brief  Query if a non-blocking I2C transfer is complete.
+ *
+ * @param[in]     hDevice             Device handle obtained from adi_spi_Open().
+ * @param[out]    pbCompletionState   Pointer to Boolean into which the I2C bus state is written.
+ *
+ * @return         Status
+ *                - #ADI_I2C_SUCCESS                Call completed successfully.
+ *                - #ADI_I2C_BAD_DEVICE_HANDLE [D]  Invalid device handle parameter.
+ *                - #ADI_I2C_INVALID_SUBMIT_API     No matching submit call.
+ *
+ * Sets the application-provided Boolean variable pointed to by pbCompletionState either:
+ *     - true, when the non-blocking transactions is complete, or
+ *     - false, while the non-blocking transactions is still underway.
+ *
+ * This API is used in conjunction with a non-blocking #adi_i2c_SubmitBuffer() transfer to
+ * determine when the transaction is complete.  Typically, non-blocking calls are used when the
+ * calling application has other work to do while I2C controller serializes data over the I2C bus,
+ * which is an interrupt-driven process.  The transaction is submitted as a non-blocking call and
+ * the submitting API returns immediately, allowing the calling application to perform its other tasks.
+ * The I2C driver services the interrupts to transfer data while the application performs its
+ * other tasks.
+ *
+ * Non-blocking calls can be polled with this API for completion, or if the application has completed
+ * its other tasks and wants to just wait on the I2C completion without further polling, it may call
+ * the associated #adi_i2c_GetBuffer() API to convert the currently unblocked transaction to
+ * a blocking one.
+ *
+ * @note This API is inappropriate in context of blocking calls to #adi_i2c_ReadWrite().
+ *
+ * @sa adi_i2c_ReadWrite().
+ * @sa adi_i2c_SubmitBuffer().
+ * @sa adi_i2c_GetBuffer().
+ * @sa ADI_I2C_TRANSACTION.
+ */
+ADI_I2C_RESULT adi_i2c_IsBufferAvailable (ADI_I2C_HANDLE const hDevice, bool* const pbCompletionState) {
+
+#ifdef ADI_DEBUG
+    if (IsDeviceHandle(hDevice)) {
+        return ADI_I2C_BAD_DEVICE_HANDLE;
+    }
+#endif
+
+    /* fail if not a submit-based transaction */
+    if (false == hDevice->bSubmitCalled) {
+        return ADI_I2C_INVALID_SUBMIT_API;
+    }
+
+    /* return true when bus goes quiet */
+    if (I2C_BUSY) {
+        *pbCompletionState = false;
+    } else {
+        *pbCompletionState = true;
+    }
+
+    return ADI_I2C_SUCCESS;
+}
+
+
+/*!
+ * @brief  Request ownership of a submitted buffer.
+ *
+ * @param[in]     hDevice             Device handle obtained from adi_spi_Open().
+ * @param[out]    pHwErrors           Pointer to hardware error return variable.
+ *
+ * @return         Status
+ *                - #ADI_I2C_SUCCESS                Call completed successfully.
+ *                - #ADI_I2C_BAD_DEVICE_HANDLE [D]  Invalid device handle parameter.
+ *                - #ADI_I2C_INVALID_SUBMIT_API     No matching submit call.
+ *                - #ADI_I2C_HW_ERROR_DETECTED      A hardware error occurred, check \a pHwErrors.
+ *
+ * This is a potentially blocking MANDATORY call that the application MUST use to reclaim
+ * ownership of any "submitted" transaction (submitted via a previous #adi_i2c_SubmitBuffer()
+ * call) and obtain the transaction success/failure result code.  This API blocks until the
+ * transaction is complete and returns the transaction result code.  If the transaction is
+ * already complete, the blocking is trivial and control is returned immediately.
+ *
+ * Non-blocking calls can also be (optionally) polled with the non-blocking
+ * #adi_i2c_IsBufferAvailable() API to see if and when the transaction is complete.
+ *
+ * The #adi_i2c_GetBuffer() call is a MANDATORY compliment to #adi_i2c_SubmitBuffer() and
+ * allows the I2C driver to synchronize its internal blocking object.
+ *
+ * @note Application must check the return code to verify if any I2C Bus errors occurred.  Hardware
+ * errors (I2C Protocol errors) are indicated with the #ADI_I2C_HW_ERROR_DETECTED return code, and
+ * the set of hardware errors (enum #ADI_I2C_HW_ERRORS) that occurred (there may be multiple) are
+ * indicated in the value set to user variable pointed to by \a pHwErrors.
+ *
+ * @sa adi_i2c_ReadWrite().
+ * @sa adi_i2c_SubmitBuffer().
+ * @sa adi_i2c_IsBufferAvailable().
+ * @sa ADI_I2C_TRANSACTION.
+ * @sa ADI_I2C_HW_ERRORS.
+ */
+ADI_I2C_RESULT adi_i2c_GetBuffer (ADI_I2C_HANDLE const hDevice, uint32_t* const pHwErrors) {
+
+#ifdef ADI_DEBUG
+    if (IsDeviceHandle(hDevice)) {
+        return ADI_I2C_BAD_DEVICE_HANDLE;
+    }
+#endif
+
+    /* fail if not a submit-based transaction */
+    if (false == hDevice->bSubmitCalled) {
+        return ADI_I2C_INVALID_SUBMIT_API;
+    }
+
+    /* block until complete or error interrupt sets the semaphore */
+    SEM_PEND(hDevice, ADI_I2C_SEMAPHORE_FAILED);
+
+    /* delay until bus goes quiet */
+    while (I2C_BUSY) {
+        ;
+    }
+
+    /* copy out any hardware errors... */
+    *pHwErrors = hDevice->hwErrors;
+    if (0u != hDevice->hwErrors) {
+        /* set the HW error return code */
+        hDevice->result = ADI_I2C_HW_ERROR_DETECTED;
+    }
+
+    /* return transaction result code */
+    return hDevice->result;
+}
+
+/*!
+ * @brief  Reset an I2C device and driver instance.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_spi_Open().
+ *
+ * @return      Status
+ *                - #ADI_I2C_SUCCESS                Call completed successfully.
+ *                - #ADI_I2C_BAD_DEVICE_HANDLE [D]  Invalid device handle parameter.
+ *
+ * Reset the I2C physical controller and device driver internals.
+ */
+ADI_I2C_RESULT adi_i2c_Reset (ADI_I2C_HANDLE const hDevice) {
+
+#ifdef ADI_DEBUG
+    if (IsDeviceHandle(hDevice)) {
+        return ADI_I2C_BAD_DEVICE_HANDLE;
+    }
+#endif
+
+    /* destroy/recreate the semaphore to force a clear state */
+    SEM_DELETE(hDevice, ADI_I2C_SEMAPHORE_FAILED)
+        ;
+    SEM_CREATE(hDevice, "i2c_sem", ADI_I2C_SEMAPHORE_FAILED)
+        ;
+
+    /* reset the driver and HW state */
+    return i2cReset(hDevice);
+}
+
+
+/*!
+ * @brief  Set the I2C serial bus speed.
+ *
+ * @param[in]     hDevice             Device handle obtained from adi_spi_Open().
+ * @param[in]     requestedBitRate32  Requested I2C bus clock rate (in Hz).
+ *
+ * @return         Status
+ *                - #ADI_I2C_SUCCESS                Call completed successfully.
+ *                - #ADI_I2C_BAD_DEVICE_HANDLE [D]  Invalid device handle parameter.
+ *                - #ADI_I2C_DEVICE_IN_USE [D]      Device is busy.
+ *                - #ADI_I2C_BAD_SYS_CLOCK          Failure to obtain the current PCLK rate.
+ *                - #ADI_I2C_BAD_BITRATE            Requested clock speed exceeds operational specification.
+ *
+ * Sets the I2C bus clock speed to the requested user parameter, \a requestedBitRate.
+ *
+ * @note Any I2C Bus clock rate may be requested up to and including the "FAST" mode I2C clock
+ * rate (400 kHz), including the "STANDARD" mode (100 kHz).  Faster clock rates beyond "FAST"
+ * mode (e.g., "FAST+" or "HIGH-SPEED" modes) are not supported by the hardware.  Slower clock
+ * rates below approximately 55 kHz (assuming a 26 MHz system clock) are physically unrealizable
+ * due to the fixed 8-bit field-width of the 8-bit I2C clock rate divide register.\n\n
+ *
+ * @note Default clock rate may be specified statically in the default user configuration file,
+ * "adi_i2c_config.h".
+ */
+ADI_I2C_RESULT adi_i2c_SetBitRate (ADI_I2C_HANDLE const hDevice, uint32_t const requestedBitRate32) {
+
+    uint32_t clockFrequency32, halfClock32;
+    uint16_t halfClock16;
+    uint16_t highTime16, lowTime16;
+
+#ifdef ADI_DEBUG
+    if (IsDeviceHandle(hDevice)) {
+        return ADI_I2C_BAD_DEVICE_HANDLE;
+    }
+    if (I2C_BUSY) {
+        return ADI_I2C_DEVICE_IN_USE;
+    }
+#endif
+
+    /* get input clockrate from power service */
+    if (ADI_PWR_SUCCESS != adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &clockFrequency32)) {
+        return ADI_I2C_BAD_SYS_CLOCK;
+    }
+
+    /* block requests above max rated 400kHz operation */
+    if (ADI_I2C_MAX_RATE < requestedBitRate32) {
+        return ADI_I2C_BAD_BITRATE;
+    }
+
+    /* compute half-cycle period in 32-bits (">>1" is divide by 2) */
+    halfClock32 = (clockFrequency32 / requestedBitRate32) >> 1;  /* HRM equation */
+
+    /* downcast to 16-bit to match destination field */
+    halfClock16 = (uint16_t)(halfClock32 & 0x0000ffffu);
+
+    /* check for lost precision in conversion */
+    if (halfClock32 != halfClock16) {
+        return ADI_I2C_BAD_BITRATE;
+    }
+
+    /* adjust high and low durations per HRM */
+    highTime16 = halfClock16 - 7u;  /* empirical: varies with board layout, pullups, etc */
+    lowTime16  = halfClock16 - 1u;
+
+    /* shift values into their clock rate divider register positions */
+    highTime16 <<= BITP_I2C_DIV_HIGH;
+    lowTime16  <<= BITP_I2C_DIV_LOW;
+
+    /* check for divider overflows beyond designated (8-bit) field masks */
+    if (    (uZero16 != ((uint16_t)highTime16 & (uint16_t)(~(BITM_I2C_DIV_HIGH))))
+            ||
+            (uZero16 != ((uint16_t)lowTime16 & (uint16_t)(~(BITM_I2C_DIV_LOW))))
+       ) {
+       return ADI_I2C_BAD_BITRATE;
+    }
+
+    /* program new values */
+    hDevice->pDev->DIV = highTime16 | lowTime16;
+
+    return ADI_I2C_SUCCESS;
+}
+
+
+/*!
+ * @brief  Set the I2C serial bus slave address.
+ *
+ * @param[in]     hDevice             Device handle obtained from adi_spi_Open().
+ * @param[in]     SlaveAddress        New 7-bit address for targeting a slave device.
+ *
+ * @return         Status
+ *                - #ADI_I2C_SUCCESS                Call completed successfully.
+ *                - #ADI_I2C_BAD_DEVICE_HANDLE [D]  Invalid device handle parameter.
+ *                - #ADI_I2C_DEVICE_IN_USE [D]      Device is busy.
+ *                - #ADI_I2C_INVALID_SLAVE_ADDRESS  Slave address exceeds the 7-bit limit.
+ *
+ * Sets the 7-bit (unformatted) slave address for which all subsequent I2C bus traffic is directed.
+ * Read/write address formatting is performed by the driver, depending on bus direction.
+ *
+ * @note This driver does not support the I2C 10-bit extended addressing scheme.\n\n
+ *
+ * @note Default slave address may be specified statically in the default user configuration file,
+ * "adi_i2c_config.h".
+ */
+ADI_I2C_RESULT adi_i2c_SetSlaveAddress (ADI_I2C_HANDLE const hDevice, uint16_t const SlaveAddress) {
+
+#ifdef ADI_DEBUG
+    if (IsDeviceHandle(hDevice)) {
+        return ADI_I2C_BAD_DEVICE_HANDLE;
+    }
+    if (I2C_BUSY) {
+        return ADI_I2C_DEVICE_IN_USE;
+    }
+#endif
+
+    /* verify no slave address bits fall outside the 7-bit addressing model (10-bit addressing not supported) */
+    if (uZero16 != (SlaveAddress & (uint16_t)(~(BITM_I2C_ADDR1_VALUE >> 1)))) {
+        return ADI_I2C_INVALID_SLAVE_ADDRESS;
+    }
+
+    /* save new address */
+    hDevice->i2cDeviceAddress = SlaveAddress;
+
+    return ADI_I2C_SUCCESS;
+}
+
+
+/*!
+ * @brief  Transmit a General Call command to all slave devices on the I2C bus.
+ *
+ * @param[in]     hDevice            Device handle obtained from adi_spi_Open().
+ * @param[in]     pData              Pointer to data buffer to transmit.
+ * @param[in]     nDataSize          Size of data buffer to transmit.
+ * @param[out]    pHwErrors          Pointer to hardware error return variable.
+ *
+ * @return         Status
+ *                - #ADI_I2C_SUCCESS                Call completed successfully.
+ *                - #ADI_I2C_BAD_DEVICE_HANDLE [D]  Invalid device handle parameter.
+ *                - #ADI_I2C_DEVICE_IN_USE [D]      Device is busy.
+ *
+ * Broadcasts the given command buffer across the I2C bus to reserved General Call (GC)
+ * address (address zero).  All, some, or none of the slave devices on the I2C bus will
+ * respond, depending on their capabilities.  All responding slave devices will process
+ * the GC command according to their capabilities.
+ *
+ * The GC command is a blocking transaction.
+ *
+ * The application is responsible for formatting the GC command into the data buffer
+ * according to various Philips Semiconductor (now, NXP) documents, such as the 2014
+ * Revision 6 document: "UM10204 I2C-Bus Specification and User Manual"
+ * (see www.nxp.com/documents/user_manual/UM10204.pdf).
+ *
+ * No prologue precedes the GC command data; the GC command data is transmitted verbatim.
+ *
+ * @note The currently active slave address is saved and restored when transmitting GC
+ * commands to the reserved GC address (address zero).
+ *
+ */
+ADI_I2C_RESULT adi_i2c_IssueGeneralCall (ADI_I2C_HANDLE const hDevice, uint8_t* const pData, uint8_t const nDataSize, uint32_t* const pHwErrors) {
+
+	ADI_I2C_RESULT result;
+	ADI_I2C_TRANSACTION xfr;
+
+#ifdef ADI_DEBUG
+    if (IsDeviceHandle(hDevice)) {
+        return ADI_I2C_BAD_DEVICE_HANDLE;
+    }
+    if (I2C_BUSY) {
+        return ADI_I2C_DEVICE_IN_USE;
+    }
+#endif
+
+    /* force general call reserved target address of zero */
+    uint16_t savedSlaveAddress = hDevice->i2cDeviceAddress;
+    hDevice->i2cDeviceAddress = 0u;
+
+    /* setup the transfer */
+    xfr.pPrologue        = NULL;
+    xfr.nPrologueSize    = 0u;
+    xfr.pData            = pData;
+    xfr.nDataSize        = nDataSize;
+    xfr.bReadNotWrite    = false;
+    xfr.bRepeatStart     = false;
+
+    /* dispatch as a blocking transmit call */
+    result = adi_i2c_ReadWrite(hDevice, &xfr, pHwErrors);
+
+    /* always restore saved slave address */
+    hDevice->i2cDeviceAddress = savedSlaveAddress;
+
+    if (ADI_I2C_SUCCESS != result) {
+		return result;  /* read/write failure... */
+	} else {
+		return hDevice->result;  /* actual result */
+	}
+}
+
+
+ /*! \cond PRIVATE */
+
+
+/**********************************************************************************\
+|*****************************static helper functions******************************|
+\**********************************************************************************/
+
+static void submitTransaction(ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction) {
+
+    /* reset internal return code */
+    hDevice->result = ADI_I2C_SUCCESS;
+
+    /* reset hardware error code */
+    hDevice->hwErrors = ADI_I2C_HW_ERROR_NONE;
+
+    /* wait for HW to be ready */
+    while (I2C_BUSY) {
+        ;
+    }
+
+    /* save common user parameters */
+    hDevice->pNextPrologueByte      = pTransaction->pPrologue;
+    hDevice->remainingPrologueCount = pTransaction->nPrologueSize;
+    hDevice->bRepeatStart           = pTransaction->bRepeatStart;
+
+    /* encode (mask and upshift) the slave address, leaving room for the r/w control bit (LSB) */
+    hDevice->i2cEncodedDeviceAddress = (hDevice->i2cDeviceAddress & (BITM_I2C_ADDR1_VALUE >> 1)) << 1;
+
+    /* dispatch */
+    if (pTransaction->bReadNotWrite) {
+
+        /* setup read parameters */
+        hDevice->pNextReadByte           = pTransaction->pData;
+        hDevice->remainingReadCount      = pTransaction->nDataSize;
+        hDevice->pNextWriteByte          = NULL;
+        hDevice->remainingWriteCount     = 0u;
+
+        /* set read bit */
+        hDevice->i2cEncodedDeviceAddress |= READ_NOT_WRITE;
+
+        /* commence receive */
+        commenceReceive(hDevice);
+
+    } else {
+
+        /* setup write parameters */
+        hDevice->pNextReadByte           = NULL;
+        hDevice->remainingReadCount      = 0u;
+        hDevice->pNextWriteByte          = pTransaction->pData;
+        hDevice->remainingWriteCount     = pTransaction->nDataSize;
+
+        /* clear read bit */
+        hDevice->i2cEncodedDeviceAddress &= (~READ_NOT_WRITE);
+
+        /* commence transmit */
+        commenceTransmit(hDevice);
+    }
+}
+
+
+static void commenceTransmit(ADI_I2C_HANDLE const hDevice) {
+
+    /* transmit is always pure transmit, whether we have a prologue or not... */
+
+    /* enable PIO interrupts */
+    NVIC_EnableIRQ(hDevice->pDevInfo->pioIRQn);
+
+    /* enable i2c for PIO-based transmit interrupts */
+    hDevice->pDev->MCTL |= (BITM_I2C_MCTL_IENMTX | BITM_I2C_MCTL_MASEN);
+
+    /* how many bytes are available in the transmit FIFO (2-deep) */
+    uint16_t writableBytes = 2u - (hDevice->pDev->MSTAT & (uint16_t)BITM_I2C_MSTAT_MTXF);
+
+    /* prime transmit FIFO with any prologue data */
+    while ((0u < writableBytes) && (hDevice->remainingPrologueCount)) {
+        hDevice->pDev->MTX = *hDevice->pNextPrologueByte;
+        hDevice->pNextPrologueByte++;
+        hDevice->remainingPrologueCount--;
+        writableBytes--;
+    }
+
+    /* flesh out any remaining FIFO space with transmit data */
+    while ((0u < writableBytes) && (hDevice->remainingWriteCount)) {
+        hDevice->pDev->MTX = *hDevice->pNextWriteByte;
+        hDevice->pNextWriteByte++;
+        hDevice->remainingWriteCount--;
+        writableBytes--;
+    }
+
+    /* launch the transmit */
+    hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress;
+}
+
+
+/* initiate receive addressing phase */
+static void commenceReceive(ADI_I2C_HANDLE const hDevice) {
+
+    /* receive can be either pure receive (no prologue),
+       or a transmit (of prologue) followed by a receive */
+
+    /* enable PIO interrupts */
+    NVIC_EnableIRQ(hDevice->pDevInfo->pioIRQn);
+
+    /* enable i2c for PIO-based receive interrupts */
+    hDevice->pDev->MCTL |= (uint16_t)(BITM_I2C_MCTL_IENMRX | BITM_I2C_MCTL_MASEN);
+
+    /* program HW receive count */
+    if (hDevice->remainingReadCount  > BITM_I2C_MRXCNT_EXTEND) {
+        hDevice->pDev->MRXCNT        = BITM_I2C_MRXCNT_EXTEND;
+        hDevice->remainingReadCount -= BITM_I2C_MRXCNT_EXTEND;
+    } else {
+        hDevice->pDev->MRXCNT        = hDevice->remainingReadCount - 1u;
+        hDevice->remainingReadCount  = 0u;
+    }
+
+    /* if we have prologue (the dreaded "COMBINED FORMAT"), transmit the prologue prior to data receive... */
+    if (hDevice->remainingPrologueCount) {
+
+        /* -OR- in transmit interrupt enable if we have prologue data to send */
+        hDevice->pDev->MCTL |= BITM_I2C_MCTL_IENMTX;
+
+        /* how many bytes are available in the transmit FIFO (should be 2) */
+        uint16_t writableBytes = 2u - (hDevice->pDev->MSTAT & (uint16_t)BITM_I2C_MSTAT_MTXF);
+
+        /* prime transmit FIFO with any prologue data (memory address or command) first */
+        while ((0u < writableBytes) && (hDevice->remainingPrologueCount)) {
+            hDevice->pDev->MTX = *hDevice->pNextPrologueByte;
+            hDevice->pNextPrologueByte++;
+            hDevice->remainingPrologueCount--;
+            writableBytes--;
+        }
+
+        /* initiate prologue transmit with read bit cleared (for prologue write) */
+        /* (read sequence is initiated by transmit handler, *after* prologue is transmitted...) */
+        hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress & (uint16_t)(~READ_NOT_WRITE);
+
+    } else {
+
+        /* no prologue... initiate pure receive (read bit already set) */
+        hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress;
+    }
+}
+
+
+/* reset the I2C HW */
+static ADI_I2C_RESULT i2cReset(ADI_I2C_HANDLE const hDevice) {
+
+	volatile uint16_t temp;
+    /* disable interrupts */
+    NVIC_DisableIRQ(hDevice->pDevInfo->pioIRQn);
+
+    /* reset any pending interrupts and TX FIFO (W1C) */
+    temp = hDevice->pDev->MSTAT;
+    hDevice->pDev->MSTAT = temp;
+
+    /* discard any rogue RX FIFO data */
+    while (uZero16 != (hDevice->pDev->STAT & (uint16_t)BITM_I2C_STAT_MRXF)) {
+        volatile uint16_t delme ADI_UNUSED_ATTRIBUTE = hDevice->pDev->MTX;
+    }
+
+    /* reset i2c control register */
+    hDevice->pDev->MCTL = 0u;
+
+    /* reset repeat start logic */
+    hDevice->pDev->SHCTL = 1u;
+
+    /* (re)assert controller defaults from user config values */
+    hDevice->pDev->MCTL         = hDevice->pDevInfo->pConfig->MasterControlRegister;
+    hDevice->pDev->DIV          = hDevice->pDevInfo->pConfig->ClockDividerRegister;
+    hDevice->pDev->SHCTL        = hDevice->pDevInfo->pConfig->SharedControlRegister;
+    hDevice->pDev->TCTL         = hDevice->pDevInfo->pConfig->TimingControlRegister;
+    hDevice->pDev->ASTRETCH_SCL = hDevice->pDevInfo->pConfig->ClockStretchRegister;
+    hDevice->i2cDeviceAddress   = hDevice->pDevInfo->pConfig->TargetSlaveAddress;
+
+    return ADI_I2C_SUCCESS;
+}
+
+
+/**********************************************************************************\
+|********************************interrupt handlers********************************|
+\**********************************************************************************/
+
+
+/* transmit interrupt handler */
+static void transmitHandler(ADI_I2C_HANDLE const hDevice) {
+
+    /* how much room in transmit FIFO? */
+    /* DO ***NOT*** USE MSTAT:MTXF... FALSELY INDICATES MOSTLY FULL FIFO! */
+    uint16_t writableBytes = 2u - ((hDevice->pDev->STAT & (uint16_t)BITM_I2C_STAT_MTXF) >> BITP_I2C_STAT_MTXF);
+
+    /* for extended prologues, continue pushing prologue data out */
+    while ((0u < writableBytes) && (hDevice->remainingPrologueCount)) {
+        hDevice->pDev->MTX = *hDevice->pNextPrologueByte;
+        hDevice->pNextPrologueByte++;
+        hDevice->remainingPrologueCount--;
+        writableBytes--;
+    }
+
+    /* once the prologue is done... */
+    if (0u == hDevice->remainingPrologueCount) {
+
+        /* if we have a completed prologue associated with a read sequence...  */
+        if (0u < hDevice->remainingReadCount) {
+
+            /* initiate the read (subsequently driven by receive interrupt handler) */
+            hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress;
+
+        } else {
+
+            /* normal transmit interrupt: just push transmit data */
+            while ((0u < writableBytes) && (hDevice->remainingWriteCount)) {
+                hDevice->pDev->MTX = *hDevice->pNextWriteByte;
+                hDevice->pNextWriteByte++;
+                hDevice->remainingWriteCount--;
+                writableBytes--;
+            }
+        }
+    }
+
+    /* clear TX interrupt as we complete transmit writes */
+    if (0u == hDevice->remainingWriteCount) {
+        hDevice->pDev->MSTAT = BITM_I2C_MSTAT_MTXREQ;
+    }
+}
+
+
+/* receive interrupt handler */
+static void receiveHandler(ADI_I2C_HANDLE const hDevice) {
+
+    /* note: we never need to deal with prologue data here... it will already be transmitted... */
+
+    /* how many bytes in receive FIFO? */
+    uint16_t readableBytes = (hDevice->pDev->STAT & (uint16_t)BITM_I2C_STAT_MRXF) >> BITP_I2C_STAT_MRXF;
+
+    /* pull bytes from fifo */
+    while (0u < readableBytes) {
+
+        readableBytes--;
+
+        /* pull one byte */
+        *hDevice->pNextReadByte = (uint8_t)hDevice->pDev->MRX;
+        hDevice->pNextReadByte++;
+
+        if ((0u == hDevice->pDev->MCRXCNT) && (hDevice->remainingReadCount)) {
+
+            /* if HW read counter goes to zero with remaining data to read, reprogram read count */
+            if (hDevice->remainingReadCount  > BITM_I2C_MRXCNT_EXTEND) {
+                /* use extended count flag for large remaining counts... */
+                hDevice->pDev->MRXCNT        = BITM_I2C_MRXCNT_EXTEND;
+                hDevice->remainingReadCount -= BITM_I2C_MRXCNT_EXTEND;
+            } else {
+                /* new count fits... no need for extended count */
+                hDevice->pDev->MRXCNT        = hDevice->remainingReadCount - 1u;
+                hDevice->remainingReadCount  = 0u;
+            }
+        }
+    }
+}
+
+/* completion interrupt handler */
+static void completeHandler(ADI_I2C_HANDLE const hDevice) {
+
+    /* block on busy until all transmit data has both left
+       the fifo AND has been fully serialized to the bus. */
+    while (I2C_BUSY) {
+        ;
+    }
+
+    /* disable interrupts */
+    NVIC_DisableIRQ(hDevice->pDevInfo->pioIRQn);
+
+    /* reset controller to default user config state */
+    hDevice->pDev->MCTL = (uint16_t)gConfigInfo->MasterControlRegister;
+}
+
+
+/* error interrupt handler */
+static void errorHandler(ADI_I2C_HANDLE const hDevice) {
+
+    /* accumulate I2C bus errors */
+
+    if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_NACKADDR)) {
+        hDevice->hwErrors |= ADI_I2C_HW_ERROR_NACK_ADDR;
+    }
+
+    if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_NACKDATA)) {
+        hDevice->hwErrors |= ADI_I2C_HW_ERROR_NACK_DATA;
+    }
+
+    if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_ALOST)) {
+        hDevice->hwErrors |= ADI_I2C_HW_ERROR_ARBITRATION_LOST;
+    }
+
+    /* if no other errors exist, note we had an unexpected error */
+    if (hDevice->hwErrors == ADI_I2C_HW_ERROR_NONE) {
+        hDevice->hwErrors = ADI_I2C_HW_ERROR_UNEXPECTED_ERROR;
+    }
+}
+
+
+/**********************************************************************************\
+|*****************************I2C INTERRUPT HANDLER********************************|
+\**********************************************************************************/
+
+
+/* PIO mode I2C interrupt handler */
+void I2C0_Master_Int_Handler(void) {
+
+    bool bPost = false;
+
+    /* rtos prologue */
+    ISR_PROLOG()
+        ;
+
+    /* recover device handle */
+    ADI_I2C_HANDLE const hDevice = (ADI_I2C_HANDLE)i2c_device_info[0].hDevice;
+
+    /* save destructive status read... */
+    hDevice->hwStatus = hDevice->pDev->MSTAT;
+
+    /* if RepeatStart request is pending, rewrite address register ASAP (and only once) to block stop bit */
+    if (hDevice->bRepeatStart) {
+        hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress;
+        hDevice->bRepeatStart = false;  /* just do it once on 1st interrupt */
+    }
+
+    /* forward TX interrupts to TX handler */
+    if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_MTXREQ)) {
+        transmitHandler(hDevice);
+    }
+
+    /* forward RX interrupts to RX handler */
+    if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_MRXREQ)) {
+        receiveHandler(hDevice);
+    }
+
+    /* dispatch any errors */
+    if (uZero16 != (hDevice->hwStatus & ADI_I2C_STATUS_ERROR_MASK)) {
+        errorHandler(hDevice);
+
+      /* post on bus error */
+      bPost = true;
+    }
+
+    /* transmit complete */
+    if (uZero16 != (hDevice->hwStatus & BITM_I2C_MSTAT_TCOMP)) {
+        completeHandler(hDevice);
+
+      /* post on completion */
+      bPost = true;
+    }
+
+    /* just post once */
+    if (true == bPost) {
+        SEM_POST(hDevice);
+    }
+
+    /* rtos epilogue */
+    ISR_EPILOG()
+        ;
+}
+
+/*! \endcond */
+
+
+/* @} */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/i2c/adi_i2c_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/i2c/adi_i2c_data.c
new file mode 100755
index 00000000000..ebd22ecb97f
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/i2c/adi_i2c_data.c
@@ -0,0 +1,121 @@
+/*
+ *****************************************************************************
+ * @file:    adi_i2c_data.c
+ * @brief:   Data declaration for I2C Device Driver
+ *****************************************************************************
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be coni2ccuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_I2C_DATA_C
+#define ADI_I2C_DATA_C
+
+ /*! \cond PRIVATE */
+
+#include <adi_processor.h>
+#include "adi_i2c_def.h"
+#include "adi_i2c_config.h"
+
+
+/* Stores the information about the specific device */
+static ADI_I2C_DEVICE_INFO i2c_device_info [ADI_I2C_NUM_INSTANCES] =
+{
+    /* fixed instance data for the singular I2C0 controller */
+    {
+        I2C_MST_EVT_IRQn,              /* pio interrupt number         */
+        (ADI_I2C_TypeDef *)pADI_I2C0,  /* i2c controller pointer       */
+        NULL,                          /* pointer to user config data  */
+        NULL                           /* i2c device handle (user mem) */
+    },
+
+    /* no other i2c instances at this time */
+};
+
+/* build I2C Application configuration array */
+static ADI_I2C_CONFIG gConfigInfo[ADI_I2C_NUM_INSTANCES] =
+{
+    /* the one-and-only (so far) instance data for I2C, I2C0... */
+    {
+        /**** I2C_MCTL Master Control register *** */
+        (
+            /* note: Master IENMTX and IENMRX (transmit and receive interrupts) are managed dynamically */
+            ( ADI_I2C_CFG_MCTL_MXMITDEC     << BITP_I2C_MCTL_MXMITDEC     ) |
+            ( ADI_I2C_CFG_MCTL_IENCMP       << BITP_I2C_MCTL_IENCMP       ) |
+            ( ADI_I2C_CFG_MCTL_IENACK       << BITP_I2C_MCTL_IENACK       ) |
+            ( ADI_I2C_CFG_MCTL_IENALOST     << BITP_I2C_MCTL_IENALOST     ) |
+            ( ADI_I2C_CFG_MCTL_STRETCHSCL   << BITP_I2C_MCTL_STRETCHSCL   ) |
+            ( ADI_I2C_CFG_MCTL_LOOPBACK     << BITP_I2C_MCTL_LOOPBACK     ) |
+            ( ADI_I2C_CFG_MCTL_COMPLETE     << BITP_I2C_MCTL_COMPLETE     ) |
+            ( ADI_I2C_CFG_MCTL_MASEN        << BITP_I2C_MCTL_MASEN        )
+        ),
+
+        /**** I2C_DIV Clock Divider register *** */
+        (
+            ( ADI_I2C_CFG_DIV_HIGH          << BITP_I2C_DIV_HIGH          ) |
+            ( ADI_I2C_CFG_DIV_LOW           << BITP_I2C_DIV_LOW           )
+        ),
+
+        /**** I2C_SHCTL Shared Control register *** */
+        (
+            ( ADI_I2C_CFG_SHCTL_RST         << BITP_I2C_TCTL_FILTEROFF    )
+        ),
+
+        /**** I2C_TCTL Timing control register *** */
+        (
+            ( ADI_I2C_CFG_TCTL_FILTEROFF    << BITP_I2C_SHCTL_RST         ) |
+            ( ADI_I2C_CFG_TCTL_THDATIN      << BITP_I2C_TCTL_THDATIN      )
+        ),
+
+        /**** I2C_ASTRETCH Master Clock Stretch register *** */
+        (
+            ( ADI_I2C_CFG_ASTRETCH_MST      << BITP_I2C_ASTRETCH_SCL_MST  )
+        ),
+
+        /**** Target Slave configuration value (not a register) *** */
+        (
+            ( ADI_I2C_CFG_SLAVE_ADDRESS                                   )
+        ),
+    }
+};
+
+/*! \endcond */
+
+
+#endif /* ADI_I2C_DATA_C */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/i2c/adi_i2c_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/i2c/adi_i2c_def.h
new file mode 100755
index 00000000000..bbf8bc57cba
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/i2c/adi_i2c_def.h
@@ -0,0 +1,141 @@
+/*!
+ *****************************************************************************
+ @file:    adi_i2c_def.h
+ @brief:   Internal I2C device driver definitions and macros
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+#ifndef ADI_I2C_DEF_H
+#define ADI_I2C_DEF_H
+
+/*! \cond PRIVATE */
+
+#include <drivers/i2c/adi_i2c.h>
+
+#define ADI_I2C_NUM_INSTANCES       (1u)
+#define ADI_I2C_STATUS_ERROR_MASK ( (1u << BITP_I2C_MSTAT_NACKADDR) \
+                                  | (1u << BITP_I2C_MSTAT_NACKDATA) \
+                                  | (1u << BITP_I2C_MSTAT_ALOST)    )
+
+/* Internal Actions */
+static void           submitTransaction  (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction);
+static void           commenceTransmit   (ADI_I2C_HANDLE const hDevice);
+static void           commenceReceive    (ADI_I2C_HANDLE const hDevice);
+static ADI_I2C_RESULT i2cReset           (ADI_I2C_HANDLE const hDevice);
+
+/* interrupt event handlers */
+static void           transmitHandler    (ADI_I2C_HANDLE const hDevice);
+static void           receiveHandler     (ADI_I2C_HANDLE const hDevice);
+static void           completeHandler    (ADI_I2C_HANDLE const hDevice);
+static void           errorHandler       (ADI_I2C_HANDLE const hDevice);
+
+#if defined(__ADUCM302x__)
+/*
+ *  SYS Device Structure
+ */
+typedef struct _ADI_SYS_STRUCT
+{
+        ADI_SYS_TypeDef       *pReg;      /* Pointer to register base */
+} ADI_SYS_STRUCT;
+
+/* alias for the actual device structure */
+typedef struct _ADI_SYS_STRUCT  ADI_SYS_REGISTERS;
+
+#endif
+/*
+ *****************************************************************************
+ * I2C Configuration structure.
+ *****************************************************************************/
+typedef struct __ADI_I2C_CONFIG {
+    uint16_t MasterControlRegister;  /* I2C_MCTL register configuration.      */
+    uint16_t ClockDividerRegister;   /* I2C_DIV  register.                    */
+    uint16_t SharedControlRegister;  /* I2C_DIV  register.                    */
+    uint16_t TimingControlRegister;  /* I2C_TCTL register.                    */
+    uint16_t ClockStretchRegister;   /* I2C_ASTRETCH register.                */
+    uint16_t TargetSlaveAddress;     /* slave address value (not a register). */
+} ADI_I2C_CONFIG;
+
+
+/* I2C physical device instance data */
+typedef struct __ADI_I2C_DEVICE_INFO {
+    IRQn_Type             pioIRQn;  /* PIO interrupt number                */
+    ADI_I2C_TypeDef      *pDev;     /* pointer to i2c controller           */
+    ADI_I2C_CONFIG       *pConfig;  /* pointer to user config info         */
+    ADI_I2C_HANDLE        hDevice;  /* I2C handle or NULL if uninitialized */
+} ADI_I2C_DEVICE_INFO;
+
+/* I2C driver instance data structure */
+typedef struct __ADI_I2C_DEV_DATA_TYPE {
+
+    /* make sure to synchronize ANY size changes with ADI_I2C_MEMORY_SIZE macro in adi_i2c.h */
+
+    /* device attributes */
+    ADI_I2C_TypeDef      *pDev;
+    ADI_I2C_DEVICE_INFO  *pDevInfo;
+
+
+    /* driver state */
+    uint16_t              hwStatus;
+    bool                  bRepeatStart;
+    uint16_t              i2cDeviceAddress;
+    uint16_t              i2cEncodedDeviceAddress;    /* encoded as 7-bit device address + r/w LSB */
+    bool                  bSubmitCalled;
+
+    /* prologue data */
+    volatile uint8_t     *pNextPrologueByte;
+    volatile uint16_t     remainingPrologueCount;
+
+    /* write data */
+    volatile uint8_t     *pNextWriteByte;
+    volatile uint16_t     remainingWriteCount;
+
+    /* read data */
+    volatile uint8_t     *pNextReadByte;
+    volatile uint16_t     remainingReadCount;
+
+    ADI_I2C_RESULT        result;    /* collector for return status */
+    ADI_I2C_HW_ERRORS     hwErrors;  /* collector for error status */
+
+    SEM_VAR_DECLR        /* blocking object: "Semaphore" for rtos,  "nLowPowerExitFlag" for non-rtos */
+
+} ADI_I2C_DEV_DATA_TYPE;
+
+/*! \endcond */
+
+#endif    /* end of ifndef ADI_I2C_DEF_H */
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/pwr/adi_pwr.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/pwr/adi_pwr.c
new file mode 100755
index 00000000000..0ffe5f76bd6
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/pwr/adi_pwr.c
@@ -0,0 +1,1918 @@
+/*
+ *****************************************************************************
+ * @file:    adi_pwr.c
+ * @brief:   Power Management driver implementation.
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/*! \addtogroup Power_Driver Power Driver
+ *  @{
+ *  @brief Power Management Driver
+ *  @note The application must include drivers/pwr/adi_pwr.h to use this driver
+ *  @note The API #adi_pwr_EnableClockSource requires the GPIO driver if
+ *  #ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO is set to 1. In that case the
+ *  application must include the GPIO driver sources to avoid link errors.
+ */
+
+
+#include <stdlib.h>     /* for 'NULL' */
+#include <adi_callback.h>
+#include <adi_pwr_config.h>
+#include <rtos_map/adi_rtos_map.h>
+#include <drivers/pwr/adi_pwr.h>
+#include "adi_pwr_def.h"
+#include <drivers/gpio/adi_gpio.h>
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm011 (rule 6.3): Types which specify sign and size should be used
+*   We use bool which is accepted by MISRA but the toolchain does not accept it
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   The rule makes an exception for memory-mapped register accesses.
+* Pm057 (rule 15.2): Every non-empty case clause in a switch statement shall be terminated with a break statement.
+*   In some cases we have return statement instead of break. It is not valid to both return and break in MISRA 2012.
+*/
+#pragma diag_suppress=Pm011,Pm073,Pm050,Pm140,Pm143,Pm057
+#endif /* __ICCARM__ */
+
+/*! \cond PRIVATE */
+
+/*----------------------------------------------------------------------------
+  Internal Clock Variables. The external ones are defined in system.c
+ *---------------------------------------------------------------------------*/
+#ifdef ADI_DEBUG
+/* not needed unless its debug mode */
+extern uint32_t lfClock;    /* "lf_clk" coming out of LF mux             */
+#endif
+
+extern uint32_t hfClock;    /* "root_clk" output of HF mux               */
+extern uint32_t gpioClock;  /* external GPIO clock                       */
+
+static ADI_CALLBACK  gpfCallbackFunction;
+static void *gpPowcbParam = NULL;
+static uint32_t gnLowPowerIntOccFlag = 0u;
+
+/*! \endcond */
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *---------------------------------------------------------------------------*/
+/**
+ * Initialize the clock configuration register with the default values.
+ *
+ * @return      Status
+ *    - #ADI_PWR_SUCCESS : Successfully initialized the power service.
+ */
+ADI_PWR_RESULT adi_pwr_Init (void)
+{
+    /* Enable internal HF oscillators */
+    pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+
+    pADI_CLKG0_OSC->CTL = OSCCTRL_CONFIG_VALUE;
+
+    gpfCallbackFunction = NULL;
+    pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+
+    /* Switch on the internal HF oscillator */
+    pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_HFOSC_EN;
+
+    /* wait for HF OSC to stabilize */
+    while ((pADI_CLKG0_OSC->CTL & (1U << BITP_CLKG_OSC_CTL_HFOSC_OK)) == 0u)
+    {
+    }
+
+    /* Switch over to the internal HF oscillator */
+    pADI_CLKG0_CLK->CTL0 &= ~(BITM_CLKG_CLK_CTL0_CLKMUX);
+
+    /* complete remaining reset sequence */
+    pADI_CLKG0_CLK->CTL0    = CLOCK_CTL0_CONFIG_VALUE;
+    pADI_CLKG0_CLK->CTL1    = CLOCK_CTL1_CONFIG_VALUE;
+    
+#if defined(__ADUCM4x50__)    
+    pADI_CLKG0_CLK->CTL2    = CLOCK_CTL2_CONFIG_VALUE;
+#endif /*__ADUCM4x50__ */     
+    
+    pADI_CLKG0_CLK->CTL3    = CLOCK_CTL3_CONFIG_VALUE;
+    /* No CLK CTL4 */
+    pADI_CLKG0_CLK->CTL5    = CLOCK_CTL5_CONFIG_VALUE;
+
+    /*
+     * Configure the power management registers
+     */
+    pADI_PMG0->IEN          = PWM_INTERRUPT_CONFIG;
+    pADI_PMG0->PWRMOD       = PWM_PWRMOD_CONFIG;
+    pADI_PMG0->CTL1         = PWM_HPBUCK_CONTROL;
+    
+    /* disable external HF crystal oscillator */
+    /* (don't disable LF crystal or the RTC will lose time */
+    pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+    pADI_CLKG0_OSC->CTL &= ~BITM_CLKG_OSC_CTL_HFX_EN;
+
+    NVIC_EnableIRQ(PMG0_VREG_OVR_IRQn);
+    NVIC_EnableIRQ(PMG0_BATT_RANGE_IRQn);
+
+    NVIC_EnableIRQ(CLKG_XTAL_OSC_EVT_IRQn);
+    NVIC_EnableIRQ(CLKG_PLL_EVT_IRQn);
+
+    /* compute new internal clocks based on the newly reset controller */
+    SystemCoreClockUpdate();
+
+    return(ADI_PWR_SUCCESS);
+}
+
+
+/**
+ * @brief  Updates the internal SystemCoreClock variable with current core
+ *         Clock retrieved from cpu registers.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS : Updated core system core clock variables.
+ *
+ * Updates the internal SystemCoreClock variable with current core
+ * Clock retrieved from cpu registers.
+ *
+ * @sa adi_pwr_GetClockFrequency ()
+ */
+ADI_PWR_RESULT adi_pwr_UpdateCoreClock (void)
+{
+    SystemCoreClockUpdate();
+    return(ADI_PWR_SUCCESS);
+}
+
+/**
+ * @brief  Registers or unregister the callback function.
+ *
+ * @details Application can register or unregister the callback function which
+ *          will be called to notify the events from the driver.
+ *
+ * @param[in]  pfCallback   : Callback function pointer.
+ * @param[in]  pcbParam     : Callback parameter.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS            : Successfully installed the callback function.
+ *              - #ADI_PWR_NULL_POINTER [D]   : Failed to install the callback function since the call back function pointer is NULL.
+ */
+ADI_PWR_RESULT adi_pwr_RegisterCallback(
+               const ADI_CALLBACK pfCallback,
+               void *pcbParam
+           )
+{
+
+#ifdef ADI_DEBUG
+   if(pfCallback == NULL)
+   {
+      return(ADI_PWR_NULL_POINTER);
+   }
+#endif
+
+    gpfCallbackFunction = pfCallback;
+    gpPowcbParam        = pcbParam;
+
+    return ADI_PWR_SUCCESS;
+}
+
+/**
+ * @brief  Sets the system external clock frequency
+ *
+ * @param[in]  ExtClkFreq: External clock frequency in Hz
+
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS                : Successfully set the external clock as source.
+ *              - #ADI_PWR_INVALID_CLOCK_SPEED [D]: Specified clock is out of range.
+ *
+ * @sa adi_pwr_GetClockFrequency ()
+ */
+ADI_PWR_RESULT adi_pwr_SetExtClkFreq (const uint32_t ExtClkFreq)
+{
+#ifdef ADI_DEBUG
+    if(ExtClkFreq > MAXIMUM_EXT_CLOCK)
+    {
+         return(ADI_PWR_INVALID_CLOCK_SPEED);
+    }
+#endif
+    gpioClock = ExtClkFreq;
+    return(ADI_PWR_SUCCESS);
+}
+
+/**
+ * @brief  Sets the input clock source for PLL multiplexer.
+ *
+ * @param[in]  eClockID: Clock source to the System PLL multiplexer.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS              : Successfully set the PLL multiplexer clock source.
+ *              - #ADI_PWR_INVALID_CLOCK_ID [D] : Specified clock ID is invalid.
+ *
+ * @sa adi_pwr_SetLFClockMux()
+ */
+ADI_PWR_RESULT  adi_pwr_SetPLLClockMux(const ADI_CLOCK_MUX_ID eClockID)
+{
+    uint32_t tmp;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    /* Validate the given clock ID */
+    switch (eClockID)
+    {
+        case ADI_CLOCK_MUX_SPLL_HFOSC:
+        case ADI_CLOCK_MUX_SPLL_HFXTAL:
+          
+#if defined(__ADUCM4x50__)          
+        case ADI_CLOCK_MUX_SPLL_GPIO:
+#endif /* __ADUCM4x50__ */           
+            break;
+
+            
+      /* Any other clock ID is not valid since we are configuring the SPLL clock multiplexer.
+       * Only valid input clock to the multiplexer is HFOSC, HFXTAL, GPIO */
+        default:
+            return(ADI_PWR_INVALID_CLOCK_ID);
+    }
+#endif /* ADI_DEBUG */
+
+    /* update the mux setting inside a critical region */
+    ADI_ENTER_CRITICAL_REGION();
+    tmp     =   (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_PLL_IPSEL);
+    tmp     |=  (( (uint32_t)eClockID - (uint32_t)ADI_CLOCK_MUX_SPLL_HFOSC) << BITP_CLKG_CLK_CTL0_PLL_IPSEL);
+    pADI_CLKG0_CLK->CTL0 = tmp;
+    ADI_EXIT_CRITICAL_REGION();
+
+    return(ADI_PWR_SUCCESS);
+}
+
+/**
+ * @brief  Sets the input clock for low frequency clock multiplexer.
+ *
+ * @param[in]  eClockID: Clock source to the low frequency clock multiplexer.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS                : Successfully LF clock multiplexer clock source.
+ *              - #ADI_PWR_INVALID_CLOCK_ID [D]   : Specified clock ID is invalid.
+ *
+ * @sa adi_pwr_SetRootClockMux()
+ * @sa adi_pwr_SetPLLClockMux()
+ */
+ADI_PWR_RESULT  adi_pwr_SetLFClockMux(const ADI_CLOCK_MUX_ID eClockID)
+{
+    uint32_t tmp;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    switch (eClockID)
+    {
+
+        case ADI_CLOCK_MUX_LFCLK_LFOSC:
+        case ADI_CLOCK_MUX_LFCLK_LFXTAL:
+            break;
+      /* Any other clock ID is not valid since we are configuring the Low frequency clock multiplexer.
+       * Only valid input clock to the multiplexer is LFOSC, LFXTAL */
+
+    default:
+        return(ADI_PWR_INVALID_CLOCK_ID);
+
+    }
+#endif /* ADI_DEBUG */
+
+    /* update the mux setting inside a critical region */
+    ADI_ENTER_CRITICAL_REGION();
+
+    pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+    tmp = (pADI_CLKG0_OSC->CTL & ~BITM_CLKG_OSC_CTL_LFCLK_MUX);
+    tmp |=(((uint32_t)eClockID - (uint32_t)ADI_CLOCK_MUX_LFCLK_LFOSC) << BITP_CLKG_OSC_CTL_LFCLK_MUX);
+    pADI_CLKG0_OSC->CTL = tmp;
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    return(ADI_PWR_SUCCESS);
+}
+
+/**
+ * @brief  Sets clock source for the Reference clock multiplexer.
+ *
+ * @param[in]  eClockID: Clock source to the reference clock multiplexer.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS                : Successfully set the source for reference clock multiplexer.
+ *              - #ADI_PWR_INVALID_CLOCK_ID [D]   : Specified clock ID is invalid.
+ *
+ * @sa adi_pwr_SetLFClockMux()
+ * @sa adi_pwr_SetRootClockMux()
+ * @sa adi_pwr_SetPLLClockMux()
+ */
+
+ADI_PWR_RESULT  adi_pwr_SetRefClockMux(const ADI_CLOCK_MUX_ID eClockID)
+{
+    uint32_t tmp;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    switch (eClockID)
+    {
+
+        case ADI_CLOCK_MUX_REF_HFOSC_CLK:
+        case ADI_CLOCK_MUX_REF_HFXTAL_26MHZ_CLK:
+        case ADI_CLOCK_MUX_REF_HFXTAL_16MHZ_CLK:
+            break;
+      /* Any other clock ID is not valid since we are configuring the out clock multiplexer.*/
+
+        default:
+            return(ADI_PWR_INVALID_CLOCK_ID);
+    }
+#endif /* ADI_DEBUG */
+
+    /* update the mux setting inside a critical region */
+    ADI_ENTER_CRITICAL_REGION();
+
+    tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_RCLKMUX);
+    tmp |=(((uint32_t)eClockID - (uint32_t)ADI_CLOCK_MUX_REF_HFOSC_CLK) << BITP_CLKG_CLK_CTL0_RCLKMUX);
+    pADI_CLKG0_CLK->CTL0 = tmp;
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    return(ADI_PWR_SUCCESS);
+}
+
+/**
+ * @brief  Sets the source for the root clock multiplexer.
+ *
+ * @param[in]  eClockID: Clock source to the root clock multiplexer.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS                : Successfully set the source for root clock multiplexer.
+ *              - #ADI_PWR_INVALID_CLOCK_ID [D]   : Specified clock ID is invalid.
+ *
+ * @sa adi_pwr_SetLFClockMux()
+ * @sa adi_pwr_SetPLLClockMux()
+ */
+ADI_PWR_RESULT  adi_pwr_SetRootClockMux(const ADI_CLOCK_MUX_ID eClockID)
+{
+    uint32_t tmp;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    switch (eClockID)
+    {
+       case ADI_CLOCK_MUX_ROOT_HFOSC:
+       case ADI_CLOCK_MUX_ROOT_HFXTAL:
+       case ADI_CLOCK_MUX_ROOT_SPLL:
+       case ADI_CLOCK_MUX_ROOT_GPIO:
+            break;
+		  /* Any other clock ID is not valid since we are configuring the root clock multiplexer.
+		   * Only valid input clock to the multiplexer is HFOSC, HFXTAL, SPLL, GPIO */
+		default:
+        	return(ADI_PWR_INVALID_CLOCK_ID);
+    }
+#endif /* ADI_DEBUG */
+
+    /* update the mux setting inside a critical region */
+    ADI_ENTER_CRITICAL_REGION();
+
+    tmp =  (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_CLKMUX);
+    tmp |= (((uint32_t)eClockID - (uint32_t)ADI_CLOCK_MUX_ROOT_HFOSC) << BITP_CLKG_CLK_CTL0_CLKMUX);
+    pADI_CLKG0_CLK->CTL0 = tmp;
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    return(ADI_PWR_SUCCESS);
+}
+
+
+/**
+ * @brief  Gets the system external clock frequency.
+ *         Gets the clock frequency of the source connected to the external GPIO clock input source.
+ *
+ * @param [in]  pExtClock : Pointer to write the external clock frequency.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS          : Successfully returning the external clock frequency.
+ *              - #ADI_PWR_NULL_POINTER [D] : If the given pointer is pointing to NULL.
+ *              - #ADI_PWR_FAILURE [D]      : The system is not initialized yet. Call SystemInit before calling this API.
+ */
+ADI_PWR_RESULT adi_pwr_GetExtClkFreq (uint32_t *pExtClock)
+{
+#ifdef ADI_DEBUG
+    /* Trap here if the app fails to set the external clock frequency. */
+    if (0u == gpioClock)
+    {
+        return (ADI_PWR_FAILURE);
+    }
+
+    if(pExtClock == NULL)
+    {
+        return (ADI_PWR_NULL_POINTER);
+    }
+#endif
+    *pExtClock = gpioClock;
+    return  ADI_PWR_SUCCESS;
+}
+
+
+/*!
+ * @brief      Get the frequency of the given clock.
+ *             Obtain individual peripheral clock frequencies
+ *
+ * @param[in]  eClockId : Clock identifier
+ * @param[out] pClock   : Pointer to a location to store the clock frequency.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS                      : Successfully returned the queried clock.
+ *              - #ADI_PWR_SYSTEM_NOT_INITIALIZED [D]   : The system is not initialized yet. Call SystemInit before calling this API.
+ *
+ * @sa adi_PWR_SetClockDivide
+ * @sa SystemSetClockDivider
+*/
+ADI_PWR_RESULT adi_pwr_GetClockFrequency (const ADI_CLOCK_ID eClockId, uint32_t *pClock )
+{
+    uint32_t src, nDiv;
+
+#ifdef ADI_DEBUG
+    /* trap here if the app fails to call SystemInit(). */
+    if ((0u == hfClock) || (0u == lfClock))
+    {
+        return ADI_PWR_SYSTEM_NOT_INITIALIZED;
+    }
+#endif
+
+    /* refresh internal clock variables */
+    SystemCoreClockUpdate();
+    src = hfClock;
+
+    switch (eClockId) {
+
+        /* HCLOCK domain */
+        case ADI_CLOCK_HCLK:
+            nDiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT;
+            break;
+
+        /* PCLOCK domain */
+        case ADI_CLOCK_PCLK:
+            nDiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_PCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_PCLKDIVCNT;
+            break;
+
+        default:
+            return ADI_PWR_INVALID_CLOCK_ID;
+    } /* end switch */
+
+    if(nDiv == 0u)
+    {
+        nDiv = 1u;
+    }
+
+    *pClock =  (src/nDiv);
+
+    return ADI_PWR_SUCCESS;
+}
+
+
+/*!
+    @brief      Enable/disable individual peripheral clocks.
+
+    @param[in]  eClockGate       Clock identifier
+    @param[in]  bEnable          Flag to indicate whether to enable/disable individual clock.
+                                 true  - to enable individual clock.
+                                 false - to disable individual clock.
+
+    @return     Status
+                    - #ADI_PWR_SUCCESS  if we have successfully enabled or disabled the clock.
+
+    @details    Manage individual peripheral clock gates to enable or disable the clocks to the peripheral.
+*/
+ADI_PWR_RESULT adi_pwr_EnableClock (const ADI_CLOCK_GATE eClockGate, const bool bEnable)
+{
+    uint32_t mask;
+    ADI_INT_STATUS_ALLOC();
+
+    mask = (uint16_t)eClockGate;
+    /* update the Clock Gate register in a critical region */
+    ADI_ENTER_CRITICAL_REGION();
+
+        /* NOTE NEGATIVE LOGIC!!! */
+        if (bEnable == true) {
+
+        /* clear disable bit */
+            pADI_CLKG0_CLK->CTL5 &= ~mask;
+        } else {
+            /* set disable bit */
+            pADI_CLKG0_CLK->CTL5 |= mask;
+        }
+
+    /* end critical region */
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_PWR_SUCCESS;
+}
+
+
+/*!
+    @brief      Sets the clock divide factor for an individual clock group.
+
+    @param[in]  eClockId   Clock domain identifier.
+    @param[in]  nDiv       Clock divide value to be set (right-justified uint16_t).
+
+    @return     Status
+                    - #ADI_PWR_SUCCESS                      if successfully set the given clock divide factor.
+                    - #ADI_PWR_INVALID_CLOCK_DIVIDER [D]    if the divider is out of range.
+                    - #ADI_PWR_INVALID_CLOCK_ID [D]         if the given clock is invalid.
+                    - #ADI_PWR_INVALID_CLOCK_RATIO [D]      if the given clock ratio invalid.
+
+    @details    Manage individual peripheral clock dividers.
+
+    @sa         SystemGetClockFrequency
+*/
+ADI_PWR_RESULT adi_pwr_SetClockDivider (const ADI_CLOCK_ID eClockId, const uint16_t nDiv)
+{
+    uint32_t mask;
+    uint32_t value;
+    uint32_t tmp;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    uint32_t hdiv, pdiv;
+#endif  /*ADI_DEBUG*/
+
+    switch (eClockId)
+    {
+        case ADI_CLOCK_HCLK:
+#ifdef ADI_DEBUG
+            /* Verify the divide factor is within the range */
+            if ((nDiv > CLOCK_MAX_DIV_VALUE) || (nDiv < CLOCK_MIN_DIV_VALUE))
+            {
+                return ADI_PWR_INVALID_CLOCK_DIVIDER;
+            }
+
+            /* verify PCLK freq is <= requested HCLK */
+            pdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_PCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_PCLKDIVCNT;
+            hdiv = nDiv;
+            if (hdiv > pdiv) {
+                return ADI_PWR_INVALID_CLOCK_SPEED;
+            }
+
+            /* verify new PDIV:HDIV ratio will be integral */
+            if ((pdiv % hdiv) != 0u) 
+            {
+                return ADI_PWR_INVALID_CLOCK_RATIO;
+            }
+#endif  /*ADI_DEBUG*/
+
+            mask = BITM_CLKG_CLK_CTL1_HCLKDIVCNT;
+            value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_HCLKDIVCNT;
+            break;
+
+        case ADI_CLOCK_PCLK:
+#ifdef ADI_DEBUG
+
+            /* Verify the divide factor is within the range */
+            if ((nDiv > CLOCK_MAX_DIV_VALUE) || (nDiv < CLOCK_MIN_DIV_VALUE))
+            {
+                return ADI_PWR_INVALID_CLOCK_DIVIDER;
+            }
+
+            /* verify requested PCLK freq is <= HCLK */
+            pdiv = nDiv;
+            hdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT;
+            if (hdiv > pdiv) {
+                return ADI_PWR_INVALID_CLOCK_SPEED;
+            }
+
+            /* verify new PDIV:HDIV ratio will be integral */
+            if ((pdiv % hdiv) != 0u) 
+            {
+                return ADI_PWR_INVALID_CLOCK_RATIO;
+            }
+#endif  /*ADI_DEBUG*/
+            mask = BITM_CLKG_CLK_CTL1_PCLKDIVCNT;
+            value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_PCLKDIVCNT;
+            break;
+
+        case ADI_CLOCK_ACLK:
+#ifdef ADI_DEBUG
+            /* Verify the divide factor is within the range */
+            if ((nDiv > ACLK_MAX_DIV_VALUE) || (nDiv < ACLK_MIN_DIV_VALUE))
+            {
+                return ADI_PWR_INVALID_CLOCK_DIVIDER;
+            }
+
+            /* verify requested ACLK freq is <= HCLK */
+            pdiv = nDiv;
+            hdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT;
+            if (hdiv > pdiv) {
+                return ADI_PWR_INVALID_CLOCK_SPEED;
+            }
+
+            /* verify new PDIV:HDIV ratio will be integral */
+            if ((pdiv % hdiv) != 0u)
+            {
+                return ADI_PWR_INVALID_CLOCK_RATIO;
+            }
+#endif  /*ADI_DEBUG*/
+
+            mask = BITM_CLKG_CLK_CTL1_ACLKDIVCNT;
+            value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_ACLKDIVCNT;
+            break;
+
+
+        default:
+            return ADI_PWR_INVALID_CLOCK_ID;
+    } /* end switch */
+
+    /* critical region */
+    ADI_ENTER_CRITICAL_REGION();
+
+    /* read-modify-write without any interrupts */
+    /* change in a tmp variable and write entire new value all at once */
+    tmp = pADI_CLKG0_CLK->CTL1;
+    tmp &= ~mask;                       /* blank the field */
+    tmp |= value;                       /* set the new value */
+    pADI_CLKG0_CLK->CTL1 = tmp;         /* write the new value */
+
+    /* end critical region */
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* refresh internal clock variables */
+    SystemCoreClockUpdate();
+
+    return ADI_PWR_SUCCESS;
+}
+
+/*!
+ * @brief       To Enable/disable clock sources.
+ *
+ * @param[in]   eClockSource :    Clock source identifier.
+ * @param[in]   bEnable      :    Enable (true) or disable (false) the clock source.
+ *
+ * @return      Status
+ *                  - #ADI_PWR_SUCCESS          if the clock source powers up successfully.
+ *                  - #ADI_PWR_INVALID_PARAM    if the clock source is not valid.
+ *
+ * @details    Enables or disables clock sources without additional checks, by writing a "1" or "0" to the enable bit.
+ *
+ */
+ADI_PWR_RESULT adi_pwr_EnableClockSource (const ADI_CLOCK_SOURCE_ID eClockSource, const bool bEnable)
+{
+    uint32_t val = 0u;
+    volatile uint32_t *pReg = NULL;
+    uint32_t nMask = 0u;
+    ADI_INT_STATUS_ALLOC();
+
+    /* This switch statement does not handle every value in the ADI_CLOCK_SOURCE_ID enumeration
+     * which results on a gcc warning. This is done intentionally:
+     * ADI_CLOCK_SOURCE_LFOSC is not checked  because it is enabled always and it cannot be disabled
+     * ADI_CLOCK_SOURCE_GPIO is only checked if a specific configuration macro is defined
+     */
+    switch(eClockSource)
+    {
+        case ADI_CLOCK_SOURCE_HFXTAL:
+            val     =   (1u << BITP_CLKG_OSC_CTL_HFX_EN);
+            pReg    =   &pADI_CLKG0_OSC->CTL;
+            nMask   =   BITM_CLKG_OSC_CTL_HFX_OK;
+            break;
+
+        case ADI_CLOCK_SOURCE_LFXTAL:
+            val     =   (1u << BITP_CLKG_OSC_CTL_LFX_EN);
+            pReg    =   &pADI_CLKG0_OSC->CTL;
+            nMask   =   BITM_CLKG_OSC_CTL_LFX_OK;
+            break;
+
+        case ADI_CLOCK_SOURCE_HFOSC:
+            val     =   (1u << BITP_CLKG_OSC_CTL_HFOSC_EN);
+            pReg    =   &pADI_CLKG0_OSC->CTL;
+            nMask   =   BITM_CLKG_OSC_CTL_HFOSC_OK;
+            break;
+
+        case ADI_CLOCK_SOURCE_SPLL:
+            val     =   (1u << BITP_CLKG_CLK_CTL3_SPLLEN);
+            pReg    =   &pADI_CLKG0_CLK->CTL3;
+            nMask   =   BITM_CLKG_CLK_CTL3_SPLLEN;
+            break;
+
+#if (ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO == 1)
+        case ADI_CLOCK_SOURCE_GPIO:
+            if(adi_gpio_PullUpEnable(ADI_GPIO_PORT1,ADI_GPIO_PIN_10,false) != ADI_GPIO_SUCCESS)
+            {
+               return(ADI_PWR_FAILURE);
+            }
+            if(adi_gpio_InputEnable(ADI_GPIO_PORT1,ADI_GPIO_PIN_10,true) != ADI_GPIO_SUCCESS)
+            {
+               return ADI_PWR_SUCCESS;
+            }
+            break;
+#endif
+
+        default:
+            return(ADI_PWR_INVALID_PARAM);
+
+    } /* end switch */
+
+    ADI_ENTER_CRITICAL_REGION();
+
+        pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+        if (bEnable == true)
+        {
+            *pReg |= val;
+        }
+        else
+        {
+            *pReg &= ~val;
+        }
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    if((nMask !=0u) && (bEnable == true))
+    {
+        while(0u== (pADI_CLKG0_OSC->CTL & nMask)){}
+    }
+
+    return (ADI_PWR_SUCCESS);
+}
+
+
+/*!
+ * @brief       Return the status of a clock source.
+ *
+ * @param[in]    eClockSource  : Clock source identifier.
+ * @param[out]   peStatus      : Pointer to variable of type  #ADI_CLOCK_SOURCE_STATUS for storing clock source status.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS               if the clock source is disabled.
+ *              - #ADI_PWR_NULL_POINTER [D]      if the given pointer is pointing to NULL.
+
+ *  @details    Return the status of a clock source.
+ *
+ */
+ADI_PWR_RESULT adi_pwr_GetClockStatus (const ADI_CLOCK_SOURCE_ID eClockSource, ADI_CLOCK_SOURCE_STATUS *peStatus)
+{
+    uint32_t val = pADI_CLKG0_OSC->CTL;
+
+#ifdef ADI_DEBUG
+    if(peStatus == NULL)
+    {
+        return ADI_PWR_NULL_POINTER;
+    }
+#endif /* ADI_DEBUG */
+
+    *peStatus = ADI_CLOCK_SOURCE_DISABLED;
+
+    switch(eClockSource)
+    {
+        case ADI_CLOCK_SOURCE_HFOSC:
+            if ((val & BITM_CLKG_OSC_CTL_HFOSC_EN) != 0u)
+            {
+                /* Clock source enabled, now check for stable */
+                if ((val & BITM_CLKG_OSC_CTL_HFOSC_OK) != 0u)
+                {
+                    *peStatus = ADI_CLOCK_SOURCE_ENABLED_STABLE;
+                }
+                else
+                {
+                    *peStatus  = ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE;
+                }
+            }
+            break;
+
+        case ADI_CLOCK_SOURCE_HFXTAL:
+            if ((val & BITM_CLKG_OSC_CTL_HFX_EN) != 0u)
+            {
+                /* Clock source enabled, now check for stable */
+                if ((val & BITM_CLKG_OSC_CTL_HFX_OK) != 0u)
+                {
+                    *peStatus  = ADI_CLOCK_SOURCE_ENABLED_STABLE;
+                }
+                else
+                {
+                    *peStatus  = ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE;
+                }
+            }
+            break;
+
+        case ADI_CLOCK_SOURCE_LFXTAL:
+            if ((val & BITM_CLKG_OSC_CTL_LFX_EN) != 0u)
+            {
+                /* Clock source enabled, now check for stable */
+                if ((val & BITM_CLKG_OSC_CTL_LFX_OK) != 0u)
+                {
+                    *peStatus  = ADI_CLOCK_SOURCE_ENABLED_STABLE;
+                }
+                else
+                {
+                    *peStatus  = ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE;
+                }
+            }
+            break;
+
+        case ADI_CLOCK_SOURCE_LFOSC:
+            /* Clock source enabled, now check for stable */
+            if ((val & BITM_CLKG_OSC_CTL_LFOSC_OK) != 0u)
+            {
+                *peStatus  = ADI_CLOCK_SOURCE_ENABLED_STABLE;
+            }
+            else
+            {
+                *peStatus  = ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE;
+            }
+            break;
+
+        /* Since the clock through GPIO is supplied externally we cannot get
+           the clock status for GPIO */
+        case ADI_CLOCK_SOURCE_GPIO:
+        default:
+            *peStatus  =  ADI_CLOCK_SOURCE_ID_NOT_VALID;
+             break;
+
+    } /* end switch */
+
+    return ADI_PWR_SUCCESS;
+}
+
+/*!
+ * @brief       Enable/Disable the clock interrupt to monitor status of LFXTAL, HFXTAL and PLL.
+ *
+ * @param[in]   eIrq    : Specify which interrupt need to be enable/disabled.
+   @param[in]   bEnable : Specifies to enable/disable the specified interrupt.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS  Enabled the specified interrupt.
+ *
+ * @sa adi_pwr_SetVoltageRange()
+ */
+
+ADI_PWR_RESULT adi_pwr_EnableClockInterrupt(const ADI_PWR_CLOCK_IRQ eIrq, const bool bEnable)
+{
+    ADI_INT_STATUS_ALLOC();
+    volatile uint32_t *pReg = NULL;
+    uint32_t tmp;
+
+    switch(eIrq)
+    {
+#if defined(__ADUCM4x50__)      
+        /*! Interrupt for root clock monitor and Clock Fail */
+        case ADI_PWR_ROOT_CLOCK_MON_IEN:
+            pReg = &pADI_CLKG0_OSC->CTL;
+            break;
+#endif /* __ADUCM4x50__ */
+            
+        /*! Interrupt for LFXTAL clock monitor and Clock Fail */
+        case ADI_PWR_LFXTAL_CLOCK_MON_IEN:
+            pReg = &pADI_CLKG0_OSC->CTL;
+            break;
+
+        /*! Interrupt when LFXTAL clock becomes stable/unstable */
+        case ADI_PWR_LFXTAL_STATUS_IEN:
+            pReg = &pADI_CLKG0_CLK->CTL0;
+            break;
+
+        /*! Interrupt when HFXTAL clock becomes stable/unstable */
+        case ADI_PWR_HFXTAL_STATUS_IEN:
+            pReg = &pADI_CLKG0_CLK->CTL0;
+            break;
+
+        /*! Interrupt when PLL-LOCK/PLL-UNLOCK  */
+        case ADI_PWR_PLL_STATUS_IEN:
+            pReg = &pADI_CLKG0_CLK->CTL3;
+            break;
+
+        default:
+            break;
+    }
+
+    ADI_ENTER_CRITICAL_REGION();
+
+    tmp = *pReg;
+
+    if(bEnable == true)
+    {
+        tmp |= (uint32_t)eIrq;
+    }
+    else
+    {
+        tmp &= ~((uint32_t)eIrq);
+    }
+
+    /* If we have to write to oscillator control register unlock it */
+    if(pReg == &pADI_CLKG0_OSC->CTL)
+    {
+        pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+    }
+    *pReg = tmp;
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    return(ADI_PWR_SUCCESS);
+}
+
+
+/*!
+ * @brief       Program PLL frequency.
+ *
+ * @param[in]   nDivFactor   PLL divider(M).
+ * @param[in]   nMulFactor   PLL Multiplier(N)
+ * @param[in]   bDiv2        PLL DIV2 parameter.
+ * @param[in]   bMul2        PLL DIV2 parameter.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS                    if the PLL has been programmed successfully.
+ *              - #ADI_PWR_OPERATION_NOT_ALLOWED [D]  if trying to program SPLL and SPLL drives the system clock.
+ *              - #ADI_PWR_INVALID_CLOCK_ID [D]       if the clock identifier does not match either PLL.
+ *
+ *  @details    Program PLL frequency (parameters M, N, DIV2) forSystem PLL(SPLL).
+ *
+ *              SPLL = input clock * ["(N *  (1+ bMul2 )" / "((1+bDiv2)*M)" ]
+ *              where input clock can be HFOSC or HFXTAL.
+ */
+ADI_PWR_RESULT adi_pwr_SetPll(uint8_t  nDivFactor, const uint8_t  nMulFactor, const bool bDiv2, const bool bMul2)
+{
+    uint32_t                val, cfg = 0u;
+    uint8_t nTempDivFactor = nDivFactor, nTempMulFactor = nMulFactor;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    /* Check if multiplication factor and division factor is more than 6 bits */
+    if (((nMulFactor & ~0x3Fu) != 0u) || ((nDivFactor & ~0x3Fu) != 0u))
+    {
+        return ADI_PWR_INVALID_CLOCK_DIVIDER;
+    }
+
+    /* Check if the PLL is multipexed in as root clock source, parameters should not change in that case */
+    if((pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_CLKMUX) ==
+       ((uint32_t)((ADI_CLOCK_MUX_ROOT_SPLL - ADI_CLOCK_MUX_ROOT_HFOSC) << BITP_CLKG_CLK_CTL0_CLKMUX))) 
+    {
+         return ADI_PWR_OPERATION_NOT_ALLOWED;
+    }
+#endif
+
+     if(nTempDivFactor < MINIMUM_PLL_DIVIDER)
+     {
+         nTempDivFactor = MINIMUM_PLL_DIVIDER;
+     }
+     if(nTempMulFactor < MINIMUM_PLL_MULTIPLIER)
+     {
+         nTempMulFactor = MINIMUM_PLL_MULTIPLIER;
+     }
+
+    cfg =  (((uint32_t)nTempDivFactor) << BITP_CLKG_CLK_CTL3_SPLLMSEL)|( ((uint32_t) nTempMulFactor) << BITP_CLKG_CLK_CTL3_SPLLNSEL);
+
+    if(bDiv2 == true)
+    {
+      cfg |= (1u <<BITP_CLKG_CLK_CTL3_SPLLDIV2);
+    }
+    if(bMul2 == true)
+    {
+      cfg |= (1u <<BITP_CLKG_CLK_CTL3_SPLLMUL2);
+    }
+
+    /* critical region */
+    ADI_ENTER_CRITICAL_REGION();
+
+    val = pADI_CLKG0_CLK->CTL3;
+    val &= ~( BITM_CLKG_CLK_CTL3_SPLLMUL2 | BITM_CLKG_CLK_CTL3_SPLLMSEL | BITM_CLKG_CLK_CTL3_SPLLDIV2 | BITM_CLKG_CLK_CTL3_SPLLNSEL);
+    val |= cfg;
+    pADI_CLKG0_CLK->CTL3 = val;
+
+   /* end critical region */
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_PWR_SUCCESS;
+}
+
+
+/*!
+ * @brief       Enable/Disable the power management interrupt.
+ *
+ * @param[in]   eIrq    : Specify which interrupt need to be enable/disabled.
+   @param[in]   bEnable : Specifies to enable/disable  the interrupt.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS      Enabled the specified interrupt.
+ *              - #ADI_PWR_FAILURE [D]  Enabling the battery monitoring interrupt when range is set to safe range (VBAT > 2.75 ).
+ *
+ * @note : User should configure the appropriate voltage range before enabling the interrupt for battery voltage range.
+ *
+ * @sa adi_pwr_SetVoltageRange()
+ */
+ADI_PWR_RESULT adi_pwr_EnablePMGInterrupt(const ADI_PWR_PMG_IRQ eIrq, const bool bEnable)
+{
+   ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+   if(((pADI_PMG0->IEN & BITM_PMG_IEN_RANGEBAT) == 0u) || (eIrq != ADI_PWR_BATTERY_VOLTAGE_RANGE_IEN))
+   {
+       return(ADI_PWR_FAILURE);
+   }
+#endif
+
+  ADI_ENTER_CRITICAL_REGION();
+  if(bEnable == true)
+  {
+    pADI_PMG0->IEN  |= (uint32_t)eIrq;
+  }
+  else
+  {
+    pADI_PMG0->IEN  &= ~(uint32_t)(eIrq);
+  }
+  ADI_EXIT_CRITICAL_REGION();
+
+  return(ADI_PWR_SUCCESS);
+}
+
+
+
+/*!
+ * @brief       Enable/disable LFXTAL bypass mode.
+ *
+   @param[in]   bEnable : Specifies to enable/disable  the LFXTAL bypass mode
+ *\n                      true: To enable LFXTAL bypass mode.
+ * \n                     false: To disable LFXTAL bypass mode.
+ * @return      Status
+ *                     - #ADI_PWR_SUCCESS     Enabled/Disabled LFXTAL bypass mode.
+ *                     - #ADI_PWR_FAILURE[D]  Failed to Enable/Disable LFXTAL bypass mode.
+ *
+ */
+ADI_PWR_RESULT  adi_pwr_EnableLFXTALBypass(const bool bEnable)
+{
+    volatile uint32_t nDelay = 0xFFFFFFu;
+    if(bEnable == true)
+    {
+        /* Write the oscillator key */
+        pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+        /* Disable the LFXTAL */
+        pADI_CLKG0_OSC->CTL  &= ~(BITM_CLKG_OSC_CTL_LFX_EN);
+        /* Wait till status de-asserted. */
+        while(nDelay != 0u)
+        {
+            if((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK) == 0u)
+            {
+                break;
+            }
+            nDelay--;
+        }
+#ifdef ADI_DEBUG
+        if(nDelay == 0u)
+        {
+            return(ADI_PWR_FAILURE);
+        }
+#endif
+        pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+        /* Enable the BYPASS mode */
+        pADI_CLKG0_OSC->CTL  |= (BITM_CLKG_OSC_CTL_LFX_BYP);
+        /* Wait till status asserted. */
+        nDelay = 0xFFFFFFu;
+        while(nDelay != 0u)
+        {
+            if(((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK)== BITM_CLKG_OSC_CTL_LFX_OK))
+            {
+                break;
+            }
+            nDelay--;
+        }
+#ifdef ADI_DEBUG
+        if(nDelay == 0u)
+        {
+            return(ADI_PWR_FAILURE);
+        }
+#endif
+
+    }
+    else
+    {
+        /* Write the oscillator key */
+        pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+        /* Disable  the BYPASS mode */
+        pADI_CLKG0_OSC->CTL  &= ~(BITM_CLKG_OSC_CTL_LFX_BYP);
+        /* Wait till status de-asserted. */
+        while(nDelay != 0u)
+        {
+            if((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK) == 0u)
+            {
+                break;
+            }
+            nDelay--;
+        }
+#ifdef ADI_DEBUG
+        if(nDelay == 0u)
+        {
+            return(ADI_PWR_FAILURE);
+        }
+#endif
+    }
+
+    return(ADI_PWR_SUCCESS);
+}
+
+
+#if defined(__ADUCM4x50__)
+/*!
+ * @brief       Enables or disables the LFXTAL Robust mode.
+ *              The Robust mode enables the LFXTAL oscillator to work also when an additional resistive
+ *              load is placed between the crystal pins and GND. This feature is capable of tolerating
+ *              the presence of impurities on the PCB board, where these impurities allow a high-resistance
+ *              leakage path from the crystal pins to ground, which can cause problems to the circuit operation
+ *
+ *  @param[in]  bEnable  :  Flag which indicates whether to enable or disable LFXTAL Robust mode.
+                            true    - Enable Robust mode.
+                            false   - Disable Robust mode.
+ *  @return     Status
+ *                      - #ADI_PWR_SUCCESS     Enabled/Disabled LFXTAL Robust mode.
+ *
+ * @sa adi_pwr_SetLFXTALRobustModeLoad()
+ */
+ADI_PWR_RESULT adi_pwr_EnableLFXTALRobustMode( const bool bEnable )
+{
+    /* Write the oscillator key */
+    pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+
+    if(bEnable == true)
+    {
+        pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_LFX_ROBUST_EN;
+    }
+    else
+    {
+        pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_LFX_ROBUST_EN);
+    }
+
+    return(ADI_PWR_SUCCESS);
+}
+
+/*!
+ * @brief       Enable/Disable the LFXTAL Fail Auto switch.
+ *              Enables/Disable automatic Switching of the LF Mux to LF OSC on LF XTAL Failure.
+ *
+ *  @param[in]  bEnable   :  Flag which indicates whether to enable/disable LFXTAL Auto switch.
+ *                           true  - Enable LFXTAL Auto switch.
+ *                           false - Disable LFXTAL Auto switch.
+ *  @return     Status
+ *                - #ADI_PWR_SUCCESS     Enabled/Disabled LFXTAL Auto switch mode.
+ */
+ADI_PWR_RESULT adi_pwr_EnableLFXTALFailAutoSwitch( const bool  bEnable )
+{
+    /* Write the oscillator key */
+    pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+
+    if(bEnable == true)
+    {
+        pADI_CLKG0_OSC->CTL  |= BITM_CLKG_OSC_CTL_LFX_AUTSW_EN;
+    }
+    else
+    {
+        pADI_CLKG0_OSC->CTL  &= ~(BITM_CLKG_OSC_CTL_LFX_AUTSW_EN);
+    }
+    return(ADI_PWR_SUCCESS);
+}
+
+
+/*!
+ * @brief       Sets the LFXT Robust Mode Load.
+ *              Selects the amount of loading tolerated when LFXTAL robust mode is enabled.
+ *
+ *  @param[in]  eLoad   :  Amount of loading tolerance required.
+ *  @return     Status
+ *                 - #ADI_PWR_SUCCESS     Successfully set the load tolerance for LFXTAL Robust mode.
+ *
+ * @sa adi_pwr_EnableLFXTALRobustMode()
+ */
+ADI_PWR_RESULT adi_pwr_SetLFXTALRobustModeLoad( const ADI_PWR_LFXTAL_LOAD eLoad )
+{
+    uint32_t tmp;
+
+    tmp =   pADI_CLKG0_OSC->CTL & ~BITM_CLKG_OSC_CTL_LFX_ROBUST_LD;
+    tmp |=  ((uint32_t)eLoad) << BITP_CLKG_OSC_CTL_LFX_ROBUST_LD;
+
+    /* Write the oscillator key */
+    pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+    pADI_CLKG0_OSC->CTL = tmp;
+
+    return(ADI_PWR_SUCCESS);
+}
+
+/*!
+ * @brief       To enable/disable auto switching of root clock to HFOSC upon detection of Root clock failure.
+ *              This feature is valid only when the ROOT clock monitor is enabled. The root clock monitoring
+ *              can be enabled by using the API #adi_pwr_EnableClockInterrupt.
+ *
+ *  @param[in]  bEnable   :  Flag which indicates whether to enable or disable Root clock auto switch.
+ *                           true  - Enable Root clock auto switch.
+                             false - Disable Root clock auto switch.
+ *  @return     Status
+ *                 - #ADI_PWR_SUCCESS     Successfully set the load tolerance for LFXTAL Robust mode.
+ *
+ * @sa adi_pwr_EnableClockInterrupt()
+ */
+ADI_PWR_RESULT adi_pwr_EnableRootClockFailAutoSwitch( const bool bEnable )
+{
+    /* Write the oscillator key */
+    pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+
+    if(bEnable == true)
+    {
+        pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_ROOT_AUTSW_EN;
+    }
+    else
+    {
+        pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_ROOT_AUTSW_EN);
+    }
+
+    return(ADI_PWR_SUCCESS);
+}
+
+
+/*!
+ * @brief       Sets the HF Oscillator divide factor.
+ *
+ *              Sets the divide factor for the clocks derived from the HF oscillator clock.
+ *
+ * @param[in]  eDivFactor :  HF Clock divide factor to be set.
+ *
+ * @return     Status
+ *                 - #ADI_PWR_SUCCESS   Successfully set the clock divide factor for HF Oscillator.
+ *
+ * @note        When the HF Oscillator auto divide by 1 is set, the divide factor set is automatically
+ *              changed to 1 when coming out of Flexi mode. Application should set it back to the
+ *              required divide after coming out of Flexi mode.
+ *
+ * @sa adi_pwr_EnableHFOscAutoDivBy1()
+ */
+ADI_PWR_RESULT adi_pwr_SetHFOscDivFactor( const ADI_PWR_HFOSC_DIV  eDivFactor )
+{
+    uint32_t tmp;
+
+    tmp =  (pADI_CLKG0_CLK->CTL2 & ~BITM_CLKG_CLK_CTL2_HFOSCDIVCLKSEL);
+    tmp |= ((uint32_t) eDivFactor << BITP_CLKG_CLK_CTL2_HFOSCDIVCLKSEL);
+    pADI_CLKG0_CLK->CTL2 = tmp;
+
+    return(ADI_PWR_SUCCESS);
+}
+
+
+/*!
+ * @brief       Enable or disable the HF oscillator automatic divide by 1 during wakeup from Flexi mode.
+ *
+ *              This is used to enable/disable the fast wakeup from Flexi power mode. When the fast wakeup
+ *              from Flexi mode is enabled, the frequency undivided 26MHz HF oscillator clock itself will
+ *              be used during the wake up. The undivided HFOSC clock is selected automatically by setting
+ *              the HF oscillator divide factor to 1. This updated divided by 1 clock selection will remain
+ *              same until the new divider value is set.
+ *
+ *              When disabled the HF Oscillator divide factor will remain unchanged during the wakeup.
+ *
+ * @param[in]  bEnable :  Flag which indicates whether HF oscillator automatic divide by 1 is enabled/disabled.
+ *                        'true'  - To enable automatic divide by 1.
+ *                        'false' - To disable automatic divide by 1.
+ *
+ * @return     Status
+ *                 - #ADI_PWR_SUCCESS   Successfully enable/disabled HF Oscillator automatic divide by 1.
+ *
+ * @sa adi_pwr_SetHFOscDivFactor()
+ */
+ADI_PWR_RESULT adi_pwr_EnableHFOscAutoDivBy1( const bool bEnable )
+{
+    if(bEnable == true)
+    {
+        pADI_CLKG0_CLK->CTL2 |= BITM_CLKG_CLK_CTL2_HFOSCAUTODIV_EN;
+    }
+    else
+    {
+        pADI_CLKG0_CLK->CTL2 &= ~(BITM_CLKG_CLK_CTL2_HFOSCAUTODIV_EN);
+    }
+
+    return(ADI_PWR_SUCCESS);
+}
+
+
+/*!
+ * @brief       Set the clock output through the GPIO.
+ *
+ * @param[in]   eClockOutput : Clock to be output through the GPIO pin.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS  Successfully set the GPIO clock output.
+ */
+ADI_PWR_RESULT  adi_pwr_SetGPIOClockOutput( const ADI_CLOCK_OUTPUT_ID eClockOutput )
+{
+    uint32_t tmp;
+
+    tmp =  (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_CLKOUT);
+    tmp |= ((uint32_t)eClockOutput << BITP_CLKG_CLK_CTL0_CLKOUT);
+    pADI_CLKG0_CLK->CTL0 = tmp;
+
+    return(ADI_PWR_SUCCESS);
+}
+
+/*!
+ * @brief       Enable or disable the HPBuck Low Power mode.
+ *              The HPBUCK Low Power mode can be selected, when the Chip is in Flexi Power mode
+ *              and low power modules such as Timer, Beeper only are enabled.
+ *
+ * @param[in]   bEnable : Flag which indicates whether to enable or disable HPBuck low power mode.
+ *                        'true'  - Enable HPBuck low power mode.
+ *                        'false' - Disable HPBuck low power mode.
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS  Successfully enabled or disabled the HPBuck low power mode.
+ */
+ADI_PWR_RESULT adi_pwr_EnableHPBuckLowPowerMode( const bool bEnable )
+{
+  if(bEnable == true)
+  {
+    pADI_PMG0->CTL1  |= BITM_PMG_CTL1_HPBUCK_LOWPWR_MODE;
+  }
+  else
+  {
+    pADI_PMG0->CTL1  &= ~(BITM_PMG_CTL1_HPBUCK_LOWPWR_MODE);
+  }
+
+  return(ADI_PWR_SUCCESS);
+}
+
+/*!
+ * @brief  Set the HP Buck load mode.
+ *
+ *         HP Buck load mode can be set based on the system load.
+ *         The low load mode can be set when the system is running below 26Mhz.
+ *         The High load mode can be set when the system is running at greater than 26Mhz.
+ *
+ * @param[in]   eLoadMode : Load mode to be set.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS  Successfully set the load mode.
+ */
+ADI_PWR_RESULT adi_pwr_SetHPBuckLoadMode( const ADI_PWR_HPBUCK_LD_MODE eLoadMode )
+{
+  if(eLoadMode == ADI_PWR_HPBUCK_LD_MODE_HIGH)
+  {
+    pADI_PMG0->CTL1  |= BITM_PMG_CTL1_HPBUCK_LD_MODE;
+  }
+  else
+  {
+    pADI_PMG0->CTL1  &= ~(BITM_PMG_CTL1_HPBUCK_LD_MODE);
+  }
+
+  return(ADI_PWR_SUCCESS);
+}
+#endif /* ADUCM4x50 */
+
+/*!
+ * @brief       Enables or disables the HP Buck.
+ *
+ * @param[in]   bEnable : Flag which indicates whether to enable or disable HPBuck
+ *                        'true'  - To enable HPBuck.
+ *                        'false' - To disable HPBuck.
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS  Successfully enabled or disabled HPBUCK successfully.
+ */
+ADI_PWR_RESULT  adi_pwr_EnableHPBuck(const bool bEnable)
+{
+  if(bEnable == true)
+  {
+    pADI_PMG0->CTL1  |= BITM_PMG_CTL1_HPBUCKEN;
+  }
+  else
+  {
+    pADI_PMG0->CTL1  &= ~(BITM_PMG_CTL1_HPBUCKEN);
+  }
+
+  return(ADI_PWR_SUCCESS);
+}
+
+/*!
+ * @brief       Function to retrieve the wakeup from shut down mode status.
+ *
+ * @param[in]   peStatus    : Pointer to #ADI_PWR_WAKEUP_STATUS for returning the wakeup status.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS: Successfully returned the shut down status.
+ */
+ADI_PWR_RESULT adi_pwr_GetWakeUpStatus(ADI_PWR_WAKEUP_STATUS  *peStatus)
+{
+    *peStatus =(ADI_PWR_WAKEUP_STATUS) pADI_PMG0->SHDN_STAT;
+    return(ADI_PWR_SUCCESS);
+}
+
+
+/*!
+ * @brief      To  Monitor voltage range of battery.
+ *
+ * @param[in]   eRange    : Specify the voltage range for the battery.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS: Successfully programmed battery range.
+ *  @details
+ *
+ */
+ADI_PWR_RESULT adi_pwr_SetVoltageRange(const ADI_PWR_VOLTAGE_RANGE eRange)
+{
+    uint32_t tmp;
+
+    tmp = (pADI_PMG0->IEN & ~BITM_PMG_IEN_RANGEBAT);
+    tmp |= ((uint32_t)eRange << BITP_PMG_IEN_RANGEBAT);
+    pADI_PMG0->IEN = tmp;
+
+    return(ADI_PWR_SUCCESS);
+}
+
+/*! \cond PRIVATE */
+
+/*
+ * Interrupt handler for PLL interrupts.
+ */
+void PLL_Int_Handler(void)
+{
+     ISR_PROLOG();
+
+    /* As the same status word is shared between two interrupts
+       Crystal_osc_Int_Handler and PLL_Int_Handler
+       check and clear status bits handled in this handler */
+     uint32_t nStatus = (pADI_CLKG0_CLK->STAT0 &
+                        (BITM_CLKG_CLK_STAT0_SPLLUNLK | BITM_CLKG_CLK_STAT0_SPLLLK));
+
+     /* If a callback is registered notify the events */
+     if(gpfCallbackFunction != NULL)
+     {
+        if((nStatus & BITM_CLKG_CLK_STAT0_SPLLUNLK ) != 0u)
+        {
+            /* PLL unlock event */
+            gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_PLLC_UNLOCK,(void *)0);
+        }
+        else if((nStatus & BITM_CLKG_CLK_STAT0_SPLLLK) != 0u)
+        {
+            /* PLL lock event */
+            gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_PLLC_LOCK,(void *)0);
+        }
+        else
+        {
+           /* Do nothing */
+        }
+     }
+
+     /* Clear the status bits */
+     pADI_CLKG0_CLK->STAT0 = nStatus;
+
+     ISR_EPILOG();
+}
+
+/*
+ * Interrupt handler for oscillator interrupts.
+ */
+void Crystal_osc_Int_Handler(void)
+{
+     ISR_PROLOG();
+
+     /* As the same status word is shared between two interrupts
+        Crystal_osc_Int_Handler and PLL_Int_Handler
+        check and clear status bits handled in this handler */
+     uint32_t nClkStatus = (pADI_CLKG0_CLK->STAT0 &
+                         (BITM_CLKG_CLK_STAT0_HFXTALNOK |
+                          BITM_CLKG_CLK_STAT0_HFXTALOK  |
+                          BITM_CLKG_CLK_STAT0_LFXTALOK  |
+                          BITM_CLKG_CLK_STAT0_LFXTALNOK));
+#if defined(__ADUCM4x50__)
+     /* Check if the interrupt was generated due to failure in Root Clock or LFXTAL */
+     uint32_t nOscStatus = (pADI_CLKG0_OSC->CTL &   (BITM_CLKG_OSC_CTL_LFX_FAIL_STA   |
+                                                     BITM_CLKG_OSC_CTL_ROOT_FAIL_STA  |
+                                                     BITM_CLKG_OSC_CTL_ROOT_AUTSW_STA |
+                                                     BITM_CLKG_OSC_CTL_LFX_AUTSW_STA ));
+#endif /* __ADUCM4x50__ */
+
+     uint32_t nEvent = 0u;
+
+
+     if(gpfCallbackFunction != NULL)
+     {
+         /* Is the interrupt caused due to HFXTAL or LFXTAL status */
+         if(nClkStatus != 0u)
+         {
+                  if ((nClkStatus & BITM_CLKG_CLK_STAT0_HFXTALNOK) != 0u) { nEvent |= ADI_PWR_EVENT_OSC_HFXTAL_CLOCK_NO_OK;  }
+             else if ((nClkStatus & BITM_CLKG_CLK_STAT0_HFXTALOK)  != 0u) { nEvent |= ADI_PWR_EVENT_OSC_HFXTAL_CLOCK_OK; }
+             else if ((nClkStatus & BITM_CLKG_CLK_STAT0_LFXTALOK)  != 0u) { nEvent |= ADI_PWR_EVENT_OSC_LFXTAL_CLOCK_OK; }
+             else if ((nClkStatus & BITM_CLKG_CLK_STAT0_LFXTALNOK) != 0u) { nEvent |= ADI_PWR_EVENT_OSC_LFXTAL_CLOCK_NO_OK; }
+             else { /* do nothing */ }
+
+             if(nEvent != 0u)  { gpfCallbackFunction( gpPowcbParam, nEvent, (void *)0u); }
+
+         }
+#if defined(__ADUCM4x50__)         
+         /* Or is the interrupt caused due to Root Clock or LFXTAL failure status */
+         else if(nOscStatus != 0u)
+         {
+            /* Did the LFXTAL failed */
+            if( (nOscStatus & BITM_CLKG_OSC_CTL_LFX_FAIL_STA) != 0u)
+            {
+                /* Notifiy LFXTAL failure */
+                gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_LFXTAL_MON_FAIL, (void *)0u);
+
+                /* Did the HW auto switched to LFOSC due to LFXTAL failure */
+                if((nOscStatus & BITM_CLKG_OSC_CTL_LFX_AUTSW_STA) != 0u)
+                {
+                   /* Notify about the auto switch to LFOSC */
+                   gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_LFXTAL_AUTO_SWITCH, (void *)0u);
+                }
+            }
+            /* Did the root clock failed */
+            else if((nOscStatus & BITM_CLKG_OSC_CTL_ROOT_FAIL_STA) != 0u)
+            {
+               /* Indicate about the root clock failure */
+               gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_ROOT_CLOCK_MON_FAIL, (void *)0u);
+
+               /* Did the HW auto switched to HFOSC due to root clock failure */
+               if((nOscStatus & BITM_CLKG_OSC_CTL_ROOT_AUTSW_STA) != 0u)
+               {
+                  /* Notify about auto switch to HFOSC */
+                  gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_ROOT_CLOCK_FAIL_AUTO_SWITCH, (void *)0u);
+               }
+            }
+            else
+            {
+               /* Do nothing */
+            }
+         }
+         else
+         {
+            /* Do nothing */
+         }
+#endif /* __ADUCM4x50__ */         
+     }
+
+    /* Clear the staus bits */
+    if(nClkStatus != 0u)
+    {
+      pADI_CLKG0_CLK->STAT0 = nClkStatus;
+    }
+#if defined(__ADUCM4x50__)    
+    else if(nOscStatus  != 0u)
+    {
+        /* Write the oscillator key to clear the status bits */
+        pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+
+        /* Clear only status bits */
+        pADI_CLKG0_OSC->CTL |= nOscStatus;
+    }
+    else
+    {
+        /* Do nothing */
+    }
+#endif /* __ADUCM4x50__ */
+
+    ISR_EPILOG();
+}
+
+/*
+ * Interrupt handler for battery voltage interrupt.
+ */
+void Battery_Voltage_Int_Handler(void)
+{
+    ISR_PROLOG();
+    uint32_t nStatus = pADI_PMG0->PSM_STAT;
+
+     if ((nStatus & BITM_PMG_PSM_STAT_VBATUNDR) != 0u)
+     {
+     if(gpfCallbackFunction != NULL)
+     {
+             gpfCallbackFunction( gpPowcbParam, (uint32_t)nStatus, (void *)0);
+     }
+         pADI_PMG0->PSM_STAT |= (BITM_PMG_PSM_STAT_VBATUNDR);
+     }
+    ISR_EPILOG();
+}
+
+/*
+ * Interrupt handler for battery voltage interrupt.
+ */
+void Vreg_over_Int_Handler(void)
+{
+    ISR_PROLOG();
+     uint32_t nStatus = pADI_PMG0->PSM_STAT;
+
+     if(gpfCallbackFunction != NULL)
+     {
+        if ((nStatus & BITM_PMG_PSM_STAT_VREGOVR) != 0u)
+        {
+            gpfCallbackFunction(gpPowcbParam, (uint32_t)ADI_PWR_EVENT_VREG_OVER_VOLTAGE, NULL);
+        }
+        if ((nStatus & BITM_PMG_PSM_STAT_VREGUNDR) != 0u)
+        {
+            gpfCallbackFunction(gpPowcbParam, (uint32_t)ADI_PWR_EVENT_VREG_UNDER_VOLTAGE, NULL);
+        }
+     }
+     pADI_PMG0->PSM_STAT |= (nStatus &(BITM_PMG_PSM_STAT_VREGOVR | BITM_PMG_PSM_STAT_VREGUNDR));
+    ISR_EPILOG();
+}
+
+/*! \endcond */
+/*!
+    @brief      Puts the processor into given low power mode.
+
+    @param[in]  PowerMode          One of the ADI_PWR_POWER_MODE enum values, defining the specific
+                                   low-power modes to use.
+
+    @param[in,out] pnInterruptOccurred
+                                   Control parameter selection low-power operation.  Either a NULL pointer
+                                   for automatic hardware-based sleeping between interrupts, or a pointer
+                                   to uint32_t for software looping sleep between interrupts.
+
+                                   If a pointer to uint32_t is passed in, the integer must be \b 0 on entry,
+                                   and will be set to \b 0 on exit.
+
+                                   When a NULL is passed, it means the application wants the low-power
+                                   implementation to use the automatic "sleep-on-exit" hardware sleep
+                                   mode in which wakeup interrupts are dispatched and then automatically
+                                   put the processor back to sleep on exit.  All interrupts execute the
+                                   same WFI instruction (no looping) under hardware control, which results
+                                   in a faster re-sleep than the software mode.
+
+                                   When a non-NULL value is passed, it is interpreted as a pointer to a
+                                   shared integer application control variable allowing the wake-up
+                                   interrupts to control whether/when the control loop should re-sleep the
+                                   processor as each interrupt exits.  Any interrupt that sets the variable
+                                   will cause the sleep loop to exit.  Otherwise, exiting interrupts will
+                                   cause the core to re-sleep until the variable is set.  Each interrupt executes
+                                   a different WFI instruction inside a software loop (slower re-sleep).
+
+    @param[in]  PriorityMask       A right-justified (un shifted) wakeup interrupt priority mask, corresponding
+                                   to the programmable interrupt priority encoding scheme defined by the Cortex
+                                   NVIC controller.  The \a PriorityMask value blocks interrupts with an equal
+                                   or lower priority than the specified level, such that only higher-priority
+                                   interrupts (less in numerical value) than the priority mask awake the
+                                   processor.  A zero-valued \a PriorityMask disables interrupt masking.
+
+    @return     Status
+                    - #ADI_PWR_SUCCESS                    If successfully put the processor into low power mode.
+                    - #ADI_PWR_INVALID_PARAM[D]           PriorityMask contains unimplemented hardware bits.
+
+
+
+    Puts the processor into a low-power mode with interrupt-based wakeup(s).  Applications specify the low-power
+    mode, a pointer to an application-defined interrupt variable, and an interrupt priority mask controlling the
+    interrupt priority level that may awake the processor.
+
+    @par pnInterruptOccurred
+    When NULL, the processor is automatically put back to sleep as awaking interrupts exit.  This mode employs
+    the hardware "sleep-on-exit" system control register bit: SLEEPONEXIT_BIT in conjunction with the "wait-for-
+    interrupt" (WFI) instruction to implement a persistent sleep mode.
+
+    When non-Null, a software strategy is used to control sleeping.  As awakening interrupts are processed, they
+    can increment the interrupt controlling variable and thereby cause the sleep mode to be exited.  Note that all 
+    interrupts share a common variable and any interrupt that sets the variable will cause the sleep mode to be 
+    exited.
+
+    Use of the \a pnInterruptOccurred parameter provides a mechanism to resolve two potential hibernation trouble
+    spots: 1) the inherent race between the intended wakeup interrupt and the execution of the Wait-For-Interrupt
+    instruction (WFI) used to sleep the processor, and 2) unrelated interrupts (of sufficient priority)
+    that may terminate the wait prematurely.
+
+    In the first case of the race condition, the race is avoided by testing the \a pnInterruptOccurred variable prior
+    to the WFI within a common critical section.  This allows the #adi_pwr_EnterLowPowerMode() implementation
+    to insure the intended wakeup interrupt has not occurred already and control whether to sleep the processor.
+    This insures the intended wakeup interrupt has not already occurred prior to the wait, thereby eliminating the
+    race condition otherwise present.
+
+    In the second case of an unrelated interrupt terminating the sleep prematurely, the problem is solved by
+    requiring the interrupt handler(s) which is(are) intended to awake the sleeping processor to set the
+    application-defined \a pnInterruptOccurred variable in their respective interrupt handler(s).  This insures only those
+    interrupts that explicitly set the variable will break the sleeping processor out of the sleep cycle.  Other
+    (incidental) interrupts put the processor back to sleep after the interrupt because the variable would not have been set.
+    This is why there is a loop around the WFI instruction.
+
+    The \a pnInterruptOccurred variable must be initialized to zero before first use, and this should be done
+    prior to enabling any interrupt which may set it (otherwise interrupts may be missed). If this variable is
+    global or static then static initialization to zero or false will be sufficient.
+
+    The variable should only be set, from an interrupt handler, by calling adi_pwr_ExitLowPowerMode() and passing
+    the variable by reference. The variable should not be assigned to directly, other than for initialization.
+
+    #adi_pwr_EnterLowPowerMode() will always clear the variable again before returning, so it does not
+    need to be cleared by user code on each use. Explicitly clearing the variable, outside of #adi_pwr_EnterLowPowerMode()
+    runs the risk of missing interrupts.
+
+    @par PriorityMask
+    A zero-valued \a PriorityMask disables interrupt masking, leaving all interrupts eligible to awake the
+    sleeping processor.  This means that zero-valued interrupts cannot be masked.  A non-zero \a PriorityMask
+    limits interrupts that may awake the sleeping processor to those with a higher priority level (lower
+    numerically) than the specified \a PriorityMask value.
+
+    Each "programmable" peripheral interrupt has an associated priority-level register (which defaults to
+    zero) within the Nested Vectored Interrupt Controller (NVIC).  The number of interrupt priority encoding
+    bits is defined by constant __NVIC_PRIO_BITS and is a fixed silicon attribute configured during chip
+    design.  The interrupt priority-level registers range in width from 3 to 8 bits.
+
+    This processor uses 3-bit priority encoding, allowing priority levels ranging between 0 (the highest,
+    default programmable priority) and 7 (the lowest).  For example, if the \a PriorityMask parameter is
+    set to 3, only interrupts with assigned priority 0, 1, and 2 may awake the processor.  Since default
+    priority of all programmable interrupts is 0, setting up maskable interrupts requires that they be
+    demoted in priority (raised numerically) relative to interrupts that are intended to awake the processor.
+
+    @note    The number of priority levels is uncorrelated with the actual number of interrupts or their position
+             in the Interrupt Vector Table (IVT).  Interrupt priorities may be programmed individually.\n\n
+
+    @note    The priority levels are actually stored in the core as a left-justified value in an 8-bit field.
+             The #adi_pwr_EnterLowPowerMode() API takes care of aligning the passed \a PriorityMask value to the
+             core register (BASEPRI).\n\n
+
+    @note    The default priority level for all interrupts is zero, which implies it is impossible to mask interrupts
+             with a default zero-level priority encoding.  All interrupt priorities must be managed to create meaningful
+             interrupt masks for low-power wakeups, as described above.\n\n
+
+    @warning Do not modify the BASEPRI register (used for masking interrupt priority) during interrupts that take
+             the core out of low-power mode momentarily.  The BASEPRI register is saved/restored on low-power mode
+             entry/exit to honor user priority requests.  Interrupt-level changes to BASEPRI will be clobbered on
+             low-power exit as the saved value is restored.\n\n
+
+    @sa      adi_pwr_ExitLowPowerMode
+*/
+ADI_PWR_RESULT adi_pwr_EnterLowPowerMode ( const ADI_PWR_POWER_MODE PowerMode,
+                                           uint32_t volatile *      pnInterruptOccurred,
+                                           const uint8_t            PriorityMask
+                                         )
+{
+    uint32_t savedPriority;
+    uint32_t scrSetBits = 0u;
+    uint32_t scrClrBits = 0u;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+
+    /* verify the requested priority mask bits are right-justified and don't exceed __NVIC_PRIO_BITS in width */
+    if ((PriorityMask & ~((1u << __NVIC_PRIO_BITS) - 1u)) != 0u)
+    {
+        return ADI_PWR_INVALID_PARAM;
+    }
+
+#endif  /* ADI_DEBUG */
+
+    /* pre-calculate the sleep-on-exit set/clear bits */
+    if(NULL == pnInterruptOccurred) {
+        scrSetBits |= SCB_SCR_SLEEPONEXIT_Msk;
+
+        /* point to private control variable when in hardware (sleep-on-exit) mode */
+        pnInterruptOccurred = &gnLowPowerIntOccFlag;
+    }
+
+    /* pre-calculate the deepsleep and sleep-on-exit set/clear bits */
+    switch (PowerMode) {
+
+        case ADI_PWR_MODE_ACTIVE:    /* Note: this value is a "reserved" PWRMODE register code. */
+            return ADI_PWR_SUCCESS;  /* avoids the reserved value "1" being written to PWRMODE. */
+
+        case ADI_PWR_MODE_FLEXI:  /* wfi without deepsleep or sleep-on-exit */
+            scrClrBits |= (uint32_t)(BITM_NVIC_INTCON0_SLEEPDEEP | BITM_NVIC_INTCON0_SLEEPONEXIT);
+            break;
+
+        case ADI_PWR_MODE_HIBERNATE:  /* wfi with deepsleep and sleep-on-exit per pnInterruptOccurred setting */
+            scrSetBits |= BITM_NVIC_INTCON0_SLEEPDEEP;
+
+            break;
+
+        case ADI_PWR_MODE_SHUTDOWN:  /* wfi with both deepsleep and sleep-on-exit */
+            /* Note: sleep-on-exit causes WFI to never exit and wakeup is only through system reset. */
+            scrSetBits |= (uint32_t)(BITM_NVIC_INTCON0_SLEEPDEEP | BITM_NVIC_INTCON0_SLEEPONEXIT);
+            break;
+
+        default:
+            return ADI_PWR_INVALID_POWER_MODE;
+
+    } /* end switch */
+
+    /* put the power mode and system control mods, as well as the WFI loop inside a critical section */
+    ADI_ENTER_CRITICAL_REGION();
+
+        { /* these lines must be in a success-checking loop if they are not inside critical section */
+            /* Uninterruptable unlock sequence */
+            pADI_PMG0->PWRKEY = ADI_PMG_KEY;
+
+            /* Clear the previous mode and set new mode */
+            pADI_PMG0->PWRMOD = (uint32_t) ( ( pADI_PMG0->PWRMOD & (uint32_t) (~BITM_PMG_PWRMOD_MODE) ) | PowerMode );
+        }
+
+        /* Update the SCR (sleepdeep and sleep-on-exit bits) */
+        SCB->SCR = ((SCB->SCR | scrSetBits) & ~scrClrBits);
+
+        /* save/restore current Base Priority Level */
+        savedPriority = __get_BASEPRI();
+
+        /* assert caller's priority threshold (left-justified) */
+        __set_BASEPRI((uint32_t)PriorityMask << (8u -__NVIC_PRIO_BITS));
+        
+        /* if we are in the software looping mode, loop on the user's variable until set */
+        while (0u == *pnInterruptOccurred) {
+
+            __DSB();  /* bus sync to insure register writes from interrupt handlers are always complete before WFI */
+
+            /* NOTE: aggressive compiler optimizations can muck up critical timing here, so reduce if hangs are present */
+
+            /* The WFI loop MUST reside in a critical section because we need to insure that the interrupt
+               that is planned to take us out of WFI (via a call to adi_pwr_ExitLowPowerMode()) is not
+               dispatched until we get into the WFI.  If that interrupt sneaks in prior to our getting to the
+               WFI, then we may end up waiting (potentially forever) for an interrupt that has already occurred.
+            */
+            __WFI();
+
+            /* Recycle the critical section so that other (non-wakeup) interrupts are dispatched.
+               This allows *pnInterruptOccurred to be set from any interrupt context.
+             */
+            ADI_EXIT_CRITICAL_REGION();
+            /* nop */
+            ADI_ENTER_CRITICAL_REGION();
+
+        }  /* end while */
+
+        /* ...still within critical section... */
+
+        (*pnInterruptOccurred)--;       /* decrement the completion variable on exit */
+
+        /* Restore previous base priority */
+        __set_BASEPRI(savedPriority);
+
+        /* clear sleep-on-exit bit to avoid sleeping on exception return to thread level */
+        SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
+
+        __DSB(); /* bus sync before re-enabling interrupts */
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_PWR_SUCCESS;
+}
+
+
+/*!
+ * Companion function to #adi_pwr_EnterLowPowerMode() that allows interrupts to \n
+ * break out of the "FLEXI" mode in which the processor stays in \n
+ * sleep while peripherals are active. \n
+
+  @param[in,out] pnInterruptOccurred
+                                   Control parameter selection low-power operation. Either a NULL pointer \n
+                                   for hardware sleep-on-exit feature, or a pointer to uint32_t for software  \n
+                                   looping sleep between interrupts.
+    @return     Status
+                    - #ADI_PWR_SUCCESS                    If successfully exited from low power mode.
+
+ * @sa adi_pwr_EnterLowPowerMode
+ */
+ADI_PWR_RESULT adi_pwr_ExitLowPowerMode(uint32_t volatile * pnInterruptOccurred)
+{
+    ADI_INT_STATUS_ALLOC();
+
+    /* Manage the exit depending on pnInterruptOccurred convention... */
+    /* NULL pointer means we are using the hardware sleep-on-exit feature */
+    /* non-NULL pointer means we are using a software looping variable top sleep */
+
+    if (NULL == pnInterruptOccurred) {
+
+        pnInterruptOccurred = &gnLowPowerIntOccFlag;  /* point to private control variable in hardware mode */
+
+        /* clear hardware sleep-on-exit feature */
+        ADI_ENTER_CRITICAL_REGION();
+
+            SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
+            __DSB();  /* bus sync before interrupt exit */
+
+        ADI_EXIT_CRITICAL_REGION();
+    }
+
+    /* set control variable (whether hardware or software based) so WFI exits in SystemEnterLowPowerMode() */
+    (*pnInterruptOccurred)++;
+    return ADI_PWR_SUCCESS;
+}
+
+/*
+** EOF
+*/
+
+/*! @} */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/pwr/adi_pwr_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/pwr/adi_pwr_def.h
new file mode 100755
index 00000000000..9ba47c90ccb
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/pwr/adi_pwr_def.h
@@ -0,0 +1,235 @@
+/*
+ *****************************************************************************
+ * @file:    adi_pwr_def.h
+ * @brief:   Definitions for the system clock and power management.
+ *-----------------------------------------------------------------------------
+ *
+ * Copyright (c) 2016 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright notice,
+ *   this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ *   this list of conditions and the following disclaimer in the documentation
+ *   and/or other materials provided with the distribution.
+ * - Modified versions of the software must be conspicuously marked as such.
+ * - This software is licensed solely and exclusively for use with processors
+ *   manufactured by or for Analog Devices, Inc.
+ * - This software may not be combined or merged with other code in any manner
+ *   that would cause the software to become subject to terms and conditions
+ *   which differ from those listed here.
+ * - Neither the name of Analog Devices, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ * - The use of this software may or may not infringe the patent rights of one
+ *   or more patent holders.  This license does not release you from the
+ *   requirement that you obtain separate licenses from these patent holders
+ *   to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+ * PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef ADI_PWR_DEF_H
+#define ADI_PWR_DEF_H
+
+ /*Power control register access key */
+#define ADI_PMG_KEY             (0x4859u)
+
+ /*Osc control register access key */
+#define ADI_OSC_KEY             (0xCB14u)
+
+ /*HCLK/PCLK minimum Divider value */
+#define CLOCK_MIN_DIV_VALUE     (0x1u)
+
+ /*HCLK/PCLK maximum Divider value */
+#define CLOCK_MAX_DIV_VALUE     (32u)
+
+ /*ADC Clock minimum Divider value */
+#define ACLK_MIN_DIV_VALUE      (0x1u)
+
+ /*ADC Clock maximum Divider value */
+#define ACLK_MAX_DIV_VALUE      (511u)
+
+/* Minimum divider for PLL */
+#define MINIMUM_PLL_DIVIDER     (0x02u)
+
+/* Minimum multiplier for PLL */
+#define MINIMUM_PLL_MULTIPLIER  (0x08u)
+
+/* Maximum external clock */
+#define MAXIMUM_EXT_CLOCK       (26000000u)
+
+/* Macro mapping from ADuCM4x50 to ADuCM302x */
+#if defined(__ADUCM302x__)
+
+#define BITM_CLKG_OSC_CTL_HFOSC_EN   BITM_CLKG_OSC_CTL_HFOSCEN
+#define BITP_CLKG_OSC_CTL_HFOSC_OK   BITP_CLKG_OSC_CTL_HFOSCOK
+#define BITM_CLKG_OSC_CTL_HFX_EN     BITM_CLKG_OSC_CTL_LFXTALEN  
+#define BITM_CLKG_CLK_CTL0_PLL_IPSEL BITM_CLKG_CLK_CTL0_SPLLIPSEL
+#define BITP_CLKG_CLK_CTL0_PLL_IPSEL BITP_CLKG_CLK_CTL0_SPLLIPSEL 
+#define BITM_CLKG_OSC_CTL_LFCLK_MUX  BITM_CLKG_OSC_CTL_LFCLKMUX
+#define BITP_CLKG_OSC_CTL_LFCLK_MUX  BITP_CLKG_OSC_CTL_LFCLKMUX
+#define BITP_CLKG_OSC_CTL_HFX_EN     BITP_CLKG_OSC_CTL_HFXTALEN
+#define BITM_CLKG_OSC_CTL_HFX_OK     BITM_CLKG_OSC_CTL_HFXTALOK         
+#define BITP_CLKG_OSC_CTL_LFX_EN     BITP_CLKG_OSC_CTL_LFXTALEN
+#define BITM_CLKG_OSC_CTL_LFX_EN     BITM_CLKG_OSC_CTL_LFXTALEN
+#define BITM_CLKG_OSC_CTL_LFX_OK     BITM_CLKG_OSC_CTL_LFXTALOK
+#define BITP_CLKG_OSC_CTL_HFOSC_EN   BITP_CLKG_OSC_CTL_HFOSCEN
+#define BITM_CLKG_OSC_CTL_HFOSC_OK   BITM_CLKG_OSC_CTL_HFOSCOK
+#define BITM_CLKG_OSC_CTL_LFOSC_OK   BITM_CLKG_OSC_CTL_LFOSCOK
+#define BITM_CLKG_OSC_CTL_LFX_BYP    BITM_CLKG_OSC_CTL_LFXTAL_BYPASS
+   
+#endif /* __ADUCM302x__ */
+
+#if defined(__ADUCM4x50__)
+ /* Default osc  control register value */
+#define OSCCTRL_CONFIG_VALUE                                                                                              \
+          ( (uint32_t) ADI_PWR_LF_CLOCK_MUX                             << BITP_CLKG_OSC_CTL_LFCLK_MUX                  | \
+            (uint32_t) ADI_PWR_HFOSC_CLOCK_ENABLE                       << BITP_CLKG_OSC_CTL_HFOSC_EN                   | \
+            (uint32_t) ADI_PWR_LFXTAL_CLOCK_ENABLE                      << BITP_CLKG_OSC_CTL_LFX_EN                     | \
+            (uint32_t) ADI_PWR_HFXTAL_CLOCK_ENABLE                      << BITP_CLKG_OSC_CTL_HFX_EN                     | \
+            (uint32_t) ADI_PWR_LFXTAL_CLOCK_MON_ENABLE                  << BITP_CLKG_OSC_CTL_LFX_MON_EN                 | \
+            (uint32_t) ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE           << BITP_CLKG_OSC_CTL_LFX_AUTSW_EN               | \
+            (uint32_t) ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE                << BITP_CLKG_OSC_CTL_LFX_ROBUST_EN              | \
+            (uint32_t) ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT                << BITP_CLKG_OSC_CTL_LFX_ROBUST_LD              | \
+            (uint32_t) ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE                << BITP_CLKG_OSC_CTL_ROOT_MON_EN                | \
+            (uint32_t) ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE        << BITP_CLKG_OSC_CTL_ROOT_AUTSW_EN )
+#else
+            
+ /* Default osc control register value */
+#define OSCCTRL_CONFIG_VALUE                                                                                              \
+          ( (uint32_t) ADI_PWR_LF_CLOCK_MUX                             << BITP_CLKG_OSC_CTL_LFCLKMUX                   | \
+            (uint32_t) ADI_PWR_HFOSC_CLOCK_ENABLE                       << BITP_CLKG_OSC_CTL_HFOSCEN                    | \
+            (uint32_t) ADI_PWR_LFXTAL_CLOCK_ENABLE                      << BITP_CLKG_OSC_CTL_LFXTALEN                   | \
+            (uint32_t) ADI_PWR_HFXTAL_CLOCK_ENABLE                      << BITP_CLKG_OSC_CTL_HFXTALEN                   | \
+            (uint32_t) ADI_PWR_LFXTAL_CLOCK_MON_ENABLE                  << BITP_CLKG_OSC_CTL_LFXTAL_MON_EN )            
+#endif  /* __ADUCM4x50__ */      
+     
+#if defined(__ADUCM4x50__)            
+ /* Default clock control register-0 value */
+#define CLOCK_CTL0_CONFIG_VALUE                                                                                           \
+          ( (uint32_t) ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX                  << BITP_CLKG_CLK_CTL0_CLKMUX                    | \
+            (uint32_t) ADI_PWR_GPIO_CLOCK_OUT_SELECT                    << BITP_CLKG_CLK_CTL0_CLKOUT                    | \
+            (uint32_t) ADI_PWR_INPUT_TO_RCLK_MUX                        << BITP_CLKG_CLK_CTL0_RCLKMUX                   | \
+            (uint32_t) ADI_PWR_INPUT_TO_SPLL_MUX                        << BITP_CLKG_CLK_CTL0_PLL_IPSEL                 | \
+            (uint32_t) ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE            << BITP_CLKG_CLK_CTL0_LFXTALIE                  | \
+            (uint32_t) ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE            << BITP_CLKG_CLK_CTL0_HFXTALIE )
+#else
+/* Default clock control register-0 value */
+#define CLOCK_CTL0_CONFIG_VALUE                                                                                           \
+          ( (uint32_t) ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX                  << BITP_CLKG_CLK_CTL0_CLKMUX                    | \
+            (uint32_t) ADI_PWR_INPUT_TO_RCLK_MUX                        << BITP_CLKG_CLK_CTL0_RCLKMUX                   | \
+            (uint32_t) ADI_PWR_INPUT_TO_SPLL_MUX                        << BITP_CLKG_CLK_CTL0_SPLLIPSEL                 | \
+            (uint32_t) ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE            << BITP_CLKG_CLK_CTL0_LFXTALIE                  | \
+            (uint32_t) ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE            << BITP_CLKG_CLK_CTL0_HFXTALIE )            
+#endif            
+            
+ /* Default clock control register-1 value */
+#define CLOCK_CTL1_CONFIG_VALUE                                                                                           \
+          ( (uint32_t) ADI_PWR_HCLK_DIVIDE_COUNT                        << BITP_CLKG_CLK_CTL1_HCLKDIVCNT                | \
+            (uint32_t) ADI_PWR_PCLK_DIVIDE_COUNT                        << BITP_CLKG_CLK_CTL1_PCLKDIVCNT                | \
+            (uint32_t) ADI_PWR_ACLK_DIVIDE_COUNT                        << BITP_CLKG_CLK_CTL1_ACLKDIVCNT )
+
+#if defined(__ADUCM4x50__)            
+/* Default clock control register-2 value */
+#define CLOCK_CTL2_CONFIG_VALUE                                                                                           \
+          ( (uint32_t) ADI_PWR_HFOSC_AUTO_DIV_BY_1                      << BITP_CLKG_CLK_CTL2_HFOSCAUTODIV_EN           | \
+            (uint32_t) ADI_PWR_HFOSC_DIVIDE_SELECT                      << BITP_CLKG_CLK_CTL2_HFOSCDIVCLKSEL )
+            
+#endif /* __ADUCM4x50__ */
+            
+ /* Default clock control register-3 value */
+#define CLOCK_CTL3_CONFIG_VALUE                                                                                           \
+          ( (uint32_t) ADI_PWR_SPLL_MUL_FACTOR                          << BITP_CLKG_CLK_CTL3_SPLLNSEL                  | \
+            (uint32_t) ADI_PWR_SPLL_ENABLE_DIV2                         << BITP_CLKG_CLK_CTL3_SPLLDIV2                  | \
+            (uint32_t) ADI_PWR_SPLL_ENABLE                              << BITP_CLKG_CLK_CTL3_SPLLEN                    | \
+            (uint32_t) ADI_PWR_SPLL_INTERRUPT_ENABLE                    << BITP_CLKG_CLK_CTL3_SPLLIE                    | \
+            (uint32_t) ADI_PWR_SPLL_DIV_FACTOR                          << BITP_CLKG_CLK_CTL3_SPLLMSEL                  | \
+            (uint32_t) ADI_PWR_SPLL_ENABLE_MUL2                         << BITP_CLKG_CLK_CTL3_SPLLMUL2 )
+
+#if defined(__ADUCM4x50__)            
+ /* Default clock control register-5 value */
+#define CLOCK_CTL5_CONFIG_VALUE                                                                                           \
+          ( (uint32_t) ADI_PWR_GPT0_CLOCK_ENABLE                        << BITP_CLKG_CLK_CTL5_GPTCLK0OFF                | \
+            (uint32_t) ADI_PWR_GPT1_CLOCK_ENABLE                        << BITP_CLKG_CLK_CTL5_GPTCLK1OFF                | \
+            (uint32_t) ADI_PWR_GPT2_CLOCK_ENABLE                        << BITP_CLKG_CLK_CTL5_GPTCLK2OFF                | \
+            (uint32_t) ADI_PWR_I2C_CLOCK_ENABLE                         << BITP_CLKG_CLK_CTL5_UCLKI2COFF                | \
+            (uint32_t) ADI_PWR_GPIO_CLOCK_ENABLE                        << BITP_CLKG_CLK_CTL5_GPIOCLKOFF                | \
+            (uint32_t) ADI_PWR_PCLK_ENABLE                              << BITP_CLKG_CLK_CTL5_PERCLKOFF                 | \
+            (uint32_t) ADI_PWR_TIMER_RGB_ENABLE                         << BITP_CLKG_CLK_CTL5_TMRRGBCLKOFF )
+#else
+ /* Default clock control register-5 value */
+#define CLOCK_CTL5_CONFIG_VALUE                                                                                           \
+          ( (uint32_t) ADI_PWR_GPT0_CLOCK_ENABLE                        << BITP_CLKG_CLK_CTL5_GPTCLK0OFF                | \
+            (uint32_t) ADI_PWR_GPT1_CLOCK_ENABLE                        << BITP_CLKG_CLK_CTL5_GPTCLK1OFF                | \
+            (uint32_t) ADI_PWR_GPT2_CLOCK_ENABLE                        << BITP_CLKG_CLK_CTL5_GPTCLK2OFF                | \
+            (uint32_t) ADI_PWR_I2C_CLOCK_ENABLE                         << BITP_CLKG_CLK_CTL5_UCLKI2COFF                | \
+            (uint32_t) ADI_PWR_GPIO_CLOCK_ENABLE                        << BITP_CLKG_CLK_CTL5_GPIOCLKOFF                | \
+            (uint32_t) ADI_PWR_PCLK_ENABLE                              << BITP_CLKG_CLK_CTL5_PERCLKOFF )
+#endif
+            
+/* Default configuration for Power supply monitor Interrupt Enable Register */            
+#define PWM_INTERRUPT_CONFIG                                                                                              \
+          ( (uint32_t) ADI_PWR_ENABLE_VBAT_INTERRUPT                    << BITP_PMG_IEN_VBAT                            | \
+            (uint32_t) ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT      << BITP_PMG_IEN_VREGUNDR                        | \
+            (uint32_t) ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT       << BITP_PMG_IEN_VREGOVR                         | \
+            (uint32_t) ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT   << BITP_PMG_IEN_IENBAT                          | \
+            (uint32_t) ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT      << BITP_PMG_IEN_RANGEBAT )
+            
+ /* Default configuration for Power Mode Register */            
+ #define PWM_PWRMOD_CONFIG                                                                                                \
+         (  (uint32_t) ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING        << BITP_PMG_PWRMOD_MONVBATN ) 
+ 
+#if defined(__ADUCM4x50__)              
+/* Default configuration for HP Buck Control register */
+#define PWM_HPBUCK_CONTROL                                                                                                \
+         (  (uint32_t) ADI_PWR_HP_BUCK_ENABLE                           << BITP_PMG_CTL1_HPBUCKEN                       | \
+            (uint32_t) ADI_PWR_HP_BUCK_LOAD_MODE                        << BITP_PMG_CTL1_HPBUCK_LD_MODE                 | \
+            (uint32_t) ADI_PWR_HP_BUCK_LOW_POWER_MODE                   << BITP_PMG_CTL1_HPBUCK_LOWPWR_MODE )  
+#else
+/* Default configuration for HP Buck Control register */
+#define PWM_HPBUCK_CONTROL                                                                                                \
+         (  (uint32_t) ADI_PWR_HP_BUCK_ENABLE                           << BITP_PMG_CTL1_HPBUCKEN )
+#endif            
+
+ /*Selecting HFOSC as input for generating root clock*/
+#define HFMUX_INTERNAL_OSC_VAL      (0u << BITP_CLKG_CLK_CTL0_CLKMUX)
+
+ /*Selecting HFXTAL as input for generating root clock*/
+#define HFMUX_EXTERNAL_XTAL_VAL     (1u << BITP_CLKG_CLK_CTL0_CLKMUX)
+
+ /*Selecting SPLL as input for generating root clock*/
+#define HFMUX_SYSTEM_SPLL_VAL       (2u << BITP_CLKG_CLK_CTL0_CLKMUX)
+
+ /*Selecting GPIO as input for generating root clock*/
+#define HFMUX_GPIO_VAL              (3u << BITP_CLKG_CLK_CTL0_CLKMUX)
+
+/* Interrupt handler for the battery voltage interrupt */
+void Battery_Voltage_Int_Handler(void);
+/* Interrupt handler for the VREG under/over voltage interrupt */
+void Vreg_over_Int_Handler(void);
+/* Interrupt handler for PLL interrupts. */
+void PLL_Int_Handler(void);     
+/*Interrupt handler for oscillator interrupts.*/                                 
+void Crystal_osc_Int_Handler(void);
+
+#endif /* ADI_PWR_DEF_H */
+
+
+/*
+** EOF
+*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rng/adi_rng.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rng/adi_rng.c
new file mode 100755
index 00000000000..c771cca5cd8
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rng/adi_rng.c
@@ -0,0 +1,796 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_rng.c
+ * @brief:   Random Number Generator Driver
+ *----------------------------------------------------------------------------
+ *
+Copyright (c) 2012-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+/*! \addtogroup RNG_Driver RNG Driver
+ *  Random Number Generator Driver
+ *  @{
+ */
+
+ /*! \cond PRIVATE */
+
+#include <stdlib.h>  /* for 'NULL' definition */
+#include <assert.h>
+
+#include <adi_processor.h>
+#include <drivers/rng/adi_rng.h>
+#include "adi_rng_def.h"
+#include <rtos_map/adi_rtos_map.h>
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm011 (rule 6.3): Types which specify sign and size should be used
+*   We use bool which is accepted by MISRA but the toolchain does not accept it
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+*
+* Pm050 (rule 14.2): a null statement shall only occur on a line by itself
+*   Needed for null expansion of ISR_PROLOG in no-OS case and others.
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   The rule makes an exception for memory-mapped register accesses.
+*/
+#pragma diag_suppress=Pm011,Pm073,Pm143,Pm050
+#endif /* __ICCARM__ */
+
+#if   defined(__ADUCM4x50__) ||   defined(__ADUCM302x__)
+#define NUM_RNG_DEVICES       (1u)
+#else
+#error "Unsupported processor"
+#endif
+
+/*==============  D A T A  ===============*/
+
+/**
+ * Information for managing all the RNG devices available
+ */
+#ifdef __ICCARM__
+#pragma diag_suppress=Pm140
+#endif
+
+static ADI_RNG_DEV_TYPE gRNG_Device[NUM_RNG_DEVICES] =
+{
+  {(ADI_RNG_TypeDef*)pADI_RNG0,NULL} /* RNG0 */
+};
+#ifdef __ICCARM__
+#pragma diag_default=Pm140
+#endif
+
+/* Forward prototypes */
+void RNG_Int_Handler(void);
+
+/** Check the validity of a handle for debug mode */
+#ifdef ADI_DEBUG
+#define ADI_RNG_INVALID_HANDLE(h) (&gRNG_Device[0] != (h))
+#endif
+
+/*! \endcond */
+
+/*!
+    @brief Opena a Random Number Generator Device
+
+    @param[in]  nDeviceNum   Device number to be opened.
+    @param[in]  pMemory      Pointer to the memory to be used by the driver.
+                             Size of the memory should be at least #ADI_RNG_MEMORY_SIZE bytes.
+    @param[in]  MemorySize   Size of the memory passed in pMemory parameter.
+    @param[out] phDevice     Pointer to a location in the calling function memory space to which
+                             the device handle will be written upon successful driver initialization.
+
+    @return    Status
+               - #ADI_RNG_SUCCESS                      RNG device driver opened successfully.
+               - #ADI_RNG_INVALID_PARAM [D]            The memory passed to the API is either NULL or its size is not sufficient.
+               - #ADI_RNG_ALREADY_INITIALIZED [D]  The RNG is already initialized.
+               - #ADI_RNG_BAD_DEVICE_NUM [D]       The device number is invalid.
+
+    Initialize and allocate a RNG device for other use.  The core NVIC RNG interrupt is enabled.  This API
+    must preceed all other RNG API calls and the handle returned must be passed to all other RNG API calls.
+
+    @note   The contents of \a ppDevice will be set to NULL upon failure.\n\n
+
+    @note   The RNG device driver will clear all pending interrupts and disable all RNG
+            interrupts during RNG device initialization.
+
+    @sa    adi_rng_Close().
+*/
+ADI_RNG_RESULT adi_rng_Open(
+                            uint32_t             const  nDeviceNum,
+                            void*                const  pMemory,
+                            uint32_t             const  MemorySize,
+                            ADI_RNG_HANDLE*      const  phDevice
+                            )
+{
+    ADI_RNG_DEV_TYPE *pDevice;
+
+    /* store a bad handle in case of failure */
+    *phDevice = (ADI_RNG_HANDLE) NULL;
+
+#ifdef ADI_DEBUG
+    if (nDeviceNum >= NUM_RNG_DEVICES)
+    {
+        return ADI_RNG_BAD_DEVICE_NUM;
+    }
+
+    if ((NULL == pMemory) || ( MemorySize < (uint32_t) ADI_RNG_MEMORY_SIZE))
+    {
+        return ADI_RNG_INVALID_PARAM;
+    }
+    assert (ADI_RNG_MEMORY_SIZE == sizeof(ADI_RNG_DEV_DATA_TYPE));
+#endif
+
+    /* local pointer to instance data */
+    pDevice = &gRNG_Device[nDeviceNum];
+
+#ifdef ADI_DEBUG
+    if (NULL != pDevice->pData)
+    {
+        return ADI_RNG_ALREADY_INITIALIZED;
+    }
+#endif
+
+    /* Set the internal device data */
+    pDevice->pData = pMemory;
+
+    /* initialize internal device data */
+    pDevice->pData->IRQn    = RNG0_EVT_IRQn;
+    pDevice->pData->CBFunc  = NULL;
+
+    /* clear any pending interrupts. Both bits are write 1 to clear */
+    pDevice->pRNG->STAT = BITM_RNG_STAT_RNRDY | BITM_RNG_STAT_STUCK;
+
+    /* Set the RNG register based on static configuration */
+    pDevice->pRNG->CTL = (uint16_t)RNG0_CFG_ONLY_8_BIT << BITP_RNG_CTL_SINGLE;
+    pDevice->pRNG->LEN = (RNG0_CFG_LENGTH_RELOAD << BITP_RNG_LEN_RELOAD)
+                       | (RNG0_CFG_LENGTH_PRESCALER << BITP_RNG_LEN_PRESCALE);
+
+   /* The interrupt handler only gets used in the case of callback mode so its
+    * enabling only happens in the adi_rng_RegisterCallBack API.
+    */
+    NVIC_ClearPendingIRQ(pDevice->pData->IRQn);
+
+    /* store handle at application handle pointer */
+    *phDevice = pDevice;
+
+    return ADI_RNG_SUCCESS;
+}
+
+
+/*!
+ * @brief  Uninitializes and deallocates the RNG device.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rng_Open().
+ *
+ * @return      Status
+ *                - #ADI_RNG_SUCCESS                    Call completed successfully.
+ *                - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+ *
+ * Uninitialize and release an allocated RNG device for other use.  The core NVIC RNG interrupt is disabled.
+ *
+ * @sa        adi_rng_Open().
+ */
+ADI_RNG_RESULT adi_rng_Close(ADI_RNG_HANDLE hDevice)
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+
+#ifdef ADI_DEBUG
+    if (ADI_RNG_INVALID_HANDLE(pDevice)){
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (NULL == pDevice->pData) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+#endif
+
+    /* uninitialize */
+    NVIC_DisableIRQ(pDevice->pData->IRQn);
+    pDevice->pData = NULL;
+
+    return ADI_RNG_SUCCESS;
+}
+
+/*!
+ * @brief  Enables/Disables the RNG device.
+ *
+ * @param[in]   hDevice       Device handle obtained from adi_rng_Open().
+ * @param[in]   bFlag         Flag to specify whether to enable or disable RNG device.
+ *
+ * @return      Status
+ *                - #ADI_RNG_SUCCESS                    Call completed successfully.
+ *                - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+ *
+ * @sa        adi_rng_Open().
+ * @sa        adi_rng_RegisterCallback().
+ */
+ADI_RNG_RESULT adi_rng_Enable (ADI_RNG_HANDLE const hDevice, bool const bFlag)
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    if (ADI_RNG_INVALID_HANDLE(pDevice)) {
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (NULL == pDevice->pData) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+#endif
+
+    ADI_ENTER_CRITICAL_REGION();
+    if (true == bFlag) {
+        pDevice->pRNG->CTL |= BITM_RNG_CTL_EN;
+    } else {
+        pDevice->pRNG->CTL &= (uint16_t)~(BITM_RNG_CTL_EN);
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_RNG_SUCCESS;
+}
+
+/*!
+ * @brief  Enables/Disables Buffering for RNG.
+ *
+ * @param[in]   hDevice       Device handle obtained from adi_rng_Open().
+ * @param[in]   bFlag         Flag to specify whether to enable or disable buffering for RNG device.
+ *                            When buffering is enabled, adi_rng_GetRngData returns 32-bit values.
+ *                            When buffering is disabled the API returns 8-bit values.
+ *
+ * @return      Status
+ *                - #ADI_RNG_SUCCESS                    Call completed successfully.
+ *                - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+ *
+ * @sa        adi_rng_Open().
+ * @sa        adi_rng_RegisterCallback().
+ * @sa        adi_rng_GetRngData().
+ */
+ADI_RNG_RESULT adi_rng_EnableBuffering (ADI_RNG_HANDLE const hDevice, bool const bFlag)
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    if (ADI_RNG_INVALID_HANDLE(pDevice)) {
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (NULL == pDevice->pData) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+#endif
+
+    ADI_ENTER_CRITICAL_REGION();
+    if (true == bFlag) {
+        pDevice->pRNG->CTL &= (uint16_t)~(BITM_RNG_CTL_SINGLE);
+    } else {
+        pDevice->pRNG->CTL |= BITM_RNG_CTL_SINGLE;
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_RNG_SUCCESS;
+}
+
+/*!
+ * @brief  Sets the reload and prescale value for the sample counter.
+ *         The Sample Length will be nLenReload*2^nLenPrescaler.
+ *
+ * @param[in]   hDevice        Device handle obtained from adi_rng_Open().
+ * @param[in]   nLenPrescaler  Prescaler value for the sample counter (0-10).
+ * @param[in]   nLenReload     Reload value for the sample counter (0-4095)
+ *
+ * @return      Status
+ *                - #ADI_RNG_SUCCESS                    Call completed successfully.
+ *                - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+ *
+ * @sa        adi_rng_Open().
+ * @sa        adi_rng_RegisterCallback().
+ */
+ADI_RNG_RESULT adi_rng_SetSampleLen (
+                                     ADI_RNG_HANDLE const hDevice,
+                                     uint16_t       const nLenPrescaler,
+                                     uint16_t       const nLenReload
+                                     )
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    if (ADI_RNG_INVALID_HANDLE(pDevice)){
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (NULL == pDevice->pData) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+
+    if (   (nLenPrescaler > 10u)
+        || ((0u == nLenPrescaler) && (0u == nLenReload))
+        || (nLenReload > 4095u)) {
+        return ADI_RNG_INVALID_PARAM;
+    }
+#endif
+
+    ADI_ENTER_CRITICAL_REGION();
+    /* Set the sample reload and prescaler value */
+    pDevice->pRNG->LEN =   (uint16_t)((uint16_t)(nLenReload    << BITP_RNG_LEN_RELOAD)   & BITM_RNG_LEN_RELOAD)
+                         | (uint16_t)((uint16_t)(nLenPrescaler << BITP_RNG_LEN_PRESCALE) & BITM_RNG_LEN_PRESCALE);
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_RNG_SUCCESS;
+}
+
+
+/*!
+ * @brief  Retrieves the current state of RNG data/CRC accumulator register.
+ *
+ * @param[in]   hDevice       Device handle obtained from adi_rng_Open().
+ * @param[out]  pbFlag        Pointer to an application-defined boolean variable into which to write the result:
+ *                              - true  = RNG data is ready to be read.
+ *                              - false = RNG data is not ready.
+ *
+ * @return      Status
+ *                - #ADI_RNG_SUCCESS                    Call completed successfully.
+ *                - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+                  - #ADI_RNG_INVALID_PARAM [D]          Argument is incorrect.
+ *
+ * Retrieve the current state of RNG data/CRC accumulator register. The register holds the final entropy value
+ * accumulated by RNG and it should to read only when the data is ready.
+ *
+ * @sa        adi_rng_Open().
+ * @sa        adi_rng_GetRngData().
+ * @sa        adi_rng_RegisterCallback().
+ */
+ADI_RNG_RESULT adi_rng_GetRdyStatus (ADI_RNG_HANDLE const hDevice, bool* const pbFlag)
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+
+#ifdef ADI_DEBUG
+    if (ADI_RNG_INVALID_HANDLE(pDevice)){
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (NULL == pDevice->pData) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+
+    if (NULL == pbFlag) {
+        return ADI_RNG_INVALID_PARAM;
+    }
+#endif
+
+    /* Get the RNG Ready status bit */
+    if ((pDevice->pRNG->STAT & BITM_RNG_STAT_RNRDY) != 0u)
+    {
+        *pbFlag = true;
+    }
+    else
+    {
+        *pbFlag = false;
+    }
+
+    return ADI_RNG_SUCCESS;
+}
+
+/*!
+ * @brief  Retrieve whether the RNG oscillator output is stuck at a constant value
+ *
+ * @param[in]   hDevice       Device handle obtained from adi_rng_Open().
+ * @param[out]  pbFlag        Pointer to an application-defined boolean variable into which to write the result:
+ *                              - true  = RNG oscillator is stuck at a constant value.
+ *                              - false = RNG oscillator is not stuck at a constant value.
+ *
+ * @return      Status
+ *                - #ADI_RNG_SUCCESS                    Call completed successfully.
+ *                - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+                  - #ADI_RNG_INVALID_PARAM [D]          Argument is incorrect.
+ *
+ * @sa        adi_rng_Open().
+ * @sa        adi_rng_GetRngData().
+ * @sa        adi_rng_RegisterCallback().
+ */
+ADI_RNG_RESULT adi_rng_GetStuckStatus (
+                                       ADI_RNG_HANDLE const hDevice,
+                                       bool* const pbFlag
+                                       )
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+
+#ifdef ADI_DEBUG
+    if (ADI_RNG_INVALID_HANDLE(pDevice)){
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (pDevice->pData == NULL) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+
+    if (NULL == pbFlag) {
+        return ADI_RNG_INVALID_PARAM;
+    }
+#endif
+
+    /* Get the stuck status bit */
+    if ((pDevice->pRNG->STAT & BITM_RNG_STAT_STUCK) != 0u)
+    {
+        *pbFlag = true;
+    }
+    else
+    {
+        *pbFlag = false;
+    }
+
+    return ADI_RNG_SUCCESS;
+}
+
+
+/*!
+ * @brief  Retrieve the current value of the RNG data register.
+ *
+ * @param[in]   hDevice       Device handle obtained from adi_rng_Open().
+ * @param[in]   pRegData      Pointer to an application-defined variable into which to write the result.
+ *                            Only lower 8-bit is valid if buffering is not enabled
+ *
+ * @return      Status
+ *                - #ADI_RNG_SUCCESS                    Call completed successfully.
+ *                - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+ *                - #ADI_RNG_INVALID_PARAM [D]      pRegData is a NULL pointer.
+ *                - #ADI_RNG_INVALID_STATE[D]       Random number ready status is not set
+ *
+ * Retrieve the current value of RNG data register. If the buffering is enabled all 32-bit of value written to
+ * pRegData is valid else only the lower 8-bit is valid.
+ *
+ * @sa        adi_rng_Open().
+ * @sa        adi_rng_GetRdyStatus().
+ * @sa        adi_rng_RegisterCallback().
+ */
+ADI_RNG_RESULT adi_rng_GetRngData (ADI_RNG_HANDLE const hDevice, uint32_t* const pRegData)
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+
+#ifdef ADI_DEBUG
+    if (ADI_RNG_INVALID_HANDLE(pDevice)){
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (NULL == pDevice->pData) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+
+    if (NULL == pRegData) {
+        return ADI_RNG_INVALID_PARAM;
+    }
+
+    if ((pDevice->pRNG->STAT & BITM_RNG_STAT_RNRDY) == 0u) {
+        return ADI_RNG_INVALID_STATE;
+    }
+#endif
+
+    /* Get the RNG CRC accumulator value */
+    *pRegData = pDevice->pRNG->DATA;
+
+    return ADI_RNG_SUCCESS;
+}
+
+
+/*!
+ * @brief  Retrieve the current RNG Oscillator count.
+ *
+ * @param[in]   hDevice       Device handle obtained from adi_rng_Open().
+ * @param[in]   pOscCount     Pointer to an application-defined variable into which to write the result.
+ *
+ * @return      Status
+ *                - #ADI_RNG_SUCCESS                    Call completed successfully.
+ *                - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+ *                - #ADI_RNG_INVALID_STATE[D]       Random number ready status is not set
+                  - #ADI_RNG_INVALID_PARAM [D]          Argument is incorrect.
+ *
+ * @sa        adi_rng_Open().
+ * @sa        adi_rng_RegisterCallback().
+ */
+ADI_RNG_RESULT adi_rng_GetOscCount (ADI_RNG_HANDLE const hDevice, uint32_t* const pOscCount)
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+
+#ifdef ADI_DEBUG
+   if (ADI_RNG_INVALID_HANDLE(pDevice)){
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (NULL == pDevice->pData) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+
+    if (NULL == pOscCount) {
+        return (ADI_RNG_INVALID_PARAM);
+    }
+
+    if ((pDevice->pRNG->STAT & BITM_RNG_STAT_RNRDY) == 0u) {
+        return ADI_RNG_INVALID_STATE;
+    }
+#endif
+
+    /* Get the oscillator count high count */
+    *pOscCount = pDevice->pRNG->OSCCNT;
+
+    return ADI_RNG_SUCCESS;
+}
+
+/*!
+ * @brief  Retrieve the current RNG Oscillator difference value for the given index.
+ *
+ * @param[in]   hDevice     Device handle obtained from adi_rng_Open().
+ * @param[in]   nIndex      Index of the difference register.
+ * @param[out]  pOscDiff    Pointer to an application-defined variable into which to
+ *                          write the oscillator difference value for the given index.
+ *
+ * @return      Status
+ *              - #ADI_RNG_SUCCESS                    Call completed successfully.
+ *              - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *              - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+ *              - #ADI_RNG_INVALID_STATE[D]       Random number ready status is not set
+                - #ADI_RNG_INVALID_PARAM [D]          Argument is incorrect.
+ *
+ * @sa        adi_rng_Open().
+ * @sa        adi_Rng_RegisterCallback().
+ */
+ADI_RNG_RESULT adi_rng_GetOscDiff (
+                                   ADI_RNG_HANDLE const hDevice,
+                                   uint32_t       const nIndex,
+                                   uint8_t*       const pOscDiff
+                                   )
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+
+#ifdef ADI_DEBUG
+   if (ADI_RNG_INVALID_HANDLE(pDevice)){
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (NULL == pDevice->pData) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+
+    if ((NULL == pOscDiff) || (nIndex > 3u)) {
+        return( ADI_RNG_INVALID_PARAM );
+    }
+
+    if ((pDevice->pRNG->STAT & BITM_RNG_STAT_RNRDY) == 0u) {
+        return ADI_RNG_INVALID_STATE;
+    }
+#endif
+
+    /* Get the Osc Difference Register */
+    *pOscDiff = (uint8_t)pDevice->pRNG->OSCDIFF[nIndex];
+
+    return ADI_RNG_SUCCESS;
+}
+
+/*!
+ * @brief  Retrieve the current RNG sample length prescale and reload value configured in the device.
+ *
+ * @param[in]   hDevice        Device handle obtained from adi_rng_Open().
+ * @param[out]  pLenPrescaler  Pointer to an application-defined variable into which the prescaler value is written.
+ * @param[out]  pLenReload     Pointer to an application-defined variable into which the reload value for the sample counter is written.
+ *
+ * @return      Status
+ *                - #ADI_RNG_SUCCESS                    Call completed successfully.
+ *                - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+                  - #ADI_RNG_INVALID_PARAM [D]          Argument is incorrect.
+ *
+ *
+ * @sa        adi_rng_Open().
+ * @sa        adi_rng_RegisterCallback().
+ */
+ADI_RNG_RESULT adi_rng_GetSampleLen (
+                                     ADI_RNG_HANDLE const hDevice,
+                                     uint16_t*      const pLenPrescaler,
+                                     uint16_t*      const pLenReload
+                                     )
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+
+#ifdef ADI_DEBUG
+   if (ADI_RNG_INVALID_HANDLE(pDevice)){
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (NULL == pDevice->pData) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+
+    if ((NULL == pLenPrescaler) || (NULL == pLenReload)) {
+        return ADI_RNG_INVALID_PARAM;
+    }
+#endif
+
+    *pLenPrescaler = (pDevice->pRNG->LEN & BITM_RNG_LEN_PRESCALE) >> BITP_RNG_LEN_PRESCALE;
+    *pLenReload    = (pDevice->pRNG->LEN & BITM_RNG_LEN_RELOAD)   >> BITP_RNG_LEN_RELOAD;
+
+    return ADI_RNG_SUCCESS;
+}
+
+
+/*************************************************************************************************
+**************************************************************************************************
+*****************************************   CALLBACKS   ******************************************
+*****************************************      AND      ******************************************
+*****************************************   INTERRUPT   ******************************************
+**************************************************************************************************
+*************************************************************************************************/
+
+
+/*!
+    @brief RNG Application callback registration API.
+
+    @param[in]   hDevice     Device handle obtained from #adi_rng_Open().
+    @param[in]   cbFunc      Application callback address; the function to call on the interrupt.
+    @param[in]   pCBParam    Application handle to be passed in the call back.
+
+    @return    Status
+               - #ADI_RNG_SUCCESS                    The callback is successfully registered.
+               - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+               - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+
+    Registers an application-defined callback \a cbFunc function address of type ADI_CALLBACK with the RNG device driver.
+    Callbacks are made in response to received RNG interrupts.
+
+    The callback to the application is made in context of the originating interrupt (i.e., the RNG driver's
+    RNG interrupt handler that is registered in the system's interrupt vector table).  Extended processing
+    during the callback (an extension of the RNG's interrupt handler) is discouraged so as to avoid lower-priority
+    interrupt blocking.  Also, any register read-modify-write operations should be protected using the
+    ADI_ENTER_CRITICAL_REGION()/ADI_EXIT_CRITICAL_REGION() pair to prevent higher-priority interrupts from modifying
+    said register during the read-modify-write operation.
+
+    @note   CALLBACKS: RNG interrupt callbacks are \b disabled by default during RNG device driver
+            initialization (#adi_rng_Open()).  The application uses the #adi_rng_RegisterCallback()
+            API to request an application-defined callback from the RNG device driver. The RNG device
+            driver clears the interrupt when the callback exits.
+            The application callback should <b>avoid extended processing</b>
+            during callbacks as the callback is executing context of the initiating interrupt and will
+            block lower-priority interrupts.  If extended application-level interrupt processing is
+            required, the application should schedule it for the main application loop and exit the
+            callback as soon as possible.\n
+
+
+    @sa    adi_rng_Open().
+*/
+ADI_RNG_RESULT adi_rng_RegisterCallback (
+                                         ADI_RNG_HANDLE  hDevice,
+                                         ADI_CALLBACK    cbFunc,
+                                         void           *pCBParam)
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+
+#ifdef ADI_DEBUG
+   if (ADI_RNG_INVALID_HANDLE(pDevice)){
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (NULL == pDevice->pData) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+#endif
+
+    /* save the callback info */
+    pDevice->pData->CBFunc   = cbFunc;
+    pDevice->pData->pCBParam = pCBParam;
+
+    if (NULL != cbFunc) {
+        /* enable RNG interrupts in NVIC */
+        NVIC_EnableIRQ(pDevice->pData->IRQn);
+    } else {
+        NVIC_DisableIRQ(pDevice->pData->IRQn);
+    }
+
+    return ADI_RNG_SUCCESS;
+}
+
+/*! \cond PRIVATE */
+/* RNG driver interrupt handler. Overrides weak default handler in startup file */
+void RNG_Int_Handler(void)
+{
+    ISR_PROLOG();
+    ADI_RNG_DEV_TYPE *pDevice = &gRNG_Device[0];
+    register uint16_t candidate;
+
+    /* if we have an initialized driver... */
+    if (NULL != pDevice->pData)
+    {
+        /* if we have a registered callback */
+        if (NULL != pDevice->pData->CBFunc)
+        {
+            ADI_INT_STATUS_ALLOC();
+
+            ADI_ENTER_CRITICAL_REGION();
+            /* read status register without other interrupts in between */
+            candidate = pDevice->pRNG->STAT;
+            ADI_EXIT_CRITICAL_REGION();
+
+            /* Only have bits in stat that are necessary */
+            candidate = candidate & (BITM_RNG_STAT_STUCK | BITM_RNG_STAT_RNRDY);
+
+            while (0u != candidate) {
+                uint32_t nEvent;
+
+                if (0u != (candidate & BITM_RNG_STAT_RNRDY)) {
+                    nEvent = ADI_RNG_EVENT_READY;
+                    candidate &= (uint16_t)~BITM_RNG_STAT_RNRDY;
+                } else if (0u != (candidate & BITM_RNG_STAT_STUCK)) {
+                    nEvent = ADI_RNG_EVENT_STUCK;
+                    candidate &= (uint16_t)~BITM_RNG_STAT_STUCK;
+                } else {
+                    break;
+                }
+
+                pDevice->pData->CBFunc (
+                                        pDevice->pData->pCBParam,
+                                        nEvent,
+                                        NULL
+                                        );
+            }
+
+            pDevice->pRNG->STAT = BITM_RNG_STAT_RNRDY | BITM_RNG_STAT_STUCK;
+        }
+    }
+    ISR_EPILOG();
+}
+/*! \endcond */
+
+/*
+** EOF
+*/
+
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rng/adi_rng_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rng/adi_rng_def.h
new file mode 100755
index 00000000000..462861d976a
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rng/adi_rng_def.h
@@ -0,0 +1,69 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_rng_def.h
+ * @brief:   Random Number Generator Driver private data structures
+ *----------------------------------------------------------------------------
+ *
+Copyright (c) 2012-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#ifndef ADI_RNG_DEF_H
+#define ADI_RNG_DEF_H
+
+ /*! \cond PRIVATE */
+
+
+/*! RNG device internal instance data structure */
+typedef struct __ADI_RNG_DEV_DATA_TYPE
+{
+    IRQn_Type                      IRQn;      /*!< RNG interrupt number       */
+    ADI_CALLBACK                   CBFunc;    /*!< Callback function          */
+    void                          *pCBParam;  /*!< Callback parameter         */
+} ADI_RNG_DEV_DATA_TYPE;
+
+/*! RNG device internal data structure */
+typedef struct __ADI_RNG_DEV_TYPE
+{
+    volatile ADI_RNG_TypeDef      *pRNG;      /*!< MMR address for this RNG   */
+    ADI_RNG_DEV_DATA_TYPE         *pData;     /*!< Pointer to instance data   */
+} ADI_RNG_DEV_TYPE;
+
+
+/*! \endcond */
+#endif /* ADI_RNG_DEF_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtc/adi_rtc.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtc/adi_rtc.c
new file mode 100755
index 00000000000..3efa64d9115
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtc/adi_rtc.c
@@ -0,0 +1,2673 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_rtc.c
+ * @brief:   Real-Time Clock Device Implementations.
+ * @version: $Revision: 35155 $
+ * @date:    $Date: 2016-07-26 13:09:22 -0400 (Tue, 26 Jul 2016) $
+ *----------------------------------------------------------------------------
+ *
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+/*! \addtogroup RTC_Driver RTC Driver
+ *  @{
+ * @brief Real Time Clock (RTC) Driver
+ * @details The RTC driver manages all instances of the RTC peripheral.
+ * @note The application must include drivers/rtc/adi_rtc.h to use this driver
+ */
+
+
+/*! \cond PRIVATE */
+
+#if defined(__ADUCM302x__)
+#define BITP_CLKG_OSC_CTL_LFX_FAIL_STA BITP_CLKG_OSC_CTL_LFX_FAIL_STAT 
+#endif  /* __ADUCM302x__ */
+
+#if defined ( __ADSPGCC__ )
+#define UNUSED __attribute__ ((unused))
+#else
+#define UNUSED
+#endif
+
+#include <stdlib.h>  /* for 'NULL" definition */
+#include <assert.h>
+#include <string.h>
+#include <rtos_map/adi_rtos_map.h>
+
+
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm011 (rule 6.3): Types which specify sign and size should be used
+*   We use bool which is accepted by MISRA but the toolchain does not accept it
+*
+* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
+*   This isn't a header as such.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+*
+* Pm050 (rule 14.2): a null statement shall only occur on a line by itself
+*   Needed for null expansion of ADI_INSTALL_HANDLER and others.
+*
+* Pm109 (rule 20.12): the time handling functions of library <time.h> shall not be used
+* Pm150 (rule 20.2): the names of standard library macros, objects and function shall not be reused
+*   Needed to implement the <time.h> functions here.
+*
+* Pm129 (rule 12.7): bitwise operations shall not be performed on signed integer types 
+*   The rule makes an exception for valid expressions.
+*
+* Pm029: this bitwise operation is in a boolean context - logical operators should not be confused with bitwise operators 
+*   The rule is suppressed as the bitwise and logical operators are being used correctly and are not being confused
+*
+* Pm126: if the bitwise operators ~ and << are applied to an operand of underlying type 'unsigned char' or 'unsigned short', the result shall be immediately cast to the underlying type of the operand
+*   The behaviour as described is correct
+*
+* Pm031: bitwise operations shall not be performed on signed integer types 
+*   Device drivers often require bit banging on MMRs that are defined as signed
+
+*/
+#pragma diag_suppress=Pm011,Pm123,Pm073,Pm143,Pm050,Pm109,Pm150,Pm140,Pm129,Pm029,Pm126,Pm031
+#endif /* __ICCARM__ */
+/*! \endcond */
+   
+
+#include <drivers/rtc/adi_rtc.h>
+
+   
+/*! \cond PRIVATE */
+
+
+#include "adi_rtc_data.c"
+
+
+#if defined(__ADUCM302x__)
+#define BITP_RTC_SSMSK_SS1MSK   BITP_RTC_SSMSK_SSMSK
+#endif /* __ADUCM302x__ */
+
+#if defined(__ADUCM4x50__)
+
+/* Data structures used to manage the enabling of all RTC interrupts */
+static uint16_t cr0 = 0u, cr1 = 0u, cr3oc = 0u, cr4oc = 0u, cr2ic = 0u, cr5ocs = 0u;
+
+struct xxx
+{
+  uint16_t *cr;
+  uint16_t  bitPositionl; 
+}
+
+Interrupt_Details[ADI_RTC_NUM_INTERRUPTS] =
+{
+  { &cr0, BITP_RTC_CR0_ALMINTEN }, 
+  { &cr0, BITP_RTC_CR0_MOD60ALMINTEN }, 
+  { &cr0, BITP_RTC_CR0_ISOINTEN },
+  { &cr0, BITP_RTC_CR0_WPNDERRINTEN },
+  { &cr0, BITP_RTC_CR0_WSYNCINTEN },
+  { &cr0, BITP_RTC_CR0_WPNDINTEN },
+  { &cr1, BITP_RTC_CR1_CNTINTEN },
+  { &cr1, BITP_RTC_CR1_PSINTEN },
+  { &cr1, BITP_RTC_CR1_TRMINTEN },
+  { &cr1, BITP_RTC_CR1_CNTROLLINTEN },
+  { &cr1, BITP_RTC_CR1_CNTMOD60ROLLINTEN },
+  { &cr3oc, BITP_RTC_CR3SS_SS1IRQEN },
+  { &cr3oc, BITP_RTC_CR3SS_SS2IRQEN },
+  { &cr3oc, BITP_RTC_CR3SS_SS2IRQEN },
+  { &cr3oc, BITP_RTC_CR3SS_SS4IRQEN },
+  { &cr2ic, BITP_RTC_CR2IC_IC0IRQEN },
+  { &cr2ic, BITP_RTC_CR2IC_IC2IRQEN },
+  { &cr2ic, BITP_RTC_CR2IC_IC3IRQEN },
+  { &cr2ic, BITP_RTC_CR2IC_IC4IRQEN },
+  { &cr2ic, BITP_CLKG_OSC_CTL_LFX_FAIL_STA },
+  { &cr3oc, BITM_RTC_CR3SS_SS4FEIRQEN},
+  { &cr3oc, BITM_RTC_CR3SS_SS3FEIRQEN},  
+  { &cr3oc, BITM_RTC_CR3SS_SS2FEIRQEN},  
+  { &cr3oc, BITM_RTC_CR3SS_SS1FEIRQEN}, 
+  { &cr4oc, BITP_RTC_CR4SS_SS4MSKEN},  
+  { &cr4oc, BITP_RTC_CR4SS_SS3MSKEN},  
+  { &cr4oc, BITP_RTC_CR4SS_SS2MSKEN},  
+  { &cr4oc, BITP_RTC_CR4SS_SS1MSKEN},  
+  { &cr5ocs, BITP_RTC_CR5SSS_SS3SMPMTCHIRQEN},  
+  { &cr5ocs, BITP_RTC_CR5SSS_SS2SMPMTCHIRQEN},  
+  { &cr5ocs, BITP_RTC_CR5SSS_SS1SMPMTCHIRQEN}
+  
+};
+#elif defined(__ADUCM302x__)
+
+/* Data structures used to manage the enabling of all RTC interrupts */
+static uint16_t cr0 = 0u, cr1 = 0u, cr3oc = 0u, cr4oc = 0u, cr2ic = 0u;
+
+struct xxx
+{
+  uint16_t *cr;
+  uint16_t  bitPositionl; 
+}
+
+Interrupt_Details[ADI_RTC_NUM_INTERRUPTS] =
+{
+  { &cr0, BITP_RTC_CR0_ALMINTEN }, 
+  { &cr0, BITP_RTC_CR0_MOD60ALMINTEN }, 
+  { &cr0, BITP_RTC_CR0_ISOINTEN },
+  { &cr0, BITP_RTC_CR0_WPNDERRINTEN },
+  { &cr0, BITP_RTC_CR0_WSYNCINTEN },
+  { &cr0, BITP_RTC_CR0_WPNDINTEN },
+  { &cr1, BITP_RTC_CR1_CNTINTEN },
+  { &cr1, BITP_RTC_CR1_PSINTEN },
+  { &cr1, BITP_RTC_CR1_TRMINTEN },
+  { &cr1, BITP_RTC_CR1_CNTROLLINTEN },
+  { &cr1, BITP_RTC_CR1_CNTMOD60ROLLINTEN },
+  { &cr3oc, BITP_RTC_CR3SS_SS1IRQEN },
+  { &cr2ic, BITP_RTC_CR2IC_IC0IRQEN },
+  { &cr2ic, BITP_RTC_CR2IC_IC2IRQEN },
+  { &cr2ic, BITP_RTC_CR2IC_IC3IRQEN },
+  { &cr2ic, BITP_RTC_CR2IC_IC4IRQEN },  
+};
+#else
+#error RTC is not ported for this processor
+#endif
+
+
+/* Forward prototypes */
+void RTC0_Int_Handler(void);
+void RTC1_Int_Handler(void);
+
+
+
+#ifdef ADI_DEBUG
+static ADI_RTC_RESULT ValidateHandle( ADI_RTC_DEVICE *pInDevice)
+{
+    /* Return code */
+    ADI_RTC_RESULT    nResult = ADI_RTC_INVALID_HANDLE;
+    uint32_t i;
+    for(i = 0u; i < ADI_RTC_NUM_INSTANCE; i++)
+    {
+        if(aRTCDeviceInfo[i].hDevice == pInDevice)
+        {
+            return(ADI_RTC_SUCCESS);
+        }
+    }
+    return (nResult);
+}
+#endif
+/*! \endcond */
+
+/*!
+    @brief RTC Initialization
+
+ * @param[in]   DeviceNumber    The RTC device instance number to be opened.
+ * @param[in]   pDeviceMemory   The pointer to the device  memory passed by application.
+ * @param[in]   MemorySize      The memory size passed by application.
+ * @param[out]  phDevice        The pointer to a location where the handle to the opened RTC device is written.
+    @return    Status
+               - #ADI_RTC_SUCCESS                   RTC device driver initialized successfully.
+               - #ADI_RTC_INVALID_INSTANCE [D]         The RTC instance number is invalid.
+               - #ADI_RTC_FAILURE                      General RTC initialization failure.
+
+            The RTC controller interrupt enable state is unaltered during driver initialization.
+            Use the #adi_rtc_EnableInterrupts API to manage interrupting.
+
+    @note   The contents of phDevice will be set to NULL upon failure.\n\n
+
+    @note   On #ADI_RTC_SUCCESS the RTC device driver is initialized and made ready for use,
+            though pending interrupts may be latched.  During initialization, the content of the
+            various RTC control, count, alarm and status registers are untouched to preserve prior
+            RTC initializations and operation.  The core NVIC RTC interrupt is enabled.\n\n
+
+
+    @note   SAFE WRITES: The "safe write" mode is enabled by default and can be changed using the macro
+                         "ADI_RTC_CFG_ENABLE_SAFE_WRITE" defined in adi_rtc_config.h file.
+
+    @sa    adi_rtc_Enable().
+    @sa    adi_rtc_EnableInterrupts().
+    @sa    adi_rtc_SetCount().
+    @sa    adi_rtc_Close()
+*/
+ADI_RTC_RESULT adi_rtc_Open(
+               uint32_t         DeviceNumber,
+               void            *pDeviceMemory,
+               uint32_t         MemorySize,
+               ADI_RTC_HANDLE  *phDevice
+               )
+{
+    ADI_RTC_DEVICE *pDevice = pDeviceMemory;
+
+    /* store a bad handle in case of failure */
+    *phDevice = (ADI_RTC_HANDLE) NULL;
+
+#ifdef ADI_DEBUG
+    if ( DeviceNumber >= ADI_RTC_NUM_INSTANCE)
+    {
+        return ADI_RTC_INVALID_INSTANCE;
+    }
+    assert(ADI_RTC_MEMORY_SIZE == sizeof(ADI_RTC_DEVICE));
+    if (aRTCDeviceInfo[DeviceNumber].hDevice != NULL)
+    {
+        return ADI_RTC_IN_USE;
+    }
+    if(MemorySize < ADI_RTC_MEMORY_SIZE)
+    {
+      return(ADI_RTC_FAILURE);
+    }
+#endif
+
+    memset(pDeviceMemory,0,MemorySize);
+    /* initialize device data entries */
+    pDevice->pRTCRegs    = aRTCDeviceInfo[DeviceNumber].pRTCRegs;
+    
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
+
+    pDevice->pRTCRegs->CR0 = 0u;
+    pDevice->pRTCRegs->CR1 = 0u;
+    
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)    
+
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDSR0)
+
+    pDevice->pRTCRegs->SR0 = ADI_RTC_SR3_IRQ_STATUS_MASK;
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCSR0)    
+    
+    pDevice->pRTCRegs->CNT0 = 0u;
+    pDevice->pRTCRegs->CNT1 = 0u;
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCNT0)    
+    
+    /* local pointer to instance data */
+    aRTCDeviceInfo[DeviceNumber].hDevice = pDevice;
+    pDevice->pDeviceInfo = &aRTCDeviceInfo[DeviceNumber];
+
+    /* Use static configuration to initialize the RTC */
+    rtc_init(pDevice,&aRTCConfig[DeviceNumber]);
+   
+    /* store handle at application handle pointer */
+    *phDevice = pDevice;
+    pDevice->eIRQn =  aRTCDeviceInfo[DeviceNumber].eIRQn;
+    /* Enable RTC interrupts in NVIC */
+    NVIC_EnableIRQ((IRQn_Type)(pDevice->eIRQn));
+
+    return ADI_RTC_SUCCESS;            /* initialized */
+}
+
+
+/*!
+ * @brief  Uninitialize and deallocate an RTC device.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS              Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * Uninitialize and release an allocated RTC device for other use.  The core NVIC RTC interrupt is disabled.
+ *
+ * @sa        adi_rtc_Open().
+ */
+ADI_RTC_RESULT adi_rtc_Close(ADI_RTC_HANDLE const hDevice)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+
+    /* uninitialize */
+    NVIC_DisableIRQ( pDevice->eIRQn);
+
+    pDevice->pRTCRegs   = NULL;
+    pDevice->pfCallback = NULL;
+    pDevice->pCBParam   = NULL;
+    pDevice->cbWatch    = 0u;
+   
+    pDevice->pDeviceInfo->hDevice = NULL;
+    return ADI_RTC_SUCCESS;
+}
+
+
+/*************************************************************************************************
+**************************************************************************************************
+****************************************  ENABLE APIS  *******************************************
+**************************************************************************************************
+*************************************************************************************************/
+
+
+/*!
+ * @brief  Enable RTC alarm.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   bEnable    boolean Flag to enable/disable  alarm logic.
+ *              - true  :   Enable alarm logic.
+ *              - false :   Disable alarm logic.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]     Invalid device handle parameter.
+ *
+ * Enable/disable operation of RTC internal alarm logic.
+ *
+ * Alarm events and interrupt notifications are gated by enabling the alarm logic.
+ * RTC alarm interrupts require both RTC device and RTC alarm interrupt to be enabled
+ * to have been set.
+ *
+ * The alarm is relative to some future alarm value match against the RTC counter.
+ *
+ * @note The RTC device driver does not modify the alarm enable on the hardware except through use of this API.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ * @sa        adi_rtc_EnableInterrupts().
+ * @sa        adi_rtc_GetAlarm().
+ * @sa        adi_rtc_GetCount().
+ * @sa        adi_rtc_SetAlarm().
+ * @sa        adi_rtc_SetCount().
+ */
+ADI_RTC_RESULT adi_rtc_EnableAlarm(ADI_RTC_HANDLE const hDevice, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
+      
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* set/clear RTC alarm enable */
+    if (bEnable)
+    {
+        pDevice->pRTCRegs->CR0  |= BITM_RTC_CR0_ALMEN;
+    }
+    else
+    {
+        pDevice->pRTCRegs->CR0 &= (uint16_t)(~BITM_RTC_CR0_ALMEN);
+    }
+    ADI_EXIT_CRITICAL_REGION();
+    
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)    
+
+    return ADI_RTC_SUCCESS;
+}
+
+/*!
+ * @brief  Enable MOD60 RTC alarm.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   bEnable    boolean Flag for enable/disable mod60  alarm logic.
+ *               - true   :  Enable mod60 alarm logic.
+ *               - false  :  Disable mod60 alarm logic.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * Enable/disable operation of RTC internal MOD60 alarm logic.
+ *
+ * Alarm events and interrupt notifications are gated by enabling the alarm logic.
+ * RTC alarm interrupts require both RTC device and RTC alarm interrupt to be enabled
+ * to have been set.
+ *
+ * The alarm is relative to some future alarm value match against the RTC counter.
+ *
+ * @note The RTC device driver does not modify the alarm enable on the hardware except through use of this API.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ * @sa        adi_rtc_EnableInterrupts().
+ * @sa        adi_rtc_GetAlarm().
+ * @sa        adi_rtc_GetCount().
+ * @sa        adi_rtc_SetAlarm().
+ * @sa        adi_rtc_SetCount().
+ */
+ADI_RTC_RESULT adi_rtc_EnableMod60Alarm(ADI_RTC_HANDLE const hDevice, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+    /* Mod-60 Alarm is present only in RTC-1 */
+    if(pDevice->pRTCRegs == pADI_RTC0)
+    {
+        return(ADI_RTC_OPERATION_NOT_ALLOWED);
+    }
+
+#endif
+
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
+
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* set/clear RTC alarm enable */
+    if (bEnable)
+    {
+        pDevice->pRTCRegs->CR0  |= BITM_RTC_CR0_MOD60ALMEN;
+    }
+    else
+    {
+        pDevice->pRTCRegs->CR0 &= (uint16_t)(~BITM_RTC_CR0_MOD60ALMEN);
+    }
+    ADI_EXIT_CRITICAL_REGION();
+    
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)    
+
+    return ADI_RTC_SUCCESS;
+}
+
+/*!
+ * @brief  Enable RTC device.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   bEnable    boolean Flag for enabling/disabling  the RTC device.
+ *                - true   :     Enable RTC device.
+ *                - false  :     Disable RTC device.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * Global enable/disable of the RTC controller.  Enables counting of elapsed real time and acts
+ * as a master enable for the RTC.
+ *
+ * @note When enabled, the RTC input clock pre-scaler and trim interval  are realigned.
+ *
+ * @note The RTC device driver does not modify the device enable on the hardware except through use of this API.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_EnableAlarm().
+ */
+
+ADI_RTC_RESULT adi_rtc_Enable(ADI_RTC_HANDLE const hDevice, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
+    
+
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* set/clear RTC device enable */
+    if (bEnable)
+    {
+         pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_CNTEN;
+    }
+    else
+    {
+        pDevice->pRTCRegs->CR0 &=(uint16_t)(~BITM_RTC_CR0_CNTEN);
+    }
+    ADI_EXIT_CRITICAL_REGION();
+    
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)    
+      
+    return ADI_RTC_SUCCESS;
+}
+
+
+/*!
+ * @brief  Manage interrupt enable/disable in the RTC and NVIC controller.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   Interrupts Conveys which interrupts are affected.
+ * @param[in]   bEnable     Flag which controls whether to enable or disable RTC interrupt.
+ *               - true  :  Enable RTC interrupts.
+ *               - false :  Disable RTC interrupts.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * Enable/disable RTC interrupt as well as manage global NVIC enable/disable for the RTC.
+ * Input parameter \a Interrupts is a interrupt ID of type #ADI_RTC_INT_TYPE designating the 
+ * interrupt to be enabled or disabled.  The interrupt parameter may be zero, which will then simply
+ * manage the NVIC RTC enable and leave the individual RTC interrupt enables unchanged.
+ * Input parameter \a bEnable controls whether to enable or disable the designated set of interrupts.
+ *
+ * @note The RTC device driver does not modify the interrupt enables on the hardware except through use of this API.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ */
+ADI_RTC_RESULT adi_rtc_EnableInterrupts (ADI_RTC_HANDLE const hDevice, ADI_RTC_INT_TYPE Interrupts, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+    if( (pDevice->pRTCRegs == pADI_RTC0) &&(((uint16_t)((ADI_RTC_MOD60ALM_INT | ADI_RTC_ISO_DONE_INT|
+                                             ADI_RTC_COUNT_INT    | 
+                                             ADI_RTC_TRIM_INT    | ADI_RTC_COUNT_ROLLOVER_INT |
+                                             ADI_RTC_MOD60_ROLLOVER_INT
+                                             )) & (uint16_t)Interrupts) != 0u))
+    {
+        return(ADI_RTC_INVALID_PARAM);
+    }
+    
+    assert(sizeof(Interrupt_Details)/sizeof(Interrupt_Details[0]) == ADI_RTC_NUM_INTERRUPTS);
+#endif
+    
+    /* TODO - more sync for new registers */
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
+    PEND_BEFORE_WRITE(SR2,BITM_RTC_SR2_WPNDCR1MIR)
+    
+    uint8_t ndx = 0u;
+    cr0 = 0u; cr1 = 0u; cr3oc = 0u; cr4oc = 0u; cr2ic = 0u; 
+    
+#if defined(__ADUCM4x50__)    
+    cr5ocs = 0u;
+#endif /* __ADUCM4x50__ */
+    
+    while( Interrupts )
+    {
+      if( 0u != (Interrupts & 1u) )
+      {
+        uint16_t *cr = Interrupt_Details[ndx].cr;
+        uint16_t  enableBitPosition = Interrupt_Details[ndx].bitPositionl;
+        *cr = *cr | (1u << enableBitPosition);
+      }
+      Interrupts >>= 1;
+      ndx++;
+    }
+    /* set/clear interrupt enable bit(s) in control register */
+    if (bEnable)
+    {
+        pDevice->pRTCRegs->CR0 |= cr0;
+        pDevice->pRTCRegs->CR1 |= cr1;
+        pDevice->pRTCRegs->CR3SS |= cr3oc;
+        pDevice->pRTCRegs->CR4SS |= cr4oc;
+        pDevice->pRTCRegs->CR2IC |= cr2ic;
+        
+#if defined(__ADUCM4x50__)        
+        pDevice->pRTCRegs->CR5SSS |= cr5ocs;
+#endif /* __ADUCM4x50__ */       
+    } 
+    else
+    {
+        pDevice->pRTCRegs->CR0 &= ~cr0;
+        pDevice->pRTCRegs->CR1 &= ~cr1;
+        pDevice->pRTCRegs->CR3SS &= ~cr3oc;
+        pDevice->pRTCRegs->CR4SS &= ~cr4oc;
+        pDevice->pRTCRegs->CR2IC &= ~cr2ic;
+#if defined(__ADUCM4x50__)        
+        pDevice->pRTCRegs->CR5SSS &= ~cr5ocs;
+#endif /*  __ADUCM4x50__ */       
+    }
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)    
+    SYNC_AFTER_WRITE(SR2,BITM_RTC_SR2_WSYNCCR1MIR)        
+    return ADI_RTC_SUCCESS;
+}
+
+
+/*!
+ * @brief  Enable RTC automatic clock trimming.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   bEnable      Flag controlling RTC enabling trim.
+ *                - true     Enable RTC trimming.
+ *                - false    Disable RTC trimming.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * Enable/disable automatic application of trim values to the main RTC clock.  Allows application
+ * of periodic real-time RTC clock adjustments to correct for drift.  Trim values are pre-calibrated
+ * and stored at manufacture.  Trim values may be recalibrated by monitoring the RTC clock externally
+ * and computing/storing new trim values (see #adi_rtc_SetTrim).
+ *
+ * @note The trim interval is reset with device enable, #adi_rtc_Enable().
+ *
+ * @note The RTC device driver does not modify the trim enable on the hardware except through use of this API.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ * @sa        adi_rtc_GetTrim().
+ * @sa        adi_rtc_SetTrim().
+ */
+ADI_RTC_RESULT adi_rtc_EnableTrim (ADI_RTC_HANDLE const hDevice, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
+    
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* set/clear trim enable bit(s) in control register */
+    if (bEnable)
+    {
+        pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_TRMEN;
+    }
+    else
+    {
+        pDevice->pRTCRegs->CR0 &=(uint16_t)(~BITM_RTC_CR0_TRMEN);
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)    
+    
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Enable input capture for the specified channel.
+ *
+ * @param[in]   hDevice       Device handle obtained from adi_rtc_Open().
+ * @param[in]   eInpChannel   Specify input compare channel. 
+ * @param[in]   bEnable      Flag for enabling  RTC input capture for specified channel.
+ *                - true     Enable input capture.
+ *                - false    Disable input capture.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ */
+ADI_RTC_RESULT adi_rtc_EnableInputCapture (ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eInpChannel, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC)
+    
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* set/clear trim input capture enable for specified channel*/
+    if (bEnable)
+    {
+        pDevice->pRTCRegs->CR2IC |=(uint16_t)eInpChannel;
+    }
+    else
+    {
+        pDevice->pRTCRegs->CR2IC &= (uint16_t)(~(uint16_t)eInpChannel);
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC)    
+    
+    return ADI_RTC_SUCCESS;
+}
+
+/*!
+ * @brief  Enable Overwrite of Unread Snapshots for all RTC Input Capture Channels.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   bEnable      Flag for enabling  overwriting the unread snapshot.
+ *                - true     Enable overwrite snapshot.
+ *                - false    Disable overwrite of snapshot.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ */
+ADI_RTC_RESULT adi_rtc_EnableOverwriteSnapshot (ADI_RTC_HANDLE const hDevice, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC)
+    
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* set/clear trim input capture enable for specified channel*/
+    if (bEnable)
+    {
+        pDevice->pRTCRegs->CR2IC |= BITM_RTC_CR2IC_ICOWUSEN;
+    }
+    else
+    {
+        pDevice->pRTCRegs->CR2IC &= (uint16_t)~BITM_RTC_CR2IC_ICOWUSEN;
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC)    
+    
+    return ADI_RTC_SUCCESS;
+}
+
+/*!
+ * @brief  Set  input capture polarity  for the specified channel.
+ *
+ * @param[in]   hDevice        Device handle obtained from adi_rtc_Open().
+ * @param[in]   eInpChannel    Specify which input capture  channel.  
+ * @param[in]   bEnable        Flag for selecting   RTC input capture polarity.
+ *                - false     channel uses a *high-to-low* transition on its GPIO pin to signal an input capture event
+ *                - true      channel uses a *low-to-high* transition on its GPIO pin to signal an input capture event.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ */
+ADI_RTC_RESULT adi_rtc_SetInputCapturePolarity (ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eInpChannel, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+    uint32_t nInpChannel = (uint16_t)eInpChannel;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC)
+    
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* set/clear trim input capture enable for specified channel*/
+    if (bEnable)
+    {
+        pDevice->pRTCRegs->CR2IC |= (uint16_t)(nInpChannel << BITP_RTC_CR2IC_IC0LH);
+    }
+    else
+    {
+        pDevice->pRTCRegs->CR2IC &= (uint16_t)~(nInpChannel << BITP_RTC_CR2IC_IC0LH);
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC)    
+    
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Enable output for the specified Sensor Strobe Channel.
+ *
+ * @param[in]   hDevice      Device handle obtained from adi_rtc_Open().
+ * @param[in]   eSSChannel   Specify which Sensor Strobe channel.
+ * @param[in]   bEnable      Flag for enabling  output for specified Sensor Strobe channel.
+ *                - true     Enable output.
+ *                - false    Disable output.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ */
+ADI_RTC_RESULT adi_rtc_EnableSensorStrobeOutput (ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR3SS)
+    
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* set/clear Sensor Strobe enable for specified channel*/
+    if (bEnable)
+    {
+        pDevice->pRTCRegs->CR3SS |=(uint16_t)eSSChannel;
+    }
+    else
+    {
+        pDevice->pRTCRegs->CR3SS &= (uint16_t)(~(uint16_t)eSSChannel);
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR3SS)    
+    
+    return ADI_RTC_SUCCESS;
+}
+
+/*!
+ * @brief  Enable auto reload for given Sensor Strobe Channel.
+ *
+ * @param[in]   hDevice        Device handle obtained from adi_rtc_Open().
+ * @param[in]   eSSChannel     Sensor Strobe Channel number.
+ * @param[in]   bEnable        Flag to enable auto reload for given Sensor Strobe Channel.
+ *                - true       Enable auto reload.
+ *                - false      Disable auto reload.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ */
+ADI_RTC_RESULT adi_rtc_EnableAutoReload(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR4SS)
+    
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* set/clear auto reload enable options */
+    /* Note that channel 4 does not have this feature */
+    if (bEnable)
+    {
+      switch( eSSChannel)
+      {
+      case ADI_RTC_SS_CHANNEL_1:
+        pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS1ARLEN;
+        break;
+#if defined(__ADUCM4x50__)        
+      case ADI_RTC_SS_CHANNEL_2:
+        pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS2ARLEN;
+        break;
+      case ADI_RTC_SS_CHANNEL_3:
+        pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS3ARLEN;
+        break;
+#endif /* __ADUCM4x50__ */        
+      default:
+        return ADI_RTC_FAILURE;
+      }
+        
+    }
+    else
+    {
+      switch( eSSChannel)
+      {
+      case ADI_RTC_SS_CHANNEL_1:
+        pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS1ARLEN;
+        break;
+#if defined(__ADUCM4x50__)        
+      case ADI_RTC_SS_CHANNEL_2:
+        pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS2ARLEN;
+        break;
+      case ADI_RTC_SS_CHANNEL_3:
+        pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS3ARLEN;
+        break;
+#endif /* __ADUCM4x50__ */        
+      default:
+        return ADI_RTC_FAILURE;
+      }
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR4SS)    
+    
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Set auto reload value for the given Sensor Strobe channel.
+ *
+ * @param[in]   hDevice     Device handle obtained from adi_rtc_Open().
+ * @param[in]   eSSChannel  Sensor Strobe channel for which auto reload to be set. 
+ * @param[in]   nValue      Auto reload value to be set.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ * 
+ *
+ */
+ADI_RTC_RESULT adi_rtc_SetAutoReloadValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t nValue)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    
+    switch( eSSChannel )
+    {
+        case ADI_RTC_SS_CHANNEL_1:
+            /* Wait till previously posted write to Control Register to complete */ 
+            PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1)
+            pDevice->pRTCRegs->SS1 = nValue;
+            /* Wait till  write to Control Register to take effect */    
+            SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS1)    
+            break;
+#if defined(__ADUCM4x50__)     
+        case ADI_RTC_SS_CHANNEL_2:
+            /* Wait till previously posted write to Control Register to complete */ 
+            PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2)
+            pDevice->pRTCRegs->SS2 = nValue;
+            /* Wait till  write to Control Register to take effect */    
+            SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS2)    
+            break;
+          
+        case ADI_RTC_SS_CHANNEL_3:
+            /* Wait till previously posted write to Control Register to complete */ 
+            PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3)
+            pDevice->pRTCRegs->SS3 = nValue;
+            /* Wait till  write to Control Register to take effect */    
+            SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS3)    
+            break;
+
+        case ADI_RTC_SS_CHANNEL_4:
+            PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS4)
+            pDevice->pRTCRegs->SS4 = nValue;
+            /* Wait till  write to Control Register to take effect */    
+            SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS4)    
+            break;
+#endif /* __ADUCM4x50__ */
+            
+        default:
+            return ADI_RTC_FAILURE;
+
+    }
+    
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Enable or disable thermometer-code masking for the given Sensor Strobe Channel.
+ *
+ * @param[in]   hDevice         Device handle obtained from adi_rtc_Open().
+ * @param[in]   eSSChannel      Sensor Strobe channel for which thermometer-code masking to be enabled or disabled. 
+ * @param[in]   bEnable         Flag to enable or disable masking for the given Sensor Strobe channel.
+ *                - true        Enable masking .
+ *                - false       Disable masking.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ */
+ADI_RTC_RESULT adi_rtc_EnableSensorStrobeChannelMask(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR5, BITM_RTC_SR5_WPENDCR4SS)
+    
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();    
+    /* set/clear auto reload enable options */
+    if (bEnable)
+    {
+        pDevice->pRTCRegs->CR4SS |= (uint16_t)eSSChannel;
+    }
+    else
+    {
+        pDevice->pRTCRegs->CR4SS &= (uint16_t)~(uint16_t)eSSChannel;
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR4SS)    
+    
+    return ADI_RTC_SUCCESS;
+}
+
+/*!
+ * @brief  To set channel mask for the given Sensor Strobe channel.
+ *
+ * @param[in]   hDevice      Device handle obtained from adi_rtc_Open().
+ * @param[in]   eSSChannel   Sensor Strobe Channel for which the mask to be set. 
+ * @param[in]   nMask        Channel Mask to be set for Sensor Strobe channel.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_CHANNEL         The given channel is invalid.
+ */
+ADI_RTC_RESULT adi_rtc_SetSensorStrobeChannelMask(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint8_t nMask)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+    uint16_t        MaskPos = 0u;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    
+    switch( eSSChannel )
+    {
+        case ADI_RTC_SS_CHANNEL_1:
+            MaskPos  = (uint16_t)BITP_RTC_SSMSK_SS1MSK;
+            break;
+#if defined(__ADUCM4x50__)     
+        case ADI_RTC_SS_CHANNEL_2:
+            MaskPos  = (uint16_t)BITP_RTC_SSMSK_SS2MSK;
+            break;
+          
+        case ADI_RTC_SS_CHANNEL_3:
+            MaskPos  = (uint16_t)BITP_RTC_SSMSK_SS3MSK;
+            break;
+
+        case ADI_RTC_SS_CHANNEL_4:
+            MaskPos  = (uint16_t)BITP_RTC_SSMSK_SS4MSK; 
+            break;
+#endif /* __ADUCM4x50__ */            
+        default:
+            return ADI_RTC_INVALID_CHANNEL;
+    }
+
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR5, BITM_RTC_SR5_WPENDSSMSK)
+    
+    pDevice->pRTCRegs->SSMSK = ((uint16_t)nMask & 0xFu) << MaskPos;
+
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR4, BITM_RTC_SR4_WSYNCSSMSK)    
+    
+    return ADI_RTC_SUCCESS;
+}
+
+/*************************************************************************************************
+**************************************************************************************************
+******************************************   GET APIS   ******************************************
+**************************************************************************************************
+*************************************************************************************************/
+
+
+/*!
+ * @brief  Get current RTC alarm value.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[out]  pAlarm     Pointer to application memory where the alarm value is written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ * Read the currently programmed 32-bit RTC alarm value and write it to the address provided by parameter \a pAlarm.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_SetAlarm().
+ */
+ADI_RTC_RESULT adi_rtc_GetAlarm (ADI_RTC_HANDLE hDevice, uint32_t *pAlarm)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+    uint32_t nAlarm;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
+
+    /* disable interrupts during paired read */
+    NVIC_DisableIRQ(pDevice->eIRQn);
+        nAlarm  =(uint32_t) pDevice->pRTCRegs->ALM1 << 16u;
+        nAlarm |= (uint32_t)pDevice->pRTCRegs->ALM0;
+    NVIC_EnableIRQ((IRQn_Type)(pDevice->eIRQn));
+
+    *pAlarm = nAlarm;
+
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Get current RTC alarm value  with fractional part also.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[out]  pAlarm     Pointer to application memory where the alarm value is written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ * Read the currently programmed 32-bit RTC alarm value and write it to the address provided by parameter \a pAlarm.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_SetAlarm().
+ */
+ADI_RTC_RESULT adi_rtc_GetAlarmEx (ADI_RTC_HANDLE hDevice, float *pAlarm)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+    uint32_t nAlarm,nTemp;
+    uint16_t nPreScale;
+    float fFraction;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
+    nPreScale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP;
+    /* disable interrupts during paired read */
+    NVIC_DisableIRQ(pDevice->eIRQn);
+    nAlarm  = (uint32_t)pDevice->pRTCRegs->ALM1 << 16u;
+    nAlarm |= (uint32_t)pDevice->pRTCRegs->ALM0;
+    NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn);
+    nTemp = 1lu<<nPreScale;
+    fFraction = (float)pDevice->pRTCRegs->ALM2 /(float)(nTemp);
+
+    *pAlarm = (float)nAlarm+fFraction;
+
+    return ADI_RTC_SUCCESS;
+}
+
+
+/*!
+ * @brief  Get current RTC control register value.
+ *
+ * @param[in]   hDevice      Device handle obtained from adi_rtc_Open().
+ * @param[in]   eRegister    Specify which register content need to be returned.
+ *
+ * @param[out]  pControl   Pointer to application memory where the control register value is written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ * Read the currently programmed 16-bit RTC control register value and write it to the address provided by parameter \a pControl.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtcSetControl().
+ */
+ADI_RTC_RESULT adi_rtc_GetControl (ADI_RTC_HANDLE hDevice, ADI_RTC_CONTROL_REGISTER eRegister ,uint32_t *pControl)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
+
+     switch(eRegister)
+     {
+     case ADI_RTC_CONTROL_REGISTER_0:
+         *pControl = pDevice->pRTCRegs->CR0;
+         break;
+     case ADI_RTC_CONTROL_REGISTER_1:
+         *pControl = pDevice->pRTCRegs->CR1;
+         break;
+     default:
+         return(ADI_RTC_FAILURE);
+     }
+    return ADI_RTC_SUCCESS;
+}
+
+
+/*!
+ * @brief  Get current RTC count value.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[out]  pCount     Pointer to application memory where the count value is written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ * Read the current 32-bit RTC count value and write it to the address provided by parameter \a pCount.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ * @sa        adi_rtc_SetCount().
+ */
+ADI_RTC_RESULT adi_rtc_GetCount(ADI_RTC_HANDLE const hDevice, uint32_t *pCount)
+{
+    uint32_t nCount;
+    ADI_RTC_DEVICE *pDevice = hDevice;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+
+    /* Wait till previously posted write to couunt Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1))
+
+    /* disable interrupts during paired read */
+    NVIC_DisableIRQ(pDevice->eIRQn);
+    nCount  = (uint32_t)pDevice->pRTCRegs->CNT1 << 16u;
+    nCount |= pDevice->pRTCRegs->CNT0;
+    *pCount = nCount;
+    NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn);
+
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Get current RTC count value with fraction.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[out]  pfCount    Pointer to application memory where the count(with fraction) value is written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ * Read the current 32-bit RTC count value and write it to the address provided by parameter \a pCount.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ * @sa        adi_rtc_SetCount().
+ */
+ADI_RTC_RESULT adi_rtc_GetCountEx(ADI_RTC_HANDLE const hDevice, float *pfCount)
+{
+    uint32_t nCount,nTemp;
+    uint16_t nPrescale;
+    ADI_RTC_DEVICE *pDevice = hDevice;
+    float fFraction;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to couunt Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1))
+    nPrescale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP;
+    /* disable interrupts during paired read */
+    NVIC_DisableIRQ(pDevice->eIRQn);
+    nCount  = (uint32_t)pDevice->pRTCRegs->CNT1 << 16u;
+    nCount |= pDevice->pRTCRegs->CNT0;
+    nTemp = (1lu<<nPrescale);
+    fFraction = (float)pDevice->pRTCRegs->CNT2/(float)(nTemp); 
+    NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn);
+    *pfCount = (float)nCount+ fFraction;
+
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Get current RTC count value of all registers.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[out]  pnCount    Pointer to application memory where the count's 32 MSB are written.
+ * @param[out]  pfCount    Pointer to application memory where the count's 16 LSB are written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]  NULL pointer for input parameter.
+ *
+ * Read the current 32-bit RTC count integer value and fractional value in the integer format.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ * @sa        adi_rtc_SetCount().
+ */
+ADI_RTC_RESULT adi_rtc_GetCountRegs(ADI_RTC_HANDLE const hDevice, uint32_t *pnCount, uint32_t *pfCount)
+{
+    uint32_t nCount;
+    ADI_RTC_DEVICE *pDevice = hDevice;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to couunt Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1))
+    /* disable interrupts during paired read */
+    NVIC_DisableIRQ(pDevice->eIRQn);
+    nCount  = (uint32_t)pDevice->pRTCRegs->CNT1 << 16u;
+    nCount |= pDevice->pRTCRegs->CNT0;
+    *pnCount= nCount;
+    *pfCount = (uint32_t)pDevice->pRTCRegs->CNT2; 
+    NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn);
+    return ADI_RTC_SUCCESS;
+}
+
+
+
+/*!
+ * @brief  Get current RTC clock trim value.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[out]  peTrim     Pointer to #ADI_RTC_TRIM_VALUE where the  trim value is to be  written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS              Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ * Read the current 16-bit RTC trim value and write it to the address provided by parameter \a pTrim.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_EnableInterrupts().
+ * @sa        adi_rtc_EnableTrim().
+ * @sa        adi_rtc_GetWritePendStatus().
+ * @sa        adi_rtc_GetWriteSyncStatus().
+ * @sa        adi_rtc_SetTrim().
+ */
+ADI_RTC_RESULT adi_rtc_GetTrim (ADI_RTC_HANDLE hDevice, ADI_RTC_TRIM_VALUE *peTrim)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+    if(peTrim == NULL)
+    {
+        return( ADI_RTC_INVALID_PARAM);
+    }
+#endif
+
+    /* Wait till previously posted write to couunt Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDTRM);
+
+    *peTrim =(ADI_RTC_TRIM_VALUE)(pDevice->pRTCRegs->TRM & BITM_RTC_TRM_VALUE);
+
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Get Sensor Strobe value for the given Sensor Strobe channel.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   eSSChannel Sensor Strobe Channel whose value to be read.
+ * @param[out]  pValue     Pointer to application memory where the Sensor Strobe value to be written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ * @sa        adi_rtc_SetCount().
+ */
+ADI_RTC_RESULT adi_rtc_GetSensorStrobeValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t *pValue)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+    
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    switch( eSSChannel )
+    {
+    case ADI_RTC_SS_CHANNEL_1:
+      PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1)
+      *pValue = pDevice->pRTCRegs->SS1;
+      break;
+#if defined(__ADUCM4x50__)      
+    case ADI_RTC_SS_CHANNEL_2:
+      /* Wait till previously posted write to Control Register to complete */ 
+      PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2)
+      *pValue = pDevice->pRTCRegs->SS2;
+      break;
+      
+    case ADI_RTC_SS_CHANNEL_3:
+      /* Wait till previously posted write to Control Register to complete */ 
+      PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3)
+      *pValue = pDevice->pRTCRegs->SS3;
+      break;
+      
+    case ADI_RTC_SS_CHANNEL_4:
+      PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS4)
+      *pValue = pDevice->pRTCRegs->SS4;
+      break;
+#endif /* __ADUCM4x50__ */      
+    default:
+      return ADI_RTC_FAILURE;
+    }
+    
+    
+    
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Set Sensor Strobe value for the given Sensor Strobe channel.
+ *
+ * @param[in]   hDevice         Device handle obtained from adi_rtc_Open().
+ * @param[in]   eSSChannel      Sensor Strobe Channel. 
+ * @param[out]  nValue          Sensor Strobe value to be set for the given Sensor Strobe channel .
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ * @sa        adi_rtc_SetCount().
+ */
+ADI_RTC_RESULT adi_rtc_SetSensorStrobeValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t nValue)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    
+    switch( eSSChannel )
+    {
+    case ADI_RTC_SS_CHANNEL_1:
+      /* Wait till previously posted write to Control Register to complete */ 
+      PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1)
+      pDevice->pRTCRegs->SS1 = nValue;
+      /* Wait till  write to Control Register to take effect */    
+      SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS1)    
+      break;
+      
+#if defined(__ADUCM4x50__)     
+    case ADI_RTC_SS_CHANNEL_2:
+      /* Wait till previously posted write to Control Register to complete */ 
+      PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2)
+      pDevice->pRTCRegs->SS2 = nValue;
+      /* Wait till  write to Control Register to take effect */    
+      SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS2)    
+      break;
+      
+    case ADI_RTC_SS_CHANNEL_3:
+      /* Wait till previously posted write to Control Register to complete */ 
+      PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3)
+      pDevice->pRTCRegs->SS3 = nValue;
+      /* Wait till  write to Control Register to take effect */    
+      SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS3)    
+      break;
+      
+    case ADI_RTC_SS_CHANNEL_4:
+      /* Wait till previously posted write to Control Register to complete */ 
+      PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS4)
+      pDevice->pRTCRegs->SS4 = nValue;
+      /* Wait till  write to Control Register to take effect */    
+      SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS4)    
+      break;
+#endif /* __ADUCM4x50__ */      
+    default:
+      return ADI_RTC_FAILURE;
+    }
+      
+    return ADI_RTC_SUCCESS;
+}
+
+/*!
+ * @brief  Get input capture value for specified input channel.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   eChannel   Specify which input capture  channel. 
+ * @param[out]  pValue     Pointer to application memory where the input capture value to be written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS              Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *                - #ADI_RTC_INVALID_CHANNEL [D]     Input channel-0 is not valid for this operation since 
+ *                                                   channel-0 can provide precise (47bit) capture value.
+ *
+ *
+ *
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ * @sa        adi_rtc_SetCount().
+ */
+ADI_RTC_RESULT adi_rtc_GetInputCaptureValue(ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eChannel, uint16_t *pValue)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+    ADI_RTC_RESULT eResult= ADI_RTC_SUCCESS;
+    
+#ifdef ADI_DEBUG
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    switch(eChannel)
+    {
+        case ADI_RTC_INPUT_CHANNEL_2:
+           *pValue = pDevice->pRTCRegs->IC2;
+            break;
+        case ADI_RTC_INPUT_CHANNEL_3:
+           *pValue = pDevice->pRTCRegs->IC3;
+            break;
+          
+        case ADI_RTC_INPUT_CHANNEL_4:
+           *pValue = pDevice->pRTCRegs->IC4;
+            break;
+        default:  
+           eResult = ADI_RTC_INVALID_CHANNEL;
+           break;
+    }
+    return(eResult);
+}
+/*!
+ * @brief  Get snapshot of the value of RTC .
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   eChannel   Specify input channel from which captured value to be obtained.
+ * @param[in]   pFraction  Pointer to application memory where the  fractional part of snap shot value to be written.
+ * @param[out]  pValue     Pointer to application memory where the snap shot value  of RTC  to be written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS              Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ *
+ *
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ * @sa        adi_rtc_SetCount().
+ */
+ADI_RTC_RESULT adi_rtc_GetSnapShot(ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eChannel, uint32_t *pValue, uint16_t *pFraction)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+    ADI_RTC_RESULT eResult= ADI_RTC_SUCCESS;
+    uint32_t nCount = 0u;
+#ifdef ADI_DEBUG
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* disable interrupts during paired read */
+    NVIC_DisableIRQ(pDevice->eIRQn);
+    nCount  = (uint32_t)pDevice->pRTCRegs->SNAP1 << 16u;
+    nCount |= pDevice->pRTCRegs->SNAP0;
+    *pFraction = pDevice->pRTCRegs->SNAP2;
+    *pValue = nCount;
+    NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn);
+    return(eResult);
+}
+
+
+/*!
+ * @brief  Get current RTC posted write pending status.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[out]  pPendBits  Pointer to application memory where the posted write status is written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS              Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ *
+ * \b Pending \b Writes: Register writes to internal RTC registers take time to complete because the RTC controller
+ * clock is running at a much slower (32kHz) rate than the core processor clock.  So each RTC write register has a
+ * one-deep FIFO to hold write values until the RTC can effect them.  This gives rise to the notion of a \a pending
+ * \a write state: if a write is already pending and another write from the core comes along before the first (pending)
+ * write has cleared to its destination register, the second write may be lost because the FIFO is full already.
+ *
+ * To avoid data loss, the user may tell the RTC device driver to enforce safe writes with the configuration switch
+ *  ADI_RTC_CFG_ENABLE_SAFE_WRITE.  Enabeling safe writes (on be default) insures write data is never lost by
+ * detecting and pausing on pending writes prior writing new data.  The penalty in using safe writes is the stall
+ * overhead in execution (which is not incurred if there is nothing pending).  Additionally, \a all pending writes
+ * may also be synchronized manually with the #adi_rtc_SynchronizeAllWrites() API, which will pause until all
+ * pending RTC writes have completed.
+ *
+ * The distinction between "pend" status (#adi_rtc_GetWritePendStatus()) and "sync" (#adi_rtc_GetWriteSyncStatus())
+ * status is that the \a pend state is normally clear and is set only while no room remains in a register's write FIFO,
+ * whereas \a sync state is normally set and is clear only while the effects of the write are not yet apparent.
+ *
+ * Each write error
+ * source may be configured to interrupt the core by enabling the appropriate
+ * write error interrupt mask bit in the RTC control register (see the
+ * #adi_rtc_EnableInterrupts() API), at which time, the RTC interrupt handler
+ * will be dispatched.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        #adi_rtc_EnableInterrupts().
+ * @sa        adi_rtc_GetWriteSyncStatus().
+ * @sa        adi_rtc_SynchronizeAllWrites().
+ */
+ADI_RTC_RESULT adi_rtc_GetWritePendStatus (ADI_RTC_HANDLE const hDevice, ADI_RTC_WRITE_STATUS *pPendBits)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+    uint16_t nPendBits;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* get the value */
+    nPendBits = pDevice->pRTCRegs->SR1 & ADI_RTC_WRITE_STATUS_MASK;
+    *pPendBits = (ADI_RTC_WRITE_STATUS)nPendBits;
+
+    return ADI_RTC_SUCCESS;
+}
+
+
+/*!
+ * @brief  Get current RTC posted write synchronization status.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[out]  pSyncBits  Pointer to application memory where the posted write status is written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS              Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ *
+ * \b Pending \b Writes: Register writes to internal RTC registers take time to complete because the RTC controller
+ * clock is running at a much slower (32kHz) rate than the core processor clock.  So each RTC write register has a
+ * one-deep FIFO to hold write values until the RTC can effect them.  This gives rise to the notion of a \a pending
+ * \a write state: if a write is already pending and another write from the core comes along before the first (pending)
+ * write has cleared to its destination register, the second write may be lost because the FIFO is full already.
+ *
+ * To avoid data loss, the user may tell the RTC device driver to enforce safe writes with the
+ * #ADI_RTC_CFG_ENABLE_SAFE_WRITE switch.  Enabling safe writes (on be default) insures write data is never lost by
+ * detecting and pausing on pending writes prior writing new data.  The penalty in using safe writes is the stall
+ * overhead in execution (which is not incurred if there is nothing pending).  Additionally, \a all pending writes
+ * may also be synchronized manually with the #adi_rtc_SynchronizeAllWrites() API, which will pause until all
+ * pending RTC writes have completed.
+ *
+ * The distinction between "pend" status (#adi_rtc_GetWritePendStatus()) and "sync" (#adi_rtc_GetWriteSyncStatus())
+ * status is that the \a pend state is normally clear is set only while no room remains in a register's write FIFO,
+ * whereas \a sync state is normally set and is clear only while the effects of the write are not yet apparent.
+ *
+ * Each write error source may be configured to interrupt the core by enabling
+ * the appropriate write error interrupt mask bit in the RTC control register
+ * (see the #adi_rtc_EnableInterrupts() API), at which time, the RTC interrupt
+ * handler will be dispatched.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        #adi_rtc_EnableInterrupts().
+ * @sa        adi_rtc_GetWritePendStatus().
+ * @sa        adi_rtcStallOnPendingWrites().
+ * @sa        adi_rtc_SynchronizeAllWrites().
+ */
+ADI_RTC_RESULT  adi_rtc_GetWriteSyncStatus (ADI_RTC_HANDLE const hDevice, ADI_RTC_WRITE_STATUS *pSyncBits)
+{
+   ADI_RTC_DEVICE *pDevice = hDevice;
+   uint16_t nSyncBits;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to couunt Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDSR0);
+
+    /* get the value */
+    nSyncBits = pDevice->pRTCRegs->SR0 & ADI_RTC_WRITE_STATUS_MASK;
+    *pSyncBits = (ADI_RTC_WRITE_STATUS)nSyncBits;
+
+    return ADI_RTC_SUCCESS;
+}
+
+
+/*************************************************************************************************
+**************************************************************************************************
+******************************************   SET APIS   ******************************************
+**************************************************************************************************
+*************************************************************************************************/
+
+
+/*!
+ * @brief  Set a new RTC alarm value.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   nAlarm     New alarm value to set.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * Writes the 32-bit RTC alarm comparator with the value provided by \a Alarm.
+ *
+ * Honours the safe write mode if set.  Otherwise, it is the application's responsibility to
+ * synchronize any multiple writes to the same register.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_GetAlarm().
+ * @sa        adi_rtc_EnableAlarm().
+ * @sa        adi_rtc_GetWritePendStatus().
+ * @sa        adi_rtc_SynchronizeAllWrites().
+ */
+ADI_RTC_RESULT adi_rtc_SetAlarm (ADI_RTC_HANDLE const  hDevice, uint32_t nAlarm)
+{
+   ADI_RTC_DEVICE *pDevice = hDevice;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+
+    /* Wait till previously posted write to Alram Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
+
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* RTC hardware insures paired write, so no need to disable interrupts */
+    pDevice->pRTCRegs->ALM0 = (uint16_t)nAlarm;
+    pDevice->pRTCRegs->ALM1 = (uint16_t)(nAlarm >> 16);
+    pDevice->pRTCRegs->ALM2 = 0u;
+    ADI_EXIT_CRITICAL_REGION();
+    
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1))    
+
+    return ADI_RTC_SUCCESS;
+}
+
+/*!
+ * @brief  Set Prescale. This is  power of 2 division factor for the RTC base clock.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   nPreScale  Prescale value to be set. if "nPreScale" is 5, RTC base clock is
+                           divided by 32.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_GetAlarm().
+ * @sa        adi_rtc_EnableAlarm().
+ * @sa        adi_rtc_GetWritePendStatus().
+ * @sa        adi_rtc_SynchronizeAllWrites().
+ */
+ADI_RTC_RESULT adi_rtc_SetPreScale(ADI_RTC_HANDLE const  hDevice, uint8_t nPreScale )
+{
+   ADI_RTC_DEVICE *pDevice = hDevice;
+   uint16_t nTemp;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+    /* Pre scale is invalid for RTC0 */
+    if(pDevice->pRTCRegs == pADI_RTC0)
+    {
+        return(ADI_RTC_OPERATION_NOT_ALLOWED);
+    }
+#endif
+    PEND_BEFORE_WRITE(SR2,BITM_RTC_SR2_WPNDCR1MIR)
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* RTC hardware insures paired write, so no need to disable interrupts */
+    /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/
+    nTemp = pDevice->pRTCRegs->CR1 & (uint16_t)~BITM_RTC_CR1_PRESCALE2EXP;
+    nTemp |= (uint16_t)((uint16_t)nPreScale << BITP_RTC_CR1_PRESCALE2EXP);
+    pDevice->pRTCRegs->CR1 = nTemp;
+    ADI_EXIT_CRITICAL_REGION();
+    
+    SYNC_AFTER_WRITE(SR2,BITM_RTC_SR2_WSYNCCR1MIR)   
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Set the pre-scale. This is  power of 2 division factor for the RTC base clock.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   nPeriod    Periodic, modulo-60 alarm time in pre-scaled RTC time units beyond a modulo-60 boundary.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ *  @note     This API helps  the CPU to position a periodic (repeating) alarm interrupt from the RTC at any integer number of pre-scaled RTC time units from a modulo-60 boundary (roll-over event) of the value of count.
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_GetAlarm().
+ * @sa        adi_rtc_EnableAlarm().
+ * @sa        adi_rtc_GetWritePendStatus().
+ * @sa        adi_rtc_SynchronizeAllWrites().
+ */
+ADI_RTC_RESULT adi_rtc_SetMod60AlarmPeriod(ADI_RTC_HANDLE const hDevice, uint8_t nPeriod )
+{
+   ADI_RTC_DEVICE *pDevice = hDevice;
+   uint16_t nTemp;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+
+    /* Mod60 Alarm is valid only in RTC-1 */
+    if(pDevice->pRTCRegs == pADI_RTC0)
+    {
+        return(ADI_RTC_OPERATION_NOT_ALLOWED);
+    }
+
+#endif
+
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
+
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* RTC hardware insures paired write, so no need to disable interrupts */
+    /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/
+    nTemp = pDevice->pRTCRegs->CR0 & BITM_RTC_CR0_MOD60ALM;
+    nTemp |= (uint16_t)((uint16_t)nPeriod << BITP_RTC_CR0_MOD60ALM);
+    pDevice->pRTCRegs->CR0 = nTemp;
+    ADI_EXIT_CRITICAL_REGION();
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)    
+
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Set a new RTC alarm value with fractional value.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   fAlarm     New alarm value to set.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * Writes the 32-bit RTC alarm comparator with the value provided by \a Alarm.
+ *
+ * Honours the safe write mode if set.  Otherwise, it is the application's responsibility to
+ * synchronize any multiple writes to the same register.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_GetAlarm().
+ * @sa        adi_rtc_EnableAlarm().
+ * @sa        adi_rtc_GetWritePendStatus().
+ * @sa        adi_rtc_SynchronizeAllWrites().
+ */
+ADI_RTC_RESULT adi_rtc_SetAlarmEx(ADI_RTC_HANDLE const hDevice, float fAlarm)
+{
+   ADI_RTC_DEVICE *pDevice = hDevice;
+   uint32_t nAlarm = (uint32_t)fAlarm,nTemp;
+   uint16_t nPreScale;
+   float fFraction;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+    /* Only 1Hz clocking is supported in RTC-0.So no fractional Alarm. */
+    if(pDevice->pRTCRegs == pADI_RTC0)
+    {
+        return(ADI_RTC_OPERATION_NOT_ALLOWED);
+    }
+
+#endif
+
+    /* Wait till previously posted write to Alarm Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
+    nPreScale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP;
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* RTC hardware insures paired write, so no need to disable interrupts */
+    /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/
+    pDevice->pRTCRegs->ALM0 = (uint16_t)nAlarm;
+    pDevice->pRTCRegs->ALM1 = (uint16_t)(nAlarm >> 16);
+    nTemp = 1lu<<nPreScale;
+    fFraction = (fAlarm - (float)nAlarm) *(float)(nTemp);
+    pDevice->pRTCRegs->ALM2 = (uint16_t)(fFraction);
+    ADI_EXIT_CRITICAL_REGION();
+    /* Wait till  write to Alarm Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1))    
+
+    return ADI_RTC_SUCCESS;
+}
+
+/*!
+ * @brief  Set a new RTC control register value.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   eRegister  Specify which register need to be initialized.
+ * @param[in]   Control    New control register value to set.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * Writes the 16-bit RTC control register with the value provided by \a Control.
+ *
+ * Honours the safe write mode if set.  Otherwise, it is the application's responsibility to
+ * synchronize any multiple writes to the same register.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_GetControlRegister().
+ * @sa        adi_rtc_GetWritePendStatus().
+ * @sa        adi_rtc_SynchronizeAllWrites().
+ */
+ADI_RTC_RESULT adi_rtc_SetControlRegister(ADI_RTC_HANDLE const hDevice,ADI_RTC_CONTROL_REGISTER eRegister, uint32_t Control)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
+
+     switch(eRegister)
+     {
+     case ADI_RTC_CONTROL_REGISTER_0:
+          pDevice->pRTCRegs->CR0 = (uint16_t)Control;
+         break;
+     case ADI_RTC_CONTROL_REGISTER_1:
+         pDevice->pRTCRegs->CR1 = (uint16_t)Control;
+         break;
+     default:
+         return(ADI_RTC_FAILURE);
+     }
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)    
+    
+    return ADI_RTC_SUCCESS;
+
+}
+
+/*!
+ * @brief      Registers a Callback function with the RTC device driver. The registered call
+ *              back function will be called when an event is detected.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param [in]  pfCallback  Function pointer to Callback function. Passing a NULL pointer will
+ *                          unregister the call back function.
+ *
+ * @param [in]  pCBparam    Call back function parameter.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS              Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * @sa        adi_rtc_Open().
+ */
+ADI_RTC_RESULT adi_rtc_RegisterCallback(
+               ADI_RTC_HANDLE const  hDevice,
+               ADI_CALLBACK   const   pfCallback,
+               void        *const     pCBparam
+               )
+
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+
+#if (ADI_RTC_CFG_ENABLE_SAFE_WRITE == 1)
+    /* pause on pending writes to CR to avoid data loss */
+        while((pDevice->pRTCRegs->SR1 & (uint32_t)ADI_RTC_WRITE_STATUS_CONTROL0)!=0u)
+        {
+        }
+#endif
+    /* Store the address of the callback function */
+    pDevice->pfCallback =  pfCallback;
+    /* Store the call back parameter */
+    pDevice->pCBParam    =  pCBparam;
+
+    return ADI_RTC_SUCCESS;
+
+}
+
+/*!
+ * @brief  Set a new RTC count value.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   nCount     New count value to set.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * Writes the main 32-bit RTC counter with the value provided by \a Count.
+ *
+ * Honours the safe write mode if set.  Otherwise, it is the application's responsibility to
+ * synchronize any multiple writes to the same register.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_SetCount().
+ * @sa        adi_rtc_GetWritePendStatus().
+ * @sa        adi_rtc_SynchronizeAllWrites().
+ */
+ADI_RTC_RESULT adi_rtc_SetCount (ADI_RTC_HANDLE const hDevice, uint32_t nCount)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+
+#if (ADI_RTC_CFG_ENABLE_SAFE_WRITE == 1)
+    /* pause on pending writes to CR to avoid data loss */
+        while((pDevice->pRTCRegs->SR1 & (uint32_t)(ADI_RTC_WRITE_STATUS_COUNT0 | ADI_RTC_WRITE_STATUS_COUNT1)) !=0u)
+        {
+
+        }
+#endif
+
+    /* Wait till previously posted write to count Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1))
+
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* RTC hardware insures paired write, so no need to disable interrupts */
+    pDevice->pRTCRegs->CNT0 = (uint16_t)nCount;
+    pDevice->pRTCRegs->CNT1 = (uint16_t)(nCount >> 16);
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* Wait till  write to count Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCCNT0|BITM_RTC_SR0_WSYNCCNT1))    
+
+    return ADI_RTC_SUCCESS;
+}
+
+
+/*!
+ * @brief  Set an RTC gateway command.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   Command    Gateway command value.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * Writes the 16-bit RTC gateway register with the command provided by \a Command.
+ *
+ * The gateway register is used to force the RTC to perform some urgent action.
+ *
+ * Currently, only the #ADI_RTC_GATEWAY_FLUSH command is defined, which will cancel all
+ * RTC register write transactions, both pending and executing.  It is intended to truncate
+ * all core interactions in preparation for an imminent power loss when the RTC power
+ * isolation barrier will be activated.
+ *
+ * @sa        adi_rtc_Open().
+ */
+ADI_RTC_RESULT adi_rtc_SetGateway(ADI_RTC_HANDLE const hDevice, uint16_t Command)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* set the command */
+    pDevice->pRTCRegs->GWY = Command;
+    return ADI_RTC_SUCCESS;
+}
+
+
+
+/*!
+ * @brief  Set a new RTC trim value.
+ *
+ * @param[in]   hDevice      Device handle obtained from adi_rtc_Open().
+ * @param[in]   eInterval    Specify the trimming interval and will always in the range of (2^2 to S^17 pre-scaled RTC clock ).
+ * @param[in]   eTrimValue   Specify the trimming value.
+ * @param[in]   eOperation   Specify the operation(Add or subtract) need to be performed for trimming.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       Input parameter out of range.
+ *
+ * The RTC hardware has the ability to automatically trim the clock to compensate for variations
+ * in oscillator tolerance .   Automatic trimming is enabled with the #adi_rtc_EnableTrim() API.
+ *
+ * @note Alarms are not affected by automatic trim operations.
+ *
+ * @note The trim boundary (interval) alignment is reset when new trim values are written.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_EnableTrim().
+ * @sa        adi_rtc_GetTrim().
+ */
+ADI_RTC_RESULT adi_rtc_SetTrim(ADI_RTC_HANDLE const hDevice,  ADI_RTC_TRIM_INTERVAL eInterval, ADI_RTC_TRIM_VALUE  eTrimValue, ADI_RTC_TRIM_POLARITY eOperation)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+    uint32_t trm = (uint32_t)eInterval | (uint32_t)eTrimValue | (uint32_t)eOperation;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+
+#endif
+
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDTRM)
+
+    pDevice->pRTCRegs->TRM = (uint16_t)trm;
+    
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCTRM)    
+
+    return ADI_RTC_SUCCESS;
+}
+
+
+/*************************************************************************************************
+**************************************************************************************************
+************************************   SYNCHRONIZATION API   *************************************
+**************************************************************************************************
+*************************************************************************************************/
+
+
+/*!
+ * @brief  Force synchronization of all pending writes.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]     Invalid device handle parameter.
+ *
+ * Blocking call to coerce all outstanding posted RTC register writes to fully flush and synchronize.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_GetWritePendStatus().
+ * @sa        adi_rtc_GetWriteSyncStatus().
+*/
+ADI_RTC_RESULT adi_rtc_SynchronizeAllWrites (ADI_RTC_HANDLE const hDevice)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+
+#endif
+
+    /* forced block until all SYNC bits are set (ignore bSafe) */
+    while (ADI_RTC_WRITE_STATUS_MASK != (pDevice->pRTCRegs->SR0 & ADI_RTC_WRITE_STATUS_MASK))
+    {
+
+    }
+
+    return ADI_RTC_SUCCESS;
+}
+
+
+/*! \cond PRIVATE */
+
+/*
+ * @brief       Initializes the device  using static configuration 
+ *
+ * @param[in]   pDevice    Pointer to RTC device .
+                pConfig    Pointer to static configuration device structure.
+ *
+*/
+
+static void rtc_init(ADI_RTC_DEVICE *pDevice,ADI_RTC_CONFIG *pConfig)
+{
+  
+  /* FIXME - static init is even more now */
+  
+    /* Control register -0 which controls all main stream activity of RTC0 */
+    pDevice->pRTCRegs->CR0  =   pConfig->CR0;
+    /* Control register -1  which is  granularity of RTC control register */    
+    pDevice->pRTCRegs->CR1  =   pConfig->CR1;
+    /*CNT0 contains the lower 16 bits of the RTC counter  */    
+    pDevice->pRTCRegs->CNT0 =   pConfig->CNT0;
+    /*CNT1 contains the lower 16 bits of the RTC counter  */        
+    pDevice->pRTCRegs->CNT1 =   pConfig->CNT1;
+    /* ALM0 contains the lower 16 bits of the Alarm register */
+    pDevice->pRTCRegs->ALM0 =   pConfig->ALM0;
+    /* ALM1 contains the upper  16 bits of the Alarm register */
+    pDevice->pRTCRegs->ALM1 =   pConfig->ALM1;
+     /* ALM1 contains the fractional part of  the Alarm register */
+    pDevice->pRTCRegs->ALM2 =   pConfig->ALM2;
+    /* Set Input capture/sensor strobe registers only for RTC1 */
+    if(pDevice->pRTCRegs == pADI_RTC1)
+    {
+        pDevice->pRTCRegs->CR2IC  =   pConfig->CR2IC;
+        pDevice->pRTCRegs->CR3SS  =   pConfig->CR3SS;
+        pDevice->pRTCRegs->CR4SS  =   pConfig->CR4SS;
+        pDevice->pRTCRegs->SSMSK  =   pConfig->SSMSK;
+        pDevice->pRTCRegs->SS1    =   pConfig->SS1;
+#if defined(__ADUCM4x50__)        
+        pDevice->pRTCRegs->CR5SSS =   pConfig->CR5SSS;
+        pDevice->pRTCRegs->CR6SSS =   pConfig->CR6SSS;
+        pDevice->pRTCRegs->CR7SSS =   pConfig->CR7SSS;
+        pDevice->pRTCRegs->GPMUX0 =   pConfig->GPMUX0;
+        pDevice->pRTCRegs->GPMUX1 =   pConfig->GPMUX1;
+#endif /* __ADUCM4x50__ */        
+    }
+}
+
+
+
+/*! @brief  RTC device driver interrupt handler.  Overrides weakly-bound default interrupt handler in <Device>_startup.c. */
+void RTC0_Int_Handler(void)
+{
+    ISR_PROLOG();    
+    uint16_t nIntSrc0, nIntSrc2, nIntSrc3;
+    uint32_t fired = 0u, enables = 0u;
+    ADI_RTC_DEVICE *pDevice = aRTCDeviceInfo[0].hDevice;
+
+    /* determine qualified interrupt source(s) */
+    /* need to test each interrupt source and whether it is enabled before notifying */
+    /* because each source is latched regardless of whether it is enabled or not :-( */
+
+    /* CR0   SR0 */
+    enables = (uint32_t)pDevice->pRTCRegs->CR0  & ADI_RTC_INT_ENA_MASK_CR0;
+    nIntSrc0 = pDevice->pRTCRegs->SR0 & ADI_RTC_INT_SOURCE_MASK_SR0;
+    if( nIntSrc0 && enables )
+    {
+      if( (enables & BITM_RTC_CR0_MOD60ALMEN) && (nIntSrc0 & BITM_RTC_SR0_MOD60ALMINT))
+      {
+        fired |= ADI_RTC_MOD60ALM_INT;
+      }
+      if( (enables & BITM_RTC_CR0_ALMINTEN) && (nIntSrc0 & BITM_RTC_SR0_ALMINT))
+      {
+        fired |= ADI_RTC_ALARM_INT;
+      }
+      if( (enables & BITM_RTC_CR0_ISOINTEN) && (nIntSrc0 & BITM_RTC_SR0_ISOINT))
+      {
+        fired |= ADI_RTC_ISO_DONE_INT;
+      }
+      if( (enables & BITM_RTC_CR0_WPNDINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDINT))
+      {
+        fired |= ADI_RTC_WRITE_PEND_INT;
+      }
+      if( (enables & BITM_RTC_CR0_WSYNCINTEN) && (nIntSrc0 & BITM_RTC_SR0_WSYNCINT))
+      {
+        fired |= ADI_RTC_WRITE_SYNC_INT;
+      }
+      if( (enables & BITM_RTC_CR0_WPNDERRINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDERRINT))
+      {
+        fired |= ADI_RTC_WRITE_PENDERR_INT;
+      }
+    }
+      
+    /* CR1  SR2 */
+    enables = (uint32_t)pDevice->pRTCRegs->CR1  & ADI_RTC_INT_ENA_MASK_CR1;
+    nIntSrc2 = pDevice->pRTCRegs->SR2 & ADI_RTC_INT_SOURCE_MASK_SR2;
+    if( nIntSrc2 && enables )
+    {
+      if( (enables & BITM_RTC_CR1_CNTMOD60ROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTMOD60ROLLINT))
+      {
+        fired |= ADI_RTC_MOD60_ROLLOVER_INT;
+      }
+      if( (enables & BITM_RTC_CR1_CNTROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTROLLINT))
+      {
+        fired |= ADI_RTC_COUNT_ROLLOVER_INT;
+      }
+      if( (enables & BITM_RTC_CR1_TRMINTEN) && (nIntSrc2 & BITM_RTC_SR2_TRMINT))
+      {
+        fired |= ADI_RTC_TRIM_INT;
+      }
+      if( (enables & BITM_RTC_CR1_PSINTEN) && (nIntSrc2 & BITM_RTC_SR2_PSINT))
+      {
+        fired |= ADI_RTC_PSI_INT;
+      }
+      if( (enables & BITM_RTC_CR1_CNTINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTINT))
+      {
+        fired |= ADI_RTC_COUNT_INT;
+      }
+    }
+    
+    /* CR3OC, CR2IC  SR3*/
+    enables = pDevice->pRTCRegs->CR3SS  &  (uint16_t)ADI_RTC_INT_ENA_MASK_CR3SS;
+    nIntSrc3 = pDevice->pRTCRegs->SR3 & ADI_RTC_SR3_IRQ_STATUS_MASK;
+    if( nIntSrc3 && enables )
+    {
+#if defined(__ADUCM4x50__)      
+      if( (enables & BITM_RTC_CR3SS_SS4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4IRQ))
+      {
+        fired |= ADI_RTC_SENSOR_STROBE_CH4_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3IRQ))
+      {
+        fired |= ADI_RTC_SENSOR_STROBE_CH3_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2IRQ))
+      {
+        fired |= ADI_RTC_SENSOR_STROBE_CH2_INT;
+      }
+#endif /* __ADUCM4x50__ */
+      
+      if( (enables & BITM_RTC_CR3SS_SS1IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1IRQ))
+      {
+        fired |= ADI_RTC_SENSOR_STROBE_CH1_INT;
+      }
+      
+#if defined(__ADUCM4x50__)      
+      if( (enables & BITM_RTC_CR3SS_SS4FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4FEIRQ))
+      {
+        fired |= ADI_RTC_RTCSS4_FE_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS3FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2FEIRQ))
+      {
+        fired |= ADI_RTC_RTCSS3_FE_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS2FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3FEIRQ))
+      {
+        fired |= ADI_RTC_RTCSS2_FE_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS1FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1FEIRQ))
+      {
+        fired |= ADI_RTC_RTCSS1_FE_INT;
+      }
+#endif /* __ADUCM4x50__ */      
+   }
+   enables = pDevice->pRTCRegs->CR3SS  & (uint16_t)ADI_RTC_INT_ENA_MASK_CR2IC;
+   if( nIntSrc3 && enables )
+   {
+      if( (enables & BITM_RTC_CR2IC_IC4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC4IRQ))
+      {
+        fired |= ADI_RTC_INPUT_CAPTURE_CH4_INT;
+      }
+      if( (enables & BITM_RTC_CR2IC_IC3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC3IRQ))
+      {
+        fired |= ADI_RTC_INPUT_CAPTURE_CH3_INT;
+      }
+      if( (enables & BITM_RTC_CR2IC_IC2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC2IRQ))
+      {
+        fired |= ADI_RTC_INPUT_CAPTURE_CH2_INT;
+      }
+      if( (enables & BITM_RTC_CR2IC_IC0IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC0IRQ))
+      {
+        fired |= ADI_RTC_INPUT_CAPTURE_CH0_INT;
+      }
+   }
+   
+    
+    if (pDevice->pfCallback != NULL) {
+
+        /* forward to the user if he is watching this interrupt */
+        /* pass the "fired" value as the event.  argument param is not used */
+        if ( fired)
+        {
+            pDevice->pfCallback (pDevice->pCBParam, fired, NULL);
+        }
+    }
+    
+    /* Write 1 to clear the interrupts */ 
+    pDevice->pRTCRegs->SR0 |= nIntSrc0;
+    pDevice->pRTCRegs->SR2 |= nIntSrc2;
+    pDevice->pRTCRegs->SR3 |= nIntSrc3;
+    ISR_EPILOG();        
+}
+
+/*! @brief  RTC device driver interrupt handler.  Overrides weakly-bound default interrupt handler in <Device>_startup.c. */
+void RTC1_Int_Handler(void)
+{
+    ISR_PROLOG();    
+    uint16_t nIntSrc0, nIntSrc2, nIntSrc3;
+    uint32_t fired = 0u, enables = 0u;
+    ADI_RTC_DEVICE *pDevice = aRTCDeviceInfo[1].hDevice;
+
+    /* determine qualified interrupt source(s) */
+    /* need to test each interrupt source and whether it is enabled before notifying */
+    /* because each source is latched regardless of whether it is enabled or not :-( */
+
+    /* CR0   SR0 */
+    enables = (uint32_t)pDevice->pRTCRegs->CR0  & ADI_RTC_INT_ENA_MASK_CR0;
+    nIntSrc0 = pDevice->pRTCRegs->SR0 & ADI_RTC_INT_SOURCE_MASK_SR0;
+    if( nIntSrc0 && enables )
+    {
+      if( (enables & BITM_RTC_CR0_MOD60ALMEN) && (nIntSrc0 & BITM_RTC_SR0_MOD60ALMINT))
+      {
+        fired |= ADI_RTC_MOD60ALM_INT;
+      }
+      if( (enables & BITM_RTC_CR0_ALMINTEN) && (nIntSrc0 & BITM_RTC_SR0_ALMINT))
+      {
+        fired |= ADI_RTC_ALARM_INT;
+      }
+      if( (enables & BITM_RTC_CR0_ISOINTEN) && (nIntSrc0 & BITM_RTC_SR0_ISOINT))
+      {
+        fired |= ADI_RTC_ISO_DONE_INT;
+      }
+      if( (enables & BITM_RTC_CR0_WPNDINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDINT))
+      {
+        fired |= ADI_RTC_WRITE_PEND_INT;
+      }
+      if( (enables & BITM_RTC_CR0_WSYNCINTEN) && (nIntSrc0 & BITM_RTC_SR0_WSYNCINT))
+      {
+        fired |= ADI_RTC_WRITE_SYNC_INT;
+      }
+      if( (enables & BITM_RTC_CR0_WPNDERRINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDERRINT))
+      {
+        fired |= ADI_RTC_WRITE_PENDERR_INT;
+      }
+    }
+      
+    /* CR1  SR2 */
+    enables = (uint32_t)pDevice->pRTCRegs->CR1  & ADI_RTC_INT_ENA_MASK_CR1;
+    nIntSrc2 = pDevice->pRTCRegs->SR2 & ADI_RTC_INT_SOURCE_MASK_SR2;
+    if( nIntSrc2 && enables )
+    {
+      if( (enables & BITM_RTC_CR1_CNTMOD60ROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTMOD60ROLLINT))
+      {
+        fired |= ADI_RTC_MOD60_ROLLOVER_INT;
+      }
+      if( (enables & BITM_RTC_CR1_CNTROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTROLLINT))
+      {
+        fired |= ADI_RTC_COUNT_ROLLOVER_INT;
+      }
+      if( (enables & BITM_RTC_CR1_TRMINTEN) && (nIntSrc2 & BITM_RTC_SR2_TRMINT))
+      {
+        fired |= ADI_RTC_TRIM_INT;
+      }
+      if( (enables & BITM_RTC_CR1_PSINTEN) && (nIntSrc2 & BITM_RTC_SR2_PSINT))
+      {
+        fired |= ADI_RTC_PSI_INT;
+      }
+      if( (enables & BITM_RTC_CR1_CNTINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTINT))
+      {
+        fired |= ADI_RTC_COUNT_INT;
+      }
+    }
+    
+    /* CR3OC, CR2IC  SR3*/
+    enables = pDevice->pRTCRegs->CR3SS  & (uint32_t)ADI_RTC_INT_ENA_MASK_CR3SS;
+    nIntSrc3 = pDevice->pRTCRegs->SR3 & ADI_RTC_SR3_IRQ_STATUS_MASK;
+    if( nIntSrc3 && enables )
+    {
+#if defined(__ADUCM4x50__)      
+      if( (enables & BITM_RTC_CR3SS_SS4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4IRQ))
+      {
+        fired |= ADI_RTC_SENSOR_STROBE_CH4_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3IRQ))
+      {
+        fired |= ADI_RTC_SENSOR_STROBE_CH3_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2IRQ))
+      {
+        fired |= ADI_RTC_SENSOR_STROBE_CH2_INT;
+      }
+#endif /* __ADUCM4x50__ */      
+      if( (enables & BITM_RTC_CR3SS_SS1IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1IRQ))
+      {
+        fired |= ADI_RTC_SENSOR_STROBE_CH1_INT;
+      }
+#if defined(__ADUCM4x50__)      
+      if( (enables & BITM_RTC_CR3SS_SS4FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4FEIRQ))
+      {
+        fired |= ADI_RTC_RTCSS4_FE_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS3FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2FEIRQ))
+      {
+        fired |= ADI_RTC_RTCSS3_FE_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS2FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3FEIRQ))
+      {
+        fired |= ADI_RTC_RTCSS2_FE_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS1FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1FEIRQ))
+      {
+        fired |= ADI_RTC_RTCSS1_FE_INT;
+      }
+#endif /* __ADUCM4x50__ */      
+   }
+   enables = pDevice->pRTCRegs->CR2IC  & (uint32_t)ADI_RTC_INT_ENA_MASK_CR2IC;
+   if( nIntSrc3 && enables )
+   {
+      if( (enables & BITM_RTC_CR2IC_IC4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC4IRQ))
+      {
+        fired |= ADI_RTC_INPUT_CAPTURE_CH4_INT;
+      }
+      if( (enables & BITM_RTC_CR2IC_IC3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC3IRQ))
+      {
+        fired |= ADI_RTC_INPUT_CAPTURE_CH3_INT;
+      }
+      if( (enables & BITM_RTC_CR2IC_IC2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC2IRQ))
+      {
+        fired |= ADI_RTC_INPUT_CAPTURE_CH2_INT;
+      }
+      if( (enables & BITM_RTC_CR2IC_IC0IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC0IRQ))
+      {
+        fired |= ADI_RTC_INPUT_CAPTURE_CH0_INT;
+      }
+   }
+   
+    if (pDevice->pfCallback != NULL) {
+
+        /* forward to the user if he is watching this interrupt */
+        /* pass the "fired" value as the event.  argument param is not used */
+        if ( fired)
+        {
+            pDevice->pfCallback (pDevice->pCBParam, fired, NULL);
+        }
+    }
+    
+    /* Write 1 to clear the interrupts */ 
+    pDevice->pRTCRegs->SR0 |= nIntSrc0;
+    pDevice->pRTCRegs->SR2 |= nIntSrc2;
+    pDevice->pRTCRegs->SR3 |= nIntSrc3;
+    
+    ISR_EPILOG();        
+}
+
+/*! \endcond */
+
+/* @} */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtc/adi_rtc_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtc/adi_rtc_data.c
new file mode 100755
index 00000000000..a4403847156
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtc/adi_rtc_data.c
@@ -0,0 +1,202 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_rtc_data.c
+ * @brief:   rtc device data file
+ * @version: $Revision: 34933 $
+ * @date:    $Date: 2016-06-28 07:11:25 -0400 (Tue, 28 Jun 2016) $
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/*! \cond PRIVATE */
+#ifndef ADI_RTC_DATA_C_
+#define ADI_RTC_DATA_C_
+
+#include <stdlib.h>
+#include <adi_processor.h>
+#include "adi_rtc_def.h"
+
+static ADI_RTC_DEVICE_INFO aRTCDeviceInfo[ADI_RTC_NUM_INSTANCE] =
+{
+     {
+	(ADI_RTC_TypeDef *)pADI_RTC0,RTC0_EVT_IRQn, NULL
+     },
+     {
+	(ADI_RTC_TypeDef *)pADI_RTC1,RTC1_EVT_IRQn,NULL,
+     }
+};
+
+
+static ADI_RTC_CONFIG aRTCConfig[ADI_RTC_NUM_INSTANCE] =
+{
+  {
+    /* CR0 */
+   RTC0_CFG_ENABLE_ALARM                    <<  BITP_RTC_CR0_ALMEN         |
+   RTC0_CFG_ENABLE_ALARM_INTERRUPT          <<  BITP_RTC_CR0_ALMINTEN      |
+   RTC0_CFG_ENABLE_TRIM                      <<  BITP_RTC_CR0_TRMEN         |
+   RTC0_CFG_ENABLE_PENDERROR_INTERRUPT       <<  BITP_RTC_CR0_WPNDERRINTEN  |
+   RTC0_CFG_ENABLE_WSYNC_INTERRUPT           <<  BITP_RTC_CR0_WSYNCINTEN    |
+   RTC0_CFG_ENABLE_WRITEPEND_INTERRUPT       <<  BITP_RTC_CR0_WPNDINTEN ,
+   /* CR1 */
+   0,
+   /* CNT0 */
+   RTC0_CFG_COUNT_VALUE_0,
+   /* CNT1 */
+   RTC0_CFG_COUNT_VALUE_1,
+   /* ALM0 */
+   RTC0_CFG_ALARM_VALUE_0,
+   /* ALM1 */
+   RTC0_CFG_ALARM_VALUE_1,
+   /* ALM2 */
+   0,
+   /* TRIM */
+   RTC0_CFG_POW2_TRIM_INTERVAL               << BITP_RTC_TRM_IVL2EXPMIN   |
+   RTC0_CFG_TRIM_INTERVAL                    << BITP_RTC_TRM_IVL          |
+   RTC0_CFG_TRIM_OPERATION                   << BITP_RTC_TRM_ADD          |
+   RTC0_CFG_TRIM_VALUE                       << BITP_RTC_TRM_VALUE,
+   0,     /* CR2IC */
+   0,     /* CR3SS */
+   0,     /* CR4SS */
+   0,     /* SSMSK */
+   0,     /* SS1 */
+   0,     /* CR5SSS */
+   0,     /* CR6SSS */
+   0,     /* CR7SSS */
+   0,     /* GPMUX0 */
+   0     /* GPMUX1 */
+
+  },
+  /* RTC-1 */
+  {
+    /* CR0 */
+   RTC1_CFG_ENABLE_ALARM                    <<  BITP_RTC_CR0_ALMEN         |
+   RTC1_CFG_ENABLE_ALARM_INTERRUPT          <<  BITP_RTC_CR0_ALMINTEN      |
+   RTC1_CFG_ENABLE_TRIM                      <<  BITP_RTC_CR0_TRMEN         |
+   RTC1_CFG_ENABLE_MOD60_ALARM              <<  BITP_RTC_CR0_MOD60ALMEN    |
+   RTC1_CFG_ENABLE_MOD60_ALARM_PERIOD       <<  BITP_RTC_CR0_MOD60ALM      |
+   RTC1_CFG_ENABLE_MOD60_ALARM_INTERRUPT    <<  BITP_RTC_CR0_MOD60ALMINTEN |
+   RTC1_CFG_ENABLE_ISO_INTERRUPT             <<  BITP_RTC_CR0_ISOINTEN      |
+   RTC1_CFG_ENABLE_PENDERROR_INTERRUPT       <<  BITP_RTC_CR0_WPNDERRINTEN  |
+   RTC1_CFG_ENABLE_WSYNC_INTERRUPT           <<  BITP_RTC_CR0_WSYNCINTEN    |
+   RTC1_CFG_ENABLE_WRITEPEND_INTERRUPT       <<  BITP_RTC_CR0_WPNDINTEN ,
+    /* CR1 */
+   RTC1_CFG_ENABLE_COUNT_INTERRUPT           <<  BITP_RTC_CR1_CNTINTEN       |
+   RTC1_CFG_ENABLE_MOD1_COUNT_INTERRUPT      <<  BITP_RTC_CR1_PSINTEN        |
+   RTC1_CFG_ENABLE_TRIM_INTERRUPT            <<  BITP_RTC_CR1_TRMINTEN    |
+   RTC1_CFG_CNT_MOD60_ROLLLOVER_INTERRUPT    <<  BITP_RTC_CR1_CNTROLLINTEN   |
+   RTC1_CFG_PRESCALE                         <<  BITP_RTC_CR1_PRESCALE2EXP   |
+   RTC1_CFG_CNT_ROLLLOVER_INTERRUPT          <<  BITP_RTC_CR1_CNTMOD60ROLLINTEN ,
+   /* CNT0 */
+   RTC1_CFG_COUNT_VALUE_0,
+   /* CNT1 */
+   RTC1_CFG_COUNT_VALUE_1,
+
+   /* ALM[123] */
+   RTC1_CFG_ALARM_VALUE_0,
+   RTC1_CFG_ALARM_VALUE_1,
+   RTC1_CFG_ALARM_VALUE_2,
+
+   /* TRIM */
+   RTC1_CFG_POW2_TRIM_INTERVAL               << BITP_RTC_TRM_IVL2EXPMIN  |
+   RTC1_CFG_TRIM_INTERVAL                    << BITP_RTC_TRM_IVL         |
+   RTC1_CFG_TRIM_OPERATION                   << BITP_RTC_TRM_ADD         |
+   RTC1_CFG_TRIM_VALUE                       << BITP_RTC_TRM_VALUE,
+
+   /* CR2IC */
+   RTC1_CFG_IC0_ENABLE                       <<  BITP_RTC_CR2IC_IC0EN    |
+   RTC1_CFG_IC2_ENABLE                       <<  BITP_RTC_CR2IC_IC2EN    |
+   RTC1_CFG_IC3_ENABLE                       <<  BITP_RTC_CR2IC_IC3EN    |
+   RTC1_CFG_IC4_ENABLE                       <<  BITP_RTC_CR2IC_IC4EN    |
+   RTC1_CFG_IC0_INT_ENABLE                   <<  BITP_RTC_CR2IC_IC0IRQEN |
+   RTC1_CFG_IC0_INT_ENABLE                   <<  BITP_RTC_CR2IC_IC2IRQEN |
+   RTC1_CFG_IC0_INT_ENABLE                   <<  BITP_RTC_CR2IC_IC3IRQEN |
+   RTC1_CFG_IC0_INT_ENABLE                   <<  BITP_RTC_CR2IC_IC4IRQEN |
+   RTC1_CFG_IC0_EDGE_POLARITY                <<  BITP_RTC_CR2IC_IC0LH    |
+   RTC1_CFG_IC2_EDGE_POLARITY                <<  BITP_RTC_CR2IC_IC2LH    |
+   RTC1_CFG_IC3_EDGE_POLARITY                <<  BITP_RTC_CR2IC_IC3LH    |
+   RTC1_CFG_IC4_EDGE_POLARITY                <<  BITP_RTC_CR2IC_IC4LH    |
+   RTC1_CFG_IC_OVER_WRITE_ENABLE             <<  BITP_RTC_CR2IC_ICOWUSEN,
+
+#if defined(__ADUCM4x50__)
+   /* CR3SS */
+   RTC1_CFG_SS1_ENABLE                       <<  BITP_RTC_CR3SS_SS1EN    |
+   RTC1_CFG_SS2_ENABLE                       <<  BITP_RTC_CR3SS_SS2EN    |
+   RTC1_CFG_SS3_ENABLE                       <<  BITP_RTC_CR3SS_SS3EN    |
+   RTC1_CFG_SS4_ENABLE                       <<  BITP_RTC_CR3SS_SS4EN    |
+   RTC1_CFG_SS1_INT_ENABLE                   <<  BITP_RTC_CR3SS_SS1IRQEN |
+   RTC1_CFG_SS2_INT_ENABLE                   <<  BITP_RTC_CR3SS_SS2IRQEN |
+   RTC1_CFG_SS3_INT_ENABLE                   <<  BITP_RTC_CR3SS_SS3IRQEN |
+   RTC1_CFG_SS4_INT_ENABLE                   <<  BITP_RTC_CR3SS_SS4IRQEN,
+
+   /* CR4SS */
+   RTC1_CFG_SS1_MASK_ENABLE                  <<  BITP_RTC_CR4SS_SS1MSKEN |
+   RTC1_CFG_SS2_MASK_ENABLE                  <<  BITP_RTC_CR4SS_SS2MSKEN |
+   RTC1_CFG_SS3_MASK_ENABLE                  <<  BITP_RTC_CR4SS_SS3MSKEN |
+   RTC1_CFG_SS4_MASK_ENABLE                  <<  BITP_RTC_CR4SS_SS4MSKEN |
+   RTC1_CFG_SS1_AUTO_RELOADING_ENABLE        <<  BITP_RTC_CR4SS_SS1ARLEN,
+#elif defined(__ADUCM302x__)
+   /* CR3SS */
+   RTC1_CFG_SS1_ENABLE                       <<  BITP_RTC_CR3SS_SS1EN    |
+   RTC1_CFG_SS1_INT_ENABLE                   <<  BITP_RTC_CR3SS_SS1IRQEN |
+
+   /* CR4SS */
+   RTC1_CFG_SS1_MASK_ENABLE                  <<  BITP_RTC_CR4SS_SS1MSKEN |
+   RTC1_CFG_SS1_AUTO_RELOADING_ENABLE        <<  BITP_RTC_CR4SS_SS1ARLEN,
+#else
+#error RTC driver not ported to this processor
+#endif
+   /* SSMSK */
+   RTC1_CFG_SS1_MASK_VALUE,
+
+   /* SS1 */
+   RTC1_CFG_SS1_AUTO_RELOAD_VALUE,
+
+   0,      /* CR5SSS */                      /* TODO: Add the following to the static configuration macros */
+   0,      /* CR6SSS */
+   0,      /* CR7SSS */
+   0x4688, /* GPMUX0 */
+   0x01F5, /* GPMUX1 */
+
+  }
+
+};
+
+#endif
+/*! \endcond */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtc/adi_rtc_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtc/adi_rtc_def.h
new file mode 100755
index 00000000000..a6fca0e37b5
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtc/adi_rtc_def.h
@@ -0,0 +1,165 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_rtc_def.h
+ * @brief:   RTC def file
+ * @version: $Revision: 33205 $
+ * @date:    $Date: 2016-01-11 05:46:07 -0500 (Mon, 11 Jan 2016) $
+ *-----------------------------------------------------------------------------
+ *
+ * Copyright (c) 2010-2016 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright notice,
+ *   this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ *   this list of conditions and the following disclaimer in the documentation
+ *   and/or other materials provided with the distribution.
+ * - Modified versions of the software must be conspicuously marked as such.
+ * - This software is licensed solely and exclusively for use with processors
+ *   manufactured by or for Analog Devices, Inc.
+ * - This software may not be combined or merged with other code in any manner
+ *   that would cause the software to become subject to terms and conditions
+ *   which differ from those listed here.
+ * - Neither the name of Analog Devices, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ * - The use of this software may or may not infringe the patent rights of one
+ *   or more patent holders.  This license does not release you from the
+ *   requirement that you obtain separate licenses from these patent holders
+ *   to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+ * PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef ADI_RTC_DEF_H__
+#define ADI_RTC_DEF_H__
+
+#include <drivers/rtc/adi_rtc.h>
+
+/*! \cond PRIVATE */
+#define ADI_RTC_NUM_INSTANCE 2u
+
+
+
+#define ADI_RTC_INT_ENA_MASK_CR0         0XF804u
+
+#define ADI_RTC_INT_ENA_MASK_CR1         0X1Fu
+
+#define ADI_RTC_INT_ENA_MASK_CR2IC       0xF41C
+#define ADI_RTC_INT_ENA_MASK_CR3SS       0x1FFE
+#define ADI_RTC_INT_ENA_MASK_CR4SS       0x0E0E
+#define ADI_RTC_INT_ENA_MASK_CR5SSS      0x0FFF
+
+#define ADI_RTC_INT_SOURCE_MASK_SR0      0x007Eu
+#define ADI_RTC_INT_SOURCE_MASK_SR2      0x001Fu
+
+#define ADI_RTC_WRITE_STATUS_MASK        0XCF8u
+#define ADI_RTC_SR2_IRQ_STATUS_MASK      0X1Fu
+#define ADI_RTC_SR3_IRQ_STATUS_MASK      0X1FFFu
+
+
+
+#define ADI_RTC_TRIM_MASK (BITM_RTC_TRM_VALUE | BITM_RTC_TRM_ADD|BITM_RTC_TRM_IVL | BITM_RTC_TRM_IVL2EXPMIN )
+
+#if (ADI_RTC_CFG_ENABLE_SAFE_WRITE == 1)
+    /* pause on pending writes to CR to avoid data loss */
+
+#ifdef __ICCARM__
+/*
+* Pm154 (rule 19.10): in the definition of a function-like macro, each instance
+*                     of a parameter shall be enclosed in parentheses
+*   Parameter use without parentheses needed for struct field name in register access macro.
+*/
+#pragma diag_suppress=Pm154
+#endif /* __ICCARM__ */
+
+#define  PEND_BEFORE_WRITE(reg,mask) while((pDevice->pRTCRegs->reg&(mask))!=0u)\
+        {\
+        }
+
+#define  SYNC_AFTER_WRITE(reg,mask) while((pDevice->pRTCRegs->reg&(mask))==0u)\
+        {\
+        }
+
+#ifdef __ICCARM__
+#pragma diag_default=Pm154
+#endif /* __ICCARM__ */
+
+#else
+    /* pause on pending writes to CR to avoid data loss */
+#define  PEND_BEFORE_WRITE(reg,mask)
+#define  SYNC_AFTER_WRITE(reg,mask)
+#endif
+
+/*
+ * The following is used for static configuration
+ */
+typedef struct
+{
+    uint16_t    CR0;             /*!< CR0 16 bit control register-0 value */
+    uint16_t    CR1;             /*!< CR1 16 bit control register-1 value */
+    uint16_t    CNT0;            /*!< CNT0 16 bit count register value */
+    uint16_t    CNT1;            /*!< CNT1 16 bit count register value */
+
+    uint16_t    ALM0;            /*!< ALM0 16 bit integer part of alarm value */
+    uint16_t    ALM1;            /*!< ALM1 16 bit integer part of alarm value */
+    uint16_t    ALM2;            /*!< ALM2 16 bit integer part of alarm value */
+    uint16_t    TRIM;              /*!< 16 bit trim register value */
+    uint16_t    CR2IC;           /*!< CR2IC 16 bit control (which controls the input capture ) register-2 value */
+    uint16_t    CR3SS;           /*!< CR3SS 16 bit control ( Controls enabling sensor strobe /IRQ etc )register-3 value */
+    uint16_t    CR4SS;           /*!< CR4SS 16 bit control ( controls Auto reload  and mask for sensor strobe  ) register-4 value */
+    uint16_t    SSMSK;           /*!< OCMSK Mask register for sensor strobe channel */
+    uint16_t    SS1;             /*!< 16 bit Auto reload value */
+
+    uint16_t    CR5SSS;         /*!< Configure Sensor Strobe Channel GPIO Sampling Register */
+    uint16_t    CR6SSS;         /*!< Configure Sensor Strobe Channel GPIO Sampling Register */
+    uint16_t    CR7SSS;         /*!< Configure Sensor Strobe Channel GPIO Sampling Register */
+    uint16_t    GPMUX0;         /*!< Control register for selecting a GPIO (pin) as data to be sampled by a Sensor Strobe  channel */
+    uint16_t    GPMUX1;         /*!< Control register for selecting a GPIO (pin) as data to be sampled by a Sensor Strobe  channel */
+}ADI_RTC_CONFIG;
+
+/* Device information structure */
+typedef struct _ADI_RTC_DEVICE_INFO
+{
+    volatile ADI_RTC_TypeDef  *pRTCRegs;   /* Base address of the  SPORT registers */
+    const IRQn_Type            eIRQn;      /* IRQn */
+    ADI_RTC_HANDLE             hDevice;    /* RTC handle */
+}ADI_RTC_DEVICE_INFO;
+
+/*! RTC driver instance data */
+typedef struct _ADI_RTC_DEVICE
+{
+    volatile ADI_RTC_TypeDef *pRTCRegs;    /* Pointer to RTC Memory Mapped Registers */
+
+    ADI_CALLBACK              pfCallback;  /*  Function pointer for callback function. */
+
+    void                     *pCBParam;    /*  Parameter to callback function. */
+    IRQn_Type                eIRQn;        /* IRQn */
+    uint32_t  cbWatch;
+    ADI_RTC_DEVICE_INFO     *pDeviceInfo;  /*  Parameter to callback function. */
+
+} ADI_RTC_DEVICE;
+
+
+static void rtc_init(ADI_RTC_DEVICE *pDevice,ADI_RTC_CONFIG *pConfig);
+
+#ifdef ADI_DEBUG
+static ADI_RTC_RESULT ValidateHandle( ADI_RTC_DEVICE *pInDevice);
+#endif
+/*! \endcond */
+#endif /* ADI_RTC_DEF_H__ */
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map.h
new file mode 100755
index 00000000000..7224c14faa4
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map.h
@@ -0,0 +1,71 @@
+/*!
+ *****************************************************************************
+ @file:    adi_rtos_map.h
+ @brief:   RTOS API mapping file.
+           This is the main RTOS mapping header file which will include other
+           RTOS mapping files based on the RTOS selection.
+           
+           The purpose of RTOS mapping file is for mapping the abstracted
+           RTOS macros to the RTOS API calls based on the chosen RTOS.
+           
+           NOTE: This file is intended to be used by only the drivers. Not at 
+                 the application level.
+           
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+#ifndef ADI_RTOS_MAP_H
+#define ADI_RTOS_MAP_H
+
+#include <adi_global_config.h>
+
+#if   (ADI_CFG_RTOS == ADI_CFG_RTOS_MICRIUM_III)
+    
+#include "rtos_map/adi_rtos_map_ucos_iii.h"
+
+#elif (ADI_CFG_RTOS == ADI_CFG_RTOS_FREERTOS)
+    
+#include "rtos_map/adi_rtos_map_freertos.h"    
+
+#else 
+    
+#include "rtos_map/adi_rtos_map_noos.h"
+
+#endif /* ADI_CFG_RTOS_MICRIUM_III */ 
+
+#endif /* ADI_RTOS_MAP_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map_freertos.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map_freertos.h
new file mode 100755
index 00000000000..97cbcaeeb78
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map_freertos.h
@@ -0,0 +1,144 @@
+/*!
+ *****************************************************************************
+ @file:    adi_rtos_map_freertos.h
+ @brief:   FreeRTOS RTOS API mapping file.
+
+           This file maps the RTOS macros to FreeRTOS APIs
+           
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+
+#ifndef ADI_RTOS_MAP_FREERTOS_H
+#define ADI_RTOS_MAP_FREERTOS_H
+
+/* If building a c file */
+#if defined(__STDC__)
+
+#include <FreeRTOS.h>
+#include "semphr.h"
+
+extern BaseType_t xHigherPriorityTaskWoken;
+  
+/*! Macro that declares the semaphore type that the drivers use. 
+    The macro should be used within the device data structure.
+    It should not be used to declare the semaphore as a global variable. */
+#define SEM_VAR_DECLR                                                                    \
+                            StaticQueue_t hSemaphore;                                  
+                            
+/*! Memory required for semaphore in terms bytes. This size is used to compute 
+    the total memory required for the operation of the driver. FreeRtos does not 
+    require semaphore memory to be passed by application. But memory is required
+    to store the handle. */
+#define ADI_SEM_SIZE        (sizeof(StaticQueue_t))                            
+
+/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */
+
+                        /*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */
+#define SEM_CREATE(DEV, name, error)                                                     \
+                   do {                                                                  \
+                         xSemaphoreCreateBinaryStatic(&(DEV)->hSemaphore);                \
+                      } while (0)
+
+/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */
+#define SEM_DELETE(DEV, error)                                                           \
+                   do {                                                                  \
+                            vSemaphoreDelete (&(DEV)->hSemaphore);                        \
+                      } while (0)
+
+
+/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the device driver structure that contains the semaphore handle.*/
+#define SEM_PEND(DEV, error)                                                             \
+                 do {                                                                    \
+                       if(xSemaphoreTake (&(DEV)->hSemaphore, portMAX_DELAY) != pdTRUE)   \
+                       return((error));                                                  \
+                    } while (0)
+
+/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */
+/* Note that priority inversion is supported */
+#define SEM_POST(DEV)                                                                     \
+        do {                                                                              \
+          /* Assume that a higher priority task can be schedule in */                     \
+          BaseType_t xHigherPriorityTaskWoken = pdTRUE;                                   \
+          xSemaphoreGiveFromISR(&(DEV)->hSemaphore, &xHigherPriorityTaskWoken);           \
+        } while (0)                        
+
+/*! Defines a local variable where interrupt status register value is stored. 
+    This macro should be used within a function in which critical section
+    macros ADI_ENTER_CRITICAL_REGION and ADI_EXIT_CRITICAL_REGION are 
+    used. 
+    
+    @sa ADI_ENTER_CRITICAL_REGION()
+    @sa ADI_EXIT_CRITICAL_REGION()
+    */
+#define ADI_INT_STATUS_ALLOC()
+
+/*! Macro to enter critical section. To use this macro, the
+    interrupt status variable should be defined (ADI_INT_STATUS_ALLOC)
+    in the same scope. 
+    
+    @sa ADI_INT_STATUS_ALLOC()
+*/
+#define ADI_ENTER_CRITICAL_REGION()  vPortEnterCritical()
+
+/*! Macro to exit critical section.To use this macro, the
+    interrupt status variable should be defined (ADI_INT_STATUS_ALLOC)
+    in the same scope. 
+
+    @sa  ADI_INT_STATUS_ALLOC()   
+*/ 
+#define ADI_EXIT_CRITICAL_REGION() vPortExitCritical()
+
+/*! Code that uCOS requires to be run in the beginning of an interrupt handler. 
+    @sa ISR_EPILOG()
+*/
+#define ISR_PROLOG()            
+
+/*! Code that uCOS requires to be run in the end of an interrupt handler. 
+    @sa ISR_PROLOG()
+*/
+#define ISR_EPILOG()   portYIELD()         
+     
+#endif /* __STDC__  */
+
+#define PENDSV_HANDLER   xPortPendSVHandler
+#define SYSTICK_HANDLER  xPortSysTickHandler
+#define SVC_HANDLER      vPortSVCHandler
+
+
+#endif /* ADI_RTOS_MAP_FREERTOS_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map_noos.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map_noos.h
new file mode 100755
index 00000000000..e508f1ccf57
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map_noos.h
@@ -0,0 +1,180 @@
+/*!
+ *****************************************************************************
+ @file:    adi_rtos_map_noos.h
+ @brief:   No OS API mapping file.
+
+           This file maps the RTOS macros to No OS APIs
+
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+
+#ifndef ADI_RTOS_MAP_NOOS_H
+#define ADI_RTOS_MAP_NOOS_H
+
+/* If building a c file */
+#if defined(__STDC__)
+
+#include <stdint.h>
+#include <stddef.h>
+#include <drivers/pwr/adi_pwr.h>
+#include <adi_cyclecount.h>
+
+/*! Defines a local variable where interrupt status register value is stored.
+    This macro should be used within a function in which critical section
+    macros ADI_ENTER_CRITICAL_REGION and ADI_EXIT_CRITICAL_REGION are
+    used.
+
+    @sa ADI_ENTER_CRITICAL_REGION()
+    @sa ADI_EXIT_CRITICAL_REGION()
+    */
+#define ADI_INT_STATUS_ALLOC()      uint32_t IntStatus = 0u
+
+/*! Macro to enter critical section. To use this macro, the
+    interrupt status variable should be defined (ADI_INT_STATUS_ALLOC)
+    in the same scope.
+
+    @sa ADI_INT_STATUS_ALLOC()
+*/
+#define ADI_ENTER_CRITICAL_REGION()                                                \
+do {                                                                               \
+      IntStatus  = __get_PRIMASK();                                                \
+    __disable_irq();                                                               \
+} while (0)
+
+
+/*! Macro to exit critical section.To use this macro, the
+    interrupt status variable should be defined (ADI_INT_STATUS_ALLOC)
+    in the same scope.
+
+    @sa  ADI_INT_STATUS_ALLOC()
+*/
+#define ADI_EXIT_CRITICAL_REGION()                                                 \
+do {                                                                               \
+  __set_PRIMASK(IntStatus);                                                        \
+} while (0)
+
+
+/*! Memory required for semaphore in terms bytes. This size is used to compute
+    the total memory required for the operation of the driver. */
+#define ADI_SEM_SIZE        (sizeof(uint32_t))
+    
+/*! Code that uCOS requires to be run in the beginning of an interrupt handler.
+    @sa ISR_EPILOG()
+*/
+#if defined(ADI_CYCLECOUNT_ENABLED) && (ADI_CYCLECOUNT_ENABLED == 1u)
+#define  ISR_PROLOG() adi_cyclecount_start();
+#else
+#define  ISR_PROLOG()
+#endif
+
+
+/*! Code that uCOS requires to be run in the end of an interrupt handler.
+    @sa ISR_PROLOG()
+*/
+#if defined(ADI_CYCLECOUNT_ENABLED) && (ADI_CYCLECOUNT_ENABLED == 1u)
+#define  ISR_EPILOG() adi_cyclecount_stop();
+#else
+#define  ISR_EPILOG()
+#endif
+
+#if (ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT == 1)
+
+/*! Macro that declares the semaphore type that the drivers use.
+    The macro should be used within the device data structure.
+    It should not be used to declare the semaphore as a global variable. */
+#define SEM_VAR_DECLR         volatile uint32_t nLowPowerExitFlag;
+
+/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */
+#define SEM_CREATE(DEV, name, error) \
+    (DEV)->nLowPowerExitFlag = 0u
+    
+/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */
+#define SEM_DELETE(DEV, error) do { } while(0)
+
+/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the   device driver structure that contains the semaphore handle. */
+#define SEM_PEND(DEV, error)                                                                    \
+   do {                                                                                         \
+        ADI_PWR_RESULT eResult;                                                                 \
+        eResult = adi_pwr_EnterLowPowerMode(ADI_PWR_MODE_FLEXI, &(DEV)->nLowPowerExitFlag, 0u); \
+        if(eResult != ADI_PWR_SUCCESS) { return ((error)); }                                    \
+   } while(0)
+
+
+/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */
+#define SEM_POST(DEV)                                                              \
+   do {                                                                            \
+        adi_pwr_ExitLowPowerMode(&(DEV)->nLowPowerExitFlag);                       \
+   } while(0)
+
+
+#else /* ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT == 0 */
+
+/*! Macro that declares the semaphore type that the drivers use.
+    The macro should be used within the device data structure.
+    It should not be used to declare the semaphore as a global variable. */
+#define SEM_VAR_DECLR       volatile uint32_t nSemCount;
+
+/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */
+#define SEM_CREATE(DEV, name, error) \
+   (DEV)->nSemCount = 0
+    
+/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */
+#define SEM_DELETE(DEV, error)  do { } while(0)
+
+/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the   device driver structure that contains the semaphore handle. */
+#define SEM_PEND(DEV, error)                                                       \
+    while ((DEV)->nSemCount == 0u) {}                                              \
+    (DEV)->nSemCount--
+
+/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */
+#define SEM_POST(DEV) {                                                            \
+    (DEV)->nSemCount++;                                                            \
+}
+
+#endif /* ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT */
+
+#endif /* __STDC__ */
+
+#define PENDSV_HANDLER      PendSV_Handler
+#define SYSTICK_HANDLER     SysTick_Handler
+#define SVC_HANDLER         SVC_Handler
+
+
+#endif /* ADI_RTOS_MAP_NOOS_H */
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map_ucos_iii.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map_ucos_iii.h
new file mode 100755
index 00000000000..e055b7010fb
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map_ucos_iii.h
@@ -0,0 +1,167 @@
+/*!
+ *****************************************************************************
+ @file:    adi_rtos_map_ucos_iii.h
+ @brief:   uCOS-III RTOS API mapping file.
+
+           This file maps the RTOS macros to uCOS-III APIs
+           
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+
+#ifndef ADI_RTOS_MAP_UCOS_III_H
+#define ADI_RTOS_MAP_UCOS_III_H
+
+/* If building a c file */
+#if defined(__STDC__)
+
+#include <cpu.h>
+#include <os.h>
+#include <stdint.h>
+#include <stddef.h>
+
+/*! Macro that declares the semaphore type that the drivers use. 
+    The macro should be used within the device data structure.
+    It should not be used to declare the semaphore as a global variable. */
+#define SEM_VAR_DECLR                                                                           \
+                    OS_SEM Semaphore;                                  
+
+/*! Memory required for semaphore in terms bytes. This size is used to compute 
+    the total memory required for the operation of the driver. uCOS-III requires
+    semaphore memory to be passed by application. But there is no memory required
+    to store the handle. For every semaphore related call the same memory pointer 
+    that was used during create will be passed. */
+#define ADI_SEM_SIZE        (sizeof(OS_SEM))
+                                        
+/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */
+#define SEM_CREATE(DEV, name, error)                                                            \
+                   do {                                                                         \
+                         OS_ERR os_error;                                                       \
+                         OSSemCreate(&((DEV)->Semaphore), name ,0u, &os_error);                 \
+                         if(OS_ERR_NONE != os_error) {return((error));}                         \
+                      } while (0)
+
+/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */
+#define SEM_DELETE(DEV, error)                                                                  \
+                   do {                                                                         \
+                         OS_ERR os_error;                                                       \
+                         OSSemDel( &((DEV)->Semaphore), OS_OPT_DEL_NO_PEND, &os_error );        \
+                         if(OS_ERR_NONE != os_error) {return((error));}                         \
+                      } while (0)
+
+
+/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the device driver structure that contains the semaphore handle.*/
+#define SEM_PEND(DEV, error)                                                                    \
+        do {                                                                                    \
+              OS_ERR  os_error;                                                                 \
+              OSSemPend    (&((DEV)->Semaphore), 0u, OS_OPT_PEND_BLOCKING , NULL, &os_error);   \
+              if(OS_ERR_NONE != os_error) {return((error));}                                    \
+           } while (0)
+               
+/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */
+#define SEM_POST(DEV)                                                                           \
+        do {                                                                                    \
+          OS_ERR  os_error;                                                                     \
+          OSSemPost(&((DEV)->Semaphore), OS_OPT_POST_1, &os_error);                             \
+        } while (0)
+          
+
+/*! Defines a local variable where interrupt status register value is stored. 
+    This macro should be used within a function in which critical section
+    macros ADI_ENTER_CRITICAL_REGION and ADI_EXIT_CRITICAL_REGION are 
+    used. 
+    
+    @sa ADI_ENTER_CRITICAL_REGION()
+    @sa ADI_EXIT_CRITICAL_REGION()
+*/
+#define ADI_INT_STATUS_ALLOC()     CPU_SR_ALLOC()
+    
+/*! Macro to enter critical section. To use this macro, the
+    interrupt status variable should be defined (ADI_INT_STATUS_ALLOC)
+    in the same scope. 
+    
+    @sa ADI_INT_STATUS_ALLOC()
+*/
+#define ADI_ENTER_CRITICAL_REGION()  CPU_CRITICAL_ENTER()
+
+/*! Macro to exit critical section.To use this macro, the
+    interrupt status variable should be defined (ADI_INT_STATUS_ALLOC)
+    in the same scope. 
+
+    @sa  ADI_INT_STATUS_ALLOC()   
+*/ 
+#define ADI_EXIT_CRITICAL_REGION() CPU_CRITICAL_EXIT()
+
+
+/*! Code that uCOS requires to be run in the beginning of an interrupt handler. 
+    @sa ISR_EPILOG()
+*/
+#if defined(ADI_CYCLECOUNT_ENABLED) && (ADI_CYCLECOUNT_ENABLED == 1)
+#define ADI_RTOS_UCOS_III_CYCLECOUNT_START adi_cyclecount_start();
+#define ADI_RTOS_UCOS_III_CYCLECOUNT_STOP  adi_cyclecount_stop();
+#else
+#define ADI_RTOS_UCOS_III_CYCLECOUNT_START 
+#define ADI_RTOS_UCOS_III_CYCLECOUNT_STOP  
+#endif
+
+#define ISR_PROLOG()                                                                            \
+                            do {                                                                \
+                                    CPU_SR_ALLOC();                                             \
+                                    CPU_CRITICAL_ENTER();                                       \
+                                    OSIntEnter();                                               \
+                                    CPU_CRITICAL_EXIT();                                        \
+                                    ADI_RTOS_UCOS_III_CYCLECOUNT_START                          \
+                               } while (0);
+
+/*! Code that uCOS requires to be run in the end of an interrupt handler. 
+    @sa ISR_PROLOG()
+*/
+#define ISR_EPILOG()                                                                            \
+                            do {                                                                \
+                                   ADI_RTOS_UCOS_III_CYCLECOUNT_STOP                            \
+                                   OSIntExit();                                                 \
+                            } while (0);                                                        \
+
+#endif /* __STDC__ */
+
+#define PENDSV_HANDLER   OS_CPU_PendSVHandler
+#define SYSTICK_HANDLER  OS_CPU_SysTickHandler
+#define SVC_HANDLER      SVC_Handler
+          
+
+#endif /* ADI_RTOS_MAP_UCOS_III_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/spi/adi_spi.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/spi/adi_spi.c
new file mode 100755
index 00000000000..0bb53ac35a5
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/spi/adi_spi.c
@@ -0,0 +1,2017 @@
+/*! *****************************************************************************
+ * @file:    adi_spi.c
+ * @brief:   SPI  device  driver global file.
+ * @details: This a global file which includes a specific file based on the processor family.
+ *           This included file will be  containing  SPI device  driver functions.
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+/** @addtogroup SPI_Driver SPI Driver
+ *  @{
+ * @brief Serial Peripheral Interface (SPI) Driver
+ * @details The SPI driver manages all instances of the SPI peripheral.
+ * @note The application must include drivers/spi/adi_spi.h to use this driver.
+ * @note This driver requires the DMA driver.The application must include the DMA driver sources to avoid link errors.
+ * @note Also note that the SPI will be configured by default to operate in Master mode. 
+ * @note To configure the driver to operate in slave mode the static configuration file adi_spi_config.h must be modified. 
+ * @note Specifically, the macro ADI_SPIx_MASTER_MODE must be set to '0' to indicate that slave mode functionality is needed. 
+ * @note Since there are three SPI devices there are three macros, ADI_SPI0_MASTER_MODE, ADI_SPI1_MASTER_MODE and ADI_SPI2_MASTER_MODE to control the functionality of each SPI controller. 
+ * @note Each instance of the SPI operates independently from all other instances.
+ * @note
+ * @note When operating the SPI at high bit rates the application may need to modify the IRQ interrupt mode. The API adi_spi_SetIrqmode() can be used for this.
+ * @note At higher bit rates the ISR could mask a TX/RX interrupt. Specifically, it is possible that while servicing a TX/RX event another TX/RX event could occur. It is
+ * @note possible, therefore, that when the ISR clears the interrupt status it will not only be clearing the current TX event but the next TX/RX event as well. The result
+ * @note could that a final TX/RX event will not be processed. One way to work around this would be to set IRQMODE such that TX/RX events will occur only after N bytes
+ * @note are in the FIFO. This will only work for short bursts less than the size of the FIFO. For larger transfer DMA mode, which will not have any of these issues,  should be used.
+ * @note Finally, if interrupt mode is required at hight bit rates note that the SPI ISR has been designed with minimal cycle count as the highest priority. 
+ * @note The ISR could certainly be modified to re-examine the FIFO before existing at the cost of additional cycles.
+ */
+
+ /*! \cond PRIVATE */
+#include <adi_processor.h>
+/*! \endcond */
+
+#include <stdlib.h>  /* for 'NULL" definition */
+#include <string.h>
+
+#include <drivers/spi/adi_spi.h>
+#include <drivers/pwr/adi_pwr.h>
+#include <drivers/general/adi_drivers_general.h>
+#include <adi_callback.h>
+#include <rtos_map/adi_rtos_map.h>
+#include "adi_spi_config.h"
+#include <adi_cyclecount.h>
+
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
+*   This isn't a header as such.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+*
+* Pm088 (rule 17.4): pointer arithmetic should not be used.
+*   Relying on pointer arithmetic for buffer handling.
+*
+* Pm152: (MISRA C 2004 rule 17.4) array indexing shall only be applied to objects defined as an array type  
+*   Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors
+*
+* Pm151 (rule 17.4): array indexing shall only be applied to objects of array type
+* Pm123 (rule 18.5): there shall be no definition of objects in a header file
+*
+* Pm50: (MISRA C 2004 rule 14.3) a null statement shall only occur on a line by itself, and shall not have any other text on the same line
+*    Some Macros, such as ISR_PROLOGUE, may not have any expansion resulting in just the terminating ';'
+*
+*Pm140: (MISRA C 2004 rule 11.3) a cast should not be performed between a pointer type and an integral type
+*    MMR addresses are defined as simple constants. Accessing the MMR requires casting to a pointer type
+*
+* Pm031: (MISRA C 2004 rule 12.7)  bitwise operations shall not be performed on signed integer types 
+*    MMR macros are beyond the control of the driver.
+*
+*/
+#pragma diag_suppress=Pm050,Pm073,Pm088,Pm123,Pm143,Pm152,Pm140,Pm031
+
+#endif /* __ICCARM__ */
+
+#include "adi_spi_data.c"
+
+/*! \cond PRIVATE */
+
+/* handle checker for debug mode */
+#define ADI_SPI_VALIDATE_HANDLE(h) ((spi_device_info[0].hDevice != (h)) && (spi_device_info[1].hDevice != (h)) && (spi_device_info[2].hDevice != (h)))
+
+/*! \endcond */
+
+/*
+ * Local prototypes
+ */
+static void common_SPI_Int_Handler (ADI_SPI_DEV_DATA_TYPE* pDD);
+static void StartTransaction       (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr);
+static void TxDmaErrorCallback     (void *pCBParam, uint32_t Event, void *pArg);
+static void RxDmaErrorCallback     (void *pCBParam, uint32_t Event, void *pArg);
+
+/* ISR forward declarations */
+/*! \cond PRIVATE */
+void SPI0_Int_Handler(void);
+void SPI1_Int_Handler(void);
+void SPI2_Int_Handler(void);
+void DMA_SPI0_TX_Int_Handler(void);
+void DMA_SPI0_RX_Int_Handler(void);
+void DMA_SPI1_TX_Int_Handler(void);
+void DMA_SPI1_RX_Int_Handler(void);
+void DMA_SPIH_TX_Int_Handler(void);
+void DMA_SPIH_RX_Int_Handler(void);
+/*! \endcond */
+
+/*
+    //////////////////////////////////////////////////////////////////////////////
+    //////////////////////   API IMPLEMENTATIONS   ///////////////////////////////
+    //////////////////////////////////////////////////////////////////////////////
+*/
+
+/*!
+ * @brief  Initialize and allocate an SPI device for use in Master Mode.
+ *
+ * @param[in]   nDeviceNum   Zero-based device index designating which device to initialize.
+ *\n
+ * @param [in]  pDevMemory   Pointer to a buffer of size ADI_SPI_MEMORY_SIZE
+ *\n                         required by the driver for the operation of specified SPI device.
+ *
+ * @param [in]  nMemorySize  Size of the buffer to which "pMemory" points. 
+ *
+ * @param[out]  phDevice     The caller's device handle pointer for storing the initialized device instance data pointer.
+ *
+ * @return            Status
+ *                    - #ADI_SPI_INVALID_DEVICE_NUM [D]     Invalid device index.
+ *                    - #ADI_SPI_INVALID_PARAM [D]          Invalid parameter.
+ *                    - #ADI_SPI_SEMAPHORE_FAILED           Semaphore creation failed.
+ *                    - #ADI_SPI_DMA_REG_FAILED             Failed to register DMA callbacks with common DMA service.
+ *                    - #ADI_SPI_IN_USE                     SPI is already open and in use.
+ *                    - #ADI_SPI_SUCCESS                    Call completed successfully.
+ *
+* @note :  No other SPI APIs may be called until the device open function is called.
+ *\n       Initialize an SPI device using internal default configuration settings and allocate the
+ *\n       device for use.The returned device handle is required to be passed to all subsequent
+ *\n       calls to convey which device instance to operate on.
+ *\n       The contents of phDevice will be set to NULL upon failure. Device is opened in Master mode.
+ *\n
+ * @sa      adi_spi_SetMasterMode()
+ * @sa      adi_spi_Close().
+ */
+ADI_SPI_RESULT adi_spi_Open(uint32_t nDeviceNum,
+                            void *pDevMemory,
+                            uint32_t nMemorySize,
+                            ADI_SPI_HANDLE* const phDevice)
+{
+
+#ifdef ADI_DEBUG
+
+    if (nDeviceNum >= ADI_SPI_NUM_INSTANCES)
+    {
+        return ADI_SPI_INVALID_DEVICE_NUM;
+    }
+
+    if (nMemorySize != sizeof(struct __ADI_SPI_DEV_DATA_TYPE))
+    {
+        return ADI_SPI_INVALID_PARAM;
+    }
+    
+    if( spi_device_info[nDeviceNum].hDevice != NULL )
+    {
+        return ADI_SPI_IN_USE;
+    }
+
+#endif
+
+    ADI_SPI_HANDLE hDevice = pDevMemory;
+    
+    /* 
+     * Link the two data structures together.
+     *   
+     *         ADI_SPI_DEVICE_INFO  <==>   ADI_SPI_HANDLE
+     *
+     * Clear the ADI_SPI_HANDLE memory. This also sets all bool 
+     * structure members to false so we do not need to waste cycles 
+     * setting these explicitly (e.g. hDevice->bDMA = false)
+     *
+     * Other fields, such as callback related fields, are also zeroed
+     * and therefore properly initialized.
+     */
+    
+    memset(pDevMemory,0,nMemorySize);
+    hDevice->pDevInfo =  &spi_device_info[nDeviceNum];
+	spi_device_info[nDeviceNum].hDevice = (ADI_SPI_DEV_DATA_TYPE *)pDevMemory;
+
+
+    /* 
+     * Although the ADI_SPI_DEVICE_INFO struct has the address of the SPI registers
+     * for this instance, copying it to the ADI_SPI_HANDLE struct will minimize
+     * the runtime footprint and cycle count when accessing the SPI registers
+     */
+    hDevice->pSpi = spi_device_info[nDeviceNum].pSpiRegs;
+
+    SEM_CREATE(hDevice, "SPI_SEM", ADI_SPI_SEMAPHORE_FAILED);
+
+   /* Static Configuration */
+    /* Initialize the device based on the given configuration parameters */
+    ADI_SPI_CFG_TYPE const* pSPICfg = &gSPICfg[nDeviceNum];
+    hDevice->pSpi->CTL = pSPICfg->SPI_CTL;
+    hDevice->pSpi->DIV = pSPICfg->SPI_DIV;
+
+    /* write the device data pointer into the caller's handle */
+    *phDevice = hDevice;
+    hDevice->pSpi->CTL |= BITM_SPI_CTL_SPIEN;
+    
+    /* Make sure the DMA controller and its SRAM based descriptors are initialized */
+    adi_dma_Init();
+
+    /* Setup the DMA TX callback */
+    if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback((DMA_CHANn_TypeDef) hDevice->pDevInfo->dmaTxChannelNumber, TxDmaErrorCallback, (void *) hDevice)) 
+    {
+         return  ADI_SPI_DMA_REG_FAILED;
+    }
+
+    /* Setup the DMA RX callback */
+    if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback((DMA_CHANn_TypeDef) hDevice->pDevInfo->dmaRxChannelNumber, RxDmaErrorCallback, (void *) hDevice)) 
+    {
+         return  ADI_SPI_DMA_REG_FAILED;
+    }
+
+    return ADI_SPI_SUCCESS;
+}
+
+
+/*!
+ * @brief  Uninitialize and deallocate an SPI device.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_spi_Open().
+ *
+ * @return      Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]       Invalid device handle parameter.
+ *                - #ADI_SPI_SUCCESS                  Call completed successfully.
+ *
+ * Uninitialize and release an allocated SPI device,and memory associated with it for other use.
+ *
+ * @sa  adi_spi_Open().
+ */
+ADI_SPI_RESULT adi_spi_Close (ADI_SPI_HANDLE const hDevice)
+{
+
+    ADI_SPI_RESULT result = ADI_SPI_SUCCESS;
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+
+#endif
+    
+    
+    /* disable Interrupt    */
+    NVIC_DisableIRQ(hDevice->pDevInfo->eIRQn);
+
+    
+     /* destroy semaphore */
+    SEM_DELETE((ADI_SPI_HANDLE) hDevice,ADI_SPI_SEMAPHORE_FAILED);
+
+    /* invalidate initialization state */
+    hDevice->pDevInfo->hDevice  = NULL;
+    return result;
+}
+
+
+/*!
+ * @brief  Register or unregister the callback.
+ *
+ * @param [in]   hDevice        Device handle obtained from adi_spi_Open().
+ * @param [in]   pfCallback     Pointer to the callback function. Can be passed as NULL to unregister the
+ *\n                            previously registered callback.
+ * @param [in]   pCBParam       Callback parameter which will be passed back to the application when the
+ *\n                            callback is called.
+ *
+ * @return      Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]  Invalid device handle parameter.
+ *                - #ADI_SPI_SUCCESS                    Call completed successfully.
+ */
+ADI_SPI_RESULT adi_spi_RegisterCallback (ADI_SPI_HANDLE const hDevice,  ADI_CALLBACK const pfCallback, void *const pCBParam )
+{
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice)) {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+
+#endif
+    /* Save the application provided callback and callback parameters */
+    hDevice->pfCallback = pfCallback;
+    hDevice->pCBParam   = pCBParam;
+
+    return ADI_SPI_SUCCESS;
+}
+
+/*!
+ * @brief  Set the IRQ mode.
+ *
+ * @param[in]    hDevice      Device handle obtained from adi_spi_Open().
+ * @param[in]    nMode        IRQ mode value to set.
+*                - true     Set continuous transfer mode.
+*                - false    Clear continuous transfer mode.
+ *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *                - #ADI_SPI_SUCCESS                        Call completed successfully.
+ *
+ * These bits configure when the Tx/Rx interrupts occur in a transfer. 
+ * For DMA Rxtransfer, these bits should be 0. 
+ * Valid values are 0-7
+ *      Tx interrupt occurs when (nMode+1) byte(s) has been transferred.
+ *      Rx interrupt occurs when (nMode+1) or more bytes have been received into the FIFO.
+ *
+ *  @note The application will have to carefully manage IRQMODE relative to a transaction's buffer size.
+ *  @note Specifically, the application must ensure that the last byte causes an interrupt else the 
+ *  @note transaction will not terminate. As explained in the SPI driver overview, this functionality
+ *  @note is typically needed when operating in interrupt mode with a high SPI bit rate (typically issues
+ *  @note are seen at SPI clock rates of 4MHz or greater). The max clock rate will vary depending on the application.
+ *  @note The max clock rate is a function of the SPI ISR cycle count plus any other delay that might be caused
+ *  @note by other parts of the system. Finally, please note that while sustaining interrupt mode SPI transaction
+ *  @note at high bit rates will work buffers that are the size of the SPI FIFO or less, transactions that are 
+ *  @note larger that the size of the FIFO may run into issues associated with masked/lost interrupts. If this
+ *  @note does prove to be an issue for an applicatoon then the SPI ISR could be modified to examine the FIFO
+ *  @note status on a continuous basis in the ISR (as opposed to examining the FIFO status just once at the start
+ *  @note of the ISR). However, adding this functionality to the ISR will increase the ISR cycle count and footprint. 
+ *
+ */
+ADI_SPI_RESULT adi_spi_SetIrqmode (ADI_SPI_CONST_HANDLE const hDevice, const uint8_t nMode)
+{
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice)) {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+    
+    if (nMode > ADI_SPI_IRQ_PARAM) {
+        return ADI_SPI_INVALID_PARAM;
+    }
+
+#endif
+    
+    uint16_t ien = hDevice->pSpi->IEN;
+    ien = ien & (uint16_t)~BITM_SPI_IEN_IRQMODE;
+    ien = ien | (nMode & BITM_SPI_IEN_IRQMODE);
+    hDevice->pSpi->IEN = ien;
+
+    return ADI_SPI_SUCCESS;
+}
+
+
+/*!
+ * @brief  Set the continuous transfer mode.
+ *
+ * @param[in]    hDevice      Device handle obtained from adi_spi_Open().
+ * @param[in]    bFlag        Flag to manage SPI continuous transfer mode.
+*                - true     Set continuous transfer mode.
+*                - false    Clear continuous transfer mode.
+ *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *                - #ADI_SPI_SUCCESS                        Call completed successfully.
+ *
+ * Setting this mode causes the SPI controller to drive the Chip Select signal continuously until the transaction
+ * is complete.  Clearing it causes Chip Select to cycle between bytes.
+ *
+ *
+ */
+ADI_SPI_RESULT adi_spi_SetContinuousMode (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag)
+{
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice)) {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+
+#endif
+
+    if (true == bFlag) {
+        hDevice->pSpi->CTL |= (BITM_SPI_CTL_CON);
+    } else {
+        hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CON;
+    }
+
+    return ADI_SPI_SUCCESS;
+}
+
+/*!
+ * @brief  Set the internal loopback mode.
+ *
+ * @param[in]    hDevice      Device handle obtained from adi_spi_Open().
+ * @param[in]    bFlag        Flag to manage internal SPI loopback mode.
+ *                - true     Set internal loopback mode.
+ *                - false    Clear internal loopback mode.
+ *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *                - #ADI_SPI_SUCCESS                        Call completed successfully.
+ *
+ * Set or clear the internal SPI loopback mode.  Primarily used for testing.
+ *
+ */
+ADI_SPI_RESULT adi_spi_SetLoopback (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag)
+{
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+
+#endif
+
+    if (true == bFlag) {
+        hDevice->pSpi->CTL |= (BITM_SPI_CTL_LOOPBACK);
+    } else {
+        hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_LOOPBACK;
+    }
+
+    return ADI_SPI_SUCCESS;
+}
+
+/*!
+ * @brief  Set SPI Master-Mode operation.
+ *
+ * @param[in]    hDevice      Device handle obtained from adi_spi_Open().
+ * @param[in]    bFlag        Flag to select either Master-Mode or Slave-Mode operation.
+ *\n                - true     Enable Master-Mode. Default.
+ *\n                - false    Enable Slave-Mode.
+ *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *                - #ADI_SPI_SUCCESS                        Call completed successfully.
+ *
+ * Controls SPI Master/Slave mode of operation, set for Master-Mode, clear for Slave-Mode.
+ *
+ */
+ADI_SPI_RESULT adi_spi_SetMasterMode (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag)
+{
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+
+#endif
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    if (true == bFlag) {        /* hardware default */
+        hDevice->pSpi->CTL |= (ADI_SPI_MASTERCON_INITIALIZER);
+   } else {
+        hDevice->pSpi->CNT = 0u;
+        hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_MASEN;
+        hDevice->pSpi->CTL |= (ADI_SPI_SLAVECON_INITIALIZER);
+    }
+    ADI_EXIT_CRITICAL_REGION();
+    return ADI_SPI_SUCCESS;
+}
+
+
+/*!
+ * @brief  Set the SPI receive FIFO overflow mode.
+ *
+ * @param[in]    hDevice      Device handle obtained from adi_spi_Open().
+ * @param[in]    bFlag        Flag to manage receive FIFO overflow behaviour.
+ *\n              - true     Discard old data on receive FIFO overflow.
+ *\n              - false    Discard new data on receive FIFO overflow.
+ *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *                - #ADI_SPI_SUCCESS                        Call completed successfully.
+ *
+ * Controls what to do with excess incoming data when the receive FIFO becomes full.
+ * Either the new data or the old data is discarded.  Set the receive FIFO overflow mode
+ * to replace data in the RX register (top of receive FIFO) with the incoming new data.
+ * Clear it to discard incoming new data and preserve old unread data.
+
+ *
+ */
+ADI_SPI_RESULT adi_spi_SetReceiveOverflow (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag)
+{
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+
+#endif
+
+    if (true == bFlag) {
+        hDevice->pSpi->CTL |= (BITM_SPI_CTL_RXOF);
+    } else {
+        hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_RXOF;
+    }
+
+    return ADI_SPI_SUCCESS;
+}
+
+
+/*!
+ * @brief  Set the SPI transmit FIFO underflow mode.
+ *
+ * @param[in]    hDevice      Device handle obtained from adi_spi_Open().
+ * @param[in]    bFlag        Flag to manage transmit FIFO underflow behaviour.
+ *\n               - true     Send zeroes on transmit FIFO underflow.
+ *\n               - false    Resend last data on transmit FIFO underflow.
+ *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *                - #ADI_SPI_SUCCESS                        Call completed successfully.
+ *
+ *\n  Controls what to transmit when lacking valid data because the transmit FIFO is empty.
+ *\n  Either zeros or the last valid data are transmitted.  Set transmit FIFO underflow mode to send zeros.
+ *\n Clear it to resend the last transmitted data.
+ *
+ */
+ADI_SPI_RESULT adi_spi_SetTransmitUnderflow (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag)
+{
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+#endif
+
+    if (true == bFlag) {
+        hDevice->pSpi->CTL |= (BITM_SPI_CTL_ZEN);
+    } else {
+        hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_ZEN;
+    }
+
+    return ADI_SPI_SUCCESS;
+}
+
+
+
+
+
+
+/*!
+ * @brief  Set the SPI serial clock frequency.
+ *
+ * @param[in]    hDevice      Device handle obtained from adi_spi_Open()
+ * @param[in]    Hertz        Target frequency (in Hz) for SPI bitrate.
+ *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *                - #ADI_SPI_INVALID_PARAM              Specified frequency is out of range.
+ *                - #ADI_SPI_BAD_SYS_CLOCK              Unable to obtain PCLK which is needed to calculate the new bit rate.
+ *                - #ADI_SPI_SUCCESS                    Call completed successfully.
+ *
+ * Compute and set the internal SPI clock rate divider register to produce
+ *\n the desired serial clock frequency.  Resulting frequency is subject to arithmetic rounding errors.
+ *\n Use #adi_spi_GetBitrate() to obtain the exact frequency produced, including rounding errors.
+ *
+ * @sa        adi_spi_GetBitrate().
+ */
+ADI_SPI_RESULT adi_spi_SetBitrate (ADI_SPI_CONST_HANDLE const hDevice, const uint32_t Hertz)
+{
+    uint32_t incoming_clock;
+    uint16_t Div;
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+#endif
+
+    if( adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &incoming_clock) != ADI_PWR_SUCCESS)
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+
+    /* requested rate needs to be 2x or less than incoming clock */
+    if ((2U * Hertz) > incoming_clock)
+    {
+        return ADI_SPI_BAD_SYS_CLOCK;
+    }
+
+     /* compute the SPI divider value */
+     Div = (uint16_t) ((incoming_clock / Hertz) >> 1U) - 1U;  /* '>>1' is really a divide by 2 */
+
+    /* range check that computed divider fits */
+    if (Div != (Div & BITM_SPI_DIV_VALUE))
+    {
+        return ADI_SPI_INVALID_PARAM;
+    }
+
+    /* store it in core */
+    hDevice->pSpi->DIV = Div;
+
+    return ADI_SPI_SUCCESS;
+}
+
+
+/*!
+ * @brief  Get the SPI serial clock frequency.
+ *
+ * @param[in]    hDevice     Device handle obtained from adi_spi_Open()
+ * \n
+ * @param[out]    pnBitrate   Pointer to the location where Bitrate need to be written.
+ *
+ * @return
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *                - #ADI_SPI_SUCCESS                        Call completed successfully.
+ *
+ * Get the current serial clock frequency.  The returned value is exact but
+ *\n may not exactly match the value set with #adi_spi_SetBitrate() due to
+ *\n computational round-off errors resulting from fixed register size and
+ *\n finite-precision arithmetic.
+ *
+ * @sa        adi_spi_SetBitrate().
+ */
+ADI_SPI_RESULT adi_spi_GetBitrate (ADI_SPI_CONST_HANDLE const hDevice, uint32_t* const pnBitrate)
+{
+    uint32_t incoming_clock;
+    ADI_PWR_RESULT ePwrResult;
+    uint32_t Div;
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+#endif
+    Div = hDevice->pSpi->DIV;  /* assumes this is always a right-justified value */
+
+    ePwrResult = adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &incoming_clock);
+    if(ePwrResult != ADI_PWR_SUCCESS)
+    {
+        *pnBitrate= 0u;
+         return(ADI_SPI_FAILURE);
+    }
+    *pnBitrate= (incoming_clock / (Div + 1U)) >> 1U;  /* '>>1' is divide by 2 */
+     return(ADI_SPI_SUCCESS);
+
+}
+
+/*!
+ * @brief  Set the clock polarity.
+ *
+ * @param[in]    hDevice      Device handle obtained from adi_spi_Open()
+ * @param[in]    bFlag        Flag to manage the idle state of the serial data clock between samples.
+ *\n               - true     Clock is idled high.
+ *\n               - false    Clock is idled low.
+ *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *                - #ADI_SPI_ERR_NOT_INITIALIZED [D]        Device has not been previously configured for use.
+ *                - #ADI_SPI_SUCCESS                        Call completed successfully.
+ *
+ * Sets the SPI clock polarity control bit (CPOL).  Used in conjunction with clock phase (CPHA) to program
+ *\n the exact timing of serial data capture and transmit.  Both clock phase and polarity must be considered in
+ *\n selecting the data transfer mode best suited to the Master/Slave device pair, typically dependant on the
+ *\n manufacturer and timing requirements of the external SPI device.
+ *
+ *\n Both Master and Slave devices must use the same settings for clock phase and polarity.
+ *
+ *\n If the phase of the clock is zero (CPHA=0), receive data are latched on the rising-clock-edge with
+ *\n CPOL=0 (idle-low) polarity, and on the falling-clock-edge with CPOL=1 (idle high) ploarity.
+ *
+ *\n If CPHA=1, the effective clock edges are reversed; CPOL=0 latches receive data on the falling-clock-edge
+ *\n and CPOL=1 latches receive data on the rising-clock-edge.
+ *
+ *\n Data are transmitted on the opposite clock edge as the receive, i.e., receive and transmit are out of phase.
+ *
+ * @sa        adi_spi_SetClockPhase().
+ */
+ADI_SPI_RESULT adi_spi_SetClockPolarity (ADI_SPI_HANDLE const hDevice, const bool bFlag)
+{
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+#endif
+
+    if (true == bFlag) {
+        hDevice->pSpi->CTL |= (BITM_SPI_CTL_CPOL);
+    } else {
+        hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CPOL;
+    }
+
+    return ADI_SPI_SUCCESS;
+}
+
+/*!
+ * @brief  Set the chip select.
+ *
+ * @param[in]    hDevice       Device handle obtained from adi_spi_Open().
+ * @param[in]    eChipSelect   An enum value representing the requested Chip Select.
+ *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *                - #ADI_SPI_SUCCESS                        Call completed successfully.
+ *
+ * Sets the desired chip select to use for activating an external slave device.
+ *
+ * @note      Chip select \a ADI_SPI0_CSn is reserved for SPI device 0 (SPI0) internal chip select line
+ *            dedicated for communications with the UHF device.
+ *
+ */
+ADI_SPI_RESULT adi_spi_SetChipSelect (ADI_SPI_HANDLE const hDevice, const ADI_SPI_CHIP_SELECT eChipSelect)
+{
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+#endif
+
+    hDevice->ChipSelect = eChipSelect;
+
+    return ADI_SPI_SUCCESS;
+}
+
+/*!
+ * @brief  Set the clock phase.
+ *
+ * @param[in]    hDevice      Device handle obtained from adi_spi_Open().
+ * @param[in]    bFlag        Flag to manage the phase of the serial data clock.
+ *\n                - true     Sample data on trailing-edge of each serial bit.
+ *\n                - false    Sample data on leading-edge of each serial bit.
+ *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *                - #ADI_SPI_ERR_NOT_INITIALIZED [D]        Device has not been previously configured for use.
+ *                - #ADI_SPI_SUCCESS                        Call completed successfully.
+ *
+ *\n Sets the SPI clock polarity phase bit (CPHA).  Used in conjunction with clock polarity (CPOL) to program
+ *\n the exact timing of serial data capture and transmit.  Both clock phase and polarity must be considered in
+ *\n selecting the data transfer mode best suited to the Master/Slave device pair, typically dependant on the
+ *\n manufacturer and timing requirements of the external SPI device.
+ *
+ *\n Both Master and Slave devices must use the same settings for clock phase and polarity.
+ *
+ *\n If the phase of the clock is zero (CPHA=0), receive data are latched on the rising-clock-edge with
+ *\n CPOL=0 (idle-low) polarity, and on the falling-clock-edge with CPOL=1 (idle high) ploarity.
+ *
+ *\n If CPHA=1, the effective clock edges are reversed; CPOL=0 latches receive data on the falling-clock-edge
+ *\n and CPOL=1 latches receive data on the rising-clock-edge.
+ *
+ *\n Data are transmitted on the opposite clock edge as the receive, i.e., receive and transmit are out of phase.
+ *
+ * @sa        adi_spi_SetClockPolarity().
+ */
+ADI_SPI_RESULT adi_spi_SetClockPhase (ADI_SPI_HANDLE const hDevice, const bool bFlag)
+{
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+#endif
+
+    if (true == bFlag) {
+        hDevice->pSpi->CTL |= (BITM_SPI_CTL_CPHA);
+    } else {
+        hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CPHA;
+    }
+
+    return ADI_SPI_SUCCESS;
+}
+
+/*!
+ * @brief  Submit data buffers for SPI Master-Mode transaction in "Blocking mode".This function
+ *\n          returns only after the data transfer is complete
+ *
+ * @param[in]     hDevice     Device handle obtained from adi_spi_Open().
+ * @param[in]     pXfr        Pointer to transfer data struct #ADI_SPI_TRANSCEIVER.
+  *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]        Invalid device handle parameter.
+ *                - #ADI_SPI_BUFFER_NOT_SUBMITTED [D]  Failed to submit the buffer.
+ *                - #ADI_SPI_INVALID_POINTER [D]       Invalid data pointer detected (NULL).
+ *                - #ADI_SPI_INVALID_PARAM [D]         Invalid size parameter detected (0).
+ *                - #ADI_SPI_SUCCESS                   Call completed successfully.
+ *
+ *\n
+ *\n Request a non-blocking mode transmit and receive of multiple data bytes
+ *\n over the SPI serial channel.  
+ *\n Buffer allocations are made by the calling code (the application).
+ *\n
+ *\n The transmit buffer is sent and the receive buffer is written according
+ *\n to the size and increment information contained by the \a pXft transfer
+ *\n data structure parameter.
+ *\n
+ *\n
+ * @sa adi_spi_MasterSubmitBuffer().
+ * @sa ADI_SPI_TRANSCEIVER
+ */
+ADI_SPI_RESULT adi_spi_MasterReadWrite (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr)
+{
+    ADI_SPI_RESULT eResult;
+    hDevice->bBlockingMode = true;
+    eResult = adi_spi_MasterSubmitBuffer(hDevice,pXfr);
+    hDevice->bBlockingMode = false;
+    if( (eResult == ADI_SPI_SUCCESS) && (hDevice->HWErrors != 0u))
+    {
+      eResult = ADI_SPI_HW_ERROR_OCCURRED;
+    }
+    return(eResult);
+}
+
+/*!
+ * @brief  Submit data buffers for SPI Master-Mode transaction.
+ *
+ * @param[in]     hDevice     Device handle obtained from adi_spi_Open().
+ * @param[in]     pXfr        Pointer to transfer data struct.
+  *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]        Invalid device handle parameter.
+ *                - #ADI_SPI_IN_USE [D]    DMA transaction already under way.
+ *                - #ADI_SPI_INVALID_POINTER [D]     Invalid data pointer detected (NULL).
+ *                - #ADI_SPI_INVALID_PARAM [D]    Invalid size parameter detected (0).
+ *                - #ADI_SPI_SUCCESS                       Call completed successfully.
+ *
+ *\n Request a blocking mode transmit and receive of multiple data bytes
+ *\n over the SPI serial channel.  
+ *\n Buffer allocations are made by the calling code (the application).
+ *\n
+ *\n The transmit buffer is sent and the receive buffer is written according
+ *\n to the size and increment information contained by the \a pXft transfer
+ *\n data structure parameter.
+ *
+ *
+ * @sa adi_spi_MasterReadWrite().
+ * @sa adi_spi_isBufferAvailable()
+ * @sa ADI_SPI_TRANSCEIVER
+ */
+
+ADI_SPI_RESULT adi_spi_MasterSubmitBuffer (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr)
+{
+    ADI_SPI_RESULT result = ADI_SPI_SUCCESS;
+    volatile uint16_t nStatus;
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+
+    if ((NULL == pXfr->pTransmitter) && (NULL == pXfr->pReceiver))
+    {
+        return ADI_SPI_INVALID_POINTER;
+    }
+    
+    if( (pXfr->bRD_CTL == true) && (pXfr->TransmitterBytes > 16u))
+    {
+      return ADI_SPI_INVALID_PARAM;
+    }
+
+#endif /* ADI_DEBUG */
+
+    /* Initialize the transaction. 'hDevice' must hold the transaction values as pXfr is owned by the application */
+    hDevice->pTxBuffer    = pXfr->pTransmitter;
+    hDevice->pRxBuffer    = pXfr->pReceiver;
+    hDevice->TxRemaining  = pXfr->TransmitterBytes;
+    hDevice->RxRemaining  = pXfr->ReceiverBytes;
+    hDevice->TxIncrement  = (uint8_t)pXfr->nTxIncrement;
+    hDevice->RxIncrement  = (uint8_t)pXfr->nRxIncrement;
+    hDevice->bDmaMode     = pXfr->bDMA;
+    hDevice->bRdCtlMode   = pXfr->bRD_CTL;
+    hDevice->bTransferComplete   = false;
+    hDevice->HWErrors            = ADI_SPI_HW_ERROR_NONE;
+
+    
+    /* 
+     *
+     * TIM
+     *   If set:   initiate transfer with write to SPI_TX register
+     *   If clear:  initiate transfer with a read from SPI_RX register
+     *
+     * RFLUSH
+     *   Clear this bit to ensure that incoming data is ignored
+     *
+     * TFLUSH
+     *   Clear this not to ensure that transmitted data is not a zero (if SPI_CTL.ZEN is set) or last transmitted byte
+     *
+     */
+    
+
+    hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_TIM | BITM_SPI_CTL_RFLUSH | BITM_SPI_CTL_TFLUSH);
+
+    /*
+     * If in DMA mode then make sure XFRDONE interrupt is not set. DMA mode will generate three interrupts
+     *   TX DMA
+     *   RX DMA
+     *   XFRDONE
+     *
+     * There is a race condition between XFRDONE and DMA interrupts. They are on different clocks.
+     * 
+     * SPI XfrDone is counted on SPI clock (SCL) edge, which is a fixed timing related to SPI bit protocol. 
+     * But the DMA works upon system clock (HCLK) and it could finish on various timing upon SCL/HCLK ratio.
+     * And bus bandwidth (e.g., DMA hold off until processor frees up the bus). So SPI RX DMA done interrupt 
+     * could be issued earlier or later than SPI XferDone interrupt.
+     *
+     */
+    if( hDevice->bDmaMode==true ) {
+      /* The race condition has been between RX and XFRDONE. If there are no bytes to receive then */
+      /* do not clear XFRDONE                                                                      */
+      if( hDevice->RxRemaining != 0u) {
+        hDevice->pSpi->IEN &= (uint16_t)~(BITM_SPI_IEN_XFRDONE);
+      } else {
+        hDevice->pSpi->IEN |= (BITM_SPI_IEN_XFRDONE);
+      }
+      
+    } else {
+      
+      /* In interrupt mode always enable XFRDONE */
+      uint16_t activeInterrupts = BITM_SPI_IEN_XFRDONE;
+      /* Enable underflow on;y if sending bytes */
+      if( hDevice->TxRemaining ) {
+        activeInterrupts |= BITM_SPI_IEN_TXUNDR;
+      }
+      /* Enable overflow only if receiving bytes */
+      if( hDevice->RxRemaining ) {
+        activeInterrupts |= BITM_SPI_IEN_RXOVR;
+      }
+      
+      hDevice->pSpi->IEN |= activeInterrupts;
+      
+      /* 
+       * In interrupt mode, when there is nothing to receive, need to initiate a transaction
+       * on an TX write only. Initiating on an RX read will start the transaction, but just for
+       * a single byte (and we're not sure why this is true)
+       */
+      
+      if( hDevice->RxRemaining == 0u) {
+        hDevice->pSpi->CTL |= ( BITM_SPI_CTL_TIM ); 
+      }
+        
+    }
+
+
+    /* STAT bits are cleared by writing a '1' to them. Clear any residual status*/
+    nStatus = hDevice->pSpi->STAT;
+    hDevice->pSpi->STAT = nStatus;
+
+    /* Make sure we are in master mode */
+    hDevice->pSpi->CTL |= ( BITM_SPI_CTL_MASEN);
+
+    /* Set ChipSelect */
+    hDevice->pSpi->CS_CTL  = hDevice->ChipSelect;
+  
+    StartTransaction(hDevice, pXfr);
+    
+    
+    /* block if required  */
+    if (hDevice->bBlockingMode == true)
+    {
+	SEM_PEND(hDevice,ADI_SPI_PEND_FAILED);
+    }
+    
+    return result;
+}
+
+/*********************************************************************************************************/
+/*                                                                                                       */
+/*                        SPI DRIVER Master Mode transaction start                                       */
+/*                                                                                                       */
+/*********************************************************************************************************/
+
+static void StartTransaction(ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr)
+{ 
+    /* Transaction completion is determined by the number of bytes to be received */
+    uint16_t nCount;
+    
+    /* Work around SPI anomaly */
+    if( (hDevice->bDmaMode == true) && (hDevice->bRdCtlMode == true) && (pXfr->ReceiverBytes == 1))
+    {
+    	/* Switch to PIO mode if the transaction is setup for a DMA transfer in RD_CTL mode with an RX count of 1 */
+    	hDevice->bDmaMode = false;
+    }
+    /* Effectively flush the FIFOs before the start of the next transaction */
+    hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH);
+    hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH);
+
+    /* Disable any prior notion of DMA */    
+    hDevice->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
+
+   
+    /*
+     * If the transaction is DMA based then set up the DMA descriptors for this transaction
+     */
+
+    uint16_t dmaFlags = 0u;
+    
+    if( hDevice->bDmaMode == true) 
+    {
+      dmaFlags = BITM_SPI_DMA_EN;
+
+      uint16_t sz = pXfr->TransmitterBytes;
+      if( sz )
+      {
+        uint16_t TxChanNum = hDevice->pDevInfo->dmaTxChannelNumber;
+    
+        /* Enable the interrupt for the given DMA */
+        NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaTxIrqNumber));
+
+        /* Disables source address decrement for TX channel */
+        pADI_DMA0->SRCADDR_CLR = 1U << TxChanNum;
+      
+        /* Enable the channel */
+        pADI_DMA0->EN_SET = 1U << TxChanNum;
+          
+        /* Enables SPI peripheral to generate DMA requests. */
+        pADI_DMA0->RMSK_CLR = 1U << TxChanNum;
+
+        /* Set the primary as the current DMA descriptor */
+        pADI_DMA0->ALT_CLR = 1U << TxChanNum;
+     
+        /* fill in the DMA RAM descriptors */
+        if( (sz & 1U) != 0u )
+        {
+          /* DMA is performed on 16-bit data. Make sure the DMA engine is properly aligned to even counts */
+          /* The SPI_CNT register will hold the "real" transfer count                                     */
+          sz++;
+        }
+        
+        pPrimaryCCD[TxChanNum].DMASRCEND =   (uint32_t)(pXfr->pTransmitter + (sz - 2U));
+              
+        pPrimaryCCD[TxChanNum].DMADSTEND =   (uint32_t)&hDevice->pSpi->TX;
+
+        pPrimaryCCD[TxChanNum].DMACDC = ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) |
+                              (ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_SRC_INC) |
+                              (ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) |
+                              ((sz/2U -1U)<< DMA_BITP_CTL_N_MINUS_1) |
+                              (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
+      
+        dmaFlags |= (BITM_SPI_DMA_TXEN);
+      }
+
+      sz = pXfr->ReceiverBytes;
+      if( sz )
+      {
+        
+        uint16_t RxChanNum = hDevice->pDevInfo->dmaRxChannelNumber;
+        NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaRxIrqNumber));
+
+        /* Disables destination address decrement for RX channel */
+        pADI_DMA0->DSTADDR_CLR = 1U << RxChanNum;
+        
+        /* Enable the channel */
+        pADI_DMA0->EN_SET = 1U << RxChanNum;
+        
+        /* Enables SPI peripheral to generate DMA requests. */
+        pADI_DMA0->RMSK_CLR = 1U << RxChanNum;
+
+        /* Set the primary as the current DMA descriptor */
+        pADI_DMA0->ALT_CLR = 1U << RxChanNum;
+        
+        if( (sz & 1U) != 0u )
+        {
+          /* DMA is performed on 16-bit data. Make sure the DMA engine is properly aligned to even counts */
+          /* The SPI_CNT register will hold the "real" transfer count                                     */
+          sz++;
+        }
+        
+        pPrimaryCCD[RxChanNum].DMASRCEND =   (uint32_t)&hDevice->pSpi->RX;
+              
+        pPrimaryCCD[RxChanNum].DMADSTEND =   (uint32_t)(pXfr->pReceiver + (sz - 2U));
+
+        pPrimaryCCD[RxChanNum].DMACDC = (ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_DST_INC) |
+                              (ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) |
+                              (ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) |
+                              ((sz/2U -1U) << DMA_BITP_CTL_N_MINUS_1) |
+                              (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
+        
+        dmaFlags |= (BITM_SPI_DMA_RXEN );
+
+      }
+    }
+
+    /*
+     * SPI CNT register
+     *     Non Read Mode:  Size of the entire transactions
+     *     Read Mode: Size of the RX transaction 
+     *
+     * RD_CTL.SZ
+     *     Read Mode: Size of the TX transaction
+     */
+    
+    hDevice->pSpi->RD_CTL = 0u;
+    if( hDevice->bRdCtlMode)
+    {
+      /* "Half Duplex Mode" */
+      
+      /* The number of bytes to be transmitted */
+      uint32_t nBytes = hDevice->TxRemaining - 1U;
+      
+      /* Enable RD_CTL and set the TX count for the half-duplex mode of operation */
+      hDevice->pSpi->RD_CTL &=  (uint16_t)~((uint16_t)(BITM_SPI_RD_CTL_TXBYTES <<  BITP_SPI_RD_CTL_TXBYTES));
+
+      hDevice->pSpi->RD_CTL |=  (uint16_t)( (uint16_t)(nBytes << BITP_SPI_RD_CTL_TXBYTES) |
+                                            (uint16_t)(1 << BITP_SPI_RD_CTL_CMDEN));
+      
+      /* RD_CTL requires continuous mode operation. */
+      hDevice->pSpi->CTL |= (BITM_SPI_CTL_CON);
+
+      /* CNT represent the number of bytes to receive */
+      hDevice->pSpi->CNT =  hDevice->RxRemaining;
+      
+    }
+    else
+    {
+      /* Full duplex mode of operation */
+      if(hDevice->RxRemaining == 0u)
+      {
+        /* There is nothing to receive. Flush the RX FIFO and to ignore all incoming data */
+         hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH);
+      } 
+      else if(hDevice->TxRemaining == 0u)
+      {
+        /* If there is nothing to transmit then clear the TX FIFO */
+        hDevice->pSpi->CTL |= (BITM_SPI_CTL_TFLUSH);
+      }
+      else
+      {
+        /* Misra compliance: All if/else chains should end with a final else clause */
+      }
+      
+      /* Set CNT to MAX of RX/TX */
+
+      nCount = hDevice->RxRemaining >  hDevice->TxRemaining ? hDevice->RxRemaining : hDevice->TxRemaining;
+      hDevice->pSpi->CNT = (uint16_t)nCount;
+
+    }
+    
+    
+    if( hDevice->bDmaMode == false) 
+    {
+      /* Make sure that the application passed in a TX Buffer */
+      if( hDevice->pTxBuffer != NULL)
+      {
+        /* interrupt mode: Fill in the FIFO  */
+        nCount = 0u;
+        while((nCount < ADI_SPI_FIFO_SIZE) && (hDevice->TxRemaining != 0u))
+        {
+            /* grab the lead byte */
+            hDevice->pSpi->TX = *hDevice->pTxBuffer;
+            /* modify tx pointer and buffer count prior to interrupt */
+            hDevice->pTxBuffer += hDevice->TxIncrement;
+            /* decrement the byte count */
+            hDevice->TxRemaining--;
+            nCount++;
+        }
+      }
+      
+    } else {
+      
+      hDevice->pSpi->DMA |= dmaFlags;
+    }
+    
+    if((hDevice->pSpi->CTL & BITM_SPI_CTL_TIM) != BITM_SPI_CTL_TIM)
+    {
+      uint16_t byte ADI_UNUSED_ATTRIBUTE = hDevice->pSpi->RX;
+    }
+    
+    
+    NVIC_EnableIRQ(hDevice->pDevInfo->eIRQn);
+   
+    return;
+}
+
+/*!
+ * @brief  Block until the SPI transaction is complete.
+ *
+ * @param[in]     hDevice      Device handle obtained from adi_spi_Open().
+ *\n
+ * @param[out]   pHWErrors     Pointer to hardware error return variable.
+ *\n
+ * @return         Status
+ *                - #ADI_SPI_SUCCESS                    Call completed successfully.
+ *                - #ADI_SPI_SEMAPHORE_FAILED           Semaphore Pend failed
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *
+ * @sa        adi_spi_MasterSubmitBuffer().
+ * @sa        adi_spi_SlaveSubmitBuffer().
+ */
+ADI_SPI_RESULT adi_spi_GetBuffer(
+               ADI_SPI_HANDLE const hDevice,
+               uint32_t * const pHWErrors
+              )
+{
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        *pHWErrors = ADI_SPI_HW_ERROR_NONE;
+        return ADI_SPI_INVALID_HANDLE;
+    }
+#endif
+
+    SEM_PEND(hDevice,ADI_SPI_SEMAPHORE_FAILED);
+    *pHWErrors = hDevice->HWErrors;
+    return(ADI_SPI_SUCCESS);
+}
+
+/*!
+ * @brief  Get the SPI transaction completion status.
+ *
+ * @param[in]     hDevice      Device handle obtained from adi_spi_Open().
+ *\n
+ * @param[out] bComplete      Pointer to boolean variable that indicates
+ *\n                - true    DMA transmit sequence is complete.
+ *\n                - false   DMA transmit sequence is incomplete.
+ *\n
+ * @return         Status
+ *                - #ADI_SPI_SUCCESS                    Call completed successfully.
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *
+ * @sa        adi_spi_MasterSubmitBuffer().
+ * @sa        adi_spi_SlaveSubmitBuffer().
+ */
+
+ADI_SPI_RESULT  adi_spi_isBufferAvailable(ADI_SPI_CONST_HANDLE const hDevice,  bool* const bComplete)
+{
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+#endif
+
+    *bComplete = hDevice->bTransferComplete;
+    return(ADI_SPI_SUCCESS);
+}
+
+/*!
+ * @brief  Submit data buffers for SPI Slave-Mode transaction.
+ *
+ * @param[in]     hDevice     Device handle obtained from adi_spi_Open().
+ * @param[in]     pXfr        Pointer to transfer data struct.
+  *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]        Invalid device handle parameter.
+ *                - #ADI_SPI_IN_USE [D]    DMA transaction already under way.
+ *                - #ADI_SPI_INVALID_POINTER [D]     Invalid data pointer detected (NULL).
+ *                - #ADI_SPI_INVALID_PARAM [D]    Invalid size parameter detected (0).
+ *                - #ADI_SPI_SUCCESS                       Call completed successfully.
+ *
+ *\n Request a non-blocking transmit and receive of multiple data bytes
+ *\n over the SPI serial channel.  Honours current blocking and DMA modes.
+ *\n Buffer allocations are made by the calling code (the application).
+ *\n
+ *\n The transmit buffer is sent and the receive buffer is written according
+ *\n to the size and increment information contained by the \a pXft transfer
+ *\n data structure parameter.
+ *\n
+ *\n The application must make a call to adi_spi_GetBuffer() to retrieve the buffer
+ *\n
+ *\n @note:
+ *
+ * @sa adi_spi_MasterReadWrite().
+ * @sa adi_spi_EnableDmaMode().
+ * @sa adi_spi_isBufferAvailable().
+ * @sa adi_spi_GetBuffer().
+ */
+ADI_SPI_RESULT adi_spi_SlaveSubmitBuffer (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr)
+{
+    volatile uint16_t ADI_UNUSED_ATTRIBUTE byte;
+    uint32_t nCount = 0u;
+    
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+    if ((NULL == pXfr->pTransmitter) && (NULL == pXfr->pReceiver))
+    {
+        return ADI_SPI_INVALID_POINTER;
+    }
+    
+    if ((0u == pXfr->pTransmitter) && (0u == pXfr->pReceiver) )
+    {
+        return ADI_SPI_INVALID_PARAM;
+    }
+    /* Return error if the RX buffer is not null and count is equal to zero or vice versa.*/
+    if (((pXfr->pReceiver != NULL) && (pXfr->ReceiverBytes == 0u)) || ((pXfr->pReceiver == NULL) && ((pXfr->ReceiverBytes > 0u))))
+    {
+        return ADI_SPI_INVALID_PARAM;
+    }
+    
+    /* Return error if the Tx buffer is not null and count is equal to zero or vice versa.*/
+    if (((pXfr->pTransmitter != NULL) && (pXfr->TransmitterBytes == 0u)) || ((pXfr->pTransmitter == NULL) && (pXfr->TransmitterBytes > 0u)))
+    {
+        return ADI_SPI_INVALID_PARAM;
+    }
+
+    /* DMA count register is only 8 bits, so block size is limited to 255 */
+    if ((pXfr->bDMA==true) && (pXfr->TransmitterBytes != 0u) &&(((uint32_t)pXfr->pTransmitter&0x1U) !=0u ) )
+    {
+        return ADI_SPI_INVALID_PARAM;
+    }
+
+#endif /* ADI_DEBUG */
+
+    /* Effectively flush the FIFOs before the start of the next transaction */
+    hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH);
+    hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH);
+
+    /* Shut down any DMA enables that are still lingering from a prior transaction */
+    hDevice->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
+    
+    hDevice->bTransferComplete   = false;
+    hDevice->pTxBuffer           = pXfr->pTransmitter;
+    hDevice->pRxBuffer           = pXfr->pReceiver;
+    hDevice->TxRemaining         = pXfr->TransmitterBytes;
+    hDevice->RxRemaining         = pXfr->ReceiverBytes;
+    hDevice->TxIncrement         = (uint8_t)pXfr->nTxIncrement;
+    hDevice->RxIncrement         = (uint8_t)pXfr->nRxIncrement;
+    hDevice->pSpi->CNT           = (uint16_t)nCount;
+    hDevice->bDmaMode            = pXfr->bDMA;
+    hDevice->bRdCtlMode          = pXfr->bRD_CTL;
+    hDevice->HWErrors            = ADI_SPI_HW_ERROR_NONE;
+
+    
+    /* Configure SPI. First step is to clear CTL bits that may have been set previously  */
+    hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_TIM | BITM_SPI_CTL_RFLUSH | BITM_SPI_CTL_TFLUSH | BITM_SPI_CTL_CON);
+    if( hDevice->TxRemaining == 0u )
+    {
+      /* This will prevent TX underflow interrupts from occurring */
+      hDevice->pSpi->CTL |= BITM_SPI_CTL_TFLUSH;
+    }
+    if( hDevice->RxRemaining == 0u )
+    {
+      /* This will prevent data from entering RX. Also prevents overflow interrupts from occurring */
+      hDevice->pSpi->CTL |= BITM_SPI_CTL_RFLUSH;
+      
+      /* If SPI_CTL.TIM is set, the Tx FIFO status causes the interrupt. */
+      if( hDevice->bDmaMode != true) {
+        hDevice->pSpi->CTL |= BITM_SPI_CTL_TIM;
+      }
+      
+    }
+      
+    hDevice->pSpi->CNT    = (uint16_t) hDevice->TxRemaining > hDevice->RxRemaining ? hDevice->TxRemaining : hDevice->RxRemaining;
+    
+    uint16_t nDMAFlags = 0u;
+      
+    if( hDevice->bDmaMode == true) 
+    {
+      uint16_t sz = pXfr->TransmitterBytes;
+      if( sz )
+      {
+        uint16_t TxChanNum = hDevice->pDevInfo->dmaTxChannelNumber;
+    
+        /* Enable the interrupt for the given DMA */
+        NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaTxIrqNumber));
+
+        /* Disables source address decrement for TX channel */
+        pADI_DMA0->SRCADDR_CLR = 1U << TxChanNum;
+      
+        /* Enable the channel */
+        pADI_DMA0->EN_SET = 1U << TxChanNum;
+          
+        /* Enables SPI peripheral to generate DMA requests. */
+        pADI_DMA0->RMSK_CLR = 1U << TxChanNum;
+
+        /* Set the primary as the current DMA descriptor */
+        pADI_DMA0->ALT_CLR = 1U << TxChanNum;
+     
+        /* fill in the DMA RAM descriptors */
+        if( (sz & 1U) != 0u )
+        {
+          /* DMA is performed on 16-bit data. Make sure the DMA engine is properly aligned to even counts */
+          /* The SPI_CNT register will hold the "real" transfer count                                     */
+          sz++;
+        }
+        
+        pPrimaryCCD[TxChanNum].DMASRCEND =   (uint32_t)(pXfr->pTransmitter + (sz - 2U));
+              
+        pPrimaryCCD[TxChanNum].DMADSTEND =   (uint32_t)&hDevice->pSpi->TX;
+
+        pPrimaryCCD[TxChanNum].DMACDC = ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) |
+                              (ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_SRC_INC) |
+                              (ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) |
+                              ((sz/2U -1U)<< DMA_BITP_CTL_N_MINUS_1) |
+                              (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
+      
+        nDMAFlags |= (BITM_SPI_DMA_TXEN);
+      }
+
+      sz = pXfr->ReceiverBytes;
+      if( sz )
+      {
+        
+        uint16_t RxChanNum = hDevice->pDevInfo->dmaRxChannelNumber;
+        NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaRxIrqNumber));
+
+        /* Disables destination address decrement for RX channel */
+        pADI_DMA0->DSTADDR_CLR = 1U << RxChanNum;
+        
+        /* Enable the channel */
+        pADI_DMA0->EN_SET = 1U << RxChanNum;
+        
+        /* Enables SPI peripheral to generate DMA requests. */
+        pADI_DMA0->RMSK_CLR = 1U << RxChanNum;
+
+        /* Set the primary as the current DMA descriptor */
+        pADI_DMA0->ALT_CLR = 1U << RxChanNum;
+        
+        if( (sz & 1U) != 0u )
+        {
+          /* DMA is performed on 16-bit data. Make sure the DMA engine is properly aligned to even counts */
+          /* The SPI_CNT register will hold the "real" transfer count                                     */
+          sz++;
+        }
+        
+        pPrimaryCCD[RxChanNum].DMASRCEND =   (uint32_t)&hDevice->pSpi->RX;
+              
+        pPrimaryCCD[RxChanNum].DMADSTEND =   (uint32_t)(pXfr->pReceiver + (sz - 2U));
+
+        pPrimaryCCD[RxChanNum].DMACDC = (ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_DST_INC) |
+                              (ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) |
+                              (ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) |
+                              ((sz/2U -1U) << DMA_BITP_CTL_N_MINUS_1) |
+                              (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
+        
+        nDMAFlags |= (BITM_SPI_DMA_RXEN );
+
+      }
+    }
+
+    /* Make sure XFRDONE is shut down. This IEN has no affect in slave mode */
+    hDevice->pSpi->IEN &= (uint16_t)~BITM_SPI_IEN_XFRDONE;
+
+    if( hDevice->bDmaMode == false) {
+      /* Make sure we are not in continuous mode from a prior DMA transaction  */
+      hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CON;
+
+    
+      /* interrupt mode: Enable the UNDERFLOW and OVERFLOW interrupts */
+      /* XFRDONE is invalid in slave mode */
+      uint16_t activeInterrupts = 0u;
+      /* Enable underflow on;y if sending bytes */
+      if( hDevice->TxRemaining ) {
+        activeInterrupts |= BITM_SPI_IEN_TXUNDR;
+      }
+      /* Enable overflow only if receiving bytes */
+      if( hDevice->RxRemaining ) {
+        activeInterrupts |= BITM_SPI_IEN_RXOVR;
+      }
+      hDevice->pSpi->IEN |= activeInterrupts;
+
+      /* interrupt mode: Fill in the FIFO and enable the TX by a dummy read. */
+      while((nCount < ADI_SPI_FIFO_SIZE) && (hDevice->TxRemaining != 0u))
+      {
+          /* grab the lead byte */
+          hDevice->pSpi->TX = *hDevice->pTxBuffer;
+          /* modify tx pointer and buffer count prior to interrupt */
+          hDevice->pTxBuffer += hDevice->TxIncrement;
+          /* decrement the byte count */
+          hDevice->TxRemaining--;
+          nCount++;
+      }
+    } else {
+
+      /* DMA mode. Enable the controller */
+      hDevice->pSpi->DMA |= (uint16_t)(BITM_SPI_DMA_EN | nDMAFlags);
+    }
+     
+    if((hDevice->pSpi->CTL & BITM_SPI_CTL_TIM) != BITM_SPI_CTL_TIM)
+    {
+         byte = hDevice->pSpi->RX;    
+    }
+    NVIC_EnableIRQ(hDevice->pDevInfo->eIRQn);
+
+    if (hDevice->bBlockingMode == true)
+    {
+	SEM_PEND(hDevice,ADI_SPI_SEMAPHORE_FAILED);
+    }
+
+    return ADI_SPI_SUCCESS;
+}
+
+
+
+/*!
+ * @brief  Submit data buffers for SPI Slave-Mode transaction in "Blocking mode".This function
+ *\n          returns only after the data transfer is complete
+ *
+ * @param[in]     hDevice     Device handle obtained from adi_spi_Open().
+ * @param[in]     pXfr        Pointer to transfer data struct #ADI_SPI_TRANSCEIVER.
+  *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]        Invalid device handle parameter.
+ *                - #ADI_SPI_BUFFER_NOT_SUBMITTED [D]  Failed to submit the buffer.
+ *                - #ADI_SPI_INVALID_POINTER [D]       Invalid data pointer detected (NULL).
+ *                - #ADI_SPI_INVALID_PARAM [D]         Invalid size parameter detected (0).
+ *                - #ADI_SPI_SUCCESS                   Call completed successfully.
+ *
+ *\n
+ *\n Request a non-blocking mode transmit and receive of multiple data bytes
+ *\n over the SPI serial channel.  
+ *\n Buffer allocations are made by the calling code (the application).
+ *\n
+ *\n The transmit buffer is sent and the receive buffer is written according
+ *\n to the size and increment information contained by the \a pXft transfer
+ *\n data structure parameter.
+ *\n
+ *\n
+ * @sa adi_spi_SlaveSubmitBuffer().
+ * @sa ADI_SPI_TRANSCEIVER
+ */
+ADI_SPI_RESULT adi_spi_SlaveReadWrite (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr)
+{
+    ADI_SPI_RESULT eResult;
+    hDevice->bBlockingMode = true;
+    eResult = adi_spi_SlaveSubmitBuffer(hDevice,pXfr);
+    hDevice->bBlockingMode = false;
+    if( (eResult == ADI_SPI_SUCCESS) && (hDevice->HWErrors != 0u))
+    {
+      eResult = ADI_SPI_HW_ERROR_OCCURRED;
+    }
+    return(eResult);
+}
+
+/*
+ *****************************************************************************
+ * SPI Internal Static Support Functions
+ *****************************************************************************/
+
+
+ /*! \cond PRIVATE */
+
+
+/*-----------------------------------------------------------------------------
+ *
+ * SPI ISR
+ *
+ *----------------------------------------------------------------------------*/
+
+
+
+static void common_SPI_Int_Handler (ADI_SPI_DEV_DATA_TYPE* pDD)
+{
+   
+  /* read status register - first thing */
+  volatile  uint16_t nFifoStatus = pDD->pSpi->FIFO_STAT;
+  uint16_t nErrorStatus = pDD->pSpi->STAT;
+
+  uint16_t writableBytes;
+  uint16_t readableBytes;
+
+
+  
+  /* Trap overflow/underflow errors and terminate the current transaction if there is an error. */
+  if(  BITM_SPI_STAT_RXOVR == (BITM_SPI_STAT_RXOVR & nErrorStatus)) {
+      pDD->HWErrors |= (uint32_t)ADI_SPI_HW_ERROR_RX_OVERFLOW;
+  } else if( BITM_SPI_STAT_TXUNDR == (BITM_SPI_STAT_TXUNDR & nErrorStatus)) {
+      pDD->HWErrors |= (uint32_t)ADI_SPI_HW_ERROR_TX_UNDERFLOW;
+  }
+  else
+  {
+    
+    /* calculate number of bytes that can be written to tx fifo */
+    writableBytes = ADI_SPI_FIFO_SIZE - ((BITM_SPI_FIFO_STAT_TX & nFifoStatus) >> BITP_SPI_FIFO_STAT_TX);
+    /* calculate number of bytes to read from rx fifo */
+    readableBytes = ((BITM_SPI_FIFO_STAT_RX & nFifoStatus) >> BITP_SPI_FIFO_STAT_RX);
+    
+    /* fill tx fifo */
+    while ((writableBytes != 0u) && (pDD->TxRemaining != 0u))
+    {
+      pDD->pSpi->TX = *pDD->pTxBuffer;
+      pDD->pTxBuffer  += pDD->TxIncrement;
+      pDD->TxRemaining--;
+      writableBytes--;
+    }
+    
+    /*
+     * Now focus on the RX FIFO but only if we are not in RD_CTL mode OR, if we
+     * are in RD_CTL mode, TX bytes are all transmitted 
+     */
+    
+    if( (pDD->bRdCtlMode==false) || (pDD->TxRemaining==0u) )
+    {
+      /* empty rx fifo */
+      while ((readableBytes != 0u) &&(pDD->RxRemaining != 0u))
+      {
+      
+        *pDD->pRxBuffer = (uint8_t) pDD->pSpi->RX;
+        pDD->pRxBuffer += pDD->RxIncrement;
+        pDD->RxRemaining--;
+        readableBytes--;
+      }
+    }
+  }
+
+  
+  /* Terminate the transaction and notify the caller 
+   *   1) Master mode: If there are no more bytes to RX or TX and XFRDONE is set
+   *   2) Slave mode: If there are no more bytes to RX or TX  (XFRDONE is invalid in slave mode)
+   *   3) If there was a HW error 
+   */
+  bool terminate = false;
+  if( (pDD->RxRemaining == 0u) && (pDD->TxRemaining == 0u))
+  {
+    if( BITM_SPI_CTL_MASEN == (pDD->pSpi->CTL & BITM_SPI_CTL_MASEN ))
+    {
+      /* Master mode */
+      if( BITM_SPI_STAT_XFRDONE == (pDD->pSpi->STAT & BITM_SPI_STAT_XFRDONE ))
+      {
+        /* Master mode XFRDONE */
+        terminate = true;
+      }
+    } else {
+      /* Slave mode - we're all done here */
+        terminate = true;
+    }
+  }
+
+  if( terminate || (pDD->HWErrors != (uint32_t)ADI_SPI_HW_ERROR_NONE))  
+  {
+      
+    /* Clear possible interrupt sources: XFRDONE and underflow and overflow */  
+    pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR);  
+    pDD->bTransferComplete  = true;
+    NVIC_DisableIRQ(pDD->pDevInfo->eIRQn);
+    
+    /* If a callback is registered notify the buffer processed event to the application */
+    if(NULL != pDD->pfCallback ){
+        pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
+    }
+    else
+    {
+        SEM_POST(pDD);
+    }
+      
+  }
+  
+  /* All interrupts are cleared by a write of 1 to the status register bits (W1C)  */
+  pDD->pSpi->STAT = nErrorStatus;
+
+#if defined(ADI_CYCLECOUNT_SPI_ISR_ENABLED) && (ADI_CYCLECOUNT_SPI_ISR_ENABLED == 1u)
+  ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_SPI);    
+#endif
+
+
+  
+}
+
+
+/* Internal DMA Callback for receiving DMA faults from common DMA error handler. */
+static void RxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) {
+
+    /* Recover the device handle. */
+    ADI_SPI_HANDLE hDevice = (ADI_SPI_HANDLE) pCBParam;
+
+    /* Save the DMA error. */
+    switch (Event) {
+        case ADI_DMA_EVENT_ERR_BUS:
+            hDevice->HWErrors |= ADI_SPI_HW_ERROR_RX_CHAN_DMA_BUS_FAULT;
+            break;
+        case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR:
+            hDevice->HWErrors |= ADI_SPI_HW_ERROR_RX_CHAN_DMA_INVALID_DESCR;
+            break;
+        default:
+            hDevice->HWErrors |= ADI_SPI_HW_ERROR_RX_CHAN_DMA_UNKNOWN_ERROR;
+            break;
+    }
+	
+	/* If a callback is registered notify the buffer processed event to the application */
+    if(NULL != hDevice->pfCallback ){
+        hDevice->pfCallback(hDevice->pCBParam, hDevice->HWErrors, NULL);
+    }
+    else
+    {
+        SEM_POST(hDevice);
+    }	
+}
+
+
+/* Internal DMA Callback for receiving DMA faults from common DMA error handler. */
+static void TxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) {
+
+    /* Recover the device handle. */
+    ADI_SPI_HANDLE hDevice = (ADI_SPI_HANDLE) pArg;
+
+    /* Save the DMA error. */
+    switch (Event) {
+        case ADI_DMA_EVENT_ERR_BUS:
+            hDevice->HWErrors |= ADI_SPI_HW_ERROR_TX_CHAN_DMA_BUS_FAULT;
+            break;
+        case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR:
+            hDevice->HWErrors |= ADI_SPI_HW_ERROR_TX_CHAN_DMA_INVALID_DESCR;
+            break;
+        default:
+            hDevice->HWErrors |= ADI_SPI_HW_ERROR_TX_CHAN_DMA_UNKNOWN_ERROR;
+            break;
+    }
+    
+    /* If a callback is registered notify the buffer processed event to the application */
+    if(NULL != hDevice->pfCallback ){
+        hDevice->pfCallback(hDevice->pCBParam, hDevice->HWErrors, NULL);
+    }
+    else
+    {
+        SEM_POST(hDevice);
+    }	
+}
+
+
+/*!
+ * @brief  SPI0 Interrupt Handler.
+ *
+ * @return void.
+ *
+ * Overrides default SPI0 interrupt handler.
+ */
+void SPI0_Int_Handler(void) {
+    ISR_PROLOG();
+    common_SPI_Int_Handler(spi_device_info[0].hDevice );
+    ISR_EPILOG();
+}
+
+
+/*!
+ * @brief  SPI1 Interrupt Handler.
+ *
+ * @return void.
+ *
+ * Overrides default SPI1 interrupt handler.
+ */
+void SPI1_Int_Handler(void) {
+    ISR_PROLOG();
+    common_SPI_Int_Handler(spi_device_info[1].hDevice);
+    ISR_EPILOG();
+}
+
+/*!
+ * @brief  SPI2 Interrupt Handler.
+ *
+ * @return void.
+ *
+ * Overrides default SPI2 interrupt handler.
+ */
+void SPI2_Int_Handler(void) {
+    ISR_PROLOG();    
+    common_SPI_Int_Handler(spi_device_info[2].hDevice );
+    ISR_EPILOG();
+}
+
+
+/*
+    //////////////////////////////////////////////////////////////////////////////
+    //////////////////////////   DMA-RELATED   ///////////////////////////////////
+    //////////////////////////////////////////////////////////////////////////////
+*/
+
+
+/*
+ * SPI DMA interrupt handlers
+ */
+
+
+#if defined(ADI_SPI0_MASTER_MODE) && (ADI_SPI0_MASTER_MODE==1u)
+void DMA_SPI0_TX_Int_Handler(void)  
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[0].hDevice;
+   pDD->TxRemaining = 0u;
+   ISR_EPILOG();       
+}
+
+/* Master mode DMA ISR */
+void DMA_SPI0_RX_Int_Handler(void)  
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[0].hDevice;
+   pDD->RxRemaining = 0u;
+   /* Disable DMA */
+   pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
+   /* Master mode: Now allow the XFRDONE interrupt to occur. It's the SPI ISR that really ends the transaction */
+   /* The slave mode is not affected by this setting */
+   pDD->pSpi->IEN |= BITM_SPI_IEN_XFRDONE;
+   ISR_EPILOG();       
+}
+#endif
+#if defined(ADI_SPI0_MASTER_MODE) && (ADI_SPI0_MASTER_MODE==0u)
+/* Slave mode DMA ISRs */
+void DMA_SPI0_TX_Int_Handler(void)  
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[0].hDevice;
+   pDD->TxRemaining = 0u;
+   if( pDD->RxRemaining == 0)
+   {
+     /* If a callback is registered notify the buffer processed event to the application */
+     if(NULL != pDD->pfCallback ){
+         pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
+     }
+     else
+     {
+         SEM_POST(pDD);
+     }
+   }
+   ISR_EPILOG();       
+}
+void DMA_SPI0_RX_Int_Handler(void)  
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[0].hDevice;
+   pDD->RxRemaining = 0u;
+   /* Disable DMA */
+   pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
+   pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR);  
+   pDD->bTransferComplete  = true;
+   NVIC_DisableIRQ(pDD->pDevInfo->eIRQn);
+    
+   /* If a callback is registered notify the buffer processed event to the application */
+   if(NULL != pDD->pfCallback ){
+       pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
+   }
+   else
+   {
+       SEM_POST(pDD);
+   }
+   ISR_EPILOG();       
+}
+#endif
+
+
+
+
+#if defined(ADI_SPI1_MASTER_MODE) && (ADI_SPI1_MASTER_MODE==1u)
+/* Master mode DMA ISR */
+void DMA_SPI1_TX_Int_Handler(void) 
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[1].hDevice;
+   pDD->TxRemaining = 0u;
+   ISR_EPILOG();       
+}
+
+void DMA_SPI1_RX_Int_Handler(void)  
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[1].hDevice;
+   pDD->RxRemaining = 0u;
+   /* Disable DMA */
+   pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
+   /* Master mode: Now allow the XFRDONE interrupt to occur. It's the SPI ISR that really ends the transaction */
+   /* The slave mode is not affected by this setting */
+   pDD->pSpi->IEN |= BITM_SPI_IEN_XFRDONE;
+   ISR_EPILOG();       
+}
+#endif
+
+
+#if defined(ADI_SPI1_MASTER_MODE) && (ADI_SPI1_MASTER_MODE==0u)
+/* Slave mode DMA ISRs */
+void DMA_SPI1_TX_Int_Handler(void) 
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[1].hDevice;
+   pDD->TxRemaining = 0u;
+   if( pDD->RxRemaining == 0)
+   {
+     /* If a callback is registered notify the buffer processed event to the application */
+     if(NULL != pDD->pfCallback ){
+         pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
+     }
+     else
+     {
+         SEM_POST(pDD);
+     }
+   }
+   ISR_EPILOG();       
+}
+
+
+void DMA_SPI1_RX_Int_Handler(void)  
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[1].hDevice;
+   pDD->RxRemaining = 0u;
+   /* Disable DMA */
+   pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
+   pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR);  
+   pDD->bTransferComplete  = true;
+   NVIC_DisableIRQ(pDD->pDevInfo->eIRQn);
+    
+   /* If a callback is registered notify the buffer processed event to the application */
+   if(NULL != pDD->pfCallback ){
+       pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
+   }
+   else
+   {
+       SEM_POST(pDD);
+   }
+   ISR_EPILOG();       
+}
+#endif
+
+
+#if defined(ADI_SPI2_MASTER_MODE) && (ADI_SPI2_MASTER_MODE==1u)
+/* Master mode DMA ISR */
+
+void DMA_SPIH_TX_Int_Handler(void)  
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[2].hDevice;
+   pDD->TxRemaining = 0u;
+   ISR_EPILOG();       
+}
+
+void DMA_SPIH_RX_Int_Handler(void)  
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[2].hDevice;
+   pDD->RxRemaining = 0u;
+   /* Disable DMA */
+   pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
+   /* Master mode: Now allow the XFRDONE interrupt to occur. It's the SPI ISR that really ends the transaction */
+   /* The slave mode is not affected by this setting */
+   pDD->pSpi->IEN |= BITM_SPI_IEN_XFRDONE;
+   ISR_EPILOG();       
+}
+#endif
+#if defined(ADI_SPI2_MASTER_MODE) && (ADI_SPI2_MASTER_MODE==0u)
+/* Master mode DMA ISRs */
+
+void DMA_SPIH_TX_Int_Handler(void)  
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[2].hDevice;
+   pDD->TxRemaining = 0u;
+   ISR_EPILOG();       
+   if( pDD->RxRemaining == 0)
+   {
+     /* If a callback is registered notify the buffer processed event to the application */
+     if(NULL != pDD->pfCallback ){
+         pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
+     }
+     else
+     {
+         SEM_POST(pDD);
+     }
+   }
+   ISR_EPILOG();   
+}
+
+void DMA_SPIH_RX_Int_Handler(void)  
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[2].hDevice;
+   pDD->RxRemaining = 0u;
+   /* Disable DMA */
+   pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
+   pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR);  
+   pDD->bTransferComplete  = true;
+   NVIC_DisableIRQ(pDD->pDevInfo->eIRQn);
+    
+   /* If a callback is registered notify the buffer processed event to the application */
+   if(NULL != pDD->pfCallback ){
+       pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
+   }
+   else
+   {
+       SEM_POST(pDD);
+   }
+   ISR_EPILOG();       
+}
+#endif
+
+
+
+
+/*! \endcond */
+
+
+/* @} */
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/spi/adi_spi_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/spi/adi_spi_data.c
new file mode 100755
index 00000000000..ecbcb00b62e
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/spi/adi_spi_data.c
@@ -0,0 +1,163 @@
+/*
+ *****************************************************************************
+ * @file:    adi_spi_data.c
+ * @brief:   Data declaration for SPORT Device Driver
+ *****************************************************************************
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef _ADI_SPI_DATA_C_
+#define _ADI_SPI_DATA_C_
+
+ /*! \cond PRIVATE */
+
+#include <adi_processor.h>
+#include "adi_spi_def.h"
+#include "adi_spi_config.h"
+#include <drivers/dma/adi_dma.h>
+
+/* Stores the information about the specific device */
+static  ADI_SPI_DEVICE_INFO spi_device_info [ADI_SPI_NUM_INSTANCES]=
+{
+    {
+             DMA0_CH4_DONE_IRQn,
+             SPI0_TX_CHANn,
+	     DMA0_CH5_DONE_IRQn,
+             SPI0_RX_CHANn,
+	     (volatile ADI_SPI_TypeDef *)pADI_SPI0,
+	     SPI0_EVT_IRQn,
+	     NULL
+    },
+    {
+             DMA0_CH6_DONE_IRQn,
+             SPI1_TX_CHANn,
+	     DMA0_CH7_DONE_IRQn,
+             SPI1_RX_CHANn,
+	     (volatile ADI_SPI_TypeDef *)pADI_SPI1,
+	     SPI1_EVT_IRQn,
+	     NULL
+    },
+
+    {
+             DMA0_CH0_DONE_IRQn,
+             SPI2_TX_CHANn,
+   	     DMA0_CH1_DONE_IRQn,
+             SPI2_RX_CHANn,
+   	     (volatile ADI_SPI_TypeDef *)pADI_SPI2,
+	     SPI2_EVT_IRQn,
+	     NULL
+    }
+};
+
+/* SPI Application configuration array */
+static const ADI_SPI_CFG_TYPE gSPICfg[ADI_SPI_NUM_INSTANCES] =
+{
+  /* Initialize SPI0 Instance configuration. */
+  {
+       /**** SPI_CFG register configuration *** */
+       (( ADI_SPI0_CFG_ENABLE               << BITP_SPI_CTL_SPIEN         ) |
+        ( ADI_SPI0_CFG_CLK_PHASE            << BITP_SPI_CTL_CPHA          ) |
+        ( ADI_SPI0_CFG_CLK_POLARITY         << BITP_SPI_CTL_CPOL          ) |
+        ( ADI_SPI0_CFG_WIRED_OR             << BITP_SPI_CTL_WOM           ) |
+        ( ADI_SPI0_CFG_LSB_MSB              << BITP_SPI_CTL_LSB           ) |
+        ( ADI_SPI0_CFG_TRANSFER_INITIATE    << BITP_SPI_CTL_TIM           ) |
+        ( ADI_SPI0_CFG_TX_UNDERFLOW         << BITP_SPI_CTL_ZEN           ) |
+        ( ADI_SPI0_CFG_RX_OVERFLOW          << BITP_SPI_CTL_RXOF          ) |
+        ( ADI_SPI0_CFG_MISO_ENABLE          << BITP_SPI_CTL_OEN           ) |
+        ( ADI_SPI0_CFG_LOOPBACK             << BITP_SPI_CTL_LOOPBACK      ) |
+        ( ADI_SPI0_CFG_CONTINUOUS           << BITP_SPI_CTL_CON           ) |
+        ( ADI_SPI0_CFG_RX_FLUSH             << BITP_SPI_CTL_RFLUSH        ) |
+        ( ADI_SPI0_CFG_TX_FLUSH             << BITP_SPI_CTL_TFLUSH        ) |
+        ( ADI_SPI0_CFG_CSERR_RESET          << BITP_SPI_CTL_CSRST         )),
+
+       /**** SPI_DIV buad rate selection register *** */
+       (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI0_CFG_BIT_RATE)) >>1u)-1u))\
+                                        << BITP_SPI_DIV_VALUE           )
+    },
+  /* Initialize SPI1 Instance configuration. */
+  {
+       /**** SPI_CFG register configuration *** */
+       (( ADI_SPI1_CFG_ENABLE               << BITP_SPI_CTL_SPIEN            ) |
+        ( ADI_SPI1_CFG_CLK_PHASE            << BITP_SPI_CTL_CPHA          ) |
+        ( ADI_SPI1_CFG_CLK_POLARITY         << BITP_SPI_CTL_CPOL          ) |
+        ( ADI_SPI1_CFG_WIRED_OR             << BITP_SPI_CTL_WOM           ) |
+        ( ADI_SPI1_CFG_LSB_MSB              << BITP_SPI_CTL_LSB           ) |
+        ( ADI_SPI1_CFG_TRANSFER_INITIATE    << BITP_SPI_CTL_TIM           ) |
+        ( ADI_SPI1_CFG_TX_UNDERFLOW         << BITP_SPI_CTL_ZEN           ) |
+        ( ADI_SPI1_CFG_RX_OVERFLOW          << BITP_SPI_CTL_RXOF          ) |
+        ( ADI_SPI1_CFG_MISO_ENABLE          << BITP_SPI_CTL_OEN           ) |
+        ( ADI_SPI1_CFG_LOOPBACK             << BITP_SPI_CTL_LOOPBACK      ) |
+        ( ADI_SPI1_CFG_CONTINUOUS           << BITP_SPI_CTL_CON           ) |
+        ( ADI_SPI1_CFG_RX_FLUSH             << BITP_SPI_CTL_RFLUSH        ) |
+        ( ADI_SPI1_CFG_TX_FLUSH             << BITP_SPI_CTL_TFLUSH        ) |
+        ( ADI_SPI1_CFG_CSERR_RESET          << BITP_SPI_CTL_CSRST         )),
+
+       /**** SPI_DIV buad rate selection register *** */
+       (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI1_CFG_BIT_RATE)) >>1u)-1u))\
+                                        << BITP_SPI_DIV_VALUE           )
+    },
+  /* Initialize SPI2 Instance configuration. */
+  {
+       /**** SPI_CFG register configuration *** */
+       (( ADI_SPI2_CFG_ENABLE               << BITP_SPI_CTL_SPIEN            ) |
+        ( ADI_SPI2_CFG_CLK_PHASE            << BITP_SPI_CTL_CPHA          ) |
+        ( ADI_SPI2_CFG_CLK_POLARITY         << BITP_SPI_CTL_CPOL          ) |
+        ( ADI_SPI2_CFG_WIRED_OR             << BITP_SPI_CTL_WOM           ) |
+        ( ADI_SPI2_CFG_LSB_MSB              << BITP_SPI_CTL_LSB           ) |
+        ( ADI_SPI2_CFG_TRANSFER_INITIATE    << BITP_SPI_CTL_TIM           ) |
+        ( ADI_SPI2_CFG_TX_UNDERFLOW         << BITP_SPI_CTL_ZEN           ) |
+        ( ADI_SPI2_CFG_RX_OVERFLOW          << BITP_SPI_CTL_RXOF          ) |
+        ( ADI_SPI2_CFG_MISO_ENABLE          << BITP_SPI_CTL_OEN           ) |
+        ( ADI_SPI2_CFG_LOOPBACK             << BITP_SPI_CTL_LOOPBACK      ) |
+        ( ADI_SPI2_CFG_CONTINUOUS           << BITP_SPI_CTL_CON           ) |
+        ( ADI_SPI2_CFG_RX_FLUSH             << BITP_SPI_CTL_RFLUSH        ) |
+        ( ADI_SPI2_CFG_TX_FLUSH             << BITP_SPI_CTL_TFLUSH        ) |
+        ( ADI_SPI2_CFG_CSERR_RESET          << BITP_SPI_CTL_CSRST         )),
+
+       /**** SPI_DIV buad rate selection register *** */
+       (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI2_CFG_BIT_RATE)) >>1u)-1u))\
+                                        << BITP_SPI_DIV_VALUE           )
+    }
+};
+
+/*! \endcond */
+
+#endif /* _ADI_SPI_DATA_C_ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/spi/adi_spi_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/spi/adi_spi_def.h
new file mode 100755
index 00000000000..4e21f336acf
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/spi/adi_spi_def.h
@@ -0,0 +1,154 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_spi_def.h
+ * @brief:   SPI Device Driver definition 
+ *****************************************************************************
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#ifndef ADI_SPI_DEF_H_
+#define ADI_SPI_DEF_H_
+
+
+
+#include <drivers/spi/adi_spi.h>
+
+#define ADI_SPI_NUM_INSTANCES         (3u)
+#define ADI_SPI_FIFO_SIZE             (8u)
+#define ADI_SPI_IRQ_PARAM             (7u)
+
+/* Macro mapping from ADuCM4x50 to ADuCM302x */
+#if defined(__ADUCM302x__)
+#define DMA_SPIH_TX_Int_Handler(void) DMA_SPI2_TX_Int_Handler(void)
+#define DMA_SPIH_RX_Int_Handler(void) DMA_SPI2_RX_Int_Handler(void)
+#endif
+
+ /*! \cond PRIVATE */
+
+/*
+ *****************************************************************************
+ * SPI Bitrate Initializer.  Sets a default serial clockrate for the SPI channel.
+ *****************************************************************************/
+/* #define ADI_SPI_BITRATE_INITIALIZER   4000000 // 4MHz default bitrate */
+#define ADI_SPI_BITRATE_INITIALIZER      250000u  /* depends on processor */
+
+/*
+ *****************************************************************************
+ * SPI0/SPI1 Control Register Initializer.  This macro configures default
+ * settings for the SPI configuration control register when operated in Master-mode.
+ *****************************************************************************/
+/* SPI master DMA mode control configuration */
+#define ADI_SPI_MASTERCON_INITIALIZER      BITM_SPI_CTL_MASEN
+
+/*
+ *****************************************************************************
+ * SPI0/SPI1 Control Register Initializer.  This macro configures default
+ * settings for the SPI configuration control register when operated in Slave-mode.
+ *****************************************************************************/
+ #define ADI_SPI_SLAVECON_INITIALIZER  BITM_SPI_CTL_OEN           \
+                                     | BITM_SPI_CTL_ZEN           \
+                                     | BITM_SPI_CTL_SPIEN
+
+/* 16-bit DMA... (two-byte size and increment) */
+#define ADI_DMA_DATA_WIDTH      ADI_DMA_WIDTH_2_BYTE  /*!< DMA data attribute */
+#define ADI_DMA_DATA_INCREMENT  ADI_DMA_INCR_HALFWORD   /*!< DMA data attribute */
+
+
+
+/*!
+ *****************************************************************************
+ * SPI Configuration structure.
+ *****************************************************************************/
+typedef struct ADI_SPI_CONFIG
+{
+    uint16_t SPI_CTL;                          /*!< SPI_CTL register configuration. */
+    uint16_t SPI_DIV;                          /*!< SPI_DIV  register.     */
+} ADI_SPI_CFG_TYPE;
+
+/*! SPI device information */
+
+typedef struct __ADI_SPI_DEVICE_INFO
+{
+    const uint16_t               dmaTxIrqNumber;     /*  DMA channel ID-Tx */
+    const uint16_t               dmaTxChannelNumber; /*  Tx */
+    const uint16_t               dmaRxIrqNumber;     /*  DMA channel ID-Rx */    
+    const uint16_t               dmaRxChannelNumber; /*  DMA channel ID-Rx */    
+    volatile ADI_SPI_TypeDef     *pSpiRegs;          /*  Base address of the  SPI registers */
+    const IRQn_Type              eIRQn;              /*  IRQn */   
+    ADI_SPI_HANDLE               hDevice;            /*  SPI handle */
+}ADI_SPI_DEVICE_INFO;
+
+
+/*! \struct ADI_SPI_DEV_DATA_TYPE SPI Device instance data structure */
+typedef struct __ADI_SPI_DEV_DATA_TYPE
+{
+
+    /* device attributes */
+    volatile ADI_SPI_TypeDef *pSpi;              /*!< track MMR device pointer   */
+    ADI_SPI_DEVICE_INFO      *pDevInfo;
+
+    /* Callback and Callback parameters */
+    ADI_CALLBACK             pfCallback;         /*!< Callback address          */
+    void *                   pCBParam;           /*!< Callback parameter        */
+    /* The last recorded SPI event */
+    uint32_t                 HWErrors;           /*!< HW transaction status */
+
+    uint8_t*                 pTxBuffer;          /*!< Transmit Buffer           */
+    uint8_t*                 pRxBuffer;          /*!< Receive Buffer            */
+    uint16_t                 TxRemaining;        /*!< Transmit Count            */
+    uint16_t                 RxRemaining;        /*!< Receive Count             */
+    uint8_t                  TxIncrement;        /*!< Transmit Increment        */
+    uint8_t                  RxIncrement;        /*!< Receive Increment         */
+    
+    volatile bool            bTransferComplete;  /*!< Transfer Complete Flag    */
+
+    bool                     bDmaMode;           /*!< DMA mode flag              */
+    bool                     bRdCtlMode;         /* Use half duplex read control feature */
+    bool                     bBlockingMode;      /*!< blocking mode flag         */
+    ADI_SPI_CHIP_SELECT      ChipSelect;         /*!< track chip select          */
+    
+    SEM_VAR_DECLR
+} ADI_SPI_DEV_DATA_TYPE;
+
+
+
+/*! \endcond */
+
+#endif	/* ADI_SPI_DEF_H__ */
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sport/adi_sport.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sport/adi_sport.c
new file mode 100755
index 00000000000..5c352c2bc50
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sport/adi_sport.c
@@ -0,0 +1,1771 @@
+/*! ****************************************************************************
+ * @file:    adi_sport.c
+ * @brief:   SPORT (Serial Port) device driver source file.
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/** @addtogroup SPORT_Driver SPORT Driver
+ *  @{
+ */
+
+/*! \cond PRIVATE */
+
+/*=============  I N C L U D E S   =============*/
+
+#include <assert.h>
+#include <string.h>     /* memset declaration */
+
+#include <drivers/general/adi_drivers_general.h>
+#include <adi_sport_config.h>
+#include <drivers/sport/adi_sport.h>
+#include <adi_cyclecount.h>
+#include "adi_sport_def.h"
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
+*   This isn't a header as such.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+*
+* Pm050 (rule 14.2): a null statement shall only occur on a line by itself
+*   Needed for null expansion of ADI_INSTALL_HANDLER and others.
+*
+* Pm088 (rule 17.4): pointer arithmetic should not be used.
+*   Relying on pointer arithmetic for buffer handling.
+*
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   The rule makes an exception for memory-mapped register accesses.
+*
+* Pm152: (MISRA C 2004 rule 17.4) array indexing shall only be applied to objects defined as an array type
+*   Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors
+
+*/
+#pragma diag_suppress=Pm026,Pm050,Pm073,Pm088,Pm123,Pm140,Pm143,Pm152,Pm153
+#endif /* __ICCARM__ */
+
+/*==============  D A T A  ===============*/
+
+#define SPORT0_A_REGS   ((volatile ADI_SPORT_TypeDef*)REG_SPORT0_CTL_A)
+#define SPORT0_B_REGS   ((volatile ADI_SPORT_TypeDef*)REG_SPORT0_CTL_B)
+
+#define SPORT0_A_CFG    { 0u, 0u, 0u, 0u, 0u }
+#define SPORT0_B_CFG    { 0u, 0u, 0u, 0u, 0u }
+
+#define DXS_FIFO_IS_FULL(STAT)  (((STAT) & BITM_SPORT_STAT_A_DXS) == BITM_SPORT_STAT_A_DXS)
+#define DXS_FIFO_IS_EMPTY(STAT) (((STAT) & BITM_SPORT_STAT_A_DXS) == 0u)
+
+static  ADI_SPORT_DEVICE_INFO gSportDevInfo [ADI_SPORT_NUM_INSTANCES][ADI_SPORT_NUM_CHANNELS] =
+{
+    {/* registers       configuration  initial state                  DMA channel    DMA IRQ             SPORT IRQ         handle */
+        {SPORT0_A_REGS, SPORT0_A_CFG,  ADI_SPORT_STATE_UNINITIALIZED, SPORT0A_CHANn, DMA0_CH2_DONE_IRQn, SPORT_A_EVT_IRQn, NULL},
+        {SPORT0_B_REGS, SPORT0_B_CFG,  ADI_SPORT_STATE_UNINITIALIZED, SPORT0B_CHANn, DMA0_CH3_DONE_IRQn, SPORT_B_EVT_IRQn, NULL},
+    },
+};
+
+
+static const ADI_SPORT_CONFIG gSportCfg[ADI_SPORT_NUM_INSTANCES][ADI_SPORT_NUM_CHANNELS] =
+{
+  { /* configuration for SPORT 0 */
+     /* Configuration for half-SPORT A */
+     { /* SPORT_CTL register */
+       ((ADI_CFG_SPORT0A_ENABLE_FSMUXSEL)       << BITP_SPORT_CTL_A_FSMUXSEL)   |
+       ((ADI_CFG_SPORT0A_ENABLE_CKMUXSEL)       << BITP_SPORT_CTL_A_CKMUXSEL)   |
+       ((ADI_CFG_SPORT0A_LSB_FIRST)             << BITP_SPORT_CTL_A_LSBF)       |
+       ((ADI_CFG_SPORT0A_SERIAL_WLEN - 1u)      << BITP_SPORT_CTL_A_SLEN)       |
+       ((ADI_CFG_SPORT0A_INTERNAL_CLK)          << BITP_SPORT_CTL_A_ICLK)       |
+       ((ADI_CFG_SPORT0A_OPERATION_MODE)        << BITP_SPORT_CTL_A_OPMODE)     |
+       ((ADI_CFG_SPORT0A_CLOCK_EDGE)            << BITP_SPORT_CTL_A_CKRE)       |
+       ((ADI_CFG_SPORT0A_FS_REQUIRED)           << BITP_SPORT_CTL_A_FSR)        |
+       ((ADI_CFG_SPORT0A_INTERNAL_FS)           << BITP_SPORT_CTL_A_IFS)        |
+       ((ADI_CFG_SPORT0A_DATA_INDEPENDENT_FS)   << BITP_SPORT_CTL_A_DIFS)       |
+       ((ADI_CFG_SPORT0A_ACTIVE_LOW_FS)         << BITP_SPORT_CTL_A_LFS)        |
+       ((ADI_CFG_SPORT0A_LATE_FS)               << BITP_SPORT_CTL_A_LAFS)       |
+       ((ADI_CFG_SPORT0A_ENABLE_PACKING)        << BITP_SPORT_CTL_A_PACK)       |
+       ((ADI_CFG_SPORT0A_FS_ERROR_OPERATION)    << BITP_SPORT_CTL_A_FSERRMODE)  |
+       ((ADI_CFG_SPORT0A_GATED_CLOCK)           << BITP_SPORT_CTL_A_GCLKEN),
+
+        /* SPORT_DIV register */
+       ((ADI_CFG_SPORT0A_CLOCK_DIVISOR)         << BITP_SPORT_DIV_A_CLKDIV)     |
+       ((ADI_CFG_SPORT0A_FS_DIVISOR)            << BITP_SPORT_DIV_A_FSDIV),
+
+        /* SPORT_CONVT register */
+       ((ADI_CFG_SPORT0A_CONVT_WIDTH)           << BITP_SPORT_CNVT_A_WID)       |
+       ((ADI_CFG_SPORT0A_CONVT_POLARITY)        << BITP_SPORT_CNVT_A_POL)       |
+       ((ADI_CFG_SPORT0A_CONVT_FS_DURATION)     << BITP_SPORT_CNVT_A_CNVT2FS),
+
+       /* Default DMA data size for SPORT */
+       ADI_DMA_WIDTH_4_BYTE,
+
+       /* Default DMA data increment for SPORT */
+       ADI_DMA_INCR_4_BYTE
+     },
+
+     /* Configuration for half-SPORT B */
+     { /* SPORT_CTL register */
+       ((ADI_CFG_SPORT0B_LSB_FIRST)             << BITP_SPORT_CTL_B_LSBF)       |
+       ((ADI_CFG_SPORT0B_SERIAL_WLEN - 1u)      << BITP_SPORT_CTL_B_SLEN)       |
+       ((ADI_CFG_SPORT0B_INTERNAL_CLK)          << BITP_SPORT_CTL_B_ICLK)       |
+       ((ADI_CFG_SPORT0B_OPERATION_MODE)        << BITP_SPORT_CTL_B_OPMODE)     |
+       ((ADI_CFG_SPORT0B_CLOCK_EDGE)            << BITP_SPORT_CTL_B_CKRE)       |
+       ((ADI_CFG_SPORT0B_FS_REQUIRED)           << BITP_SPORT_CTL_B_FSR)        |
+       ((ADI_CFG_SPORT0B_INTERNAL_FS)           << BITP_SPORT_CTL_B_IFS)        |
+       ((ADI_CFG_SPORT0B_DATA_INDEPENDENT_FS)   << BITP_SPORT_CTL_B_DIFS)       |
+       ((ADI_CFG_SPORT0B_ACTIVE_LOW_FS)         << BITP_SPORT_CTL_B_LFS)        |
+       ((ADI_CFG_SPORT0B_LATE_FS)               << BITP_SPORT_CTL_B_LAFS)       |
+       ((ADI_CFG_SPORT0B_ENABLE_PACKING)        << BITP_SPORT_CTL_B_PACK)       |
+       ((ADI_CFG_SPORT0B_FS_ERROR_OPERATION)    << BITP_SPORT_CTL_B_FSERRMODE)  |
+       ((ADI_CFG_SPORT0B_GATED_CLOCK)           << BITP_SPORT_CTL_B_GCLKEN),
+
+        /* SPORT_DIV register */
+       ((ADI_CFG_SPORT0B_CLOCK_DIVISOR)         << BITP_SPORT_DIV_B_CLKDIV)     |
+       ((ADI_CFG_SPORT0B_FS_DIVISOR)            << BITP_SPORT_DIV_B_FSDIV),
+
+        /* SPORT_CONVT register */
+       ((ADI_CFG_SPORT0B_CONVT_WIDTH)           << BITP_SPORT_CNVT_B_WID)       |
+       ((ADI_CFG_SPORT0B_CONVT_POLARITY)        << BITP_SPORT_CNVT_B_POL)       |
+       ((ADI_CFG_SPORT0B_CONVT_FS_DURATION)     << BITP_SPORT_CNVT_B_CNVT2FS),
+
+       /* Default DMA data size for SPORT */
+       ADI_DMA_WIDTH_4_BYTE,
+
+       /* Default DMA data increment for SPORT */
+       ADI_DMA_INCR_4_BYTE
+     }
+  }
+};
+
+/*! \endcond */
+
+/*=============  C O D E  =============*/
+
+extern void SPORT0A_Int_Handler(void);          /*!< Interrupt handler for the SPORT0-A */
+extern void SPORT0B_Int_Handler(void);          /*!< Interrupt handler for the SPORT0-B */
+extern void DMA_SPORT0A_Int_Handler(void);      /*!< DMA handler for the SPORT0-A */
+extern void DMA_SPORT0B_Int_Handler(void);      /*!< DMA handler for the SPORT0-B */
+
+/*=============  L O C A L   F U N C T I O N S =============*/
+
+/*=============  P U B L I C   F U N C T I O N S =============*/
+
+/**
+ * @brief       Initialization function for SPORT device.
+ * @details     Initialization function for SPORT device. This function must be
+ *              called before operating any SPORT device.
+ *
+ * @param [in]  nDevNum         SPORT Device instance to be opened.
+ * @param [in]  eChannel        Channel ID of the SPORT device (A or B)
+ * @param [in]  eDirection      Direction of the SPORT operation (i.e Rx or Tx)
+ * @param [in]  pMemory         Pointer to a 32 bit aligned buffer containing
+ *                              ADI_SPORT_MEMORY_SIZE bytes. This buffer is
+ *                              required by the SPORT driver for its operations.
+ *                              The "ADI_SPORT_MEMORY_SIZE" varies based on the
+ *                              configuration.
+ * @param [in]  nMemSize        Size of the buffer to which "pMemory" points.
+ * @param [out] phDevice        Pointer to a location where a handle to the
+ *                              opened SPORT driver can be stored. This handle
+ *                              will be used to identity a SPORT device when
+ *                              calling SPORT management functions.
+ *
+ * @return      Status
+ * - #ADI_SPORT_SUCCESS                 Successful device initialization.
+ * - #ADI_SPORT_DEVICE_IN_USE           Device already initialized.
+ * - #ADI_SPORT_FAILED                  Failed initialize a semaphore for managing device.
+ * - #ADI_SPORT_INVALID_DEVICE_NUM      Invalid SPORT device identifier
+ * - #ADI_SPORT_INVALID_NULL_POINTER    Invalid pointer (callback function or device handle).
+ *
+ * @sa  adi_sport_Close()
+ */
+ADI_SPORT_RESULT adi_sport_Open(
+    const uint32_t              nDevNum,
+    const ADI_SPORT_CHANNEL     eChannel,
+    const ADI_SPORT_DIRECTION   eDirection,
+    void                        *pMemory,
+    const uint32_t              nMemSize,
+    ADI_SPORT_HANDLE * const    phDevice
+    )
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+
+    assert(ADI_SPORT_MEMORY_SIZE == sizeof(ADI_SPORT_DEVICE));  /* validate the memory size macro */
+#ifdef ADI_DEBUG
+    if (nDevNum >= ADI_SPORT_NUM_INSTANCES)
+    {
+        result = ADI_SPORT_INVALID_DEVICE_NUM;          /* SPORT identifier must be within [0..ADI_SPORT_NUM_INSTANCES-1] */
+    }
+    else if (phDevice == NULL)
+    {
+        result = ADI_SPORT_INVALID_NULL_POINTER;        /* the pointer to device handle must be valid */
+    }
+    else if (ADI_SPORT_MEMORY_SIZE != nMemSize)
+    {
+        result = ADI_SPORT_FAILED;
+    }
+    else if (ADI_SPORT_STATE_UNINITIALIZED != gSportDevInfo[nDevNum][eChannel].eState)
+    {
+        result = ADI_SPORT_DEVICE_IN_USE;               /* the device instance must not be in use */
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        ADI_SPORT_DEVICE * pDevice = pMemory;           /* Pointer to the SPORT device instance (from supplied memory) */
+        ADI_SPORT_DEVICE_INFO * sportInfo = &gSportDevInfo[nDevNum][eChannel];  /* SPORT info for HSPORT A or HSPORT B */
+        ADI_SPORT_CONFIG const * sportCfg = &gSportCfg[nDevNum][eChannel];      /* SPORT configuration for HSPORT A or HSPORT B */
+
+        assert(eChannel < ADI_SPORT_NUM_CHANNELS);
+
+        memset(pMemory, 0, nMemSize);           /* clear the device instance data before initializing it */
+
+        pDevice->pSportInfo = sportInfo;        /* Initialize the pointer which provides the device information (HSPORT A or HSPORT B). */
+        pDevice->eDirection = eDirection;       /* Initialize the direction (BEFORE calling sport_Configure)*/
+        pDevice->nHwError = (uint32_t) ADI_SPORT_HW_NO_ERR;
+
+        adi_dma_Init();                         /* Set up the DMA Controller. */
+        sport_Init(pDevice);                    /* Initialize the data transmission buffers */
+        sport_Configure(pDevice,sportCfg);      /* Configure the SPORT */
+
+        if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(sportInfo->eDMAChnlID, sport_DmaErrorCallback, pDevice))
+        {
+            adi_sport_Close(pDevice);
+            result = ADI_SPORT_DMA_REGISTER_FAILED;
+        }
+
+        if (ADI_SPORT_SUCCESS == result)
+        {
+            ADI_SPORT_DEVICE_INFO * devInfo = &gSportDevInfo[nDevNum][eChannel];
+
+            /* Create a "semaphore" (varies per OS) used for blocking buffer resource management. */
+            if (ADI_HALF_SPORT_A == eChannel)
+            {
+                SEM_CREATE(&pDevice->sportChannel, "SPORT0_A_SEM", ADI_SPORT_FAILED);
+            }else{
+                SEM_CREATE(&pDevice->sportChannel, "SPORT0_B_SEM", ADI_SPORT_FAILED);
+            }
+
+            /* Change the state of the specified device */
+            ADI_INT_STATUS_ALLOC();
+            ADI_ENTER_CRITICAL_REGION();
+                devInfo->eState = ADI_SPORT_STATE_INITIALIZED;
+                devInfo->hDevice = pDevice;
+            ADI_EXIT_CRITICAL_REGION();
+            *phDevice = pDevice;                /* Return the device handle to the application */
+        }
+    }
+
+    return result;
+}
+
+/**
+ * @brief       Closes the operation of specified SPORT device.
+ *
+ * @details     Closes the operation of specified SPORT device.
+ *              Device need to be opened again for any further use.
+ *
+ * @param [in]  hDevice SPORT device handle whose operation is to be closed.
+ *                      This handle was obtained when a SPORT device is opened
+ *                      successfully.
+ *
+ * @return      Status
+ *
+ *      - #ADI_SPORT_SUCCESS            Successfully closed the specified device.
+ *      - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle.
+ *      - #ADI_SPORT_FAILED         [D] SPORT device internal error.
+ *
+ * @note        It is user's responsibility to free/reuse the memory supplied
+ *              during the opening of the device.
+ *
+ * @sa          adi_sport_Open()
+ */
+ADI_SPORT_RESULT adi_sport_Close(ADI_SPORT_HANDLE const hDevice)
+{
+    ADI_SPORT_RESULT    result = ADI_SPORT_SUCCESS;             /* return code */
+    ADI_SPORT_DEVICE *  pDevice = (ADI_SPORT_DEVICE *) hDevice; /* Pointer to SPORT device instance */
+#ifdef ADI_DEBUG
+    if (ADI_SPORT_SUCCESS == (result=ValidateHandle(pDevice)))  /* Validate the given handle */
+#endif /* ADI_DEBUG */
+    {
+        ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo;
+
+        /* Free up the device */
+        ADI_INT_STATUS_ALLOC();
+        ADI_ENTER_CRITICAL_REGION();
+            NVIC_DisableIRQ(pSportInfo->eIRQn);                 /* Disable SPORT event interrupts. */
+            NVIC_DisableIRQ(pSportInfo->eDMAn);                 /* Disable DMA SPORT interrupts. */
+            pSportInfo->eState  = ADI_SPORT_STATE_UNINITIALIZED;
+            pSportInfo->hDevice = NULL;                         /* Free up the device memory. */
+        ADI_EXIT_CRITICAL_REGION();
+
+        SEM_DELETE(&pDevice->sportChannel, ADI_SPORT_FAILED);   /* Delete SPORT channel semaphore. */
+
+        adi_dma_RegisterCallback(pSportInfo->eDMAChnlID, NULL, NULL);   /* unregister the callback function in the DMA error handler */
+
+        pSportInfo->pSportRegs->CTL_A = 0u;
+    }
+    return result;
+}
+
+/**
+ * @brief       Submit the buffer for transmitting/receiving the data. This function can
+ *              be used to submit the buffers for both transmitting and receiving. It will
+ *              be returned after successfully submitting the buffer for transmitting data.
+ *              User will be notified if a call back function is registered with an event code
+ *              #ADI_SPORT_EVENT_RX_BUFFER_PROCESSED or #ADI_SPORT_EVENT_TX_BUFFER_PROCESSED"
+ *              depending on the direction in which device is operating.
+ *
+ * @param [in]  hDevice   Device handle to SPORT device is obtained when a SPORT device is opened
+ *                        successfully.
+ *
+ * @param [in]  pBuffer   Pointer to buffer from where data need to be transmitted OR to which
+ *                        received data need to to be written.
+ *
+ * @param [in]  nNumBytes Size in bytes of the data to be transmitted/received.
+ * @param [in]  bDMA      True if the buffer must be processed through DMA-driven SPORT operations.
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                        Buffer successfully submitted to the specified SPORT.
+ *  - #ADI_SPORT_INVALID_HANDLE                 Invalid SPORT device handle.
+ *  - #ADI_SPORT_INVALID_PARAMETER              Number of bytes is too large for a SPORT transfer or the buffer is mis-aligned
+ *  - #ADI_SPORT_BUFFERS_NOT_SUBMITTED          All the SPORT buffers are already being used
+ *
+ * @sa          adi_sport_GetBuffer()
+ *
+ */
+ADI_SPORT_RESULT adi_sport_SubmitBuffer(ADI_SPORT_HANDLE const hDevice,
+                                        void *           const pBuffer,
+                                        uint32_t         const nNumBytes,
+                                        bool             const bDMA
+                                        )
+{
+    ADI_SPORT_DEVICE *  pDevice = (ADI_SPORT_DEVICE *) hDevice;         /* pointer to SPORT device instance */
+    ADI_SPORT_RESULT    result = ADI_SPORT_SUCCESS;                     /* return code */
+
+#ifdef ADI_DEBUG
+    ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg;      /* short cut to SPORT configuration */
+
+    if(ADI_SPORT_SUCCESS != (result=ValidateHandle(hDevice)))           /* validate the given handle */
+    {
+    }
+    else if (  ((2u >= nNumBytes) && ((pDevice->pSportInfo->pSportRegs->CTL_A & BITM_SPORT_CTL_A_OPMODE) != 0u))
+            || (0u != (nNumBytes & ~(BITM_SPORT_NUMTRAN_A_VALUE)))      /* buffer size limited by SPORT transmission capabilities */
+            )
+    {
+        result = ADI_SPORT_INVALID_PARAMETER;
+    }
+    else
+#endif /* ADI_DEBUG */
+    /* Check that there is a free buffer to use for this transmit operation. pFreeBuffer
+       is the next buffer available, so if it is in use we can make the assumption that
+       there are no buffers available. The start address is set to NULL once the buffer
+       has finished being processed in "adi_sport_GetBuffer()".
+    */
+    if (NULL != pDevice->sportChannel.pFreeBuffer->pStartAddress)
+    {
+        result = ADI_SPORT_BUFFERS_NOT_SUBMITTED;
+    }
+    else
+    {
+#ifdef ADI_DEBUG
+        const uint32_t addr = (uint32_t) pBuffer;
+
+        if (true == bDMA)
+        {
+            /**
+             * Using SPORT configuration data, let's define information such as data
+             * size in bytes, data number, number of data and bytes in the DMA transfer
+             * being prepared, last byte position for the DMA transfer
+             *
+             * It's important to keep in mind that for buffer that contain too many data
+             * multiple DMA transfers are needed: it's up to the application to split the
+             * DMA requests in requests which have an appropriate number of data.
+             */
+            const uint32_t dataSizeInBytes = GetBytesPerSportData(pSportCfg->CTL);
+            const uint32_t full = nNumBytes / dataSizeInBytes;          /* number of full data to transmit/receive */
+            const uint32_t partial = nNumBytes % dataSizeInBytes;       /* number of partial data to transmit/receive */
+            const uint32_t misaligned = addr % dataSizeInBytes;         /* number of data to transmit/receive */
+
+            if (  (full > DMA_TRANSFER_LIMIT)                           /* number of data to process too large for DMA */
+               || (0u != partial)                                       /* buffer size not a multiple of dataSizeInBytes */
+               || (0u != misaligned)                                    /* buffer mis-aligned */
+               )
+            {
+                result = ADI_SPORT_INVALID_PARAMETER;
+            }
+        } else {
+            const uint32_t misAligned = addr % 4u;
+            const uint32_t invalidNum = nNumBytes % 4u;
+
+            if (  (0u != misAligned)                                    /* mis-aligned buffer */
+               || (0u != invalidNum)                                    /* number of bytes not a multiple of 32-bit  */
+               )
+            {
+                result = ADI_SPORT_INVALID_PARAMETER;                   /* reject the buffer submission */
+            }
+        }
+        if (ADI_SPORT_SUCCESS == result)
+#endif /* ADI_DEBUG */
+        {
+            ADI_DT_CHANNEL * pSportChnl = &pDevice->sportChannel;
+
+            pSportChnl->pFreeBuffer->pStartAddress = pBuffer;   /* Set the start address of the data buffer */
+            pSportChnl->pFreeBuffer->nCount        = nNumBytes; /* Set the buffer size */
+            pSportChnl->pFreeBuffer->nIndex        = 0u;        /* Initialize the buffer index to zero (1st data in buffer) */
+            pSportChnl->pFreeBuffer->bDMA          = bDMA;      /* Set the DMA boolean value. */
+            pSportChnl->pFreeBuffer->bInUse        = true;      /* this buffer is now being used by the SPORT */
+
+            /* Now that this "pFreeBuffer" is no longer free for use, update the
+            "pFreeBuffer" to the next buffer. "pFreeBuffer" will only be updated
+            during the process of submitting a buffer or a read/write operation.
+            */
+            pSportChnl->pFreeBuffer = pSportChnl->pFreeBuffer->pNextBuffer;
+
+            /* Set the data transfer mode in case it was #ADI_DT_MODE_NONE. This
+            will be set back to #ADI_DT_MODE_NONE once this transaction is complete.
+            Then, if a buffer is not currently active, set up the interrupts for
+            this transaction. Otherwise if a buffer is currently active, this will
+            be taken care of in the ISR.
+            */
+            if (pSportChnl->eDataTranferMode == ADI_DT_MODE_NONE)   /* if the SPORT is available for a transmission */
+            {
+                pSportChnl->eDataTranferMode = ADI_DT_MODE_NONBLOCKING;
+
+                /* call an appropriate function based on mode in which device is operating */
+                if (true == bDMA)                                   /* select a DMA driven or a core driven non-blocking transmission */
+                {
+                    result = sport_SubmitBufferDmaMode(pDevice, pSportChnl->pFillBuffer);
+                } else {
+                    result = sport_SubmitBufferIntMode(pDevice, pSportChnl->pFillBuffer);
+                }
+            }
+
+            if(ADI_SPORT_SUCCESS != result)                             /* if an error occurred...*/
+            {
+                pSportChnl->eDataTranferMode = ADI_DT_MODE_NONE;        /* SPORT is available */
+            }
+        }
+    }
+
+    return result;
+}
+
+/*
+ * @brief       Submit a buffer for SPORT Rx or Tx DMA driven transmission.
+ *
+ * @param [in]  pDevice Pointer to SPORT device.
+ *
+ * @param [in]  pBuffer Pointer to data transfer buffer information.
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                 buffer successfully submitted to the DMA associated with the SPORT.
+ *  - #ADI_SPORT_BUFFERS_NOT_SUBMITTED   Failed to submit the buffer to the DMA associated with the SPORT.
+ */
+/** Function prototype for submitting a buffer for SPORT Rx or Tx DMA driven transmission */
+static ADI_SPORT_RESULT sport_SubmitBufferDmaMode(ADI_SPORT_DEVICE * pDevice,
+                                                  ADI_DT_BUFF_INFO * pBuff)
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+    ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo;           /* short cut to SPORT information */
+    ADI_SPORT_CONFIG * pSportCfg = &pSportInfo->sportCfg;               /* short cut to SPORT configuration */
+
+#ifdef ADI_DEBUG
+    if (  (pBuff != pDevice->sportChannel.pFillBuffer)                  /* a submitted buffer should always be the current fill buffer */
+       || (true != pBuff->bInUse)                                       /* Processed buffers should already be marked as being used */
+       || (0u != pBuff->nIndex)                                         /* processing should start from index 0 */
+       )
+    {
+        result = ADI_SPORT_FAILED;
+    }
+    else
+#endif
+    {
+        volatile ADI_SPORT_TypeDef* pSportRegs = pSportInfo->pSportRegs;/* short cut to SPORT registers */
+        const uint32_t dmaChnlId = (uint32_t) pSportInfo->eDMAChnlID;   /* identifier for the DMA channel to be used */
+        const uint32_t dmaChnlBit = (1u << dmaChnlId);                  /* bit representing the DMA channel to be used */
+
+        /**
+         * Using SPORT configuration data, let's define information such as data
+         * size in bytes, data number, number of data and bytes in the DMA transfer
+         * being prepared, last byte position for the DMA transfer
+         *
+         * It's important to keep in mind that for buffer that contain too many data
+         * multiple DMA transfers are needed, so a buffer may have had part of its
+         * content already DMA-transferred: nIndex defines the position of the first
+         * byte in a buffer that has not been DMA-transferred yet.
+         */
+        const uint32_t dmaIncNone = (uint32_t) ADI_DMA_INCR_NONE;
+        const uint32_t dmaDcc = (uint32_t) DMA_ENUM_CTL_CYCLE_CTL_BASIC;
+        const uint32_t bytesPerData = GetBytesPerSportData(pSportCfg->CTL);
+
+        const uint32_t dataSizeInBytes = (1u << pSportCfg->DMA_WIDTH);  /* number of bytes in each data to transmit/receive */
+              uint32_t numDmaData = pBuff->nCount / dataSizeInBytes;    /* number of DMA data to transmit/receive */
+        const uint32_t dmaDataEnd = (pBuff->nCount - dataSizeInBytes);  /* position of last <8,16,32>-bit data in the DMA transfer being setup */
+        const uint32_t startAddress = (uint32_t) pBuff->pStartAddress;  /* address of the first byte in the data buffer */
+        const uint32_t numSportData = pBuff->nCount / bytesPerData;     /* number of SPORT data to transmit/receive */
+
+        assert(pBuff->nCount == (numSportData * bytesPerData));
+        assert(numSportData <= 0xFFFu);
+        assert(0u == (pBuff->nCount % dataSizeInBytes));
+        assert(numDmaData <= DMA_TRANSFER_LIMIT);
+        assert((ADI_SPORT_DIR_RX == pDevice->eDirection) || (ADI_SPORT_DIR_TX == pDevice->eDirection));
+        SPORT_CHECK_CFG_CTL(pSportCfg->CTL);
+
+        pSportRegs->CTL_A = 0u;                                         /* make sure SPORT is disable */
+        pADI_DMA0->SRCADDR_CLR = dmaChnlBit;                             /* Clear source address decrement for TX channel DMA. */
+        pADI_DMA0->EN_SET = dmaChnlBit;                                 /* Enable channel DMA. */
+        pADI_DMA0->RMSK_CLR = dmaChnlBit;                               /* Enable SPORT peripheral to generate DMA requests. */
+        pADI_DMA0->ALT_CLR = dmaChnlBit;                                /* Set the primary control data structure as the current DMA descriptor. */
+        pADI_DMA0->PRI_SET = dmaChnlBit;
+
+        if (ADI_SPORT_DIR_RX == pDevice->eDirection)
+        {
+            pPrimaryCCD[dmaChnlId].DMASRCEND = (uint32_t) &pSportRegs->RX_A;    /* address of the last src data in the DMA transfer being setup */
+            pPrimaryCCD[dmaChnlId].DMADSTEND = startAddress + dmaDataEnd;       /* address of the last dst data in the DMA transfer being setup */
+            pPrimaryCCD[dmaChnlId].DMACDC    =
+              (pSportCfg->DMA_INC << ((uint32_t)DMA_BITP_CTL_DST_INC))  |       /* destination address incremented by N bytes */
+              (dmaIncNone         << ((uint32_t)DMA_BITP_CTL_SRC_INC));         /* source address not incremented */
+        }
+        else                                                                    /* ADI_SPORT_DIR_TX */
+        {
+            pPrimaryCCD[dmaChnlId].DMASRCEND = startAddress + dmaDataEnd;       /* address of the last src data in the DMA transfer being setup */
+            pPrimaryCCD[dmaChnlId].DMADSTEND = (uint32_t) &pSportRegs->TX_A;    /* address of the last dst data in the DMA transfer being setup */
+            pPrimaryCCD[dmaChnlId].DMACDC    =
+              (dmaIncNone         << ((uint32_t)DMA_BITP_CTL_DST_INC))  |       /* destination address not incremented */
+              (pSportCfg->DMA_INC << ((uint32_t)DMA_BITP_CTL_SRC_INC));         /* source address incremented by N byte */
+
+            /**
+             * Fix for data transmission when DMA is used with packed data.
+             */
+            if (numDmaData < numSportData)
+            {
+                pPrimaryCCD[dmaChnlId].DMASRCEND = startAddress + dmaDataEnd + dataSizeInBytes;       /* address of the last src data in the DMA transfer being setup */
+                numDmaData++;
+            }
+        }
+        pPrimaryCCD[dmaChnlId].DMACDC |=
+          (pSportCfg->DMA_WIDTH << ((uint32_t)DMA_BITP_CTL_SRC_SIZE))   |       /* source data size in bytes */
+          (0u                   << ((uint32_t) DMA_BITP_CTL_R_POWER))   |
+          ((numDmaData - 1u)    << ((uint32_t)DMA_BITP_CTL_N_MINUS_1))  |       /* number of DMA transfers (minus 1) */
+          (dmaDcc               << ((uint32_t)DMA_BITP_CTL_CYCLE_CTL));
+
+        ADI_INT_STATUS_ALLOC();
+        ADI_ENTER_CRITICAL_REGION();
+            pDevice->pSportInfo->eState = ADI_SPORT_STATE_DATA_FLOW_ENABLED;
+            pSportRegs->NUMTRAN_A = numSportData;
+
+            /* Enable SPORT DMA request interrupt for the SPORT tx channel. */
+            NVIC_ClearPendingIRQ(pSportInfo->eIRQn);
+            NVIC_ClearPendingIRQ(pSportInfo->eDMAn);
+
+            uint32_t ien_a = ((uint32_t)BITM_SPORT_IEN_A_SYSDATERR) |
+                             ((uint32_t)BITM_SPORT_IEN_A_FSERRMSK) |
+                             ((uint32_t)BITM_SPORT_IEN_A_DERRMSK);
+            if (ADI_SPORT_DIR_RX == pDevice->eDirection)
+            {
+                /* Allow SPORT DMA interrupt handling to mark SPORT Rx as complete */
+                NVIC_EnableIRQ(pSportInfo->eDMAn);
+            }
+            else
+            {
+              /* SPORT DMA Tx is complete when TFI is raised: enable TFI */
+                ien_a |= ((uint32_t)BITM_SPORT_IEN_A_TF);
+            }
+
+            NVIC_EnableIRQ(pSportInfo->eIRQn);
+            
+            pSportRegs->IEN_A = ien_a;
+            pSportRegs->CTL_A = pSportCfg->CTL |
+                                ((uint32_t)BITM_SPORT_CTL_A_SPEN) |
+                                ((uint32_t)BITM_SPORT_CTL_A_DMAEN);
+        ADI_EXIT_CRITICAL_REGION();
+
+        SPORT_CHECK_CFG_CTL(pSportCfg->CTL);
+    }
+    return result;
+}
+
+/** Function prototype for  */
+/*
+ * @brief       Submit a buffer for SPORT Rx or Tx core driven transmission.
+ *
+ * @details     Submit a buffer for SPORT Rx or Tx core driven transmission.
+ *              The buffer must be 32-bit aligned and contain N * 32-bit data.
+ *
+ * @param [in]  pDevice Pointer to SPORT device.
+ *
+ * @param [in]  pBuffer Pointer to data transfer buffer information.
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                   Successfully submitted the buffer for data transfer.
+ *
+ *  - #ADI_SPORT_BUFFERS_NOT_SUBMITTED     No free descriptor for data transfer.
+ *
+ *
+ */
+static ADI_SPORT_RESULT sport_SubmitBufferIntMode(ADI_SPORT_DEVICE * pDevice, ADI_DT_BUFF_INFO * pBuff)
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+#ifdef ADI_DEBUG
+    if (  (pBuff != pDevice->sportChannel.pFillBuffer)  /* a submitted buffer should always be the current fill buffer */
+       || (true != pBuff->bInUse)                       /* Processed buffers should already be marked as being used */
+       || (0u != pBuff->nIndex)                         /* processing should start from index 0 */
+       )
+    {
+        result = ADI_SPORT_FAILED;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg;
+        volatile ADI_SPORT_TypeDef * pSportRegs = pDevice->pSportInfo->pSportRegs;
+        uint32_t ctl = pSportCfg->CTL;
+        uint32_t bytesPerData = GetBytesPerSportData(ctl);
+
+        /**
+         * Buffer can be too large for being processed in one submission.
+         * Consequently, if pBuff->nCount requires more than than 12-bit,
+         * multiple buffer submissions will be required by the application;
+         * the SPORT driver cannot process large buffers implicitly.
+         * The number of bytes in submitted buffers must be a multiple of 4
+         * because data are processed by the SPORT driver as 32-bit data.
+         */
+
+        /* use the SPORT configuration to setup the SPORT registers */
+
+        pBuff->nCount /= bytesPerData;                  /* number of data to be transmitted */
+
+#ifdef ADI_DEBUG
+        uint32_t pack = SPORT_GET_PACKEN(pSportCfg->CTL);
+        assert( ((9u > bytesPerData) && (1u == pack)) || ((17u > bytesPerData) && (2u == pack)) || (0u == pack));
+#endif
+        assert(pBuff->nCount <= 0xFFFu);
+        SPORT_CHECK_CFG_CTL(pSportCfg->CTL);
+
+        ADI_INT_STATUS_ALLOC();
+        ADI_ENTER_CRITICAL_REGION();
+            pSportRegs->CTL_A = 0u;                     /* make sure SPORT is disable */
+            pSportRegs->NUMTRAN_A = pBuff->nCount;
+            pDevice->pSportInfo->eState = ADI_SPORT_STATE_DATA_FLOW_ENABLED;
+
+            /* Enable SPORT Interrupt. */
+            NVIC_ClearPendingIRQ(pDevice->pSportInfo->eIRQn);
+            NVIC_EnableIRQ(pDevice->pSportInfo->eIRQn);
+            pSportRegs->IEN_A |= ((uint32_t) ( BITM_SPORT_IEN_A_DATA
+                                             | BITM_SPORT_IEN_A_SYSDATERR
+                                             | BITM_SPORT_IEN_A_FSERRMSK
+                                             | BITM_SPORT_IEN_A_DERRMSK
+                                             | BITM_SPORT_IEN_A_TF
+                                             )
+                                 );
+            pSportRegs->CTL_A =  pSportCfg->CTL | ((uint32_t)BITM_SPORT_CTL_A_SPEN);
+        ADI_EXIT_CRITICAL_REGION();
+    }
+    return result;
+}
+
+/**
+ * @brief       This function returns the address of a processed buffer. This
+ *              is a blocking function: it waits until a buffer has been dealt
+ *              with. This function returns an error if a callback function is
+ *              registered. #adi_sport_IsBufferAvailable can be used as a peek
+ *              function to know whether a buffer is available.
+ *
+ * @param [in]  hDevice  Device handle to SPORT device, obtained when a SPORT
+ *                       device is openedsuccessfully.
+ *
+ * @param [out] ppBuffer Pointer to a location where the the address of the
+ *                       buffer is to be written. Contains the address of an
+ *                       "empty" buffer (i.e the content of the buffer is
+ *                       transmitted) OR "filled" buffer which contains the
+ *                       received data.
+ *
+ * @param [out] pHwError Pointer to 32-bit value reporting SPORT/DMA events
+ *                       that can occur when processing buffer ppBuffer.
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                Successfully returned. ppBuffer points
+ *                                      to the address of the buffer.
+ *
+ *  - #ADI_SPORT_FAILED                 Failed to get the buffer since device
+ *                                      is operating in call back mode.
+ *                                      ppBuffer points NULL.
+ *
+ *  - #ADI_SPORT_HW_ERROR               SPORT hardware or DMA error detected
+ *
+ *  - #ADI_SPORT_INVALID_HANDLE   [D]   Invalid SPORT device handle.
+ *
+ * @sa          adi_sport_SubmitBuffer()
+ * @sa          adi_sport_IsBufferAvailable()
+ *
+ */
+ADI_SPORT_RESULT adi_sport_GetBuffer(ADI_SPORT_HANDLE   const hDevice,
+                                     void **            const ppBuffer,
+                                     uint32_t *               pHwError)
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+    ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE*) hDevice;   /* Pointer to SPORT device instance */
+
+    *ppBuffer = NULL;
+#ifdef ADI_DEBUG
+    if (ADI_SPORT_SUCCESS != (result=ValidateHandle(pDevice)))  /* Validate the given handle */
+    {
+    }
+    else
+#endif /* ADI_DEBUG */
+    if (NULL != pDevice->pfCallback)
+    {
+        result = ADI_SPORT_FAILED;
+    } else {
+        ADI_DT_CHANNEL * pSportChnl = &pDevice->sportChannel;
+
+        SEM_PEND(pSportChnl,ADI_SPORT_FAILED);                          /* wait for a submitted buffer to be processed */
+
+        ADI_INT_STATUS_ALLOC();
+        ADI_ENTER_CRITICAL_REGION();
+            *pHwError = pDevice->nHwError;
+            pDevice->nHwError = 0u;
+            *ppBuffer  = pSportChnl->pActiveBuffer->pStartAddress;      /* return the buffer start address in *ppBuffer */
+            pSportChnl->pActiveBuffer->pStartAddress = NULL;            /* clear the free buffer address */
+            pSportChnl->pActiveBuffer = pSportChnl->pActiveBuffer->pNextBuffer;
+        ADI_EXIT_CRITICAL_REGION();
+        if (0u != *pHwError)
+        {
+            result = ADI_SPORT_HW_ERROR;
+        }
+    }
+    return result;
+}
+
+/**
+ * @brief       Peek function to know whether an empty/filled buffer is available. Call to this
+ *              function is valid only if the call back function is not registered. Call to this
+ *              function results in error if a call back function is registered.
+ *
+ * @param [in]  hDevice      Device handle to SPORT device obtained when a SPORT device is opened
+ *                           successfully.
+ *
+ * @param [out] pbAvailable  Pointer to a boolean variable. Contains "True" if there is an
+ *                           empty/filled buffer and a call to #adi_sport_GetBuffer is ensured to be
+ *                           successful. Contains "false" if there is no empty buffer.
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                Successfully retrieved the status of availability of the buffer.
+ *  - #ADI_SPORT_INVALID_HANDLE         Failed to retrieve the status of the buffer availability.
+ *  - #ADI_SPORT_OPERATION_NOT_ALLOWED  Function cannot be called (no buffer to be processed or callback function registered).
+ *  - ADI_SPORT_PERIPHERAL_ERROR        Hardware error detected
+ *
+ * @sa          adi_sport_GetBuffer()
+ * @sa          adi_sport_GetBuffer()
+ *
+ */
+ADI_SPORT_RESULT adi_sport_IsBufferAvailable(ADI_SPORT_HANDLE const hDevice,
+                                             bool *           const pbAvailable)
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+    ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE*) hDevice;   /* Pointer to SPORT device instance */
+
+    *pbAvailable = false;
+#ifdef ADI_DEBUG
+    if (ADI_SPORT_SUCCESS != (result=ValidateHandle(pDevice)))  /* Validate the given handle */
+    {
+    }
+    else
+#endif /* ADI_DEBUG */
+    if (NULL != pDevice->pfCallback)
+    {
+        result = ADI_SPORT_OPERATION_NOT_ALLOWED;
+    }
+    else
+    {
+        ADI_DT_BUFF_INFO * pActiveBuffer = pDevice->sportChannel.pActiveBuffer;
+
+        if (pActiveBuffer->pStartAddress == NULL)
+        {
+            result = ADI_SPORT_OPERATION_NOT_ALLOWED;
+        }
+        else if (false == pActiveBuffer->bInUse)                /* this buffer has been processed by the SPORT */
+        {
+            *pbAvailable = true;
+        }
+        else
+        {
+        }
+    }
+    return result;
+}
+
+/**
+ * @brief       Register and unregister a Callback function with the SPORT device driver.
+ *              A registered call back function will be called, if not NULL, when a buffer
+ *              is processed OR hardware error(s) encountered.
+ *
+ * @param [in]  hDevice     Device handle to SPORT device is obtained when a SPORT device is opened
+ *                          successfully.
+ *
+ * @param [in]  pfCallback  Function pointer to Callback function. Passing a NULL pointer will
+ *                          unregister the call back function.
+ *
+ * @param [in]  pCBparam    Call back function parameter.
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                    Successfully registered specified callback function.
+ *
+ *  - #ADI_SPORT_INVALID_HANDLE        [D]  Invalid SPORT device handle.
+ *
+ *  - #ADI_SPORT_OPERATION_NOT_ALLOWED [D]  Operation is not allowed when data flow is enabled.
+ *
+ */
+ADI_SPORT_RESULT adi_sport_RegisterCallback(ADI_SPORT_HANDLE    const hDevice,
+                                            ADI_CALLBACK        const pfCallback,
+                                            void *              const pCBparam)
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+    ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice;   /* Pointer to SPORT device instance */
+#ifdef ADI_DEBUG
+    /* Validate the given handle */
+    if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice)))
+    {
+    }
+    /* Check if the data flow is already enabled */
+    else if (ADI_SPORT_STATE_DATA_FLOW_ENABLED == pDevice->pSportInfo->eState)
+    {
+        /* Not allowed to register a callback if the data flow is enabled. */
+        result = ADI_SPORT_OPERATION_NOT_ALLOWED;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        ADI_INT_STATUS_ALLOC();
+        ADI_ENTER_CRITICAL_REGION();
+            pDevice->pfCallback = pfCallback;   /* Store the address of the callback function */
+            pDevice->pCBParam   = pCBparam;     /* Store the call back parameter */
+        ADI_EXIT_CRITICAL_REGION();
+    }
+    return result;
+}
+
+/**
+ * @brief       Sets data format for the specified SPORT device.
+ *
+ * @details     Sets data type,Big endian (MSB first) OR Little endian (LSB first) and word
+ *              length(in bits) for the specified SPORT device.This function return error if the
+ *              device is already enabled.
+ *
+ * @param [in]  hDevice              Device handle to SPORT device.
+ *
+ * @param [in]  nWordLength          Specify the word size of the data. Valid range is from
+ *                                   4(nWordLength = 3) to 32(nWordLength =31).
+ *
+ * @param [in]  bLSBFirst            Configure the specified SPORT device to operate either LSB
+ *                                   first or MSB first.
+ * \n
+ * \n                                true : LSB first (Little endian) .
+ * \n
+ * \n                                false : MSB first (Big endian)
+ *
+ * @param [in]  ePackMode            Mode of packging need to configured. Please refer #ADI_SPORT_PACKING_MODE.
+ *
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                    Successfully configured the device to operate in
+ *                                          specified data format.
+ *
+ *  - #ADI_SPORT_INVALID_HANDLE        [D]  Invalid SPORT device handle.
+ *
+ *  - #ADI_SPORT_INVALID_WORD_LENGTH   [D]  Invalid word size.
+ *
+ *  - #ADI_SPORT_OPERATION_NOT_ALLOWED [D]  Operation is not allowed when data flow is enabled.
+ *
+ */
+ADI_SPORT_RESULT adi_sport_ConfigData(ADI_SPORT_HANDLE const            hDevice,
+                                      const uint8_t                     nWordLength,
+                                      const ADI_SPORT_PACKING_MODE      ePackMode,
+                                      const bool                        bLSBFirst
+                                      )
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+    ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice;                  /* Pointer to SPORT device instance */
+#ifdef ADI_DEBUG
+    if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice)))
+    {
+    }
+    if(pDevice->pSportInfo->eState == ADI_SPORT_STATE_DATA_FLOW_ENABLED)        /* Not allowed to change when data flow is enabled */
+    {
+        result = ADI_SPORT_OPERATION_NOT_ALLOWED;
+    }
+    else
+#endif /* ADI_DEBUG */
+    if (nWordLength > SPORT_WORD_TRANSFER_LENGTH)
+    {
+        result = ADI_SPORT_INVALID_WORD_LENGTH;
+    }
+    else
+    {
+        ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo;               /* short cut to SPORT information */
+        ADI_SPORT_CONFIG * pSportCfg = &pSportInfo->sportCfg;                   /* short cut to SPORT configuration */
+        const uint32_t bytesPerData = ((nWordLength < 9u) ? (1u) : ((nWordLength < 17u) ? (2u) : (4u)));
+
+        const uint32_t wordPos = (uint32_t) BITP_SPORT_CTL_A_SLEN;
+        const uint32_t wordLen = (uint32_t) nWordLength;
+        const uint32_t ctlSlen = (wordLen - 1u) << wordPos;
+        const uint32_t packMode = (uint32_t) ePackMode;
+        const uint32_t ctlSlenBits = (0x1Fu  << wordPos);
+        const uint32_t ctlDataMask = ~(BITM_SPORT_DATA_CONFIG | ctlSlenBits | BITM_SPORT_CTL_A_LSBF);
+
+        uint32_t ctl = pDevice->pSportInfo->sportCfg.CTL;
+        ctl &= ctlDataMask;                             /* clear all the fields(i.e Set to "0" ) */
+        ctl |= (packMode | ctlSlen);                    /* assign packing and slen information */
+        if (true == bLSBFirst)
+        {
+            ctl |= BITM_SPORT_CTL_A_LSBF;               /* set the the LSB first field */
+        }
+        pDevice->pSportInfo->sportCfg.CTL = ctl;        /* CTL value set - CTL_A is assigned when submitting a buffer */
+
+        SPORT_CHECK_CFG_CTL(pDevice->pSportInfo->sportCfg.CTL);
+
+        switch (bytesPerData)
+        {
+        case 1u:
+            if (((uint32_t) ADI_SPORT_8BIT_PACKING) == packMode)
+            {
+                pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE;
+                pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE;
+            } else {
+                pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_1_BYTE;
+                pSportCfg->DMA_INC = ADI_DMA_INCR_1_BYTE;
+
+                assert(((uint32_t) ADI_SPORT_NO_PACKING) == packMode);
+            }
+            break;
+
+        case 2u:
+          if (((uint32_t) ADI_SPORT_16BIT_PACKING) == packMode)
+          {
+              pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE;
+              pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE;
+          } else {
+              pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_2_BYTE;
+              pSportCfg->DMA_INC = ADI_DMA_INCR_2_BYTE;
+
+              assert(((uint32_t) ADI_SPORT_NO_PACKING) == packMode);
+          }
+          break;
+
+        default:
+            pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE;
+            pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE;
+            assert((4u == bytesPerData) || (((uint32_t) ADI_SPORT_NO_PACKING) == packMode));
+            break;
+        }
+    }
+    return result;
+}
+
+/**
+ * @brief       Configure the clock for the specified SPORT device.
+ *
+ * @details     Configure the SPORT device to use the "internal/external " rising/falling clock
+ *              edge,clock edge and for enabling the gated Clock Mode.
+ *
+ * @details     fspclk = fsclk/(2*( nClockRatio + 1))
+ *
+ * @details     fspclk: frequency of SPORT clock
+ *
+ * @param [in]  hDevice        Device handle to SPORT device.
+ *
+ * @param [in]  nClockRatio    The value which determines the ratio between System clock and SPORT
+ *                             clock as explained above.
+ *
+ *
+ * @param [in]  bUseIntlClock  Boolean flag to indicate whether to use internal clock or external
+ *                             clock for data transmission. By default, device is configured to use
+ *                             the external clock.
+ * \n
+ * \n                          true : Device configured to use Internal clock.
+ * \n
+ * \n                          false : Device configured to use external clock..
+ *
+ * @param [in]  bRisingEdge     Boolean flag to indicate whether to drive data and internal frame
+ *                             sync with rising edge OR falling edge of SP clock.
+ * \n
+ * \n                          true : Use falling edge of the clock.
+ * \n
+ * \n                          false : Use rising edge of the clock.
+ *
+ * @param [in]  bGatedClk      Boolean flag to indicate whether to enable/disable gated clock for
+ *                             the specified SPORT channel.Ignored in Multi channel mode. Clock will
+ *                             be active only when active data is getting transmitted or received
+ *                             when this mode is enabled.
+ * \n                          true : Enable gated clock mode.
+ * \n
+ * \n                          false : Disable gated clock mode.
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                    Successfully configured clock for the specified device.
+ *
+ *  - #ADI_SPORT_INVALID_HANDLE        [D]  Invalid SPORT device handle.
+ *
+ *  - #ADI_SPORT_OPERATION_NOT_ALLOWED [D]  Operation is not allowed when data flow is enabled.
+ *
+ */
+ADI_SPORT_RESULT adi_sport_ConfigClock(ADI_SPORT_HANDLE const      hDevice,
+                                       const uint16_t              nClockRatio,
+                                       const bool                  bUseIntlClock,
+                                       const bool                  bRisingEdge,
+                                       const bool                  bGatedClk)
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+    ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice;  /* Pointer to SPORT device instance */
+
+#ifdef ADI_DEBUG
+    if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice)))
+    {
+    }
+    else if (ADI_SPORT_STATE_DATA_FLOW_ENABLED == pDevice->pSportInfo->eState)
+    {
+        result = ADI_SPORT_OPERATION_NOT_ALLOWED;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg;
+        uint32_t clockRatio = (uint32_t) nClockRatio;
+
+        uint32_t ctl = pSportCfg->CTL;
+        uint32_t dv = pSportCfg->DIV;
+
+        ctl &= ~BITM_SPORT_CLOCK_CONFIG;                /* clear all clock configuration fields */
+
+        dv &= ~BITM_SPORT_DIV_A_CLKDIV;
+        dv |= (clockRatio & BITM_SPORT_DIV_A_CLKDIV);   /* update the clock divisior value */
+
+        if (true == bUseIntlClock)
+        {
+            ctl  |= BITM_SPORT_CTL_A_ICLK;              /* select the internal clock */
+        }
+        if (true == bRisingEdge)
+        {
+            ctl |= BITM_SPORT_CTL_A_CKRE;               /* select the rising edge of the  clock */
+        }
+        if (true == bGatedClk)
+        {
+            ctl |= BITM_SPORT_CTL_A_GCLKEN;             /* Enable the Gated clock */
+        }
+        pDevice->pSportInfo->pSportRegs->DIV_A = pSportCfg->DIV = dv;  /* DIV value set */
+        pSportCfg->CTL = ctl;                           /* CTL value set - CTL_A is assigned when submitting a buffer */
+
+        SPORT_CHECK_CFG_CTL(pSportCfg->CTL);
+    }
+    return result;
+}
+
+/**
+ * @brief       Frame Sync(FS) configuration for the specified SPORT.
+ *
+ * @details     Configure the SPORT to use internal/external frame sync,level/edge sensitive
+ *              early/late frame sync etc.
+ *
+ * @param [in]  hDevice           Device handle to SPORT device.
+ *
+ * @param [in]  nFsDivisor        The value which decides the number of SPORT clock cycles between
+ *                                each frame count.
+ *
+ * @param [in]  bFSRequired       Boolean flag to indicate whether frame sync required OR not to
+ *                                the frame sync for the data transfer.
+ * \n
+ * \n                             true : Device requires a frame sync for its operation.
+ * \n
+ * \n                             false : Device does not requires a frame sync for its operation
+ * \n
+ * \n
+ *
+ * @param [in]  bInternalFS       Boolean flag to indicate whether to configure the specified SPORT
+ *                                device to use the internal frame sync OR external frame sync as
+ *                                below.
+ * \n
+ * \n                             true : Use internal frame sync.
+ * \n
+ * \n                             false : Use external frame sync
+ * \n
+ * \n
+ *
+ * @param [in]  bDataFS           Boolean flag to indicate whether to configure the specified SPORT
+ *                                device to use the data-independent frame sync OR Serial port uses
+ *                                a data-dependent frame sync. Valid only if the specified device is
+ *                                in "transmit"(TX)mode . Ignored if the device is opened in
+ *                                "receive"(RX) mode.
+ * \n
+ * \n                             true : Use data-independent frame sync.
+ * \n
+ * \n                             false : Use data-dependent frame sync.
+ * \n
+ * \n
+ *
+ * @param [in]  bActiveLowFS      Boolean flag to indicate whether to configure the specified SPORT
+ *                                device for active low frame sync OR active high frame sync. Call
+ *                                to this function will return error if SPORT is configured in I2S
+ *                                mode.
+ * \n
+ * \n                             true : Use active low frame sync.
+ * \n
+ * \n                             false : Use active high frame sync.
+ * \n
+ * \n
+ *
+ * @param [in]  bLateFS           Boolean flag to indicate whether to use the late frame sync OR
+ *                                Early frame sync.
+ * \n
+ * \n                             true : Use late frame sync.
+ * \n
+ * \n                             false : Use Early frame sync.
+ * \n
+ * \n
+ *
+* @param [in]  bFSErrorOperation  Frame Sync Error Operation.  This
+ *\n                              decides the way the SPORT responds when a frame sync error occurs.
+ * \n
+ * \n                             true : When frame Sync error occurs, discard the receive data.
+ * \n
+ * \n                             false : Flag the Frame Sync error and continue normal operation
+    * \n
+ * \n
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                    Successfully configured the frame sync requirement.
+ *
+ *  - #ADI_SPORT_INVALID_HANDLE        [D]  Invalid SPORT device handle.
+ *
+ *  - #ADI_SPORT_OPERATION_NOT_ALLOWED [D]  Operation is not allowed when data flow is enabled.
+ *
+ */
+ADI_SPORT_RESULT adi_sport_ConfigFrameSync(ADI_SPORT_HANDLE const       hDevice,
+                                           const uint16_t               nFsDivisor,
+                                           const bool                   bFSRequired,
+                                           const bool                   bInternalFS,
+                                           const bool                   bDataFS,
+                                           const bool                   bActiveLowFS,
+                                           const bool                   bLateFS,
+                                           const bool                   bFSErrorOperation)
+{
+    ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice;          /* Pointer to SPORT device instance */
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+
+#ifdef ADI_DEBUG
+    /* Validate the given handle */
+    if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice)))
+    {
+    }
+    else if(pDevice->pSportInfo->eState == ADI_SPORT_STATE_DATA_FLOW_ENABLED)
+    {
+        result = ADI_SPORT_OPERATION_NOT_ALLOWED;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg;
+        const uint32_t fsDivisor = (uint32_t) nFsDivisor;
+
+        uint32_t ctl = pSportCfg->CTL;
+        uint32_t dv = pSportCfg->DIV;
+
+        dv &= ~BITM_SPORT_DIV_A_FSDIV;                  /* clear all the fields of frame sync */
+        dv |= (fsDivisor << BITP_SPORT_DIV_A_FSDIV);
+
+        ctl &= ~BITM_SPORT_FS_CONFIG;                   /* clear all the fields of frame sync */
+
+        if ((ADI_SPORT_DIR_RX == pDevice->eDirection) || (true == bDataFS))
+        {
+            ctl |= BITM_SPORT_CTL_A_DIFS;               /* Set this bit when SPORT is opened in RX mode */
+        }
+        if (true == bFSRequired)                        /* "Frame sync required" is reserved when device */
+        {                                               /* is operating in I2S and MC mode */
+            ctl |= BITM_SPORT_CTL_A_FSR;                /* Frame Sync(FS) is required */
+        }
+        if (true == bInternalFS)
+        {
+            ctl |= BITM_SPORT_CTL_A_IFS;                /* Select the internal Frame Sync(FS)*/
+        }
+        if (true == bActiveLowFS)
+        {
+            ctl |= BITM_SPORT_CTL_A_LFS;                /* Select the Active High Frame Sync(FS)*/
+        }
+        if (true == bLateFS)
+        {
+            ctl |= BITM_SPORT_CTL_A_LAFS;               /* Select the Late Frame Sync(FS)*/
+        }
+        if (true == bFSErrorOperation)
+        {
+            ctl |= BITM_SPORT_CTL_A_FSERRMODE;          /* Select the edge sensitive Frame Sync(FS)*/
+        }
+        pDevice->pSportInfo->pSportRegs->DIV_A = pSportCfg->DIV = dv;   /* DIV value set */
+        pSportCfg->CTL = ctl;                           /* CTL value set - CTL_A is assigned when submitting a buffer */
+
+        SPORT_CHECK_CFG_CTL(pSportCfg->CTL);
+    }
+    return result;
+}
+
+/**
+ * @brief       Configure the SPORT use the Clocks and Frame Sync of other Half-Sport
+ *
+ * @param [in]  hDevice       Device handle to SPORT device.
+ *
+ * @param [in]  bUseOtherFS   Boolean flag to indicate whether to use own Frame Sync(false) OR to
+ *                            use frame sync of other half SPORT (true).
+ * \n
+ * \n                         true : Use frame sync of other half SPORT device.
+ * \n
+ * \n                         false : Use own frame sync.
+ *
+ * @param [in]  bUseOtherClk  Boolean flag to indicate whether to use own clock clock(false) OR to
+ *                            use clock of other half SPORT(true).
+ * \n
+ * \n                         true : Use clock of other half SPORT device.
+ * \n
+ * \n                         false : Use own clock.
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                    Successfully enabled the specified SPORT to use the clk
+ *                                          and FS of other half SPORT.
+ *
+ *  - #ADI_SPORT_INVALID_HANDLE        [D]  Invalid SPORT device handle.
+ *
+ *  - #ADI_SPORT_OPERATION_NOT_ALLOWED [D]  Operation is not allowed when data flow is enabled.
+ *
+ */
+ADI_SPORT_RESULT adi_sport_MultiplexSportSignal(ADI_SPORT_HANDLE const  hDevice,
+                                                const bool              bUseOtherFS,
+                                                const bool              bUseOtherClk)
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+    ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *)hDevice;   /* Pointer to SPORT device instance */
+#ifdef ADI_DEBUG
+    if((result = ValidateHandle(pDevice)) != ADI_SPORT_SUCCESS) /* Validate the given handle */
+    {
+    }
+    else if (pDevice->pSportInfo->eState == ADI_SPORT_STATE_DATA_FLOW_ENABLED)
+    {
+        result = ADI_SPORT_OPERATION_NOT_ALLOWED;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg;
+        uint32_t ctl = pSportCfg->CTL;
+
+        /* clear the muxing fields of the control register 2 */
+        ctl &= (uint32_t)(~(BITM_SPORT_CTL_A_CKMUXSEL | BITM_SPORT_CTL_A_FSMUXSEL));
+        if (true == bUseOtherFS)
+        {
+            ctl |= BITM_SPORT_CTL_A_FSMUXSEL;   /* Use the  the frame sync of  other half sport*/
+        }
+        if(bUseOtherClk  == true)
+        {
+            ctl |= BITM_SPORT_CTL_A_CKMUXSEL;   /* Use the  the clock of  other half sport*/
+        }
+        pSportCfg->CTL = ctl;                   /* CTL value set - CTL_A is assigned when submitting a buffer */
+
+        SPORT_CHECK_CFG_CTL(pSportCfg->CTL);
+    }
+
+    return result;
+}
+/**
+ * @brief       Configure the SPORT use the Clocks and Frame Sync of other Half-Sport
+ *
+ * @param [in]  hDevice       Device handle to SPORT device.
+ *
+ * @param [in]  nFSDuration  Specify the value of the number of clocks which would be programmed corresponding to the
+ *                           desired time duration from assertion of CONVT signal to Frame sync signal
+ *
+ * @param [in]  nWidth       Specify the value of the number of serial clocks for which CONVT signal should be active.
+
+ *
+ * @param [in]  bActiveLow    Boolean flag to indicate the polarity of the Convt signal.
+ * \n
+ * \n                         true :  Active low Polarity.
+ * \n
+ * \n                         false : Active High Polarity.
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                    Successfully enabled the specified SPORT to use the clk
+ *                                          and FS of other half SPORT.
+ *
+ *  - #ADI_SPORT_INVALID_HANDLE        [D]  Invalid SPORT device handle.
+ *
+ *  - #ADI_SPORT_OPERATION_NOT_ALLOWED [D]  Operation is not allowed when data flow is enabled.
+ *
+ */
+ADI_SPORT_RESULT adi_sport_ConfigTimerMode(ADI_SPORT_HANDLE const       hDevice,
+                                           const uint8_t                nFSDuration,
+                                           const uint8_t                nWidth,
+                                           const bool                   bActiveLow)
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+    ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE*) hDevice;   /* Pointer to SPORT device instance */
+
+#ifdef ADI_DEBUG    /* Validate the given handle */
+    if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice)))
+    {
+    }
+    else if (ADI_SPORT_STATE_DATA_FLOW_ENABLED == pDevice->pSportInfo->eState)
+    {
+        result = ADI_SPORT_OPERATION_NOT_ALLOWED;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg;
+        uint32_t cnvt = pSportCfg->TIM_CONVT;
+
+        /* clear the muxing fields of the control register 2 */
+        cnvt &= (uint32_t)(~(BITM_SPORT_CNVT_A_POL |  BITM_SPORT_CNVT_A_WID | BITM_SPORT_CNVT_A_CNVT2FS ));
+        cnvt |= (((uint32_t) nFSDuration << ((uint32_t) BITP_SPORT_CNVT_A_CNVT2FS)) | ((uint32_t) nWidth));
+        if(bActiveLow == true)
+        {
+          cnvt |= ((uint32_t) BITM_SPORT_CNVT_A_POL);   /* Use the  the clock of  other half sport*/
+        }
+        pDevice->pSportInfo->pSportRegs->CNVT_A = pSportCfg->TIM_CONVT = cnvt;
+    }
+    return result;
+}
+
+/*! \cond PRIVATE */
+
+/**
+ * @brief       Create a circular linked list for buffer management.
+ *
+ * @details     Create a circular linked list for buffer management and
+ *              initialize the free buffer, the fill buffer and he active
+ *              buffer with the first buffer in this circular array.
+ *
+ * @param [in]  hDevice  Device handle to SPORT device.
+ *
+ * @param [in]  NumDesc  Number of descriptorS.
+ *
+ */
+static inline void sport_Init (ADI_SPORT_DEVICE *pDevice)
+{
+    uint32_t            i;
+    ADI_DT_CHANNEL      *pChannel = &pDevice->sportChannel;
+    ADI_DT_BUFF_INFO    *pBufInfo = &pChannel->BufInfo[0];              /* initialize this variable with the first array element */
+    ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo;           /* short cut to SPORT information */
+    ADI_SPORT_CONFIG * pSportCfg = &pSportInfo->sportCfg;               /* short cut to SPORT configuration */
+    const uint32_t bytesPerData = GetBytesPerSportData(pSportCfg->CTL); /* number of bytes in SPORT data (1, 2, or 4) */
+    const uint32_t packMode = SPORT_GET_PACKEN(pSportCfg->CTL);         /* SPORT data pack mode */
+
+    /* Initialize the all descriptors. Make it circular. */
+    for(i = 0u; i < ADI_DT_BUFNUM; i++)
+    {
+        pBufInfo[i].pStartAddress  =   NULL;
+        pBufInfo[i].nCount         =   0u;
+        pBufInfo[i].nIndex         =   0u;
+        pBufInfo[i].pNextBuffer    =   &pBufInfo[(i+1u) % ADI_DT_BUFNUM];       /* link the buffers in a circular way */
+    }
+    pChannel->pFreeBuffer   =  &pChannel->BufInfo[0u];  /* the first free buffer is the first array element */
+    pChannel->pActiveBuffer =  &pChannel->BufInfo[0u];  /* the first active buffer is the first array element */
+    pChannel->pFillBuffer   =  &pChannel->BufInfo[0u];  /* the first fill buffer is the first array element */
+
+    switch (bytesPerData)
+    {
+    case 1u:
+        if (SPORT_BIT_PACK_8 == packMode)
+        {
+            pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE;
+            pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE;
+        } else {
+            pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_1_BYTE;
+            pSportCfg->DMA_INC = ADI_DMA_INCR_1_BYTE;
+
+            assert(SPORT_BIT_PACK_NONE == packMode);
+        }
+        break;
+
+    case 2u:
+        if (SPORT_BIT_PACK_16 == packMode)
+        {
+            pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE;
+            pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE;
+        } else {
+            pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_2_BYTE;
+            pSportCfg->DMA_INC = ADI_DMA_INCR_2_BYTE;
+
+            assert(SPORT_BIT_PACK_NONE == packMode);
+        }
+        break;
+
+  default:
+        pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE;
+        pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE;
+        assert((4u == bytesPerData) || (SPORT_BIT_PACK_NONE == packMode));
+        break;
+    }
+}
+
+/*
+ * @brief       Configure the registers with the half-SPORT
+ *
+ * @param [in]  hDevice         Device handle to SPORT device.
+ * @param [in]  sportCfg     SPORT configuration to be used.
+ *
+ * @return      None
+ */
+static inline void sport_Configure (ADI_SPORT_DEVICE *pDevice, ADI_SPORT_CONFIG const * sportCfg)
+{
+    /* Configure the SPORT device using static configuration parameters.
+     * pSportInfo is mapped to one of the half-SPORT available; this is the
+     * half-SPORT configured. (CTL_A, DIV_A, CNVT_A and NUMTRAN_A map either
+     * to half-SPORT A registers or half-SPORT B registers, depending on
+     * sportRegs.)
+     */
+    volatile ADI_SPORT_TypeDef * sportRegs = pDevice->pSportInfo->pSportRegs;
+    ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg;
+
+    /* record the SPORT default configuration */
+    memcpy(pSportCfg, sportCfg, sizeof(ADI_SPORT_CONFIG));
+
+    switch (pDevice->eDirection)        /* Set the direction of operation */
+    {
+    case ADI_SPORT_DIR_RX:
+        pSportCfg->CTL &= ~BITM_SPORT_CTL_A_SPTRAN;
+        break;
+    case ADI_SPORT_DIR_TX:
+        pSportCfg->CTL |= BITM_SPORT_CTL_A_SPTRAN;
+        break;
+    default:
+        assert(0);
+        break;
+    }
+    /* use the SPORT configuration to setup the SPORT registers */
+    sportRegs->CTL_A      = pSportCfg->CTL;
+    sportRegs->DIV_A      = pSportCfg->DIV;
+    sportRegs->CNVT_A     = pSportCfg->TIM_CONVT;
+    sportRegs->NUMTRAN_A  = 0u;
+
+    SPORT_CHECK_CFG_CTL(pSportCfg->CTL);
+}
+
+#ifdef ADI_DEBUG
+static ADI_SPORT_RESULT ValidateHandle(ADI_SPORT_HANDLE const hDevice)
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_INVALID_HANDLE;
+    ADI_SPORT_DEVICE * pInDevice = (ADI_SPORT_DEVICE*) hDevice;
+    ADI_SPORT_DEVICE_INFO *poDeviceInfo = &gSportDevInfo[0][0];
+    uint32_t i;
+
+    /* Pointer to SPORT device instance */
+    for (i=0u; i<(ADI_SPORT_NUM_INSTANCES << 1u); i++)        /* 2 half-devices per SPORT */
+    {
+        if (pInDevice == poDeviceInfo->hDevice)
+        {
+            result = ADI_SPORT_SUCCESS;
+            break;
+        }
+        poDeviceInfo++;
+    }
+    return result;
+}
+#endif /* ADI_DEBUG */
+
+/* mask for events to be recorded in the driver HW error */
+#define recEvt  ((uint32_t) (BITM_SPORT_STAT_A_SYSDATERR | BITM_SPORT_STAT_A_FSERR | BITM_SPORT_STAT_A_DERR))
+
+/* bits to be cleared by the ISR */
+#define clrEvt  ((recEvt | BITM_SPORT_STAT_A_TFI))
+
+static void sport_Terminate(ADI_SPORT_DEVICE * pDevice)
+{
+    ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo;           /* get SPORT device information */
+    volatile ADI_SPORT_TypeDef * pRegs = pSportInfo->pSportRegs;        /* access SPORT registers */
+
+    ADI_DT_CHANNEL * pSportChnl = &pDevice->sportChannel;
+    ADI_DT_BUFF_INFO * pBuff = pSportChnl->pFillBuffer;
+
+    pRegs->CTL_A &= ~BITM_SPORT_CTL_A_SPEN;                             /* disable SPORT */
+    pRegs->IEN_A &= ~(BITM_SPORT_IEN_A_TF | BITM_SPORT_IEN_A_DATA);     /* disable SPORT interrupts */
+    pRegs->NUMTRAN_A = 0u;
+
+#ifdef ADI_DEBUG
+    {
+        /* ============================================= */
+        /* Check the number of data transmitted/received */
+        /* nIndex is incremented each time a data packed */
+        /* or unpacked in received. The size in bytes of */
+        /* each data depends on the SPORT configuration. */
+        /* In core driven operations, nCount represents  */
+        /* the number of 32-bit words transmitted.       */
+        /* In DMA driven operations, nCount represents   */
+        /* the number of DMA data transmitted            */
+        /* ============================================= */
+        const uint32_t ctl = pRegs->CTL_A;
+        const uint32_t bytesPerData = GetBytesPerSportData(ctl);
+        const uint32_t nIndex = pBuff->nIndex * (4u / bytesPerData);
+        assert((nIndex>=pBuff->nCount)||(true==pBuff->bDMA));           /* buffer must be fully processed */
+    }
+#endif
+
+    pBuff->bInUse = false;                                              /* mark buffer as ready */
+
+    NVIC_DisableIRQ(pSportInfo->eIRQn);                                 /* suspend SPORT Interrupt */
+    NVIC_DisableIRQ(pSportInfo->eDMAn);                                 /* suspend SPORT DMA interrupt */
+
+    pDevice->pSportInfo->eState = ADI_SPORT_STATE_PAUSED;
+
+    if(NULL != pDevice->pfCallback)                                     /* Call the callback function if one is registered. */
+    {
+        uint32_t evt = ( (ADI_SPORT_DIR_RX == pDevice->eDirection)
+                       ? ((uint32_t) ADI_SPORT_EVENT_RX_BUFFER_PROCESSED)
+                       : ((uint32_t) ADI_SPORT_EVENT_TX_BUFFER_PROCESSED)
+                       );
+
+        pDevice->pfCallback(pDevice->pCBParam,evt,pBuff->pStartAddress);
+        pBuff->pStartAddress = NULL;                                    /* No need to keep the processed buffer address */
+    }
+    else
+    {
+        SEM_POST(pSportChnl);                                           /* signal the buffer availability through a semaphore */
+    }
+    pRegs->STAT_A = clrEvt;                                             /* clear status register bits (W1C) */
+    pSportChnl->eDataTranferMode = ADI_DT_MODE_NONE;                    /* SPORT is available */
+    pBuff = pBuff->pNextBuffer;                                         /* point to the next buffer to process */
+    pSportChnl->pFillBuffer = pBuff;                                    /* this is the new pFillBuffer */
+
+    if ((0u != pBuff->pStartAddress) && (true == pBuff->bInUse))        /* valid buffer not being processed yet */
+    {
+        ADI_SPORT_RESULT result;
+
+        pSportChnl->eDataTranferMode = ADI_DT_MODE_NONBLOCKING;
+        if (true == pBuff->bDMA)
+        {
+            result = sport_SubmitBufferDmaMode(pDevice, pBuff);
+        }
+        else
+        {
+            result = sport_SubmitBufferIntMode(pDevice, pBuff);
+        }
+        
+        if(ADI_SPORT_SUCCESS != result)                                 /* if an error occurred...*/
+        {
+            pSportChnl->eDataTranferMode = ADI_DT_MODE_NONE;            /* SPORT is available */
+        }
+    }
+}
+
+/*
+ * @brief       Common SPORT interrupt handler function called by SPORT0 A and SPORT0 B ISRs.
+ *
+ * @details     Process SPORT0 A and B interrupts, recording HW errors that must be reported,
+ *              reading/writing transmitted data, launching new SPORT transmissions if more
+ *              buffers are to be processed, and deactivating the SPORT device if there are
+ *              no pending requests. (Common fucntion for both core driven and DMA driven
+ *              SPORT operations.)
+ *
+ * @param [in]  pDevice         Sport device pointer related to the calling ISR.
+ */
+static void sport_InterruptHandler(ADI_SPORT_DEVICE * pDevice)
+{
+    ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo;           /* get SPORT device information */
+    volatile ADI_SPORT_TypeDef * pRegs = pSportInfo->pSportRegs;        /* access SPORT registers */
+    const uint32_t sportStatus = pRegs->STAT_A;                         /* read SPORT status */
+    const uint32_t dataRequest = (sportStatus & BITM_SPORT_STAT_A_DATA);/* set if any data to be processed by the SPORT */
+    const uint32_t hwEvents = sportStatus & recEvt;                     /* HW events to be recorded in the driver */
+
+
+    /* This implementation assumes an identity mapping between BITM_SPORT_STAT values
+     * and their equivalent event in ADI_SPORT_EVENT, e.g. ADI_SPORT_HW_ERR_FS and
+     * BITM_SPORT_STAT_A_FSERR share the same value. This simplifies event processing
+     * and reports. */
+    assert(((uint32_t) ADI_SPORT_HW_ERR_RX_OVERFLOW) == BITM_SPORT_STAT_A_DERR);
+    assert(((uint32_t) ADI_SPORT_HW_ERR_TX_UNDERFLOW) == BITM_SPORT_STAT_A_DERR);
+    assert(((uint32_t) ADI_SPORT_HW_ERR_FS) == BITM_SPORT_STAT_A_FSERR);
+    assert(((uint32_t) ADI_SPORT_HW_ERR_SYSDATAERR) == BITM_SPORT_STAT_A_SYSDATERR);
+
+    if (0u != hwEvents)                                                 /* any event recorded? */
+    {
+        if (NULL != pDevice->pfCallback)                                /* if a callback has been registered ? */
+        {
+            pDevice->pfCallback(pDevice->pCBParam,hwEvents,NULL);       /* then call it */
+        } else {
+            pDevice->nHwError |= hwEvents;                              /* else set the driver HW error */
+            SEM_POST(&pDevice->sportChannel);                           /* and signal this through a semaphore */
+        }
+    }
+
+    if (0u != dataRequest)                                              /* Tx FIFO is not full or Rx FIFO is not empty */
+    {
+        ADI_DT_BUFF_INFO * pBuff = pDevice->sportChannel.pFillBuffer;
+        uint32_t * pNextWord = (uint32_t*) pBuff->pStartAddress;
+
+        if ((NULL != pNextWord) && (pBuff->nIndex < pBuff->nCount))     /* This buffer has not been fully processed yet */
+        {
+            if (ADI_SPORT_DIR_RX == pDevice->eDirection)
+            {
+                pNextWord[pBuff->nIndex++] = pRegs->RX_A;               /* Read the data received in RX and increment the index */
+                while (!DXS_FIFO_IS_EMPTY(pRegs->STAT_A))               /* and if there are more data available in the FIFO */
+                {
+                    pNextWord[pBuff->nIndex++] = pRegs->RX_A;           /* Read remaining data received in RX and increment the index */
+                }
+            }
+            else
+            {
+                pRegs->TX_A = pNextWord[pBuff->nIndex++];               /* Write the data to be sent into TX and increment the index */
+                while (  (pBuff->nIndex < pBuff->nCount)                /* and if there are more data to be sent */
+                      && (!DXS_FIFO_IS_FULL(pRegs->STAT_A))             /* and there is still room in the FIFO */
+                      )
+                {
+                    pRegs->TX_A = pNextWord[pBuff->nIndex++];           /* then write more data to be sent into TX and increment the index */
+                }
+            }
+        }
+    }
+
+    /* ========================================================== */
+    /* Common to core driven operations and DMA driven operations */
+    /* ========================================================== */
+    if (0u != (pRegs->STAT_A & BITM_SPORT_STAT_A_TFI))                  /* If a SPORT Tx/Rx request has finished */
+    {
+        sport_Terminate(pDevice);
+    }
+
+#if defined(ADI_CYCLECOUNT_SPORT_ISR_ENABLED) && (ADI_CYCLECOUNT_SPORT_ISR_ENABLED == 1u)
+    ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_SPORT);    
+#endif
+}
+
+/** Interrupt handler for SPORT0 A */
+void SPORT0A_Int_Handler(void)
+{
+    ISR_PROLOG();
+        sport_InterruptHandler(gSportDevInfo[0][ADI_HALF_SPORT_A].hDevice);
+    ISR_EPILOG();
+}
+
+/** Interrupt handler for SPORT0 B */
+void SPORT0B_Int_Handler(void)
+{
+    ISR_PROLOG();
+        sport_InterruptHandler(gSportDevInfo[0][ADI_HALF_SPORT_B].hDevice);
+    ISR_EPILOG();
+}
+
+void DMA_SPORT0A_Int_Handler(void)
+{
+    ISR_PROLOG();
+        /**
+         * if SPORT is in Rx mode, then the DMA interrupt is the signal for
+         * end of transmission: buffer is ready. (In Tx mode, the signal is
+         * the TFI event and SPORT DMA interrup is not enabled).
+         */
+        sport_Terminate(gSportDevInfo[0][ADI_HALF_SPORT_A].hDevice);
+#if defined(ADI_CYCLECOUNT_SPORT_ISR_ENABLED) && (ADI_CYCLECOUNT_SPORT_ISR_ENABLED == 1u)
+        ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_SPORT);    
+#endif
+    ISR_EPILOG();
+}
+
+void DMA_SPORT0B_Int_Handler(void)
+{
+    ISR_PROLOG();
+        /**
+         * if SPORT is in Rx mode, then the DMA interrupt is the signal for
+         * end of transmission: buffer is ready. (In Tx mode, the signal is
+         * the TFI event and SPORT DMA interrup is not enabled).
+         */
+        sport_Terminate(gSportDevInfo[0][ADI_HALF_SPORT_B].hDevice);
+#if defined(ADI_CYCLECOUNT_SPORT_ISR_ENABLED) && (ADI_CYCLECOUNT_SPORT_ISR_ENABLED == 1u)
+        ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_SPORT);    
+#endif
+    ISR_EPILOG();
+}
+
+static void sport_DmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg)
+{
+    ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE*) pCBParam;          /* Recover the device handle. */
+    ADI_DT_BUFF_INFO * pFillBuffer = pDevice->sportChannel.pFillBuffer;
+    ADI_DT_BUFF_INFO * pNextBuffer = pFillBuffer->pNextBuffer;
+    uint32_t nEvent = 0u;
+
+    if (ADI_DMA_EVENT_ERR_BUS == Event)
+    {
+        nEvent = (uint32_t) ADI_SPORT_DMA_ERR_BUS;                      /* SPORT DMA bus error detected  */
+    } else {
+        assert(ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR == Event);
+        nEvent = (uint32_t) ADI_SPORT_DMA_ERR_INVALID_DESCRIPTOR;       /* SPORT DMA invalid descriptor error detected  */
+    }
+
+    pDevice->nHwError |= nEvent;
+    sport_InterruptHandler(pDevice);
+
+    while (  (NULL != pNextBuffer->pStartAddress)
+          && (true == pNextBuffer->bInUse)
+          && (true == pNextBuffer->bDMA)
+          )                                                             /* another buffer is pending for a DMA driven request */
+    {
+        pDevice->nHwError |= nEvent;
+        pNextBuffer->bInUse = false;
+        sport_InterruptHandler(pDevice);
+        pNextBuffer = pNextBuffer->pNextBuffer;
+    }
+}
+
+static inline uint32_t GetBytesPerSportData(const uint32_t ctlVal)
+{
+    const uint32_t wlen = SPORT_GET_WLEN(ctlVal);
+    const uint32_t bytesPerData = ((wlen < 9u) ? (1u) : ((wlen < 17u) ? (2u) : (4u)));
+    return bytesPerData;
+}
+
+/*! \endcond */
+
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sport/adi_sport_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sport/adi_sport_def.h
new file mode 100755
index 00000000000..7244562e9ae
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sport/adi_sport_def.h
@@ -0,0 +1,193 @@
+/*! *****************************************************************************
+ * @file:    adi_sport_def.h
+ * @brief:   UART Device Driver definition for processor
+ -----------------------------------------------------------------------------
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+/*! \cond PRIVATE */
+#ifndef ADI_SPORT_DEF_H
+#define ADI_SPORT_DEF_H
+
+#include <drivers/general/adi_data_transfer.h>
+
+#if defined(ADI_CFG_SPORT0A_SERIAL_WLEN)
+#if (ADI_CFG_SPORT0A_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0A_SERIAL_WLEN > 32u)
+#error "Invalid word length : it must be between 4 and 32"
+#endif
+#else
+#error "ADI_CFG_SPORT0A_SERIAL_WLEN undefined!!! "
+#endif
+
+#if defined(ADI_CFG_SPORT0B_SERIAL_WLEN)
+#if (ADI_CFG_SPORT0B_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0B_SERIAL_WLEN > 32u)
+#error "Invalid word length : it must be between 4 and 32"
+#endif
+#else
+#error "ADI_CFG_SPORT0B_SERIAL_WLEN undefined!!! "
+#endif
+
+#define ADI_SPORT_NUM_INSTANCES         (1u)    /*!< Number of SPORT devices available */
+#define ADI_SPORT_NUM_CHANNELS          (2u)    /*!< Number of SPORT channel for each SPORT devcie */
+
+#define BITM_SPORT_DATA_CONFIG  ( BITM_SPORT_CTL_A_LSBF \
+                                | BITM_SPORT_CTL_A_PACK)
+
+#define BITM_SPORT_CLOCK_CONFIG ( BITM_SPORT_CTL_A_ICLK \
+                                | BITM_SPORT_CTL_A_CKRE \
+                                | BITM_SPORT_CTL_A_GCLKEN)
+
+#define BITM_SPORT_FS_CONFIG    ( BITM_SPORT_CTL_A_FSR \
+                                | BITM_SPORT_CTL_A_IFS \
+                                | BITM_SPORT_CTL_A_DIFS \
+                                | BITM_SPORT_CTL_A_LFS \
+                                | BITM_SPORT_CTL_A_LAFS \
+                                | BITM_SPORT_CTL_A_FSERRMODE)
+
+#define SPORT_BYTE_TRANSFER_LENGTH      (8u)
+#define SPORT_HALFWORD_TRANSFER_LENGTH  (16u)
+#define SPORT_WORD_TRANSFER_LENGTH      (32u)
+
+#define SPORT_GET_WLEN(ctlVal)          ((((ctlVal) & (uint32_t) BITM_SPORT_CTL_A_SLEN) >> ((uint32_t) BITP_SPORT_CTL_A_SLEN)) + 1u)
+#define SPORT_GET_PACKEN(ctlVal)        ((ctlVal) & (uint32_t) BITM_SPORT_CTL_A_PACK) >> ((uint32_t) BITP_SPORT_CTL_A_PACK)
+
+#define SPORT_CHECK_CFG_CTL(CFG)        assert(0u == ((CFG) & (((uint32_t)BITM_SPORT_CTL_A_SPEN) | ((uint32_t)BITM_SPORT_CTL_A_DMAEN))))
+
+
+#define SPORT_BIT_PACK_NONE     (((uint32_t) ADI_SPORT_NO_PACKING)    >> ((uint32_t) BITP_SPORT_CTL_A_PACK))
+#define SPORT_BIT_PACK_8        (((uint32_t) ADI_SPORT_8BIT_PACKING)  >> ((uint32_t) BITP_SPORT_CTL_A_PACK))
+#define SPORT_BIT_PACK_16       (((uint32_t) ADI_SPORT_16BIT_PACKING) >> ((uint32_t) BITP_SPORT_CTL_A_PACK))
+
+/*!
+ *****************************************************************************
+ * \struct  ADI_SPORT_STATE
+ *  Enumeration of different SPORT states.
+ *****************************************************************************/
+typedef enum
+{
+    ADI_SPORT_STATE_UNINITIALIZED = 0,  /*!< SPORT is not yet initialized */
+    ADI_SPORT_STATE_INITIALIZED,        /*!< SPORT is initialized */
+    ADI_SPORT_STATE_DATA_FLOW_ENABLED,  /*!< SPORT Tx or Rx data flow is enabled (SPORT peripheral cannot be re-configured) */
+    ADI_SPORT_STATE_DATA_FLOW_DISABLED, /*!< SPORT Tx or Rx data flow is disabled (SPORT peripheral can be re-configured) */
+    ADI_SPORT_STATE_PAUSED
+} ADI_SPORT_STATE;
+
+/*!
+ *****************************************************************************
+ * \struct  ADI_SPORT_CONFIG
+ *  Structure for initializing the static config.
+ *****************************************************************************/
+
+typedef struct _ADI_SPORT_CONFIG
+{
+    uint32_t    CTL;            /*!< SPORT_CTL register. */
+    uint32_t    DIV;            /*!< SPORT_DIV register. */
+    uint32_t    TIM_CONVT;      /*!< TIM_CONVT Register. */
+    uint32_t    DMA_WIDTH;      /*!< DMA_WIDTH */
+    uint32_t    DMA_INC;        /*!< DMA_INC */
+} ADI_SPORT_CONFIG;
+
+/*!
+ *****************************************************************************
+ * \struct  ADI_SPORT_DEVICE_INFO
+ *  SPORT device information.
+ *****************************************************************************/
+typedef struct _ADI_SPORT_DEVICE_INFO
+{
+    volatile ADI_SPORT_TypeDef* pSportRegs;     /*!< Base address of the SPORT registers */
+    ADI_SPORT_CONFIG            sportCfg;       /*!< SPORT configuration data */
+    ADI_SPORT_STATE             eState;         /*!< To indicate the state of the device */
+    const DMA_CHANn_TypeDef     eDMAChnlID;     /*!< DMA channel ID */
+    const IRQn_Type             eDMAn;          /*!< DMA channel IRQ identifier */
+    const IRQn_Type             eIRQn;          /*!< SPORT IRQ identifier */
+    ADI_SPORT_HANDLE            hDevice;        /*!< SPORT handle */
+} ADI_SPORT_DEVICE_INFO;
+
+/******************************************************************************
+ * SPORT Device internal API function prototypes
+ *****************************************************************************/
+
+#define NUM_SPORT_BUFFER                (2u)
+
+/** SPORT driver instance data */
+typedef struct _ADI_SPORT_DEVICE
+{
+    ADI_SPORT_DEVICE_INFO *     pSportInfo;     /*!< pointer to the structure which stores the information about the SPORT instances.*/
+    ADI_SPORT_DIRECTION         eDirection;     /*!< Direction in which the SPORT is opened */
+    ADI_CALLBACK                pfCallback;     /*!< Function pointer for callback function. */
+    void *                      pCBParam;       /*!< Parameter to callback function. */
+    ADI_DT_CHANNEL              sportChannel;   /*!< SPORT channel to manage transmitted data buffers */
+    volatile uint32_t           nHwError;       /*!< variable to store the hardware status */
+} ADI_SPORT_DEVICE;
+
+/** Initialize a SPORT device */
+static inline void sport_Init (ADI_SPORT_DEVICE * pDevice);
+
+/** Configure a SPORT device */
+static inline void sport_Configure (ADI_SPORT_DEVICE *pDevice, ADI_SPORT_CONFIG const * sportCfg);
+
+/** Function prototype for submitting a buffer for SPORT Rx or Tx DMA driven transmission */
+static ADI_SPORT_RESULT sport_SubmitBufferDmaMode(ADI_SPORT_DEVICE * pDevice, ADI_DT_BUFF_INFO * pBuff);
+
+/** Function prototype for submitting a buffer for SPORT Rx or Tx core driven transmission */
+static ADI_SPORT_RESULT sport_SubmitBufferIntMode(ADI_SPORT_DEVICE * pDevice, ADI_DT_BUFF_INFO * pBuff);
+
+/** Fucntion prototype for completing a SPORT transmission (Rx or Tx) */
+static void sport_Terminate(ADI_SPORT_DEVICE * pDevice);
+
+/** Interrupt Handlers */
+
+/** SPORT interrupt handler */
+static void sport_InterruptHandler(ADI_SPORT_DEVICE * pDevice);
+
+static inline void sport_DmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg);
+
+static inline uint32_t GetBytesPerSportData(const uint32_t ctlVal);
+
+/*
+ * Handle Validation function
+*/
+#ifdef ADI_DEBUG
+static ADI_SPORT_RESULT ValidateHandle(ADI_SPORT_HANDLE const hDevice);
+#endif /* ADI_DEBUG */
+
+#endif  /* end of ifndef ADI_SPORT_DEF_H */
+/*! \endcond */
+
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x.h
new file mode 100755
index 00000000000..6794f1840ae
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x.h
@@ -0,0 +1,4494 @@
+/* ================================================================================
+
+     Project      :   ADuCM302x
+     File         :   ADuCM302x.h
+     Description  :   Register Definitions
+
+     Date         :   Feb 6, 2017
+
+     Copyright (c) 2014-2017 Analog Devices, Inc.  All Rights Reserved.
+     This software is proprietary and confidential to Analog Devices, Inc. and
+     its licensors.
+
+     This file was auto-generated. Do not make local changes to this file.
+
+   ================================================================================ */
+
+#ifndef _DEF_ADUCM302X_H
+#define _DEF_ADUCM302X_H
+
+#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__))
+#include <stdint.h>
+#endif /* _LANGUAGE_C */
+
+
+#if defined (_MISRA_RULES)
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit")
+#pragma diag(suppress:misra_rule_19_7:"ADI header allows function-like macros")
+#pragma diag(suppress:misra_rule_19_13:"ADI headers can use the # and ## preprocessor operators")
+#endif /* _MISRA_RULES */
+
+/* _ADI_MSK_3 might be defined in wrapper includes - otherwise provide a default */
+#if !defined(_ADI_MSK_3)
+/* do not add casts to literal constants in assembly code */
+#if defined(_LANGUAGE_ASM) || defined(__ASSEMBLER__)
+/* Use unsuffixed literals for BITM macros */
+#define _ADI_MSK_3( mask, smask, type ) (mask) 
+#else
+/* Use casted suffixed literals for BITM macros */
+#define _ADI_MSK_3( mask, smask, type ) ((type)(smask))
+#endif
+#endif
+
+#ifndef __ADI_GENERATED_DEF_HEADERS__
+#define __ADI_GENERATED_DEF_HEADERS__    1
+#endif
+
+#define __ADI_HAS_ADC__            1
+#define __ADI_HAS_BEEP__           1
+#define __ADI_HAS_BUSM__           1
+#define __ADI_HAS_CLKG_OSC__       1
+#define __ADI_HAS_CLKG__           1
+#define __ADI_HAS_CLKG_CLK__       1
+#define __ADI_HAS_CRC__            1
+#define __ADI_HAS_CRYPT__          1
+#define __ADI_HAS_DMA__            1
+#define __ADI_HAS_XINT__           1
+#define __ADI_HAS_FLCC__           1
+#define __ADI_HAS_FLCC_CACHE__     1
+#define __ADI_HAS_FLCC_DFT__       1
+#define __ADI_HAS_FLCC_TEST__      1
+#define __ADI_HAS_GPIO__           1
+#define __ADI_HAS_TMR__            1
+#define __ADI_HAS_I2C__            1
+#define __ADI_HAS_NVIC__           1
+#define __ADI_HAS_PMG__            1
+#define __ADI_HAS_PMG_TST__        1
+#define __ADI_HAS_PTI__            1
+#define __ADI_HAS_RNG__            1
+#define __ADI_HAS_RTC__            1
+#define __ADI_HAS_SPI__            1
+#define __ADI_HAS_SPORT__          1
+#define __ADI_HAS_SYS__            1
+#define __ADI_HAS_UART__           1
+#define __ADI_HAS_WDT__            1
+
+/* ============================================================================================================================
+        General Purpose Timer
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        TMR0
+   ============================================================================================================================ */
+#define REG_TMR0_LOAD                        0x40000000            /*  TMR0 16-bit Load Value */
+#define REG_TMR0_CURCNT                      0x40000004            /*  TMR0 16-bit Timer Value */
+#define REG_TMR0_CTL                         0x40000008            /*  TMR0 Control */
+#define REG_TMR0_CLRINT                      0x4000000C            /*  TMR0 Clear Interrupt */
+#define REG_TMR0_CAPTURE                     0x40000010            /*  TMR0 Capture */
+#define REG_TMR0_ALOAD                       0x40000014            /*  TMR0 16-bit Load Value, Asynchronous */
+#define REG_TMR0_ACURCNT                     0x40000018            /*  TMR0 16-bit Timer Value, Asynchronous */
+#define REG_TMR0_STAT                        0x4000001C            /*  TMR0 Status */
+#define REG_TMR0_PWMCTL                      0x40000020            /*  TMR0 PWM Control Register */
+#define REG_TMR0_PWMMATCH                    0x40000024            /*  TMR0 PWM Match Value */
+
+/* ============================================================================================================================
+        TMR1
+   ============================================================================================================================ */
+#define REG_TMR1_LOAD                        0x40000400            /*  TMR1 16-bit Load Value */
+#define REG_TMR1_CURCNT                      0x40000404            /*  TMR1 16-bit Timer Value */
+#define REG_TMR1_CTL                         0x40000408            /*  TMR1 Control */
+#define REG_TMR1_CLRINT                      0x4000040C            /*  TMR1 Clear Interrupt */
+#define REG_TMR1_CAPTURE                     0x40000410            /*  TMR1 Capture */
+#define REG_TMR1_ALOAD                       0x40000414            /*  TMR1 16-bit Load Value, Asynchronous */
+#define REG_TMR1_ACURCNT                     0x40000418            /*  TMR1 16-bit Timer Value, Asynchronous */
+#define REG_TMR1_STAT                        0x4000041C            /*  TMR1 Status */
+#define REG_TMR1_PWMCTL                      0x40000420            /*  TMR1 PWM Control Register */
+#define REG_TMR1_PWMMATCH                    0x40000424            /*  TMR1 PWM Match Value */
+
+/* ============================================================================================================================
+        TMR2
+   ============================================================================================================================ */
+#define REG_TMR2_LOAD                        0x40000800            /*  TMR2 16-bit Load Value */
+#define REG_TMR2_CURCNT                      0x40000804            /*  TMR2 16-bit Timer Value */
+#define REG_TMR2_CTL                         0x40000808            /*  TMR2 Control */
+#define REG_TMR2_CLRINT                      0x4000080C            /*  TMR2 Clear Interrupt */
+#define REG_TMR2_CAPTURE                     0x40000810            /*  TMR2 Capture */
+#define REG_TMR2_ALOAD                       0x40000814            /*  TMR2 16-bit Load Value, Asynchronous */
+#define REG_TMR2_ACURCNT                     0x40000818            /*  TMR2 16-bit Timer Value, Asynchronous */
+#define REG_TMR2_STAT                        0x4000081C            /*  TMR2 Status */
+#define REG_TMR2_PWMCTL                      0x40000820            /*  TMR2 PWM Control Register */
+#define REG_TMR2_PWMMATCH                    0x40000824            /*  TMR2 PWM Match Value */
+
+/* ============================================================================================================================
+        TMR Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_LOAD                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_LOAD_VALUE                   0            /*  Load Value */
+#define BITM_TMR_LOAD_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Load Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_CURCNT                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_CURCNT_VALUE                 0            /*  Current Count */
+#define BITM_TMR_CURCNT_VALUE                (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Current Count */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_CTL                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_CTL_SYNCBYP                 15            /*  Synchronization Bypass */
+#define BITP_TMR_CTL_RSTEN                   14            /*  Counter and Prescale Reset Enable */
+#define BITP_TMR_CTL_EVTEN                   13            /*  Event Select */
+#define BITP_TMR_CTL_EVTRANGE                 8            /*  Event Select Range */
+#define BITP_TMR_CTL_RLD                      7            /*  Reload Control */
+#define BITP_TMR_CTL_CLK                      5            /*  Clock Select */
+#define BITP_TMR_CTL_EN                       4            /*  Timer Enable */
+#define BITP_TMR_CTL_MODE                     3            /*  Timer Mode */
+#define BITP_TMR_CTL_UP                       2            /*  Count up */
+#define BITP_TMR_CTL_PRE                      0            /*  Prescaler */
+#define BITM_TMR_CTL_SYNCBYP                 (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Synchronization Bypass */
+#define BITM_TMR_CTL_RSTEN                   (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Counter and Prescale Reset Enable */
+#define BITM_TMR_CTL_EVTEN                   (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Event Select */
+#define BITM_TMR_CTL_EVTRANGE                (_ADI_MSK_3(0x00001F00,0x00001F00U, uint16_t  ))    /*  Event Select Range */
+#define BITM_TMR_CTL_RLD                     (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Reload Control */
+#define BITM_TMR_CTL_CLK                     (_ADI_MSK_3(0x00000060,0x00000060U, uint16_t  ))    /*  Clock Select */
+#define BITM_TMR_CTL_EN                      (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Timer Enable */
+#define BITM_TMR_CTL_MODE                    (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Timer Mode */
+#define BITM_TMR_CTL_UP                      (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Count up */
+#define BITM_TMR_CTL_PRE                     (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t  ))    /*  Prescaler */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_CLRINT                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_CLRINT_EVTCAPT               1            /*  Clear Captured Event Interrupt */
+#define BITP_TMR_CLRINT_TIMEOUT               0            /*  Clear Timeout Interrupt */
+#define BITM_TMR_CLRINT_EVTCAPT              (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Clear Captured Event Interrupt */
+#define BITM_TMR_CLRINT_TIMEOUT              (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Clear Timeout Interrupt */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_CAPTURE                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_CAPTURE_VALUE                0            /*  16-bit Captured Value */
+#define BITM_TMR_CAPTURE_VALUE               (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  16-bit Captured Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_ALOAD                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_ALOAD_VALUE                  0            /*  Load Value, Asynchronous */
+#define BITM_TMR_ALOAD_VALUE                 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Load Value, Asynchronous */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_ACURCNT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_ACURCNT_VALUE                0            /*  Counter Value */
+#define BITM_TMR_ACURCNT_VALUE               (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Counter Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_STAT                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_STAT_CNTRST                  8            /*  Counter Reset Occurring */
+#define BITP_TMR_STAT_PDOK                    7            /*  Clear Interrupt Register Synchronization */
+#define BITP_TMR_STAT_BUSY                    6            /*  Timer Busy */
+#define BITP_TMR_STAT_CAPTURE                 1            /*  Capture Event Pending */
+#define BITP_TMR_STAT_TIMEOUT                 0            /*  Timeout Event Occurred */
+#define BITM_TMR_STAT_CNTRST                 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Counter Reset Occurring */
+#define BITM_TMR_STAT_PDOK                   (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Clear Interrupt Register Synchronization */
+#define BITM_TMR_STAT_BUSY                   (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Timer Busy */
+#define BITM_TMR_STAT_CAPTURE                (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Capture Event Pending */
+#define BITM_TMR_STAT_TIMEOUT                (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Timeout Event Occurred */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_PWMCTL                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_PWMCTL_IDLESTATE             1            /*  PWM Idle State */
+#define BITP_TMR_PWMCTL_MATCH                 0            /*  PWM Match Enabled */
+#define BITM_TMR_PWMCTL_IDLESTATE            (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  PWM Idle State */
+#define BITM_TMR_PWMCTL_MATCH                (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  PWM Match Enabled */
+#define ENUM_TMR_PWMCTL_IDLE_LOW             (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  IDLESTATE: PWM idles low */
+#define ENUM_TMR_PWMCTL_IDLE_HIGH            (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  IDLESTATE: PWM idles high */
+#define ENUM_TMR_PWMCTL_PWM_TOGGLE           (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  MATCH: PWM in toggle mode */
+#define ENUM_TMR_PWMCTL_PWM_MATCH            (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  MATCH: PWM in match mode */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_PWMMATCH                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_PWMMATCH_VALUE               0            /*  PWM Match Value */
+#define BITM_TMR_PWMMATCH_VALUE              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  PWM Match Value */
+
+
+/* ============================================================================================================================
+        Real-Time Clock
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        RTC0
+   ============================================================================================================================ */
+#define REG_RTC0_CR0                         0x40001000            /*  RTC0 RTC Control 0 */
+#define REG_RTC0_SR0                         0x40001004            /*  RTC0 RTC Status 0 */
+#define REG_RTC0_SR1                         0x40001008            /*  RTC0 RTC Status 1 */
+#define REG_RTC0_CNT0                        0x4000100C            /*  RTC0 RTC Count 0 */
+#define REG_RTC0_CNT1                        0x40001010            /*  RTC0 RTC Count 1 */
+#define REG_RTC0_ALM0                        0x40001014            /*  RTC0 RTC Alarm 0 */
+#define REG_RTC0_ALM1                        0x40001018            /*  RTC0 RTC Alarm 1 */
+#define REG_RTC0_TRM                         0x4000101C            /*  RTC0 RTC Trim */
+#define REG_RTC0_GWY                         0x40001020            /*  RTC0 RTC Gateway */
+#define REG_RTC0_CR1                         0x40001028            /*  RTC0 RTC Control 1 */
+#define REG_RTC0_SR2                         0x4000102C            /*  RTC0 RTC Status 2 */
+#define REG_RTC0_SNAP0                       0x40001030            /*  RTC0 RTC Snapshot 0 */
+#define REG_RTC0_SNAP1                       0x40001034            /*  RTC0 RTC Snapshot 1 */
+#define REG_RTC0_SNAP2                       0x40001038            /*  RTC0 RTC Snapshot 2 */
+#define REG_RTC0_MOD                         0x4000103C            /*  RTC0 RTC Modulo */
+#define REG_RTC0_CNT2                        0x40001040            /*  RTC0 RTC Count 2 */
+#define REG_RTC0_ALM2                        0x40001044            /*  RTC0 RTC Alarm 2 */
+#define REG_RTC0_SR3                         0x40001048            /*  RTC0 RTC Status 3 */
+#define REG_RTC0_CR2IC                       0x4000104C            /*  RTC0 RTC Control 2 for Configuring Input Capture Channels */
+#define REG_RTC0_CR3SS                       0x40001050            /*  RTC0 RTC Control 3 for Configuring SensorStrobe Channel */
+#define REG_RTC0_CR4SS                       0x40001054            /*  RTC0 RTC Control 4 for Configuring SensorStrobe Channel */
+#define REG_RTC0_SSMSK                       0x40001058            /*  RTC0 RTC Mask for SensorStrobe Channel */
+#define REG_RTC0_SS1ARL                      0x4000105C            /*  RTC0 RTC Auto-Reload for SensorStrobe Channel 1 */
+#define REG_RTC0_IC2                         0x40001064            /*  RTC0 RTC Input Capture Channel 2 */
+#define REG_RTC0_IC3                         0x40001068            /*  RTC0 RTC Input Capture Channel 3 */
+#define REG_RTC0_IC4                         0x4000106C            /*  RTC0 RTC Input Capture Channel 4 */
+#define REG_RTC0_SS1                         0x40001070            /*  RTC0 RTC SensorStrobe Channel 1 */
+#define REG_RTC0_SR4                         0x40001080            /*  RTC0 RTC Status 4 */
+#define REG_RTC0_SR5                         0x40001084            /*  RTC0 RTC Status 5 */
+#define REG_RTC0_SR6                         0x40001088            /*  RTC0 RTC Status 6 */
+#define REG_RTC0_SS1TGT                      0x4000108C            /*  RTC0 RTC SensorStrobe Channel 1 Target */
+#define REG_RTC0_FRZCNT                      0x40001090            /*  RTC0 RTC Freeze Count */
+
+/* ============================================================================================================================
+        RTC1
+   ============================================================================================================================ */
+#define REG_RTC1_CR0                         0x40001400            /*  RTC1 RTC Control 0 */
+#define REG_RTC1_SR0                         0x40001404            /*  RTC1 RTC Status 0 */
+#define REG_RTC1_SR1                         0x40001408            /*  RTC1 RTC Status 1 */
+#define REG_RTC1_CNT0                        0x4000140C            /*  RTC1 RTC Count 0 */
+#define REG_RTC1_CNT1                        0x40001410            /*  RTC1 RTC Count 1 */
+#define REG_RTC1_ALM0                        0x40001414            /*  RTC1 RTC Alarm 0 */
+#define REG_RTC1_ALM1                        0x40001418            /*  RTC1 RTC Alarm 1 */
+#define REG_RTC1_TRM                         0x4000141C            /*  RTC1 RTC Trim */
+#define REG_RTC1_GWY                         0x40001420            /*  RTC1 RTC Gateway */
+#define REG_RTC1_CR1                         0x40001428            /*  RTC1 RTC Control 1 */
+#define REG_RTC1_SR2                         0x4000142C            /*  RTC1 RTC Status 2 */
+#define REG_RTC1_SNAP0                       0x40001430            /*  RTC1 RTC Snapshot 0 */
+#define REG_RTC1_SNAP1                       0x40001434            /*  RTC1 RTC Snapshot 1 */
+#define REG_RTC1_SNAP2                       0x40001438            /*  RTC1 RTC Snapshot 2 */
+#define REG_RTC1_MOD                         0x4000143C            /*  RTC1 RTC Modulo */
+#define REG_RTC1_CNT2                        0x40001440            /*  RTC1 RTC Count 2 */
+#define REG_RTC1_ALM2                        0x40001444            /*  RTC1 RTC Alarm 2 */
+#define REG_RTC1_SR3                         0x40001448            /*  RTC1 RTC Status 3 */
+#define REG_RTC1_CR2IC                       0x4000144C            /*  RTC1 RTC Control 2 for Configuring Input Capture Channels */
+#define REG_RTC1_CR3SS                       0x40001450            /*  RTC1 RTC Control 3 for Configuring SensorStrobe Channel */
+#define REG_RTC1_CR4SS                       0x40001454            /*  RTC1 RTC Control 4 for Configuring SensorStrobe Channel */
+#define REG_RTC1_SSMSK                       0x40001458            /*  RTC1 RTC Mask for SensorStrobe Channel */
+#define REG_RTC1_SS1ARL                      0x4000145C            /*  RTC1 RTC Auto-Reload for SensorStrobe Channel 1 */
+#define REG_RTC1_IC2                         0x40001464            /*  RTC1 RTC Input Capture Channel 2 */
+#define REG_RTC1_IC3                         0x40001468            /*  RTC1 RTC Input Capture Channel 3 */
+#define REG_RTC1_IC4                         0x4000146C            /*  RTC1 RTC Input Capture Channel 4 */
+#define REG_RTC1_SS1                         0x40001470            /*  RTC1 RTC SensorStrobe Channel 1 */
+#define REG_RTC1_SR4                         0x40001480            /*  RTC1 RTC Status 4 */
+#define REG_RTC1_SR5                         0x40001484            /*  RTC1 RTC Status 5 */
+#define REG_RTC1_SR6                         0x40001488            /*  RTC1 RTC Status 6 */
+#define REG_RTC1_SS1TGT                      0x4000148C            /*  RTC1 RTC SensorStrobe Channel 1 Target */
+#define REG_RTC1_FRZCNT                      0x40001490            /*  RTC1 RTC Freeze Count */
+
+/* ============================================================================================================================
+        RTC Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_CR0                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_CR0_WPNDINTEN               15            /*  Enable Write Pending Sourced Interrupts to the CPU */
+#define BITP_RTC_CR0_WSYNCINTEN              14            /*  Enable Write Synchronization Sourced Interrupts to the CPU */
+#define BITP_RTC_CR0_WPNDERRINTEN            13            /*  Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Register-write Pending Error Occurs */
+#define BITP_RTC_CR0_ISOINTEN                12            /*  Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power Domain is Activated and Subsequently De-activated */
+#define BITP_RTC_CR0_MOD60ALMINTEN           11            /*  Enable Periodic Modulo-60 RTC Alarm  Sourced Interrupts to the CPU */
+#define BITP_RTC_CR0_MOD60ALM                 5            /*  Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60 Boundary */
+#define BITP_RTC_CR0_MOD60ALMEN               4            /*  Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary */
+#define BITP_RTC_CR0_TRMEN                    3            /*  Enable RTC Digital Trimming */
+#define BITP_RTC_CR0_ALMINTEN                 2            /*  Enable ALMINT Sourced Alarm Interrupts to the CPU */
+#define BITP_RTC_CR0_ALMEN                    1            /*  Enable the RTC Alarm (Absolute) Operation */
+#define BITP_RTC_CR0_CNTEN                    0            /*  Global Enable for the RTC */
+#define BITM_RTC_CR0_WPNDINTEN               (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Enable Write Pending Sourced Interrupts to the CPU */
+#define BITM_RTC_CR0_WSYNCINTEN              (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Enable Write Synchronization Sourced Interrupts to the CPU */
+#define BITM_RTC_CR0_WPNDERRINTEN            (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Register-write Pending Error Occurs */
+#define BITM_RTC_CR0_ISOINTEN                (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power Domain is Activated and Subsequently De-activated */
+#define BITM_RTC_CR0_MOD60ALMINTEN           (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Enable Periodic Modulo-60 RTC Alarm  Sourced Interrupts to the CPU */
+#define BITM_RTC_CR0_MOD60ALM                (_ADI_MSK_3(0x000007E0,0x000007E0U, uint16_t  ))    /*  Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60 Boundary */
+#define BITM_RTC_CR0_MOD60ALMEN              (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary */
+#define BITM_RTC_CR0_TRMEN                   (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Enable RTC Digital Trimming */
+#define BITM_RTC_CR0_ALMINTEN                (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Enable ALMINT Sourced Alarm Interrupts to the CPU */
+#define BITM_RTC_CR0_ALMEN                   (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Enable the RTC Alarm (Absolute) Operation */
+#define BITM_RTC_CR0_CNTEN                   (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Global Enable for the RTC */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SR0                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SR0_ISOENB                  14            /*  Visibility of 32kHz Sourced Registers */
+#define BITP_RTC_SR0_WSYNCTRM                13            /*  Synchronisation Status of Posted Writes to TRM */
+#define BITP_RTC_SR0_WSYNCALM1               12            /*  Synchronisation Status of Posted Writes to ALM1 */
+#define BITP_RTC_SR0_WSYNCALM0               11            /*  Synchronisation Status of Posted Writes to ALM0 */
+#define BITP_RTC_SR0_WSYNCCNT1               10            /*  Synchronisation Status of Posted Writes to CNT1 */
+#define BITP_RTC_SR0_WSYNCCNT0                9            /*  Synchronisation Status of Posted Writes to CNT0 */
+#define BITP_RTC_SR0_WSYNCSR0                 8            /*  Synchronisation Status of Posted Writes to SR0 */
+#define BITP_RTC_SR0_WSYNCCR0                 7            /*  Synchronisation Status of Posted Writes to CR0 */
+#define BITP_RTC_SR0_WPNDINT                  6            /*  Write Pending Interrupt */
+#define BITP_RTC_SR0_WSYNCINT                 5            /*  Write Synchronisation Interrupt */
+#define BITP_RTC_SR0_WPNDERRINT               4            /*  Write Pending Error Interrupt Source */
+#define BITP_RTC_SR0_ISOINT                   3            /*  RTC Power-Domain Isolation Interrupt Source */
+#define BITP_RTC_SR0_MOD60ALMINT              2            /*  Modulo-60 RTC Alarm Interrupt Source */
+#define BITP_RTC_SR0_ALMINT                   1            /*  Alarm Interrupt Source */
+#define BITM_RTC_SR0_ISOENB                  (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Visibility of 32kHz Sourced Registers */
+#define BITM_RTC_SR0_WSYNCTRM                (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to TRM */
+#define BITM_RTC_SR0_WSYNCALM1               (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to ALM1 */
+#define BITM_RTC_SR0_WSYNCALM0               (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to ALM0 */
+#define BITM_RTC_SR0_WSYNCCNT1               (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to CNT1 */
+#define BITM_RTC_SR0_WSYNCCNT0               (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to CNT0 */
+#define BITM_RTC_SR0_WSYNCSR0                (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to SR0 */
+#define BITM_RTC_SR0_WSYNCCR0                (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to CR0 */
+#define BITM_RTC_SR0_WPNDINT                 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Write Pending Interrupt */
+#define BITM_RTC_SR0_WSYNCINT                (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Write Synchronisation Interrupt */
+#define BITM_RTC_SR0_WPNDERRINT              (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Write Pending Error Interrupt Source */
+#define BITM_RTC_SR0_ISOINT                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  RTC Power-Domain Isolation Interrupt Source */
+#define BITM_RTC_SR0_MOD60ALMINT             (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Modulo-60 RTC Alarm Interrupt Source */
+#define BITM_RTC_SR0_ALMINT                  (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Alarm Interrupt Source */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SR1                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SR1_WPNDTRM                 13            /*  Pending Status of Posted Writes to TRM */
+#define BITP_RTC_SR1_WPNDALM1                12            /*  Pending Status of Posted Writes to ALM1 */
+#define BITP_RTC_SR1_WPNDALM0                11            /*  Pending Status of Posted Writes to ALM0 */
+#define BITP_RTC_SR1_WPNDCNT1                10            /*  Pending Status of Posted Writes to CNT1 */
+#define BITP_RTC_SR1_WPNDCNT0                 9            /*  Pending Status of Posted Writes to CNT0 */
+#define BITP_RTC_SR1_WPNDSR0                  8            /*  Pending Status of Posted Clearances of Interrupt Sources in SR0 */
+#define BITP_RTC_SR1_WPNDCR0                  7            /*  Pending Status of Posted Writes to CR0 */
+#define BITM_RTC_SR1_WPNDTRM                 (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Pending Status of Posted Writes to TRM */
+#define BITM_RTC_SR1_WPNDALM1                (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Pending Status of Posted Writes to ALM1 */
+#define BITM_RTC_SR1_WPNDALM0                (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Pending Status of Posted Writes to ALM0 */
+#define BITM_RTC_SR1_WPNDCNT1                (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Pending Status of Posted Writes to CNT1 */
+#define BITM_RTC_SR1_WPNDCNT0                (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Pending Status of Posted Writes to CNT0 */
+#define BITM_RTC_SR1_WPNDSR0                 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Pending Status of Posted Clearances of Interrupt Sources in SR0 */
+#define BITM_RTC_SR1_WPNDCR0                 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Pending Status of Posted Writes to CR0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_CNT0                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_CNT0_VALUE                   0            /*  Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */
+#define BITM_RTC_CNT0_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_CNT1                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_CNT1_VALUE                   0            /*  Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */
+#define BITM_RTC_CNT1_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_ALM0                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_ALM0_VALUE                   0            /*  Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time */
+#define BITM_RTC_ALM0_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_ALM1                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_ALM1_VALUE                   0            /*  Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time */
+#define BITM_RTC_ALM1_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_TRM                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_TRM_IVL2EXPMIN               6            /*  Minimum Power-of-two Interval of Prescaled RTC Time Units Which TRM:TRMIVL TRMIVL Can Select */
+#define BITP_RTC_TRM_IVL                      4            /*  Trim Interval in Prescaled RTC Time Units */
+#define BITP_RTC_TRM_ADD                      3            /*  Trim Polarity */
+#define BITP_RTC_TRM_VALUE                    0            /*  Trim Value in Prescaled RTC Time Units to Be Added or Subtracted from the RTC Count at the End of a Periodic Interval Selected by TRM:TRMIVL */
+#define BITM_RTC_TRM_IVL2EXPMIN              (_ADI_MSK_3(0x000003C0,0x000003C0U, uint16_t  ))    /*  Minimum Power-of-two Interval of Prescaled RTC Time Units Which TRM:TRMIVL TRMIVL Can Select */
+#define BITM_RTC_TRM_IVL                     (_ADI_MSK_3(0x00000030,0x00000030U, uint16_t  ))    /*  Trim Interval in Prescaled RTC Time Units */
+#define BITM_RTC_TRM_ADD                     (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Trim Polarity */
+#define BITM_RTC_TRM_VALUE                   (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t  ))    /*  Trim Value in Prescaled RTC Time Units to Be Added or Subtracted from the RTC Count at the End of a Periodic Interval Selected by TRM:TRMIVL */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_GWY                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_GWY_SWKEY                    0            /*  Software-keyed Command Issued by the CPU */
+#define BITM_RTC_GWY_SWKEY                   (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Software-keyed Command Issued by the CPU */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_CR1                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_CR1_PRESCALE2EXP             5            /*  Prescale Power of 2 Division Factor for the RTC Base Clock */
+#define BITP_RTC_CR1_CNTMOD60ROLLINTEN        4            /*  Enable for the RTC Modulo-60 Count Roll-Over Interrupt Source, in SR2:RTCCNTMOD60ROLLINT    */
+#define BITP_RTC_CR1_CNTROLLINTEN             3            /*  Enable for the RTC Count Roll-Over Interrupt Source, in SR2:RTCCNTROLLINT */
+#define BITP_RTC_CR1_TRMINTEN                 2            /*  Enable for the RTC Trim Interrupt Source, in SR2:RTCTRMINT */
+#define BITP_RTC_CR1_PSINTEN                  1            /*  Enable for the Prescaled, Modulo-1 Interrupt Source, in SR2:RTCPSINT */
+#define BITP_RTC_CR1_CNTINTEN                 0            /*  Enable for the RTC Count Interrupt Source */
+#define BITM_RTC_CR1_PRESCALE2EXP            (_ADI_MSK_3(0x000001E0,0x000001E0U, uint16_t  ))    /*  Prescale Power of 2 Division Factor for the RTC Base Clock */
+#define BITM_RTC_CR1_CNTMOD60ROLLINTEN       (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Enable for the RTC Modulo-60 Count Roll-Over Interrupt Source, in SR2:RTCCNTMOD60ROLLINT    */
+#define BITM_RTC_CR1_CNTROLLINTEN            (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Enable for the RTC Count Roll-Over Interrupt Source, in SR2:RTCCNTROLLINT */
+#define BITM_RTC_CR1_TRMINTEN                (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Enable for the RTC Trim Interrupt Source, in SR2:RTCTRMINT */
+#define BITM_RTC_CR1_PSINTEN                 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Enable for the Prescaled, Modulo-1 Interrupt Source, in SR2:RTCPSINT */
+#define BITM_RTC_CR1_CNTINTEN                (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Enable for the RTC Count Interrupt Source */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SR2                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SR2_WSYNCALM2MIR            15            /*  Synchronization Status of Posted Writes to ALM2 */
+#define BITP_RTC_SR2_WSYNCCR1MIR             14            /*  Synchronization Status of Posted Writes to CR1 */
+#define BITP_RTC_SR2_WPNDALM2MIR             13            /*  Pending Status of Posted Writes to ALM2 */
+#define BITP_RTC_SR2_WPNDCR1MIR              12            /*  Pending Status of Posted Writes to CR1 */
+#define BITP_RTC_SR2_TRMBDYMIR                7            /*  Mirror of MOD:RTCTRMBDY */
+#define BITP_RTC_SR2_CNTMOD60ROLL             6            /*  RTC Count Modulo-60 Roll-Over */
+#define BITP_RTC_SR2_CNTROLL                  5            /*  RTC Count Roll-Over */
+#define BITP_RTC_SR2_CNTMOD60ROLLINT          4            /*  RTC Modulo-60 Count Roll-Over Interrupt Source */
+#define BITP_RTC_SR2_CNTROLLINT               3            /*  RTC Count Roll-Over Interrupt Source */
+#define BITP_RTC_SR2_TRMINT                   2            /*  RTC Trim Interrupt Source */
+#define BITP_RTC_SR2_PSINT                    1            /*  RTC Prescaled, Modulo-1 Boundary Interrupt Source */
+#define BITP_RTC_SR2_CNTINT                   0            /*  RTC Count Interrupt Source */
+#define BITM_RTC_SR2_WSYNCALM2MIR            (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Synchronization Status of Posted Writes to ALM2 */
+#define BITM_RTC_SR2_WSYNCCR1MIR             (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Synchronization Status of Posted Writes to CR1 */
+#define BITM_RTC_SR2_WPNDALM2MIR             (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Pending Status of Posted Writes to ALM2 */
+#define BITM_RTC_SR2_WPNDCR1MIR              (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Pending Status of Posted Writes to CR1 */
+#define BITM_RTC_SR2_TRMBDYMIR               (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Mirror of MOD:RTCTRMBDY */
+#define BITM_RTC_SR2_CNTMOD60ROLL            (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  RTC Count Modulo-60 Roll-Over */
+#define BITM_RTC_SR2_CNTROLL                 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  RTC Count Roll-Over */
+#define BITM_RTC_SR2_CNTMOD60ROLLINT         (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  RTC Modulo-60 Count Roll-Over Interrupt Source */
+#define BITM_RTC_SR2_CNTROLLINT              (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  RTC Count Roll-Over Interrupt Source */
+#define BITM_RTC_SR2_TRMINT                  (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  RTC Trim Interrupt Source */
+#define BITM_RTC_SR2_PSINT                   (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  RTC Prescaled, Modulo-1 Boundary Interrupt Source */
+#define BITM_RTC_SR2_CNTINT                  (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  RTC Count Interrupt Source */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SNAP0                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SNAP0_VALUE                  0            /*  Constituent Part of the 47-bit Input Capture Channel 0, Containing a Sticky Snapshot of  CNT0 */
+#define BITM_RTC_SNAP0_VALUE                 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Constituent Part of the 47-bit Input Capture Channel 0, Containing a Sticky Snapshot of  CNT0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SNAP1                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SNAP1_VALUE                  0            /*  Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of  CNT1 */
+#define BITM_RTC_SNAP1_VALUE                 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of  CNT1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SNAP2                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SNAP2_VALUE                  0            /*  Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT2 */
+#define BITM_RTC_SNAP2_VALUE                 (_ADI_MSK_3(0x00007FFF,0x00007FFFU, uint16_t  ))    /*  Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_MOD                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_MOD_CNT0_4TOZERO            11            /*  Mirror of CNT0[4:0] */
+#define BITP_RTC_MOD_TRMBDY                  10            /*  Trim Boundary Indicator */
+#define BITP_RTC_MOD_INCR                     6            /*  Most Recent Increment Value Added to the RTC Count in CNT1 and CNT0 */
+#define BITP_RTC_MOD_CNTMOD60                 0            /*  Modulo-60 Value of the RTC Count: CNT1 and CNT0 */
+#define BITM_RTC_MOD_CNT0_4TOZERO            (_ADI_MSK_3(0x0000F800,0x0000F800U, uint16_t  ))    /*  Mirror of CNT0[4:0] */
+#define BITM_RTC_MOD_TRMBDY                  (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Trim Boundary Indicator */
+#define BITM_RTC_MOD_INCR                    (_ADI_MSK_3(0x000003C0,0x000003C0U, uint16_t  ))    /*  Most Recent Increment Value Added to the RTC Count in CNT1 and CNT0 */
+#define BITM_RTC_MOD_CNTMOD60                (_ADI_MSK_3(0x0000003F,0x0000003FU, uint16_t  ))    /*  Modulo-60 Value of the RTC Count: CNT1 and CNT0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_CNT2                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_CNT2_VALUE                   0            /*  Fractional Bits of the RTC Real-Time Count */
+#define BITM_RTC_CNT2_VALUE                  (_ADI_MSK_3(0x00007FFF,0x00007FFFU, uint16_t  ))    /*  Fractional Bits of the RTC Real-Time Count */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_ALM2                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_ALM2_VALUE                   0            /*  Fractional Bits of the Alarm Target Time */
+#define BITM_RTC_ALM2_VALUE                  (_ADI_MSK_3(0x00007FFF,0x00007FFFU, uint16_t  ))    /*  Fractional Bits of the Alarm Target Time */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SR3                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SR3_SS1IRQ                   9            /*  Sticky Interrupt Source for SensorStrobe Channel 1 */
+#define BITP_RTC_SR3_ALMINTMIR                8            /*  Read-only Mirror of the ALMINT Interrupt Source in SR0 Register */
+#define BITP_RTC_SR3_IC4IRQ                   4            /*  Sticky Interrupt Source for the RTC Input Capture Channel 4 */
+#define BITP_RTC_SR3_IC3IRQ                   3            /*  Sticky Interrupt Source for the RTC Input Capture Channel 3 */
+#define BITP_RTC_SR3_IC2IRQ                   2            /*  Sticky Interrupt Source for the RTC Input Capture Channel 2 */
+#define BITP_RTC_SR3_IC0IRQ                   0            /*  Sticky Interrupt Source for the RTC Input Capture Channel 0 */
+#define BITM_RTC_SR3_SS1IRQ                  (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Sticky Interrupt Source for SensorStrobe Channel 1 */
+#define BITM_RTC_SR3_ALMINTMIR               (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Read-only Mirror of the ALMINT Interrupt Source in SR0 Register */
+#define BITM_RTC_SR3_IC4IRQ                  (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Sticky Interrupt Source for the RTC Input Capture Channel 4 */
+#define BITM_RTC_SR3_IC3IRQ                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Sticky Interrupt Source for the RTC Input Capture Channel 3 */
+#define BITM_RTC_SR3_IC2IRQ                  (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Sticky Interrupt Source for the RTC Input Capture Channel 2 */
+#define BITM_RTC_SR3_IC0IRQ                  (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Sticky Interrupt Source for the RTC Input Capture Channel 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_CR2IC                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_CR2IC_ICOWUSEN              15            /*  Enable Overwrite of Unread Snapshots for All Input Capture Channels */
+#define BITP_RTC_CR2IC_IC4IRQEN              14            /*  Interrupt Enable for the RTC Input Capture Channel 4 */
+#define BITP_RTC_CR2IC_IC3IRQEN              13            /*  Interrupt Enable for the RTC Input Capture Channel 3 */
+#define BITP_RTC_CR2IC_IC2IRQEN              12            /*  Interrupt Enable for the RTC Input Capture Channel 2 */
+#define BITP_RTC_CR2IC_IC0IRQEN              10            /*  Interrupt Enable for the RTC Input Capture Channel 0 */
+#define BITP_RTC_CR2IC_IC4LH                  9            /*  Polarity of the Active-going Capture Edge for the Input Capture Channel 4 */
+#define BITP_RTC_CR2IC_IC3LH                  8            /*  Polarity of the Active-going Capture Edge for the Input Capture Channel 3 */
+#define BITP_RTC_CR2IC_IC2LH                  7            /*  Polarity of the Active-going Capture Edge for the Input Capture Channel 2 */
+#define BITP_RTC_CR2IC_IC0LH                  5            /*  Polarity of the Active-Going Capture Edge for the RTC Input Capture Channel 0 */
+#define BITP_RTC_CR2IC_IC4EN                  4            /*  Enable for the RTC Input Capture Channel 4 */
+#define BITP_RTC_CR2IC_IC3EN                  3            /*  Enable for the RTC Input Capture Channel 3 */
+#define BITP_RTC_CR2IC_IC2EN                  2            /*  Enable for the RTC Input Capture Channel 2 */
+#define BITP_RTC_CR2IC_IC0EN                  0            /*  Enable for the RTC Input Capture Channel 0 */
+#define BITM_RTC_CR2IC_ICOWUSEN              (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Enable Overwrite of Unread Snapshots for All Input Capture Channels */
+#define BITM_RTC_CR2IC_IC4IRQEN              (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Interrupt Enable for the RTC Input Capture Channel 4 */
+#define BITM_RTC_CR2IC_IC3IRQEN              (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Interrupt Enable for the RTC Input Capture Channel 3 */
+#define BITM_RTC_CR2IC_IC2IRQEN              (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Interrupt Enable for the RTC Input Capture Channel 2 */
+#define BITM_RTC_CR2IC_IC0IRQEN              (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Interrupt Enable for the RTC Input Capture Channel 0 */
+#define BITM_RTC_CR2IC_IC4LH                 (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Polarity of the Active-going Capture Edge for the Input Capture Channel 4 */
+#define BITM_RTC_CR2IC_IC3LH                 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Polarity of the Active-going Capture Edge for the Input Capture Channel 3 */
+#define BITM_RTC_CR2IC_IC2LH                 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Polarity of the Active-going Capture Edge for the Input Capture Channel 2 */
+#define BITM_RTC_CR2IC_IC0LH                 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Polarity of the Active-Going Capture Edge for the RTC Input Capture Channel 0 */
+#define BITM_RTC_CR2IC_IC4EN                 (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Enable for the RTC Input Capture Channel 4 */
+#define BITM_RTC_CR2IC_IC3EN                 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Enable for the RTC Input Capture Channel 3 */
+#define BITM_RTC_CR2IC_IC2EN                 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Enable for the RTC Input Capture Channel 2 */
+#define BITM_RTC_CR2IC_IC0EN                 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Enable for the RTC Input Capture Channel 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_CR3SS                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_CR3SS_SS1IRQEN               9            /*  Interrupt Enable for SensorStrobe Channel 1 */
+#define BITP_RTC_CR3SS_SS1EN                  1            /*  Enable for SensorStrobe Channel 1 */
+#define BITM_RTC_CR3SS_SS1IRQEN              (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Interrupt Enable for SensorStrobe Channel 1 */
+#define BITM_RTC_CR3SS_SS1EN                 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Enable for SensorStrobe Channel 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_CR4SS                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_CR4SS_SS1ARLEN               9            /*  Enable for Auto-Reloading When SensorStrobe Match Occurs */
+#define BITP_RTC_CR4SS_SS1MSKEN               1            /*  Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 */
+#define BITM_RTC_CR4SS_SS1ARLEN              (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Enable for Auto-Reloading When SensorStrobe Match Occurs */
+#define BITM_RTC_CR4SS_SS1MSKEN              (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 */
+#define ENUM_RTC_CR4SS_NO_MSK                (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  SS1MSKEN: Do not apply a mask to SensorStrobe Channel 1 Register */
+#define ENUM_RTC_CR4SS_THERM_MSK             (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  SS1MSKEN: Apply thermometer decoded mask */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SSMSK                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SSMSK_SSMSK                  0            /*  Thermometer-Encoded Masks for SensorStrobe Channels */
+#define BITM_RTC_SSMSK_SSMSK                 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Thermometer-Encoded Masks for SensorStrobe Channels */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SS1ARL                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SS1ARL_SS1ARL                0            /*  Auto-Reload Value When SensorStrobe Match Occurs */
+#define BITM_RTC_SS1ARL_SS1ARL               (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Auto-Reload Value When SensorStrobe Match Occurs */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_IC2                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_IC2_IC2                      0            /*  RTC Input Capture Channel 2 */
+#define BITM_RTC_IC2_IC2                     (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  RTC Input Capture Channel 2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_IC3                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_IC3_IC3                      0            /*  RTC Input Capture Channel 3 */
+#define BITM_RTC_IC3_IC3                     (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  RTC Input Capture Channel 3 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_IC4                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_IC4_IC4                      0            /*  RTC Input Capture Channel 4 */
+#define BITM_RTC_IC4_IC4                     (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  RTC Input Capture Channel 4 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SS1                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SS1_SS1                      0            /*  SensorStrobe Channel 1 */
+#define BITM_RTC_SS1_SS1                     (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  SensorStrobe Channel 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SR4                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SR4_RSYNCIC4                14            /*  Synchronization Status of Posted Reads of RTC Input Channel 4 */
+#define BITP_RTC_SR4_RSYNCIC3                13            /*  Synchronization Status of Posted Reads of RTC Input Channel 3 */
+#define BITP_RTC_SR4_RSYNCIC2                12            /*  Synchronization Status of Posted Reads of RTC Input Channel 2 */
+#define BITP_RTC_SR4_RSYNCIC0                10            /*  Synchronization Status of Posted Reads of RTC Input Channel 0 */
+#define BITP_RTC_SR4_WSYNCSS1                 6            /*  Synchronization Status of Posted Writes to SensorStrobe Channel 1 */
+#define BITP_RTC_SR4_WSYNCSS1ARL              5            /*  Synchronization Status of Posted Writes to RTC Auto-Reload for SensorStrobe Channel 1 Register */
+#define BITP_RTC_SR4_WSYNCSSMSK               4            /*  Synchronization Status of Posted Writes to Masks for SensorStrobe Channel Register */
+#define BITP_RTC_SR4_WSYNCCR4SS               3            /*  Synchronization Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */
+#define BITP_RTC_SR4_WSYNCCR3SS               2            /*  Synchronization Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */
+#define BITP_RTC_SR4_WSYNCCR2IC               1            /*  Synchronization Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */
+#define BITP_RTC_SR4_WSYNCSR3                 0            /*  Synchronisation Status of Posted Writes to SR3 */
+#define BITM_RTC_SR4_RSYNCIC4                (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Synchronization Status of Posted Reads of RTC Input Channel 4 */
+#define BITM_RTC_SR4_RSYNCIC3                (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Synchronization Status of Posted Reads of RTC Input Channel 3 */
+#define BITM_RTC_SR4_RSYNCIC2                (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Synchronization Status of Posted Reads of RTC Input Channel 2 */
+#define BITM_RTC_SR4_RSYNCIC0                (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Synchronization Status of Posted Reads of RTC Input Channel 0 */
+#define BITM_RTC_SR4_WSYNCSS1                (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Synchronization Status of Posted Writes to SensorStrobe Channel 1 */
+#define BITM_RTC_SR4_WSYNCSS1ARL             (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Synchronization Status of Posted Writes to RTC Auto-Reload for SensorStrobe Channel 1 Register */
+#define BITM_RTC_SR4_WSYNCSSMSK              (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Synchronization Status of Posted Writes to Masks for SensorStrobe Channel Register */
+#define BITM_RTC_SR4_WSYNCCR4SS              (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Synchronization Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */
+#define BITM_RTC_SR4_WSYNCCR3SS              (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Synchronization Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */
+#define BITM_RTC_SR4_WSYNCCR2IC              (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Synchronization Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */
+#define BITM_RTC_SR4_WSYNCSR3                (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to SR3 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SR5                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SR5_RPENDIC4                14            /*  Pending Status of Posted Reads of IC4 */
+#define BITP_RTC_SR5_RPENDIC3                13            /*  Pending Status of Posted Reads of IC3 */
+#define BITP_RTC_SR5_RPENDIC2                12            /*  Pending Status of Posted Reads of IC2 */
+#define BITP_RTC_SR5_RPENDIC0                10            /*  Pending Status of Posted Reads of Input Capture Channel 0 */
+#define BITP_RTC_SR5_WPENDSS1                 6            /*  Pending Status of Posted Writes to SensorStrobe Channel 1 */
+#define BITP_RTC_SR5_WPENDSS1ARL              5            /*  Pending Status of Posted Writes to RTC Auto-Reload for SensorStrobe Channel 1 Register */
+#define BITP_RTC_SR5_WPENDSSMSK               4            /*  Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */
+#define BITP_RTC_SR5_WPENDCR4SS               3            /*  Pending Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */
+#define BITP_RTC_SR5_WPENDCR3SS               2            /*  Pending Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */
+#define BITP_RTC_SR5_WPENDCR2IC               1            /*  Pending Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */
+#define BITP_RTC_SR5_WPENDSR3                 0            /*  Pending Status of Posted Clearances of Interrupt Sources in RTC Status 3 Register */
+#define BITM_RTC_SR5_RPENDIC4                (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Pending Status of Posted Reads of IC4 */
+#define BITM_RTC_SR5_RPENDIC3                (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Pending Status of Posted Reads of IC3 */
+#define BITM_RTC_SR5_RPENDIC2                (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Pending Status of Posted Reads of IC2 */
+#define BITM_RTC_SR5_RPENDIC0                (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Pending Status of Posted Reads of Input Capture Channel 0 */
+#define BITM_RTC_SR5_WPENDSS1                (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Pending Status of Posted Writes to SensorStrobe Channel 1 */
+#define BITM_RTC_SR5_WPENDSS1ARL             (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Pending Status of Posted Writes to RTC Auto-Reload for SensorStrobe Channel 1 Register */
+#define BITM_RTC_SR5_WPENDSSMSK              (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */
+#define BITM_RTC_SR5_WPENDCR4SS              (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Pending Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */
+#define BITM_RTC_SR5_WPENDCR3SS              (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Pending Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */
+#define BITM_RTC_SR5_WPENDCR2IC              (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Pending Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */
+#define BITM_RTC_SR5_WPENDSR3                (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Pending Status of Posted Clearances of Interrupt Sources in RTC Status 3 Register */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SR6                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SR6_FRZCNTPTR                9            /*  Pointer for the Triple-Read Sequence of FRZCNT */
+#define BITP_RTC_SR6_IC0SNAP                  8            /*  Confirmation That RTC Snapshot 0, 1, 2 Registers Reflect the Value of Input-Capture Channel RTC Input Capture Channel 0 */
+#define BITP_RTC_SR6_IC4UNR                   4            /*  Sticky Unread Status of the Input Capture Channel 4 */
+#define BITP_RTC_SR6_IC3UNR                   3            /*  Sticky Unread Status of the Input Capture Channel 3 */
+#define BITP_RTC_SR6_IC2UNR                   2            /*  Sticky Unread Status of the Input Capture Channel 2 */
+#define BITP_RTC_SR6_IC0UNR                   0            /*  Sticky Unread Status of the Input Capture Channel 0 */
+#define BITM_RTC_SR6_FRZCNTPTR               (_ADI_MSK_3(0x00000600,0x00000600U, uint16_t  ))    /*  Pointer for the Triple-Read Sequence of FRZCNT */
+#define BITM_RTC_SR6_IC0SNAP                 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Confirmation That RTC Snapshot 0, 1, 2 Registers Reflect the Value of Input-Capture Channel RTC Input Capture Channel 0 */
+#define BITM_RTC_SR6_IC4UNR                  (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Sticky Unread Status of the Input Capture Channel 4 */
+#define BITM_RTC_SR6_IC3UNR                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Sticky Unread Status of the Input Capture Channel 3 */
+#define BITM_RTC_SR6_IC2UNR                  (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Sticky Unread Status of the Input Capture Channel 2 */
+#define BITM_RTC_SR6_IC0UNR                  (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Sticky Unread Status of the Input Capture Channel 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SS1TGT                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SS1TGT_SS1TGT                0            /*  Current Target Value for the SensorStrobe Channel 1 */
+#define BITM_RTC_SS1TGT_SS1TGT               (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Current Target Value for the SensorStrobe Channel 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_FRZCNT                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_FRZCNT_FRZCNT                0            /*  RTC Freeze Count. Coherent, Triple 16-Bit Read of the 47-Bit RTC Count */
+#define BITM_RTC_FRZCNT_FRZCNT               (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  RTC Freeze Count. Coherent, Triple 16-Bit Read of the 47-Bit RTC Count */
+
+
+/* ============================================================================================================================
+        System Identification and Debug Enable
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        SYS
+   ============================================================================================================================ */
+#define REG_SYS_ADIID                        0x40002020            /*  SYS ADI Identification */
+#define REG_SYS_CHIPID                       0x40002024            /*  SYS Chip Identifier */
+#define REG_SYS_SWDEN                        0x40002040            /*  SYS Serial Wire Debug Enable */
+
+/* ============================================================================================================================
+        SYS Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          SYS_ADIID                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SYS_ADIID_VALUE                  0            /*  ADI Cortex Device */
+#define BITM_SYS_ADIID_VALUE                 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  ADI Cortex Device */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SYS_CHIPID                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SYS_CHIPID_PARTID                4            /*  Part Identifier */
+#define BITP_SYS_CHIPID_REV                   0            /*  Silicon Revision */
+#define BITM_SYS_CHIPID_PARTID               (_ADI_MSK_3(0x0000FFF0,0x0000FFF0U, uint16_t  ))    /*  Part Identifier */
+#define BITM_SYS_CHIPID_REV                  (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t  ))    /*  Silicon Revision */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SYS_SWDEN                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SYS_SWDEN_VALUE                  0            /*  SWD Interface Enable */
+#define BITM_SYS_SWDEN_VALUE                 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  SWD Interface Enable */
+
+
+/* ============================================================================================================================
+        Watchdog Timer
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        WDT0
+   ============================================================================================================================ */
+#define REG_WDT0_LOAD                        0x40002C00            /*  WDT0 Load Value */
+#define REG_WDT0_CCNT                        0x40002C04            /*  WDT0 Current Count Value */
+#define REG_WDT0_CTL                         0x40002C08            /*  WDT0 Control */
+#define REG_WDT0_RESTART                     0x40002C0C            /*  WDT0 Clear Interrupt */
+#define REG_WDT0_STAT                        0x40002C18            /*  WDT0 Status */
+
+/* ============================================================================================================================
+        WDT Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          WDT_LOAD                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_WDT_LOAD_VALUE                   0            /*  Load Value */
+#define BITM_WDT_LOAD_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Load Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          WDT_CCNT                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_WDT_CCNT_VALUE                   0            /*  Current Count Value */
+#define BITM_WDT_CCNT_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Current Count Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          WDT_CTL                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_WDT_CTL_SPARE                    7            /*  Unused Spare Bit */
+#define BITP_WDT_CTL_MODE                     6            /*  Timer Mode */
+#define BITP_WDT_CTL_EN                       5            /*  Timer Enable */
+#define BITP_WDT_CTL_PRE                      2            /*  Prescaler */
+#define BITP_WDT_CTL_IRQ                      1            /*  Timer Interrupt */
+#define BITM_WDT_CTL_SPARE                   (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Unused Spare Bit */
+#define BITM_WDT_CTL_MODE                    (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Timer Mode */
+#define BITM_WDT_CTL_EN                      (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Timer Enable */
+#define BITM_WDT_CTL_PRE                     (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t  ))    /*  Prescaler */
+#define BITM_WDT_CTL_IRQ                     (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Timer Interrupt */
+#define ENUM_WDT_CTL_FREE_RUN                (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  MODE: Free running mode */
+#define ENUM_WDT_CTL_PERIODIC                (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  MODE: Periodic mode */
+#define ENUM_WDT_CTL_WDT_DIS                 (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  EN: WDT not enabled */
+#define ENUM_WDT_CTL_WDT_EN                  (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  EN: WDT enabled */
+#define ENUM_WDT_CTL_DIV1                    (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  PRE: Source clock/1 */
+#define ENUM_WDT_CTL_DIV16                   (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  PRE: Source clock/16 */
+#define ENUM_WDT_CTL_DIV256                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  PRE: Source clock/256 (default) */
+#define ENUM_WDT_CTL_RST                     (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  IRQ: WDT asserts reset when timed out */
+#define ENUM_WDT_CTL_INT                     (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  IRQ: WDT generates interrupt when timed out */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          WDT_RESTART                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_WDT_RESTART_CLRWORD              0            /*  Clear Watchdog */
+#define BITM_WDT_RESTART_CLRWORD             (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Clear Watchdog */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          WDT_STAT                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_WDT_STAT_RSTCTL                  5            /*  Reset Control Register Written and Locked */
+#define BITP_WDT_STAT_LOCKED                  4            /*  Lock Status Bit */
+#define BITP_WDT_STAT_COUNTING                3            /*  Control Register Write Sync in Progress */
+#define BITP_WDT_STAT_LOADING                 2            /*  Load Register Write Sync in Progress */
+#define BITP_WDT_STAT_CLRIRQ                  1            /*  Clear Interrupt Register Write Sync in Progress */
+#define BITP_WDT_STAT_IRQ                     0            /*  WDT Interrupt */
+#define BITM_WDT_STAT_RSTCTL                 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Reset Control Register Written and Locked */
+#define BITM_WDT_STAT_LOCKED                 (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Lock Status Bit */
+#define BITM_WDT_STAT_COUNTING               (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Control Register Write Sync in Progress */
+#define BITM_WDT_STAT_LOADING                (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Load Register Write Sync in Progress */
+#define BITM_WDT_STAT_CLRIRQ                 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Clear Interrupt Register Write Sync in Progress */
+#define BITM_WDT_STAT_IRQ                    (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  WDT Interrupt */
+
+
+/* ============================================================================================================================
+        I2C Master/Slave
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        I2C0
+   ============================================================================================================================ */
+#define REG_I2C0_MCTL                        0x40003000            /*  I2C0 Master Control */
+#define REG_I2C0_MSTAT                       0x40003004            /*  I2C0 Master Status */
+#define REG_I2C0_MRX                         0x40003008            /*  I2C0 Master Receive Data */
+#define REG_I2C0_MTX                         0x4000300C            /*  I2C0 Master Transmit Data */
+#define REG_I2C0_MRXCNT                      0x40003010            /*  I2C0 Master Receive Data Count */
+#define REG_I2C0_MCRXCNT                     0x40003014            /*  I2C0 Master Current Receive Data Count */
+#define REG_I2C0_ADDR1                       0x40003018            /*  I2C0 Master Address Byte 1 */
+#define REG_I2C0_ADDR2                       0x4000301C            /*  I2C0 Master Address Byte 2 */
+#define REG_I2C0_BYT                         0x40003020            /*  I2C0 Start Byte */
+#define REG_I2C0_DIV                         0x40003024            /*  I2C0 Serial Clock Period Divisor */
+#define REG_I2C0_SCTL                        0x40003028            /*  I2C0 Slave Control */
+#define REG_I2C0_SSTAT                       0x4000302C            /*  I2C0 Slave I2C Status/Error/IRQ */
+#define REG_I2C0_SRX                         0x40003030            /*  I2C0 Slave Receive */
+#define REG_I2C0_STX                         0x40003034            /*  I2C0 Slave Transmit */
+#define REG_I2C0_ALT                         0x40003038            /*  I2C0 Hardware General Call ID */
+#define REG_I2C0_ID0                         0x4000303C            /*  I2C0 First Slave Address Device ID */
+#define REG_I2C0_ID1                         0x40003040            /*  I2C0 Second Slave Address Device ID */
+#define REG_I2C0_ID2                         0x40003044            /*  I2C0 Third Slave Address Device ID */
+#define REG_I2C0_ID3                         0x40003048            /*  I2C0 Fourth Slave Address Device ID */
+#define REG_I2C0_STAT                        0x4000304C            /*  I2C0 Master and Slave FIFO Status */
+#define REG_I2C0_SHCTL                       0x40003050            /*  I2C0 Shared Control */
+#define REG_I2C0_TCTL                        0x40003054            /*  I2C0 Timing Control Register */
+#define REG_I2C0_ASTRETCH_SCL                0x40003058            /*  I2C0 Automatic Stretch SCL */
+
+/* ============================================================================================================================
+        I2C Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_MCTL                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_MCTL_STOPBUSCLR             13            /*  Prestop Bus Clear */
+#define BITP_I2C_MCTL_BUSCLR                 12            /*  Bus-Clear Enable */
+#define BITP_I2C_MCTL_MTXDMA                 11            /*  Enable Master Tx DMA Request */
+#define BITP_I2C_MCTL_MRXDMA                 10            /*  Enable Master Rx DMA Request */
+#define BITP_I2C_MCTL_MXMITDEC                9            /*  Decrement Master Tx FIFO Status When a Byte Txed */
+#define BITP_I2C_MCTL_IENCMP                  8            /*  Transaction Completed (or Stop Detected) Interrupt Enable */
+#define BITP_I2C_MCTL_IENACK                  7            /*  ACK Not Received Interrupt Enable */
+#define BITP_I2C_MCTL_IENALOST                6            /*  Arbitration Lost Interrupt Enable */
+#define BITP_I2C_MCTL_IENMTX                  5            /*  Transmit Request Interrupt Enable */
+#define BITP_I2C_MCTL_IENMRX                  4            /*  Receive Request Interrupt Enable */
+#define BITP_I2C_MCTL_STRETCHSCL              3            /*  Stretch SCL Enable */
+#define BITP_I2C_MCTL_LOOPBACK                2            /*  Internal Loopback Enable */
+#define BITP_I2C_MCTL_COMPLETE                1            /*  Start Back-off Disable */
+#define BITP_I2C_MCTL_MASEN                   0            /*  Master Enable */
+#define BITM_I2C_MCTL_STOPBUSCLR             (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Prestop Bus Clear */
+#define BITM_I2C_MCTL_BUSCLR                 (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Bus-Clear Enable */
+#define BITM_I2C_MCTL_MTXDMA                 (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Enable Master Tx DMA Request */
+#define BITM_I2C_MCTL_MRXDMA                 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Enable Master Rx DMA Request */
+#define BITM_I2C_MCTL_MXMITDEC               (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Decrement Master Tx FIFO Status When a Byte Txed */
+#define BITM_I2C_MCTL_IENCMP                 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Transaction Completed (or Stop Detected) Interrupt Enable */
+#define BITM_I2C_MCTL_IENACK                 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  ACK Not Received Interrupt Enable */
+#define BITM_I2C_MCTL_IENALOST               (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Arbitration Lost Interrupt Enable */
+#define BITM_I2C_MCTL_IENMTX                 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Transmit Request Interrupt Enable */
+#define BITM_I2C_MCTL_IENMRX                 (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Receive Request Interrupt Enable */
+#define BITM_I2C_MCTL_STRETCHSCL             (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Stretch SCL Enable */
+#define BITM_I2C_MCTL_LOOPBACK               (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Internal Loopback Enable */
+#define BITM_I2C_MCTL_COMPLETE               (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Start Back-off Disable */
+#define BITM_I2C_MCTL_MASEN                  (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Master Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_MSTAT                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_MSTAT_SCLFILT               14            /*  State of SCL Line */
+#define BITP_I2C_MSTAT_SDAFILT               13            /*  State of SDA Line */
+#define BITP_I2C_MSTAT_MTXUNDR               12            /*  Master Transmit Underflow */
+#define BITP_I2C_MSTAT_MSTOP                 11            /*  STOP Driven by This I2C Master */
+#define BITP_I2C_MSTAT_LINEBUSY              10            /*  Line is Busy */
+#define BITP_I2C_MSTAT_MRXOVR                 9            /*  Master Receive FIFO Overflow */
+#define BITP_I2C_MSTAT_TCOMP                  8            /*  Transaction Complete or Stop Detected */
+#define BITP_I2C_MSTAT_NACKDATA               7            /*  ACK Not Received in Response to Data Write */
+#define BITP_I2C_MSTAT_MBUSY                  6            /*  Master Busy */
+#define BITP_I2C_MSTAT_ALOST                  5            /*  Arbitration Lost */
+#define BITP_I2C_MSTAT_NACKADDR               4            /*  ACK Not Received in Response to an Address */
+#define BITP_I2C_MSTAT_MRXREQ                 3            /*  Master Receive Request */
+#define BITP_I2C_MSTAT_MTXREQ                 2            /*  Master Transmit Request/Clear Master Transmit Interrupt */
+#define BITP_I2C_MSTAT_MTXF                   0            /*  Master Transmit FIFO Status */
+#define BITM_I2C_MSTAT_SCLFILT               (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  State of SCL Line */
+#define BITM_I2C_MSTAT_SDAFILT               (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  State of SDA Line */
+#define BITM_I2C_MSTAT_MTXUNDR               (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Master Transmit Underflow */
+#define BITM_I2C_MSTAT_MSTOP                 (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  STOP Driven by This I2C Master */
+#define BITM_I2C_MSTAT_LINEBUSY              (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Line is Busy */
+#define BITM_I2C_MSTAT_MRXOVR                (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Master Receive FIFO Overflow */
+#define BITM_I2C_MSTAT_TCOMP                 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Transaction Complete or Stop Detected */
+#define BITM_I2C_MSTAT_NACKDATA              (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  ACK Not Received in Response to Data Write */
+#define BITM_I2C_MSTAT_MBUSY                 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Master Busy */
+#define BITM_I2C_MSTAT_ALOST                 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Arbitration Lost */
+#define BITM_I2C_MSTAT_NACKADDR              (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  ACK Not Received in Response to an Address */
+#define BITM_I2C_MSTAT_MRXREQ                (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Master Receive Request */
+#define BITM_I2C_MSTAT_MTXREQ                (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Master Transmit Request/Clear Master Transmit Interrupt */
+#define BITM_I2C_MSTAT_MTXF                  (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t  ))    /*  Master Transmit FIFO Status */
+#define ENUM_I2C_MSTAT_FIFO_EMPTY            (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  MTXF: FIFO Empty. */
+#define ENUM_I2C_MSTAT_FIFO_1BYTE            (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  MTXF: 1 byte in FIFO. */
+#define ENUM_I2C_MSTAT_FIFO_FULL             (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t  ))    /*  MTXF: FIFO Full. */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_MRX                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_MRX_VALUE                    0            /*  Master Receive Register */
+#define BITM_I2C_MRX_VALUE                   (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Master Receive Register */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_MTX                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_MTX_VALUE                    0            /*  Master Transmit Register */
+#define BITM_I2C_MTX_VALUE                   (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Master Transmit Register */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_MRXCNT                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_MRXCNT_EXTEND                8            /*  Extended Read */
+#define BITP_I2C_MRXCNT_VALUE                 0            /*  Receive Count */
+#define BITM_I2C_MRXCNT_EXTEND               (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Extended Read */
+#define BITM_I2C_MRXCNT_VALUE                (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Receive Count */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_MCRXCNT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_MCRXCNT_VALUE                0            /*  Current Receive Count */
+#define BITM_I2C_MCRXCNT_VALUE               (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Current Receive Count */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_ADDR1                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_ADDR1_VALUE                  0            /*  Address Byte 1 */
+#define BITM_I2C_ADDR1_VALUE                 (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Address Byte 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_ADDR2                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_ADDR2_VALUE                  0            /*  Address Byte 2 */
+#define BITM_I2C_ADDR2_VALUE                 (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Address Byte 2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_BYT                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_BYT_SBYTE                    0            /*  Start Byte */
+#define BITM_I2C_BYT_SBYTE                   (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Start Byte */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_DIV                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_DIV_HIGH                     8            /*  Serial Clock High Time */
+#define BITP_I2C_DIV_LOW                      0            /*  Serial Clock Low Time */
+#define BITM_I2C_DIV_HIGH                    (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t  ))    /*  Serial Clock High Time */
+#define BITM_I2C_DIV_LOW                     (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Serial Clock Low Time */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_SCTL                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_SCTL_STXDMA                 14            /*  Enable Slave Tx DMA Request */
+#define BITP_I2C_SCTL_SRXDMA                 13            /*  Enable Slave Rx DMA Request */
+#define BITP_I2C_SCTL_IENREPST               12            /*  Repeated Start Interrupt Enable */
+#define BITP_I2C_SCTL_STXDEC                 11            /*  Decrement Slave Tx FIFO Status When a Byte is Txed */
+#define BITP_I2C_SCTL_IENSTX                 10            /*  Slave Transmit Request Interrupt Enable */
+#define BITP_I2C_SCTL_IENSRX                  9            /*  Slave Receive Request Interrupt Enable */
+#define BITP_I2C_SCTL_IENSTOP                 8            /*  Stop Condition Detected Interrupt Enable */
+#define BITP_I2C_SCTL_NACK                    7            /*  NACK Next Communication */
+#define BITP_I2C_SCTL_EARLYTXR                5            /*  Early Transmit Request Mode */
+#define BITP_I2C_SCTL_GCSBCLR                 4            /*  General Call Status Bit Clear */
+#define BITP_I2C_SCTL_HGCEN                   3            /*  Hardware General Call Enable */
+#define BITP_I2C_SCTL_GCEN                    2            /*  General Call Enable */
+#define BITP_I2C_SCTL_ADR10EN                 1            /*  Enabled 10-bit Addressing */
+#define BITP_I2C_SCTL_SLVEN                   0            /*  Slave Enable */
+#define BITM_I2C_SCTL_STXDMA                 (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Enable Slave Tx DMA Request */
+#define BITM_I2C_SCTL_SRXDMA                 (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Enable Slave Rx DMA Request */
+#define BITM_I2C_SCTL_IENREPST               (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Repeated Start Interrupt Enable */
+#define BITM_I2C_SCTL_STXDEC                 (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Decrement Slave Tx FIFO Status When a Byte is Txed */
+#define BITM_I2C_SCTL_IENSTX                 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Slave Transmit Request Interrupt Enable */
+#define BITM_I2C_SCTL_IENSRX                 (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Slave Receive Request Interrupt Enable */
+#define BITM_I2C_SCTL_IENSTOP                (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Stop Condition Detected Interrupt Enable */
+#define BITM_I2C_SCTL_NACK                   (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  NACK Next Communication */
+#define BITM_I2C_SCTL_EARLYTXR               (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Early Transmit Request Mode */
+#define BITM_I2C_SCTL_GCSBCLR                (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  General Call Status Bit Clear */
+#define BITM_I2C_SCTL_HGCEN                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Hardware General Call Enable */
+#define BITM_I2C_SCTL_GCEN                   (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  General Call Enable */
+#define BITM_I2C_SCTL_ADR10EN                (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Enabled 10-bit Addressing */
+#define BITM_I2C_SCTL_SLVEN                  (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Slave Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_SSTAT                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_SSTAT_START                 14            /*  Start and Matching Address */
+#define BITP_I2C_SSTAT_REPSTART              13            /*  Repeated Start and Matching Address */
+#define BITP_I2C_SSTAT_IDMAT                 11            /*  Device ID Matched */
+#define BITP_I2C_SSTAT_STOP                  10            /*  Stop After Start and Matching Address */
+#define BITP_I2C_SSTAT_GCID                   8            /*  General ID */
+#define BITP_I2C_SSTAT_GCINT                  7            /*  General Call Interrupt */
+#define BITP_I2C_SSTAT_SBUSY                  6            /*  Slave Busy */
+#define BITP_I2C_SSTAT_NOACK                  5            /*  ACK Not Generated by the Slave */
+#define BITP_I2C_SSTAT_SRXOVR                 4            /*  Slave Receive FIFO Overflow */
+#define BITP_I2C_SSTAT_SRXREQ                 3            /*  Slave Receive Request */
+#define BITP_I2C_SSTAT_STXREQ                 2            /*  Slave Transmit Request/Slave Transmit Interrupt */
+#define BITP_I2C_SSTAT_STXUNDR                1            /*  Slave Transmit FIFO Underflow */
+#define BITP_I2C_SSTAT_STXFSEREQ              0            /*  Slave Tx FIFO Status or Early Request */
+#define BITM_I2C_SSTAT_START                 (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Start and Matching Address */
+#define BITM_I2C_SSTAT_REPSTART              (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Repeated Start and Matching Address */
+#define BITM_I2C_SSTAT_IDMAT                 (_ADI_MSK_3(0x00001800,0x00001800U, uint16_t  ))    /*  Device ID Matched */
+#define BITM_I2C_SSTAT_STOP                  (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Stop After Start and Matching Address */
+#define BITM_I2C_SSTAT_GCID                  (_ADI_MSK_3(0x00000300,0x00000300U, uint16_t  ))    /*  General ID */
+#define BITM_I2C_SSTAT_GCINT                 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  General Call Interrupt */
+#define BITM_I2C_SSTAT_SBUSY                 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Slave Busy */
+#define BITM_I2C_SSTAT_NOACK                 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  ACK Not Generated by the Slave */
+#define BITM_I2C_SSTAT_SRXOVR                (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Slave Receive FIFO Overflow */
+#define BITM_I2C_SSTAT_SRXREQ                (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Slave Receive Request */
+#define BITM_I2C_SSTAT_STXREQ                (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Slave Transmit Request/Slave Transmit Interrupt */
+#define BITM_I2C_SSTAT_STXUNDR               (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Slave Transmit FIFO Underflow */
+#define BITM_I2C_SSTAT_STXFSEREQ             (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Slave Tx FIFO Status or Early Request */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_SRX                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_SRX_VALUE                    0            /*  Slave Receive Register */
+#define BITM_I2C_SRX_VALUE                   (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Slave Receive Register */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_STX                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_STX_VALUE                    0            /*  Slave Transmit Register */
+#define BITM_I2C_STX_VALUE                   (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Slave Transmit Register */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_ALT                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_ALT_ID                       0            /*  Slave Alt */
+#define BITM_I2C_ALT_ID                      (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Slave Alt */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_ID0                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_ID0_VALUE                    0            /*  Slave Device ID 0 */
+#define BITM_I2C_ID0_VALUE                   (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Slave Device ID 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_ID1                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_ID1_VALUE                    0            /*  Slave Device ID 1 */
+#define BITM_I2C_ID1_VALUE                   (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Slave Device ID 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_ID2                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_ID2_VALUE                    0            /*  Slave Device ID 2 */
+#define BITM_I2C_ID2_VALUE                   (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Slave Device ID 2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_ID3                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_ID3_VALUE                    0            /*  Slave Device ID 3 */
+#define BITM_I2C_ID3_VALUE                   (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Slave Device ID 3 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_STAT                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_STAT_MFLUSH                  9            /*  Flush the Master Transmit FIFO */
+#define BITP_I2C_STAT_SFLUSH                  8            /*  Flush the Slave Transmit FIFO */
+#define BITP_I2C_STAT_MRXF                    6            /*  Master Receive FIFO Status */
+#define BITP_I2C_STAT_MTXF                    4            /*  Master Transmit FIFO Status */
+#define BITP_I2C_STAT_SRXF                    2            /*  Slave Receive FIFO Status */
+#define BITP_I2C_STAT_STXF                    0            /*  Slave Transmit FIFO Status */
+#define BITM_I2C_STAT_MFLUSH                 (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Flush the Master Transmit FIFO */
+#define BITM_I2C_STAT_SFLUSH                 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Flush the Slave Transmit FIFO */
+#define BITM_I2C_STAT_MRXF                   (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t  ))    /*  Master Receive FIFO Status */
+#define BITM_I2C_STAT_MTXF                   (_ADI_MSK_3(0x00000030,0x00000030U, uint16_t  ))    /*  Master Transmit FIFO Status */
+#define BITM_I2C_STAT_SRXF                   (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t  ))    /*  Slave Receive FIFO Status */
+#define BITM_I2C_STAT_STXF                   (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t  ))    /*  Slave Transmit FIFO Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_SHCTL                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_SHCTL_RST                    0            /*  Reset START STOP Detect Circuit */
+#define BITM_I2C_SHCTL_RST                   (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Reset START STOP Detect Circuit */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_TCTL                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_TCTL_FILTEROFF               8            /*  Input Filter Control */
+#define BITP_I2C_TCTL_THDATIN                 0            /*  Data in Hold Start */
+#define BITM_I2C_TCTL_FILTEROFF              (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Input Filter Control */
+#define BITM_I2C_TCTL_THDATIN                (_ADI_MSK_3(0x0000001F,0x0000001FU, uint16_t  ))    /*  Data in Hold Start */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_ASTRETCH_SCL                     Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_ASTRETCH_SCL_SLVTMO          9            /*  Slave Automatic Stretch Timeout */
+#define BITP_I2C_ASTRETCH_SCL_MSTTMO          8            /*  Master Automatic Stretch Timeout */
+#define BITP_I2C_ASTRETCH_SCL_SLV             4            /*  Slave Automatic Stretch Mode */
+#define BITP_I2C_ASTRETCH_SCL_MST             0            /*  Master Automatic Stretch Mode */
+#define BITM_I2C_ASTRETCH_SCL_SLVTMO         (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Slave Automatic Stretch Timeout */
+#define BITM_I2C_ASTRETCH_SCL_MSTTMO         (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Master Automatic Stretch Timeout */
+#define BITM_I2C_ASTRETCH_SCL_SLV            (_ADI_MSK_3(0x000000F0,0x000000F0U, uint16_t  ))    /*  Slave Automatic Stretch Mode */
+#define BITM_I2C_ASTRETCH_SCL_MST            (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t  ))    /*  Master Automatic Stretch Mode */
+
+
+/* ============================================================================================================================
+        Serial Peripheral Interface
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        SPI0
+   ============================================================================================================================ */
+#define REG_SPI0_STAT                        0x40004000            /*  SPI0 Status */
+#define REG_SPI0_RX                          0x40004004            /*  SPI0 Receive */
+#define REG_SPI0_TX                          0x40004008            /*  SPI0 Transmit */
+#define REG_SPI0_DIV                         0x4000400C            /*  SPI0 SPI Baud Rate Selection */
+#define REG_SPI0_CTL                         0x40004010            /*  SPI0 SPI Configuration */
+#define REG_SPI0_IEN                         0x40004014            /*  SPI0 SPI Interrupts Enable */
+#define REG_SPI0_CNT                         0x40004018            /*  SPI0 Transfer Byte Count */
+#define REG_SPI0_DMA                         0x4000401C            /*  SPI0 SPI DMA Enable */
+#define REG_SPI0_FIFO_STAT                   0x40004020            /*  SPI0 FIFO Status */
+#define REG_SPI0_RD_CTL                      0x40004024            /*  SPI0 Read Control */
+#define REG_SPI0_FLOW_CTL                    0x40004028            /*  SPI0 Flow Control */
+#define REG_SPI0_WAIT_TMR                    0x4000402C            /*  SPI0 Wait Timer for Flow Control */
+#define REG_SPI0_CS_CTL                      0x40004030            /*  SPI0 Chip Select Control for Multi-slave Connections */
+#define REG_SPI0_CS_OVERRIDE                 0x40004034            /*  SPI0 Chip Select Override */
+
+/* ============================================================================================================================
+        SPI1
+   ============================================================================================================================ */
+#define REG_SPI1_STAT                        0x40004400            /*  SPI1 Status */
+#define REG_SPI1_RX                          0x40004404            /*  SPI1 Receive */
+#define REG_SPI1_TX                          0x40004408            /*  SPI1 Transmit */
+#define REG_SPI1_DIV                         0x4000440C            /*  SPI1 SPI Baud Rate Selection */
+#define REG_SPI1_CTL                         0x40004410            /*  SPI1 SPI Configuration */
+#define REG_SPI1_IEN                         0x40004414            /*  SPI1 SPI Interrupts Enable */
+#define REG_SPI1_CNT                         0x40004418            /*  SPI1 Transfer Byte Count */
+#define REG_SPI1_DMA                         0x4000441C            /*  SPI1 SPI DMA Enable */
+#define REG_SPI1_FIFO_STAT                   0x40004420            /*  SPI1 FIFO Status */
+#define REG_SPI1_RD_CTL                      0x40004424            /*  SPI1 Read Control */
+#define REG_SPI1_FLOW_CTL                    0x40004428            /*  SPI1 Flow Control */
+#define REG_SPI1_WAIT_TMR                    0x4000442C            /*  SPI1 Wait Timer for Flow Control */
+#define REG_SPI1_CS_CTL                      0x40004430            /*  SPI1 Chip Select Control for Multi-slave Connections */
+#define REG_SPI1_CS_OVERRIDE                 0x40004434            /*  SPI1 Chip Select Override */
+
+/* ============================================================================================================================
+        SPI2
+   ============================================================================================================================ */
+#define REG_SPI2_STAT                        0x40024000            /*  SPI2 Status */
+#define REG_SPI2_RX                          0x40024004            /*  SPI2 Receive */
+#define REG_SPI2_TX                          0x40024008            /*  SPI2 Transmit */
+#define REG_SPI2_DIV                         0x4002400C            /*  SPI2 SPI Baud Rate Selection */
+#define REG_SPI2_CTL                         0x40024010            /*  SPI2 SPI Configuration */
+#define REG_SPI2_IEN                         0x40024014            /*  SPI2 SPI Interrupts Enable */
+#define REG_SPI2_CNT                         0x40024018            /*  SPI2 Transfer Byte Count */
+#define REG_SPI2_DMA                         0x4002401C            /*  SPI2 SPI DMA Enable */
+#define REG_SPI2_FIFO_STAT                   0x40024020            /*  SPI2 FIFO Status */
+#define REG_SPI2_RD_CTL                      0x40024024            /*  SPI2 Read Control */
+#define REG_SPI2_FLOW_CTL                    0x40024028            /*  SPI2 Flow Control */
+#define REG_SPI2_WAIT_TMR                    0x4002402C            /*  SPI2 Wait Timer for Flow Control */
+#define REG_SPI2_CS_CTL                      0x40024030            /*  SPI2 Chip Select Control for Multi-slave Connections */
+#define REG_SPI2_CS_OVERRIDE                 0x40024034            /*  SPI2 Chip Select Override */
+
+/* ============================================================================================================================
+        SPI Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_STAT                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_STAT_RDY                    15            /*  Detected an Edge on Ready Indicator for Flow Control */
+#define BITP_SPI_STAT_CSFALL                 14            /*  Detected a Falling Edge on CS, in Slave CON Mode */
+#define BITP_SPI_STAT_CSRISE                 13            /*  Detected a Rising Edge on CS, in Slave CON Mode */
+#define BITP_SPI_STAT_CSERR                  12            /*  Detected a CS Error Condition in Slave Mode */
+#define BITP_SPI_STAT_CS                     11            /*  CS Status */
+#define BITP_SPI_STAT_RXOVR                   7            /*  SPI Rx FIFO Overflow */
+#define BITP_SPI_STAT_RXIRQ                   6            /*  SPI Rx IRQ */
+#define BITP_SPI_STAT_TXIRQ                   5            /*  SPI Tx IRQ */
+#define BITP_SPI_STAT_TXUNDR                  4            /*  SPI Tx FIFO Underflow */
+#define BITP_SPI_STAT_TXDONE                  3            /*  SPI Tx Done in Read Command Mode */
+#define BITP_SPI_STAT_TXEMPTY                 2            /*  SPI Tx FIFO Empty Interrupt */
+#define BITP_SPI_STAT_XFRDONE                 1            /*  SPI Transfer Completion */
+#define BITP_SPI_STAT_IRQ                     0            /*  SPI Interrupt Status */
+#define BITM_SPI_STAT_RDY                    (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Detected an Edge on Ready Indicator for Flow Control */
+#define BITM_SPI_STAT_CSFALL                 (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Detected a Falling Edge on CS, in Slave CON Mode */
+#define BITM_SPI_STAT_CSRISE                 (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Detected a Rising Edge on CS, in Slave CON Mode */
+#define BITM_SPI_STAT_CSERR                  (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Detected a CS Error Condition in Slave Mode */
+#define BITM_SPI_STAT_CS                     (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  CS Status */
+#define BITM_SPI_STAT_RXOVR                  (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  SPI Rx FIFO Overflow */
+#define BITM_SPI_STAT_RXIRQ                  (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  SPI Rx IRQ */
+#define BITM_SPI_STAT_TXIRQ                  (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  SPI Tx IRQ */
+#define BITM_SPI_STAT_TXUNDR                 (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  SPI Tx FIFO Underflow */
+#define BITM_SPI_STAT_TXDONE                 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  SPI Tx Done in Read Command Mode */
+#define BITM_SPI_STAT_TXEMPTY                (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  SPI Tx FIFO Empty Interrupt */
+#define BITM_SPI_STAT_XFRDONE                (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  SPI Transfer Completion */
+#define BITM_SPI_STAT_IRQ                    (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  SPI Interrupt Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_RX                               Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_RX_BYTE2                     8            /*  8-bit Receive Buffer, Used Only in DMA Modes */
+#define BITP_SPI_RX_BYTE1                     0            /*  8-bit Receive Buffer */
+#define BITM_SPI_RX_BYTE2                    (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t  ))    /*  8-bit Receive Buffer, Used Only in DMA Modes */
+#define BITM_SPI_RX_BYTE1                    (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  8-bit Receive Buffer */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_TX                               Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_TX_BYTE2                     8            /*  8-bit Transmit Buffer, Used Only in DMA Modes */
+#define BITP_SPI_TX_BYTE1                     0            /*  8-bit Transmit Buffer */
+#define BITM_SPI_TX_BYTE2                    (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t  ))    /*  8-bit Transmit Buffer, Used Only in DMA Modes */
+#define BITM_SPI_TX_BYTE1                    (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  8-bit Transmit Buffer */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_DIV                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_DIV_VALUE                    0            /*  SPI Clock Divider */
+#define BITM_SPI_DIV_VALUE                   (_ADI_MSK_3(0x0000003F,0x0000003FU, uint16_t  ))    /*  SPI Clock Divider */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_CTL                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_CTL_CSRST                   14            /*  Reset Mode for CS Error Bit */
+#define BITP_SPI_CTL_TFLUSH                  13            /*  SPI Tx FIFO Flush Enable */
+#define BITP_SPI_CTL_RFLUSH                  12            /*  SPI Rx FIFO Flush Enable */
+#define BITP_SPI_CTL_CON                     11            /*  Continuous Transfer Enable */
+#define BITP_SPI_CTL_LOOPBACK                10            /*  Loopback Enable */
+#define BITP_SPI_CTL_OEN                      9            /*  Slave MISO Output Enable */
+#define BITP_SPI_CTL_RXOF                     8            /*  Rx Overflow Overwrite Enable */
+#define BITP_SPI_CTL_ZEN                      7            /*  Transmit Zeros Enable */
+#define BITP_SPI_CTL_TIM                      6            /*  SPI Transfer and Interrupt Mode */
+#define BITP_SPI_CTL_LSB                      5            /*  LSB First Transfer Enable */
+#define BITP_SPI_CTL_WOM                      4            /*  SPI Wired-OR Mode */
+#define BITP_SPI_CTL_CPOL                     3            /*  Serial Clock Polarity */
+#define BITP_SPI_CTL_CPHA                     2            /*  Serial Clock Phase Mode */
+#define BITP_SPI_CTL_MASEN                    1            /*  Master Mode Enable */
+#define BITP_SPI_CTL_SPIEN                    0            /*  SPI Enable */
+#define BITM_SPI_CTL_CSRST                   (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Reset Mode for CS Error Bit */
+#define BITM_SPI_CTL_TFLUSH                  (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  SPI Tx FIFO Flush Enable */
+#define BITM_SPI_CTL_RFLUSH                  (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  SPI Rx FIFO Flush Enable */
+#define BITM_SPI_CTL_CON                     (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Continuous Transfer Enable */
+#define BITM_SPI_CTL_LOOPBACK                (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Loopback Enable */
+#define BITM_SPI_CTL_OEN                     (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Slave MISO Output Enable */
+#define BITM_SPI_CTL_RXOF                    (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Rx Overflow Overwrite Enable */
+#define BITM_SPI_CTL_ZEN                     (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Transmit Zeros Enable */
+#define BITM_SPI_CTL_TIM                     (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  SPI Transfer and Interrupt Mode */
+#define BITM_SPI_CTL_LSB                     (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  LSB First Transfer Enable */
+#define BITM_SPI_CTL_WOM                     (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  SPI Wired-OR Mode */
+#define BITM_SPI_CTL_CPOL                    (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Serial Clock Polarity */
+#define BITM_SPI_CTL_CPHA                    (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Serial Clock Phase Mode */
+#define BITM_SPI_CTL_MASEN                   (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Master Mode Enable */
+#define BITM_SPI_CTL_SPIEN                   (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  SPI Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_IEN                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_IEN_TXEMPTY                 14            /*  Tx FIFO Empty Interrupt Enable */
+#define BITP_SPI_IEN_XFRDONE                 13            /*  SPI Transfer Completion Interrupt Enable */
+#define BITP_SPI_IEN_TXDONE                  12            /*  SPI Transmit Done Interrupt Enable */
+#define BITP_SPI_IEN_RDY                     11            /*  Ready Signal Edge Interrupt Enable */
+#define BITP_SPI_IEN_RXOVR                   10            /*  Rx Overflow Interrupt Enable */
+#define BITP_SPI_IEN_TXUNDR                   9            /*  Tx Underflow Interrupt Enable */
+#define BITP_SPI_IEN_CS                       8            /*  Enable Interrupt on Every CS Edge in Slave CON Mode */
+#define BITP_SPI_IEN_IRQMODE                  0            /*  SPI IRQ Mode Bits */
+#define BITM_SPI_IEN_TXEMPTY                 (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Tx FIFO Empty Interrupt Enable */
+#define BITM_SPI_IEN_XFRDONE                 (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  SPI Transfer Completion Interrupt Enable */
+#define BITM_SPI_IEN_TXDONE                  (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  SPI Transmit Done Interrupt Enable */
+#define BITM_SPI_IEN_RDY                     (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Ready Signal Edge Interrupt Enable */
+#define BITM_SPI_IEN_RXOVR                   (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Rx Overflow Interrupt Enable */
+#define BITM_SPI_IEN_TXUNDR                  (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Tx Underflow Interrupt Enable */
+#define BITM_SPI_IEN_CS                      (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Enable Interrupt on Every CS Edge in Slave CON Mode */
+#define BITM_SPI_IEN_IRQMODE                 (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t  ))    /*  SPI IRQ Mode Bits */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_CNT                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_CNT_FRAMECONT               15            /*  Continue Frame */
+#define BITP_SPI_CNT_VALUE                    0            /*  Transfer Byte Count */
+#define BITM_SPI_CNT_FRAMECONT               (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Continue Frame */
+#define BITM_SPI_CNT_VALUE                   (_ADI_MSK_3(0x00003FFF,0x00003FFFU, uint16_t  ))    /*  Transfer Byte Count */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_DMA                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_DMA_RXEN                     2            /*  Enable Receive DMA Request */
+#define BITP_SPI_DMA_TXEN                     1            /*  Enable Transmit DMA Request */
+#define BITP_SPI_DMA_EN                       0            /*  Enable DMA for Data Transfer */
+#define BITM_SPI_DMA_RXEN                    (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Enable Receive DMA Request */
+#define BITM_SPI_DMA_TXEN                    (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Enable Transmit DMA Request */
+#define BITM_SPI_DMA_EN                      (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Enable DMA for Data Transfer */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_FIFO_STAT                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_FIFO_STAT_RX                 8            /*  SPI Rx FIFO Dtatus */
+#define BITP_SPI_FIFO_STAT_TX                 0            /*  SPI Tx FIFO Status */
+#define BITM_SPI_FIFO_STAT_RX                (_ADI_MSK_3(0x00000F00,0x00000F00U, uint16_t  ))    /*  SPI Rx FIFO Dtatus */
+#define BITM_SPI_FIFO_STAT_TX                (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t  ))    /*  SPI Tx FIFO Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_RD_CTL                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_RD_CTL_THREEPIN              8            /*  Three Pin SPI Mode */
+#define BITP_SPI_RD_CTL_TXBYTES               2            /*  Transmit Byte Count - 1 (Read Command) */
+#define BITP_SPI_RD_CTL_OVERLAP               1            /*  Tx/Rx Overlap Mode */
+#define BITP_SPI_RD_CTL_CMDEN                 0            /*  Read Command Enable */
+#define BITM_SPI_RD_CTL_THREEPIN             (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Three Pin SPI Mode */
+#define BITM_SPI_RD_CTL_TXBYTES              (_ADI_MSK_3(0x0000003C,0x0000003CU, uint16_t  ))    /*  Transmit Byte Count - 1 (Read Command) */
+#define BITM_SPI_RD_CTL_OVERLAP              (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Tx/Rx Overlap Mode */
+#define BITM_SPI_RD_CTL_CMDEN                (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Read Command Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_FLOW_CTL                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_FLOW_CTL_RDBURSTSZ           8            /*  Read Data Burst Size - 1 */
+#define BITP_SPI_FLOW_CTL_RDYPOL              4            /*  Polarity of RDY/MISO Line */
+#define BITP_SPI_FLOW_CTL_MODE                0            /*  Flow Control Mode */
+#define BITM_SPI_FLOW_CTL_RDBURSTSZ          (_ADI_MSK_3(0x00000F00,0x00000F00U, uint16_t  ))    /*  Read Data Burst Size - 1 */
+#define BITM_SPI_FLOW_CTL_RDYPOL             (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Polarity of RDY/MISO Line */
+#define BITM_SPI_FLOW_CTL_MODE               (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t  ))    /*  Flow Control Mode */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_WAIT_TMR                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_WAIT_TMR_VALUE               0            /*  Wait Timer */
+#define BITM_SPI_WAIT_TMR_VALUE              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Wait Timer */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_CS_CTL                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_CS_CTL_SEL                   0            /*  Chip Select Control */
+#define BITM_SPI_CS_CTL_SEL                  (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t  ))    /*  Chip Select Control */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_CS_OVERRIDE                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_CS_OVERRIDE_CTL              0            /*  CS Override Control */
+#define BITM_SPI_CS_OVERRIDE_CTL             (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t  ))    /*  CS Override Control */
+
+
+/* ============================================================================================================================
+        
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        UART0
+   ============================================================================================================================ */
+#define REG_UART0_RX                         0x40005000            /*  UART0 Receive Buffer Register */
+#define REG_UART0_TX                         0x40005000            /*  UART0 Transmit Holding Register */
+#define REG_UART0_IEN                        0x40005004            /*  UART0 Interrupt Enable */
+#define REG_UART0_IIR                        0x40005008            /*  UART0 Interrupt ID */
+#define REG_UART0_LCR                        0x4000500C            /*  UART0 Line Control */
+#define REG_UART0_MCR                        0x40005010            /*  UART0 Modem Control */
+#define REG_UART0_LSR                        0x40005014            /*  UART0 Line Status */
+#define REG_UART0_MSR                        0x40005018            /*  UART0 Modem Status */
+#define REG_UART0_SCR                        0x4000501C            /*  UART0 Scratch Buffer */
+#define REG_UART0_FCR                        0x40005020            /*  UART0 FIFO Control */
+#define REG_UART0_FBR                        0x40005024            /*  UART0 Fractional Baud Rate */
+#define REG_UART0_DIV                        0x40005028            /*  UART0 Baud Rate Divider */
+#define REG_UART0_LCR2                       0x4000502C            /*  UART0 Second Line Control */
+#define REG_UART0_CTL                        0x40005030            /*  UART0 UART Control Register */
+#define REG_UART0_RFC                        0x40005034            /*  UART0 RX FIFO Byte Count */
+#define REG_UART0_TFC                        0x40005038            /*  UART0 TX FIFO Byte Count */
+#define REG_UART0_RSC                        0x4000503C            /*  UART0 RS485 Half-duplex Control */
+#define REG_UART0_ACR                        0x40005040            /*  UART0 Auto Baud Control */
+#define REG_UART0_ASRL                       0x40005044            /*  UART0 Auto Baud Status (Low) */
+#define REG_UART0_ASRH                       0x40005048            /*  UART0 Auto Baud Status (High) */
+
+/* ============================================================================================================================
+        UART Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_RX                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_RX_RBR                      0            /*  Receive Buffer Register */
+#define BITM_UART_RX_RBR                     (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Receive Buffer Register */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_TX                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_TX_THR                      0            /*  Transmit Holding Register */
+#define BITM_UART_TX_THR                     (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Transmit Holding Register */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_IEN                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_IEN_EDMAR                   5            /*  DMA Requests in Receive Mode */
+#define BITP_UART_IEN_EDMAT                   4            /*  DMA Requests in Transmit Mode */
+#define BITP_UART_IEN_EDSSI                   3            /*  Modem Status Interrupt */
+#define BITP_UART_IEN_ELSI                    2            /*  Rx Status Interrupt */
+#define BITP_UART_IEN_ETBEI                   1            /*  Transmit Buffer Empty Interrupt */
+#define BITP_UART_IEN_ERBFI                   0            /*  Receive Buffer Full Interrupt */
+#define BITM_UART_IEN_EDMAR                  (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  DMA Requests in Receive Mode */
+#define BITM_UART_IEN_EDMAT                  (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  DMA Requests in Transmit Mode */
+#define BITM_UART_IEN_EDSSI                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Modem Status Interrupt */
+#define BITM_UART_IEN_ELSI                   (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Rx Status Interrupt */
+#define BITM_UART_IEN_ETBEI                  (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Transmit Buffer Empty Interrupt */
+#define BITM_UART_IEN_ERBFI                  (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Receive Buffer Full Interrupt */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_IIR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_IIR_FEND                    6            /*  FIFO Enabled */
+#define BITP_UART_IIR_STAT                    1            /*  Interrupt Status */
+#define BITP_UART_IIR_NIRQ                    0            /*  Interrupt Flag */
+#define BITM_UART_IIR_FEND                   (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t  ))    /*  FIFO Enabled */
+#define BITM_UART_IIR_STAT                   (_ADI_MSK_3(0x0000000E,0x0000000EU, uint16_t  ))    /*  Interrupt Status */
+#define BITM_UART_IIR_NIRQ                   (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Interrupt Flag */
+#define ENUM_UART_IIR_STAT_EDSSI             (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  STAT: Modem status interrupt (Read MSR register to clear) */
+#define ENUM_UART_IIR_STAT_ETBEI             (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  STAT: Transmit buffer empty interrupt (Write to Tx register or read IIR register to clear) */
+#define ENUM_UART_IIR_STAT_ERBFI             (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  STAT: Receive buffer full interrupt (Read Rx register to clear) */
+#define ENUM_UART_IIR_STAT_RLSI              (_ADI_MSK_3(0x00000006,0x00000006U, uint16_t  ))    /*  STAT: Receive line status interrupt (Read LSR register to clear) */
+#define ENUM_UART_IIR_STAT_RFTOI             (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t  ))    /*  STAT: Receive FIFO time-out interrupt (Read Rx register to clear) */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_LCR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_LCR_BRK                     6            /*  Set Break */
+#define BITP_UART_LCR_SP                      5            /*  Stick Parity */
+#define BITP_UART_LCR_EPS                     4            /*  Parity Select */
+#define BITP_UART_LCR_PEN                     3            /*  Parity Enable */
+#define BITP_UART_LCR_STOP                    2            /*  Stop Bit */
+#define BITP_UART_LCR_WLS                     0            /*  Word Length Select */
+#define BITM_UART_LCR_BRK                    (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Set Break */
+#define BITM_UART_LCR_SP                     (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Stick Parity */
+#define BITM_UART_LCR_EPS                    (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Parity Select */
+#define BITM_UART_LCR_PEN                    (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Parity Enable */
+#define BITM_UART_LCR_STOP                   (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Stop Bit */
+#define BITM_UART_LCR_WLS                    (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t  ))    /*  Word Length Select */
+#define ENUM_UART_LCR_PAR_NOTFORCED          (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  SP: Parity will not be forced based on Parity Select and Parity Enable bits. */
+#define ENUM_UART_LCR_PAR_FORCED             (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  SP: Parity forced based on Parity Select and Parity Enable bits. */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_MCR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_MCR_LOOPBACK                4            /*  Loopback Mode */
+#define BITP_UART_MCR_OUT2                    3            /*  Output 2 */
+#define BITP_UART_MCR_OUT1                    2            /*  Output 1 */
+#define BITP_UART_MCR_RTS                     1            /*  Request to Send */
+#define BITP_UART_MCR_DTR                     0            /*  Data Terminal Ready */
+#define BITM_UART_MCR_LOOPBACK               (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Loopback Mode */
+#define BITM_UART_MCR_OUT2                   (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Output 2 */
+#define BITM_UART_MCR_OUT1                   (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Output 1 */
+#define BITM_UART_MCR_RTS                    (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Request to Send */
+#define BITM_UART_MCR_DTR                    (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Data Terminal Ready */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_LSR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_LSR_FIFOERR                 7            /*  Rx FIFO Parity Error/Frame Error/Break Indication */
+#define BITP_UART_LSR_TEMT                    6            /*  Transmit and Shift Register Empty Status */
+#define BITP_UART_LSR_THRE                    5            /*  Transmit Register Empty */
+#define BITP_UART_LSR_BI                      4            /*  Break Indicator */
+#define BITP_UART_LSR_FE                      3            /*  Framing Error */
+#define BITP_UART_LSR_PE                      2            /*  Parity Error */
+#define BITP_UART_LSR_OE                      1            /*  Overrun Error */
+#define BITP_UART_LSR_DR                      0            /*  Data Ready */
+#define BITM_UART_LSR_FIFOERR                (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Rx FIFO Parity Error/Frame Error/Break Indication */
+#define BITM_UART_LSR_TEMT                   (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Transmit and Shift Register Empty Status */
+#define BITM_UART_LSR_THRE                   (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Transmit Register Empty */
+#define BITM_UART_LSR_BI                     (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Break Indicator */
+#define BITM_UART_LSR_FE                     (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Framing Error */
+#define BITM_UART_LSR_PE                     (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Parity Error */
+#define BITM_UART_LSR_OE                     (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Overrun Error */
+#define BITM_UART_LSR_DR                     (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Data Ready */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_MSR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_MSR_DCD                     7            /*  Data Carrier Detect */
+#define BITP_UART_MSR_RI                      6            /*  Ring Indicator */
+#define BITP_UART_MSR_DSR                     5            /*  Data Set Ready */
+#define BITP_UART_MSR_CTS                     4            /*  Clear to Send */
+#define BITP_UART_MSR_DDCD                    3            /*  Delta DCD */
+#define BITP_UART_MSR_TERI                    2            /*  Trailing Edge RI */
+#define BITP_UART_MSR_DDSR                    1            /*  Delta DSR */
+#define BITP_UART_MSR_DCTS                    0            /*  Delta CTS */
+#define BITM_UART_MSR_DCD                    (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Data Carrier Detect */
+#define BITM_UART_MSR_RI                     (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Ring Indicator */
+#define BITM_UART_MSR_DSR                    (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Data Set Ready */
+#define BITM_UART_MSR_CTS                    (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Clear to Send */
+#define BITM_UART_MSR_DDCD                   (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Delta DCD */
+#define BITM_UART_MSR_TERI                   (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Trailing Edge RI */
+#define BITM_UART_MSR_DDSR                   (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Delta DSR */
+#define BITM_UART_MSR_DCTS                   (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Delta CTS */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_SCR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_SCR_SCR                     0            /*  Scratch */
+#define BITM_UART_SCR_SCR                    (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Scratch */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_FCR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_FCR_RFTRIG                  6            /*  Rx FIFO Trigger Level */
+#define BITP_UART_FCR_FDMAMD                  3            /*  FIFO DMA Mode */
+#define BITP_UART_FCR_TFCLR                   2            /*  Clear Tx FIFO */
+#define BITP_UART_FCR_RFCLR                   1            /*  Clear Rx FIFO */
+#define BITP_UART_FCR_FIFOEN                  0            /*  FIFO Enable as to Work in 16550 Mode */
+#define BITM_UART_FCR_RFTRIG                 (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t  ))    /*  Rx FIFO Trigger Level */
+#define BITM_UART_FCR_FDMAMD                 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  FIFO DMA Mode */
+#define BITM_UART_FCR_TFCLR                  (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Clear Tx FIFO */
+#define BITM_UART_FCR_RFCLR                  (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Clear Rx FIFO */
+#define BITM_UART_FCR_FIFOEN                 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  FIFO Enable as to Work in 16550 Mode */
+#define ENUM_UART_FCR_MODE0                  (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  FDMAMD: In DMA mode 0, RX DMA request will be asserted whenever there's data in RBR or RX FIFO and de-assert whenever RBR or RX FIFO is empty; TX DMA request will be asserted whenever THR or TX FIFO is empty and de-assert whenever data written to. */
+#define ENUM_UART_FCR_MODE1                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  FDMAMD: in DMA mode 1, RX DMA request will be asserted whenever RX FIFO trig level or time out reached and de-assert thereafter when RX FIFO is empty; TX DMA request will be asserted whenever TX FIFO is empty and de-assert thereafter when TX FIFO is completely filled up full. */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_FBR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_FBR_FBEN                   15            /*  Fractional Baud Rate Generator Enable */
+#define BITP_UART_FBR_DIVM                   11            /*  Fractional Baud Rate M Divide Bits 1 to 3 */
+#define BITP_UART_FBR_DIVN                    0            /*  Fractional Baud Rate N Divide Bits 0 to 2047 */
+#define BITM_UART_FBR_FBEN                   (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Fractional Baud Rate Generator Enable */
+#define BITM_UART_FBR_DIVM                   (_ADI_MSK_3(0x00001800,0x00001800U, uint16_t  ))    /*  Fractional Baud Rate M Divide Bits 1 to 3 */
+#define BITM_UART_FBR_DIVN                   (_ADI_MSK_3(0x000007FF,0x000007FFU, uint16_t  ))    /*  Fractional Baud Rate N Divide Bits 0 to 2047 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_DIV                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_DIV_DIV                     0            /*  Baud Rate Divider */
+#define BITM_UART_DIV_DIV                    (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Baud Rate Divider */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_LCR2                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_LCR2_OSR                    0            /*  Over Sample Rate */
+#define BITM_UART_LCR2_OSR                   (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t  ))    /*  Over Sample Rate */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_CTL                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_CTL_REV                     8            /*  UART Revision ID */
+#define BITP_UART_CTL_RXINV                   4            /*  Invert Receiver Line */
+#define BITP_UART_CTL_FORCECLK                1            /*  Force UCLK on */
+#define BITM_UART_CTL_REV                    (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t  ))    /*  UART Revision ID */
+#define BITM_UART_CTL_RXINV                  (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Invert Receiver Line */
+#define BITM_UART_CTL_FORCECLK               (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Force UCLK on */
+#define ENUM_UART_CTL_NOTINV_RX              (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  RXINV: Don't invert receiver line (idling high). */
+#define ENUM_UART_CTL_INV_RX                 (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  RXINV: Invert receiver line (idling low). */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_RFC                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_RFC_RFC                     0            /*  Current Rx FIFO Data Bytes */
+#define BITM_UART_RFC_RFC                    (_ADI_MSK_3(0x0000001F,0x0000001FU, uint16_t  ))    /*  Current Rx FIFO Data Bytes */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_TFC                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_TFC_TFC                     0            /*  Current Tx FIFO Data Bytes */
+#define BITM_UART_TFC_TFC                    (_ADI_MSK_3(0x0000001F,0x0000001FU, uint16_t  ))    /*  Current Tx FIFO Data Bytes */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_RSC                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_RSC_DISTX                   3            /*  Hold off Tx When Receiving */
+#define BITP_UART_RSC_DISRX                   2            /*  Disable Rx When Transmitting */
+#define BITP_UART_RSC_OENSP                   1            /*  SOUT_EN De-assert Before Full Stop Bit(s) */
+#define BITP_UART_RSC_OENP                    0            /*  SOUT_EN Polarity */
+#define BITM_UART_RSC_DISTX                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Hold off Tx When Receiving */
+#define BITM_UART_RSC_DISRX                  (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Disable Rx When Transmitting */
+#define BITM_UART_RSC_OENSP                  (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  SOUT_EN De-assert Before Full Stop Bit(s) */
+#define BITM_UART_RSC_OENP                   (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  SOUT_EN Polarity */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_ACR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_ACR_EEC                     8            /*  Ending Edge Count */
+#define BITP_UART_ACR_SEC                     4            /*  Starting Edge Count */
+#define BITP_UART_ACR_TOIEN                   2            /*  Enable Time-out Interrupt */
+#define BITP_UART_ACR_DNIEN                   1            /*  Enable Done Interrupt */
+#define BITP_UART_ACR_ABE                     0            /*  Auto Baud Enable */
+#define BITM_UART_ACR_EEC                    (_ADI_MSK_3(0x00000F00,0x00000F00U, uint16_t  ))    /*  Ending Edge Count */
+#define BITM_UART_ACR_SEC                    (_ADI_MSK_3(0x00000070,0x00000070U, uint16_t  ))    /*  Starting Edge Count */
+#define BITM_UART_ACR_TOIEN                  (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Enable Time-out Interrupt */
+#define BITM_UART_ACR_DNIEN                  (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Enable Done Interrupt */
+#define BITM_UART_ACR_ABE                    (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Auto Baud Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_ASRL                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_ASRL_CNT                    4            /*  Auto Baud Counter Value */
+#define BITP_UART_ASRL_NEETO                  3            /*  Timed Out Due to No Valid Ending Edge Found */
+#define BITP_UART_ASRL_NSETO                  2            /*  Timed Out Due to No Valid Start Edge Found */
+#define BITP_UART_ASRL_BRKTO                  1            /*  Timed Out Due to Long Time Break Condition */
+#define BITP_UART_ASRL_DONE                   0            /*  Auto Baud Done Successfully */
+#define BITM_UART_ASRL_CNT                   (_ADI_MSK_3(0x0000FFF0,0x0000FFF0U, uint16_t  ))    /*  Auto Baud Counter Value */
+#define BITM_UART_ASRL_NEETO                 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Timed Out Due to No Valid Ending Edge Found */
+#define BITM_UART_ASRL_NSETO                 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Timed Out Due to No Valid Start Edge Found */
+#define BITM_UART_ASRL_BRKTO                 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Timed Out Due to Long Time Break Condition */
+#define BITM_UART_ASRL_DONE                  (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Auto Baud Done Successfully */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_ASRH                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_ASRH_CNT                    0            /*  Auto Baud Counter Value */
+#define BITM_UART_ASRH_CNT                   (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Auto Baud Counter Value */
+
+
+/* ============================================================================================================================
+        Beeper Driver
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        BEEP0
+   ============================================================================================================================ */
+#define REG_BEEP0_CFG                        0x40005C00            /*  BEEP0 Beeper Configuration */
+#define REG_BEEP0_STAT                       0x40005C04            /*  BEEP0 Beeper Status */
+#define REG_BEEP0_TONEA                      0x40005C08            /*  BEEP0 Tone A Data */
+#define REG_BEEP0_TONEB                      0x40005C0C            /*  BEEP0 Tone B Data */
+
+/* ============================================================================================================================
+        BEEP Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          BEEP_CFG                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_BEEP_CFG_SEQATENDIRQ            15            /*  Sequence End IRQ */
+#define BITP_BEEP_CFG_SEQNEARENDIRQ          14            /*  Sequence 1 Cycle from End IRQ */
+#define BITP_BEEP_CFG_BENDIRQ                13            /*  Tone B End IRQ */
+#define BITP_BEEP_CFG_BSTARTIRQ              12            /*  Tone B Start IRQ */
+#define BITP_BEEP_CFG_AENDIRQ                11            /*  Tone A End IRQ */
+#define BITP_BEEP_CFG_ASTARTIRQ              10            /*  Tone A Start IRQ */
+#define BITP_BEEP_CFG_EN                      8            /*  Beeper Enable */
+#define BITP_BEEP_CFG_SEQREPEAT               0            /*  Beeper Sequence Repeat Value */
+#define BITM_BEEP_CFG_SEQATENDIRQ            (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Sequence End IRQ */
+#define BITM_BEEP_CFG_SEQNEARENDIRQ          (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Sequence 1 Cycle from End IRQ */
+#define BITM_BEEP_CFG_BENDIRQ                (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Tone B End IRQ */
+#define BITM_BEEP_CFG_BSTARTIRQ              (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Tone B Start IRQ */
+#define BITM_BEEP_CFG_AENDIRQ                (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Tone A End IRQ */
+#define BITM_BEEP_CFG_ASTARTIRQ              (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Tone A Start IRQ */
+#define BITM_BEEP_CFG_EN                     (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Beeper Enable */
+#define BITM_BEEP_CFG_SEQREPEAT              (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Beeper Sequence Repeat Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          BEEP_STAT                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_BEEP_STAT_SEQENDED              15            /*  Sequencer Has Ended */
+#define BITP_BEEP_STAT_SEQNEAREND            14            /*  Sequencer Last Tone-pair Has Started */
+#define BITP_BEEP_STAT_BENDED                13            /*  Tone B Has Ended */
+#define BITP_BEEP_STAT_BSTARTED              12            /*  Tone B Has Started */
+#define BITP_BEEP_STAT_AENDED                11            /*  Tone A Has Ended */
+#define BITP_BEEP_STAT_ASTARTED              10            /*  Tone A Has Started */
+#define BITP_BEEP_STAT_BUSY                   8            /*  Beeper is Busy */
+#define BITP_BEEP_STAT_SEQREMAIN              0            /*  Remaining Tone-pair Iterations to Play in Sequence Mode */
+#define BITM_BEEP_STAT_SEQENDED              (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Sequencer Has Ended */
+#define BITM_BEEP_STAT_SEQNEAREND            (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Sequencer Last Tone-pair Has Started */
+#define BITM_BEEP_STAT_BENDED                (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Tone B Has Ended */
+#define BITM_BEEP_STAT_BSTARTED              (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Tone B Has Started */
+#define BITM_BEEP_STAT_AENDED                (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Tone A Has Ended */
+#define BITM_BEEP_STAT_ASTARTED              (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Tone A Has Started */
+#define BITM_BEEP_STAT_BUSY                  (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Beeper is Busy */
+#define BITM_BEEP_STAT_SEQREMAIN             (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Remaining Tone-pair Iterations to Play in Sequence Mode */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          BEEP_TONEA                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_BEEP_TONEA_DIS                  15            /*  Output Disable */
+#define BITP_BEEP_TONEA_FREQ                  8            /*  Tone Frequency */
+#define BITP_BEEP_TONEA_DUR                   0            /*  Tone Duration */
+#define BITM_BEEP_TONEA_DIS                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Output Disable */
+#define BITM_BEEP_TONEA_FREQ                 (_ADI_MSK_3(0x00007F00,0x00007F00U, uint16_t  ))    /*  Tone Frequency */
+#define BITM_BEEP_TONEA_DUR                  (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Tone Duration */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          BEEP_TONEB                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_BEEP_TONEB_DIS                  15            /*  Output Disable */
+#define BITP_BEEP_TONEB_FREQ                  8            /*  Tone Frequency */
+#define BITP_BEEP_TONEB_DUR                   0            /*  Tone Duration */
+#define BITM_BEEP_TONEB_DIS                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Output Disable */
+#define BITM_BEEP_TONEB_FREQ                 (_ADI_MSK_3(0x00007F00,0x00007F00U, uint16_t  ))    /*  Tone Frequency */
+#define BITM_BEEP_TONEB_DUR                  (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Tone Duration */
+
+
+/* ============================================================================================================================
+        
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        ADC0
+   ============================================================================================================================ */
+#define REG_ADC0_CFG                         0x40007000            /*  ADC0 ADC Configuration */
+#define REG_ADC0_PWRUP                       0x40007004            /*  ADC0 ADC Power-up Time */
+#define REG_ADC0_CAL_WORD                    0x40007008            /*  ADC0 Calibration Word */
+#define REG_ADC0_CNV_CFG                     0x4000700C            /*  ADC0 ADC Conversion Configuration */
+#define REG_ADC0_CNV_TIME                    0x40007010            /*  ADC0 ADC Conversion Time */
+#define REG_ADC0_AVG_CFG                     0x40007014            /*  ADC0 Averaging Configuration */
+#define REG_ADC0_IRQ_EN                      0x40007020            /*  ADC0 Interrupt Enable */
+#define REG_ADC0_STAT                        0x40007024            /*  ADC0 ADC Status */
+#define REG_ADC0_OVF                         0x40007028            /*  ADC0 Overflow of Output Registers */
+#define REG_ADC0_ALERT                       0x4000702C            /*  ADC0 Alert Indication */
+#define REG_ADC0_CH0_OUT                     0x40007030            /*  ADC0 Conversion Result Channel 0 */
+#define REG_ADC0_CH1_OUT                     0x40007034            /*  ADC0 Conversion Result Channel 1 */
+#define REG_ADC0_CH2_OUT                     0x40007038            /*  ADC0 Conversion Result Channel 2 */
+#define REG_ADC0_CH3_OUT                     0x4000703C            /*  ADC0 Conversion Result Channel 3 */
+#define REG_ADC0_CH4_OUT                     0x40007040            /*  ADC0 Conversion Result Channel 4 */
+#define REG_ADC0_CH5_OUT                     0x40007044            /*  ADC0 Conversion Result Channel 5 */
+#define REG_ADC0_CH6_OUT                     0x40007048            /*  ADC0 Conversion Result Channel 6 */
+#define REG_ADC0_CH7_OUT                     0x4000704C            /*  ADC0 Conversion Result Channel 7 */
+#define REG_ADC0_BAT_OUT                     0x40007050            /*  ADC0 Battery Monitoring Result */
+#define REG_ADC0_TMP_OUT                     0x40007054            /*  ADC0 Temperature Result */
+#define REG_ADC0_TMP2_OUT                    0x40007058            /*  ADC0 Temperature Result 2 */
+#define REG_ADC0_DMA_OUT                     0x4000705C            /*  ADC0 DMA Output Register */
+#define REG_ADC0_LIM0_LO                     0x40007060            /*  ADC0 Channel 0 Low Limit */
+#define REG_ADC0_LIM0_HI                     0x40007064            /*  ADC0 Channel 0 High Limit */
+#define REG_ADC0_HYS0                        0x40007068            /*  ADC0 Channel 0 Hysteresis */
+#define REG_ADC0_LIM1_LO                     0x40007070            /*  ADC0 Channel 1 Low Limit */
+#define REG_ADC0_LIM1_HI                     0x40007074            /*  ADC0 Channel 1 High Limit */
+#define REG_ADC0_HYS1                        0x40007078            /*  ADC0 Channel 1 Hysteresis */
+#define REG_ADC0_LIM2_LO                     0x40007080            /*  ADC0 Channel 2 Low Limit */
+#define REG_ADC0_LIM2_HI                     0x40007084            /*  ADC0 Channel 2 High Limit */
+#define REG_ADC0_HYS2                        0x40007088            /*  ADC0 Channel 2 Hysteresis */
+#define REG_ADC0_LIM3_LO                     0x40007090            /*  ADC0 Channel 3 Low Limit */
+#define REG_ADC0_LIM3_HI                     0x40007094            /*  ADC0 Channel 3 High Limit */
+#define REG_ADC0_HYS3                        0x40007098            /*  ADC0 Channel 3 Hysteresis */
+#define REG_ADC0_CFG1                        0x400070C0            /*  ADC0 Reference Buffer Low Power Mode */
+
+/* ============================================================================================================================
+        ADC Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CFG                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CFG_FAST_DISCH               9            /*  Fast Switchover of Vref from 2.5 to 1.25 */
+#define BITP_ADC_CFG_TMPEN                    8            /*  Power up Temperature Sensor */
+#define BITP_ADC_CFG_SINKEN                   7            /*  Enable Additional Sink Current Capability */
+#define BITP_ADC_CFG_RST                      6            /*  Reset */
+#define BITP_ADC_CFG_STARTCAL                 5            /*  Start a New Offset Calibration Cycle */
+#define BITP_ADC_CFG_EN                       4            /*  Enable ADC Subsystem */
+#define BITP_ADC_CFG_REFBUFEN                 2            /*  Enable Internal Reference Buffer */
+#define BITP_ADC_CFG_VREFSEL                  1            /*  Select Vref as 1.25V or 2.5V */
+#define BITP_ADC_CFG_PWRUP                    0            /*  Powering up the ADC */
+#define BITM_ADC_CFG_FAST_DISCH              (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Fast Switchover of Vref from 2.5 to 1.25 */
+#define BITM_ADC_CFG_TMPEN                   (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Power up Temperature Sensor */
+#define BITM_ADC_CFG_SINKEN                  (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Enable Additional Sink Current Capability */
+#define BITM_ADC_CFG_RST                     (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Reset */
+#define BITM_ADC_CFG_STARTCAL                (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Start a New Offset Calibration Cycle */
+#define BITM_ADC_CFG_EN                      (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Enable ADC Subsystem */
+#define BITM_ADC_CFG_REFBUFEN                (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Enable Internal Reference Buffer */
+#define BITM_ADC_CFG_VREFSEL                 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Select Vref as 1.25V or 2.5V */
+#define BITM_ADC_CFG_PWRUP                   (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Powering up the ADC */
+#define ENUM_ADC_CFG_EXT_REF                 (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  REFBUFEN: External reference is used */
+#define ENUM_ADC_CFG_BUF_REF                 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  REFBUFEN: Reference buffer is enabled */
+#define ENUM_ADC_CFG_V_2P5                   (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  VREFSEL: Vref = 2.5V */
+#define ENUM_ADC_CFG_V_1P25                  (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  VREFSEL: Vref = 1.25V */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_PWRUP                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_PWRUP_WAIT                   0            /*  Program This with 526/PCLKDIVCNT */
+#define BITM_ADC_PWRUP_WAIT                  (_ADI_MSK_3(0x000003FF,0x000003FFU, uint16_t  ))    /*  Program This with 526/PCLKDIVCNT */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CAL_WORD                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CAL_WORD_VALUE               0            /*  Offset Calibration Word */
+#define BITM_ADC_CAL_WORD_VALUE              (_ADI_MSK_3(0x0000007F,0x0000007FU, uint16_t  ))    /*  Offset Calibration Word */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CNV_CFG                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CNV_CFG_MULTI               15            /*  Multiple Conversions */
+#define BITP_ADC_CNV_CFG_SINGLE              14            /*  Single Conversion Start */
+#define BITP_ADC_CNV_CFG_DMAEN               13            /*  DMA Channel Enable */
+#define BITP_ADC_CNV_CFG_AUTOMODE            12            /*  Auto Mode Enable */
+#define BITP_ADC_CNV_CFG_TMP2                10            /*  Temperature Measurement 2 */
+#define BITP_ADC_CNV_CFG_TMP                  9            /*  Temperature Measurement 1 */
+#define BITP_ADC_CNV_CFG_BAT                  8            /*  Battery Monitoring Enable */
+#define BITP_ADC_CNV_CFG_SEL                  0            /*  Selection of Channel(s) to Convert */
+#define BITM_ADC_CNV_CFG_MULTI               (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Multiple Conversions */
+#define BITM_ADC_CNV_CFG_SINGLE              (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Single Conversion Start */
+#define BITM_ADC_CNV_CFG_DMAEN               (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  DMA Channel Enable */
+#define BITM_ADC_CNV_CFG_AUTOMODE            (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Auto Mode Enable */
+#define BITM_ADC_CNV_CFG_TMP2                (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Temperature Measurement 2 */
+#define BITM_ADC_CNV_CFG_TMP                 (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Temperature Measurement 1 */
+#define BITM_ADC_CNV_CFG_BAT                 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Battery Monitoring Enable */
+#define BITM_ADC_CNV_CFG_SEL                 (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Selection of Channel(s) to Convert */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CNV_TIME                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CNV_TIME_DLY                 8            /*  Delay Between Two Consecutive Conversions */
+#define BITP_ADC_CNV_TIME_SAMPTIME            0            /*  Sampling Time */
+#define BITM_ADC_CNV_TIME_DLY                (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t  ))    /*  Delay Between Two Consecutive Conversions */
+#define BITM_ADC_CNV_TIME_SAMPTIME           (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Sampling Time */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_AVG_CFG                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_AVG_CFG_EN                  15            /*  Enable Averaging on Channels Enabled in Enable Register */
+#define BITP_ADC_AVG_CFG_OS                  14            /*  Enable Oversampling */
+#define BITP_ADC_AVG_CFG_FACTOR               0            /*  Averaging Factor */
+#define BITM_ADC_AVG_CFG_EN                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Enable Averaging on Channels Enabled in Enable Register */
+#define BITM_ADC_AVG_CFG_OS                  (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Enable Oversampling */
+#define BITM_ADC_AVG_CFG_FACTOR              (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Averaging Factor */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_IRQ_EN                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_IRQ_EN_RDY                  13            /*  Set to Enable Interrupt When ADC is Ready to Convert */
+#define BITP_ADC_IRQ_EN_ALERT                12            /*  Interrupt on Crossing Lower or Higher Limit Enable */
+#define BITP_ADC_IRQ_EN_OVF                  11            /*  Enable Overflow Interrupt */
+#define BITP_ADC_IRQ_EN_CALDONE              10            /*  Enable Interrupt for Calibration Done */
+#define BITP_ADC_IRQ_EN_CNVDONE               0            /*  Enable Conversion Done Interrupt */
+#define BITM_ADC_IRQ_EN_RDY                  (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Set to Enable Interrupt When ADC is Ready to Convert */
+#define BITM_ADC_IRQ_EN_ALERT                (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Interrupt on Crossing Lower or Higher Limit Enable */
+#define BITM_ADC_IRQ_EN_OVF                  (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Enable Overflow Interrupt */
+#define BITM_ADC_IRQ_EN_CALDONE              (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Enable Interrupt for Calibration Done */
+#define BITM_ADC_IRQ_EN_CNVDONE              (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Enable Conversion Done Interrupt */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_STAT                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_STAT_RDY                    15            /*  ADC Ready to Start Converting */
+#define BITP_ADC_STAT_CALDONE                14            /*  Calibration Done */
+#define BITP_ADC_STAT_TMP2DONE               10            /*  Conversion Done for Temperature Sensing 2 */
+#define BITP_ADC_STAT_TMPDONE                 9            /*  Conversion Done for Temperature Sensing */
+#define BITP_ADC_STAT_BATDONE                 8            /*  Conversion Done - Battery Monitoring */
+#define BITP_ADC_STAT_DONE7                   7            /*  Conversion Done on Channel 7 */
+#define BITP_ADC_STAT_DONE6                   6            /*  Conversion Done on Channel 6 */
+#define BITP_ADC_STAT_DONE5                   5            /*  Conversion Done on Channel 5 */
+#define BITP_ADC_STAT_DONE4                   4            /*  Conversion Done on Channel 4 */
+#define BITP_ADC_STAT_DONE3                   3            /*  Conversion Done on Channel 3 */
+#define BITP_ADC_STAT_DONE2                   2            /*  Conversion Done on Channel 2 */
+#define BITP_ADC_STAT_DONE1                   1            /*  Conversion Done on Channel 1 */
+#define BITP_ADC_STAT_DONE0                   0            /*  Conversion Done on Channel 0 */
+#define BITM_ADC_STAT_RDY                    (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  ADC Ready to Start Converting */
+#define BITM_ADC_STAT_CALDONE                (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Calibration Done */
+#define BITM_ADC_STAT_TMP2DONE               (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Conversion Done for Temperature Sensing 2 */
+#define BITM_ADC_STAT_TMPDONE                (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Conversion Done for Temperature Sensing */
+#define BITM_ADC_STAT_BATDONE                (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Conversion Done - Battery Monitoring */
+#define BITM_ADC_STAT_DONE7                  (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Conversion Done on Channel 7 */
+#define BITM_ADC_STAT_DONE6                  (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Conversion Done on Channel 6 */
+#define BITM_ADC_STAT_DONE5                  (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Conversion Done on Channel 5 */
+#define BITM_ADC_STAT_DONE4                  (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Conversion Done on Channel 4 */
+#define BITM_ADC_STAT_DONE3                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Conversion Done on Channel 3 */
+#define BITM_ADC_STAT_DONE2                  (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Conversion Done on Channel 2 */
+#define BITM_ADC_STAT_DONE1                  (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Conversion Done on Channel 1 */
+#define BITM_ADC_STAT_DONE0                  (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Conversion Done on Channel 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_OVF                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_OVF_TMP2                    10            /*  Overflow in TMP2_OUT */
+#define BITP_ADC_OVF_TMP                      9            /*  Overflow in TMP_OUT */
+#define BITP_ADC_OVF_BAT                      8            /*  Overflow in BAT_OUT */
+#define BITP_ADC_OVF_CH7                      7            /*  Overflow in CH7_OUT */
+#define BITP_ADC_OVF_CH6                      6            /*  Overflow in CH6_OUT */
+#define BITP_ADC_OVF_CH5                      5            /*  Overflow in CH5_OUT */
+#define BITP_ADC_OVF_CH4                      4            /*  Overflow in CH4_OUT */
+#define BITP_ADC_OVF_CH3                      3            /*  Overflow in CH3_OUT */
+#define BITP_ADC_OVF_CH2                      2            /*  Overflow in CH2_OUT */
+#define BITP_ADC_OVF_CH1                      1            /*  Overflow in CH1_OUT */
+#define BITP_ADC_OVF_CH0                      0            /*  Overflow in CH0_OUT */
+#define BITM_ADC_OVF_TMP2                    (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Overflow in TMP2_OUT */
+#define BITM_ADC_OVF_TMP                     (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Overflow in TMP_OUT */
+#define BITM_ADC_OVF_BAT                     (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Overflow in BAT_OUT */
+#define BITM_ADC_OVF_CH7                     (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Overflow in CH7_OUT */
+#define BITM_ADC_OVF_CH6                     (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Overflow in CH6_OUT */
+#define BITM_ADC_OVF_CH5                     (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Overflow in CH5_OUT */
+#define BITM_ADC_OVF_CH4                     (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Overflow in CH4_OUT */
+#define BITM_ADC_OVF_CH3                     (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Overflow in CH3_OUT */
+#define BITM_ADC_OVF_CH2                     (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Overflow in CH2_OUT */
+#define BITM_ADC_OVF_CH1                     (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Overflow in CH1_OUT */
+#define BITM_ADC_OVF_CH0                     (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Overflow in CH0_OUT */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_ALERT                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_ALERT_LO3                    7            /*  Channel 3 Low Alert Status */
+#define BITP_ADC_ALERT_HI3                    6            /*  Channel 3 High Alert Status */
+#define BITP_ADC_ALERT_LO2                    5            /*  Channel 2 Low Alert Status */
+#define BITP_ADC_ALERT_HI2                    4            /*  Channel 2 High Alert Status */
+#define BITP_ADC_ALERT_LO1                    3            /*  Channel 1 Low Alert Status */
+#define BITP_ADC_ALERT_HI1                    2            /*  Channel 1 High Alert Status */
+#define BITP_ADC_ALERT_LO0                    1            /*  Channel 0 Low Alert Status */
+#define BITP_ADC_ALERT_HI0                    0            /*  Channel 0 High Alert Status */
+#define BITM_ADC_ALERT_LO3                   (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Channel 3 Low Alert Status */
+#define BITM_ADC_ALERT_HI3                   (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Channel 3 High Alert Status */
+#define BITM_ADC_ALERT_LO2                   (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Channel 2 Low Alert Status */
+#define BITM_ADC_ALERT_HI2                   (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Channel 2 High Alert Status */
+#define BITM_ADC_ALERT_LO1                   (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Channel 1 Low Alert Status */
+#define BITM_ADC_ALERT_HI1                   (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Channel 1 High Alert Status */
+#define BITM_ADC_ALERT_LO0                   (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Channel 0 Low Alert Status */
+#define BITM_ADC_ALERT_HI0                   (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Channel 0 High Alert Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CH0_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CH0_OUT_RESULT               0            /*  Conversion Result of Channel 0 */
+#define BITM_ADC_CH0_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion Result of Channel 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CH1_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CH1_OUT_RESULT               0            /*  Conversion Result of Channel 1 */
+#define BITM_ADC_CH1_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion Result of Channel 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CH2_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CH2_OUT_RESULT               0            /*  Conversion Result of Channel 2 */
+#define BITM_ADC_CH2_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion Result of Channel 2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CH3_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CH3_OUT_RESULT               0            /*  Conversion Result of Channel 3 */
+#define BITM_ADC_CH3_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion Result of Channel 3 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CH4_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CH4_OUT_RESULT               0            /*  Conversion Result of Channel 4 */
+#define BITM_ADC_CH4_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion Result of Channel 4 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CH5_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CH5_OUT_RESULT               0            /*  Conversion Result of Channel 5 */
+#define BITM_ADC_CH5_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion Result of Channel 5 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CH6_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CH6_OUT_RESULT               0            /*  Conversion Result of Channel 6 */
+#define BITM_ADC_CH6_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion Result of Channel 6 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CH7_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CH7_OUT_RESULT               0            /*  Conversion Result of Channel 7 */
+#define BITM_ADC_CH7_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion Result of Channel 7 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_BAT_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_BAT_OUT_RESULT               0            /*  Conversion Result of Battery Monitoring */
+#define BITM_ADC_BAT_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion Result of Battery Monitoring */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_TMP_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_TMP_OUT_RESULT               0            /*  Conversion Result of Temperature Measurement 1 */
+#define BITM_ADC_TMP_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion Result of Temperature Measurement 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_TMP2_OUT                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_TMP2_OUT_RESULT              0            /*  Conversion Result of Temperature Measurement 2 */
+#define BITM_ADC_TMP2_OUT_RESULT             (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion Result of Temperature Measurement 2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_DMA_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_DMA_OUT_RESULT               0            /*  Conversion Result for DMA */
+#define BITM_ADC_DMA_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion Result for DMA */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_LIM0_LO                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_LIM0_LO_EN                  15            /*  Enable Low Limit Comparison on Channel 0 */
+#define BITP_ADC_LIM0_LO_VALUE                0            /*  Low Limit for Channel 0 */
+#define BITM_ADC_LIM0_LO_EN                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Enable Low Limit Comparison on Channel 0 */
+#define BITM_ADC_LIM0_LO_VALUE               (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t  ))    /*  Low Limit for Channel 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_LIM0_HI                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_LIM0_HI_EN                  15            /*  Enable High Limit Comparison on Channel 0 */
+#define BITP_ADC_LIM0_HI_VALUE                0            /*  High Limit for Channel 0 */
+#define BITM_ADC_LIM0_HI_EN                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Enable High Limit Comparison on Channel 0 */
+#define BITM_ADC_LIM0_HI_VALUE               (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t  ))    /*  High Limit for Channel 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_HYS0                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_HYS0_EN                     15            /*  Enable Hysteresis for Comparison on Channel 0 */
+#define BITP_ADC_HYS0_MONCYC                 12            /*  Number of Conversion Cycles to Monitor Channel 0 */
+#define BITP_ADC_HYS0_VALUE                   0            /*  Hysteresis Value for Channel 0 */
+#define BITM_ADC_HYS0_EN                     (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Enable Hysteresis for Comparison on Channel 0 */
+#define BITM_ADC_HYS0_MONCYC                 (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t  ))    /*  Number of Conversion Cycles to Monitor Channel 0 */
+#define BITM_ADC_HYS0_VALUE                  (_ADI_MSK_3(0x000001FF,0x000001FFU, uint16_t  ))    /*  Hysteresis Value for Channel 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_LIM1_LO                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_LIM1_LO_EN                  15            /*  Enable Low Limit Comparison on Channel 1 */
+#define BITP_ADC_LIM1_LO_VALUE                0            /*  Low Limit for Channel 1 */
+#define BITM_ADC_LIM1_LO_EN                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Enable Low Limit Comparison on Channel 1 */
+#define BITM_ADC_LIM1_LO_VALUE               (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t  ))    /*  Low Limit for Channel 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_LIM1_HI                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_LIM1_HI_EN                  15            /*  Enable High Limit Comparison on Channel 1 */
+#define BITP_ADC_LIM1_HI_VALUE                0            /*  High Limit for Channel 1 */
+#define BITM_ADC_LIM1_HI_EN                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Enable High Limit Comparison on Channel 1 */
+#define BITM_ADC_LIM1_HI_VALUE               (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t  ))    /*  High Limit for Channel 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_HYS1                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_HYS1_EN                     15            /*  Enable Hysteresis for Comparison on Channel 1 */
+#define BITP_ADC_HYS1_MONCYC                 12            /*  Number of Conversion Cycles to Monitor Channel 1 */
+#define BITP_ADC_HYS1_VALUE                   0            /*  Hysteresis Value for Channel 1 */
+#define BITM_ADC_HYS1_EN                     (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Enable Hysteresis for Comparison on Channel 1 */
+#define BITM_ADC_HYS1_MONCYC                 (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t  ))    /*  Number of Conversion Cycles to Monitor Channel 1 */
+#define BITM_ADC_HYS1_VALUE                  (_ADI_MSK_3(0x000001FF,0x000001FFU, uint16_t  ))    /*  Hysteresis Value for Channel 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_LIM2_LO                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_LIM2_LO_EN                  15            /*  Enable Low Limit Comparison on Channel 2 */
+#define BITP_ADC_LIM2_LO_VALUE                0            /*  Low Limit for Channel 2 */
+#define BITM_ADC_LIM2_LO_EN                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Enable Low Limit Comparison on Channel 2 */
+#define BITM_ADC_LIM2_LO_VALUE               (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t  ))    /*  Low Limit for Channel 2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_LIM2_HI                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_LIM2_HI_EN                  15            /*  Enable High Limit Comparison on Channel */
+#define BITP_ADC_LIM2_HI_VALUE                0            /*  High Limit for Channel 2 */
+#define BITM_ADC_LIM2_HI_EN                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Enable High Limit Comparison on Channel */
+#define BITM_ADC_LIM2_HI_VALUE               (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t  ))    /*  High Limit for Channel 2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_HYS2                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_HYS2_EN                     15            /*  Enable Hysteresis for Comparison on Channel 2 */
+#define BITP_ADC_HYS2_MONCYC                 12            /*  Number of Conversion Cycles to Monitor Channel 2 */
+#define BITP_ADC_HYS2_VALUE                   0            /*  Hysteresis Value for Channel 2 */
+#define BITM_ADC_HYS2_EN                     (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Enable Hysteresis for Comparison on Channel 2 */
+#define BITM_ADC_HYS2_MONCYC                 (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t  ))    /*  Number of Conversion Cycles to Monitor Channel 2 */
+#define BITM_ADC_HYS2_VALUE                  (_ADI_MSK_3(0x000001FF,0x000001FFU, uint16_t  ))    /*  Hysteresis Value for Channel 2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_LIM3_LO                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_LIM3_LO_EN                  15            /*  Enable Low Limit Comparison on Channel 3 */
+#define BITP_ADC_LIM3_LO_VALUE                0            /*  Low Limit for Channel 3 */
+#define BITM_ADC_LIM3_LO_EN                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Enable Low Limit Comparison on Channel 3 */
+#define BITM_ADC_LIM3_LO_VALUE               (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t  ))    /*  Low Limit for Channel 3 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_LIM3_HI                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_LIM3_HI_EN                  15            /*  Enable High Limit Comparison on Channel 3 */
+#define BITP_ADC_LIM3_HI_VALUE                0            /*  High Limit for Channel 3 */
+#define BITM_ADC_LIM3_HI_EN                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Enable High Limit Comparison on Channel 3 */
+#define BITM_ADC_LIM3_HI_VALUE               (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t  ))    /*  High Limit for Channel 3 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_HYS3                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_HYS3_EN                     15            /*  Enable Hysteresis for Comparison on Channel 3 */
+#define BITP_ADC_HYS3_MONCYC                 12            /*  Number of Conversion Cycles to Monitor Channel 3 */
+#define BITP_ADC_HYS3_VALUE                   0            /*  Hysteresis Value for Channel 3 */
+#define BITM_ADC_HYS3_EN                     (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Enable Hysteresis for Comparison on Channel 3 */
+#define BITM_ADC_HYS3_MONCYC                 (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t  ))    /*  Number of Conversion Cycles to Monitor Channel 3 */
+#define BITM_ADC_HYS3_VALUE                  (_ADI_MSK_3(0x000001FF,0x000001FFU, uint16_t  ))    /*  Hysteresis Value for Channel 3 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CFG1                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CFG1_RBUFLP                  0            /*  Enable Low Power Mode for Reference Buffer */
+#define BITM_ADC_CFG1_RBUFLP                 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Enable Low Power Mode for Reference Buffer */
+
+
+/* ============================================================================================================================
+        DMA
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        DMA0
+   ============================================================================================================================ */
+#define REG_DMA0_STAT                        0x40010000            /*  DMA0 DMA Status */
+#define REG_DMA0_CFG                         0x40010004            /*  DMA0 DMA Configuration */
+#define REG_DMA0_PDBPTR                      0x40010008            /*  DMA0 DMA Channel Primary Control Database Pointer */
+#define REG_DMA0_ADBPTR                      0x4001000C            /*  DMA0 DMA Channel Alternate Control Database Pointer */
+#define REG_DMA0_SWREQ                       0x40010014            /*  DMA0 DMA Channel Software Request */
+#define REG_DMA0_RMSK_SET                    0x40010020            /*  DMA0 DMA Channel Request Mask Set */
+#define REG_DMA0_RMSK_CLR                    0x40010024            /*  DMA0 DMA Channel Request Mask Clear */
+#define REG_DMA0_EN_SET                      0x40010028            /*  DMA0 DMA Channel Enable Set */
+#define REG_DMA0_EN_CLR                      0x4001002C            /*  DMA0 DMA Channel Enable Clear */
+#define REG_DMA0_ALT_SET                     0x40010030            /*  DMA0 DMA Channel Primary Alternate Set */
+#define REG_DMA0_ALT_CLR                     0x40010034            /*  DMA0 DMA Channel Primary Alternate Clear */
+#define REG_DMA0_PRI_SET                     0x40010038            /*  DMA0 DMA Channel Priority Set */
+#define REG_DMA0_PRI_CLR                     0x4001003C            /*  DMA0 DMA Channel Priority Clear */
+#define REG_DMA0_ERRCHNL_CLR                 0x40010048            /*  DMA0 DMA per Channel Error Clear */
+#define REG_DMA0_ERR_CLR                     0x4001004C            /*  DMA0 DMA Bus Error Clear */
+#define REG_DMA0_INVALIDDESC_CLR             0x40010050            /*  DMA0 DMA per Channel Invalid Descriptor Clear */
+#define REG_DMA0_BS_SET                      0x40010800            /*  DMA0 DMA Channel Bytes Swap Enable Set */
+#define REG_DMA0_BS_CLR                      0x40010804            /*  DMA0 DMA Channel Bytes Swap Enable Clear */
+#define REG_DMA0_SRCADDR_SET                 0x40010810            /*  DMA0 DMA Channel Source Address Decrement Enable Set */
+#define REG_DMA0_SRCADDR_CLR                 0x40010814            /*  DMA0 DMA Channel Source Address Decrement Enable Clear */
+#define REG_DMA0_DSTADDR_SET                 0x40010818            /*  DMA0 DMA Channel Destination Address Decrement Enable Set */
+#define REG_DMA0_DSTADDR_CLR                 0x4001081C            /*  DMA0 DMA Channel Destination Address Decrement Enable Clear */
+#define REG_DMA0_REVID                       0x40010FE0            /*  DMA0 DMA Controller Revision ID */
+
+/* ============================================================================================================================
+        DMA Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_STAT                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_STAT_CHANM1                 16            /*  Number of Available DMA Channels Minus 1 */
+#define BITP_DMA_STAT_MEN                     0            /*  Enable Status of the Controller */
+#define BITM_DMA_STAT_CHANM1                 (_ADI_MSK_3(0x001F0000,0x001F0000UL, uint32_t  ))    /*  Number of Available DMA Channels Minus 1 */
+#define BITM_DMA_STAT_MEN                    (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Enable Status of the Controller */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_CFG                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_CFG_MEN                      0            /*  Controller Enable */
+#define BITM_DMA_CFG_MEN                     (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Controller Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_PDBPTR                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_PDBPTR_ADDR                  0            /*  Pointer to the Base Address of the Primary Data Structure */
+#define BITM_DMA_PDBPTR_ADDR                 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Pointer to the Base Address of the Primary Data Structure */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_ADBPTR                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_ADBPTR_ADDR                  0            /*  Base Address of the Alternate Data Structure */
+#define BITM_DMA_ADBPTR_ADDR                 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Base Address of the Alternate Data Structure */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_SWREQ                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_SWREQ_CHAN                   0            /*  Generate Software Request */
+#define BITM_DMA_SWREQ_CHAN                  (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t  ))    /*  Generate Software Request */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_RMSK_SET                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_RMSK_SET_CHAN                0            /*  Mask Requests from DMA Channels */
+#define BITM_DMA_RMSK_SET_CHAN               (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t  ))    /*  Mask Requests from DMA Channels */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_RMSK_CLR                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_RMSK_CLR_CHAN                0            /*  Clear Request Mask Set Bits */
+#define BITM_DMA_RMSK_CLR_CHAN               (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t  ))    /*  Clear Request Mask Set Bits */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_EN_SET                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_EN_SET_CHAN                  0            /*  Enable DMA Channels */
+#define BITM_DMA_EN_SET_CHAN                 (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t  ))    /*  Enable DMA Channels */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_EN_CLR                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_EN_CLR_CHAN                  0            /*  Disable DMA Channels */
+#define BITM_DMA_EN_CLR_CHAN                 (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t  ))    /*  Disable DMA Channels */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_ALT_SET                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_ALT_SET_CHAN                 0            /*  Control Structure Status / Select Alternate Structure */
+#define BITM_DMA_ALT_SET_CHAN                (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t  ))    /*  Control Structure Status / Select Alternate Structure */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_ALT_CLR                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_ALT_CLR_CHAN                 0            /*  Select Primary Data Structure */
+#define BITM_DMA_ALT_CLR_CHAN                (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t  ))    /*  Select Primary Data Structure */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_PRI_SET                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_PRI_SET_CHAN                 0            /*  Configure Channel for High Priority */
+#define BITM_DMA_PRI_SET_CHAN                (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t  ))    /*  Configure Channel for High Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_PRI_CLR                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_PRI_CLR_CHPRICLR             0            /*  Configure Channel for Default Priority Level */
+#define BITM_DMA_PRI_CLR_CHPRICLR            (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t  ))    /*  Configure Channel for Default Priority Level */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_ERRCHNL_CLR                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_ERRCHNL_CLR_CHAN             0            /*  Per Channel Bus Error Status/Clear */
+#define BITM_DMA_ERRCHNL_CLR_CHAN            (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t  ))    /*  Per Channel Bus Error Status/Clear */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_ERR_CLR                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_ERR_CLR_CHAN                 0            /*  Bus Error Status */
+#define BITM_DMA_ERR_CLR_CHAN                (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t  ))    /*  Bus Error Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_INVALIDDESC_CLR                  Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_INVALIDDESC_CLR_CHAN         0            /*  Per Channel Invalid Descriptor Status/Clear */
+#define BITM_DMA_INVALIDDESC_CLR_CHAN        (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t  ))    /*  Per Channel Invalid Descriptor Status/Clear */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_BS_SET                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_BS_SET_CHAN                  0            /*  Byte Swap Status */
+#define BITM_DMA_BS_SET_CHAN                 (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t  ))    /*  Byte Swap Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_BS_CLR                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_BS_CLR_CHAN                  0            /*  Disable Byte Swap */
+#define BITM_DMA_BS_CLR_CHAN                 (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t  ))    /*  Disable Byte Swap */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_SRCADDR_SET                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_SRCADDR_SET_CHAN             0            /*  Source Address Decrement Status */
+#define BITM_DMA_SRCADDR_SET_CHAN            (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t  ))    /*  Source Address Decrement Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_SRCADDR_CLR                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_SRCADDR_CLR_CHAN             0            /*  Disable Source Address Decrement */
+#define BITM_DMA_SRCADDR_CLR_CHAN            (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t  ))    /*  Disable Source Address Decrement */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_DSTADDR_SET                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_DSTADDR_SET_CHAN             0            /*  Destination Address Decrement Status */
+#define BITM_DMA_DSTADDR_SET_CHAN            (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t  ))    /*  Destination Address Decrement Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_DSTADDR_CLR                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_DSTADDR_CLR_CHAN             0            /*  Disable Destination Address Decrement */
+#define BITM_DMA_DSTADDR_CLR_CHAN            (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t  ))    /*  Disable Destination Address Decrement */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_REVID                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_REVID_VALUE                  0            /*  DMA Controller Revision ID */
+#define BITM_DMA_REVID_VALUE                 (_ADI_MSK_3(0x000000FF,0x000000FFUL, uint32_t  ))    /*  DMA Controller Revision ID */
+
+
+/* ============================================================================================================================
+        Flash Controller
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        FLCC0
+   ============================================================================================================================ */
+#define REG_FLCC0_STAT                       0x40018000            /*  FLCC0 Status */
+#define REG_FLCC0_IEN                        0x40018004            /*  FLCC0 Interrupt Enable */
+#define REG_FLCC0_CMD                        0x40018008            /*  FLCC0 Command */
+#define REG_FLCC0_KH_ADDR                    0x4001800C            /*  FLCC0 Write Address */
+#define REG_FLCC0_KH_DATA0                   0x40018010            /*  FLCC0 Write Lower Data */
+#define REG_FLCC0_KH_DATA1                   0x40018014            /*  FLCC0 Write Upper Data */
+#define REG_FLCC0_PAGE_ADDR0                 0x40018018            /*  FLCC0 Lower Page Address */
+#define REG_FLCC0_PAGE_ADDR1                 0x4001801C            /*  FLCC0 Upper Page Address */
+#define REG_FLCC0_KEY                        0x40018020            /*  FLCC0 Key */
+#define REG_FLCC0_WR_ABORT_ADDR              0x40018024            /*  FLCC0 Write Abort Address */
+#define REG_FLCC0_WRPROT                     0x40018028            /*  FLCC0 Write Protection */
+#define REG_FLCC0_SIGNATURE                  0x4001802C            /*  FLCC0 Signature */
+#define REG_FLCC0_UCFG                       0x40018030            /*  FLCC0 User Configuration */
+#define REG_FLCC0_TIME_PARAM0                0x40018034            /*  FLCC0 Time Parameter 0 */
+#define REG_FLCC0_TIME_PARAM1                0x40018038            /*  FLCC0 Time Parameter 1 */
+#define REG_FLCC0_ABORT_EN_LO                0x4001803C            /*  FLCC0 IRQ Abort Enable (Lower Bits) */
+#define REG_FLCC0_ABORT_EN_HI                0x40018040            /*  FLCC0 IRQ Abort Enable (Upper Bits) */
+#define REG_FLCC0_ECC_CFG                    0x40018044            /*  FLCC0 ECC Configuration */
+#define REG_FLCC0_ECC_ADDR                   0x40018048            /*  FLCC0 ECC Status (Address) */
+#define REG_FLCC0_POR_SEC                    0x40018050            /*  FLCC0 Flash Security */
+#define REG_FLCC0_VOL_CFG                    0x40018054            /*  FLCC0 Volatile Flash Configuration */
+
+/* ============================================================================================================================
+        FLCC Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_STAT                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_STAT_CACHESRAMPERR         29            /*  SRAM Parity Errors in Cache Controller */
+#define BITP_FLCC_STAT_ECCDCODE              27            /*  DCode AHB Bus Error ECC Status */
+#define BITP_FLCC_STAT_ECCICODE              25            /*  ICode AHB Bus Error ECC Status */
+#define BITP_FLCC_STAT_ECCERRCNT             17            /*  ECC Correction Counter */
+#define BITP_FLCC_STAT_ECCINFOSIGN           15            /*  ECC Status of Flash Initialization */
+#define BITP_FLCC_STAT_INIT                  14            /*  Flash Controller Initialization in Progress */
+#define BITP_FLCC_STAT_SIGNERR               13            /*  Signature Check Failure During Initialization */
+#define BITP_FLCC_STAT_OVERLAP               11            /*  Overlapping Command */
+#define BITP_FLCC_STAT_ECCRDERR               9            /*  ECC IRQ Cause */
+#define BITP_FLCC_STAT_ECCERRCMD              7            /*  ECC Errors Detected During User Issued SIGN Command */
+#define BITP_FLCC_STAT_SLEEPING               6            /*  Flash Array is in Low Power (Sleep) Mode */
+#define BITP_FLCC_STAT_CMDFAIL                4            /*  Provides Information on Command Failures */
+#define BITP_FLCC_STAT_WRALCOMP               3            /*  Write Almost Complete */
+#define BITP_FLCC_STAT_CMDCOMP                2            /*  Command Complete */
+#define BITP_FLCC_STAT_WRCLOSE                1            /*  WRITE Registers are Closed */
+#define BITP_FLCC_STAT_CMDBUSY                0            /*  Command Busy */
+#define BITM_FLCC_STAT_CACHESRAMPERR         (_ADI_MSK_3(0x20000000,0x20000000UL, uint32_t  ))    /*  SRAM Parity Errors in Cache Controller */
+#define BITM_FLCC_STAT_ECCDCODE              (_ADI_MSK_3(0x18000000,0x18000000UL, uint32_t  ))    /*  DCode AHB Bus Error ECC Status */
+#define BITM_FLCC_STAT_ECCICODE              (_ADI_MSK_3(0x06000000,0x06000000UL, uint32_t  ))    /*  ICode AHB Bus Error ECC Status */
+#define BITM_FLCC_STAT_ECCERRCNT             (_ADI_MSK_3(0x000E0000,0x000E0000UL, uint32_t  ))    /*  ECC Correction Counter */
+#define BITM_FLCC_STAT_ECCINFOSIGN           (_ADI_MSK_3(0x00018000,0x00018000UL, uint32_t  ))    /*  ECC Status of Flash Initialization */
+#define BITM_FLCC_STAT_INIT                  (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t  ))    /*  Flash Controller Initialization in Progress */
+#define BITM_FLCC_STAT_SIGNERR               (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t  ))    /*  Signature Check Failure During Initialization */
+#define BITM_FLCC_STAT_OVERLAP               (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t  ))    /*  Overlapping Command */
+#define BITM_FLCC_STAT_ECCRDERR              (_ADI_MSK_3(0x00000600,0x00000600UL, uint32_t  ))    /*  ECC IRQ Cause */
+#define BITM_FLCC_STAT_ECCERRCMD             (_ADI_MSK_3(0x00000180,0x00000180UL, uint32_t  ))    /*  ECC Errors Detected During User Issued SIGN Command */
+#define BITM_FLCC_STAT_SLEEPING              (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t  ))    /*  Flash Array is in Low Power (Sleep) Mode */
+#define BITM_FLCC_STAT_CMDFAIL               (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t  ))    /*  Provides Information on Command Failures */
+#define BITM_FLCC_STAT_WRALCOMP              (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Write Almost Complete */
+#define BITM_FLCC_STAT_CMDCOMP               (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Command Complete */
+#define BITM_FLCC_STAT_WRCLOSE               (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  WRITE Registers are Closed */
+#define BITM_FLCC_STAT_CMDBUSY               (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Command Busy */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_IEN                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_IEN_ECC_ERROR               6            /*  Control 2-bit ECC Error Events */
+#define BITP_FLCC_IEN_CMDFAIL                 2            /*  Command Fail Interrupt Enable */
+#define BITP_FLCC_IEN_WRALCMPLT               1            /*  Write Almost Complete Interrupt Enable */
+#define BITP_FLCC_IEN_CMDCMPLT                0            /*  Command Complete Interrupt Enable */
+#define BITM_FLCC_IEN_ECC_ERROR              (_ADI_MSK_3(0x000000C0,0x000000C0UL, uint32_t  ))    /*  Control 2-bit ECC Error Events */
+#define BITM_FLCC_IEN_CMDFAIL                (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Command Fail Interrupt Enable */
+#define BITM_FLCC_IEN_WRALCMPLT              (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Write Almost Complete Interrupt Enable */
+#define BITM_FLCC_IEN_CMDCMPLT               (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Command Complete Interrupt Enable */
+#define ENUM_FLCC_IEN_NONE_ERR               (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  ECC_ERROR: Do not generate a response to ECC events */
+#define ENUM_FLCC_IEN_BUS_ERR_ERR            (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t  ))    /*  ECC_ERROR: Generate Bus Errors in response to ECC events */
+#define ENUM_FLCC_IEN_IRQ_ERR                (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t  ))    /*  ECC_ERROR: Generate IRQs in response to ECC events */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_CMD                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_CMD_VALUE                   0            /*  Commands */
+#define BITM_FLCC_CMD_VALUE                  (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t  ))    /*  Commands */
+#define ENUM_FLCC_CMD_IDLE                   (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  VALUE: IDLE */
+#define ENUM_FLCC_CMD_ABORT                  (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  VALUE: ABORT */
+#define ENUM_FLCC_CMD_SLEEP                  (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  VALUE: Requests flash to enter Sleep mode */
+#define ENUM_FLCC_CMD_SIGN                   (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t  ))    /*  VALUE: SIGN */
+#define ENUM_FLCC_CMD_WRITE                  (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  VALUE: WRITE */
+#define ENUM_FLCC_CMD_BLANK_CHECK            (_ADI_MSK_3(0x00000005,0x00000005UL, uint32_t  ))    /*  VALUE: Checks all of User Space; fails if any bits in user space are cleared */
+#define ENUM_FLCC_CMD_ERASEPAGE              (_ADI_MSK_3(0x00000006,0x00000006UL, uint32_t  ))    /*  VALUE: ERASEPAGE */
+#define ENUM_FLCC_CMD_MASSERASE              (_ADI_MSK_3(0x00000007,0x00000007UL, uint32_t  ))    /*  VALUE: MASSERASE */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_KH_ADDR                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_KH_ADDR_VALUE               3            /*  Key Hole Address */
+#define BITM_FLCC_KH_ADDR_VALUE              (_ADI_MSK_3(0x0007FFF8,0x0007FFF8UL, uint32_t  ))    /*  Key Hole Address */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_KH_DATA0                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_KH_DATA0_VALUE              0            /*  Lower 32 Bits of Key Hole Data */
+#define BITM_FLCC_KH_DATA0_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Lower 32 Bits of Key Hole Data */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_KH_DATA1                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_KH_DATA1_VALUE              0            /*  Upper Half of 64-bit Dualword Data to Be Written */
+#define BITM_FLCC_KH_DATA1_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Upper Half of 64-bit Dualword Data to Be Written */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_PAGE_ADDR0                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_PAGE_ADDR0_VALUE           10            /*  Lower Address Bits of the Page Address */
+#define BITM_FLCC_PAGE_ADDR0_VALUE           (_ADI_MSK_3(0x0007FC00,0x0007FC00UL, uint32_t  ))    /*  Lower Address Bits of the Page Address */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_PAGE_ADDR1                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_PAGE_ADDR1_VALUE           10            /*  Upper Address Bits of the Page Address */
+#define BITM_FLCC_PAGE_ADDR1_VALUE           (_ADI_MSK_3(0x0007FC00,0x0007FC00UL, uint32_t  ))    /*  Upper Address Bits of the Page Address */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_KEY                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_KEY_VALUE                   0            /*  Key Register */
+#define BITM_FLCC_KEY_VALUE                  (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Key Register */
+#define ENUM_FLCC_KEY_USERKEY                (_ADI_MSK_3(0x676C7565,0x676C7565UL, uint32_t  ))    /*  VALUE: USERKEY */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_WR_ABORT_ADDR                   Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_WR_ABORT_ADDR_VALUE         0            /*  Address Targeted by an Ongoing Write Command */
+#define BITM_FLCC_WR_ABORT_ADDR_VALUE        (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Address Targeted by an Ongoing Write Command */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_WRPROT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_WRPROT_WORD                 0            /*  Write Protect */
+#define BITM_FLCC_WRPROT_WORD                (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Write Protect */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_SIGNATURE                       Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_SIGNATURE_VALUE             0            /*  Signature */
+#define BITM_FLCC_SIGNATURE_VALUE            (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Signature */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_UCFG                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_UCFG_AUTOINCEN              1            /*  Auto Address Increment for Key Hole Access */
+#define BITP_FLCC_UCFG_KHDMAEN                0            /*  Key Hole DMA Enable */
+#define BITM_FLCC_UCFG_AUTOINCEN             (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Auto Address Increment for Key Hole Access */
+#define BITM_FLCC_UCFG_KHDMAEN               (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Key Hole DMA Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_TIME_PARAM0                     Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_TIME_PARAM0_TNVH1          28            /*  NVSTR Hold Time During Mass Erase */
+#define BITP_FLCC_TIME_PARAM0_TERASE         24            /*  Erase Time */
+#define BITP_FLCC_TIME_PARAM0_TRCV           20            /*  Recovery Time */
+#define BITP_FLCC_TIME_PARAM0_TNVH           16            /*  NVSTR Hold Time */
+#define BITP_FLCC_TIME_PARAM0_TPROG          12            /*  Program Time */
+#define BITP_FLCC_TIME_PARAM0_TPGS            8            /*  NVSTR to Program Setup Time */
+#define BITP_FLCC_TIME_PARAM0_TNVS            4            /*  PROG/ERASE to NVSTR Setup Time */
+#define BITP_FLCC_TIME_PARAM0_DIVREFCLK       0            /*  Divide Reference Clock (by 2) */
+#define BITM_FLCC_TIME_PARAM0_TNVH1          (_ADI_MSK_3(0xF0000000,0xF0000000UL, uint32_t  ))    /*  NVSTR Hold Time During Mass Erase */
+#define BITM_FLCC_TIME_PARAM0_TERASE         (_ADI_MSK_3(0x0F000000,0x0F000000UL, uint32_t  ))    /*  Erase Time */
+#define BITM_FLCC_TIME_PARAM0_TRCV           (_ADI_MSK_3(0x00F00000,0x00F00000UL, uint32_t  ))    /*  Recovery Time */
+#define BITM_FLCC_TIME_PARAM0_TNVH           (_ADI_MSK_3(0x000F0000,0x000F0000UL, uint32_t  ))    /*  NVSTR Hold Time */
+#define BITM_FLCC_TIME_PARAM0_TPROG          (_ADI_MSK_3(0x0000F000,0x0000F000UL, uint32_t  ))    /*  Program Time */
+#define BITM_FLCC_TIME_PARAM0_TPGS           (_ADI_MSK_3(0x00000F00,0x00000F00UL, uint32_t  ))    /*  NVSTR to Program Setup Time */
+#define BITM_FLCC_TIME_PARAM0_TNVS           (_ADI_MSK_3(0x000000F0,0x000000F0UL, uint32_t  ))    /*  PROG/ERASE to NVSTR Setup Time */
+#define BITM_FLCC_TIME_PARAM0_DIVREFCLK      (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Divide Reference Clock (by 2) */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_TIME_PARAM1                     Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_TIME_PARAM1_TWK             0            /*  Wakeup Time */
+#define BITM_FLCC_TIME_PARAM1_TWK            (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t  ))    /*  Wakeup Time */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_ABORT_EN_LO                     Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_ABORT_EN_LO_VALUE           0            /*  Sys IRQ Abort Enable */
+#define BITM_FLCC_ABORT_EN_LO_VALUE          (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Sys IRQ Abort Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_ABORT_EN_HI                     Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_ABORT_EN_HI_VALUE           0            /*  Sys IRQ Abort Enable */
+#define BITM_FLCC_ABORT_EN_HI_VALUE          (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Sys IRQ Abort Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_ECC_CFG                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_ECC_CFG_PTR                 8            /*  ECC Start Page Pointer */
+#define BITP_FLCC_ECC_CFG_INFOEN              1            /*  Info Space ECC Enable Bit */
+#define BITP_FLCC_ECC_CFG_EN                  0            /*  ECC Enable */
+#define BITM_FLCC_ECC_CFG_PTR                (_ADI_MSK_3(0xFFFFFF00,0xFFFFFF00UL, uint32_t  ))    /*  ECC Start Page Pointer */
+#define BITM_FLCC_ECC_CFG_INFOEN             (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Info Space ECC Enable Bit */
+#define BITM_FLCC_ECC_CFG_EN                 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  ECC Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_ECC_ADDR                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_ECC_ADDR_VALUE              0            /*  ECC Error Address */
+#define BITM_FLCC_ECC_ADDR_VALUE             (_ADI_MSK_3(0x0007FFFF,0x0007FFFFUL, uint32_t  ))    /*  ECC Error Address */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_POR_SEC                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_POR_SEC_SECURE              0            /*  Prevent Read/Write Access to User Space (Sticky When Set) */
+#define BITM_FLCC_POR_SEC_SECURE             (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Prevent Read/Write Access to User Space (Sticky When Set) */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_VOL_CFG                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_VOL_CFG_INFO_REMAP          0            /*  Alias the Info Space to the Base Address of User Space */
+#define BITM_FLCC_VOL_CFG_INFO_REMAP         (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Alias the Info Space to the Base Address of User Space */
+
+
+/* ============================================================================================================================
+        Cache Controller
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        FLCC0_CACHE
+   ============================================================================================================================ */
+#define REG_FLCC0_CACHE_STAT                 0x40018058            /*  FLCC0_CACHE Cache Status */
+#define REG_FLCC0_CACHE_SETUP                0x4001805C            /*  FLCC0_CACHE Cache Setup */
+#define REG_FLCC0_CACHE_KEY                  0x40018060            /*  FLCC0_CACHE Cache Key */
+
+/* ============================================================================================================================
+        FLCC_CACHE Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_CACHE_STAT                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_CACHE_STAT_ICEN             0            /*  I-Cache Enabled */
+#define BITM_FLCC_CACHE_STAT_ICEN            (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  I-Cache Enabled */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_CACHE_SETUP                     Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_CACHE_SETUP_ICEN            0            /*  I-Cache Enable */
+#define BITM_FLCC_CACHE_SETUP_ICEN           (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  I-Cache Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_CACHE_KEY                       Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_CACHE_KEY_VALUE             0            /*  Cache Key Register */
+#define BITM_FLCC_CACHE_KEY_VALUE            (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Cache Key Register */
+
+
+/* ============================================================================================================================
+        
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        GPIO0
+   ============================================================================================================================ */
+#define REG_GPIO0_CFG                        0x40020000            /*  GPIO0 Port Configuration */
+#define REG_GPIO0_OEN                        0x40020004            /*  GPIO0 Port Output Enable */
+#define REG_GPIO0_PE                         0x40020008            /*  GPIO0 Port Output Pull-up/Pull-down Enable */
+#define REG_GPIO0_IEN                        0x4002000C            /*  GPIO0 Port Input Path Enable */
+#define REG_GPIO0_IN                         0x40020010            /*  GPIO0 Port Registered Data Input */
+#define REG_GPIO0_OUT                        0x40020014            /*  GPIO0 Port Data Output */
+#define REG_GPIO0_SET                        0x40020018            /*  GPIO0 Port Data Out Set */
+#define REG_GPIO0_CLR                        0x4002001C            /*  GPIO0 Port Data Out Clear */
+#define REG_GPIO0_TGL                        0x40020020            /*  GPIO0 Port Pin Toggle */
+#define REG_GPIO0_POL                        0x40020024            /*  GPIO0 Port Interrupt Polarity */
+#define REG_GPIO0_IENA                       0x40020028            /*  GPIO0 Port Interrupt A Enable */
+#define REG_GPIO0_IENB                       0x4002002C            /*  GPIO0 Port Interrupt B Enable */
+#define REG_GPIO0_INT                        0x40020030            /*  GPIO0 Port Interrupt Status */
+#define REG_GPIO0_DS                         0x40020034            /*  GPIO0 Port Drive Strength Select */
+
+/* ============================================================================================================================
+        GPIO1
+   ============================================================================================================================ */
+#define REG_GPIO1_CFG                        0x40020040            /*  GPIO1 Port Configuration */
+#define REG_GPIO1_OEN                        0x40020044            /*  GPIO1 Port Output Enable */
+#define REG_GPIO1_PE                         0x40020048            /*  GPIO1 Port Output Pull-up/Pull-down Enable */
+#define REG_GPIO1_IEN                        0x4002004C            /*  GPIO1 Port Input Path Enable */
+#define REG_GPIO1_IN                         0x40020050            /*  GPIO1 Port Registered Data Input */
+#define REG_GPIO1_OUT                        0x40020054            /*  GPIO1 Port Data Output */
+#define REG_GPIO1_SET                        0x40020058            /*  GPIO1 Port Data Out Set */
+#define REG_GPIO1_CLR                        0x4002005C            /*  GPIO1 Port Data Out Clear */
+#define REG_GPIO1_TGL                        0x40020060            /*  GPIO1 Port Pin Toggle */
+#define REG_GPIO1_POL                        0x40020064            /*  GPIO1 Port Interrupt Polarity */
+#define REG_GPIO1_IENA                       0x40020068            /*  GPIO1 Port Interrupt A Enable */
+#define REG_GPIO1_IENB                       0x4002006C            /*  GPIO1 Port Interrupt B Enable */
+#define REG_GPIO1_INT                        0x40020070            /*  GPIO1 Port Interrupt Status */
+#define REG_GPIO1_DS                         0x40020074            /*  GPIO1 Port Drive Strength Select */
+
+/* ============================================================================================================================
+        GPIO2
+   ============================================================================================================================ */
+#define REG_GPIO2_CFG                        0x40020080            /*  GPIO2 Port Configuration */
+#define REG_GPIO2_OEN                        0x40020084            /*  GPIO2 Port Output Enable */
+#define REG_GPIO2_PE                         0x40020088            /*  GPIO2 Port Output Pull-up/Pull-down Enable */
+#define REG_GPIO2_IEN                        0x4002008C            /*  GPIO2 Port Input Path Enable */
+#define REG_GPIO2_IN                         0x40020090            /*  GPIO2 Port Registered Data Input */
+#define REG_GPIO2_OUT                        0x40020094            /*  GPIO2 Port Data Output */
+#define REG_GPIO2_SET                        0x40020098            /*  GPIO2 Port Data Out Set */
+#define REG_GPIO2_CLR                        0x4002009C            /*  GPIO2 Port Data Out Clear */
+#define REG_GPIO2_TGL                        0x400200A0            /*  GPIO2 Port Pin Toggle */
+#define REG_GPIO2_POL                        0x400200A4            /*  GPIO2 Port Interrupt Polarity */
+#define REG_GPIO2_IENA                       0x400200A8            /*  GPIO2 Port Interrupt A Enable */
+#define REG_GPIO2_IENB                       0x400200AC            /*  GPIO2 Port Interrupt B Enable */
+#define REG_GPIO2_INT                        0x400200B0            /*  GPIO2 Port Interrupt Status */
+#define REG_GPIO2_DS                         0x400200B4            /*  GPIO2 Port Drive Strength Select */
+
+/* ============================================================================================================================
+        GPIO Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_CFG                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_CFG_PIN15                  30            /*  Pin 15 Configuration Bits */
+#define BITP_GPIO_CFG_PIN14                  28            /*  Pin 14 Configuration Bits */
+#define BITP_GPIO_CFG_PIN13                  26            /*  Pin 13 Configuration Bits */
+#define BITP_GPIO_CFG_PIN12                  24            /*  Pin 12 Configuration Bits */
+#define BITP_GPIO_CFG_PIN11                  22            /*  Pin 11 Configuration Bits */
+#define BITP_GPIO_CFG_PIN10                  20            /*  Pin 10 Configuration Bits */
+#define BITP_GPIO_CFG_PIN09                  18            /*  Pin 9 Configuration Bits */
+#define BITP_GPIO_CFG_PIN08                  16            /*  Pin 8 Configuration Bits */
+#define BITP_GPIO_CFG_PIN07                  14            /*  Pin 7 Configuration Bits */
+#define BITP_GPIO_CFG_PIN06                  12            /*  Pin 6 Configuration Bits */
+#define BITP_GPIO_CFG_PIN05                  10            /*  Pin 5 Configuration Bits */
+#define BITP_GPIO_CFG_PIN04                   8            /*  Pin 4 Configuration Bits */
+#define BITP_GPIO_CFG_PIN03                   6            /*  Pin 3 Configuration Bits */
+#define BITP_GPIO_CFG_PIN02                   4            /*  Pin 2 Configuration Bits */
+#define BITP_GPIO_CFG_PIN01                   2            /*  Pin 1 Configuration Bits */
+#define BITP_GPIO_CFG_PIN00                   0            /*  Pin 0 Configuration Bits */
+#define BITM_GPIO_CFG_PIN15                  (_ADI_MSK_3(0xC0000000,0xC0000000UL, uint32_t  ))    /*  Pin 15 Configuration Bits */
+#define BITM_GPIO_CFG_PIN14                  (_ADI_MSK_3(0x30000000,0x30000000UL, uint32_t  ))    /*  Pin 14 Configuration Bits */
+#define BITM_GPIO_CFG_PIN13                  (_ADI_MSK_3(0x0C000000,0x0C000000UL, uint32_t  ))    /*  Pin 13 Configuration Bits */
+#define BITM_GPIO_CFG_PIN12                  (_ADI_MSK_3(0x03000000,0x03000000UL, uint32_t  ))    /*  Pin 12 Configuration Bits */
+#define BITM_GPIO_CFG_PIN11                  (_ADI_MSK_3(0x00C00000,0x00C00000UL, uint32_t  ))    /*  Pin 11 Configuration Bits */
+#define BITM_GPIO_CFG_PIN10                  (_ADI_MSK_3(0x00300000,0x00300000UL, uint32_t  ))    /*  Pin 10 Configuration Bits */
+#define BITM_GPIO_CFG_PIN09                  (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t  ))    /*  Pin 9 Configuration Bits */
+#define BITM_GPIO_CFG_PIN08                  (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t  ))    /*  Pin 8 Configuration Bits */
+#define BITM_GPIO_CFG_PIN07                  (_ADI_MSK_3(0x0000C000,0x0000C000UL, uint32_t  ))    /*  Pin 7 Configuration Bits */
+#define BITM_GPIO_CFG_PIN06                  (_ADI_MSK_3(0x00003000,0x00003000UL, uint32_t  ))    /*  Pin 6 Configuration Bits */
+#define BITM_GPIO_CFG_PIN05                  (_ADI_MSK_3(0x00000C00,0x00000C00UL, uint32_t  ))    /*  Pin 5 Configuration Bits */
+#define BITM_GPIO_CFG_PIN04                  (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t  ))    /*  Pin 4 Configuration Bits */
+#define BITM_GPIO_CFG_PIN03                  (_ADI_MSK_3(0x000000C0,0x000000C0UL, uint32_t  ))    /*  Pin 3 Configuration Bits */
+#define BITM_GPIO_CFG_PIN02                  (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t  ))    /*  Pin 2 Configuration Bits */
+#define BITM_GPIO_CFG_PIN01                  (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t  ))    /*  Pin 1 Configuration Bits */
+#define BITM_GPIO_CFG_PIN00                  (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t  ))    /*  Pin 0 Configuration Bits */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_OEN                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_OEN_VALUE                   0            /*  Pin Output Drive Enable */
+#define BITM_GPIO_OEN_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Pin Output Drive Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_PE                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_PE_VALUE                    0            /*  Pin Pull Enable */
+#define BITM_GPIO_PE_VALUE                   (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Pin Pull Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_IEN                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_IEN_VALUE                   0            /*  Input Path Enable */
+#define BITM_GPIO_IEN_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Input Path Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_IN                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_IN_VALUE                    0            /*  Registered Data Input */
+#define BITM_GPIO_IN_VALUE                   (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Registered Data Input */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_OUT                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_OUT_VALUE                   0            /*  Data Out */
+#define BITM_GPIO_OUT_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Data Out */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_SET                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_SET_VALUE                   0            /*  Set the Output High for the Pin */
+#define BITM_GPIO_SET_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Set the Output High for the Pin */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_CLR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_CLR_VALUE                   0            /*  Set the Output Low for the Port Pin */
+#define BITM_GPIO_CLR_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Set the Output Low for the Port Pin */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_TGL                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_TGL_VALUE                   0            /*  Toggle the Output of the Port Pin */
+#define BITM_GPIO_TGL_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Toggle the Output of the Port Pin */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_POL                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_POL_VALUE                   0            /*  Interrupt polarity */
+#define BITM_GPIO_POL_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Interrupt polarity */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_IENA                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_IENA_VALUE                  0            /*  Interrupt A enable */
+#define BITM_GPIO_IENA_VALUE                 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Interrupt A enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_IENB                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_IENB_VALUE                  0            /*  Interrupt B enable */
+#define BITM_GPIO_IENB_VALUE                 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Interrupt B enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_INT                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_INT_VALUE                   0            /*  Interrupt Status */
+#define BITM_GPIO_INT_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Interrupt Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_DS                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_DS_VALUE                    0            /*  Drive Strength Select */
+#define BITM_GPIO_DS_VALUE                   (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Drive Strength Select */
+
+
+/* ============================================================================================================================
+        Serial Port
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        SPORT0
+   ============================================================================================================================ */
+#define REG_SPORT0_CTL_A                     0x40038000            /*  SPORT0 Half SPORT 'A' Control */
+#define REG_SPORT0_DIV_A                     0x40038004            /*  SPORT0 Half SPORT 'A' Divisor */
+#define REG_SPORT0_IEN_A                     0x40038008            /*  SPORT0 Half SPORT A's Interrupt Enable */
+#define REG_SPORT0_STAT_A                    0x4003800C            /*  SPORT0 Half SPORT A's Status */
+#define REG_SPORT0_NUMTRAN_A                 0x40038010            /*  SPORT0 Half SPORT A Number of Transfers */
+#define REG_SPORT0_CNVT_A                    0x40038014            /*  SPORT0 Half SPORT 'A' CNV Width */
+#define REG_SPORT0_TX_A                      0x40038020            /*  SPORT0 Half SPORT 'A' Tx Buffer */
+#define REG_SPORT0_RX_A                      0x40038028            /*  SPORT0 Half SPORT 'A' Rx Buffer */
+#define REG_SPORT0_CTL_B                     0x40038040            /*  SPORT0 Half SPORT 'B' Control */
+#define REG_SPORT0_DIV_B                     0x40038044            /*  SPORT0 Half SPORT 'B' Divisor */
+#define REG_SPORT0_IEN_B                     0x40038048            /*  SPORT0 Half SPORT B's Interrupt Enable */
+#define REG_SPORT0_STAT_B                    0x4003804C            /*  SPORT0 Half SPORT B's Status */
+#define REG_SPORT0_NUMTRAN_B                 0x40038050            /*  SPORT0 Half SPORT B Number of Transfers */
+#define REG_SPORT0_CNVT_B                    0x40038054            /*  SPORT0 Half SPORT 'B' CNV Width */
+#define REG_SPORT0_TX_B                      0x40038060            /*  SPORT0 Half SPORT 'B' Tx Buffer */
+#define REG_SPORT0_RX_B                      0x40038068            /*  SPORT0 Half SPORT 'B' Rx Buffer */
+
+/* ============================================================================================================================
+        SPORT Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_CTL_A                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_CTL_A_DMAEN               26            /*  DMA Enable */
+#define BITP_SPORT_CTL_A_SPTRAN              25            /*  Serial Port Transfer Direction */
+#define BITP_SPORT_CTL_A_GCLKEN              21            /*  Gated Clock Enable */
+#define BITP_SPORT_CTL_A_FSERRMODE           20            /*  Frame Sync Error Operation */
+#define BITP_SPORT_CTL_A_PACK                18            /*  Packing Enable */
+#define BITP_SPORT_CTL_A_LAFS                17            /*  Late Frame Sync */
+#define BITP_SPORT_CTL_A_LFS                 16            /*  Active-Low Frame Sync */
+#define BITP_SPORT_CTL_A_DIFS                15            /*  Data-Independent Frame Sync */
+#define BITP_SPORT_CTL_A_IFS                 14            /*  Internal Frame Sync */
+#define BITP_SPORT_CTL_A_FSR                 13            /*  Frame Sync Required */
+#define BITP_SPORT_CTL_A_CKRE                12            /*  Clock Rising Edge */
+#define BITP_SPORT_CTL_A_OPMODE              11            /*  Operation Mode */
+#define BITP_SPORT_CTL_A_ICLK                10            /*  Internal Clock */
+#define BITP_SPORT_CTL_A_SLEN                 4            /*  Serial Word Length */
+#define BITP_SPORT_CTL_A_LSBF                 3            /*  Least-Significant Bit First */
+#define BITP_SPORT_CTL_A_CKMUXSEL             2            /*  Clock Multiplexer Select */
+#define BITP_SPORT_CTL_A_FSMUXSEL             1            /*  Frame Sync Multiplexer Select */
+#define BITP_SPORT_CTL_A_SPEN                 0            /*  Serial Port Enable */
+#define BITM_SPORT_CTL_A_DMAEN               (_ADI_MSK_3(0x04000000,0x04000000UL, uint32_t  ))    /*  DMA Enable */
+#define BITM_SPORT_CTL_A_SPTRAN              (_ADI_MSK_3(0x02000000,0x02000000UL, uint32_t  ))    /*  Serial Port Transfer Direction */
+#define BITM_SPORT_CTL_A_GCLKEN              (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t  ))    /*  Gated Clock Enable */
+#define BITM_SPORT_CTL_A_FSERRMODE           (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t  ))    /*  Frame Sync Error Operation */
+#define BITM_SPORT_CTL_A_PACK                (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t  ))    /*  Packing Enable */
+#define BITM_SPORT_CTL_A_LAFS                (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t  ))    /*  Late Frame Sync */
+#define BITM_SPORT_CTL_A_LFS                 (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t  ))    /*  Active-Low Frame Sync */
+#define BITM_SPORT_CTL_A_DIFS                (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t  ))    /*  Data-Independent Frame Sync */
+#define BITM_SPORT_CTL_A_IFS                 (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t  ))    /*  Internal Frame Sync */
+#define BITM_SPORT_CTL_A_FSR                 (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t  ))    /*  Frame Sync Required */
+#define BITM_SPORT_CTL_A_CKRE                (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t  ))    /*  Clock Rising Edge */
+#define BITM_SPORT_CTL_A_OPMODE              (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t  ))    /*  Operation Mode */
+#define BITM_SPORT_CTL_A_ICLK                (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t  ))    /*  Internal Clock */
+#define BITM_SPORT_CTL_A_SLEN                (_ADI_MSK_3(0x000001F0,0x000001F0UL, uint32_t  ))    /*  Serial Word Length */
+#define BITM_SPORT_CTL_A_LSBF                (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Least-Significant Bit First */
+#define BITM_SPORT_CTL_A_CKMUXSEL            (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Clock Multiplexer Select */
+#define BITM_SPORT_CTL_A_FSMUXSEL            (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Frame Sync Multiplexer Select */
+#define BITM_SPORT_CTL_A_SPEN                (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Serial Port Enable */
+#define ENUM_SPORT_CTL_A_CTL_RX              (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  SPTRAN: Receive */
+#define ENUM_SPORT_CTL_A_CTL_TX              (_ADI_MSK_3(0x02000000,0x02000000UL, uint32_t  ))    /*  SPTRAN: Transmit */
+#define ENUM_SPORT_CTL_A_CTL_GCLK_DIS        (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  GCLKEN: Disable */
+#define ENUM_SPORT_CTL_A_CTL_GCLK_EN         (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t  ))    /*  GCLKEN: Enable */
+#define ENUM_SPORT_CTL_A_CTL_PACK_DIS        (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  PACK: Disable */
+#define ENUM_SPORT_CTL_A_CTL_PACK_8BIT       (_ADI_MSK_3(0x00040000,0x00040000UL, uint32_t  ))    /*  PACK: 8-bit packing enable */
+#define ENUM_SPORT_CTL_A_CTL_PACK_16BIT      (_ADI_MSK_3(0x00080000,0x00080000UL, uint32_t  ))    /*  PACK: 16-bit packing enable */
+#define ENUM_SPORT_CTL_A_CTL_PACK_RSV        (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t  ))    /*  PACK: Reserved */
+#define ENUM_SPORT_CTL_A_CTL_EARLY_FS        (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  LAFS: Early frame sync */
+#define ENUM_SPORT_CTL_A_CTL_LATE_FS         (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t  ))    /*  LAFS: Late frame sync */
+#define ENUM_SPORT_CTL_A_CTL_FS_LO           (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  LFS: Active high frame sync */
+#define ENUM_SPORT_CTL_A_CTL_FS_HI           (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t  ))    /*  LFS: Active low frame sync */
+#define ENUM_SPORT_CTL_A_CTL_DATA_DEP_FS     (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  DIFS: Data-dependent frame sync */
+#define ENUM_SPORT_CTL_A_CTL_DATA_INDP_FS    (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t  ))    /*  DIFS: Data-independent frame sync */
+#define ENUM_SPORT_CTL_A_CTL_EXTERNAL_FS     (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  IFS: External frame sync */
+#define ENUM_SPORT_CTL_A_CTL_INTERNAL_FS     (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t  ))    /*  IFS: Internal frame sync */
+#define ENUM_SPORT_CTL_A_CTL_FS_NOT_REQ      (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  FSR: No frame sync required */
+#define ENUM_SPORT_CTL_A_CTL_FS_REQ          (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t  ))    /*  FSR: Frame sync required */
+#define ENUM_SPORT_CTL_A_CTL_CLK_FALL_EDGE   (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  CKRE: Clock falling edge */
+#define ENUM_SPORT_CTL_A_CTL_CLK_RISE_EDGE   (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t  ))    /*  CKRE: Clock rising edge */
+#define ENUM_SPORT_CTL_A_CTL_SERIAL          (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  OPMODE: DSP standard */
+#define ENUM_SPORT_CTL_A_CTL_TIMER_EN_MODE   (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t  ))    /*  OPMODE: Timer_enable mode */
+#define ENUM_SPORT_CTL_A_CTL_EXTERNAL_CLK    (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  ICLK: External clock */
+#define ENUM_SPORT_CTL_A_CTL_INTERNAL_CLK    (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t  ))    /*  ICLK: Internal clock */
+#define ENUM_SPORT_CTL_A_CTL_MSB_FIRST       (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  LSBF: MSB first sent/received */
+#define ENUM_SPORT_CTL_A_CTL_LSB_FIRST       (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  LSBF: LSB first sent/received */
+#define ENUM_SPORT_CTL_A_CTL_CLK_MUX_DIS     (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  CKMUXSEL: Disable serial clock multiplexing */
+#define ENUM_SPORT_CTL_A_CTL_CLK_MUX_EN      (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  CKMUXSEL: Enable serial clock multiplexing */
+#define ENUM_SPORT_CTL_A_CTL_FS_MUX_DIS      (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  FSMUXSEL: Disable frame sync multiplexing */
+#define ENUM_SPORT_CTL_A_CTL_FS_MUX_EN       (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  FSMUXSEL: Enable frame sync multiplexing */
+#define ENUM_SPORT_CTL_A_CTL_DIS             (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  SPEN: Disable */
+#define ENUM_SPORT_CTL_A_CTL_EN              (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  SPEN: Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_DIV_A                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_DIV_A_FSDIV               16            /*  Frame Sync Divisor */
+#define BITP_SPORT_DIV_A_CLKDIV               0            /*  Clock Divisor */
+#define BITM_SPORT_DIV_A_FSDIV               (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t  ))    /*  Frame Sync Divisor */
+#define BITM_SPORT_DIV_A_CLKDIV              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t  ))    /*  Clock Divisor */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_IEN_A                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_IEN_A_SYSDATERR            4            /*  Data Error for System Writes or Reads */
+#define BITP_SPORT_IEN_A_DATA                 3            /*  Data Request Interrupt to the Core */
+#define BITP_SPORT_IEN_A_FSERRMSK             2            /*  Frame Sync Error (Interrupt) Mask */
+#define BITP_SPORT_IEN_A_DERRMSK              1            /*  Data Error (Interrupt) Mask */
+#define BITP_SPORT_IEN_A_TF                   0            /*  Transfer Finish Interrupt Enable */
+#define BITM_SPORT_IEN_A_SYSDATERR           (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  Data Error for System Writes or Reads */
+#define BITM_SPORT_IEN_A_DATA                (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Data Request Interrupt to the Core */
+#define BITM_SPORT_IEN_A_FSERRMSK            (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Frame Sync Error (Interrupt) Mask */
+#define BITM_SPORT_IEN_A_DERRMSK             (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Data Error (Interrupt) Mask */
+#define BITM_SPORT_IEN_A_TF                  (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Transfer Finish Interrupt Enable */
+#define ENUM_SPORT_IEN_A_CTL_TXFIN_DIS       (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  TF: Transfer finish Interrupt is disabled */
+#define ENUM_SPORT_IEN_A_CTL_TXFIN_EN        (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  TF: Transfer Finish Interrupt is Enabled */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_STAT_A                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_STAT_A_DXS                 8            /*  Data Transfer Buffer Status */
+#define BITP_SPORT_STAT_A_SYSDATERR           4            /*  System Data Error Status */
+#define BITP_SPORT_STAT_A_DATA                3            /*  Data Buffer Status */
+#define BITP_SPORT_STAT_A_FSERR               2            /*  Frame Sync Error Status */
+#define BITP_SPORT_STAT_A_DERR                1            /*  Data Error Status */
+#define BITP_SPORT_STAT_A_TFI                 0            /*  Transmit Finish Interrupt Status */
+#define BITM_SPORT_STAT_A_DXS                (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t  ))    /*  Data Transfer Buffer Status */
+#define BITM_SPORT_STAT_A_SYSDATERR          (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  System Data Error Status */
+#define BITM_SPORT_STAT_A_DATA               (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Data Buffer Status */
+#define BITM_SPORT_STAT_A_FSERR              (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Frame Sync Error Status */
+#define BITM_SPORT_STAT_A_DERR               (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Data Error Status */
+#define BITM_SPORT_STAT_A_TFI                (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Transmit Finish Interrupt Status */
+#define ENUM_SPORT_STAT_A_CTL_EMPTY          (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  DXS: Empty */
+#define ENUM_SPORT_STAT_A_CTL_RSV            (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t  ))    /*  DXS: Reserved */
+#define ENUM_SPORT_STAT_A_CTL_PART_FULL      (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t  ))    /*  DXS: Partially full */
+#define ENUM_SPORT_STAT_A_CTL_FULL           (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t  ))    /*  DXS: Full */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_NUMTRAN_A                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_NUMTRAN_A_VALUE            0            /*  Number of Transfers (Half SPORT A) */
+#define BITM_SPORT_NUMTRAN_A_VALUE           (_ADI_MSK_3(0x00000FFF,0x00000FFFUL, uint32_t  ))    /*  Number of Transfers (Half SPORT A) */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_CNVT_A                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_CNVT_A_CNVT2FS            16            /*  SPT_CNVT to FS Duration: Half SPORT a */
+#define BITP_SPORT_CNVT_A_POL                 8            /*  Polarity of the SPT_CNVT Signal */
+#define BITP_SPORT_CNVT_A_WID                 0            /*  SPT_CNVT Signal Width: Half SPORT a */
+#define BITM_SPORT_CNVT_A_CNVT2FS            (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t  ))    /*  SPT_CNVT to FS Duration: Half SPORT a */
+#define BITM_SPORT_CNVT_A_POL                (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t  ))    /*  Polarity of the SPT_CNVT Signal */
+#define BITM_SPORT_CNVT_A_WID                (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t  ))    /*  SPT_CNVT Signal Width: Half SPORT a */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_TX_A                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_TX_A_VALUE                 0            /*  Transmit Buffer */
+#define BITM_SPORT_TX_A_VALUE                (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Transmit Buffer */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_RX_A                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_RX_A_VALUE                 0            /*  Receive Buffer */
+#define BITM_SPORT_RX_A_VALUE                (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Receive Buffer */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_CTL_B                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_CTL_B_DMAEN               26            /*  DMA Enable */
+#define BITP_SPORT_CTL_B_SPTRAN              25            /*  Serial Port Transfer Direction */
+#define BITP_SPORT_CTL_B_GCLKEN              21            /*  Gated Clock Enable */
+#define BITP_SPORT_CTL_B_FSERRMODE           20            /*  Frame Sync Error Operation */
+#define BITP_SPORT_CTL_B_PACK                18            /*  Packing Enable */
+#define BITP_SPORT_CTL_B_LAFS                17            /*  Late Frame Sync */
+#define BITP_SPORT_CTL_B_LFS                 16            /*  Active-Low Frame Sync */
+#define BITP_SPORT_CTL_B_DIFS                15            /*  Data-Independent Frame Sync */
+#define BITP_SPORT_CTL_B_IFS                 14            /*  Internal Frame Sync */
+#define BITP_SPORT_CTL_B_FSR                 13            /*  Frame Sync Required */
+#define BITP_SPORT_CTL_B_CKRE                12            /*  Clock Rising Edge */
+#define BITP_SPORT_CTL_B_OPMODE              11            /*  Operation Mode */
+#define BITP_SPORT_CTL_B_ICLK                10            /*  Internal Clock */
+#define BITP_SPORT_CTL_B_SLEN                 4            /*  Serial Word Length */
+#define BITP_SPORT_CTL_B_LSBF                 3            /*  Least-Significant Bit First */
+#define BITP_SPORT_CTL_B_SPEN                 0            /*  Serial Port Enable */
+#define BITM_SPORT_CTL_B_DMAEN               (_ADI_MSK_3(0x04000000,0x04000000UL, uint32_t  ))    /*  DMA Enable */
+#define BITM_SPORT_CTL_B_SPTRAN              (_ADI_MSK_3(0x02000000,0x02000000UL, uint32_t  ))    /*  Serial Port Transfer Direction */
+#define BITM_SPORT_CTL_B_GCLKEN              (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t  ))    /*  Gated Clock Enable */
+#define BITM_SPORT_CTL_B_FSERRMODE           (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t  ))    /*  Frame Sync Error Operation */
+#define BITM_SPORT_CTL_B_PACK                (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t  ))    /*  Packing Enable */
+#define BITM_SPORT_CTL_B_LAFS                (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t  ))    /*  Late Frame Sync */
+#define BITM_SPORT_CTL_B_LFS                 (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t  ))    /*  Active-Low Frame Sync */
+#define BITM_SPORT_CTL_B_DIFS                (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t  ))    /*  Data-Independent Frame Sync */
+#define BITM_SPORT_CTL_B_IFS                 (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t  ))    /*  Internal Frame Sync */
+#define BITM_SPORT_CTL_B_FSR                 (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t  ))    /*  Frame Sync Required */
+#define BITM_SPORT_CTL_B_CKRE                (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t  ))    /*  Clock Rising Edge */
+#define BITM_SPORT_CTL_B_OPMODE              (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t  ))    /*  Operation Mode */
+#define BITM_SPORT_CTL_B_ICLK                (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t  ))    /*  Internal Clock */
+#define BITM_SPORT_CTL_B_SLEN                (_ADI_MSK_3(0x000001F0,0x000001F0UL, uint32_t  ))    /*  Serial Word Length */
+#define BITM_SPORT_CTL_B_LSBF                (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Least-Significant Bit First */
+#define BITM_SPORT_CTL_B_SPEN                (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Serial Port Enable */
+#define ENUM_SPORT_CTL_B_CTL_PACK_DIS        (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  PACK: Disable */
+#define ENUM_SPORT_CTL_B_CTL_PACK_8BIT       (_ADI_MSK_3(0x00040000,0x00040000UL, uint32_t  ))    /*  PACK: 8-bit packing enable */
+#define ENUM_SPORT_CTL_B_CTL_PACK_16BIT      (_ADI_MSK_3(0x00080000,0x00080000UL, uint32_t  ))    /*  PACK: 16-bit packing enable */
+#define ENUM_SPORT_CTL_B_CTL_PACK_RSV        (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t  ))    /*  PACK: Reserved */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_DIV_B                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_DIV_B_FSDIV               16            /*  Frame Sync Divisor */
+#define BITP_SPORT_DIV_B_CLKDIV               0            /*  Clock Divisor */
+#define BITM_SPORT_DIV_B_FSDIV               (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t  ))    /*  Frame Sync Divisor */
+#define BITM_SPORT_DIV_B_CLKDIV              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t  ))    /*  Clock Divisor */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_IEN_B                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_IEN_B_SYSDATERR            4            /*  Data Error for System Writes or Reads */
+#define BITP_SPORT_IEN_B_DATA                 3            /*  Data Request Interrupt to the Core */
+#define BITP_SPORT_IEN_B_FSERRMSK             2            /*  Frame Sync Error (Interrupt) Mask */
+#define BITP_SPORT_IEN_B_DERRMSK              1            /*  Data Error (Interrupt) Mask */
+#define BITP_SPORT_IEN_B_TF                   0            /*  Transmit Finish Interrupt Enable */
+#define BITM_SPORT_IEN_B_SYSDATERR           (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  Data Error for System Writes or Reads */
+#define BITM_SPORT_IEN_B_DATA                (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Data Request Interrupt to the Core */
+#define BITM_SPORT_IEN_B_FSERRMSK            (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Frame Sync Error (Interrupt) Mask */
+#define BITM_SPORT_IEN_B_DERRMSK             (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Data Error (Interrupt) Mask */
+#define BITM_SPORT_IEN_B_TF                  (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Transmit Finish Interrupt Enable */
+#define ENUM_SPORT_IEN_B_CTL_TXFIN_DIS       (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  TF: Transfer Finish Interrupt is disabled */
+#define ENUM_SPORT_IEN_B_CTL_TXFIN_EN        (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  TF: Transfer Finish Interrupt is Enabled */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_STAT_B                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_STAT_B_DXS                 8            /*  Data Transfer Buffer Status */
+#define BITP_SPORT_STAT_B_SYSDATERR           4            /*  System Data Error Status */
+#define BITP_SPORT_STAT_B_DATA                3            /*  Data Buffer Status */
+#define BITP_SPORT_STAT_B_FSERR               2            /*  Frame Sync Error Status */
+#define BITP_SPORT_STAT_B_DERR                1            /*  Data Error Status */
+#define BITP_SPORT_STAT_B_TFI                 0            /*  Transmit Finish Interrupt Status */
+#define BITM_SPORT_STAT_B_DXS                (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t  ))    /*  Data Transfer Buffer Status */
+#define BITM_SPORT_STAT_B_SYSDATERR          (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  System Data Error Status */
+#define BITM_SPORT_STAT_B_DATA               (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Data Buffer Status */
+#define BITM_SPORT_STAT_B_FSERR              (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Frame Sync Error Status */
+#define BITM_SPORT_STAT_B_DERR               (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Data Error Status */
+#define BITM_SPORT_STAT_B_TFI                (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Transmit Finish Interrupt Status */
+#define ENUM_SPORT_STAT_B_CTL_EMPTY          (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  DXS: Empty */
+#define ENUM_SPORT_STAT_B_CTL_RSV            (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t  ))    /*  DXS: Reserved */
+#define ENUM_SPORT_STAT_B_CTL_PART_FULL      (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t  ))    /*  DXS: Partially full */
+#define ENUM_SPORT_STAT_B_CTL_FULL           (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t  ))    /*  DXS: Full */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_NUMTRAN_B                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_NUMTRAN_B_VALUE            0            /*  Number of Transfers (Half SPORT A) */
+#define BITM_SPORT_NUMTRAN_B_VALUE           (_ADI_MSK_3(0x00000FFF,0x00000FFFUL, uint32_t  ))    /*  Number of Transfers (Half SPORT A) */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_CNVT_B                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_CNVT_B_CNVT2FS            16            /*  SPT_CNVT to FS Duration: Half SPORT B */
+#define BITP_SPORT_CNVT_B_POL                 8            /*  Polarity of the SPT_CNVT Signal */
+#define BITP_SPORT_CNVT_B_WID                 0            /*  SPT_CNVT Signal Width: Half SPORT B */
+#define BITM_SPORT_CNVT_B_CNVT2FS            (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t  ))    /*  SPT_CNVT to FS Duration: Half SPORT B */
+#define BITM_SPORT_CNVT_B_POL                (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t  ))    /*  Polarity of the SPT_CNVT Signal */
+#define BITM_SPORT_CNVT_B_WID                (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t  ))    /*  SPT_CNVT Signal Width: Half SPORT B */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_TX_B                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_TX_B_VALUE                 0            /*  Transmit Buffer */
+#define BITM_SPORT_TX_B_VALUE                (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Transmit Buffer */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_RX_B                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_RX_B_VALUE                 0            /*  Receive Buffer */
+#define BITM_SPORT_RX_B_VALUE                (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Receive Buffer */
+
+
+/* ============================================================================================================================
+        CRC Accelerator
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        CRC0
+   ============================================================================================================================ */
+#define REG_CRC0_CTL                         0x40040000            /*  CRC0 CRC Control */
+#define REG_CRC0_IPDATA                      0x40040004            /*  CRC0 Input Data Word */
+#define REG_CRC0_RESULT                      0x40040008            /*  CRC0 CRC Result */
+#define REG_CRC0_POLY                        0x4004000C            /*  CRC0 Programmable CRC Polynomial */
+#define REG_CRC0_IPBITS0                     0x40040010            /*  CRC0 Input Data Bits */
+#define REG_CRC0_IPBITS1                     0x40040011            /*  CRC0 Input Data Bits */
+#define REG_CRC0_IPBITS2                     0x40040012            /*  CRC0 Input Data Bits */
+#define REG_CRC0_IPBITS3                     0x40040013            /*  CRC0 Input Data Bits */
+#define REG_CRC0_IPBITS4                     0x40040014            /*  CRC0 Input Data Bits */
+#define REG_CRC0_IPBITS5                     0x40040015            /*  CRC0 Input Data Bits */
+#define REG_CRC0_IPBITS6                     0x40040016            /*  CRC0 Input Data Bits */
+#define REG_CRC0_IPBITS7                     0x40040017            /*  CRC0 Input Data Bits */
+#define REG_CRC0_IPBITSn(i)                  (REG_CRC0_IPBITS0 + ((i) * 1))
+#define REG_CRC0_IPBITSn_COUNT               8
+#define REG_CRC0_IPBYTE                      0x40040010            /*  CRC0 Input Data Byte */
+
+/* ============================================================================================================================
+        CRC Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRC_CTL                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRC_CTL_REVID                   28            /*  Revision ID */
+#define BITP_CRC_CTL_W16SWP                   4            /*  Word16 Swap */
+#define BITP_CRC_CTL_BYTMIRR                  3            /*  Byte Mirroring */
+#define BITP_CRC_CTL_BITMIRR                  2            /*  Bit Mirroring */
+#define BITP_CRC_CTL_LSBFIRST                 1            /*  LSB First Calculation Order */
+#define BITP_CRC_CTL_EN                       0            /*  CRC Peripheral Enable */
+#define BITM_CRC_CTL_REVID                   (_ADI_MSK_3(0xF0000000,0xF0000000UL, uint32_t  ))    /*  Revision ID */
+#define BITM_CRC_CTL_W16SWP                  (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  Word16 Swap */
+#define BITM_CRC_CTL_BYTMIRR                 (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Byte Mirroring */
+#define BITM_CRC_CTL_BITMIRR                 (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Bit Mirroring */
+#define BITM_CRC_CTL_LSBFIRST                (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  LSB First Calculation Order */
+#define BITM_CRC_CTL_EN                      (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  CRC Peripheral Enable */
+#define ENUM_CRC_CTL_W16SP_DIS               (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  W16SWP: Word16 Swap disabled */
+#define ENUM_CRC_CTL_W16SP_EN                (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  W16SWP: Word16 Swap enabled */
+#define ENUM_CRC_CTL_BYTEMIR_DIS             (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  BYTMIRR: Byte Mirroring is disabled */
+#define ENUM_CRC_CTL_BYTEMIR_EN              (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  BYTMIRR: Byte Mirroring is enabled */
+#define ENUM_CRC_CTL_BITMIRR_DIS             (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  BITMIRR: Bit Mirroring is disabled */
+#define ENUM_CRC_CTL_BITMIRR_EN              (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  BITMIRR: Bit Mirroring is enabled */
+#define ENUM_CRC_CTL_MSB_FIRST               (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  LSBFIRST: MSB First CRC calculation is done */
+#define ENUM_CRC_CTL_LSB_FIRST               (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  LSBFIRST: LSB First CRC calculation is done */
+#define ENUM_CRC_CTL_CRC_DIS                 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  EN: CRC peripheral is disabled */
+#define ENUM_CRC_CTL_CRC_EN                  (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  EN: CRC peripheral is enabled */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRC_IPDATA                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRC_IPDATA_VALUE                 0            /*  Data Input */
+#define BITM_CRC_IPDATA_VALUE                (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Data Input */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRC_RESULT                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRC_RESULT_VALUE                 0            /*  CRC Residue */
+#define BITM_CRC_RESULT_VALUE                (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  CRC Residue */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRC_POLY                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRC_POLY_VALUE                   0            /*  CRC Reduction Polynomial */
+#define BITM_CRC_POLY_VALUE                  (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  CRC Reduction Polynomial */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRC_IPBITS[n]                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRC_IPBITS_DATA_BITS             0            /*  Input Data Bits */
+#define BITM_CRC_IPBITS_DATA_BITS            (_ADI_MSK_3(0x000000FF,0x000000FFU, uint8_t   ))    /*  Input Data Bits */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRC_IPBYTE                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRC_IPBYTE_DATA_BYTE             0            /*  Input Data Byte */
+#define BITM_CRC_IPBYTE_DATA_BYTE            (_ADI_MSK_3(0x000000FF,0x000000FFU, uint8_t   ))    /*  Input Data Byte */
+
+
+/* ============================================================================================================================
+        Random Number Generator
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        RNG0
+   ============================================================================================================================ */
+#define REG_RNG0_CTL                         0x40040400            /*  RNG0 RNG Control Register */
+#define REG_RNG0_LEN                         0x40040404            /*  RNG0 RNG Sample Length Register */
+#define REG_RNG0_STAT                        0x40040408            /*  RNG0 RNG Status Register */
+#define REG_RNG0_DATA                        0x4004040C            /*  RNG0 RNG Data Register */
+#define REG_RNG0_OSCCNT                      0x40040410            /*  RNG0 Oscillator Count */
+#define REG_RNG0_OSCDIFF0                    0x40040414            /*  RNG0 Oscillator Difference */
+#define REG_RNG0_OSCDIFF1                    0x40040415            /*  RNG0 Oscillator Difference */
+#define REG_RNG0_OSCDIFF2                    0x40040416            /*  RNG0 Oscillator Difference */
+#define REG_RNG0_OSCDIFF3                    0x40040417            /*  RNG0 Oscillator Difference */
+#define REG_RNG0_OSCDIFFn(i)                 (REG_RNG0_OSCDIFF0 + ((i) * 1))
+#define REG_RNG0_OSCDIFFn_COUNT              4
+
+/* ============================================================================================================================
+        RNG Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          RNG_CTL                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RNG_CTL_SINGLE                   3            /*  Generate a Single Number */
+#define BITP_RNG_CTL_EN                       0            /*  RNG Enable */
+#define BITM_RNG_CTL_SINGLE                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Generate a Single Number */
+#define BITM_RNG_CTL_EN                      (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  RNG Enable */
+#define ENUM_RNG_CTL_WORD                    (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  SINGLE: Buffer Word */
+#define ENUM_RNG_CTL_SINGLE                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  SINGLE: Single Byte */
+#define ENUM_RNG_CTL_DISABLE                 (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  EN: Disable the RNG */
+#define ENUM_RNG_CTL_ENABLE                  (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  EN: Enable the RNG */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RNG_LEN                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RNG_LEN_PRESCALE                12            /*  Prescaler for the Sample Counter */
+#define BITP_RNG_LEN_RELOAD                   0            /*  Reload Value for the Sample Counter */
+#define BITM_RNG_LEN_PRESCALE                (_ADI_MSK_3(0x0000F000,0x0000F000U, uint16_t  ))    /*  Prescaler for the Sample Counter */
+#define BITM_RNG_LEN_RELOAD                  (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t  ))    /*  Reload Value for the Sample Counter */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RNG_STAT                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RNG_STAT_STUCK                   1            /*  Sampled Data Stuck High or Low */
+#define BITP_RNG_STAT_RNRDY                   0            /*  Random Number Ready */
+#define BITM_RNG_STAT_STUCK                  (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Sampled Data Stuck High or Low */
+#define BITM_RNG_STAT_RNRDY                  (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Random Number Ready */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RNG_DATA                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RNG_DATA_BUFF                    8            /*  Buffer for RNG Data */
+#define BITP_RNG_DATA_VALUE                   0            /*  Value of the CRC Accumulator */
+#define BITM_RNG_DATA_BUFF                   (_ADI_MSK_3(0xFFFFFF00,0xFFFFFF00UL, uint32_t  ))    /*  Buffer for RNG Data */
+#define BITM_RNG_DATA_VALUE                  (_ADI_MSK_3(0x000000FF,0x000000FFUL, uint32_t  ))    /*  Value of the CRC Accumulator */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RNG_OSCCNT                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RNG_OSCCNT_VALUE                 0            /*  Oscillator Count */
+#define BITM_RNG_OSCCNT_VALUE                (_ADI_MSK_3(0x0FFFFFFF,0x0FFFFFFFUL, uint32_t  ))    /*  Oscillator Count */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RNG_OSCDIFF[n]                       Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RNG_OSCDIFF_DELTA                0            /*  Oscillator Count Difference */
+#define BITM_RNG_OSCDIFF_DELTA               (_ADI_MSK_3(0x000000FF,0x000000FF, int8_t    ))    /*  Oscillator Count Difference */
+
+
+/* ============================================================================================================================
+        Register Map for the Crypto Block
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        CRYPT0
+   ============================================================================================================================ */
+#define REG_CRYPT0_CFG                       0x40044000            /*  CRYPT0 Configuration Register */
+#define REG_CRYPT0_DATALEN                   0x40044004            /*  CRYPT0 Payload Data Length */
+#define REG_CRYPT0_PREFIXLEN                 0x40044008            /*  CRYPT0 Authentication Data Length */
+#define REG_CRYPT0_INTEN                     0x4004400C            /*  CRYPT0 Interrupt Enable Register */
+#define REG_CRYPT0_STAT                      0x40044010            /*  CRYPT0 Status Register */
+#define REG_CRYPT0_INBUF                     0x40044014            /*  CRYPT0 Input Buffer */
+#define REG_CRYPT0_OUTBUF                    0x40044018            /*  CRYPT0 Output Buffer */
+#define REG_CRYPT0_NONCE0                    0x4004401C            /*  CRYPT0 Nonce Bits [31:0] */
+#define REG_CRYPT0_NONCE1                    0x40044020            /*  CRYPT0 Nonce Bits [63:32] */
+#define REG_CRYPT0_NONCE2                    0x40044024            /*  CRYPT0 Nonce Bits [95:64] */
+#define REG_CRYPT0_NONCE3                    0x40044028            /*  CRYPT0 Nonce Bits [127:96] */
+#define REG_CRYPT0_AESKEY0                   0x4004402C            /*  CRYPT0 AES Key Bits [31:0] */
+#define REG_CRYPT0_AESKEY1                   0x40044030            /*  CRYPT0 AES Key Bits [63:32] */
+#define REG_CRYPT0_AESKEY2                   0x40044034            /*  CRYPT0 AES Key Bits [95:64] */
+#define REG_CRYPT0_AESKEY3                   0x40044038            /*  CRYPT0 AES Key Bits [127:96] */
+#define REG_CRYPT0_AESKEY4                   0x4004403C            /*  CRYPT0 AES Key Bits [159:128] */
+#define REG_CRYPT0_AESKEY5                   0x40044040            /*  CRYPT0 AES Key Bits [191:160] */
+#define REG_CRYPT0_AESKEY6                   0x40044044            /*  CRYPT0 AES Key Bits [223:192] */
+#define REG_CRYPT0_AESKEY7                   0x40044048            /*  CRYPT0 AES Key Bits [255:224] */
+#define REG_CRYPT0_CNTRINIT                  0x4004404C            /*  CRYPT0 Counter Initialization Vector */
+#define REG_CRYPT0_SHAH0                     0x40044050            /*  CRYPT0 SHA Bits [31:0] */
+#define REG_CRYPT0_SHAH1                     0x40044054            /*  CRYPT0 SHA Bits [63:32] */
+#define REG_CRYPT0_SHAH2                     0x40044058            /*  CRYPT0 SHA Bits [95:64] */
+#define REG_CRYPT0_SHAH3                     0x4004405C            /*  CRYPT0 SHA Bits [127:96] */
+#define REG_CRYPT0_SHAH4                     0x40044060            /*  CRYPT0 SHA Bits [159:128] */
+#define REG_CRYPT0_SHAH5                     0x40044064            /*  CRYPT0 SHA Bits [191:160] */
+#define REG_CRYPT0_SHAH6                     0x40044068            /*  CRYPT0 SHA Bits [223:192] */
+#define REG_CRYPT0_SHAH7                     0x4004406C            /*  CRYPT0 SHA Bits [255:224] */
+#define REG_CRYPT0_SHA_LAST_WORD             0x40044070            /*  CRYPT0 SHA Last Word and Valid Bits Information */
+#define REG_CRYPT0_CCM_NUM_VALID_BYTES       0x40044074            /*  CRYPT0 NUM_VALID_BYTES */
+
+/* ============================================================================================================================
+        CRYPT Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_CFG                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_CFG_REVID                 28            /*  Rev ID for Crypto */
+#define BITP_CRYPT_CFG_SHAINIT               26            /*  Restarts SHA Computation */
+#define BITP_CRYPT_CFG_SHA256EN              25            /*  Enable SHA-256 Operation */
+#define BITP_CRYPT_CFG_CMACEN                20            /*  Enable CMAC Mode Operation */
+#define BITP_CRYPT_CFG_CCMEN                 19            /*  Enable CCM/CCM* Mode Operation */
+#define BITP_CRYPT_CFG_CBCEN                 18            /*  Enable CBC Mode Operation */
+#define BITP_CRYPT_CFG_CTREN                 17            /*  Enable CTR Mode Operation */
+#define BITP_CRYPT_CFG_ECBEN                 16            /*  Enable ECB Mode Operation */
+#define BITP_CRYPT_CFG_AESKEYLEN              8            /*  Select Key Length for AES Cipher */
+#define BITP_CRYPT_CFG_AES_BYTESWAP           6            /*  Byte Swap 32 Bit AES Input Data */
+#define BITP_CRYPT_CFG_OUTFLUSH               5            /*  Output Buffer Flush */
+#define BITP_CRYPT_CFG_INFLUSH                4            /*  Input Buffer Flush */
+#define BITP_CRYPT_CFG_OUTDMAEN               3            /*  Enable DMA Channel Request for Output Buffer */
+#define BITP_CRYPT_CFG_INDMAEN                2            /*  Enable DMA Channel Request for Input Buffer */
+#define BITP_CRYPT_CFG_ENCR                   1            /*  Encrypt or Decrypt */
+#define BITP_CRYPT_CFG_BLKEN                  0            /*  Enable Bit for Crypto Block */
+#define BITM_CRYPT_CFG_REVID                 (_ADI_MSK_3(0xF0000000,0xF0000000UL, uint32_t  ))    /*  Rev ID for Crypto */
+#define BITM_CRYPT_CFG_SHAINIT               (_ADI_MSK_3(0x04000000,0x04000000UL, uint32_t  ))    /*  Restarts SHA Computation */
+#define BITM_CRYPT_CFG_SHA256EN              (_ADI_MSK_3(0x02000000,0x02000000UL, uint32_t  ))    /*  Enable SHA-256 Operation */
+#define BITM_CRYPT_CFG_CMACEN                (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t  ))    /*  Enable CMAC Mode Operation */
+#define BITM_CRYPT_CFG_CCMEN                 (_ADI_MSK_3(0x00080000,0x00080000UL, uint32_t  ))    /*  Enable CCM/CCM* Mode Operation */
+#define BITM_CRYPT_CFG_CBCEN                 (_ADI_MSK_3(0x00040000,0x00040000UL, uint32_t  ))    /*  Enable CBC Mode Operation */
+#define BITM_CRYPT_CFG_CTREN                 (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t  ))    /*  Enable CTR Mode Operation */
+#define BITM_CRYPT_CFG_ECBEN                 (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t  ))    /*  Enable ECB Mode Operation */
+#define BITM_CRYPT_CFG_AESKEYLEN             (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t  ))    /*  Select Key Length for AES Cipher */
+#define BITM_CRYPT_CFG_AES_BYTESWAP          (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t  ))    /*  Byte Swap 32 Bit AES Input Data */
+#define BITM_CRYPT_CFG_OUTFLUSH              (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  Output Buffer Flush */
+#define BITM_CRYPT_CFG_INFLUSH               (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  Input Buffer Flush */
+#define BITM_CRYPT_CFG_OUTDMAEN              (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Enable DMA Channel Request for Output Buffer */
+#define BITM_CRYPT_CFG_INDMAEN               (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Enable DMA Channel Request for Input Buffer */
+#define BITM_CRYPT_CFG_ENCR                  (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Encrypt or Decrypt */
+#define BITM_CRYPT_CFG_BLKEN                 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Enable Bit for Crypto Block */
+#define ENUM_CRYPT_CFG_AESKEYLEN128          (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  AESKEYLEN: Uses 128-bit long key */
+#define ENUM_CRYPT_CFG_AESKEYLEN256          (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t  ))    /*  AESKEYLEN: Uses 256-bit long key */
+#define ENUM_CRYPT_CFG_DMA_DISABLE_OUTBUF    (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  OUTDMAEN: Disable DMA Requesting for Output Buffer */
+#define ENUM_CRYPT_CFG_DMA_ENABLE_OUTBUF     (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  OUTDMAEN: Enable DMA Requesting for Output Buffer */
+#define ENUM_CRYPT_CFG_DMA_DISABLE_INBUF     (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  INDMAEN: Disable DMA Requesting for Input Buffer */
+#define ENUM_CRYPT_CFG_DMA_ENABLE_INBUF      (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  INDMAEN: Enable DMA Requesting for Input Buffer */
+#define ENUM_CRYPT_CFG_ENABLE                (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  BLKEN: Enable Crypto Block */
+#define ENUM_CRYPT_CFG_DISABLE               (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  BLKEN: Disable Crypto Block */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_DATALEN                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_DATALEN_VALUE              0            /*  Length of Payload Data */
+#define BITM_CRYPT_DATALEN_VALUE             (_ADI_MSK_3(0x000FFFFF,0x000FFFFFUL, uint32_t  ))    /*  Length of Payload Data */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_PREFIXLEN                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_PREFIXLEN_VALUE            0            /*  Length of Associated Data */
+#define BITM_CRYPT_PREFIXLEN_VALUE           (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t  ))    /*  Length of Associated Data */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_INTEN                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_INTEN_SHADONEN             5            /*  Enable SHA_Done Interrupt */
+#define BITP_CRYPT_INTEN_INOVREN              2            /*  Enable Input Overflow Interrupt */
+#define BITP_CRYPT_INTEN_OUTRDYEN             1            /*  Enables the Output Ready Interrupt */
+#define BITP_CRYPT_INTEN_INRDYEN              0            /*  Enable Input Ready Interrupt */
+#define BITM_CRYPT_INTEN_SHADONEN            (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  Enable SHA_Done Interrupt */
+#define BITM_CRYPT_INTEN_INOVREN             (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Enable Input Overflow Interrupt */
+#define BITM_CRYPT_INTEN_OUTRDYEN            (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Enables the Output Ready Interrupt */
+#define BITM_CRYPT_INTEN_INRDYEN             (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Enable Input Ready Interrupt */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_STAT                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_STAT_OUTWORDS             10            /*  Number of Words in the Output Buffer */
+#define BITP_CRYPT_STAT_INWORDS               7            /*  Number of Words in the Input Buffer */
+#define BITP_CRYPT_STAT_SHABUSY               6            /*  SHA Busy. in Computation */
+#define BITP_CRYPT_STAT_SHADONE               5            /*  SHA Computation Complete */
+#define BITP_CRYPT_STAT_INOVR                 2            /*  Overflow in the Input Buffer */
+#define BITP_CRYPT_STAT_OUTRDY                1            /*  Output Data Ready */
+#define BITP_CRYPT_STAT_INRDY                 0            /*  Input Buffer Status */
+#define BITM_CRYPT_STAT_OUTWORDS             (_ADI_MSK_3(0x00001C00,0x00001C00UL, uint32_t  ))    /*  Number of Words in the Output Buffer */
+#define BITM_CRYPT_STAT_INWORDS              (_ADI_MSK_3(0x00000380,0x00000380UL, uint32_t  ))    /*  Number of Words in the Input Buffer */
+#define BITM_CRYPT_STAT_SHABUSY              (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t  ))    /*  SHA Busy. in Computation */
+#define BITM_CRYPT_STAT_SHADONE              (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  SHA Computation Complete */
+#define BITM_CRYPT_STAT_INOVR                (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Overflow in the Input Buffer */
+#define BITM_CRYPT_STAT_OUTRDY               (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Output Data Ready */
+#define BITM_CRYPT_STAT_INRDY                (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Input Buffer Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_INBUF                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_INBUF_VALUE                0            /*  Input Buffer */
+#define BITM_CRYPT_INBUF_VALUE               (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Input Buffer */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_OUTBUF                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_OUTBUF_VALUE               0            /*  Output Buffer */
+#define BITM_CRYPT_OUTBUF_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Output Buffer */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_NONCE0                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_NONCE0_VALUE               0            /*  Word 0: Nonce Bits [31:0] */
+#define BITM_CRYPT_NONCE0_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 0: Nonce Bits [31:0] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_NONCE1                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_NONCE1_VALUE               0            /*  Word 1: Nonce Bits [63:32] */
+#define BITM_CRYPT_NONCE1_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 1: Nonce Bits [63:32] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_NONCE2                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_NONCE2_VALUE               0            /*  Word 2: Nonce Bits [95:64] */
+#define BITM_CRYPT_NONCE2_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 2: Nonce Bits [95:64] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_NONCE3                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_NONCE3_VALUE               0            /*  Word 3: Nonce Bits [127:96] */
+#define BITM_CRYPT_NONCE3_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 3: Nonce Bits [127:96] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_AESKEY0                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_AESKEY0_VALUE              0            /*  Key: Bytes [3:0] */
+#define BITM_CRYPT_AESKEY0_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Key: Bytes [3:0] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_AESKEY1                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_AESKEY1_VALUE              0            /*  Key: Bytes [7:4] */
+#define BITM_CRYPT_AESKEY1_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Key: Bytes [7:4] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_AESKEY2                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_AESKEY2_VALUE              0            /*  Key: Bytes [11:8] */
+#define BITM_CRYPT_AESKEY2_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Key: Bytes [11:8] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_AESKEY3                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_AESKEY3_VALUE              0            /*  Key: Bytes [15:12] */
+#define BITM_CRYPT_AESKEY3_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Key: Bytes [15:12] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_AESKEY4                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_AESKEY4_VALUE              0            /*  Key: Bytes [19:16] */
+#define BITM_CRYPT_AESKEY4_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Key: Bytes [19:16] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_AESKEY5                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_AESKEY5_VALUE              0            /*  Key: Bytes [23:20] */
+#define BITM_CRYPT_AESKEY5_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Key: Bytes [23:20] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_AESKEY6                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_AESKEY6_VALUE              0            /*  Key: Bytes [27:24] */
+#define BITM_CRYPT_AESKEY6_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Key: Bytes [27:24] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_AESKEY7                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_AESKEY7_VALUE              0            /*  Key: Bytes [31:28] */
+#define BITM_CRYPT_AESKEY7_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Key: Bytes [31:28] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_CNTRINIT                       Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_CNTRINIT_VALUE             0            /*  Counter Initialization Value */
+#define BITM_CRYPT_CNTRINIT_VALUE            (_ADI_MSK_3(0x000FFFFF,0x000FFFFFUL, uint32_t  ))    /*  Counter Initialization Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_SHAH0                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_SHAH0_SHAHASH0             0            /*  Word 0: SHA Hash */
+#define BITM_CRYPT_SHAH0_SHAHASH0            (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 0: SHA Hash */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_SHAH1                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_SHAH1_SHAHASH1             0            /*  Word 1: SHA Hash */
+#define BITM_CRYPT_SHAH1_SHAHASH1            (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 1: SHA Hash */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_SHAH2                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_SHAH2_SHAHASH2             0            /*  Word 2: SHA Hash */
+#define BITM_CRYPT_SHAH2_SHAHASH2            (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 2: SHA Hash */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_SHAH3                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_SHAH3_SHAHASH3             0            /*  Word 3: SHA Hash */
+#define BITM_CRYPT_SHAH3_SHAHASH3            (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 3: SHA Hash */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_SHAH4                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_SHAH4_SHAHASH4             0            /*  Word 4: SHA Hash */
+#define BITM_CRYPT_SHAH4_SHAHASH4            (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 4: SHA Hash */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_SHAH5                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_SHAH5_SHAHASH5             0            /*  Word 5: SHA Hash */
+#define BITM_CRYPT_SHAH5_SHAHASH5            (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 5: SHA Hash */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_SHAH6                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_SHAH6_SHAHASH6             0            /*  Word 6: SHA Hash */
+#define BITM_CRYPT_SHAH6_SHAHASH6            (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 6: SHA Hash */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_SHAH7                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_SHAH7_SHAHASH7             0            /*  Word 7: SHA Hash */
+#define BITM_CRYPT_SHAH7_SHAHASH7            (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 7: SHA Hash */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_SHA_LAST_WORD                  Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_SHA_LAST_WORD_O_BITS_VALID  1            /*  Bits Valid in SHA Last Word Input */
+#define BITP_CRYPT_SHA_LAST_WORD_O_LAST_WORD  0            /*  Last SHA Input Word */
+#define BITM_CRYPT_SHA_LAST_WORD_O_BITS_VALID (_ADI_MSK_3(0x0000003E,0x0000003EUL, uint32_t  ))    /*  Bits Valid in SHA Last Word Input */
+#define BITM_CRYPT_SHA_LAST_WORD_O_LAST_WORD (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Last SHA Input Word */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_CCM_NUM_VALID_BYTES            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_CCM_NUM_VALID_BYTES_NUM_VALID_BYTES  0            /*  Number of Valid Bytes in CCM Last Data */
+#define BITM_CRYPT_CCM_NUM_VALID_BYTES_NUM_VALID_BYTES (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t  ))    /*  Number of Valid Bytes in CCM Last Data */
+
+
+/* ============================================================================================================================
+        Power Management Registers
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        PMG0
+   ============================================================================================================================ */
+#define REG_PMG0_IEN                         0x4004C000            /*  PMG0 Power Supply Monitor Interrupt Enable */
+#define REG_PMG0_PSM_STAT                    0x4004C004            /*  PMG0 Power Supply Monitor Status */
+#define REG_PMG0_PWRMOD                      0x4004C008            /*  PMG0 Power Mode Register */
+#define REG_PMG0_PWRKEY                      0x4004C00C            /*  PMG0 Key Protection for PWRMOD and SRAMRET */
+#define REG_PMG0_SHDN_STAT                   0x4004C010            /*  PMG0 Shutdown Status Register */
+#define REG_PMG0_SRAMRET                     0x4004C014            /*  PMG0 Control for Retention SRAM in Hibernate Mode */
+#define REG_PMG0_RST_STAT                    0x4004C040            /*  PMG0 Reset Status */
+#define REG_PMG0_CTL1                        0x4004C044            /*  PMG0 HP Buck Control */
+
+/* ============================================================================================================================
+        PMG Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_IEN                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_IEN_IENBAT                  10            /*  Interrupt Enable for VBAT Range */
+#define BITP_PMG_IEN_RANGEBAT                 8            /*  Battery Monitor Range */
+#define BITP_PMG_IEN_VREGOVR                  2            /*  Enable Interrupt When VREG Overvoltage: Above 1.32V */
+#define BITP_PMG_IEN_VREGUNDR                 1            /*  Enable Interrupt When VREG Undervoltage: Below 1V */
+#define BITP_PMG_IEN_VBAT                     0            /*  Enable Interrupt for VBAT */
+#define BITM_PMG_IEN_IENBAT                  (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t  ))    /*  Interrupt Enable for VBAT Range */
+#define BITM_PMG_IEN_RANGEBAT                (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t  ))    /*  Battery Monitor Range */
+#define BITM_PMG_IEN_VREGOVR                 (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Enable Interrupt When VREG Overvoltage: Above 1.32V */
+#define BITM_PMG_IEN_VREGUNDR                (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Enable Interrupt When VREG Undervoltage: Below 1V */
+#define BITM_PMG_IEN_VBAT                    (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Enable Interrupt for VBAT */
+#define ENUM_PMG_IEN_REGION1                 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  RANGEBAT: Configure to generate interrupt if VBAT > 2.75 V */
+#define ENUM_PMG_IEN_REGION2                 (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t  ))    /*  RANGEBAT: Configure to generate interrupt if VBAT between 2.75 V - 1.6 V */
+#define ENUM_PMG_IEN_REGION3                 (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t  ))    /*  RANGEBAT: Configure to generate interrupt if VBAT between 2.3 V - 1.6 V */
+#define ENUM_PMG_IEN_NA                      (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t  ))    /*  RANGEBAT: N/A */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_PSM_STAT                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_PSM_STAT_RORANGE3           15            /*  VBAT Range3 (2.3v - 1.6v) */
+#define BITP_PMG_PSM_STAT_RORANGE2           14            /*  VBAT Range2 (2.75v - 2.3v) */
+#define BITP_PMG_PSM_STAT_RORANGE1           13            /*  VBAT Range1 (> 2.75v) */
+#define BITP_PMG_PSM_STAT_RANGE3             10            /*  VBAT Range3 (2.3v - 1.6v) */
+#define BITP_PMG_PSM_STAT_RANGE2              9            /*  VBAT Range2 (2.75v - 2.3v) */
+#define BITP_PMG_PSM_STAT_RANGE1              8            /*  VBAT Range1 (> 2.75v) */
+#define BITP_PMG_PSM_STAT_WICENACK            7            /*  WIC Enable Acknowledge from Cortex */
+#define BITP_PMG_PSM_STAT_VREGOVR             2            /*  Status Bit for Alarm Indicating Overvoltage for VREG */
+#define BITP_PMG_PSM_STAT_VREGUNDR            1            /*  Status Bit for Alarm Indicating VREG is Below 1V */
+#define BITP_PMG_PSM_STAT_VBATUNDR            0            /*  Status Bit Indicating an Alarm That Battery is Below 1.8V */
+#define BITM_PMG_PSM_STAT_RORANGE3           (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t  ))    /*  VBAT Range3 (2.3v - 1.6v) */
+#define BITM_PMG_PSM_STAT_RORANGE2           (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t  ))    /*  VBAT Range2 (2.75v - 2.3v) */
+#define BITM_PMG_PSM_STAT_RORANGE1           (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t  ))    /*  VBAT Range1 (> 2.75v) */
+#define BITM_PMG_PSM_STAT_RANGE3             (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t  ))    /*  VBAT Range3 (2.3v - 1.6v) */
+#define BITM_PMG_PSM_STAT_RANGE2             (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t  ))    /*  VBAT Range2 (2.75v - 2.3v) */
+#define BITM_PMG_PSM_STAT_RANGE1             (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t  ))    /*  VBAT Range1 (> 2.75v) */
+#define BITM_PMG_PSM_STAT_WICENACK           (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t  ))    /*  WIC Enable Acknowledge from Cortex */
+#define BITM_PMG_PSM_STAT_VREGOVR            (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Status Bit for Alarm Indicating Overvoltage for VREG */
+#define BITM_PMG_PSM_STAT_VREGUNDR           (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Status Bit for Alarm Indicating VREG is Below 1V */
+#define BITM_PMG_PSM_STAT_VBATUNDR           (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Status Bit Indicating an Alarm That Battery is Below 1.8V */
+#define ENUM_PMG_PSM_STAT_BATSTAT1           (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  RORANGE1: VBAT not in the range specified */
+#define ENUM_PMG_PSM_STAT_BATSTAT0           (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t  ))    /*  RORANGE1: VBAT in the range specified */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_PWRMOD                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_PWRMOD_MONVBATN              3            /*  Monitor VBAT During Hibernate Mode. Monitors VBAT by Default */
+#define BITP_PMG_PWRMOD_MODE                  0            /*  Power Mode Bits */
+#define BITM_PMG_PWRMOD_MONVBATN             (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Monitor VBAT During Hibernate Mode. Monitors VBAT by Default */
+#define BITM_PMG_PWRMOD_MODE                 (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t  ))    /*  Power Mode Bits */
+#define ENUM_PMG_PWRMOD_VBAT_MONEN           (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  MONVBATN: VBAT monitor enabled in PMG block. */
+#define ENUM_PMG_PWRMOD_VBAT_MONDIS          (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  MONVBATN: VBAT monitor disabled in PMG block. */
+#define ENUM_PMG_PWRMOD_FLEXI                (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  MODE: Flexi Mode */
+#define ENUM_PMG_PWRMOD_HIBERNATE            (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  MODE: Hibernate Mode */
+#define ENUM_PMG_PWRMOD_SHUTDOWN             (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t  ))    /*  MODE: Shutdown Mode */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_PWRKEY                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_PWRKEY_VALUE                 0            /*  Power Control Key Register */
+#define BITM_PMG_PWRKEY_VALUE                (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t  ))    /*  Power Control Key Register */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_SHDN_STAT                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_SHDN_STAT_RTC                3            /*  Wakeup by Interrupt from RTC */
+#define BITP_PMG_SHDN_STAT_EXTINT2            2            /*  Wakeup by Interrupt from External Interrupt 2 */
+#define BITP_PMG_SHDN_STAT_EXTINT1            1            /*  Wakeup by Interrupt from External Interrupt 1 */
+#define BITP_PMG_SHDN_STAT_EXTINT0            0            /*  Wakeup by Interrupt from External Interrupt 0 */
+#define BITM_PMG_SHDN_STAT_RTC               (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Wakeup by Interrupt from RTC */
+#define BITM_PMG_SHDN_STAT_EXTINT2           (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Wakeup by Interrupt from External Interrupt 2 */
+#define BITM_PMG_SHDN_STAT_EXTINT1           (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Wakeup by Interrupt from External Interrupt 1 */
+#define BITM_PMG_SHDN_STAT_EXTINT0           (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Wakeup by Interrupt from External Interrupt 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_SRAMRET                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_SRAMRET_BNK2EN               1            /*  Enable Retention Bank 2 (16kB) */
+#define BITP_PMG_SRAMRET_BNK1EN               0            /*  Enable Retention Bank 1 (8kB) */
+#define BITM_PMG_SRAMRET_BNK2EN              (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Enable Retention Bank 2 (16kB) */
+#define BITM_PMG_SRAMRET_BNK1EN              (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Enable Retention Bank 1 (8kB) */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_RST_STAT                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_RST_STAT_PORSRC              4            /*  Power-on-Reset Source */
+#define BITP_PMG_RST_STAT_SWRST               3            /*  Software Reset */
+#define BITP_PMG_RST_STAT_WDRST               2            /*  Watchdog Time-out Reset */
+#define BITP_PMG_RST_STAT_EXTRST              1            /*  External Reset */
+#define BITP_PMG_RST_STAT_POR                 0            /*  Power-on-Reset */
+#define BITM_PMG_RST_STAT_PORSRC             (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t  ))    /*  Power-on-Reset Source */
+#define BITM_PMG_RST_STAT_SWRST              (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Software Reset */
+#define BITM_PMG_RST_STAT_WDRST              (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Watchdog Time-out Reset */
+#define BITM_PMG_RST_STAT_EXTRST             (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  External Reset */
+#define BITM_PMG_RST_STAT_POR                (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Power-on-Reset */
+#define ENUM_PMG_RST_STAT_FAILSAFE_HV        (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  PORSRC: POR triggered because VBAT drops below Fail Safe */
+#define ENUM_PMG_RST_STAT_RST_VBAT           (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  PORSRC: POR trigger because VBAT supply (VBAT < 1.7 V) */
+#define ENUM_PMG_RST_STAT_RST_VREG           (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  PORSRC: POR triggered because VDD supply (VDD < 1.08 V) */
+#define ENUM_PMG_RST_STAT_FAILSAFE_LV        (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t  ))    /*  PORSRC: POR triggered because VREG drops below Fail Safe */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_CTL1                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_CTL1_HPBUCKEN                0            /*  Enable HP Buck */
+#define BITM_PMG_CTL1_HPBUCKEN               (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Enable HP Buck */
+
+
+/* ============================================================================================================================
+        External interrupt configuration
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        XINT0
+   ============================================================================================================================ */
+#define REG_XINT0_CFG0                       0x4004C080            /*  XINT0 External Interrupt Configuration */
+#define REG_XINT0_EXT_STAT                   0x4004C084            /*  XINT0 External Wakeup Interrupt Status */
+#define REG_XINT0_CLR                        0x4004C090            /*  XINT0 External Interrupt Clear */
+#define REG_XINT0_NMICLR                     0x4004C094            /*  XINT0 Non-Maskable Interrupt Clear */
+
+/* ============================================================================================================================
+        XINT Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          XINT_CFG0                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_XINT_CFG0_UART_RX_MDE           21            /*  External Interrupt Using UART_RX Wakeup Mode Registers */
+#define BITP_XINT_CFG0_UART_RX_EN            20            /*  External Interrupt Enable Bit */
+#define BITP_XINT_CFG0_IRQ3EN                15            /*  External Interrupt 3 Enable Bit */
+#define BITP_XINT_CFG0_IRQ3MDE               12            /*  External Interrupt 3 Mode Registers */
+#define BITP_XINT_CFG0_IRQ2EN                11            /*  External Interrupt 2 Enable Bit */
+#define BITP_XINT_CFG0_IRQ2MDE                8            /*  External Interrupt 2 Mode Registers */
+#define BITP_XINT_CFG0_IRQ1EN                 7            /*  External Interrupt 1 Enable Bit */
+#define BITP_XINT_CFG0_IRQ1MDE                4            /*  External Interrupt 1 Mode Registers */
+#define BITP_XINT_CFG0_IRQ0EN                 3            /*  External Interrupt 0 Enable Bit */
+#define BITP_XINT_CFG0_IRQ0MDE                0            /*  External Interrupt 0 Mode Registers */
+#define BITM_XINT_CFG0_UART_RX_MDE           (_ADI_MSK_3(0x00E00000,0x00E00000UL, uint32_t  ))    /*  External Interrupt Using UART_RX Wakeup Mode Registers */
+#define BITM_XINT_CFG0_UART_RX_EN            (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t  ))    /*  External Interrupt Enable Bit */
+#define BITM_XINT_CFG0_IRQ3EN                (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t  ))    /*  External Interrupt 3 Enable Bit */
+#define BITM_XINT_CFG0_IRQ3MDE               (_ADI_MSK_3(0x00007000,0x00007000UL, uint32_t  ))    /*  External Interrupt 3 Mode Registers */
+#define BITM_XINT_CFG0_IRQ2EN                (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t  ))    /*  External Interrupt 2 Enable Bit */
+#define BITM_XINT_CFG0_IRQ2MDE               (_ADI_MSK_3(0x00000700,0x00000700UL, uint32_t  ))    /*  External Interrupt 2 Mode Registers */
+#define BITM_XINT_CFG0_IRQ1EN                (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t  ))    /*  External Interrupt 1 Enable Bit */
+#define BITM_XINT_CFG0_IRQ1MDE               (_ADI_MSK_3(0x00000070,0x00000070UL, uint32_t  ))    /*  External Interrupt 1 Mode Registers */
+#define BITM_XINT_CFG0_IRQ0EN                (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  External Interrupt 0 Enable Bit */
+#define BITM_XINT_CFG0_IRQ0MDE               (_ADI_MSK_3(0x00000007,0x00000007UL, uint32_t  ))    /*  External Interrupt 0 Mode Registers */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          XINT_EXT_STAT                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_XINT_EXT_STAT_STAT_UART_RXWKUP   5            /*  Interrupt Status Bit for UART RX Wakeup Interrupt */
+#define BITP_XINT_EXT_STAT_STAT_EXTINT3       3            /*  Interrupt Status Bit for External Interrupt 3 */
+#define BITP_XINT_EXT_STAT_STAT_EXTINT2       2            /*  Interrupt Status Bit for External Interrupt 2 */
+#define BITP_XINT_EXT_STAT_STAT_EXTINT1       1            /*  Interrupt Status Bit for External Interrupt 1 */
+#define BITP_XINT_EXT_STAT_STAT_EXTINT0       0            /*  Interrupt Status Bit for External Interrupt 0 */
+#define BITM_XINT_EXT_STAT_STAT_UART_RXWKUP  (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  Interrupt Status Bit for UART RX Wakeup Interrupt */
+#define BITM_XINT_EXT_STAT_STAT_EXTINT3      (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Interrupt Status Bit for External Interrupt 3 */
+#define BITM_XINT_EXT_STAT_STAT_EXTINT2      (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Interrupt Status Bit for External Interrupt 2 */
+#define BITM_XINT_EXT_STAT_STAT_EXTINT1      (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Interrupt Status Bit for External Interrupt 1 */
+#define BITM_XINT_EXT_STAT_STAT_EXTINT0      (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Interrupt Status Bit for External Interrupt 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          XINT_CLR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_XINT_CLR_UART_RX_CLR             5            /*  External Interrupt Clear for UART_RX Wakeup Interrupt */
+#define BITP_XINT_CLR_IRQ3                    3            /*  External Interrupt 3 */
+#define BITP_XINT_CLR_IRQ2                    2            /*  External Interrupt 2 */
+#define BITP_XINT_CLR_IRQ1                    1            /*  External Interrupt 1 */
+#define BITP_XINT_CLR_IRQ0                    0            /*  External Interrupt 0 */
+#define BITM_XINT_CLR_UART_RX_CLR            (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  External Interrupt Clear for UART_RX Wakeup Interrupt */
+#define BITM_XINT_CLR_IRQ3                   (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  External Interrupt 3 */
+#define BITM_XINT_CLR_IRQ2                   (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  External Interrupt 2 */
+#define BITM_XINT_CLR_IRQ1                   (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  External Interrupt 1 */
+#define BITM_XINT_CLR_IRQ0                   (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  External Interrupt 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          XINT_NMICLR                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_XINT_NMICLR_CLR                  0            /*  NMI Clear */
+#define BITM_XINT_NMICLR_CLR                 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  NMI Clear */
+
+
+/* ============================================================================================================================
+        Clocking registers
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        CLKG0_OSC
+   ============================================================================================================================ */
+#define REG_CLKG0_OSC_KEY                    0x4004C10C            /*  CLKG0_OSC Key Protection for CLKG_OSC_CTL */
+#define REG_CLKG0_OSC_CTL                    0x4004C110            /*  CLKG0_OSC Oscillator Control */
+
+/* ============================================================================================================================
+        CLKG_OSC Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          CLKG_OSC_KEY                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CLKG_OSC_KEY_VALUE               0            /*  Oscillator K */
+#define BITM_CLKG_OSC_KEY_VALUE              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t  ))    /*  Oscillator K */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CLKG_OSC_CTL                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CLKG_OSC_CTL_LFXTAL_MON_FAIL_STAT 31            /*  LFXTAL Not Stable */
+#define BITP_CLKG_OSC_CTL_HFXTALOK           11            /*  Status of HFXTAL Oscillator */
+#define BITP_CLKG_OSC_CTL_LFXTALOK           10            /*  Status of LFXTAL Oscillator */
+#define BITP_CLKG_OSC_CTL_HFOSCOK             9            /*  Status of HFOSC */
+#define BITP_CLKG_OSC_CTL_LFOSCOK             8            /*  Status of LFOSC Oscillator */
+#define BITP_CLKG_OSC_CTL_LFXTAL_MON_EN       5            /*  LFXTAL Clock Monitor and Clock Fail Interrupt Enable */
+#define BITP_CLKG_OSC_CTL_LFXTAL_BYPASS       4            /*  Low Frequency Crystal Oscillator Bypass */
+#define BITP_CLKG_OSC_CTL_HFXTALEN            3            /*  High Frequency Crystal Oscillator Enable */
+#define BITP_CLKG_OSC_CTL_LFXTALEN            2            /*  Low Frequency Crystal Oscillator Enable */
+#define BITP_CLKG_OSC_CTL_HFOSCEN             1            /*  High Frequency Internal Oscillator Enable */
+#define BITP_CLKG_OSC_CTL_LFCLKMUX            0            /*  32kHz Clock Select Mux */
+#define BITM_CLKG_OSC_CTL_LFXTAL_MON_FAIL_STAT (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t  ))    /*  LFXTAL Not Stable */
+#define BITM_CLKG_OSC_CTL_HFXTALOK           (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t  ))    /*  Status of HFXTAL Oscillator */
+#define BITM_CLKG_OSC_CTL_LFXTALOK           (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t  ))    /*  Status of LFXTAL Oscillator */
+#define BITM_CLKG_OSC_CTL_HFOSCOK            (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t  ))    /*  Status of HFOSC */
+#define BITM_CLKG_OSC_CTL_LFOSCOK            (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t  ))    /*  Status of LFOSC Oscillator */
+#define BITM_CLKG_OSC_CTL_LFXTAL_MON_EN      (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  LFXTAL Clock Monitor and Clock Fail Interrupt Enable */
+#define BITM_CLKG_OSC_CTL_LFXTAL_BYPASS      (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  Low Frequency Crystal Oscillator Bypass */
+#define BITM_CLKG_OSC_CTL_HFXTALEN           (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  High Frequency Crystal Oscillator Enable */
+#define BITM_CLKG_OSC_CTL_LFXTALEN           (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Low Frequency Crystal Oscillator Enable */
+#define BITM_CLKG_OSC_CTL_HFOSCEN            (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  High Frequency Internal Oscillator Enable */
+#define BITM_CLKG_OSC_CTL_LFCLKMUX           (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  32kHz Clock Select Mux */
+#define ENUM_CLKG_OSC_CTL_LFXTAL_RUNNING     (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  LFXTAL_MON_FAIL_STAT: LFXTAL is running fine */
+#define ENUM_CLKG_OSC_CTL_LFXTAL_NOTRUNNING  (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t  ))    /*  LFXTAL_MON_FAIL_STAT: LFXTAL is not running */
+
+
+/* ============================================================================================================================
+        Power Management Registers
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        PMG0_TST
+   ============================================================================================================================ */
+#define REG_PMG0_TST_SRAM_CTL                0x4004C260            /*  PMG0_TST Control for SRAM Parity and Instruction SRAM */
+#define REG_PMG0_TST_SRAM_INITSTAT           0x4004C264            /*  PMG0_TST Initialization Status Register */
+#define REG_PMG0_TST_CLR_LATCH_GPIOS         0x4004C268            /*  PMG0_TST Clear GPIO After Shutdown Mode */
+#define REG_PMG0_TST_SCRPAD_IMG              0x4004C26C            /*  PMG0_TST Scratch Pad Image */
+#define REG_PMG0_TST_SCRPAD_3V_RD            0x4004C270            /*  PMG0_TST Scratch Pad Saved in Battery Domain */
+
+/* ============================================================================================================================
+        PMG_TST Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_TST_SRAM_CTL                     Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_TST_SRAM_CTL_INSTREN        31            /*  Enables Instruction SRAM */
+#define BITP_PMG_TST_SRAM_CTL_PENBNK5        21            /*  Enable Parity Check SRAM Bank 5 */
+#define BITP_PMG_TST_SRAM_CTL_PENBNK4        20            /*  Enable Parity Check SRAM Bank 4 */
+#define BITP_PMG_TST_SRAM_CTL_PENBNK3        19            /*  Enable Parity Check SRAM Bank 3 */
+#define BITP_PMG_TST_SRAM_CTL_PENBNK2        18            /*  Enable Parity Check SRAM Bank 2 */
+#define BITP_PMG_TST_SRAM_CTL_PENBNK1        17            /*  Enable Parity Check SRAM Bank 1 */
+#define BITP_PMG_TST_SRAM_CTL_PENBNK0        16            /*  Enable Parity Check SRAM Bank 0 */
+#define BITP_PMG_TST_SRAM_CTL_ABTINIT        15            /*  Abort Current Initialization. Self-cleared */
+#define BITP_PMG_TST_SRAM_CTL_AUTOINIT       14            /*  Automatic Initialization on Wakeup from Hibernate Mode */
+#define BITP_PMG_TST_SRAM_CTL_STARTINIT      13            /*  Write 1 to Trigger Initialization */
+#define BITP_PMG_TST_SRAM_CTL_BNK5EN          5            /*  Enable Initialization of SRAM Bank 5 */
+#define BITP_PMG_TST_SRAM_CTL_BNK4EN          4            /*  Enable Initialization of SRAM Bank 4 */
+#define BITP_PMG_TST_SRAM_CTL_BNK3EN          3            /*  Enable Initialization of SRAM Bank 3 */
+#define BITP_PMG_TST_SRAM_CTL_BNK2EN          2            /*  Enable Initialization of SRAM Bank 2 */
+#define BITP_PMG_TST_SRAM_CTL_BNK1EN          1            /*  Enable Initialization of SRAM Bank 1 */
+#define BITP_PMG_TST_SRAM_CTL_BNK0EN          0            /*  Enable Initialization of SRAM Bank 0 */
+#define BITM_PMG_TST_SRAM_CTL_INSTREN        (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t  ))    /*  Enables Instruction SRAM */
+#define BITM_PMG_TST_SRAM_CTL_PENBNK5        (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t  ))    /*  Enable Parity Check SRAM Bank 5 */
+#define BITM_PMG_TST_SRAM_CTL_PENBNK4        (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t  ))    /*  Enable Parity Check SRAM Bank 4 */
+#define BITM_PMG_TST_SRAM_CTL_PENBNK3        (_ADI_MSK_3(0x00080000,0x00080000UL, uint32_t  ))    /*  Enable Parity Check SRAM Bank 3 */
+#define BITM_PMG_TST_SRAM_CTL_PENBNK2        (_ADI_MSK_3(0x00040000,0x00040000UL, uint32_t  ))    /*  Enable Parity Check SRAM Bank 2 */
+#define BITM_PMG_TST_SRAM_CTL_PENBNK1        (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t  ))    /*  Enable Parity Check SRAM Bank 1 */
+#define BITM_PMG_TST_SRAM_CTL_PENBNK0        (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t  ))    /*  Enable Parity Check SRAM Bank 0 */
+#define BITM_PMG_TST_SRAM_CTL_ABTINIT        (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t  ))    /*  Abort Current Initialization. Self-cleared */
+#define BITM_PMG_TST_SRAM_CTL_AUTOINIT       (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t  ))    /*  Automatic Initialization on Wakeup from Hibernate Mode */
+#define BITM_PMG_TST_SRAM_CTL_STARTINIT      (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t  ))    /*  Write 1 to Trigger Initialization */
+#define BITM_PMG_TST_SRAM_CTL_BNK5EN         (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  Enable Initialization of SRAM Bank 5 */
+#define BITM_PMG_TST_SRAM_CTL_BNK4EN         (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  Enable Initialization of SRAM Bank 4 */
+#define BITM_PMG_TST_SRAM_CTL_BNK3EN         (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Enable Initialization of SRAM Bank 3 */
+#define BITM_PMG_TST_SRAM_CTL_BNK2EN         (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Enable Initialization of SRAM Bank 2 */
+#define BITM_PMG_TST_SRAM_CTL_BNK1EN         (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Enable Initialization of SRAM Bank 1 */
+#define BITM_PMG_TST_SRAM_CTL_BNK0EN         (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Enable Initialization of SRAM Bank 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_TST_SRAM_INITSTAT                Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_TST_SRAM_INITSTAT_BNK5       5            /*  Initialization Done of SRAM Bank 5 */
+#define BITP_PMG_TST_SRAM_INITSTAT_BNK4       4            /*  Initialization Done of SRAM Bank 4 */
+#define BITP_PMG_TST_SRAM_INITSTAT_BNK3       3            /*  Initialization Done of SRAM Bank 3 */
+#define BITP_PMG_TST_SRAM_INITSTAT_BNK2       2            /*  Initialization Done of SRAM Bank 2 */
+#define BITP_PMG_TST_SRAM_INITSTAT_BNK1       1            /*  Initialization Done of SRAM Bank 1 */
+#define BITP_PMG_TST_SRAM_INITSTAT_BNK0       0            /*  Initialization Done of SRAM Bank 0 */
+#define BITM_PMG_TST_SRAM_INITSTAT_BNK5      (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  Initialization Done of SRAM Bank 5 */
+#define BITM_PMG_TST_SRAM_INITSTAT_BNK4      (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  Initialization Done of SRAM Bank 4 */
+#define BITM_PMG_TST_SRAM_INITSTAT_BNK3      (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Initialization Done of SRAM Bank 3 */
+#define BITM_PMG_TST_SRAM_INITSTAT_BNK2      (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Initialization Done of SRAM Bank 2 */
+#define BITM_PMG_TST_SRAM_INITSTAT_BNK1      (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Initialization Done of SRAM Bank 1 */
+#define BITM_PMG_TST_SRAM_INITSTAT_BNK0      (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Initialization Done of SRAM Bank 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_TST_CLR_LATCH_GPIOS              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_TST_CLR_LATCH_GPIOS_VALUE    0            /*  Clear GPIOs Latches */
+#define BITM_PMG_TST_CLR_LATCH_GPIOS_VALUE   (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Clear GPIOs Latches */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_TST_SCRPAD_IMG                   Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_TST_SCRPAD_IMG_DATA          0            /*  Scratch Image */
+#define BITM_PMG_TST_SCRPAD_IMG_DATA         (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Scratch Image */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_TST_SCRPAD_3V_RD                 Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_TST_SCRPAD_3V_RD_DATA        0            /*  Reading the Scratch Pad Stored in Shutdown Mode */
+#define BITM_PMG_TST_SCRPAD_3V_RD_DATA       (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Reading the Scratch Pad Stored in Shutdown Mode */
+
+
+/* ============================================================================================================================
+        Clocking registers
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        CLKG0_CLK
+   ============================================================================================================================ */
+#define REG_CLKG0_CLK_CTL0                   0x4004C300            /*  CLKG0_CLK Miscellaneous Clock Settings */
+#define REG_CLKG0_CLK_CTL1                   0x4004C304            /*  CLKG0_CLK Clock Dividers */
+#define REG_CLKG0_CLK_CTL3                   0x4004C30C            /*  CLKG0_CLK System PLL */
+#define REG_CLKG0_CLK_CTL5                   0x4004C314            /*  CLKG0_CLK User Clock Gating Control */
+#define REG_CLKG0_CLK_STAT0                  0x4004C318            /*  CLKG0_CLK Clocking Status */
+
+/* ============================================================================================================================
+        CLKG_CLK Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          CLKG_CLK_CTL0                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CLKG_CLK_CTL0_HFXTALIE          15            /*  High Frequency Crystal Interrupt Enable */
+#define BITP_CLKG_CLK_CTL0_LFXTALIE          14            /*  Low Frequency Crystal Interrupt Enable */
+#define BITP_CLKG_CLK_CTL0_SPLLIPSEL         11            /*  SPLL Source Select Mux */
+#define BITP_CLKG_CLK_CTL0_RCLKMUX            8            /*  Flash Reference Clock and HP Buck Source Mux */
+#define BITP_CLKG_CLK_CTL0_CLKMUX             0            /*  Clock Mux Select */
+#define BITM_CLKG_CLK_CTL0_HFXTALIE          (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t  ))    /*  High Frequency Crystal Interrupt Enable */
+#define BITM_CLKG_CLK_CTL0_LFXTALIE          (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t  ))    /*  Low Frequency Crystal Interrupt Enable */
+#define BITM_CLKG_CLK_CTL0_SPLLIPSEL         (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t  ))    /*  SPLL Source Select Mux */
+#define BITM_CLKG_CLK_CTL0_RCLKMUX           (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t  ))    /*  Flash Reference Clock and HP Buck Source Mux */
+#define BITM_CLKG_CLK_CTL0_CLKMUX            (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t  ))    /*  Clock Mux Select */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CLKG_CLK_CTL1                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CLKG_CLK_CTL1_ACLKDIVCNT        16            /*  ACLK Divide Count */
+#define BITP_CLKG_CLK_CTL1_PCLKDIVCNT         8            /*  PCLK Divide Count */
+#define BITP_CLKG_CLK_CTL1_HCLKDIVCNT         0            /*  HCLK Divide Count */
+#define BITM_CLKG_CLK_CTL1_ACLKDIVCNT        (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t  ))    /*  ACLK Divide Count */
+#define BITM_CLKG_CLK_CTL1_PCLKDIVCNT        (_ADI_MSK_3(0x00003F00,0x00003F00UL, uint32_t  ))    /*  PCLK Divide Count */
+#define BITM_CLKG_CLK_CTL1_HCLKDIVCNT        (_ADI_MSK_3(0x0000003F,0x0000003FUL, uint32_t  ))    /*  HCLK Divide Count */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CLKG_CLK_CTL3                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CLKG_CLK_CTL3_SPLLMUL2          16            /*  System PLL Multiply by 2 */
+#define BITP_CLKG_CLK_CTL3_SPLLMSEL          11            /*  System PLL M Divider */
+#define BITP_CLKG_CLK_CTL3_SPLLIE            10            /*  System PLL Interrupt Enable */
+#define BITP_CLKG_CLK_CTL3_SPLLEN             9            /*  System PLL Enable */
+#define BITP_CLKG_CLK_CTL3_SPLLDIV2           8            /*  System PLL Division by 2 */
+#define BITP_CLKG_CLK_CTL3_SPLLNSEL           0            /*  System PLL N Multiplier */
+#define BITM_CLKG_CLK_CTL3_SPLLMUL2          (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t  ))    /*  System PLL Multiply by 2 */
+#define BITM_CLKG_CLK_CTL3_SPLLMSEL          (_ADI_MSK_3(0x00007800,0x00007800UL, uint32_t  ))    /*  System PLL M Divider */
+#define BITM_CLKG_CLK_CTL3_SPLLIE            (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t  ))    /*  System PLL Interrupt Enable */
+#define BITM_CLKG_CLK_CTL3_SPLLEN            (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t  ))    /*  System PLL Enable */
+#define BITM_CLKG_CLK_CTL3_SPLLDIV2          (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t  ))    /*  System PLL Division by 2 */
+#define BITM_CLKG_CLK_CTL3_SPLLNSEL          (_ADI_MSK_3(0x0000001F,0x0000001FUL, uint32_t  ))    /*  System PLL N Multiplier */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CLKG_CLK_CTL5                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CLKG_CLK_CTL5_PERCLKOFF          5            /*  Disables All Clocks Connected to All Peripherals */
+#define BITP_CLKG_CLK_CTL5_GPIOCLKOFF         4            /*  GPIO Clock Control */
+#define BITP_CLKG_CLK_CTL5_UCLKI2COFF         3            /*  I2C Clock User Control */
+#define BITP_CLKG_CLK_CTL5_GPTCLK2OFF         2            /*  Timer 2 User Control */
+#define BITP_CLKG_CLK_CTL5_GPTCLK1OFF         1            /*  Timer 1 User Control */
+#define BITP_CLKG_CLK_CTL5_GPTCLK0OFF         0            /*  Timer 0 User Control */
+#define BITM_CLKG_CLK_CTL5_PERCLKOFF         (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  Disables All Clocks Connected to All Peripherals */
+#define BITM_CLKG_CLK_CTL5_GPIOCLKOFF        (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  GPIO Clock Control */
+#define BITM_CLKG_CLK_CTL5_UCLKI2COFF        (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  I2C Clock User Control */
+#define BITM_CLKG_CLK_CTL5_GPTCLK2OFF        (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Timer 2 User Control */
+#define BITM_CLKG_CLK_CTL5_GPTCLK1OFF        (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Timer 1 User Control */
+#define BITM_CLKG_CLK_CTL5_GPTCLK0OFF        (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Timer 0 User Control */
+#define ENUM_CLKG_CLK_CTL5_PERIPH_CLK_ACT    (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  PERCLKOFF: Clocks to all peripherals are active */
+#define ENUM_CLKG_CLK_CTL5_PERIPH_CLK_OFF    (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  PERCLKOFF: Clocks to all peripherals are gated off */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CLKG_CLK_STAT0                       Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CLKG_CLK_STAT0_HFXTALNOK        14            /*  HF Crystal Not Stable */
+#define BITP_CLKG_CLK_STAT0_HFXTALOK         13            /*  HF Crystal Stable */
+#define BITP_CLKG_CLK_STAT0_HFXTAL           12            /*  HF Crystal Status */
+#define BITP_CLKG_CLK_STAT0_LFXTALNOK        10            /*  LF Crystal Not Stable */
+#define BITP_CLKG_CLK_STAT0_LFXTALOK          9            /*  LF Crystal Stable */
+#define BITP_CLKG_CLK_STAT0_LFXTAL            8            /*  LF Crystal Status */
+#define BITP_CLKG_CLK_STAT0_SPLLUNLK          2            /*  System PLL Unlock */
+#define BITP_CLKG_CLK_STAT0_SPLLLK            1            /*  System PLL Lock */
+#define BITP_CLKG_CLK_STAT0_SPLL              0            /*  System PLL Status */
+#define BITM_CLKG_CLK_STAT0_HFXTALNOK        (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t  ))    /*  HF Crystal Not Stable */
+#define BITM_CLKG_CLK_STAT0_HFXTALOK         (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t  ))    /*  HF Crystal Stable */
+#define BITM_CLKG_CLK_STAT0_HFXTAL           (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t  ))    /*  HF Crystal Status */
+#define BITM_CLKG_CLK_STAT0_LFXTALNOK        (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t  ))    /*  LF Crystal Not Stable */
+#define BITM_CLKG_CLK_STAT0_LFXTALOK         (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t  ))    /*  LF Crystal Stable */
+#define BITM_CLKG_CLK_STAT0_LFXTAL           (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t  ))    /*  LF Crystal Status */
+#define BITM_CLKG_CLK_STAT0_SPLLUNLK         (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  System PLL Unlock */
+#define BITM_CLKG_CLK_STAT0_SPLLLK           (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  System PLL Lock */
+#define BITM_CLKG_CLK_STAT0_SPLL             (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  System PLL Status */
+
+
+/* ============================================================================================================================
+        Bus matrix
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        BUSM0
+   ============================================================================================================================ */
+#define REG_BUSM0_ARBIT0                     0x4004C800            /*  BUSM0 Arbitration Priority Configuration for FLASH and SRAM0 */
+#define REG_BUSM0_ARBIT1                     0x4004C804            /*  BUSM0 Arbitration Priority Configuration for SRAM1 and SIP */
+#define REG_BUSM0_ARBIT2                     0x4004C808            /*  BUSM0 Arbitration Priority Configuration for APB32 and APB16 */
+#define REG_BUSM0_ARBIT3                     0x4004C80C            /*  BUSM0 Arbitration Priority Configuration for APB16 priority for core and for DMA1 */
+
+/* ============================================================================================================================
+        BUSM Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          BUSM_ARBIT0                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_BUSM_ARBIT0_SRAM0_DMA0          20            /*  SRAM0 priority for DMA0 */
+#define BITP_BUSM_ARBIT0_SRAM0_SBUS          18            /*  SRAM0 priority for SBUS */
+#define BITP_BUSM_ARBIT0_SRAM0_DCODE         16            /*  SRAM0 priority for Dcode */
+#define BITP_BUSM_ARBIT0_FLSH_DMA0            4            /*  Flash priority for DMA0 */
+#define BITP_BUSM_ARBIT0_FLSH_SBUS            2            /*  Flash priority for SBUS */
+#define BITP_BUSM_ARBIT0_FLSH_DCODE           0            /*  Flash priority for DCODE */
+#define BITM_BUSM_ARBIT0_SRAM0_DMA0          (_ADI_MSK_3(0x00300000,0x00300000UL, uint32_t  ))    /*  SRAM0 priority for DMA0 */
+#define BITM_BUSM_ARBIT0_SRAM0_SBUS          (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t  ))    /*  SRAM0 priority for SBUS */
+#define BITM_BUSM_ARBIT0_SRAM0_DCODE         (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t  ))    /*  SRAM0 priority for Dcode */
+#define BITM_BUSM_ARBIT0_FLSH_DMA0           (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t  ))    /*  Flash priority for DMA0 */
+#define BITM_BUSM_ARBIT0_FLSH_SBUS           (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t  ))    /*  Flash priority for SBUS */
+#define BITM_BUSM_ARBIT0_FLSH_DCODE          (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t  ))    /*  Flash priority for DCODE */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          BUSM_ARBIT1                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_BUSM_ARBIT1_SIP_DMA0            20            /*  SIP priority for DMA0 */
+#define BITP_BUSM_ARBIT1_SIP_SBUS            18            /*  SIP priority for SBUS */
+#define BITP_BUSM_ARBIT1_SIP_DCODE           16            /*  SIP priority for DCODE */
+#define BITP_BUSM_ARBIT1_SRAM1_DMA0           4            /*  SRAM1 priority for DMA0 */
+#define BITP_BUSM_ARBIT1_SRAM1_SBUS           2            /*  SRAM1 priority for SBUS */
+#define BITP_BUSM_ARBIT1_SRAM1_DCODE          0            /*  SRAM1 priority for Dcode */
+#define BITM_BUSM_ARBIT1_SIP_DMA0            (_ADI_MSK_3(0x00300000,0x00300000UL, uint32_t  ))    /*  SIP priority for DMA0 */
+#define BITM_BUSM_ARBIT1_SIP_SBUS            (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t  ))    /*  SIP priority for SBUS */
+#define BITM_BUSM_ARBIT1_SIP_DCODE           (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t  ))    /*  SIP priority for DCODE */
+#define BITM_BUSM_ARBIT1_SRAM1_DMA0          (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t  ))    /*  SRAM1 priority for DMA0 */
+#define BITM_BUSM_ARBIT1_SRAM1_SBUS          (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t  ))    /*  SRAM1 priority for SBUS */
+#define BITM_BUSM_ARBIT1_SRAM1_DCODE         (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t  ))    /*  SRAM1 priority for Dcode */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          BUSM_ARBIT2                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_BUSM_ARBIT2_APB16_DMA0          20            /*  APB16 priority for DMA0 */
+#define BITP_BUSM_ARBIT2_APB16_SBUS          18            /*  APB16 priority for SBUS */
+#define BITP_BUSM_ARBIT2_APB16_DCODE         16            /*  APB16 priority for DCODE */
+#define BITP_BUSM_ARBIT2_APB32_DMA0           4            /*  APB32 priority for DMA0 */
+#define BITP_BUSM_ARBIT2_APB32_SBUS           2            /*  APB32 priority for SBUS */
+#define BITP_BUSM_ARBIT2_APB32_DCODE          0            /*  APB32 priority for DCODE */
+#define BITM_BUSM_ARBIT2_APB16_DMA0          (_ADI_MSK_3(0x00300000,0x00300000UL, uint32_t  ))    /*  APB16 priority for DMA0 */
+#define BITM_BUSM_ARBIT2_APB16_SBUS          (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t  ))    /*  APB16 priority for SBUS */
+#define BITM_BUSM_ARBIT2_APB16_DCODE         (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t  ))    /*  APB16 priority for DCODE */
+#define BITM_BUSM_ARBIT2_APB32_DMA0          (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t  ))    /*  APB32 priority for DMA0 */
+#define BITM_BUSM_ARBIT2_APB32_SBUS          (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t  ))    /*  APB32 priority for SBUS */
+#define BITM_BUSM_ARBIT2_APB32_DCODE         (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t  ))    /*  APB32 priority for DCODE */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          BUSM_ARBIT3                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_BUSM_ARBIT3_APB16_4DMA_DMA1     17            /*  APB16 for dma priority for DMA1 */
+#define BITP_BUSM_ARBIT3_APB16_4DMA_CORE     16            /*  APB16 for dma priority for CORE */
+#define BITP_BUSM_ARBIT3_APB16_DMA1           1            /*  APB16 priority for DMA1 */
+#define BITP_BUSM_ARBIT3_APB16_CORE           0            /*  APB16 priority for CORE */
+#define BITM_BUSM_ARBIT3_APB16_4DMA_DMA1     (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t  ))    /*  APB16 for dma priority for DMA1 */
+#define BITM_BUSM_ARBIT3_APB16_4DMA_CORE     (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t  ))    /*  APB16 for dma priority for CORE */
+#define BITM_BUSM_ARBIT3_APB16_DMA1          (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  APB16 priority for DMA1 */
+#define BITM_BUSM_ARBIT3_APB16_CORE          (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  APB16 priority for CORE */
+
+
+/* ============================================================================================================================
+        Parallel Test Interface
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        PTI0
+   ============================================================================================================================ */
+#define REG_PTI0_RST_ISR_STARTADDR           0x4004CD00            /*  PTI0 Reset ISR Start Address */
+#define REG_PTI0_RST_STACK_PTR               0x4004CD04            /*  PTI0 Reset Stack Pointer */
+#define REG_PTI0_CTL                         0x4004CD08            /*  PTI0 Parallel Test Interface Control Register */
+
+/* ============================================================================================================================
+        PTI Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          PTI_RST_ISR_STARTADDR                Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PTI_RST_ISR_STARTADDR_VALUE      0
+#define BITM_PTI_RST_ISR_STARTADDR_VALUE     (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PTI_RST_STACK_PTR                    Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PTI_RST_STACK_PTR_VALUE          0
+#define BITM_PTI_RST_STACK_PTR_VALUE         (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PTI_CTL                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PTI_CTL_EN                       0
+#define BITM_PTI_CTL_EN                      (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))
+
+
+/* ============================================================================================================================
+        Cortex-M3 Interrupt Controller
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        NVIC0
+   ============================================================================================================================ */
+#define REG_NVIC0_INTNUM                     0xE000E004            /*  NVIC0 Interrupt Control Type */
+#define REG_NVIC0_STKSTA                     0xE000E010            /*  NVIC0 Systick Control and Status */
+#define REG_NVIC0_STKLD                      0xE000E014            /*  NVIC0 Systick Reload Value */
+#define REG_NVIC0_STKVAL                     0xE000E018            /*  NVIC0 Systick Current Value */
+#define REG_NVIC0_STKCAL                     0xE000E01C            /*  NVIC0 Systick Calibration Value */
+#define REG_NVIC0_INTSETE0                   0xE000E100            /*  NVIC0 IRQ0..31 Set_Enable */
+#define REG_NVIC0_INTSETE1                   0xE000E104            /*  NVIC0 IRQ32..63 Set_Enable */
+#define REG_NVIC0_INTCLRE0                   0xE000E180            /*  NVIC0 IRQ0..31 Clear_Enable */
+#define REG_NVIC0_INTCLRE1                   0xE000E184            /*  NVIC0 IRQ32..63 Clear_Enable */
+#define REG_NVIC0_INTSETP0                   0xE000E200            /*  NVIC0 IRQ0..31 Set_Pending */
+#define REG_NVIC0_INTSETP1                   0xE000E204            /*  NVIC0 IRQ32..63 Set_Pending */
+#define REG_NVIC0_INTCLRP0                   0xE000E280            /*  NVIC0 IRQ0..31 Clear_Pending */
+#define REG_NVIC0_INTCLRP1                   0xE000E284            /*  NVIC0 IRQ32..63 Clear_Pending */
+#define REG_NVIC0_INTACT0                    0xE000E300            /*  NVIC0 IRQ0..31 Active Bit */
+#define REG_NVIC0_INTACT1                    0xE000E304            /*  NVIC0 IRQ32..63 Active Bit */
+#define REG_NVIC0_INTPRI0                    0xE000E400            /*  NVIC0 IRQ0..3 Priority */
+#define REG_NVIC0_INTPRI1                    0xE000E404            /*  NVIC0 IRQ4..7 Priority */
+#define REG_NVIC0_INTPRI2                    0xE000E408            /*  NVIC0 IRQ8..11 Priority */
+#define REG_NVIC0_INTPRI3                    0xE000E40C            /*  NVIC0 IRQ12..15 Priority */
+#define REG_NVIC0_INTPRI4                    0xE000E410            /*  NVIC0 IRQ16..19 Priority */
+#define REG_NVIC0_INTPRI5                    0xE000E414            /*  NVIC0 IRQ20..23 Priority */
+#define REG_NVIC0_INTPRI6                    0xE000E418            /*  NVIC0 IRQ24..27 Priority */
+#define REG_NVIC0_INTPRI7                    0xE000E41C            /*  NVIC0 IRQ28..31 Priority */
+#define REG_NVIC0_INTPRI8                    0xE000E420            /*  NVIC0 IRQ32..35 Priority */
+#define REG_NVIC0_INTPRI9                    0xE000E424            /*  NVIC0 IRQ36..39 Priority */
+#define REG_NVIC0_INTPRI10                   0xE000E428            /*  NVIC0 IRQ40..43 Priority */
+#define REG_NVIC0_INTCPID                    0xE000ED00            /*  NVIC0 CPUID Base */
+#define REG_NVIC0_INTSTA                     0xE000ED04            /*  NVIC0 Interrupt Control State */
+#define REG_NVIC0_INTVEC                     0xE000ED08            /*  NVIC0 Vector Table Offset */
+#define REG_NVIC0_INTAIRC                    0xE000ED0C            /*  NVIC0 Application Interrupt/Reset Control */
+#define REG_NVIC0_INTCON0                    0xE000ED10            /*  NVIC0 System Control */
+#define REG_NVIC0_INTCON1                    0xE000ED14            /*  NVIC0 Configuration Control */
+#define REG_NVIC0_INTSHPRIO0                 0xE000ED18            /*  NVIC0 System Handlers 4-7 Priority */
+#define REG_NVIC0_INTSHPRIO1                 0xE000ED1C            /*  NVIC0 System Handlers 8-11 Priority */
+#define REG_NVIC0_INTSHPRIO3                 0xE000ED20            /*  NVIC0 System Handlers 12-15 Priority */
+#define REG_NVIC0_INTSHCSR                   0xE000ED24            /*  NVIC0 System Handler Control and State */
+#define REG_NVIC0_INTCFSR                    0xE000ED28            /*  NVIC0 Configurable Fault Status */
+#define REG_NVIC0_INTHFSR                    0xE000ED2C            /*  NVIC0 Hard Fault Status */
+#define REG_NVIC0_INTDFSR                    0xE000ED30            /*  NVIC0 Debug Fault Status */
+#define REG_NVIC0_INTMMAR                    0xE000ED34            /*  NVIC0 Mem Manage Address */
+#define REG_NVIC0_INTBFAR                    0xE000ED38            /*  NVIC0 Bus Fault Address */
+#define REG_NVIC0_INTAFSR                    0xE000ED3C            /*  NVIC0 Auxiliary Fault Status */
+#define REG_NVIC0_INTPFR0                    0xE000ED40            /*  NVIC0 Processor Feature Register 0 */
+#define REG_NVIC0_INTPFR1                    0xE000ED44            /*  NVIC0 Processor Feature Register 1 */
+#define REG_NVIC0_INTDFR0                    0xE000ED48            /*  NVIC0 Debug Feature Register 0 */
+#define REG_NVIC0_INTAFR0                    0xE000ED4C            /*  NVIC0 Auxiliary Feature Register 0 */
+#define REG_NVIC0_INTMMFR0                   0xE000ED50            /*  NVIC0 Memory Model Feature Register 0 */
+#define REG_NVIC0_INTMMFR1                   0xE000ED54            /*  NVIC0 Memory Model Feature Register 1 */
+#define REG_NVIC0_INTMMFR2                   0xE000ED58            /*  NVIC0 Memory Model Feature Register 2 */
+#define REG_NVIC0_INTMMFR3                   0xE000ED5C            /*  NVIC0 Memory Model Feature Register 3 */
+#define REG_NVIC0_INTISAR0                   0xE000ED60            /*  NVIC0 ISA Feature Register 0 */
+#define REG_NVIC0_INTISAR1                   0xE000ED64            /*  NVIC0 ISA Feature Register 1 */
+#define REG_NVIC0_INTISAR2                   0xE000ED68            /*  NVIC0 ISA Feature Register 2 */
+#define REG_NVIC0_INTISAR3                   0xE000ED6C            /*  NVIC0 ISA Feature Register 3 */
+#define REG_NVIC0_INTISAR4                   0xE000ED70            /*  NVIC0 ISA Feature Register 4 */
+#define REG_NVIC0_INTTRGI                    0xE000EF00            /*  NVIC0 Software Trigger Interrupt Register */
+#define REG_NVIC0_INTPID4                    0xE000EFD0            /*  NVIC0 Peripheral Identification Register 4 */
+#define REG_NVIC0_INTPID5                    0xE000EFD4            /*  NVIC0 Peripheral Identification Register 5 */
+#define REG_NVIC0_INTPID6                    0xE000EFD8            /*  NVIC0 Peripheral Identification Register 6 */
+#define REG_NVIC0_INTPID7                    0xE000EFDC            /*  NVIC0 Peripheral Identification Register 7 */
+#define REG_NVIC0_INTPID0                    0xE000EFE0            /*  NVIC0 Peripheral Identification Bits7:0 */
+#define REG_NVIC0_INTPID1                    0xE000EFE4            /*  NVIC0 Peripheral Identification Bits15:8 */
+#define REG_NVIC0_INTPID2                    0xE000EFE8            /*  NVIC0 Peripheral Identification Bits16:23 */
+#define REG_NVIC0_INTPID3                    0xE000EFEC            /*  NVIC0 Peripheral Identification Bits24:31 */
+#define REG_NVIC0_INTCID0                    0xE000EFF0            /*  NVIC0 Component Identification Bits7:0 */
+#define REG_NVIC0_INTCID1                    0xE000EFF4            /*  NVIC0 Component Identification Bits15:8 */
+#define REG_NVIC0_INTCID2                    0xE000EFF8            /*  NVIC0 Component Identification Bits16:23 */
+#define REG_NVIC0_INTCID3                    0xE000EFFC            /*  NVIC0 Component Identification Bits24:31 */
+
+/* ============================================================================================================================
+        NVIC Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTNUM                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTNUM_VALUE                0            /*  Interrupt Control Type */
+#define BITM_NVIC_INTNUM_VALUE               (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Interrupt Control Type */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_STKSTA                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_STKSTA_VALUE                0            /*  Systick Control and Status */
+#define BITM_NVIC_STKSTA_VALUE               (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Systick Control and Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_STKLD                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_STKLD_VALUE                 0            /*  Systick Reload Value */
+#define BITM_NVIC_STKLD_VALUE                (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Systick Reload Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_STKVAL                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_STKVAL_VALUE                0            /*  Systick Current Value */
+#define BITM_NVIC_STKVAL_VALUE               (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Systick Current Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_STKCAL                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_STKCAL_VALUE                0            /*  Systick Calibration Value */
+#define BITM_NVIC_STKCAL_VALUE               (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Systick Calibration Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTSETE0                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTSETE0_VALUE              0            /*  IRQ0..31 Set_Enable */
+#define BITM_NVIC_INTSETE0_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ0..31 Set_Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTSETE1                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTSETE1_VALUE              0            /*  IRQ32..63 Set_Enable */
+#define BITM_NVIC_INTSETE1_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ32..63 Set_Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCLRE0                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCLRE0_VALUE              0            /*  IRQ0..31 Clear_Enable */
+#define BITM_NVIC_INTCLRE0_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ0..31 Clear_Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCLRE1                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCLRE1_VALUE              0            /*  IRQ32..63 Clear_Enable */
+#define BITM_NVIC_INTCLRE1_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ32..63 Clear_Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTSETP0                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTSETP0_VALUE              0            /*  IRQ0..31 Set_Pending */
+#define BITM_NVIC_INTSETP0_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ0..31 Set_Pending */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTSETP1                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTSETP1_VALUE              0            /*  IRQ32..63 Set_Pending */
+#define BITM_NVIC_INTSETP1_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ32..63 Set_Pending */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCLRP0                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCLRP0_VALUE              0            /*  IRQ0..31 Clear_Pending */
+#define BITM_NVIC_INTCLRP0_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ0..31 Clear_Pending */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCLRP1                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCLRP1_VALUE              0            /*  IRQ32..63 Clear_Pending */
+#define BITM_NVIC_INTCLRP1_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ32..63 Clear_Pending */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTACT0                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTACT0_VALUE               0            /*  IRQ0..31 Active Bit */
+#define BITM_NVIC_INTACT0_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ0..31 Active Bit */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTACT1                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTACT1_VALUE               0            /*  IRQ32..63 Active Bit */
+#define BITM_NVIC_INTACT1_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ32..63 Active Bit */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI0                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI0_VALUE               0            /*  IRQ0..3 Priority */
+#define BITM_NVIC_INTPRI0_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ0..3 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI1                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI1_VALUE               0            /*  IRQ4..7 Priority */
+#define BITM_NVIC_INTPRI1_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ4..7 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI2                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI2_VALUE               0            /*  IRQ8..11 Priority */
+#define BITM_NVIC_INTPRI2_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ8..11 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI3                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI3_VALUE               0            /*  IRQ12..15 Priority */
+#define BITM_NVIC_INTPRI3_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ12..15 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI4                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI4_VALUE               0            /*  IRQ16..19 Priority */
+#define BITM_NVIC_INTPRI4_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ16..19 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI5                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI5_VALUE               0            /*  IRQ20..23 Priority */
+#define BITM_NVIC_INTPRI5_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ20..23 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI6                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI6_VALUE               0            /*  IRQ24..27 Priority */
+#define BITM_NVIC_INTPRI6_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ24..27 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI7                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI7_VALUE               0            /*  IRQ28..31 Priority */
+#define BITM_NVIC_INTPRI7_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ28..31 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI8                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI8_VALUE               0            /*  IRQ32..35 Priority */
+#define BITM_NVIC_INTPRI8_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ32..35 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI9                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI9_VALUE               0            /*  IRQ36..39 Priority */
+#define BITM_NVIC_INTPRI9_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ36..39 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI10                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI10_VALUE              0            /*  IRQ40..43 Priority */
+#define BITM_NVIC_INTPRI10_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ40..43 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCPID                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCPID_VALUE               0            /*  CPUID Base */
+#define BITM_NVIC_INTCPID_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  CPUID Base */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTSTA                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTSTA_VALUE                0            /*  Interrupt Control State */
+#define BITM_NVIC_INTSTA_VALUE               (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Interrupt Control State */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTVEC                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTVEC_VALUE                0            /*  Vector Table Offset */
+#define BITM_NVIC_INTVEC_VALUE               (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Vector Table Offset */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTAIRC                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTAIRC_VALUE               0            /*  Application Interrupt/Reset Control */
+#define BITM_NVIC_INTAIRC_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Application Interrupt/Reset Control */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCON0                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCON0_SLEEPDEEP           2            /*  deep sleep flag for HIBERNATE mode */
+#define BITP_NVIC_INTCON0_SLEEPONEXIT         1            /*  Sleeps the core on exit from an ISR */
+#define BITM_NVIC_INTCON0_SLEEPDEEP          (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  deep sleep flag for HIBERNATE mode */
+#define BITM_NVIC_INTCON0_SLEEPONEXIT        (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Sleeps the core on exit from an ISR */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCON1                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCON1_VALUE               0            /*  Configuration Control */
+#define BITM_NVIC_INTCON1_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Configuration Control */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTSHPRIO0                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTSHPRIO0_VALUE            0            /*  System Handlers 4-7 Priority */
+#define BITM_NVIC_INTSHPRIO0_VALUE           (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  System Handlers 4-7 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTSHPRIO1                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTSHPRIO1_VALUE            0            /*  System Handlers 8-11 Priority */
+#define BITM_NVIC_INTSHPRIO1_VALUE           (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  System Handlers 8-11 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTSHPRIO3                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTSHPRIO3_VALUE            0            /*  System Handlers 12-15 Priority */
+#define BITM_NVIC_INTSHPRIO3_VALUE           (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  System Handlers 12-15 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTSHCSR                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTSHCSR_VALUE              0            /*  System Handler Control and State */
+#define BITM_NVIC_INTSHCSR_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  System Handler Control and State */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCFSR                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCFSR_VALUE               0            /*  Configurable Fault Status */
+#define BITM_NVIC_INTCFSR_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Configurable Fault Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTHFSR                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTHFSR_VALUE               0            /*  Hard Fault Status */
+#define BITM_NVIC_INTHFSR_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Hard Fault Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTDFSR                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTDFSR_VALUE               0            /*  Debug Fault Status */
+#define BITM_NVIC_INTDFSR_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Debug Fault Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTMMAR                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTMMAR_VALUE               0            /*  Mem Manage Address */
+#define BITM_NVIC_INTMMAR_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Mem Manage Address */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTBFAR                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTBFAR_VALUE               0            /*  Bus Fault Address */
+#define BITM_NVIC_INTBFAR_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Bus Fault Address */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTAFSR                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTAFSR_VALUE               0            /*  Auxiliary Fault Status */
+#define BITM_NVIC_INTAFSR_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Auxiliary Fault Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPFR0                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPFR0_VALUE               0            /*  Processor Feature Register 0 */
+#define BITM_NVIC_INTPFR0_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Processor Feature Register 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPFR1                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPFR1_VALUE               0            /*  Processor Feature Register 1 */
+#define BITM_NVIC_INTPFR1_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Processor Feature Register 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTDFR0                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTDFR0_VALUE               0            /*  Debug Feature Register 0 */
+#define BITM_NVIC_INTDFR0_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Debug Feature Register 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTAFR0                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTAFR0_VALUE               0            /*  Auxiliary Feature Register 0 */
+#define BITM_NVIC_INTAFR0_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Auxiliary Feature Register 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTMMFR0                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTMMFR0_VALUE              0            /*  Memory Model Feature Register 0 */
+#define BITM_NVIC_INTMMFR0_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Memory Model Feature Register 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTMMFR1                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTMMFR1_VALUE              0            /*  Memory Model Feature Register 1 */
+#define BITM_NVIC_INTMMFR1_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Memory Model Feature Register 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTMMFR2                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTMMFR2_VALUE              0            /*  Memory Model Feature Register 2 */
+#define BITM_NVIC_INTMMFR2_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Memory Model Feature Register 2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTMMFR3                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTMMFR3_VALUE              0            /*  Memory Model Feature Register 3 */
+#define BITM_NVIC_INTMMFR3_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Memory Model Feature Register 3 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTISAR0                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTISAR0_VALUE              0            /*  ISA Feature Register 0 */
+#define BITM_NVIC_INTISAR0_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  ISA Feature Register 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTISAR1                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTISAR1_VALUE              0            /*  ISA Feature Register 1 */
+#define BITM_NVIC_INTISAR1_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  ISA Feature Register 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTISAR2                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTISAR2_VALUE              0            /*  ISA Feature Register 2 */
+#define BITM_NVIC_INTISAR2_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  ISA Feature Register 2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTISAR3                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTISAR3_VALUE              0            /*  ISA Feature Register 3 */
+#define BITM_NVIC_INTISAR3_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  ISA Feature Register 3 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTISAR4                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTISAR4_VALUE              0            /*  ISA Feature Register 4 */
+#define BITM_NVIC_INTISAR4_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  ISA Feature Register 4 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTTRGI                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTTRGI_VALUE               0            /*  Software Trigger Interrupt Register */
+#define BITM_NVIC_INTTRGI_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Software Trigger Interrupt Register */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPID4                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPID4_VALUE               0            /*  Peripheral Identification Register 4 */
+#define BITM_NVIC_INTPID4_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Peripheral Identification Register 4 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPID5                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPID5_VALUE               0            /*  Peripheral Identification Register 5 */
+#define BITM_NVIC_INTPID5_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Peripheral Identification Register 5 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPID6                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPID6_VALUE               0            /*  Peripheral Identification Register 6 */
+#define BITM_NVIC_INTPID6_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Peripheral Identification Register 6 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPID7                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPID7_VALUE               0            /*  Peripheral Identification Register 7 */
+#define BITM_NVIC_INTPID7_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Peripheral Identification Register 7 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPID0                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPID0_VALUE               0            /*  Peripheral Identification Bits7:0 */
+#define BITM_NVIC_INTPID0_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Peripheral Identification Bits7:0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPID1                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPID1_VALUE               0            /*  Peripheral Identification Bits15:8 */
+#define BITM_NVIC_INTPID1_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Peripheral Identification Bits15:8 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPID2                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPID2_VALUE               0            /*  Peripheral Identification Bits16:23 */
+#define BITM_NVIC_INTPID2_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Peripheral Identification Bits16:23 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPID3                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPID3_VALUE               0            /*  Peripheral Identification Bits24:31 */
+#define BITM_NVIC_INTPID3_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Peripheral Identification Bits24:31 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCID0                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCID0_VALUE               0            /*  Component Identification Bits7:0 */
+#define BITM_NVIC_INTCID0_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Component Identification Bits7:0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCID1                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCID1_VALUE               0            /*  Component Identification Bits15:8 */
+#define BITM_NVIC_INTCID1_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Component Identification Bits15:8 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCID2                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCID2_VALUE               0            /*  Component Identification Bits16:23 */
+#define BITM_NVIC_INTCID2_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Component Identification Bits16:23 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCID3                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCID3_VALUE               0            /*  Component Identification Bits24:31 */
+#define BITM_NVIC_INTCID3_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Component Identification Bits24:31 */
+
+/* ====================================================================================================
+ *    Interrupt Definitions
+ * ==================================================================================================== */
+#define INTR_RESET                           (-15)		/* Cortex-M3 Reset */
+#define INTR_NonMaskableInt                  (-14)		/* Cortex-M3 Non-maskable Interrupt */
+#define INTR_HardFault                       (-13)		/* Cortex-M3 Hardware Fault */
+#define INTR_MemoryManagement                (-12)		/* Cortex-M3 Memory Management Interrupt */
+#define INTR_BusFault                        (-11)		/* Cortex-M3 Bus Fault */
+#define INTR_UsageFault                      (-10)		/* Cortex-M3 Usage Fault */
+#define INTR_SVCall                          ( -5)		/* Cortex-M3 SVCall Interrupt */
+#define INTR_DebugMonitor                    ( -4)		/* Cortex-M3 Debug Monitor */
+#define INTR_PendSV                          ( -2)		/* Cortex-M3 PendSV Interrupt */
+#define INTR_SysTick                         ( -1)		/* Cortex-M3 SysTick Interrupt */
+#define INTR_RTC1_EVT                          0		/* Event */
+#define INTR_XINT_EVT0                         1		/* External Wakeup Interrupt n */
+#define INTR_XINT_EVT1                         2		/* External Wakeup Interrupt n */
+#define INTR_XINT_EVT2                         3		/* External Wakeup Interrupt n */
+#define INTR_XINT_EVT3                         4		/* External Wakeup Interrupt n */
+#define INTR_WDT_EXP                           5		/* Expiration */
+#define INTR_PMG0_VREG_OVR                     6		/* Voltage Regulator (VREG) Overvoltage */
+#define INTR_PMG0_BATT_RANGE                   7		/* Battery Voltage (VBAT) Out of Range */
+#define INTR_RTC0_EVT                          8		/* Event */
+#define INTR_SYS_GPIO_INTA                     9		/* GPIO Interrupt A */
+#define INTR_SYS_GPIO_INTB                    10		/* GPIO Interrupt B */
+#define INTR_TMR0_EVT                         11		/* Event */
+#define INTR_TMR1_EVT                         12		/* Event */
+#define INTR_FLCC_EVT                         13		/* Event */
+#define INTR_UART_EVT                         14		/* Event */
+#define INTR_SPI0_EVT                         15		/* Event */
+#define INTR_SPI2_EVT                         16		/* Event */
+#define INTR_I2C_SLV_EVT                      17		/* Slave Event */
+#define INTR_I2C_MST_EVT                      18		/* Master Event */
+#define INTR_DMA_CHAN_ERR                     19		/* Channel Error */
+#define INTR_DMA0_CH0_DONE                    20		/* Channel 0 Done */
+#define INTR_DMA0_CH1_DONE                    21		/* Channel 1 Done */
+#define INTR_DMA0_CH2_DONE                    22		/* Channel 2 Done */
+#define INTR_DMA0_CH3_DONE                    23		/* Channel 3 Done */
+#define INTR_DMA0_CH4_DONE                    24		/* Channel 4 Done */
+#define INTR_DMA0_CH5_DONE                    25		/* Channel 5 Done */
+#define INTR_DMA0_CH6_DONE                    26		/* Channel 6 Done */
+#define INTR_DMA0_CH7_DONE                    27		/* Channel 7 Done */
+#define INTR_DMA0_CH8_DONE                    28		/* Channel 8 Done */
+#define INTR_DMA0_CH9_DONE                    29		/* Channel 9 Done */
+#define INTR_DMA0_CH10_DONE                   30		/* Channel 10 Done */
+#define INTR_DMA0_CH11_DONE                   31		/* Channel 11 Done */
+#define INTR_DMA0_CH12_DONE                   32		/* Channel 12 Done */
+#define INTR_DMA0_CH13_DONE                   33		/* Channel 13 Done */
+#define INTR_DMA0_CH14_DONE                   34		/* Channel 14 Done */
+#define INTR_DMA0_CH15_DONE                   35		/* Channel 15 Done */
+#define INTR_SPORT_A_EVT                      36		/* Channel A Event */
+#define INTR_SPORT_B_EVT                      37		/* Channel B Event */
+#define INTR_CRYPT_EVT                        38		/* Event */
+#define INTR_DMA0_CH24_DONE                   39		/* Channel 24 Done */
+#define INTR_TMR2_EVT                         40		/* Event */
+#define INTR_CLKG_XTAL_OSC_EVT                41		/* Crystal Oscillator Event */
+#define INTR_SPI1_EVT                         42		/* Event */
+#define INTR_CLKG_PLL_EVT                     43		/* PLL Event */
+#define INTR_RNG0_EVT                         44		/* Event */
+#define INTR_BEEP_EVT                         45		/* Event */
+#define INTR_ADC0_EVT                         46		/* Event */
+#define INTR_DMA0_CH16_DONE                   56		/* Channel 16 Done */
+#define INTR_DMA0_CH17_DONE                   57		/* Channel 17 Done */
+#define INTR_DMA0_CH18_DONE                   58		/* Channel 18 Done */
+#define INTR_DMA0_CH19_DONE                   59		/* Channel 19 Done */
+#define INTR_DMA0_CH20_DONE                   60		/* Channel 20 Done */
+#define INTR_DMA0_CH21_DONE                   61		/* Channel 21 Done */
+#define INTR_DMA0_CH22_DONE                   62		/* Channel 22 Done */
+#define INTR_DMA0_CH23_DONE                   63		/* Channel 23 Done */
+
+
+#if defined (_MISRA_RULES)
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif	/* end ifndef _DEF_ADUCM302X_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_cdef.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_cdef.h
new file mode 100755
index 00000000000..fea68318596
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_cdef.h
@@ -0,0 +1,663 @@
+/* ================================================================================
+
+     Project      :   ADuCM302x
+     File         :   ADuCM302x_cdef.h
+     Description  :   C MMR Pointer Definitions
+
+     Date         :   Feb 6, 2017
+
+     Copyright (c) 2014-2017 Analog Devices, Inc.  All Rights Reserved.
+     This software is proprietary and confidential to Analog Devices, Inc. and
+     its licensors.
+
+     This file was auto-generated. Do not make local changes to this file.
+
+   ================================================================================ */
+
+#ifndef _ADUCM302X_CDEF_H
+#define _ADUCM302X_CDEF_H
+
+#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__))
+#include <stdint.h>
+#endif /* _LANGUAGE_C */
+
+/* pickup register bitfield and bit masks */
+#include "ADuCM302x.h"
+
+
+#ifndef __IO
+#ifdef __cplusplus
+#define     __I     volatile      /* read-only */
+#define     __C
+#else
+#define     __I     volatile      /* read-only */
+#define     __C     const
+#endif
+#define     __O     volatile      /* write-only */
+#define     __IO    volatile      /* read-write */
+#endif
+#if defined (_MISRA_RULES)
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit")
+#pragma diag(suppress:misra_rule_19_7:"ADI header allows function-like macros")
+#pragma diag(suppress:misra_rule_19_13:"ADI headers can use the # and ## preprocessor operators")
+#endif /* _MISRA_RULES */
+
+
+/*  =================================================================================
+ *      General Purpose Timer (TMR0)
+ *  ================================================================================= */
+#define pREG_TMR0_LOAD                   ((__IO     uint16_t  *) REG_TMR0_LOAD)                   /*  16-bit Load Value */
+#define pREG_TMR0_CURCNT                 ((__I __C  uint16_t  *) REG_TMR0_CURCNT)                 /*  16-bit Timer Value */
+#define pREG_TMR0_CTL                    ((__IO     uint16_t  *) REG_TMR0_CTL)                    /*  Control */
+#define pREG_TMR0_CLRINT                 ((__O      uint16_t  *) REG_TMR0_CLRINT)                 /*  Clear Interrupt */
+#define pREG_TMR0_CAPTURE                ((__I __C  uint16_t  *) REG_TMR0_CAPTURE)                /*  Capture */
+#define pREG_TMR0_ALOAD                  ((__IO     uint16_t  *) REG_TMR0_ALOAD)                  /*  16-bit Load Value, Asynchronous */
+#define pREG_TMR0_ACURCNT                ((__I __C  uint16_t  *) REG_TMR0_ACURCNT)                /*  16-bit Timer Value, Asynchronous */
+#define pREG_TMR0_STAT                   ((__I __C  uint16_t  *) REG_TMR0_STAT)                   /*  Status */
+#define pREG_TMR0_PWMCTL                 ((__IO     uint16_t  *) REG_TMR0_PWMCTL)                 /*  PWM Control Register */
+#define pREG_TMR0_PWMMATCH               ((__IO     uint16_t  *) REG_TMR0_PWMMATCH)               /*  PWM Match Value */
+
+/*  =================================================================================
+ *      General Purpose Timer (TMR1)
+ *  ================================================================================= */
+#define pREG_TMR1_LOAD                   ((__IO     uint16_t  *) REG_TMR1_LOAD)                   /*  16-bit Load Value */
+#define pREG_TMR1_CURCNT                 ((__I __C  uint16_t  *) REG_TMR1_CURCNT)                 /*  16-bit Timer Value */
+#define pREG_TMR1_CTL                    ((__IO     uint16_t  *) REG_TMR1_CTL)                    /*  Control */
+#define pREG_TMR1_CLRINT                 ((__O      uint16_t  *) REG_TMR1_CLRINT)                 /*  Clear Interrupt */
+#define pREG_TMR1_CAPTURE                ((__I __C  uint16_t  *) REG_TMR1_CAPTURE)                /*  Capture */
+#define pREG_TMR1_ALOAD                  ((__IO     uint16_t  *) REG_TMR1_ALOAD)                  /*  16-bit Load Value, Asynchronous */
+#define pREG_TMR1_ACURCNT                ((__I __C  uint16_t  *) REG_TMR1_ACURCNT)                /*  16-bit Timer Value, Asynchronous */
+#define pREG_TMR1_STAT                   ((__I __C  uint16_t  *) REG_TMR1_STAT)                   /*  Status */
+#define pREG_TMR1_PWMCTL                 ((__IO     uint16_t  *) REG_TMR1_PWMCTL)                 /*  PWM Control Register */
+#define pREG_TMR1_PWMMATCH               ((__IO     uint16_t  *) REG_TMR1_PWMMATCH)               /*  PWM Match Value */
+
+/*  =================================================================================
+ *      General Purpose Timer (TMR2)
+ *  ================================================================================= */
+#define pREG_TMR2_LOAD                   ((__IO     uint16_t  *) REG_TMR2_LOAD)                   /*  16-bit Load Value */
+#define pREG_TMR2_CURCNT                 ((__I __C  uint16_t  *) REG_TMR2_CURCNT)                 /*  16-bit Timer Value */
+#define pREG_TMR2_CTL                    ((__IO     uint16_t  *) REG_TMR2_CTL)                    /*  Control */
+#define pREG_TMR2_CLRINT                 ((__O      uint16_t  *) REG_TMR2_CLRINT)                 /*  Clear Interrupt */
+#define pREG_TMR2_CAPTURE                ((__I __C  uint16_t  *) REG_TMR2_CAPTURE)                /*  Capture */
+#define pREG_TMR2_ALOAD                  ((__IO     uint16_t  *) REG_TMR2_ALOAD)                  /*  16-bit Load Value, Asynchronous */
+#define pREG_TMR2_ACURCNT                ((__I __C  uint16_t  *) REG_TMR2_ACURCNT)                /*  16-bit Timer Value, Asynchronous */
+#define pREG_TMR2_STAT                   ((__I __C  uint16_t  *) REG_TMR2_STAT)                   /*  Status */
+#define pREG_TMR2_PWMCTL                 ((__IO     uint16_t  *) REG_TMR2_PWMCTL)                 /*  PWM Control Register */
+#define pREG_TMR2_PWMMATCH               ((__IO     uint16_t  *) REG_TMR2_PWMMATCH)               /*  PWM Match Value */
+
+/*  =================================================================================
+ *      Real-Time Clock (RTC0)
+ *  ================================================================================= */
+#define pREG_RTC0_CR0                    ((__IO     uint16_t  *) REG_RTC0_CR0)                    /*  RTC Control 0 */
+#define pREG_RTC0_SR0                    ((__IO     uint16_t  *) REG_RTC0_SR0)                    /*  RTC Status 0 */
+#define pREG_RTC0_SR1                    ((__I __C  uint16_t  *) REG_RTC0_SR1)                    /*  RTC Status 1 */
+#define pREG_RTC0_CNT0                   ((__IO     uint16_t  *) REG_RTC0_CNT0)                   /*  RTC Count 0 */
+#define pREG_RTC0_CNT1                   ((__IO     uint16_t  *) REG_RTC0_CNT1)                   /*  RTC Count 1 */
+#define pREG_RTC0_ALM0                   ((__IO     uint16_t  *) REG_RTC0_ALM0)                   /*  RTC Alarm 0 */
+#define pREG_RTC0_ALM1                   ((__IO     uint16_t  *) REG_RTC0_ALM1)                   /*  RTC Alarm 1 */
+#define pREG_RTC0_TRM                    ((__IO     uint16_t  *) REG_RTC0_TRM)                    /*  RTC Trim */
+#define pREG_RTC0_GWY                    ((__O      uint16_t  *) REG_RTC0_GWY)                    /*  RTC Gateway */
+#define pREG_RTC0_CR1                    ((__IO     uint16_t  *) REG_RTC0_CR1)                    /*  RTC Control 1 */
+#define pREG_RTC0_SR2                    ((__IO     uint16_t  *) REG_RTC0_SR2)                    /*  RTC Status 2 */
+#define pREG_RTC0_SNAP0                  ((__I __C  uint16_t  *) REG_RTC0_SNAP0)                  /*  RTC Snapshot 0 */
+#define pREG_RTC0_SNAP1                  ((__I __C  uint16_t  *) REG_RTC0_SNAP1)                  /*  RTC Snapshot 1 */
+#define pREG_RTC0_SNAP2                  ((__I __C  uint16_t  *) REG_RTC0_SNAP2)                  /*  RTC Snapshot 2 */
+#define pREG_RTC0_MOD                    ((__I __C  uint16_t  *) REG_RTC0_MOD)                    /*  RTC Modulo */
+#define pREG_RTC0_CNT2                   ((__I __C  uint16_t  *) REG_RTC0_CNT2)                   /*  RTC Count 2 */
+#define pREG_RTC0_ALM2                   ((__IO     uint16_t  *) REG_RTC0_ALM2)                   /*  RTC Alarm 2 */
+#define pREG_RTC0_SR3                    ((__IO     uint16_t  *) REG_RTC0_SR3)                    /*  RTC Status 3 */
+#define pREG_RTC0_CR2IC                  ((__IO     uint16_t  *) REG_RTC0_CR2IC)                  /*  RTC Control 2 for Configuring Input Capture Channels */
+#define pREG_RTC0_CR3SS                  ((__IO     uint16_t  *) REG_RTC0_CR3SS)                  /*  RTC Control 3 for Configuring SensorStrobe Channel */
+#define pREG_RTC0_CR4SS                  ((__IO     uint16_t  *) REG_RTC0_CR4SS)                  /*  RTC Control 4 for Configuring SensorStrobe Channel */
+#define pREG_RTC0_SSMSK                  ((__IO     uint16_t  *) REG_RTC0_SSMSK)                  /*  RTC Mask for SensorStrobe Channel */
+#define pREG_RTC0_SS1ARL                 ((__IO     uint16_t  *) REG_RTC0_SS1ARL)                 /*  RTC Auto-Reload for SensorStrobe Channel 1 */
+#define pREG_RTC0_IC2                    ((__I __C  uint16_t  *) REG_RTC0_IC2)                    /*  RTC Input Capture Channel 2 */
+#define pREG_RTC0_IC3                    ((__I __C  uint16_t  *) REG_RTC0_IC3)                    /*  RTC Input Capture Channel 3 */
+#define pREG_RTC0_IC4                    ((__I __C  uint16_t  *) REG_RTC0_IC4)                    /*  RTC Input Capture Channel 4 */
+#define pREG_RTC0_SS1                    ((__IO     uint16_t  *) REG_RTC0_SS1)                    /*  RTC SensorStrobe Channel 1 */
+#define pREG_RTC0_SR4                    ((__I __C  uint16_t  *) REG_RTC0_SR4)                    /*  RTC Status 4 */
+#define pREG_RTC0_SR5                    ((__I __C  uint16_t  *) REG_RTC0_SR5)                    /*  RTC Status 5 */
+#define pREG_RTC0_SR6                    ((__I __C  uint16_t  *) REG_RTC0_SR6)                    /*  RTC Status 6 */
+#define pREG_RTC0_SS1TGT                 ((__I __C  uint16_t  *) REG_RTC0_SS1TGT)                 /*  RTC SensorStrobe Channel 1 Target */
+#define pREG_RTC0_FRZCNT                 ((__I __C  uint16_t  *) REG_RTC0_FRZCNT)                 /*  RTC Freeze Count */
+
+/*  =================================================================================
+ *      Real-Time Clock (RTC1)
+ *  ================================================================================= */
+#define pREG_RTC1_CR0                    ((__IO     uint16_t  *) REG_RTC1_CR0)                    /*  RTC Control 0 */
+#define pREG_RTC1_SR0                    ((__IO     uint16_t  *) REG_RTC1_SR0)                    /*  RTC Status 0 */
+#define pREG_RTC1_SR1                    ((__I __C  uint16_t  *) REG_RTC1_SR1)                    /*  RTC Status 1 */
+#define pREG_RTC1_CNT0                   ((__IO     uint16_t  *) REG_RTC1_CNT0)                   /*  RTC Count 0 */
+#define pREG_RTC1_CNT1                   ((__IO     uint16_t  *) REG_RTC1_CNT1)                   /*  RTC Count 1 */
+#define pREG_RTC1_ALM0                   ((__IO     uint16_t  *) REG_RTC1_ALM0)                   /*  RTC Alarm 0 */
+#define pREG_RTC1_ALM1                   ((__IO     uint16_t  *) REG_RTC1_ALM1)                   /*  RTC Alarm 1 */
+#define pREG_RTC1_TRM                    ((__IO     uint16_t  *) REG_RTC1_TRM)                    /*  RTC Trim */
+#define pREG_RTC1_GWY                    ((__O      uint16_t  *) REG_RTC1_GWY)                    /*  RTC Gateway */
+#define pREG_RTC1_CR1                    ((__IO     uint16_t  *) REG_RTC1_CR1)                    /*  RTC Control 1 */
+#define pREG_RTC1_SR2                    ((__IO     uint16_t  *) REG_RTC1_SR2)                    /*  RTC Status 2 */
+#define pREG_RTC1_SNAP0                  ((__I __C  uint16_t  *) REG_RTC1_SNAP0)                  /*  RTC Snapshot 0 */
+#define pREG_RTC1_SNAP1                  ((__I __C  uint16_t  *) REG_RTC1_SNAP1)                  /*  RTC Snapshot 1 */
+#define pREG_RTC1_SNAP2                  ((__I __C  uint16_t  *) REG_RTC1_SNAP2)                  /*  RTC Snapshot 2 */
+#define pREG_RTC1_MOD                    ((__I __C  uint16_t  *) REG_RTC1_MOD)                    /*  RTC Modulo */
+#define pREG_RTC1_CNT2                   ((__I __C  uint16_t  *) REG_RTC1_CNT2)                   /*  RTC Count 2 */
+#define pREG_RTC1_ALM2                   ((__IO     uint16_t  *) REG_RTC1_ALM2)                   /*  RTC Alarm 2 */
+#define pREG_RTC1_SR3                    ((__IO     uint16_t  *) REG_RTC1_SR3)                    /*  RTC Status 3 */
+#define pREG_RTC1_CR2IC                  ((__IO     uint16_t  *) REG_RTC1_CR2IC)                  /*  RTC Control 2 for Configuring Input Capture Channels */
+#define pREG_RTC1_CR3SS                  ((__IO     uint16_t  *) REG_RTC1_CR3SS)                  /*  RTC Control 3 for Configuring SensorStrobe Channel */
+#define pREG_RTC1_CR4SS                  ((__IO     uint16_t  *) REG_RTC1_CR4SS)                  /*  RTC Control 4 for Configuring SensorStrobe Channel */
+#define pREG_RTC1_SSMSK                  ((__IO     uint16_t  *) REG_RTC1_SSMSK)                  /*  RTC Mask for SensorStrobe Channel */
+#define pREG_RTC1_SS1ARL                 ((__IO     uint16_t  *) REG_RTC1_SS1ARL)                 /*  RTC Auto-Reload for SensorStrobe Channel 1 */
+#define pREG_RTC1_IC2                    ((__I __C  uint16_t  *) REG_RTC1_IC2)                    /*  RTC Input Capture Channel 2 */
+#define pREG_RTC1_IC3                    ((__I __C  uint16_t  *) REG_RTC1_IC3)                    /*  RTC Input Capture Channel 3 */
+#define pREG_RTC1_IC4                    ((__I __C  uint16_t  *) REG_RTC1_IC4)                    /*  RTC Input Capture Channel 4 */
+#define pREG_RTC1_SS1                    ((__IO     uint16_t  *) REG_RTC1_SS1)                    /*  RTC SensorStrobe Channel 1 */
+#define pREG_RTC1_SR4                    ((__I __C  uint16_t  *) REG_RTC1_SR4)                    /*  RTC Status 4 */
+#define pREG_RTC1_SR5                    ((__I __C  uint16_t  *) REG_RTC1_SR5)                    /*  RTC Status 5 */
+#define pREG_RTC1_SR6                    ((__I __C  uint16_t  *) REG_RTC1_SR6)                    /*  RTC Status 6 */
+#define pREG_RTC1_SS1TGT                 ((__I __C  uint16_t  *) REG_RTC1_SS1TGT)                 /*  RTC SensorStrobe Channel 1 Target */
+#define pREG_RTC1_FRZCNT                 ((__I __C  uint16_t  *) REG_RTC1_FRZCNT)                 /*  RTC Freeze Count */
+
+/*  =================================================================================
+ *      System Identification and Debug Enable (SYS)
+ *  ================================================================================= */
+#define pREG_SYS_ADIID                   ((__I __C  uint16_t  *) REG_SYS_ADIID)                   /*  ADI Identification */
+#define pREG_SYS_CHIPID                  ((__I __C  uint16_t  *) REG_SYS_CHIPID)                  /*  Chip Identifier */
+#define pREG_SYS_SWDEN                   ((__O      uint16_t  *) REG_SYS_SWDEN)                   /*  Serial Wire Debug Enable */
+
+/*  =================================================================================
+ *      Watchdog Timer (WDT0)
+ *  ================================================================================= */
+#define pREG_WDT0_LOAD                   ((__IO     uint16_t  *) REG_WDT0_LOAD)                   /*  Load Value */
+#define pREG_WDT0_CCNT                   ((__I __C  uint16_t  *) REG_WDT0_CCNT)                   /*  Current Count Value */
+#define pREG_WDT0_CTL                    ((__IO     uint16_t  *) REG_WDT0_CTL)                    /*  Control */
+#define pREG_WDT0_RESTART                ((__O      uint16_t  *) REG_WDT0_RESTART)                /*  Clear Interrupt */
+#define pREG_WDT0_STAT                   ((__I __C  uint16_t  *) REG_WDT0_STAT)                   /*  Status */
+
+/*  =================================================================================
+ *      I2C Master/Slave (I2C0)
+ *  ================================================================================= */
+#define pREG_I2C0_MCTL                   ((__IO     uint16_t  *) REG_I2C0_MCTL)                   /*  Master Control */
+#define pREG_I2C0_MSTAT                  ((__IO     uint16_t  *) REG_I2C0_MSTAT)                  /*  Master Status */
+#define pREG_I2C0_MRX                    ((__I __C  uint16_t  *) REG_I2C0_MRX)                    /*  Master Receive Data */
+#define pREG_I2C0_MTX                    ((__IO     uint16_t  *) REG_I2C0_MTX)                    /*  Master Transmit Data */
+#define pREG_I2C0_MRXCNT                 ((__IO     uint16_t  *) REG_I2C0_MRXCNT)                 /*  Master Receive Data Count */
+#define pREG_I2C0_MCRXCNT                ((__I __C  uint16_t  *) REG_I2C0_MCRXCNT)                /*  Master Current Receive Data Count */
+#define pREG_I2C0_ADDR1                  ((__IO     uint16_t  *) REG_I2C0_ADDR1)                  /*  Master Address Byte 1 */
+#define pREG_I2C0_ADDR2                  ((__IO     uint16_t  *) REG_I2C0_ADDR2)                  /*  Master Address Byte 2 */
+#define pREG_I2C0_BYT                    ((__IO     uint16_t  *) REG_I2C0_BYT)                    /*  Start Byte */
+#define pREG_I2C0_DIV                    ((__IO     uint16_t  *) REG_I2C0_DIV)                    /*  Serial Clock Period Divisor */
+#define pREG_I2C0_SCTL                   ((__IO     uint16_t  *) REG_I2C0_SCTL)                   /*  Slave Control */
+#define pREG_I2C0_SSTAT                  ((__IO     uint16_t  *) REG_I2C0_SSTAT)                  /*  Slave I2C Status/Error/IRQ */
+#define pREG_I2C0_SRX                    ((__I __C  uint16_t  *) REG_I2C0_SRX)                    /*  Slave Receive */
+#define pREG_I2C0_STX                    ((__IO     uint16_t  *) REG_I2C0_STX)                    /*  Slave Transmit */
+#define pREG_I2C0_ALT                    ((__IO     uint16_t  *) REG_I2C0_ALT)                    /*  Hardware General Call ID */
+#define pREG_I2C0_ID0                    ((__IO     uint16_t  *) REG_I2C0_ID0)                    /*  First Slave Address Device ID */
+#define pREG_I2C0_ID1                    ((__IO     uint16_t  *) REG_I2C0_ID1)                    /*  Second Slave Address Device ID */
+#define pREG_I2C0_ID2                    ((__IO     uint16_t  *) REG_I2C0_ID2)                    /*  Third Slave Address Device ID */
+#define pREG_I2C0_ID3                    ((__IO     uint16_t  *) REG_I2C0_ID3)                    /*  Fourth Slave Address Device ID */
+#define pREG_I2C0_STAT                   ((__IO     uint16_t  *) REG_I2C0_STAT)                   /*  Master and Slave FIFO Status */
+#define pREG_I2C0_SHCTL                  ((__O      uint16_t  *) REG_I2C0_SHCTL)                  /*  Shared Control */
+#define pREG_I2C0_TCTL                   ((__IO     uint16_t  *) REG_I2C0_TCTL)                   /*  Timing Control Register */
+#define pREG_I2C0_ASTRETCH_SCL           ((__IO     uint16_t  *) REG_I2C0_ASTRETCH_SCL)           /*  Automatic Stretch SCL */
+
+/*  =================================================================================
+ *      Serial Peripheral Interface (SPI0)
+ *  ================================================================================= */
+#define pREG_SPI0_STAT                   ((__IO     uint16_t  *) REG_SPI0_STAT)                   /*  Status */
+#define pREG_SPI0_RX                     ((__I __C  uint16_t  *) REG_SPI0_RX)                     /*  Receive */
+#define pREG_SPI0_TX                     ((__O      uint16_t  *) REG_SPI0_TX)                     /*  Transmit */
+#define pREG_SPI0_DIV                    ((__IO     uint16_t  *) REG_SPI0_DIV)                    /*  SPI Baud Rate Selection */
+#define pREG_SPI0_CTL                    ((__IO     uint16_t  *) REG_SPI0_CTL)                    /*  SPI Configuration */
+#define pREG_SPI0_IEN                    ((__IO     uint16_t  *) REG_SPI0_IEN)                    /*  SPI Interrupts Enable */
+#define pREG_SPI0_CNT                    ((__IO     uint16_t  *) REG_SPI0_CNT)                    /*  Transfer Byte Count */
+#define pREG_SPI0_DMA                    ((__IO     uint16_t  *) REG_SPI0_DMA)                    /*  SPI DMA Enable */
+#define pREG_SPI0_FIFO_STAT              ((__I __C  uint16_t  *) REG_SPI0_FIFO_STAT)              /*  FIFO Status */
+#define pREG_SPI0_RD_CTL                 ((__IO     uint16_t  *) REG_SPI0_RD_CTL)                 /*  Read Control */
+#define pREG_SPI0_FLOW_CTL               ((__IO     uint16_t  *) REG_SPI0_FLOW_CTL)               /*  Flow Control */
+#define pREG_SPI0_WAIT_TMR               ((__IO     uint16_t  *) REG_SPI0_WAIT_TMR)               /*  Wait Timer for Flow Control */
+#define pREG_SPI0_CS_CTL                 ((__IO     uint16_t  *) REG_SPI0_CS_CTL)                 /*  Chip Select Control for Multi-slave Connections */
+#define pREG_SPI0_CS_OVERRIDE            ((__IO     uint16_t  *) REG_SPI0_CS_OVERRIDE)            /*  Chip Select Override */
+
+/*  =================================================================================
+ *      Serial Peripheral Interface (SPI1)
+ *  ================================================================================= */
+#define pREG_SPI1_STAT                   ((__IO     uint16_t  *) REG_SPI1_STAT)                   /*  Status */
+#define pREG_SPI1_RX                     ((__I __C  uint16_t  *) REG_SPI1_RX)                     /*  Receive */
+#define pREG_SPI1_TX                     ((__O      uint16_t  *) REG_SPI1_TX)                     /*  Transmit */
+#define pREG_SPI1_DIV                    ((__IO     uint16_t  *) REG_SPI1_DIV)                    /*  SPI Baud Rate Selection */
+#define pREG_SPI1_CTL                    ((__IO     uint16_t  *) REG_SPI1_CTL)                    /*  SPI Configuration */
+#define pREG_SPI1_IEN                    ((__IO     uint16_t  *) REG_SPI1_IEN)                    /*  SPI Interrupts Enable */
+#define pREG_SPI1_CNT                    ((__IO     uint16_t  *) REG_SPI1_CNT)                    /*  Transfer Byte Count */
+#define pREG_SPI1_DMA                    ((__IO     uint16_t  *) REG_SPI1_DMA)                    /*  SPI DMA Enable */
+#define pREG_SPI1_FIFO_STAT              ((__I __C  uint16_t  *) REG_SPI1_FIFO_STAT)              /*  FIFO Status */
+#define pREG_SPI1_RD_CTL                 ((__IO     uint16_t  *) REG_SPI1_RD_CTL)                 /*  Read Control */
+#define pREG_SPI1_FLOW_CTL               ((__IO     uint16_t  *) REG_SPI1_FLOW_CTL)               /*  Flow Control */
+#define pREG_SPI1_WAIT_TMR               ((__IO     uint16_t  *) REG_SPI1_WAIT_TMR)               /*  Wait Timer for Flow Control */
+#define pREG_SPI1_CS_CTL                 ((__IO     uint16_t  *) REG_SPI1_CS_CTL)                 /*  Chip Select Control for Multi-slave Connections */
+#define pREG_SPI1_CS_OVERRIDE            ((__IO     uint16_t  *) REG_SPI1_CS_OVERRIDE)            /*  Chip Select Override */
+
+/*  =================================================================================
+ *      Serial Peripheral Interface (SPI2)
+ *  ================================================================================= */
+#define pREG_SPI2_STAT                   ((__IO     uint16_t  *) REG_SPI2_STAT)                   /*  Status */
+#define pREG_SPI2_RX                     ((__I __C  uint16_t  *) REG_SPI2_RX)                     /*  Receive */
+#define pREG_SPI2_TX                     ((__O      uint16_t  *) REG_SPI2_TX)                     /*  Transmit */
+#define pREG_SPI2_DIV                    ((__IO     uint16_t  *) REG_SPI2_DIV)                    /*  SPI Baud Rate Selection */
+#define pREG_SPI2_CTL                    ((__IO     uint16_t  *) REG_SPI2_CTL)                    /*  SPI Configuration */
+#define pREG_SPI2_IEN                    ((__IO     uint16_t  *) REG_SPI2_IEN)                    /*  SPI Interrupts Enable */
+#define pREG_SPI2_CNT                    ((__IO     uint16_t  *) REG_SPI2_CNT)                    /*  Transfer Byte Count */
+#define pREG_SPI2_DMA                    ((__IO     uint16_t  *) REG_SPI2_DMA)                    /*  SPI DMA Enable */
+#define pREG_SPI2_FIFO_STAT              ((__I __C  uint16_t  *) REG_SPI2_FIFO_STAT)              /*  FIFO Status */
+#define pREG_SPI2_RD_CTL                 ((__IO     uint16_t  *) REG_SPI2_RD_CTL)                 /*  Read Control */
+#define pREG_SPI2_FLOW_CTL               ((__IO     uint16_t  *) REG_SPI2_FLOW_CTL)               /*  Flow Control */
+#define pREG_SPI2_WAIT_TMR               ((__IO     uint16_t  *) REG_SPI2_WAIT_TMR)               /*  Wait Timer for Flow Control */
+#define pREG_SPI2_CS_CTL                 ((__IO     uint16_t  *) REG_SPI2_CS_CTL)                 /*  Chip Select Control for Multi-slave Connections */
+#define pREG_SPI2_CS_OVERRIDE            ((__IO     uint16_t  *) REG_SPI2_CS_OVERRIDE)            /*  Chip Select Override */
+
+/*  =================================================================================
+ *       (UART0)
+ *  ================================================================================= */
+#define pREG_UART0_TX                    ((__O      uint16_t  *) REG_UART0_TX)                    /*  Transmit Holding Register */
+#define pREG_UART0_RX                    ((__I __C  uint16_t  *) REG_UART0_RX)                    /*  Receive Buffer Register */
+#define pREG_UART0_IEN                   ((__IO     uint16_t  *) REG_UART0_IEN)                   /*  Interrupt Enable */
+#define pREG_UART0_IIR                   ((__I __C  uint16_t  *) REG_UART0_IIR)                   /*  Interrupt ID */
+#define pREG_UART0_LCR                   ((__IO     uint16_t  *) REG_UART0_LCR)                   /*  Line Control */
+#define pREG_UART0_MCR                   ((__IO     uint16_t  *) REG_UART0_MCR)                   /*  Modem Control */
+#define pREG_UART0_LSR                   ((__I __C  uint16_t  *) REG_UART0_LSR)                   /*  Line Status */
+#define pREG_UART0_MSR                   ((__I __C  uint16_t  *) REG_UART0_MSR)                   /*  Modem Status */
+#define pREG_UART0_SCR                   ((__IO     uint16_t  *) REG_UART0_SCR)                   /*  Scratch Buffer */
+#define pREG_UART0_FCR                   ((__IO     uint16_t  *) REG_UART0_FCR)                   /*  FIFO Control */
+#define pREG_UART0_FBR                   ((__IO     uint16_t  *) REG_UART0_FBR)                   /*  Fractional Baud Rate */
+#define pREG_UART0_DIV                   ((__IO     uint16_t  *) REG_UART0_DIV)                   /*  Baud Rate Divider */
+#define pREG_UART0_LCR2                  ((__IO     uint16_t  *) REG_UART0_LCR2)                  /*  Second Line Control */
+#define pREG_UART0_CTL                   ((__IO     uint16_t  *) REG_UART0_CTL)                   /*  UART Control Register */
+#define pREG_UART0_RFC                   ((__I __C  uint16_t  *) REG_UART0_RFC)                   /*  RX FIFO Byte Count */
+#define pREG_UART0_TFC                   ((__I __C  uint16_t  *) REG_UART0_TFC)                   /*  TX FIFO Byte Count */
+#define pREG_UART0_RSC                   ((__IO     uint16_t  *) REG_UART0_RSC)                   /*  RS485 Half-duplex Control */
+#define pREG_UART0_ACR                   ((__IO     uint16_t  *) REG_UART0_ACR)                   /*  Auto Baud Control */
+#define pREG_UART0_ASRL                  ((__I __C  uint16_t  *) REG_UART0_ASRL)                  /*  Auto Baud Status (Low) */
+#define pREG_UART0_ASRH                  ((__I __C  uint16_t  *) REG_UART0_ASRH)                  /*  Auto Baud Status (High) */
+
+/*  =================================================================================
+ *      Beeper Driver (BEEP0)
+ *  ================================================================================= */
+#define pREG_BEEP0_CFG                   ((__IO     uint16_t  *) REG_BEEP0_CFG)                   /*  Beeper Configuration */
+#define pREG_BEEP0_STAT                  ((__IO     uint16_t  *) REG_BEEP0_STAT)                  /*  Beeper Status */
+#define pREG_BEEP0_TONEA                 ((__IO     uint16_t  *) REG_BEEP0_TONEA)                 /*  Tone A Data */
+#define pREG_BEEP0_TONEB                 ((__IO     uint16_t  *) REG_BEEP0_TONEB)                 /*  Tone B Data */
+
+/*  =================================================================================
+ *       (ADC0)
+ *  ================================================================================= */
+#define pREG_ADC0_CFG                    ((__IO     uint16_t  *) REG_ADC0_CFG)                    /*  ADC Configuration */
+#define pREG_ADC0_PWRUP                  ((__IO     uint16_t  *) REG_ADC0_PWRUP)                  /*  ADC Power-up Time */
+#define pREG_ADC0_CAL_WORD               ((__IO     uint16_t  *) REG_ADC0_CAL_WORD)               /*  Calibration Word */
+#define pREG_ADC0_CNV_CFG                ((__IO     uint16_t  *) REG_ADC0_CNV_CFG)                /*  ADC Conversion Configuration */
+#define pREG_ADC0_CNV_TIME               ((__IO     uint16_t  *) REG_ADC0_CNV_TIME)               /*  ADC Conversion Time */
+#define pREG_ADC0_AVG_CFG                ((__IO     uint16_t  *) REG_ADC0_AVG_CFG)                /*  Averaging Configuration */
+#define pREG_ADC0_IRQ_EN                 ((__IO     uint16_t  *) REG_ADC0_IRQ_EN)                 /*  Interrupt Enable */
+#define pREG_ADC0_STAT                   ((__IO     uint16_t  *) REG_ADC0_STAT)                   /*  ADC Status */
+#define pREG_ADC0_OVF                    ((__IO     uint16_t  *) REG_ADC0_OVF)                    /*  Overflow of Output Registers */
+#define pREG_ADC0_ALERT                  ((__IO     uint16_t  *) REG_ADC0_ALERT)                  /*  Alert Indication */
+#define pREG_ADC0_CH0_OUT                ((__I __C  uint16_t  *) REG_ADC0_CH0_OUT)                /*  Conversion Result Channel 0 */
+#define pREG_ADC0_CH1_OUT                ((__I __C  uint16_t  *) REG_ADC0_CH1_OUT)                /*  Conversion Result Channel 1 */
+#define pREG_ADC0_CH2_OUT                ((__I __C  uint16_t  *) REG_ADC0_CH2_OUT)                /*  Conversion Result Channel 2 */
+#define pREG_ADC0_CH3_OUT                ((__I __C  uint16_t  *) REG_ADC0_CH3_OUT)                /*  Conversion Result Channel 3 */
+#define pREG_ADC0_CH4_OUT                ((__I __C  uint16_t  *) REG_ADC0_CH4_OUT)                /*  Conversion Result Channel 4 */
+#define pREG_ADC0_CH5_OUT                ((__I __C  uint16_t  *) REG_ADC0_CH5_OUT)                /*  Conversion Result Channel 5 */
+#define pREG_ADC0_CH6_OUT                ((__I __C  uint16_t  *) REG_ADC0_CH6_OUT)                /*  Conversion Result Channel 6 */
+#define pREG_ADC0_CH7_OUT                ((__I __C  uint16_t  *) REG_ADC0_CH7_OUT)                /*  Conversion Result Channel 7 */
+#define pREG_ADC0_BAT_OUT                ((__I __C  uint16_t  *) REG_ADC0_BAT_OUT)                /*  Battery Monitoring Result */
+#define pREG_ADC0_TMP_OUT                ((__I __C  uint16_t  *) REG_ADC0_TMP_OUT)                /*  Temperature Result */
+#define pREG_ADC0_TMP2_OUT               ((__I __C  uint16_t  *) REG_ADC0_TMP2_OUT)               /*  Temperature Result 2 */
+#define pREG_ADC0_DMA_OUT                ((__I __C  uint16_t  *) REG_ADC0_DMA_OUT)                /*  DMA Output Register */
+#define pREG_ADC0_LIM0_LO                ((__IO     uint16_t  *) REG_ADC0_LIM0_LO)                /*  Channel 0 Low Limit */
+#define pREG_ADC0_LIM0_HI                ((__IO     uint16_t  *) REG_ADC0_LIM0_HI)                /*  Channel 0 High Limit */
+#define pREG_ADC0_HYS0                   ((__IO     uint16_t  *) REG_ADC0_HYS0)                   /*  Channel 0 Hysteresis */
+#define pREG_ADC0_LIM1_LO                ((__IO     uint16_t  *) REG_ADC0_LIM1_LO)                /*  Channel 1 Low Limit */
+#define pREG_ADC0_LIM1_HI                ((__IO     uint16_t  *) REG_ADC0_LIM1_HI)                /*  Channel 1 High Limit */
+#define pREG_ADC0_HYS1                   ((__IO     uint16_t  *) REG_ADC0_HYS1)                   /*  Channel 1 Hysteresis */
+#define pREG_ADC0_LIM2_LO                ((__IO     uint16_t  *) REG_ADC0_LIM2_LO)                /*  Channel 2 Low Limit */
+#define pREG_ADC0_LIM2_HI                ((__IO     uint16_t  *) REG_ADC0_LIM2_HI)                /*  Channel 2 High Limit */
+#define pREG_ADC0_HYS2                   ((__IO     uint16_t  *) REG_ADC0_HYS2)                   /*  Channel 2 Hysteresis */
+#define pREG_ADC0_LIM3_LO                ((__IO     uint16_t  *) REG_ADC0_LIM3_LO)                /*  Channel 3 Low Limit */
+#define pREG_ADC0_LIM3_HI                ((__IO     uint16_t  *) REG_ADC0_LIM3_HI)                /*  Channel 3 High Limit */
+#define pREG_ADC0_HYS3                   ((__IO     uint16_t  *) REG_ADC0_HYS3)                   /*  Channel 3 Hysteresis */
+#define pREG_ADC0_CFG1                   ((__IO     uint16_t  *) REG_ADC0_CFG1)                   /*  Reference Buffer Low Power Mode */
+
+/*  =================================================================================
+ *      DMA (DMA0)
+ *  ================================================================================= */
+#define pREG_DMA0_STAT                   ((__I __C  uint32_t  *) REG_DMA0_STAT)                   /*  DMA Status */
+#define pREG_DMA0_CFG                    ((__O      uint32_t  *) REG_DMA0_CFG)                    /*  DMA Configuration */
+#define pREG_DMA0_PDBPTR                 ((__IO     uint32_t  *) REG_DMA0_PDBPTR)                 /*  DMA Channel Primary Control Database Pointer */
+#define pREG_DMA0_ADBPTR                 ((__I __C  uint32_t  *) REG_DMA0_ADBPTR)                 /*  DMA Channel Alternate Control Database Pointer */
+#define pREG_DMA0_SWREQ                  ((__O      uint32_t  *) REG_DMA0_SWREQ)                  /*  DMA Channel Software Request */
+#define pREG_DMA0_RMSK_SET               ((__IO     uint32_t  *) REG_DMA0_RMSK_SET)               /*  DMA Channel Request Mask Set */
+#define pREG_DMA0_RMSK_CLR               ((__O      uint32_t  *) REG_DMA0_RMSK_CLR)               /*  DMA Channel Request Mask Clear */
+#define pREG_DMA0_EN_SET                 ((__IO     uint32_t  *) REG_DMA0_EN_SET)                 /*  DMA Channel Enable Set */
+#define pREG_DMA0_EN_CLR                 ((__O      uint32_t  *) REG_DMA0_EN_CLR)                 /*  DMA Channel Enable Clear */
+#define pREG_DMA0_ALT_SET                ((__IO     uint32_t  *) REG_DMA0_ALT_SET)                /*  DMA Channel Primary Alternate Set */
+#define pREG_DMA0_ALT_CLR                ((__O      uint32_t  *) REG_DMA0_ALT_CLR)                /*  DMA Channel Primary Alternate Clear */
+#define pREG_DMA0_PRI_SET                ((__O      uint32_t  *) REG_DMA0_PRI_SET)                /*  DMA Channel Priority Set */
+#define pREG_DMA0_PRI_CLR                ((__O      uint32_t  *) REG_DMA0_PRI_CLR)                /*  DMA Channel Priority Clear */
+#define pREG_DMA0_ERRCHNL_CLR            ((__IO     uint32_t  *) REG_DMA0_ERRCHNL_CLR)            /*  DMA per Channel Error Clear */
+#define pREG_DMA0_ERR_CLR                ((__IO     uint32_t  *) REG_DMA0_ERR_CLR)                /*  DMA Bus Error Clear */
+#define pREG_DMA0_INVALIDDESC_CLR        ((__IO     uint32_t  *) REG_DMA0_INVALIDDESC_CLR)        /*  DMA per Channel Invalid Descriptor Clear */
+#define pREG_DMA0_BS_SET                 ((__IO     uint32_t  *) REG_DMA0_BS_SET)                 /*  DMA Channel Bytes Swap Enable Set */
+#define pREG_DMA0_BS_CLR                 ((__O      uint32_t  *) REG_DMA0_BS_CLR)                 /*  DMA Channel Bytes Swap Enable Clear */
+#define pREG_DMA0_SRCADDR_SET            ((__IO     uint32_t  *) REG_DMA0_SRCADDR_SET)            /*  DMA Channel Source Address Decrement Enable Set */
+#define pREG_DMA0_SRCADDR_CLR            ((__O      uint32_t  *) REG_DMA0_SRCADDR_CLR)            /*  DMA Channel Source Address Decrement Enable Clear */
+#define pREG_DMA0_DSTADDR_SET            ((__IO     uint32_t  *) REG_DMA0_DSTADDR_SET)            /*  DMA Channel Destination Address Decrement Enable Set */
+#define pREG_DMA0_DSTADDR_CLR            ((__O      uint32_t  *) REG_DMA0_DSTADDR_CLR)            /*  DMA Channel Destination Address Decrement Enable Clear */
+#define pREG_DMA0_REVID                  ((__I __C  uint32_t  *) REG_DMA0_REVID)                  /*  DMA Controller Revision ID */
+
+/*  =================================================================================
+ *      Flash Controller (FLCC0)
+ *  ================================================================================= */
+#define pREG_FLCC0_STAT                  ((__IO     uint32_t  *) REG_FLCC0_STAT)                  /*  Status */
+#define pREG_FLCC0_IEN                   ((__IO     uint32_t  *) REG_FLCC0_IEN)                   /*  Interrupt Enable */
+#define pREG_FLCC0_CMD                   ((__IO     uint32_t  *) REG_FLCC0_CMD)                   /*  Command */
+#define pREG_FLCC0_KH_ADDR               ((__IO     uint32_t  *) REG_FLCC0_KH_ADDR)               /*  Write Address */
+#define pREG_FLCC0_KH_DATA0              ((__IO     uint32_t  *) REG_FLCC0_KH_DATA0)              /*  Write Lower Data */
+#define pREG_FLCC0_KH_DATA1              ((__IO     uint32_t  *) REG_FLCC0_KH_DATA1)              /*  Write Upper Data */
+#define pREG_FLCC0_PAGE_ADDR0            ((__IO     uint32_t  *) REG_FLCC0_PAGE_ADDR0)            /*  Lower Page Address */
+#define pREG_FLCC0_PAGE_ADDR1            ((__IO     uint32_t  *) REG_FLCC0_PAGE_ADDR1)            /*  Upper Page Address */
+#define pREG_FLCC0_KEY                   ((__O      uint32_t  *) REG_FLCC0_KEY)                   /*  Key */
+#define pREG_FLCC0_WR_ABORT_ADDR         ((__I __C  uint32_t  *) REG_FLCC0_WR_ABORT_ADDR)         /*  Write Abort Address */
+#define pREG_FLCC0_WRPROT                ((__IO     uint32_t  *) REG_FLCC0_WRPROT)                /*  Write Protection */
+#define pREG_FLCC0_SIGNATURE             ((__I __C  uint32_t  *) REG_FLCC0_SIGNATURE)             /*  Signature */
+#define pREG_FLCC0_UCFG                  ((__IO     uint32_t  *) REG_FLCC0_UCFG)                  /*  User Configuration */
+#define pREG_FLCC0_TIME_PARAM0           ((__IO     uint32_t  *) REG_FLCC0_TIME_PARAM0)           /*  Time Parameter 0 */
+#define pREG_FLCC0_TIME_PARAM1           ((__IO     uint32_t  *) REG_FLCC0_TIME_PARAM1)           /*  Time Parameter 1 */
+#define pREG_FLCC0_ABORT_EN_LO           ((__IO     uint32_t  *) REG_FLCC0_ABORT_EN_LO)           /*  IRQ Abort Enable (Lower Bits) */
+#define pREG_FLCC0_ABORT_EN_HI           ((__IO     uint32_t  *) REG_FLCC0_ABORT_EN_HI)           /*  IRQ Abort Enable (Upper Bits) */
+#define pREG_FLCC0_ECC_CFG               ((__IO     uint32_t  *) REG_FLCC0_ECC_CFG)               /*  ECC Configuration */
+#define pREG_FLCC0_ECC_ADDR              ((__I __C  uint32_t  *) REG_FLCC0_ECC_ADDR)              /*  ECC Status (Address) */
+#define pREG_FLCC0_POR_SEC               ((__IO     uint32_t  *) REG_FLCC0_POR_SEC)               /*  Flash Security */
+#define pREG_FLCC0_VOL_CFG               ((__IO     uint32_t  *) REG_FLCC0_VOL_CFG)               /*  Volatile Flash Configuration */
+
+/*  =================================================================================
+ *      Cache Controller (FLCC0_CACHE)
+ *  ================================================================================= */
+#define pREG_FLCC0_CACHE_STAT            ((__I __C  uint32_t  *) REG_FLCC0_CACHE_STAT)            /*  Cache Status */
+#define pREG_FLCC0_CACHE_SETUP           ((__IO     uint32_t  *) REG_FLCC0_CACHE_SETUP)           /*  Cache Setup */
+#define pREG_FLCC0_CACHE_KEY             ((__O      uint32_t  *) REG_FLCC0_CACHE_KEY)             /*  Cache Key */
+
+/*  =================================================================================
+ *       (GPIO0)
+ *  ================================================================================= */
+#define pREG_GPIO0_CFG                   ((__IO     uint32_t  *) REG_GPIO0_CFG)                   /*  Port Configuration */
+#define pREG_GPIO0_OEN                   ((__IO     uint16_t  *) REG_GPIO0_OEN)                   /*  Port Output Enable */
+#define pREG_GPIO0_PE                    ((__IO     uint16_t  *) REG_GPIO0_PE)                    /*  Port Output Pull-up/Pull-down Enable */
+#define pREG_GPIO0_IEN                   ((__IO     uint16_t  *) REG_GPIO0_IEN)                   /*  Port Input Path Enable */
+#define pREG_GPIO0_IN                    ((__I __C  uint16_t  *) REG_GPIO0_IN)                    /*  Port Registered Data Input */
+#define pREG_GPIO0_OUT                   ((__IO     uint16_t  *) REG_GPIO0_OUT)                   /*  Port Data Output */
+#define pREG_GPIO0_SET                   ((__O      uint16_t  *) REG_GPIO0_SET)                   /*  Port Data Out Set */
+#define pREG_GPIO0_CLR                   ((__O      uint16_t  *) REG_GPIO0_CLR)                   /*  Port Data Out Clear */
+#define pREG_GPIO0_TGL                   ((__O      uint16_t  *) REG_GPIO0_TGL)                   /*  Port Pin Toggle */
+#define pREG_GPIO0_POL                   ((__IO     uint16_t  *) REG_GPIO0_POL)                   /*  Port Interrupt Polarity */
+#define pREG_GPIO0_IENA                  ((__IO     uint16_t  *) REG_GPIO0_IENA)                  /*  Port Interrupt A Enable */
+#define pREG_GPIO0_IENB                  ((__IO     uint16_t  *) REG_GPIO0_IENB)                  /*  Port Interrupt B Enable */
+#define pREG_GPIO0_INT                   ((__IO     uint16_t  *) REG_GPIO0_INT)                   /*  Port Interrupt Status */
+#define pREG_GPIO0_DS                    ((__IO     uint16_t  *) REG_GPIO0_DS)                    /*  Port Drive Strength Select */
+
+/*  =================================================================================
+ *       (GPIO1)
+ *  ================================================================================= */
+#define pREG_GPIO1_CFG                   ((__IO     uint32_t  *) REG_GPIO1_CFG)                   /*  Port Configuration */
+#define pREG_GPIO1_OEN                   ((__IO     uint16_t  *) REG_GPIO1_OEN)                   /*  Port Output Enable */
+#define pREG_GPIO1_PE                    ((__IO     uint16_t  *) REG_GPIO1_PE)                    /*  Port Output Pull-up/Pull-down Enable */
+#define pREG_GPIO1_IEN                   ((__IO     uint16_t  *) REG_GPIO1_IEN)                   /*  Port Input Path Enable */
+#define pREG_GPIO1_IN                    ((__I __C  uint16_t  *) REG_GPIO1_IN)                    /*  Port Registered Data Input */
+#define pREG_GPIO1_OUT                   ((__IO     uint16_t  *) REG_GPIO1_OUT)                   /*  Port Data Output */
+#define pREG_GPIO1_SET                   ((__O      uint16_t  *) REG_GPIO1_SET)                   /*  Port Data Out Set */
+#define pREG_GPIO1_CLR                   ((__O      uint16_t  *) REG_GPIO1_CLR)                   /*  Port Data Out Clear */
+#define pREG_GPIO1_TGL                   ((__O      uint16_t  *) REG_GPIO1_TGL)                   /*  Port Pin Toggle */
+#define pREG_GPIO1_POL                   ((__IO     uint16_t  *) REG_GPIO1_POL)                   /*  Port Interrupt Polarity */
+#define pREG_GPIO1_IENA                  ((__IO     uint16_t  *) REG_GPIO1_IENA)                  /*  Port Interrupt A Enable */
+#define pREG_GPIO1_IENB                  ((__IO     uint16_t  *) REG_GPIO1_IENB)                  /*  Port Interrupt B Enable */
+#define pREG_GPIO1_INT                   ((__IO     uint16_t  *) REG_GPIO1_INT)                   /*  Port Interrupt Status */
+#define pREG_GPIO1_DS                    ((__IO     uint16_t  *) REG_GPIO1_DS)                    /*  Port Drive Strength Select */
+
+/*  =================================================================================
+ *       (GPIO2)
+ *  ================================================================================= */
+#define pREG_GPIO2_CFG                   ((__IO     uint32_t  *) REG_GPIO2_CFG)                   /*  Port Configuration */
+#define pREG_GPIO2_OEN                   ((__IO     uint16_t  *) REG_GPIO2_OEN)                   /*  Port Output Enable */
+#define pREG_GPIO2_PE                    ((__IO     uint16_t  *) REG_GPIO2_PE)                    /*  Port Output Pull-up/Pull-down Enable */
+#define pREG_GPIO2_IEN                   ((__IO     uint16_t  *) REG_GPIO2_IEN)                   /*  Port Input Path Enable */
+#define pREG_GPIO2_IN                    ((__I __C  uint16_t  *) REG_GPIO2_IN)                    /*  Port Registered Data Input */
+#define pREG_GPIO2_OUT                   ((__IO     uint16_t  *) REG_GPIO2_OUT)                   /*  Port Data Output */
+#define pREG_GPIO2_SET                   ((__O      uint16_t  *) REG_GPIO2_SET)                   /*  Port Data Out Set */
+#define pREG_GPIO2_CLR                   ((__O      uint16_t  *) REG_GPIO2_CLR)                   /*  Port Data Out Clear */
+#define pREG_GPIO2_TGL                   ((__O      uint16_t  *) REG_GPIO2_TGL)                   /*  Port Pin Toggle */
+#define pREG_GPIO2_POL                   ((__IO     uint16_t  *) REG_GPIO2_POL)                   /*  Port Interrupt Polarity */
+#define pREG_GPIO2_IENA                  ((__IO     uint16_t  *) REG_GPIO2_IENA)                  /*  Port Interrupt A Enable */
+#define pREG_GPIO2_IENB                  ((__IO     uint16_t  *) REG_GPIO2_IENB)                  /*  Port Interrupt B Enable */
+#define pREG_GPIO2_INT                   ((__IO     uint16_t  *) REG_GPIO2_INT)                   /*  Port Interrupt Status */
+#define pREG_GPIO2_DS                    ((__IO     uint16_t  *) REG_GPIO2_DS)                    /*  Port Drive Strength Select */
+
+/*  =================================================================================
+ *      Serial Port (SPORT0)
+ *  ================================================================================= */
+#define pREG_SPORT0_CTL_A                ((__IO     uint32_t  *) REG_SPORT0_CTL_A)                /*  Half SPORT 'A' Control */
+#define pREG_SPORT0_DIV_A                ((__IO     uint32_t  *) REG_SPORT0_DIV_A)                /*  Half SPORT 'A' Divisor */
+#define pREG_SPORT0_IEN_A                ((__IO     uint32_t  *) REG_SPORT0_IEN_A)                /*  Half SPORT A's Interrupt Enable */
+#define pREG_SPORT0_STAT_A               ((__IO     uint32_t  *) REG_SPORT0_STAT_A)               /*  Half SPORT A's Status */
+#define pREG_SPORT0_NUMTRAN_A            ((__IO     uint32_t  *) REG_SPORT0_NUMTRAN_A)            /*  Half SPORT A Number of Transfers */
+#define pREG_SPORT0_CNVT_A               ((__IO     uint32_t  *) REG_SPORT0_CNVT_A)               /*  Half SPORT 'A' CNV Width */
+#define pREG_SPORT0_TX_A                 ((__O      uint32_t  *) REG_SPORT0_TX_A)                 /*  Half SPORT 'A' Tx Buffer */
+#define pREG_SPORT0_RX_A                 ((__I __C  uint32_t  *) REG_SPORT0_RX_A)                 /*  Half SPORT 'A' Rx Buffer */
+#define pREG_SPORT0_CTL_B                ((__IO     uint32_t  *) REG_SPORT0_CTL_B)                /*  Half SPORT 'B' Control */
+#define pREG_SPORT0_DIV_B                ((__IO     uint32_t  *) REG_SPORT0_DIV_B)                /*  Half SPORT 'B' Divisor */
+#define pREG_SPORT0_IEN_B                ((__IO     uint32_t  *) REG_SPORT0_IEN_B)                /*  Half SPORT B's Interrupt Enable */
+#define pREG_SPORT0_STAT_B               ((__IO     uint32_t  *) REG_SPORT0_STAT_B)               /*  Half SPORT B's Status */
+#define pREG_SPORT0_NUMTRAN_B            ((__IO     uint32_t  *) REG_SPORT0_NUMTRAN_B)            /*  Half SPORT B Number of Transfers */
+#define pREG_SPORT0_CNVT_B               ((__IO     uint32_t  *) REG_SPORT0_CNVT_B)               /*  Half SPORT 'B' CNV Width */
+#define pREG_SPORT0_TX_B                 ((__O      uint32_t  *) REG_SPORT0_TX_B)                 /*  Half SPORT 'B' Tx Buffer */
+#define pREG_SPORT0_RX_B                 ((__I __C  uint32_t  *) REG_SPORT0_RX_B)                 /*  Half SPORT 'B' Rx Buffer */
+
+/*  =================================================================================
+ *      CRC Accelerator (CRC0)
+ *  ================================================================================= */
+#define pREG_CRC0_CTL                    ((__IO     uint32_t  *) REG_CRC0_CTL)                    /*  CRC Control */
+#define pREG_CRC0_IPDATA                 ((__O      uint32_t  *) REG_CRC0_IPDATA)                 /*  Input Data Word */
+#define pREG_CRC0_RESULT                 ((__IO     uint32_t  *) REG_CRC0_RESULT)                 /*  CRC Result */
+#define pREG_CRC0_POLY                   ((__IO     uint32_t  *) REG_CRC0_POLY)                   /*  Programmable CRC Polynomial */
+#define pREG_CRC0_IPBYTE                 ((__O      uint8_t   *) REG_CRC0_IPBYTE)                 /*  Input Data Byte */
+#define pREG_CRC0_IPBITS0                ((__O      uint8_t   *) REG_CRC0_IPBITS0)                /*  Input Data Bits */
+#define pREG_CRC0_IPBITS1                ((__O      uint8_t   *) REG_CRC0_IPBITS1)                /*  Input Data Bits */
+#define pREG_CRC0_IPBITS2                ((__O      uint8_t   *) REG_CRC0_IPBITS2)                /*  Input Data Bits */
+#define pREG_CRC0_IPBITS3                ((__O      uint8_t   *) REG_CRC0_IPBITS3)                /*  Input Data Bits */
+#define pREG_CRC0_IPBITS4                ((__O      uint8_t   *) REG_CRC0_IPBITS4)                /*  Input Data Bits */
+#define pREG_CRC0_IPBITS5                ((__O      uint8_t   *) REG_CRC0_IPBITS5)                /*  Input Data Bits */
+#define pREG_CRC0_IPBITS6                ((__O      uint8_t   *) REG_CRC0_IPBITS6)                /*  Input Data Bits */
+#define pREG_CRC0_IPBITS7                ((__O      uint8_t   *) REG_CRC0_IPBITS7)                /*  Input Data Bits */
+
+/*  =================================================================================
+ *      Random Number Generator (RNG0)
+ *  ================================================================================= */
+#define pREG_RNG0_CTL                    ((__IO     uint16_t  *) REG_RNG0_CTL)                    /*  RNG Control Register */
+#define pREG_RNG0_LEN                    ((__IO     uint16_t  *) REG_RNG0_LEN)                    /*  RNG Sample Length Register */
+#define pREG_RNG0_STAT                   ((__IO     uint16_t  *) REG_RNG0_STAT)                   /*  RNG Status Register */
+#define pREG_RNG0_DATA                   ((__I __C  uint32_t  *) REG_RNG0_DATA)                   /*  RNG Data Register */
+#define pREG_RNG0_OSCCNT                 ((__I __C  uint32_t  *) REG_RNG0_OSCCNT)                 /*  Oscillator Count */
+#define pREG_RNG0_OSCDIFF0               ((__I __C  int8_t    *) REG_RNG0_OSCDIFF0)               /*  Oscillator Difference */
+#define pREG_RNG0_OSCDIFF1               ((__I __C  int8_t    *) REG_RNG0_OSCDIFF1)               /*  Oscillator Difference */
+#define pREG_RNG0_OSCDIFF2               ((__I __C  int8_t    *) REG_RNG0_OSCDIFF2)               /*  Oscillator Difference */
+#define pREG_RNG0_OSCDIFF3               ((__I __C  int8_t    *) REG_RNG0_OSCDIFF3)               /*  Oscillator Difference */
+
+/*  =================================================================================
+ *      Register Map for the Crypto Block (CRYPT0)
+ *  ================================================================================= */
+#define pREG_CRYPT0_CFG                  ((__IO     uint32_t  *) REG_CRYPT0_CFG)                  /*  Configuration Register */
+#define pREG_CRYPT0_DATALEN              ((__IO     uint32_t  *) REG_CRYPT0_DATALEN)              /*  Payload Data Length */
+#define pREG_CRYPT0_PREFIXLEN            ((__IO     uint32_t  *) REG_CRYPT0_PREFIXLEN)            /*  Authentication Data Length */
+#define pREG_CRYPT0_INTEN                ((__IO     uint32_t  *) REG_CRYPT0_INTEN)                /*  Interrupt Enable Register */
+#define pREG_CRYPT0_STAT                 ((__IO     uint32_t  *) REG_CRYPT0_STAT)                 /*  Status Register */
+#define pREG_CRYPT0_INBUF                ((__O      uint32_t  *) REG_CRYPT0_INBUF)                /*  Input Buffer */
+#define pREG_CRYPT0_OUTBUF               ((__I __C  uint32_t  *) REG_CRYPT0_OUTBUF)               /*  Output Buffer */
+#define pREG_CRYPT0_NONCE0               ((__IO     uint32_t  *) REG_CRYPT0_NONCE0)               /*  Nonce Bits [31:0] */
+#define pREG_CRYPT0_NONCE1               ((__IO     uint32_t  *) REG_CRYPT0_NONCE1)               /*  Nonce Bits [63:32] */
+#define pREG_CRYPT0_NONCE2               ((__IO     uint32_t  *) REG_CRYPT0_NONCE2)               /*  Nonce Bits [95:64] */
+#define pREG_CRYPT0_NONCE3               ((__IO     uint32_t  *) REG_CRYPT0_NONCE3)               /*  Nonce Bits [127:96] */
+#define pREG_CRYPT0_AESKEY0              ((__O      uint32_t  *) REG_CRYPT0_AESKEY0)              /*  AES Key Bits [31:0] */
+#define pREG_CRYPT0_AESKEY1              ((__O      uint32_t  *) REG_CRYPT0_AESKEY1)              /*  AES Key Bits [63:32] */
+#define pREG_CRYPT0_AESKEY2              ((__O      uint32_t  *) REG_CRYPT0_AESKEY2)              /*  AES Key Bits [95:64] */
+#define pREG_CRYPT0_AESKEY3              ((__O      uint32_t  *) REG_CRYPT0_AESKEY3)              /*  AES Key Bits [127:96] */
+#define pREG_CRYPT0_AESKEY4              ((__O      uint32_t  *) REG_CRYPT0_AESKEY4)              /*  AES Key Bits [159:128] */
+#define pREG_CRYPT0_AESKEY5              ((__O      uint32_t  *) REG_CRYPT0_AESKEY5)              /*  AES Key Bits [191:160] */
+#define pREG_CRYPT0_AESKEY6              ((__O      uint32_t  *) REG_CRYPT0_AESKEY6)              /*  AES Key Bits [223:192] */
+#define pREG_CRYPT0_AESKEY7              ((__O      uint32_t  *) REG_CRYPT0_AESKEY7)              /*  AES Key Bits [255:224] */
+#define pREG_CRYPT0_CNTRINIT             ((__IO     uint32_t  *) REG_CRYPT0_CNTRINIT)             /*  Counter Initialization Vector */
+#define pREG_CRYPT0_SHAH0                ((__IO     uint32_t  *) REG_CRYPT0_SHAH0)                /*  SHA Bits [31:0] */
+#define pREG_CRYPT0_SHAH1                ((__IO     uint32_t  *) REG_CRYPT0_SHAH1)                /*  SHA Bits [63:32] */
+#define pREG_CRYPT0_SHAH2                ((__IO     uint32_t  *) REG_CRYPT0_SHAH2)                /*  SHA Bits [95:64] */
+#define pREG_CRYPT0_SHAH3                ((__IO     uint32_t  *) REG_CRYPT0_SHAH3)                /*  SHA Bits [127:96] */
+#define pREG_CRYPT0_SHAH4                ((__IO     uint32_t  *) REG_CRYPT0_SHAH4)                /*  SHA Bits [159:128] */
+#define pREG_CRYPT0_SHAH5                ((__IO     uint32_t  *) REG_CRYPT0_SHAH5)                /*  SHA Bits [191:160] */
+#define pREG_CRYPT0_SHAH6                ((__IO     uint32_t  *) REG_CRYPT0_SHAH6)                /*  SHA Bits [223:192] */
+#define pREG_CRYPT0_SHAH7                ((__IO     uint32_t  *) REG_CRYPT0_SHAH7)                /*  SHA Bits [255:224] */
+#define pREG_CRYPT0_SHA_LAST_WORD        ((__IO     uint32_t  *) REG_CRYPT0_SHA_LAST_WORD)        /*  SHA Last Word and Valid Bits Information */
+#define pREG_CRYPT0_CCM_NUM_VALID_BYTES  ((__IO     uint32_t  *) REG_CRYPT0_CCM_NUM_VALID_BYTES)  /*  NUM_VALID_BYTES */
+
+/*  =================================================================================
+ *      Power Management  (PMG0)
+ *  ================================================================================= */
+#define pREG_PMG0_IEN                    ((__IO     uint32_t  *) REG_PMG0_IEN)                    /*  Power Supply Monitor Interrupt Enable */
+#define pREG_PMG0_PSM_STAT               ((__IO     uint32_t  *) REG_PMG0_PSM_STAT)               /*  Power Supply Monitor Status */
+#define pREG_PMG0_PWRMOD                 ((__IO     uint32_t  *) REG_PMG0_PWRMOD)                 /*  Power Mode Register */
+#define pREG_PMG0_PWRKEY                 ((__O      uint32_t  *) REG_PMG0_PWRKEY)                 /*  Key Protection for PWRMOD and SRAMRET */
+#define pREG_PMG0_SHDN_STAT              ((__I __C  uint32_t  *) REG_PMG0_SHDN_STAT)              /*  Shutdown Status Register */
+#define pREG_PMG0_SRAMRET                ((__IO     uint32_t  *) REG_PMG0_SRAMRET)                /*  Control for Retention SRAM in Hibernate Mode */
+#define pREG_PMG0_RST_STAT               ((__IO     uint32_t  *) REG_PMG0_RST_STAT)               /*  Reset Status */
+#define pREG_PMG0_CTL1                   ((__IO     uint32_t  *) REG_PMG0_CTL1)                   /*  HP Buck Control */
+
+/*  =================================================================================
+ *      External interrupt configuration (XINT0)
+ *  ================================================================================= */
+#define pREG_XINT0_CFG0                  ((__IO     uint32_t  *) REG_XINT0_CFG0)                  /*  External Interrupt Configuration */
+#define pREG_XINT0_EXT_STAT              ((__I __C  uint32_t  *) REG_XINT0_EXT_STAT)              /*  External Wakeup Interrupt Status */
+#define pREG_XINT0_CLR                   ((__IO     uint32_t  *) REG_XINT0_CLR)                   /*  External Interrupt Clear */
+#define pREG_XINT0_NMICLR                ((__IO     uint32_t  *) REG_XINT0_NMICLR)                /*  Non-Maskable Interrupt Clear */
+
+/*  =================================================================================
+ *      Clocking  (CLKG0_OSC)
+ *  ================================================================================= */
+#define pREG_CLKG0_OSC_KEY               ((__O      uint32_t  *) REG_CLKG0_OSC_KEY)               /*  Key Protection for CLKG_OSC_CTL */
+#define pREG_CLKG0_OSC_CTL               ((__IO     uint32_t  *) REG_CLKG0_OSC_CTL)               /*  Oscillator Control */
+
+/*  =================================================================================
+ *      Power Management  (PMG0_TST)
+ *  ================================================================================= */
+#define pREG_PMG0_TST_SRAM_CTL           ((__IO     uint32_t  *) REG_PMG0_TST_SRAM_CTL)           /*  Control for SRAM Parity and Instruction SRAM */
+#define pREG_PMG0_TST_SRAM_INITSTAT      ((__IO     uint32_t  *) REG_PMG0_TST_SRAM_INITSTAT)      /*  Initialization Status Register */
+#define pREG_PMG0_TST_CLR_LATCH_GPIOS    ((__O      uint16_t  *) REG_PMG0_TST_CLR_LATCH_GPIOS)    /*  Clear GPIO After Shutdown Mode */
+#define pREG_PMG0_TST_SCRPAD_IMG         ((__IO     uint32_t  *) REG_PMG0_TST_SCRPAD_IMG)         /*  Scratch Pad Image */
+#define pREG_PMG0_TST_SCRPAD_3V_RD       ((__I __C  uint32_t  *) REG_PMG0_TST_SCRPAD_3V_RD)       /*  Scratch Pad Saved in Battery Domain */
+
+/*  =================================================================================
+ *      Clocking  (CLKG0_CLK)
+ *  ================================================================================= */
+#define pREG_CLKG0_CLK_CTL0              ((__IO     uint32_t  *) REG_CLKG0_CLK_CTL0)              /*  Miscellaneous Clock Settings */
+#define pREG_CLKG0_CLK_CTL1              ((__IO     uint32_t  *) REG_CLKG0_CLK_CTL1)              /*  Clock Dividers */
+#define pREG_CLKG0_CLK_CTL3              ((__IO     uint32_t  *) REG_CLKG0_CLK_CTL3)              /*  System PLL */
+#define pREG_CLKG0_CLK_CTL5              ((__IO     uint32_t  *) REG_CLKG0_CLK_CTL5)              /*  User Clock Gating Control */
+#define pREG_CLKG0_CLK_STAT0             ((__IO     uint32_t  *) REG_CLKG0_CLK_STAT0)             /*  Clocking Status */
+
+/*  =================================================================================
+ *      Bus matrix (BUSM0)
+ *  ================================================================================= */
+#define pREG_BUSM0_ARBIT0                ((__IO     uint32_t  *) REG_BUSM0_ARBIT0)                /*  Arbitration Priority Configuration for FLASH and SRAM0 */
+#define pREG_BUSM0_ARBIT1                ((__IO     uint32_t  *) REG_BUSM0_ARBIT1)                /*  Arbitration Priority Configuration for SRAM1 and SIP */
+#define pREG_BUSM0_ARBIT2                ((__IO     uint32_t  *) REG_BUSM0_ARBIT2)                /*  Arbitration Priority Configuration for APB32 and APB16 */
+#define pREG_BUSM0_ARBIT3                ((__IO     uint32_t  *) REG_BUSM0_ARBIT3)                /*  Arbitration Priority Configuration for APB16 priority for core and for DMA1 */
+
+/*  =================================================================================
+ *      Parallel Test Interface (PTI0)
+ *  ================================================================================= */
+#define pREG_PTI0_RST_ISR_STARTADDR      ((__IO     uint32_t  *) REG_PTI0_RST_ISR_STARTADDR)      /*  Reset ISR Start Address */
+#define pREG_PTI0_RST_STACK_PTR          ((__IO     uint32_t  *) REG_PTI0_RST_STACK_PTR)          /*  Reset Stack Pointer */
+#define pREG_PTI0_CTL                    ((__IO     uint32_t  *) REG_PTI0_CTL)                    /*  Parallel Test Interface Control Register */
+
+/*  =================================================================================
+ *      Cortex-M3 Interrupt Controller (NVIC0)
+ *  ================================================================================= */
+#define pREG_NVIC0_INTNUM                ((__IO     uint32_t  *) REG_NVIC0_INTNUM)                /*  Interrupt Control Type */
+#define pREG_NVIC0_STKSTA                ((__IO     uint32_t  *) REG_NVIC0_STKSTA)                /*  Systick Control and Status */
+#define pREG_NVIC0_STKLD                 ((__IO     uint32_t  *) REG_NVIC0_STKLD)                 /*  Systick Reload Value */
+#define pREG_NVIC0_STKVAL                ((__IO     uint32_t  *) REG_NVIC0_STKVAL)                /*  Systick Current Value */
+#define pREG_NVIC0_STKCAL                ((__IO     uint32_t  *) REG_NVIC0_STKCAL)                /*  Systick Calibration Value */
+#define pREG_NVIC0_INTSETE0              ((__IO     uint32_t  *) REG_NVIC0_INTSETE0)              /*  IRQ0..31 Set_Enable */
+#define pREG_NVIC0_INTSETE1              ((__IO     uint32_t  *) REG_NVIC0_INTSETE1)              /*  IRQ32..63 Set_Enable */
+#define pREG_NVIC0_INTCLRE0              ((__IO     uint32_t  *) REG_NVIC0_INTCLRE0)              /*  IRQ0..31 Clear_Enable */
+#define pREG_NVIC0_INTCLRE1              ((__IO     uint32_t  *) REG_NVIC0_INTCLRE1)              /*  IRQ32..63 Clear_Enable */
+#define pREG_NVIC0_INTSETP0              ((__IO     uint32_t  *) REG_NVIC0_INTSETP0)              /*  IRQ0..31 Set_Pending */
+#define pREG_NVIC0_INTSETP1              ((__IO     uint32_t  *) REG_NVIC0_INTSETP1)              /*  IRQ32..63 Set_Pending */
+#define pREG_NVIC0_INTCLRP0              ((__IO     uint32_t  *) REG_NVIC0_INTCLRP0)              /*  IRQ0..31 Clear_Pending */
+#define pREG_NVIC0_INTCLRP1              ((__IO     uint32_t  *) REG_NVIC0_INTCLRP1)              /*  IRQ32..63 Clear_Pending */
+#define pREG_NVIC0_INTACT0               ((__IO     uint32_t  *) REG_NVIC0_INTACT0)               /*  IRQ0..31 Active Bit */
+#define pREG_NVIC0_INTACT1               ((__IO     uint32_t  *) REG_NVIC0_INTACT1)               /*  IRQ32..63 Active Bit */
+#define pREG_NVIC0_INTPRI0               ((__IO     uint32_t  *) REG_NVIC0_INTPRI0)               /*  IRQ0..3 Priority */
+#define pREG_NVIC0_INTPRI1               ((__IO     uint32_t  *) REG_NVIC0_INTPRI1)               /*  IRQ4..7 Priority */
+#define pREG_NVIC0_INTPRI2               ((__IO     uint32_t  *) REG_NVIC0_INTPRI2)               /*  IRQ8..11 Priority */
+#define pREG_NVIC0_INTPRI3               ((__IO     uint32_t  *) REG_NVIC0_INTPRI3)               /*  IRQ12..15 Priority */
+#define pREG_NVIC0_INTPRI4               ((__IO     uint32_t  *) REG_NVIC0_INTPRI4)               /*  IRQ16..19 Priority */
+#define pREG_NVIC0_INTPRI5               ((__IO     uint32_t  *) REG_NVIC0_INTPRI5)               /*  IRQ20..23 Priority */
+#define pREG_NVIC0_INTPRI6               ((__IO     uint32_t  *) REG_NVIC0_INTPRI6)               /*  IRQ24..27 Priority */
+#define pREG_NVIC0_INTPRI7               ((__IO     uint32_t  *) REG_NVIC0_INTPRI7)               /*  IRQ28..31 Priority */
+#define pREG_NVIC0_INTPRI8               ((__IO     uint32_t  *) REG_NVIC0_INTPRI8)               /*  IRQ32..35 Priority */
+#define pREG_NVIC0_INTPRI9               ((__IO     uint32_t  *) REG_NVIC0_INTPRI9)               /*  IRQ36..39 Priority */
+#define pREG_NVIC0_INTPRI10              ((__IO     uint32_t  *) REG_NVIC0_INTPRI10)              /*  IRQ40..43 Priority */
+#define pREG_NVIC0_INTCPID               ((__IO     uint32_t  *) REG_NVIC0_INTCPID)               /*  CPUID Base */
+#define pREG_NVIC0_INTSTA                ((__IO     uint32_t  *) REG_NVIC0_INTSTA)                /*  Interrupt Control State */
+#define pREG_NVIC0_INTVEC                ((__IO     uint32_t  *) REG_NVIC0_INTVEC)                /*  Vector Table Offset */
+#define pREG_NVIC0_INTAIRC               ((__IO     uint32_t  *) REG_NVIC0_INTAIRC)               /*  Application Interrupt/Reset Control */
+#define pREG_NVIC0_INTCON0               ((__IO     uint16_t  *) REG_NVIC0_INTCON0)               /*  System Control */
+#define pREG_NVIC0_INTCON1               ((__IO     uint32_t  *) REG_NVIC0_INTCON1)               /*  Configuration Control */
+#define pREG_NVIC0_INTSHPRIO0            ((__IO     uint32_t  *) REG_NVIC0_INTSHPRIO0)            /*  System Handlers 4-7 Priority */
+#define pREG_NVIC0_INTSHPRIO1            ((__IO     uint32_t  *) REG_NVIC0_INTSHPRIO1)            /*  System Handlers 8-11 Priority */
+#define pREG_NVIC0_INTSHPRIO3            ((__IO     uint32_t  *) REG_NVIC0_INTSHPRIO3)            /*  System Handlers 12-15 Priority */
+#define pREG_NVIC0_INTSHCSR              ((__IO     uint32_t  *) REG_NVIC0_INTSHCSR)              /*  System Handler Control and State */
+#define pREG_NVIC0_INTCFSR               ((__IO     uint32_t  *) REG_NVIC0_INTCFSR)               /*  Configurable Fault Status */
+#define pREG_NVIC0_INTHFSR               ((__IO     uint32_t  *) REG_NVIC0_INTHFSR)               /*  Hard Fault Status */
+#define pREG_NVIC0_INTDFSR               ((__IO     uint32_t  *) REG_NVIC0_INTDFSR)               /*  Debug Fault Status */
+#define pREG_NVIC0_INTMMAR               ((__IO     uint32_t  *) REG_NVIC0_INTMMAR)               /*  Mem Manage Address */
+#define pREG_NVIC0_INTBFAR               ((__IO     uint32_t  *) REG_NVIC0_INTBFAR)               /*  Bus Fault Address */
+#define pREG_NVIC0_INTAFSR               ((__IO     uint32_t  *) REG_NVIC0_INTAFSR)               /*  Auxiliary Fault Status */
+#define pREG_NVIC0_INTPFR0               ((__IO     uint32_t  *) REG_NVIC0_INTPFR0)               /*  Processor Feature Register 0 */
+#define pREG_NVIC0_INTPFR1               ((__IO     uint32_t  *) REG_NVIC0_INTPFR1)               /*  Processor Feature Register 1 */
+#define pREG_NVIC0_INTDFR0               ((__IO     uint32_t  *) REG_NVIC0_INTDFR0)               /*  Debug Feature Register 0 */
+#define pREG_NVIC0_INTAFR0               ((__IO     uint32_t  *) REG_NVIC0_INTAFR0)               /*  Auxiliary Feature Register 0 */
+#define pREG_NVIC0_INTMMFR0              ((__IO     uint32_t  *) REG_NVIC0_INTMMFR0)              /*  Memory Model Feature Register 0 */
+#define pREG_NVIC0_INTMMFR1              ((__IO     uint32_t  *) REG_NVIC0_INTMMFR1)              /*  Memory Model Feature Register 1 */
+#define pREG_NVIC0_INTMMFR2              ((__IO     uint32_t  *) REG_NVIC0_INTMMFR2)              /*  Memory Model Feature Register 2 */
+#define pREG_NVIC0_INTMMFR3              ((__IO     uint32_t  *) REG_NVIC0_INTMMFR3)              /*  Memory Model Feature Register 3 */
+#define pREG_NVIC0_INTISAR0              ((__IO     uint32_t  *) REG_NVIC0_INTISAR0)              /*  ISA Feature Register 0 */
+#define pREG_NVIC0_INTISAR1              ((__IO     uint32_t  *) REG_NVIC0_INTISAR1)              /*  ISA Feature Register 1 */
+#define pREG_NVIC0_INTISAR2              ((__IO     uint32_t  *) REG_NVIC0_INTISAR2)              /*  ISA Feature Register 2 */
+#define pREG_NVIC0_INTISAR3              ((__IO     uint32_t  *) REG_NVIC0_INTISAR3)              /*  ISA Feature Register 3 */
+#define pREG_NVIC0_INTISAR4              ((__IO     uint32_t  *) REG_NVIC0_INTISAR4)              /*  ISA Feature Register 4 */
+#define pREG_NVIC0_INTTRGI               ((__IO     uint32_t  *) REG_NVIC0_INTTRGI)               /*  Software Trigger Interrupt Register */
+#define pREG_NVIC0_INTPID4               ((__IO     uint32_t  *) REG_NVIC0_INTPID4)               /*  Peripheral Identification Register 4 */
+#define pREG_NVIC0_INTPID5               ((__IO     uint32_t  *) REG_NVIC0_INTPID5)               /*  Peripheral Identification Register 5 */
+#define pREG_NVIC0_INTPID6               ((__IO     uint32_t  *) REG_NVIC0_INTPID6)               /*  Peripheral Identification Register 6 */
+#define pREG_NVIC0_INTPID7               ((__IO     uint32_t  *) REG_NVIC0_INTPID7)               /*  Peripheral Identification Register 7 */
+#define pREG_NVIC0_INTPID0               ((__IO     uint32_t  *) REG_NVIC0_INTPID0)               /*  Peripheral Identification Bits7:0 */
+#define pREG_NVIC0_INTPID1               ((__IO     uint32_t  *) REG_NVIC0_INTPID1)               /*  Peripheral Identification Bits15:8 */
+#define pREG_NVIC0_INTPID2               ((__IO     uint32_t  *) REG_NVIC0_INTPID2)               /*  Peripheral Identification Bits16:23 */
+#define pREG_NVIC0_INTPID3               ((__IO     uint32_t  *) REG_NVIC0_INTPID3)               /*  Peripheral Identification Bits24:31 */
+#define pREG_NVIC0_INTCID0               ((__IO     uint32_t  *) REG_NVIC0_INTCID0)               /*  Component Identification Bits7:0 */
+#define pREG_NVIC0_INTCID1               ((__IO     uint32_t  *) REG_NVIC0_INTCID1)               /*  Component Identification Bits15:8 */
+#define pREG_NVIC0_INTCID2               ((__IO     uint32_t  *) REG_NVIC0_INTCID2)               /*  Component Identification Bits16:23 */
+#define pREG_NVIC0_INTCID3               ((__IO     uint32_t  *) REG_NVIC0_INTCID3)               /*  Component Identification Bits24:31 */
+
+#if defined (_MISRA_RULES)
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+
+#endif
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_device.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_device.h
new file mode 100755
index 00000000000..08c509962b8
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_device.h
@@ -0,0 +1,1206 @@
+/* ================================================================================
+
+     Project      :   ADuCM302x
+     File         :   ADuCM302x_device.h
+     Description  :   C Register Definitions
+
+     Date         :   Feb 6, 2017
+
+     Copyright (c) 2014-2017 Analog Devices, Inc.  All Rights Reserved.
+     This software is proprietary and confidential to Analog Devices, Inc. and
+     its licensors.
+
+     This file was auto-generated. Do not make local changes to this file.
+
+   ================================================================================ */
+
+#ifndef _ADUCM302X_DEVICE_H
+#define _ADUCM302X_DEVICE_H
+
+/* pickup integer types */
+#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__))
+#include <stdint.h>
+#endif /* _LANGUAGE_C */
+
+/* pickup register bitfield and bit masks */
+#include "ADuCM302x_typedefs.h"
+
+#ifndef __IO
+#ifdef __cplusplus
+#define     __I     volatile      /* read-only */
+#define     __C
+#else
+#define     __I     volatile      /* read-only */
+#define     __C     const
+#endif
+#define     __O     volatile      /* write-only */
+#define     __IO    volatile      /* read-write */
+#endif
+
+#if defined (_MISRA_RULES)
+/*
+  anonymous unions violate ISO 9899:1990 and therefore MISRA Rule 1.1.
+  Use of unions violates MISRA Rule 18.4.
+  Anonymous unions are required for this implementation.
+  Re-use of identifiers violates MISRA Rule 5.7.
+  Field names are repeated for the ADuCM302x register map.
+*/
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_1_1:"Allow anonymous unions")
+#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit")
+#pragma diag(suppress:misra_rule_5_3:"Header will re-use typedef identifiers")
+#pragma diag(suppress:misra_rule_5_6:"Header will re-use identifiers in the same scope")
+#pragma diag(suppress:misra_rule_5_7:"Header will re-use identifiers")
+#pragma diag(suppress:misra_rule_18_4:"Allow the use of a union")
+#endif /* _MISRA_RULES */
+
+/** @defgroup TMR General Purpose Timer (TMR) Module
+ *  General Purpose Timer
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_TMR_TypeDef
+ *  \brief  General Purpose Timer
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_TypeDef__
+typedef struct _ADI_TMR_TypeDef
+{
+    __IO     uint16_t   LOAD;                          /*!< 16-bit Load Value */
+    __I __C  uint8_t  RESERVED0[2];
+    __I __C  uint16_t   CURCNT;                        /*!< 16-bit Timer Value */
+    __I __C  uint8_t  RESERVED1[2];
+    __IO     uint16_t   CTL;                           /*!< Control */
+    __I __C  uint8_t  RESERVED2[2];
+    __O      uint16_t   CLRINT;                        /*!< Clear Interrupt */
+    __I __C  uint8_t  RESERVED3[2];
+    __I __C  uint16_t   CAPTURE;                       /*!< Capture */
+    __I __C  uint8_t  RESERVED4[2];
+    __IO     uint16_t   ALOAD;                         /*!< 16-bit Load Value, Asynchronous */
+    __I __C  uint8_t  RESERVED5[2];
+    __I __C  uint16_t   ACURCNT;                       /*!< 16-bit Timer Value, Asynchronous */
+    __I __C  uint8_t  RESERVED6[2];
+    __I __C  uint16_t   STAT;                          /*!< Status */
+    __I __C  uint8_t  RESERVED7[2];
+    __IO     uint16_t   PWMCTL;                        /*!< PWM Control Register */
+    __I __C  uint8_t  RESERVED8[2];
+    __IO     uint16_t   PWMMATCH;                      /*!< PWM Match Value */
+} ADI_TMR_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup RTC Real-Time Clock (RTC) Module
+ *  Real-Time Clock
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_RTC_TypeDef
+ *  \brief  Real-Time Clock
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_TypeDef__
+typedef struct _ADI_RTC_TypeDef
+{
+    __IO     uint16_t   CR0;                           /*!< RTC Control 0 */
+    __I __C  uint8_t  RESERVED0[2];
+    __IO     uint16_t   SR0;                           /*!< RTC Status 0 */
+    __I __C  uint8_t  RESERVED1[2];
+    __I __C  uint16_t   SR1;                           /*!< RTC Status 1 */
+    __I __C  uint8_t  RESERVED2[2];
+    __IO     uint16_t   CNT0;                          /*!< RTC Count 0 */
+    __I __C  uint8_t  RESERVED3[2];
+    __IO     uint16_t   CNT1;                          /*!< RTC Count 1 */
+    __I __C  uint8_t  RESERVED4[2];
+    __IO     uint16_t   ALM0;                          /*!< RTC Alarm 0 */
+    __I __C  uint8_t  RESERVED5[2];
+    __IO     uint16_t   ALM1;                          /*!< RTC Alarm 1 */
+    __I __C  uint8_t  RESERVED6[2];
+    __IO     uint16_t   TRM;                           /*!< RTC Trim */
+    __I __C  uint8_t  RESERVED7[2];
+    __O      uint16_t   GWY;                           /*!< RTC Gateway */
+    __I __C  uint8_t  RESERVED8[6];
+    __IO     uint16_t   CR1;                           /*!< RTC Control 1 */
+    __I __C  uint8_t  RESERVED9[2];
+    __IO     uint16_t   SR2;                           /*!< RTC Status 2 */
+    __I __C  uint8_t  RESERVED10[2];
+    __I __C  uint16_t   SNAP0;                         /*!< RTC Snapshot 0 */
+    __I __C  uint8_t  RESERVED11[2];
+    __I __C  uint16_t   SNAP1;                         /*!< RTC Snapshot 1 */
+    __I __C  uint8_t  RESERVED12[2];
+    __I __C  uint16_t   SNAP2;                         /*!< RTC Snapshot 2 */
+    __I __C  uint8_t  RESERVED13[2];
+    __I __C  uint16_t   MOD;                           /*!< RTC Modulo */
+    __I __C  uint8_t  RESERVED14[2];
+    __I __C  uint16_t   CNT2;                          /*!< RTC Count 2 */
+    __I __C  uint8_t  RESERVED15[2];
+    __IO     uint16_t   ALM2;                          /*!< RTC Alarm 2 */
+    __I __C  uint8_t  RESERVED16[2];
+    __IO     uint16_t   SR3;                           /*!< RTC Status 3 */
+    __I __C  uint8_t  RESERVED17[2];
+    __IO     uint16_t   CR2IC;                         /*!< RTC Control 2 for Configuring Input Capture Channels */
+    __I __C  uint8_t  RESERVED18[2];
+    __IO     uint16_t   CR3SS;                         /*!< RTC Control 3 for Configuring SensorStrobe Channel */
+    __I __C  uint8_t  RESERVED19[2];
+    __IO     uint16_t   CR4SS;                         /*!< RTC Control 4 for Configuring SensorStrobe Channel */
+    __I __C  uint8_t  RESERVED20[2];
+    __IO     uint16_t   SSMSK;                         /*!< RTC Mask for SensorStrobe Channel */
+    __I __C  uint8_t  RESERVED21[2];
+    __IO     uint16_t   SS1ARL;                        /*!< RTC Auto-Reload for SensorStrobe Channel 1 */
+    __I __C  uint8_t  RESERVED22[6];
+    __I __C  uint16_t   IC2;                           /*!< RTC Input Capture Channel 2 */
+    __I __C  uint8_t  RESERVED23[2];
+    __I __C  uint16_t   IC3;                           /*!< RTC Input Capture Channel 3 */
+    __I __C  uint8_t  RESERVED24[2];
+    __I __C  uint16_t   IC4;                           /*!< RTC Input Capture Channel 4 */
+    __I __C  uint8_t  RESERVED25[2];
+    __IO     uint16_t   SS1;                           /*!< RTC SensorStrobe Channel 1 */
+    __I __C  uint8_t  RESERVED26[14];
+    __I __C  uint16_t   SR4;                           /*!< RTC Status 4 */
+    __I __C  uint8_t  RESERVED27[2];
+    __I __C  uint16_t   SR5;                           /*!< RTC Status 5 */
+    __I __C  uint8_t  RESERVED28[2];
+    __I __C  uint16_t   SR6;                           /*!< RTC Status 6 */
+    __I __C  uint8_t  RESERVED29[2];
+    __I __C  uint16_t   SS1TGT;                        /*!< RTC SensorStrobe Channel 1 Target */
+    __I __C  uint8_t  RESERVED30[2];
+    __I __C  uint16_t   FRZCNT;                        /*!< RTC Freeze Count */
+} ADI_RTC_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup SYS System Identification and Debug Enable (SYS) Module
+ *  System Identification and Debug Enable
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_SYS_TypeDef
+ *  \brief  System Identification and Debug Enable
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SYS_TypeDef__
+typedef struct _ADI_SYS_TypeDef
+{
+    __I __C  uint8_t  RESERVED0[32];
+    __I __C  uint16_t   ADIID;                         /*!< ADI Identification */
+    __I __C  uint8_t  RESERVED1[2];
+    __I __C  uint16_t   CHIPID;                        /*!< Chip Identifier */
+    __I __C  uint8_t  RESERVED2[26];
+    __O      uint16_t   SWDEN;                         /*!< Serial Wire Debug Enable */
+} ADI_SYS_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SYS_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup WDT Watchdog Timer (WDT) Module
+ *  Watchdog Timer
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_WDT_TypeDef
+ *  \brief  Watchdog Timer
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_TypeDef__
+typedef struct _ADI_WDT_TypeDef
+{
+    __IO     uint16_t   LOAD;                          /*!< Load Value */
+    __I __C  uint8_t  RESERVED0[2];
+    __I __C  uint16_t   CCNT;                          /*!< Current Count Value */
+    __I __C  uint8_t  RESERVED1[2];
+    __IO     uint16_t   CTL;                           /*!< Control */
+    __I __C  uint8_t  RESERVED2[2];
+    __O      uint16_t   RESTART;                       /*!< Clear Interrupt */
+    __I __C  uint8_t  RESERVED3[10];
+    __I __C  uint16_t   STAT;                          /*!< Status */
+} ADI_WDT_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup I2C I2C Master/Slave (I2C) Module
+ *  I2C Master/Slave
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_I2C_TypeDef
+ *  \brief  I2C Master/Slave
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_TypeDef__
+typedef struct _ADI_I2C_TypeDef
+{
+    __IO     uint16_t   MCTL;                          /*!< Master Control */
+    __I __C  uint8_t  RESERVED0[2];
+    __IO     uint16_t   MSTAT;                         /*!< Master Status */
+    __I __C  uint8_t  RESERVED1[2];
+    __I __C  uint16_t   MRX;                           /*!< Master Receive Data */
+    __I __C  uint8_t  RESERVED2[2];
+    __IO     uint16_t   MTX;                           /*!< Master Transmit Data */
+    __I __C  uint8_t  RESERVED3[2];
+    __IO     uint16_t   MRXCNT;                        /*!< Master Receive Data Count */
+    __I __C  uint8_t  RESERVED4[2];
+    __I __C  uint16_t   MCRXCNT;                       /*!< Master Current Receive Data Count */
+    __I __C  uint8_t  RESERVED5[2];
+    __IO     uint16_t   ADDR1;                         /*!< Master Address Byte 1 */
+    __I __C  uint8_t  RESERVED6[2];
+    __IO     uint16_t   ADDR2;                         /*!< Master Address Byte 2 */
+    __I __C  uint8_t  RESERVED7[2];
+    __IO     uint16_t   BYT;                           /*!< Start Byte */
+    __I __C  uint8_t  RESERVED8[2];
+    __IO     uint16_t   DIV;                           /*!< Serial Clock Period Divisor */
+    __I __C  uint8_t  RESERVED9[2];
+    __IO     uint16_t   SCTL;                          /*!< Slave Control */
+    __I __C  uint8_t  RESERVED10[2];
+    __IO     uint16_t   SSTAT;                         /*!< Slave I2C Status/Error/IRQ */
+    __I __C  uint8_t  RESERVED11[2];
+    __I __C  uint16_t   SRX;                           /*!< Slave Receive */
+    __I __C  uint8_t  RESERVED12[2];
+    __IO     uint16_t   STX;                           /*!< Slave Transmit */
+    __I __C  uint8_t  RESERVED13[2];
+    __IO     uint16_t   ALT;                           /*!< Hardware General Call ID */
+    __I __C  uint8_t  RESERVED14[2];
+    __IO     uint16_t   ID0;                           /*!< First Slave Address Device ID */
+    __I __C  uint8_t  RESERVED15[2];
+    __IO     uint16_t   ID1;                           /*!< Second Slave Address Device ID */
+    __I __C  uint8_t  RESERVED16[2];
+    __IO     uint16_t   ID2;                           /*!< Third Slave Address Device ID */
+    __I __C  uint8_t  RESERVED17[2];
+    __IO     uint16_t   ID3;                           /*!< Fourth Slave Address Device ID */
+    __I __C  uint8_t  RESERVED18[2];
+    __IO     uint16_t   STAT;                          /*!< Master and Slave FIFO Status */
+    __I __C  uint8_t  RESERVED19[2];
+    __O      uint16_t   SHCTL;                         /*!< Shared Control */
+    __I __C  uint8_t  RESERVED20[2];
+    __IO     uint16_t   TCTL;                          /*!< Timing Control Register */
+    __I __C  uint8_t  RESERVED21[2];
+    __IO     uint16_t   ASTRETCH_SCL;                  /*!< Automatic Stretch SCL */
+} ADI_I2C_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup SPI Serial Peripheral Interface (SPI) Module
+ *  Serial Peripheral Interface
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_SPI_TypeDef
+ *  \brief  Serial Peripheral Interface
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_TypeDef__
+typedef struct _ADI_SPI_TypeDef
+{
+    __IO     uint16_t   STAT;                          /*!< Status */
+    __I __C  uint8_t  RESERVED0[2];
+    __I __C  uint16_t   RX;                            /*!< Receive */
+    __I __C  uint8_t  RESERVED1[2];
+    __O      uint16_t   TX;                            /*!< Transmit */
+    __I __C  uint8_t  RESERVED2[2];
+    __IO     uint16_t   DIV;                           /*!< SPI Baud Rate Selection */
+    __I __C  uint8_t  RESERVED3[2];
+    __IO     uint16_t   CTL;                           /*!< SPI Configuration */
+    __I __C  uint8_t  RESERVED4[2];
+    __IO     uint16_t   IEN;                           /*!< SPI Interrupts Enable */
+    __I __C  uint8_t  RESERVED5[2];
+    __IO     uint16_t   CNT;                           /*!< Transfer Byte Count */
+    __I __C  uint8_t  RESERVED6[2];
+    __IO     uint16_t   DMA;                           /*!< SPI DMA Enable */
+    __I __C  uint8_t  RESERVED7[2];
+    __I __C  uint16_t   FIFO_STAT;                     /*!< FIFO Status */
+    __I __C  uint8_t  RESERVED8[2];
+    __IO     uint16_t   RD_CTL;                        /*!< Read Control */
+    __I __C  uint8_t  RESERVED9[2];
+    __IO     uint16_t   FLOW_CTL;                      /*!< Flow Control */
+    __I __C  uint8_t  RESERVED10[2];
+    __IO     uint16_t   WAIT_TMR;                      /*!< Wait Timer for Flow Control */
+    __I __C  uint8_t  RESERVED11[2];
+    __IO     uint16_t   CS_CTL;                        /*!< Chip Select Control for Multi-slave Connections */
+    __I __C  uint8_t  RESERVED12[2];
+    __IO     uint16_t   CS_OVERRIDE;                   /*!< Chip Select Override */
+    __I __C  uint8_t  RESERVED13[4];
+} ADI_SPI_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup UART  (UART) Module
+ *  
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_UART_TypeDef
+ *  \brief  
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_TypeDef__
+typedef struct _ADI_UART_TypeDef
+{
+    union {
+    __I __C  uint16_t   RX;                            /*!< Receive Buffer Register */
+    __O      uint16_t   TX;                            /*!< Transmit Holding Register */
+    };
+    __I __C  uint8_t  RESERVED0[2];
+    __IO     uint16_t   IEN;                           /*!< Interrupt Enable */
+    __I __C  uint8_t  RESERVED1[2];
+    __I __C  uint16_t   IIR;                           /*!< Interrupt ID */
+    __I __C  uint8_t  RESERVED2[2];
+    __IO     uint16_t   LCR;                           /*!< Line Control */
+    __I __C  uint8_t  RESERVED3[2];
+    __IO     uint16_t   MCR;                           /*!< Modem Control */
+    __I __C  uint8_t  RESERVED4[2];
+    __I __C  uint16_t   LSR;                           /*!< Line Status */
+    __I __C  uint8_t  RESERVED5[2];
+    __I __C  uint16_t   MSR;                           /*!< Modem Status */
+    __I __C  uint8_t  RESERVED6[2];
+    __IO     uint16_t   SCR;                           /*!< Scratch Buffer */
+    __I __C  uint8_t  RESERVED7[2];
+    __IO     uint16_t   FCR;                           /*!< FIFO Control */
+    __I __C  uint8_t  RESERVED8[2];
+    __IO     uint16_t   FBR;                           /*!< Fractional Baud Rate */
+    __I __C  uint8_t  RESERVED9[2];
+    __IO     uint16_t   DIV;                           /*!< Baud Rate Divider */
+    __I __C  uint8_t  RESERVED10[2];
+    __IO     uint16_t   LCR2;                          /*!< Second Line Control */
+    __I __C  uint8_t  RESERVED11[2];
+    __IO     uint16_t   CTL;                           /*!< UART Control Register */
+    __I __C  uint8_t  RESERVED12[2];
+    __I __C  uint16_t   RFC;                           /*!< RX FIFO Byte Count */
+    __I __C  uint8_t  RESERVED13[2];
+    __I __C  uint16_t   TFC;                           /*!< TX FIFO Byte Count */
+    __I __C  uint8_t  RESERVED14[2];
+    __IO     uint16_t   RSC;                           /*!< RS485 Half-duplex Control */
+    __I __C  uint8_t  RESERVED15[2];
+    __IO     uint16_t   ACR;                           /*!< Auto Baud Control */
+    __I __C  uint8_t  RESERVED16[2];
+    __I __C  uint16_t   ASRL;                          /*!< Auto Baud Status (Low) */
+    __I __C  uint8_t  RESERVED17[2];
+    __I __C  uint16_t   ASRH;                          /*!< Auto Baud Status (High) */
+} ADI_UART_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup BEEP Beeper Driver (BEEP) Module
+ *  Beeper Driver
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_BEEP_TypeDef
+ *  \brief  Beeper Driver
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_TypeDef__
+typedef struct _ADI_BEEP_TypeDef
+{
+    __IO     uint16_t   CFG;                           /*!< Beeper Configuration */
+    __I __C  uint8_t  RESERVED0[2];
+    __IO     uint16_t   STAT;                          /*!< Beeper Status */
+    __I __C  uint8_t  RESERVED1[2];
+    __IO     uint16_t   TONEA;                         /*!< Tone A Data */
+    __I __C  uint8_t  RESERVED2[2];
+    __IO     uint16_t   TONEB;                         /*!< Tone B Data */
+} ADI_BEEP_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup ADC  (ADC) Module
+ *  
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_ADC_TypeDef
+ *  \brief  
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_TypeDef__
+typedef struct _ADI_ADC_TypeDef
+{
+    __IO     uint16_t   CFG;                           /*!< ADC Configuration */
+    __I __C  uint8_t  RESERVED0[2];
+    __IO     uint16_t   PWRUP;                         /*!< ADC Power-up Time */
+    __I __C  uint8_t  RESERVED1[2];
+    __IO     uint16_t   CAL_WORD;                      /*!< Calibration Word */
+    __I __C  uint8_t  RESERVED2[2];
+    __IO     uint16_t   CNV_CFG;                       /*!< ADC Conversion Configuration */
+    __I __C  uint8_t  RESERVED3[2];
+    __IO     uint16_t   CNV_TIME;                      /*!< ADC Conversion Time */
+    __I __C  uint8_t  RESERVED4[2];
+    __IO     uint16_t   AVG_CFG;                       /*!< Averaging Configuration */
+    __I __C  uint8_t  RESERVED5[10];
+    __IO     uint16_t   IRQ_EN;                        /*!< Interrupt Enable */
+    __I __C  uint8_t  RESERVED6[2];
+    __IO     uint16_t   STAT;                          /*!< ADC Status */
+    __I __C  uint8_t  RESERVED7[2];
+    __IO     uint16_t   OVF;                           /*!< Overflow of Output Registers */
+    __I __C  uint8_t  RESERVED8[2];
+    __IO     uint16_t   ALERT;                         /*!< Alert Indication */
+    __I __C  uint8_t  RESERVED9[2];
+    __I __C  uint16_t   CH0_OUT;                       /*!< Conversion Result Channel 0 */
+    __I __C  uint8_t  RESERVED10[2];
+    __I __C  uint16_t   CH1_OUT;                       /*!< Conversion Result Channel 1 */
+    __I __C  uint8_t  RESERVED11[2];
+    __I __C  uint16_t   CH2_OUT;                       /*!< Conversion Result Channel 2 */
+    __I __C  uint8_t  RESERVED12[2];
+    __I __C  uint16_t   CH3_OUT;                       /*!< Conversion Result Channel 3 */
+    __I __C  uint8_t  RESERVED13[2];
+    __I __C  uint16_t   CH4_OUT;                       /*!< Conversion Result Channel 4 */
+    __I __C  uint8_t  RESERVED14[2];
+    __I __C  uint16_t   CH5_OUT;                       /*!< Conversion Result Channel 5 */
+    __I __C  uint8_t  RESERVED15[2];
+    __I __C  uint16_t   CH6_OUT;                       /*!< Conversion Result Channel 6 */
+    __I __C  uint8_t  RESERVED16[2];
+    __I __C  uint16_t   CH7_OUT;                       /*!< Conversion Result Channel 7 */
+    __I __C  uint8_t  RESERVED17[2];
+    __I __C  uint16_t   BAT_OUT;                       /*!< Battery Monitoring Result */
+    __I __C  uint8_t  RESERVED18[2];
+    __I __C  uint16_t   TMP_OUT;                       /*!< Temperature Result */
+    __I __C  uint8_t  RESERVED19[2];
+    __I __C  uint16_t   TMP2_OUT;                      /*!< Temperature Result 2 */
+    __I __C  uint8_t  RESERVED20[2];
+    __I __C  uint16_t   DMA_OUT;                       /*!< DMA Output Register */
+    __I __C  uint8_t  RESERVED21[2];
+    __IO     uint16_t   LIM0_LO;                       /*!< Channel 0 Low Limit */
+    __I __C  uint8_t  RESERVED22[2];
+    __IO     uint16_t   LIM0_HI;                       /*!< Channel 0 High Limit */
+    __I __C  uint8_t  RESERVED23[2];
+    __IO     uint16_t   HYS0;                          /*!< Channel 0 Hysteresis */
+    __I __C  uint8_t  RESERVED24[6];
+    __IO     uint16_t   LIM1_LO;                       /*!< Channel 1 Low Limit */
+    __I __C  uint8_t  RESERVED25[2];
+    __IO     uint16_t   LIM1_HI;                       /*!< Channel 1 High Limit */
+    __I __C  uint8_t  RESERVED26[2];
+    __IO     uint16_t   HYS1;                          /*!< Channel 1 Hysteresis */
+    __I __C  uint8_t  RESERVED27[6];
+    __IO     uint16_t   LIM2_LO;                       /*!< Channel 2 Low Limit */
+    __I __C  uint8_t  RESERVED28[2];
+    __IO     uint16_t   LIM2_HI;                       /*!< Channel 2 High Limit */
+    __I __C  uint8_t  RESERVED29[2];
+    __IO     uint16_t   HYS2;                          /*!< Channel 2 Hysteresis */
+    __I __C  uint8_t  RESERVED30[6];
+    __IO     uint16_t   LIM3_LO;                       /*!< Channel 3 Low Limit */
+    __I __C  uint8_t  RESERVED31[2];
+    __IO     uint16_t   LIM3_HI;                       /*!< Channel 3 High Limit */
+    __I __C  uint8_t  RESERVED32[2];
+    __IO     uint16_t   HYS3;                          /*!< Channel 3 Hysteresis */
+    __I __C  uint8_t  RESERVED33[38];
+    __IO     uint16_t   CFG1;                          /*!< Reference Buffer Low Power Mode */
+    __I __C  uint8_t  RESERVED34[576];
+} ADI_ADC_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup DMA DMA (DMA) Module
+ *  DMA
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_DMA_TypeDef
+ *  \brief  DMA
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_TypeDef__
+typedef struct _ADI_DMA_TypeDef
+{
+    __I __C  uint32_t   STAT;                          /*!< DMA Status */
+    __O      uint32_t   CFG;                           /*!< DMA Configuration */
+    __IO     uint32_t   PDBPTR;                        /*!< DMA Channel Primary Control Database Pointer */
+    __I __C  uint32_t   ADBPTR;                        /*!< DMA Channel Alternate Control Database Pointer */
+    __I __C  uint8_t  RESERVED0[4];
+    __O      uint32_t   SWREQ;                         /*!< DMA Channel Software Request */
+    __I __C  uint8_t  RESERVED1[8];
+    __IO     uint32_t   RMSK_SET;                      /*!< DMA Channel Request Mask Set */
+    __O      uint32_t   RMSK_CLR;                      /*!< DMA Channel Request Mask Clear */
+    __IO     uint32_t   EN_SET;                        /*!< DMA Channel Enable Set */
+    __O      uint32_t   EN_CLR;                        /*!< DMA Channel Enable Clear */
+    __IO     uint32_t   ALT_SET;                       /*!< DMA Channel Primary Alternate Set */
+    __O      uint32_t   ALT_CLR;                       /*!< DMA Channel Primary Alternate Clear */
+    __O      uint32_t   PRI_SET;                       /*!< DMA Channel Priority Set */
+    __O      uint32_t   PRI_CLR;                       /*!< DMA Channel Priority Clear */
+    __I __C  uint8_t  RESERVED2[8];
+    __IO     uint32_t   ERRCHNL_CLR;                   /*!< DMA per Channel Error Clear */
+    __IO     uint32_t   ERR_CLR;                       /*!< DMA Bus Error Clear */
+    __IO     uint32_t   INVALIDDESC_CLR;               /*!< DMA per Channel Invalid Descriptor Clear */
+    __I __C  uint8_t  RESERVED3[1964];
+    __IO     uint32_t   BS_SET;                        /*!< DMA Channel Bytes Swap Enable Set */
+    __O      uint32_t   BS_CLR;                        /*!< DMA Channel Bytes Swap Enable Clear */
+    __I __C  uint8_t  RESERVED4[8];
+    __IO     uint32_t   SRCADDR_SET;                   /*!< DMA Channel Source Address Decrement Enable Set */
+    __O      uint32_t   SRCADDR_CLR;                   /*!< DMA Channel Source Address Decrement Enable Clear */
+    __IO     uint32_t   DSTADDR_SET;                   /*!< DMA Channel Destination Address Decrement Enable Set */
+    __O      uint32_t   DSTADDR_CLR;                   /*!< DMA Channel Destination Address Decrement Enable Clear */
+    __I __C  uint8_t  RESERVED5[1984];
+    __I __C  uint32_t   REVID;                         /*!< DMA Controller Revision ID */
+} ADI_DMA_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup FLCC Flash Controller (FLCC) Module
+ *  Flash Controller
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_FLCC_TypeDef
+ *  \brief  Flash Controller
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_TypeDef__
+typedef struct _ADI_FLCC_TypeDef
+{
+    __IO     uint32_t   STAT;                          /*!< Status */
+    __IO     uint32_t   IEN;                           /*!< Interrupt Enable */
+    __IO     uint32_t   CMD;                           /*!< Command */
+    __IO     uint32_t   KH_ADDR;                       /*!< Write Address */
+    __IO     uint32_t   KH_DATA0;                      /*!< Write Lower Data */
+    __IO     uint32_t   KH_DATA1;                      /*!< Write Upper Data */
+    __IO     uint32_t   PAGE_ADDR0;                    /*!< Lower Page Address */
+    __IO     uint32_t   PAGE_ADDR1;                    /*!< Upper Page Address */
+    __O      uint32_t   KEY;                           /*!< Key */
+    __I __C  uint32_t   WR_ABORT_ADDR;                 /*!< Write Abort Address */
+    __IO     uint32_t   WRPROT;                        /*!< Write Protection */
+    __I __C  uint32_t   SIGNATURE;                     /*!< Signature */
+    __IO     uint32_t   UCFG;                          /*!< User Configuration */
+    __IO     uint32_t   TIME_PARAM0;                   /*!< Time Parameter 0 */
+    __IO     uint32_t   TIME_PARAM1;                   /*!< Time Parameter 1 */
+    __IO     uint32_t   ABORT_EN_LO;                   /*!< IRQ Abort Enable (Lower Bits) */
+    __IO     uint32_t   ABORT_EN_HI;                   /*!< IRQ Abort Enable (Upper Bits) */
+    __IO     uint32_t   ECC_CFG;                       /*!< ECC Configuration */
+    __I __C  uint32_t   ECC_ADDR;                      /*!< ECC Status (Address) */
+    __I __C  uint8_t  RESERVED0[4];
+    __IO     uint32_t   POR_SEC;                       /*!< Flash Security */
+    __IO     uint32_t   VOL_CFG;                       /*!< Volatile Flash Configuration */
+} ADI_FLCC_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup FLCC_CACHE Cache Controller (FLCC_CACHE) Module
+ *  Cache Controller
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_FLCC_CACHE_TypeDef
+ *  \brief  Cache Controller
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_TypeDef__
+typedef struct _ADI_FLCC_CACHE_TypeDef
+{
+    __I __C  uint32_t   STAT;                          /*!< Cache Status */
+    __IO     uint32_t   SETUP;                         /*!< Cache Setup */
+    __O      uint32_t   KEY;                           /*!< Cache Key */
+    __I __C  uint8_t  RESERVED0[40];
+} ADI_FLCC_CACHE_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup GPIO  (GPIO) Module
+ *  
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_GPIO_TypeDef
+ *  \brief  
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_TypeDef__
+typedef struct _ADI_GPIO_TypeDef
+{
+    __IO     uint32_t   CFG;                           /*!< Port Configuration */
+    __IO     uint16_t   OEN;                           /*!< Port Output Enable */
+    __I __C  uint8_t  RESERVED0[2];
+    __IO     uint16_t   PE;                            /*!< Port Output Pull-up/Pull-down Enable */
+    __I __C  uint8_t  RESERVED1[2];
+    __IO     uint16_t   IEN;                           /*!< Port Input Path Enable */
+    __I __C  uint8_t  RESERVED2[2];
+    __I __C  uint16_t   IN;                            /*!< Port Registered Data Input */
+    __I __C  uint8_t  RESERVED3[2];
+    __IO     uint16_t   OUT;                           /*!< Port Data Output */
+    __I __C  uint8_t  RESERVED4[2];
+    __O      uint16_t   SET;                           /*!< Port Data Out Set */
+    __I __C  uint8_t  RESERVED5[2];
+    __O      uint16_t   CLR;                           /*!< Port Data Out Clear */
+    __I __C  uint8_t  RESERVED6[2];
+    __O      uint16_t   TGL;                           /*!< Port Pin Toggle */
+    __I __C  uint8_t  RESERVED7[2];
+    __IO     uint16_t   POL;                           /*!< Port Interrupt Polarity */
+    __I __C  uint8_t  RESERVED8[2];
+    __IO     uint16_t   IENA;                          /*!< Port Interrupt A Enable */
+    __I __C  uint8_t  RESERVED9[2];
+    __IO     uint16_t   IENB;                          /*!< Port Interrupt B Enable */
+    __I __C  uint8_t  RESERVED10[2];
+    __IO     uint16_t   INT;                           /*!< Port Interrupt Status */
+    __I __C  uint8_t  RESERVED11[2];
+    __IO     uint16_t   DS;                            /*!< Port Drive Strength Select */
+} ADI_GPIO_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup SPORT Serial Port (SPORT) Module
+ *  Serial Port
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_SPORT_TypeDef
+ *  \brief  Serial Port
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_TypeDef__
+typedef struct _ADI_SPORT_TypeDef
+{
+    __IO     uint32_t   CTL_A;                         /*!< Half SPORT 'A' Control */
+    __IO     uint32_t   DIV_A;                         /*!< Half SPORT 'A' Divisor */
+    __IO     uint32_t   IEN_A;                         /*!< Half SPORT A's Interrupt Enable */
+    __IO     uint32_t   STAT_A;                        /*!< Half SPORT A's Status */
+    __IO     uint32_t   NUMTRAN_A;                     /*!< Half SPORT A Number of Transfers */
+    __IO     uint32_t   CNVT_A;                        /*!< Half SPORT 'A' CNV Width */
+    __I __C  uint8_t  RESERVED0[8];
+    __O      uint32_t   TX_A;                          /*!< Half SPORT 'A' Tx Buffer */
+    __I __C  uint8_t  RESERVED1[4];
+    __I __C  uint32_t   RX_A;                          /*!< Half SPORT 'A' Rx Buffer */
+    __I __C  uint8_t  RESERVED2[20];
+    __IO     uint32_t   CTL_B;                         /*!< Half SPORT 'B' Control */
+    __IO     uint32_t   DIV_B;                         /*!< Half SPORT 'B' Divisor */
+    __IO     uint32_t   IEN_B;                         /*!< Half SPORT B's Interrupt Enable */
+    __IO     uint32_t   STAT_B;                        /*!< Half SPORT B's Status */
+    __IO     uint32_t   NUMTRAN_B;                     /*!< Half SPORT B Number of Transfers */
+    __IO     uint32_t   CNVT_B;                        /*!< Half SPORT 'B' CNV Width */
+    __I __C  uint8_t  RESERVED3[8];
+    __O      uint32_t   TX_B;                          /*!< Half SPORT 'B' Tx Buffer */
+    __I __C  uint8_t  RESERVED4[4];
+    __I __C  uint32_t   RX_B;                          /*!< Half SPORT 'B' Rx Buffer */
+    __I __C  uint8_t  RESERVED5[16];
+} ADI_SPORT_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup CRC CRC Accelerator (CRC) Module
+ *  CRC Accelerator
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_CRC_TypeDef
+ *  \brief  CRC Accelerator
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_TypeDef__
+typedef struct _ADI_CRC_TypeDef
+{
+    __IO     uint32_t   CTL;                           /*!< CRC Control */
+    __O      uint32_t   IPDATA;                        /*!< Input Data Word */
+    __IO     uint32_t   RESULT;                        /*!< CRC Result */
+    __IO     uint32_t   POLY;                          /*!< Programmable CRC Polynomial */
+    union {
+    __O      uint8_t    IPBITS[8];                     /*!< Input Data Bits */
+    __O      uint8_t    IPBYTE;                        /*!< Input Data Byte */
+    };
+} ADI_CRC_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup RNG Random Number Generator (RNG) Module
+ *  Random Number Generator
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_RNG_TypeDef
+ *  \brief  Random Number Generator
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_TypeDef__
+typedef struct _ADI_RNG_TypeDef
+{
+    __IO     uint16_t   CTL;                           /*!< RNG Control Register */
+    __I __C  uint8_t  RESERVED0[2];
+    __IO     uint16_t   LEN;                           /*!< RNG Sample Length Register */
+    __I __C  uint8_t  RESERVED1[2];
+    __IO     uint16_t   STAT;                          /*!< RNG Status Register */
+    __I __C  uint8_t  RESERVED2[2];
+    __I __C  uint32_t   DATA;                          /*!< RNG Data Register */
+    __I __C  uint32_t   OSCCNT;                        /*!< Oscillator Count */
+    __I __C  int8_t     OSCDIFF[4];                    /*!< Oscillator Difference */
+} ADI_RNG_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup CRYPT Register Map for the Crypto Block (CRYPT) Module
+ *  Register Map for the Crypto Block
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_CRYPT_TypeDef
+ *  \brief  Register Map for the Crypto Block
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_TypeDef__
+typedef struct _ADI_CRYPT_TypeDef
+{
+    __IO     uint32_t   CFG;                           /*!< Configuration Register */
+    __IO     uint32_t   DATALEN;                       /*!< Payload Data Length */
+    __IO     uint32_t   PREFIXLEN;                     /*!< Authentication Data Length */
+    __IO     uint32_t   INTEN;                         /*!< Interrupt Enable Register */
+    __IO     uint32_t   STAT;                          /*!< Status Register */
+    __O      uint32_t   INBUF;                         /*!< Input Buffer */
+    __I __C  uint32_t   OUTBUF;                        /*!< Output Buffer */
+    __IO     uint32_t   NONCE0;                        /*!< Nonce Bits [31:0] */
+    __IO     uint32_t   NONCE1;                        /*!< Nonce Bits [63:32] */
+    __IO     uint32_t   NONCE2;                        /*!< Nonce Bits [95:64] */
+    __IO     uint32_t   NONCE3;                        /*!< Nonce Bits [127:96] */
+    __O      uint32_t   AESKEY0;                       /*!< AES Key Bits [31:0] */
+    __O      uint32_t   AESKEY1;                       /*!< AES Key Bits [63:32] */
+    __O      uint32_t   AESKEY2;                       /*!< AES Key Bits [95:64] */
+    __O      uint32_t   AESKEY3;                       /*!< AES Key Bits [127:96] */
+    __O      uint32_t   AESKEY4;                       /*!< AES Key Bits [159:128] */
+    __O      uint32_t   AESKEY5;                       /*!< AES Key Bits [191:160] */
+    __O      uint32_t   AESKEY6;                       /*!< AES Key Bits [223:192] */
+    __O      uint32_t   AESKEY7;                       /*!< AES Key Bits [255:224] */
+    __IO     uint32_t   CNTRINIT;                      /*!< Counter Initialization Vector */
+    __IO     uint32_t   SHAH0;                         /*!< SHA Bits [31:0] */
+    __IO     uint32_t   SHAH1;                         /*!< SHA Bits [63:32] */
+    __IO     uint32_t   SHAH2;                         /*!< SHA Bits [95:64] */
+    __IO     uint32_t   SHAH3;                         /*!< SHA Bits [127:96] */
+    __IO     uint32_t   SHAH4;                         /*!< SHA Bits [159:128] */
+    __IO     uint32_t   SHAH5;                         /*!< SHA Bits [191:160] */
+    __IO     uint32_t   SHAH6;                         /*!< SHA Bits [223:192] */
+    __IO     uint32_t   SHAH7;                         /*!< SHA Bits [255:224] */
+    __IO     uint32_t   SHA_LAST_WORD;                 /*!< SHA Last Word and Valid Bits Information */
+    __IO     uint32_t   CCM_NUM_VALID_BYTES;           /*!< NUM_VALID_BYTES */
+} ADI_CRYPT_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup PMG Power Management  (PMG) Module
+ *  Power Management 
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_PMG_TypeDef
+ *  \brief  Power Management 
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TypeDef__
+typedef struct _ADI_PMG_TypeDef
+{
+    __IO     uint32_t   IEN;                           /*!< Power Supply Monitor Interrupt Enable */
+    __IO     uint32_t   PSM_STAT;                      /*!< Power Supply Monitor Status */
+    __IO     uint32_t   PWRMOD;                        /*!< Power Mode Register */
+    __O      uint32_t   PWRKEY;                        /*!< Key Protection for PWRMOD and SRAMRET */
+    __I __C  uint32_t   SHDN_STAT;                     /*!< Shutdown Status Register */
+    __IO     uint32_t   SRAMRET;                       /*!< Control for Retention SRAM in Hibernate Mode */
+    __I __C  uint8_t  RESERVED0[40];
+    __IO     uint32_t   RST_STAT;                      /*!< Reset Status */
+    __IO     uint32_t   CTL1;                          /*!< HP Buck Control */
+    __I __C  uint8_t  RESERVED1[20];
+} ADI_PMG_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup XINT External interrupt configuration (XINT) Module
+ *  External interrupt configuration
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_XINT_TypeDef
+ *  \brief  External interrupt configuration
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_TypeDef__
+typedef struct _ADI_XINT_TypeDef
+{
+    __IO     uint32_t   CFG0;                          /*!< External Interrupt Configuration */
+    __I __C  uint32_t   EXT_STAT;                      /*!< External Wakeup Interrupt Status */
+    __I __C  uint8_t  RESERVED0[8];
+    __IO     uint32_t   CLR;                           /*!< External Interrupt Clear */
+    __IO     uint32_t   NMICLR;                        /*!< Non-Maskable Interrupt Clear */
+} ADI_XINT_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup CLKG_OSC Clocking  (CLKG_OSC) Module
+ *  Clocking 
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_CLKG_OSC_TypeDef
+ *  \brief  Clocking 
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_TypeDef__
+typedef struct _ADI_CLKG_OSC_TypeDef
+{
+    __I __C  uint8_t  RESERVED0[12];
+    __O      uint32_t   KEY;                           /*!< Key Protection for CLKG_OSC_CTL */
+    __IO     uint32_t   CTL;                           /*!< Oscillator Control */
+    __I __C  uint8_t  RESERVED1[8];
+} ADI_CLKG_OSC_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup PMG_TST Power Management  (PMG_TST) Module
+ *  Power Management 
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_PMG_TST_TypeDef
+ *  \brief  Power Management 
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_TypeDef__
+typedef struct _ADI_PMG_TST_TypeDef
+{
+    __I __C  uint8_t  RESERVED0[96];
+    __IO     uint32_t   SRAM_CTL;                      /*!< Control for SRAM Parity and Instruction SRAM */
+    __IO     uint32_t   SRAM_INITSTAT;                 /*!< Initialization Status Register */
+    __O      uint16_t   CLR_LATCH_GPIOS;               /*!< Clear GPIO After Shutdown Mode */
+    __I __C  uint8_t  RESERVED1[2];
+    __IO     uint32_t   SCRPAD_IMG;                    /*!< Scratch Pad Image */
+    __I __C  uint32_t   SCRPAD_3V_RD;                  /*!< Scratch Pad Saved in Battery Domain */
+} ADI_PMG_TST_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup CLKG_CLK Clocking  (CLKG_CLK) Module
+ *  Clocking 
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_CLKG_CLK_TypeDef
+ *  \brief  Clocking 
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_TypeDef__
+typedef struct _ADI_CLKG_CLK_TypeDef
+{
+    __IO     uint32_t   CTL0;                          /*!< Miscellaneous Clock Settings */
+    __IO     uint32_t   CTL1;                          /*!< Clock Dividers */
+    __I __C  uint8_t  RESERVED0[4];
+    __IO     uint32_t   CTL3;                          /*!< System PLL */
+    __I __C  uint8_t  RESERVED1[4];
+    __IO     uint32_t   CTL5;                          /*!< User Clock Gating Control */
+    __IO     uint32_t   STAT0;                         /*!< Clocking Status */
+    __I __C  uint8_t  RESERVED2[20];
+} ADI_CLKG_CLK_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup BUSM Bus matrix (BUSM) Module
+ *  Bus matrix
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_BUSM_TypeDef
+ *  \brief  Bus matrix
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_TypeDef__
+typedef struct _ADI_BUSM_TypeDef
+{
+    __IO     uint32_t   ARBIT0;                        /*!< Arbitration Priority Configuration for FLASH and SRAM0 */
+    __IO     uint32_t   ARBIT1;                        /*!< Arbitration Priority Configuration for SRAM1 and SIP */
+    __IO     uint32_t   ARBIT2;                        /*!< Arbitration Priority Configuration for APB32 and APB16 */
+    __IO     uint32_t   ARBIT3;                        /*!< Arbitration Priority Configuration for APB16 priority for core and for DMA1 */
+    __I __C  uint8_t  RESERVED0[4];
+} ADI_BUSM_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup PTI Parallel Test Interface (PTI) Module
+ *  Parallel Test Interface
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_PTI_TypeDef
+ *  \brief  Parallel Test Interface
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PTI_TypeDef__
+typedef struct _ADI_PTI_TypeDef
+{
+    __IO     uint32_t   RST_ISR_STARTADDR;             /*!< Reset ISR Start Address */
+    __IO     uint32_t   RST_STACK_PTR;                 /*!< Reset Stack Pointer */
+    __IO     uint32_t   CTL;                           /*!< Parallel Test Interface Control Register */
+} ADI_PTI_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PTI_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup NVIC Cortex-M3 Interrupt Controller (NVIC) Module
+ *  Cortex-M3 Interrupt Controller
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_NVIC_TypeDef
+ *  \brief  Cortex-M3 Interrupt Controller
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_TypeDef__
+typedef struct _ADI_NVIC_TypeDef
+{
+    __I __C  uint8_t  RESERVED0[4];
+    __IO     uint32_t   INTNUM;                        /*!< Interrupt Control Type */
+    __I __C  uint8_t  RESERVED1[8];
+    __IO     uint32_t   STKSTA;                        /*!< Systick Control and Status */
+    __IO     uint32_t   STKLD;                         /*!< Systick Reload Value */
+    __IO     uint32_t   STKVAL;                        /*!< Systick Current Value */
+    __IO     uint32_t   STKCAL;                        /*!< Systick Calibration Value */
+    __I __C  uint8_t  RESERVED2[224];
+    __IO     uint32_t   INTSETE0;                      /*!< IRQ0..31 Set_Enable */
+    __IO     uint32_t   INTSETE1;                      /*!< IRQ32..63 Set_Enable */
+    __I __C  uint8_t  RESERVED3[120];
+    __IO     uint32_t   INTCLRE0;                      /*!< IRQ0..31 Clear_Enable */
+    __IO     uint32_t   INTCLRE1;                      /*!< IRQ32..63 Clear_Enable */
+    __I __C  uint8_t  RESERVED4[120];
+    __IO     uint32_t   INTSETP0;                      /*!< IRQ0..31 Set_Pending */
+    __IO     uint32_t   INTSETP1;                      /*!< IRQ32..63 Set_Pending */
+    __I __C  uint8_t  RESERVED5[120];
+    __IO     uint32_t   INTCLRP0;                      /*!< IRQ0..31 Clear_Pending */
+    __IO     uint32_t   INTCLRP1;                      /*!< IRQ32..63 Clear_Pending */
+    __I __C  uint8_t  RESERVED6[120];
+    __IO     uint32_t   INTACT0;                       /*!< IRQ0..31 Active Bit */
+    __IO     uint32_t   INTACT1;                       /*!< IRQ32..63 Active Bit */
+    __I __C  uint8_t  RESERVED7[248];
+    __IO     uint32_t   INTPRI0;                       /*!< IRQ0..3 Priority */
+    __IO     uint32_t   INTPRI1;                       /*!< IRQ4..7 Priority */
+    __IO     uint32_t   INTPRI2;                       /*!< IRQ8..11 Priority */
+    __IO     uint32_t   INTPRI3;                       /*!< IRQ12..15 Priority */
+    __IO     uint32_t   INTPRI4;                       /*!< IRQ16..19 Priority */
+    __IO     uint32_t   INTPRI5;                       /*!< IRQ20..23 Priority */
+    __IO     uint32_t   INTPRI6;                       /*!< IRQ24..27 Priority */
+    __IO     uint32_t   INTPRI7;                       /*!< IRQ28..31 Priority */
+    __IO     uint32_t   INTPRI8;                       /*!< IRQ32..35 Priority */
+    __IO     uint32_t   INTPRI9;                       /*!< IRQ36..39 Priority */
+    __IO     uint32_t   INTPRI10;                      /*!< IRQ40..43 Priority */
+    __I __C  uint8_t  RESERVED8[2260];
+    __IO     uint32_t   INTCPID;                       /*!< CPUID Base */
+    __IO     uint32_t   INTSTA;                        /*!< Interrupt Control State */
+    __IO     uint32_t   INTVEC;                        /*!< Vector Table Offset */
+    __IO     uint32_t   INTAIRC;                       /*!< Application Interrupt/Reset Control */
+    __IO     uint16_t   INTCON0;                       /*!< System Control */
+    __I __C  uint8_t  RESERVED9[2];
+    __IO     uint32_t   INTCON1;                       /*!< Configuration Control */
+    __IO     uint32_t   INTSHPRIO0;                    /*!< System Handlers 4-7 Priority */
+    __IO     uint32_t   INTSHPRIO1;                    /*!< System Handlers 8-11 Priority */
+    __IO     uint32_t   INTSHPRIO3;                    /*!< System Handlers 12-15 Priority */
+    __IO     uint32_t   INTSHCSR;                      /*!< System Handler Control and State */
+    __IO     uint32_t   INTCFSR;                       /*!< Configurable Fault Status */
+    __IO     uint32_t   INTHFSR;                       /*!< Hard Fault Status */
+    __IO     uint32_t   INTDFSR;                       /*!< Debug Fault Status */
+    __IO     uint32_t   INTMMAR;                       /*!< Mem Manage Address */
+    __IO     uint32_t   INTBFAR;                       /*!< Bus Fault Address */
+    __IO     uint32_t   INTAFSR;                       /*!< Auxiliary Fault Status */
+    __IO     uint32_t   INTPFR0;                       /*!< Processor Feature Register 0 */
+    __IO     uint32_t   INTPFR1;                       /*!< Processor Feature Register 1 */
+    __IO     uint32_t   INTDFR0;                       /*!< Debug Feature Register 0 */
+    __IO     uint32_t   INTAFR0;                       /*!< Auxiliary Feature Register 0 */
+    __IO     uint32_t   INTMMFR0;                      /*!< Memory Model Feature Register 0 */
+    __IO     uint32_t   INTMMFR1;                      /*!< Memory Model Feature Register 1 */
+    __IO     uint32_t   INTMMFR2;                      /*!< Memory Model Feature Register 2 */
+    __IO     uint32_t   INTMMFR3;                      /*!< Memory Model Feature Register 3 */
+    __IO     uint32_t   INTISAR0;                      /*!< ISA Feature Register 0 */
+    __IO     uint32_t   INTISAR1;                      /*!< ISA Feature Register 1 */
+    __IO     uint32_t   INTISAR2;                      /*!< ISA Feature Register 2 */
+    __IO     uint32_t   INTISAR3;                      /*!< ISA Feature Register 3 */
+    __IO     uint32_t   INTISAR4;                      /*!< ISA Feature Register 4 */
+    __I __C  uint8_t  RESERVED10[396];
+    __IO     uint32_t   INTTRGI;                       /*!< Software Trigger Interrupt Register */
+    __I __C  uint8_t  RESERVED11[204];
+    __IO     uint32_t   INTPID4;                       /*!< Peripheral Identification Register 4 */
+    __IO     uint32_t   INTPID5;                       /*!< Peripheral Identification Register 5 */
+    __IO     uint32_t   INTPID6;                       /*!< Peripheral Identification Register 6 */
+    __IO     uint32_t   INTPID7;                       /*!< Peripheral Identification Register 7 */
+    __IO     uint32_t   INTPID0;                       /*!< Peripheral Identification Bits7:0 */
+    __IO     uint32_t   INTPID1;                       /*!< Peripheral Identification Bits15:8 */
+    __IO     uint32_t   INTPID2;                       /*!< Peripheral Identification Bits16:23 */
+    __IO     uint32_t   INTPID3;                       /*!< Peripheral Identification Bits24:31 */
+    __IO     uint32_t   INTCID0;                       /*!< Component Identification Bits7:0 */
+    __IO     uint32_t   INTCID1;                       /*!< Component Identification Bits15:8 */
+    __IO     uint32_t   INTCID2;                       /*!< Component Identification Bits16:23 */
+    __IO     uint32_t   INTCID3;                       /*!< Component Identification Bits24:31 */
+} ADI_NVIC_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_TypeDef__ */
+
+/*!@}*/
+
+/* ******************************************************************************
+ *    Peripheral Memory Map Declarations
+ * *****************************************************************************/
+/*!    @defgroup PMEMMAPDEC Peripheral Memory Map Declarations
+ *     \addtogroup PMEMMAPDEC
+ *     @{ */
+#define ADI_TMR0_BASE                  0x40000000    /*!<  Base address of TMR0 */
+#define ADI_TMR1_BASE                  0x40000400    /*!<  Base address of TMR1 */
+#define ADI_TMR2_BASE                  0x40000800    /*!<  Base address of TMR2 */
+#define ADI_RTC0_BASE                  0x40001000    /*!<  Base address of RTC0 */
+#define ADI_RTC1_BASE                  0x40001400    /*!<  Base address of RTC1 */
+#define ADI_SYS_BASE                   0x40002000    /*!<  Base address of SYS */
+#define ADI_WDT0_BASE                  0x40002c00    /*!<  Base address of WDT0 */
+#define ADI_I2C0_BASE                  0x40003000    /*!<  Base address of I2C0 */
+#define ADI_SPI0_BASE                  0x40004000    /*!<  Base address of SPI0 */
+#define ADI_SPI1_BASE                  0x40004400    /*!<  Base address of SPI1 */
+#define ADI_SPI2_BASE                  0x40024000    /*!<  Base address of SPI2 */
+#define ADI_UART0_BASE                 0x40005000    /*!<  Base address of UART0 */
+#define ADI_BEEP0_BASE                 0x40005c00    /*!<  Base address of BEEP0 */
+#define ADI_ADC0_BASE                  0x40007000    /*!<  Base address of ADC0 */
+#define ADI_DMA0_BASE                  0x40010000    /*!<  Base address of DMA0 */
+#define ADI_FLCC0_BASE                 0x40018000    /*!<  Base address of FLCC0 */
+#define ADI_FLCC0_CACHE_BASE           0x40018058    /*!<  Base address of FLCC0_CACHE */
+#define ADI_GPIO0_BASE                 0x40020000    /*!<  Base address of GPIO0 */
+#define ADI_GPIO1_BASE                 0x40020040    /*!<  Base address of GPIO1 */
+#define ADI_GPIO2_BASE                 0x40020080    /*!<  Base address of GPIO2 */
+#define ADI_SPORT0_BASE                0x40038000    /*!<  Base address of SPORT0 */
+#define ADI_CRC0_BASE                  0x40040000    /*!<  Base address of CRC0 */
+#define ADI_RNG0_BASE                  0x40040400    /*!<  Base address of RNG0 */
+#define ADI_CRYPT0_BASE                0x40044000    /*!<  Base address of CRYPT0 */
+#define ADI_PMG0_BASE                  0x4004c000    /*!<  Base address of PMG0 */
+#define ADI_XINT0_BASE                 0x4004c080    /*!<  Base address of XINT0 */
+#define ADI_CLKG0_OSC_BASE             0x4004c100    /*!<  Base address of CLKG0_OSC */
+#define ADI_PMG0_TST_BASE              0x4004c200    /*!<  Base address of PMG0_TST */
+#define ADI_CLKG0_CLK_BASE             0x4004c300    /*!<  Base address of CLKG0_CLK */
+#define ADI_BUSM0_BASE                 0x4004c800    /*!<  Base address of BUSM0 */
+#define ADI_PTI0_BASE                  0x4004cd00    /*!<  Base address of PTI0 */
+#define ADI_NVIC0_BASE                 0xe000e000    /*!<  Base address of NVIC0 */
+
+/*!    @} */
+
+/* ******************************************************************************
+ *    Peripheral Pointer Declarations
+ * *****************************************************************************/
+/*!    @Defgroup Pptrdec Peripheral Pointer Declarations
+ *     \Addtogroup Pptrdec
+ *     @{ */
+#define pADI_TMR0                      ((ADI_TMR_TypeDef      *) ADI_TMR0_BASE       ) /*!<  Pointer to General Purpose Timer (TMR0) */
+#define pADI_TMR1                      ((ADI_TMR_TypeDef      *) ADI_TMR1_BASE       ) /*!<  Pointer to General Purpose Timer (TMR1) */
+#define pADI_TMR2                      ((ADI_TMR_TypeDef      *) ADI_TMR2_BASE       ) /*!<  Pointer to General Purpose Timer (TMR2) */
+#define pADI_RTC0                      ((ADI_RTC_TypeDef      *) ADI_RTC0_BASE       ) /*!<  Pointer to Real-Time Clock (RTC0) */
+#define pADI_RTC1                      ((ADI_RTC_TypeDef      *) ADI_RTC1_BASE       ) /*!<  Pointer to Real-Time Clock (RTC1) */
+#define pADI_SYS                       ((ADI_SYS_TypeDef      *) ADI_SYS_BASE        ) /*!<  Pointer to System Identification and Debug Enable (SYS) */
+#define pADI_WDT0                      ((ADI_WDT_TypeDef      *) ADI_WDT0_BASE       ) /*!<  Pointer to Watchdog Timer (WDT0) */
+#define pADI_I2C0                      ((ADI_I2C_TypeDef      *) ADI_I2C0_BASE       ) /*!<  Pointer to I2C Master/Slave (I2C0) */
+#define pADI_SPI0                      ((ADI_SPI_TypeDef      *) ADI_SPI0_BASE       ) /*!<  Pointer to Serial Peripheral Interface (SPI0) */
+#define pADI_SPI1                      ((ADI_SPI_TypeDef      *) ADI_SPI1_BASE       ) /*!<  Pointer to Serial Peripheral Interface (SPI1) */
+#define pADI_SPI2                      ((ADI_SPI_TypeDef      *) ADI_SPI2_BASE       ) /*!<  Pointer to Serial Peripheral Interface (SPI2) */
+#define pADI_UART0                     ((ADI_UART_TypeDef     *) ADI_UART0_BASE      ) /*!<  Pointer to  (UART0) */
+#define pADI_BEEP0                     ((ADI_BEEP_TypeDef     *) ADI_BEEP0_BASE      ) /*!<  Pointer to Beeper Driver (BEEP0) */
+#define pADI_ADC0                      ((ADI_ADC_TypeDef      *) ADI_ADC0_BASE       ) /*!<  Pointer to  (ADC0) */
+#define pADI_DMA0                      ((ADI_DMA_TypeDef      *) ADI_DMA0_BASE       ) /*!<  Pointer to DMA (DMA0) */
+#define pADI_FLCC0                     ((ADI_FLCC_TypeDef     *) ADI_FLCC0_BASE      ) /*!<  Pointer to Flash Controller (FLCC0) */
+#define pADI_FLCC0_CACHE               ((ADI_FLCC_CACHE_TypeDef *) ADI_FLCC0_CACHE_BASE) /*!<  Pointer to Cache Controller (FLCC0_CACHE) */
+#define pADI_GPIO0                     ((ADI_GPIO_TypeDef     *) ADI_GPIO0_BASE      ) /*!<  Pointer to  (GPIO0) */
+#define pADI_GPIO1                     ((ADI_GPIO_TypeDef     *) ADI_GPIO1_BASE      ) /*!<  Pointer to  (GPIO1) */
+#define pADI_GPIO2                     ((ADI_GPIO_TypeDef     *) ADI_GPIO2_BASE      ) /*!<  Pointer to  (GPIO2) */
+#define pADI_SPORT0                    ((ADI_SPORT_TypeDef    *) ADI_SPORT0_BASE     ) /*!<  Pointer to Serial Port (SPORT0) */
+#define pADI_CRC0                      ((ADI_CRC_TypeDef      *) ADI_CRC0_BASE       ) /*!<  Pointer to CRC Accelerator (CRC0) */
+#define pADI_RNG0                      ((ADI_RNG_TypeDef      *) ADI_RNG0_BASE       ) /*!<  Pointer to Random Number Generator (RNG0) */
+#define pADI_CRYPT0                    ((ADI_CRYPT_TypeDef    *) ADI_CRYPT0_BASE     ) /*!<  Pointer to Register Map for the Crypto Block (CRYPT0) */
+#define pADI_PMG0                      ((ADI_PMG_TypeDef      *) ADI_PMG0_BASE       ) /*!<  Pointer to Power Management  (PMG0) */
+#define pADI_XINT0                     ((ADI_XINT_TypeDef     *) ADI_XINT0_BASE      ) /*!<  Pointer to External interrupt configuration (XINT0) */
+#define pADI_CLKG0_OSC                 ((ADI_CLKG_OSC_TypeDef *) ADI_CLKG0_OSC_BASE  ) /*!<  Pointer to Clocking  (CLKG0_OSC) */
+#define pADI_PMG0_TST                  ((ADI_PMG_TST_TypeDef  *) ADI_PMG0_TST_BASE   ) /*!<  Pointer to Power Management  (PMG0_TST) */
+#define pADI_CLKG0_CLK                 ((ADI_CLKG_CLK_TypeDef *) ADI_CLKG0_CLK_BASE  ) /*!<  Pointer to Clocking  (CLKG0_CLK) */
+#define pADI_BUSM0                     ((ADI_BUSM_TypeDef     *) ADI_BUSM0_BASE      ) /*!<  Pointer to Bus matrix (BUSM0) */
+#define pADI_PTI0                      ((ADI_PTI_TypeDef      *) ADI_PTI0_BASE       ) /*!<  Pointer to Parallel Test Interface (PTI0) */
+#define pADI_NVIC0                     ((ADI_NVIC_TypeDef     *) ADI_NVIC0_BASE      ) /*!<  Pointer to Cortex-M3 Interrupt Controller (NVIC0) */
+
+/*!    @} */
+
+
+/*  =========================================================================
+ *! \enum   IRQn_Type
+ *! \brief  Interrupt Number Assignments
+ *  ========================================================================= */
+#ifndef __ADI_NO_DECL_ENUM_IRQn_Type__
+
+typedef enum
+{
+  RESET_IRQn                     =   -15,    /*!< Cortex-M3 Reset */
+  NonMaskableInt_IRQn            =   -14,    /*!< Cortex-M3 Non-maskable Interrupt */
+  HardFault_IRQn                 =   -13,    /*!< Cortex-M3 Hardware Fault */
+  MemoryManagement_IRQn          =   -12,    /*!< Cortex-M3 Memory Management Interrupt */
+  BusFault_IRQn                  =   -11,    /*!< Cortex-M3 Bus Fault */
+  UsageFault_IRQn                =   -10,    /*!< Cortex-M3 Usage Fault */
+  SVCall_IRQn                    =    -5,    /*!< Cortex-M3 SVCall Interrupt */
+  DebugMonitor_IRQn              =    -4,    /*!< Cortex-M3 Debug Monitor */
+  PendSV_IRQn                    =    -2,    /*!< Cortex-M3 PendSV Interrupt */
+  SysTick_IRQn                   =    -1,    /*!< Cortex-M3 SysTick Interrupt */
+  RTC1_EVT_IRQn                  =     0,    /*!< Event */
+  XINT_EVT0_IRQn                 =     1,    /*!< External Wakeup Interrupt n */
+  XINT_EVT1_IRQn                 =     2,    /*!< External Wakeup Interrupt n */
+  XINT_EVT2_IRQn                 =     3,    /*!< External Wakeup Interrupt n */
+  XINT_EVT3_IRQn                 =     4,    /*!< External Wakeup Interrupt n */
+  WDT_EXP_IRQn                   =     5,    /*!< Expiration */
+  PMG0_VREG_OVR_IRQn             =     6,    /*!< Voltage Regulator (VREG) Overvoltage */
+  PMG0_BATT_RANGE_IRQn           =     7,    /*!< Battery Voltage (VBAT) Out of Range */
+  RTC0_EVT_IRQn                  =     8,    /*!< Event */
+  SYS_GPIO_INTA_IRQn             =     9,    /*!< GPIO Interrupt A */
+  SYS_GPIO_INTB_IRQn             =    10,    /*!< GPIO Interrupt B */
+  TMR0_EVT_IRQn                  =    11,    /*!< Event */
+  TMR1_EVT_IRQn                  =    12,    /*!< Event */
+  FLCC_EVT_IRQn                  =    13,    /*!< Event */
+  UART_EVT_IRQn                  =    14,    /*!< Event */
+  SPI0_EVT_IRQn                  =    15,    /*!< Event */
+  SPI2_EVT_IRQn                  =    16,    /*!< Event */
+  I2C_SLV_EVT_IRQn               =    17,    /*!< Slave Event */
+  I2C_MST_EVT_IRQn               =    18,    /*!< Master Event */
+  DMA_CHAN_ERR_IRQn              =    19,    /*!< Channel Error */
+  DMA0_CH0_DONE_IRQn             =    20,    /*!< Channel 0 Done */
+  DMA0_CH1_DONE_IRQn             =    21,    /*!< Channel 1 Done */
+  DMA0_CH2_DONE_IRQn             =    22,    /*!< Channel 2 Done */
+  DMA0_CH3_DONE_IRQn             =    23,    /*!< Channel 3 Done */
+  DMA0_CH4_DONE_IRQn             =    24,    /*!< Channel 4 Done */
+  DMA0_CH5_DONE_IRQn             =    25,    /*!< Channel 5 Done */
+  DMA0_CH6_DONE_IRQn             =    26,    /*!< Channel 6 Done */
+  DMA0_CH7_DONE_IRQn             =    27,    /*!< Channel 7 Done */
+  DMA0_CH8_DONE_IRQn             =    28,    /*!< Channel 8 Done */
+  DMA0_CH9_DONE_IRQn             =    29,    /*!< Channel 9 Done */
+  DMA0_CH10_DONE_IRQn            =    30,    /*!< Channel 10 Done */
+  DMA0_CH11_DONE_IRQn            =    31,    /*!< Channel 11 Done */
+  DMA0_CH12_DONE_IRQn            =    32,    /*!< Channel 12 Done */
+  DMA0_CH13_DONE_IRQn            =    33,    /*!< Channel 13 Done */
+  DMA0_CH14_DONE_IRQn            =    34,    /*!< Channel 14 Done */
+  DMA0_CH15_DONE_IRQn            =    35,    /*!< Channel 15 Done */
+  SPORT_A_EVT_IRQn               =    36,    /*!< Channel A Event */
+  SPORT_B_EVT_IRQn               =    37,    /*!< Channel B Event */
+  CRYPT_EVT_IRQn                 =    38,    /*!< Event */
+  DMA0_CH24_DONE_IRQn            =    39,    /*!< Channel 24 Done */
+  TMR2_EVT_IRQn                  =    40,    /*!< Event */
+  CLKG_XTAL_OSC_EVT_IRQn         =    41,    /*!< Crystal Oscillator Event */
+  SPI1_EVT_IRQn                  =    42,    /*!< Event */
+  CLKG_PLL_EVT_IRQn              =    43,    /*!< PLL Event */
+  RNG0_EVT_IRQn                  =    44,    /*!< Event */
+  BEEP_EVT_IRQn                  =    45,    /*!< Event */
+  ADC0_EVT_IRQn                  =    46,    /*!< Event */
+  DMA0_CH16_DONE_IRQn            =    56,    /*!< Channel 16 Done */
+  DMA0_CH17_DONE_IRQn            =    57,    /*!< Channel 17 Done */
+  DMA0_CH18_DONE_IRQn            =    58,    /*!< Channel 18 Done */
+  DMA0_CH19_DONE_IRQn            =    59,    /*!< Channel 19 Done */
+  DMA0_CH20_DONE_IRQn            =    60,    /*!< Channel 20 Done */
+  DMA0_CH21_DONE_IRQn            =    61,    /*!< Channel 21 Done */
+  DMA0_CH22_DONE_IRQn            =    62,    /*!< Channel 22 Done */
+  DMA0_CH23_DONE_IRQn            =    63,    /*!< Channel 23 Done */
+} IRQn_Type;  /* typedef name for fixed interrupt numbers */
+#endif /* !__ADI_NO_DECL_ENUM_IRQn_Type__ */
+
+
+
+#if defined (_MISRA_RULES)
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_typedefs.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_typedefs.h
new file mode 100755
index 00000000000..a151f993fe3
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_typedefs.h
@@ -0,0 +1,9553 @@
+/* ================================================================================
+
+     Project      :   ADuCM302x
+     File         :   ADuCM302x_typedefs.h
+     Description  :   C Register Structures
+
+     Date         :   Feb 6, 2017
+
+     Copyright (c) 2014-2017 Analog Devices, Inc.  All Rights Reserved.
+     This software is proprietary and confidential to Analog Devices, Inc. and
+     its licensors.
+
+     This file was auto-generated. Do not make local changes to this file.
+
+   ================================================================================ */
+
+#ifndef _ADUCM302X_TYPEDEFS_H
+#define _ADUCM302X_TYPEDEFS_H
+
+/* pickup integer types */
+#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__))
+#include <stdint.h>
+#endif /* _LANGUAGE_C */
+
+#if defined (_MISRA_RULES)
+/*
+  anonymous unions violate ISO 9899:1990 and therefore MISRA Rule 1.1.
+  Use of unions violates MISRA Rule 18.4.
+  Anonymous unions are required for this implementation.
+  Re-use of identifiers violates MISRA Rule 5.7.
+  Field names are repeated for the ADuCM302x register map.
+*/
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_1_1:"Allow anonymous unions")
+#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit")
+#pragma diag(suppress:misra_rule_5_3:"Header will re-use typedef identifiers")
+#pragma diag(suppress:misra_rule_5_6:"Header will re-use identifiers in the same scope")
+#pragma diag(suppress:misra_rule_5_7:"Header will re-use identifiers")
+#pragma diag(suppress:misra_rule_18_4:"Allow the use of a union")
+#endif /* _MISRA_RULES */
+
+/** @defgroup LOAD 16-bit Load Value (LOAD) Register
+ *  16-bit Load Value (LOAD) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_LOAD_Struct
+ *! \brief  16-bit Load Value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_LOAD_t__
+typedef struct _ADI_TMR_LOAD_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Load Value */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_LOAD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_LOAD_t__ */
+
+/*@}*/
+
+/** @defgroup CURCNT 16-bit Timer Value (CURCNT) Register
+ *  16-bit Timer Value (CURCNT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_CURCNT_Struct
+ *! \brief  16-bit Timer Value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CURCNT_t__
+typedef struct _ADI_TMR_CURCNT_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Current Count */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_CURCNT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CURCNT_t__ */
+
+/*@}*/
+
+/** @defgroup CTL Control (CTL) Register
+ *  Control (CTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_CTL_Struct
+ *! \brief  Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CTL_t__
+typedef struct _ADI_TMR_CTL_t {
+  union {
+    struct {
+      unsigned int PRE        :  2;  /**< Prescaler */
+      unsigned int UP         :  1;  /**< Count up */
+      unsigned int MODE       :  1;  /**< Timer Mode */
+      unsigned int EN         :  1;  /**< Timer Enable */
+      unsigned int CLK        :  2;  /**< Clock Select */
+      unsigned int RLD        :  1;  /**< Reload Control */
+      unsigned int EVTRANGE   :  5;  /**< Event Select Range */
+      unsigned int EVTEN      :  1;  /**< Event Select */
+      unsigned int RSTEN      :  1;  /**< Counter and Prescale Reset Enable */
+      unsigned int SYNCBYP    :  1;  /**< Synchronization Bypass */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup CLRINT Clear Interrupt (CLRINT) Register
+ *  Clear Interrupt (CLRINT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_CLRINT_Struct
+ *! \brief  Clear Interrupt Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CLRINT_t__
+typedef struct _ADI_TMR_CLRINT_t {
+  union {
+    struct {
+      unsigned int TIMEOUT    :  1;  /**< Clear Timeout Interrupt */
+      unsigned int EVTCAPT    :  1;  /**< Clear Captured Event Interrupt */
+      unsigned int reserved2  : 14;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_CLRINT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CLRINT_t__ */
+
+/*@}*/
+
+/** @defgroup CAPTURE Capture (CAPTURE) Register
+ *  Capture (CAPTURE) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_CAPTURE_Struct
+ *! \brief  Capture Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CAPTURE_t__
+typedef struct _ADI_TMR_CAPTURE_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< 16-bit Captured Value */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_CAPTURE_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CAPTURE_t__ */
+
+/*@}*/
+
+/** @defgroup ALOAD 16-bit Load Value, Asynchronous (ALOAD) Register
+ *  16-bit Load Value, Asynchronous (ALOAD) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_ALOAD_Struct
+ *! \brief  16-bit Load Value, Asynchronous Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_ALOAD_t__
+typedef struct _ADI_TMR_ALOAD_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Load Value, Asynchronous */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_ALOAD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_ALOAD_t__ */
+
+/*@}*/
+
+/** @defgroup ACURCNT 16-bit Timer Value, Asynchronous (ACURCNT) Register
+ *  16-bit Timer Value, Asynchronous (ACURCNT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_ACURCNT_Struct
+ *! \brief  16-bit Timer Value, Asynchronous Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_ACURCNT_t__
+typedef struct _ADI_TMR_ACURCNT_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Counter Value */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_ACURCNT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_ACURCNT_t__ */
+
+/*@}*/
+
+/** @defgroup STAT Status (STAT) Register
+ *  Status (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_STAT_Struct
+ *! \brief  Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_STAT_t__
+typedef struct _ADI_TMR_STAT_t {
+  union {
+    struct {
+      unsigned int TIMEOUT    :  1;  /**< Timeout Event Occurred */
+      unsigned int CAPTURE    :  1;  /**< Capture Event Pending */
+      unsigned int reserved2  :  4;
+      unsigned int BUSY       :  1;  /**< Timer Busy */
+      unsigned int PDOK       :  1;  /**< Clear Interrupt Register Synchronization */
+      unsigned int CNTRST     :  1;  /**< Counter Reset Occurring */
+      unsigned int reserved9  :  7;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup PWMCTL PWM Control Register (PWMCTL) Register
+ *  PWM Control Register (PWMCTL) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_TMR_PWMCTL_MATCH
+ *! \brief  PWM Match Enabled (MATCH) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  TMR_PWMCTL_PWM_TOGGLE = 0,  /**< PWM in toggle mode */
+  TMR_PWMCTL_PWM_MATCH  = 1   /**< PWM in match mode  */
+} ADI_TMR_PWMCTL_MATCH;
+
+
+/*  =========================================================================
+ *! \enum   ADI_TMR_PWMCTL_IDLESTATE
+ *! \brief  PWM Idle State (IDLESTATE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  TMR_PWMCTL_IDLE_LOW  = 0,  /**< PWM idles low  */
+  TMR_PWMCTL_IDLE_HIGH = 1   /**< PWM idles high */
+} ADI_TMR_PWMCTL_IDLESTATE;
+
+
+/* ==========================================================================
+ *! \struct ADI_TMR_PWMCTL_Struct
+ *! \brief  PWM Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_PWMCTL_t__
+typedef struct _ADI_TMR_PWMCTL_t {
+  union {
+    struct {
+      unsigned int MATCH      :  1;  /**< PWM Match Enabled */
+      unsigned int IDLESTATE  :  1;  /**< PWM Idle State */
+      unsigned int reserved2  : 14;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_PWMCTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_PWMCTL_t__ */
+
+/*@}*/
+
+/** @defgroup PWMMATCH PWM Match Value (PWMMATCH) Register
+ *  PWM Match Value (PWMMATCH) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_PWMMATCH_Struct
+ *! \brief  PWM Match Value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_PWMMATCH_t__
+typedef struct _ADI_TMR_PWMMATCH_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< PWM Match Value */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_PWMMATCH_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_PWMMATCH_t__ */
+
+/*@}*/
+
+/** @defgroup CR0 RTC Control 0 (CR0) Register
+ *  RTC Control 0 (CR0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_CR0_Struct
+ *! \brief  RTC Control 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR0_t__
+typedef struct _ADI_RTC_CR0_t {
+  union {
+    struct {
+      unsigned int CNTEN      :  1;  /**< Global Enable for the RTC */
+      unsigned int ALMEN      :  1;  /**< Enable the RTC Alarm (Absolute) Operation */
+      unsigned int ALMINTEN   :  1;  /**< Enable ALMINT Sourced Alarm Interrupts to the CPU */
+      unsigned int TRMEN      :  1;  /**< Enable RTC Digital Trimming */
+      unsigned int MOD60ALMEN :  1;  /**< Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary */
+      unsigned int MOD60ALM   :  6;  /**< Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60 Boundary */
+      unsigned int MOD60ALMINTEN :  1;  /**< Enable Periodic Modulo-60 RTC Alarm  Sourced Interrupts to the CPU */
+      unsigned int ISOINTEN      :  1;  /**< Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power Domain is Activated and Subsequently De-activated */
+      unsigned int WPNDERRINTEN  :  1;  /**< Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Register-write Pending Error Occurs */
+      unsigned int WSYNCINTEN    :  1;  /**< Enable Write Synchronization Sourced Interrupts to the CPU */
+      unsigned int WPNDINTEN     :  1;  /**< Enable Write Pending Sourced Interrupts to the CPU */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_CR0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR0_t__ */
+
+/*@}*/
+
+/** @defgroup SR0 RTC Status 0 (SR0) Register
+ *  RTC Status 0 (SR0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SR0_Struct
+ *! \brief  RTC Status 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR0_t__
+typedef struct _ADI_RTC_SR0_t {
+  union {
+    struct {
+      unsigned int reserved0  :  1;
+      unsigned int ALMINT     :  1;  /**< Alarm Interrupt Source */
+      unsigned int MOD60ALMINT :  1;  /**< Modulo-60 RTC Alarm Interrupt Source */
+      unsigned int ISOINT      :  1;  /**< RTC Power-Domain Isolation Interrupt Source */
+      unsigned int WPNDERRINT  :  1;  /**< Write Pending Error Interrupt Source */
+      unsigned int WSYNCINT    :  1;  /**< Write Synchronisation Interrupt */
+      unsigned int WPNDINT     :  1;  /**< Write Pending Interrupt */
+      unsigned int WSYNCCR0    :  1;  /**< Synchronisation Status of Posted Writes to CR0 */
+      unsigned int WSYNCSR0    :  1;  /**< Synchronisation Status of Posted Writes to SR0 */
+      unsigned int WSYNCCNT0   :  1;  /**< Synchronisation Status of Posted Writes to CNT0 */
+      unsigned int WSYNCCNT1   :  1;  /**< Synchronisation Status of Posted Writes to CNT1 */
+      unsigned int WSYNCALM0   :  1;  /**< Synchronisation Status of Posted Writes to ALM0 */
+      unsigned int WSYNCALM1   :  1;  /**< Synchronisation Status of Posted Writes to ALM1 */
+      unsigned int WSYNCTRM    :  1;  /**< Synchronisation Status of Posted Writes to TRM */
+      unsigned int ISOENB      :  1;  /**< Visibility of 32kHz Sourced Registers */
+      unsigned int reserved15  :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SR0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR0_t__ */
+
+/*@}*/
+
+/** @defgroup SR1 RTC Status 1 (SR1) Register
+ *  RTC Status 1 (SR1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SR1_Struct
+ *! \brief  RTC Status 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR1_t__
+typedef struct _ADI_RTC_SR1_t {
+  union {
+    struct {
+      unsigned int reserved0  :  7;
+      unsigned int WPNDCR0    :  1;  /**< Pending Status of Posted Writes to CR0 */
+      unsigned int WPNDSR0    :  1;  /**< Pending Status of Posted Clearances of Interrupt Sources in SR0 */
+      unsigned int WPNDCNT0   :  1;  /**< Pending Status of Posted Writes to CNT0 */
+      unsigned int WPNDCNT1   :  1;  /**< Pending Status of Posted Writes to CNT1 */
+      unsigned int WPNDALM0   :  1;  /**< Pending Status of Posted Writes to ALM0 */
+      unsigned int WPNDALM1   :  1;  /**< Pending Status of Posted Writes to ALM1 */
+      unsigned int WPNDTRM    :  1;  /**< Pending Status of Posted Writes to TRM */
+      unsigned int reserved14 :  2;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SR1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR1_t__ */
+
+/*@}*/
+
+/** @defgroup CNT0 RTC Count 0 (CNT0) Register
+ *  RTC Count 0 (CNT0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_CNT0_Struct
+ *! \brief  RTC Count 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CNT0_t__
+typedef struct _ADI_RTC_CNT0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_CNT0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CNT0_t__ */
+
+/*@}*/
+
+/** @defgroup CNT1 RTC Count 1 (CNT1) Register
+ *  RTC Count 1 (CNT1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_CNT1_Struct
+ *! \brief  RTC Count 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CNT1_t__
+typedef struct _ADI_RTC_CNT1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_CNT1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CNT1_t__ */
+
+/*@}*/
+
+/** @defgroup ALM0 RTC Alarm 0 (ALM0) Register
+ *  RTC Alarm 0 (ALM0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_ALM0_Struct
+ *! \brief  RTC Alarm 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_ALM0_t__
+typedef struct _ADI_RTC_ALM0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_ALM0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_ALM0_t__ */
+
+/*@}*/
+
+/** @defgroup ALM1 RTC Alarm 1 (ALM1) Register
+ *  RTC Alarm 1 (ALM1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_ALM1_Struct
+ *! \brief  RTC Alarm 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_ALM1_t__
+typedef struct _ADI_RTC_ALM1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_ALM1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_ALM1_t__ */
+
+/*@}*/
+
+/** @defgroup TRM RTC Trim (TRM) Register
+ *  RTC Trim (TRM) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_TRM_Struct
+ *! \brief  RTC Trim Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_TRM_t__
+typedef struct _ADI_RTC_TRM_t {
+  union {
+    struct {
+      unsigned int VALUE      :  3;  /**< Trim Value in Prescaled RTC Time Units to Be Added or Subtracted from the RTC Count at the End of a Periodic Interval Selected by TRM:TRMIVL */
+      unsigned int ADD        :  1;  /**< Trim Polarity */
+      unsigned int IVL        :  2;  /**< Trim Interval in Prescaled RTC Time Units */
+      unsigned int IVL2EXPMIN :  4;  /**< Minimum Power-of-two Interval of Prescaled RTC Time Units Which TRM:TRMIVL TRMIVL Can Select */
+      unsigned int reserved10 :  6;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_TRM_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_TRM_t__ */
+
+/*@}*/
+
+/** @defgroup GWY RTC Gateway (GWY) Register
+ *  RTC Gateway (GWY) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_GWY_Struct
+ *! \brief  RTC Gateway Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_GWY_t__
+typedef struct _ADI_RTC_GWY_t {
+  union {
+    struct {
+      unsigned int SWKEY      : 16;  /**< Software-keyed Command Issued by the CPU */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_GWY_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_GWY_t__ */
+
+/*@}*/
+
+/** @defgroup CR1 RTC Control 1 (CR1) Register
+ *  RTC Control 1 (CR1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_CR1_Struct
+ *! \brief  RTC Control 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR1_t__
+typedef struct _ADI_RTC_CR1_t {
+  union {
+    struct {
+      unsigned int CNTINTEN   :  1;  /**< Enable for the RTC Count Interrupt Source */
+      unsigned int PSINTEN    :  1;  /**< Enable for the Prescaled, Modulo-1 Interrupt Source, in SR2:RTCPSINT */
+      unsigned int TRMINTEN   :  1;  /**< Enable for the RTC Trim Interrupt Source, in SR2:RTCTRMINT */
+      unsigned int CNTROLLINTEN :  1;  /**< Enable for the RTC Count Roll-Over Interrupt Source, in SR2:RTCCNTROLLINT */
+      unsigned int CNTMOD60ROLLINTEN :  1;  /**< Enable for the RTC Modulo-60 Count Roll-Over Interrupt Source, in SR2:RTCCNTMOD60ROLLINT    */
+      unsigned int PRESCALE2EXP      :  4;  /**< Prescale Power of 2 Division Factor for the RTC Base Clock */
+      unsigned int reserved9         :  7;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_CR1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR1_t__ */
+
+/*@}*/
+
+/** @defgroup SR2 RTC Status 2 (SR2) Register
+ *  RTC Status 2 (SR2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SR2_Struct
+ *! \brief  RTC Status 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR2_t__
+typedef struct _ADI_RTC_SR2_t {
+  union {
+    struct {
+      unsigned int CNTINT     :  1;  /**< RTC Count Interrupt Source */
+      unsigned int PSINT      :  1;  /**< RTC Prescaled, Modulo-1 Boundary Interrupt Source */
+      unsigned int TRMINT     :  1;  /**< RTC Trim Interrupt Source */
+      unsigned int CNTROLLINT :  1;  /**< RTC Count Roll-Over Interrupt Source */
+      unsigned int CNTMOD60ROLLINT :  1;  /**< RTC Modulo-60 Count Roll-Over Interrupt Source */
+      unsigned int CNTROLL         :  1;  /**< RTC Count Roll-Over */
+      unsigned int CNTMOD60ROLL    :  1;  /**< RTC Count Modulo-60 Roll-Over */
+      unsigned int TRMBDYMIR       :  1;  /**< Mirror of MOD:RTCTRMBDY */
+      unsigned int reserved8       :  4;
+      unsigned int WPNDCR1MIR      :  1;  /**< Pending Status of Posted Writes to CR1 */
+      unsigned int WPNDALM2MIR     :  1;  /**< Pending Status of Posted Writes to ALM2 */
+      unsigned int WSYNCCR1MIR     :  1;  /**< Synchronization Status of Posted Writes to CR1 */
+      unsigned int WSYNCALM2MIR    :  1;  /**< Synchronization Status of Posted Writes to ALM2 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SR2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR2_t__ */
+
+/*@}*/
+
+/** @defgroup SNAP0 RTC Snapshot 0 (SNAP0) Register
+ *  RTC Snapshot 0 (SNAP0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SNAP0_Struct
+ *! \brief  RTC Snapshot 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SNAP0_t__
+typedef struct _ADI_RTC_SNAP0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Constituent Part of the 47-bit Input Capture Channel 0, Containing a Sticky Snapshot of  CNT0 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SNAP0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SNAP0_t__ */
+
+/*@}*/
+
+/** @defgroup SNAP1 RTC Snapshot 1 (SNAP1) Register
+ *  RTC Snapshot 1 (SNAP1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SNAP1_Struct
+ *! \brief  RTC Snapshot 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SNAP1_t__
+typedef struct _ADI_RTC_SNAP1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of  CNT1 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SNAP1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SNAP1_t__ */
+
+/*@}*/
+
+/** @defgroup SNAP2 RTC Snapshot 2 (SNAP2) Register
+ *  RTC Snapshot 2 (SNAP2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SNAP2_Struct
+ *! \brief  RTC Snapshot 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SNAP2_t__
+typedef struct _ADI_RTC_SNAP2_t {
+  union {
+    struct {
+      unsigned int VALUE      : 15;  /**< Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT2 */
+      unsigned int reserved15 :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SNAP2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SNAP2_t__ */
+
+/*@}*/
+
+/** @defgroup MOD RTC Modulo (MOD) Register
+ *  RTC Modulo (MOD) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_MOD_Struct
+ *! \brief  RTC Modulo Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_MOD_t__
+typedef struct _ADI_RTC_MOD_t {
+  union {
+    struct {
+      unsigned int CNTMOD60   :  6;  /**< Modulo-60 Value of the RTC Count: CNT1 and CNT0 */
+      unsigned int INCR       :  4;  /**< Most Recent Increment Value Added to the RTC Count in CNT1 and CNT0 */
+      unsigned int TRMBDY     :  1;  /**< Trim Boundary Indicator */
+      unsigned int CNT0_4TOZERO :  5;  /**< Mirror of CNT0[4:0] */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_MOD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_MOD_t__ */
+
+/*@}*/
+
+/** @defgroup CNT2 RTC Count 2 (CNT2) Register
+ *  RTC Count 2 (CNT2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_CNT2_Struct
+ *! \brief  RTC Count 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CNT2_t__
+typedef struct _ADI_RTC_CNT2_t {
+  union {
+    struct {
+      unsigned int VALUE      : 15;  /**< Fractional Bits of the RTC Real-Time Count */
+      unsigned int reserved15 :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_CNT2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CNT2_t__ */
+
+/*@}*/
+
+/** @defgroup ALM2 RTC Alarm 2 (ALM2) Register
+ *  RTC Alarm 2 (ALM2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_ALM2_Struct
+ *! \brief  RTC Alarm 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_ALM2_t__
+typedef struct _ADI_RTC_ALM2_t {
+  union {
+    struct {
+      unsigned int VALUE      : 15;  /**< Fractional Bits of the Alarm Target Time */
+      unsigned int reserved15 :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_ALM2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_ALM2_t__ */
+
+/*@}*/
+
+/** @defgroup SR3 RTC Status 3 (SR3) Register
+ *  RTC Status 3 (SR3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SR3_Struct
+ *! \brief  RTC Status 3 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR3_t__
+typedef struct _ADI_RTC_SR3_t {
+  union {
+    struct {
+      unsigned int IC0IRQ     :  1;  /**< Sticky Interrupt Source for the RTC Input Capture Channel 0 */
+      unsigned int reserved1  :  1;
+      unsigned int IC2IRQ     :  1;  /**< Sticky Interrupt Source for the RTC Input Capture Channel 2 */
+      unsigned int IC3IRQ     :  1;  /**< Sticky Interrupt Source for the RTC Input Capture Channel 3 */
+      unsigned int IC4IRQ     :  1;  /**< Sticky Interrupt Source for the RTC Input Capture Channel 4 */
+      unsigned int reserved5  :  3;
+      unsigned int ALMINTMIR  :  1;  /**< Read-only Mirror of the ALMINT Interrupt Source in SR0 Register */
+      unsigned int SS1IRQ     :  1;  /**< Sticky Interrupt Source for SensorStrobe Channel 1 */
+      unsigned int reserved10 :  6;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SR3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR3_t__ */
+
+/*@}*/
+
+/** @defgroup CR2IC RTC Control 2 for Configuring Input Capture Channels (CR2IC) Register
+ *  RTC Control 2 for Configuring Input Capture Channels (CR2IC) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_CR2IC_Struct
+ *! \brief  RTC Control 2 for Configuring Input Capture Channels Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR2IC_t__
+typedef struct _ADI_RTC_CR2IC_t {
+  union {
+    struct {
+      unsigned int IC0EN      :  1;  /**< Enable for the RTC Input Capture Channel 0 */
+      unsigned int reserved1  :  1;
+      unsigned int IC2EN      :  1;  /**< Enable for the RTC Input Capture Channel 2 */
+      unsigned int IC3EN      :  1;  /**< Enable for the RTC Input Capture Channel 3 */
+      unsigned int IC4EN      :  1;  /**< Enable for the RTC Input Capture Channel 4 */
+      unsigned int IC0LH      :  1;  /**< Polarity of the Active-Going Capture Edge for the RTC Input Capture Channel 0 */
+      unsigned int reserved6  :  1;
+      unsigned int IC2LH      :  1;  /**< Polarity of the Active-going Capture Edge for the Input Capture Channel 2 */
+      unsigned int IC3LH      :  1;  /**< Polarity of the Active-going Capture Edge for the Input Capture Channel 3 */
+      unsigned int IC4LH      :  1;  /**< Polarity of the Active-going Capture Edge for the Input Capture Channel 4 */
+      unsigned int IC0IRQEN   :  1;  /**< Interrupt Enable for the RTC Input Capture Channel 0 */
+      unsigned int reserved11 :  1;
+      unsigned int IC2IRQEN   :  1;  /**< Interrupt Enable for the RTC Input Capture Channel 2 */
+      unsigned int IC3IRQEN   :  1;  /**< Interrupt Enable for the RTC Input Capture Channel 3 */
+      unsigned int IC4IRQEN   :  1;  /**< Interrupt Enable for the RTC Input Capture Channel 4 */
+      unsigned int ICOWUSEN   :  1;  /**< Enable Overwrite of Unread Snapshots for All Input Capture Channels */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_CR2IC_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR2IC_t__ */
+
+/*@}*/
+
+/** @defgroup CR3SS RTC Control 3 for Configuring SensorStrobe Channel (CR3SS) Register
+ *  RTC Control 3 for Configuring SensorStrobe Channel (CR3SS) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_CR3SS_Struct
+ *! \brief  RTC Control 3 for Configuring SensorStrobe Channel Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR3SS_t__
+typedef struct _ADI_RTC_CR3SS_t {
+  union {
+    struct {
+      unsigned int reserved0  :  1;
+      unsigned int SS1EN      :  1;  /**< Enable for SensorStrobe Channel 1 */
+      unsigned int reserved2  :  7;
+      unsigned int SS1IRQEN   :  1;  /**< Interrupt Enable for SensorStrobe Channel 1 */
+      unsigned int reserved10 :  6;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_CR3SS_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR3SS_t__ */
+
+/*@}*/
+
+/** @defgroup CR4SS RTC Control 4 for Configuring SensorStrobe Channel (CR4SS) Register
+ *  RTC Control 4 for Configuring SensorStrobe Channel (CR4SS) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_RTC_CR4SS_SS1MSKEN
+ *! \brief  Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 (SS1MSKEN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  RTC_CR4SS_NO_MSK    = 0,  /**< Do not apply a mask to SensorStrobe Channel 1 Register */
+  RTC_CR4SS_THERM_MSK = 1   /**< Apply thermometer decoded mask                         */
+} ADI_RTC_CR4SS_SS1MSKEN;
+
+
+/* ==========================================================================
+ *! \struct ADI_RTC_CR4SS_Struct
+ *! \brief  RTC Control 4 for Configuring SensorStrobe Channel Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR4SS_t__
+typedef struct _ADI_RTC_CR4SS_t {
+  union {
+    struct {
+      unsigned int reserved0  :  1;
+      unsigned int SS1MSKEN   :  1;  /**< Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 */
+      unsigned int reserved2  :  7;
+      unsigned int SS1ARLEN   :  1;  /**< Enable for Auto-Reloading When SensorStrobe Match Occurs */
+      unsigned int reserved10 :  6;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_CR4SS_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR4SS_t__ */
+
+/*@}*/
+
+/** @defgroup SSMSK RTC Mask for SensorStrobe Channel (SSMSK) Register
+ *  RTC Mask for SensorStrobe Channel (SSMSK) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SSMSK_Struct
+ *! \brief  RTC Mask for SensorStrobe Channel Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SSMSK_t__
+typedef struct _ADI_RTC_SSMSK_t {
+  union {
+    struct {
+      unsigned int SSMSK      : 16;  /**< Thermometer-Encoded Masks for SensorStrobe Channels */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SSMSK_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SSMSK_t__ */
+
+/*@}*/
+
+/** @defgroup SS1ARL RTC Auto-Reload for SensorStrobe Channel 1 (SS1ARL) Register
+ *  RTC Auto-Reload for SensorStrobe Channel 1 (SS1ARL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SS1ARL_Struct
+ *! \brief  RTC Auto-Reload for SensorStrobe Channel 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS1ARL_t__
+typedef struct _ADI_RTC_SS1ARL_t {
+  union {
+    struct {
+      unsigned int SS1ARL     : 16;  /**< Auto-Reload Value When SensorStrobe Match Occurs */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SS1ARL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS1ARL_t__ */
+
+/*@}*/
+
+/** @defgroup IC2 RTC Input Capture Channel 2 (IC2) Register
+ *  RTC Input Capture Channel 2 (IC2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_IC2_Struct
+ *! \brief  RTC Input Capture Channel 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_IC2_t__
+typedef struct _ADI_RTC_IC2_t {
+  union {
+    struct {
+      unsigned int IC2        : 16;  /**< RTC Input Capture Channel 2 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_IC2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_IC2_t__ */
+
+/*@}*/
+
+/** @defgroup IC3 RTC Input Capture Channel 3 (IC3) Register
+ *  RTC Input Capture Channel 3 (IC3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_IC3_Struct
+ *! \brief  RTC Input Capture Channel 3 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_IC3_t__
+typedef struct _ADI_RTC_IC3_t {
+  union {
+    struct {
+      unsigned int IC3        : 16;  /**< RTC Input Capture Channel 3 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_IC3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_IC3_t__ */
+
+/*@}*/
+
+/** @defgroup IC4 RTC Input Capture Channel 4 (IC4) Register
+ *  RTC Input Capture Channel 4 (IC4) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_IC4_Struct
+ *! \brief  RTC Input Capture Channel 4 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_IC4_t__
+typedef struct _ADI_RTC_IC4_t {
+  union {
+    struct {
+      unsigned int IC4        : 16;  /**< RTC Input Capture Channel 4 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_IC4_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_IC4_t__ */
+
+/*@}*/
+
+/** @defgroup SS1 RTC SensorStrobe Channel 1 (SS1) Register
+ *  RTC SensorStrobe Channel 1 (SS1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SS1_Struct
+ *! \brief  RTC SensorStrobe Channel 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS1_t__
+typedef struct _ADI_RTC_SS1_t {
+  union {
+    struct {
+      unsigned int SS1        : 16;  /**< SensorStrobe Channel 1 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SS1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS1_t__ */
+
+/*@}*/
+
+/** @defgroup SR4 RTC Status 4 (SR4) Register
+ *  RTC Status 4 (SR4) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SR4_Struct
+ *! \brief  RTC Status 4 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR4_t__
+typedef struct _ADI_RTC_SR4_t {
+  union {
+    struct {
+      unsigned int WSYNCSR3   :  1;  /**< Synchronisation Status of Posted Writes to SR3 */
+      unsigned int WSYNCCR2IC :  1;  /**< Synchronization Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */
+      unsigned int WSYNCCR3SS :  1;  /**< Synchronization Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */
+      unsigned int WSYNCCR4SS :  1;  /**< Synchronization Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */
+      unsigned int WSYNCSSMSK :  1;  /**< Synchronization Status of Posted Writes to Masks for SensorStrobe Channel Register */
+      unsigned int WSYNCSS1ARL :  1;  /**< Synchronization Status of Posted Writes to RTC Auto-Reload for SensorStrobe Channel 1 Register */
+      unsigned int WSYNCSS1    :  1;  /**< Synchronization Status of Posted Writes to SensorStrobe Channel 1 */
+      unsigned int reserved7   :  3;
+      unsigned int RSYNCIC0    :  1;  /**< Synchronization Status of Posted Reads of RTC Input Channel 0 */
+      unsigned int reserved11  :  1;
+      unsigned int RSYNCIC2    :  1;  /**< Synchronization Status of Posted Reads of RTC Input Channel 2 */
+      unsigned int RSYNCIC3    :  1;  /**< Synchronization Status of Posted Reads of RTC Input Channel 3 */
+      unsigned int RSYNCIC4    :  1;  /**< Synchronization Status of Posted Reads of RTC Input Channel 4 */
+      unsigned int reserved15  :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SR4_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR4_t__ */
+
+/*@}*/
+
+/** @defgroup SR5 RTC Status 5 (SR5) Register
+ *  RTC Status 5 (SR5) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SR5_Struct
+ *! \brief  RTC Status 5 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR5_t__
+typedef struct _ADI_RTC_SR5_t {
+  union {
+    struct {
+      unsigned int WPENDSR3   :  1;  /**< Pending Status of Posted Clearances of Interrupt Sources in RTC Status 3 Register */
+      unsigned int WPENDCR2IC :  1;  /**< Pending Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */
+      unsigned int WPENDCR3SS :  1;  /**< Pending Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */
+      unsigned int WPENDCR4SS :  1;  /**< Pending Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */
+      unsigned int WPENDSSMSK :  1;  /**< Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */
+      unsigned int WPENDSS1ARL :  1;  /**< Pending Status of Posted Writes to RTC Auto-Reload for SensorStrobe Channel 1 Register */
+      unsigned int WPENDSS1    :  1;  /**< Pending Status of Posted Writes to SensorStrobe Channel 1 */
+      unsigned int reserved7   :  3;
+      unsigned int RPENDIC0    :  1;  /**< Pending Status of Posted Reads of Input Capture Channel 0 */
+      unsigned int reserved11  :  1;
+      unsigned int RPENDIC2    :  1;  /**< Pending Status of Posted Reads of IC2 */
+      unsigned int RPENDIC3    :  1;  /**< Pending Status of Posted Reads of IC3 */
+      unsigned int RPENDIC4    :  1;  /**< Pending Status of Posted Reads of IC4 */
+      unsigned int reserved15  :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SR5_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR5_t__ */
+
+/*@}*/
+
+/** @defgroup SR6 RTC Status 6 (SR6) Register
+ *  RTC Status 6 (SR6) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SR6_Struct
+ *! \brief  RTC Status 6 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR6_t__
+typedef struct _ADI_RTC_SR6_t {
+  union {
+    struct {
+      unsigned int IC0UNR     :  1;  /**< Sticky Unread Status of the Input Capture Channel 0 */
+      unsigned int reserved1  :  1;
+      unsigned int IC2UNR     :  1;  /**< Sticky Unread Status of the Input Capture Channel 2 */
+      unsigned int IC3UNR     :  1;  /**< Sticky Unread Status of the Input Capture Channel 3 */
+      unsigned int IC4UNR     :  1;  /**< Sticky Unread Status of the Input Capture Channel 4 */
+      unsigned int reserved5  :  3;
+      unsigned int IC0SNAP    :  1;  /**< Confirmation That RTC Snapshot 0, 1, 2 Registers Reflect the Value of Input-Capture Channel RTC Input Capture Channel 0 */
+      unsigned int FRZCNTPTR  :  2;  /**< Pointer for the Triple-Read Sequence of FRZCNT */
+      unsigned int reserved11 :  5;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SR6_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR6_t__ */
+
+/*@}*/
+
+/** @defgroup SS1TGT RTC SensorStrobe Channel 1 Target (SS1TGT) Register
+ *  RTC SensorStrobe Channel 1 Target (SS1TGT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SS1TGT_Struct
+ *! \brief  RTC SensorStrobe Channel 1 Target Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS1TGT_t__
+typedef struct _ADI_RTC_SS1TGT_t {
+  union {
+    struct {
+      unsigned int SS1TGT     : 16;  /**< Current Target Value for the SensorStrobe Channel 1 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SS1TGT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS1TGT_t__ */
+
+/*@}*/
+
+/** @defgroup FRZCNT RTC Freeze Count (FRZCNT) Register
+ *  RTC Freeze Count (FRZCNT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_FRZCNT_Struct
+ *! \brief  RTC Freeze Count Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_FRZCNT_t__
+typedef struct _ADI_RTC_FRZCNT_t {
+  union {
+    struct {
+      unsigned int FRZCNT     : 16;  /**< RTC Freeze Count. Coherent, Triple 16-Bit Read of the 47-Bit RTC Count */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_FRZCNT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_FRZCNT_t__ */
+
+/*@}*/
+
+/** @defgroup ADIID ADI Identification (ADIID) Register
+ *  ADI Identification (ADIID) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SYS_ADIID_Struct
+ *! \brief  ADI Identification Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SYS_ADIID_t__
+typedef struct _ADI_SYS_ADIID_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< ADI Cortex Device */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SYS_ADIID_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SYS_ADIID_t__ */
+
+/*@}*/
+
+/** @defgroup CHIPID Chip Identifier (CHIPID) Register
+ *  Chip Identifier (CHIPID) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SYS_CHIPID_Struct
+ *! \brief  Chip Identifier Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SYS_CHIPID_t__
+typedef struct _ADI_SYS_CHIPID_t {
+  union {
+    struct {
+      unsigned int REV        :  4;  /**< Silicon Revision */
+      unsigned int PARTID     : 12;  /**< Part Identifier */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SYS_CHIPID_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SYS_CHIPID_t__ */
+
+/*@}*/
+
+/** @defgroup SWDEN Serial Wire Debug Enable (SWDEN) Register
+ *  Serial Wire Debug Enable (SWDEN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SYS_SWDEN_Struct
+ *! \brief  Serial Wire Debug Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SYS_SWDEN_t__
+typedef struct _ADI_SYS_SWDEN_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< SWD Interface Enable */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SYS_SWDEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SYS_SWDEN_t__ */
+
+/*@}*/
+
+/** @defgroup LOAD Load Value (LOAD) Register
+ *  Load Value (LOAD) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_WDT_LOAD_Struct
+ *! \brief  Load Value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_LOAD_t__
+typedef struct _ADI_WDT_LOAD_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Load Value */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_WDT_LOAD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_LOAD_t__ */
+
+/*@}*/
+
+/** @defgroup CCNT Current Count Value (CCNT) Register
+ *  Current Count Value (CCNT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_WDT_CCNT_Struct
+ *! \brief  Current Count Value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_CCNT_t__
+typedef struct _ADI_WDT_CCNT_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Current Count Value */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_WDT_CCNT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_CCNT_t__ */
+
+/*@}*/
+
+/** @defgroup CTL Control (CTL) Register
+ *  Control (CTL) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_WDT_CTL_IRQ
+ *! \brief  Timer Interrupt (IRQ) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  WDT_CTL_RST = 0,  /**< WDT asserts reset when timed out       */
+  WDT_CTL_INT = 1   /**< WDT generates interrupt when timed out */
+} ADI_WDT_CTL_IRQ;
+
+
+/*  =========================================================================
+ *! \enum   ADI_WDT_CTL_PRE
+ *! \brief  Prescaler (PRE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  WDT_CTL_DIV1   = 0,  /**< Source clock/1             */
+  WDT_CTL_DIV16  = 1,  /**< Source clock/16            */
+  WDT_CTL_DIV256 = 2   /**< Source clock/256 (default) */
+} ADI_WDT_CTL_PRE;
+
+
+/*  =========================================================================
+ *! \enum   ADI_WDT_CTL_EN
+ *! \brief  Timer Enable (EN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  WDT_CTL_WDT_DIS = 0,  /**< WDT not enabled */
+  WDT_CTL_WDT_EN  = 1   /**< WDT enabled     */
+} ADI_WDT_CTL_EN;
+
+
+/*  =========================================================================
+ *! \enum   ADI_WDT_CTL_MODE
+ *! \brief  Timer Mode (MODE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  WDT_CTL_FREE_RUN = 0,  /**< Free running mode */
+  WDT_CTL_PERIODIC = 1   /**< Periodic mode     */
+} ADI_WDT_CTL_MODE;
+
+
+/* ==========================================================================
+ *! \struct ADI_WDT_CTL_Struct
+ *! \brief  Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_CTL_t__
+typedef struct _ADI_WDT_CTL_t {
+  union {
+    struct {
+      unsigned int reserved0  :  1;
+      unsigned int IRQ        :  1;  /**< Timer Interrupt */
+      unsigned int PRE        :  2;  /**< Prescaler */
+      unsigned int reserved4  :  1;
+      unsigned int EN         :  1;  /**< Timer Enable */
+      unsigned int MODE       :  1;  /**< Timer Mode */
+      unsigned int SPARE      :  1;  /**< Unused Spare Bit */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_WDT_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup RESTART Clear Interrupt (RESTART) Register
+ *  Clear Interrupt (RESTART) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_WDT_RESTART_Struct
+ *! \brief  Clear Interrupt Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_RESTART_t__
+typedef struct _ADI_WDT_RESTART_t {
+  union {
+    struct {
+      unsigned int CLRWORD    : 16;  /**< Clear Watchdog */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_WDT_RESTART_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_RESTART_t__ */
+
+/*@}*/
+
+/** @defgroup STAT Status (STAT) Register
+ *  Status (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_WDT_STAT_Struct
+ *! \brief  Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_STAT_t__
+typedef struct _ADI_WDT_STAT_t {
+  union {
+    struct {
+      unsigned int IRQ        :  1;  /**< WDT Interrupt */
+      unsigned int CLRIRQ     :  1;  /**< Clear Interrupt Register Write Sync in Progress */
+      unsigned int LOADING    :  1;  /**< Load Register Write Sync in Progress */
+      unsigned int COUNTING   :  1;  /**< Control Register Write Sync in Progress */
+      unsigned int LOCKED     :  1;  /**< Lock Status Bit */
+      unsigned int RSTCTL     :  1;  /**< Reset Control Register Written and Locked */
+      unsigned int reserved6  : 10;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_WDT_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup MCTL Master Control (MCTL) Register
+ *  Master Control (MCTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_MCTL_Struct
+ *! \brief  Master Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MCTL_t__
+typedef struct _ADI_I2C_MCTL_t {
+  union {
+    struct {
+      unsigned int MASEN      :  1;  /**< Master Enable */
+      unsigned int COMPLETE   :  1;  /**< Start Back-off Disable */
+      unsigned int LOOPBACK   :  1;  /**< Internal Loopback Enable */
+      unsigned int STRETCHSCL :  1;  /**< Stretch SCL Enable */
+      unsigned int IENMRX     :  1;  /**< Receive Request Interrupt Enable */
+      unsigned int IENMTX     :  1;  /**< Transmit Request Interrupt Enable */
+      unsigned int IENALOST   :  1;  /**< Arbitration Lost Interrupt Enable */
+      unsigned int IENACK     :  1;  /**< ACK Not Received Interrupt Enable */
+      unsigned int IENCMP     :  1;  /**< Transaction Completed (or Stop Detected) Interrupt Enable */
+      unsigned int MXMITDEC   :  1;  /**< Decrement Master Tx FIFO Status When a Byte Txed */
+      unsigned int MRXDMA     :  1;  /**< Enable Master Rx DMA Request */
+      unsigned int MTXDMA     :  1;  /**< Enable Master Tx DMA Request */
+      unsigned int BUSCLR     :  1;  /**< Bus-Clear Enable */
+      unsigned int STOPBUSCLR :  1;  /**< Prestop Bus Clear */
+      unsigned int reserved14 :  2;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_MCTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MCTL_t__ */
+
+/*@}*/
+
+/** @defgroup MSTAT Master Status (MSTAT) Register
+ *  Master Status (MSTAT) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_I2C_MSTAT_MTXF
+ *! \brief  Master Transmit FIFO Status (MTXF) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  I2C_MSTAT_FIFO_EMPTY = 0,  /**< FIFO Empty.     */
+  I2C_MSTAT_FIFO_1BYTE = 2,  /**< 1 byte in FIFO. */
+  I2C_MSTAT_FIFO_FULL  = 3   /**< FIFO Full.      */
+} ADI_I2C_MSTAT_MTXF;
+
+
+/* ==========================================================================
+ *! \struct ADI_I2C_MSTAT_Struct
+ *! \brief  Master Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MSTAT_t__
+typedef struct _ADI_I2C_MSTAT_t {
+  union {
+    struct {
+      unsigned int MTXF       :  2;  /**< Master Transmit FIFO Status */
+      unsigned int MTXREQ     :  1;  /**< Master Transmit Request/Clear Master Transmit Interrupt */
+      unsigned int MRXREQ     :  1;  /**< Master Receive Request */
+      unsigned int NACKADDR   :  1;  /**< ACK Not Received in Response to an Address */
+      unsigned int ALOST      :  1;  /**< Arbitration Lost */
+      unsigned int MBUSY      :  1;  /**< Master Busy */
+      unsigned int NACKDATA   :  1;  /**< ACK Not Received in Response to Data Write */
+      unsigned int TCOMP      :  1;  /**< Transaction Complete or Stop Detected */
+      unsigned int MRXOVR     :  1;  /**< Master Receive FIFO Overflow */
+      unsigned int LINEBUSY   :  1;  /**< Line is Busy */
+      unsigned int MSTOP      :  1;  /**< STOP Driven by This I2C Master */
+      unsigned int MTXUNDR    :  1;  /**< Master Transmit Underflow */
+      unsigned int SDAFILT    :  1;  /**< State of SDA Line */
+      unsigned int SCLFILT    :  1;  /**< State of SCL Line */
+      unsigned int reserved15 :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_MSTAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MSTAT_t__ */
+
+/*@}*/
+
+/** @defgroup MRX Master Receive Data (MRX) Register
+ *  Master Receive Data (MRX) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_MRX_Struct
+ *! \brief  Master Receive Data Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MRX_t__
+typedef struct _ADI_I2C_MRX_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Master Receive Register */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_MRX_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MRX_t__ */
+
+/*@}*/
+
+/** @defgroup MTX Master Transmit Data (MTX) Register
+ *  Master Transmit Data (MTX) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_MTX_Struct
+ *! \brief  Master Transmit Data Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MTX_t__
+typedef struct _ADI_I2C_MTX_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Master Transmit Register */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_MTX_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MTX_t__ */
+
+/*@}*/
+
+/** @defgroup MRXCNT Master Receive Data Count (MRXCNT) Register
+ *  Master Receive Data Count (MRXCNT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_MRXCNT_Struct
+ *! \brief  Master Receive Data Count Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MRXCNT_t__
+typedef struct _ADI_I2C_MRXCNT_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Receive Count */
+      unsigned int EXTEND     :  1;  /**< Extended Read */
+      unsigned int reserved9  :  7;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_MRXCNT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MRXCNT_t__ */
+
+/*@}*/
+
+/** @defgroup MCRXCNT Master Current Receive Data Count (MCRXCNT) Register
+ *  Master Current Receive Data Count (MCRXCNT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_MCRXCNT_Struct
+ *! \brief  Master Current Receive Data Count Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MCRXCNT_t__
+typedef struct _ADI_I2C_MCRXCNT_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Current Receive Count */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_MCRXCNT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MCRXCNT_t__ */
+
+/*@}*/
+
+/** @defgroup ADDR1 Master Address Byte 1 (ADDR1) Register
+ *  Master Address Byte 1 (ADDR1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_ADDR1_Struct
+ *! \brief  Master Address Byte 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ADDR1_t__
+typedef struct _ADI_I2C_ADDR1_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Address Byte 1 */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_ADDR1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ADDR1_t__ */
+
+/*@}*/
+
+/** @defgroup ADDR2 Master Address Byte 2 (ADDR2) Register
+ *  Master Address Byte 2 (ADDR2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_ADDR2_Struct
+ *! \brief  Master Address Byte 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ADDR2_t__
+typedef struct _ADI_I2C_ADDR2_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Address Byte 2 */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_ADDR2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ADDR2_t__ */
+
+/*@}*/
+
+/** @defgroup BYT Start Byte (BYT) Register
+ *  Start Byte (BYT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_BYT_Struct
+ *! \brief  Start Byte Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_BYT_t__
+typedef struct _ADI_I2C_BYT_t {
+  union {
+    struct {
+      unsigned int SBYTE      :  8;  /**< Start Byte */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_BYT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_BYT_t__ */
+
+/*@}*/
+
+/** @defgroup DIV Serial Clock Period Divisor (DIV) Register
+ *  Serial Clock Period Divisor (DIV) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_DIV_Struct
+ *! \brief  Serial Clock Period Divisor Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_DIV_t__
+typedef struct _ADI_I2C_DIV_t {
+  union {
+    struct {
+      unsigned int LOW        :  8;  /**< Serial Clock Low Time */
+      unsigned int HIGH       :  8;  /**< Serial Clock High Time */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_DIV_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_DIV_t__ */
+
+/*@}*/
+
+/** @defgroup SCTL Slave Control (SCTL) Register
+ *  Slave Control (SCTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_SCTL_Struct
+ *! \brief  Slave Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_SCTL_t__
+typedef struct _ADI_I2C_SCTL_t {
+  union {
+    struct {
+      unsigned int SLVEN      :  1;  /**< Slave Enable */
+      unsigned int ADR10EN    :  1;  /**< Enabled 10-bit Addressing */
+      unsigned int GCEN       :  1;  /**< General Call Enable */
+      unsigned int HGCEN      :  1;  /**< Hardware General Call Enable */
+      unsigned int GCSBCLR    :  1;  /**< General Call Status Bit Clear */
+      unsigned int EARLYTXR   :  1;  /**< Early Transmit Request Mode */
+      unsigned int reserved6  :  1;
+      unsigned int NACK       :  1;  /**< NACK Next Communication */
+      unsigned int IENSTOP    :  1;  /**< Stop Condition Detected Interrupt Enable */
+      unsigned int IENSRX     :  1;  /**< Slave Receive Request Interrupt Enable */
+      unsigned int IENSTX     :  1;  /**< Slave Transmit Request Interrupt Enable */
+      unsigned int STXDEC     :  1;  /**< Decrement Slave Tx FIFO Status When a Byte is Txed */
+      unsigned int IENREPST   :  1;  /**< Repeated Start Interrupt Enable */
+      unsigned int SRXDMA     :  1;  /**< Enable Slave Rx DMA Request */
+      unsigned int STXDMA     :  1;  /**< Enable Slave Tx DMA Request */
+      unsigned int reserved15 :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_SCTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_SCTL_t__ */
+
+/*@}*/
+
+/** @defgroup SSTAT Slave I2C Status/Error/IRQ (SSTAT) Register
+ *  Slave I2C Status/Error/IRQ (SSTAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_SSTAT_Struct
+ *! \brief  Slave I2C Status/Error/IRQ Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_SSTAT_t__
+typedef struct _ADI_I2C_SSTAT_t {
+  union {
+    struct {
+      unsigned int STXFSEREQ  :  1;  /**< Slave Tx FIFO Status or Early Request */
+      unsigned int STXUNDR    :  1;  /**< Slave Transmit FIFO Underflow */
+      unsigned int STXREQ     :  1;  /**< Slave Transmit Request/Slave Transmit Interrupt */
+      unsigned int SRXREQ     :  1;  /**< Slave Receive Request */
+      unsigned int SRXOVR     :  1;  /**< Slave Receive FIFO Overflow */
+      unsigned int NOACK      :  1;  /**< ACK Not Generated by the Slave */
+      unsigned int SBUSY      :  1;  /**< Slave Busy */
+      unsigned int GCINT      :  1;  /**< General Call Interrupt */
+      unsigned int GCID       :  2;  /**< General ID */
+      unsigned int STOP       :  1;  /**< Stop After Start and Matching Address */
+      unsigned int IDMAT      :  2;  /**< Device ID Matched */
+      unsigned int REPSTART   :  1;  /**< Repeated Start and Matching Address */
+      unsigned int START      :  1;  /**< Start and Matching Address */
+      unsigned int reserved15 :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_SSTAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_SSTAT_t__ */
+
+/*@}*/
+
+/** @defgroup SRX Slave Receive (SRX) Register
+ *  Slave Receive (SRX) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_SRX_Struct
+ *! \brief  Slave Receive Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_SRX_t__
+typedef struct _ADI_I2C_SRX_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Slave Receive Register */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_SRX_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_SRX_t__ */
+
+/*@}*/
+
+/** @defgroup STX Slave Transmit (STX) Register
+ *  Slave Transmit (STX) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_STX_Struct
+ *! \brief  Slave Transmit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_STX_t__
+typedef struct _ADI_I2C_STX_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Slave Transmit Register */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_STX_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_STX_t__ */
+
+/*@}*/
+
+/** @defgroup ALT Hardware General Call ID (ALT) Register
+ *  Hardware General Call ID (ALT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_ALT_Struct
+ *! \brief  Hardware General Call ID Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ALT_t__
+typedef struct _ADI_I2C_ALT_t {
+  union {
+    struct {
+      unsigned int ID         :  8;  /**< Slave Alt */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_ALT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ALT_t__ */
+
+/*@}*/
+
+/** @defgroup ID0 First Slave Address Device ID (ID0) Register
+ *  First Slave Address Device ID (ID0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_ID0_Struct
+ *! \brief  First Slave Address Device ID Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ID0_t__
+typedef struct _ADI_I2C_ID0_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Slave Device ID 0 */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_ID0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ID0_t__ */
+
+/*@}*/
+
+/** @defgroup ID1 Second Slave Address Device ID (ID1) Register
+ *  Second Slave Address Device ID (ID1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_ID1_Struct
+ *! \brief  Second Slave Address Device ID Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ID1_t__
+typedef struct _ADI_I2C_ID1_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Slave Device ID 1 */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_ID1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ID1_t__ */
+
+/*@}*/
+
+/** @defgroup ID2 Third Slave Address Device ID (ID2) Register
+ *  Third Slave Address Device ID (ID2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_ID2_Struct
+ *! \brief  Third Slave Address Device ID Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ID2_t__
+typedef struct _ADI_I2C_ID2_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Slave Device ID 2 */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_ID2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ID2_t__ */
+
+/*@}*/
+
+/** @defgroup ID3 Fourth Slave Address Device ID (ID3) Register
+ *  Fourth Slave Address Device ID (ID3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_ID3_Struct
+ *! \brief  Fourth Slave Address Device ID Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ID3_t__
+typedef struct _ADI_I2C_ID3_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Slave Device ID 3 */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_ID3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ID3_t__ */
+
+/*@}*/
+
+/** @defgroup STAT Master and Slave FIFO Status (STAT) Register
+ *  Master and Slave FIFO Status (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_STAT_Struct
+ *! \brief  Master and Slave FIFO Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_STAT_t__
+typedef struct _ADI_I2C_STAT_t {
+  union {
+    struct {
+      unsigned int STXF       :  2;  /**< Slave Transmit FIFO Status */
+      unsigned int SRXF       :  2;  /**< Slave Receive FIFO Status */
+      unsigned int MTXF       :  2;  /**< Master Transmit FIFO Status */
+      unsigned int MRXF       :  2;  /**< Master Receive FIFO Status */
+      unsigned int SFLUSH     :  1;  /**< Flush the Slave Transmit FIFO */
+      unsigned int MFLUSH     :  1;  /**< Flush the Master Transmit FIFO */
+      unsigned int reserved10 :  6;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup SHCTL Shared Control (SHCTL) Register
+ *  Shared Control (SHCTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_SHCTL_Struct
+ *! \brief  Shared Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_SHCTL_t__
+typedef struct _ADI_I2C_SHCTL_t {
+  union {
+    struct {
+      unsigned int RST        :  1;  /**< Reset START STOP Detect Circuit */
+      unsigned int reserved1  : 15;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_SHCTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_SHCTL_t__ */
+
+/*@}*/
+
+/** @defgroup TCTL Timing Control Register (TCTL) Register
+ *  Timing Control Register (TCTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_TCTL_Struct
+ *! \brief  Timing Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_TCTL_t__
+typedef struct _ADI_I2C_TCTL_t {
+  union {
+    struct {
+      unsigned int THDATIN    :  5;  /**< Data in Hold Start */
+      unsigned int reserved5  :  3;
+      unsigned int FILTEROFF  :  1;  /**< Input Filter Control */
+      unsigned int reserved9  :  7;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_TCTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_TCTL_t__ */
+
+/*@}*/
+
+/** @defgroup ASTRETCH_SCL Automatic Stretch SCL (ASTRETCH_SCL) Register
+ *  Automatic Stretch SCL (ASTRETCH_SCL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_ASTRETCH_SCL_Struct
+ *! \brief  Automatic Stretch SCL Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ASTRETCH_SCL_t__
+typedef struct _ADI_I2C_ASTRETCH_SCL_t {
+  union {
+    struct {
+      unsigned int MST        :  4;  /**< Master Automatic Stretch Mode */
+      unsigned int SLV        :  4;  /**< Slave Automatic Stretch Mode */
+      unsigned int MSTTMO     :  1;  /**< Master Automatic Stretch Timeout */
+      unsigned int SLVTMO     :  1;  /**< Slave Automatic Stretch Timeout */
+      unsigned int reserved10 :  6;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_ASTRETCH_SCL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ASTRETCH_SCL_t__ */
+
+/*@}*/
+
+/** @defgroup STAT Status (STAT) Register
+ *  Status (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_STAT_Struct
+ *! \brief  Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_STAT_t__
+typedef struct _ADI_SPI_STAT_t {
+  union {
+    struct {
+      unsigned int IRQ        :  1;  /**< SPI Interrupt Status */
+      unsigned int XFRDONE    :  1;  /**< SPI Transfer Completion */
+      unsigned int TXEMPTY    :  1;  /**< SPI Tx FIFO Empty Interrupt */
+      unsigned int TXDONE     :  1;  /**< SPI Tx Done in Read Command Mode */
+      unsigned int TXUNDR     :  1;  /**< SPI Tx FIFO Underflow */
+      unsigned int TXIRQ      :  1;  /**< SPI Tx IRQ */
+      unsigned int RXIRQ      :  1;  /**< SPI Rx IRQ */
+      unsigned int RXOVR      :  1;  /**< SPI Rx FIFO Overflow */
+      unsigned int reserved8  :  3;
+      unsigned int CS         :  1;  /**< CS Status */
+      unsigned int CSERR      :  1;  /**< Detected a CS Error Condition in Slave Mode */
+      unsigned int CSRISE     :  1;  /**< Detected a Rising Edge on CS, in Slave CON Mode */
+      unsigned int CSFALL     :  1;  /**< Detected a Falling Edge on CS, in Slave CON Mode */
+      unsigned int RDY        :  1;  /**< Detected an Edge on Ready Indicator for Flow Control */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup RX Receive (RX) Register
+ *  Receive (RX) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_RX_Struct
+ *! \brief  Receive Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_RX_t__
+typedef struct _ADI_SPI_RX_t {
+  union {
+    struct {
+      unsigned int BYTE1      :  8;  /**< 8-bit Receive Buffer */
+      unsigned int BYTE2      :  8;  /**< 8-bit Receive Buffer, Used Only in DMA Modes */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_RX_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_RX_t__ */
+
+/*@}*/
+
+/** @defgroup TX Transmit (TX) Register
+ *  Transmit (TX) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_TX_Struct
+ *! \brief  Transmit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_TX_t__
+typedef struct _ADI_SPI_TX_t {
+  union {
+    struct {
+      unsigned int BYTE1      :  8;  /**< 8-bit Transmit Buffer */
+      unsigned int BYTE2      :  8;  /**< 8-bit Transmit Buffer, Used Only in DMA Modes */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_TX_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_TX_t__ */
+
+/*@}*/
+
+/** @defgroup DIV SPI Baud Rate Selection (DIV) Register
+ *  SPI Baud Rate Selection (DIV) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_DIV_Struct
+ *! \brief  SPI Baud Rate Selection Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_DIV_t__
+typedef struct _ADI_SPI_DIV_t {
+  union {
+    struct {
+      unsigned int VALUE      :  6;  /**< SPI Clock Divider */
+      unsigned int reserved6  : 10;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_DIV_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_DIV_t__ */
+
+/*@}*/
+
+/** @defgroup CTL SPI Configuration (CTL) Register
+ *  SPI Configuration (CTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_CTL_Struct
+ *! \brief  SPI Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_CTL_t__
+typedef struct _ADI_SPI_CTL_t {
+  union {
+    struct {
+      unsigned int SPIEN      :  1;  /**< SPI Enable */
+      unsigned int MASEN      :  1;  /**< Master Mode Enable */
+      unsigned int CPHA       :  1;  /**< Serial Clock Phase Mode */
+      unsigned int CPOL       :  1;  /**< Serial Clock Polarity */
+      unsigned int WOM        :  1;  /**< SPI Wired-OR Mode */
+      unsigned int LSB        :  1;  /**< LSB First Transfer Enable */
+      unsigned int TIM        :  1;  /**< SPI Transfer and Interrupt Mode */
+      unsigned int ZEN        :  1;  /**< Transmit Zeros Enable */
+      unsigned int RXOF       :  1;  /**< Rx Overflow Overwrite Enable */
+      unsigned int OEN        :  1;  /**< Slave MISO Output Enable */
+      unsigned int LOOPBACK   :  1;  /**< Loopback Enable */
+      unsigned int CON        :  1;  /**< Continuous Transfer Enable */
+      unsigned int RFLUSH     :  1;  /**< SPI Rx FIFO Flush Enable */
+      unsigned int TFLUSH     :  1;  /**< SPI Tx FIFO Flush Enable */
+      unsigned int CSRST      :  1;  /**< Reset Mode for CS Error Bit */
+      unsigned int reserved15 :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup IEN SPI Interrupts Enable (IEN) Register
+ *  SPI Interrupts Enable (IEN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_IEN_Struct
+ *! \brief  SPI Interrupts Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_IEN_t__
+typedef struct _ADI_SPI_IEN_t {
+  union {
+    struct {
+      unsigned int IRQMODE    :  3;  /**< SPI IRQ Mode Bits */
+      unsigned int reserved3  :  5;
+      unsigned int CS         :  1;  /**< Enable Interrupt on Every CS Edge in Slave CON Mode */
+      unsigned int TXUNDR     :  1;  /**< Tx Underflow Interrupt Enable */
+      unsigned int RXOVR      :  1;  /**< Rx Overflow Interrupt Enable */
+      unsigned int RDY        :  1;  /**< Ready Signal Edge Interrupt Enable */
+      unsigned int TXDONE     :  1;  /**< SPI Transmit Done Interrupt Enable */
+      unsigned int XFRDONE    :  1;  /**< SPI Transfer Completion Interrupt Enable */
+      unsigned int TXEMPTY    :  1;  /**< Tx FIFO Empty Interrupt Enable */
+      unsigned int reserved15 :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_IEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_IEN_t__ */
+
+/*@}*/
+
+/** @defgroup CNT Transfer Byte Count (CNT) Register
+ *  Transfer Byte Count (CNT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_CNT_Struct
+ *! \brief  Transfer Byte Count Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_CNT_t__
+typedef struct _ADI_SPI_CNT_t {
+  union {
+    struct {
+      unsigned int VALUE      : 14;  /**< Transfer Byte Count */
+      unsigned int reserved14 :  1;
+      unsigned int FRAMECONT  :  1;  /**< Continue Frame */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_CNT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_CNT_t__ */
+
+/*@}*/
+
+/** @defgroup DMA SPI DMA Enable (DMA) Register
+ *  SPI DMA Enable (DMA) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_DMA_Struct
+ *! \brief  SPI DMA Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_DMA_t__
+typedef struct _ADI_SPI_DMA_t {
+  union {
+    struct {
+      unsigned int EN         :  1;  /**< Enable DMA for Data Transfer */
+      unsigned int TXEN       :  1;  /**< Enable Transmit DMA Request */
+      unsigned int RXEN       :  1;  /**< Enable Receive DMA Request */
+      unsigned int reserved3  : 13;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_DMA_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_DMA_t__ */
+
+/*@}*/
+
+/** @defgroup FIFO_STAT FIFO Status (FIFO_STAT) Register
+ *  FIFO Status (FIFO_STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_FIFO_STAT_Struct
+ *! \brief  FIFO Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_FIFO_STAT_t__
+typedef struct _ADI_SPI_FIFO_STAT_t {
+  union {
+    struct {
+      unsigned int TX         :  4;  /**< SPI Tx FIFO Status */
+      unsigned int reserved4  :  4;
+      unsigned int RX         :  4;  /**< SPI Rx FIFO Dtatus */
+      unsigned int reserved12 :  4;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_FIFO_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_FIFO_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup RD_CTL Read Control (RD_CTL) Register
+ *  Read Control (RD_CTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_RD_CTL_Struct
+ *! \brief  Read Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_RD_CTL_t__
+typedef struct _ADI_SPI_RD_CTL_t {
+  union {
+    struct {
+      unsigned int CMDEN      :  1;  /**< Read Command Enable */
+      unsigned int OVERLAP    :  1;  /**< Tx/Rx Overlap Mode */
+      unsigned int TXBYTES    :  4;  /**< Transmit Byte Count - 1 (Read Command) */
+      unsigned int reserved6  :  2;
+      unsigned int THREEPIN   :  1;  /**< Three Pin SPI Mode */
+      unsigned int reserved9  :  7;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_RD_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_RD_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup FLOW_CTL Flow Control (FLOW_CTL) Register
+ *  Flow Control (FLOW_CTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_FLOW_CTL_Struct
+ *! \brief  Flow Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_FLOW_CTL_t__
+typedef struct _ADI_SPI_FLOW_CTL_t {
+  union {
+    struct {
+      unsigned int MODE       :  2;  /**< Flow Control Mode */
+      unsigned int reserved2  :  2;
+      unsigned int RDYPOL     :  1;  /**< Polarity of RDY/MISO Line */
+      unsigned int reserved5  :  3;
+      unsigned int RDBURSTSZ  :  4;  /**< Read Data Burst Size - 1 */
+      unsigned int reserved12 :  4;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_FLOW_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_FLOW_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup WAIT_TMR Wait Timer for Flow Control (WAIT_TMR) Register
+ *  Wait Timer for Flow Control (WAIT_TMR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_WAIT_TMR_Struct
+ *! \brief  Wait Timer for Flow Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_WAIT_TMR_t__
+typedef struct _ADI_SPI_WAIT_TMR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Wait Timer */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_WAIT_TMR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_WAIT_TMR_t__ */
+
+/*@}*/
+
+/** @defgroup CS_CTL Chip Select Control for Multi-slave Connections (CS_CTL) Register
+ *  Chip Select Control for Multi-slave Connections (CS_CTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_CS_CTL_Struct
+ *! \brief  Chip Select Control for Multi-slave Connections Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_CS_CTL_t__
+typedef struct _ADI_SPI_CS_CTL_t {
+  union {
+    struct {
+      unsigned int SEL        :  4;  /**< Chip Select Control */
+      unsigned int reserved4  : 12;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_CS_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_CS_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup CS_OVERRIDE Chip Select Override (CS_OVERRIDE) Register
+ *  Chip Select Override (CS_OVERRIDE) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_CS_OVERRIDE_Struct
+ *! \brief  Chip Select Override Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_CS_OVERRIDE_t__
+typedef struct _ADI_SPI_CS_OVERRIDE_t {
+  union {
+    struct {
+      unsigned int CTL        :  2;  /**< CS Override Control */
+      unsigned int reserved2  : 14;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_CS_OVERRIDE_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_CS_OVERRIDE_t__ */
+
+/*@}*/
+
+/** @defgroup RX Receive Buffer Register (RX) Register
+ *  Receive Buffer Register (RX) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_RX_Struct
+ *! \brief  Receive Buffer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_RX_t__
+typedef struct _ADI_UART_RX_t {
+  union {
+    struct {
+      unsigned int RBR        :  8;  /**< Receive Buffer Register */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_RX_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_RX_t__ */
+
+/*@}*/
+
+/** @defgroup TX Transmit Holding Register (TX) Register
+ *  Transmit Holding Register (TX) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_TX_Struct
+ *! \brief  Transmit Holding Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_TX_t__
+typedef struct _ADI_UART_TX_t {
+  union {
+    struct {
+      unsigned int THR        :  8;  /**< Transmit Holding Register */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_TX_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_TX_t__ */
+
+/*@}*/
+
+/** @defgroup IEN Interrupt Enable (IEN) Register
+ *  Interrupt Enable (IEN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_IEN_Struct
+ *! \brief  Interrupt Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_IEN_t__
+typedef struct _ADI_UART_IEN_t {
+  union {
+    struct {
+      unsigned int ERBFI      :  1;  /**< Receive Buffer Full Interrupt */
+      unsigned int ETBEI      :  1;  /**< Transmit Buffer Empty Interrupt */
+      unsigned int ELSI       :  1;  /**< Rx Status Interrupt */
+      unsigned int EDSSI      :  1;  /**< Modem Status Interrupt */
+      unsigned int EDMAT      :  1;  /**< DMA Requests in Transmit Mode */
+      unsigned int EDMAR      :  1;  /**< DMA Requests in Receive Mode */
+      unsigned int reserved6  : 10;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_IEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_IEN_t__ */
+
+/*@}*/
+
+/** @defgroup IIR Interrupt ID (IIR) Register
+ *  Interrupt ID (IIR) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_UART_IIR_STAT
+ *! \brief  Interrupt Status (STAT) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  UART_IIR_STAT_EDSSI = 0,  /**< Modem status interrupt (Read MSR register to clear)                                  */
+  UART_IIR_STAT_ETBEI = 1,  /**< Transmit buffer empty interrupt (Write to Tx register or read IIR register to clear) */
+  UART_IIR_STAT_ERBFI = 2,  /**< Receive buffer full interrupt (Read Rx register to clear)                            */
+  UART_IIR_STAT_RLSI  = 3,  /**< Receive line status interrupt (Read LSR register to clear)                           */
+  UART_IIR_STAT_RFTOI = 6   /**< Receive FIFO time-out interrupt (Read Rx register to clear)                          */
+} ADI_UART_IIR_STAT;
+
+
+/* ==========================================================================
+ *! \struct ADI_UART_IIR_Struct
+ *! \brief  Interrupt ID Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_IIR_t__
+typedef struct _ADI_UART_IIR_t {
+  union {
+    struct {
+      unsigned int NIRQ       :  1;  /**< Interrupt Flag */
+      unsigned int STAT       :  3;  /**< Interrupt Status */
+      unsigned int reserved4  :  2;
+      unsigned int FEND       :  2;  /**< FIFO Enabled */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_IIR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_IIR_t__ */
+
+/*@}*/
+
+/** @defgroup LCR Line Control (LCR) Register
+ *  Line Control (LCR) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_UART_LCR_SP
+ *! \brief  Stick Parity (SP) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  UART_LCR_PAR_NOTFORCED = 0,  /**< Parity will not be forced based on Parity Select and Parity Enable bits. */
+  UART_LCR_PAR_FORCED    = 1   /**< Parity forced based on Parity Select and Parity Enable bits.             */
+} ADI_UART_LCR_SP;
+
+
+/* ==========================================================================
+ *! \struct ADI_UART_LCR_Struct
+ *! \brief  Line Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_LCR_t__
+typedef struct _ADI_UART_LCR_t {
+  union {
+    struct {
+      unsigned int WLS        :  2;  /**< Word Length Select */
+      unsigned int STOP       :  1;  /**< Stop Bit */
+      unsigned int PEN        :  1;  /**< Parity Enable */
+      unsigned int EPS        :  1;  /**< Parity Select */
+      unsigned int SP         :  1;  /**< Stick Parity */
+      unsigned int BRK        :  1;  /**< Set Break */
+      unsigned int reserved7  :  9;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_LCR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_LCR_t__ */
+
+/*@}*/
+
+/** @defgroup MCR Modem Control (MCR) Register
+ *  Modem Control (MCR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_MCR_Struct
+ *! \brief  Modem Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_MCR_t__
+typedef struct _ADI_UART_MCR_t {
+  union {
+    struct {
+      unsigned int DTR        :  1;  /**< Data Terminal Ready */
+      unsigned int RTS        :  1;  /**< Request to Send */
+      unsigned int OUT1       :  1;  /**< Output 1 */
+      unsigned int OUT2       :  1;  /**< Output 2 */
+      unsigned int LOOPBACK   :  1;  /**< Loopback Mode */
+      unsigned int reserved5  : 11;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_MCR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_MCR_t__ */
+
+/*@}*/
+
+/** @defgroup LSR Line Status (LSR) Register
+ *  Line Status (LSR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_LSR_Struct
+ *! \brief  Line Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_LSR_t__
+typedef struct _ADI_UART_LSR_t {
+  union {
+    struct {
+      unsigned int DR         :  1;  /**< Data Ready */
+      unsigned int OE         :  1;  /**< Overrun Error */
+      unsigned int PE         :  1;  /**< Parity Error */
+      unsigned int FE         :  1;  /**< Framing Error */
+      unsigned int BI         :  1;  /**< Break Indicator */
+      unsigned int THRE       :  1;  /**< Transmit Register Empty */
+      unsigned int TEMT       :  1;  /**< Transmit and Shift Register Empty Status */
+      unsigned int FIFOERR    :  1;  /**< Rx FIFO Parity Error/Frame Error/Break Indication */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_LSR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_LSR_t__ */
+
+/*@}*/
+
+/** @defgroup MSR Modem Status (MSR) Register
+ *  Modem Status (MSR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_MSR_Struct
+ *! \brief  Modem Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_MSR_t__
+typedef struct _ADI_UART_MSR_t {
+  union {
+    struct {
+      unsigned int DCTS       :  1;  /**< Delta CTS */
+      unsigned int DDSR       :  1;  /**< Delta DSR */
+      unsigned int TERI       :  1;  /**< Trailing Edge RI */
+      unsigned int DDCD       :  1;  /**< Delta DCD */
+      unsigned int CTS        :  1;  /**< Clear to Send */
+      unsigned int DSR        :  1;  /**< Data Set Ready */
+      unsigned int RI         :  1;  /**< Ring Indicator */
+      unsigned int DCD        :  1;  /**< Data Carrier Detect */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_MSR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_MSR_t__ */
+
+/*@}*/
+
+/** @defgroup SCR Scratch Buffer (SCR) Register
+ *  Scratch Buffer (SCR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_SCR_Struct
+ *! \brief  Scratch Buffer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_SCR_t__
+typedef struct _ADI_UART_SCR_t {
+  union {
+    struct {
+      unsigned int SCR        :  8;  /**< Scratch */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_SCR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_SCR_t__ */
+
+/*@}*/
+
+/** @defgroup FCR FIFO Control (FCR) Register
+ *  FIFO Control (FCR) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_UART_FCR_FDMAMD
+ *! \brief  FIFO DMA Mode (FDMAMD) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  UART_FCR_MODE0 = 0,  /**< In DMA mode 0, RX DMA request will be asserted whenever there's data in RBR or RX FIFO and de-assert whenever RBR or RX FIFO is empty; TX DMA request will be asserted whenever THR or TX FIFO is empty and de-assert whenever data written to.                              */
+  UART_FCR_MODE1 = 1   /**< in DMA mode 1, RX DMA request will be asserted whenever RX FIFO trig level or time out reached and de-assert thereafter when RX FIFO is empty; TX DMA request will be asserted whenever TX FIFO is empty and de-assert thereafter when TX FIFO is completely filled up full. */
+} ADI_UART_FCR_FDMAMD;
+
+
+/* ==========================================================================
+ *! \struct ADI_UART_FCR_Struct
+ *! \brief  FIFO Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_FCR_t__
+typedef struct _ADI_UART_FCR_t {
+  union {
+    struct {
+      unsigned int FIFOEN     :  1;  /**< FIFO Enable as to Work in 16550 Mode */
+      unsigned int RFCLR      :  1;  /**< Clear Rx FIFO */
+      unsigned int TFCLR      :  1;  /**< Clear Tx FIFO */
+      unsigned int FDMAMD     :  1;  /**< FIFO DMA Mode */
+      unsigned int reserved4  :  2;
+      unsigned int RFTRIG     :  2;  /**< Rx FIFO Trigger Level */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_FCR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_FCR_t__ */
+
+/*@}*/
+
+/** @defgroup FBR Fractional Baud Rate (FBR) Register
+ *  Fractional Baud Rate (FBR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_FBR_Struct
+ *! \brief  Fractional Baud Rate Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_FBR_t__
+typedef struct _ADI_UART_FBR_t {
+  union {
+    struct {
+      unsigned int DIVN       : 11;  /**< Fractional Baud Rate N Divide Bits 0 to 2047 */
+      unsigned int DIVM       :  2;  /**< Fractional Baud Rate M Divide Bits 1 to 3 */
+      unsigned int reserved13 :  2;
+      unsigned int FBEN       :  1;  /**< Fractional Baud Rate Generator Enable */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_FBR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_FBR_t__ */
+
+/*@}*/
+
+/** @defgroup DIV Baud Rate Divider (DIV) Register
+ *  Baud Rate Divider (DIV) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_DIV_Struct
+ *! \brief  Baud Rate Divider Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_DIV_t__
+typedef struct _ADI_UART_DIV_t {
+  union {
+    struct {
+      unsigned int DIV        : 16;  /**< Baud Rate Divider */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_DIV_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_DIV_t__ */
+
+/*@}*/
+
+/** @defgroup LCR2 Second Line Control (LCR2) Register
+ *  Second Line Control (LCR2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_LCR2_Struct
+ *! \brief  Second Line Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_LCR2_t__
+typedef struct _ADI_UART_LCR2_t {
+  union {
+    struct {
+      unsigned int OSR        :  2;  /**< Over Sample Rate */
+      unsigned int reserved2  : 14;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_LCR2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_LCR2_t__ */
+
+/*@}*/
+
+/** @defgroup CTL UART Control Register (CTL) Register
+ *  UART Control Register (CTL) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_UART_CTL_RXINV
+ *! \brief  Invert Receiver Line (RXINV) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  UART_CTL_NOTINV_RX = 0,  /**< Don't invert receiver line (idling high). */
+  UART_CTL_INV_RX    = 1   /**< Invert receiver line (idling low).        */
+} ADI_UART_CTL_RXINV;
+
+
+/* ==========================================================================
+ *! \struct ADI_UART_CTL_Struct
+ *! \brief  UART Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_CTL_t__
+typedef struct _ADI_UART_CTL_t {
+  union {
+    struct {
+      unsigned int reserved0  :  1;
+      unsigned int FORCECLK   :  1;  /**< Force UCLK on */
+      unsigned int reserved2  :  2;
+      unsigned int RXINV      :  1;  /**< Invert Receiver Line */
+      unsigned int reserved5  :  3;
+      unsigned int REV        :  8;  /**< UART Revision ID */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup RFC RX FIFO Byte Count (RFC) Register
+ *  RX FIFO Byte Count (RFC) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_RFC_Struct
+ *! \brief  RX FIFO Byte Count Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_RFC_t__
+typedef struct _ADI_UART_RFC_t {
+  union {
+    struct {
+      unsigned int RFC        :  5;  /**< Current Rx FIFO Data Bytes */
+      unsigned int reserved5  : 11;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_RFC_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_RFC_t__ */
+
+/*@}*/
+
+/** @defgroup TFC TX FIFO Byte Count (TFC) Register
+ *  TX FIFO Byte Count (TFC) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_TFC_Struct
+ *! \brief  TX FIFO Byte Count Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_TFC_t__
+typedef struct _ADI_UART_TFC_t {
+  union {
+    struct {
+      unsigned int TFC        :  5;  /**< Current Tx FIFO Data Bytes */
+      unsigned int reserved5  : 11;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_TFC_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_TFC_t__ */
+
+/*@}*/
+
+/** @defgroup RSC RS485 Half-duplex Control (RSC) Register
+ *  RS485 Half-duplex Control (RSC) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_RSC_Struct
+ *! \brief  RS485 Half-duplex Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_RSC_t__
+typedef struct _ADI_UART_RSC_t {
+  union {
+    struct {
+      unsigned int OENP       :  1;  /**< SOUT_EN Polarity */
+      unsigned int OENSP      :  1;  /**< SOUT_EN De-assert Before Full Stop Bit(s) */
+      unsigned int DISRX      :  1;  /**< Disable Rx When Transmitting */
+      unsigned int DISTX      :  1;  /**< Hold off Tx When Receiving */
+      unsigned int reserved4  : 12;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_RSC_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_RSC_t__ */
+
+/*@}*/
+
+/** @defgroup ACR Auto Baud Control (ACR) Register
+ *  Auto Baud Control (ACR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_ACR_Struct
+ *! \brief  Auto Baud Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_ACR_t__
+typedef struct _ADI_UART_ACR_t {
+  union {
+    struct {
+      unsigned int ABE        :  1;  /**< Auto Baud Enable */
+      unsigned int DNIEN      :  1;  /**< Enable Done Interrupt */
+      unsigned int TOIEN      :  1;  /**< Enable Time-out Interrupt */
+      unsigned int reserved3  :  1;
+      unsigned int SEC        :  3;  /**< Starting Edge Count */
+      unsigned int reserved7  :  1;
+      unsigned int EEC        :  4;  /**< Ending Edge Count */
+      unsigned int reserved12 :  4;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_ACR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_ACR_t__ */
+
+/*@}*/
+
+/** @defgroup ASRL Auto Baud Status (Low) (ASRL) Register
+ *  Auto Baud Status (Low) (ASRL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_ASRL_Struct
+ *! \brief  Auto Baud Status (Low) Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_ASRL_t__
+typedef struct _ADI_UART_ASRL_t {
+  union {
+    struct {
+      unsigned int DONE       :  1;  /**< Auto Baud Done Successfully */
+      unsigned int BRKTO      :  1;  /**< Timed Out Due to Long Time Break Condition */
+      unsigned int NSETO      :  1;  /**< Timed Out Due to No Valid Start Edge Found */
+      unsigned int NEETO      :  1;  /**< Timed Out Due to No Valid Ending Edge Found */
+      unsigned int CNT        : 12;  /**< CNT[11:0] Auto Baud Counter Value */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_ASRL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_ASRL_t__ */
+
+/*@}*/
+
+/** @defgroup ASRH Auto Baud Status (High) (ASRH) Register
+ *  Auto Baud Status (High) (ASRH) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_ASRH_Struct
+ *! \brief  Auto Baud Status (High) Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_ASRH_t__
+typedef struct _ADI_UART_ASRH_t {
+  union {
+    struct {
+      unsigned int CNT        :  8;  /**< CNT[19:12] Auto Baud Counter Value */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_ASRH_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_ASRH_t__ */
+
+/*@}*/
+
+/** @defgroup CFG Beeper Configuration (CFG) Register
+ *  Beeper Configuration (CFG) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_BEEP_CFG_Struct
+ *! \brief  Beeper Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_CFG_t__
+typedef struct _ADI_BEEP_CFG_t {
+  union {
+    struct {
+      unsigned int SEQREPEAT  :  8;  /**< Beeper Sequence Repeat Value */
+      unsigned int EN         :  1;  /**< Beeper Enable */
+      unsigned int reserved9  :  1;
+      unsigned int ASTARTIRQ  :  1;  /**< Tone A Start IRQ */
+      unsigned int AENDIRQ    :  1;  /**< Tone A End IRQ */
+      unsigned int BSTARTIRQ  :  1;  /**< Tone B Start IRQ */
+      unsigned int BENDIRQ    :  1;  /**< Tone B End IRQ */
+      unsigned int SEQNEARENDIRQ :  1;  /**< Sequence 1 Cycle from End IRQ */
+      unsigned int SEQATENDIRQ   :  1;  /**< Sequence End IRQ */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_BEEP_CFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_CFG_t__ */
+
+/*@}*/
+
+/** @defgroup STAT Beeper Status (STAT) Register
+ *  Beeper Status (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_BEEP_STAT_Struct
+ *! \brief  Beeper Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_STAT_t__
+typedef struct _ADI_BEEP_STAT_t {
+  union {
+    struct {
+      unsigned int SEQREMAIN  :  8;  /**< Remaining Tone-pair Iterations to Play in Sequence Mode */
+      unsigned int BUSY       :  1;  /**< Beeper is Busy */
+      unsigned int reserved9  :  1;
+      unsigned int ASTARTED   :  1;  /**< Tone A Has Started */
+      unsigned int AENDED     :  1;  /**< Tone A Has Ended */
+      unsigned int BSTARTED   :  1;  /**< Tone B Has Started */
+      unsigned int BENDED     :  1;  /**< Tone B Has Ended */
+      unsigned int SEQNEAREND :  1;  /**< Sequencer Last Tone-pair Has Started */
+      unsigned int SEQENDED   :  1;  /**< Sequencer Has Ended */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_BEEP_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup TONEA Tone A Data (TONEA) Register
+ *  Tone A Data (TONEA) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_BEEP_TONEA_Struct
+ *! \brief  Tone A Data Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_TONEA_t__
+typedef struct _ADI_BEEP_TONEA_t {
+  union {
+    struct {
+      unsigned int DUR        :  8;  /**< Tone Duration */
+      unsigned int FREQ       :  7;  /**< Tone Frequency */
+      unsigned int DIS        :  1;  /**< Output Disable */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_BEEP_TONEA_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_TONEA_t__ */
+
+/*@}*/
+
+/** @defgroup TONEB Tone B Data (TONEB) Register
+ *  Tone B Data (TONEB) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_BEEP_TONEB_Struct
+ *! \brief  Tone B Data Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_TONEB_t__
+typedef struct _ADI_BEEP_TONEB_t {
+  union {
+    struct {
+      unsigned int DUR        :  8;  /**< Tone Duration */
+      unsigned int FREQ       :  7;  /**< Tone Frequency */
+      unsigned int DIS        :  1;  /**< Output Disable */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_BEEP_TONEB_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_TONEB_t__ */
+
+/*@}*/
+
+/** @defgroup CFG ADC Configuration (CFG) Register
+ *  ADC Configuration (CFG) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_ADC_CFG_VREFSEL
+ *! \brief  Select Vref as 1.25V or 2.5V (VREFSEL) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  ADC_CFG_V_2P5  = 0,  /**< Vref = 2.5V  */
+  ADC_CFG_V_1P25 = 1   /**< Vref = 1.25V */
+} ADI_ADC_CFG_VREFSEL;
+
+
+/*  =========================================================================
+ *! \enum   ADI_ADC_CFG_REFBUFEN
+ *! \brief  Enable Internal Reference Buffer (REFBUFEN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  ADC_CFG_EXT_REF = 0,  /**< External reference is used  */
+  ADC_CFG_BUF_REF = 1   /**< Reference buffer is enabled */
+} ADI_ADC_CFG_REFBUFEN;
+
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CFG_Struct
+ *! \brief  ADC Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CFG_t__
+typedef struct _ADI_ADC_CFG_t {
+  union {
+    struct {
+      unsigned int PWRUP      :  1;  /**< Powering up the ADC */
+      unsigned int VREFSEL    :  1;  /**< Select Vref as 1.25V or 2.5V */
+      unsigned int REFBUFEN   :  1;  /**< Enable Internal Reference Buffer */
+      unsigned int reserved3  :  1;
+      unsigned int EN         :  1;  /**< Enable ADC Subsystem */
+      unsigned int STARTCAL   :  1;  /**< Start a New Offset Calibration Cycle */
+      unsigned int RST        :  1;  /**< Reset */
+      unsigned int SINKEN     :  1;  /**< Enable Additional Sink Current Capability */
+      unsigned int TMPEN      :  1;  /**< Power up Temperature Sensor */
+      unsigned int FAST_DISCH :  1;  /**< Fast Switchover of Vref from 2.5 to 1.25 */
+      unsigned int reserved10 :  6;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CFG_t__ */
+
+/*@}*/
+
+/** @defgroup PWRUP ADC Power-up Time (PWRUP) Register
+ *  ADC Power-up Time (PWRUP) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_PWRUP_Struct
+ *! \brief  ADC Power-up Time Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_PWRUP_t__
+typedef struct _ADI_ADC_PWRUP_t {
+  union {
+    struct {
+      unsigned int WAIT       : 10;  /**< Program This with 526/PCLKDIVCNT */
+      unsigned int reserved10 :  6;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_PWRUP_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_PWRUP_t__ */
+
+/*@}*/
+
+/** @defgroup CAL_WORD Calibration Word (CAL_WORD) Register
+ *  Calibration Word (CAL_WORD) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CAL_WORD_Struct
+ *! \brief  Calibration Word Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CAL_WORD_t__
+typedef struct _ADI_ADC_CAL_WORD_t {
+  union {
+    struct {
+      unsigned int VALUE      :  7;  /**< Offset Calibration Word */
+      unsigned int reserved7  :  9;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CAL_WORD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CAL_WORD_t__ */
+
+/*@}*/
+
+/** @defgroup CNV_CFG ADC Conversion Configuration (CNV_CFG) Register
+ *  ADC Conversion Configuration (CNV_CFG) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CNV_CFG_Struct
+ *! \brief  ADC Conversion Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CNV_CFG_t__
+typedef struct _ADI_ADC_CNV_CFG_t {
+  union {
+    struct {
+      unsigned int SEL        :  8;  /**< Selection of Channel(s) to Convert */
+      unsigned int BAT        :  1;  /**< Battery Monitoring Enable */
+      unsigned int TMP        :  1;  /**< Temperature Measurement 1 */
+      unsigned int TMP2       :  1;  /**< Temperature Measurement 2 */
+      unsigned int reserved11 :  1;
+      unsigned int AUTOMODE   :  1;  /**< Auto Mode Enable */
+      unsigned int DMAEN      :  1;  /**< DMA Channel Enable */
+      unsigned int SINGLE     :  1;  /**< Single Conversion Start */
+      unsigned int MULTI      :  1;  /**< Multiple Conversions */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CNV_CFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CNV_CFG_t__ */
+
+/*@}*/
+
+/** @defgroup CNV_TIME ADC Conversion Time (CNV_TIME) Register
+ *  ADC Conversion Time (CNV_TIME) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CNV_TIME_Struct
+ *! \brief  ADC Conversion Time Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CNV_TIME_t__
+typedef struct _ADI_ADC_CNV_TIME_t {
+  union {
+    struct {
+      unsigned int SAMPTIME   :  8;  /**< Sampling Time */
+      unsigned int DLY        :  8;  /**< Delay Between Two Consecutive Conversions */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CNV_TIME_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CNV_TIME_t__ */
+
+/*@}*/
+
+/** @defgroup AVG_CFG Averaging Configuration (AVG_CFG) Register
+ *  Averaging Configuration (AVG_CFG) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_AVG_CFG_Struct
+ *! \brief  Averaging Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_AVG_CFG_t__
+typedef struct _ADI_ADC_AVG_CFG_t {
+  union {
+    struct {
+      unsigned int FACTOR     :  8;  /**< Averaging Factor */
+      unsigned int reserved8  :  6;
+      unsigned int OS         :  1;  /**< Enable Oversampling */
+      unsigned int EN         :  1;  /**< Enable Averaging on Channels Enabled in Enable Register */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_AVG_CFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_AVG_CFG_t__ */
+
+/*@}*/
+
+/** @defgroup IRQ_EN Interrupt Enable (IRQ_EN) Register
+ *  Interrupt Enable (IRQ_EN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_IRQ_EN_Struct
+ *! \brief  Interrupt Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_IRQ_EN_t__
+typedef struct _ADI_ADC_IRQ_EN_t {
+  union {
+    struct {
+      unsigned int CNVDONE    :  1;  /**< Enable Conversion Done Interrupt */
+      unsigned int reserved1  :  9;
+      unsigned int CALDONE    :  1;  /**< Enable Interrupt for Calibration Done */
+      unsigned int OVF        :  1;  /**< Enable Overflow Interrupt */
+      unsigned int ALERT      :  1;  /**< Interrupt on Crossing Lower or Higher Limit Enable */
+      unsigned int RDY        :  1;  /**< Set to Enable Interrupt When ADC is Ready to Convert */
+      unsigned int reserved14 :  2;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_IRQ_EN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_IRQ_EN_t__ */
+
+/*@}*/
+
+/** @defgroup STAT ADC Status (STAT) Register
+ *  ADC Status (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_STAT_Struct
+ *! \brief  ADC Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_STAT_t__
+typedef struct _ADI_ADC_STAT_t {
+  union {
+    struct {
+      unsigned int DONE0      :  1;  /**< Conversion Done on Channel 0 */
+      unsigned int DONE1      :  1;  /**< Conversion Done on Channel 1 */
+      unsigned int DONE2      :  1;  /**< Conversion Done on Channel 2 */
+      unsigned int DONE3      :  1;  /**< Conversion Done on Channel 3 */
+      unsigned int DONE4      :  1;  /**< Conversion Done on Channel 4 */
+      unsigned int DONE5      :  1;  /**< Conversion Done on Channel 5 */
+      unsigned int DONE6      :  1;  /**< Conversion Done on Channel 6 */
+      unsigned int DONE7      :  1;  /**< Conversion Done on Channel 7 */
+      unsigned int BATDONE    :  1;  /**< Conversion Done - Battery Monitoring */
+      unsigned int TMPDONE    :  1;  /**< Conversion Done for Temperature Sensing */
+      unsigned int TMP2DONE   :  1;  /**< Conversion Done for Temperature Sensing 2 */
+      unsigned int reserved11 :  3;
+      unsigned int CALDONE    :  1;  /**< Calibration Done */
+      unsigned int RDY        :  1;  /**< ADC Ready to Start Converting */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup OVF Overflow of Output Registers (OVF) Register
+ *  Overflow of Output Registers (OVF) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_OVF_Struct
+ *! \brief  Overflow of Output Registers Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_OVF_t__
+typedef struct _ADI_ADC_OVF_t {
+  union {
+    struct {
+      unsigned int CH0        :  1;  /**< Overflow in CH0_OUT */
+      unsigned int CH1        :  1;  /**< Overflow in CH1_OUT */
+      unsigned int CH2        :  1;  /**< Overflow in CH2_OUT */
+      unsigned int CH3        :  1;  /**< Overflow in CH3_OUT */
+      unsigned int CH4        :  1;  /**< Overflow in CH4_OUT */
+      unsigned int CH5        :  1;  /**< Overflow in CH5_OUT */
+      unsigned int CH6        :  1;  /**< Overflow in CH6_OUT */
+      unsigned int CH7        :  1;  /**< Overflow in CH7_OUT */
+      unsigned int BAT        :  1;  /**< Overflow in BAT_OUT */
+      unsigned int TMP        :  1;  /**< Overflow in TMP_OUT */
+      unsigned int TMP2       :  1;  /**< Overflow in TMP2_OUT */
+      unsigned int reserved11 :  5;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_OVF_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_OVF_t__ */
+
+/*@}*/
+
+/** @defgroup ALERT Alert Indication (ALERT) Register
+ *  Alert Indication (ALERT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_ALERT_Struct
+ *! \brief  Alert Indication Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_ALERT_t__
+typedef struct _ADI_ADC_ALERT_t {
+  union {
+    struct {
+      unsigned int HI0        :  1;  /**< Channel 0 High Alert Status */
+      unsigned int LO0        :  1;  /**< Channel 0 Low Alert Status */
+      unsigned int HI1        :  1;  /**< Channel 1 High Alert Status */
+      unsigned int LO1        :  1;  /**< Channel 1 Low Alert Status */
+      unsigned int HI2        :  1;  /**< Channel 2 High Alert Status */
+      unsigned int LO2        :  1;  /**< Channel 2 Low Alert Status */
+      unsigned int HI3        :  1;  /**< Channel 3 High Alert Status */
+      unsigned int LO3        :  1;  /**< Channel 3 Low Alert Status */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_ALERT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_ALERT_t__ */
+
+/*@}*/
+
+/** @defgroup CH0_OUT Conversion Result Channel 0 (CH0_OUT) Register
+ *  Conversion Result Channel 0 (CH0_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CH0_OUT_Struct
+ *! \brief  Conversion Result Channel 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH0_OUT_t__
+typedef struct _ADI_ADC_CH0_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion Result of Channel 0 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CH0_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH0_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup CH1_OUT Conversion Result Channel 1 (CH1_OUT) Register
+ *  Conversion Result Channel 1 (CH1_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CH1_OUT_Struct
+ *! \brief  Conversion Result Channel 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH1_OUT_t__
+typedef struct _ADI_ADC_CH1_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion Result of Channel 1 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CH1_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH1_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup CH2_OUT Conversion Result Channel 2 (CH2_OUT) Register
+ *  Conversion Result Channel 2 (CH2_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CH2_OUT_Struct
+ *! \brief  Conversion Result Channel 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH2_OUT_t__
+typedef struct _ADI_ADC_CH2_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion Result of Channel 2 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CH2_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH2_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup CH3_OUT Conversion Result Channel 3 (CH3_OUT) Register
+ *  Conversion Result Channel 3 (CH3_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CH3_OUT_Struct
+ *! \brief  Conversion Result Channel 3 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH3_OUT_t__
+typedef struct _ADI_ADC_CH3_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion Result of Channel 3 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CH3_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH3_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup CH4_OUT Conversion Result Channel 4 (CH4_OUT) Register
+ *  Conversion Result Channel 4 (CH4_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CH4_OUT_Struct
+ *! \brief  Conversion Result Channel 4 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH4_OUT_t__
+typedef struct _ADI_ADC_CH4_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion Result of Channel 4 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CH4_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH4_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup CH5_OUT Conversion Result Channel 5 (CH5_OUT) Register
+ *  Conversion Result Channel 5 (CH5_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CH5_OUT_Struct
+ *! \brief  Conversion Result Channel 5 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH5_OUT_t__
+typedef struct _ADI_ADC_CH5_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion Result of Channel 5 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CH5_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH5_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup CH6_OUT Conversion Result Channel 6 (CH6_OUT) Register
+ *  Conversion Result Channel 6 (CH6_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CH6_OUT_Struct
+ *! \brief  Conversion Result Channel 6 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH6_OUT_t__
+typedef struct _ADI_ADC_CH6_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion Result of Channel 6 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CH6_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH6_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup CH7_OUT Conversion Result Channel 7 (CH7_OUT) Register
+ *  Conversion Result Channel 7 (CH7_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CH7_OUT_Struct
+ *! \brief  Conversion Result Channel 7 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH7_OUT_t__
+typedef struct _ADI_ADC_CH7_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion Result of Channel 7 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CH7_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH7_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup BAT_OUT Battery Monitoring Result (BAT_OUT) Register
+ *  Battery Monitoring Result (BAT_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_BAT_OUT_Struct
+ *! \brief  Battery Monitoring Result Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_BAT_OUT_t__
+typedef struct _ADI_ADC_BAT_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion Result of Battery Monitoring */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_BAT_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_BAT_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup TMP_OUT Temperature Result (TMP_OUT) Register
+ *  Temperature Result (TMP_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_TMP_OUT_Struct
+ *! \brief  Temperature Result Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_TMP_OUT_t__
+typedef struct _ADI_ADC_TMP_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion Result of Temperature Measurement 1 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_TMP_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_TMP_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup TMP2_OUT Temperature Result 2 (TMP2_OUT) Register
+ *  Temperature Result 2 (TMP2_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_TMP2_OUT_Struct
+ *! \brief  Temperature Result 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_TMP2_OUT_t__
+typedef struct _ADI_ADC_TMP2_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion Result of Temperature Measurement 2 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_TMP2_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_TMP2_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup DMA_OUT DMA Output Register (DMA_OUT) Register
+ *  DMA Output Register (DMA_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_DMA_OUT_Struct
+ *! \brief  DMA Output Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_DMA_OUT_t__
+typedef struct _ADI_ADC_DMA_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion Result for DMA */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_DMA_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_DMA_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup LIM0_LO Channel 0 Low Limit (LIM0_LO) Register
+ *  Channel 0 Low Limit (LIM0_LO) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_LIM0_LO_Struct
+ *! \brief  Channel 0 Low Limit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM0_LO_t__
+typedef struct _ADI_ADC_LIM0_LO_t {
+  union {
+    struct {
+      unsigned int VALUE      : 12;  /**< Low Limit for Channel 0 */
+      unsigned int reserved12 :  3;
+      unsigned int EN         :  1;  /**< Enable Low Limit Comparison on Channel 0 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_LIM0_LO_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM0_LO_t__ */
+
+/*@}*/
+
+/** @defgroup LIM0_HI Channel 0 High Limit (LIM0_HI) Register
+ *  Channel 0 High Limit (LIM0_HI) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_LIM0_HI_Struct
+ *! \brief  Channel 0 High Limit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM0_HI_t__
+typedef struct _ADI_ADC_LIM0_HI_t {
+  union {
+    struct {
+      unsigned int VALUE      : 12;  /**< High Limit for Channel 0 */
+      unsigned int reserved12 :  3;
+      unsigned int EN         :  1;  /**< Enable High Limit Comparison on Channel 0 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_LIM0_HI_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM0_HI_t__ */
+
+/*@}*/
+
+/** @defgroup HYS0 Channel 0 Hysteresis (HYS0) Register
+ *  Channel 0 Hysteresis (HYS0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_HYS0_Struct
+ *! \brief  Channel 0 Hysteresis Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_HYS0_t__
+typedef struct _ADI_ADC_HYS0_t {
+  union {
+    struct {
+      unsigned int VALUE      :  9;  /**< Hysteresis Value for Channel 0 */
+      unsigned int reserved9  :  3;
+      unsigned int MONCYC     :  3;  /**< Number of Conversion Cycles to Monitor Channel 0 */
+      unsigned int EN         :  1;  /**< Enable Hysteresis for Comparison on Channel 0 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_HYS0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_HYS0_t__ */
+
+/*@}*/
+
+/** @defgroup LIM1_LO Channel 1 Low Limit (LIM1_LO) Register
+ *  Channel 1 Low Limit (LIM1_LO) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_LIM1_LO_Struct
+ *! \brief  Channel 1 Low Limit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM1_LO_t__
+typedef struct _ADI_ADC_LIM1_LO_t {
+  union {
+    struct {
+      unsigned int VALUE      : 12;  /**< Low Limit for Channel 1 */
+      unsigned int reserved12 :  3;
+      unsigned int EN         :  1;  /**< Enable Low Limit Comparison on Channel 1 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_LIM1_LO_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM1_LO_t__ */
+
+/*@}*/
+
+/** @defgroup LIM1_HI Channel 1 High Limit (LIM1_HI) Register
+ *  Channel 1 High Limit (LIM1_HI) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_LIM1_HI_Struct
+ *! \brief  Channel 1 High Limit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM1_HI_t__
+typedef struct _ADI_ADC_LIM1_HI_t {
+  union {
+    struct {
+      unsigned int VALUE      : 12;  /**< High Limit for Channel 1 */
+      unsigned int reserved12 :  3;
+      unsigned int EN         :  1;  /**< Enable High Limit Comparison on Channel 1 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_LIM1_HI_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM1_HI_t__ */
+
+/*@}*/
+
+/** @defgroup HYS1 Channel 1 Hysteresis (HYS1) Register
+ *  Channel 1 Hysteresis (HYS1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_HYS1_Struct
+ *! \brief  Channel 1 Hysteresis Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_HYS1_t__
+typedef struct _ADI_ADC_HYS1_t {
+  union {
+    struct {
+      unsigned int VALUE      :  9;  /**< Hysteresis Value for Channel 1 */
+      unsigned int reserved9  :  3;
+      unsigned int MONCYC     :  3;  /**< Number of Conversion Cycles to Monitor Channel 1 */
+      unsigned int EN         :  1;  /**< Enable Hysteresis for Comparison on Channel 1 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_HYS1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_HYS1_t__ */
+
+/*@}*/
+
+/** @defgroup LIM2_LO Channel 2 Low Limit (LIM2_LO) Register
+ *  Channel 2 Low Limit (LIM2_LO) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_LIM2_LO_Struct
+ *! \brief  Channel 2 Low Limit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM2_LO_t__
+typedef struct _ADI_ADC_LIM2_LO_t {
+  union {
+    struct {
+      unsigned int VALUE      : 12;  /**< Low Limit for Channel 2 */
+      unsigned int reserved12 :  3;
+      unsigned int EN         :  1;  /**< Enable Low Limit Comparison on Channel 2 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_LIM2_LO_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM2_LO_t__ */
+
+/*@}*/
+
+/** @defgroup LIM2_HI Channel 2 High Limit (LIM2_HI) Register
+ *  Channel 2 High Limit (LIM2_HI) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_LIM2_HI_Struct
+ *! \brief  Channel 2 High Limit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM2_HI_t__
+typedef struct _ADI_ADC_LIM2_HI_t {
+  union {
+    struct {
+      unsigned int VALUE      : 12;  /**< High Limit for Channel 2 */
+      unsigned int reserved12 :  3;
+      unsigned int EN         :  1;  /**< Enable High Limit Comparison on Channel */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_LIM2_HI_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM2_HI_t__ */
+
+/*@}*/
+
+/** @defgroup HYS2 Channel 2 Hysteresis (HYS2) Register
+ *  Channel 2 Hysteresis (HYS2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_HYS2_Struct
+ *! \brief  Channel 2 Hysteresis Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_HYS2_t__
+typedef struct _ADI_ADC_HYS2_t {
+  union {
+    struct {
+      unsigned int VALUE      :  9;  /**< Hysteresis Value for Channel 2 */
+      unsigned int reserved9  :  3;
+      unsigned int MONCYC     :  3;  /**< Number of Conversion Cycles to Monitor Channel 2 */
+      unsigned int EN         :  1;  /**< Enable Hysteresis for Comparison on Channel 2 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_HYS2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_HYS2_t__ */
+
+/*@}*/
+
+/** @defgroup LIM3_LO Channel 3 Low Limit (LIM3_LO) Register
+ *  Channel 3 Low Limit (LIM3_LO) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_LIM3_LO_Struct
+ *! \brief  Channel 3 Low Limit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM3_LO_t__
+typedef struct _ADI_ADC_LIM3_LO_t {
+  union {
+    struct {
+      unsigned int VALUE      : 12;  /**< Low Limit for Channel 3 */
+      unsigned int reserved12 :  3;
+      unsigned int EN         :  1;  /**< Enable Low Limit Comparison on Channel 3 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_LIM3_LO_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM3_LO_t__ */
+
+/*@}*/
+
+/** @defgroup LIM3_HI Channel 3 High Limit (LIM3_HI) Register
+ *  Channel 3 High Limit (LIM3_HI) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_LIM3_HI_Struct
+ *! \brief  Channel 3 High Limit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM3_HI_t__
+typedef struct _ADI_ADC_LIM3_HI_t {
+  union {
+    struct {
+      unsigned int VALUE      : 12;  /**< High Limit for Channel 3 */
+      unsigned int reserved12 :  3;
+      unsigned int EN         :  1;  /**< Enable High Limit Comparison on Channel 3 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_LIM3_HI_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM3_HI_t__ */
+
+/*@}*/
+
+/** @defgroup HYS3 Channel 3 Hysteresis (HYS3) Register
+ *  Channel 3 Hysteresis (HYS3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_HYS3_Struct
+ *! \brief  Channel 3 Hysteresis Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_HYS3_t__
+typedef struct _ADI_ADC_HYS3_t {
+  union {
+    struct {
+      unsigned int VALUE      :  9;  /**< Hysteresis Value for Channel 3 */
+      unsigned int reserved9  :  3;
+      unsigned int MONCYC     :  3;  /**< Number of Conversion Cycles to Monitor Channel 3 */
+      unsigned int EN         :  1;  /**< Enable Hysteresis for Comparison on Channel 3 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_HYS3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_HYS3_t__ */
+
+/*@}*/
+
+/** @defgroup CFG1 Reference Buffer Low Power Mode (CFG1) Register
+ *  Reference Buffer Low Power Mode (CFG1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CFG1_Struct
+ *! \brief  Reference Buffer Low Power Mode Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CFG1_t__
+typedef struct _ADI_ADC_CFG1_t {
+  union {
+    struct {
+      unsigned int RBUFLP     :  1;  /**< Enable Low Power Mode for Reference Buffer */
+      unsigned int reserved1  : 15;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CFG1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CFG1_t__ */
+
+/*@}*/
+
+/** @defgroup STAT DMA Status (STAT) Register
+ *  DMA Status (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_STAT_Struct
+ *! \brief  DMA Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_STAT_t__
+typedef struct _ADI_DMA_STAT_t {
+  union {
+    struct {
+      unsigned int MEN        :  1;  /**< Enable Status of the Controller */
+      unsigned int reserved1  : 15;
+      unsigned int CHANM1     :  5;  /**< Number of Available DMA Channels Minus 1 */
+      unsigned int reserved21 : 11;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup CFG DMA Configuration (CFG) Register
+ *  DMA Configuration (CFG) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_CFG_Struct
+ *! \brief  DMA Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_CFG_t__
+typedef struct _ADI_DMA_CFG_t {
+  union {
+    struct {
+      unsigned int MEN        :  1;  /**< Controller Enable */
+      unsigned int reserved1  : 31;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_CFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_CFG_t__ */
+
+/*@}*/
+
+/** @defgroup PDBPTR DMA Channel Primary Control Database Pointer (PDBPTR) Register
+ *  DMA Channel Primary Control Database Pointer (PDBPTR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_PDBPTR_Struct
+ *! \brief  DMA Channel Primary Control Database Pointer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_PDBPTR_t__
+typedef struct _ADI_DMA_PDBPTR_t {
+  union {
+    struct {
+      unsigned int ADDR       : 32;  /**< Pointer to the Base Address of the Primary Data Structure */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_PDBPTR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_PDBPTR_t__ */
+
+/*@}*/
+
+/** @defgroup ADBPTR DMA Channel Alternate Control Database Pointer (ADBPTR) Register
+ *  DMA Channel Alternate Control Database Pointer (ADBPTR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_ADBPTR_Struct
+ *! \brief  DMA Channel Alternate Control Database Pointer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ADBPTR_t__
+typedef struct _ADI_DMA_ADBPTR_t {
+  union {
+    struct {
+      unsigned int ADDR       : 32;  /**< Base Address of the Alternate Data Structure */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_ADBPTR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ADBPTR_t__ */
+
+/*@}*/
+
+/** @defgroup SWREQ DMA Channel Software Request (SWREQ) Register
+ *  DMA Channel Software Request (SWREQ) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_SWREQ_Struct
+ *! \brief  DMA Channel Software Request Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_SWREQ_t__
+typedef struct _ADI_DMA_SWREQ_t {
+  union {
+    struct {
+      unsigned int CHAN       : 25;  /**< Generate Software Request */
+      unsigned int reserved25 :  7;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_SWREQ_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_SWREQ_t__ */
+
+/*@}*/
+
+/** @defgroup RMSK_SET DMA Channel Request Mask Set (RMSK_SET) Register
+ *  DMA Channel Request Mask Set (RMSK_SET) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_RMSK_SET_Struct
+ *! \brief  DMA Channel Request Mask Set Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_RMSK_SET_t__
+typedef struct _ADI_DMA_RMSK_SET_t {
+  union {
+    struct {
+      unsigned int CHAN       : 25;  /**< Mask Requests from DMA Channels */
+      unsigned int reserved25 :  7;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_RMSK_SET_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_RMSK_SET_t__ */
+
+/*@}*/
+
+/** @defgroup RMSK_CLR DMA Channel Request Mask Clear (RMSK_CLR) Register
+ *  DMA Channel Request Mask Clear (RMSK_CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_RMSK_CLR_Struct
+ *! \brief  DMA Channel Request Mask Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_RMSK_CLR_t__
+typedef struct _ADI_DMA_RMSK_CLR_t {
+  union {
+    struct {
+      unsigned int CHAN       : 25;  /**< Clear Request Mask Set Bits */
+      unsigned int reserved25 :  7;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_RMSK_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_RMSK_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup EN_SET DMA Channel Enable Set (EN_SET) Register
+ *  DMA Channel Enable Set (EN_SET) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_EN_SET_Struct
+ *! \brief  DMA Channel Enable Set Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_EN_SET_t__
+typedef struct _ADI_DMA_EN_SET_t {
+  union {
+    struct {
+      unsigned int CHAN       : 25;  /**< Enable DMA Channels */
+      unsigned int reserved25 :  7;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_EN_SET_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_EN_SET_t__ */
+
+/*@}*/
+
+/** @defgroup EN_CLR DMA Channel Enable Clear (EN_CLR) Register
+ *  DMA Channel Enable Clear (EN_CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_EN_CLR_Struct
+ *! \brief  DMA Channel Enable Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_EN_CLR_t__
+typedef struct _ADI_DMA_EN_CLR_t {
+  union {
+    struct {
+      unsigned int CHAN       : 25;  /**< Disable DMA Channels */
+      unsigned int reserved25 :  7;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_EN_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_EN_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup ALT_SET DMA Channel Primary Alternate Set (ALT_SET) Register
+ *  DMA Channel Primary Alternate Set (ALT_SET) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_ALT_SET_Struct
+ *! \brief  DMA Channel Primary Alternate Set Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ALT_SET_t__
+typedef struct _ADI_DMA_ALT_SET_t {
+  union {
+    struct {
+      unsigned int CHAN       : 25;  /**< Control Structure Status / Select Alternate Structure */
+      unsigned int reserved25 :  7;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_ALT_SET_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ALT_SET_t__ */
+
+/*@}*/
+
+/** @defgroup ALT_CLR DMA Channel Primary Alternate Clear (ALT_CLR) Register
+ *  DMA Channel Primary Alternate Clear (ALT_CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_ALT_CLR_Struct
+ *! \brief  DMA Channel Primary Alternate Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ALT_CLR_t__
+typedef struct _ADI_DMA_ALT_CLR_t {
+  union {
+    struct {
+      unsigned int CHAN       : 25;  /**< Select Primary Data Structure */
+      unsigned int reserved25 :  7;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_ALT_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ALT_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup PRI_SET DMA Channel Priority Set (PRI_SET) Register
+ *  DMA Channel Priority Set (PRI_SET) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_PRI_SET_Struct
+ *! \brief  DMA Channel Priority Set Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_PRI_SET_t__
+typedef struct _ADI_DMA_PRI_SET_t {
+  union {
+    struct {
+      unsigned int CHAN       : 25;  /**< Configure Channel for High Priority */
+      unsigned int reserved25 :  7;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_PRI_SET_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_PRI_SET_t__ */
+
+/*@}*/
+
+/** @defgroup PRI_CLR DMA Channel Priority Clear (PRI_CLR) Register
+ *  DMA Channel Priority Clear (PRI_CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_PRI_CLR_Struct
+ *! \brief  DMA Channel Priority Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_PRI_CLR_t__
+typedef struct _ADI_DMA_PRI_CLR_t {
+  union {
+    struct {
+      unsigned int CHPRICLR   : 25;  /**< Configure Channel for Default Priority Level */
+      unsigned int reserved25 :  7;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_PRI_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_PRI_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup ERRCHNL_CLR DMA per Channel Error Clear (ERRCHNL_CLR) Register
+ *  DMA per Channel Error Clear (ERRCHNL_CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_ERRCHNL_CLR_Struct
+ *! \brief  DMA per Channel Error Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ERRCHNL_CLR_t__
+typedef struct _ADI_DMA_ERRCHNL_CLR_t {
+  union {
+    struct {
+      unsigned int CHAN       : 25;  /**< Per Channel Bus Error Status/Clear */
+      unsigned int reserved25 :  7;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_ERRCHNL_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ERRCHNL_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup ERR_CLR DMA Bus Error Clear (ERR_CLR) Register
+ *  DMA Bus Error Clear (ERR_CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_ERR_CLR_Struct
+ *! \brief  DMA Bus Error Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ERR_CLR_t__
+typedef struct _ADI_DMA_ERR_CLR_t {
+  union {
+    struct {
+      unsigned int CHAN       : 25;  /**< Bus Error Status */
+      unsigned int reserved25 :  7;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_ERR_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ERR_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup INVALIDDESC_CLR DMA per Channel Invalid Descriptor Clear (INVALIDDESC_CLR) Register
+ *  DMA per Channel Invalid Descriptor Clear (INVALIDDESC_CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_INVALIDDESC_CLR_Struct
+ *! \brief  DMA per Channel Invalid Descriptor Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_INVALIDDESC_CLR_t__
+typedef struct _ADI_DMA_INVALIDDESC_CLR_t {
+  union {
+    struct {
+      unsigned int CHAN       : 25;  /**< Per Channel Invalid Descriptor Status/Clear */
+      unsigned int reserved25 :  7;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_INVALIDDESC_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_INVALIDDESC_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup BS_SET DMA Channel Bytes Swap Enable Set (BS_SET) Register
+ *  DMA Channel Bytes Swap Enable Set (BS_SET) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_BS_SET_Struct
+ *! \brief  DMA Channel Bytes Swap Enable Set Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_BS_SET_t__
+typedef struct _ADI_DMA_BS_SET_t {
+  union {
+    struct {
+      unsigned int CHAN       : 25;  /**< Byte Swap Status */
+      unsigned int reserved25 :  7;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_BS_SET_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_BS_SET_t__ */
+
+/*@}*/
+
+/** @defgroup BS_CLR DMA Channel Bytes Swap Enable Clear (BS_CLR) Register
+ *  DMA Channel Bytes Swap Enable Clear (BS_CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_BS_CLR_Struct
+ *! \brief  DMA Channel Bytes Swap Enable Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_BS_CLR_t__
+typedef struct _ADI_DMA_BS_CLR_t {
+  union {
+    struct {
+      unsigned int CHAN       : 25;  /**< Disable Byte Swap */
+      unsigned int reserved25 :  7;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_BS_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_BS_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup SRCADDR_SET DMA Channel Source Address Decrement Enable Set (SRCADDR_SET) Register
+ *  DMA Channel Source Address Decrement Enable Set (SRCADDR_SET) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_SRCADDR_SET_Struct
+ *! \brief  DMA Channel Source Address Decrement Enable Set Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_SRCADDR_SET_t__
+typedef struct _ADI_DMA_SRCADDR_SET_t {
+  union {
+    struct {
+      unsigned int CHAN       : 25;  /**< Source Address Decrement Status */
+      unsigned int reserved25 :  7;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_SRCADDR_SET_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_SRCADDR_SET_t__ */
+
+/*@}*/
+
+/** @defgroup SRCADDR_CLR DMA Channel Source Address Decrement Enable Clear (SRCADDR_CLR) Register
+ *  DMA Channel Source Address Decrement Enable Clear (SRCADDR_CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_SRCADDR_CLR_Struct
+ *! \brief  DMA Channel Source Address Decrement Enable Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_SRCADDR_CLR_t__
+typedef struct _ADI_DMA_SRCADDR_CLR_t {
+  union {
+    struct {
+      unsigned int CHAN       : 25;  /**< Disable Source Address Decrement */
+      unsigned int reserved25 :  7;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_SRCADDR_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_SRCADDR_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup DSTADDR_SET DMA Channel Destination Address Decrement Enable Set (DSTADDR_SET) Register
+ *  DMA Channel Destination Address Decrement Enable Set (DSTADDR_SET) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_DSTADDR_SET_Struct
+ *! \brief  DMA Channel Destination Address Decrement Enable Set Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_DSTADDR_SET_t__
+typedef struct _ADI_DMA_DSTADDR_SET_t {
+  union {
+    struct {
+      unsigned int CHAN       : 25;  /**< Destination Address Decrement Status */
+      unsigned int reserved25 :  7;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_DSTADDR_SET_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_DSTADDR_SET_t__ */
+
+/*@}*/
+
+/** @defgroup DSTADDR_CLR DMA Channel Destination Address Decrement Enable Clear (DSTADDR_CLR) Register
+ *  DMA Channel Destination Address Decrement Enable Clear (DSTADDR_CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_DSTADDR_CLR_Struct
+ *! \brief  DMA Channel Destination Address Decrement Enable Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_DSTADDR_CLR_t__
+typedef struct _ADI_DMA_DSTADDR_CLR_t {
+  union {
+    struct {
+      unsigned int CHAN       : 25;  /**< Disable Destination Address Decrement */
+      unsigned int reserved25 :  7;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_DSTADDR_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_DSTADDR_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup REVID DMA Controller Revision ID (REVID) Register
+ *  DMA Controller Revision ID (REVID) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_REVID_Struct
+ *! \brief  DMA Controller Revision ID Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_REVID_t__
+typedef struct _ADI_DMA_REVID_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< DMA Controller Revision ID */
+      unsigned int reserved8  : 24;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_REVID_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_REVID_t__ */
+
+/*@}*/
+
+/** @defgroup STAT Status (STAT) Register
+ *  Status (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_STAT_Struct
+ *! \brief  Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_STAT_t__
+typedef struct _ADI_FLCC_STAT_t {
+  union {
+    struct {
+      unsigned int CMDBUSY    :  1;  /**< Command Busy */
+      unsigned int WRCLOSE    :  1;  /**< WRITE Registers are Closed */
+      unsigned int CMDCOMP    :  1;  /**< Command Complete */
+      unsigned int WRALCOMP   :  1;  /**< Write Almost Complete */
+      unsigned int CMDFAIL    :  2;  /**< Provides Information on Command Failures */
+      unsigned int SLEEPING   :  1;  /**< Flash Array is in Low Power (Sleep) Mode */
+      unsigned int ECCERRCMD  :  2;  /**< ECC Errors Detected During User Issued SIGN Command */
+      unsigned int ECCRDERR   :  2;  /**< ECC IRQ Cause */
+      unsigned int OVERLAP    :  1;  /**< Overlapping Command */
+      unsigned int reserved12 :  1;
+      unsigned int SIGNERR    :  1;  /**< Signature Check Failure During Initialization */
+      unsigned int INIT       :  1;  /**< Flash Controller Initialization in Progress */
+      unsigned int ECCINFOSIGN :  2;  /**< ECC Status of Flash Initialization */
+      unsigned int ECCERRCNT   :  3;  /**< ECC Correction Counter */
+      unsigned int reserved20  :  5;
+      unsigned int ECCICODE    :  2;  /**< ICode AHB Bus Error ECC Status */
+      unsigned int ECCDCODE    :  2;  /**< DCode AHB Bus Error ECC Status */
+      unsigned int CACHESRAMPERR :  1;  /**< SRAM Parity Errors in Cache Controller */
+      unsigned int reserved30    :  2;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup IEN Interrupt Enable (IEN) Register
+ *  Interrupt Enable (IEN) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_FLCC_IEN_ECC_ERROR
+ *! \brief  Control 2-bit ECC Error Events (ECC_ERROR) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  FLCC_IEN_NONE_ERR    = 0,  /**< Do not generate a response to ECC events      */
+  FLCC_IEN_BUS_ERR_ERR = 1,  /**< Generate Bus Errors in response to ECC events */
+  FLCC_IEN_IRQ_ERR     = 2   /**< Generate IRQs in response to ECC events       */
+} ADI_FLCC_IEN_ECC_ERROR;
+
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_IEN_Struct
+ *! \brief  Interrupt Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_IEN_t__
+typedef struct _ADI_FLCC_IEN_t {
+  union {
+    struct {
+      unsigned int CMDCMPLT   :  1;  /**< Command Complete Interrupt Enable */
+      unsigned int WRALCMPLT  :  1;  /**< Write Almost Complete Interrupt Enable */
+      unsigned int CMDFAIL    :  1;  /**< Command Fail Interrupt Enable */
+      unsigned int reserved3  :  3;
+      unsigned int ECC_ERROR  :  2;  /**< Control 2-bit ECC Error Events */
+      unsigned int reserved8  : 24;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_IEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_IEN_t__ */
+
+/*@}*/
+
+/** @defgroup CMD Command (CMD) Register
+ *  Command (CMD) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_FLCC_CMD_VALUE
+ *! \brief  Commands (VALUE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  FLCC_CMD_IDLE        = 0,  /**< IDLE                                                                  */
+  FLCC_CMD_ABORT       = 1,  /**< ABORT                                                                 */
+  FLCC_CMD_SLEEP       = 2,  /**< Requests flash to enter Sleep mode                                    */
+  FLCC_CMD_SIGN        = 3,  /**< SIGN                                                                  */
+  FLCC_CMD_WRITE       = 4,  /**< WRITE                                                                 */
+  FLCC_CMD_BLANK_CHECK = 5,  /**< Checks all of User Space; fails if any bits in user space are cleared */
+  FLCC_CMD_ERASEPAGE   = 6,  /**< ERASEPAGE                                                             */
+  FLCC_CMD_MASSERASE   = 7   /**< MASSERASE                                                             */
+} ADI_FLCC_CMD_VALUE;
+
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_CMD_Struct
+ *! \brief  Command Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CMD_t__
+typedef struct _ADI_FLCC_CMD_t {
+  union {
+    struct {
+      unsigned int VALUE      :  4;  /**< Commands */
+      unsigned int reserved4  : 28;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_CMD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CMD_t__ */
+
+/*@}*/
+
+/** @defgroup KH_ADDR Write Address (KH_ADDR) Register
+ *  Write Address (KH_ADDR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_KH_ADDR_Struct
+ *! \brief  Write Address Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_KH_ADDR_t__
+typedef struct _ADI_FLCC_KH_ADDR_t {
+  union {
+    struct {
+      unsigned int reserved0  :  3;
+      unsigned int VALUE      : 16;  /**< Key Hole Address */
+      unsigned int reserved19 : 13;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_KH_ADDR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_KH_ADDR_t__ */
+
+/*@}*/
+
+/** @defgroup KH_DATA0 Write Lower Data (KH_DATA0) Register
+ *  Write Lower Data (KH_DATA0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_KH_DATA0_Struct
+ *! \brief  Write Lower Data Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_KH_DATA0_t__
+typedef struct _ADI_FLCC_KH_DATA0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Lower 32 Bits of Key Hole Data */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_KH_DATA0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_KH_DATA0_t__ */
+
+/*@}*/
+
+/** @defgroup KH_DATA1 Write Upper Data (KH_DATA1) Register
+ *  Write Upper Data (KH_DATA1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_KH_DATA1_Struct
+ *! \brief  Write Upper Data Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_KH_DATA1_t__
+typedef struct _ADI_FLCC_KH_DATA1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Upper Half of 64-bit Dualword Data to Be Written */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_KH_DATA1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_KH_DATA1_t__ */
+
+/*@}*/
+
+/** @defgroup PAGE_ADDR0 Lower Page Address (PAGE_ADDR0) Register
+ *  Lower Page Address (PAGE_ADDR0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_PAGE_ADDR0_Struct
+ *! \brief  Lower Page Address Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_PAGE_ADDR0_t__
+typedef struct _ADI_FLCC_PAGE_ADDR0_t {
+  union {
+    struct {
+      unsigned int reserved0  : 10;
+      unsigned int VALUE      :  9;  /**< Lower Address Bits of the Page Address */
+      unsigned int reserved19 : 13;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_PAGE_ADDR0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_PAGE_ADDR0_t__ */
+
+/*@}*/
+
+/** @defgroup PAGE_ADDR1 Upper Page Address (PAGE_ADDR1) Register
+ *  Upper Page Address (PAGE_ADDR1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_PAGE_ADDR1_Struct
+ *! \brief  Upper Page Address Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_PAGE_ADDR1_t__
+typedef struct _ADI_FLCC_PAGE_ADDR1_t {
+  union {
+    struct {
+      unsigned int reserved0  : 10;
+      unsigned int VALUE      :  9;  /**< Upper Address Bits of the Page Address */
+      unsigned int reserved19 : 13;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_PAGE_ADDR1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_PAGE_ADDR1_t__ */
+
+/*@}*/
+
+/** @defgroup KEY Key (KEY) Register
+ *  Key (KEY) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_FLCC_KEY_VALUE
+ *! \brief  Key Register (VALUE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  FLCC_KEY_USERKEY = 1735161189   /**< USERKEY */
+} ADI_FLCC_KEY_VALUE;
+
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_KEY_Struct
+ *! \brief  Key Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_KEY_t__
+typedef struct _ADI_FLCC_KEY_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Key Register */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_KEY_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_KEY_t__ */
+
+/*@}*/
+
+/** @defgroup WR_ABORT_ADDR Write Abort Address (WR_ABORT_ADDR) Register
+ *  Write Abort Address (WR_ABORT_ADDR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_WR_ABORT_ADDR_Struct
+ *! \brief  Write Abort Address Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_WR_ABORT_ADDR_t__
+typedef struct _ADI_FLCC_WR_ABORT_ADDR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Address Targeted by an Ongoing Write Command */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_WR_ABORT_ADDR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_WR_ABORT_ADDR_t__ */
+
+/*@}*/
+
+/** @defgroup WRPROT Write Protection (WRPROT) Register
+ *  Write Protection (WRPROT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_WRPROT_Struct
+ *! \brief  Write Protection Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_WRPROT_t__
+typedef struct _ADI_FLCC_WRPROT_t {
+  union {
+    struct {
+      unsigned int WORD       : 32;  /**< Write Protect */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_WRPROT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_WRPROT_t__ */
+
+/*@}*/
+
+/** @defgroup SIGNATURE Signature (SIGNATURE) Register
+ *  Signature (SIGNATURE) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_SIGNATURE_Struct
+ *! \brief  Signature Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_SIGNATURE_t__
+typedef struct _ADI_FLCC_SIGNATURE_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Signature */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_SIGNATURE_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_SIGNATURE_t__ */
+
+/*@}*/
+
+/** @defgroup UCFG User Configuration (UCFG) Register
+ *  User Configuration (UCFG) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_UCFG_Struct
+ *! \brief  User Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_UCFG_t__
+typedef struct _ADI_FLCC_UCFG_t {
+  union {
+    struct {
+      unsigned int KHDMAEN    :  1;  /**< Key Hole DMA Enable */
+      unsigned int AUTOINCEN  :  1;  /**< Auto Address Increment for Key Hole Access */
+      unsigned int reserved2  : 30;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_UCFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_UCFG_t__ */
+
+/*@}*/
+
+/** @defgroup TIME_PARAM0 Time Parameter 0 (TIME_PARAM0) Register
+ *  Time Parameter 0 (TIME_PARAM0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_TIME_PARAM0_Struct
+ *! \brief  Time Parameter 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_TIME_PARAM0_t__
+typedef struct _ADI_FLCC_TIME_PARAM0_t {
+  union {
+    struct {
+      unsigned int DIVREFCLK  :  1;  /**< Divide Reference Clock (by 2) */
+      unsigned int reserved1  :  3;
+      unsigned int TNVS       :  4;  /**< PROG/ERASE to NVSTR Setup Time */
+      unsigned int TPGS       :  4;  /**< NVSTR to Program Setup Time */
+      unsigned int TPROG      :  4;  /**< Program Time */
+      unsigned int TNVH       :  4;  /**< NVSTR Hold Time */
+      unsigned int TRCV       :  4;  /**< Recovery Time */
+      unsigned int TERASE     :  4;  /**< Erase Time */
+      unsigned int TNVH1      :  4;  /**< NVSTR Hold Time During Mass Erase */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_TIME_PARAM0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_TIME_PARAM0_t__ */
+
+/*@}*/
+
+/** @defgroup TIME_PARAM1 Time Parameter 1 (TIME_PARAM1) Register
+ *  Time Parameter 1 (TIME_PARAM1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_TIME_PARAM1_Struct
+ *! \brief  Time Parameter 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_TIME_PARAM1_t__
+typedef struct _ADI_FLCC_TIME_PARAM1_t {
+  union {
+    struct {
+      unsigned int TWK        :  4;  /**< Wakeup Time */
+      unsigned int reserved4  : 28;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_TIME_PARAM1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_TIME_PARAM1_t__ */
+
+/*@}*/
+
+/** @defgroup ABORT_EN_LO IRQ Abort Enable (Lower Bits) (ABORT_EN_LO) Register
+ *  IRQ Abort Enable (Lower Bits) (ABORT_EN_LO) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_ABORT_EN_LO_Struct
+ *! \brief  IRQ Abort Enable (Lower Bits) Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_ABORT_EN_LO_t__
+typedef struct _ADI_FLCC_ABORT_EN_LO_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< VALUE[31:0] Sys IRQ Abort Enable */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_ABORT_EN_LO_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_ABORT_EN_LO_t__ */
+
+/*@}*/
+
+/** @defgroup ABORT_EN_HI IRQ Abort Enable (Upper Bits) (ABORT_EN_HI) Register
+ *  IRQ Abort Enable (Upper Bits) (ABORT_EN_HI) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_ABORT_EN_HI_Struct
+ *! \brief  IRQ Abort Enable (Upper Bits) Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_ABORT_EN_HI_t__
+typedef struct _ADI_FLCC_ABORT_EN_HI_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< VALUE[63:32] Sys IRQ Abort Enable */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_ABORT_EN_HI_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_ABORT_EN_HI_t__ */
+
+/*@}*/
+
+/** @defgroup ECC_CFG ECC Configuration (ECC_CFG) Register
+ *  ECC Configuration (ECC_CFG) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_ECC_CFG_Struct
+ *! \brief  ECC Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_ECC_CFG_t__
+typedef struct _ADI_FLCC_ECC_CFG_t {
+  union {
+    struct {
+      unsigned int EN         :  1;  /**< ECC Enable */
+      unsigned int INFOEN     :  1;  /**< Info Space ECC Enable Bit */
+      unsigned int reserved2  :  6;
+      unsigned int PTR        : 24;  /**< ECC Start Page Pointer */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_ECC_CFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_ECC_CFG_t__ */
+
+/*@}*/
+
+/** @defgroup ECC_ADDR ECC Status (Address) (ECC_ADDR) Register
+ *  ECC Status (Address) (ECC_ADDR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_ECC_ADDR_Struct
+ *! \brief  ECC Status (Address) Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_ECC_ADDR_t__
+typedef struct _ADI_FLCC_ECC_ADDR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 19;  /**< ECC Error Address */
+      unsigned int reserved19 : 13;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_ECC_ADDR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_ECC_ADDR_t__ */
+
+/*@}*/
+
+/** @defgroup POR_SEC Flash Security (POR_SEC) Register
+ *  Flash Security (POR_SEC) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_POR_SEC_Struct
+ *! \brief  Flash Security Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_POR_SEC_t__
+typedef struct _ADI_FLCC_POR_SEC_t {
+  union {
+    struct {
+      unsigned int SECURE     :  1;  /**< Prevent Read/Write Access to User Space (Sticky When Set) */
+      unsigned int reserved1  : 31;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_POR_SEC_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_POR_SEC_t__ */
+
+/*@}*/
+
+/** @defgroup VOL_CFG Volatile Flash Configuration (VOL_CFG) Register
+ *  Volatile Flash Configuration (VOL_CFG) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_VOL_CFG_Struct
+ *! \brief  Volatile Flash Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_VOL_CFG_t__
+typedef struct _ADI_FLCC_VOL_CFG_t {
+  union {
+    struct {
+      unsigned int INFO_REMAP :  1;  /**< Alias the Info Space to the Base Address of User Space */
+      unsigned int reserved1  : 31;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_VOL_CFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_VOL_CFG_t__ */
+
+/*@}*/
+
+/** @defgroup STAT Cache Status (STAT) Register
+ *  Cache Status (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_CACHE_STAT_Struct
+ *! \brief  Cache Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_STAT_t__
+typedef struct _ADI_FLCC_CACHE_STAT_t {
+  union {
+    struct {
+      unsigned int ICEN       :  1;  /**< I-Cache Enabled */
+      unsigned int reserved1  : 31;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_CACHE_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup SETUP Cache Setup (SETUP) Register
+ *  Cache Setup (SETUP) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_CACHE_SETUP_Struct
+ *! \brief  Cache Setup Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_SETUP_t__
+typedef struct _ADI_FLCC_CACHE_SETUP_t {
+  union {
+    struct {
+      unsigned int ICEN       :  1;  /**< I-Cache Enable */
+      unsigned int reserved1  : 31;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_CACHE_SETUP_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_SETUP_t__ */
+
+/*@}*/
+
+/** @defgroup KEY Cache Key (KEY) Register
+ *  Cache Key (KEY) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_CACHE_KEY_Struct
+ *! \brief  Cache Key Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_KEY_t__
+typedef struct _ADI_FLCC_CACHE_KEY_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Cache Key Register */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_CACHE_KEY_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_KEY_t__ */
+
+/*@}*/
+
+/** @defgroup CFG Port Configuration (CFG) Register
+ *  Port Configuration (CFG) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_CFG_Struct
+ *! \brief  Port Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_CFG_t__
+typedef struct _ADI_GPIO_CFG_t {
+  union {
+    struct {
+      unsigned int PIN00      :  2;  /**< Pin 0 Configuration Bits */
+      unsigned int PIN01      :  2;  /**< Pin 1 Configuration Bits */
+      unsigned int PIN02      :  2;  /**< Pin 2 Configuration Bits */
+      unsigned int PIN03      :  2;  /**< Pin 3 Configuration Bits */
+      unsigned int PIN04      :  2;  /**< Pin 4 Configuration Bits */
+      unsigned int PIN05      :  2;  /**< Pin 5 Configuration Bits */
+      unsigned int PIN06      :  2;  /**< Pin 6 Configuration Bits */
+      unsigned int PIN07      :  2;  /**< Pin 7 Configuration Bits */
+      unsigned int PIN08      :  2;  /**< Pin 8 Configuration Bits */
+      unsigned int PIN09      :  2;  /**< Pin 9 Configuration Bits */
+      unsigned int PIN10      :  2;  /**< Pin 10 Configuration Bits */
+      unsigned int PIN11      :  2;  /**< Pin 11 Configuration Bits */
+      unsigned int PIN12      :  2;  /**< Pin 12 Configuration Bits */
+      unsigned int PIN13      :  2;  /**< Pin 13 Configuration Bits */
+      unsigned int PIN14      :  2;  /**< Pin 14 Configuration Bits */
+      unsigned int PIN15      :  2;  /**< Pin 15 Configuration Bits */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_GPIO_CFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_CFG_t__ */
+
+/*@}*/
+
+/** @defgroup OEN Port Output Enable (OEN) Register
+ *  Port Output Enable (OEN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_OEN_Struct
+ *! \brief  Port Output Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_OEN_t__
+typedef struct _ADI_GPIO_OEN_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Pin Output Drive Enable */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_OEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_OEN_t__ */
+
+/*@}*/
+
+/** @defgroup PE Port Output Pull-up/Pull-down Enable (PE) Register
+ *  Port Output Pull-up/Pull-down Enable (PE) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_PE_Struct
+ *! \brief  Port Output Pull-up/Pull-down Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_PE_t__
+typedef struct _ADI_GPIO_PE_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Pin Pull Enable */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_PE_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_PE_t__ */
+
+/*@}*/
+
+/** @defgroup IEN Port Input Path Enable (IEN) Register
+ *  Port Input Path Enable (IEN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_IEN_Struct
+ *! \brief  Port Input Path Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_IEN_t__
+typedef struct _ADI_GPIO_IEN_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Input Path Enable */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_IEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_IEN_t__ */
+
+/*@}*/
+
+/** @defgroup IN Port Registered Data Input (IN) Register
+ *  Port Registered Data Input (IN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_IN_Struct
+ *! \brief  Port Registered Data Input Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_IN_t__
+typedef struct _ADI_GPIO_IN_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Registered Data Input */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_IN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_IN_t__ */
+
+/*@}*/
+
+/** @defgroup OUT Port Data Output (OUT) Register
+ *  Port Data Output (OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_OUT_Struct
+ *! \brief  Port Data Output Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_OUT_t__
+typedef struct _ADI_GPIO_OUT_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Data Out */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup SET Port Data Out Set (SET) Register
+ *  Port Data Out Set (SET) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_SET_Struct
+ *! \brief  Port Data Out Set Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_SET_t__
+typedef struct _ADI_GPIO_SET_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Set the Output High for the Pin */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_SET_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_SET_t__ */
+
+/*@}*/
+
+/** @defgroup CLR Port Data Out Clear (CLR) Register
+ *  Port Data Out Clear (CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_CLR_Struct
+ *! \brief  Port Data Out Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_CLR_t__
+typedef struct _ADI_GPIO_CLR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Set the Output Low for the Port Pin */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup TGL Port Pin Toggle (TGL) Register
+ *  Port Pin Toggle (TGL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_TGL_Struct
+ *! \brief  Port Pin Toggle Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_TGL_t__
+typedef struct _ADI_GPIO_TGL_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Toggle the Output of the Port Pin */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_TGL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_TGL_t__ */
+
+/*@}*/
+
+/** @defgroup POL Port Interrupt Polarity (POL) Register
+ *  Port Interrupt Polarity (POL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_POL_Struct
+ *! \brief  Port Interrupt Polarity Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_POL_t__
+typedef struct _ADI_GPIO_POL_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Interrupt polarity */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_POL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_POL_t__ */
+
+/*@}*/
+
+/** @defgroup IENA Port Interrupt A Enable (IENA) Register
+ *  Port Interrupt A Enable (IENA) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_IENA_Struct
+ *! \brief  Port Interrupt A Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_IENA_t__
+typedef struct _ADI_GPIO_IENA_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Interrupt A enable */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_IENA_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_IENA_t__ */
+
+/*@}*/
+
+/** @defgroup IENB Port Interrupt B Enable (IENB) Register
+ *  Port Interrupt B Enable (IENB) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_IENB_Struct
+ *! \brief  Port Interrupt B Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_IENB_t__
+typedef struct _ADI_GPIO_IENB_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Interrupt B enable */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_IENB_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_IENB_t__ */
+
+/*@}*/
+
+/** @defgroup INT Port Interrupt Status (INT) Register
+ *  Port Interrupt Status (INT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_INT_Struct
+ *! \brief  Port Interrupt Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_INT_t__
+typedef struct _ADI_GPIO_INT_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Interrupt Status */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_INT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_INT_t__ */
+
+/*@}*/
+
+/** @defgroup DS Port Drive Strength Select (DS) Register
+ *  Port Drive Strength Select (DS) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_DS_Struct
+ *! \brief  Port Drive Strength Select Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_DS_t__
+typedef struct _ADI_GPIO_DS_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Drive Strength Select */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_DS_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_DS_t__ */
+
+/*@}*/
+
+/** @defgroup CTL_A Half SPORT 'A' Control (CTL_A) Register
+ *  Half SPORT 'A' Control (CTL_A) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_SPEN
+ *! \brief  Serial Port Enable (SPEN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_DIS = 0,  /**< Disable */
+  SPORT_CTL_A_CTL_EN  = 1   /**< Enable  */
+} ADI_SPORT_CTL_A_SPEN;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_FSMUXSEL
+ *! \brief  Frame Sync Multiplexer Select (FSMUXSEL) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_FS_MUX_DIS = 0,  /**< Disable frame sync multiplexing */
+  SPORT_CTL_A_CTL_FS_MUX_EN  = 1   /**< Enable frame sync multiplexing  */
+} ADI_SPORT_CTL_A_FSMUXSEL;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_CKMUXSEL
+ *! \brief  Clock Multiplexer Select (CKMUXSEL) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_CLK_MUX_DIS = 0,  /**< Disable serial clock multiplexing */
+  SPORT_CTL_A_CTL_CLK_MUX_EN  = 1   /**< Enable serial clock multiplexing  */
+} ADI_SPORT_CTL_A_CKMUXSEL;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_LSBF
+ *! \brief  Least-Significant Bit First (LSBF) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_MSB_FIRST = 0,  /**< MSB first sent/received */
+  SPORT_CTL_A_CTL_LSB_FIRST = 1   /**< LSB first sent/received */
+} ADI_SPORT_CTL_A_LSBF;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_ICLK
+ *! \brief  Internal Clock (ICLK) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_EXTERNAL_CLK = 0,  /**< External clock */
+  SPORT_CTL_A_CTL_INTERNAL_CLK = 1   /**< Internal clock */
+} ADI_SPORT_CTL_A_ICLK;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_OPMODE
+ *! \brief  Operation Mode (OPMODE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_SERIAL        = 0,  /**< DSP standard      */
+  SPORT_CTL_A_CTL_TIMER_EN_MODE = 1   /**< Timer_enable mode */
+} ADI_SPORT_CTL_A_OPMODE;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_CKRE
+ *! \brief  Clock Rising Edge (CKRE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_CLK_FALL_EDGE = 0,  /**< Clock falling edge */
+  SPORT_CTL_A_CTL_CLK_RISE_EDGE = 1   /**< Clock rising edge  */
+} ADI_SPORT_CTL_A_CKRE;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_FSR
+ *! \brief  Frame Sync Required (FSR) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_FS_NOT_REQ = 0,  /**< No frame sync required */
+  SPORT_CTL_A_CTL_FS_REQ     = 1   /**< Frame sync required    */
+} ADI_SPORT_CTL_A_FSR;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_IFS
+ *! \brief  Internal Frame Sync (IFS) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_EXTERNAL_FS = 0,  /**< External frame sync */
+  SPORT_CTL_A_CTL_INTERNAL_FS = 1   /**< Internal frame sync */
+} ADI_SPORT_CTL_A_IFS;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_DIFS
+ *! \brief  Data-Independent Frame Sync (DIFS) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_DATA_DEP_FS  = 0,  /**< Data-dependent frame sync   */
+  SPORT_CTL_A_CTL_DATA_INDP_FS = 1   /**< Data-independent frame sync */
+} ADI_SPORT_CTL_A_DIFS;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_LFS
+ *! \brief  Active-Low Frame Sync (LFS) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_FS_LO = 0,  /**< Active high frame sync */
+  SPORT_CTL_A_CTL_FS_HI = 1   /**< Active low frame sync  */
+} ADI_SPORT_CTL_A_LFS;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_LAFS
+ *! \brief  Late Frame Sync (LAFS) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_EARLY_FS = 0,  /**< Early frame sync */
+  SPORT_CTL_A_CTL_LATE_FS  = 1   /**< Late frame sync  */
+} ADI_SPORT_CTL_A_LAFS;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_PACK
+ *! \brief  Packing Enable (PACK) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_PACK_DIS   = 0,  /**< Disable               */
+  SPORT_CTL_A_CTL_PACK_8BIT  = 1,  /**< 8-bit packing enable  */
+  SPORT_CTL_A_CTL_PACK_16BIT = 2,  /**< 16-bit packing enable */
+  SPORT_CTL_A_CTL_PACK_RSV   = 3   /**< Reserved              */
+} ADI_SPORT_CTL_A_PACK;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_GCLKEN
+ *! \brief  Gated Clock Enable (GCLKEN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_GCLK_DIS = 0,  /**< Disable */
+  SPORT_CTL_A_CTL_GCLK_EN  = 1   /**< Enable  */
+} ADI_SPORT_CTL_A_GCLKEN;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_SPTRAN
+ *! \brief  Serial Port Transfer Direction (SPTRAN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_RX = 0,  /**< Receive  */
+  SPORT_CTL_A_CTL_TX = 1   /**< Transmit */
+} ADI_SPORT_CTL_A_SPTRAN;
+
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_CTL_A_Struct
+ *! \brief  Half SPORT 'A' Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_CTL_A_t__
+typedef struct _ADI_SPORT_CTL_A_t {
+  union {
+    struct {
+      unsigned int SPEN       :  1;  /**< Serial Port Enable */
+      unsigned int FSMUXSEL   :  1;  /**< Frame Sync Multiplexer Select */
+      unsigned int CKMUXSEL   :  1;  /**< Clock Multiplexer Select */
+      unsigned int LSBF       :  1;  /**< Least-Significant Bit First */
+      unsigned int SLEN       :  5;  /**< Serial Word Length */
+      unsigned int reserved9  :  1;
+      unsigned int ICLK       :  1;  /**< Internal Clock */
+      unsigned int OPMODE     :  1;  /**< Operation Mode */
+      unsigned int CKRE       :  1;  /**< Clock Rising Edge */
+      unsigned int FSR        :  1;  /**< Frame Sync Required */
+      unsigned int IFS        :  1;  /**< Internal Frame Sync */
+      unsigned int DIFS       :  1;  /**< Data-Independent Frame Sync */
+      unsigned int LFS        :  1;  /**< Active-Low Frame Sync */
+      unsigned int LAFS       :  1;  /**< Late Frame Sync */
+      unsigned int PACK       :  2;  /**< Packing Enable */
+      unsigned int FSERRMODE  :  1;  /**< Frame Sync Error Operation */
+      unsigned int GCLKEN     :  1;  /**< Gated Clock Enable */
+      unsigned int reserved22 :  3;
+      unsigned int SPTRAN     :  1;  /**< Serial Port Transfer Direction */
+      unsigned int DMAEN      :  1;  /**< DMA Enable */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_CTL_A_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_CTL_A_t__ */
+
+/*@}*/
+
+/** @defgroup DIV_A Half SPORT 'A' Divisor (DIV_A) Register
+ *  Half SPORT 'A' Divisor (DIV_A) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_DIV_A_Struct
+ *! \brief  Half SPORT 'A' Divisor Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_DIV_A_t__
+typedef struct _ADI_SPORT_DIV_A_t {
+  union {
+    struct {
+      unsigned int CLKDIV     : 16;  /**< Clock Divisor */
+      unsigned int FSDIV      :  8;  /**< Frame Sync Divisor */
+      unsigned int reserved24 :  8;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_DIV_A_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_DIV_A_t__ */
+
+/*@}*/
+
+/** @defgroup IEN_A Half SPORT A's Interrupt Enable (IEN_A) Register
+ *  Half SPORT A's Interrupt Enable (IEN_A) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_IEN_A_TF
+ *! \brief  Transfer Finish Interrupt Enable (TF) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_IEN_A_CTL_TXFIN_DIS = 0,  /**< Transfer finish Interrupt is disabled */
+  SPORT_IEN_A_CTL_TXFIN_EN  = 1   /**< Transfer Finish Interrupt is Enabled  */
+} ADI_SPORT_IEN_A_TF;
+
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_IEN_A_Struct
+ *! \brief  Half SPORT A's Interrupt Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_IEN_A_t__
+typedef struct _ADI_SPORT_IEN_A_t {
+  union {
+    struct {
+      unsigned int TF         :  1;  /**< Transfer Finish Interrupt Enable */
+      unsigned int DERRMSK    :  1;  /**< Data Error (Interrupt) Mask */
+      unsigned int FSERRMSK   :  1;  /**< Frame Sync Error (Interrupt) Mask */
+      unsigned int DATA       :  1;  /**< Data Request Interrupt to the Core */
+      unsigned int SYSDATERR  :  1;  /**< Data Error for System Writes or Reads */
+      unsigned int reserved5  : 27;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_IEN_A_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_IEN_A_t__ */
+
+/*@}*/
+
+/** @defgroup STAT_A Half SPORT A's Status (STAT_A) Register
+ *  Half SPORT A's Status (STAT_A) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_STAT_A_DXS
+ *! \brief  Data Transfer Buffer Status (DXS) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_STAT_A_CTL_EMPTY     = 0,  /**< Empty          */
+  SPORT_STAT_A_CTL_RSV       = 1,  /**< Reserved       */
+  SPORT_STAT_A_CTL_PART_FULL = 2,  /**< Partially full */
+  SPORT_STAT_A_CTL_FULL      = 3   /**< Full           */
+} ADI_SPORT_STAT_A_DXS;
+
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_STAT_A_Struct
+ *! \brief  Half SPORT A's Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_STAT_A_t__
+typedef struct _ADI_SPORT_STAT_A_t {
+  union {
+    struct {
+      unsigned int TFI        :  1;  /**< Transmit Finish Interrupt Status */
+      unsigned int DERR       :  1;  /**< Data Error Status */
+      unsigned int FSERR      :  1;  /**< Frame Sync Error Status */
+      unsigned int DATA       :  1;  /**< Data Buffer Status */
+      unsigned int SYSDATERR  :  1;  /**< System Data Error Status */
+      unsigned int reserved5  :  3;
+      unsigned int DXS        :  2;  /**< Data Transfer Buffer Status */
+      unsigned int reserved10 : 22;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_STAT_A_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_STAT_A_t__ */
+
+/*@}*/
+
+/** @defgroup NUMTRAN_A Half SPORT A Number of Transfers (NUMTRAN_A) Register
+ *  Half SPORT A Number of Transfers (NUMTRAN_A) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_NUMTRAN_A_Struct
+ *! \brief  Half SPORT A Number of Transfers Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_NUMTRAN_A_t__
+typedef struct _ADI_SPORT_NUMTRAN_A_t {
+  union {
+    struct {
+      unsigned int VALUE      : 12;  /**< Number of Transfers (Half SPORT A) */
+      unsigned int reserved12 : 20;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_NUMTRAN_A_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_NUMTRAN_A_t__ */
+
+/*@}*/
+
+/** @defgroup CNVT_A Half SPORT 'A' CNV Width (CNVT_A) Register
+ *  Half SPORT 'A' CNV Width (CNVT_A) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_CNVT_A_Struct
+ *! \brief  Half SPORT 'A' CNV Width Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_CNVT_A_t__
+typedef struct _ADI_SPORT_CNVT_A_t {
+  union {
+    struct {
+      unsigned int WID        :  4;  /**< SPT_CNVT Signal Width: Half SPORT a */
+      unsigned int reserved4  :  4;
+      unsigned int POL        :  1;  /**< Polarity of the SPT_CNVT Signal */
+      unsigned int reserved9  :  7;
+      unsigned int CNVT2FS    :  8;  /**< SPT_CNVT to FS Duration: Half SPORT a */
+      unsigned int reserved24 :  8;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_CNVT_A_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_CNVT_A_t__ */
+
+/*@}*/
+
+/** @defgroup TX_A Half SPORT 'A' Tx Buffer (TX_A) Register
+ *  Half SPORT 'A' Tx Buffer (TX_A) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_TX_A_Struct
+ *! \brief  Half SPORT 'A' Tx Buffer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_TX_A_t__
+typedef struct _ADI_SPORT_TX_A_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Transmit Buffer */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_TX_A_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_TX_A_t__ */
+
+/*@}*/
+
+/** @defgroup RX_A Half SPORT 'A' Rx Buffer (RX_A) Register
+ *  Half SPORT 'A' Rx Buffer (RX_A) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_RX_A_Struct
+ *! \brief  Half SPORT 'A' Rx Buffer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_RX_A_t__
+typedef struct _ADI_SPORT_RX_A_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Receive Buffer */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_RX_A_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_RX_A_t__ */
+
+/*@}*/
+
+/** @defgroup CTL_B Half SPORT 'B' Control (CTL_B) Register
+ *  Half SPORT 'B' Control (CTL_B) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_B_PACK
+ *! \brief  Packing Enable (PACK) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_B_CTL_PACK_DIS   = 0,  /**< Disable               */
+  SPORT_CTL_B_CTL_PACK_8BIT  = 1,  /**< 8-bit packing enable  */
+  SPORT_CTL_B_CTL_PACK_16BIT = 2,  /**< 16-bit packing enable */
+  SPORT_CTL_B_CTL_PACK_RSV   = 3   /**< Reserved              */
+} ADI_SPORT_CTL_B_PACK;
+
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_CTL_B_Struct
+ *! \brief  Half SPORT 'B' Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_CTL_B_t__
+typedef struct _ADI_SPORT_CTL_B_t {
+  union {
+    struct {
+      unsigned int SPEN       :  1;  /**< Serial Port Enable */
+      unsigned int reserved1  :  2;
+      unsigned int LSBF       :  1;  /**< Least-Significant Bit First */
+      unsigned int SLEN       :  5;  /**< Serial Word Length */
+      unsigned int reserved9  :  1;
+      unsigned int ICLK       :  1;  /**< Internal Clock */
+      unsigned int OPMODE     :  1;  /**< Operation Mode */
+      unsigned int CKRE       :  1;  /**< Clock Rising Edge */
+      unsigned int FSR        :  1;  /**< Frame Sync Required */
+      unsigned int IFS        :  1;  /**< Internal Frame Sync */
+      unsigned int DIFS       :  1;  /**< Data-Independent Frame Sync */
+      unsigned int LFS        :  1;  /**< Active-Low Frame Sync */
+      unsigned int LAFS       :  1;  /**< Late Frame Sync */
+      unsigned int PACK       :  2;  /**< Packing Enable */
+      unsigned int FSERRMODE  :  1;  /**< Frame Sync Error Operation */
+      unsigned int GCLKEN     :  1;  /**< Gated Clock Enable */
+      unsigned int reserved22 :  3;
+      unsigned int SPTRAN     :  1;  /**< Serial Port Transfer Direction */
+      unsigned int DMAEN      :  1;  /**< DMA Enable */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_CTL_B_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_CTL_B_t__ */
+
+/*@}*/
+
+/** @defgroup DIV_B Half SPORT 'B' Divisor (DIV_B) Register
+ *  Half SPORT 'B' Divisor (DIV_B) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_DIV_B_Struct
+ *! \brief  Half SPORT 'B' Divisor Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_DIV_B_t__
+typedef struct _ADI_SPORT_DIV_B_t {
+  union {
+    struct {
+      unsigned int CLKDIV     : 16;  /**< Clock Divisor */
+      unsigned int FSDIV      :  8;  /**< Frame Sync Divisor */
+      unsigned int reserved24 :  8;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_DIV_B_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_DIV_B_t__ */
+
+/*@}*/
+
+/** @defgroup IEN_B Half SPORT B's Interrupt Enable (IEN_B) Register
+ *  Half SPORT B's Interrupt Enable (IEN_B) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_IEN_B_TF
+ *! \brief  Transmit Finish Interrupt Enable (TF) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_IEN_B_CTL_TXFIN_DIS = 0,  /**< Transfer Finish Interrupt is disabled */
+  SPORT_IEN_B_CTL_TXFIN_EN  = 1   /**< Transfer Finish Interrupt is Enabled  */
+} ADI_SPORT_IEN_B_TF;
+
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_IEN_B_Struct
+ *! \brief  Half SPORT B's Interrupt Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_IEN_B_t__
+typedef struct _ADI_SPORT_IEN_B_t {
+  union {
+    struct {
+      unsigned int TF         :  1;  /**< Transmit Finish Interrupt Enable */
+      unsigned int DERRMSK    :  1;  /**< Data Error (Interrupt) Mask */
+      unsigned int FSERRMSK   :  1;  /**< Frame Sync Error (Interrupt) Mask */
+      unsigned int DATA       :  1;  /**< Data Request Interrupt to the Core */
+      unsigned int SYSDATERR  :  1;  /**< Data Error for System Writes or Reads */
+      unsigned int reserved5  : 27;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_IEN_B_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_IEN_B_t__ */
+
+/*@}*/
+
+/** @defgroup STAT_B Half SPORT B's Status (STAT_B) Register
+ *  Half SPORT B's Status (STAT_B) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_STAT_B_DXS
+ *! \brief  Data Transfer Buffer Status (DXS) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_STAT_B_CTL_EMPTY     = 0,  /**< Empty          */
+  SPORT_STAT_B_CTL_RSV       = 1,  /**< Reserved       */
+  SPORT_STAT_B_CTL_PART_FULL = 2,  /**< Partially full */
+  SPORT_STAT_B_CTL_FULL      = 3   /**< Full           */
+} ADI_SPORT_STAT_B_DXS;
+
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_STAT_B_Struct
+ *! \brief  Half SPORT B's Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_STAT_B_t__
+typedef struct _ADI_SPORT_STAT_B_t {
+  union {
+    struct {
+      unsigned int TFI        :  1;  /**< Transmit Finish Interrupt Status */
+      unsigned int DERR       :  1;  /**< Data Error Status */
+      unsigned int FSERR      :  1;  /**< Frame Sync Error Status */
+      unsigned int DATA       :  1;  /**< Data Buffer Status */
+      unsigned int SYSDATERR  :  1;  /**< System Data Error Status */
+      unsigned int reserved5  :  3;
+      unsigned int DXS        :  2;  /**< Data Transfer Buffer Status */
+      unsigned int reserved10 : 22;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_STAT_B_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_STAT_B_t__ */
+
+/*@}*/
+
+/** @defgroup NUMTRAN_B Half SPORT B Number of Transfers (NUMTRAN_B) Register
+ *  Half SPORT B Number of Transfers (NUMTRAN_B) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_NUMTRAN_B_Struct
+ *! \brief  Half SPORT B Number of Transfers Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_NUMTRAN_B_t__
+typedef struct _ADI_SPORT_NUMTRAN_B_t {
+  union {
+    struct {
+      unsigned int VALUE      : 12;  /**< Number of Transfers (Half SPORT A) */
+      unsigned int reserved12 : 20;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_NUMTRAN_B_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_NUMTRAN_B_t__ */
+
+/*@}*/
+
+/** @defgroup CNVT_B Half SPORT 'B' CNV Width (CNVT_B) Register
+ *  Half SPORT 'B' CNV Width (CNVT_B) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_CNVT_B_Struct
+ *! \brief  Half SPORT 'B' CNV Width Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_CNVT_B_t__
+typedef struct _ADI_SPORT_CNVT_B_t {
+  union {
+    struct {
+      unsigned int WID        :  4;  /**< SPT_CNVT Signal Width: Half SPORT B */
+      unsigned int reserved4  :  4;
+      unsigned int POL        :  1;  /**< Polarity of the SPT_CNVT Signal */
+      unsigned int reserved9  :  7;
+      unsigned int CNVT2FS    :  8;  /**< SPT_CNVT to FS Duration: Half SPORT B */
+      unsigned int reserved24 :  8;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_CNVT_B_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_CNVT_B_t__ */
+
+/*@}*/
+
+/** @defgroup TX_B Half SPORT 'B' Tx Buffer (TX_B) Register
+ *  Half SPORT 'B' Tx Buffer (TX_B) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_TX_B_Struct
+ *! \brief  Half SPORT 'B' Tx Buffer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_TX_B_t__
+typedef struct _ADI_SPORT_TX_B_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Transmit Buffer */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_TX_B_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_TX_B_t__ */
+
+/*@}*/
+
+/** @defgroup RX_B Half SPORT 'B' Rx Buffer (RX_B) Register
+ *  Half SPORT 'B' Rx Buffer (RX_B) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_RX_B_Struct
+ *! \brief  Half SPORT 'B' Rx Buffer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_RX_B_t__
+typedef struct _ADI_SPORT_RX_B_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Receive Buffer */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_RX_B_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_RX_B_t__ */
+
+/*@}*/
+
+/** @defgroup CTL CRC Control (CTL) Register
+ *  CRC Control (CTL) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_CRC_CTL_EN
+ *! \brief  CRC Peripheral Enable (EN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CRC_CTL_CRC_DIS = 0,  /**< CRC peripheral is disabled */
+  CRC_CTL_CRC_EN  = 1   /**< CRC peripheral is enabled  */
+} ADI_CRC_CTL_EN;
+
+
+/*  =========================================================================
+ *! \enum   ADI_CRC_CTL_LSBFIRST
+ *! \brief  LSB First Calculation Order (LSBFIRST) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CRC_CTL_MSB_FIRST = 0,  /**< MSB First CRC calculation is done */
+  CRC_CTL_LSB_FIRST = 1   /**< LSB First CRC calculation is done */
+} ADI_CRC_CTL_LSBFIRST;
+
+
+/*  =========================================================================
+ *! \enum   ADI_CRC_CTL_BITMIRR
+ *! \brief  Bit Mirroring (BITMIRR) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CRC_CTL_BITMIRR_DIS = 0,  /**< Bit Mirroring is disabled */
+  CRC_CTL_BITMIRR_EN  = 1   /**< Bit Mirroring is enabled  */
+} ADI_CRC_CTL_BITMIRR;
+
+
+/*  =========================================================================
+ *! \enum   ADI_CRC_CTL_BYTMIRR
+ *! \brief  Byte Mirroring (BYTMIRR) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CRC_CTL_BYTEMIR_DIS = 0,  /**< Byte Mirroring is disabled */
+  CRC_CTL_BYTEMIR_EN  = 1   /**< Byte Mirroring is enabled  */
+} ADI_CRC_CTL_BYTMIRR;
+
+
+/*  =========================================================================
+ *! \enum   ADI_CRC_CTL_W16SWP
+ *! \brief  Word16 Swap (W16SWP) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CRC_CTL_W16SP_DIS = 0,  /**< Word16 Swap disabled */
+  CRC_CTL_W16SP_EN  = 1   /**< Word16 Swap enabled  */
+} ADI_CRC_CTL_W16SWP;
+
+
+/* ==========================================================================
+ *! \struct ADI_CRC_CTL_Struct
+ *! \brief  CRC Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_CTL_t__
+typedef struct _ADI_CRC_CTL_t {
+  union {
+    struct {
+      unsigned int EN         :  1;  /**< CRC Peripheral Enable */
+      unsigned int LSBFIRST   :  1;  /**< LSB First Calculation Order */
+      unsigned int BITMIRR    :  1;  /**< Bit Mirroring */
+      unsigned int BYTMIRR    :  1;  /**< Byte Mirroring */
+      unsigned int W16SWP     :  1;  /**< Word16 Swap */
+      unsigned int reserved5  : 23;
+      unsigned int RevID      :  4;  /**< Revision ID */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRC_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup IPDATA Input Data Word (IPDATA) Register
+ *  Input Data Word (IPDATA) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRC_IPDATA_Struct
+ *! \brief  Input Data Word Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_IPDATA_t__
+typedef struct _ADI_CRC_IPDATA_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Data Input */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRC_IPDATA_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_IPDATA_t__ */
+
+/*@}*/
+
+/** @defgroup RESULT CRC Result (RESULT) Register
+ *  CRC Result (RESULT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRC_RESULT_Struct
+ *! \brief  CRC Result Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_RESULT_t__
+typedef struct _ADI_CRC_RESULT_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< CRC Residue */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRC_RESULT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_RESULT_t__ */
+
+/*@}*/
+
+/** @defgroup POLY Programmable CRC Polynomial (POLY) Register
+ *  Programmable CRC Polynomial (POLY) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRC_POLY_Struct
+ *! \brief  Programmable CRC Polynomial Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_POLY_t__
+typedef struct _ADI_CRC_POLY_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< CRC Reduction Polynomial */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRC_POLY_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_POLY_t__ */
+
+/*@}*/
+
+/** @defgroup IPBITS Input Data Bits (IPBITS) Register
+ *  Input Data Bits (IPBITS) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRC_IPBITS_Struct
+ *! \brief  Input Data Bits Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_IPBITS_t__
+typedef struct _ADI_CRC_IPBITS_t {
+  union {
+    struct {
+      unsigned int DATA_BITS  :  8;  /**< Input Data Bits */
+    };
+    uint8_t VALUE8;
+  };
+} ADI_CRC_IPBITS_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_IPBITS_t__ */
+
+/*@}*/
+
+/** @defgroup IPBYTE Input Data Byte (IPBYTE) Register
+ *  Input Data Byte (IPBYTE) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRC_IPBYTE_Struct
+ *! \brief  Input Data Byte Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_IPBYTE_t__
+typedef struct _ADI_CRC_IPBYTE_t {
+  union {
+    struct {
+      unsigned int DATA_BYTE  :  8;  /**< Input Data Byte */
+    };
+    uint8_t VALUE8;
+  };
+} ADI_CRC_IPBYTE_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_IPBYTE_t__ */
+
+/*@}*/
+
+/** @defgroup CTL RNG Control Register (CTL) Register
+ *  RNG Control Register (CTL) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_RNG_CTL_EN
+ *! \brief  RNG Enable (EN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  RNG_CTL_DISABLE = 0,  /**< Disable the RNG */
+  RNG_CTL_ENABLE  = 1   /**< Enable the RNG  */
+} ADI_RNG_CTL_EN;
+
+
+/*  =========================================================================
+ *! \enum   ADI_RNG_CTL_SINGLE
+ *! \brief  Generate a Single Number (SINGLE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  RNG_CTL_WORD   = 0,  /**< Buffer Word */
+  RNG_CTL_SINGLE = 1   /**< Single Byte */
+} ADI_RNG_CTL_SINGLE;
+
+
+/* ==========================================================================
+ *! \struct ADI_RNG_CTL_Struct
+ *! \brief  RNG Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_CTL_t__
+typedef struct _ADI_RNG_CTL_t {
+  union {
+    struct {
+      unsigned int EN         :  1;  /**< RNG Enable */
+      unsigned int reserved1  :  2;
+      unsigned int SINGLE     :  1;  /**< Generate a Single Number */
+      unsigned int reserved4  : 12;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RNG_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup LEN RNG Sample Length Register (LEN) Register
+ *  RNG Sample Length Register (LEN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RNG_LEN_Struct
+ *! \brief  RNG Sample Length Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_LEN_t__
+typedef struct _ADI_RNG_LEN_t {
+  union {
+    struct {
+      unsigned int RELOAD     : 12;  /**< Reload Value for the Sample Counter */
+      unsigned int PRESCALE   :  4;  /**< Prescaler for the Sample Counter */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RNG_LEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_LEN_t__ */
+
+/*@}*/
+
+/** @defgroup STAT RNG Status Register (STAT) Register
+ *  RNG Status Register (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RNG_STAT_Struct
+ *! \brief  RNG Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_STAT_t__
+typedef struct _ADI_RNG_STAT_t {
+  union {
+    struct {
+      unsigned int RNRDY      :  1;  /**< Random Number Ready */
+      unsigned int STUCK      :  1;  /**< Sampled Data Stuck High or Low */
+      unsigned int reserved2  : 14;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RNG_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup DATA RNG Data Register (DATA) Register
+ *  RNG Data Register (DATA) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RNG_DATA_Struct
+ *! \brief  RNG Data Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_DATA_t__
+typedef struct _ADI_RNG_DATA_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Value of the CRC Accumulator */
+      unsigned int BUFF       : 24;  /**< Buffer for RNG Data */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_RNG_DATA_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_DATA_t__ */
+
+/*@}*/
+
+/** @defgroup OSCCNT Oscillator Count (OSCCNT) Register
+ *  Oscillator Count (OSCCNT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RNG_OSCCNT_Struct
+ *! \brief  Oscillator Count Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_OSCCNT_t__
+typedef struct _ADI_RNG_OSCCNT_t {
+  union {
+    struct {
+      unsigned int VALUE      : 28;  /**< Oscillator Count */
+      unsigned int reserved28 :  4;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_RNG_OSCCNT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_OSCCNT_t__ */
+
+/*@}*/
+
+/** @defgroup OSCDIFF Oscillator Difference (OSCDIFF) Register
+ *  Oscillator Difference (OSCDIFF) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RNG_OSCDIFF_Struct
+ *! \brief  Oscillator Difference Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_OSCDIFF_t__
+typedef struct _ADI_RNG_OSCDIFF_t {
+  union {
+    struct {
+      signed int DELTA      :  8;  /**< Oscillator Count Difference */
+    };
+    int8_t VALUE8;
+  };
+} ADI_RNG_OSCDIFF_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_OSCDIFF_t__ */
+
+/*@}*/
+
+/** @defgroup CFG Configuration Register (CFG) Register
+ *  Configuration Register (CFG) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_CRYPT_CFG_BLKEN
+ *! \brief  Enable Bit for Crypto Block (BLKEN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CRYPT_CFG_ENABLE  = 0,  /**< Enable Crypto Block  */
+  CRYPT_CFG_DISABLE = 1   /**< Disable Crypto Block */
+} ADI_CRYPT_CFG_BLKEN;
+
+
+/*  =========================================================================
+ *! \enum   ADI_CRYPT_CFG_INDMAEN
+ *! \brief  Enable DMA Channel Request for Input Buffer (INDMAEN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CRYPT_CFG_DMA_DISABLE_INBUF = 0,  /**< Disable DMA Requesting for Input Buffer */
+  CRYPT_CFG_DMA_ENABLE_INBUF  = 1   /**< Enable DMA Requesting for Input Buffer  */
+} ADI_CRYPT_CFG_INDMAEN;
+
+
+/*  =========================================================================
+ *! \enum   ADI_CRYPT_CFG_OUTDMAEN
+ *! \brief  Enable DMA Channel Request for Output Buffer (OUTDMAEN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CRYPT_CFG_DMA_DISABLE_OUTBUF = 0,  /**< Disable DMA Requesting for Output Buffer */
+  CRYPT_CFG_DMA_ENABLE_OUTBUF  = 1   /**< Enable DMA Requesting for Output Buffer  */
+} ADI_CRYPT_CFG_OUTDMAEN;
+
+
+/*  =========================================================================
+ *! \enum   ADI_CRYPT_CFG_AESKEYLEN
+ *! \brief  Select Key Length for AES Cipher (AESKEYLEN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CRYPT_CFG_AESKEYLEN128 = 0,  /**< Uses 128-bit long key */
+  CRYPT_CFG_AESKEYLEN256 = 2   /**< Uses 256-bit long key */
+} ADI_CRYPT_CFG_AESKEYLEN;
+
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_CFG_Struct
+ *! \brief  Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_CFG_t__
+typedef struct _ADI_CRYPT_CFG_t {
+  union {
+    struct {
+      unsigned int BLKEN      :  1;  /**< Enable Bit for Crypto Block */
+      unsigned int ENCR       :  1;  /**< Encrypt or Decrypt */
+      unsigned int INDMAEN    :  1;  /**< Enable DMA Channel Request for Input Buffer */
+      unsigned int OUTDMAEN   :  1;  /**< Enable DMA Channel Request for Output Buffer */
+      unsigned int INFLUSH    :  1;  /**< Input Buffer Flush */
+      unsigned int OUTFLUSH   :  1;  /**< Output Buffer Flush */
+      unsigned int AES_BYTESWAP :  1;  /**< Byte Swap 32 Bit AES Input Data */
+      unsigned int reserved7    :  1;
+      unsigned int AESKEYLEN    :  2;  /**< Select Key Length for AES Cipher */
+      unsigned int reserved10   :  6;
+      unsigned int ECBEN        :  1;  /**< Enable ECB Mode Operation */
+      unsigned int CTREN        :  1;  /**< Enable CTR Mode Operation */
+      unsigned int CBCEN        :  1;  /**< Enable CBC Mode Operation */
+      unsigned int CCMEN        :  1;  /**< Enable CCM/CCM* Mode Operation */
+      unsigned int CMACEN       :  1;  /**< Enable CMAC Mode Operation */
+      unsigned int reserved21   :  4;
+      unsigned int SHA256EN     :  1;  /**< Enable SHA-256 Operation */
+      unsigned int SHAINIT      :  1;  /**< Restarts SHA Computation */
+      unsigned int reserved27   :  1;
+      unsigned int RevID        :  4;  /**< Rev ID for Crypto */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_CFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_CFG_t__ */
+
+/*@}*/
+
+/** @defgroup DATALEN Payload Data Length (DATALEN) Register
+ *  Payload Data Length (DATALEN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_DATALEN_Struct
+ *! \brief  Payload Data Length Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_DATALEN_t__
+typedef struct _ADI_CRYPT_DATALEN_t {
+  union {
+    struct {
+      unsigned int VALUE      : 20;  /**< Length of Payload Data */
+      unsigned int reserved20 : 12;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_DATALEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_DATALEN_t__ */
+
+/*@}*/
+
+/** @defgroup PREFIXLEN Authentication Data Length (PREFIXLEN) Register
+ *  Authentication Data Length (PREFIXLEN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_PREFIXLEN_Struct
+ *! \brief  Authentication Data Length Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_PREFIXLEN_t__
+typedef struct _ADI_CRYPT_PREFIXLEN_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Length of Associated Data */
+      unsigned int reserved16 : 16;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_PREFIXLEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_PREFIXLEN_t__ */
+
+/*@}*/
+
+/** @defgroup INTEN Interrupt Enable Register (INTEN) Register
+ *  Interrupt Enable Register (INTEN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_INTEN_Struct
+ *! \brief  Interrupt Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_INTEN_t__
+typedef struct _ADI_CRYPT_INTEN_t {
+  union {
+    struct {
+      unsigned int INRDYEN    :  1;  /**< Enable Input Ready Interrupt */
+      unsigned int OUTRDYEN   :  1;  /**< Enables the Output Ready Interrupt */
+      unsigned int INOVREN    :  1;  /**< Enable Input Overflow Interrupt */
+      unsigned int reserved3  :  2;
+      unsigned int SHADONEN   :  1;  /**< Enable SHA_Done Interrupt */
+      unsigned int reserved6  : 26;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_INTEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_INTEN_t__ */
+
+/*@}*/
+
+/** @defgroup STAT Status Register (STAT) Register
+ *  Status Register (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_STAT_Struct
+ *! \brief  Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_STAT_t__
+typedef struct _ADI_CRYPT_STAT_t {
+  union {
+    struct {
+      unsigned int INRDY      :  1;  /**< Input Buffer Status */
+      unsigned int OUTRDY     :  1;  /**< Output Data Ready */
+      unsigned int INOVR      :  1;  /**< Overflow in the Input Buffer */
+      unsigned int reserved3  :  2;
+      unsigned int SHADONE    :  1;  /**< SHA Computation Complete */
+      unsigned int SHABUSY    :  1;  /**< SHA Busy. in Computation */
+      unsigned int INWORDS    :  3;  /**< Number of Words in the Input Buffer */
+      unsigned int OUTWORDS   :  3;  /**< Number of Words in the Output Buffer */
+      unsigned int reserved13 : 19;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup INBUF Input Buffer (INBUF) Register
+ *  Input Buffer (INBUF) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_INBUF_Struct
+ *! \brief  Input Buffer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_INBUF_t__
+typedef struct _ADI_CRYPT_INBUF_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Input Buffer */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_INBUF_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_INBUF_t__ */
+
+/*@}*/
+
+/** @defgroup OUTBUF Output Buffer (OUTBUF) Register
+ *  Output Buffer (OUTBUF) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_OUTBUF_Struct
+ *! \brief  Output Buffer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_OUTBUF_t__
+typedef struct _ADI_CRYPT_OUTBUF_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Output Buffer */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_OUTBUF_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_OUTBUF_t__ */
+
+/*@}*/
+
+/** @defgroup NONCE0 Nonce Bits [31:0] (NONCE0) Register
+ *  Nonce Bits [31:0] (NONCE0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_NONCE0_Struct
+ *! \brief  Nonce Bits [31:0] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE0_t__
+typedef struct _ADI_CRYPT_NONCE0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Word 0: Nonce Bits [31:0] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_NONCE0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE0_t__ */
+
+/*@}*/
+
+/** @defgroup NONCE1 Nonce Bits [63:32] (NONCE1) Register
+ *  Nonce Bits [63:32] (NONCE1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_NONCE1_Struct
+ *! \brief  Nonce Bits [63:32] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE1_t__
+typedef struct _ADI_CRYPT_NONCE1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Word 1: Nonce Bits [63:32] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_NONCE1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE1_t__ */
+
+/*@}*/
+
+/** @defgroup NONCE2 Nonce Bits [95:64] (NONCE2) Register
+ *  Nonce Bits [95:64] (NONCE2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_NONCE2_Struct
+ *! \brief  Nonce Bits [95:64] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE2_t__
+typedef struct _ADI_CRYPT_NONCE2_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Word 2: Nonce Bits [95:64] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_NONCE2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE2_t__ */
+
+/*@}*/
+
+/** @defgroup NONCE3 Nonce Bits [127:96] (NONCE3) Register
+ *  Nonce Bits [127:96] (NONCE3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_NONCE3_Struct
+ *! \brief  Nonce Bits [127:96] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE3_t__
+typedef struct _ADI_CRYPT_NONCE3_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Word 3: Nonce Bits [127:96] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_NONCE3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE3_t__ */
+
+/*@}*/
+
+/** @defgroup AESKEY0 AES Key Bits [31:0] (AESKEY0) Register
+ *  AES Key Bits [31:0] (AESKEY0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_AESKEY0_Struct
+ *! \brief  AES Key Bits [31:0] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY0_t__
+typedef struct _ADI_CRYPT_AESKEY0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Key: Bytes [3:0] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_AESKEY0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY0_t__ */
+
+/*@}*/
+
+/** @defgroup AESKEY1 AES Key Bits [63:32] (AESKEY1) Register
+ *  AES Key Bits [63:32] (AESKEY1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_AESKEY1_Struct
+ *! \brief  AES Key Bits [63:32] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY1_t__
+typedef struct _ADI_CRYPT_AESKEY1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Key: Bytes [7:4] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_AESKEY1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY1_t__ */
+
+/*@}*/
+
+/** @defgroup AESKEY2 AES Key Bits [95:64] (AESKEY2) Register
+ *  AES Key Bits [95:64] (AESKEY2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_AESKEY2_Struct
+ *! \brief  AES Key Bits [95:64] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY2_t__
+typedef struct _ADI_CRYPT_AESKEY2_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Key: Bytes [11:8] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_AESKEY2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY2_t__ */
+
+/*@}*/
+
+/** @defgroup AESKEY3 AES Key Bits [127:96] (AESKEY3) Register
+ *  AES Key Bits [127:96] (AESKEY3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_AESKEY3_Struct
+ *! \brief  AES Key Bits [127:96] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY3_t__
+typedef struct _ADI_CRYPT_AESKEY3_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Key: Bytes [15:12] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_AESKEY3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY3_t__ */
+
+/*@}*/
+
+/** @defgroup AESKEY4 AES Key Bits [159:128] (AESKEY4) Register
+ *  AES Key Bits [159:128] (AESKEY4) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_AESKEY4_Struct
+ *! \brief  AES Key Bits [159:128] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY4_t__
+typedef struct _ADI_CRYPT_AESKEY4_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Key: Bytes [19:16] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_AESKEY4_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY4_t__ */
+
+/*@}*/
+
+/** @defgroup AESKEY5 AES Key Bits [191:160] (AESKEY5) Register
+ *  AES Key Bits [191:160] (AESKEY5) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_AESKEY5_Struct
+ *! \brief  AES Key Bits [191:160] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY5_t__
+typedef struct _ADI_CRYPT_AESKEY5_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Key: Bytes [23:20] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_AESKEY5_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY5_t__ */
+
+/*@}*/
+
+/** @defgroup AESKEY6 AES Key Bits [223:192] (AESKEY6) Register
+ *  AES Key Bits [223:192] (AESKEY6) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_AESKEY6_Struct
+ *! \brief  AES Key Bits [223:192] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY6_t__
+typedef struct _ADI_CRYPT_AESKEY6_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Key: Bytes [27:24] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_AESKEY6_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY6_t__ */
+
+/*@}*/
+
+/** @defgroup AESKEY7 AES Key Bits [255:224] (AESKEY7) Register
+ *  AES Key Bits [255:224] (AESKEY7) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_AESKEY7_Struct
+ *! \brief  AES Key Bits [255:224] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY7_t__
+typedef struct _ADI_CRYPT_AESKEY7_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Key: Bytes [31:28] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_AESKEY7_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY7_t__ */
+
+/*@}*/
+
+/** @defgroup CNTRINIT Counter Initialization Vector (CNTRINIT) Register
+ *  Counter Initialization Vector (CNTRINIT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_CNTRINIT_Struct
+ *! \brief  Counter Initialization Vector Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_CNTRINIT_t__
+typedef struct _ADI_CRYPT_CNTRINIT_t {
+  union {
+    struct {
+      unsigned int VALUE      : 20;  /**< Counter Initialization Value */
+      unsigned int reserved20 : 12;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_CNTRINIT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_CNTRINIT_t__ */
+
+/*@}*/
+
+/** @defgroup SHAH0 SHA Bits [31:0] (SHAH0) Register
+ *  SHA Bits [31:0] (SHAH0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_SHAH0_Struct
+ *! \brief  SHA Bits [31:0] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH0_t__
+typedef struct _ADI_CRYPT_SHAH0_t {
+  union {
+    struct {
+      unsigned int SHAHASH0   : 32;  /**< Word 0: SHA Hash */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_SHAH0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH0_t__ */
+
+/*@}*/
+
+/** @defgroup SHAH1 SHA Bits [63:32] (SHAH1) Register
+ *  SHA Bits [63:32] (SHAH1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_SHAH1_Struct
+ *! \brief  SHA Bits [63:32] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH1_t__
+typedef struct _ADI_CRYPT_SHAH1_t {
+  union {
+    struct {
+      unsigned int SHAHASH1   : 32;  /**< Word 1: SHA Hash */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_SHAH1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH1_t__ */
+
+/*@}*/
+
+/** @defgroup SHAH2 SHA Bits [95:64] (SHAH2) Register
+ *  SHA Bits [95:64] (SHAH2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_SHAH2_Struct
+ *! \brief  SHA Bits [95:64] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH2_t__
+typedef struct _ADI_CRYPT_SHAH2_t {
+  union {
+    struct {
+      unsigned int SHAHASH2   : 32;  /**< Word 2: SHA Hash */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_SHAH2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH2_t__ */
+
+/*@}*/
+
+/** @defgroup SHAH3 SHA Bits [127:96] (SHAH3) Register
+ *  SHA Bits [127:96] (SHAH3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_SHAH3_Struct
+ *! \brief  SHA Bits [127:96] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH3_t__
+typedef struct _ADI_CRYPT_SHAH3_t {
+  union {
+    struct {
+      unsigned int SHAHASH3   : 32;  /**< Word 3: SHA Hash */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_SHAH3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH3_t__ */
+
+/*@}*/
+
+/** @defgroup SHAH4 SHA Bits [159:128] (SHAH4) Register
+ *  SHA Bits [159:128] (SHAH4) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_SHAH4_Struct
+ *! \brief  SHA Bits [159:128] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH4_t__
+typedef struct _ADI_CRYPT_SHAH4_t {
+  union {
+    struct {
+      unsigned int SHAHASH4   : 32;  /**< Word 4: SHA Hash */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_SHAH4_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH4_t__ */
+
+/*@}*/
+
+/** @defgroup SHAH5 SHA Bits [191:160] (SHAH5) Register
+ *  SHA Bits [191:160] (SHAH5) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_SHAH5_Struct
+ *! \brief  SHA Bits [191:160] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH5_t__
+typedef struct _ADI_CRYPT_SHAH5_t {
+  union {
+    struct {
+      unsigned int SHAHASH5   : 32;  /**< Word 5: SHA Hash */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_SHAH5_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH5_t__ */
+
+/*@}*/
+
+/** @defgroup SHAH6 SHA Bits [223:192] (SHAH6) Register
+ *  SHA Bits [223:192] (SHAH6) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_SHAH6_Struct
+ *! \brief  SHA Bits [223:192] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH6_t__
+typedef struct _ADI_CRYPT_SHAH6_t {
+  union {
+    struct {
+      unsigned int SHAHASH6   : 32;  /**< Word 6: SHA Hash */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_SHAH6_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH6_t__ */
+
+/*@}*/
+
+/** @defgroup SHAH7 SHA Bits [255:224] (SHAH7) Register
+ *  SHA Bits [255:224] (SHAH7) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_SHAH7_Struct
+ *! \brief  SHA Bits [255:224] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH7_t__
+typedef struct _ADI_CRYPT_SHAH7_t {
+  union {
+    struct {
+      unsigned int SHAHASH7   : 32;  /**< Word 7: SHA Hash */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_SHAH7_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH7_t__ */
+
+/*@}*/
+
+/** @defgroup SHA_LAST_WORD SHA Last Word and Valid Bits Information (SHA_LAST_WORD) Register
+ *  SHA Last Word and Valid Bits Information (SHA_LAST_WORD) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_SHA_LAST_WORD_Struct
+ *! \brief  SHA Last Word and Valid Bits Information Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHA_LAST_WORD_t__
+typedef struct _ADI_CRYPT_SHA_LAST_WORD_t {
+  union {
+    struct {
+      unsigned int O_Last_Word :  1;  /**< Last SHA Input Word */
+      unsigned int O_Bits_Valid :  5;  /**< Bits Valid in SHA Last Word Input */
+      unsigned int reserved6    : 26;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_SHA_LAST_WORD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHA_LAST_WORD_t__ */
+
+/*@}*/
+
+/** @defgroup CCM_NUM_VALID_BYTES NUM_VALID_BYTES (CCM_NUM_VALID_BYTES) Register
+ *  NUM_VALID_BYTES (CCM_NUM_VALID_BYTES) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_CCM_NUM_VALID_BYTES_Struct
+ *! \brief  NUM_VALID_BYTES Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_CCM_NUM_VALID_BYTES_t__
+typedef struct _ADI_CRYPT_CCM_NUM_VALID_BYTES_t {
+  union {
+    struct {
+      unsigned int NUM_VALID_BYTES :  4;  /**< Number of Valid Bytes in CCM Last Data */
+      unsigned int reserved4       : 28;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_CCM_NUM_VALID_BYTES_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_CCM_NUM_VALID_BYTES_t__ */
+
+/*@}*/
+
+/** @defgroup IEN Power Supply Monitor Interrupt Enable (IEN) Register
+ *  Power Supply Monitor Interrupt Enable (IEN) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_PMG_IEN_RANGEBAT
+ *! \brief  Battery Monitor Range (RANGEBAT) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  PMG_IEN_REGION1 = 0,  /**< Configure to generate interrupt if VBAT > 2.75 V               */
+  PMG_IEN_REGION2 = 1,  /**< Configure to generate interrupt if VBAT between 2.75 V - 1.6 V */
+  PMG_IEN_REGION3 = 2,  /**< Configure to generate interrupt if VBAT between 2.3 V - 1.6 V  */
+  PMG_IEN_NA      = 3   /**< N/A                                                            */
+} ADI_PMG_IEN_RANGEBAT;
+
+
+/* ==========================================================================
+ *! \struct ADI_PMG_IEN_Struct
+ *! \brief  Power Supply Monitor Interrupt Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_IEN_t__
+typedef struct _ADI_PMG_IEN_t {
+  union {
+    struct {
+      unsigned int VBAT       :  1;  /**< Enable Interrupt for VBAT */
+      unsigned int VREGUNDR   :  1;  /**< Enable Interrupt When VREG Undervoltage: Below 1V */
+      unsigned int VREGOVR    :  1;  /**< Enable Interrupt When VREG Overvoltage: Above 1.32V */
+      unsigned int reserved3  :  5;
+      unsigned int RANGEBAT   :  2;  /**< Battery Monitor Range */
+      unsigned int IENBAT     :  1;  /**< Interrupt Enable for VBAT Range */
+      unsigned int reserved11 : 21;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_IEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_IEN_t__ */
+
+/*@}*/
+
+/** @defgroup PSM_STAT Power Supply Monitor Status (PSM_STAT) Register
+ *  Power Supply Monitor Status (PSM_STAT) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_PMG_PSM_STAT_RORANGE1
+ *! \brief  VBAT Range1 (> 2.75v) (RORANGE1) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  PMG_PSM_STAT_BATSTAT1 = 0,  /**< VBAT not in the range specified */
+  PMG_PSM_STAT_BATSTAT0 = 1   /**< VBAT in the range specified     */
+} ADI_PMG_PSM_STAT_RORANGE1;
+
+
+/* ==========================================================================
+ *! \struct ADI_PMG_PSM_STAT_Struct
+ *! \brief  Power Supply Monitor Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_PSM_STAT_t__
+typedef struct _ADI_PMG_PSM_STAT_t {
+  union {
+    struct {
+      unsigned int VBATUNDR   :  1;  /**< Status Bit Indicating an Alarm That Battery is Below 1.8V */
+      unsigned int VREGUNDR   :  1;  /**< Status Bit for Alarm Indicating VREG is Below 1V */
+      unsigned int VREGOVR    :  1;  /**< Status Bit for Alarm Indicating Overvoltage for VREG */
+      unsigned int reserved3  :  4;
+      unsigned int WICENACK   :  1;  /**< WIC Enable Acknowledge from Cortex */
+      unsigned int RANGE1     :  1;  /**< VBAT Range1 (> 2.75v) */
+      unsigned int RANGE2     :  1;  /**< VBAT Range2 (2.75v - 2.3v) */
+      unsigned int RANGE3     :  1;  /**< VBAT Range3 (2.3v - 1.6v) */
+      unsigned int reserved11 :  2;
+      unsigned int RORANGE1   :  1;  /**< VBAT Range1 (> 2.75v) */
+      unsigned int RORANGE2   :  1;  /**< VBAT Range2 (2.75v - 2.3v) */
+      unsigned int RORANGE3   :  1;  /**< VBAT Range3 (2.3v - 1.6v) */
+      unsigned int reserved16 : 16;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_PSM_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_PSM_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup PWRMOD Power Mode Register (PWRMOD) Register
+ *  Power Mode Register (PWRMOD) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_PMG_PWRMOD_MODE
+ *! \brief  Power Mode Bits (MODE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  PMG_PWRMOD_FLEXI     = 0,  /**< Flexi Mode     */
+  PMG_PWRMOD_HIBERNATE = 2,  /**< Hibernate Mode */
+  PMG_PWRMOD_SHUTDOWN  = 3   /**< Shutdown Mode  */
+} ADI_PMG_PWRMOD_MODE;
+
+
+/*  =========================================================================
+ *! \enum   ADI_PMG_PWRMOD_MONVBATN
+ *! \brief  Monitor VBAT During Hibernate Mode. Monitors VBAT by Default (MONVBATN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  PMG_PWRMOD_VBAT_MONEN  = 0,  /**< VBAT monitor enabled in PMG block.  */
+  PMG_PWRMOD_VBAT_MONDIS = 1   /**< VBAT monitor disabled in PMG block. */
+} ADI_PMG_PWRMOD_MONVBATN;
+
+
+/* ==========================================================================
+ *! \struct ADI_PMG_PWRMOD_Struct
+ *! \brief  Power Mode Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_PWRMOD_t__
+typedef struct _ADI_PMG_PWRMOD_t {
+  union {
+    struct {
+      unsigned int MODE       :  2;  /**< Power Mode Bits */
+      unsigned int reserved2  :  1;
+      unsigned int MONVBATN   :  1;  /**< Monitor VBAT During Hibernate Mode. Monitors VBAT by Default */
+      unsigned int reserved4  : 28;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_PWRMOD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_PWRMOD_t__ */
+
+/*@}*/
+
+/** @defgroup PWRKEY Key Protection for PWRMOD and SRAMRET (PWRKEY) Register
+ *  Key Protection for PWRMOD and SRAMRET (PWRKEY) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PMG_PWRKEY_Struct
+ *! \brief  Key Protection for PWRMOD and SRAMRET Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_PWRKEY_t__
+typedef struct _ADI_PMG_PWRKEY_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Power Control Key Register */
+      unsigned int reserved16 : 16;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_PWRKEY_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_PWRKEY_t__ */
+
+/*@}*/
+
+/** @defgroup SHDN_STAT Shutdown Status Register (SHDN_STAT) Register
+ *  Shutdown Status Register (SHDN_STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PMG_SHDN_STAT_Struct
+ *! \brief  Shutdown Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_SHDN_STAT_t__
+typedef struct _ADI_PMG_SHDN_STAT_t {
+  union {
+    struct {
+      unsigned int EXTINT0    :  1;  /**< Wakeup by Interrupt from External Interrupt 0 */
+      unsigned int EXTINT1    :  1;  /**< Wakeup by Interrupt from External Interrupt 1 */
+      unsigned int EXTINT2    :  1;  /**< Wakeup by Interrupt from External Interrupt 2 */
+      unsigned int RTC        :  1;  /**< Wakeup by Interrupt from RTC */
+      unsigned int reserved4  : 28;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_SHDN_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_SHDN_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup SRAMRET Control for Retention SRAM in Hibernate Mode (SRAMRET) Register
+ *  Control for Retention SRAM in Hibernate Mode (SRAMRET) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PMG_SRAMRET_Struct
+ *! \brief  Control for Retention SRAM in Hibernate Mode Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_SRAMRET_t__
+typedef struct _ADI_PMG_SRAMRET_t {
+  union {
+    struct {
+      unsigned int BNK1EN     :  1;  /**< Enable Retention Bank 1 (8kB) */
+      unsigned int BNK2EN     :  1;  /**< Enable Retention Bank 2 (16kB) */
+      unsigned int reserved2  : 30;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_SRAMRET_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_SRAMRET_t__ */
+
+/*@}*/
+
+/** @defgroup RST_STAT Reset Status (RST_STAT) Register
+ *  Reset Status (RST_STAT) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_PMG_RST_STAT_PORSRC
+ *! \brief  Power-on-Reset Source (PORSRC) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  PMG_RST_STAT_FAILSAFE_HV = 0,  /**< POR triggered because VBAT drops below Fail Safe */
+  PMG_RST_STAT_RST_VBAT    = 1,  /**< POR trigger because VBAT supply (VBAT < 1.7 V)   */
+  PMG_RST_STAT_RST_VREG    = 2,  /**< POR triggered because VDD supply (VDD < 1.08 V)  */
+  PMG_RST_STAT_FAILSAFE_LV = 3   /**< POR triggered because VREG drops below Fail Safe */
+} ADI_PMG_RST_STAT_PORSRC;
+
+
+/* ==========================================================================
+ *! \struct ADI_PMG_RST_STAT_Struct
+ *! \brief  Reset Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_RST_STAT_t__
+typedef struct _ADI_PMG_RST_STAT_t {
+  union {
+    struct {
+      unsigned int POR        :  1;  /**< Power-on-Reset */
+      unsigned int EXTRST     :  1;  /**< External Reset */
+      unsigned int WDRST      :  1;  /**< Watchdog Time-out Reset */
+      unsigned int SWRST      :  1;  /**< Software Reset */
+      unsigned int PORSRC     :  2;  /**< Power-on-Reset Source */
+      unsigned int reserved6  : 26;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_RST_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_RST_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup CTL1 HP Buck Control (CTL1) Register
+ *  HP Buck Control (CTL1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PMG_CTL1_Struct
+ *! \brief  HP Buck Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_CTL1_t__
+typedef struct _ADI_PMG_CTL1_t {
+  union {
+    struct {
+      unsigned int HPBUCKEN   :  1;  /**< Enable HP Buck */
+      unsigned int reserved1  : 31;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_CTL1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_CTL1_t__ */
+
+/*@}*/
+
+/** @defgroup CFG0 External Interrupt Configuration (CFG0) Register
+ *  External Interrupt Configuration (CFG0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_XINT_CFG0_Struct
+ *! \brief  External Interrupt Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_CFG0_t__
+typedef struct _ADI_XINT_CFG0_t {
+  union {
+    struct {
+      unsigned int IRQ0MDE    :  3;  /**< External Interrupt 0 Mode Registers */
+      unsigned int IRQ0EN     :  1;  /**< External Interrupt 0 Enable Bit */
+      unsigned int IRQ1MDE    :  3;  /**< External Interrupt 1 Mode Registers */
+      unsigned int IRQ1EN     :  1;  /**< External Interrupt 1 Enable Bit */
+      unsigned int IRQ2MDE    :  3;  /**< External Interrupt 2 Mode Registers */
+      unsigned int IRQ2EN     :  1;  /**< External Interrupt 2 Enable Bit */
+      unsigned int IRQ3MDE    :  3;  /**< External Interrupt 3 Mode Registers */
+      unsigned int IRQ3EN     :  1;  /**< External Interrupt 3 Enable Bit */
+      unsigned int reserved16 :  4;
+      unsigned int UART_RX_EN :  1;  /**< External Interrupt Enable Bit */
+      unsigned int UART_RX_MDE :  3;  /**< External Interrupt Using UART_RX Wakeup Mode Registers */
+      unsigned int reserved24  :  8;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_XINT_CFG0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_CFG0_t__ */
+
+/*@}*/
+
+/** @defgroup EXT_STAT External Wakeup Interrupt Status (EXT_STAT) Register
+ *  External Wakeup Interrupt Status (EXT_STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_XINT_EXT_STAT_Struct
+ *! \brief  External Wakeup Interrupt Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_EXT_STAT_t__
+typedef struct _ADI_XINT_EXT_STAT_t {
+  union {
+    struct {
+      unsigned int STAT_EXTINT0 :  1;  /**< Interrupt Status Bit for External Interrupt 0 */
+      unsigned int STAT_EXTINT1 :  1;  /**< Interrupt Status Bit for External Interrupt 1 */
+      unsigned int STAT_EXTINT2 :  1;  /**< Interrupt Status Bit for External Interrupt 2 */
+      unsigned int STAT_EXTINT3 :  1;  /**< Interrupt Status Bit for External Interrupt 3 */
+      unsigned int reserved4        :  1;
+      unsigned int STAT_UART_RXWKUP :  1;  /**< Interrupt Status Bit for UART RX Wakeup Interrupt */
+      unsigned int reserved6        : 26;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_XINT_EXT_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_EXT_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup CLR External Interrupt Clear (CLR) Register
+ *  External Interrupt Clear (CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_XINT_CLR_Struct
+ *! \brief  External Interrupt Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_CLR_t__
+typedef struct _ADI_XINT_CLR_t {
+  union {
+    struct {
+      unsigned int IRQ0       :  1;  /**< External Interrupt 0 */
+      unsigned int IRQ1       :  1;  /**< External Interrupt 1 */
+      unsigned int IRQ2       :  1;  /**< External Interrupt 2 */
+      unsigned int IRQ3       :  1;  /**< External Interrupt 3 */
+      unsigned int reserved4   :  1;
+      unsigned int UART_RX_CLR :  1;  /**< External Interrupt Clear for UART_RX Wakeup Interrupt */
+      unsigned int reserved6   : 26;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_XINT_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup NMICLR Non-Maskable Interrupt Clear (NMICLR) Register
+ *  Non-Maskable Interrupt Clear (NMICLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_XINT_NMICLR_Struct
+ *! \brief  Non-Maskable Interrupt Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_NMICLR_t__
+typedef struct _ADI_XINT_NMICLR_t {
+  union {
+    struct {
+      unsigned int CLR        :  1;  /**< NMI Clear */
+      unsigned int reserved1  : 31;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_XINT_NMICLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_NMICLR_t__ */
+
+/*@}*/
+
+/** @defgroup KEY Key Protection for CLKG_OSC_CTL (KEY) Register
+ *  Key Protection for CLKG_OSC_CTL (KEY) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CLKG_OSC_KEY_Struct
+ *! \brief  Key Protection for CLKG_OSC_CTL Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_KEY_t__
+typedef struct _ADI_CLKG_OSC_KEY_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Oscillator K */
+      unsigned int reserved16 : 16;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CLKG_OSC_KEY_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_KEY_t__ */
+
+/*@}*/
+
+/** @defgroup CTL Oscillator Control (CTL) Register
+ *  Oscillator Control (CTL) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_CLKG_OSC_CTL_LFXTAL_MON_FAIL_STAT
+ *! \brief  LFXTAL Not Stable (LFXTAL_MON_FAIL_STAT) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CLKG_OSC_CTL_LFXTAL_RUNNING    = 0,  /**< LFXTAL is running fine */
+  CLKG_OSC_CTL_LFXTAL_NOTRUNNING = 1   /**< LFXTAL is not running  */
+} ADI_CLKG_OSC_CTL_LFXTAL_MON_FAIL_STAT;
+
+
+/* ==========================================================================
+ *! \struct ADI_CLKG_OSC_CTL_Struct
+ *! \brief  Oscillator Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_CTL_t__
+typedef struct _ADI_CLKG_OSC_CTL_t {
+  union {
+    struct {
+      unsigned int LFCLKMUX   :  1;  /**< 32kHz Clock Select Mux */
+      unsigned int HFOSCEN    :  1;  /**< High Frequency Internal Oscillator Enable */
+      unsigned int LFXTALEN   :  1;  /**< Low Frequency Crystal Oscillator Enable */
+      unsigned int HFXTALEN   :  1;  /**< High Frequency Crystal Oscillator Enable */
+      unsigned int LFXTAL_BYPASS :  1;  /**< Low Frequency Crystal Oscillator Bypass */
+      unsigned int LFXTAL_MON_EN :  1;  /**< LFXTAL Clock Monitor and Clock Fail Interrupt Enable */
+      unsigned int reserved6     :  2;
+      unsigned int LFOSCOK       :  1;  /**< Status of LFOSC Oscillator */
+      unsigned int HFOSCOK       :  1;  /**< Status of HFOSC */
+      unsigned int LFXTALOK      :  1;  /**< Status of LFXTAL Oscillator */
+      unsigned int HFXTALOK      :  1;  /**< Status of HFXTAL Oscillator */
+      unsigned int reserved12           : 19;
+      unsigned int LFXTAL_MON_FAIL_STAT :  1;  /**< LFXTAL Not Stable */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CLKG_OSC_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup SRAM_CTL Control for SRAM Parity and Instruction SRAM (SRAM_CTL) Register
+ *  Control for SRAM Parity and Instruction SRAM (SRAM_CTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PMG_TST_SRAM_CTL_Struct
+ *! \brief  Control for SRAM Parity and Instruction SRAM Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_SRAM_CTL_t__
+typedef struct _ADI_PMG_TST_SRAM_CTL_t {
+  union {
+    struct {
+      unsigned int BNK0EN     :  1;  /**< Enable Initialization of SRAM Bank 0 */
+      unsigned int BNK1EN     :  1;  /**< Enable Initialization of SRAM Bank 1 */
+      unsigned int BNK2EN     :  1;  /**< Enable Initialization of SRAM Bank 2 */
+      unsigned int BNK3EN     :  1;  /**< Enable Initialization of SRAM Bank 3 */
+      unsigned int BNK4EN     :  1;  /**< Enable Initialization of SRAM Bank 4 */
+      unsigned int BNK5EN     :  1;  /**< Enable Initialization of SRAM Bank 5 */
+      unsigned int reserved6  :  7;
+      unsigned int STARTINIT  :  1;  /**< Write 1 to Trigger Initialization */
+      unsigned int AUTOINIT   :  1;  /**< Automatic Initialization on Wakeup from Hibernate Mode */
+      unsigned int ABTINIT    :  1;  /**< Abort Current Initialization. Self-cleared */
+      unsigned int PENBNK0    :  1;  /**< Enable Parity Check SRAM Bank 0 */
+      unsigned int PENBNK1    :  1;  /**< Enable Parity Check SRAM Bank 1 */
+      unsigned int PENBNK2    :  1;  /**< Enable Parity Check SRAM Bank 2 */
+      unsigned int PENBNK3    :  1;  /**< Enable Parity Check SRAM Bank 3 */
+      unsigned int PENBNK4    :  1;  /**< Enable Parity Check SRAM Bank 4 */
+      unsigned int PENBNK5    :  1;  /**< Enable Parity Check SRAM Bank 5 */
+      unsigned int reserved22 :  9;
+      unsigned int INSTREN    :  1;  /**< Enables Instruction SRAM */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_TST_SRAM_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_SRAM_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup SRAM_INITSTAT Initialization Status Register (SRAM_INITSTAT) Register
+ *  Initialization Status Register (SRAM_INITSTAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PMG_TST_SRAM_INITSTAT_Struct
+ *! \brief  Initialization Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_SRAM_INITSTAT_t__
+typedef struct _ADI_PMG_TST_SRAM_INITSTAT_t {
+  union {
+    struct {
+      unsigned int BNK0       :  1;  /**< Initialization Done of SRAM Bank 0 */
+      unsigned int BNK1       :  1;  /**< Initialization Done of SRAM Bank 1 */
+      unsigned int BNK2       :  1;  /**< Initialization Done of SRAM Bank 2 */
+      unsigned int BNK3       :  1;  /**< Initialization Done of SRAM Bank 3 */
+      unsigned int BNK4       :  1;  /**< Initialization Done of SRAM Bank 4 */
+      unsigned int BNK5       :  1;  /**< Initialization Done of SRAM Bank 5 */
+      unsigned int reserved6  : 26;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_TST_SRAM_INITSTAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_SRAM_INITSTAT_t__ */
+
+/*@}*/
+
+/** @defgroup CLR_LATCH_GPIOS Clear GPIO After Shutdown Mode (CLR_LATCH_GPIOS) Register
+ *  Clear GPIO After Shutdown Mode (CLR_LATCH_GPIOS) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PMG_TST_CLR_LATCH_GPIOS_Struct
+ *! \brief  Clear GPIO After Shutdown Mode Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_CLR_LATCH_GPIOS_t__
+typedef struct _ADI_PMG_TST_CLR_LATCH_GPIOS_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Clear GPIOs Latches */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_PMG_TST_CLR_LATCH_GPIOS_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_CLR_LATCH_GPIOS_t__ */
+
+/*@}*/
+
+/** @defgroup SCRPAD_IMG Scratch Pad Image (SCRPAD_IMG) Register
+ *  Scratch Pad Image (SCRPAD_IMG) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PMG_TST_SCRPAD_IMG_Struct
+ *! \brief  Scratch Pad Image Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_SCRPAD_IMG_t__
+typedef struct _ADI_PMG_TST_SCRPAD_IMG_t {
+  union {
+    struct {
+      unsigned int DATA       : 32;  /**< Scratch Image */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_TST_SCRPAD_IMG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_SCRPAD_IMG_t__ */
+
+/*@}*/
+
+/** @defgroup SCRPAD_3V_RD Scratch Pad Saved in Battery Domain (SCRPAD_3V_RD) Register
+ *  Scratch Pad Saved in Battery Domain (SCRPAD_3V_RD) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PMG_TST_SCRPAD_3V_RD_Struct
+ *! \brief  Scratch Pad Saved in Battery Domain Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_SCRPAD_3V_RD_t__
+typedef struct _ADI_PMG_TST_SCRPAD_3V_RD_t {
+  union {
+    struct {
+      unsigned int DATA       : 32;  /**< Reading the Scratch Pad Stored in Shutdown Mode */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_TST_SCRPAD_3V_RD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_SCRPAD_3V_RD_t__ */
+
+/*@}*/
+
+/** @defgroup CTL0 Miscellaneous Clock Settings (CTL0) Register
+ *  Miscellaneous Clock Settings (CTL0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CLKG_CLK_CTL0_Struct
+ *! \brief  Miscellaneous Clock Settings Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL0_t__
+typedef struct _ADI_CLKG_CLK_CTL0_t {
+  union {
+    struct {
+      unsigned int CLKMUX     :  2;  /**< Clock Mux Select */
+      unsigned int reserved2  :  6;
+      unsigned int RCLKMUX    :  2;  /**< Flash Reference Clock and HP Buck Source Mux */
+      unsigned int reserved10 :  1;
+      unsigned int SPLLIPSEL  :  1;  /**< SPLL Source Select Mux */
+      unsigned int reserved12 :  2;
+      unsigned int LFXTALIE   :  1;  /**< Low Frequency Crystal Interrupt Enable */
+      unsigned int HFXTALIE   :  1;  /**< High Frequency Crystal Interrupt Enable */
+      unsigned int reserved16 : 16;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CLKG_CLK_CTL0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL0_t__ */
+
+/*@}*/
+
+/** @defgroup CTL1 Clock Dividers (CTL1) Register
+ *  Clock Dividers (CTL1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CLKG_CLK_CTL1_Struct
+ *! \brief  Clock Dividers Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL1_t__
+typedef struct _ADI_CLKG_CLK_CTL1_t {
+  union {
+    struct {
+      unsigned int HCLKDIVCNT :  6;  /**< HCLK Divide Count */
+      unsigned int reserved6  :  2;
+      unsigned int PCLKDIVCNT :  6;  /**< PCLK Divide Count */
+      unsigned int reserved14 :  2;
+      unsigned int ACLKDIVCNT :  8;  /**< ACLK Divide Count */
+      unsigned int reserved24 :  8;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CLKG_CLK_CTL1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL1_t__ */
+
+/*@}*/
+
+/** @defgroup CTL3 System PLL (CTL3) Register
+ *  System PLL (CTL3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CLKG_CLK_CTL3_Struct
+ *! \brief  System PLL Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL3_t__
+typedef struct _ADI_CLKG_CLK_CTL3_t {
+  union {
+    struct {
+      unsigned int SPLLNSEL   :  5;  /**< System PLL N Multiplier */
+      unsigned int reserved5  :  3;
+      unsigned int SPLLDIV2   :  1;  /**< System PLL Division by 2 */
+      unsigned int SPLLEN     :  1;  /**< System PLL Enable */
+      unsigned int SPLLIE     :  1;  /**< System PLL Interrupt Enable */
+      unsigned int SPLLMSEL   :  4;  /**< System PLL M Divider */
+      unsigned int reserved15 :  1;
+      unsigned int SPLLMUL2   :  1;  /**< System PLL Multiply by 2 */
+      unsigned int reserved17 : 15;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CLKG_CLK_CTL3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL3_t__ */
+
+/*@}*/
+
+/** @defgroup CTL5 User Clock Gating Control (CTL5) Register
+ *  User Clock Gating Control (CTL5) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_CLKG_CLK_CTL5_PERCLKOFF
+ *! \brief  Disables All Clocks Connected to All Peripherals (PERCLKOFF) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CLKG_CLK_CTL5_PERIPH_CLK_ACT = 0,  /**< Clocks to all peripherals are active    */
+  CLKG_CLK_CTL5_PERIPH_CLK_OFF = 1   /**< Clocks to all peripherals are gated off */
+} ADI_CLKG_CLK_CTL5_PERCLKOFF;
+
+
+/* ==========================================================================
+ *! \struct ADI_CLKG_CLK_CTL5_Struct
+ *! \brief  User Clock Gating Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL5_t__
+typedef struct _ADI_CLKG_CLK_CTL5_t {
+  union {
+    struct {
+      unsigned int GPTCLK0OFF :  1;  /**< Timer 0 User Control */
+      unsigned int GPTCLK1OFF :  1;  /**< Timer 1 User Control */
+      unsigned int GPTCLK2OFF :  1;  /**< Timer 2 User Control */
+      unsigned int UCLKI2COFF :  1;  /**< I2C Clock User Control */
+      unsigned int GPIOCLKOFF :  1;  /**< GPIO Clock Control */
+      unsigned int PERCLKOFF  :  1;  /**< Disables All Clocks Connected to All Peripherals */
+      unsigned int reserved6  : 26;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CLKG_CLK_CTL5_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL5_t__ */
+
+/*@}*/
+
+/** @defgroup STAT0 Clocking Status (STAT0) Register
+ *  Clocking Status (STAT0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CLKG_CLK_STAT0_Struct
+ *! \brief  Clocking Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_STAT0_t__
+typedef struct _ADI_CLKG_CLK_STAT0_t {
+  union {
+    struct {
+      unsigned int SPLL       :  1;  /**< System PLL Status */
+      unsigned int SPLLLK     :  1;  /**< System PLL Lock */
+      unsigned int SPLLUNLK   :  1;  /**< System PLL Unlock */
+      unsigned int reserved3  :  5;
+      unsigned int LFXTAL     :  1;  /**< LF Crystal Status */
+      unsigned int LFXTALOK   :  1;  /**< LF Crystal Stable */
+      unsigned int LFXTALNOK  :  1;  /**< LF Crystal Not Stable */
+      unsigned int reserved11 :  1;
+      unsigned int HFXTAL     :  1;  /**< HF Crystal Status */
+      unsigned int HFXTALOK   :  1;  /**< HF Crystal Stable */
+      unsigned int HFXTALNOK  :  1;  /**< HF Crystal Not Stable */
+      unsigned int reserved15 : 17;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CLKG_CLK_STAT0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_STAT0_t__ */
+
+/*@}*/
+
+/** @defgroup ARBIT0 Arbitration Priority Configuration for FLASH and SRAM0 (ARBIT0) Register
+ *  Arbitration Priority Configuration for FLASH and SRAM0 (ARBIT0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_BUSM_ARBIT0_Struct
+ *! \brief  Arbitration Priority Configuration for FLASH and SRAM0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT0_t__
+typedef struct _ADI_BUSM_ARBIT0_t {
+  union {
+    struct {
+      unsigned int FLSH_DCODE :  2;  /**< Flash priority for DCODE */
+      unsigned int FLSH_SBUS  :  2;  /**< Flash priority for SBUS */
+      unsigned int FLSH_DMA0  :  2;  /**< Flash priority for DMA0 */
+      unsigned int reserved6   : 10;
+      unsigned int SRAM0_DCODE :  2;  /**< SRAM0 priority for Dcode */
+      unsigned int SRAM0_SBUS  :  2;  /**< SRAM0 priority for SBUS */
+      unsigned int SRAM0_DMA0  :  2;  /**< SRAM0 priority for DMA0 */
+      unsigned int reserved22  : 10;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_BUSM_ARBIT0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT0_t__ */
+
+/*@}*/
+
+/** @defgroup ARBIT1 Arbitration Priority Configuration for SRAM1 and SIP (ARBIT1) Register
+ *  Arbitration Priority Configuration for SRAM1 and SIP (ARBIT1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_BUSM_ARBIT1_Struct
+ *! \brief  Arbitration Priority Configuration for SRAM1 and SIP Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT1_t__
+typedef struct _ADI_BUSM_ARBIT1_t {
+  union {
+    struct {
+      unsigned int SRAM1_DCODE :  2;  /**< SRAM1 priority for Dcode */
+      unsigned int SRAM1_SBUS  :  2;  /**< SRAM1 priority for SBUS */
+      unsigned int SRAM1_DMA0  :  2;  /**< SRAM1 priority for DMA0 */
+      unsigned int reserved6   : 10;
+      unsigned int SIP_DCODE   :  2;  /**< SIP priority for DCODE */
+      unsigned int SIP_SBUS    :  2;  /**< SIP priority for SBUS */
+      unsigned int SIP_DMA0    :  2;  /**< SIP priority for DMA0 */
+      unsigned int reserved22  : 10;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_BUSM_ARBIT1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT1_t__ */
+
+/*@}*/
+
+/** @defgroup ARBIT2 Arbitration Priority Configuration for APB32 and APB16 (ARBIT2) Register
+ *  Arbitration Priority Configuration for APB32 and APB16 (ARBIT2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_BUSM_ARBIT2_Struct
+ *! \brief  Arbitration Priority Configuration for APB32 and APB16 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT2_t__
+typedef struct _ADI_BUSM_ARBIT2_t {
+  union {
+    struct {
+      unsigned int APB32_DCODE :  2;  /**< APB32 priority for DCODE */
+      unsigned int APB32_SBUS  :  2;  /**< APB32 priority for SBUS */
+      unsigned int APB32_DMA0  :  2;  /**< APB32 priority for DMA0 */
+      unsigned int reserved6   : 10;
+      unsigned int APB16_DCODE :  2;  /**< APB16 priority for DCODE */
+      unsigned int APB16_SBUS  :  2;  /**< APB16 priority for SBUS */
+      unsigned int APB16_DMA0  :  2;  /**< APB16 priority for DMA0 */
+      unsigned int reserved22  : 10;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_BUSM_ARBIT2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT2_t__ */
+
+/*@}*/
+
+/** @defgroup ARBIT3 Arbitration Priority Configuration for APB16 priority for core and for DMA1 (ARBIT3) Register
+ *  Arbitration Priority Configuration for APB16 priority for core and for DMA1 (ARBIT3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_BUSM_ARBIT3_Struct
+ *! \brief  Arbitration Priority Configuration for APB16 priority for core and for DMA1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT3_t__
+typedef struct _ADI_BUSM_ARBIT3_t {
+  union {
+    struct {
+      unsigned int APB16_CORE :  1;  /**< APB16 priority for CORE */
+      unsigned int APB16_DMA1 :  1;  /**< APB16 priority for DMA1 */
+      unsigned int reserved2       : 14;
+      unsigned int APB16_4DMA_CORE :  1;  /**< APB16 for dma priority for CORE */
+      unsigned int APB16_4DMA_DMA1 :  1;  /**< APB16 for dma priority for DMA1 */
+      unsigned int reserved18      : 14;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_BUSM_ARBIT3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT3_t__ */
+
+/*@}*/
+
+/** @defgroup RST_ISR_STARTADDR Reset ISR Start Address (RST_ISR_STARTADDR) Register
+ *  Reset ISR Start Address (RST_ISR_STARTADDR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PTI_RST_ISR_STARTADDR_Struct
+ *! \brief  Reset ISR Start Address Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PTI_RST_ISR_STARTADDR_t__
+typedef struct _ADI_PTI_RST_ISR_STARTADDR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PTI_RST_ISR_STARTADDR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PTI_RST_ISR_STARTADDR_t__ */
+
+/*@}*/
+
+/** @defgroup RST_STACK_PTR Reset Stack Pointer (RST_STACK_PTR) Register
+ *  Reset Stack Pointer (RST_STACK_PTR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PTI_RST_STACK_PTR_Struct
+ *! \brief  Reset Stack Pointer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PTI_RST_STACK_PTR_t__
+typedef struct _ADI_PTI_RST_STACK_PTR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PTI_RST_STACK_PTR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PTI_RST_STACK_PTR_t__ */
+
+/*@}*/
+
+/** @defgroup CTL Parallel Test Interface Control Register (CTL) Register
+ *  Parallel Test Interface Control Register (CTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PTI_CTL_Struct
+ *! \brief  Parallel Test Interface Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PTI_CTL_t__
+typedef struct _ADI_PTI_CTL_t {
+  union {
+    struct {
+      unsigned int EN         :  1;
+      unsigned int reserved1  : 31;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PTI_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PTI_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup INTNUM Interrupt Control Type (INTNUM) Register
+ *  Interrupt Control Type (INTNUM) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTNUM_Struct
+ *! \brief  Interrupt Control Type Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTNUM_t__
+typedef struct _ADI_NVIC_INTNUM_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Interrupt Control Type */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTNUM_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTNUM_t__ */
+
+/*@}*/
+
+/** @defgroup STKSTA Systick Control and Status (STKSTA) Register
+ *  Systick Control and Status (STKSTA) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_STKSTA_Struct
+ *! \brief  Systick Control and Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_STKSTA_t__
+typedef struct _ADI_NVIC_STKSTA_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Systick Control and Status */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_STKSTA_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_STKSTA_t__ */
+
+/*@}*/
+
+/** @defgroup STKLD Systick Reload Value (STKLD) Register
+ *  Systick Reload Value (STKLD) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_STKLD_Struct
+ *! \brief  Systick Reload Value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_STKLD_t__
+typedef struct _ADI_NVIC_STKLD_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Systick Reload Value */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_STKLD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_STKLD_t__ */
+
+/*@}*/
+
+/** @defgroup STKVAL Systick Current Value (STKVAL) Register
+ *  Systick Current Value (STKVAL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_STKVAL_Struct
+ *! \brief  Systick Current Value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_STKVAL_t__
+typedef struct _ADI_NVIC_STKVAL_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Systick Current Value */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_STKVAL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_STKVAL_t__ */
+
+/*@}*/
+
+/** @defgroup STKCAL Systick Calibration Value (STKCAL) Register
+ *  Systick Calibration Value (STKCAL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_STKCAL_Struct
+ *! \brief  Systick Calibration Value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_STKCAL_t__
+typedef struct _ADI_NVIC_STKCAL_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Systick Calibration Value */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_STKCAL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_STKCAL_t__ */
+
+/*@}*/
+
+/** @defgroup INTSETE0 IRQ0..31 Set_Enable (INTSETE0) Register
+ *  IRQ0..31 Set_Enable (INTSETE0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTSETE0_Struct
+ *! \brief  IRQ0..31 Set_Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETE0_t__
+typedef struct _ADI_NVIC_INTSETE0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ0..31 Set_Enable */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTSETE0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETE0_t__ */
+
+/*@}*/
+
+/** @defgroup INTSETE1 IRQ32..63 Set_Enable (INTSETE1) Register
+ *  IRQ32..63 Set_Enable (INTSETE1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTSETE1_Struct
+ *! \brief  IRQ32..63 Set_Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETE1_t__
+typedef struct _ADI_NVIC_INTSETE1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ32..63 Set_Enable */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTSETE1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETE1_t__ */
+
+/*@}*/
+
+/** @defgroup INTCLRE0 IRQ0..31 Clear_Enable (INTCLRE0) Register
+ *  IRQ0..31 Clear_Enable (INTCLRE0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCLRE0_Struct
+ *! \brief  IRQ0..31 Clear_Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRE0_t__
+typedef struct _ADI_NVIC_INTCLRE0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ0..31 Clear_Enable */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCLRE0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRE0_t__ */
+
+/*@}*/
+
+/** @defgroup INTCLRE1 IRQ32..63 Clear_Enable (INTCLRE1) Register
+ *  IRQ32..63 Clear_Enable (INTCLRE1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCLRE1_Struct
+ *! \brief  IRQ32..63 Clear_Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRE1_t__
+typedef struct _ADI_NVIC_INTCLRE1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ32..63 Clear_Enable */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCLRE1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRE1_t__ */
+
+/*@}*/
+
+/** @defgroup INTSETP0 IRQ0..31 Set_Pending (INTSETP0) Register
+ *  IRQ0..31 Set_Pending (INTSETP0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTSETP0_Struct
+ *! \brief  IRQ0..31 Set_Pending Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETP0_t__
+typedef struct _ADI_NVIC_INTSETP0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ0..31 Set_Pending */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTSETP0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETP0_t__ */
+
+/*@}*/
+
+/** @defgroup INTSETP1 IRQ32..63 Set_Pending (INTSETP1) Register
+ *  IRQ32..63 Set_Pending (INTSETP1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTSETP1_Struct
+ *! \brief  IRQ32..63 Set_Pending Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETP1_t__
+typedef struct _ADI_NVIC_INTSETP1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ32..63 Set_Pending */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTSETP1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETP1_t__ */
+
+/*@}*/
+
+/** @defgroup INTCLRP0 IRQ0..31 Clear_Pending (INTCLRP0) Register
+ *  IRQ0..31 Clear_Pending (INTCLRP0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCLRP0_Struct
+ *! \brief  IRQ0..31 Clear_Pending Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRP0_t__
+typedef struct _ADI_NVIC_INTCLRP0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ0..31 Clear_Pending */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCLRP0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRP0_t__ */
+
+/*@}*/
+
+/** @defgroup INTCLRP1 IRQ32..63 Clear_Pending (INTCLRP1) Register
+ *  IRQ32..63 Clear_Pending (INTCLRP1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCLRP1_Struct
+ *! \brief  IRQ32..63 Clear_Pending Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRP1_t__
+typedef struct _ADI_NVIC_INTCLRP1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ32..63 Clear_Pending */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCLRP1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRP1_t__ */
+
+/*@}*/
+
+/** @defgroup INTACT0 IRQ0..31 Active Bit (INTACT0) Register
+ *  IRQ0..31 Active Bit (INTACT0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTACT0_Struct
+ *! \brief  IRQ0..31 Active Bit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTACT0_t__
+typedef struct _ADI_NVIC_INTACT0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ0..31 Active Bit */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTACT0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTACT0_t__ */
+
+/*@}*/
+
+/** @defgroup INTACT1 IRQ32..63 Active Bit (INTACT1) Register
+ *  IRQ32..63 Active Bit (INTACT1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTACT1_Struct
+ *! \brief  IRQ32..63 Active Bit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTACT1_t__
+typedef struct _ADI_NVIC_INTACT1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ32..63 Active Bit */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTACT1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTACT1_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI0 IRQ0..3 Priority (INTPRI0) Register
+ *  IRQ0..3 Priority (INTPRI0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI0_Struct
+ *! \brief  IRQ0..3 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI0_t__
+typedef struct _ADI_NVIC_INTPRI0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ0..3 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI0_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI1 IRQ4..7 Priority (INTPRI1) Register
+ *  IRQ4..7 Priority (INTPRI1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI1_Struct
+ *! \brief  IRQ4..7 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI1_t__
+typedef struct _ADI_NVIC_INTPRI1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ4..7 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI1_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI2 IRQ8..11 Priority (INTPRI2) Register
+ *  IRQ8..11 Priority (INTPRI2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI2_Struct
+ *! \brief  IRQ8..11 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI2_t__
+typedef struct _ADI_NVIC_INTPRI2_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ8..11 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI2_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI3 IRQ12..15 Priority (INTPRI3) Register
+ *  IRQ12..15 Priority (INTPRI3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI3_Struct
+ *! \brief  IRQ12..15 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI3_t__
+typedef struct _ADI_NVIC_INTPRI3_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ12..15 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI3_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI4 IRQ16..19 Priority (INTPRI4) Register
+ *  IRQ16..19 Priority (INTPRI4) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI4_Struct
+ *! \brief  IRQ16..19 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI4_t__
+typedef struct _ADI_NVIC_INTPRI4_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ16..19 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI4_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI4_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI5 IRQ20..23 Priority (INTPRI5) Register
+ *  IRQ20..23 Priority (INTPRI5) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI5_Struct
+ *! \brief  IRQ20..23 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI5_t__
+typedef struct _ADI_NVIC_INTPRI5_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ20..23 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI5_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI5_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI6 IRQ24..27 Priority (INTPRI6) Register
+ *  IRQ24..27 Priority (INTPRI6) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI6_Struct
+ *! \brief  IRQ24..27 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI6_t__
+typedef struct _ADI_NVIC_INTPRI6_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ24..27 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI6_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI6_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI7 IRQ28..31 Priority (INTPRI7) Register
+ *  IRQ28..31 Priority (INTPRI7) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI7_Struct
+ *! \brief  IRQ28..31 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI7_t__
+typedef struct _ADI_NVIC_INTPRI7_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ28..31 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI7_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI7_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI8 IRQ32..35 Priority (INTPRI8) Register
+ *  IRQ32..35 Priority (INTPRI8) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI8_Struct
+ *! \brief  IRQ32..35 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI8_t__
+typedef struct _ADI_NVIC_INTPRI8_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ32..35 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI8_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI8_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI9 IRQ36..39 Priority (INTPRI9) Register
+ *  IRQ36..39 Priority (INTPRI9) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI9_Struct
+ *! \brief  IRQ36..39 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI9_t__
+typedef struct _ADI_NVIC_INTPRI9_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ36..39 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI9_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI9_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI10 IRQ40..43 Priority (INTPRI10) Register
+ *  IRQ40..43 Priority (INTPRI10) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI10_Struct
+ *! \brief  IRQ40..43 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI10_t__
+typedef struct _ADI_NVIC_INTPRI10_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ40..43 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI10_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI10_t__ */
+
+/*@}*/
+
+/** @defgroup INTCPID CPUID Base (INTCPID) Register
+ *  CPUID Base (INTCPID) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCPID_Struct
+ *! \brief  CPUID Base Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCPID_t__
+typedef struct _ADI_NVIC_INTCPID_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< CPUID Base */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCPID_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCPID_t__ */
+
+/*@}*/
+
+/** @defgroup INTSTA Interrupt Control State (INTSTA) Register
+ *  Interrupt Control State (INTSTA) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTSTA_Struct
+ *! \brief  Interrupt Control State Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSTA_t__
+typedef struct _ADI_NVIC_INTSTA_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Interrupt Control State */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTSTA_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSTA_t__ */
+
+/*@}*/
+
+/** @defgroup INTVEC Vector Table Offset (INTVEC) Register
+ *  Vector Table Offset (INTVEC) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTVEC_Struct
+ *! \brief  Vector Table Offset Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTVEC_t__
+typedef struct _ADI_NVIC_INTVEC_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Vector Table Offset */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTVEC_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTVEC_t__ */
+
+/*@}*/
+
+/** @defgroup INTAIRC Application Interrupt/Reset Control (INTAIRC) Register
+ *  Application Interrupt/Reset Control (INTAIRC) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTAIRC_Struct
+ *! \brief  Application Interrupt/Reset Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTAIRC_t__
+typedef struct _ADI_NVIC_INTAIRC_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Application Interrupt/Reset Control */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTAIRC_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTAIRC_t__ */
+
+/*@}*/
+
+/** @defgroup INTCON0 System Control (INTCON0) Register
+ *  System Control (INTCON0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCON0_Struct
+ *! \brief  System Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCON0_t__
+typedef struct _ADI_NVIC_INTCON0_t {
+  union {
+    struct {
+      unsigned int reserved0   :  1;
+      unsigned int SLEEPONEXIT :  1;  /**< Sleeps the core on exit from an ISR */
+      unsigned int SLEEPDEEP   :  1;  /**< deep sleep flag for HIBERNATE mode */
+      unsigned int reserved3   : 13;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_NVIC_INTCON0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCON0_t__ */
+
+/*@}*/
+
+/** @defgroup INTCON1 Configuration Control (INTCON1) Register
+ *  Configuration Control (INTCON1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCON1_Struct
+ *! \brief  Configuration Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCON1_t__
+typedef struct _ADI_NVIC_INTCON1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Configuration Control */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCON1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCON1_t__ */
+
+/*@}*/
+
+/** @defgroup INTSHPRIO0 System Handlers 4-7 Priority (INTSHPRIO0) Register
+ *  System Handlers 4-7 Priority (INTSHPRIO0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTSHPRIO0_Struct
+ *! \brief  System Handlers 4-7 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO0_t__
+typedef struct _ADI_NVIC_INTSHPRIO0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< System Handlers 4-7 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTSHPRIO0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO0_t__ */
+
+/*@}*/
+
+/** @defgroup INTSHPRIO1 System Handlers 8-11 Priority (INTSHPRIO1) Register
+ *  System Handlers 8-11 Priority (INTSHPRIO1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTSHPRIO1_Struct
+ *! \brief  System Handlers 8-11 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO1_t__
+typedef struct _ADI_NVIC_INTSHPRIO1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< System Handlers 8-11 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTSHPRIO1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO1_t__ */
+
+/*@}*/
+
+/** @defgroup INTSHPRIO3 System Handlers 12-15 Priority (INTSHPRIO3) Register
+ *  System Handlers 12-15 Priority (INTSHPRIO3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTSHPRIO3_Struct
+ *! \brief  System Handlers 12-15 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO3_t__
+typedef struct _ADI_NVIC_INTSHPRIO3_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< System Handlers 12-15 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTSHPRIO3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO3_t__ */
+
+/*@}*/
+
+/** @defgroup INTSHCSR System Handler Control and State (INTSHCSR) Register
+ *  System Handler Control and State (INTSHCSR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTSHCSR_Struct
+ *! \brief  System Handler Control and State Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHCSR_t__
+typedef struct _ADI_NVIC_INTSHCSR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< System Handler Control and State */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTSHCSR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHCSR_t__ */
+
+/*@}*/
+
+/** @defgroup INTCFSR Configurable Fault Status (INTCFSR) Register
+ *  Configurable Fault Status (INTCFSR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCFSR_Struct
+ *! \brief  Configurable Fault Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCFSR_t__
+typedef struct _ADI_NVIC_INTCFSR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Configurable Fault Status */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCFSR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCFSR_t__ */
+
+/*@}*/
+
+/** @defgroup INTHFSR Hard Fault Status (INTHFSR) Register
+ *  Hard Fault Status (INTHFSR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTHFSR_Struct
+ *! \brief  Hard Fault Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTHFSR_t__
+typedef struct _ADI_NVIC_INTHFSR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Hard Fault Status */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTHFSR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTHFSR_t__ */
+
+/*@}*/
+
+/** @defgroup INTDFSR Debug Fault Status (INTDFSR) Register
+ *  Debug Fault Status (INTDFSR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTDFSR_Struct
+ *! \brief  Debug Fault Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTDFSR_t__
+typedef struct _ADI_NVIC_INTDFSR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Debug Fault Status */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTDFSR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTDFSR_t__ */
+
+/*@}*/
+
+/** @defgroup INTMMAR Mem Manage Address (INTMMAR) Register
+ *  Mem Manage Address (INTMMAR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTMMAR_Struct
+ *! \brief  Mem Manage Address Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMAR_t__
+typedef struct _ADI_NVIC_INTMMAR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Mem Manage Address */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTMMAR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMAR_t__ */
+
+/*@}*/
+
+/** @defgroup INTBFAR Bus Fault Address (INTBFAR) Register
+ *  Bus Fault Address (INTBFAR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTBFAR_Struct
+ *! \brief  Bus Fault Address Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTBFAR_t__
+typedef struct _ADI_NVIC_INTBFAR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Bus Fault Address */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTBFAR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTBFAR_t__ */
+
+/*@}*/
+
+/** @defgroup INTAFSR Auxiliary Fault Status (INTAFSR) Register
+ *  Auxiliary Fault Status (INTAFSR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTAFSR_Struct
+ *! \brief  Auxiliary Fault Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTAFSR_t__
+typedef struct _ADI_NVIC_INTAFSR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Auxiliary Fault Status */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTAFSR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTAFSR_t__ */
+
+/*@}*/
+
+/** @defgroup INTPFR0 Processor Feature Register 0 (INTPFR0) Register
+ *  Processor Feature Register 0 (INTPFR0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPFR0_Struct
+ *! \brief  Processor Feature Register 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPFR0_t__
+typedef struct _ADI_NVIC_INTPFR0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Processor Feature Register 0 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPFR0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPFR0_t__ */
+
+/*@}*/
+
+/** @defgroup INTPFR1 Processor Feature Register 1 (INTPFR1) Register
+ *  Processor Feature Register 1 (INTPFR1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPFR1_Struct
+ *! \brief  Processor Feature Register 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPFR1_t__
+typedef struct _ADI_NVIC_INTPFR1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Processor Feature Register 1 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPFR1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPFR1_t__ */
+
+/*@}*/
+
+/** @defgroup INTDFR0 Debug Feature Register 0 (INTDFR0) Register
+ *  Debug Feature Register 0 (INTDFR0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTDFR0_Struct
+ *! \brief  Debug Feature Register 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTDFR0_t__
+typedef struct _ADI_NVIC_INTDFR0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Debug Feature Register 0 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTDFR0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTDFR0_t__ */
+
+/*@}*/
+
+/** @defgroup INTAFR0 Auxiliary Feature Register 0 (INTAFR0) Register
+ *  Auxiliary Feature Register 0 (INTAFR0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTAFR0_Struct
+ *! \brief  Auxiliary Feature Register 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTAFR0_t__
+typedef struct _ADI_NVIC_INTAFR0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Auxiliary Feature Register 0 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTAFR0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTAFR0_t__ */
+
+/*@}*/
+
+/** @defgroup INTMMFR0 Memory Model Feature Register 0 (INTMMFR0) Register
+ *  Memory Model Feature Register 0 (INTMMFR0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTMMFR0_Struct
+ *! \brief  Memory Model Feature Register 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR0_t__
+typedef struct _ADI_NVIC_INTMMFR0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Memory Model Feature Register 0 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTMMFR0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR0_t__ */
+
+/*@}*/
+
+/** @defgroup INTMMFR1 Memory Model Feature Register 1 (INTMMFR1) Register
+ *  Memory Model Feature Register 1 (INTMMFR1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTMMFR1_Struct
+ *! \brief  Memory Model Feature Register 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR1_t__
+typedef struct _ADI_NVIC_INTMMFR1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Memory Model Feature Register 1 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTMMFR1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR1_t__ */
+
+/*@}*/
+
+/** @defgroup INTMMFR2 Memory Model Feature Register 2 (INTMMFR2) Register
+ *  Memory Model Feature Register 2 (INTMMFR2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTMMFR2_Struct
+ *! \brief  Memory Model Feature Register 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR2_t__
+typedef struct _ADI_NVIC_INTMMFR2_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Memory Model Feature Register 2 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTMMFR2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR2_t__ */
+
+/*@}*/
+
+/** @defgroup INTMMFR3 Memory Model Feature Register 3 (INTMMFR3) Register
+ *  Memory Model Feature Register 3 (INTMMFR3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTMMFR3_Struct
+ *! \brief  Memory Model Feature Register 3 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR3_t__
+typedef struct _ADI_NVIC_INTMMFR3_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Memory Model Feature Register 3 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTMMFR3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR3_t__ */
+
+/*@}*/
+
+/** @defgroup INTISAR0 ISA Feature Register 0 (INTISAR0) Register
+ *  ISA Feature Register 0 (INTISAR0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTISAR0_Struct
+ *! \brief  ISA Feature Register 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR0_t__
+typedef struct _ADI_NVIC_INTISAR0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< ISA Feature Register 0 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTISAR0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR0_t__ */
+
+/*@}*/
+
+/** @defgroup INTISAR1 ISA Feature Register 1 (INTISAR1) Register
+ *  ISA Feature Register 1 (INTISAR1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTISAR1_Struct
+ *! \brief  ISA Feature Register 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR1_t__
+typedef struct _ADI_NVIC_INTISAR1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< ISA Feature Register 1 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTISAR1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR1_t__ */
+
+/*@}*/
+
+/** @defgroup INTISAR2 ISA Feature Register 2 (INTISAR2) Register
+ *  ISA Feature Register 2 (INTISAR2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTISAR2_Struct
+ *! \brief  ISA Feature Register 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR2_t__
+typedef struct _ADI_NVIC_INTISAR2_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< ISA Feature Register 2 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTISAR2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR2_t__ */
+
+/*@}*/
+
+/** @defgroup INTISAR3 ISA Feature Register 3 (INTISAR3) Register
+ *  ISA Feature Register 3 (INTISAR3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTISAR3_Struct
+ *! \brief  ISA Feature Register 3 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR3_t__
+typedef struct _ADI_NVIC_INTISAR3_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< ISA Feature Register 3 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTISAR3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR3_t__ */
+
+/*@}*/
+
+/** @defgroup INTISAR4 ISA Feature Register 4 (INTISAR4) Register
+ *  ISA Feature Register 4 (INTISAR4) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTISAR4_Struct
+ *! \brief  ISA Feature Register 4 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR4_t__
+typedef struct _ADI_NVIC_INTISAR4_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< ISA Feature Register 4 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTISAR4_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR4_t__ */
+
+/*@}*/
+
+/** @defgroup INTTRGI Software Trigger Interrupt Register (INTTRGI) Register
+ *  Software Trigger Interrupt Register (INTTRGI) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTTRGI_Struct
+ *! \brief  Software Trigger Interrupt Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTTRGI_t__
+typedef struct _ADI_NVIC_INTTRGI_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Software Trigger Interrupt Register */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTTRGI_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTTRGI_t__ */
+
+/*@}*/
+
+/** @defgroup INTPID4 Peripheral Identification Register 4 (INTPID4) Register
+ *  Peripheral Identification Register 4 (INTPID4) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPID4_Struct
+ *! \brief  Peripheral Identification Register 4 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID4_t__
+typedef struct _ADI_NVIC_INTPID4_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Peripheral Identification Register 4 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPID4_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID4_t__ */
+
+/*@}*/
+
+/** @defgroup INTPID5 Peripheral Identification Register 5 (INTPID5) Register
+ *  Peripheral Identification Register 5 (INTPID5) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPID5_Struct
+ *! \brief  Peripheral Identification Register 5 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID5_t__
+typedef struct _ADI_NVIC_INTPID5_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Peripheral Identification Register 5 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPID5_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID5_t__ */
+
+/*@}*/
+
+/** @defgroup INTPID6 Peripheral Identification Register 6 (INTPID6) Register
+ *  Peripheral Identification Register 6 (INTPID6) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPID6_Struct
+ *! \brief  Peripheral Identification Register 6 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID6_t__
+typedef struct _ADI_NVIC_INTPID6_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Peripheral Identification Register 6 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPID6_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID6_t__ */
+
+/*@}*/
+
+/** @defgroup INTPID7 Peripheral Identification Register 7 (INTPID7) Register
+ *  Peripheral Identification Register 7 (INTPID7) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPID7_Struct
+ *! \brief  Peripheral Identification Register 7 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID7_t__
+typedef struct _ADI_NVIC_INTPID7_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Peripheral Identification Register 7 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPID7_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID7_t__ */
+
+/*@}*/
+
+/** @defgroup INTPID0 Peripheral Identification Bits7:0 (INTPID0) Register
+ *  Peripheral Identification Bits7:0 (INTPID0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPID0_Struct
+ *! \brief  Peripheral Identification Bits7:0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID0_t__
+typedef struct _ADI_NVIC_INTPID0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Peripheral Identification Bits7:0 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPID0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID0_t__ */
+
+/*@}*/
+
+/** @defgroup INTPID1 Peripheral Identification Bits15:8 (INTPID1) Register
+ *  Peripheral Identification Bits15:8 (INTPID1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPID1_Struct
+ *! \brief  Peripheral Identification Bits15:8 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID1_t__
+typedef struct _ADI_NVIC_INTPID1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Peripheral Identification Bits15:8 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPID1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID1_t__ */
+
+/*@}*/
+
+/** @defgroup INTPID2 Peripheral Identification Bits16:23 (INTPID2) Register
+ *  Peripheral Identification Bits16:23 (INTPID2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPID2_Struct
+ *! \brief  Peripheral Identification Bits16:23 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID2_t__
+typedef struct _ADI_NVIC_INTPID2_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Peripheral Identification Bits16:23 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPID2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID2_t__ */
+
+/*@}*/
+
+/** @defgroup INTPID3 Peripheral Identification Bits24:31 (INTPID3) Register
+ *  Peripheral Identification Bits24:31 (INTPID3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPID3_Struct
+ *! \brief  Peripheral Identification Bits24:31 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID3_t__
+typedef struct _ADI_NVIC_INTPID3_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Peripheral Identification Bits24:31 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPID3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID3_t__ */
+
+/*@}*/
+
+/** @defgroup INTCID0 Component Identification Bits7:0 (INTCID0) Register
+ *  Component Identification Bits7:0 (INTCID0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCID0_Struct
+ *! \brief  Component Identification Bits7:0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID0_t__
+typedef struct _ADI_NVIC_INTCID0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Component Identification Bits7:0 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCID0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID0_t__ */
+
+/*@}*/
+
+/** @defgroup INTCID1 Component Identification Bits15:8 (INTCID1) Register
+ *  Component Identification Bits15:8 (INTCID1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCID1_Struct
+ *! \brief  Component Identification Bits15:8 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID1_t__
+typedef struct _ADI_NVIC_INTCID1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Component Identification Bits15:8 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCID1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID1_t__ */
+
+/*@}*/
+
+/** @defgroup INTCID2 Component Identification Bits16:23 (INTCID2) Register
+ *  Component Identification Bits16:23 (INTCID2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCID2_Struct
+ *! \brief  Component Identification Bits16:23 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID2_t__
+typedef struct _ADI_NVIC_INTCID2_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Component Identification Bits16:23 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCID2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID2_t__ */
+
+/*@}*/
+
+/** @defgroup INTCID3 Component Identification Bits24:31 (INTCID3) Register
+ *  Component Identification Bits24:31 (INTCID3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCID3_Struct
+ *! \brief  Component Identification Bits24:31 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID3_t__
+typedef struct _ADI_NVIC_INTCID3_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Component Identification Bits24:31 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCID3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID3_t__ */
+
+/*@}*/
+
+
+#if defined (_MISRA_RULES)
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/adi_cio_macros.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/adi_cio_macros.h
new file mode 100755
index 00000000000..45f235b44be
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/adi_cio_macros.h
@@ -0,0 +1,50 @@
+/*
+** adi_cio_macros.h
+**
+** Copyright (C) 2016 Analog Devices, Inc. All Rights Reserved.
+**
+*/
+
+#ifndef _ADI_CIO_MACROS_H
+#define _ADI_CIO_MACROS_H
+
+/*
+ * Macro definitions in adi_ADuCM4*50_cdef.h and the struct definitions
+ * in adi_ADuCM4*50_device.h use macros "__I __C", "__O" and "__IO" to
+ * represent read-only, write-only and read/write register attributes.
+ *
+ * The core_cm4.h include file will define macros __I, __O and __IO as below
+ * but it does not define __C.
+ *
+ * The __C macro is defined to nothing here. The __C macro is intended for
+ * the proprietary compilers in CCES to avoid MISRA Rule 19.4 errors regarding
+ * permitted macro expansions. The iccarm.exe MISRA checking does not fault
+ * the combined "volatile const" __I macro so __C is not required.
+ *
+ * Each of the macro defines is guarded by a #ifndef check to allow them
+ * to be redefined if required.
+ *
+ * Workaround for 01-00-0757 / 01-00-0759
+ */
+
+#ifndef __I
+  #ifdef __cplusplus
+    #define   __I   volatile       /*!< Defines 'read only' permissions    */
+  #else
+    #define   __I   volatile const /*!< Defines 'read only' permissions    */
+  #endif
+#endif
+
+#ifndef __O
+  #define   __O     volatile       /*!< Defines 'write only' permissions   */
+#endif
+
+#ifndef __IO
+  #define   __IO    volatile       /*!< Defines 'read / write' permissions */
+#endif
+
+#ifndef __C
+  #define     __C     /*nothing*/
+#endif
+
+#endif /* _ADI_CIO_MACROS_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/platform.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/platform.h
new file mode 100755
index 00000000000..37dbeae3816
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/platform.h
@@ -0,0 +1,60 @@
+/*!
+ *****************************************************************************
+ * @file:    platform.h
+ * @brief:   Include appropriate architecture definitions.
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#ifndef __ADI_SYS_PLATFORM_H__
+#define __ADI_SYS_PLATFORM_H__
+
+/* Include the ADI cdef header for the selected target. */
+
+#if defined(__ADUCM4050__)
+#include <ADuCM4050_cdef.h>
+#elif defined(__ADUCM3027__)
+#include <ADuCM3027_cdef.h>
+#elif defined(__ADUCM3029__)
+#include <ADuCM3029_cdef.h>
+#else
+#error <sys/platform.h> not configured for this target.
+#endif
+
+#endif /* __ADI_SYS_PLATFORM_H__ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/system_ADuCM3029.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/system_ADuCM3029.h
new file mode 100755
index 00000000000..d36a11ee65b
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/system_ADuCM3029.h
@@ -0,0 +1,127 @@
+/*!
+ *****************************************************************************
+ * @file:    system_ADuCM3029.h
+ * @brief:   CMSIS Cortex-M3 Device Peripheral Access Layer Header File
+ *           for the ADI ADuCxxx Device Series
+ * @version: $Revision: 36134 $
+ * @date:    $Date: 2017-01-12 05:13:23 -0500 (Thu, 12 Jan 2017) $
+ *-----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ *****************************************************************************/
+
+
+/*! \addtogroup SYS_Driver System Interfaces
+ *  @{
+ * add result types to doxygen
+ */
+
+#ifndef SYSTEM_ADUCM3029_H
+#define SYSTEM_ADUCM3029_H
+
+#include <stddef.h>     /* for 'NULL' */
+#include <stdint.h>
+#include <stdbool.h>
+#include <adi_processor.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*! \cond PRIVATE */
+#define SUCCESS 0u
+
+#define FAILURE 1u
+
+/* System clock constant */
+#define __HFOSC     26000000u  
+
+/* System clock constant (may also be 16000000) */
+#define __HFXTAL    26000000u  
+
+/*System clock constant (same whether internal osc or external xtal) */
+#define __LFCLK        32768u 
+
+/* Selecting HFOSC as input for generating root clock*/
+#define HFMUX_INTERNAL_OSC_VAL      (0u << BITP_CLKG_CLK_CTL0_CLKMUX)
+
+/* Selecting HFXTL as input for generating root clock*/
+#define HFMUX_EXTERNAL_XTAL_VAL     (1u << BITP_CLKG_CLK_CTL0_CLKMUX)
+
+/* Selecting SPLL as input for generating root clock*/
+#define HFMUX_SYSTEM_SPLL_VAL       (2u << BITP_CLKG_CLK_CTL0_CLKMUX)
+
+/* Selecting GPIO as input for generating root clock*/
+#define HFMUX_GPIO_VAL              (3u << BITP_CLKG_CLK_CTL0_CLKMUX)
+
+/*
+ * Security options
+ */
+typedef struct {
+        const uint32_t ReadProtectKeyHash[4];    
+        const uint32_t CrcOfReadProtectKeyHash;  
+        const uint32_t LastCRCPage;              
+        const uint32_t InCircuitWriteProtectCode;
+        const uint32_t FlashBlockWriteProtect;   
+
+} ADI_ADUCM302X_SECURITY_OPTIONS;
+
+/*! \endcond  */
+
+/*! Cache controller key */
+#define CACHE_CONTROLLER_KEY 0xF123F456u
+/*! Power  key */
+#define PWRKEY_VALUE_KEY 0x4859u
+
+  
+/**
+ *  SRAM banks
+ */
+typedef uint32_t ADI_SRAM_BANK;
+
+/*! SRAM_BANK_0 */
+#define ADI_SRAM_BANK_0  (1u << 0)
+/*! SRAM_BANK_1 */
+#define ADI_SRAM_BANK_1  (1u << 1)
+/*! SRAM_BANK_2 */
+#define ADI_SRAM_BANK_2  (1u << 2)
+/*! SRAM_BANK_3 */
+#define ADI_SRAM_BANK_3  (1u << 3)
+/*! SRAM_BANK_4 */
+#define ADI_SRAM_BANK_4  (1u << 4)
+/*! SRAM_BANK_5 */
+#define ADI_SRAM_BANK_5  (1u << 5)
+/*! SRAM_BANK_6 */
+#define ADI_SRAM_BANK_6  (1u << 6)
+/*! SRAM_BANK_7 */
+#define ADI_SRAM_BANK_7  (1u << 7)
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+void adi_system_EnableCache(bool bEnable);
+uint32_t  adi_system_EnableRetention(ADI_SRAM_BANK eBank, bool bEnable);
+void adi_system_EnableISRAM(bool bEnable);
+extern uint32_t SystemCoreClock;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_ADUCM3029_H */
+
+/**@}*/
+
+/*
+** EOF
+*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr.c
new file mode 100755
index 00000000000..9e889131ca2
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr.c
@@ -0,0 +1,643 @@
+/*! *****************************************************************************
+ * @file    adi_tmr.c
+ * @brief   GP and RGB timer device driver implementation
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm011 (rule 6.3): the basic types of char, int, short, long, float, and double should not be used
+*   Necessary for stdbool.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+*
+* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
+*   Static configuration data file is included.
+*
+* Pm140 (Rule 11.4): a cast should not be performed between a pointer type and an integral type
+*   This violation appears when deferencing the pointer to the register typedef. No way around this.
+*
+* Pm141 (Rule 11.4): a cast should not be performed between a pointer to object type and a different pointer to object type
+*   The pointer casting is necessary to allow the GP and RGB timers to abstracted into one driver. This has been approved by the PO.
+*/
+#pragma diag_suppress=Pm011,Pm073,Pm123,Pm140,Pm141,Pm143
+#endif /* __ICCARM__ */
+
+
+/** @addtogroup TMR_Driver Timer Driver
+ *  @{
+ * @brief General Purpose and RGB Timer Driver
+ * @details The timer driver controls the timer period, event capture, and
+ * pulse width modulation (PWM) features of the General Purpose (GP) Timers and
+ * the RGB Timer.
+ *  @note The application must include drivers/tmr/adi_tmr.h to use this driver
+ */
+
+#include <adi_processor.h>
+#include <adi_tmr_config.h>
+#include <rtos_map/adi_rtos_map.h>
+#include <drivers/tmr/adi_tmr.h>
+
+/* Static configuration data */
+#include "adi_tmr_data.c"
+
+#if defined(__ADUCM4x50__)
+/* In adi_tmr_ConfigPwm, the bit positions for just PWM0 are used for PWM1 and PWM2 to simplify the code. Check here to make sure this is safe. */
+#if BITP_TMR_RGB_PWM0CTL_IDLESTATE != BITP_TMR_RGB_PWM1CTL_IDLESTATE
+#error "Bit positions for PWM0 and PWM1 do not match. Fix adi_tmr_ConfigPwm."
+#endif
+#if BITP_TMR_RGB_PWM0CTL_IDLESTATE != BITP_TMR_RGB_PWM2CTL_IDLESTATE
+#error "Bit positions for PWM0 and PWM2 do not match. Fix adi_tmr_ConfigPwm."
+#endif
+#if BITP_TMR_RGB_PWM0CTL_MATCH != BITP_TMR_RGB_PWM1CTL_MATCH
+#error "Bit positions for PWM0 and PWM1 do not match. Fix adi_tmr_ConfigPwm."
+#endif
+#if BITP_TMR_RGB_PWM0CTL_MATCH != BITP_TMR_RGB_PWM2CTL_MATCH
+#error "Bit positions for PWM0 and PWM2 do not match. Fix adi_tmr_ConfigPwm."
+#endif
+#endif /*__ADUCM4x50__*/
+
+/*! Number of events that can be captured */
+#if defined(__ADUCM302x__)
+#define ADI_TMR_NUM_EVENTS (16u)
+#elif defined(__ADUCM4x50__)
+#define ADI_TMR_NUM_EVENTS (40u)
+#else
+#error TMR is not ported for this processor
+#endif
+
+/*! \cond PRIVATE */
+
+/* Since the RGB typedef is a superset of the GP typedef, treat the GP timers as RGB timers and restrict top register access */
+#if defined(__ADUCM302x__)
+static ADI_TMR_TypeDef * adi_tmr_registers[ADI_TMR_DEVICE_NUM] = {pADI_TMR0, pADI_TMR1, pADI_TMR2};
+#elif defined(__ADUCM4x50__)
+static ADI_TMR_RGB_TypeDef * adi_tmr_registers[ADI_TMR_DEVICE_NUM] = {(ADI_TMR_RGB_TypeDef *) pADI_TMR0, (ADI_TMR_RGB_TypeDef *) pADI_TMR1, (ADI_TMR_RGB_TypeDef *) pADI_TMR2, pADI_TMR_RGB};
+#else
+#error TMR is not ported for this processor
+#endif
+
+/* Interrupt enums */
+#if defined(__ADUCM302x__)
+static const IRQn_Type adi_tmr_interrupt[ADI_TMR_DEVICE_NUM] = {TMR0_EVT_IRQn, TMR1_EVT_IRQn, TMR2_EVT_IRQn};
+#elif defined(__ADUCM4x50__)
+static const IRQn_Type adi_tmr_interrupt[ADI_TMR_DEVICE_NUM] = {TMR0_EVT_IRQn, TMR1_EVT_IRQn, TMR2_EVT_IRQn, TMR_RGB_EVT_IRQn};
+#else
+#error TMR is not ported for this processor
+#endif
+
+/* Private data that the driver needs to retain between function calls */
+static ADI_CALLBACK adi_tmr_callbacks[ADI_TMR_DEVICE_NUM];
+static void * adi_tmr_parameters[ADI_TMR_DEVICE_NUM];
+
+static ADI_TMR_RESULT WaitForStatusBit   (ADI_TMR_DEVICE const eDevice, uint16_t nBusyBit);
+static void           CommonIntHandler   (ADI_TMR_DEVICE const eDevice);
+       void           GP_Tmr0_Int_Handler(void);
+       void           GP_Tmr1_Int_Handler(void);
+       void           GP_Tmr2_Int_Handler(void);
+#if defined(__ADUCM4x50__)
+       void           RGB_Tmr_Int_Handler(void);
+#endif
+
+/*! \endcond */
+
+
+/*********************************************************************************
+                                    API IMPLEMENTATIONS 
+*********************************************************************************/
+
+
+/*!
+ * @brief       Initialize GP or RGB Timer
+ *
+ * @details     Setup callback function, device interrupt, and perform static configuration (if applicable).
+ *
+ * @note        This function can only be called when the timer is disabled. This function should be called
+ *              before any other functions are called.
+ *
+ * @param [in]  eDevice : Device number
+ *
+ * @param [in]  pfCallback : Callback function
+ *
+ * @param [in]  pCBParam : Callback function parameter
+ *
+ * @param [in]  bEnableInt : True to enable the device interrupt, false to disable it
+ *
+ * @return      ADI_TMR_RESULT
+ *                - #ADI_TMR_BAD_DEVICE_NUM        [D]  Invalid eDevice parameter supplied
+ *                - #ADI_TMR_OPERATION_NOT_ALLOWED [D]  Timer is currently running
+ *                - #ADI_TMR_SUCCESS                    Function call completed successfully
+ *
+ */
+ADI_TMR_RESULT adi_tmr_Init(ADI_TMR_DEVICE const eDevice, ADI_CALLBACK const pfCallback, void * const pCBParam, bool bEnableInt) {
+#ifdef ADI_DEBUG
+    /* IF(Bad device input parameter) */
+    if (eDevice >= ADI_TMR_DEVICE_NUM) {
+        return ADI_TMR_BAD_DEVICE_NUM;
+    } /* ENDIF */
+    /* IF(The timer is already running) */
+    if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_EN) == BITM_TMR_RGB_CTL_EN) {
+        return ADI_TMR_OPERATION_NOT_ALLOWED;
+    } /* ENDIF */         
+#endif
+    /* Setup the callback function */
+    adi_tmr_callbacks [eDevice] = pfCallback;
+    adi_tmr_parameters[eDevice] = pCBParam;
+
+    /* IF(Enable interrupt) */
+    if (bEnableInt == true) {
+        NVIC_EnableIRQ(adi_tmr_interrupt[eDevice]);
+    /* ELSE(Disable interrupt) */
+    } else {
+        NVIC_DisableIRQ(adi_tmr_interrupt[eDevice]);
+    } /* ENDIF */
+
+    /* Static configuration */
+    adi_tmr_registers[eDevice]->CTL           = aTimerCtlConfig     [eDevice];
+    adi_tmr_registers[eDevice]->LOAD          = aTimerLoadConfig    [eDevice];
+    adi_tmr_registers[eDevice]->ALOAD         = aTimerALoadConfig   [eDevice];
+    adi_tmr_registers[eDevice]->PWM0CTL       = aTimerPwmCtlConfig  [eDevice];
+    adi_tmr_registers[eDevice]->PWM0MATCH     = aTimerPwmMatchConfig[eDevice];
+#if defined(__ADUCM4x50__)
+    adi_tmr_registers[eDevice]->EVENTSELECT   = aTimerEventConfig   [eDevice];
+
+    /* IF(Initializing the RGB timer, there are 2 other PWM outputs to configure) */
+    if (eDevice == ADI_TMR_DEVICE_RGB) { 
+        /* The array is bumped by 1 to get to the 5th entry in the static config array, which contains RGB PWM1 */
+        adi_tmr_registers[eDevice]->PWM1CTL   = aTimerPwmCtlConfig  [eDevice+1u];
+        adi_tmr_registers[eDevice]->PWM1MATCH = aTimerPwmMatchConfig[eDevice+1u];
+        /* The array is bumped by 2 to get to the 6th entry in the static config array, which contains RGB PWM2 */
+        adi_tmr_registers[eDevice]->PWM2CTL   = aTimerPwmCtlConfig  [eDevice+2u];        
+        adi_tmr_registers[eDevice]->PWM2MATCH = aTimerPwmMatchConfig[eDevice+2u];
+    } /* ENDIF */
+#endif /*__ADUCM4x50__*/
+
+    return ADI_TMR_SUCCESS;
+}
+
+
+/*!
+ * @brief       Configure GP or RGB Timer
+ *
+ * @details     Configure the basic hardware timer parameters.
+ *
+ * @note        This function can only be called when the timer is disabled.
+ *
+ * @param [in]  eDevice : Device number
+ *
+ * @param [in]  timerConfig : Timer configuration structure, filled by user prior to function call
+ *
+ * @return      ADI_TMR_RESULT
+ *                - #ADI_TMR_BAD_DEVICE_NUM           [D] Invalid eDevice parameter supplied
+ *                - #ADI_TMR_BAD_RELOAD_CONFIGURATION [D] bPeriodic is false and bReloading is true
+ *                - #ADI_TMR_OPERATION_NOT_ALLOWED    [D] Timer is currently running
+ *                - #ADI_TMR_DEVICE_BUSY                  Timer is busy processing a previous control register write
+ *                - #ADI_TMR_SUCCESS                      Function call completed successfully
+ *
+ */
+ADI_TMR_RESULT adi_tmr_ConfigTimer(ADI_TMR_DEVICE const eDevice, ADI_TMR_CONFIG* timerConfig) {
+    uint16_t nTemp;
+#ifdef ADI_DEBUG
+    /* IF(Bad device input parameter) */
+    if (eDevice >= ADI_TMR_DEVICE_NUM) {
+        return ADI_TMR_BAD_DEVICE_NUM;
+    } /* ENDIF */
+    /* IF(Bad configuration, cannot enable reloading while in free running mode) */
+    if ((timerConfig->bPeriodic == false) && (timerConfig->bReloading == true)) {
+        return ADI_TMR_BAD_RELOAD_CONFIGURATION;
+    } /* ENDIF */
+    /* IF(The timer is already running) */
+    if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_EN) == BITM_TMR_RGB_CTL_EN) {
+        return ADI_TMR_OPERATION_NOT_ALLOWED;
+    } /* ENDIF */
+#endif
+    /* Set the load registers */
+    adi_tmr_registers[eDevice]->LOAD  = timerConfig->nLoad;
+    adi_tmr_registers[eDevice]->ALOAD = timerConfig->nAsyncLoad;
+
+    /* IF(Busy bit does not clear after waiting) */
+    if (ADI_TMR_SUCCESS != WaitForStatusBit(eDevice, (uint16_t) BITM_TMR_RGB_STAT_BUSY)) {
+        return ADI_TMR_DEVICE_BUSY; 
+    } /* ENDIF */
+
+    /* Read the control register and clear everything aside to the event capture bits, which are the only fields not set in this function */
+    nTemp  = adi_tmr_registers[eDevice]->CTL;
+    nTemp &= (uint16_t) (BITM_TMR_RGB_CTL_EVTEN | BITM_TMR_RGB_CTL_RSTEN );  
+
+    /* Setup the prescaler and the clock source */
+    nTemp |=  (uint16_t)(((uint16_t) timerConfig->ePrescaler  ) << BITP_TMR_RGB_CTL_PRE);
+    nTemp |=  (uint16_t)(((uint16_t) timerConfig->eClockSource) << BITP_TMR_RGB_CTL_CLK);
+
+    /* IF(Periodic mode) */
+    if (timerConfig->bPeriodic == true) {
+        nTemp |= (1u << BITP_TMR_RGB_CTL_MODE);
+    } /* ENDIF */    
+    
+    /* IF(Counting up) */
+    if (timerConfig->bCountingUp == true) {
+        nTemp |= (1u << BITP_TMR_RGB_CTL_UP);
+    } /* ENDIF */
+    
+    /* IF(Reloading is enabled) */
+    if (timerConfig->bReloading == true) {
+        nTemp |= (1u << BITP_TMR_RGB_CTL_RLD);
+    } /* ENDIF */
+    
+    /* IF(Sync bypass is enabled) */
+    if (timerConfig->bSyncBypass == true) {
+        nTemp |= (1u << BITP_TMR_RGB_CTL_SYNCBYP);
+    } /* ENDIF */
+    
+    /* Update the control register with the new configuration */
+    adi_tmr_registers[eDevice]->CTL = nTemp;
+
+    return ADI_TMR_SUCCESS;
+}
+
+
+/*!
+ * @brief       Setup GP or RGB Timer Event Capture
+ *
+ * @details     The timer can be configured to capture the timer value when a specific event occurs. The
+ *              list of events can be found in the hardware reference manual. The callback function specified
+ *              in #adi_tmr_Init will be supplied #ADI_TMR_EVENT_CAPTURE to indicate the event occured. The 
+ *              user can then read the captured value by calling #adi_tmr_GetCaptureCount.
+ *
+ * @note        This function can only be called when the timer is disabled.
+ *
+ * @param [in]  eDevice : Device number
+ *
+ * @param [in]  eventConfig : Event configuration structure, filled by user prior to function call
+ *
+ * @return      ADI_TMR_RESULT
+ *                - #ADI_TMR_BAD_DEVICE_NUM        [D] Invalid eDevice parameter supplied
+ *                - #ADI_TMR_BAD_EVENT_ID          [D] Event ID was not out of the valid range [0,#ADI_TMR_NUM_EVENTS]
+ *                - #ADI_TMR_OPERATION_NOT_ALLOWED [D] Timer is currently running
+ *                - #ADI_TMR_DEVICE_BUSY               Timer is busy processing a previous control register write
+ *                - #ADI_TMR_SUCCESS                   Function call completed successfully
+ *
+ */
+ADI_TMR_RESULT adi_tmr_ConfigEvent(ADI_TMR_DEVICE const eDevice, ADI_TMR_EVENT_CONFIG* eventConfig) {
+#ifdef ADI_DEBUG
+    /* IF(Bad device input parameter) */
+    if (eDevice >= ADI_TMR_DEVICE_NUM) {
+        return ADI_TMR_BAD_DEVICE_NUM;
+    } /* ENDIF */
+    /* IF(Bad event input parameter) */
+    if (eventConfig->nEventID >= ADI_TMR_NUM_EVENTS) {
+        return ADI_TMR_BAD_EVENT_ID;
+    } /* ENDIF */
+    /* IF(The timer is already running) */
+    if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_EN) == BITM_TMR_RGB_CTL_EN) {
+        return ADI_TMR_OPERATION_NOT_ALLOWED;
+    } /* ENDIF */        
+#endif
+
+#if defined(__ADUCM4x50__)
+    /* Set the event number */
+    adi_tmr_registers[eDevice]->EVENTSELECT = (uint16_t) eventConfig->nEventID;
+#endif
+    
+    /* IF(Busy bit does not clear after waiting) */
+    if (ADI_TMR_SUCCESS != WaitForStatusBit(eDevice, (uint16_t) BITM_TMR_RGB_STAT_BUSY)) {
+        return ADI_TMR_DEVICE_BUSY; 
+    } /* ENDIF */
+
+    /* Clear the event enable bit and keep the other bits */
+    adi_tmr_registers[eDevice]->CTL &= (uint16_t) ~(BITM_TMR_RGB_CTL_EVTEN | BITM_TMR_RGB_CTL_RSTEN );
+
+    /* IF(Turning event capture on) */
+    if (eventConfig->bEnable == true) {
+        adi_tmr_registers[eDevice]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_EVTEN;
+    } /* ENDIF */
+
+    /* IF(Enabling reset on event capture) */
+    if (eventConfig->bPrescaleReset == true) {
+        adi_tmr_registers[eDevice]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_RSTEN;
+    } /* ENDIF */
+
+#if defined(__ADUCM302x__)
+    /* Write the event index */
+    adi_tmr_registers[eDevice]->CTL |= (uint16_t) (((uint16_t) eventConfig->nEventID) << BITP_TMR_CTL_EVTRANGE);
+#endif
+    
+    return ADI_TMR_SUCCESS;
+}
+
+
+/*!
+ * @brief       Setup GP or RGB Timer Pulse Width Modulation
+ *
+ * @details     The timer can be configured to generate a pulse width modulation output signal.
+ *              The period of this signal is simply determined by the period of timer. The duty
+ *              cycle will be 50% in toggle mode, or can be configured by the user for a different
+ *              value using the match value. The pulse will toggle when the timer count matches
+ *              the match value. The user can also specify the polarity of the signal by choosing
+ *              if the signal idles low or high. GPIO muxing will be required to use the PWM output.
+ *
+ * @note        This function can only be called when the timer is disabled.
+ *
+ * @param [in]  eDevice : Device number
+ *
+ * @param [in]  pwmConfig : PWM configuration structure, filled by user prior to function call
+ *
+ * @return      ADI_TMR_RESULT
+ *                - #ADI_TMR_BAD_DEVICE_NUM          [D] Invalid eDevice parameter supplied
+ *                - #ADI_TMR_OPERATION_NOT_ALLOWED   [D] Timer is currently running
+ *                - #ADI_TMR_BAD_PWM_NUM             [D] Invalid eOutput parameter supplied
+ *                - #ADI_TMR_SUCCESS                     Function call completed successfully
+ *
+ */
+ADI_TMR_RESULT adi_tmr_ConfigPwm(ADI_TMR_DEVICE const eDevice, ADI_TMR_PWM_CONFIG* pwmConfig) {
+    uint16_t nControl = 0u;
+#ifdef ADI_DEBUG
+    /* IF(Bad device input parameter) */
+    if (eDevice >= ADI_TMR_DEVICE_NUM) {
+        return ADI_TMR_BAD_DEVICE_NUM;
+    } /* ENDIF */
+    /* IF(The timer is already running) */
+    if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_EN) == BITM_TMR_RGB_CTL_EN) {
+        return ADI_TMR_OPERATION_NOT_ALLOWED;
+    } /* ENDIF */
+#if defined(__ADUCM4x50__)
+    /* IF(Bad PWM output and device combo OR bad PWM output) */
+    if (((eDevice != ADI_TMR_DEVICE_RGB) && (pwmConfig->eOutput != ADI_TMR_PWM_OUTPUT_0)) || (pwmConfig->eOutput >= ADI_TMR_PWM_OUTPUT_NUM)) {
+        return ADI_TMR_BAD_PWM_NUM;
+    } /* ENDIF */
+#endif
+#endif
+    /* IF(Idle high is set) */
+    if (pwmConfig->bIdleHigh == true) {
+        nControl = (1u << ((uint16_t) BITP_TMR_RGB_PWM0CTL_IDLESTATE));
+    } /* ENDIF */
+ 
+    /* IF(Match mode is enabled) */
+    if (pwmConfig->bMatch == true) {
+        nControl |= (1u << ((uint16_t) BITP_TMR_RGB_PWM0CTL_MATCH));
+    } /* ENDIF */    
+    
+    /* IF(PWM output 0) */
+    if (pwmConfig->eOutput == ADI_TMR_PWM_OUTPUT_0) {
+        adi_tmr_registers[eDevice]->PWM0CTL   = nControl;
+        adi_tmr_registers[eDevice]->PWM0MATCH = pwmConfig->nMatchValue;
+    }
+#if defined(__ADUCM4x50__)	
+    /* IF(PWM output 1) */
+      else if (pwmConfig->eOutput == ADI_TMR_PWM_OUTPUT_1) {
+        adi_tmr_registers[eDevice]->PWM1CTL   = nControl;
+        adi_tmr_registers[eDevice]->PWM1MATCH = pwmConfig->nMatchValue;     
+    /* ELSE(PWM output 2) */
+    } else {
+        adi_tmr_registers[eDevice]->PWM2CTL   = nControl;
+        adi_tmr_registers[eDevice]->PWM2MATCH = pwmConfig->nMatchValue;
+    } /* ENDIF */
+#endif
+    return ADI_TMR_SUCCESS;
+}
+
+
+/*!
+ * @brief       Enable or Disable the GP or RGB Timer
+ *
+ * @details     Start or stop the timer.
+ *
+ * @param [in]  eDevice : Device number
+ *
+ * @param [in]  bEnable : True to enable, false to disable
+ *
+ * @return      ADI_TMR_RESULT
+ *                - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied
+ *                - #ADI_TMR_DEVICE_BUSY        Timer is busy processing a previous control register write
+ *                - #ADI_TMR_SUCCESS            Function call completed successfully
+ *
+ */
+ADI_TMR_RESULT adi_tmr_Enable(ADI_TMR_DEVICE const eDevice, bool bEnable) {
+#ifdef ADI_DEBUG
+    /* IF(Bad device input parameter) */
+    if (eDevice >= ADI_TMR_DEVICE_NUM) {
+        return ADI_TMR_BAD_DEVICE_NUM;
+    } /* ENDIF */
+#endif
+    /* IF(Busy bit does not clear after waiting) */
+    if (ADI_TMR_SUCCESS != WaitForStatusBit(eDevice, (uint16_t) BITM_TMR_RGB_STAT_BUSY)) {
+        return ADI_TMR_DEVICE_BUSY; 
+    } /* ENDIF */
+
+    /* Clear the enable bit and keep the other bits */
+    adi_tmr_registers[eDevice]->CTL &= (uint16_t) ~BITM_TMR_RGB_CTL_EN;
+
+    /* IF(Turning the timer on) */
+    if (bEnable == true) {
+        adi_tmr_registers[eDevice]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_EN;
+    } /* ENDIF */
+
+    return ADI_TMR_SUCCESS;
+}
+
+
+/*!
+ * @brief       Get GP or RGB Timer Current Count
+ *
+ * @details     Read the timer.
+ *
+ * @param [in]  eDevice : Device number
+ *
+ * @param [out] pCount : Pointer to the result.
+ *
+ * @return      ADI_TMR_RESULT
+ *                - #ADI_TMR_BAD_DEVICE_NUM [D]      Invalid eDevice parameter supplied
+ *                - #ADI_TMR_NULL_POINTER   [D]      Invalid pCount parameter supplied
+ *                - #ADI_TMR_SUCCESS                 Function call completed successfully
+ *
+ */
+ADI_TMR_RESULT adi_tmr_GetCurrentCount(ADI_TMR_DEVICE const eDevice, uint16_t *pCount) {
+#ifdef ADI_DEBUG
+    /* IF(Bad device input parameter) */
+    if (eDevice >= ADI_TMR_DEVICE_NUM) {
+        return ADI_TMR_BAD_DEVICE_NUM;
+    } /* ENDIF */
+    /* IF(Null pointer) */
+    if (pCount == NULL) {
+        return ADI_TMR_NULL_POINTER; 
+    } /* ENDIF */
+#endif
+    *pCount = adi_tmr_registers[eDevice]->CURCNT;
+    return ADI_TMR_SUCCESS;
+}
+
+
+/*!
+ * @brief       Get GP or RGB Timer Captured Count
+ *
+ * @details     Read the captured timer value. This should be called after the callback function
+ *              is called with #ADI_TMR_EVENT_CAPTURE in the Event field.
+ *
+ * @param [in]  eDevice : Device number
+ *
+ * @param [out] pCount : Pointer to the result.
+ *
+ * @return      ADI_TMR_RESULT
+ *                - #ADI_TMR_BAD_DEVICE_NUM [D]      Invalid eDevice parameter supplied
+ *                - #ADI_TMR_NULL_POINTER   [D]      Invalid pCount parameter supplied
+ *                - #ADI_TMR_SUCCESS                 Function call completed successfully
+ *
+ */
+ADI_TMR_RESULT adi_tmr_GetCaptureCount(ADI_TMR_DEVICE const eDevice, uint16_t *pCount) {
+#ifdef ADI_DEBUG
+    /* IF(Bad device input parameter) */
+    if (eDevice >= ADI_TMR_DEVICE_NUM) {
+        return ADI_TMR_BAD_DEVICE_NUM;
+    } /* ENDIF */
+    /* IF(Null pointer) */
+    if (pCount == NULL) {
+        return ADI_TMR_NULL_POINTER; 
+    } /* ENDIF */
+#endif
+    *pCount = adi_tmr_registers[eDevice]->CAPTURE;
+    return ADI_TMR_SUCCESS;
+}
+
+
+/*!
+ * @brief       Reload GP or RGB Timer
+ *
+ * @details     Only relevent in peridic mode and when bReloading was set to 
+ *              true when configuring the timer. Calling this function will
+ *              reload (i.e. reset) the timer to the LOAD value.
+ *
+ * @param [in]  eDevice : Device number
+ *
+ * @return      ADI_TMR_RESULT
+ *                - #ADI_TMR_BAD_DEVICE_NUM  [D]     Invalid eDevice parameter supplied
+ *                - #ADI_TMR_RELOAD_DISABLED [D]     Reloading not enabled for this timer
+ *                - #ADI_TMR_DEVICE_BUSY             Reload did not take effect in time
+ *                - #ADI_TMR_SUCCESS                 Function call completed successfully
+ *
+ */
+ADI_TMR_RESULT adi_tmr_Reload(ADI_TMR_DEVICE const eDevice) {
+#ifdef ADI_DEBUG
+    /* IF(Bad device input parameter) */
+    if (eDevice >= ADI_TMR_DEVICE_NUM) {
+        return ADI_TMR_BAD_DEVICE_NUM;
+    } /* ENDIF */
+    /* IF(Reloading has not been enabled) */
+    if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_RLD) != BITM_TMR_RGB_CTL_RLD) {
+        return ADI_TMR_RELOAD_DISABLED;
+    } /* ENDIF */
+#endif
+    /* Clear the timeout bit to cause a reload to happen */
+    adi_tmr_registers[eDevice]->CLRINT = BITM_TMR_RGB_CLRINT_TIMEOUT;
+    /* IF(The clear interrupt does not take effect in a reasonable amount of time) */
+    if (ADI_TMR_SUCCESS != WaitForStatusBit(eDevice, (uint16_t) BITM_TMR_RGB_STAT_PDOK)) {
+        return ADI_TMR_DEVICE_BUSY; 
+    } /* ENDIF */    
+    return ADI_TMR_SUCCESS;
+}
+
+
+/*********************************************************************************
+                                   PRIVATE FUNCTIONS
+*********************************************************************************/
+
+ /*! \cond PRIVATE */
+
+static ADI_TMR_RESULT WaitForStatusBit(ADI_TMR_DEVICE const eDevice, uint16_t nBusyBit) {
+    /* FOR(Number of arbitrary iterations) */
+    for (uint16_t i = 0u; i < 1000u; i++) { 
+            /* IF(Busy bit is low) */
+            if ((adi_tmr_registers[(eDevice)]->STAT & nBusyBit) == ((uint16_t) 0u)) {
+                return ADI_TMR_SUCCESS;
+            } /* ENDIF */
+    } /* ENDFOR */
+    return ADI_TMR_DEVICE_BUSY;
+}
+
+static void CommonIntHandler(ADI_TMR_DEVICE const eDevice) {
+    /* Read status register */
+    uint16_t IntStatus = adi_tmr_registers[eDevice]->STAT;
+    /* IF(Callback function has been set) */
+    if(adi_tmr_callbacks[eDevice] != NULL) {
+        /* IF(Timeout interrupt occurred) */
+        if((IntStatus & ((uint16_t) BITM_TMR_RGB_STAT_TIMEOUT)) != ((uint16_t) 0u)) {
+            adi_tmr_callbacks[eDevice](adi_tmr_parameters[eDevice], ADI_TMR_EVENT_TIMEOUT, NULL);
+        } /* ENDIF */
+        /* IF(Event capture interrupt occurred) */
+        if((IntStatus & ((uint16_t) BITM_TMR_RGB_STAT_CAPTURE)) != ((uint16_t) 0u)) {
+            adi_tmr_callbacks[eDevice](adi_tmr_parameters[eDevice], ADI_TMR_EVENT_CAPTURE, NULL);
+        } /* ENDIF */
+    } /* ENDIF */
+    /* Clear pending interrupt */
+    adi_tmr_registers[eDevice]->CLRINT = (BITM_TMR_RGB_CLRINT_EVTCAPT | BITM_TMR_RGB_CLRINT_TIMEOUT);
+}
+
+void GP_Tmr0_Int_Handler(void) {
+    ISR_PROLOG()
+    CommonIntHandler(ADI_TMR_DEVICE_GP0);
+    ISR_EPILOG()
+}
+
+void GP_Tmr1_Int_Handler(void) {
+    ISR_PROLOG()
+    CommonIntHandler(ADI_TMR_DEVICE_GP1);
+    ISR_EPILOG()
+}
+
+void GP_Tmr2_Int_Handler(void) {
+    ISR_PROLOG()
+    CommonIntHandler(ADI_TMR_DEVICE_GP2);
+    ISR_EPILOG()
+}
+
+#if defined(__ADUCM4x50__)
+void RGB_Tmr_Int_Handler(void) {
+    ISR_PROLOG()
+    CommonIntHandler(ADI_TMR_DEVICE_RGB);
+    ISR_EPILOG()
+}
+#endif
+/*! \endcond */
+
+/*! @} */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr_data.c
new file mode 100755
index 00000000000..22e656b56cf
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr_data.c
@@ -0,0 +1,194 @@
+/*! *****************************************************************************
+ * @file    adi_tmr_data.c
+ * @brief   GP and RGB timer static configuration data
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+
+#ifndef ADI_TMR_DATA
+#define ADI_TMR_DATA
+
+
+#include <stdlib.h>
+#include <adi_tmr_config.h>
+#include <drivers/tmr/adi_tmr.h>
+#include <adi_processor.h>
+
+/* Macro mapping from ADuCM4x50 to ADuCM302x */
+#if defined(__ADUCM302x__)
+#define BITM_TMR_RGB_CTL_EN             BITM_TMR_CTL_EN
+#define PWM0CTL                         PWMCTL
+#define PWM0MATCH                       PWMMATCH
+#define BITM_TMR_RGB_STAT_BUSY          BITM_TMR_STAT_BUSY
+#define BITM_TMR_RGB_CTL_EVTEN          BITM_TMR_CTL_EVTEN
+#define BITM_TMR_RGB_CTL_RSTEN          BITM_TMR_CTL_RSTEN
+#define BITP_TMR_RGB_CTL_RSTEN          BITP_TMR_CTL_RSTEN
+#define BITP_TMR_RGB_CTL_EVTEN          BITP_TMR_CTL_EVTEN
+#define BITP_TMR_RGB_CTL_PRE            BITP_TMR_CTL_PRE
+#define BITP_TMR_RGB_CTL_CLK            BITP_TMR_CTL_CLK
+#define BITP_TMR_RGB_CTL_MODE           BITP_TMR_CTL_MODE
+#define BITP_TMR_RGB_CTL_UP             BITP_TMR_CTL_UP
+#define BITP_TMR_RGB_CTL_RLD            BITP_TMR_CTL_RLD
+#define BITP_TMR_RGB_CTL_SYNCBYP        BITP_TMR_CTL_SYNCBYP
+#define BITP_TMR_RGB_PWM0CTL_IDLESTATE  BITP_TMR_PWMCTL_IDLESTATE
+#define BITP_TMR_RGB_PWM0CTL_MATCH      BITP_TMR_PWMCTL_MATCH
+#define BITM_TMR_RGB_CLRINT_TIMEOUT     BITM_TMR_CLRINT_TIMEOUT
+#define BITM_TMR_RGB_STAT_PDOK          BITM_TMR_STAT_PDOK
+#define BITM_TMR_RGB_STAT_TIMEOUT       BITM_TMR_STAT_TIMEOUT
+#define BITM_TMR_RGB_STAT_CAPTURE       BITM_TMR_STAT_CAPTURE
+#define BITM_TMR_RGB_CLRINT_EVTCAPT     BITM_TMR_CLRINT_EVTCAPT
+#define BITM_TMR_RGB_CLRINT_TIMEOUT     BITM_TMR_CLRINT_TIMEOUT
+#define BITM_TMR_RGB_CTL_RLD            BITM_TMR_CTL_RLD
+#endif /*__ADUCM302x__*/
+
+/* CTL register static configuration */
+static uint16_t aTimerCtlConfig[] =
+{
+    (TMR0_CFG_COUNT_UP              << BITP_TMR_RGB_CTL_UP)      |
+    (TMR0_CFG_MODE                  << BITP_TMR_RGB_CTL_MODE)    |
+    (TMR0_CFG_PRESCALE_FACTOR       << BITP_TMR_RGB_CTL_PRE)     |
+    (TMR0_CFG_CLOCK_SOURCE          << BITP_TMR_RGB_CTL_CLK)     |
+    (TMR0_CFG_ENABLE_RELOADING      << BITP_TMR_RGB_CTL_RLD)     |
+    (TMR0_CFG_ENABLE_SYNC_BYPASS    << BITP_TMR_RGB_CTL_SYNCBYP) |
+    (TMR0_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN)   |
+    (TMR0_CFG_ENABLE_EVENT_CAPTURE  << BITP_TMR_RGB_CTL_EVTEN),
+
+    (TMR1_CFG_COUNT_UP              << BITP_TMR_RGB_CTL_UP)      |
+    (TMR1_CFG_MODE                  << BITP_TMR_RGB_CTL_MODE)    |
+    (TMR1_CFG_PRESCALE_FACTOR       << BITP_TMR_RGB_CTL_PRE)     |
+    (TMR1_CFG_CLOCK_SOURCE          << BITP_TMR_RGB_CTL_CLK)     |
+    (TMR1_CFG_ENABLE_RELOADING      << BITP_TMR_RGB_CTL_RLD)     |
+    (TMR1_CFG_ENABLE_SYNC_BYPASS    << BITP_TMR_RGB_CTL_SYNCBYP) |
+    (TMR1_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN)   |
+    (TMR1_CFG_ENABLE_EVENT_CAPTURE  << BITP_TMR_RGB_CTL_EVTEN),
+
+    (TMR2_CFG_COUNT_UP              << BITP_TMR_RGB_CTL_UP)      |
+    (TMR2_CFG_MODE                  << BITP_TMR_RGB_CTL_MODE)    |
+    (TMR2_CFG_PRESCALE_FACTOR       << BITP_TMR_RGB_CTL_PRE)     |
+    (TMR2_CFG_CLOCK_SOURCE          << BITP_TMR_RGB_CTL_CLK)     |
+    (TMR2_CFG_ENABLE_RELOADING      << BITP_TMR_RGB_CTL_RLD)     |
+    (TMR2_CFG_ENABLE_SYNC_BYPASS    << BITP_TMR_RGB_CTL_SYNCBYP) |
+    (TMR2_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN)   |
+    (TMR2_CFG_ENABLE_EVENT_CAPTURE  << BITP_TMR_RGB_CTL_EVTEN),
+
+#if defined(__ADUCM4x50__)
+    (TMR3_CFG_COUNT_UP              << BITP_TMR_RGB_CTL_UP)      |
+    (TMR3_CFG_MODE                  << BITP_TMR_RGB_CTL_MODE)    |
+    (TMR3_CFG_PRESCALE_FACTOR       << BITP_TMR_RGB_CTL_PRE)     |
+    (TMR3_CFG_CLOCK_SOURCE          << BITP_TMR_RGB_CTL_CLK)     |
+    (TMR3_CFG_ENABLE_RELOADING      << BITP_TMR_RGB_CTL_RLD)     |
+    (TMR3_CFG_ENABLE_SYNC_BYPASS    << BITP_TMR_RGB_CTL_SYNCBYP) |
+    (TMR3_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN)   |
+    (TMR3_CFG_ENABLE_EVENT_CAPTURE  << BITP_TMR_RGB_CTL_EVTEN),
+#endif
+};
+
+/* LOAD register static configuration */
+static uint16_t aTimerLoadConfig[] =
+{
+    TMR0_CFG_LOAD_VALUE,
+    TMR1_CFG_LOAD_VALUE,
+    TMR2_CFG_LOAD_VALUE,
+#if defined(__ADUCM4x50__)
+    TMR3_CFG_LOAD_VALUE,
+#endif
+};
+
+/* Asynchronous LOAD static configuraton */
+static uint16_t aTimerALoadConfig[] =
+{
+    TMR0_CFG_ASYNC_LOAD_VALUE,
+    TMR1_CFG_ASYNC_LOAD_VALUE,
+    TMR2_CFG_ASYNC_LOAD_VALUE,
+#if defined(__ADUCM4x50__)
+    TMR3_CFG_ASYNC_LOAD_VALUE,
+#endif
+};
+
+/* EVENTSELECT static configuration */
+#if defined(__ADUCM4x50__)
+static uint16_t aTimerEventConfig[] =
+{
+    TMR0_CFG_EVENT_CAPTURE,
+    TMR1_CFG_EVENT_CAPTURE,
+    TMR2_CFG_EVENT_CAPTURE,
+    TMR3_CFG_EVENT_CAPTURE,
+};
+#endif
+
+/* PWM CTL static configuration */
+static uint16_t aTimerPwmCtlConfig[] =
+{
+  (TMR0_CFG_PWM0_IDLE_STATE  << BITP_TMR_RGB_PWM0CTL_IDLESTATE) |
+  (TMR0_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH),
+
+  (TMR1_CFG_PWM0_IDLE_STATE  << BITP_TMR_RGB_PWM0CTL_IDLESTATE) |
+  (TMR1_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH),
+
+  (TMR2_CFG_PWM0_IDLE_STATE  << BITP_TMR_RGB_PWM0CTL_IDLESTATE) |
+  (TMR2_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH),
+
+#if defined(__ADUCM4x50__)
+  (TMR3_CFG_PWM0_IDLE_STATE  << BITP_TMR_RGB_PWM0CTL_IDLESTATE) |
+  (TMR3_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH),
+
+  (TMR3_CFG_PWM1_IDLE_STATE  << BITP_TMR_RGB_PWM1CTL_IDLESTATE) |
+  (TMR3_CFG_PWM1_MATCH_VALUE << BITP_TMR_RGB_PWM1CTL_MATCH),
+
+  (TMR3_CFG_PWM2_IDLE_STATE  << BITP_TMR_RGB_PWM2CTL_IDLESTATE) |
+  (TMR3_CFG_PWM2_MATCH_VALUE << BITP_TMR_RGB_PWM2CTL_MATCH),
+#endif
+};
+
+/* PWM MATCH static configuration */
+static uint16_t aTimerPwmMatchConfig[] = {
+  TMR0_CFG_PWM0_MATCH_VALUE,
+  TMR1_CFG_PWM0_MATCH_VALUE,
+  TMR2_CFG_PWM0_MATCH_VALUE,
+#if defined(__ADUCM4x50__)
+  TMR3_CFG_PWM0_MATCH_VALUE,
+  TMR3_CFG_PWM1_MATCH_VALUE,
+  TMR3_CFG_PWM2_MATCH_VALUE
+#endif
+};
+
+
+#endif /* ADI_TMR_DATA */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart.c
new file mode 100755
index 00000000000..f0dc346bfa1
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart.c
@@ -0,0 +1,2797 @@
+/*! *****************************************************************************
+ * @file:     adi_uart.c
+ * @brief:    uart device driver implementation
+ * @details:  This file contains the UART device driver functions
+ -----------------------------------------------------------------------------
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+/** @addtogroup UART_Driver
+ *  @{
+ *  @brief UART Driver
+ *  @note The application must include drivers/uart/adi_uart.h to use this
+ *  driver
+ *  @note This driver requires the DMA driver.The application must
+ *  include the DMA driver sources to avoid link errors.
+ */
+
+/*!  \cond PRIVATE */
+#include <drivers/uart/adi_uart.h>
+#include <drivers/dma/adi_dma.h>
+#include "adi_uart_def.h"
+#include <adi_cyclecount.h>
+
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm50: (MISRA C 2004 rule 14.3): a null statement shall only occur on a line by itself,
+*                                 and shall not have any other text on the same line
+*                                 Some Macros, such as ISR_PROLOGUE, may not have any expansion
+*                                 resulting in just the terminating ';'.
+*
+* Pm073 (rule 14.7): A function should have a single point of exit.
+* Pm143 (rule 14.7): A function should have a single point of exit at the end of the function.
+*                    Multiple returns are used for error handling.
+*
+* Pm088 (rule 17.4): Pointer arithmetic should not be used.
+*                    Relying on pointer arithmetic for buffer handling.
+*
+* Pm123 (rule 18.5): There shall be no definition of objects in a header file.
+*
+* Pm140 (rule 11.3): A cast should not be performed between a pointer type and an integral type.
+*                    MMR addresses are defined as simple constants. Accessing the MMR requires casting to a pointer type.
+*
+* Pm152 (rule 17.4): Array indexing shall only be applied to objects defined as an array type.
+*                    Relying on pointer arithmetic for buffer handling and
+*                    Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors.
+*
+* Pm008: Code should not be commented out.
+         This code was commented out to show what the autobaud equations would look like if there were floating point precision.
+         Ideally this would be the case but for the sake of footprint size we will leave it at single point precision.
+*/
+#pragma diag_suppress=Pm050,Pm073,Pm088,Pm123,Pm140,Pm143,Pm152,Pm008
+#endif /* __ICCARM__ */
+
+
+
+
+/**********************************************************
+ * UART Data
+ **********************************************************/
+static  ADI_UART_DEVICE_INFO uart_device_info[ ] =
+{
+  {
+    UART0_TX_CHANn,             /*!< DMA channel number for UART0 Tx. */
+    UART0_RX_CHANn,             /*!< DMA channel number for UART0 Rx. */
+    DMA0_CH8_DONE_IRQn,         /*!< DMA channel IRQ for UART0 Tx.    */
+    DMA0_CH9_DONE_IRQn,         /*!< DMA channel IRQ for UART0 Rx.    */
+    (IRQn_Type)INTR_UART0_EVT,  /*!< UART0 interrupt ID.              */
+    pADI_UART0,                 /*!< Start address of UART0.          */
+    NULL                        /*!< Device Handle for UART0.         */
+  },
+#if defined (__ADUCM4x50__)
+  {
+    UART1_TX_CHANn,             /*!< DMA channel number for UART1 Tx. */
+    UART1_RX_CHANn,             /*!< DMA channel number for UART1 Rx. */
+    DMA0_CH25_DONE_IRQn,        /*!< DMA channel IRQ for UART1 Tx.    */
+    DMA0_CH26_DONE_IRQn,        /*!< DMA channel IRQ for UART1 Rx.    */
+    (IRQn_Type)INTR_UART1_EVT,  /*!< UART1 interrupt ID.              */
+    pADI_UART1,                 /*!< Start address of UART1.          */
+    NULL                        /*!< Device Handle for UART1.         */
+  },
+#endif /* __ADUCM4x50 */ 
+};
+
+static const ADI_UART_CONFIG gUARTCfg[ ] =
+{
+    {
+      /* Line control register.                                         */
+      ((ADI_UART0_CFG_WORD_LENGTH          << BITP_UART_LCR_WLS)  |
+       (ADI_UART0_CFG_STOP_BIT             << BITP_UART_LCR_STOP) |
+       (ADI_UART0_CFG_ENABLE_PARITY        << BITP_UART_LCR_PEN)  |
+       (ADI_UART0_CFG_PARITY_SELECTION     << BITP_UART_LCR_EPS)  |
+       (ADI_UART0_CFG_ENABLE_STICKY_PARITY << BITP_UART_LCR_SP)),
+
+      /* Div-C in baudrate divider register.                            */
+      ADI_UART0_CFG_DIVC,
+
+      /* Div-M and Div-N in fractional baudrate Register.               */
+      (((uint32_t)ADI_UART0_CFG_DIVN       << BITP_UART_FBR_DIVN) |
+       ((uint32_t)ADI_UART0_CFG_DIVM       << BITP_UART_FBR_DIVM) |
+       ((uint32_t)BITM_UART_FBR_FBEN)),
+
+      /* Over sample rate in second line control register.              */
+      ADI_UART0_CFG_OSR,
+
+      /* FIFO control register.                                         */
+      ((ADI_UART0_CFG_ENABLE_FIFO          << BITP_UART_FCR_FIFOEN)|
+       (ADI_UART0_CFG_TRIG_LEVEL           << BITP_UART_FCR_RFTRIG)),
+
+      /* Half duplex control register.                                  */
+      ((ADI_UART0_CFG_SOUT_POLARITY        << BITP_UART_RSC_OENP)  |
+       (ADI_UART0_CFG_DEASSERTION          << BITP_UART_RSC_OENSP) |
+       (ADI_UART0_CFG_DISABLE_RX           << BITP_UART_RSC_DISRX) |
+       (ADI_UART0_CFG_HOLD_TX              << BITP_UART_RSC_DISTX)),
+
+      /* Interrupt enable register.                                     */
+      ((ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT << BITP_UART_IEN_EDSSI) |
+      (ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT     << BITP_UART_IEN_ELSI))
+
+    },
+#if defined (__ADUCM4x50__)
+    {
+      /* Line control register.                                         */
+      ((ADI_UART1_CFG_WORD_LENGTH          << BITP_UART_LCR_WLS)  |
+       (ADI_UART1_CFG_STOP_BIT             << BITP_UART_LCR_STOP) |
+       (ADI_UART1_CFG_ENABLE_PARITY        << BITP_UART_LCR_PEN)  |
+       (ADI_UART1_CFG_PARITY_SELECTION     << BITP_UART_LCR_EPS)  |
+       (ADI_UART1_CFG_ENABLE_STICKY_PARITY << BITP_UART_LCR_SP)),
+
+      /* Div-C in Baudrate divider register.                            */
+      ADI_UART1_CFG_DIVC,
+
+      /* Div-M and Div-N in fractional baudrate Register.               */
+      (((uint32_t)ADI_UART1_CFG_DIVN       << BITP_UART_FBR_DIVN) |
+       ((uint32_t)ADI_UART1_CFG_DIVM       << BITP_UART_FBR_DIVM) |
+       ((uint32_t)BITM_UART_FBR_FBEN)),
+
+      /* Over sample rate in second line control register.              */
+      ADI_UART1_CFG_OSR,
+
+      /* FIFO control register.                                         */
+      ((ADI_UART1_CFG_ENABLE_FIFO          << BITP_UART_FCR_FIFOEN)|
+       (ADI_UART1_CFG_TRIG_LEVEL           << BITP_UART_FCR_RFTRIG)),
+
+      /* Half duplex control register.                                  */
+      ((ADI_UART1_CFG_SOUT_POLARITY        << BITP_UART_RSC_OENP)  |
+       (ADI_UART1_CFG_DEASSERTION          << BITP_UART_RSC_OENSP) |
+       (ADI_UART1_CFG_DISABLE_RX           << BITP_UART_RSC_DISRX) |
+       (ADI_UART1_CFG_HOLD_TX              << BITP_UART_RSC_DISTX)),
+
+      /* Interrupt enable register.                                     */
+      ((ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT << BITP_UART_IEN_EDSSI) |
+       (ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT    << BITP_UART_IEN_ELSI))
+    }
+#endif /*__ADUCM4x50*/
+};
+
+/*! \endcond */
+
+/*! Number of UART devices available on the chip. */
+#define ADI_UART_NUM_DEVICES (sizeof(uart_device_info)/sizeof(ADI_UART_DEVICE_INFO))
+
+/* Override "weak" default binding in startup.c */
+/*! \cond PRIVATE */
+extern void UART0_Int_Handler(void);
+extern void UART1_Int_Handler(void);
+extern void DMA_UART0_TX_Int_Handler(void);
+extern void DMA_UART0_RX_Int_Handler(void);
+
+#if defined (__ADUCM4x50__)
+extern void DMA_UART1_TX_Int_Handler(void);
+extern void DMA_UART1_RX_Int_Handler(void);
+#endif
+
+/* Internal DMA Callback for receiving DMA faults from common DMA error handler. */
+static void RxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg);
+static void RxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) {
+
+    /* Recover the device handle. */
+    ADI_UART_HANDLE hDevice = (ADI_UART_HANDLE)pCBParam;
+    ADI_UART_BUFF_INFO * pNextBuff = hDevice->pChannelRx->pFillBuffer->pNextBuffer;
+    uint32_t nEvent = 0u;
+
+    /* Save the DMA error. */
+    switch (Event) {
+        case ADI_DMA_EVENT_ERR_BUS:
+            nEvent |= (uint32_t)ADI_UART_HW_ERR_RX_CHAN_DMA_BUS_FAULT;
+            break;
+        case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR:
+            nEvent |= (uint32_t)ADI_UART_HW_ERR_RX_CHAN_DMA_INVALID_DESCR;
+            break;
+        default:
+            nEvent |= (uint32_t)ADI_UART_HW_ERR_RX_CHAN_DMA_UNKNOWN_ERROR;
+            break;
+    }
+
+    if((pNextBuff->pStartAddress != NULL) && (pNextBuff->bDMA == true))
+    {
+        hDevice->nHwError |= nEvent;
+        pNextBuff->bInUse = false;
+        uart_ManageProcessedBuffer(hDevice,hDevice->pChannelRx,ADI_UART_EVENT_RX_BUFFER_PROCESSED);
+
+    }
+    hDevice->nHwError |= nEvent;
+    uart_ManageProcessedBuffer(hDevice,hDevice->pChannelRx,ADI_UART_EVENT_RX_BUFFER_PROCESSED);
+}
+
+static void TxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg);
+static void TxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) {
+
+    /* Recover the device handle. */
+    ADI_UART_HANDLE hDevice = (ADI_UART_HANDLE)pCBParam;
+    ADI_UART_BUFF_INFO * pNextBuff = hDevice->pChannelTx->pFillBuffer->pNextBuffer;
+    uint32_t nEvent = 0u;
+
+    /* Save the DMA error. */
+    switch (Event) {
+        case ADI_DMA_EVENT_ERR_BUS:
+            nEvent |= (uint32_t)ADI_UART_HW_ERR_TX_CHAN_DMA_BUS_FAULT;
+            break;
+        case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR:
+            nEvent |= (uint32_t)ADI_UART_HW_ERR_TX_CHAN_DMA_INVALID_DESCR;
+            break;
+        default:
+            nEvent |= (uint32_t)ADI_UART_HW_ERR_TX_CHAN_DMA_UNKNOWN_ERROR;
+            break;
+    }
+    if((pNextBuff->pStartAddress != NULL) && (pNextBuff->bDMA == true))
+    {
+        hDevice->nHwError |= nEvent;
+        pNextBuff->bInUse = false;
+        uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED);
+
+    }
+
+    hDevice->nHwError |= nEvent;
+    uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED);
+}
+/*! \endcond */
+
+/**********************************************************
+ * General UART APIs
+ **********************************************************/
+
+/*!
+ * @brief       Initialization function for the UART device.
+ * @details     Opens the specified UART device. This function must be called before operating any UART device.
+ *
+ *
+ * @param [in]  nDeviceNum     UART device instance to be opened.
+ * @param [in]  eDirection     Direction of the UART operation. (i.e Rx or Tx)
+ * @param [in]  pMemory        Pointer to a 32 bit aligned buffer the size of #ADI_UART_UNIDIR_MEMORY_SIZE
+ *                             or #ADI_UART_BIDIR_MEMORY_SIZE.
+ * @param [in]  nMemSize       Size of the buffer to which "pMemory" points. This will vary based on
+ *                             direction of operation for this device instance. (i.e Rx and Tx, Rx, Tx)
+ *
+ * @param [out] phDevice       The caller's device handle pointer for storing the initialized device instance data pointer.
+ *
+ * @return      Status
+ *              - #ADI_UART_SUCCESS                     Successfully initialized UART device.
+ *              - #ADI_UART_SEMAPHORE_FAILED            Failed to create semaphore.
+ *              - #ADI_UART_INVALID_DEVICE_NUM      [D] Device instance is invalid.
+ *              - #ADI_UART_INSUFFICIENT_MEMORY     [D] Supplied memory is insufficient for the operation of specified UART device.
+ *              - #ADI_UART_DEVICE_IN_USE           [D] Device is already open.
+ *
+ * @sa  adi_uart_Close()
+ *
+ * @note: Memory supplied by the API will be used by the driver for managing the UART device. This memory can be reused once
+ *        device is closed.
+ *
+ */
+ADI_UART_RESULT adi_uart_Open(
+                              uint32_t            const nDeviceNum,
+                              ADI_UART_DIRECTION  const eDirection,
+                              void                     *pMemory,
+                              uint32_t            const nMemSize,
+                              ADI_UART_HANDLE    *const phDevice
+                             )
+{
+#ifdef ADI_DEBUG
+    /* Check if the given device number is within the range of UART
+     * devices present in the processor. There are two devices present here
+     * so this can be a 0 or 1 for ADuCM4050 and only 0 for ADuCM302x.
+     */
+    if(nDeviceNum >= ADI_UART_NUM_DEVICES)
+    {
+        return(ADI_UART_INVALID_DEVICE_NUM);
+    }
+
+    /* Verify the device is not already open. */
+    if(uart_device_info[nDeviceNum].hDevice != NULL)
+    {
+        return(ADI_UART_DEVICE_IN_USE);
+    }
+
+    /* Make sure there is enough memory for the device instance to operate in a single direction. */
+    if(eDirection !=  ADI_UART_DIR_BIDIRECTION)
+    {
+        if(nMemSize < (uint32_t)ADI_UART_UNIDIR_MEMORY_SIZE)
+        {
+            return(ADI_UART_INSUFFICIENT_MEMORY);
+        }
+        assert(nMemSize == (sizeof(ADI_UART_DEVICE) + sizeof(ADI_UART_DATA_CHANNEL)));
+    }
+
+    /* Make sure there is enough memory for the device instance to operate in both directions. */
+    else
+    {
+        if(nMemSize < (uint32_t)ADI_UART_BIDIR_MEMORY_SIZE)
+        {
+            return(ADI_UART_INSUFFICIENT_MEMORY);
+        }
+        assert(nMemSize == (sizeof(ADI_UART_DEVICE) + (sizeof(ADI_UART_DATA_CHANNEL)*2u)));
+    }
+#endif /* ADI_DEBUG */
+
+    /* Initialize the device handle to NULL in case of a failure. */
+    *phDevice = NULL;
+
+    /* Link the ADI_UART_HANDLE to the ADI_UART_DEVICE structure. */
+     ADI_UART_HANDLE hDevice = pMemory;
+
+    /* Zero the device handle memory so we do not have to explicitely initialize
+       the structure members to 0.
+    */
+    memset(pMemory, 0, nMemSize);
+
+
+    /* Set the device information. */
+    hDevice->pUartInfo = &uart_device_info[nDeviceNum];
+
+    /* Set the base of the UART register address. We do this to minimize
+       the cycle count when accessing the UART registers.
+    */
+    hDevice->pUARTRegs = uart_device_info[nDeviceNum].pUartRegs;
+
+    /* Store the direction that this device will operate in. */
+    hDevice->eDirection = eDirection;
+
+    /* Increment the device handle with the size of the UART device structure
+       so we can set the channel data next without overwriting
+       the #ADI_UART_DEVICE data.
+    */
+    pMemory = ((uint8_t *)pMemory +(sizeof(ADI_UART_DEVICE)));
+
+    /* Set up the DMA Controller. */
+    adi_dma_Init();
+
+    /* Initialize the TX-channel. */
+    if(ADI_UART_DIR_RECEIVE != eDirection)
+    {
+         hDevice->pChannelTx = (ADI_UART_DATA_CHANNEL *)pMemory;
+
+         /* Initialize the data transfer mode. */
+         hDevice->pChannelTx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE;
+
+         /* Initialize Tx buffer pointers. */
+         hDevice->pChannelTx->pFreeBuffer = &hDevice->pChannelTx->PingPong[0];
+         hDevice->pChannelTx->pActiveBuffer = &hDevice->pChannelTx->PingPong[0];
+         hDevice->pChannelTx->pFillBuffer = &hDevice->pChannelTx->PingPong[0];
+
+
+         /* Create a "semaphore" (varies per OS) used for blocking buffer resource management. */
+         SEM_CREATE(hDevice->pChannelTx, "UART_TX_SEM", ADI_UART_SEMAPHORE_FAILED);
+
+         /* Set submit buffer function pointer. */
+         hDevice->pChannelTx->pfSubmitBuffer = &uart_submittxbuffer;
+
+         hDevice->pChannelTx->PingPong[0].pNextBuffer  = &hDevice->pChannelTx->PingPong[1];
+         hDevice->pChannelTx->PingPong[1].pNextBuffer  = &hDevice->pChannelTx->PingPong[0];
+
+         /*Register DMA Callback. */
+         if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pUartInfo->dmaTxChannelNum, TxDmaErrorCallback, (void*)hDevice))
+         {
+              adi_uart_Close(hDevice);
+              return  ADI_UART_ERR_DMA_REGISTER;
+         }
+
+         /* Increment the device handle the size of #ADI_UART_DATA_CHANNEL
+            structure in case there is another channel to configure.
+         */
+         pMemory =  ((uint8_t *)pMemory + sizeof(ADI_UART_DATA_CHANNEL));
+    }
+    /* Initialize the RX-channel. */
+    if(ADI_UART_DIR_TRANSMIT != eDirection)
+    {
+        hDevice->pChannelRx = (ADI_UART_DATA_CHANNEL *)pMemory;
+
+        /* Initialize the data transfer mode. */
+        hDevice->pChannelRx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE;
+
+        /* Initialize Rx buffer pointers. */
+        hDevice->pChannelRx->pFreeBuffer = &hDevice->pChannelRx->PingPong[0];
+        hDevice->pChannelRx->pActiveBuffer = &hDevice->pChannelRx->PingPong[0];
+        hDevice->pChannelRx->pFillBuffer = &hDevice->pChannelRx->PingPong[0];
+
+        /* Create a "semaphore" (varies per OS) used for blocking buffer resource management. */
+        SEM_CREATE(hDevice->pChannelRx, "UART_RX_SEM", ADI_UART_SEMAPHORE_FAILED);
+
+        /* Set submit buffer function pointer. */
+        hDevice->pChannelRx->pfSubmitBuffer = &uart_submitrxbuffer;
+
+        hDevice->pChannelRx->PingPong[0].pNextBuffer  = &hDevice->pChannelRx->PingPong[1];
+        hDevice->pChannelRx->PingPong[1].pNextBuffer  = &hDevice->pChannelRx->PingPong[0];
+
+         /*Register DMA Callback. */
+         if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pUartInfo->dmaRxChannelNum, RxDmaErrorCallback, (void*)hDevice))
+         {
+              adi_uart_Close(hDevice);
+              return  ADI_UART_ERR_DMA_REGISTER;
+         }
+    }
+
+    /* Initialize the device with the static config values.*/
+    uart_init(hDevice, nDeviceNum);
+
+    /* Write the device data pointer to the application's handle. */
+    *phDevice = hDevice;
+
+    /* Store the device handle. */
+    uart_device_info[nDeviceNum].hDevice = hDevice;
+
+
+    /* Enable UART Interrupt. */
+    NVIC_ClearPendingIRQ(hDevice->pUartInfo->eIRQn);
+    NVIC_EnableIRQ(hDevice->pUartInfo->eIRQn);
+
+    /* Enable the interrupt for the DMA. */
+    NVIC_EnableIRQ(hDevice->pUartInfo->eDMATx);
+    NVIC_EnableIRQ(hDevice->pUartInfo->eDMARx);
+
+    /* Return SUCCESS */
+    return(ADI_UART_SUCCESS);
+}
+
+/*!
+ * @brief       Uninitialize the memory for the specified UART instance.
+ *
+ * @param [in]  hDevice   UART device handle whose operation is to be closed. This handle was obtained when the UART
+ *                        device instance was opened successfully.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS               Successfully closed the UART device instance.
+ *    - #ADI_UART_SEMAPHORE_FAILED      Failed to delete the semaphore.
+ *    - #ADI_UART_INVALID_HANDLE    [D] Invalid UART device handle.
+ *    - #ADI_UART_DEVICE_IN_USE     [D] Specified UART device is in the process of a transaction or autobaud has not completed.
+ *
+ * @details     Closes the operation of specified UART device. Device needs to be opened again for any further use.
+ *
+ * @sa  adi_uart_Open()
+ *
+ * @note: It is the user's responsibility to free/reuse the memory supplied during the opening of the device.
+ */
+ADI_UART_RESULT adi_uart_Close(
+                               ADI_UART_HANDLE const hDevice
+                              )
+{
+#ifdef ADI_DEBUG
+    /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* Make sure there are no active buffers on any active channel, autobaud is not in progress and the
+       Tx shift register is completely empty. This can be an issue if you submitted a nonblocking transmit
+       because you will receive interrupt before the hardware has fully finished the transaction. The start
+       address of the active buffer will remain in use until the buffer has been completely processed.
+       Therefore if the start address is NULL it means it has not been submitted for a transaction.
+    */
+    if(((hDevice->pUARTRegs->LSR & BITM_UART_LSR_TEMT) != BITM_UART_LSR_TEMT)                                        ||
+       ((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pFillBuffer->pStartAddress != NULL)) ||
+       ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pFillBuffer->pStartAddress != NULL)) ||
+       (hDevice->bAutobaudInProgress == true))
+    {
+        return(ADI_UART_DEVICE_IN_USE);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Disable UART status interrupts. */
+    hDevice->pUARTRegs->IEN = 0x00U;
+
+    /* Disable DMA UART interrupts. */
+    NVIC_DisableIRQ(hDevice->pUartInfo->eDMARx);
+    NVIC_DisableIRQ(hDevice->pUartInfo->eDMATx);
+
+    /* Disable UART event interrupt. */
+    NVIC_DisableIRQ(hDevice->pUartInfo->eIRQn);
+
+    /* Delete Tx-Channel semaphore. */
+    if(hDevice->eDirection != ADI_UART_DIR_RECEIVE)
+    {
+        SEM_DELETE(hDevice->pChannelTx, ADI_UART_SEMAPHORE_FAILED);
+    }
+
+    /* Delete Rx-Channel semaphore. */
+    if(hDevice->eDirection != ADI_UART_DIR_TRANSMIT)
+    {
+        SEM_DELETE(hDevice->pChannelRx, ADI_UART_SEMAPHORE_FAILED);
+    }
+
+     /* Free up the device memory. */
+    hDevice->pUartInfo->hDevice = NULL;
+
+    return(ADI_UART_SUCCESS);
+}
+
+/*!
+ * @brief       Submit a "filled" buffer for transmitting data in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING.
+ *              This function sets up the apropriate interrupts associated with the transaction and marks
+ *              the buffer as submitted.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  pBuffer    Pointer to data supplied by the API that is to be transmitted.
+ * @param [in]  nBufSize   Size of the buffer to be transmitted(in bytes). Must be smaller than 1024 bytes for DMA transfers.
+ * @param [in]  bDMA       Submit the buffer using the DMA flag.
+
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                        Successfully submitted the buffer for transmission.
+ *    - #ADI_UART_FAILED                     [D] Generic failure. In this case the size of the data buffer we are trying
+ *                                               to submit is NULL.
+ *    - #ADI_UART_INVALID_DATA_TRANSFER_MODE [D] Device is operating in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. This
+ *                                               operation is only allowed in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING.
+ *    - #ADI_UART_INVALID_HANDLE             [D] Invalid UART device handle.
+ *    - #ADI_UART_OPERATION_NOT_ALLOWED      [D] Device direction is set up as #ADI_UART_DIR_RECEIVE, so we can not complete
+ *                                               a transmit operation. The required directions are #ADI_UART_DIR_TRANSMIT or
+ *                                               #ADI_UART_DIR_BIDIRECTION.
+ *    - #ADI_UART_INVALID_POINTER            [D] Pointer to the buffer being submitted is NULL.
+ *    - #ADI_UART_DEVICE_IN_USE              [D] Autobaud in progress.
+ *    - #ADI_UART_INVALID_DATA_SIZE          [D] DMA transfers must be smaller than 1025 bytes.
+ *
+ * @sa  adi_uart_IsTxBufferAvailable()
+ * @sa  adi_uart_GetTxBuffer()
+ * @sa  adi_uart_SubmitRxBuffer()
+ *
+ * @note: Only one transfer mode (DMA vs. PIO) can be used at once. For example, if you submit a buffer in PIO mode
+ *        and then right away another using the DMA, this transaction will be denied.
+ *
+ */
+ADI_UART_RESULT adi_uart_SubmitTxBuffer(
+                                         ADI_UART_HANDLE const hDevice,
+                                         void           *const pBuffer,
+                                         uint32_t        const nBufSize,
+                                         bool            const bDMA
+                                       )
+{
+
+#ifdef ADI_DEBUG
+    /* Validate the device handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* Validate the pointer to the buffer memory. */
+    if(pBuffer == NULL)
+    {
+        return(ADI_UART_INVALID_POINTER);
+    }
+
+    /* Validate the buffer size. */
+    if(nBufSize == 0U)
+    {
+        return(ADI_UART_FAILED);
+    }
+
+    /* Autobaud in progress. */
+    if(hDevice->bAutobaudInProgress == true)
+    {
+        return(ADI_UART_DEVICE_IN_USE);
+    }
+
+    /* Make sure we are transmitting. */
+    if(ADI_UART_DIR_RECEIVE == hDevice->eDirection)
+    {
+        return(ADI_UART_OPERATION_NOT_ALLOWED);
+    }
+
+    /* Check the data transfer mode (only allowed in nonblocking mode). */
+    if(hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING)
+    {
+        return(ADI_UART_INVALID_DATA_TRANSFER_MODE);
+    }
+
+    /* Check that there is a free buffer to use for this transmit operation. pFreeBuffer
+       is the next buffer available, so if it is in use we can make the assumption that
+       there are no buffers available. The start address is set to NULL once the buffer
+       has finished being processed in "adi_uart_GetBuffer()" or "adi_uart_PendForBuffer()".
+    */
+    if(hDevice->pChannelTx->pFreeBuffer->pStartAddress != NULL)
+    {
+        return(ADI_UART_OPERATION_NOT_ALLOWED);
+    }
+
+    /* Make sure the DMA transfer size is not too large. */
+    if((bDMA == true) && (nBufSize > DMA_TRANSFER_LIMIT))
+    {
+        return(ADI_UART_INVALID_DATA_SIZE);
+    }
+
+#endif /* ADI_DEBUG */
+
+     /* Set the start address of the data buffer we are going to submit. */
+     hDevice->pChannelTx->pFreeBuffer->pStartAddress =   pBuffer;
+
+     /* Set the buffer size to the size of the data buffer passed down from the API. */
+     hDevice->pChannelTx->pFreeBuffer->nCount        =   nBufSize;
+
+     /* Initialize the buffer index to zero because we will start shifting out
+        the Tx data from the first position of the buffer.
+     */
+     hDevice->pChannelTx->pFreeBuffer->nIndex        =   0U;
+
+     /* Mark the buffer as in use so no other transactions can use it until this one is complete. */
+     hDevice->pChannelTx->pFreeBuffer->bInUse        =   true;
+
+     /* Mark the DMA as in use. */
+     hDevice->pChannelTx->pFreeBuffer->bDMA          =   bDMA;
+
+     /* Now that this "pFreeBuffer" is no longer free for use, update the
+        "pFreeBuffer" to the other PingPong buffer. Because there are only two
+        buffers in the PingPong structure, this will be the opposite of the one
+        we just submitted. "pFreeBuffer" will only be updated during the process of
+        submitting a buffer or a read/write operation.
+     */
+      hDevice->pChannelTx->pFreeBuffer = hDevice->pChannelTx->pFreeBuffer->pNextBuffer;
+
+     /* Set the data transfer mode in case it was #ADI_UART_DATA_TRANSFER_MODE_NONE.
+        This will be set back to #ADI_UART_DATA_TRANSFER_MODE_NONE once this
+        transaction is complete. Then, if a buffer is not currently active, set up the
+        interrupts for this transaction. Otherwise if a buffer is currently active,
+        this will be taken care of in the ISR.
+     */
+     if (hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONE)
+     {
+         hDevice->pChannelTx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING;
+         hDevice->pChannelTx->pfSubmitBuffer(hDevice, hDevice->pChannelTx->pFillBuffer);
+     }
+
+     return(ADI_UART_SUCCESS);
+  }
+
+/*!  \cond PRIVATE */
+
+/*
+ * @brief      This is an internal helper function for adi_uart_SubmitTxBuffer(). It sets up the Tx channel DMA
+               or device interrupts for the Tx channel to transmit data.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  pBuffer    Pointer to buffer from where data will be transmitted.
+ * @param [in]  nBufSize   Size of the buffer containing the data to be transmitted(in bytes).
+ * @param [in]  bDMA       Submit the buffer using the DMA.
+*/
+static void uart_submittxbuffer(
+                                 ADI_UART_CONST_HANDLE  const hDevice,
+                                 ADI_UART_BUFF_INFO    *const pBuffer
+                               )
+{
+  /* If this transmission is using DMA... */
+  if (pBuffer->bDMA)
+  {
+      /* Enable clear source address decrement for TX channel DMA. */
+      pADI_DMA0->SRCADDR_CLR = 1u << (uint32_t)hDevice->pUartInfo->dmaTxChannelNum;
+
+      /* Enable Tx channel DMA. */
+      pADI_DMA0->EN_SET = 1u << hDevice->pUartInfo->dmaTxChannelNum;
+
+      /* Enable UART peripheral to generate DMA requests. */
+      pADI_DMA0->RMSK_CLR = 1u << hDevice->pUartInfo->dmaTxChannelNum;
+
+      /* Set the primary control data structure as the current DMA descriptor. */
+      pADI_DMA0->ALT_CLR = 1u << hDevice->pUartInfo->dmaTxChannelNum;
+
+      /* Fill in the DMA RAM descriptors */
+      pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMASRCEND =   ((uint32_t)pBuffer->pStartAddress + (uint32_t)(pBuffer->nCount - 1u));
+
+      pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMADSTEND =   (uint32_t)&hDevice->pUARTRegs->TX;
+
+      pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMACDC    =   ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC)      |
+                                                                     ((uint32_t)ADI_DMA_INCR_1_BYTE << DMA_BITP_CTL_SRC_INC)    |
+                                                                     (ADI_DMA_WIDTH_1_BYTE << DMA_BITP_CTL_SRC_SIZE)            |
+                                                                     (0u << DMA_BITP_CTL_R_POWER)                               |
+                                                                     ((pBuffer->nCount - 1u) << DMA_BITP_CTL_N_MINUS_1)         |
+                                                                     (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
+      /* Enable UART DMA request interrupt for the Tx channel. */
+      hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_EDMAT);
+  }
+  else
+  /* If this transmission is using UART interrupts.. */
+  {
+      /* Enable buffer empty interrupts.  */
+      hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ETBEI);
+  }
+}
+
+/*! \endcond */
+
+/*!
+ * @brief       Submit an empty buffer for receiving the data in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING.
+ *              This will set up the Rx channel for notification on incoming data using either the DMA
+ *              or UART interrupts, as well as mark the buffer as submitted.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  pBuffer    Pointer to buffer from that will be filled by the driver when data has been received.
+ * @param [in]  nBufSize   Size of the buffer(in bytes). Must be smaller than 1024 bytes for DMA transfers.
+ * @param [in]  bDMA       Submit the buffer using DMA flag.
+
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                        Successfully submitted the buffer for receiving data.
+ *    - #ADI_UART_FAILED                     [D] Generic failure. In this case the size of the data buffer we are trying
+ *                                               to submit is NULL.
+ *    - #ADI_UART_INVALID_DATA_TRANSFER_MODE [D] Device is operating in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. This
+ *                                               operation is only allowed in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING.
+ *    - #ADI_UART_INVALID_HANDLE             [D] Invalid UART device handle.
+ *    - #ADI_UART_OPERATION_NOT_ALLOWED      [D] Device direction is set up as #ADI_UART_DIR_TRANSMIT, so we can not complete
+ *                                               a receive operation. The required directions are #ADI_UART_DIR_RECEIVE or
+ *                                               #ADI_UART_DIR_BIDIRECTION.
+ *    - #ADI_UART_INVALID_POINTER            [D] Pointer to the buffer being submitted is NULL.
+ *    - #ADI_UART_DEVICE_IN_USE              [D] Autobaud in progress.
+ *    - #ADI_UART_INVALID_DATA_SIZE          [D] DMA transfers must be smaller than 1025 bytes.
+ *
+ * @sa  adi_uart_IsRxBufferAvailable()
+ * @sa  adi_uart_GetRxBuffer()
+ * @sa  adi_uart_SubmitTxBuffer()
+ *
+ * @note: Only one transfer mode (DMA vs. PIO) can be used at once. For example, if you submit a buffer in PIO mode
+ *        and then right away another using the DMA, this transaction will be denied.
+*/
+ADI_UART_RESULT adi_uart_SubmitRxBuffer(
+                                         ADI_UART_HANDLE const hDevice,
+                                         void           *const pBuffer,
+                                         uint32_t        const nBufSize,
+                                         bool            const bDMA
+                                       )
+{
+
+#ifdef ADI_DEBUG
+    /* Validate the device handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* Validate the pointer to the buffer memory. */
+    if(pBuffer == NULL)
+    {
+        return(ADI_UART_INVALID_POINTER);
+    }
+
+    /* Validate the buffer size. */
+    if(nBufSize == 0U )
+    {
+        return(ADI_UART_FAILED);
+    }
+
+    /* Autobaud in progress. */
+    if(hDevice->bAutobaudInProgress == true)
+    {
+        return(ADI_UART_DEVICE_IN_USE);
+    }
+
+    /* Make sure the UART device is configured to operate in the receive direction. */
+    if(ADI_UART_DIR_TRANSMIT == hDevice->eDirection)
+    {
+        return(ADI_UART_OPERATION_NOT_ALLOWED);
+    }
+
+    /* Check for the data transfer mode(only allowed in nonblocking mode). */
+    if(hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING)
+    {
+        return(ADI_UART_INVALID_DATA_TRANSFER_MODE);
+    }
+
+    /* Check that there is a free buffer to use for this operation. pFreeBuffer
+       is the next buffer available, so if it is in use we can make the assumption that
+       there are no buffers available. If the start address is not set to NULL, then we
+       can conclude the buffer has not finished being processed because this gets set in
+       adi_uart_pend_for_buffer() and adi_uart_get_buffer().
+    */
+    if(hDevice->pChannelRx->pFreeBuffer->pStartAddress != NULL)
+    {
+        return(ADI_UART_OPERATION_NOT_ALLOWED);
+    }
+
+    /* Make sure the DMA transfer size is not too large. */
+    if((bDMA == true) && (nBufSize > DMA_TRANSFER_LIMIT))
+    {
+        return(ADI_UART_INVALID_DATA_SIZE);
+    }
+
+#endif /* ADI_DEBUG */
+
+    /* Set the start address of the buffer you are going to submit. */
+     hDevice->pChannelRx->pFreeBuffer->pStartAddress =   pBuffer;
+
+     /* Set the size of the buffer. */
+     hDevice->pChannelRx->pFreeBuffer->nCount        =   nBufSize;
+
+     /* Initialize the buffer index to 0, because as we receive data it will be put into
+        the buffer starting at the first position.
+     */
+     hDevice->pChannelRx->pFreeBuffer->nIndex        =   0U;
+
+     /* Mark the buffer as in use. */
+     hDevice->pChannelRx->pFreeBuffer->bInUse        =   true;
+
+     /* Mark the DMA as in use. */
+     hDevice->pChannelRx->pFreeBuffer->bDMA          =   bDMA;
+
+     /* Now that this "pFreeBuffer" is no longer free for use, update the
+        "pFreeBuffer" to the other PingPong buffer. Because there are only two
+        buffers in the PingPong structure, this will be the opposite of the one
+        we just submitted. "pFreeBuffer" will only be updated during the process of
+        submitting a buffer or a read/write operation.
+     */
+      hDevice->pChannelRx->pFreeBuffer = hDevice->pChannelRx->pFreeBuffer->pNextBuffer;
+
+
+    /* Set the data transfer mode in case it was #ADI_UART_DATA_TRANSFER_MODE_NONE.
+       This will be set back to #ADI_UART_DATA_TRANSFER_MODE_NONE once this
+       transaction is complete. Then, if a buffer is not currently active, set up the
+       interrupts for this transaction. Otherwise if a buffer is currently active,
+       this will be taken care of in the ISR.
+    */
+     if (hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONE)
+     {
+         hDevice->pChannelRx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING;
+         hDevice->pChannelRx->pfSubmitBuffer(hDevice, hDevice->pChannelRx->pFillBuffer);
+     }
+
+     return(ADI_UART_SUCCESS);
+}
+
+/*! \cond PRIVATE */
+
+/*
+ * @brief                  This is an internal helper function for adi_uart_SubmitRxBuffer(). It sets up the DMA
+ *                         or device receive interrupts for the Rx channel to receive data.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  pBuffer    Pointer to the empty receive buffer.
+ * @param [in]  nBufSize   Size of the receive buffer(in bytes).
+ * @param [in]  bDMA       Submit the buffer using the DMA.
+*/
+static void uart_submitrxbuffer(
+                                 ADI_UART_CONST_HANDLE   const hDevice,
+                                 ADI_UART_BUFF_INFO     *const pBuffer
+                               )
+{
+
+
+    /* If this transaction is using the DMA.. */
+    if (pBuffer->bDMA)
+    {
+        /* Enable source address decrement for RX DMA channel. */
+        pADI_DMA0->DSTADDR_CLR = 1u << (uint32_t)hDevice->pUartInfo->dmaRxChannelNum;
+
+        /* Enable Rx DMA channel. */
+        pADI_DMA0->EN_SET = 1u << hDevice->pUartInfo->dmaRxChannelNum;
+
+        /* Enable UART peripheral to generate DMA requests. */
+        pADI_DMA0->RMSK_CLR = 1u << hDevice->pUartInfo->dmaRxChannelNum;
+
+        /* Set the primary data structure as the current DMA descriptor. */
+        pADI_DMA0->ALT_CLR = 1u << hDevice->pUartInfo->dmaRxChannelNum;
+
+        /* Fill in the DMA RAM descriptors. */
+        pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMASRCEND =   (uint32_t)&hDevice->pUARTRegs->RX;
+
+        pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMADSTEND =   ((uint32_t)pBuffer->pStartAddress + (uint32_t)(pBuffer->nCount - 1u));
+
+        pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMACDC    =   (uint32_t)(ADI_DMA_INCR_1_BYTE << DMA_BITP_CTL_DST_INC)            |
+                                                                       (uint32_t)(ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC)              |
+                                                                       (ADI_DMA_WIDTH_1_BYTE << DMA_BITP_CTL_SRC_SIZE)                    |
+                                                                       (0u << DMA_BITP_CTL_R_POWER)                                       |
+                                                                       ((pBuffer->nCount - 1u) << DMA_BITP_CTL_N_MINUS_1)                 |
+                                                                       (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
+        /* Enable UART receive DMA requests. */
+        hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_EDMAR);
+    }
+    /* If this transaction is using UART interrupts.. */
+    else
+    {
+        /* Enable buffer full interrupt. */
+        hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ERBFI);
+    }
+}
+
+/*! \endcond */
+
+/*!
+ * @brief       Transfer buffer ownership from the device back to the API if the data
+ *              transmit has completed. Otherwise it will block until completion.
+ *              This allows a nonblocking call to become blocking.
+ *              This function is only called in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  ppBuffer   Contains the address of the buffer passed down from the API
+ *                         for transmitting data.
+ * @param [out] pHwError   Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status.
+ *                         If there is no hardware event, this will be 0.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                       Successfully returned buffer to the API.
+ *    - #ADI_UART_HW_ERROR_DETECTED             Hardware error(s) detected. "pHwError" can be checked for the specific error code(s).
+ *    - #ADI_UART_OPERATION_NOT_ALLOWED     [D] Call to this function is not allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING.
+ *    - #ADI_UART_INVALID_HANDLE            [D] Invalid UART device handle.
+ *    - #ADI_UART_BUFFER_NOT_SUBMITTED      [D] The buffer has not been submitted to the driver.
+ *
+ * @sa  adi_uart_IsTxBufferAvailable()
+ * @sa  adi_uart_SubmitTxBuffer()
+ *
+ * @note: If the transaction has already completed, this will return immediately rather than block.
+ */
+ADI_UART_RESULT adi_uart_GetTxBuffer(
+                                      ADI_UART_HANDLE const   hDevice,
+                                      void          **const   ppBuffer,
+                                      uint32_t               *pHwError
+                                     )
+
+{
+
+#ifdef ADI_DEBUG
+    /* Validate the device handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* Validate that this buffer has actually been submitted. */
+    if(hDevice->pChannelTx->pActiveBuffer->pStartAddress == NULL)
+    {
+        return(ADI_UART_BUFFER_NOT_SUBMITTED);
+    }
+
+    /* This function is allowed to be called when the channel is operating in NONBLOCKING mode. */
+    if(hDevice->pChannelTx->eDataTranferMode ==  ADI_UART_DATA_TRANSFER_MODE_BLOCKING)
+    {
+        return(ADI_UART_OPERATION_NOT_ALLOWED);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Blocking call to get the submitted buffer */
+    return(uart_getbuffer(hDevice, hDevice->pChannelTx, ppBuffer, pHwError));
+}
+
+
+
+/*!
+ * @brief       Transfer buffer ownership from the device back to the API if the data
+ *              receive has completed. Otherwise it will block until completion.
+ *              This allows a nonblocking call to become blocking.
+ *              This function is only called in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  ppBuffer   Contains the address of the buffer passed down from the API
+ *                         for receiving data.
+ * @param [out] pHwError   Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status.
+ *                         If there is no hardware event, this will be 0.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                       Successfully returned buffer to the API.
+ *    - #ADI_UART_HW_ERROR_DETECTED             Hardware error(s) detected. "pHwError" can be checked for the specific error code(s).
+ *    - #ADI_UART_OPERATION_NOT_ALLOWED     [D] Call to this function is not allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING.
+ *    - #ADI_UART_INVALID_HANDLE            [D] Invalid UART device handle.
+ *    - #ADI_UART_BUFFER_NOT_SUBMITTED      [D] The buffer has not been submitted to the driver.
+ *
+ * @sa  adi_uart_IsRxBufferAvailable()
+ * @sa  adi_uart_SubmitRxBuffer()
+ *
+ * @note: If the transaction has already completed, this will return immediately rather than block.
+*/
+ADI_UART_RESULT adi_uart_GetRxBuffer(
+                                      ADI_UART_HANDLE  const   hDevice,
+                                      void           **const   ppBuffer,
+                                      uint32_t                *pHwError
+                                     )
+
+{
+
+#ifdef ADI_DEBUG
+    /* Validate the device handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* Validate that this buffer has actually been submitted. */
+    if(hDevice->pChannelRx->pActiveBuffer->pStartAddress == NULL)
+    {
+        return(ADI_UART_BUFFER_NOT_SUBMITTED);
+    }
+
+     /* This function is only allowed to be called when the channel is operating in NONBLOCKING mode. */
+    if(hDevice->pChannelRx->eDataTranferMode ==  ADI_UART_DATA_TRANSFER_MODE_BLOCKING)
+    {
+        return(ADI_UART_OPERATION_NOT_ALLOWED);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Blocking call to get the full Rx Buffer */
+    return(uart_getbuffer(hDevice, hDevice->pChannelRx, ppBuffer, pHwError));
+}
+
+/*! \cond PRIVATE */
+
+/*
+ * @brief       This is an internal helper function for adi_uart_GetRxBuffer() and adi_uart_GetTxBuffer().
+ *              It blocks until until the completion of the data transaction.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  pChannel   Pointer to UART channel data structure.
+ * @param [out] ppBuffer   Contains the address of the buffer passed down from the API.
+ * @param [out] pHwError   Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status.
+ *                         If there is no hardware event, this will be 0.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                Successfully got buffer.
+ *    - #ADI_UART_HW_ERROR_DETECTED      Hardware error(s) detected. "pHwError" can be checked for the specific error code(s).
+ *
+*/
+static ADI_UART_RESULT uart_getbuffer(
+                                       ADI_UART_HANDLE        hDevice,
+                                       ADI_UART_DATA_CHANNEL *pChannel,
+                                       void                 **ppBuffer,
+                                       uint32_t              *pHwError
+                                      )
+{
+    /* Set ppBuffer to NULL in case there is an error. */
+    *ppBuffer = NULL;
+
+    /* Wait until the peripheral has finished processing the buffer. */
+    SEM_PEND(pChannel,ADI_UART_FAILED);
+
+    /* Save the address of the buffer that has just been processed, so it can be
+       returned back to the API.
+    */
+    *ppBuffer = pChannel->pActiveBuffer->pStartAddress;
+
+    /* Reinitialize the start address to NULL so this buffer can be used for a new transaction. */
+    pChannel->pActiveBuffer->pStartAddress = NULL;
+
+    /* Now that the desired data has either been transmitted or received, this buffer is no longer
+       in use. We can update "pActiveBuffer" to point to the next buffer that will become or is already
+       active.
+    */
+     pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer;
+
+     /* Set the data transfer mode to none so that the next transfer can be either in blocking or in nonblocking mode.
+        This will only be done if there are no other active buffers in flight to avoid disrupting an active transfer.
+    */
+     if(pChannel->pActiveBuffer->pStartAddress == NULL)
+     {
+        pChannel->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE;
+     }
+
+    /* If there are hardware errors and no callback, then return failure. */
+    if(hDevice->nHwError != 0u)
+    {
+        /* Save the hardware error detected. This will be passed back to the API. */
+        *pHwError = hDevice->nHwError;
+
+        /* Clear any hardware errors detected. */
+        hDevice->nHwError = 0u;
+
+        return(ADI_UART_HW_ERROR_DETECTED);
+    }
+    else
+    {
+        return(ADI_UART_SUCCESS);
+    }
+}
+
+/*! \endcond */
+
+
+/*!
+ * @brief       Submit the buffer for transmitting the data in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING.
+ *              Call to this function will not return until the entire buffer is transmitted.
+ *              Returns error if this function is called when device is operating in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING.
+ *              i.e Function "adi_uart_SubmitTxBuffer()" is called and the transfer is not yet complete.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  pBuffer    Pointer to data supplied by the API that is to be transmitted.
+ * @param [in]  nBufSize   Size of the buffer(in bytes). Must be smaller than 1024 bytes for DMA transfers.
+ * @param [in]  bDMA       Submit the buffer using the DMA flag.
+ * @param [out] pHwError   Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status.
+ *                         If there is no hardware event, this will be 0.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                             Successfully transmitted the data from the submitted buffer.
+ *    - #ADI_UART_HW_ERROR_DETECTED                   Hardware error(s) detected. "pHwError" can be checked for the specific error code(s).
+ *    - #ADI_UART_FAILED                          [D] Generic failure. In this case the size of the data buffer we are trying
+ *                                                    to submit is NULL.
+ *    - #ADI_UART_INVALID_DATA_TRANSFER_MODE      [D] Device is operating in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. This
+ *                                                    operation is only allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING.
+ *    - #ADI_UART_OPERATION_NOT_ALLOWED           [D] Device direction is set up as #ADI_UART_DIR_RECEIVE, so we can not complete
+ *                                                    a transmit operation. The required directions are #ADI_UART_DIR_TRANSMIT or
+ *                                                    #ADI_UART_DIR_BIDIRECTION.
+ *    - #ADI_UART_INVALID_HANDLE                  [D] Invalid UART device handle.
+ *    - #ADI_UART_INVALID_POINTER                 [D] The pointer to the buffer being submitted is a NULL.
+ *    - #ADI_UART_DEVICE_IN_USE                   [D] Autobaud in progress.
+ *    - #ADI_UART_INVALID_DATA_SIZE               [D] DMA transfers must be smaller than 1025 bytes.
+ *
+ * @sa  adi_uart_Read()
+ * @sa  adi_uart_SubmitTxBuffer()
+ *
+ * @note: This function is a blocking function which means that the function returns only after the completion of
+ *        buffer transmission.
+*/
+ADI_UART_RESULT adi_uart_Write(
+                               ADI_UART_HANDLE const hDevice,
+                               void           *const pBuffer,
+                               uint32_t        const nBufSize,
+                               bool            const bDMA,
+                               uint32_t             *pHwError
+                              )
+{
+
+#ifdef ADI_DEBUG
+        /* Validate the given handle. */
+        if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+        {
+            return(ADI_UART_INVALID_HANDLE);
+        }
+
+        /* Validate the pointer to the buffer memory. */
+        if(pBuffer == NULL)
+        {
+            return(ADI_UART_INVALID_POINTER);
+        }
+
+        /* Validate the buffer size. */
+        if(nBufSize == 0U )
+        {
+            return(ADI_UART_FAILED);
+        }
+
+        /* Autobaud in progress. */
+        if(hDevice->bAutobaudInProgress == true)
+        {
+            return(ADI_UART_DEVICE_IN_USE);
+        }
+
+        /* Make sure we are transmitting. */
+        if(ADI_UART_DIR_RECEIVE == hDevice->eDirection)
+        {
+            return(ADI_UART_OPERATION_NOT_ALLOWED);
+        }
+
+        /* Check for the data transfer mode (only allowed in blocking mode). */
+        if(hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING)
+        {
+            return(ADI_UART_INVALID_DATA_TRANSFER_MODE);
+        }
+
+        /* Check that there is a free buffer to use for this transmit operation. "pFreeBuffer"
+          is the next buffer available, so if it is in use we can make the assumption that
+          there are no buffers available. The start address is set to NULL once the buffer
+          has been processed.
+        */
+        if(hDevice->pChannelTx->pFreeBuffer->pStartAddress != NULL)
+        {
+            return(ADI_UART_OPERATION_NOT_ALLOWED);
+        }
+
+        /* Make sure the DMA transfer size is not too large. */
+        if((bDMA == true) && (nBufSize > DMA_TRANSFER_LIMIT))
+        {
+            return(ADI_UART_INVALID_DATA_SIZE);
+        }
+
+#endif /* ADI_DEBUG */
+
+        /* Set the data transfer mode in case it was #ADI_UART_DATA_TRANSFER_MODE_NONE. */
+        hDevice->pChannelTx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_BLOCKING;
+
+        /* Set the start address of the data buffer we are going to submit. */
+        hDevice->pChannelTx->pFreeBuffer->pStartAddress  =   pBuffer;
+
+        /* Set the buffer size to the size of the data buffer passed down from the API. */
+        hDevice->pChannelTx->pFreeBuffer->nCount         =   nBufSize;
+
+        /* Initialize the buffer index to zero because we will start shifting out
+           the Tx data from the first position of the buffer.
+        */
+        hDevice->pChannelTx->pFreeBuffer->nIndex         =   0U;
+
+        /* Mark the buffer as in use so no other transactions can use it until this one is complete. */
+        hDevice->pChannelTx->pFreeBuffer->bInUse         =   true;
+
+        /* Mark the DMA as in use. */
+        hDevice->pChannelTx->pFreeBuffer->bDMA           =   bDMA;
+
+        /* Now that this "pFreeBuffer" is no longer free for use, update the
+           "pFreeBuffer" to the other PingPong buffer. Because there are only two
+           buffers in the PingPong structure, this will be the opposite of the one
+           we just submitted. "pFreeBuffer" will only be updated during the process of
+           submitting a buffer or a read/write operation.
+        */
+        hDevice->pChannelTx->pFreeBuffer = hDevice->pChannelTx->pFreeBuffer->pNextBuffer;
+
+        hDevice->pChannelTx->pfSubmitBuffer(hDevice, hDevice->pChannelTx->pFillBuffer);
+
+        /* Block for the active buffer to complete. */
+        return(uart_PendForBuffer(hDevice, hDevice->pChannelTx, pHwError));
+}
+
+/*!
+ * @brief       Submit the buffer for reading the data in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. Call to this function will not
+ *              return until the entire buffer is filled up. Returns error if this function is called when
+ *              device is operating in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. i.e The function "adi_uart_SubmitRxBuffer()" is called
+ *              when the transfer is not yet complete.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  pBuffer    Pointer to buffer from that will be filled by the driver when data has been received.
+ * @param [in]  nBufSize   Size of the buffer(in bytes). Must be smaller than 1024 bytes for DMA transfers.
+ * @param [in]  bDMA       Submit the buffer using DMA flag.
+ * @param [out] pHwError   Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status.
+ *                         If there is no hardware event, this will be 0.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                        Successfully submitted the buffer for receiving data.
+ *    - #ADI_UART_HW_ERROR_DETECTED              Hardware error(s) detected. "pHwError" can be checked for the specific error code(s).
+ *    - #ADI_UART_FAILED                     [D] Generic failure. In this case the size of the data buffer we are trying
+ *                                               to submit is NULL.
+ *    - #ADI_UART_INVALID_DATA_TRANSFER_MODE [D] Device is operating in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. This
+ *                                               operation is only allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING.
+ *    - #ADI_UART_INVALID_HANDLE             [D] Invalid UART device handle.
+ *    - #ADI_UART_OPERATION_NOT_ALLOWED      [D] Device direction is set up as #ADI_UART_DIR_TRANSMIT, so we can not complete
+ *                                               a receive operation. The required directions are #ADI_UART_DIR_RECEIVE or
+ *                                               #ADI_UART_DIR_BIDIRECTION.
+ *    - #ADI_UART_INVALID_POINTER            [D] Pointer to the buffer being submitted is NULL.
+ *    - #ADI_UART_DEVICE_IN_USE              [D] Autobaud in progress.
+ *    - #ADI_UART_INVALID_DATA_SIZE          [D] DMA transfers must be smaller than 1025 bytes.
+ *
+ * @sa  adi_uart_Write()
+ * @sa  adi_uart_SubmitTxBuffer()
+ *
+ * @note: This function is a blocking function which means that the function returns only after the completion of
+ *        data receive.
+*/
+ADI_UART_RESULT adi_uart_Read(
+                              ADI_UART_HANDLE const hDevice,
+                              void           *const pBuffer,
+                              uint32_t        const nBufSize,
+                              bool            const bDMA,
+                              uint32_t             *pHwError
+                             )
+{
+
+#ifdef ADI_DEBUG
+     /* Validate the given handle. */
+     if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+     {
+         return(ADI_UART_INVALID_HANDLE);
+     }
+
+    /* Validate the pointer to the buffer memory. */
+    if(pBuffer == NULL)
+    {
+        return(ADI_UART_INVALID_POINTER);
+    }
+
+    /* Validate the buffer size. */
+    if(nBufSize == 0U )
+    {
+        return(ADI_UART_FAILED);
+    }
+
+    /* Autobaud in progress. */
+    if(hDevice->bAutobaudInProgress == true)
+    {
+        return(ADI_UART_DEVICE_IN_USE);
+    }
+
+    /* Make sure the UART device is configured to operate in the receive direction. */
+    if(ADI_UART_DIR_TRANSMIT == hDevice->eDirection)
+    {
+        return(ADI_UART_OPERATION_NOT_ALLOWED);
+    }
+
+    /* Check for the data transfer mode(only allowed in blocking mode).*/
+    if(hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING)
+    {
+        return(ADI_UART_INVALID_DATA_TRANSFER_MODE);
+    }
+
+    /* Check that there is a free buffer to use for this receive operation. "pFreeBuffer"
+       is the next buffer available, so if it is in use we can make the assumption that
+       there are no buffers available. The start address gets set to NULL once the buffer
+       processing has completed.
+    */
+    if(hDevice->pChannelRx->pFreeBuffer->pStartAddress != NULL)
+    {
+        return(ADI_UART_OPERATION_NOT_ALLOWED);
+    }
+
+    /* Make sure the DMA transfer size is not too large. */
+    if((bDMA == true) && (nBufSize > DMA_TRANSFER_LIMIT))
+    {
+        return(ADI_UART_INVALID_DATA_SIZE);
+    }
+
+#endif /* ADI_DEBUG */
+
+    /* Set the data transfer mode in case it was #ADI_UART_DATA_TRANSFER_MODE_NONE.
+       This will be set back to #ADI_UART_DATA_TRANSFER_MODE_NONE once this
+       transaction is complete.
+    */
+    hDevice->pChannelRx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_BLOCKING;
+
+    /* Set the start address of the buffer you are going to submit. */
+    hDevice->pChannelRx->pFreeBuffer->pStartAddress  =  pBuffer;
+
+    /* Set the size of the buffer. */
+    hDevice->pChannelRx->pFreeBuffer->nCount         =  nBufSize;
+
+    /* Initialize the buffer index to 0, because as we receive data it will be put into
+       the buffer starting at the first position.
+    */
+    hDevice->pChannelRx->pFreeBuffer->nIndex         =  0U;
+
+    /* Mark the buffer as in use. */
+    hDevice->pChannelRx->pFreeBuffer->bInUse         =  true;
+
+    /* Mark the DMA as in use. */
+    hDevice->pChannelRx->pFreeBuffer->bDMA           =  bDMA;
+
+
+    /* Now that this "pFreeBuffer" is no longer free for use, update the
+       "pFreeBuffer" to the other PingPong buffer. Because there are only two
+       buffers in the PingPong structure, this will be the opposite of the one
+       we just submitted. "pFreeBuffer" will only be updated during the process of
+       submitting a buffer or a read/write operation.
+    */
+    hDevice->pChannelRx->pFreeBuffer = hDevice->pChannelRx->pFreeBuffer->pNextBuffer;
+
+    hDevice->pChannelRx->pfSubmitBuffer(hDevice, hDevice->pChannelRx->pFillBuffer);
+
+    /* Block for the active buffer to complete. */
+    return(uart_PendForBuffer(hDevice, hDevice->pChannelRx, pHwError));
+}
+
+/*! \cond PRIVATE */
+
+/*
+ * @brief       Pends for data transaction to complete. Buffer gets returned to API.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  pChannel   Pointer to UART channel data structure.
+ * @param [out] pBuffer    Address of buffer on which data transfer being carried out.
+ * @param [out] pHwError   Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status.
+ *                         If there is no hardware event, this will be 0.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS            Successfully got buffer.
+ *    - #ADI_UART_HW_ERROR_DETECTED  Hardware error(s) detected. "pHwError" can be checked for the specific error code(s).
+ *
+*/
+static ADI_UART_RESULT uart_PendForBuffer(
+                                           ADI_UART_HANDLE        const hDevice,
+                                           ADI_UART_DATA_CHANNEL       *pChannel,
+                                           uint32_t                    *pHwError
+                                          )
+{
+
+    /* Wait until the peripheral has finished processing the buffer. */
+    SEM_PEND(pChannel,ADI_UART_FAILED);
+
+     /* Reinitialize the start address to NULL so this buffer can be used for a new transaction. */
+     pChannel->pActiveBuffer->pStartAddress = NULL;
+
+      /* Now that the desired data has either been transmitted or received, this buffer is no longer
+         in use. We can update "pActiveBuffer" to point to the next buffer that will become or is already
+         active. This will only be updated in places where transactions are completed,
+         such as uart_PendForBuffer() and uart_GetBuffer().
+      */
+       pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer;
+
+     /* Set the data transfer mode to none so that the next transfer can be either in blocking or in nonblocking mode.
+        Only if there are no active buffers.
+     */
+     if(pChannel->pActiveBuffer->pStartAddress == NULL)
+     {
+        pChannel->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE;
+     }
+
+      /* If there are hardware errors and no callback, then return failure. */
+      if(hDevice->nHwError != 0u)
+      {
+          /* Save the hardware error detected. This will be passed back to the API. */
+          *pHwError = hDevice->nHwError;
+
+          /* Clear any hardware errors detected. */
+          hDevice->nHwError = 0u;
+
+          return(ADI_UART_HW_ERROR_DETECTED);
+      }
+      else
+      {
+          return(ADI_UART_SUCCESS);
+      }
+
+}
+/*! \endcond */
+
+
+/*!
+ * @brief       Peek function to know if an empty buffer is avilable.
+ *
+ * @param [in]  hDevice      Device handle obtained from adi_uart_Open().
+ * @param [out] pbAvailable  Pointer to a boolean variable. Contains "true" if there is an empty buffer
+ *                           and a call to "adi_uart_GetTxBuffer" is ensured to be successful. Contains
+ *                           "false" if there is no empty buffer.
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                   Successfully retrieved the status of availability of the buffer.
+ *    - #ADI_UART_INVALID_HANDLE        [D] Invalid UART device handle.
+ *    - #ADI_UART_OPERATION_NOT_ALLOWED [D] Call to this function is not allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING.
+ *
+ * @sa  adi_uart_GetTxBuffer()
+ * @sa  adi_uart_IsRxBufferAvailable
+ *
+ */
+
+ADI_UART_RESULT adi_uart_IsTxBufferAvailable(
+                                              ADI_UART_HANDLE const hDevice,
+                                              bool           *const pbAvailable
+                                            )
+{
+
+#ifdef ADI_DEBUG
+    /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* This function is only allowed to be called when the channel is operating in NONBLOCKING mode. */
+    if(hDevice->pChannelTx->eDataTranferMode ==  ADI_UART_DATA_TRANSFER_MODE_BLOCKING)
+    {
+        return(ADI_UART_OPERATION_NOT_ALLOWED);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Initialize to "false" in case of an error. */
+    *pbAvailable = false;
+
+    /* Make sure the buffer has not already been processed. This would mean that there are
+       currently no active buffers. This is only updated in adi_uart_GetBuffer(), which is
+       called once a transaction has completed.
+    */
+    if (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)
+    {
+        /* If the buffer has reached the interrupt handler, "bInUse" will be
+           updated so we know that the buffer has become available.
+        */
+        if (hDevice->pChannelTx->pActiveBuffer->bInUse == false)
+        {
+            *pbAvailable = true;
+        }
+    }
+    return(ADI_UART_SUCCESS);
+}
+
+/*!
+ * @brief       Peek function to know if a filled buffer is available.
+ *
+ *
+ * @param [in]  hDevice      Device handle obtained from adi_uart_Open().
+ * @param [out] pbAvailable  Pointer to a boolean variable. Contains "true" if there is an empty buffer
+ *                           and a call to "adi_uart_GetTxBuffer" is ensured to be successful. Contains
+ *                           "false" if there is no empty buffer.
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                   Successfully retrieved the status of availability of the buffer.
+ *    - #ADI_UART_INVALID_HANDLE        [D] Invalid UART device handle.
+ *    - #ADI_UART_OPERATION_NOT_ALLOWED [D] Call to this function is not allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING.
+ *
+ * @sa  adi_uart_GetRxBuffer()
+ *
+ */
+ADI_UART_RESULT    adi_uart_IsRxBufferAvailable(
+                                                 ADI_UART_HANDLE const hDevice,
+                                                 bool           *const pbAvailable
+                                                )
+{
+
+#ifdef ADI_DEBUG
+    /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* This function is only allowed to be called when the channel is operating in NONBLOCKING mode. */
+    if(hDevice->pChannelRx->eDataTranferMode ==  ADI_UART_DATA_TRANSFER_MODE_BLOCKING)
+    {
+        return(ADI_UART_OPERATION_NOT_ALLOWED);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Initialize to "false" in case of an error. */
+    *pbAvailable = false;
+
+    /* Make sure the buffer has not already been processed. This would mean that there are
+       currently no active buffers. This is only updated in adi_uart_GetBuffer(), which is
+       called once a transaction has completed.
+    */
+    if(hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)
+    {
+        /* If the buffer has reached the interrupt handler, "bInUse" will be
+           updated so we know that the buffer has become available.
+        */
+        if (hDevice->pChannelRx->pActiveBuffer->bInUse == false)
+        {
+            *pbAvailable = true;
+        }
+    }
+    return(ADI_UART_SUCCESS);
+}
+
+/*!
+ * @brief       Function to let the API know if all the data had been drained from the Tx shift registers.
+ *
+ * @param [in]  hDevice      Device handle obtained from adi_uart_Open().
+ * @param [out] pbComplete   Pointer to a boolean variable. Contains "true" if there is no data left in the
+ *                           device to transmit and device can be disabled without data loss. Contains "false"
+ *                           if the data transmission is not complete.
+ * @return      Status
+ *    - #ADI_UART_SUCCESS            Successfully retrieved the status of data transmission.
+ *    - #ADI_UART_INVALID_HANDLE [D] Specified handle is invalid.
+ *
+ * @note  adi_uart_getTxBuffer() or the callback may indicate that a transmit transaction is complete when the
+ *        device is using the DMA. This is because the interrupt will trigger once the transmit holding register is empty.
+          However, there may still be a some data in the shift register. If the transmit channel needs
+ *        to be closed then the application must poll the transmit channel to see if all data has indeed been transmitted before
+ *        shutting down the channel. Otherwise data will be lost.
+ *
+ */
+
+ADI_UART_RESULT adi_uart_IsTxComplete(
+                                     ADI_UART_HANDLE const hDevice,
+                                     bool           *const pbComplete
+                                     )
+{
+#ifdef ADI_DEBUG
+    /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Initialize to false. */
+    *pbComplete = false;
+
+    /* If the register is empty, set the return variable to "true".
+       This register is empty, when the value becomes a 1.
+    */
+    if((hDevice->pUARTRegs->LSR & BITM_UART_LSR_TEMT) == BITM_UART_LSR_TEMT)
+    {
+        *pbComplete = true;
+    }
+    return(ADI_UART_SUCCESS);
+}
+
+
+/*!
+ * @brief       Registering a callback function.
+ *
+ * @param [in]  hDevice       Device handle obtained from adi_uart_Open().
+ * @param [in]  pfCallback    Function pointer to callback. Passing a NULL pointer will unregister
+ *                            the callback function.
+ * @param [in]  pCBParam      Callback function parameter.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                Successfully registered callback function.
+ *    - #ADI_UART_DEVICE_IN_USE      [D] This operation is not allowed when a data transfer is in progress.
+ *    - #ADI_UART_INVALID_HANDLE     [D] Invalid UART device handle.
+ *
+ *
+*/
+ADI_UART_RESULT adi_uart_RegisterCallback(
+                                          ADI_UART_HANDLE const hDevice,
+                                          const ADI_CALLBACK    pfCallback,
+                                          void           *const pCBParam
+                                         )
+{
+
+#ifdef ADI_DEBUG
+    /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* Make sure there are no active buffers on any active channel and autobaud is not in progress. */
+    if(((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) ||
+       ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)) ||
+       (hDevice->bAutobaudInProgress == true))
+    {
+        return(ADI_UART_DEVICE_IN_USE);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Set the device callback. */
+    hDevice->pfCallback = pfCallback;
+
+    /* Set the callback parameter. */
+    hDevice->pCBParam = pCBParam;
+
+    return(ADI_UART_SUCCESS);
+}
+
+
+/*!
+ * @brief        Configuration of UART data.
+ *
+ * @details      Sets the configuration parameters for the specified UART device such as wordlength, whether to
+ *               enable/disable the parity, and the number of stop bits. This function returns an error if the
+ *               device has active data or autobaud is in progress.
+ *
+ * @param [in]  hDevice      Device handle obtained from adi_uart_Open().
+ * @param [in]  eParity      Specify the type of parity check for the UART device.
+ * @param [in]  eStopBits    Specify the stop-bits for the UART device.
+ * @param [in]  eWordLength  Specify the word size of the data for the UART device.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                Successfully set the data configuration.
+ *    - #ADI_UART_DEVICE_IN_USE      [D] This operation is not allowed when a data transfer or autobaud is in progress.
+ *    - #ADI_UART_INVALID_HANDLE     [D] Invalid UART device handle.
+ *
+*/
+ADI_UART_RESULT adi_uart_SetConfiguration(
+                                         ADI_UART_HANDLE   const hDevice,
+                                         ADI_UART_PARITY   const eParity,
+                                         ADI_UART_STOPBITS const eStopBits,
+                                         ADI_UART_WORDLEN  const eWordLength
+                                         )
+{
+#ifdef ADI_DEBUG
+    /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* Make sure there are no active buffers on any active channel and autobaud is not in progress. */
+    if(((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) ||
+       ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)) ||
+       (hDevice->bAutobaudInProgress == true))
+    {
+        return(ADI_UART_DEVICE_IN_USE);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Clear all the fields.  */
+    uint16_t nDataCfg = hDevice->pUARTRegs->LCR & (uint16_t)(~(BITM_UART_LCR_WLS |BITM_UART_LCR_STOP |BITM_UART_LCR_PEN));
+
+    /* Construct the configuration word. */
+    nDataCfg |= (uint16_t)(((uint16_t)((uint16_t)eWordLength |(uint16_t)eStopBits) |(uint16_t)eParity));
+
+    /* Write to the register */
+    hDevice->pUARTRegs->LCR = nDataCfg;
+
+    /* Return Success */
+    return(ADI_UART_SUCCESS);
+}
+
+/*!
+ * @brief        Set baudrate by configuring the fractional dividors.
+ *
+ * @details      Baudrate is calculated as per below equation.
+ *
+ *               Baudrate = (UARTCLK / (nDivM + nDivN/2048)*pow(2,nOSR+2)* nDivC)).
+ *
+ * @param [in]  hDevice      Device handle obtained from adi_uart_Open().
+ * @param [in]  nDivC        Specify the "nDivC" in the above equation.
+ * @param [in]  nDivM        Specify the "nDivM" in the above equation.
+ * @param [in]  nDivN        Specify the "nDivN" in the above equation.
+ * @param [in]  nOSR         Specify the "nOSR" " in the above equation.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                 Successfully set the baudrate for the device.
+ *    - #ADI_UART_INVALID_HANDLE     [D]  Invalid UART device handle.
+ *    - #ADI_UART_DEVICE_IN_USE      [D]  Device is in use
+ *    - #ADI_UART_INVALID_PARAMETER  [D]  Input for baud rate values are out of range.
+ *
+ *   @sa  adi_uart_GetBaudRate()
+ *   @sa  adi_uart_EnableAutobaud();
+ *
+ *   @note It is expected that initialization of the power management
+ *         driver is done before calling this function.
+ *
+ */
+ADI_UART_RESULT adi_uart_ConfigBaudRate(
+                                       ADI_UART_HANDLE const hDevice,
+                                       uint16_t        const nDivC,
+                                       uint8_t         const nDivM,
+                                       uint16_t        const nDivN,
+                                       uint8_t         const nOSR
+                                       )
+{
+#ifdef ADI_DEBUG
+    /* Validate the given handle */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* Make sure there are no active buffers on any active channel. */
+    if(((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) ||
+       ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)))
+    {
+        return(ADI_UART_DEVICE_IN_USE);
+    }
+
+    /* Check if the given baudrate is valid */
+    if( (nDivM < 1u) || (nDivM > 3u)|| (nDivN > 2047u ) || (nOSR > 3u))
+    {
+        return ADI_UART_INVALID_PARAMETER;
+    }
+
+#endif /* ADI_DEBUG */
+
+    /* Write back the register contents for baudrate detection in the hardware. */
+    hDevice->pUARTRegs->DIV  =  nDivC;
+    hDevice->pUARTRegs->FBR  =  (uint16_t)((uint16_t)nDivN | (uint16_t)((uint16_t)nDivM <<BITP_UART_FBR_DIVM)) | (uint16_t)BITM_UART_FBR_FBEN;
+    hDevice->pUARTRegs->LCR2 = nOSR;
+
+    return(ADI_UART_SUCCESS);
+}
+
+
+/*!
+ * @brief       Get the baudrate of the UART device instance. This is used in the scenario when a callback has not been initialized.
+ *              This allows the the API to know if autobaud is complete. If this returns a baudrate other than 0,
+ *              it indicates that the autobaud completed, otherwise autobaud is still in progress.
+ *
+ * @param [in]   hDevice         Device handle obtained from adi_uart_Open().
+ * @param [out]  pnBaudRate      Pointer to a location where baudrate is to be written.
+ * @param [out]  pAutobaudError  Pointer to an integer that will hold the value of any baudrate error(s), that correlates with
+ *                               #ADI_UART_AUTOBAUD_ERRORS. This will be 0 if there are no errors.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                   Successfully retrieved the baudrate.
+ *    - #ADI_UART_AUTOBAUD_ERROR_DETECTED   There has been an autobaud error. The API can get the specific error(s)
+ *                                          by checking "pAutobaudError".
+ *    - #ADI_UART_INVALID_HANDLE        [D] Invalid UART device handle.
+ *    - #ADI_UART_INVALID_POINTER       [D] The pointer to baudrate or autobaud error is NULL.
+
+ *
+*/
+ADI_UART_RESULT adi_uart_GetBaudRate(
+                                      ADI_UART_HANDLE const     hDevice,
+                                      uint32_t                 *pnBaudRate,
+                                      uint32_t                 *pAutobaudError
+                                    )
+{
+
+#ifdef ADI_DEBUG
+    /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* Validate pointers. */
+    if(pnBaudRate == NULL)
+    {
+        return(ADI_UART_INVALID_POINTER);
+    }
+
+#endif /* ADI_DEBUG */
+
+    /* If an error occured during autobaud this value will be set to a
+       non-zero value. The specific error can be found by checking against
+       #ADI_UART_EVENT.
+    */
+    if(hDevice->nAutobaudError != 0u)
+    {
+      /* Save the autobaud error to pass back to the API.*/
+      *pAutobaudError = hDevice->nAutobaudError;
+
+      /* Clear the autobaud errors found. */
+      hDevice->nAutobaudError = 0u;
+
+      return(ADI_UART_AUTOBAUD_ERROR_DETECTED);
+    }
+
+    /* Return the baudrate. If this is 0, then autobaud has not completed. */
+    *pnBaudRate = hDevice->nBaudRate;
+
+    return(ADI_UART_SUCCESS);
+}
+
+
+/*!
+ * @brief       Enable/Disable UART autobaud detection as well as configures the device for autobaud detection.
+ *
+ * @details     The baud rate is detected using the hardware support.
+ *              After the baud rate is detected the interrupt handler is notified of the completion.
+ *              When a callback is not registered with UART driver, the API adi_uart_GetBaudRate()
+ *              can be used to know if autobaud is complete. Autobaud needs to be disabled in order to
+ *              clear the internal counter and to close the device.
+ *
+ * @param [in]  hDevice                 Handle to UART device whose autobaud detection to be enabled/disabled.
+ * @param [in]  bEnable                 Boolean flag to indicate whether to enable or disable the autobaud.
+ * @param [in]  bAutobaudCallbackMode   Use a callback to report autobaud errors or type #ADI_UART_AUTOBAUD_ERRORS.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                       Successfully enabled/disabled Autobaud detection.
+ *    - #ADI_UART_DEVICE_IN_USE             [D] Trying to enable/disable Autobaud when
+ *                                              dataflow is enabled or autobaud is in progress.
+ *    - #ADI_UART_INVALID_HANDLE            [D] Invalid UART device handle.
+ *
+ * @sa  adi_uart_GetBaudRate()
+ *
+ * @note: For autobaud we assume the key character being used is a carrige return (0xD), so the start edge count is
+ *        hardcoded to the second edge (first edge after start edge) and the last edge count is set to the fouth edge.
+ *        This will give us a total bit count of 8 bits that we will time in order to figure out the baud rate (bits/second).
+ */
+ADI_UART_RESULT adi_uart_EnableAutobaud(
+                                        ADI_UART_HANDLE          const hDevice,
+                                        bool                     const bEnable,
+                                        bool                     const bAutobaudCallbackMode
+                                       )
+{
+
+#ifdef ADI_DEBUG
+     /* Validate the given handle */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* Make sure there are no active buffers on any active channel and autobaud is not in progress. */
+    if(((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) ||
+       ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)))
+    {
+        return(ADI_UART_DEVICE_IN_USE);
+    }
+
+#endif /* ADI_DEBUG */
+
+    if(bEnable)
+    {
+        /* Enable Autobaud, timeout interrupt and done interrupt in the autobaud control register.
+           Set the starting edge trigger to the second edge. Set the ending edge count to
+           the fourth edge, for the carrige return key character (0xD).
+        */
+        hDevice->pUARTRegs->ACR |=(BITM_UART_ACR_ABE | BITM_UART_ACR_DNIEN | BITM_UART_ACR_TOIEN |(1u << 4u) | (3u << 8u));
+
+        /* Initialize device baudrate to 0. This will be set once autobaud is complete. */
+        hDevice->nBaudRate = 0u;
+
+        /* Change the state to indicate autobaud is in progress. */
+        hDevice->bAutobaudInProgress = true;
+
+        /* Set the callback mode for autobaud based on the user input. */
+        hDevice->bAutobaudCallbackMode = bAutobaudCallbackMode;
+    }
+    else
+    {
+        /* Change the state to indicate autobaud is not in progress. */
+        hDevice->bAutobaudInProgress = false;
+
+        /* Disable Autobaud, timeout interrupt and done interrupt in the autobaud control register. */
+        hDevice->pUARTRegs->ACR |= (uint16_t)(~(uint32_t)BITM_UART_ACR_ABE | ~(uint32_t)BITM_UART_ACR_DNIEN | ~(uint32_t)BITM_UART_ACR_TOIEN);
+
+        /* Initialize device baudrate to 0. */
+        hDevice->nBaudRate = 0u;
+    }
+
+    return ADI_UART_SUCCESS;
+}
+
+/*!
+ * @brief       Forces the UART to send out a break signal.
+ *
+ * @details     Sets the UART Tx pin to a logic-low/high (depending upon the
+ *              Tx polarity) asynchronously. The UART keeps transmitting break
+ *              until it is disabled to send the break.
+ *
+ * @param [in]  hDevice             Handle to the UART whose Tx is forced to
+ *                                  send a break.
+ * @param [in]  bEnable             Flag which indicates whether to enable or
+ *                                  disable transmitting the break.
+ *
+ * @return      Status
+ *
+ * - #ADI_UART_SUCCESS              If successfully enabled or disabled sending break.
+ * - #ADI_UART_INVALID_HANDLE   [D] If the given UART handle is invalid.
+ */
+ADI_UART_RESULT adi_uart_ForceTxBreak(
+                                      ADI_UART_HANDLE         const hDevice,
+                                      bool                    const bEnable
+                                     )
+{
+
+#ifdef ADI_DEBUG
+     /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+#endif /* ADI_DEBUG */
+
+    if(bEnable == true)
+    {
+        /* Set the force break bit. */
+        hDevice->pUARTRegs->LCR    |= BITM_UART_LCR_BRK;
+    }
+    else
+    {
+        /* Clear the force break bit. */
+        hDevice->pUARTRegs->LCR    &= (uint16_t)~(BITM_UART_LCR_BRK);
+    }
+
+    return ADI_UART_SUCCESS;
+}
+
+/*!
+ * @brief       Enable/Disable the loopback for the specified UART device.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  bEnable    Boolean flag to indicate whether to enable or disable the loopback mode.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS            Successfully enable/disable the loopback.
+ *    - #ADI_UART_INVALID_HANDLE     Invalid  UART device handle.
+ *
+*/
+ADI_UART_RESULT adi_uart_EnableLoopBack(
+                                        ADI_UART_HANDLE const hDevice,
+                                        bool            const bEnable
+                                       )
+{
+
+#ifdef ADI_DEBUG
+     /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+#endif /* ADI_DEBUG */
+
+    if(true == bEnable)
+    {
+        /* Enable loopback. */
+        hDevice->pUARTRegs->MCR |= (BITM_UART_MCR_LOOPBACK);
+    }
+    else
+    {
+        /* Disable loopback. */
+        hDevice->pUARTRegs->MCR &= (uint16_t)~(BITM_UART_MCR_LOOPBACK);
+    }
+    return(ADI_UART_SUCCESS);
+}
+
+/*!
+ * @brief       Sets the RX FIFO trigger level. This will be the amount of data in the FIFO
+ *              that will trigger an interrupt.
+ *
+ *
+ * @param [in]  hDevice         Device handle obtained from adi_uart_Open().
+ * @param [in]  eTriglevel      Trigger level to be set in terms of number of bytes.
+ *
+ * @return      Status
+ *  - #ADI_UART_SUCCESS             Successfully set the trigger level.
+ *  - #ADI_UART_INVALID_HANDLE  [D] The given UART handle is invalid.
+ */
+ADI_UART_RESULT adi_uart_SetRxFifoTriggerLevel(
+                                               ADI_UART_CONST_HANDLE         const hDevice,
+                                               ADI_UART_TRIG_LEVEL           const eTriglevel
+                                              )
+{
+#ifdef ADI_DEBUG
+     /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Clear existing FIFO trigger level. */
+    hDevice->pUARTRegs->FCR &= (uint16_t)~BITM_UART_FCR_RFTRIG;
+
+    /* Set the FIFO trigger level. */
+    hDevice->pUARTRegs->FCR |= (uint16_t)eTriglevel;
+
+    return(ADI_UART_SUCCESS);
+}
+/*!
+ * @brief       Enables internal FIFO as to work in 16550 mode. This helps to minimize system overhead
+ *              and maximize system efficiency.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  bEnable    Boolean flag to indicate whether to enable or disable FIFO.
+ *
+ * @return      Status
+ *  - #ADI_UART_SUCCESS              If successfully enabled FIFO for UART device.
+ *  - #ADI_UART_INVALID_HANDLE   [D] The given UART handle is invalid.
+ */
+ADI_UART_RESULT adi_uart_EnableFifo(
+                                     ADI_UART_HANDLE         const hDevice,
+                                     bool                    const bEnable
+                                    )
+{
+
+#ifdef ADI_DEBUG
+     /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+#endif /* ADI_DEBUG */
+
+    if(bEnable == true)
+    {
+       /* Enable TX/RX FIFO. */
+       hDevice->pUARTRegs->FCR    |=  BITM_UART_FCR_FIFOEN;
+       hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ERBFI);
+
+       hDevice->bRxFifoEn = true;
+
+    }
+    else
+    {
+       /* Disable TX/RX FIFO. */
+       hDevice->pUARTRegs->FCR    &= (uint16_t)~(BITM_UART_FCR_FIFOEN);
+
+       hDevice->bRxFifoEn = false;
+    }
+
+    return ADI_UART_SUCCESS;
+}
+
+/*!
+ * @brief      To flush the TX FIFO.
+ *
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ *
+ *
+ * @return      Status
+ *  - #ADI_UART_SUCCESS             Successfully flushed TX Fifo.
+ *  - #ADI_UART_INVALID_HANDLE  [D] The given UART handle is invalid.
+ */
+ADI_UART_RESULT adi_uart_FlushTxFifo(
+                                     ADI_UART_CONST_HANDLE         const hDevice
+                                    )
+{
+
+#ifdef ADI_DEBUG
+     /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Flush the Tx FIFO. */
+    hDevice->pUARTRegs->FCR    |=  BITM_UART_FCR_TFCLR;
+
+    return(ADI_UART_SUCCESS);
+}
+
+/*!
+ * @brief       Flush the RX FIFO.
+ *
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ *
+ *
+ * @return      Status
+ *  - #ADI_UART_SUCCESS              Successfully flushed RX Fifo.
+ *  - #ADI_UART_INVALID_HANDLE   [D] The given UART handle is invalid.
+ */
+ADI_UART_RESULT adi_uart_FlushRxFifo(
+                                      ADI_UART_CONST_HANDLE         const hDevice
+                                     )
+{
+
+#ifdef ADI_DEBUG
+     /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Flush RX FIFO. */
+    hDevice->pUARTRegs->FCR    |=  BITM_UART_FCR_RFCLR;
+
+    return ADI_UART_SUCCESS;
+}
+
+/*!
+ * @brief      Flush the Rx channel and disable interrupts. This will stop any buffers in flight and
+ *             clear out any data that was in the RX holding register as well as the Rx fifo. Once this is done,
+ *             in order to turn back on Rx interrupts, a new transaction will need to be started (adi_uart_Read()
+ *             or adi_uart_SubmitRxBuffer()).
+ *
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ *
+ * @return      Status
+ *  - #ADI_UART_SUCCESS                       Successfully flushed the Rx channel.
+ *  - #ADI_UART_INVALID_HANDLE            [D] The given UART handle is invalid.
+ */
+ADI_UART_RESULT adi_uart_FlushRxChannel(
+                                         ADI_UART_CONST_HANDLE  const hDevice
+                                        )
+{
+
+#ifdef ADI_DEBUG
+     /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Disable receive interrupts in PIO mode as well as DMA mode. */
+    hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ERBFI | BITM_UART_IEN_EDMAR);
+
+    /* Clear any data in the Rx Fifo. */
+    hDevice->pUARTRegs->FCR |=  BITM_UART_FCR_RFCLR;
+
+    /* Reset the buffers to 0. */
+    memset(hDevice->pChannelRx->PingPong,0, sizeof (hDevice->pChannelRx->PingPong));
+
+    hDevice->pChannelRx->PingPong[0].pNextBuffer  = &hDevice->pChannelRx->PingPong[1];
+    hDevice->pChannelRx->PingPong[1].pNextBuffer  = &hDevice->pChannelRx->PingPong[0];
+
+    /* Reset the buffer pointers. */
+    hDevice->pChannelRx->pActiveBuffer = &hDevice->pChannelRx->PingPong[0];
+    hDevice->pChannelRx->pFreeBuffer = &hDevice->pChannelRx->PingPong[0];
+    hDevice->pChannelRx->pFillBuffer = &hDevice->pChannelRx->PingPong[0];
+
+    /* Dummy read to flush the RX register. */
+    hDevice->pUARTRegs->RX;
+
+    return(ADI_UART_SUCCESS);
+}
+
+/*!
+ * @brief      Flush the Tx channel and disable interrupts.This will stop any buffers in flight and
+ *             clear out any data that was in the TX holding register. Any data in the TX shift register
+ *             will still finish transmitting.
+ *
+ *
+ * @param [in]  hDevice       Device handle to UART device obtained when an UART device is opened successfully.
+ *
+ * @return      Status
+ *  - #ADI_UART_SUCCESS                   Successfully flushed the Tx channel.
+ *  - #ADI_UART_INVALID_HANDLE        [D] The given UART handle is invalid.
+ */
+ADI_UART_RESULT adi_uart_FlushTxChannel(ADI_UART_CONST_HANDLE  const hDevice)
+{
+
+#ifdef ADI_DEBUG
+     /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Disable transmit interrupts in PIO mode as well as DMA mode. */
+    hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ETBEI | BITM_UART_IEN_EDMAT);
+
+    /* Clear any data in the Rx Fifo. */
+    hDevice->pUARTRegs->FCR |=  BITM_UART_FCR_TFCLR;
+
+    /* Reset the buffers to 0. */
+    memset(hDevice->pChannelTx->PingPong,0, sizeof (hDevice->pChannelTx->PingPong));
+
+    hDevice->pChannelTx->PingPong[0].pNextBuffer  = &hDevice->pChannelTx->PingPong[1];
+    hDevice->pChannelTx->PingPong[1].pNextBuffer  = &hDevice->pChannelTx->PingPong[0];
+
+    /* Reset the buffer pointers. */
+    hDevice->pChannelTx->pActiveBuffer = &hDevice->pChannelTx->PingPong[0];
+    hDevice->pChannelTx->pFreeBuffer = &hDevice->pChannelTx->PingPong[0];
+    hDevice->pChannelTx->pFillBuffer = &hDevice->pChannelTx->PingPong[0];
+
+    return(ADI_UART_SUCCESS);
+}
+
+
+/*! \cond PRIVATE */
+
+void UART0_Int_Handler(void)
+{
+    ISR_PROLOG();
+    ADI_UART_HANDLE hDevice = (ADI_UART_HANDLE)uart_device_info[0].hDevice;
+    Common_Uart_Interrupt_Handler(hDevice);
+#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u)
+    ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_UART);    
+#endif
+    ISR_EPILOG();
+    return;
+}
+
+#if defined (__ADUCM4x50__)
+
+void UART1_Int_Handler(void)
+{
+    ISR_PROLOG();
+    ADI_UART_HANDLE hDevice = (ADI_UART_HANDLE)uart_device_info[1].hDevice;
+    Common_Uart_Interrupt_Handler(hDevice);
+#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u)
+    ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_UART);    
+#endif
+    ISR_EPILOG();
+    return;
+}
+#endif
+
+static void Common_Uart_Interrupt_Handler(ADI_UART_HANDLE hDevice)
+{
+      switch(hDevice->pUARTRegs->IIR & BITM_UART_IIR_STAT )
+    {
+        /* Tx buffer empty interrupt. This means that the data has successfully left the holding register and is
+           now in transmit shift register or has completed its transfer.
+        */
+        case ENUM_UART_IIR_STAT_ETBEI:
+          uart_TxDataHandler(hDevice);
+          break;
+
+        /* Rx buffer FIFO timeout interrupt. This means that we have data in the RX FIFO
+           but there is not enough data to trigger an interrupt so we will process this data here.
+        */
+        case ENUM_UART_IIR_STAT_RFTOI:
+          uart_RxDataHandler(hDevice);
+          break;
+
+        /* Rx buffer full interrupt. This means that the RX buffer has finished receiving data. */
+        case ENUM_UART_IIR_STAT_ERBFI:
+          uart_RxDataHandler(hDevice);
+          break;
+
+        /* Line status interrupt. */
+        case ENUM_UART_IIR_STAT_RLSI:
+        {
+            /* Initialze the line status event to 0. */
+            uint32_t nEvent = 0u;
+
+            /* Get the interrupts status. */
+            uint16_t  nStatus = hDevice->pUARTRegs->LSR;
+
+            /* If a break signal is detected.. */
+            if((BITM_UART_LSR_BI & nStatus) == BITM_UART_LSR_BI)
+            {
+                /* Dummy read to flush the RX register. We do this because
+                   we do not actaully want to do anything with this data as it
+                   is only a break indicator. */
+                hDevice->pUARTRegs->RX;
+
+                /* Set the event to a break interrupt. */
+                nEvent  = (uint32_t)ADI_UART_BREAK_INTERRUPT;
+            }
+
+            /* Ignore the framing error if the break is asserted.
+               We do this because a break can trigger a false framing error.
+            */
+            else if((BITM_UART_LSR_FE & nStatus) == BITM_UART_LSR_FE)
+            {
+                /* Set the event to show a framing error has been detected. */
+                nEvent |= (uint32_t)ADI_UART_HW_ERR_FRAMING;
+            }
+            else
+            {
+              /* Do nothing. This is required for MISRA. */
+            }
+
+            if((BITM_UART_LSR_PE & nStatus) == BITM_UART_LSR_PE)
+            {
+                /* Set the event to show a parity error has been detected. */
+                nEvent  |=  (uint32_t)ADI_UART_HW_ERR_PARITY;
+            }
+            if((BITM_UART_LSR_OE & nStatus) == BITM_UART_LSR_OE)
+            {
+                /* Set the event to show a hardware overrun error has been detected, meaning receive data has
+                   been overwritten.
+                */
+                nEvent |= (uint32_t)ADI_UART_HW_ERR_OVERRUN;
+            }
+
+            /* If there was an event and autobaud is not in progress, notify the API. */
+            if((nEvent != 0u) && (hDevice->bAutobaudInProgress == false))
+            {
+                /* Set the UART device hw error bit field. This will allow us to return the
+                   specific failure to the application once we return from this ISR.
+                */
+                hDevice->nHwError |= nEvent;
+                uart_ManageProcessedBuffer(hDevice, hDevice->pChannelRx, ADI_UART_EVENT_HW_ERROR_DETECTED);
+            }
+            break;
+         }
+
+         /* If there was a modem status interrupt. For our purposes, we will only check if this is related to autobaud. */
+         case ENUM_UART_IIR_STAT_EDSSI:
+         {
+#if (ADI_UART_CFG_ENABLE_AUTOBAUD == 1)
+            /* Initialize the autobaud event to 0. */
+            uint32_t nEvent = 0u;
+
+            /* Get the autobaud interrupt status but not the counter value. */
+            uint16_t nStatus =  hDevice->pUARTRegs->ASRL & 0xFu;
+
+            /* Read the autobaud control register to see if autobaud was enabled. */
+            uint16_t  acr = (hDevice->pUARTRegs->ACR & BITM_UART_ACR_ABE);
+
+            /* If there is an autobaud event and autobaud is enabled */
+            if((nStatus != 0u) && (acr != 0u))
+            {
+                uint32_t nClock;
+                uint32_t nCount;
+
+                /*Get the clock frequency. */
+                if(adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK,&nClock) != ADI_PWR_SUCCESS)
+                {
+                  nClock = 0u;
+                }
+
+                /* Get the autobaud counter bits 12-19. */
+                nCount = (uint32_t)hDevice->pUARTRegs->ASRH << 12u;
+
+                /* Get the autobaud counter bits 0-11. */
+                nCount |= (uint32_t)hDevice->pUARTRegs->ASRL >> 4u;
+
+                /* if the autobaud event was that the autobaud is done.. */
+                if((nStatus & BITM_UART_ASRL_DONE) == BITM_UART_ASRL_DONE)
+                {
+                    /* If the fractional baud generator is enabled, calculate the fractional portional of the baudrate.
+                       It seems that in order to get a correct baudrate reading, we need the fractional divider enabled.
+                    */
+                    if ((hDevice->pUARTRegs->FBR & 0x8000u) == 0x8000u)
+                    {
+                        uint8_t nOSR = 0u;
+                        uint32_t nDivN;
+                        uint32_t nDivNSubtractor = 2048u;
+
+                        /* DIVC is always 1, unless the oversample rate is 32. */
+                        uint16_t nDivC = 1u;
+
+                        /* If the oversample rate is 4.. */
+                        if(nCount < (8u << 3u))
+                        {
+                             nDivN = ((nCount << 9u) / 8u) - nDivNSubtractor;
+                        }
+
+                        /* If the oversample rate is 8.. */
+                        else if(nCount < (8u << 4u))
+                        {
+                             nDivN = ((nCount << 8u) / 8u) - nDivNSubtractor;
+                             nOSR = 1u;
+                        }
+
+                        /* If the oversample rate is 16.. */
+                        else if(nCount < (8u << 5u))
+                        {
+                             nDivN = ((nCount << 7u) / 8u) - nDivNSubtractor;
+                             nOSR = 2u;
+                        }
+
+                        /* If the oversample rate is 32.. */
+                        else
+                        {
+                            nDivC = (uint16_t) (nCount / 32u / 8u);
+                            nDivN = ((nCount << 6u) / (8u * nDivC)) - nDivNSubtractor;
+                            nOSR = 3u;
+                        }
+
+                        /* Write back the register contents for baudrate detection in the hardware. */
+                        adi_uart_ConfigBaudRate(hDevice, nDivC, 1u, (uint16_t)nDivN, nOSR);
+
+                        /* For more precise calculations we would use floating point math here. Integer precision will do for now.
+                           This avoids bringing in extra libraries for floating point math. */
+
+                        /* Baudrate = (UARTCLK / (nDivM + nDivN / 2048) * pow(2, nOSR + 2) * nDivC)
+                        nOSR = (1u << (nOSR + 2u)); Seperate this out of the equation for misra compliance
+                        hDevice->nBaudRate = ((float)nClock / (((float)1 + (float)nDivN / (float)2048) * (float)nOSR * (float)nDivC));
+                        */
+
+                        /* In order to avoid bringing in the extra floating point libraries, we will use the non fractional baudrate for the API. */
+                        hDevice->nBaudRate = ((nClock * 8u) / nCount);
+                    }
+                    else
+                    {
+                      /* No Fractional divider: Baudrate (bits/second) = (UARTCLK (cycles/second) * counted bits (bits)) / nCount (cycles)*/
+                      hDevice->nBaudRate = ((nClock * 8u) / nCount);
+                    }
+
+                    /* If there is a callback, notify the API that autobaud is complete.
+                       If there is not a callback, the baudrate will be set to a non zero value so the user can call "Get_BaudRate"
+                       to know that autobaud has completed.
+                    */
+                    if((hDevice->pfCallback != NULL) && (hDevice->bAutobaudCallbackMode == true))
+                    {
+                        hDevice->pfCallback(hDevice->pCBParam, ADI_UART_EVENT_AUTOBAUD_COMPLETE, (void*)hDevice->nBaudRate);
+                    }
+                }
+                else
+                {
+                    if((nStatus & BITM_UART_ASRL_BRKTO) == BITM_UART_ASRL_BRKTO)
+                    {
+                        /* Autobaud timed out due to break error. */
+                       nEvent |= (uint32_t)ADI_UART_AUTOBAUD_TIMEOUT_LONGBREAK;
+                    }
+                    if((nStatus & BITM_UART_ASRL_NSETO) == BITM_UART_ASRL_NSETO)
+                    {
+                        /* Autobaud timed out due to no valid start edge found. */
+                        nEvent |= (uint32_t)ADI_UART_AUTOBAUD_TIMEOUT_NO_START_EDGE;
+                    }
+                    if((nStatus & BITM_UART_ASRL_NEETO) == BITM_UART_ASRL_NEETO)
+                    {
+                        /* Autobaud timed out due to no valid end edge found. */
+                        nEvent |= (uint32_t)ADI_UART_AUTOBAUD_TIMEOUT_NO_END_EDGE;
+                    }
+                    /* If there is an event callback.. */
+                    if((hDevice->pfCallback != NULL) && (hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING))
+                    {
+                      /* Notify application of errors through callback. */
+                      hDevice->pfCallback(hDevice->pCBParam, ADI_UART_EVENT_AUTOBAUD_ERROR_DETECTED, (void*)nEvent);
+                    }
+                    else
+                    {
+                      /* Notify application of errors through autobaud return value. */
+                      hDevice->nAutobaudError = nEvent;
+                    }
+
+                }
+
+                /* Dummy read to flush the RX register to clear the key character that was sent while configuring autobaud. */
+                hDevice->pUARTRegs->RX;
+            }
+#endif
+            /* Clear auto baud enable and interrupt registers. We disable autobaud here because it is required in order to clear the counter.  */
+             hDevice->pUARTRegs->ACR &=(uint16_t)~( BITM_UART_ACR_ABE   |
+                                                       BITM_UART_ACR_DNIEN |
+                                                       BITM_UART_ACR_TOIEN );
+
+             hDevice->bAutobaudInProgress = false;
+             break;
+         }
+        default:
+          break;
+    }
+    return;
+}
+
+
+/* DMA interrupt handlers */
+void DMA_UART0_TX_Int_Handler(void)
+{
+   ISR_PROLOG();
+   ADI_UART_HANDLE const hDevice = (ADI_UART_HANDLE)uart_device_info[0].hDevice;
+   uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED);
+#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u)
+    ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_DMA_UART_TX);    
+#endif
+   ISR_EPILOG();
+}
+
+void DMA_UART0_RX_Int_Handler(void)
+{
+   ISR_PROLOG();
+   ADI_UART_HANDLE const hDevice = (ADI_UART_HANDLE)uart_device_info[0].hDevice;
+   uart_ManageProcessedBuffer(hDevice,hDevice->pChannelRx,ADI_UART_EVENT_RX_BUFFER_PROCESSED);
+#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u)
+    ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_DMA_UART_RX);    
+#endif
+   ISR_EPILOG();
+}
+
+#if defined(__ADUCM4x50__)
+
+void DMA_UART1_TX_Int_Handler(void)
+{
+   ISR_PROLOG();
+   ADI_UART_HANDLE const hDevice = (ADI_UART_HANDLE)uart_device_info[1].hDevice;
+   uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED);
+#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u)
+    ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_DMA_UART_TX);    
+#endif
+   ISR_EPILOG();
+}
+
+void DMA_UART1_RX_Int_Handler(void)
+{
+   ISR_PROLOG();
+   ADI_UART_HANDLE const hDevice = (ADI_UART_HANDLE)uart_device_info[1].hDevice;
+   uart_ManageProcessedBuffer(hDevice,hDevice->pChannelRx,ADI_UART_EVENT_RX_BUFFER_PROCESSED);
+#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u)
+    ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_DMA_UART_RX);    
+#endif
+   ISR_EPILOG();
+}
+#endif/*__ADUCM4x50__*/
+/*
+ * @brief                  UART interrupt handler for receiving the data in interrupt mode.
+ *
+ * @param [in]  hDevice   Device handle obtained from adi_uart_Open().
+ *
+*/
+static void uart_RxDataHandler(ADI_UART_HANDLE hDevice)
+{
+    volatile uint8_t *pNextData;
+
+    /* If there is an active buffer.. */
+    if((hDevice->pChannelRx->pFillBuffer->pStartAddress != NULL) && (hDevice->pChannelRx->pFillBuffer->bInUse == true))
+    {
+           /* Get the address of the buffer we are filling. */
+           pNextData = (uint8_t *)hDevice->pChannelRx->pFillBuffer->pStartAddress;
+
+           /* Read data from the RX holding register into the buffer at the indexed location. */
+           pNextData[hDevice->pChannelRx->pFillBuffer->nIndex] = (uint8_t) hDevice->pUARTRegs->RX;
+
+           /* Increment the buffer index so we don't overwrite this data in the buffer. */
+           hDevice->pChannelRx->pFillBuffer->nIndex++;
+
+           /* If all of the data has been processed, manage the processed data buffer. Otherwise we will
+              leave everything as is and continue to receive interrupts for the incoming data, until this
+              buffer has been filled.
+           */
+           if(hDevice->pChannelRx->pFillBuffer->nIndex == hDevice->pChannelRx->pFillBuffer->nCount)
+           {
+                  uart_ManageProcessedBuffer(hDevice, hDevice->pChannelRx, ADI_UART_EVENT_RX_BUFFER_PROCESSED);
+           }
+    }
+    /* If we do not have a buffer submitted.. */
+    else
+    {
+          /* Ask the API for a buffer so we can process this data before having an overflow.
+             if there is no callback, the API will not be able to submit a buffer in time.
+          */
+          if (hDevice->pfCallback != NULL)
+          {
+              hDevice->pfCallback(hDevice->pCBParam, (uint32_t)ADI_UART_EVENT_NO_RX_BUFFER_EVENT, NULL);
+          }
+
+          /* This check here is in case in the callback the application submitted a buffer. If they did
+             not then we need to clear the RX register in order to clear this interrupt.
+          */
+          if((hDevice->pChannelRx->pFillBuffer->pStartAddress == NULL) && (hDevice->pChannelRx->pFillBuffer->bInUse == false))
+          {
+              hDevice->pUARTRegs->RX;
+          }
+    }
+
+    return;
+}
+
+/*
+ * @brief      UART interrupt handler transmitting the data in interrupt mode.
+ *
+ * @param [in]  hDevice   Device handle obtained from adi_uart_Open().
+ *
+*/
+static void uart_TxDataHandler(ADI_UART_HANDLE hDevice)
+{
+      volatile uint8_t *pNextData;
+
+    /* If there is an active buffer.. */
+   if((hDevice->pChannelTx->pFillBuffer->pStartAddress != NULL) && (hDevice->pChannelTx->pFillBuffer->bInUse == true))
+    {
+           /* Get the start address of the buffer we are transmitting data from. */
+           pNextData = (uint8_t *)hDevice->pChannelTx->pFillBuffer->pStartAddress;
+
+           /* Write data to the TX holding register. This will be shifted out at the baud rate by the shift register. */
+           hDevice->pUARTRegs->TX = (uint16_t)pNextData[hDevice->pChannelTx->pFillBuffer->nIndex];
+
+           /* Increment the buffer index. */
+          hDevice->pChannelTx->pFillBuffer->nIndex++;
+
+
+           /* If all of the characters have been transmitted, manage the data buffer. Otherwise we will leave everything
+              as is and continue to transmit this data until everything is out of the buffer. */
+           if(hDevice->pChannelTx->pFillBuffer->nIndex >= hDevice->pChannelTx->pFillBuffer->nCount)
+           {
+                  uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED);
+           }
+    }
+    return;
+}
+
+
+/*
+ * @brief       Function for managing the processed buffer. This gets called after the receive buffer has been filled
+ *              and when the transmit buffer has been emptied.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  pChannel   Channel handler for the Tx or Rx.
+ * @param [in]  eEvent     Indicate the event ID to be passed to registered callback function, if one has been registered.
+ *
+*/
+
+static void uart_ManageProcessedBuffer(ADI_UART_HANDLE hDevice,ADI_UART_DATA_CHANNEL *pChannel, ADI_UART_EVENT eEvent)
+{
+
+
+    /* Now that this transaction has completed, this buffer is no longer in use. */
+    pChannel->pFillBuffer->bInUse = false;
+
+    pChannel->pFillBuffer = pChannel->pFillBuffer->pNextBuffer;
+
+    if(eEvent == ADI_UART_EVENT_TX_BUFFER_PROCESSED)
+    {
+        /* Disable Tx buffer interrupts. */
+        hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ETBEI | BITM_UART_IEN_EDMAT);
+    }
+    else
+    {
+        /* Disable Rx buffer interrupts for the DMA. We do not disable receive buffer full interrupts to allow
+           the use of the RX FIFO.
+        */
+        hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_EDMAR);
+
+        if (hDevice->bRxFifoEn != true)
+        {
+            /* Disable Rx buffer interrupts for PIO mode if the FIFO is not enabled.
+            */
+            hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ERBFI);
+        }
+
+    }
+
+    /* If there is a callback registered, notify the API that a buffer has been processed. Clean up the buffer. */
+    if((hDevice->pfCallback != NULL) && (pChannel->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING))
+    {
+        uint32_t nEvent = hDevice->nHwError;
+        hDevice->nHwError = 0u;
+
+        uint32_t *pBuffer = pChannel->pActiveBuffer->pStartAddress;
+
+        /* Reinitialize the start address to NULL so this buffer can be used for a new transaction. */
+        pChannel->pActiveBuffer->pStartAddress = NULL;
+
+        /* Now that the desired data has either been transmitted or received, this buffer is no longer
+           in use. We can update "pActiveBuffer" to point to the next buffer that will become or is already
+           active.
+        */
+         pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer;
+
+        /* Set the data transfer mode to none so that the next transfer can be either in blocking or in nonblocking mode.
+           This will only be done if there are no other active buffers in flight to avoid disrupting an active transfer.
+        */
+        if(pChannel->pActiveBuffer->pStartAddress == NULL)
+        {
+            pChannel->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE;
+        }
+        if(nEvent != 0u)
+        {
+           hDevice->pfCallback(hDevice->pCBParam, ADI_UART_EVENT_HW_ERROR_DETECTED,(void*)nEvent);
+
+        }
+        else
+        {
+            hDevice->pfCallback(hDevice->pCBParam, (uint32_t)eEvent, (void*)pBuffer);
+        }
+
+    }
+    else
+    {
+        /* Post to the blocking function. If we are in blocking mode, this will allow the buffer to be returned to the API.
+           If we are in nonblocking mode, this will allow adi_uart_GetBuffer() to return immediately so the API can have
+           control over the buffer again.
+        */
+		
+		/* Wait until the last bit is gone before POSTing the SEMAPHORE */
+        if(eEvent == ADI_UART_EVENT_TX_BUFFER_PROCESSED)
+          while( ((hDevice->pUARTRegs->LSR & BITM_UART_LSR_TEMT) != BITM_UART_LSR_TEMT) ||(hDevice->pUARTRegs->TFC != 0))
+          {
+            /*waiting until TFC becomes zero */
+          }
+        
+        SEM_POST(pChannel);
+    }
+
+    /* If there is another buffer active. The buffer we want to check is "pFillBuffer" because that is the next one that would
+       be processed. So if it has been submitted, now would be the time to set up the interrupts based on its requirements.
+    */
+    if(pChannel->pFillBuffer->bInUse == true)
+    {
+        pChannel->pfSubmitBuffer(hDevice, pChannel->pFillBuffer);
+    }
+}
+
+
+/*
+ * @brief       Initialize the UART instance to the default values specified in "adi_uart_config.h".
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  nDeviceNum  UART device number
+*/
+
+static void uart_init(ADI_UART_CONST_HANDLE const hDevice, uint32_t const nDeviceNum)
+{
+
+    ADI_UART_CONFIG const* pUARTCfg = &gUARTCfg[nDeviceNum];
+
+    /* Line Control Register. */
+    hDevice->pUARTRegs->LCR = pUARTCfg->LCR;
+
+    /* Div-C in Baudrate divider register. */
+    hDevice->pUARTRegs->DIV = pUARTCfg->DIV;
+
+    /* Div-M and Div-N in Fractional Baudrate register. */
+    hDevice->pUARTRegs->FBR = pUARTCfg->FBR;
+
+    /* Second line control register. */
+    hDevice->pUARTRegs->LCR2 = pUARTCfg->LCR2;
+
+    /* FIFO control register. */
+    hDevice->pUARTRegs->FCR  = pUARTCfg->FCR;
+
+    /* Half Duplex Control Register. */
+    hDevice->pUARTRegs->RSC  = pUARTCfg->RSC;
+
+    /* Interrupt enable register. */
+    hDevice->pUARTRegs->IEN  = pUARTCfg->IEN;
+}
+
+#ifdef ADI_DEBUG
+/*
+ * @brief       Validate the device handle.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS          Specified handle is valid.
+ *    - #ADI_UART_INVALID_HANDLE   Specified handle is invalid.
+ *
+*/
+
+static ADI_UART_RESULT ValidateHandle(ADI_UART_CONST_HANDLE hDevice)
+{
+    uint32_t i;
+
+
+    for(i = 0U; i <  ADI_UART_NUM_DEVICES; i++)
+    {
+
+      if((hDevice == uart_device_info[i].hDevice) && (hDevice != NULL))
+       {
+           return(ADI_UART_SUCCESS);
+       }
+    }
+    return(ADI_UART_INVALID_HANDLE);
+}
+#endif /* ADI_DEBUG */
+/*! \endcond */
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart_def.h
new file mode 100755
index 00000000000..b7e65321475
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart_def.h
@@ -0,0 +1,223 @@
+/*! *****************************************************************************
+ * @file:    adi_uart_def.h
+ * @brief:   UART Device Driver definition for processor
+ -----------------------------------------------------------------------------
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+/*! \cond PRIVATE */
+#ifndef DEF_UART_DEF_H
+#define DEF_UART_DEF_H
+
+/* Macro mapping from ADuCM4x50 to ADuCM302x */
+#if defined(__ADUCM302x__)
+
+#define INTR_UART0_EVT					INTR_UART_EVT
+#define UART0_Int_Handler(void)			UART_Int_Handler(void)		
+#define DMA_UART0_TX_Int_Handler(void)	DMA_UART_TX_Int_Handler(void)
+#define DMA_UART0_RX_Int_Handler(void)	DMA_UART_RX_Int_Handler(void)
+
+#endif /* __ADUCM302x__ */
+
+/*!
+ *****************************************************************************
+ * \struct ADI_UART_BUFF_INFO
+ *  Structure for managing the submitted buffers.
+ *****************************************************************************/
+
+typedef struct UART_BUFF_INFO
+{
+    void                      *pStartAddress;             /*!< Address of buffer passed down to the UART driver.    */
+    uint32_t                   nCount;                    /*!< Size of buffer in bytes.                             */
+    uint32_t                   nIndex;                    /*!< Buffer index.                                        */   
+    bool                       bInUse;                    /*!< Buffer in use flag.                                  */
+    bool                       bDMA;                      /*!< Transaction is using the DMA flag.                   */
+    struct UART_BUFF_INFO     *pNextBuffer;               /*!< Pointer to the next buffer in the list.              */
+
+
+}ADI_UART_BUFF_INFO;
+
+
+/*! Function pointer typedef for the function which  submit the buffer */
+typedef void (*UART_BUFFER_SUBMIT) (ADI_UART_CONST_HANDLE  const hDevice,
+                                    ADI_UART_BUFF_INFO    *const pBuffer
+                                    );
+
+
+/*!
+ *****************************************************************************
+ * \struct ADI_UART_DATA_CHANNEL
+ *  Structure to manage the data transfer for a given channel.
+ *  One instance of this  structure will be created for managing the
+ *  data transfer in each direction.
+ *****************************************************************************/
+ 
+typedef struct _ADI_UART_DATA_CHANNEL
+{ 
+    ADI_UART_BUFF_INFO        PingPong[2];       /*!< Ping Pong Buffers.                                            */
+    ADI_UART_BUFF_INFO       *pFreeBuffer;       /*!< Pointer to free buffer (next buffer to submit).               */  
+    ADI_UART_BUFF_INFO       *pFillBuffer;       /*!< Pointer to the next buffer to be filled. This is needed for 
+                                                      the case where two buffers are "submitted" before a "get" is 
+                                                      called.                                                       */
+    ADI_UART_BUFF_INFO       *pActiveBuffer;     /*!< Pointer to active buffer (next buffer waiting for completion).*/
+    ADI_UART_TRANSFER_MODE    eDataTranferMode;  /*!< Data transfer mode.                                           */ 
+    UART_BUFFER_SUBMIT        pfSubmitBuffer;    /*!< Pointer to a function used for submitting a buffer.           */
+    SEM_VAR_DECLR                               
+
+}ADI_UART_DATA_CHANNEL;
+
+
+/*!
+ *****************************************************************************
+ * \struct  ADI_UART_DEVICE_INFO
+ *  Structure for storing basic device information.
+ *****************************************************************************/
+
+typedef struct _ADI_UART_DEVICE_INFO
+{
+    DMA_CHANn_TypeDef      dmaTxChannelNum;    /*!<  DMA channel ID-Tx.                  */       
+    DMA_CHANn_TypeDef      dmaRxChannelNum;    /*!<  DMA channel ID-Rx.                  */   
+    IRQn_Type              eDMATx;             /*!<  DMA channel IRQ-Tx.                 */       
+    IRQn_Type              eDMARx;             /*!<  DMA channel IRQ-Rx.                 */  
+    IRQn_Type              eIRQn;              /*!<  UART interrupt ID.                  */   
+    ADI_UART_TypeDef      *pUartRegs;          /*!<  Base address of the UART registers. */       
+    ADI_UART_HANDLE        hDevice;            /*!<  Handle for the device instance.     */
+
+}ADI_UART_DEVICE_INFO;
+
+
+/*!
+ *****************************************************************************
+ * \struct  ADI_UART_DEVICE
+ *  Structure for managing the UART device. 
+ *****************************************************************************/
+
+typedef struct _ADI_UART_DEVICE
+{
+    ADI_UART_DIRECTION          eDirection;           /*!< UART operation direction.                                       */
+    ADI_UART_DEVICE_INFO       *pUartInfo;            /*!< Access to device information about the uart instance.           */
+    volatile ADI_UART_TypeDef  *pUARTRegs;            /*!< Access to UART Memory Mapped Registers.                         */     
+    ADI_CALLBACK                pfCallback;           /*!< Callback function.                                              */
+    void                       *pCBParam;             /*!< Parameter for callback function.                                */
+    bool                        bAutobaudInProgress;  /*!< Autobaud in progress flag.                                      */   
+    volatile uint32_t           nHwError;             /*!< Line status error(s).                                           */
+    volatile uint32_t           nAutobaudError;       /*!< Autobaud error(s).                                              */         
+    ADI_UART_DATA_CHANNEL      *pChannelTx;           /*!< Tx channel.                                                     */    
+    ADI_UART_DATA_CHANNEL      *pChannelRx;           /*!< Rx channel.                                                     */
+    volatile uint32_t           nBaudRate;            /*!< Baudrate.                                                       */
+    bool                        bAutobaudCallbackMode;/*!< Autobaud detection is using callback mode flag.                 */
+    bool                        bRxFifoEn;            /*!< Rx FIFO enabled. Rx buffer full interrupts will remain enabled. */
+     
+} ADI_UART_DEVICE;
+
+
+/*!
+ *****************************************************************************
+ * \struct  ADI_UART_CONFIG
+ *  Structure for initializing the static config.
+ *****************************************************************************/
+
+typedef struct _ADI_UART_CONFIG
+{
+    uint16_t                    LCR;                 /*!< UART_COMLCR Register. */    
+
+    uint16_t                    DIV;                 /*!< UART_COMDIV Register. */ 
+
+    uint16_t                    FBR;                 /*!< UART_COMFBR Register. */ 
+
+    uint16_t                    LCR2;                /*!< UART_COMLCR2 Register.*/ 
+
+    uint16_t                    FCR;                 /*!< UART_COMFCR Register. */ 
+
+    uint16_t                    RSC;                 /*!< UART_COMRSC Register. */              
+
+    uint16_t                    IEN;                 /*!< UART_COMIEN Register .*/ 
+
+} ADI_UART_CONFIG;
+
+
+/******************************************************************************
+ * UART Device internal API function prototypes
+ *****************************************************************************/
+
+/*
+ * UART device initialization helper function.
+*/
+static void uart_init(ADI_UART_CONST_HANDLE const hDevice, uint32_t const nDeviceNum);
+
+
+/*
+ * Data transfer helper functions.
+*/
+static void uart_submittxbuffer(ADI_UART_CONST_HANDLE const hDevice, ADI_UART_BUFF_INFO *const pBuffer);
+
+static void uart_submitrxbuffer(ADI_UART_CONST_HANDLE const hDevice, ADI_UART_BUFF_INFO *const pBuffer);
+
+
+/*
+ * Data management helper functions.
+*/
+static ADI_UART_RESULT uart_getbuffer(ADI_UART_HANDLE hDevice, ADI_UART_DATA_CHANNEL *pChannel, void **ppBuffer, uint32_t *pHwError);
+
+static ADI_UART_RESULT uart_PendForBuffer(ADI_UART_HANDLE const hDevice , ADI_UART_DATA_CHANNEL *pChannel, uint32_t *pHwError);
+
+static void uart_ManageProcessedBuffer(ADI_UART_HANDLE hDevice, ADI_UART_DATA_CHANNEL *pChannel, ADI_UART_EVENT eEvent);
+
+static void uart_TxDataHandler(ADI_UART_HANDLE hDevice);
+
+static void uart_RxDataHandler(ADI_UART_HANDLE hDevice);
+
+
+/* 
+ * Interrupt Handler.
+*/
+static void Common_Uart_Interrupt_Handler(ADI_UART_HANDLE hDevice);
+
+
+/* 
+ * Handle Validation function
+*/
+#ifdef ADI_DEBUG
+static ADI_UART_RESULT  ValidateHandle(ADI_UART_CONST_HANDLE hDevice);
+#endif /* ADI_DEBUG */
+
+#endif  /* end of ifndef DEF_UART_DEF_H */
+/*! \endcond */
+
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/wdt/adi_wdt.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/wdt/adi_wdt.c
new file mode 100755
index 00000000000..b2f34894a25
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/wdt/adi_wdt.c
@@ -0,0 +1,225 @@
+/*! *****************************************************************************
+ * @file    adi_wdt.c
+ * @brief   WDT device driver implementation
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+*
+* Pm011 (rule 6.3): the basic types of char, int, short, long, float, and double should not be used
+*   Necessary for stdbool.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+*
+* Pm140 (Rule 11.4): a cast should not be performed between a pointer type and an integral type
+*   This violation appears when deferencing the pointer to the register typedef. No way around this.
+*/
+#pragma diag_suppress=Pm011,Pm073,Pm140,Pm143
+#endif /* __ICCARM__ */
+
+
+/** @addtogroup WDT_Driver WDT Driver
+ *  @{
+ * @brief Watchdog Timer (WDT) Driver
+ * @details The watchdog timer driver allows the user to enable the timer with
+ * the static configuration parameters, reset the timer, and read the timer
+ * count.  No interface is provided for setting the timer parameters are
+ * runtime since the WDT may only be configured once for the program lifetime.
+ * The timer is disabled by default by the ADuCM4x50 boot kernel.
+ * @note The application must include drivers/wdt/adi_wdt.h to use this driver
+ */
+
+#include <stdlib.h>
+#include <adi_processor.h>
+#include <rtos_map/adi_rtos_map.h>
+#include <adi_wdt_config.h>
+#include <drivers/wdt/adi_wdt.h>
+
+/*! \cond PRIVATE */
+
+/*! Bus synchronization bits that must go low before writing to the CTL or RESET registers */
+#define ADI_WDT_SYNC_BITS ((0x1u << BITP_WDT_STAT_COUNTING) | (0x1u << BITP_WDT_STAT_LOADING) | (0x1u << BITP_WDT_STAT_CLRIRQ))
+
+/*! Value that is written to the reset register to kick the dog */
+#define ADI_WDT_CLR_VALUE (0xCCCCu)
+
+/*! Store the callback locally if we are using interrupt mode */
+#if (ADI_WDT_CONTROL_TIMEOUT_MODE == 1u)
+static ADI_CALLBACK gAppCallback;
+#endif
+
+/*! \endcond */
+
+/*********************************************************************************
+                                    API IMPLEMENTATIONS 
+*********************************************************************************/
+
+
+/*!
+ * @brief      WDT Enable
+ *
+ * @details    Enables/disables the WDT with the paramters supplied in adi_wdt_config.h
+ *
+ * @param [in] bEnable    : True to turn WDT on, false to turn it off
+ *
+ * @param [in] pfCallback : If interrupt mode is enabled, specify application callback function,
+ *                          otherwise simply pass NULL for the argument.
+ *
+ * @return     ADI_WDT_RESULT
+ *                - #ADI_WDT_FAILURE_LOCKED           WDT has already been initialized
+ *                - #ADI_WDT_SUCCESS                  Function call completed successfully
+ */
+ADI_WDT_RESULT adi_wdt_Enable(bool const bEnable, ADI_CALLBACK const pfCallback) {
+    /* IF(Device is enabled, application can't modify it) */
+    if ((pADI_WDT0->STAT & ((uint16_t) BITM_WDT_STAT_LOCKED)) != ((uint16_t) 0x0u)) {
+        return ADI_WDT_FAILURE_LOCKED;
+    } /* ENDIF */
+
+    /* Setup interrupts if we are in interrupt mode */
+#if (ADI_WDT_CONTROL_TIMEOUT_MODE == 1u)
+    gAppCallback = pfCallback;
+    /* IF(We are enabling the WDT) */
+    if (bEnable == true) {
+        NVIC_EnableIRQ (WDT_EXP_IRQn);
+    /* ELSE (We are disabling the WDT, this might not be necessary, depends on startup config) */
+    } else {
+        NVIC_DisableIRQ(WDT_EXP_IRQn);
+    } /* ENDIF */
+#endif
+
+    /* WHILE(Bus sync is underway) */
+    while((pADI_WDT0->STAT & ADI_WDT_SYNC_BITS) != 0u) {
+        ;
+    } /* ENDWHILE */
+
+
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+
+    pADI_WDT0->LOAD = ADI_WDT_LOAD_VALUE;
+
+    /* IF(Turning the WDT on) */
+    if (bEnable == true) {
+        pADI_WDT0->CTL  = (ADI_WDT_CONTROL_TIMER_MODE      << BITP_WDT_CTL_MODE) |
+                          (0x1u                            << BITP_WDT_CTL_EN  ) |
+                          (ADI_WDT_CONTROL_CLOCK_PRESCALER << BITP_WDT_CTL_PRE ) |
+                          (ADI_WDT_CONTROL_TIMEOUT_MODE    << BITP_WDT_CTL_IRQ ) |
+                          (ADI_WDT_CONTROL_POWER_MODE      <<               0u );
+    /* ELSE(Turning the WDT off) */
+    } else {
+        pADI_WDT0->CTL  = (ADI_WDT_CONTROL_TIMER_MODE      << BITP_WDT_CTL_MODE) |
+                          (0x0u                            << BITP_WDT_CTL_EN  ) |
+                          (ADI_WDT_CONTROL_CLOCK_PRESCALER << BITP_WDT_CTL_PRE ) |
+                          (ADI_WDT_CONTROL_TIMEOUT_MODE    << BITP_WDT_CTL_IRQ ) |
+                          (ADI_WDT_CONTROL_POWER_MODE      <<               0u );
+    } /* ENDIF */
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_WDT_SUCCESS;
+}
+
+/*!
+ * @brief      WDT Reset
+ *
+ * @details    Resets the WDT
+ *
+ * @return     None
+ */
+void adi_wdt_Kick(void) {
+    /* WHILE(Bus sync is underway) */
+    while((pADI_WDT0->STAT & ADI_WDT_SYNC_BITS) != 0u) {
+        ;
+    } /* ENDWHILE */
+
+   /* Kick the dog! */
+    pADI_WDT0->RESTART = ADI_WDT_CLR_VALUE;
+}
+
+/*!
+ * @brief       WDT Read Count
+ *
+ * @details     Read the current WDT count
+ *
+ * @param [out] pCurCount : Pointer to memory to read the count into
+ *
+ * @return      None
+ */
+void adi_wdt_GetCount(uint16_t * const pCurCount) {
+    /* Read the count */
+    *pCurCount = pADI_WDT0->CCNT;
+}
+
+/*! \cond PRIVATE */
+
+/*!
+ * @brief     WDT0 Interrupt Handler
+ *
+ * @details   Kicks the dog and calls the user supplied callback function
+ *
+ * @return    None
+ *
+ * @note      Do not need to explicitly clear the interrupt status,
+ *            kicking the dog performs this action.
+ */
+#if (ADI_WDT_CONTROL_TIMEOUT_MODE == 1u)
+extern void WDog_Tmr_Int_Handler(void); 
+void WDog_Tmr_Int_Handler(void) {
+    ISR_PROLOG()
+    /* Kick the dog  */
+    adi_wdt_Kick();
+    /* IF(Application supplied a callback) */
+    if(gAppCallback != NULL) {
+        /* Call the callback */
+        gAppCallback(NULL, 0x0u, NULL);
+    } /* ENDIF */
+    ISR_EPILOG()
+}
+#endif /* (ADI_WDT_CONTROL_TIMEOUT_MODE == 1u) */
+
+/*! \endcond */
+
+/*! @} */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/xint/adi_xint.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/xint/adi_xint.c
new file mode 100755
index 00000000000..76674dead4c
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/xint/adi_xint.c
@@ -0,0 +1,413 @@
+/******************************************************************************
+   @file:    adi_xint.c
+   @brief:   External Interrupt device driver implementation.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+/*****************************************************************************/
+
+#include <stddef.h>
+#include <string.h>
+#include <assert.h>
+#include <drivers/xint/adi_xint.h>
+#include <rtos_map/adi_rtos_map.h>
+#include "adi_xint_def.h"
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   The rule makes an exception for memory-mapped register accesses.
+* Pm140 (rule 10.3): illegal explicit conversion from underlying MISRA type unsigned int to enum
+*   The typecast is used for efficiency of the code.
+* Pm140 (rule 17.4): array indexing shall only be applied to objects defined as an array
+*   Array indexing is required on the pointer. The memory for gpCallbackTable is passed from application
+*/
+#pragma diag_suppress=Pm073,Pm143,Pm140,Pm136,Pm152
+#endif /* __ICCARM__ */
+
+static inline void XIntCommonInterruptHandler  (const ADI_XINT_EVENT eEvent);
+void Ext_Int0_Handler(void);
+void Ext_Int1_Handler(void);
+void Ext_Int2_Handler(void);
+void Ext_Int3_Handler(void);
+
+
+
+/*==========  D A T A  ==========*/
+
+static ADI_XINT_CALLBACK_INFO *gpCallbackTable;
+
+/*! \endcond */
+
+/*! \addtogroup XINT_Driver External Interrupt Driver
+ *  @{
+ *  @brief External Interrupt (XINT) Driver
+ *  @note The application must include drivers/xint/adi_xint.h to use this driver
+ */
+
+/*!
+    @brief      Initializes the External Interrupt Driver.
+
+    @details    This function does the external interrupt driver initialization. This function should be called
+                before calling any of the XINT driver APIs.
+
+    @param[in] pMemory      Pointer to the memory to be used by the driver.
+                            Size of the memory should be at equal to #ADI_XINT_MEMORY_SIZE bytes.
+    @param[in] MemorySize   Size of the memory passed in pMemory parameter.
+
+    @return     Status
+                    - ADI_XINT_SUCCESS                  If successfully initialized XINT driver.
+                    - ADI_XINT_NULL_PARAMETER       [D] If the given pointer to the driver memory is pointing to NULL.
+                    - ADI_XINT_INVALID_MEMORY_SIZE  [D] If the given memory size is not sufficient to operate the driver.
+                   
+    @sa         adi_xint_UnInit
+*/
+ADI_XINT_RESULT adi_xint_Init(void*                const pMemory,
+                              uint32_t             const MemorySize
+)
+{
+
+#ifdef ADI_DEBUG
+        /* Verify the given memory pointer */
+        if(NULL == pMemory)
+        {
+            return ADI_XINT_NULL_PARAMETER;
+        }
+        /* Check if the memory size is sufficient to operate the driver */
+        if(MemorySize < ADI_XINT_MEMORY_SIZE)
+        {
+            return ADI_XINT_INVALID_MEMORY_SIZE;
+        }
+        assert(MemorySize == (sizeof(ADI_XINT_CALLBACK_INFO) * ADI_XINT_EVENT_MAX));
+#endif
+
+    /* Only initialize on 1st init call, i.e., preserve callbacks on multiple inits */
+    if (gpCallbackTable == NULL)
+    {
+        /* Clear the memory passed by the application */
+        memset(pMemory, 0, MemorySize);
+
+        gpCallbackTable = (ADI_XINT_CALLBACK_INFO *)pMemory;
+    }
+    return (ADI_XINT_SUCCESS);
+}
+
+
+/*!
+    @brief      Un-initialize the external interrupt driver.
+
+    @details    Terminates the XINT functions, leaving everything unchanged.
+
+    @return     Status
+                    - #ADI_XINT_SUCCESS             If successfully uninitialized XINT driver.
+                    - #ADI_XINT_NOT_INITIALIZED [D] If XINT driver not yet initialized.
+
+    @sa         adi_xint_Init
+*/
+ADI_XINT_RESULT adi_xint_UnInit(void)
+{
+
+#ifdef ADI_DEBUG
+    /* IF (not initialized) */
+    if (NULL == gpCallbackTable)
+    {
+        /* return error if not initialized */
+        return (ADI_XINT_NOT_INITIALIZED);
+    }
+#endif
+
+    /* Clear the callback pointer */
+    gpCallbackTable = NULL;
+
+    return (ADI_XINT_SUCCESS);
+}
+
+
+
+/*!
+    @brief      Enable an External Interrupt
+
+    @details    Enables and sets the triggering mode for the given external interrupt.
+                Applications may register a callback using the #adi_xint_RegisterCallback
+                API to get a notification when the interrupt occurs.
+
+                To get the external interrupt working application has to enable the input
+                (using the GPIO driver API \a adi_gpio_InputEnable) for the corresponding GPIO
+                pin. Please refer the GPIO chapter pin-muxing section of the Hardware Reference
+                Manual to see the GPIO pin that is mapped to the required external interrupt.
+
+    @param[in]  eEvent      Event which needs to be enabled.
+    @param[in]  eMode       Interrupt trigger mode for the external interrupt.
+
+    @return     Status
+                    - #ADI_XINT_SUCCESS             If successfully enabled the external interrupt.
+                    - #ADI_XINT_NOT_INITIALIZED [D] If external interrupt driver not yet initialized.
+
+    @sa         adi_xint_DisableIRQ
+    @sa         adi_xint_RegisterCallback
+*/
+ADI_XINT_RESULT adi_xint_EnableIRQ(const ADI_XINT_EVENT eEvent, const ADI_XINT_IRQ_MODE eMode)
+{
+    uint32_t            Mask;       /* mask to manipulate the register */
+    uint32_t            Pattern;    /* bit pattern that will be written into the register */
+    uint32_t            CfgReg;     /* interrupt config register value */
+    IRQn_Type           XintIrq;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == gpCallbackTable)
+    {
+        return (ADI_XINT_NOT_INITIALIZED);
+    }
+#endif
+
+    /* create the mask we'll use to clear the relevant bits in the config register */
+    Mask = (BITM_XINT_CFG0_IRQ0MDE | BITM_XINT_CFG0_IRQ0EN) << (ADI_XINT_CFG_BITS * (uint32_t)eEvent);
+
+    /* The Pattern has to be created differently for UART RX wakeup and other events as the
+       mode and enable bits are flipped in case of UART RX */
+    
+    /* Based on the event figure out the interrupt it is mapped to */
+    if(eEvent == ADI_XINT_EVENT_UART_RX)
+    {        
+          /* create the bit pattern we're going to write into the configuration register */
+         Pattern = (BITM_XINT_CFG0_UART_RX_EN | ((uint32_t)eMode << BITP_XINT_CFG0_UART_RX_MDE));
+         
+         XintIrq = XINT_EVT3_IRQn;
+    }
+    else
+    {
+        /* create the bit pattern we're going to write into the configuration register */
+        Pattern = (BITM_XINT_CFG0_IRQ0EN | eMode) << (ADI_XINT_CFG_BITS * (uint32_t)eEvent);
+        
+        XintIrq = (IRQn_Type)((uint32_t)XINT_EVT0_IRQn + (uint32_t)eEvent);
+    }
+
+    
+    ADI_ENTER_CRITICAL_REGION();
+
+    /* read/modify/write the appropriate bits in the register */
+    CfgReg = pADI_XINT0->CFG0;
+    CfgReg &= ~Mask;
+    CfgReg |= Pattern;
+    pADI_XINT0->CFG0 = CfgReg;
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* enable the interrupt */
+    NVIC_EnableIRQ(XintIrq);
+
+    return (ADI_XINT_SUCCESS);
+}
+
+
+/*!
+    @brief      Disable an External Interrupt
+
+    @details    Disables an external interrupt
+
+    @param[in]  eEvent  External Interrupt event that should be disabled.
+
+    @return     Status
+                    - #ADI_XINT_SUCCESS             If successfully disabled the external interrupt.
+                    - #ADI_XINT_NOT_INITIALIZED [D] If external interrupt driver is not yet initialized.
+
+    @sa         adi_xint_EnableIRQ
+    @sa         adi_xint_RegisterCallback
+*/
+ADI_XINT_RESULT adi_xint_DisableIRQ(const ADI_XINT_EVENT eEvent)
+{
+    uint32_t            Mask;       /* mask to manipulate the register */
+    uint32_t            CfgReg;     /* interrupt config register value */
+    IRQn_Type           XintIrq;    /* External interrupt IRQ the event is mapped to */
+
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == gpCallbackTable)
+    {
+        return (ADI_XINT_NOT_INITIALIZED);
+    }
+#endif
+
+    /* Based on the event figure out the interrupt it is mapped to */
+    if(eEvent == ADI_XINT_EVENT_UART_RX)
+    {
+        XintIrq = XINT_EVT3_IRQn;
+    }
+    else
+    {
+        XintIrq = (IRQn_Type)((uint32_t)XINT_EVT0_IRQn + (uint32_t)eEvent);
+    }
+
+    /* disable the interrupt */
+    NVIC_DisableIRQ(XintIrq);
+
+    /* create the mask we'll use to clear the relevant bits in the config register */
+    Mask = (BITM_XINT_CFG0_IRQ0MDE | BITM_XINT_CFG0_IRQ0EN) << (ADI_XINT_CFG_BITS * (uint32_t)eEvent);
+
+    ADI_ENTER_CRITICAL_REGION();
+    /* read/modify/write the appropriate bits in the register */
+    CfgReg = pADI_XINT0->CFG0;
+    CfgReg &= ~Mask;
+    pADI_XINT0->CFG0 = CfgReg;
+    ADI_EXIT_CRITICAL_REGION();
+
+    return (ADI_XINT_SUCCESS);
+}
+
+
+/*!
+    @brief      Register or unregister an application callback function for external pin interrupts.
+
+    @details    Applications may register a callback function that will be called when an
+                external interrupt occurs. In addition to registering the interrupt,
+                the application should call the #adi_xint_EnableIRQ API to enable the
+                external pin interrupt.
+
+                The driver dispatches calls to registered callback functions when the
+                properly configured pin(s) latches an external interrupt input on the XINT
+                pin(s).  The callback is dispatched with the following parameters, respectively:
+
+                - application-provided callback parameter (\a pCBParam),
+                - the interrupt ID (#ADI_XINT_EVENT) that initiated the interrupt,
+                - NULL.
+
+    @param[in]  eEvent          The interrupt for which the callback is being registered.
+    @param[in]  pfCallback      Pointer to the callback function. This can be passed as NULL to
+                                unregister the callback.
+    @param[in]  pCBParam        Callback parameter which will be passed back to the application
+                                when the callback is called..
+
+    @return     Status
+                    - #ADI_XINT_SUCCESS                 If successfully registered the callback.
+                    - #ADI_XINT_NOT_INITIALIZED     [D] If external interrupt driver is not yet initialized.
+
+    @sa         adi_xint_EnableIRQ
+    @sa         adi_xint_DisableIRQ
+*/
+ADI_XINT_RESULT  adi_xint_RegisterCallback (const ADI_XINT_EVENT eEvent, ADI_CALLBACK const pfCallback, void *const pCBParam )
+{
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == gpCallbackTable)
+    {
+        return (ADI_XINT_NOT_INITIALIZED);
+    }
+#endif
+
+    ADI_ENTER_CRITICAL_REGION();
+    gpCallbackTable[eEvent].pfCallback  = pfCallback;
+    gpCallbackTable[eEvent].pCBParam    = pCBParam;
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* return the status */
+    return (ADI_XINT_SUCCESS);
+}
+
+/*@}*/
+
+/*! \cond PRIVATE */
+/* All of the following is excluded from the doxygen output... */
+
+/* Common external interrupt handler */
+static inline void XIntCommonInterruptHandler(const ADI_XINT_EVENT eEvent)
+{
+    /* Clear the IRQ */
+    pADI_XINT0->CLR = (1u << (uint32_t)eEvent);
+
+    /* params list is: application-registered cbParam, Event ID, and NULL */
+    if(gpCallbackTable[eEvent].pfCallback != NULL)
+    {
+        gpCallbackTable[eEvent].pfCallback (gpCallbackTable[eEvent].pCBParam, (uint32_t) eEvent, NULL);
+    }
+}
+
+/* strongly-bound interrupt handlers to override the default weak bindings */
+void Ext_Int0_Handler(void)
+{
+    ISR_PROLOG()
+    XIntCommonInterruptHandler(ADI_XINT_EVENT_INT0);
+    ISR_EPILOG()
+}
+
+void Ext_Int1_Handler(void)
+{
+    ISR_PROLOG()
+    XIntCommonInterruptHandler(ADI_XINT_EVENT_INT1);
+    ISR_EPILOG()
+}
+
+void Ext_Int2_Handler(void)
+{
+    ISR_PROLOG()
+    XIntCommonInterruptHandler(ADI_XINT_EVENT_INT2);
+    ISR_EPILOG()
+
+}
+
+void Ext_Int3_Handler(void)
+{
+    ISR_PROLOG()
+    if((pADI_XINT0->EXT_STAT & BITM_XINT_EXT_STAT_STAT_UART_RXWKUP)==BITM_XINT_EXT_STAT_STAT_UART_RXWKUP)
+    {
+       XIntCommonInterruptHandler(ADI_XINT_EVENT_UART_RX);
+    }
+    else
+    {
+       XIntCommonInterruptHandler(ADI_XINT_EVENT_INT3);
+    }
+    ISR_EPILOG()
+}
+
+/*! \endcond */
+
+/*
+** EOF
+*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/xint/adi_xint_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/xint/adi_xint_def.h
new file mode 100755
index 00000000000..205602215cd
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/xint/adi_xint_def.h
@@ -0,0 +1,61 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_xint_def.h
+ * @brief:   External Interrupt Driver definition
+ *****************************************************************************
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#ifndef ADI_XINT_DEF_H
+#define ADI_XINT_DEF_H
+/*! \cond PRIVATE */
+
+/* General macros */
+#define ADI_XINT_CFG_BITS       (4u)       /*!< number of bits for each external interrupt configuration */
+
+/*! Structure to hold callback function and parameter */
+typedef struct _ADI_XINT_CALLBACK_INFO
+{
+    ADI_CALLBACK         pfCallback;        /*!< Callback function pointer */
+    void                 *pCBParam;         /*!< Callback parameter */
+} ADI_XINT_CALLBACK_INFO;
+
+
+/*! \endcond */
+#endif /* ADI_XINT_DEF_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/PeripheralNames.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/PeripheralNames.h
new file mode 100755
index 00000000000..c1cfd6c14ae
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/PeripheralNames.h
@@ -0,0 +1,136 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    OSC32KCLK = 0,
+} RTCName;
+
+typedef enum {
+    UART_0 = 0,
+    UART_1 = 1,
+    UART_2 = 2,
+    UART_3 = 3,
+    UART_4 = 4,
+} UARTName;
+
+#define STDIO_UART_TX     USBTX
+#define STDIO_UART_RX     USBRX
+#define STDIO_UART        UART_0
+
+typedef enum {
+    I2C_0 = 0,
+    I2C_1 = 1,
+    I2C_2 = 2,
+} I2CName;
+
+#define TPM_SHIFT   8
+typedef enum {
+    PWM_1  = (0 << TPM_SHIFT) | (0),  // FTM0 CH0
+    PWM_2  = (0 << TPM_SHIFT) | (1),  // FTM0 CH1
+    PWM_3  = (0 << TPM_SHIFT) | (2),  // FTM0 CH2
+    PWM_4  = (0 << TPM_SHIFT) | (3),  // FTM0 CH3
+    PWM_5  = (0 << TPM_SHIFT) | (4),  // FTM0 CH4
+    PWM_6  = (0 << TPM_SHIFT) | (5),  // FTM0 CH5
+    PWM_7  = (0 << TPM_SHIFT) | (6),  // FTM0 CH6
+    PWM_8  = (0 << TPM_SHIFT) | (7),  // FTM0 CH7
+    PWM_9  = (1 << TPM_SHIFT) | (0),  // FTM1 CH0
+    PWM_10 = (1 << TPM_SHIFT) | (1),  // FTM1 CH1
+    PWM_11 = (1 << TPM_SHIFT) | (2),  // FTM1 CH2
+    PWM_12 = (1 << TPM_SHIFT) | (3),  // FTM1 CH3
+    PWM_13 = (1 << TPM_SHIFT) | (4),  // FTM1 CH4
+    PWM_14 = (1 << TPM_SHIFT) | (5),  // FTM1 CH5
+    PWM_15 = (1 << TPM_SHIFT) | (6),  // FTM1 CH6
+    PWM_16 = (1 << TPM_SHIFT) | (7),  // FTM1 CH7
+    PWM_17 = (2 << TPM_SHIFT) | (0),  // FTM2 CH0
+    PWM_18 = (2 << TPM_SHIFT) | (1),  // FTM2 CH1
+    PWM_19 = (2 << TPM_SHIFT) | (2),  // FTM2 CH2
+    PWM_20 = (2 << TPM_SHIFT) | (3),  // FTM2 CH3
+    PWM_21 = (2 << TPM_SHIFT) | (4),  // FTM2 CH4
+    PWM_22 = (2 << TPM_SHIFT) | (5),  // FTM2 CH5
+    PWM_23 = (2 << TPM_SHIFT) | (6),  // FTM2 CH6
+    PWM_24 = (2 << TPM_SHIFT) | (7),  // FTM2 CH7
+    // could be 4 or could be 3... not sure what register
+    //  this is for... too much abstraction
+    PWM_25 = (3 << TPM_SHIFT) | (0),  // FTM3 CH0
+    PWM_26 = (3 << TPM_SHIFT) | (1),  // FTM3 CH1
+    PWM_27 = (3 << TPM_SHIFT) | (2),  // FTM3 CH2
+    PWM_28 = (3 << TPM_SHIFT) | (3),  // FTM3 CH3
+    PWM_29 = (3 << TPM_SHIFT) | (4),  // FTM3 CH4
+    PWM_30 = (3 << TPM_SHIFT) | (5),  // FTM3 CH5
+    PWM_31 = (3 << TPM_SHIFT) | (6),  // FTM3 CH6
+    PWM_32 = (3 << TPM_SHIFT) | (7),  // FTM3 CH7
+} PWMName;
+
+typedef enum {
+    ADC0_VIN0 = 0,
+    ADC0_VIN1 = 1,
+    ADC0_VIN2 = 2,
+    ADC0_VIN3 = 3,
+    ADC0_VIN4 = 4,
+    ADC0_VIN5 = 5,
+    ADC0_VIN6 = 6,
+    ADC0_VIN7 = 7
+} ADCName;
+
+typedef enum {
+    DAC_0 = 0
+} DACName;
+
+
+typedef enum {
+    SPI_0 = 0,
+    SPI_1 = 1,
+    SPI_2 = 2,
+} SPIName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/PinNames.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/PinNames.h
new file mode 100755
index 00000000000..3192608f780
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/PinNames.h
@@ -0,0 +1,221 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+/*
+    The ADuCM4050 is made in two package variants.
+
+    64 lead LFCSP & 72 ball WLCSP
+
+    There are some differences for Port 2 between the two variants
+    WLCSP also has Port 3.
+
+    The #define ADUCM4050_LFCSP is used to determine which variant the code
+    is built for.
+
+    For LFCSP leave the #define in, to build for ADUCM4050_WLCSP remove.
+*/
+#define ADUCM4050_LFCSP
+
+#include "cmsis.h"
+
+#include "adi_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+//update
+
+#define GPIO_PORT_SHIFT 12
+
+
+typedef enum {
+    P0_00  = (0 << GPIO_PORT_SHIFT | 0 ),
+    P0_01  = (0 << GPIO_PORT_SHIFT | 1 ),
+    P0_02  = (0 << GPIO_PORT_SHIFT | 2 ),
+    P0_03  = (0 << GPIO_PORT_SHIFT | 3 ),
+    P0_04  = (0 << GPIO_PORT_SHIFT | 4 ),
+    P0_05  = (0 << GPIO_PORT_SHIFT | 5 ),
+    P0_06  = (0 << GPIO_PORT_SHIFT | 6 ),
+    P0_07  = (0 << GPIO_PORT_SHIFT | 7 ),
+    P0_08  = (0 << GPIO_PORT_SHIFT | 8 ),
+    P0_09  = (0 << GPIO_PORT_SHIFT | 9 ),
+    P0_10 = (0 << GPIO_PORT_SHIFT | 10),
+    P0_11 = (0 << GPIO_PORT_SHIFT | 11),
+    P0_12 = (0 << GPIO_PORT_SHIFT | 12),
+    P0_13 = (0 << GPIO_PORT_SHIFT | 13),
+    P0_14 = (0 << GPIO_PORT_SHIFT | 14),
+    P0_15 = (0 << GPIO_PORT_SHIFT | 15),
+    P1_00  = (1 << GPIO_PORT_SHIFT | 0 ),
+    P1_01  = (1 << GPIO_PORT_SHIFT | 1 ),
+    P1_02  = (1 << GPIO_PORT_SHIFT | 2 ),
+    P1_03  = (1 << GPIO_PORT_SHIFT | 3 ),
+    P1_04  = (1 << GPIO_PORT_SHIFT | 4 ),
+    P1_05  = (1 << GPIO_PORT_SHIFT | 5 ),
+    P1_06  = (1 << GPIO_PORT_SHIFT | 6 ),
+    P1_07  = (1 << GPIO_PORT_SHIFT | 7 ),
+    P1_08  = (1 << GPIO_PORT_SHIFT | 8 ),
+    P1_09  = (1 << GPIO_PORT_SHIFT | 9 ),
+    P1_10 = (1 << GPIO_PORT_SHIFT | 10),
+    P1_11 = (1 << GPIO_PORT_SHIFT | 11),
+    P1_12 = (1 << GPIO_PORT_SHIFT | 12),
+    P1_13 = (1 << GPIO_PORT_SHIFT | 13),
+    P1_14 = (1 << GPIO_PORT_SHIFT | 14),
+    P1_15 = (1 << GPIO_PORT_SHIFT | 15),
+    P2_00  = (2 << GPIO_PORT_SHIFT | 0 ),
+    P2_01  = (2 << GPIO_PORT_SHIFT | 1 ),
+    P2_02  = (2 << GPIO_PORT_SHIFT | 2 ),
+    P2_03  = (2 << GPIO_PORT_SHIFT | 3 ),
+    P2_04  = (2 << GPIO_PORT_SHIFT | 4 ),
+    P2_05  = (2 << GPIO_PORT_SHIFT | 5 ),
+    P2_06  = (2 << GPIO_PORT_SHIFT | 6 ),
+    P2_07  = (2 << GPIO_PORT_SHIFT | 7 ),
+    P2_08  = (2 << GPIO_PORT_SHIFT | 8 ),
+    P2_09  = (2 << GPIO_PORT_SHIFT | 9 ),
+    P2_10 = (2 << GPIO_PORT_SHIFT | 10),
+    P2_11 = (2 << GPIO_PORT_SHIFT | 11),
+
+    // USB Pins
+    USBTX = P0_10,
+    USBRX = P0_11,
+    USBTX1 = P1_15,
+    USBRX1 = P2_00,
+
+    // mbed original LED naming
+    LED1 = P2_02,
+    LED2 = P2_10,
+    LED3 = LED2,
+    LED4 = LED1,
+
+    //Push buttons
+    PB0 = P1_00,        // BTN1
+    PB1 = P0_09,        // BTN2
+    BOOT = P1_01,
+    WAKE0 = P0_15,      // JP15 to select
+    WAKE1 = P1_00,      // JP8 (BTN1 jumper) to select
+    WAKE2 = P0_13,      // JP4 to select
+    WAKE3 = P2_01,      // JP15 to select
+
+    // SPI Pins
+    SPI0_SCLK = P0_00,
+    SPI0_MOSI = P0_01,
+    SPI0_MISO = P0_02,
+    SPI0_CS0 = P0_03,
+    SPI0_CS1 = P1_10,
+    SPI0_CS2 = P2_08,
+    SPI0_CS3 = P2_09,
+
+    SPI1_SCLK = P1_06,
+    SPI1_MOSI = P1_07,
+    SPI1_MISO = P1_08,
+    SPI1_CS0 = P1_09,
+    SPI1_CS1 = P2_11,
+    SPI1_CS2 = P2_02,
+    SPI1_CS3 = P1_10,
+
+    SPI2_SCLK = P1_02,
+    SPI2_MOSI = P1_03,
+    SPI2_MISO = P1_04,
+    SPI2_CS0 = P1_05,
+    SPI2_CS1 = P0_09,
+    SPI2_CS2 = P2_10,
+    SPI2_CS3 = P2_07,
+
+    // ADC Pins
+    ADC_VIN0 = P2_03,
+    ADC_VIN1 = P2_04,
+    ADC_VIN2 = P2_05,
+    ADC_VIN3 = P2_06,
+    ADC_VIN4 = P2_07,
+    ADC_VIN5 = P2_08,
+    ADC_VIN6 = P2_09,
+    ADC_VIN7 = P2_10,
+
+    // Arduino Headers
+    D0 = P0_10,        // UART0_TXD
+    D1 = P0_11,        // UART0_RXD
+    D2 = P0_15,        // INT_WAKE0
+    D3 = P0_13,        // EXT_INT_WAKE2
+    D4 = P0_09,        // EXT_SPI2_CS1
+    D5 = P2_01,        // INT_WAKE3 or EXT_RTC1_SS1 via JP8
+    D6 = P1_11,        // GPIO_27
+    D7 = P0_12,        // GPIO_08 or GPIO_12 via JP7
+
+    D8 = P1_12,         // GPIO_28
+    D9 = P1_14,         // GPIO_30
+    D10 = SPI0_CS2,     // P2_08
+    D11 = SPI0_MOSI,    // P0_01
+    D12 = SPI0_MISO,    // P0_02
+    D13 = SPI0_SCLK,    // P0_00
+    I2C_SCL = P0_04,    // I2C_SCL
+    I2C_SDA = P0_05,    // I2C_SDA
+
+    A0 = P2_03,         // ADC0
+    A1 = P2_04,         // EXT_ADC1
+    A2 = P2_05,         // EXT_ADC2
+    A3 = P2_06,         // ADC3
+    A4 = P2_07,         // SPI2_CS3
+    A5 = P2_10,         // EXT_GPIO42
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+
+typedef enum {
+    PullNone = 0,
+    PullDown = 1,
+    PullUp   = 2,
+    PullDefault = PullNone
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c
new file mode 100755
index 00000000000..3c06ae2b245
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c
@@ -0,0 +1,274 @@
+/*!
+ *****************************************************************************
+ * @file:    startup_ADuCM4050.c
+ * @brief:   Interrupt table and default handlers for ADuCM4x50
+ * @version: $Revision: $
+ * @date:    $Date: $
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2010-2017 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+#ifdef __ARMCC_VERSION
+#include <stdint.h>
+#include <rt_misc.h>
+#endif
+#include <cmsis.h>
+#include <startup_ADuCM4050.h>
+#include <mbed_rtx.h>
+
+/*----------------------------------------------------------------------------
+  Checksum options
+ *----------------------------------------------------------------------------*/
+#if defined (__ARMCC_VERSION)
+__attribute__((section(".ARM.__at_0x000001A0")))
+#elif defined(__ICCARM__)
+__root
+#endif
+const uint32_t SECTION_PLACE(blank_checksum[],".checksum") =
+{
+    BLANKX60,BLANKX600
+};
+
+
+/*----------------------------------------------------------------------------
+  External function Declaration
+ *----------------------------------------------------------------------------*/
+extern void SramInit(void);
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+WEAK_FUNCTION( NMI_Handler                )
+WEAK_FUNCTION( HardFault_Handler          )
+WEAK_FUNCTION( MemManage_Handler          )
+WEAK_FUNCTION( BusFault_Handler           )
+WEAK_FUNCTION( UsageFault_Handler         )
+WEAK_FUNCTION( SVC_Handler                )
+WEAK_FUNCTION( DebugMon_Handler           )
+WEAK_FUNCTION( PendSV_Handler             )
+WEAK_FUNCTION( SysTick_Handler            )
+WEAK_FUNCTION( RTC1_Int_Handler           )
+WEAK_FUNCTION( Ext_Int0_Handler           )
+WEAK_FUNCTION( Ext_Int1_Handler           )
+WEAK_FUNCTION( Ext_Int2_Handler           )
+WEAK_FUNCTION( Ext_Int3_Handler           )
+WEAK_FUNCTION( WDog_Tmr_Int_Handler       )
+WEAK_FUNCTION( Vreg_over_Int_Handler      )
+WEAK_FUNCTION( Battery_Voltage_Int_Handler)
+WEAK_FUNCTION( RTC0_Int_Handler           )
+WEAK_FUNCTION( GPIO_A_Int_Handler         )
+WEAK_FUNCTION( GPIO_B_Int_Handler         )
+WEAK_FUNCTION( GP_Tmr0_Int_Handler        )
+WEAK_FUNCTION( GP_Tmr1_Int_Handler        )
+WEAK_FUNCTION( Flash0_Int_Handler         )
+WEAK_FUNCTION( UART0_Int_Handler          )
+WEAK_FUNCTION( SPI0_Int_Handler           )
+WEAK_FUNCTION( SPI2_Int_Handler           )
+WEAK_FUNCTION( I2C0_Slave_Int_Handler     )
+WEAK_FUNCTION( I2C0_Master_Int_Handler    )
+WEAK_FUNCTION( DMA_Err_Int_Handler        )
+WEAK_FUNCTION( DMA_SPIH_TX_Int_Handler    )
+WEAK_FUNCTION( DMA_SPIH_RX_Int_Handler    )
+WEAK_FUNCTION( DMA_SPORT0A_Int_Handler    )
+WEAK_FUNCTION( DMA_SPORT0B_Int_Handler    )
+WEAK_FUNCTION( DMA_SPI0_TX_Int_Handler    )
+WEAK_FUNCTION( DMA_SPI0_RX_Int_Handler    )
+WEAK_FUNCTION( DMA_SPI1_TX_Int_Handler    )
+WEAK_FUNCTION( DMA_SPI1_RX_Int_Handler    )
+WEAK_FUNCTION( DMA_UART0_TX_Int_Handler   )
+WEAK_FUNCTION( DMA_UART0_RX_Int_Handler   )
+WEAK_FUNCTION( DMA_I2C0_STX_Int_Handler   )
+WEAK_FUNCTION( DMA_I2C0_SRX_Int_Handler   )
+WEAK_FUNCTION( DMA_I2C0_MX_Int_Handler    )
+WEAK_FUNCTION( DMA_AES0_IN_Int_Handler    )
+WEAK_FUNCTION( DMA_AES0_OUT_Int_Handler   )
+WEAK_FUNCTION( DMA_FLASH0_Int_Handler     )
+WEAK_FUNCTION( SPORT0A_Int_Handler        )
+WEAK_FUNCTION( SPORT0B_Int_Handler        )
+WEAK_FUNCTION( Crypto_Int_Handler         )
+WEAK_FUNCTION( DMA_ADC0_Int_Handler       )
+WEAK_FUNCTION( GP_Tmr2_Int_Handler        )
+WEAK_FUNCTION( Crystal_osc_Int_Handler    )
+WEAK_FUNCTION( SPI1_Int_Handler           )
+WEAK_FUNCTION( PLL_Int_Handler            )
+WEAK_FUNCTION( RNG_Int_Handler            )
+WEAK_FUNCTION( Beep_Int_Handler           )
+WEAK_FUNCTION( ADC0_Int_Handler           )
+WEAK_FUNCTION( DMA_SIP0_Int_Handler       )
+WEAK_FUNCTION( DMA_SIP1_Int_Handler       )
+WEAK_FUNCTION( DMA_SIP2_Int_Handler       )
+WEAK_FUNCTION( DMA_SIP3_Int_Handler       )
+WEAK_FUNCTION( DMA_SIP4_Int_Handler       )
+WEAK_FUNCTION( DMA_SIP5_Int_Handler       )
+WEAK_FUNCTION( DMA_SIP6_Int_Handler       )
+WEAK_FUNCTION( DMA_SIP7_Int_Handler       )
+WEAK_FUNCTION( UART1_Int_Handler          )
+WEAK_FUNCTION( DMA_UART1_TX_Int_Handler   )
+WEAK_FUNCTION( DMA_UART1_RX_Int_Handler   )
+WEAK_FUNCTION( RGB_Tmr_Int_Handler        )
+WEAK_FUNCTION( Root_Clk_Err_Handler       )
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+const pFunc SECTION_PLACE(IVT_NAME[104],VECTOR_SECTION) = {
+    (pFunc) INITIAL_SP,    /* Initial Stack Pointer */
+    ADUCM4050_VECTORS
+};
+
+/*----------------------------------------------------------------------------
+* Initialize .bss and .data for GNU
+*----------------------------------------------------------------------------*/
+#if defined( __GNUC__) && !defined (__ARMCC_VERSION)
+void zero_bss(void)
+{
+    uint32_t *pSrc, *pDest;
+    uint32_t *pTable __attribute__((unused));
+#ifdef __STARTUP_COPY_MULTIPLE
+    /*  Multiple sections scheme.
+     *
+     *  Between symbol address __copy_table_start__ and __copy_table_end__,
+     *  there are array of triplets, each of which specify:
+     *    offset 0: LMA of start of a section to copy from
+     *    offset 4: VMA of start of a section to copy to
+     *    offset 8: size of the section to copy. Must be multiply of 4
+     *
+     *  All addresses must be aligned to 4 bytes boundary.
+     */
+    pTable = &__copy_table_start__;
+
+    for (; pTable < &__copy_table_end__; pTable = pTable + 3) {
+        pSrc  = (uint32_t*)*(pTable + 0);
+        pDest = (uint32_t*)*(pTable + 1);
+        for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) {
+            *pDest++ = *pSrc++;
+        }
+    }
+#else
+    /*  Single section scheme.
+     *
+     *  The ranges of copy from/to are specified by following symbols
+     *    __etext: LMA of start of the section to copy from. Usually end of text
+     *    __data_start__: VMA of start of the section to copy to
+     *    __data_end__: VMA of end of the section to copy to
+     *
+     *  All addresses must be aligned to 4 bytes boundary.
+     */
+    pSrc  = &__etext;
+    pDest = &__data_start__;
+
+    for ( ; pDest < &__data_end__ ; ) {
+        *pDest++ = *pSrc++;
+    }
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+    /*  This part of work usually is done in C library startup code. Otherwise,
+     *  define this macro to enable it in this startup.
+     *
+     *  There are two schemes too. One can clear multiple BSS sections. Another
+     *  can only clear one section. The former is more size expensive than the
+     *  latter.
+     *
+     *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+     *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+     */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+    /*  Multiple sections scheme.
+     *
+     *  Between symbol address __copy_table_start__ and __copy_table_end__,
+     *  there are array of tuples specifying:
+     *    offset 0: Start of a BSS section
+     *    offset 4: Size of this BSS section. Must be multiply of 4
+     */
+    pTable = &__zero_table_start__;
+
+    for (; pTable < &__zero_table_end__; pTable = pTable + 2) {
+        pDest = (uint32_t*)*(pTable + 0);
+        for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) {
+            *pDest++ = 0;
+        }
+    }
+#elif defined (__STARTUP_CLEAR_BSS)
+    /*  Single BSS section scheme.
+     *
+     *  The BSS section is specified by following symbols
+     *    __bss_start__: start of the BSS section.
+     *    __bss_end__: end of the BSS section.
+     *
+     *  Both addresses must be aligned to 4 bytes boundary.
+     */
+    pDest = &__bss_start__;
+
+    for ( ; pDest < &__bss_end__ ; ) {
+        *pDest++ = 0ul;
+    }
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+}
+#endif
+
+/*----------------------------------------------------------------------------
+* Function    : Reset_Handler (-15)
+* Description : Reset event handler
+*----------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+    /* Initialize SRAM configuration. */
+    SramInit();
+
+#if defined(__GNUC__) && !defined (__ARMCC_VERSION)
+    zero_bss();
+#endif
+
+    /* Setup system. */
+    SystemInit();
+
+    /* Call remaining startup code and then main. */
+    RESET_EXCPT_HNDLR();
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+#if defined(__ARMCC_VERSION) || defined (__GNUC__)
+void Default_Handler(void)
+{
+    while(1);
+}
+#endif
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.h
new file mode 100755
index 00000000000..d1485407633
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.h
@@ -0,0 +1,234 @@
+/*!
+*****************************************************************************
+ * @file:    startup_ADuCM4050.h
+ * @brief:   CMSIS Cortex-M4 Core Peripheral Access Layer Header File for
+ *           ADI ADuCxxx Device Series
+ * @version: $Revision: $
+ * @date:    $Date: $
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2010-2017 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/*
+WEAK_FUNC(func)
+   If this is available for a compiler, apply whatever attributes are needed
+   to a function definition ("func") to flag that the function is a "weak" one.
+VECTOR_SECTION
+   A particular setup may have a requirement that the vector table be placed
+   in a particular section. This specifies the name of that section
+RESET_EXCPT_HNDLR
+   A particular setup may have a requirement for a different reset handler.
+   This specifies the name of that handler.
+*/
+
+#ifndef __STARTUP_H__
+#define __STARTUP_H__
+
+#include <adi_types.h>
+#define VECTOR_SECTION                 ".vectors"
+#ifdef __ARMCC_VERSION
+void Default_Handler(void);
+#define SECTION_NAME(sectionname)      __attribute__((section(sectionname)))
+#define SECTION_PLACE(def,sectionname) def __attribute__((section(sectionname)))
+#define IVT_NAME                       __Vectors
+#define RESET_EXCPT_HNDLR              __main
+#define COMPILER_NAME                  "ARMCC"
+#define WEAK_FUNCTION(x)               void x (void) __attribute__((weak, alias("Default_Handler")));
+#elif defined(__ICCARM__)
+/*
+* IAR MISRA C 2004 error suppressions:
+*
+* Pm093 (rule 18.4): use of union - overlapping storage shall not be used.
+*    Required for interrupt vector table entries.
+*
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   The rule makes an exception for memory-mapped register accesses.
+*/
+#pragma diag_suppress=Pm093,Pm140
+#define SECTION_PLACE(def,sectionname) def @ sectionname
+#define SECTION_NAME(sectionname)     def @ sectionname
+#define IVT_NAME                       __vector_table
+#define WEAK_FUNC(func)                __weak func
+#define RESET_EXCPT_HNDLR              __iar_program_start
+#define COMPILER_NAME                  "ICCARM"
+#define WEAK_FUNCTION(x)  WEAK_FUNC  ( void x (void)) { while(1){} }
+#elif defined(__GNUC__)
+extern unsigned __etext;
+extern unsigned __data_start__;
+extern unsigned __data_end__;
+extern unsigned __copy_table_start__;
+extern unsigned __copy_table_end__;
+extern unsigned __zero_table_start__;
+extern unsigned __zero_table_end__;
+extern unsigned __bss_start__;
+extern unsigned __bss_end__;
+extern unsigned __StackTop;
+void Default_Handler(void);
+/*----------------------------------------------------------------------------
+  External References
+ *----------------------------------------------------------------------------*/
+#ifndef __START
+extern void  _start(void) __attribute__((noreturn));    /* PreeMain (C library entry point) */
+#define RESET_EXCPT_HNDLR              _start
+#else
+extern int  __START(void) __attribute__((noreturn));    /* main entry point */
+#define RESET_EXCPT_HNDLR              __START
+#endif
+#ifndef __STACK_SIZE
+#define	__STACK_SIZE  0x00000400
+#endif
+#if !defined(__HEAP_SIZE) || (__HEAP_SIZE <= 0)
+#define	__HEAP_SIZE   0x00000C00
+#endif
+#define SECTION_NAME(sectionname)      __attribute__ ((section(sectionname)))
+#define SECTION_PLACE(def,sectionname) def __attribute__ ((section(sectionname)))
+#define IVT_NAME                       __Vectors
+#define COMPILER_NAME                  "GNUC"
+#define WEAK_FUNCTION(x)               void x (void) __attribute__ ((weak, alias("Default_Handler")));
+#define __STARTUP_CLEAR_BSS_MULTIPLE
+#endif // __GNUC__
+#define LASTCRCPAGE                    0
+#define BLANKX4   0xFFFFFFFF
+#define BLANKX20  BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4
+#define BLANKX100 BLANKX20,BLANKX20,BLANKX20,BLANKX20,BLANKX20,BLANKX20,BLANKX20,BLANKX20
+#define BLANKX600 BLANKX100,BLANKX100,BLANKX100,BLANKX100,BLANKX100,BLANKX100
+#define BLANKX60  BLANKX20,BLANKX20,BLANKX20
+void RESET_EXCPT_HNDLR(void);
+void Reset_Handler(void);
+/* IVT typedefs. */
+typedef void( *pFunc )( void );
+
+#define ADUCM4050_VECTORS \
+    /* Configure Initial Stack Pointer, using linker-generated symbols */\
+   Reset_Handler,                            /* -15 */                   \
+   NMI_Handler,                              /* -14 */                   \
+   HardFault_Handler,                        /* -13 */                   \
+   MemManage_Handler,                        /* -12 */                   \
+   BusFault_Handler,                         /* -11 */                   \
+   UsageFault_Handler,                       /* -10 */                   \
+   0,                                        /* -9  */                   \
+   0,                                        /* -8  */                   \
+   0,                                        /* -7  */                   \
+   0,                                        /* -6  */                   \
+   SVC_Handler,                              /* -5  */                   \
+   DebugMon_Handler,                         /* -4  */                   \
+   0,                                        /* -3  */                   \
+   PendSV_Handler,                           /* -2  */                   \
+   SysTick_Handler,                          /* -1  */                   \
+   /* External interrupts */                                             \
+   RTC1_Int_Handler,                         /* 0  */                    \
+   Ext_Int0_Handler,                         /* 1  */                    \
+   Ext_Int1_Handler,                         /* 2  */                    \
+   Ext_Int2_Handler,                         /* 3  */                    \
+   Ext_Int3_Handler,                         /* 4  */                    \
+   WDog_Tmr_Int_Handler,                     /* 5  */                    \
+   Vreg_over_Int_Handler,                    /* 6  */                    \
+   Battery_Voltage_Int_Handler,              /* 7  */                    \
+   RTC0_Int_Handler,                         /* 8  */                    \
+   GPIO_A_Int_Handler,                       /* 9  */                    \
+   GPIO_B_Int_Handler,                       /* 10 */                    \
+   GP_Tmr0_Int_Handler,                      /* 11 */                    \
+   GP_Tmr1_Int_Handler,                      /* 12 */                    \
+   Flash0_Int_Handler,                       /* 13 */                    \
+   UART0_Int_Handler,                        /* 14 */                    \
+   SPI0_Int_Handler,                         /* 15 */                    \
+   SPI2_Int_Handler,                         /* 16 */                    \
+   I2C0_Slave_Int_Handler,                   /* 17 */                    \
+   I2C0_Master_Int_Handler,                  /* 18 */                    \
+   DMA_Err_Int_Handler,                      /* 19 */                    \
+   DMA_SPIH_TX_Int_Handler,                  /* 20 */                    \
+   DMA_SPIH_RX_Int_Handler,                  /* 21 */                    \
+   DMA_SPORT0A_Int_Handler,                  /* 22 */                    \
+   DMA_SPORT0B_Int_Handler,                  /* 23 */                    \
+   DMA_SPI0_TX_Int_Handler,                  /* 24 */                    \
+   DMA_SPI0_RX_Int_Handler,                  /* 25 */                    \
+   DMA_SPI1_TX_Int_Handler,                  /* 26 */                    \
+   DMA_SPI1_RX_Int_Handler,                  /* 27 */                    \
+   DMA_UART0_TX_Int_Handler,                 /* 28 */                    \
+   DMA_UART0_RX_Int_Handler,                 /* 29 */                    \
+   DMA_I2C0_STX_Int_Handler,                 /* 30 */                    \
+   DMA_I2C0_SRX_Int_Handler,                 /* 31 */                    \
+   DMA_I2C0_MX_Int_Handler,                  /* 32 */                    \
+   DMA_AES0_IN_Int_Handler,                  /* 33 */                    \
+   DMA_AES0_OUT_Int_Handler,                 /* 34 */                    \
+   DMA_FLASH0_Int_Handler,                   /* 35 */                    \
+   SPORT0A_Int_Handler,                      /* 36 */                    \
+   SPORT0B_Int_Handler,                      /* 37 */                    \
+   Crypto_Int_Handler,                       /* 38 */                    \
+   DMA_ADC0_Int_Handler,                     /* 39 */                    \
+   GP_Tmr2_Int_Handler,                      /* 40 */                    \
+   Crystal_osc_Int_Handler,                  /* 41 */                    \
+   SPI1_Int_Handler,                         /* 42 */                    \
+   PLL_Int_Handler,                          /* 43 */                    \
+   RNG_Int_Handler,                          /* 44 */                    \
+   Beep_Int_Handler,                         /* 45 */                    \
+   ADC0_Int_Handler,                         /* 46 */                    \
+   0,                                        /* 47 */                    \
+   0,                                        /* 48 */                    \
+   0,                                        /* 49 */                    \
+   0,                                        /* 50 */                    \
+   0,                                        /* 51 */                    \
+   0,                                        /* 52 */                    \
+   0,                                        /* 53 */                    \
+   0,                                        /* 54 */                    \
+   0,                                        /* 55 */                    \
+   DMA_SIP0_Int_Handler,                     /* 56 */                    \
+   DMA_SIP1_Int_Handler,                     /* 57 */                    \
+   DMA_SIP2_Int_Handler,                     /* 58 */                    \
+   DMA_SIP3_Int_Handler,                     /* 59 */                    \
+   DMA_SIP4_Int_Handler,                     /* 60 */                    \
+   DMA_SIP5_Int_Handler,                     /* 61 */                    \
+   DMA_SIP6_Int_Handler,                     /* 62 */                    \
+   DMA_SIP7_Int_Handler,                     /* 63 */                    \
+   0,                                        /* 64 */                    \
+   0,                                        /* 65 */                    \
+   UART1_Int_Handler,                        /* 66 */                    \
+   DMA_UART1_TX_Int_Handler,                 /* 67 */                    \
+   DMA_UART1_RX_Int_Handler,                 /* 68 */                    \
+   RGB_Tmr_Int_Handler,                      /* 69 */                    \
+   0,                                        /* 70 */                    \
+   Root_Clk_Err_Handler,                     /* 71 */                    \
+   0,0,0,0,0,0,0,0,                          /* 72 - 79 */               \
+   (pFunc)BLANKX4, (pFunc)BLANKX4,           /* security_options */      \
+   (pFunc)BLANKX4, (pFunc)BLANKX4,                                       \
+   (pFunc)0xA79C3203u, (pFunc)LASTCRCPAGE,                               \
+   (pFunc)BLANKX4, (pFunc)BLANKX4            /* 80 - 87 */
+
+#endif /* __STARTUP_H__ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/system_ADuCM4050.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/system_ADuCM4050.c
new file mode 100755
index 00000000000..df75af10d2f
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/system_ADuCM4050.c
@@ -0,0 +1,322 @@
+/**************************************************************************//**
+ * @file     system_ADuCM4050.c
+ * @brief    CMSIS Cortex-M4 Device Peripheral Access Layer Source File for
+ *           Device ADuCM4x50
+ * @version  V3.10
+ * @date     23. November 2012
+ *
+ ******************************************************************************/
+/* Copyright (c) 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+
+   Portions Copyright (c) 2016 - 2017 Analog Devices, Inc.
+   ---------------------------------------------------------------------------*/
+
+#include <cmsis.h>
+#include <adi_pwr.h>
+#include <startup_ADuCM4050.h>
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#ifdef ADI_DEBUG
+/* only needed in debug mode */
+uint32_t lfClock = 0u;    /* "lf_clk" coming out of LF mux             */
+#endif
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+/* Note that these variables will be re-initialized to the value set here by the
+   LIBC startup code, so if other clock values are required, make sure set them
+   here.
+*/
+uint32_t hfClock = __HFOSC;         /* "root_clk" output of HF mux              */
+uint32_t gpioClock = 0u;            /* external GPIO clock                      */
+uint32_t SystemCoreClock = __HFOSC; /*!< System Clock Frequency (Core Clock)    */
+
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+
+/*!
+ * Update the clock.
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the variable SystemCoreClock and must be called whenever
+ *         the core clock is changed during program execution.
+ */
+void SystemCoreClockUpdate(void)
+{
+    uint32_t val, nDivisor, nMulfactor, div2, mul2;
+
+#ifdef ADI_DEBUG
+    /* "lfclock" is only used during debug checks... */
+    /* LF clock is always 32k, whether osc or xtal */
+    lfClock = __LFCLK;  /* for beep, wdt and lcd */
+    if (lfClock == 0u) {
+        while (1) {}
+    }
+#endif
+    /* Update Core Clock sources */
+    /* update the HF clock */
+    switch (pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_CLKMUX ) {
+
+        case HFMUX_INTERNAL_OSC_VAL:
+            hfClock = __HFOSC;
+            break;
+
+        case HFMUX_EXTERNAL_XTAL_VAL:
+            hfClock = __HFXTAL;
+            break;
+
+        case HFMUX_SYSTEM_SPLL_VAL:
+            /* Calculate System PLL output frequency */
+            if ((pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_PLL_IPSEL) != 0u) {
+                /* PLL input from HFXTAL */
+                val = __HFXTAL;
+            } else {
+                /* PLL input from HFOSC */
+                val = __HFOSC;
+            }
+
+            /* PLL NSEL multiplier */
+            nMulfactor = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLNSEL) >> BITP_CLKG_CLK_CTL3_SPLLNSEL;
+            /* PLL MSEL divider */
+            nDivisor = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLMSEL) >> BITP_CLKG_CLK_CTL3_SPLLMSEL;
+
+            /* PLL NSEL multiplier */
+            mul2 = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLMUL2) >> BITP_CLKG_CLK_CTL3_SPLLMUL2;
+            /* PLL MSEL divider */
+            div2 = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLDIV2) >> BITP_CLKG_CLK_CTL3_SPLLDIV2;
+
+            val = ((val << mul2) * nMulfactor / nDivisor) >> div2;
+
+            hfClock = val;
+            break;
+
+        case HFMUX_GPIO_VAL:
+            hfClock = gpioClock;
+            break;
+
+        default:
+            return;
+    } /* end switch */
+
+    SystemCoreClock = hfClock;
+}
+
+/*!
+ * Configure the SRAM banks
+ *
+ * @return none
+ *
+ * @brief  Setup the SRAM banks.
+ *         Initialize the SRAM configuration and retention.
+ */
+void SramInit(void)
+{
+    /* On reset, there is no SRAM retention.  Any retention has to be explicitly
+     * set here. */
+    adi_system_EnableRetention(ADI_SRAM_BANK_1 |
+                               ADI_SRAM_BANK_3 |
+                               ADI_SRAM_BANK_4 |
+                               ADI_SRAM_BANK_5 |
+                               ADI_SRAM_BANK_6 |
+                               ADI_SRAM_BANK_7, true);
+    /* To disable the instruction SRAM and entire 64K of SRAM is used as DSRAM */
+    adi_system_EnableISRAM(false);
+    /* To disable the instruction cache  */
+    adi_system_EnableCache(false);
+}
+
+/*!
+ * Initialize the system
+ *
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the relocate vector table.
+ */
+void SystemInit (void)
+{
+    uint32_t IntStatus;
+
+    IntStatus = __get_PRIMASK();
+    __disable_irq();
+
+    /* Set boot ROM IVT. */
+    SCB->VTOR = (uint32_t)NVIC_FLASH_VECTOR_ADDRESS;
+
+    /* Set all three (USGFAULTENA, BUSFAULTENA, and MEMFAULTENA) fault enable bits
+     * in the System Control Block, System Handler Control and State Register
+     * otherwise these faults are handled as hard faults.
+     */
+    SCB->SHCSR = SCB_SHCSR_USGFAULTENA_Msk |
+                 SCB_SHCSR_BUSFAULTENA_Msk |
+                 SCB_SHCSR_MEMFAULTENA_Msk ;
+
+#if (__FPU_PRESENT == 1u) && (__FPU_USED == 1u)
+    /* the FPU is disabled by default so enable FPU (NEON and VFP)
+     * set the System Control Block, Coprocessor Access Control Register bits:
+     * CP10 = grant CP10 coprocessor privileges and user mode access (full access)
+     * CP11 = grant CP11 coprocessor privileged and user mode access (full access)
+     * (CP10 and CP11 MUST be the same or "BEHAVIOR IS UNPREDICTABLE")
+     */
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 for Full Access */
+#endif
+
+    /* Flush instruction and data pipelines to insure assertion of new settings. */
+    __ISB();
+    __DSB();
+
+    adi_pwr_Init();
+    adi_pwr_SetClockDivider(ADI_CLOCK_HCLK,1);
+    adi_pwr_SetClockDivider(ADI_CLOCK_PCLK,1);
+
+    /* Set up the LF clock MUX. Currently LFXTAL is unstable so use the
+       internal LF Oscillator instead. LFXTAL is still required to be enabled
+       as it is required by RTC0. This LFXTAL issue is going to be fixed
+       in the next revision of the silicon. */
+    adi_pwr_EnableClockSource(ADI_CLOCK_SOURCE_LFXTAL,true);
+    adi_pwr_SetLFClockMux(ADI_CLOCK_MUX_LFCLK_LFOSC);
+    adi_pwr_EnableClockSource(ADI_CLOCK_SOURCE_LFOSC,true);
+
+    __set_PRIMASK(IntStatus);
+}
+
+/*!
+ * @brief  Enables or disables the cache.
+ * @param  bEnable Specify whether to enable/disable cache.
+ *                 - true : Enable cache.
+ *                 - false: Disable cache.
+ * @return none
+ */
+void adi_system_EnableCache(bool bEnable)
+{
+    pADI_FLCC0_CACHE->KEY = CACHE_CONTROLLER_KEY;
+    if( bEnable == true ) {
+        pADI_FLCC0_CACHE->SETUP |= BITM_FLCC_CACHE_SETUP_ICEN;
+    } else {
+        pADI_FLCC0_CACHE->SETUP &= ~BITM_FLCC_CACHE_SETUP_ICEN;
+    }
+}
+
+/*!
+ * @brief  This enables or disables instruction SRAM
+ *
+ * @param bEnable Enable/disable the instruction SRAM.
+ *               -  true : Enable instruction SRAM.
+ *               -  false : Disable instruction SRAM.
+ * @return none
+ * @note The appropriate linker file needs to support the configuration.
+ */
+void adi_system_EnableISRAM(bool bEnable)
+{
+
+    if( bEnable == true ) {
+        pADI_PMG0_TST->SRAM_CTL |= BITM_PMG_TST_SRAM_CTL_INSTREN;
+    } else {
+        pADI_PMG0_TST->SRAM_CTL &= ~BITM_PMG_TST_SRAM_CTL_INSTREN;
+    }
+}
+
+/*!
+ * @brief  This enables/disable SRAM retention during the hibernation.
+ * @param eBank:   Specify which SRAM banks.  Multiple banks can be set
+ /                 using a logical OR of the banks.
+ * @param bEnable Enable/disable the  retention for specified SRAM bank.
+ *               -  true : Enable retention during hibernation.
+ *               -  false: Disable retention during hibernation.
+ * @return   ADI_SYS_SUCCESS Configured successfully.
+ * @return   ADI_SYS_FAILURE Invalid bank, or banks, specified.  Any incorrect
+ *                           or invalid bank options will result in failure and
+ *                           no changes will have been applied.
+ * @note The appropriate linker file needs to support the configuration.
+ *       BANK  0 is always retained.
+ *       BANKS 1 can be retained individually.
+ *       BANK  2 is never retained.
+ *       BANKS 3 and 4 can only be mutually retained.
+ *       BANKS 5 can be retained individually.
+ *       BANKS 6 and 7 can only be mutually retained.
+ */
+ADI_SYS_RESULT adi_system_EnableRetention(ADI_SRAM_BANK eBank, bool bEnable)
+{
+    uint32_t retainBits = 0u;
+
+#ifdef ADI_DEBUG
+    if((0u != (eBank & ADI_SRAM_BANK_0)) ||
+            (0u != (eBank & ADI_SRAM_BANK_2))) {
+        /* Banks 0 and 2 are not selectable */
+        return ADI_SYS_FAILURE;
+    }
+
+    /* Are banks 3 or 4 selected? */
+    if(0u != (eBank & (ADI_SRAM_BANK_3 | ADI_SRAM_BANK_4))) {
+        /* If so, the only valid option is for both to be retained. */
+        if((eBank & (ADI_SRAM_BANK_3 | ADI_SRAM_BANK_4)) != (ADI_SRAM_BANK_3 | ADI_SRAM_BANK_4)) {
+            return ADI_SYS_FAILURE;
+        }
+    }
+
+    /* Are banks 6 or 7 selected? */
+    if(0u != (eBank & (ADI_SRAM_BANK_6 | ADI_SRAM_BANK_7))) {
+        /* If so, the only valid option is for both to be retained */
+        if((eBank & (ADI_SRAM_BANK_6 | ADI_SRAM_BANK_7)) != (ADI_SRAM_BANK_6 | ADI_SRAM_BANK_7)) {
+            return ADI_SYS_FAILURE;
+        }
+    }
+#endif
+    if((eBank & ADI_SRAM_BANK_1) != 0u) {
+        retainBits |= BITM_PMG_SRAMRET_RET1;
+    }
+    if((eBank & (ADI_SRAM_BANK_3 | ADI_SRAM_BANK_4)) != 0u) {
+        retainBits |= BITM_PMG_SRAMRET_RET2;
+    }
+    if((eBank & ADI_SRAM_BANK_5) != 0u) {
+        retainBits |= BITM_PMG_SRAMRET_RET3;
+    }
+    if((eBank & (ADI_SRAM_BANK_6 | ADI_SRAM_BANK_7)) != 0u) {
+        retainBits |= BITM_PMG_SRAMRET_RET4;
+    }
+
+    /* Unlock the SRAMRET register using the PWRKEY.
+     * If there is any chance that this sequence can be interrupted then it
+     * should be protected by disabling interrupts.   A write to any other
+     * register on the APB bus before writing to PMG_SRAMRET will return the
+     * protection to the lock state. */
+    pADI_PMG0->PWRKEY = PWRKEY_VALUE_KEY;
+    if(bEnable) {
+        pADI_PMG0->SRAMRET |= retainBits;
+    } else {
+        pADI_PMG0->SRAMRET &= ~(retainBits);
+    }
+
+    return ADI_SYS_SUCCESS;
+}
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_ARM_STD/ADuCM4050.sct b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_ARM_STD/ADuCM4050.sct
new file mode 100755
index 00000000000..0f7791ae5ec
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_ARM_STD/ADuCM4050.sct
@@ -0,0 +1,52 @@
+;******************************************************************************
+;  File: ADuCM4050.sct
+;  Scatter loading file for Analog Devices ADuCM4050 processor
+;
+;  Copyright (c) 2011 - 2014 ARM LIMITED
+;  Copyright (c) 2016 - 2017 Analog Devices, Inc.
+;
+;  All rights reserved.
+;  Redistribution and use in source and binary forms, with or without
+;  modification, are permitted provided that the following conditions are met:
+;  - Redistributions of source code must retain the above copyright
+;    notice, this list of conditions and the following disclaimer.
+;  - Redistributions in binary form must reproduce the above copyright
+;    notice, this list of conditions and the following disclaimer in the
+;    documentation and/or other materials provided with the distribution.
+;  - Neither the name of ARM nor the names of its contributors may be used
+;    to endorse or promote products derived from this software without
+;    specific prior written permission.
+;
+;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+;  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;  POSSIBILITY OF SUCH DAMAGE.
+;******************************************************************************
+LR_IROM1 0x00000000 0x0007F000 {
+    FLASH0   0x00000000 0x00000800 {
+        *(.vectors, +First)
+        *(.checksum)
+    }
+
+    ER_IROM1 AlignExpr(ImageLimit(FLASH0), 16) 0x0007E800 {
+        ; load address = execution address
+        *(InRoot$$Sections)
+        *(+RO)
+    }
+
+    RW_IRAM1    0x20040000 EMPTY 0 { }
+
+    ADUCM_IRAM2 0x20000200 0x7E00  { *(+RW) }
+
+    ADUCM_IRAM3 0x20048000 0x10000 { *(+ZI) }
+
+    ADUCM_HEAP  AlignExpr(ImageLimit(RW_IRAM1), 16) EMPTY
+        (ImageBase(ADUCM_IRAM3) - 0x2000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) { } ; heap
+}
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_GCC_ARM/ADuCM4050.ld b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_GCC_ARM/ADuCM4050.ld
new file mode 100755
index 00000000000..2ead54a157c
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_GCC_ARM/ADuCM4050.ld
@@ -0,0 +1,214 @@
+/*
+ * Portions Copyright (c) 2016 Analog Devices, Inc.
+ *
+ * Based on Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld file in
+ * ARM.CMSIS.4.5.0.pack.
+ */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  /* The first 0x800 bytes of flash */
+  FLASH0 (rx) : ORIGIN = 0x00000000, LENGTH = 0x800
+  /* The remaining bytes of flash minus 4KB Protected Key Storage */
+  FLASH (rx) : ORIGIN = 0x00000800, LENGTH = 512k - 4k - 0x800
+  /* SRAM bank 0 */
+  DSRAM_A (rwx) : ORIGIN = 0x20000200, LENGTH = 32k - 0x200
+  /* SRAM bank 3+4+5+6+7 */
+  DSRAM_B (rwx) : ORIGIN = 0x20048000, LENGTH = 64k
+  /* stack must not be in bank 1,2,7 where ISRAM or CACHE
+     are set at power on */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Custom stack and heap sizes */
+__stack_size__ = 0x2000;
+__heap_size__  = 0x6000;
+
+/* select custom or default sizes for stack and heap */
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0C00;
+
+
+/* Linker script to place sections and symbol values.
+ * It references the following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines the following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .vectors :
+    {
+        KEEP(*(.vectors))
+        __Vectors_End = .;
+        __Vectors_Size = __Vectors_End - __Vectors;
+        __end__ = .;
+        KEEP(*(.checksum))
+    } > FLASH0
+
+    .security_options :
+    {
+        . = ALIGN(4);
+        KEEP(*(.security_options))
+        . = ALIGN(4);
+    } > FLASH0
+
+    .text :
+    {
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (__etext2)
+        LONG (__data2_start__)
+        LONG (__data2_end__ - __data2_start__)
+        __copy_table_end__ = .;
+    } > FLASH
+    */
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (__bss2_start__)
+        LONG (__bss2_end__ - __bss2_start__)
+        __zero_table_end__ = .;
+    } > FLASH
+
+
+    __etext = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > DSRAM_A
+
+    .bss :
+    {
+        . = ALIGN(16);
+        __bss2_start__ = .;
+        *(COMMON)
+        . = ALIGN(16);
+        __bss2_end__ = .;
+        __bss_start__ = .;
+        *(.bss*)
+        . = ALIGN(16);
+        __bss_end__ = .;
+    } > DSRAM_B
+
+    __StackTop = ORIGIN(DSRAM_B);
+    __StackLimit = __StackTop  - STACK_SIZE;
+    __HeapLimit  = __StackLimit;
+    __HeapBase   = __HeapLimit - HEAP_SIZE;
+    __end__      = __HeapBase;
+    PROVIDE(end  = __end__);
+    PROVIDE(__stack = __StackTop);
+}
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_IAR/ADuCM4050.icf b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_IAR/ADuCM4050.icf
new file mode 100755
index 00000000000..318ad52023c
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_IAR/ADuCM4050.icf
@@ -0,0 +1,48 @@
+/******************************************************************************
+*  File: ADuCM4050.icf
+*  ILINK Configuration File for Analog Devices ADuCM4050 processor
+*
+*  Copyright (c) 2011 - 2014 ARM LIMITED
+*  Copyright (c) 2016 - 2017 Analog Devices, Inc.
+*
+*  All rights reserved.
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions are met:
+*  - Redistributions of source code must retain the above copyright
+*    notice, this list of conditions and the following disclaimer.
+*  - Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the distribution.
+*  - Neither the name of ARM nor the names of its contributors may be used
+*    to endorse or promote products derived from this software without
+*    specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+*  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+*  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+*  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+*  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+*  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+*  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+*  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+*  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+*  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+*  POSSIBILITY OF SUCH DAMAGE.
+******************************************************************************/
+define memory mem with size               = 4G;
+define region ROM_PAGE0_INTVEC            = mem:[from 0x00000000 size 0x000001A0];
+define region ROM_PAGE0_CHECKSUM          = mem:[from 0x000001A0 size 0x00000660];
+define region ROM_REGION                  = mem:[from 0x00000800 size 506K];
+define region RAM_bank1_region            = mem:[from 0x20040000 size 0x00008000];
+define region RAM_bank2_region            = mem:[from 0x20000200 size 0x00007E00]
+                                          | mem:[from 0x20048000 size 0x00010000];
+define block CSTACK   with alignment = 16, size = 0x2000 { };
+define block HEAP     with alignment = 16, size = 0x6000 { };
+do not initialize                         { section .noinit };
+initialize by copy                        { rw };
+place at start of ROM_PAGE0_INTVEC        { ro section .vectors  };
+place in          ROM_PAGE0_CHECKSUM      { ro section .checksum };
+place in          ROM_REGION              { ro };
+place at end of   RAM_bank1_region        { block CSTACK };
+place at start of RAM_bank1_region        { block HEAP };
+place in          RAM_bank2_region        { rw };
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/PeripheralPins.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/PeripheralPins.c
new file mode 100755
index 00000000000..8257894757b
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/PeripheralPins.c
@@ -0,0 +1,138 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+/*
+    The ADuCM4050 is made in two package variants.
+
+    64 lead LFCSP & 72 ball WLCSP
+
+    There are some differences for Port 2 between the two variants
+    WLCSP also has Port 3.
+
+    The #define ADUCM4050_LFCSP is used to determine which variant the code
+    is built for.
+
+    For LFCSP leave the #define in, to build for ADUCM4050_WLCSP remove.
+*/
+#define ADUCM4050_LFCSP
+
+#include "PeripheralPins.h"
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+    {P0_10, UART_0, 1},
+    {P1_15, UART_1, 2},
+    {NC,  NC, 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {P0_11, UART_0, 1},
+    {P2_00, UART_1, 2},
+    {NC,  NC, 0}
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+    {P0_00, SPI_0, 1},
+    {P1_06, SPI_1, 1},
+    {P1_02, SPI_2, 1},
+    {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {P0_01, SPI_0, 1},
+    {P1_07, SPI_1, 1},
+    {P1_03, SPI_2, 1},
+    {NC, NC, 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {P0_02, SPI_0, 1},
+    {P1_08, SPI_1, 1},
+    {P1_04, SPI_2, 1},
+    {NC, NC, 0}
+};
+
+#if defined(ADUCM4050_LFCSP)
+const PinMap PinMap_SPI_SSEL[] = {
+    {P0_03, SPI_0, 1},
+    {P1_09, SPI_1, 1},
+    {P2_10, SPI_2, 1},
+    {NC, NC, 0}
+};
+#else
+const PinMap PinMap_SPI_SSEL[] = {
+    {P0_03, SPI_0, 1},
+    {P1_09, SPI_1, 1},
+    {P2_15, SPI_2, 1},
+    {NC, NC, 0}
+};
+#endif
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+    {P0_05, I2C_0, 1},
+    {NC, NC, 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {P0_04, I2C_0, 1},
+    {NC, NC, 0}
+};
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+    {P2_03, ADC0_VIN0, 1},
+    {P2_04, ADC0_VIN1, 1},
+    {P2_05, ADC0_VIN2, 1},
+    {P2_06, ADC0_VIN3, 1},
+    {P2_07, ADC0_VIN4, 1},
+    {P2_08, ADC0_VIN5, 1},
+    {P2_09, ADC0_VIN6, 1},
+#ifdef ADUCM4050_LFCSP
+    {P2_10, ADC0_VIN7, 1},
+#endif
+    {NC, NC, 0}
+};
+
+/************RTC***************/
+const PinMap PinMap_RTC[] = {
+    {NC, OSC32KCLK, 0},
+};
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/PeripheralPins.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/PeripheralPins.h
new file mode 100755
index 00000000000..40ef7f85b12
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/PeripheralPins.h
@@ -0,0 +1,67 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifndef MBED_PERIPHERALPINS_H
+#define MBED_PERIPHERALPINS_H
+
+#include "pinmap.h"
+#include "PeripheralNames.h"
+
+/************RTC***************/
+extern const PinMap PinMap_RTC[];
+
+/************ADC***************/
+extern const PinMap PinMap_ADC[];
+
+/************I2C***************/
+extern const PinMap PinMap_I2C_SDA[];
+extern const PinMap PinMap_I2C_SCL[];
+
+/************UART***************/
+extern const PinMap PinMap_UART_TX[];
+extern const PinMap PinMap_UART_RX[];
+
+/************SPI***************/
+extern const PinMap PinMap_SPI_SCLK[];
+extern const PinMap PinMap_SPI_MOSI[];
+extern const PinMap PinMap_SPI_MISO[];
+extern const PinMap PinMap_SPI_SSEL[];
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c
new file mode 100755
index 00000000000..baa96a694ef
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c
@@ -0,0 +1,228 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "adi_adc_def.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ADC Device number */
+#define ADC_DEV_NUM                (0u)
+
+/* Memory Required for adc driver */
+static uint32_t DeviceMemory[(ADI_ADC_MEMORY_SIZE+3)/4];
+/* Active channel */
+static uint32_t adi_pin2channel(PinName pin);
+
+/**
+ * \defgroup hal_analogin Analogin hal functions
+ * @{
+ */
+
+/** Initialize the analogin peripheral
+ *
+ * Configures the pin used by analogin.
+ * @param obj The analogin object to initialize
+ * @param pin The analogin pin name
+ */
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    ADI_ADC_HANDLE hDevice;
+    bool bCalibrationDone = false;
+    bool bReady = false;
+
+    ADCName peripheral;
+    uint32_t function, channel;
+
+    peripheral = (ADCName)pinmap_peripheral(pin, &PinMap_ADC[0]);	// gives peripheral
+    MBED_ASSERT(peripheral != (ADCName)NC);
+
+    /* verify read function */
+    function = pinmap_function(pin, &PinMap_ADC[0]);
+    MBED_ASSERT(function == 1);
+
+    /* Configure PORT2_MUX registers */
+    pin_function(pin, function);
+
+    /* Configure active channel */
+    channel = adi_pin2channel(pin);
+    MBED_ASSERT(channel != 0xFFFFFFFF);
+    obj->UserBuffer.nChannels = channel;
+
+    /* Set ACLK to CCLK/16 */
+    adi_pwr_SetClockDivider(ADI_CLOCK_ACLK,16);
+
+    /* Set default values for conversion and delay cycles. This sets up a sampling rate of
+       16kHz. The sampling frequency is worked out from the following:
+
+       if delay time > 0:
+            Fs = ACLK / [((14 + sampling time) * oversample factor) + (delay time + 2)]
+       if delay time = 0:
+            Fs = ACLK / ((14 + sampling time) * oversample factor)
+
+       The sampling (or acquisition) and delay times are in number of ACLK clock cycles.
+    */
+    obj->DelayCycles = 0;
+    obj->SampleCycles = 88;
+
+    /* Open the ADC device */
+    adi_adc_Open(ADC_DEV_NUM, DeviceMemory, sizeof(DeviceMemory), &hDevice);
+    obj->hDevice = hDevice;
+
+    /* Power up ADC */
+    adi_adc_PowerUp(hDevice, true);
+
+    /* Set ADC reference */
+    adi_adc_SetVrefSource(hDevice, ADI_ADC_VREF_SRC_INT_2_50_V);
+
+    /* Enable ADC sub system */
+    adi_adc_EnableADCSubSystem(hDevice, true);
+
+    /* Wait untilthe ADC is ready for sampling */
+    while(bReady == false) {
+        adi_adc_IsReady(hDevice, &bReady);
+    }
+
+    /* Start calibration */
+    adi_adc_StartCalibration(hDevice);
+
+    /* Wait until calibration is done */
+    while (!bCalibrationDone) {
+        adi_adc_IsCalibrationDone(hDevice, &bCalibrationDone);
+    }
+
+    /* Set the delay time */
+    adi_adc_SetDelayTime(hDevice, obj->DelayCycles);
+
+    /* Set the acquisition time. (Application need to change it based on the impedence) */
+    adi_adc_SetAcquisitionTime(hDevice, obj->SampleCycles);
+
+}
+
+/** Read the input voltage, represented as a float in the range [0.0, 1.0]
+ *
+ * @param obj The analogin object
+ * @return A floating value representing the current input voltage
+ */
+float analogin_read(analogin_t *obj)
+{
+    float fl32 = (float)analogin_read_u16(obj)/(float)4095.0;
+
+    return(fl32);
+}
+
+/** Read the value from analogin pin, represented as an unsigned 16bit value
+ *
+ * @param obj The analogin object
+ * @return An unsigned 16bit value representing the current input voltage
+ */
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+    ADI_ADC_HANDLE  hDevice = obj->hDevice;
+    ADI_ADC_BUFFER  *pAdcBuffer;
+
+    /* Submit the buffer to the driver */
+    adi_adc_SubmitBuffer(hDevice, &obj->UserBuffer);
+
+    /* Enable the ADC */
+    adi_adc_Enable(hDevice, true);
+
+    adi_adc_GetBuffer(hDevice, &pAdcBuffer);
+    MBED_ASSERT(pAdcBuffer == &obj->UserBuffer);
+
+    return( (uint16_t)( ((uint16_t *)pAdcBuffer->pDataBuffer)[(pAdcBuffer->nNumConversionPasses) - 1]) );
+}
+
+/* Retrieve te active channel correspondoing to the input pin */
+static uint32_t adi_pin2channel(PinName pin)
+{
+
+    uint32_t activech;
+
+    switch(pin) {
+        case ADC_VIN0:
+            activech = ADI_ADC_CHANNEL_0;
+            break;
+        case ADC_VIN1:
+            activech = ADI_ADC_CHANNEL_1;
+            break;
+        case ADC_VIN2:
+            activech = ADI_ADC_CHANNEL_2;
+            break;
+        case ADC_VIN3:
+            activech = ADI_ADC_CHANNEL_3;
+            break;
+        case ADC_VIN4:
+            activech = ADI_ADC_CHANNEL_4;
+            break;
+        case ADC_VIN5:
+            activech = ADI_ADC_CHANNEL_5;
+            break;
+        case ADC_VIN6:
+            activech = ADI_ADC_CHANNEL_6;
+            break;
+        case ADC_VIN7:
+            activech = ADI_ADC_CHANNEL_7;
+            break;
+        default:
+            activech = (uint32_t) 0xFFFFFFFF;
+            break;
+    }
+
+    return ((uint32_t)activech);
+}
+
+
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // #if DEVICE_ANALOGIN
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis.h
new file mode 100755
index 00000000000..b0439b1db09
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis.h
@@ -0,0 +1,47 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+#define     __C
+#include "adi_processor.h"
+#include "cmsis_nvic.h"
+#undef      __C
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis_nvic.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis_nvic.h
new file mode 100755
index 00000000000..3a866a5d726
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis_nvic.h
@@ -0,0 +1,78 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_USER_IRQ_OFFSET 16
+#define NVIC_USER_IRQ_NUMBER 72
+#define NVIC_NUM_VECTORS     (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
+
+#define NVIC_RAM_VECTOR_ADDRESS   0x20000000
+#define NVIC_FLASH_VECTOR_ADDRESS 0x0
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Set the ISR for IRQn
+ *
+ * Sets an Interrupt Service Routine vector for IRQn; if the feature is available, the vector table is relocated to SRAM
+ * the first time this function is called
+ * @param[in] IRQn   The Interrupt Request number for which a vector will be registered
+ * @param[in] vector The ISR vector to register for IRQn
+ */
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+
+/** Get the ISR registered for IRQn
+ *
+ * Reads the Interrupt Service Routine currently registered for IRQn
+ * @param[in] IRQn   The Interrupt Request number the vector of which will be read
+ * @return           Returns the ISR registered for IRQn
+ */
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/device.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/device.h
new file mode 100755
index 00000000000..0d46738ec1a
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/device.h
@@ -0,0 +1,48 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_ID_LENGTH       24
+
+#include "objects.h"
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/flash_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/flash_api.c
new file mode 100755
index 00000000000..25afcc193fc
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/flash_api.c
@@ -0,0 +1,89 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifdef DEVICE_FLASH
+#include "flash_api.h"
+#include "flash_data.h"
+#include "mbed_critical.h"
+
+// This file is automagically generated
+
+// This is a flash algo binary blob. It is PIC (position independent code) that should be stored in RAM
+
+static unsigned FLASH_ALGO[] = {
+    0x20004A4B,0x60111E41,0x6211494A,0x60912107,0x074B6811,0xF011D5FC,0xD0000F30,0x21002001,
+    0x47706211,0x2400B510,0xD1082A01,0xF872F000,0x6D09493F,0xD00207C8,0xFFE2F7FF,0x46204604,
+    0x493BBD10,0x62082000,0xB5104770,0xF862F000,0x4010E8BD,0x4601E7D4,0x20004A35,0x60131E43,
+    0x49346191,0x21066211,0x68116091,0xD5FC074B,0x0F30F011,0x2001D000,0x62112100,0xB57C4770,
+    0x4B2C4C2B,0x62232500,0xF04FE03E,0x602333FF,0xD3042908,0x61236813,0x61636853,0xF04FE025,
+    0xE9CD33FF,0x29083300,0xE8DFD21A,0x1619F001,0x0A0D1013,0x79910407,0x1006F88D,0xF88D7951,
+    0x79111005,0x1004F88D,0xF88D78D1,0x78911003,0x1002F88D,0xF88D7851,0x78111001,0x1000F88D,
+    0x1300E9DD,0x61636121,0x60E02108,0x60A32304,0xF0136823,0xD0010F30,0xE0072501,0x075B6823,
+    0x3008D5FC,0x32083908,0xD1BE2900,0x62202000,0xBD7C4628,0x21004806,0x4A066041,0x4A066202,
+    0x22046342,0x22016382,0x62016542,0x00004770,0x40018000,0x676C7565,0xB8950950,0
+};
+
+static const flash_algo_t flash_algo_config = {
+    .init         = 0x00000025,
+    .uninit       = 0x00000043,
+    .erase_sector = 0x00000057,
+    .program_page = 0x0000007F,
+    .static_base  = 0x0000013C,
+    .algo_blob    = FLASH_ALGO
+};
+
+static const sector_info_t sectors_info[] = {
+    {0x0, 0x800},
+};
+
+static const flash_target_config_t flash_target_config = {
+    .page_size   = 0x800,
+    .flash_start = 0x0,
+    .flash_size  = 0x0007F000,
+    .sectors     = sectors_info,
+    .sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t)
+};
+
+void flash_set_target_config(flash_t *obj)
+{
+    obj->flash_algo = &flash_algo_config;
+    obj->target_config = &flash_target_config;
+}
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_api.c
new file mode 100755
index 00000000000..81d4be52cb7
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_api.c
@@ -0,0 +1,147 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include "mbed_assert.h"
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "adi_gpio.h"
+
+
+#define MUX_FUNC_0 0x0
+#define NUM_GPIO_PORTS 4
+
+extern uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE];
+extern uint8_t gpio_initialized;
+
+static uint16_t gpio_oen[NUM_GPIO_PORTS] = {0};
+static uint16_t gpio_output_val[NUM_GPIO_PORTS] = {0};
+
+
+/******************************************************************************
+   Function definitions
+ *****************************************************************************/
+uint32_t gpio_set(PinName pin)
+{
+    MBED_ASSERT(pin != (PinName)NC);
+    uint32_t pin_num = pin & 0xFF;
+
+    pin_function(pin, MUX_FUNC_0);
+
+    return (1 << pin_num);
+}
+
+void gpio_init(gpio_t *obj, PinName pin)
+{
+    obj->pin = pin;
+
+    if (pin == (PinName)NC) {
+        return;
+    }
+
+    // Initialize the GPIO driver. This function
+    // initializes the GPIO driver only once globally.
+    if (!gpio_initialized) {
+        adi_gpio_Init(gpioMemory, ADI_GPIO_MEMORY_SIZE);
+    }
+
+    pin_function(pin, MUX_FUNC_0);
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+    uint32_t pin = obj->pin;
+
+    pin_mode((PinName)pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    uint32_t port = obj->pin >> GPIO_PORT_SHIFT;
+    uint32_t pin_num = obj->pin & 0xFF;
+
+    if (direction ==  PIN_OUTPUT) {
+        adi_gpio_OutputEnable((ADI_GPIO_PORT)port, 1 << pin_num, true);
+        // save the input/output configuration
+        gpio_oen[port] |= (1 << pin_num);
+    } else {
+        adi_gpio_InputEnable((ADI_GPIO_PORT)port, 1 << pin_num, true);
+        // save the input/output configuration
+        gpio_oen[port] &= (~(1 << pin_num));
+    }
+}
+
+void gpio_write(gpio_t *obj, int value)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    uint32_t port = obj->pin >> GPIO_PORT_SHIFT;
+    uint32_t pin_num = obj->pin & 0xFF;
+
+    if (value & 1) {
+        adi_gpio_SetHigh((ADI_GPIO_PORT)port, (1 << pin_num));
+
+        // save the output port value
+        gpio_output_val[port] |= ((value & 1) << pin_num);
+    } else {
+        adi_gpio_SetLow((ADI_GPIO_PORT)port, (1 << pin_num));
+
+        // save the output port value
+        gpio_output_val[port] &= (~(1 << pin_num));
+    }
+}
+
+
+int gpio_read(gpio_t *obj)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    uint32_t port = obj->pin >> GPIO_PORT_SHIFT;
+    uint32_t pin_num = obj->pin & 0xFF;
+    uint16_t Data;
+
+    // check whether the pin is configured as input or output
+    if ((gpio_oen[port] >> pin_num) & 1) {
+        Data = gpio_output_val[port] & (1 << pin_num);
+    } else {
+        // otherwise call GetData
+        adi_gpio_GetData((ADI_GPIO_PORT)port, (1 << pin_num), &Data);
+    }
+
+    return ((((uint32_t)Data) >> pin_num) & 1);
+}
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_dev_mem.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_dev_mem.c
new file mode 100755
index 00000000000..5e0d99ad8b0
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_dev_mem.c
@@ -0,0 +1,47 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include <drivers/gpio/adi_gpio.h>
+
+// ADI GPIO device driver state memory. Only one state memory is required globally.
+uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE];
+
+// Flag to indicate whether the GPIO driver has been initialized
+uint8_t gpio_initialized = 0;
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c
new file mode 100755
index 00000000000..3cf237218bd
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c
@@ -0,0 +1,326 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include "gpio_irq_api.h"
+#include "adi_gpio.h"
+#include "adi_gpio_def.h"
+
+#ifdef DEVICE_INTERRUPTIN
+
+#define MAX_GPIO_LINES    16
+#define MAX_GPIO_PORTS    ADI_GPIO_NUM_PORTS
+
+typedef struct {
+    unsigned int id;
+    gpio_irq_event event;
+    uint8_t int_enable;
+} gpio_chan_info_t;
+
+extern uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE];
+extern uint8_t gpio_initialized;
+static gpio_chan_info_t channel_ids[MAX_GPIO_PORTS][MAX_GPIO_LINES];
+static gpio_irq_handler irq_handler = NULL;
+
+
+/** Local interrupt callback routine.
+ */
+static void gpio_irq_callback(void *pCBParam, uint32_t Event, void *pArg)
+{
+    uint16_t pin = *(ADI_GPIO_DATA*)pArg;
+    int index = 0;
+
+    // determine the index of the pin that caused the interrupt
+    while (pin) {
+        if (pin & 0x01) {
+            // call the user ISR. The argument Event is the port number of the GPIO line.
+            if (irq_handler != NULL)
+                irq_handler((uint32_t)channel_ids[Event][index].id, channel_ids[Event][index].event);
+        }
+        index++;
+        pin >>= 1;
+    }
+}
+
+
+/** Function to get the IENA and IENB register values.
+ *  Added here based on code from ADuCM302x
+ */
+static ADI_GPIO_RESULT adi_gpio_GetGroupInterruptPins(const ADI_GPIO_PORT Port, const IRQn_Type eIrq,
+        const ADI_GPIO_DATA Pins, uint16_t* const pValue)
+{
+    ADI_GPIO_TypeDef 	*pReg[ADI_GPIO_NUM_PORTS] = {pADI_GPIO0, pADI_GPIO1, pADI_GPIO2, pADI_GPIO3};
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+    uint16_t            Value = 0u;
+
+    pPort = pReg[Port];
+
+    switch (eIrq) {
+        case SYS_GPIO_INTA_IRQn:
+            Value = pPort->IENA;
+            break;
+        case SYS_GPIO_INTB_IRQn:
+            Value = pPort->IENB;
+            break;
+        default:
+            break; /* This shall never reach */
+    }
+
+    *pValue = (Value & Pins);
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/** Function to get the interrupt polarity register content.
+ *  Added here based on code from ADuCM302x
+ */
+static ADI_GPIO_RESULT adi_gpio_GetGroupInterruptPolarity(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins,
+        uint16_t* const pValue)
+{
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+    ADI_GPIO_TypeDef 	*pReg[ADI_GPIO_NUM_PORTS] = {pADI_GPIO0, pADI_GPIO1, pADI_GPIO2, pADI_GPIO3};
+
+    pPort = pReg[Port];
+
+    *pValue = (pPort->POL & Pins);
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/** Function to clear the relevant interrupt enable bits in both the IENA and IENB registers
+ *  for the given GPIO pin.
+ */
+static void disable_pin_interrupt(ADI_GPIO_PORT port, uint32_t pin_number)
+{
+    uint16_t int_reg_val;
+
+    // Read the current content of the IENA register
+    adi_gpio_GetGroupInterruptPins(port, SYS_GPIO_INTA_IRQn, 1 << pin_number, &int_reg_val);
+
+    // clear the bit for the pin
+    int_reg_val &= ~(1 << pin_number);
+
+    // write the interrupt register
+    adi_gpio_SetGroupInterruptPins(port, SYS_GPIO_INTA_IRQn, int_reg_val);
+
+    // Do the same to IENB
+    adi_gpio_GetGroupInterruptPins(port, SYS_GPIO_INTB_IRQn, 1 << pin_number, &int_reg_val);
+
+    // clear the bit for the pin
+    int_reg_val &= ~(1 << pin_number);
+
+    // write the interrupt register
+    adi_gpio_SetGroupInterruptPins(port, SYS_GPIO_INTB_IRQn, int_reg_val);
+}
+
+
+/** Function to set the relevant interrupt enable bits in either the IENA and IENB registers
+ *  for the given GPIO pin.
+ */
+static void enable_pin_interrupt(ADI_GPIO_PORT port, uint32_t pin_number, IRQn_Type eIrq)
+{
+    uint16_t int_reg_val;
+
+    // Read the current interrupt enable register content
+    adi_gpio_GetGroupInterruptPins(port, eIrq, 1 << pin_number, &int_reg_val);
+
+    // set the bit for the pin
+    int_reg_val |= (1 << pin_number);
+
+    // write the interrupt register
+    adi_gpio_SetGroupInterruptPins(port, eIrq, int_reg_val);
+}
+
+
+/** Initialize the GPIO IRQ pin
+ *
+ * @param obj     The GPIO object to initialize
+ * @param pin     The GPIO pin name
+ * @param handler The handler to be attached to GPIO IRQ
+ * @param id      The object ID (id != 0, 0 is reserved)
+ * @return -1 if pin is NC, 0 otherwise
+ */
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
+    uint32_t port = pin >> GPIO_PORT_SHIFT;
+    uint32_t pin_num = pin & 0xFF;
+
+    // check for valid pin and ID
+    if ((pin == NC) || (id == 0)) {
+        return -1;
+    }
+
+    // make sure gpio driver has been initialized
+    if (!gpio_initialized) {
+        adi_gpio_Init(gpioMemory,ADI_GPIO_MEMORY_SIZE);
+        gpio_initialized = 1;
+    }
+
+    // save the handler
+    if (handler) {
+        irq_handler = handler;
+    }
+
+    // disable the interrupt for the given pin
+    disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num);
+
+    // set the port pin as input
+    adi_gpio_InputEnable(port, 1 << pin_num, true);
+
+    // save the ID for future reference
+    channel_ids[port][pin_num].id = id;
+    channel_ids[port][pin_num].event = IRQ_NONE;
+    channel_ids[port][pin_num].int_enable = 0;
+    obj->id = id;
+    obj->pinname = pin;
+
+    return 0;
+}
+
+/** Release the GPIO IRQ PIN
+ *
+ * @param obj The gpio object
+ */
+void gpio_irq_free(gpio_irq_t *obj)
+{
+    uint32_t port = obj->pinname >> GPIO_PORT_SHIFT;
+    uint32_t pin_num = obj->pinname & 0xFF;
+
+    // disable interrupt for the given pin
+    gpio_irq_disable(obj);
+
+    // clear the status table
+    channel_ids[port][pin_num].id = 0;
+    channel_ids[port][pin_num].event = IRQ_NONE;
+    channel_ids[port][pin_num].int_enable = 0;
+}
+
+/** Enable/disable pin IRQ event
+ *
+ * @param obj    The GPIO object
+ * @param event  The GPIO IRQ event
+ * @param enable The enable flag
+ */
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+    uint16_t int_polarity_reg;
+    uint32_t port = obj->pinname >> GPIO_PORT_SHIFT;
+    uint32_t pin_num = obj->pinname & 0xFF;
+
+    if (event == IRQ_NONE) {
+        return;
+    }
+
+    // read the current polarity register
+    adi_gpio_GetGroupInterruptPolarity((ADI_GPIO_PORT)port,	1 << pin_num, &int_polarity_reg);
+
+    if (event == IRQ_RISE) {
+        int_polarity_reg |= (1 << pin_num);
+    } else {
+        int_polarity_reg &= ~(1 << pin_num);
+    }
+
+    // set the polarity register
+    adi_gpio_SetGroupInterruptPolarity((ADI_GPIO_PORT)port, int_polarity_reg);
+
+    channel_ids[port][pin_num].event = event;
+
+    // enable interrupt for this pin if enable flag is set
+    if (enable) {
+        gpio_irq_enable(obj);
+    } else {
+        gpio_irq_disable(obj);
+    }
+}
+
+/** Enable GPIO IRQ
+ *
+ * This is target dependent, as it might enable the entire port or just a pin
+ * @param obj The GPIO object
+ */
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+    uint32_t port = obj->pinname >> GPIO_PORT_SHIFT;
+    uint32_t pin_num = obj->pinname & 0xFF;
+
+    if (channel_ids[port][pin_num].event == IRQ_NONE) {
+        return;
+    }
+
+    // Group all RISE interrupts in INTA and FALL interrupts in INTB
+    if (channel_ids[port][pin_num].event == IRQ_RISE) {
+        // set the callback routine
+        adi_gpio_RegisterCallback(SYS_GPIO_INTA_IRQn, gpio_irq_callback, obj);
+        enable_pin_interrupt((ADI_GPIO_PORT)port, pin_num, SYS_GPIO_INTA_IRQn);
+    } else if (channel_ids[port][pin_num].event == IRQ_FALL) {
+        // set the callback routine
+        adi_gpio_RegisterCallback(SYS_GPIO_INTB_IRQn, gpio_irq_callback, obj);
+        enable_pin_interrupt((ADI_GPIO_PORT)port, pin_num, SYS_GPIO_INTB_IRQn);
+    }
+
+    channel_ids[port][pin_num].int_enable = 1;
+}
+
+/** Disable GPIO IRQ
+ *
+ * This is target dependent, as it might disable the entire port or just a pin
+ * @param obj The GPIO object
+ */
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+    uint32_t port = obj->pinname >> GPIO_PORT_SHIFT;
+    uint32_t pin_num = obj->pinname & 0xFF;
+
+    if (channel_ids[port][pin_num].event == IRQ_NONE) {
+        return;
+    }
+
+    // Group all RISE interrupts in INTA and FALL interrupts in INTB
+    if (channel_ids[port][pin_num].event == IRQ_RISE) {
+        disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num);
+    }
+    else if (channel_ids[port][pin_num].event == IRQ_FALL) {
+        disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num);
+    }
+
+    channel_ids[port][pin_num].int_enable = 0;
+}
+
+#endif	// #ifdef DEVICE_INTERRUPTIN
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_object.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_object.h
new file mode 100755
index 00000000000..8d59616b7f7
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_object.h
@@ -0,0 +1,61 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName pin;
+} gpio_t;
+
+static inline int gpio_is_connected(const gpio_t *obj)
+{
+    return obj->pin != (PinName)NC;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c
new file mode 100755
index 00000000000..f25d80c9105
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c
@@ -0,0 +1,220 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include "mbed_assert.h"
+#include "i2c_api.h"
+
+#if DEVICE_I2C
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+#include "drivers/i2c/adi_i2c.h"
+
+
+
+#if defined(BUILD_I2C_MI_DYNAMIC)
+#if defined(ADI_DEBUG)
+#warning "BUILD_I2C_MI_DYNAMIC is defined.  Memory allocation for I2C will be dynamic"
+int adi_i2c_memtype = 0;
+#endif
+#else
+static uint8_t          i2c_Mem[ADI_I2C_MEMORY_SIZE];
+static ADI_I2C_HANDLE   i2c_Handle;
+#if defined(ADI_DEBUG)
+#warning "BUILD_I2C_MI_DYNAMIC is NOT defined.  Memory allocation for I2C will be static"
+int adi_i2c_memtype = 1;
+#endif
+#endif
+
+
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
+    uint32_t        i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
+    uint32_t        i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL);
+    ADI_I2C_HANDLE  *pI2C_Handle;
+    uint8_t         *I2C_Mem;
+    ADI_I2C_RESULT  I2C_Return = ADI_I2C_SUCCESS;
+    uint32_t        I2C_DevNum = I2C_0;     /* ADuCM4050 only has 1 I2C port */
+
+
+#if defined(BUILD_I2C_MI_DYNAMIC)
+    I2C_DevNum = I2C_0;
+    pI2C_Handle = &obj->I2C_Handle;
+    obj->pI2C_Handle = pI2C_Handle;
+    I2C_Mem = obj->I2C_Mem;
+#else
+    I2C_DevNum = I2C_0;
+    pI2C_Handle = &i2c_Handle;
+    obj->pI2C_Handle = pI2C_Handle;
+    I2C_Mem = &i2c_Mem[0];
+#endif
+
+
+    obj->instance = pinmap_merge(i2c_sda, i2c_scl);
+    MBED_ASSERT((int)obj->instance != NC);
+    pinmap_pinout(sda, PinMap_I2C_SDA);
+    pinmap_pinout(scl, PinMap_I2C_SCL);
+    SystemCoreClockUpdate();
+    I2C_Return = adi_i2c_Open(I2C_DevNum, I2C_Mem, ADI_I2C_MEMORY_SIZE, pI2C_Handle);
+    if (I2C_Return) {
+        obj->error = I2C_EVENT_ERROR;
+        return;
+    }
+    I2C_Return = adi_i2c_Reset(*pI2C_Handle);
+    if (I2C_Return) {
+        obj->error = I2C_EVENT_ERROR;
+        return;
+    }
+}
+
+
+int i2c_start(i2c_t *obj)
+{
+    /* The Hardware does not support this feature. */
+    return -1;
+}
+
+
+int i2c_stop(i2c_t *obj)
+{
+    /* The Hardware does not support this feature. */
+    return -1;
+}
+
+
+void i2c_frequency(i2c_t *obj, int hz)
+{
+    ADI_I2C_HANDLE  I2C_Handle;
+    ADI_I2C_RESULT  I2C_Return = ADI_I2C_SUCCESS;
+
+
+    I2C_Handle = *obj->pI2C_Handle;
+    I2C_Return = adi_i2c_SetBitRate(I2C_Handle, (uint32_t) hz);
+    if (I2C_Return) {
+        obj->error = I2C_EVENT_ERROR;
+        return;
+    }
+}
+
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
+    ADI_I2C_RESULT      I2C_Return;
+    ADI_I2C_TRANSACTION I2C_inst;
+    uint8_t             I2C_PrologueData = 0x00;
+    uint32_t            I2C_Errors;                 /* HW Error result */
+    ADI_I2C_HANDLE      I2C_Handle;
+
+
+    I2C_Handle = *obj->pI2C_Handle;
+    I2C_Return = adi_i2c_SetSlaveAddress(I2C_Handle, (address & 0x0000FFFF));
+    I2C_inst.pPrologue     = &I2C_PrologueData;
+    I2C_inst.nPrologueSize = 0;
+    I2C_inst.pData         = (uint8_t*) data;
+    I2C_inst.nDataSize     = length;
+    I2C_inst.bReadNotWrite = true;
+    I2C_inst.bRepeatStart  = stop;
+    I2C_Return = adi_i2c_ReadWrite(I2C_Handle, &I2C_inst, &I2C_Errors);
+    if (I2C_Return) {
+        obj->error = I2C_EVENT_ERROR;
+        return -1;
+    } else {
+        return length;
+    }
+}
+
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
+    ADI_I2C_RESULT      I2C_Return = ADI_I2C_SUCCESS;
+    ADI_I2C_TRANSACTION I2C_inst;
+    uint8_t             I2C_PrologueData = 0x00;
+    uint32_t            I2C_Errors;                 /* HW Error result */
+    ADI_I2C_HANDLE      I2C_Handle;
+
+
+    I2C_Handle = *obj->pI2C_Handle;
+    I2C_Return = adi_i2c_SetSlaveAddress(I2C_Handle, (address & 0x0000FFFF));
+    I2C_inst.pPrologue      = &I2C_PrologueData;
+    I2C_inst.nPrologueSize  = 0;
+    I2C_inst.pData          = (uint8_t*) data;
+    I2C_inst.nDataSize      = length;
+    I2C_inst.bReadNotWrite  = false;
+    I2C_inst.bRepeatStart   = stop;
+    I2C_Return = adi_i2c_ReadWrite(I2C_Handle, &I2C_inst, &I2C_Errors);
+    if (I2C_Return) {
+        obj->error = I2C_EVENT_ERROR;
+        return -1;
+    } else {
+        return length;
+    }
+}
+
+
+void i2c_reset(i2c_t *obj)
+{
+    ADI_I2C_RESULT      I2C_Return;
+    ADI_I2C_HANDLE      I2C_Handle = *obj->pI2C_Handle;
+
+    I2C_Return = adi_i2c_Reset(I2C_Handle);
+    if (I2C_Return) {
+        obj->error = I2C_EVENT_ERROR;
+        return;
+    }
+}
+
+
+int i2c_byte_read(i2c_t *obj, int last)
+{
+    /* The Hardware does not support this feature. */
+    return -1;
+}
+
+
+int i2c_byte_write(i2c_t *obj, int data)
+{
+    /* The Hardware does not support this feature. */
+    return -1;
+}
+
+#endif  // #if DEVICE_I2C
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h
new file mode 100755
index 00000000000..495faf8c671
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h
@@ -0,0 +1,112 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+#include "gpio_object.h"
+#include "adi_rng.h"
+
+#include "adi_i2c.h"
+#include "adi_spi.h"
+#include "adi_adc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    unsigned int id;
+    PinName pinname;
+};
+
+struct sleep_s {
+    int temp;
+};
+
+struct serial_s {
+    int index;
+};
+
+struct trng_s {
+    ADI_RNG_HANDLE  RNGhDevice;
+};
+
+#define BUILD_I2C_MI_DYNAMIC
+struct i2c_s {
+    uint32_t        instance;
+    uint32_t        error;
+    ADI_I2C_HANDLE  *pI2C_Handle;
+#if defined(BUILD_I2C_MI_DYNAMIC)
+    ADI_I2C_HANDLE  I2C_Handle;
+    uint8_t         I2C_Mem[ADI_I2C_MEMORY_SIZE];
+#endif
+};
+
+#define BUILD_SPI_MI_DYNAMIC
+struct spi_s {
+    uint32_t        instance;
+    uint32_t        error;
+    ADI_SPI_HANDLE  *pSPI_Handle;
+#if defined(BUILD_SPI_MI_DYNAMIC)
+    ADI_SPI_HANDLE  SPI_Handle;
+    uint8_t         SPI_Mem[ADI_SPI_MEMORY_SIZE];
+#endif
+};
+
+#include "gpio_object.h"
+
+struct analogin_s {
+    ADI_ADC_HANDLE  hDevice;
+    ADI_ADC_BUFFER  UserBuffer;
+    uint8_t         DelayCycles;
+    uint8_t         SampleCycles;
+};
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/pinmap.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/pinmap.c
new file mode 100755
index 00000000000..bb061e0ba4a
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/pinmap.c
@@ -0,0 +1,103 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+#include "PinNames.h"
+#include "adi_gpio.h"
+
+void pin_function(PinName pin, int function)
+{
+    // pin is composed of port and pin
+    // function is the function number (the mux selection number shifted by the pin value
+    // and written to pin mux register, each pin mux takes 2 bits hence multiplying by 2)
+
+    MBED_ASSERT(pin != (PinName)NC);
+
+    uint8_t port = pin >> GPIO_PORT_SHIFT;
+    uint32_t cfg_reg, mask;
+    volatile uint32_t *pGPIO_CFG;
+
+    switch (port) {
+        case 0:
+            pGPIO_CFG = (volatile uint32_t *)REG_GPIO0_CFG;
+            break;
+        case 1:
+            pGPIO_CFG = (volatile uint32_t *)REG_GPIO1_CFG;
+            break;
+        case 2:
+            pGPIO_CFG = (volatile uint32_t *)REG_GPIO2_CFG;
+            break;
+
+        default:
+            return;
+    }
+
+    cfg_reg = *pGPIO_CFG;
+    // clear the corresponding 2 bit field first before writing the function
+    // bits
+    mask = ~(3 << (pin * 2));
+    cfg_reg = cfg_reg & mask | (function << (pin*2));
+    *pGPIO_CFG = cfg_reg;
+}
+
+void pin_mode(PinName pin, PinMode mode)
+{
+    MBED_ASSERT(pin != (PinName)NC);
+
+    uint8_t port = pin >> GPIO_PORT_SHIFT;
+    uint32_t pin_reg_value = 2 ^ (0xFF & pin);
+
+    switch (mode) {
+        case PullNone:
+            adi_gpio_PullUpEnable((ADI_GPIO_PORT)port, (ADI_GPIO_DATA) pin_reg_value,false);
+            break;
+
+        case PullDown:
+        case PullUp:
+            adi_gpio_PullUpEnable((ADI_GPIO_PORT)port, (ADI_GPIO_DATA) pin_reg_value,true);
+            break;
+
+        default:
+            break;
+    }
+}
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/rtc_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/rtc_api.c
new file mode 100755
index 00000000000..8b650705fc6
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/rtc_api.c
@@ -0,0 +1,94 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include "rtc_api.h"
+
+#if DEVICE_RTC
+
+#include "adi_rtc.h"
+#include "adi_pwr.h"
+
+#define RTC_DEVICE_NUM    0
+static uint8_t aRtcDevMem0[ADI_RTC_MEMORY_SIZE];
+static ADI_RTC_HANDLE hDevice0 = NULL;
+
+
+void rtc_init(void)
+{
+    /* initialize driver */
+    adi_rtc_Open(RTC_DEVICE_NUM,aRtcDevMem0,ADI_RTC_MEMORY_SIZE,&hDevice0);
+
+    adi_rtc_Enable(hDevice0, true);
+}
+
+void rtc_free(void)
+{
+    adi_rtc_Close(hDevice0);
+}
+
+/*
+ * Little check routine to see if the RTC has been enabled
+ * 0 = Disabled, 1 = Enabled
+ */
+int rtc_isenabled(void)
+{
+    uint32_t ControlReg;
+
+    adi_rtc_GetControl (hDevice0, ADI_RTC_CONTROL_REGISTER_0,&ControlReg);
+
+    return((int) (ControlReg & BITM_RTC_CR0_CNTEN));
+}
+
+time_t rtc_read(void)
+{
+    time_t currentCount;
+
+    adi_rtc_GetCount(hDevice0, (uint32_t *)(&currentCount));
+
+    return(currentCount);
+}
+
+void rtc_write(time_t t)
+{
+    adi_rtc_SetCount (hDevice0, t);
+}
+
+#endif //  #if DEVICE_RTC
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c
new file mode 100755
index 00000000000..fabe28d035e
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c
@@ -0,0 +1,251 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include "serial_api.h"
+
+#if DEVICE_SERIAL
+
+// math.h required for floating point operations for baud rate calculation
+#include <math.h>
+#include "mbed_assert.h"
+
+#include <string.h>
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "PeripheralPins.h"
+#include "drivers/uart/adi_uart.h"
+#define ADI_UART_MEMORY_SIZE   (ADI_UART_BIDIR_MEMORY_SIZE)
+#define ADI_UART_NUM_DEVICES   2
+
+static ADI_UART_HANDLE hDevice[ADI_UART_NUM_DEVICES];
+static uint32_t UartDeviceMem[ADI_UART_NUM_DEVICES][(ADI_UART_MEMORY_SIZE + 3)/4];
+static uint32_t serial_irq_ids[ADI_UART_NUM_DEVICES] = {0};
+static uart_irq_handler irq_handler = NULL;
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+static int rxbuffer[2];
+static int txbuffer[2];
+
+static void uart_callback(void *pCBParam, uint32_t Event, void *pArg)
+{
+    MBED_ASSERT(irq_handler);
+    serial_t *obj = pCBParam;
+    if (Event == ADI_UART_EVENT_TX_BUFFER_PROCESSED)
+        irq_handler(serial_irq_ids[obj->index], TxIrq);
+    else if (Event == ADI_UART_EVENT_RX_BUFFER_PROCESSED)
+        irq_handler(serial_irq_ids[obj->index], RxIrq);
+}
+
+
+void serial_free(serial_t *obj)
+{
+    adi_uart_Close(hDevice[obj->index]);
+}
+
+void serial_baud(serial_t *obj, int baudrate)
+{
+    uint32_t uartdivc,uartdivm,uartdivn,uartosr;
+
+    // figures based on PCLK of 26MHz
+    switch (baudrate) {
+        case    9600:
+            uartdivc= 28;
+            uartdivm= 3;
+            uartdivn= 46;
+            uartosr= 3;
+            break;
+        case   19200:
+            uartdivc= 14;
+            uartdivm= 3;
+            uartdivn= 46;
+            uartosr= 3;
+            break;
+        case   38400:
+            uartdivc= 07;
+            uartdivm= 3;
+            uartdivn= 46;
+            uartosr= 3;
+            break;
+        case   57600:
+            uartdivc= 14;
+            uartdivm= 1;
+            uartdivn= 15;
+            uartosr= 3;
+            break;
+        case  115200:
+            uartdivc= 03;
+            uartdivm= 2;
+            uartdivn= 719;
+            uartosr= 3;
+            break;
+        case  230400:
+            uartdivc= 03;
+            uartdivm= 1;
+            uartdivn= 359;
+            uartosr= 3;
+            break;
+        default:    // default of 9600kbps
+            uartdivc= 28;
+            uartdivm= 3;
+            uartdivn= 46;
+            uartosr= 3;
+            break;
+    }
+
+    adi_uart_ConfigBaudRate(hDevice[obj->index],uartdivc,uartdivm,uartdivn,uartosr);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
+    ADI_UART_PARITY convertedparity   = ADI_UART_NO_PARITY;
+    ADI_UART_STOPBITS convertedstopbits = ADI_UART_ONE_STOPBIT;
+
+    if (stop_bits) {
+        convertedstopbits = ADI_UART_ONE_AND_HALF_TWO_STOPBITS;
+    }
+
+    if (parity == ParityOdd) {
+        convertedparity = ADI_UART_ODD_PARITY;
+    } else if (parity == ParityEven) {
+        convertedparity = ADI_UART_EVEN_PARITY;
+    } else if (parity == ParityForced1) {
+        convertedparity = ADI_UART_ODD_PARITY_STICKY;
+    } else if (parity == ParityForced0) {
+        convertedparity = ADI_UART_EVEN_PARITY_STICKY;
+    }
+
+    adi_uart_SetConfiguration(hDevice[obj->index], convertedparity, convertedstopbits,
+                              (ADI_UART_WORDLEN)(data_bits - 5));
+}
+
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
+    uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
+    uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
+    obj->index = pinmap_merge(uart_tx, uart_rx);
+    MBED_ASSERT((int)obj->index != NC);
+    adi_uart_Open(obj->index,ADI_UART_DIR_BIDIRECTION,UartDeviceMem[obj->index],ADI_UART_MEMORY_SIZE,&hDevice[obj->index]);
+    serial_baud(obj, 9600);
+    serial_format(obj, 8, ParityNone, 1);
+    pinmap_pinout(tx, PinMap_UART_TX);
+    pinmap_pinout(rx, PinMap_UART_RX);
+    if (tx != NC) {
+        pin_mode(tx, PullUp);
+    }
+    if (rx != NC) {
+        pin_mode(rx, PullUp);
+    }
+    if (obj->index == STDIO_UART) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+}
+
+int serial_readable(serial_t *obj)
+{
+    bool bAvailable = false;
+    adi_uart_IsRxBufferAvailable(hDevice[obj->index], &bAvailable);
+    return bAvailable;
+}
+
+int serial_getc(serial_t *obj)
+{
+    int c;
+    void *pBuff;
+    uint32_t pHwError;
+    adi_uart_SubmitRxBuffer(hDevice[obj->index], &rxbuffer[obj->index], 1, 1);
+    adi_uart_GetRxBuffer(hDevice[obj->index], &pBuff, &pHwError);
+    c = (unsigned) rxbuffer[obj->index];
+    return (c);
+}
+
+int serial_writable(serial_t *obj)
+{
+    bool bAvailable = false;
+    adi_uart_IsTxBufferAvailable(hDevice[obj->index], &bAvailable);
+    return bAvailable;
+}
+
+void serial_putc(serial_t *obj, int c)
+{
+    void *pBuff;
+    uint32_t pHwError;
+    txbuffer[obj->index]= (char) c;
+    adi_uart_SubmitTxBuffer(hDevice[obj->index],&txbuffer[obj->index], 1, 1);
+    adi_uart_GetTxBuffer(hDevice[obj->index], &pBuff, &pHwError);
+    return;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+    MBED_ASSERT(obj);
+
+    adi_uart_RegisterCallback(hDevice[obj->index], &uart_callback, obj);
+    if (enable) {
+    } else {
+    }
+}
+
+void serial_pinout_tx(PinName tx)
+{
+    pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj)
+{
+    adi_uart_ForceTxBreak(hDevice[obj->index], true);
+}
+
+void serial_break_clear(serial_t *obj)
+{
+    adi_uart_ForceTxBreak(hDevice[obj->index], false);
+}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+
+    MBED_ASSERT(obj);
+
+    irq_handler = handler;
+    serial_irq_ids[obj->index] = id;
+}
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.c
new file mode 100755
index 00000000000..b6ea83f1ed4
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.c
@@ -0,0 +1,256 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include "sleep_api.h"
+
+#ifdef DEVICE_SLEEP
+
+#include "adi_pwr.h"
+#include "adi_pwr_def.h"
+#include "adi_rtos_map.h"
+#include "adi_ADuCM4050_device.h"
+#include "sleep.h"
+
+/**
+ * Function to put processor into sleep (FLEXI mode only).
+ */
+static void go_into_WFI(const ADI_PWR_POWER_MODE PowerMode)
+{
+    uint32_t savedPriority;
+    uint16_t savedWDT;
+    uint16_t ActiveWDT;
+    uint32_t scrSetBits = 0u;
+    uint32_t scrClrBits = 0u;
+    uint32_t IntStatus = 0u;
+
+    /* pre-calculate the sleep-on-exit set/clear bits */
+    scrSetBits |= SCB_SCR_SLEEPONEXIT_Msk;
+
+    /* wfi without deepsleep or sleep-on-exit */
+    scrClrBits |= (uint32_t)(BITM_NVIC_INTCON0_SLEEPDEEP | BITM_NVIC_INTCON0_SLEEPONEXIT);
+
+    ADI_ENTER_CRITICAL_REGION();
+
+    { /* these lines must be in a success-checking loop if they are not inside critical section */
+        /* Uninterruptable unlock sequence */
+        pADI_PMG0->PWRKEY = ADI_PMG_KEY;
+
+        /* Clear the previous mode and set new mode */
+        pADI_PMG0->PWRMOD = (uint32_t) ( ( pADI_PMG0->PWRMOD & (uint32_t) (~BITM_PMG_PWRMOD_MODE) ) | PowerMode );
+    }
+
+    /* Update the SCR (sleepdeep and sleep-on-exit bits) */
+    SCB->SCR = ((SCB->SCR | scrSetBits) & ~scrClrBits);
+
+    /* save/restore current Base Priority Level */
+    savedPriority = __get_BASEPRI();
+
+    /* assert caller's priority threshold (left-justified), currently set to 0, i.e. disable interrupt masking */
+    __set_BASEPRI(0);
+
+    /* save/restore WDT control register (which is not retained during hibernation) */
+    savedWDT = pADI_WDT0->CTL;
+
+    /* optimization: compute local WDT enable flag once (outside the loop) */
+    ActiveWDT = ((savedWDT & BITM_WDT_CTL_EN) >> BITP_WDT_CTL_EN);
+
+    /* SAR-51938: insure WDT is fully synchronized or looping on interrupts
+       in hibernate mode may lock out the sync bits.
+
+       In hibernate mode (during which the WDT registers are not retained),
+       the WDT registers will have been reset to default values after each
+       interrupt exit and we require a WDT clock domain sync.
+
+       We also need to insure a clock domain sync before (re)entering the WFI
+       in case an interrupt did a watchdog kick.
+
+       Optimization: only incur WDT sync overhead (~100us) if the WDT is enabled.
+    */
+    if (ActiveWDT > 0u) {
+        while ((pADI_WDT0->STAT & (uint32_t)(BITM_WDT_STAT_COUNTING | BITM_WDT_STAT_LOADING | BITM_WDT_STAT_CLRIRQ)) != 0u) {
+            ;
+        }
+    }
+
+    __DSB();  /* bus sync to insure register writes from interrupt handlers are always complete before WFI */
+
+    /* NOTE: aggressive compiler optimizations can muck up critical timing here, so reduce if hangs are present */
+
+    /* The WFI loop MUST reside in a critical section because we need to insure that the interrupt
+       that is planned to take us out of WFI (via a call to adi_pwr_ExitLowPowerMode()) is not
+       dispatched until we get into the WFI.  If that interrupt sneaks in prior to our getting to the
+       WFI, then we may end up waiting (potentially forever) for an interrupt that has already occurred.
+    */
+    __WFI();
+
+    /* Recycle the critical section so that other (non-wakeup) interrupts are dispatched.
+       This allows *pnInterruptOccurred to be set from any interrupt context.
+     */
+    ADI_EXIT_CRITICAL_REGION();
+    /* nop */
+    ADI_ENTER_CRITICAL_REGION();
+
+    /* ...still within critical section... */
+
+    /* Restore previous base priority */
+    __set_BASEPRI(savedPriority);
+
+    /* 	conditionally, restore WDT control register.
+    	avoid unnecessary WDT writes which will invoke a sync problem
+    	described above as SAR-51938: going into hibernation with pending,
+    	unsynchronized WDT writes may lock out the sync bits.
+
+    	Note: it takes over 1000us to sync WDT writes between the 26MHz and
+    	32kHz clock	domains, so this write may actually impact the NEXT
+    	low-power entry.
+    */
+    if (ActiveWDT > 0u) {
+        pADI_WDT0->CTL = savedWDT;
+    }
+
+    /* clear sleep-on-exit bit to avoid sleeping on exception return to thread level */
+    SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
+
+    __DSB(); /* bus sync before re-enabling interrupts */
+
+    ADI_EXIT_CRITICAL_REGION();
+}
+
+
+/**
+ * Function to enable/disable clock gating for the available clocks.
+ * PCLK overrides all the other clocks.
+ */
+void set_clock_gating(peripheral_clk_t eClk, int enable)
+{
+    uint32_t flag;
+
+    switch (eClk) {
+        case PCLK:
+            flag = 1 << BITP_CLKG_CLK_CTL5_PERCLKOFF;
+            break;
+        case GPT0_CLOCK:
+            flag = 1 << BITP_CLKG_CLK_CTL5_GPTCLK0OFF;
+            break;
+        case GPT1_CLOCK:
+            flag = 1 << BITP_CLKG_CLK_CTL5_GPTCLK1OFF;
+            break;
+        case GPT2_CLOCK:
+            flag = 1 << BITP_CLKG_CLK_CTL5_GPTCLK2OFF;
+            break;
+        case I2C_CLOCK:
+            flag = 1 << BITP_CLKG_CLK_CTL5_UCLKI2COFF;
+            break;
+        case GPIO_CLOCK:
+            flag = 1 << BITP_CLKG_CLK_CTL5_GPIOCLKOFF;
+            break;
+        case TIMER_RGB_CLOCK:
+            flag = 1 << BITP_CLKG_CLK_CTL5_TMRRGBCLKOFF;
+            break;
+        default:
+            return;
+    }
+
+    // if enable, set the bit otherwise clear the bit
+    if (enable) {
+        pADI_CLKG0_CLK->CTL5 |= flag;
+    } else {
+        pADI_CLKG0_CLK->CTL5 &= (~flag);
+    }
+}
+
+
+
+/** Send the microcontroller to sleep
+ *
+ * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
+ * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
+ * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
+ * memory state are maintained, and the peripherals continue to work and can generate interrupts.
+ *
+ * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
+ *
+ * @note
+ * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ *
+ * This mode puts the processor into FLEXI mode however the peripheral clocks are not gated
+ * hence they are still active.
+ */
+void hal_sleep(void)
+{
+    // set to go into the FLEXI mode where the processor is asleep and all peripherals are
+    // still active
+    go_into_WFI(ADI_PWR_MODE_FLEXI);
+}
+
+
+/** Send the microcontroller to deep sleep
+ *
+ * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
+ * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
+ * is still maintained.
+ *
+ * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
+ *
+ * @note
+ *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ *
+ * This mode puts the processor into FLEXI mode and all the peripheral clocks are clock gated
+ * hence they are inactive until interrupts are generated in which case the processor is awaken
+ * from sleep.
+ */
+void hal_deepsleep(void)
+{
+    // set clock gating to all the peripheral clocks
+    set_clock_gating(PCLK, 1);
+
+    // set to go into the FLEXI mode with peripheral clocks gated.
+    go_into_WFI(ADI_PWR_MODE_FLEXI);
+
+    // when exiting, clear all peripheral clock gating bits. This is done to enable clocks that aren't
+    // automatically re-enabled out of sleep such as the GPIO clock.
+    pADI_CLKG0_CLK->CTL5 = 0;
+}
+
+#endif  // #ifdef DEVICE_SLEEP
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.h
new file mode 100755
index 00000000000..5ba806dbee5
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.h
@@ -0,0 +1,69 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#ifndef __SLEEP__H__
+#define __SLEEP__H__
+
+
+/* Enumeration to specify peripheral clock types:
+   General purpose timer clocks 0-2,
+   I2C clock,
+   GPIO clock,
+   RGB timer clock.
+   Peripheral clock (PCLK) controls all the peripheral clocks, including
+   all the clocks mentioned previously
+*/
+typedef enum {
+    GPT0_CLOCK = 0,
+    GPT1_CLOCK,
+    GPT2_CLOCK,
+    I2C_CLOCK,
+    GPIO_CLOCK,
+    TIMER_RGB_CLOCK,
+    PCLK
+} peripheral_clk_t;
+
+
+/* Function to enable/disable clock gating for the available clocks.
+   PCLK overrides all the other clocks.
+*/
+void set_clock_gating(peripheral_clk_t eClk, int enable);
+
+#endif  // #ifndef __SLEEP_H__
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c
new file mode 100755
index 00000000000..a52406889b9
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c
@@ -0,0 +1,341 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include <math.h>
+#include "mbed_assert.h"
+
+#include <adi_types.h>
+
+#include "spi_api.h"
+
+#if DEVICE_SPI
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+#include "drivers/spi/adi_spi.h"
+
+
+
+#if defined(BUILD_SPI_MI_DYNAMIC)
+#if defined(ADI_DEBUG)
+#warning "BUILD_SPI_MI_DYNAMIC is defined.  Memory allocation for SPI will be dynamic"
+int adi_spi_memtype = 0;
+#endif
+#else
+ADI_SPI_HANDLE      spi_Handle0;
+uint8_t             spi_Mem0[ADI_SPI_MEMORY_SIZE];
+ADI_SPI_HANDLE      spi_Handle1;
+uint8_t             spi_Mem1[ADI_SPI_MEMORY_SIZE];
+ADI_SPI_HANDLE      spi_Handle2;
+uint8_t             spi_Mem2[ADI_SPI_MEMORY_SIZE];
+#if defined(ADI_DEBUG)
+#warning "BUILD_SPI_MI_DYNAMIC is NOT defined.  Memory allocation for SPI will be static"
+int adi_spi_memtype = 1;
+#endif
+#endif
+
+
+
+/** Initialize the SPI peripheral
+ *
+ * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
+ * @param[out] obj  The SPI object to initialize
+ * @param[in]  mosi The pin to use for MOSI
+ * @param[in]  miso The pin to use for MISO
+ * @param[in]  sclk The pin to use for SCLK
+ * @param[in]  ssel The pin to use for SSEL
+ */
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
+    // determine the SPI to use
+    uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
+    uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+    uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
+    uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
+    ADI_SPI_HANDLE      *pSPI_Handle;
+    uint8_t             *SPI_Mem;
+    ADI_SPI_RESULT      SPI_Return = ADI_SPI_SUCCESS;
+    uint32_t            nDeviceNum = 0;
+    ADI_SPI_CHIP_SELECT spi_cs = ADI_SPI_CS_NONE;
+
+
+#if defined(BUILD_SPI_MI_DYNAMIC)
+    if (mosi == SPI0_MOSI) {
+        nDeviceNum = SPI_0;
+    } else if (mosi == SPI1_MOSI) {
+        nDeviceNum = SPI_1;
+    } else if (mosi == SPI2_MOSI) {
+        nDeviceNum = SPI_2;
+    }
+    pSPI_Handle = &obj->SPI_Handle;
+    obj->pSPI_Handle = pSPI_Handle;
+    SPI_Mem = obj->SPI_Mem;
+#else
+    if (mosi == SPI0_MOSI) {
+        nDeviceNum = SPI_0;
+        pSPI_Handle = &spi_Handle0;
+        SPI_Mem = &spi_Mem0[0];
+    } else if (mosi == SPI1_MOSI) {
+        nDeviceNum = SPI_1;
+        pSPI_Handle = &spi_Handle1;
+        SPI_Mem = &spi_Mem1[0];
+    } else if (mosi == SPI2_MOSI) {
+        nDeviceNum = SPI_2;
+        pSPI_Handle = &spi_Handle2;
+        SPI_Mem = &spi_Mem2[0];
+    }
+    obj->pSPI_Handle    = pSPI_Handle;
+#endif
+
+
+    obj->instance = pinmap_merge(spi_data, spi_cntl);
+    MBED_ASSERT((int)obj->instance != NC);
+
+    // pin out the spi pins
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+    if (ssel != NC) {
+        pinmap_pinout(ssel, PinMap_SPI_SSEL);
+    }
+
+    SystemCoreClockUpdate();
+    SPI_Return = adi_spi_Open(nDeviceNum, SPI_Mem, ADI_SPI_MEMORY_SIZE, pSPI_Handle);
+    if (SPI_Return) {
+        obj->error = SPI_EVENT_ERROR;
+        return;
+    }
+
+    if (ssel != NC) {
+        if ( (ssel == SPI0_CS0) || (ssel == SPI1_CS0) || (ssel == SPI2_CS0)) {
+            spi_cs = ADI_SPI_CS0;
+        } else if ( (ssel == SPI0_CS1) || (ssel == SPI1_CS1) || (ssel == SPI2_CS1)) {
+            spi_cs = ADI_SPI_CS1;
+        } else if ( (ssel == SPI0_CS2) || (ssel == SPI1_CS2) || (ssel == SPI2_CS2)) {
+            spi_cs = ADI_SPI_CS2;
+        } else if ( (ssel == SPI0_CS3) || (ssel == SPI1_CS3) || (ssel == SPI2_CS3)) {
+            spi_cs = ADI_SPI_CS3;
+        }
+
+        SPI_Return = adi_spi_SetChipSelect(*pSPI_Handle, spi_cs);
+        if (SPI_Return) {
+            obj->error = SPI_EVENT_ERROR;
+            return;
+        }
+    }
+}
+
+
+/** Release a SPI object
+ *
+ * TODO: spi_free is currently unimplemented
+ * This will require reference counting at the C++ level to be safe
+ *
+ * Return the pins owned by the SPI object to their reset state
+ * Disable the SPI peripheral
+ * Disable the SPI clock
+ * @param[in] obj The SPI object to deinitialize
+ */
+void spi_free(spi_t *obj)
+{
+    ADI_SPI_HANDLE  SPI_Handle;
+    ADI_SPI_RESULT  SPI_Return = ADI_SPI_SUCCESS;
+
+    SPI_Handle = *obj->pSPI_Handle;
+    SPI_Return = adi_spi_Close(SPI_Handle);
+    if (SPI_Return) {
+        obj->error = SPI_EVENT_ERROR;
+        return;
+    }
+}
+
+
+/** Configure the SPI format
+ *
+ * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
+ * The default bit order is MSB.
+ * @param[in,out] obj   The SPI object to configure
+ * @param[in]     bits  The number of bits per frame
+ * @param[in]     mode  The SPI mode (clock polarity, phase, and shift direction)
+ * @param[in]     slave Zero for master mode or non-zero for slave mode
+ *
+ ** Configure the data transmission format
+ *
+ *  @param bits Number of bits per SPI frame (4 - 16)
+ *  @param mode Clock polarity and phase mode (0 - 3)
+ *
+ * @code
+ * mode | POL PHA
+ * -----+--------
+ *   0  |  0   0
+ *   1  |  0   1
+ *   2  |  1   0
+ *   3  |  1   1
+ * @endcode
+
+    bool          phase;
+        true  : trailing-edge
+        false : leading-edge
+
+    bool          polarity;
+        true  : CPOL=1 (idle high) polarity
+        false : CPOL=0 (idle-low) polarity
+ */
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+    ADI_SPI_HANDLE  SPI_Handle;
+    ADI_SPI_RESULT  SPI_Return = ADI_SPI_SUCCESS;
+    bool            master;
+
+    master = !((bool_t)slave);
+    SPI_Handle = *obj->pSPI_Handle;
+
+    SPI_Return = adi_spi_SetMasterMode(SPI_Handle, master);
+    if (SPI_Return) {
+        obj->error = SPI_EVENT_ERROR;
+        return;
+    }
+}
+
+
+/** Set the SPI baud rate
+ *
+ * Actual frequency may differ from the desired frequency due to available dividers and bus clock
+ * Configures the SPI peripheral's baud rate
+ * @param[in,out] obj The SPI object to configure
+ * @param[in]     hz  The baud rate in Hz
+ */
+void spi_frequency(spi_t *obj, int hz)
+{
+    ADI_SPI_HANDLE  SPI_Handle;
+    ADI_SPI_RESULT  SPI_Return = ADI_SPI_SUCCESS;
+
+    SPI_Handle = *obj->pSPI_Handle;
+    SPI_Return = adi_spi_SetBitrate(SPI_Handle, (uint32_t) hz);
+    if (SPI_Return) {
+        obj->error = SPI_EVENT_ERROR;
+        return;
+    }
+}
+
+
+/** Write a byte out in master mode and receive a value
+ *
+ * @param[in] obj   The SPI peripheral to use for sending
+ * @param[in] value The value to send
+ * @return Returns the value received during send
+ */
+int spi_master_write(spi_t *obj, int value)
+{
+    ADI_SPI_TRANSCEIVER transceive;
+    uint8_t         TxBuf;
+    uint8_t         RxBuf;
+    ADI_SPI_HANDLE  SPI_Handle;
+    ADI_SPI_RESULT  SPI_Return = ADI_SPI_SUCCESS;
+
+    TxBuf = (uint8_t)value;
+
+    transceive.pReceiver        = &RxBuf;
+    transceive.ReceiverBytes    = 1;        /* link transceive data size to the remaining count */
+    transceive.nRxIncrement     = 1;        /* auto increment buffer */
+    transceive.pTransmitter     = &TxBuf;   /* initialize data attributes */
+    transceive.TransmitterBytes = 1;        /* link transceive data size to the remaining count */
+    transceive.nTxIncrement     = 1;        /* auto increment buffer */
+
+    transceive.bDMA = false;
+    transceive.bRD_CTL = false;
+    SPI_Handle = *obj->pSPI_Handle;
+    SPI_Return = adi_spi_MasterReadWrite(SPI_Handle, &transceive);
+    if (SPI_Return) {
+        obj->error = SPI_EVENT_ERROR;
+        return 1;
+    }
+
+    return((int)RxBuf);
+}
+
+
+/** Write a block out in master mode and receive a value
+ *
+ *  The total number of bytes sent and recieved will be the maximum of
+ *  tx_length and rx_length. The bytes written will be padded with the
+ *  value 0xff.
+ *
+ * @param[in] obj        The SPI peripheral to use for sending
+ * @param[in] tx_buffer  Pointer to the byte-array of data to write to the device
+ * @param[in] tx_length  Number of bytes to write, may be zero
+ * @param[in] rx_buffer  Pointer to the byte-array of data to read from the device
+ * @param[in] rx_length  Number of bytes to read, may be zero
+ * @param[in] write_fill Default data transmitted while performing a read
+ * @returns
+ *      The number of bytes written and read from the device. This is
+ *      maximum of tx_length and rx_length.
+ */
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill)
+{
+    ADI_SPI_TRANSCEIVER transceive;
+    ADI_SPI_HANDLE  SPI_Handle;
+    ADI_SPI_RESULT  SPI_Return = ADI_SPI_SUCCESS;
+
+    transceive.pReceiver        = (uint8_t*)rx_buffer;
+    transceive.ReceiverBytes    = rx_length;            /* link transceive data size to the remaining count */
+    transceive.nRxIncrement     = 1;                    /* auto increment buffer */
+    transceive.pTransmitter     = (uint8_t*)tx_buffer;  /* initialize data attributes */
+    transceive.TransmitterBytes = tx_length;            /* link transceive data size to the remaining count */
+    transceive.nTxIncrement     = 1;                    /* auto increment buffer */
+
+    transceive.bDMA = false;
+    transceive.bRD_CTL = false;
+    SPI_Handle = *obj->pSPI_Handle;
+    SPI_Return = adi_spi_MasterReadWrite(SPI_Handle, &transceive);
+    if (SPI_Return) {
+        obj->error = SPI_EVENT_ERROR;
+        return -1;
+    }
+    else {
+        return((int)tx_length);
+    }
+}
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c
new file mode 100755
index 00000000000..cfab85645d5
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c
@@ -0,0 +1,135 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#if defined(DEVICE_TRNG)
+
+#include <stdlib.h>
+#include <adi_rng.h>
+#include <adi_pwr.h>
+#include "adi_rng_def.h"
+#include "cmsis.h"
+#include "trng_api.h"
+
+// Sampling counter values
+// Prescaler: 0 - 10
+// LenReload: 0 - 4095
+#define TRNG_CNT_VAL	4095
+#define TRNG_PRESCALER 	2
+
+/* Data buffers for Random numbers */
+static uint32_t RngDevMem[(ADI_RNG_MEMORY_SIZE + 3)/4];
+
+void trng_init(trng_t *obj)
+{
+	ADI_RNG_HANDLE RNGhDevice;
+
+	// Open the device
+    adi_rng_Open(0,RngDevMem,sizeof(RngDevMem),&RNGhDevice);
+
+    // Set sample length for the H/W RN accumulator
+    adi_rng_SetSampleLen(RNGhDevice, TRNG_PRESCALER, TRNG_CNT_VAL);
+
+	// Disable buffering - single byte generation only
+	adi_rng_EnableBuffering(RNGhDevice, false);
+
+	// Enable the TRNG
+    adi_rng_Enable(RNGhDevice, true);
+
+	// Save device handle
+	obj->RNGhDevice = RNGhDevice;
+}
+
+void trng_free(trng_t *obj)
+{
+    ADI_RNG_HANDLE RNGhDevice = obj->RNGhDevice;
+
+    adi_rng_Enable(RNGhDevice, false);
+    adi_rng_Close(RNGhDevice);
+}
+
+int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
+{
+    ADI_RNG_HANDLE RNGhDevice = obj->RNGhDevice;
+    bool bRNGRdy, bStuck;
+    uint32_t i;
+    volatile uint32_t nRandomNum;
+    ADI_RNG_RESULT result;
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)RNGhDevice;
+
+    for (i = 0; i < length; i++) {
+        // Loop until the device has data to be read
+        do {
+            result = adi_rng_GetRdyStatus(RNGhDevice, &bRNGRdy);
+            if (result != ADI_RNG_SUCCESS) {
+                return -1;
+            }
+        } while (!bRNGRdy);
+
+        // Check the STUCK bit to make sure the oscillator output isn't stuck
+        result = adi_rng_GetStuckStatus(RNGhDevice, &bStuck);
+
+        // If the stuck bit is set, this means there may be a problem with RNG hardware,
+        // exit with an error
+        if ( (result != ADI_RNG_SUCCESS) || ((result == ADI_RNG_SUCCESS) && (bStuck)) ) {
+            // Clear the STUCK bit by writing a 1 to it
+            pDevice->pRNG->STAT |= BITM_RNG_STAT_STUCK;
+            return -1;
+        }
+
+        // Read the RNG
+        result = adi_rng_GetRngData(RNGhDevice, (uint32_t*)(&nRandomNum));
+
+        if (result != ADI_RNG_SUCCESS) {
+            return -1;
+        }
+
+        // Save the output
+		output[i] = (uint8_t)(nRandomNum & 0xFF);
+    }
+
+    *output_length = length;
+
+    // Clear nRandomNum on the stack before exiting
+    nRandomNum = 0;
+
+    return 0;
+}
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/us_ticker.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/us_ticker.c
new file mode 100755
index 00000000000..29c53a47169
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/us_ticker.c
@@ -0,0 +1,346 @@
+/*******************************************************************************
+ * Copyright (c) 2010-2017 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *   - Redistributions of source code must retain the above copyright notice,
+ *     this list of conditions and the following disclaimer.
+ *   - Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *   - Modified versions of the software must be conspicuously marked as such.
+ *   - This software is licensed solely and exclusively for use with processors
+ *     manufactured by or for Analog Devices, Inc.
+ *   - This software may not be combined or merged with other code in any manner
+ *     that would cause the software to become subject to terms and conditions
+ *     which differ from those listed here.
+ *   - Neither the name of Analog Devices, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *   - The use of this software may or may not infringe the patent rights of one
+ *     or more patent holders.  This license does not release you from the
+ *     requirement that you obtain separate licenses from these patent holders
+ *     to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+ * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+ * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+#include <stdint.h>
+#include <stdio.h>
+#include <drivers/tmr/adi_tmr.h>
+#include <drivers/pwr/adi_pwr.h>
+#include <drivers/gpio/adi_gpio.h>
+
+#ifndef BITM_TMR_RGB_CTL_EN
+#define BITM_TMR_RGB_CTL_EN BITM_TMR_CTL_EN
+#endif
+
+typedef uint32_t timestamp_t;
+
+// defined in mbed_us_ticker_api.c which calls the ticker_irq_handler() routine
+// defined in mbed_ticker_api.c
+void us_ticker_irq_handler(void);
+
+static int us_ticker_inited = 0;
+
+static ADI_TMR_CONFIG tmrConfig, tmr2Config;
+
+static volatile uint32_t Upper_count = 0, largecnt = 0;
+
+static ADI_TMR_TypeDef * adi_tmr_registers[ADI_TMR_DEVICE_NUM] = {pADI_TMR0, pADI_TMR1, pADI_TMR2};
+
+#if defined(__ADUCM302x__)
+static const IRQn_Type adi_tmr_interrupt[ADI_TMR_DEVICE_NUM] = {TMR0_EVT_IRQn, TMR1_EVT_IRQn, TMR2_EVT_IRQn};
+#elif defined(__ADUCM4x50__)
+static const IRQn_Type adi_tmr_interrupt[ADI_TMR_DEVICE_NUM] = {TMR0_EVT_IRQn, TMR1_EVT_IRQn, TMR2_EVT_IRQn, TMR_RGB_EVT_IRQn};
+#else
+#error TMR is not ported for this processor
+#endif
+
+
+/*---------------------------------------------------------------------------*
+   Local functions
+ *---------------------------------------------------------------------------*/
+static void GP1CallbackFunction(void *pCBParam, uint32_t Event, void  * pArg)
+{
+    Upper_count++;
+}
+
+
+static uint32_t get_current_time(void)
+{
+    uint16_t tmrcnt0, tmrcnt1;
+    uint32_t totaltmr0, totaltmr1;
+    uint32_t uc1, tmrpend0, tmrpend1;
+
+    do {
+        volatile uint32_t *ucptr = &Upper_count;
+
+        /*
+         * Carefully coded to prevent race conditions.  Do not make changes unless you understand all the
+         * implications.
+         *
+         * Note this function can be called with interrupts globally disabled or enabled.  It has been coded to work in both cases.
+         *
+         * TMR0 and TMR1 both run from the same synchronous clock. TMR0 runs at 26MHz and TMR1 runs at 26/256MHz.
+         * TMR1 generates an interrupt every time it overflows its 16 bit counter.  TMR0 runs faster and provides
+         * the lowest 8 bits of the current time count.  When TMR0 and TMR1 are combined, they provide 24 bits of
+         * timer precision. i.e. (TMR0.CURCNT & 0xff) + (TMR1.CURCNT << 8)
+         *
+         * There are several race conditions protected against:
+         * 1. TMR0 and TMR1 are both read at the same time, however, on rare occasions, one will have incremented before the other.
+         * Therefore we read both timer counters, and check if the middle 8 bits match, if they don't then read the counts again
+         * until they do.  This ensures that one or the other counters are stable with respect to each other.
+         *
+         * 2. TMR1.CURCNT and Upper_count racing. Prevent this by disabling the TMR1 interrupt, which stops Upper_count increment interrupt (GP1CallbackFunction).
+         * Then check pending bit of TMR1 to see if we missed Upper_count interrupt, and add it manually later.
+         *
+         * 3. Race between the TMR1 pend, and the TMR1.CURCNT read.  Even with TMR1 interrupt disabled, the pend bit
+         * may be set while TMR1.CURCNT is being read.  We don't know if the pend bit matches the TMR1 state.
+         * To prevent this, the pending bit is read twice, and we see if it matches; if it doesn't, loop around again.
+         *
+         * Note the TMR1 interrupt is enabled on each iteration of the loop to flush out any pending TMR1 interrupt,
+         * thereby clearing any TMR1 pend's.  This have no effect if this routine is called with interrupts globally disabled.
+         */
+
+        NVIC_DisableIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]);		// Prevent Upper_count increment
+        tmrpend0 = NVIC_GetPendingIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]);
+        // Check if there is a pending interrupt for timer 1
+
+        __DMB();                                                    // memory barrier: read GP0 before GP1
+
+        tmrcnt0 = adi_tmr_registers[ADI_TMR_DEVICE_GP0]->CURCNT;    // to minimize skew, read both timers manually
+
+        __DMB();                                                    // memory barrier: read GP0 before GP1
+
+        tmrcnt1 = adi_tmr_registers[ADI_TMR_DEVICE_GP1]->CURCNT;    // read both timers manually
+
+        totaltmr0 = tmrcnt0;        								// expand to u32 bits
+        totaltmr1 = tmrcnt1;        								// expand to u32 bits
+
+        tmrcnt0 &= 0xff00u;
+        tmrcnt1 <<= 8;
+
+        __DMB();
+
+        uc1 = *ucptr;												// Read Upper_count
+
+        tmrpend1 = NVIC_GetPendingIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]);
+        // Check for a pending interrupt again.  Only leave loop if they match
+
+        NVIC_EnableIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]);		// enable interrupt on every loop to allow TMR1 interrupt to run
+    } while ((tmrcnt0 != tmrcnt1) || (tmrpend0 != tmrpend1));
+
+    totaltmr1 <<= 8;                 // Timer1 runs 256x slower
+    totaltmr1 += totaltmr0 & 0xffu;  // Use last 8 bits of Timer0 as it runs faster
+    // totaltmr1 now contain 24 bits of significance
+
+    if (tmrpend0) {					 // If an interrupt is pending, then increment local copy of upper count
+        uc1++;
+    }
+
+    uint64_t Uc = totaltmr1;         // expand out to 64 bits unsigned
+    Uc += ((uint64_t) uc1) << 24;    // Add on the upper count to get the full precision count
+
+    // Divide Uc by 26 (26MHz converted to 1MHz) todo scale for other clock freqs
+
+    Uc *= 1290555u;                  // Divide total(1/26) << 25
+    Uc >>= 25;						 // shift back.  Fixed point avoid use of floating point divide.
+    // Compiler does this inline using shifts and adds.
+
+    return Uc;
+}
+
+
+static void calc_event_counts(uint32_t timestamp)
+{
+    uint32_t calc_time, blocks, offset;
+    uint64_t aa;
+
+    calc_time = get_current_time();
+    offset = timestamp - calc_time; // offset in useconds
+
+    if (offset > 0xf0000000u)       // if offset is a really big number, assume that timer has already expired (i.e. negative)
+        offset = 0u;
+
+    if (offset > 10u) {             // it takes 10us to user timer routine after interrupt.  Offset timer to account for that.
+        offset -= 10u;
+    } else
+        offset = 0u;
+
+    aa = (uint64_t) offset;
+    aa *= 26u;                      // convert from 1MHz to 26MHz clock. todo scale for other clock freqs
+
+    blocks = aa >> 7;
+    blocks++;                       // round
+
+    largecnt = blocks>>1;           // communicate to event_timer() routine
+}
+
+static void event_timer()
+{
+    if (largecnt) {
+        uint32_t cnt = largecnt;
+
+        if (cnt > 65535u) {
+            cnt = 0u;
+        } else
+            cnt = 65536u - cnt;
+
+        tmr2Config.nLoad        = cnt;
+        tmr2Config.nAsyncLoad   = cnt;
+        adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP2, tmr2Config);
+        adi_tmr_Enable(ADI_TMR_DEVICE_GP2, true);
+    } else {
+        us_ticker_irq_handler();
+    }
+}
+
+
+/*
+ * Interrupt routine for timer 2
+ *
+ * largecnt counts how many timer ticks should be counted to reach timer event.
+ * Each interrupt happens every 65536 timer ticks, unless there are less than 65536 ticks to count.
+ * In that case do the remaining timers ticks.
+ *
+ * largecnt is a global that is used to communicate between event_timer and the interrupt routine
+ * On entry, largecnt will be any value larger than 0.
+ */
+static void GP2CallbackFunction(void *pCBParam, uint32_t Event, void  * pArg)
+{
+    if (largecnt >= 65536u) {
+        largecnt -= 65536u;
+    } else
+        largecnt = 0;
+
+    if (largecnt < 65536u) {
+        adi_tmr_Enable(ADI_TMR_DEVICE_GP2, false);
+        event_timer();
+    }
+}
+
+
+/*---------------------------------------------------------------------------*
+   us_ticker HAL APIs
+ *---------------------------------------------------------------------------*/
+void us_ticker_init(void)
+{
+    if (us_ticker_inited) {
+        return;
+    }
+
+    us_ticker_inited = 1;
+
+    /*--------------------- GP TIMER INITIALIZATION --------------------------*/
+
+    /* Set up GP0 callback function */
+    adi_tmr_Init(ADI_TMR_DEVICE_GP0, NULL, NULL, false);
+
+    /* Set up GP1 callback function */
+    adi_tmr_Init(ADI_TMR_DEVICE_GP1, GP1CallbackFunction, NULL, true);
+
+    /* Set up GP1 callback function */
+    adi_tmr_Init(ADI_TMR_DEVICE_GP2, GP2CallbackFunction, NULL, true);
+
+    /* Configure GP0 to run at 26MHz */
+    tmrConfig.bCountingUp  = true;
+    tmrConfig.bPeriodic    = true;
+    tmrConfig.ePrescaler   = ADI_TMR_PRESCALER_1;     // TMR0 at 26MHz
+    tmrConfig.eClockSource = ADI_TMR_CLOCK_PCLK;      // TMR source is PCLK (most examples use HFOSC)
+    tmrConfig.nLoad        = 0;
+    tmrConfig.nAsyncLoad   = 0;
+    tmrConfig.bReloading   = false;
+    tmrConfig.bSyncBypass  = true;                    // Allow x1 prescale: requires PCLK as a clk
+    adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP0, tmrConfig);
+
+    /* Configure GP1 to have a period 256 times longer than GP0 */
+    tmrConfig.nLoad        = 0;
+    tmrConfig.nAsyncLoad   = 0;
+    tmrConfig.ePrescaler   = ADI_TMR_PRESCALER_256;    // TMR1 = 26MHz/256
+    adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP1, tmrConfig);
+
+    /* Configure GP2 for doing event counts */
+    tmr2Config.bCountingUp  = true;
+    tmr2Config.bPeriodic    = true;
+    tmr2Config.ePrescaler   = ADI_TMR_PRESCALER_256;   // TMR2 at 26MHz/256
+    tmr2Config.eClockSource = ADI_TMR_CLOCK_PCLK;      // TMR source is PCLK (most examples use HFOSC)
+    tmr2Config.nLoad        = 0;
+    tmr2Config.nAsyncLoad   = 0;
+    tmr2Config.bReloading   = false;
+    tmr2Config.bSyncBypass  = true;                    // Allow x1 prescale
+    adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP2, tmr2Config);
+
+
+    /*------------------------- GP TIMER ENABLE ------------------------------*/
+
+    /* Manually enable both timers to get them started at the same time
+     *
+     */
+    adi_tmr_registers[ADI_TMR_DEVICE_GP0]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_EN;
+    adi_tmr_registers[ADI_TMR_DEVICE_GP1]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_EN;
+}
+
+uint32_t us_ticker_read()
+{
+    uint32_t curr_time;
+
+    if (!us_ticker_inited) {
+        us_ticker_init();
+    }
+
+    curr_time = get_current_time();
+
+    return curr_time;
+}
+
+void us_ticker_disable_interrupt(void)
+{
+    adi_tmr_Enable(ADI_TMR_DEVICE_GP2, false);
+}
+
+void us_ticker_clear_interrupt(void)
+{
+    NVIC_ClearPendingIRQ(TMR2_EVT_IRQn);
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+
+    /* timestamp is when interrupt should fire.
+     *
+     * This MUST not be called if another timer event is currently enabled.
+     *
+     */
+    calc_event_counts(timestamp);             // use timestamp to calculate largecnt to control number of timer interrupts
+    event_timer();							  // uses largecnt to initiate timer interrupts
+}
+
+/** Set pending interrupt that should be fired right away.
+ *
+ * The ticker should be initialized prior calling this function.
+ *
+ * This MUST not be called if another timer event is currently enabled.
+ */
+void us_ticker_fire_interrupt(void)
+{
+    NVIC_SetPendingIRQ(TMR2_EVT_IRQn);
+}
+
+
+/*
+** EOF
+*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050.h
new file mode 100755
index 00000000000..39158f2f9cf
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050.h
@@ -0,0 +1,26 @@
+/*
+** ADuCM4050.h
+**
+** Copyright (C) 2016 Analog Devices, Inc. All Rights Reserved.
+**
+*/
+
+#ifndef ADUCM4050_H
+#define ADUCM4050_H
+
+#include <ADuCM4050_cdef.h>
+#include <ADuCM4050_device.h>
+
+#define __CM4_REV              0x0001U /*!< CM4 Core Revision r0p1                */
+#define __MPU_PRESENT          1u      /*!< MPU present                           */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT          1u      /*!< FPU present                           */
+#endif
+#define __NVIC_PRIO_BITS       3u      /*!< Number of Bits for Priority Levels    */
+#define __Vendor_SysTickConfig 0       /*!< 1 if different SysTick Config is used */
+
+#include <core_cm4.h>
+
+#include "system_ADuCM4050.h"
+
+#endif /* ADUCM4050_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_cdef.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_cdef.h
new file mode 100755
index 00000000000..8b6f35d28cf
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_cdef.h
@@ -0,0 +1,18 @@
+/*
+** ADuCM4050_cdef.h
+**
+** Copyright (C) 2016 Analog Devices, Inc. All Rights Reserved.
+**
+*/
+
+#ifndef _WRAP_ADUCM4050_CDEF_H
+#define _WRAP_ADUCM4050_CDEF_H
+
+#include <ADuCM4050_def.h>
+
+#include <stdint.h>
+
+#include <sys/adi_cio_macros.h>
+#include <sys/adi_ADuCM4050_cdef.h>
+
+#endif /* _WRAP_ADUCM4050_CDEF_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_def.h
new file mode 100755
index 00000000000..222e865aa41
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_def.h
@@ -0,0 +1,34 @@
+/*
+** ADuCM4050_def.h
+**
+** Copyright (C) 2016-2017 Analog Devices, Inc. All Rights Reserved.
+**
+*/
+
+#ifndef _WRAP_ADUCM4050_DEF_H
+#define _WRAP_ADUCM4050_DEF_H
+
+#ifdef __ICCARM__
+/* IAR MISRA C 2004 error suppressions:
+ *
+ * Pm008 (rule 2.4): sections of code should not be 'commented out'.
+ *   Some comments are wrongly identified as code.
+ *
+ * Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters.
+ *   The YODA-generated headers rely on more. The IAR compiler supports that.
+ */
+_Pragma("diag_suppress=Pm008,Pm009")
+#endif /* __ICCARM__ */
+
+#ifdef __IASMARM__
+/* Define masks to plain numeric literal for IAR assembler. */
+#define _ADI_MSK_3( mask, smask, type ) (mask)
+#endif /* __IASMARM__ */
+
+#include <sys/adi_ADuCM4050.h>
+
+#ifdef __ICCARM__
+_Pragma("diag_default=Pm008,Pm009")
+#endif /* __ICCARM__ */
+
+#endif /* _WRAP_ADUCM4050_DEF_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_device.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_device.h
new file mode 100755
index 00000000000..28b096bfc03
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_device.h
@@ -0,0 +1,29 @@
+/*
+** ADuCM4050_device.h
+**
+** Copyright (C) 2016 Analog Devices, Inc. All Rights Reserved.
+**
+*/
+
+#ifndef _WRAP_ADUCM4050_DEVICE_H
+#define _WRAP_ADUCM4050_DEVICE_H
+
+#include <ADuCM4050_typedefs.h>
+#include <sys/adi_cio_macros.h>
+
+#ifdef __ICCARM__
+/* IAR MISRA C 2004 error suppressions:
+ *
+ * Pm093 (rule 18.4): use of union - overlapping storage shall not be used.
+ *    Unions are required by sys/adi_ADuCM4050_device.h.
+ */
+_Pragma("diag_suppress=Pm093")
+#endif /* __ICCARM__ */
+
+#include <sys/adi_ADuCM4050_device.h>
+
+#ifdef __ICCARM__
+_Pragma("diag_default=Pm093")
+#endif /* __ICCARM__ */
+
+#endif /* _WRAP_ADUCM4050_DEVICE_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_typedefs.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_typedefs.h
new file mode 100755
index 00000000000..6354190e978
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_typedefs.h
@@ -0,0 +1,31 @@
+/*
+** ADuCM4050_typedefs.h
+**
+** Copyright (C) 2016 Analog Devices, Inc. All Rights Reserved.
+**
+*/
+
+#ifndef _WRAP_ADUCM4050_TYPEDEFS_H
+#define _WRAP_ADUCM4050_TYPEDEFS_H
+
+#include <stdint.h>
+
+#ifdef __ICCARM__
+/* IAR MISRA C 2004 error suppressions:
+ *
+ * Pm008 (rule 2.4): sections of code should not be 'commented out'.
+ *   Some comments are wrongly identified as code.
+ *
+ * Pm093 (rule 18.4): use of union - overlapping storage shall not be used.
+ *    Unions are required by sys/adi_ADuCM4050_typedefs.h.
+ */
+_Pragma("diag_suppress=Pm008,Pm093")
+#endif /* __ICCARM__ */
+
+#include <sys/adi_ADuCM4050_typedefs.h>
+
+#ifdef __ICCARM__
+_Pragma("diag_default=Pm008,Pm093")
+#endif /* __ICCARM__ */
+
+#endif /* _WRAP_ADUCM4050_TYPEDEFS_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc.c
new file mode 100755
index 00000000000..ea473df8ded
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc.c
@@ -0,0 +1,2371 @@
+/*! *****************************************************************************
+ * @file:    adi_adc.c
+ * @brief:   ADC device driver global file.
+ * @details: This file contain the ADC device driver implementation.
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+/** @addtogroup  ADC_Driver ADC Driver
+ *  @{
+ *  @brief ADC Driver
+ *  @details The ADC driver manages all instances of the ADC peripheral.
+ *  @note - The application must include drivers/adc/adi_adc.h to use this driver.
+ *  @note - This driver also requires the DMA driver.  The application must include
+            the DMA driver sources to avoid link errors.    
+ */
+
+#ifndef ADI_ADC_C
+/*! \cond PRIVATE */
+#define ADI_ADC_C
+
+/*=============  I N C L U D E S   =============*/
+
+
+/* Header file with definitions specific to ADC driver implementation */
+
+/*=============  A D C    I M P L E M E N T A T I O N    S O U R C E    F I L E S  =============*/
+#include <drivers/adc/adi_adc.h>
+#include <adi_processor.h>
+#include <assert.h>
+#include <string.h>
+#include <drivers/pwr/adi_pwr.h>
+#include <adi_adc_config.h>
+#include <rtos_map/adi_rtos_map.h>
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
+*   This isn't a header as such.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+*
+* Pm050 (rule 14.2): a null statement shall only occur on a line by itself
+*   Needed for null expansion of ADI_INSTALL_HANDLER and others.
+*
+* Pm088 (rule 17.4): pointer arithmetic should not be used.
+*   Relying on pointer arithmetic for buffer handling.
+*
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   The rule makes an exception for memory-mapped register accesses.
+*
+* Pm152: (MISRA C 2004 rule 17.4) array indexing shall only be applied to objects defined as an array type
+*   Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors
+
+*/
+#pragma diag_suppress=Pm123,Pm073,Pm143,Pm050,Pm088,Pm140,Pm152
+#endif /* __ICCARM__ */
+
+#include "adi_adc_def.h"
+#include "adi_adc_data.c"
+
+/*==============  D E F I N E S  ===============*/
+#ifdef ADI_DEBUG
+#define ADI_ADC_INVALID_HANDLE(h)   (AdcDevInfo[0].hDevice != (h))
+#endif
+
+/* Specify the maximum acquisition time, based on the width of the SAMPTIME field. */
+#define ADI_MAX_ACQUISITION_TIME (((uint32_t)BITM_ADC_CNV_TIME_SAMPTIME << BITP_ADC_CNV_TIME_SAMPTIME) + 1u)
+
+/* The 12bit maximum sample value */
+#define ADI_ADC_SAMPLE_MAX ((uint16_t)(4095u))
+
+/*=============  C O D E  =============*/
+
+/*=============  D E B U G    F U N C T I O N    P R O T O T Y P E S  =============*/
+
+/* Override "weak" default binding in startup_*.c */
+/*! \cond PRIVATE */
+extern void ADC0_Int_Handler(void);
+extern void DMA_ADC0_Int_Handler (void);
+                                  
+/*! \endcond */
+
+/* Prototypes for static functions (required by MISRA-C:2004 Rule 8.1)  */
+/*=============  L O C A L   F U N C T I O N S   P R O T O T Y P E S =============*/
+static uint16_t ReadOutReg(uint32_t nChannelNum);
+
+/* ADC management functions, based on transfer method */
+#if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1
+static ADI_ADC_RESULT DmaFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode);
+#else
+static ADI_ADC_RESULT InterruptFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode);
+#endif
+
+/* Channel helper functions */
+static uint32_t GetNumChannels(uint32_t nChannels);
+static int32_t  nGetChannelNumber(ADI_ADC_CHANNEL eChannel);
+
+/* Buffer management functions */
+static void ManageFifoCompletion(ADI_ADC_DEVICE *pDevice);
+static bool InitBufferProcessing(ADI_ADC_DEVICE *pDevice);
+static void FlushFifo(ADI_ADC_DEVICE *pDevice, uint32_t nChannels);
+
+/* Internal configuration functions */
+static void EnableComparator(ADI_ADC_DEVICE *pDevice, bool bEnable);
+static void StaticConfiguration(ADI_ADC_DEVICE *pDevice);
+
+/*! \endcond */
+
+/*=============  P U B L I C   F U N C T I O N S =============*/
+
+/**
+ * @brief    Opens an ADC device instance.
+ *
+ * @param [in]  nDeviceNum   Device number to open
+ * @param [in]  pMemory      Pointer to a #ADI_ADC_MEMORY_SIZE sized buffer to manage the device
+ *                           instance.
+ * @param [in]  nMemorySize  Size of the buffer to which "pMemory" points
+ * @param [out] phDevice     Pointer to a location where ADC device handle is to be written.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Call completed successfully
+ *           - #ADI_ADC_INVALID_DEVICE_NUM      [D] Invalid Device Number
+ *           - #ADI_ADC_INSUFFICIENT_MEMORY     [D] Memory passed is not sufficient
+ *           - #ADI_ADC_IN_USE                  [D] ADC driver was already opened
+ */
+ADI_ADC_RESULT adi_adc_Open (
+    uint32_t       nDeviceNum,
+    void           *pMemory,
+    uint32_t       nMemorySize,
+    ADI_ADC_HANDLE *phDevice)
+{
+    ADI_INT_STATUS_ALLOC();
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)pMemory;
+    
+#ifdef ADI_DEBUG
+    if (nDeviceNum > (sizeof (AdcDevInfo)/sizeof(AdcDevInfo[0])))
+    {
+        return ADI_ADC_INVALID_DEVICE_NUM;
+    }
+
+    if (nMemorySize < ADI_ADC_MEMORY_SIZE)
+    {
+        return ADI_ADC_INSUFFICIENT_MEMORY;
+    }
+
+    if (AdcDevInfo[nDeviceNum].hDevice != NULL)
+    {
+        return ADI_ADC_IN_USE;
+    }
+    
+    assert (ADI_ADC_MEMORY_SIZE >= sizeof (ADI_ADC_DEVICE));
+#endif /* ADI_DEBUG */
+    
+    memset (pMemory, 0, nMemorySize);
+    
+    ADI_ENTER_CRITICAL_REGION();
+    AdcDevInfo[nDeviceNum].hDevice = (ADI_ADC_HANDLE)pDevice;
+    pDevice->pReg = AdcDevInfo[nDeviceNum].pReg;
+    ADI_EXIT_CRITICAL_REGION();
+    
+    /* Reset the ADC */
+    pDevice->pReg->CFG = BITM_ADC_CFG_RST;
+    
+    /* Enable the IRQs */ 
+    NVIC_ClearPendingIRQ(ADC0_EVT_IRQn);
+    NVIC_EnableIRQ(ADC0_EVT_IRQn);
+    
+    /* Initialize the registers to known value */
+    pDevice->pReg->IRQ_EN =   BITM_ADC_IRQ_EN_RDY | BITM_ADC_IRQ_EN_ALERT | BITM_ADC_IRQ_EN_OVF | BITM_ADC_IRQ_EN_CALDONE | BITM_ADC_IRQ_EN_CNVDONE;
+    
+    /* Do the static configuration */
+    StaticConfiguration(pDevice);
+
+    /* Create a semaphore for buffer management */
+    SEM_CREATE(pDevice, "ADC Sem", ADI_ADC_ERR_RTOS);
+
+    /* Set the default FIFO Manage function */
+#if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1
+    pDevice->pfManageFifo = DmaFIFOManage;
+    /* Make sure the DMA controller and its SRAM based descriptors are initialized */
+    adi_dma_Init();
+#else    
+    pDevice->pfManageFifo = InterruptFIFOManage;
+#endif 
+
+    /* Return the device handle back to the application */
+    *phDevice = AdcDevInfo[nDeviceNum].hDevice;
+
+    return ADI_ADC_SUCCESS;
+}
+    
+    
+/**
+ * @brief    Close the given device instance
+ *
+ * @param [in]  hDevice  Handle to the device instance
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully closed the device
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle based to the function
+ */
+ADI_ADC_RESULT adi_adc_Close (ADI_ADC_HANDLE hDevice)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    ADI_ADC_RESULT eResult;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+#endif /* ADI_DEBUG */	
+
+    /* Power down the device */
+    if ((eResult = adi_adc_PowerUp (hDevice, false)) != ADI_ADC_SUCCESS) {
+        return eResult;
+    }
+
+      /* Disable the IRQ */
+      pDevice->pReg->IRQ_EN = 0u;
+
+      /* Clear the conversion cfg register to stop any transaction */
+      pDevice->pReg->CNV_CFG = 0u;
+
+#if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1
+      /* Close the DMA if configured */
+      NVIC_DisableIRQ(DMA0_CH24_DONE_IRQn);
+#endif /* ADI_ADC_ENABLE_MULTI_ACQUIRE == 1 */
+        
+    /* Disable the ADC interrupt */
+    NVIC_DisableIRQ(ADC0_EVT_IRQn);
+    
+    /* Destroy the semaphore */
+    SEM_DELETE(pDevice, ADI_ADC_ERR_RTOS);
+
+    /* Finally, zero the device */
+    AdcDevInfo[0].hDevice = (NULL);
+
+    return ADI_ADC_SUCCESS;
+}
+
+
+/**
+ * @brief   Power up ADC
+ *
+ * @param [in]  hDevice     Handle to the device instance
+ *
+ * @param [in]  bPowerUp    'true' to power up and 'false' to power down the ADC.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully closed the device
+ *           - #ADI_ADC_BAD_SYS_CLOCK               Unable to obtain PCLK which is needed to calculate
+ *                                                  powerup values.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the function
+ */
+ADI_ADC_RESULT adi_adc_PowerUp (ADI_ADC_HANDLE hDevice, bool bPowerUp)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    uint32_t nClock = 0u;
+    uint16_t nCount = 0u;
+    ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS;
+    
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+#endif /* ADI_DEBUG */
+
+    if (bPowerUp == true)
+    {
+        if (IS_NOT_IN_ANY_STATE(ADC_STATUS_POWERED_UP))
+        {
+            if(adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &nClock) == ADI_PWR_SUCCESS)
+            {
+              /* We need the cycles equivelent of 20us entered here, based on the PCLK
+               * clock. nClock is the frequency of the PCLK, 50000 is the equivalent frequency of 20us
+               * e.g. 26,000,000Hz, 0.00002s produces 520 cycles.*/
+              nCount =  (uint16_t)(nClock / 50000u); 
+              
+              /* Powering up ADC */
+              pDevice->pReg->CFG |= BITM_ADC_CFG_PWRUP;
+
+              /* Set ADC_PWRUP.WAIT bits for the new count */
+              pDevice->pReg->PWRUP = (uint16_t)(((uint32_t)nCount << BITP_ADC_PWRUP_WAIT) &  BITM_ADC_PWRUP_WAIT);
+              
+              SET_STATE(ADC_STATUS_POWERED_UP);
+            }
+            else
+            {
+              eResult = ADI_ADC_BAD_SYS_CLOCK;
+            }
+        }
+    }
+    else
+    {
+        if (IS_IN_STATE(ADC_STATUS_POWERED_UP))
+        {
+            /* If the ADC system is up then disable the ADC subsystem */
+            if (  IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN) )
+            {
+                eResult = adi_adc_EnableADCSubSystem (hDevice, false);
+                if (eResult != ADI_ADC_SUCCESS)
+                {
+                    return eResult;
+                }                
+            }
+            
+            /* Powering down ADC */
+            pDevice->pReg->CFG &= (uint16_t)(~(BITM_ADC_CFG_PWRUP));
+            CLR_STATE(ADC_STATUS_POWERED_UP);
+        }
+    }
+
+    return eResult;
+}
+
+            
+/**
+ * @brief   Registering a callback function
+ *
+ * @param [in]  hDevice     Handle to the device instance
+ * @param [in]  pfCallback  Function pointer to callback function. Passing a NULL pointer will
+ *                          unregister the call back function.
+ * @param [in]  pCBParam    Call back function parameter
+ *
+ * @details  This function registers a call back function. Registered function will be called when
+ *           the given computation is over. It will also be called when the digital comparitor is being
+ *           used and a limit has been broken.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS              Successfully registerd the callback
+ *           - #ADI_ADC_INVALID_SEQUENCE      [D] Callback cannot be registered when ADC is enabled for sampling.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the function
+ */            
+ADI_ADC_RESULT adi_adc_RegisterCallback (
+    ADI_ADC_HANDLE hDevice,
+    ADI_CALLBACK   pfCallback,
+    void           *pCBParam)
+{
+    ADI_INT_STATUS_ALLOC();
+    
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+
+    if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) 
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+
+#endif /* ADI_DEBUG */
+
+    ADI_ENTER_CRITICAL_REGION();
+    pDevice->pfCallback = pfCallback;
+    pDevice->pCBParam = pCBParam;
+    ADI_EXIT_CRITICAL_REGION();
+    
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Enable/Disables the ADC Subsystem
+ *
+ * @param [in]  hDevice      Handle to the device instance
+ *
+ * @param [in]  bEnable      'true' to Enable and 'false' to Disable`
+ *
+ * @details  Enables/Disables the ADC Subsystem. The ADC subsystem need to be enabled before using the ADC
+ *           for sampling the signal. The driver should check whether the ADC is ready by calling adi_adc_IsReady
+ *           API before continuing. If internal reference buffer is used as voltage reference then application
+ *           has to wait at least 3.5ms after enabling irrespective of whether adi_adc_IsReady returns ready or not.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS              Successfully enabled/disabled the ADC subsystem
+ *           - #ADI_ADC_INVALID_SEQUENCE     [D] Can only be called if the ADC is powered up, 
+ *                                               and cannot be disabled when sampling or using
+ *                                               the camparator.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the function
+ */
+ADI_ADC_RESULT adi_adc_EnableADCSubSystem (
+    ADI_ADC_HANDLE hDevice,
+    bool         bEnable)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    
+    if (IS_NOT_IN_STATE(ADC_STATUS_POWERED_UP))
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+    
+    if (bEnable == true) {
+        if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) {
+            return ADI_ADC_INVALID_SEQUENCE;
+        }
+    } else {
+        if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) {
+            return ADI_ADC_INVALID_SEQUENCE;
+        }
+    }
+#endif /* ADI_DEBUG */
+
+    if (bEnable == true)
+    {
+        pDevice->pReg->CFG |= BITM_ADC_CFG_EN;
+        SET_STATE(ADC_STATUS_SUB_SYSTEM_EN);
+    }
+    else
+    {
+        pDevice->pReg->CFG &= (uint16_t)(~BITM_ADC_CFG_EN);
+        CLR_STATE(ADC_STATUS_SUB_SYSTEM_EN | ADC_STATUS_SUB_SYSTEM_READY);
+    }
+
+    return ADI_ADC_SUCCESS;
+}
+
+                
+/**
+  * @brief    Returns whether the ADC Subsystem is ready
+  *
+  * @param [in]  hDevice      Handle to the device instance
+  *
+
+* @param [in]  pbReady      Pointer to a bool variable. The variable will be set to 'true' if the ADC is ready else 'false'
+  *
+  * @details  Returns whether the ADC is ready for sampling. This API should be called after enabling the ADC sub-system using
+  *           adi_adc_EnableADCSubSystem API. If internal reference buffer is used as voltage reference then application
+  *           has to wait at least 3.5ms after enabling irrespective of whether adi_adc_IsReady returns ready or not.
+  *
+  * @return   Status
+  *           - #ADI_ADC_SUCCESS              Successfully returned the ready status
+  *           - #ADI_ADC_INVALID_SEQUENCE     [D] Cannot be called if the subsystem is not enabled.
+  *           - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the function
+  *           - #ADI_ADC_NULL_POINTER            [D] pbReady is NULL
+  */
+               
+ADI_ADC_RESULT adi_adc_IsReady (
+    ADI_ADC_HANDLE  hDevice,
+    bool         *pbReady
+)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+
+    if (pbReady == NULL)
+    {
+        return ADI_ADC_NULL_POINTER;
+    }
+    
+    if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN))
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+#endif /* ADI_DEBUG */
+
+    if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_READY))
+    {
+        *pbReady = true;
+    }
+    else
+    {
+        *pbReady = false;
+    }
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Set the Voltage Reference source
+ *
+ * @param [in] hDevice      Handle to the device instance
+ *
+ * @param [in] eVrefSrc     Voltage Reference source to be used
+ *
+ * @details  The API can be used to select the voltage reference to be used by the ADC. This option need to be
+ *           set before enabling the ADC subsystem.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Succesfully set the Vref source
+ *           - #ADI_ADC_INVALID_PARAMETER           Vref source enum passed is invalid.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle based to the function.
+ *           - #ADI_ADC_INVALID_SEQUENCE        [D] VREF cannot be changed once the ADC subsystem is enabled.
+ */
+
+ADI_ADC_RESULT adi_adc_SetVrefSource (
+    ADI_ADC_HANDLE   hDevice,
+    ADI_ADC_VREF_SRC eVrefSrc)
+{
+    ADI_ADC_RESULT eResult  = ADI_ADC_SUCCESS;
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    
+    if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) 
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+#endif /* ADI_DEBUG */
+
+    pDevice->pReg->CFG &= (uint16_t)(~(BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL | BITM_ADC_CFG_VREFVBAT));
+
+    switch (eVrefSrc)
+    {
+    case ADI_ADC_VREF_SRC_INT_1_25_V:
+        pDevice->pReg->CFG |= BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL;
+        break;
+
+    case ADI_ADC_VREF_SRC_INT_2_50_V:
+        pDevice->pReg->CFG |= BITM_ADC_CFG_REFBUFEN;
+        break;
+        
+    case ADI_ADC_VREF_SRC_VBAT:
+        pDevice->pReg->CFG |= BITM_ADC_CFG_VREFVBAT;
+        break;        
+
+    case ADI_ADC_VREF_SRC_EXT:
+        break;
+
+    default:
+        eResult = ADI_ADC_INVALID_PARAMETER;
+        break;
+    }
+
+    return eResult;
+}
+
+
+/**
+ * @brief    Enable/Disable Current Sink
+ *
+ * @param [in] hDevice      Handle to the device instance
+ *
+ * @param [in] bEnable      'true' to Enable and 'false' to Disable current sink
+ *
+ * @details  If the volatage reference is required to sink current then this option need to be enabled.
+ *           The ADC subsystem has the capability to sink upto 50uA at Vref of 1.25V and 100uA at Vref of 2.5V
+
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully enabled sink
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API
+ */
+                
+ADI_ADC_RESULT adi_adc_SinkEnable (
+    ADI_ADC_HANDLE hDevice,
+    bool         bEnable)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+#endif /* ADI_DEBUG */
+
+    if (bEnable == true)
+    {
+        pDevice->pReg->CFG |= BITM_ADC_CFG_SINKEN;
+    }
+    else
+    {
+        pDevice->pReg->CFG &= (uint16_t)~(BITM_ADC_CFG_SINKEN);
+    }
+
+    return ADI_ADC_SUCCESS;
+}
+
+
+/**
+ * @brief    Start the ADC calibration
+ *
+ * @param [in] hDevice      Handle to the device instance
+ *
+ * @details  The call to this function initiate calibration of the ADC. The user is recommended to do calibration of the ADC after
+ *           enabling the ADC subsystem. The status of the calibration can be checked using adi_adc_IsCalibrationDone API.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully initiated calibration of ADC
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_SEQUENCE        [D] Sampling cannot be enabled if the ADC is enabled.
+ */
+ADI_ADC_RESULT  adi_adc_StartCalibration(ADI_ADC_HANDLE hDevice)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+
+    /* Calibration cannot be done when ADC is processing the buffers */
+    if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN)) 
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+        
+#endif /* ADI_DEBUG */
+
+    /* Clear the calibration done state */
+    CLR_STATE(ADC_STATUS_CALIBRATION_DONE);
+
+    /* Clear ADC_STAT.CALDONE */
+    pDevice->pReg->STAT = BITM_ADC_STAT_CALDONE;
+    
+    /* Set the state as calibration enabled. This state will be cleared when we get the
+       calibration done interrupt. */
+    SET_STATE (ADC_STATUS_CALIBRATION_EN);
+    
+    /* Start ADC calibration */
+    pDevice->pReg->CFG |= BITM_ADC_CFG_STARTCAL;
+    
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Returns the status of the calibration which was initiated.
+ *
+ * @param [in]  hDevice              Handle to the device instance
+ *
+ * @param [out] pbCalibrationDone    Pointer to the location to which the status of calibration is written.
+ *                                   'true' if the calibration started by call to  is done else 'false'
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully retrieved the status of ADC calibration.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_NULL_POINTER            [D] pbCalibrationDone is NULL
+ */
+
+ADI_ADC_RESULT adi_adc_IsCalibrationDone (
+    ADI_ADC_HANDLE hDevice,
+    bool         *pbCalibrationDone)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+
+    if (pbCalibrationDone == NULL)
+    {
+        return ADI_ADC_NULL_POINTER;
+    }
+#endif /* ADI_DEBUG */
+
+    /* The driver will check whether the driver is set to calibration done state. This state will 
+     * be set in the driver when the calibration done interrupt is received by the driver
+     */
+    if (IS_IN_STATE(ADC_STATUS_CALIBRATION_DONE))
+    {
+        *pbCalibrationDone = true;
+    }
+    else
+    {
+        *pbCalibrationDone = false;
+    }
+
+    return ADI_ADC_SUCCESS;
+}
+
+
+
+/**
+ * @brief    Set the acquisition time of ADC in ADC clock cycles
+ *
+ * @param [in]  hDevice              Handle to the device instance
+ *
+ * @param [in] nAcqTimeInAClkCycles  Acquisition time in ADC clock cycles.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully set the acquisition time of ADC
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_SEQUENCE        [D] Acquisition time cannot be set when the ADC is enabled for sampling
+ *           - #ADI_ADC_INVALID_PARAMETER       [D] nAcqTimeInAClkCycles is not in the valid range
+ */
+ADI_ADC_RESULT adi_adc_SetAcquisitionTime (
+    ADI_ADC_HANDLE hDevice,
+    uint32_t       nAcqTimeInAClkCycles
+    )
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    uint16_t nCnvTime;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+
+    if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN))
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+ 
+    /* A valid range is 1u to the width of the SAMPTIME field + 1. */
+    if ((nAcqTimeInAClkCycles == 0u) || (nAcqTimeInAClkCycles > (ADI_MAX_ACQUISITION_TIME)))
+    {
+        return ADI_ADC_INVALID_PARAMETER;
+    }
+
+#endif /* ADI_DEBUG */
+
+    /* Acquisition phase is (ADC_CNV_TIME.SAMPTIME + 1) ACLK cycles */
+    nCnvTime = pDevice->pReg->CNV_TIME;
+    nCnvTime &= (uint16_t)(~BITM_ADC_CNV_TIME_SAMPTIME);
+    nCnvTime |= (uint16_t)((nAcqTimeInAClkCycles - ((uint32_t)1u)) << BITP_ADC_CNV_TIME_SAMPTIME);
+    pDevice->pReg->CNV_TIME = nCnvTime;
+
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Set the delay time of ADC in ADC cycles for multi iteration mode.
+ *
+ * @param [in]  hDevice              Handle to the device instance
+ *
+ * @param [in] nDelayInAClkCycles    Delay time in ADC clock cycles.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully set delay time
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_PARAMETER       [D] nDelayInAClkCycles is not in the valid range
+ */
+ADI_ADC_RESULT adi_adc_SetDelayTime (
+    ADI_ADC_HANDLE hDevice,
+    uint32_t nDelayInAClkCycles)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    uint16_t nCnvTime;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+
+    if (nDelayInAClkCycles > (BITM_ADC_CNV_TIME_DLY >> BITP_ADC_CNV_TIME_DLY))
+    {
+        return ADI_ADC_INVALID_PARAMETER;
+    }
+#endif /* ADI_DEBUG */
+
+    nCnvTime = pDevice->pReg->CNV_TIME;
+    nCnvTime &= (uint16_t)(~BITM_ADC_CNV_TIME_DLY);
+    nCnvTime |= (uint16_t)(nDelayInAClkCycles << BITP_ADC_CNV_TIME_DLY);
+    pDevice->pReg->CNV_TIME = nCnvTime;
+
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Set the resolution of ADC. he default resolution of ADC is 12-bit and the ADC increases the resolution
+ *           by oversampling. Averaging will be disabled when the resolution is more than 12-bits.
+ *
+ * @param [in]  hDevice       Handle to the device instance
+ *
+ * @param [in] eResolution    Enum of ADC resolution
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully set the resolution of the ADC.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API
+ *           - #ADI_ADC_INVALID_SEQUENCE        [D] Resolution cannot be changed when the ADC is enabled for sampling
+ *           - #ADI_ADC_INVALID_STATE           [D] Resolution cannot be changed from 12-bit if averaging is enabled
+ *           - #ADI_ADC_INVALID_PARAMETER           eResolution parameter passed is invalid.
+ */
+ADI_ADC_RESULT adi_adc_SetResolution (
+    ADI_ADC_HANDLE hDevice,
+    ADI_ADC_RESOLUTION eResolution)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    uint16_t nFactor;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) 
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+    if (IS_IN_ANY_STATE(ADC_STATUS_AVGERAGING_EN) && (eResolution != ADI_ADC_RESOLUTION_12_BIT)) 
+    {
+        return ADI_ADC_INVALID_STATE;
+    }
+#endif /* ADI_DEBUG */
+
+    switch (eResolution)
+    {
+    case ADI_ADC_RESOLUTION_12_BIT:
+        pDevice->pReg->AVG_CFG &= (uint16_t)(~BITM_ADC_AVG_CFG_OS);
+        if (IS_NOT_IN_STATE(ADC_STATUS_AVGERAGING_EN)) {
+          pDevice->pReg->AVG_CFG = 0u;
+        }
+        CLR_STATE(ADC_STATUS_OVERSAMPLING_EN);
+        break;
+
+    case ADI_ADC_RESOLUTION_13_BIT:
+    case ADI_ADC_RESOLUTION_14_BIT:
+    case ADI_ADC_RESOLUTION_15_BIT:
+    case ADI_ADC_RESOLUTION_16_BIT:
+        /* factor = 0x02 for 13-bit
+                    0x08 for 14-bit
+                    0x20 for 15-bit
+                    0x80 for 16-bit */
+        nFactor = (uint16_t)1u << (((uint16_t)eResolution * 2u) - ((uint16_t)1u));
+        pDevice->pReg->AVG_CFG =  BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN
+                                | (uint16_t)(nFactor << BITP_ADC_AVG_CFG_FACTOR);
+        SET_STATE(ADC_STATUS_OVERSAMPLING_EN);
+                                
+        break;
+
+    default:
+        return ADI_ADC_INVALID_PARAMETER;
+    }
+
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Enable Averaging for all ADC channels.
+ *
+ * @param [in] hDevice            Handle to the device instance
+ *
+ * @param [in] nAveragingSamples  Specifies the number of samples used for averaging. The valid value is between 1-256, in the steps of power of 2. 1 is for disabling averaging.
+ *                                The averaging require that the resolution of ADC is 12-bit.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully enabled averaging.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API  
+ *           - #ADI_ADC_INVALID_STATE           [D] Averaging cannot be enabled if the resolution is above 12bits
+ *           - #ADI_ADC_INVALID_PARAMETER       [D] nAveragingSamples parameter passed is invalid. 
+ */
+ADI_ADC_RESULT adi_adc_EnableAveraging (
+    ADI_ADC_HANDLE hDevice,
+    uint16_t        nAveragingSamples
+    )
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    uint16_t nFactor;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+
+    if ((nAveragingSamples == 0u) || (nAveragingSamples > 256u)
+        /* Or nAveragingSamples is not a power of 2 */
+        || ((nAveragingSamples & (nAveragingSamples - 1u)) != 0u))
+    {
+        return ADI_ADC_INVALID_PARAMETER;
+    }
+    if (IS_IN_STATE(ADC_STATUS_OVERSAMPLING_EN)) 
+    {
+        return ADI_ADC_INVALID_STATE;
+    }
+#endif /* ADI_DEBUG */
+
+    /* Disable averaging */
+    if (nAveragingSamples == 1u)
+    {
+        pDevice->pReg->AVG_CFG &= (uint16_t)(~BITM_ADC_AVG_CFG_EN);
+        CLR_STATE(ADC_STATUS_AVGERAGING_EN);
+    }
+    else
+    {
+        nFactor = nAveragingSamples >> 1;
+        pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_EN | (uint16_t)(nFactor << BITP_ADC_AVG_CFG_FACTOR);
+        SET_STATE(ADC_STATUS_AVGERAGING_EN);
+    }
+
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Configure low limit for an ADC channel when it is used as a digital comparator.
+ *
+ * @param [in] hDevice              Handle to the device instance
+ *
+ * @param [in] eChannel             The ADC channel for which to configure the comparator
+ *
+ * @param [in] bEnable              Enable or disable the low limit of the digital comparator
+ *
+ * @param [in] nLowLimit            The low limit of the digital comparator. If bEnable is false, this paramter is omitted.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully configured set the low limit.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_PARAMETER       [D] Parameters passed is not valid.
+ */
+ADI_ADC_RESULT adi_adc_SetLowLimit (
+    ADI_ADC_HANDLE   hDevice,
+    ADI_ADC_CHANNEL  eChannel,
+    bool             bEnable,
+    uint16_t         nLowLimit
+    )
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    static volatile uint16_t* pRegister[4] = {
+        pREG_ADC0_LIM0_LO, pREG_ADC0_LIM1_LO, pREG_ADC0_LIM2_LO, pREG_ADC0_LIM3_LO
+    };
+    int32_t nChannelNum = 0;
+    
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if ((nLowLimit > (BITM_ADC_LIM0_LO_VALUE >> BITP_ADC_LIM0_LO_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3))
+    {
+        return ADI_ADC_INVALID_PARAMETER;
+    }
+#endif /* ADI_DEBUG */
+        
+    nChannelNum = nGetChannelNumber(eChannel);
+    
+    if((nChannelNum >= 0) && (nChannelNum <= 3)) {
+      if (bEnable == true) {
+        
+        *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_LIM0_LO_VALUE)) | 
+          (uint16_t)(nLowLimit << BITP_ADC_LIM0_LO_VALUE);
+        
+        /* Now enable this channel comparitor - unused until the comparitor is enabled */   
+        pDevice->ComparitorLo |= (1u << nChannelNum);
+      }
+      else {
+        pDevice->ComparitorLo &= ~(1u << nChannelNum);
+      }
+    }
+
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Configure high limit for an ADC channel when it's used as a digital comparator.
+ *
+ * @param [in] hDevice              Handle to the device instance
+ *
+ * @param [in] eChannel             The ADC channel for which to configure the comparator
+ *
+ * @param [in] bEnable              Enable or disable the high limit of the digital comparator
+ *
+ * @param [in] nHighLimit           The high limit of the digital comparator. If bEnable is false, this paramter is omitted.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully set the high limit
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_PARAMETER       [D] Parameters passed is not valid.
+ */
+ADI_ADC_RESULT adi_adc_SetHighLimit (
+    ADI_ADC_HANDLE   hDevice,
+    ADI_ADC_CHANNEL  eChannel,
+    bool             bEnable,
+    uint16_t         nHighLimit)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    static volatile uint16_t* pRegister[4] = {
+        pREG_ADC0_LIM0_HI, pREG_ADC0_LIM1_HI, pREG_ADC0_LIM2_HI, pREG_ADC0_LIM3_HI
+    };
+    int32_t nChannelNum = 0;
+    
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if ((nHighLimit > (BITM_ADC_LIM0_HI_VALUE >> BITP_ADC_LIM0_HI_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3))
+    {
+        return ADI_ADC_INVALID_PARAMETER;
+    }
+#endif /* ADI_DEBUG */
+        
+    nChannelNum = nGetChannelNumber(eChannel);
+    
+    if((nChannelNum >= 0) && (nChannelNum <= 3)) {
+      if (bEnable == true) {
+        /* Set the given high value - only relevant if the limit is enabled. */
+        *pRegister[nChannelNum] =    (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_LIM0_HI_VALUE))
+          | (uint16_t)(nHighLimit << BITP_ADC_LIM0_HI_VALUE);
+        
+        /* Now enable this channel comparitor - unused until the comparitor is enabled */   
+        pDevice->ComparitorHi |= (1u << nChannelNum);
+      }
+      else {
+        pDevice->ComparitorHi &= ~(1u << nChannelNum);
+      }
+    }
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Configure hysteresis for an ADC channel when it's used as a digital comparator.
+ *
+ * @param [in] hDevice              Handle to the device instance
+ *
+ * @param [in] eChannel             The ADC channel for which to configure the comparator
+ *
+ * @param [in] bEnable              Enable or disable the hysteresis of the digital comparator
+ *
+ * @param [in] nHysteresis          The hysteresis to be used. If bEnable is false, this paramter is omitted.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully configured the comparator
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_PARAMETER       [D] Parameters passed is not valid.
+ */
+ADI_ADC_RESULT adi_adc_SetHysteresis (
+    ADI_ADC_HANDLE   hDevice,
+    ADI_ADC_CHANNEL  eChannel,
+    bool             bEnable,
+    uint16_t         nHysteresis)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    static volatile uint16_t* pRegister[4] = {
+        pREG_ADC0_HYS0, pREG_ADC0_HYS1, pREG_ADC0_HYS2, pREG_ADC0_HYS3
+    };
+    int32_t nChannelNum = 0;
+    
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if ((nHysteresis > (BITM_ADC_HYS0_VALUE >> BITP_ADC_HYS0_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3))
+    {
+        return ADI_ADC_INVALID_PARAMETER;
+    }
+#endif /* ADI_DEBUG */
+        
+    nChannelNum = nGetChannelNumber(eChannel);
+    
+    if((nChannelNum >= 0) && (nChannelNum <= 3)) {
+        if (bEnable == true) {
+          *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_HYS0_VALUE))
+                                  | (uint16_t)(nHysteresis << BITP_ADC_HYS0_VALUE);
+          
+          /* Now enable this channel hysteresis - unused until the comparitor is enabled */   
+          pDevice->ComparitorHys |= (1u << nChannelNum);
+        }
+        else {
+          pDevice->ComparitorHys &= ~(1u << nChannelNum);
+        }
+    }    
+
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Configure number of monitor cycles for an ADC channel when it's used as a digital comparator.
+ *
+ * @param [in] hDevice              Handle to the device instance
+ *
+ * @param [in] eChannel             The ADC channel for which to configure the comparator
+ *
+ * @param [in] nNumMonitorCycles    Number of Monitor cycles before giving interrupt
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully configured the comparator
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_PARAMETER       [D] Parameters passed is not valid.
+ */
+ADI_ADC_RESULT adi_adc_SetNumMonitorCycles(
+    ADI_ADC_HANDLE   hDevice,
+    ADI_ADC_CHANNEL  eChannel,
+    uint32_t         nNumMonitorCycles)
+{
+ #ifdef ADI_DEBUG
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+#endif /* ADI_DEBUG */
+    
+    static volatile uint16_t* pRegister[4] = {
+        pREG_ADC0_HYS0, pREG_ADC0_HYS1, pREG_ADC0_HYS2, pREG_ADC0_HYS3
+    };
+    int32_t nChannelNum = 0;
+    
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if ((nNumMonitorCycles > (BITM_ADC_HYS0_MONCYC >> BITP_ADC_HYS0_MONCYC)) || (nChannelNum < 0) || (nChannelNum > 3))
+    {
+        return ADI_ADC_INVALID_PARAMETER;
+    }
+#endif /* ADI_DEBUG */
+    
+    nChannelNum = nGetChannelNumber(eChannel);
+      
+    if((nChannelNum >= 0) && (nChannelNum <= 3)) {
+      *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_HYS0_MONCYC))
+        | (uint16_t)(nNumMonitorCycles << BITP_ADC_HYS0_MONCYC);
+    }
+    return ADI_ADC_SUCCESS;
+}
+
+
+
+/**
+ * @brief    Enable/Disable digital comparator for the given channel(s)
+ *
+ * @param [in] hDevice              Handle to the device instance
+ *
+ * @param [in] bEnableComparator    'true' to Enable and 'false' to disable
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Successfully enabled/disabled digital comparator for the given channels
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_STATE           [D] Digital comparator cannot be enabled if sampling resolution is more than 12-bit or
+ *                                                  averaging is enabled. Comparator for a given channel cannot be enbaled if none of the limits
+ *                                                  are enabled for the given channel.
+ *           - #ADI_ADC_INVALID_SEQUENCE        [D] Comparator cannot be enabled when ADC is enabled for sampling.
+ *           - #ADI_ADC_INVALID_OPERATION       [D] Comparator require callback to be registered.
+ */
+ADI_ADC_RESULT adi_adc_EnableDigitalComparator (
+    ADI_ADC_HANDLE hDevice,
+    bool         bEnableComparator
+)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    
+    if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN)) 
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+    
+    if (IS_IN_ANY_STATE(ADC_STATUS_AVGERAGING_EN | ADC_STATUS_OVERSAMPLING_EN)) 
+    {
+        return ADI_ADC_INVALID_STATE;
+    }
+    
+    if (pDevice->pfCallback == NULL) {
+        return ADI_ADC_INVALID_OPERATION;
+    }
+    
+    if (bEnableComparator == true) {
+      if((pDevice->ComparitorHi | pDevice->ComparitorLo) == 0u) {
+        return ADI_ADC_INVALID_STATE;
+      }
+    }
+#endif /* ADI_DEBUG */
+    
+    EnableComparator(pDevice, bEnableComparator);
+    
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Submit the ADC buffer for processing to the ADC Module
+ *
+ * @param [in]  hDevice   Handle to the device instance.
+ * @param [in]  pBuffer   Pointer to the #ADI_ADC_BUFFER structure which contains details
+ *                        of the buffers required by the driver.
+ *
+ * @return  Status
+ *           - #ADI_ADC_SUCCESS                     Successfully submitted the buffer
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_NULL_POINTER            [D] pBuffer is NULL
+ *           - #ADI_ADC_INVALID_BUFFER          [D] Buffer parameters are invalid.
+ *
+ * @note    The driver will take ownership of the ADI_ADC_BUFFER structure passed to the driver.
+ *          The application has to make sure the structure is not used and it's scope is valid till
+ *          the structure is returned back to the application.
+ */
+ADI_ADC_RESULT adi_adc_SubmitBuffer (
+    ADI_ADC_HANDLE hDevice,
+    ADI_ADC_BUFFER*     pBuffer
+)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    uint32_t nNumChannels = 0u;
+
+    ADC_INT_BUFFER* pIntBuffer;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if (pBuffer == NULL) {
+        return ADI_ADC_NULL_POINTER;
+    }
+    if ((pBuffer->nChannels == 0u) || (pBuffer->pDataBuffer == NULL) || (pBuffer->nNumConversionPasses == 0u))
+    {
+        return ADI_ADC_INVALID_BUFFER;
+    }
+#endif /* ADI_DEBUG */
+
+    nNumChannels = GetNumChannels(pBuffer->nChannels);
+
+    pIntBuffer = &pDevice->s_Buffer;
+
+    pIntBuffer->nConfig = ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN;
+    pIntBuffer->nStatus = ADC_BUFFER_STATUS_OK;
+    if (pBuffer->nNumConversionPasses == 1u) 
+    {
+        pIntBuffer->nConfig |= ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN;
+    }
+    pIntBuffer->pUserBuffer = pBuffer;
+    pIntBuffer->pCurDataBuffer = pBuffer->pDataBuffer;
+    pIntBuffer->nNumSamplesRemaining = nNumChannels * pBuffer->nNumConversionPasses;
+    pIntBuffer->nChannels = pBuffer->nChannels;
+    
+    pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INIT);
+    
+    return ADI_ADC_SUCCESS;
+}
+
+/**
+ * @brief    Get a processed buffer from the ADC Driver. This function is a blocking call and will only return
+ *           once it has the buffer or if any error occurred. If a callback is registered then any call to this
+ *           function will fail.
+ *
+ * @param [in]  hDevice    Handle to the device instance.
+ * @param [out] ppBuffer   Pointer to a pointer to ADI_ADC_BUFFER structure. The returned pointer
+ *                         to ADI_ADC_BUFFER is written here.
+ *
+ * @return  Status
+ *           - #ADI_ADC_SUCCESS                     Successfully returned the buffer
+ *           - #ADI_ADC_INVALID_STATE               adi_adc_GetBuffer cannot be called when no buffer is given to the driver for processing.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_OPERATION       [D] adi_adc_GetBuffer cannot be used when callback is registered.
+ *           - #ADI_ADC_NULL_POINTER            [D] ppBuffer is NULL
+ *           - #ADI_ADC_INVALID_SEQUENCE        [D] adi_adc_GetBuffer cannot be used if non-blocking is not enabled.
+ *
+ */
+ADI_ADC_RESULT adi_adc_GetBuffer (
+    ADI_ADC_HANDLE hDevice,
+    ADI_ADC_BUFFER **ppBuffer)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    ADI_ADC_RESULT eADCresult = ADI_ADC_SUCCESS;
+    
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if (ppBuffer == NULL) {
+            return ADI_ADC_NULL_POINTER;
+    }
+    if (pDevice->pfCallback != NULL) {
+        return ADI_ADC_INVALID_OPERATION;
+    }
+    if (IS_NOT_IN_STATE(ADC_STATUS_NON_BLOCKING_EN)) {
+        return ADI_ADC_INVALID_SEQUENCE;
+    } 
+#endif /* ADI_DEBUG */
+
+    if (pDevice->s_Buffer.pUserBuffer == NULL) {
+      return ADI_ADC_INVALID_STATE;
+    }
+    
+    /* Wait for read completion */
+    SEM_PEND(pDevice, ADI_ADC_ERR_RTOS);
+    
+    if ((uint16_t)(pDevice->s_Buffer.nStatus & ADC_BUFFER_STATUS_OVERFLOW) != 0u) {
+        eADCresult =  ADI_ADC_BUFFER_OVERFLOW;
+    }
+    *ppBuffer = pDevice->s_Buffer.pUserBuffer;
+    pDevice->s_Buffer.pUserBuffer = NULL;
+    CLR_STATE(ADC_STATUS_NON_BLOCKING_EN);
+    
+    return eADCresult;
+}
+
+/**
+ * @brief   Enable/Disable ADC for sampling
+ *
+ * @param [in] hDevice    Handle to the device instance
+ *
+ * @param [in] bEnable    'true' to Enable and 'false' to disable
+ *
+ * @details
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Succesfully Enabled or disabled ADC for sampling
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_STATE           [D] Non-blocking cannot be enabled if comparator is enabled or any blocking API is in progress.
+ */
+ADI_ADC_RESULT adi_adc_Enable (
+    ADI_ADC_HANDLE hDevice,
+    bool         bEnable)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    
+    if (IS_IN_ANY_STATE(ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) {
+        return ADI_ADC_INVALID_STATE;
+    }
+#endif /* ADI_DEBUG */
+
+    if (bEnable == true) {
+        /* Set the driver to be in non-blocking mode */
+        SET_STATE(ADC_STATUS_NON_BLOCKING_EN);
+        
+        /* Enable the IRQs */
+        NVIC_EnableIRQ(ADC0_EVT_IRQn);
+   
+        /* Try to submit possible number of buffers */
+        InitBufferProcessing(pDevice);
+    } else {
+        /* Disble the IRQs */
+        NVIC_DisableIRQ(ADC0_EVT_IRQn);
+        
+        /* Abort any transaction if present */
+        pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_ABORT);
+        
+        CLR_STATE(ADC_STATUS_NON_BLOCKING_EN);
+    }
+
+    return ADI_ADC_SUCCESS;    
+}
+
+
+/**
+ * @brief    This function return whether a filled buffer is available to be returned to the user.
+ *           If this function return true, then a call to adi_adc_GetBuffer will not block
+ *
+ * @param [in]  hDevice               Handle to the device instance.
+ * @param [out] pbIsBufferAvailable   Pointer to a bool variable to which the availability of buffer will be written.
+ *                                    The variable will be set to 'true' if buffer is available else 'false'
+ *
+ * @return  Status
+ *           - #ADI_ADC_SUCCESS                     Successfully returned the status of the buffer availability
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_NULL_POINTER            [D] pbIsBufferAvailable is valid
+ *           - #ADI_ADC_INVALID_OPERATION       [D] adi_adc_IsBufferAvailable cannot be used when callback is registered.
+ *
+ */
+ADI_ADC_RESULT adi_adc_IsBufferAvailable (
+    ADI_ADC_HANDLE hDevice,
+    bool         *pbIsBufferAvailable)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if (pbIsBufferAvailable == NULL) 
+    {
+        return ADI_ADC_NULL_POINTER;
+    }
+    if (pDevice->pfCallback != NULL) {
+        return ADI_ADC_INVALID_OPERATION;
+    }
+#endif /* ADI_DEBUG */
+
+    if(IS_IN_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS))  
+    {
+        *pbIsBufferAvailable = false;
+    }
+    else
+    {
+        *pbIsBufferAvailable = true;
+    }
+
+    return ADI_ADC_SUCCESS;    
+}
+
+
+/**
+ * @brief   Sample the given channels for the given number of conversion passes and put it into the given buffer. This function only return after
+ *          the channels are sampled the given number of conversion times or if any error occurs. 
+ *
+ * @param [in] hDevice      Handle to the device instance
+ *
+ * @param [in] nChannels    Channels to sample. Should be an ORed value of ADI_ADC_CHANNEL types.
+ *
+ * @param [in] nNumConversionPasses  Number of conversion passes. In one conversion pass, the ADC will sample all the given channel(s) once.
+ *
+ * @param [in] pBuffer      Pointer to the buffer to which the sampled data is put.
+ *
+ * @param [in] nBuffLength  Length of the buffer. The length of the buffer should be at least
+ *                          2*(Num of Channels)*nNumConversionPasses bytes.
+ *
+ * @details Sample all the given channels for the given number of conversion passes and put the samples values into the given buffers. 
+ *          The channels will be sampled starting from the lower number. This function only return after
+ *          the channels are sampled the given number of conversion times or if any error occurs.
+ *
+ * @return   Status
+ *           - #ADI_ADC_SUCCESS                     Succesfully Enabled or disabled ADC for sampling
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_INVALID_PARAMETER       [D] Some parameter passed to the function is not valid
+ *           - #ADI_ADC_INVALID_SEQUENCE        [D] adi_adc_ReadChannels cannot be called if camparator is enabled or if 
+ *                                                  Non-blocking is enabled or if another blocking API is in progress.
+ */
+
+ADI_ADC_RESULT adi_adc_ReadChannels (
+    ADI_ADC_HANDLE hDevice,
+    uint32_t       nChannels,
+    uint32_t       nNumConversionPasses,
+    void           *pBuffer,
+    uint32_t       nBuffLength)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    uint32_t nNumChannels = 0u;
+    ADI_ADC_RESULT eADCresult = ADI_ADC_SUCCESS;
+
+    ADC_INT_BUFFER* pIntBuffer;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if ((nChannels == 0u) || (nNumConversionPasses == 0u) || (pBuffer == NULL)) 
+    {
+        return ADI_ADC_INVALID_PARAMETER;
+    }
+    if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) 
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+#endif /* ADI_DEBUG */
+
+    nNumChannels = GetNumChannels(nChannels);
+
+    if (nBuffLength < ((nNumChannels * sizeof(uint16_t)) * nNumConversionPasses))
+    {
+        return ADI_ADC_INSUFFICIENT_MEMORY;
+    }
+    
+    /* Clear ADC status */
+    pDevice->pReg->STAT = 0xFFFFu;
+
+    /* Set the driver to be in blocking mode */
+    SET_STATE(ADC_STATUS_BLOCKING_EN);
+
+    /* Get the buffer */
+    pIntBuffer = &pDevice->s_Buffer;    
+
+    pIntBuffer->nConfig = ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN;
+    if (nNumConversionPasses == 1u) {
+        pIntBuffer->nConfig |= ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN;
+    }
+    
+    pIntBuffer->nStatus = ADC_BUFFER_STATUS_OK;
+    pIntBuffer->pUserBuffer = NULL;
+    pIntBuffer->pCurDataBuffer = pBuffer;
+    pIntBuffer->nNumSamplesRemaining = nNumChannels * nNumConversionPasses;
+    pIntBuffer->nChannels = nChannels;
+    
+    pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INIT);
+    
+    InitBufferProcessing(pDevice);
+
+    /* Wait for read completion */
+    SEM_PEND(pDevice, ADI_ADC_ERR_RTOS);  
+    
+    if ((uint16_t)(pDevice->s_Buffer.nStatus & ADC_BUFFER_STATUS_OVERFLOW) != 0u) {
+        eADCresult =  ADI_ADC_BUFFER_OVERFLOW;
+    }
+
+    /* Driver is no longer in blocking mode */
+    CLR_STATE(ADC_STATUS_BLOCKING_EN);
+
+    /* Enable the IRQs */
+    NVIC_DisableIRQ(ADC0_EVT_IRQn);
+
+    return eADCresult;
+}
+
+
+/**
+ * @brief    Returns the battery voltage.
+ *
+ * @param [in]  hDevice        Handle to the device instance.
+ *
+ * @param [in]  nRefVoltage    Reference voltage in fixed point(16.16) format.
+ *
+ * @param [out] pnBatVoltage   Pointer to a variable to which the voltage of the battery will be written.
+ *                             The battery voltage will be in fixed point (16.16) format.
+ *
+ *
+ * @return  Status
+ *           - #ADI_ADC_SUCCESS                     Successfully retrieved the battery voltage.
+ *           - #ADI_ADC_BAD_SYS_CLOCK               Unable to obtain CLK which is needed to calculate
+ *                                                  voltage conversion timing values.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_NULL_POINTER            [D] pnBatVoltage is NULL
+ *           - #ADI_ADC_INVALID_SEQUENCE        [D] ADC sub system should be up and ADC should be free for getting the battery voltage.
+ */
+ADI_ADC_RESULT adi_adc_GetBatteryVoltage (
+    ADI_ADC_HANDLE hDevice,
+    uint32_t       nRefVoltage,
+    uint32_t       *pnBatVoltage)
+{
+    ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS;
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    uint16_t nConvTimeBackup;
+    uint16_t nAvgCfgBackup;
+    uint32_t nAdcValue = 0u;
+    uint32_t nClock = 0u;  
+    uint32_t nACLKDIVCNT;
+    
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if (pnBatVoltage == NULL) 
+    {
+        return ADI_ADC_NULL_POINTER;
+    }    
+    
+    if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+    
+    if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }    
+#endif /* ADI_DEBUG */
+
+    if(adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &nClock) == ADI_PWR_SUCCESS)
+    {
+        /* Take the backup of registers that need to be changed */
+        nConvTimeBackup = pDevice->pReg->CNV_TIME;
+        nAvgCfgBackup =  pDevice->pReg->AVG_CFG;
+        
+        /* Set the required value in the registers. */
+        nACLKDIVCNT = (*pREG_CLKG0_CLK_CTL1 & BITM_CLKG_CLK_CTL1_ACLKDIVCNT) >> BITP_CLKG_CLK_CTL1_ACLKDIVCNT;
+        
+        /* Calculate the number of cycles required for conversion. 
+         * The conversion time required is 500ns = 2000000Hz 
+         */
+        nClock = nClock/nACLKDIVCNT;  /* nClock = ACLK frequency Hz */
+        pDevice->pReg->CNV_TIME = (uint16_t)((nClock/2000000u) + ((uint16_t)1u)); 
+        pDevice->pReg->AVG_CFG = 0u;
+        
+        /* Clear the battery done status */
+        pDevice->pReg->STAT = BITM_ADC_STAT_BATDONE;
+        
+        /* Clear the battery done state */
+        CLR_STATE(ADC_STATUS_BATTERY_DONE);
+        
+        /* Set the registers */
+        pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_BAT);
+        
+        /* Wait for the Battery done status */
+        while (IS_NOT_IN_STATE(ADC_STATUS_BATTERY_DONE)) { ; }
+        
+        /* Clear the conversion register */
+        pDevice->pReg->CNV_CFG = 0u;
+        
+        /* Restore the changed registers */
+        pDevice->pReg->CNV_TIME = nConvTimeBackup;
+        pDevice->pReg->AVG_CFG = nAvgCfgBackup;
+        
+        /* Calculate the battery voltage */
+        
+        /* From HRM: converting ADC result to battery voltage, following calculations should be done: 
+         * VBAT = 4 * (adc_out) * Vref / (2^12 - 1) */
+         nAdcValue = pDevice->pReg->BAT_OUT;
+        *pnBatVoltage = (4u * nAdcValue * nRefVoltage) / ADI_ADC_SAMPLE_MAX;
+    }
+    else
+    {
+         eResult = ADI_ADC_BAD_SYS_CLOCK;
+    }
+        
+    return eResult;
+}
+/**
+ * @brief    Enable or disable the temperature sensor
+ *
+ * @param [in]  hDevice  Handle to the device instance.
+ *
+ * @param [in]  bEnable  'true' to enable and 'false' to disable the temperature sensor
+ *
+ *
+ * @return  Status
+ *           - #ADI_ADC_SUCCESS                     Successfully enabled/disabled the temperature sensor
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ */
+ADI_ADC_RESULT adi_adc_EnableTemperatureSensor (
+    ADI_ADC_HANDLE hDevice,
+    bool         bEnable)
+{
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+#endif /* ADI_DEBUG */
+
+    if (bEnable == true)
+    {
+        pDevice->pReg->CFG |= (uint16_t)BITM_ADC_CFG_TMPEN;
+        SET_STATE(ADC_STATUS_TEMP_SENSOR_EN);
+    }
+    else
+    {
+        pDevice->pReg->CFG &= (uint16_t)(~BITM_ADC_CFG_TMPEN);
+        CLR_STATE(ADC_STATUS_TEMP_SENSOR_EN);
+    }
+
+    return ADI_ADC_SUCCESS;
+}
+
+
+/**
+ * @brief    Return the temperature in fixed point format in degree Celcius.
+ *
+ * @param [in]  hDevice        Handle to the device instance.
+ *
+ * @param [in]  nRefVoltage    Reference voltage in fixed point(16.16) format.
+ *
+ * @param [out] pnTemperature  Pointer to a variable to which the ADC die temperature (in degree Celsius) will be written.
+ *                             The temperature will be in fixed point (16.16) format.
+ *
+ *
+ * @return  Status
+ *           - #ADI_ADC_SUCCESS                     Successfully retrieved the die temperature
+ *           - #ADI_ADC_BAD_SYS_CLOCK               Unable to obtain CLK which is needed to calculate
+ *                                                  temperature conversion timing values.
+ *           - #ADI_ADC_INVALID_DEVICE_HANDLE   [D] Invalid device handle passed to the API 
+ *           - #ADI_ADC_NULL_POINTER            [D] pnBatVoltage is NULL
+ *           - #ADI_ADC_INVALID_SEQUENCE        [D] ADC sub system should be up and ADC should be free for getting the battery voltage. The Temperator
+ *                                                  sensor also need to be enabled.
+ *           - #ADI_ADC_INVALID_STATE           [D] Temperature sensor require an aquisition time of 65us and that cannot be set with the current
+ *                                                  ACLK since only ACLK of 255 can be stored to the sampling register. Decrease the ACLK clock to 
+ *                                                  rectify this.
+ */
+ADI_ADC_RESULT adi_adc_GetTemperature (
+    ADI_ADC_HANDLE  hDevice,
+    uint32_t        nRefVoltage,
+    int32_t*        pnTemperature
+    )
+{
+    ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS;
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice;
+    uint16_t nConvTimeBackup;
+    uint16_t nAvgCfgBackup;
+    uint32_t nAdcTmpValue = 0u;
+    uint32_t nAdcTmp2Value = 0u;
+    uint32_t nClock = 0u;  
+    uint32_t nACLKDIVCNT;
+    uint32_t nCnvTime;
+    
+#ifdef ADI_DEBUG
+    if (pDevice == NULL)
+    {
+        return ADI_ADC_INVALID_DEVICE_HANDLE;
+    }
+    if (pnTemperature == NULL) 
+    {
+        return ADI_ADC_NULL_POINTER;
+    } 
+    
+    if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN | ADC_STATUS_TEMP_SENSOR_EN))
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }
+        
+    if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN))
+    {
+        return ADI_ADC_INVALID_SEQUENCE;
+    }    
+#endif    
+    
+    
+    if(adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &nClock) == ADI_PWR_SUCCESS)
+    {    
+      /* Calculate the conversion time */
+      nACLKDIVCNT = (*pREG_CLKG0_CLK_CTL1 & BITM_CLKG_CLK_CTL1_ACLKDIVCNT) >> BITP_CLKG_CLK_CTL1_ACLKDIVCNT;
+      nCnvTime = ((nClock / nACLKDIVCNT) / (uint16_t)15385u) + 1u;   /* 65us acquisition time required = 15385Hz sample */
+      
+    #ifdef ADI_DEBUG
+      if (nCnvTime >= 256u) {
+          return ADI_ADC_INVALID_STATE;
+      }
+    #endif
+      /* Take the backup of registers that need to be changed */
+      nConvTimeBackup = pDevice->pReg->CNV_TIME;
+      nAvgCfgBackup =  pDevice->pReg->AVG_CFG;
+      
+      /* Set the required value in the registers. */
+      
+      pDevice->pReg->CNV_TIME = (uint16_t)((nCnvTime << BITP_ADC_CNV_TIME_SAMPTIME) & BITM_ADC_CNV_TIME_SAMPTIME);
+      pDevice->pReg->AVG_CFG = 0u;
+      
+      /* Clear the temperature done status */
+      pDevice->pReg->STAT =  BITM_ADC_STAT_TMPDONE | BITM_ADC_STAT_TMP2DONE;
+      
+      /* Clear the temperature done state */
+      CLR_STATE(ADC_STATUS_TMP_DONE | ADC_STATUS_TMP2_DONE);
+      
+      /* Sample Tmp register */
+      pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_TMP);
+      while (IS_NOT_IN_STATE(ADC_STATUS_TMP_DONE)) { ; }
+      nAdcTmpValue = pDevice->pReg->TMP_OUT;
+      pDevice->pReg->CNV_CFG = 0u;
+      
+      
+      /* Sample Tmp2 register */
+      pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_TMP2);
+      while (IS_NOT_IN_STATE(ADC_STATUS_TMP2_DONE)) { ; }
+      pDevice->pReg->CNV_CFG = 0u;
+      nAdcTmp2Value = pDevice->pReg->TMP2_OUT;
+
+      /* Restore the changed registers */
+      pDevice->pReg->CNV_TIME = nConvTimeBackup;
+      pDevice->pReg->AVG_CFG = nAvgCfgBackup;
+      
+      /* Calculate the temperature voltage.
+       * From the HRM: Temperature can be calculated as:
+       *
+       * T(^0 C)= code1/(code2+RG*code1)*Rvirtualreference/(ideal_sensitivity )-273.15
+       * 
+       * Some of these values are constants, and some have been read from registers.
+       * The above formula, when populated with variables and constants, would look like this:
+       * T(^0 C)= (nAdcTmpValue/(nAdcTmp2Value + nTempRG * nAdcTmpValue)) * (1.2256/1.2411e-3)) -273.15
+       */
+      {
+          uint32_t nRVirRefByIdealSensitivity = 2070960834u; /* 1.2256/1.2411e-3 in 11.21 format */
+          
+          uint32_t nTempRG = 19380u; /* 1.1829 in 2.14 format */
+          uint32_t nTmp2 = ((nAdcTmp2Value << 14u) + (nTempRG * nAdcTmpValue)); /* in 14.14 format */
+          
+          uint32_t nOffsetPart = (335544320u/nRefVoltage); /* (1.25 in 4.28 format / ReferenceVoltage(16.16)) = Result in format *.12 */
+          uint32_t nOffset = (161u * nOffsetPart);         /* 12.12 format */
+          
+          uint32_t nTmp3  = ((nAdcTmpValue << 12) - nOffset) << 8u;  /* Format 12.20 */
+          uint32_t nRatio = (nTmp3/(nTmp2 >> 10u));  /* nTmp2 resolution reduced by 10 to 14.4 and the result resolution is 0.16 */
+          uint32_t nTemp  = (nRatio * (nRVirRefByIdealSensitivity >> 16u)) >> 5u;  /* Temperature in degree kelvin in 16.16 format */
+          
+          int32_t  iTemp = (int32_t)nTemp - ((int32_t)17901158);   /* Subtract 273.15 (in 16.16) to get the temperature in degree celcius */
+          *pnTemperature = iTemp;
+      }
+    }
+    else
+    {
+       eResult = ADI_ADC_BAD_SYS_CLOCK;
+    }
+
+    return eResult;
+}
+
+
+/*! \cond PRIVATE */
+
+/*==========  S T A T I C    F U N C T I O N S  ==========*/
+/* Read the output register for the given channel number */
+static uint16_t ReadOutReg(uint32_t nChannelNum)
+{
+    const volatile uint16_t* pOutRegister = pREG_ADC0_CH0_OUT;
+    pOutRegister += nChannelNum*2u;
+    return *pOutRegister;
+}
+
+/* Init buffer processing */
+static bool InitBufferProcessing(ADI_ADC_DEVICE *pDevice)
+{
+    uint32_t nCnvReg = ((uint32_t)(pDevice->pReg->CNV_CFG) & BITM_ADC_CNV_CFG_DMAEN);
+    ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer;
+    
+    if (IS_NOT_IN_ANY_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS)) 
+    {
+        /* Clear conversion done flags */
+        pDevice->pReg->STAT = 0xFFFFu;
+        
+        /* Clear the overflow and alert register */
+        pDevice->pReg->OVF = 0xFFFFu;
+    }
+    
+    /* Calculate the conversion register value for the given configuration */
+    nCnvReg |= pIntBuffer->nChannels;
+    if ((uint16_t)(pIntBuffer->nConfig & ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN) != 0u) {
+        nCnvReg |= BITM_ADC_CNV_CFG_AUTOMODE;
+    }    
+    if ((pIntBuffer->nConfig & ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN) != 0u) {
+        nCnvReg |= BITM_ADC_CNV_CFG_SINGLE;
+    } else {
+        nCnvReg |= BITM_ADC_CNV_CFG_MULTI;
+    }    
+
+    SET_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS);
+
+    pDevice->pReg->CNV_CFG |= (uint16_t)nCnvReg;
+    
+    pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_ENABLED);
+
+    return true;
+}
+
+
+#if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1
+/* DMA Callback Handler */
+void DMA_ADC0_Int_Handler (void)
+{
+    ISR_PROLOG();
+    ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *) AdcDevInfo[0].hDevice;
+    
+    DmaFIFOManage(pDevice, ADC_FIFO_MODE_DMA_BUFFER_PROCESS);
+    
+    ISR_EPILOG();
+}
+
+static ADI_ADC_RESULT DmaFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode)
+{
+    uint16_t nCount = 0u;
+    uint16_t chanNum = ADC0_CHANn;
+    uint16_t IRQ_Backup;
+    
+    ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer;
+    
+    if(pDevice->s_Buffer.pCurDataBuffer == NULL) {
+        /* If there is nothing active... */
+        if (eFifoMode == ADC_FIFO_MODE_INTERRUPT_PROCESS) {
+            /* ...it's something leftover, so cleanup. */
+            uint16_t nStat = pDevice->pReg->STAT & 0x00FFu;
+            FlushFifo(pDevice, (uint32_t)nStat);
+            pDevice->pReg->STAT = nStat;
+        }
+    }
+    else {
+        switch (eFifoMode)
+        {
+        case ADC_FIFO_MODE_INIT:
+
+              /* Enable the interrupt for the given DMA */
+              NVIC_EnableIRQ(DMA0_CH24_DONE_IRQn);
+              
+              pADI_DMA0->SRCADDR_CLR = 1U << chanNum;
+
+              /* Enable the channel */
+              pADI_DMA0->EN_SET = 1U << chanNum;
+              
+              /* Enables  peripheral to generate DMA requests. */
+              pADI_DMA0->RMSK_CLR = 1U << chanNum;
+
+              /* Set the primary as the current DMA descriptor */
+              pADI_DMA0->ALT_CLR = 1U << chanNum;  /* Should be default */
+                            
+              /* Setup the DMA registers */
+              nCount = (uint16_t)pIntBuffer->nNumSamplesRemaining;
+
+              /* Point to the end of the DMA source */
+              pPrimaryCCD[chanNum].DMASRCEND =   (uint32_t)(&(pDevice->pReg->DMA_OUT));
+              
+              /* Point to the end of the DMA write-to destination */ 
+              pPrimaryCCD[chanNum].DMADSTEND =   (uint32_t)((void*)pIntBuffer->pCurDataBuffer) + ((nCount * 2u) - 1u);
+              
+              /* Configure the DMA itself */
+              pPrimaryCCD[chanNum].DMACDC =         ((ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_DST_INC) |            /* Increment destination address */
+                                                    (ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) |               /* Don't increment the source address */
+                                                    ((uint32_t)ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) |           /* 16bit transfers */
+                                                    ((nCount - (uint32_t)1U)<< DMA_BITP_CTL_N_MINUS_1) |        /* Data size? */
+                                                    (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL) |  /*  Basic only */
+                                                    ((uint32_t)ADI_DMA_RPOWER_1 << DMA_BITP_CTL_R_POWER));                /* Arbitration */
+          
+              /* Enable DMA */
+              pDevice->pReg->CNV_CFG |= BITM_ADC_CNV_CFG_DMAEN;
+            break;
+
+        case ADC_FIFO_MODE_ENABLED:
+            break;
+
+        case ADC_FIFO_MODE_INTERRUPT_PROCESS:
+            /* Clear the status registers */
+            pDevice->pReg->STAT = (pDevice->pReg->STAT & 0x00FFu);
+            break;
+
+        case ADC_FIFO_MODE_INTERRUPT_OVERFLOW:
+            pIntBuffer->nStatus |= ADC_BUFFER_STATUS_OVERFLOW;
+            break;
+      
+        case ADC_FIFO_MODE_DMA_BUFFER_PROCESS:
+            pIntBuffer->nNumSamplesRemaining = 0u;
+            ManageFifoCompletion(pDevice);
+            break;
+            
+        case ADC_FIFO_MODE_ABORT:
+     
+            /* Take backup of IRQ */
+            IRQ_Backup = pDevice->pReg->IRQ_EN;
+
+            /* Disable the IRQ */
+            pDevice->pReg->IRQ_EN = 0u;
+
+            /* Clear the conversion cfg register to stop any transaction */
+            pDevice->pReg->CNV_CFG = 0u;
+            
+            /* Disable the DMA channel */
+            pADI_DMA0->EN_CLR = 1U << chanNum;
+              
+            /* Clear the status bits */
+            pDevice->pReg->STAT =  pDevice->pReg->STAT;
+      
+            /* Clear the sampling in progress state */
+            CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS);
+            
+            /* Read and flush all the buffers */
+            FlushFifo(pDevice, 0x00FFu);
+          
+            /* Restore the IRQ */
+            pDevice->pReg->IRQ_EN = IRQ_Backup;      
+          
+            break;
+
+        default:
+            break;
+        } 
+    }
+    
+    return ADI_ADC_SUCCESS;
+}
+#else /* else ADI_ADC_ENABLE_MULTI_ACQUIRE == 0 */
+
+static ADI_ADC_RESULT InterruptFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode)
+{
+    ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer;
+    
+    if(pDevice->s_Buffer.pCurDataBuffer == NULL) {
+        if (eFifoMode == ADC_FIFO_MODE_INTERRUPT_PROCESS) {
+            uint16_t nStat = pDevice->pReg->STAT & 0x00FFu;
+            FlushFifo(pDevice, (uint32_t)nStat);
+            pDevice->pReg->STAT = nStat;
+        }
+        return ADI_ADC_SUCCESS;
+    }
+
+    switch (eFifoMode)
+    {
+    case ADC_FIFO_MODE_INIT:
+        {
+            /* Enable the conversion done and overflow interrupt */
+            pDevice->ActData.nCurChannel = 0u;
+        }
+        break;
+
+    case ADC_FIFO_MODE_ENABLED:
+        break;
+
+    case ADC_FIFO_MODE_INTERRUPT_PROCESS:
+        {
+            while (pIntBuffer->nNumSamplesRemaining > 0u) {
+                uint32_t nConvStatus = ((uint32_t)pDevice->pReg->STAT & (uint32_t)0x00FFu);
+                if ((nConvStatus & 0x00FFu) == 0u)
+                {
+                    break;
+                }
+                
+                uint32_t nCurChannelBitM = ((uint32_t)1u << pDevice->ActData.nCurChannel);
+                while ((nCurChannelBitM & nConvStatus) == 0u) {
+                    pDevice->ActData.nCurChannel++;
+                    if (pDevice->ActData.nCurChannel >= NUM_ADC_CHANNELS) {
+                        pDevice->ActData.nCurChannel = 0u;
+                    }
+                    nCurChannelBitM = ((uint32_t)1u << pDevice->ActData.nCurChannel);
+                }
+                
+                assert ((pIntBuffer->nChannels & ((uint32_t)1u << pDevice->ActData.nCurChannel)) != 0u);
+                
+                *pIntBuffer->pCurDataBuffer = ReadOutReg( pDevice->ActData.nCurChannel);
+                pIntBuffer->pCurDataBuffer++;
+                
+                
+                pDevice->pReg->STAT = (uint16_t)nCurChannelBitM;
+                pIntBuffer->nNumSamplesRemaining -= 1u;
+
+                pDevice->ActData.nCurChannel += 1u;
+                if ( pDevice->ActData.nCurChannel >= NUM_ADC_CHANNELS) {
+                     pDevice->ActData.nCurChannel = 0u;
+                }
+            }
+
+            if (pIntBuffer->nNumSamplesRemaining == 0u) {
+                ManageFifoCompletion(pDevice);
+            }
+        }
+        break;
+        
+    case ADC_FIFO_MODE_INTERRUPT_OVERFLOW:
+        {
+            pIntBuffer->nStatus |= ADC_BUFFER_STATUS_OVERFLOW;
+        }
+        break;
+        
+    case ADC_FIFO_MODE_ABORT:
+        {
+          uint16_t IRQ_Backup;
+    
+          /* Take backup of IRQ */
+          IRQ_Backup = pDevice->pReg->IRQ_EN;
+
+          /* Disable the IRQ */
+          pDevice->pReg->IRQ_EN = 0u;
+
+          /* Clear the conversion cfg register to stop any transaction */
+          pDevice->pReg->CNV_CFG = 0u;
+          
+          /* Clear the status bits */
+          pDevice->pReg->STAT =  pDevice->pReg->STAT;
+    
+          /* Clear the sampling in progress state */
+          CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS);
+
+          /* Read and flush all the buffers */
+          FlushFifo(pDevice, 0x00FFu);
+        
+          /* Restore the IRQ */
+          pDevice->pReg->IRQ_EN = IRQ_Backup; 
+        }
+        break;
+
+    default:
+        break;
+    }
+    
+    return ADI_ADC_SUCCESS;
+}
+#endif 
+
+static void FlushFifo(ADI_ADC_DEVICE *pDevice, uint32_t nChannels)
+{
+    uint32_t x;
+    for (x = 0u; x < 8u; x++) {
+      if ((nChannels & ((uint32_t)1u << x)) != 0u) {
+          ReadOutReg(x);
+      }
+    }
+}
+
+
+/* Called when a transfer is complete */
+static void ManageFifoCompletion(ADI_ADC_DEVICE *pDevice)
+{   
+    /* Clear the conversion configuration */
+    pDevice->pReg->CNV_CFG = 0u;
+    CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS);
+    
+    SEM_POST(pDevice);
+}
+
+
+/* Internal function to extract the number of channels
+ * in a 32bit word.  */
+static uint32_t GetNumChannels(uint32_t nChannels)
+{
+    uint32_t n = nChannels & 0x000000FFu;
+
+    n = (n & 0x00000055u) + ((n >> 1u) & 0x00000055u);
+    n = (n & 0x00000033u) + ((n >> 2u) & 0x00000033u);
+    n = (n + (n >> 4u)) & (0x0000000Fu);
+
+    return n;
+}
+
+/* Returns the channel number based on the ADI_ADC_CHANNEL type.
+ *  i.e. ADI_ADC_CHANNEL1 returns 1. */
+static int32_t nGetChannelNumber(ADI_ADC_CHANNEL eChannel)
+{
+    int32_t retVal = 0;
+    uint32_t nChannel = (uint32_t)eChannel & 0x000000FFu;
+    
+    if ((nChannel & (nChannel - (uint32_t)1u)) != 0u) {
+        return -1;
+    }
+    if ((nChannel & 0x000000AAu) != 0u) { retVal += 1; }
+    if ((nChannel & 0x000000CCu) != 0u) { retVal += 2; }
+    if ((nChannel & 0x000000F0u) != 0u) { retVal += 4; }
+    
+    return retVal;
+}
+
+/* Internal function to set static configuration options. */
+static void StaticConfiguration(ADI_ADC_DEVICE *pDevice)
+{
+    uint16_t nCfgReg = 0u;
+
+    /* Configure the resolution */
+#if ADI_ADC_CFG_RESOLUTION == 12
+    pDevice->pReg->AVG_CFG = 0u; 
+#else    
+
+#if ADI_ADC_CFG_RESOLUTION == 13
+    pDevice->pReg->AVG_CFG =  BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0002u << BITP_ADC_AVG_CFG_FACTOR);
+#elif ADI_ADC_CFG_RESOLUTION == 14     
+    pDevice->pReg->AVG_CFG =  BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0008u << BITP_ADC_AVG_CFG_FACTOR);
+#elif ADI_ADC_CFG_RESOLUTION == 15
+    pDevice->pReg->AVG_CFG =  BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0020u << BITP_ADC_AVG_CFG_FACTOR);
+#elif ADI_ADC_CFG_RESOLUTION == 16     
+    pDevice->pReg->AVG_CFG =  BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0080u << BITP_ADC_AVG_CFG_FACTOR);
+#else
+#error "Invalid Resolution"    
+#endif
+
+    SET_STATE(ADC_STATUS_OVERSAMPLING_EN);    
+#endif
+
+    /* Configure the VREF */
+#if ADI_ADC_CFG_VREF == 0     /* 1.25V Internal Reference*/
+    nCfgReg |= BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL;
+#elif ADI_ADC_CFG_VREF == 1     /* 2.5V Internal Reference */    
+    nCfgReg |= BITM_ADC_CFG_REFBUFEN;
+#elif ADI_ADC_CFG_VREF == 2     /* Battery Voltage */    
+    nCfgReg |= BITM_ADC_CFG_VREFVBAT;
+#endif
+    
+    pDevice->pReg->CFG = nCfgReg;
+
+#if ADI_ADC_ENABLE_STATIC_COMPARATOR == 1
+    /* High limit registers */
+#if ADI_ADC_COMPARATOR_AIN0_HI_EN == 1
+    pDevice->pReg->LIM0_HI = ADI_ADC_COMPARATOR_AIN0_HI_VAL;
+    pDevice->ComparitorHi |= ADI_ADC_CHANNEL_0;
+#endif
+#if ADI_ADC_COMPARATOR_AIN1_HI_EN == 1
+    pDevice->pReg->LIM1_HI = ADI_ADC_COMPARATOR_AIN1_HI_VAL;
+    pDevice->ComparitorHi |= ADI_ADC_CHANNEL_1;
+#endif
+#if ADI_ADC_COMPARATOR_AIN2_HI_EN == 1
+    pDevice->pReg->LIM2_HI = ADI_ADC_COMPARATOR_AIN2_HI_VAL;
+    pDevice->ComparitorHi |= ADI_ADC_CHANNEL_2;
+#endif
+#if ADI_ADC_COMPARATOR_AIN3_HI_EN == 1
+    pDevice->pReg->LIM3_HI = ADI_ADC_COMPARATOR_AIN3_HI_VAL;
+    pDevice->ComparitorHi |= ADI_ADC_CHANNEL_3;
+#endif
+    /* Low limit registers */
+#if ADI_ADC_COMPARATOR_AIN0_LO_EN == 1
+    pDevice->pReg->LIM0_LO = (uint16_t)ADI_ADC_COMPARATOR_AIN0_LO_VAL;
+    pDevice->ComparitorLo |= ADI_ADC_CHANNEL_0;
+#endif
+#if ADI_ADC_COMPARATOR_AIN1_LO_EN == 1
+    pDevice->pReg->LIM1_LO = ADI_ADC_COMPARATOR_AIN1_LO_VAL;
+    pDevice->ComparitorLo |= ADI_ADC_CHANNEL_1;
+#endif
+#if ADI_ADC_COMPARATOR_AIN2_LO_EN == 1
+    pDevice->pReg->LIM2_LO = ADI_ADC_COMPARATOR_AIN2_LO_VAL;
+    pDevice->ComparitorLo |= ADI_ADC_CHANNEL_2;
+#endif
+#if ADI_ADC_COMPARATOR_AIN3_LO_EN == 1
+    pDevice->pReg->LIM3_LO = ADI_ADC_COMPARATOR_AIN3_LO_VAL;
+    pDevice->ComparitorLo |= ADI_ADC_CHANNEL_3;
+#endif
+    
+    /* Hysteresis registers */
+#if ADI_ADC_COMPARATOR_AIN0_HYS_EN == 1
+    pDevice->pReg->HYS0 = (uint16_t)(ADI_ADC_COMPARATOR_AIN0_HYS_VAL | (ADI_ADC_COMPARATOR_AIN0_HYS_CYC << BITP_ADC_HYS0_MONCYC));
+    pDevice->ComparitorHys |= ADI_ADC_CHANNEL_0;
+#endif
+#if ADI_ADC_COMPARATOR_AIN1_HYS_EN == 1
+    pDevice->pReg->HYS1 = (ADI_ADC_COMPARATOR_AIN1_HYS_VAL | (ADI_ADC_COMPARATOR_AIN1_HYS_CYC << BITP_ADC_HYS0_MONCYC));
+    pDevice->ComparitorHys |= ADI_ADC_CHANNEL_1;
+#endif
+#if ADI_ADC_COMPARATOR_AIN2_HYS_EN == 1
+    pDevice->pReg->HYS2 = (ADI_ADC_COMPARATOR_AIN2_HYS_VAL | (ADI_ADC_COMPARATOR_AIN2_HYS_CYC << BITP_ADC_HYS0_MONCYC));
+    pDevice->ComparitorHys |= ADI_ADC_CHANNEL_2;
+#endif
+#if ADI_ADC_COMPARATOR_AIN3_HYS_EN == 1
+    pDevice->pReg->HYS3 = (ADI_ADC_COMPARATOR_AIN3_HYS_VAL | (ADI_ADC_COMPARATOR_AIN3_HYS_CYC << BITP_ADC_HYS0_MONCYC));
+    pDevice->ComparitorHys |= ADI_ADC_CHANNEL_3;
+#endif
+#endif
+
+}
+
+/* Internal function to enable the comparitor for previously-configured channels
+ * Does not set the limits, only enables. 
+*/
+static void EnableComparator(ADI_ADC_DEVICE *pDevice, bool bEnable)
+{
+    uint32_t x;
+    uint16_t nCnvCfg = 0u;
+    volatile uint16_t* pLO_Register[4]  = {pREG_ADC0_LIM0_LO, pREG_ADC0_LIM1_LO, pREG_ADC0_LIM2_LO, pREG_ADC0_LIM3_LO};
+    volatile uint16_t* pHI_Register[4]  = {pREG_ADC0_LIM0_HI, pREG_ADC0_LIM1_HI, pREG_ADC0_LIM2_HI, pREG_ADC0_LIM3_HI};
+    volatile uint16_t* pHYS_Register[4] = {pREG_ADC0_HYS0,    pREG_ADC0_HYS1,    pREG_ADC0_HYS2,    pREG_ADC0_HYS3};
+    
+    if (bEnable == true)
+    {
+      /* Loop round all the channels enabling each part if required. */
+      for (x = 0u; x < NUM_ADC_COMPARATOR_CHANNELS; x++) {
+          if((pDevice->ComparitorHi & (1u << x)) > 0u) {
+            *pHI_Register[x] |= BITM_ADC_LIM0_HI_EN;
+          }
+          if((pDevice->ComparitorLo & (1u << x)) > 0u) {
+            *pLO_Register[x] |= BITM_ADC_LIM0_LO_EN;
+          }
+          if((pDevice->ComparitorHys & (1u << x)) > 0u) {
+            *pHYS_Register[x] |= BITM_ADC_HYS0_EN;
+          }
+      }      
+      nCnvCfg = (uint16_t)((uint16_t)pDevice->ComparitorHi | (uint16_t)pDevice->ComparitorLo);
+      
+      pDevice->pReg->IRQ_EN &= (uint16_t)(~BITM_ADC_IRQ_EN_CNVDONE);
+      pDevice->pReg->CNV_CFG = (uint16_t)nCnvCfg | (uint16_t)(BITM_ADC_CNV_CFG_MULTI | BITM_ADC_CNV_CFG_AUTOMODE);
+      SET_STATE(ADC_STATUS_COMPARATOR_EN);
+    }    
+    else {
+      /* Loop round disabling all. */
+      for (x = 0u; x < NUM_ADC_COMPARATOR_CHANNELS; x++) {
+            *pHI_Register[x]  &= (uint16_t)(~(BITM_ADC_LIM0_HI_EN));
+            *pLO_Register[x]  &= (uint16_t)(~(BITM_ADC_LIM0_LO_EN));
+            *pHYS_Register[x] &= (uint16_t)(~(BITM_ADC_HYS0_EN));
+        }
+        pDevice->pReg->CNV_CFG = 0u;
+        pDevice->pReg->STAT = pDevice->pReg->STAT & 0x00FFu;
+        CLR_STATE(ADC_STATUS_COMPARATOR_EN);
+        pDevice->pReg->IRQ_EN |= BITM_ADC_IRQ_EN_CNVDONE;
+    }
+}
+
+
+/* In Handler handles the following cases:
+ * ADI_ADC_EVENT_ADC_READY
+ * ADI_ADC_EVENT_CALIBRATION_DONE
+ * ADC_STATUS_BATTERY_DONE
+ * ADC_STATUS_TMP_DONE
+ * ADC_STATUS_TMP2_DONE
+ * ADI_ADC_EVENT_HIGH_LIMIT_CROSSED
+ * ADI_ADC_EVENT_LOW_LIMIT_CROSSED
+*/
+void ADC0_Int_Handler(void)
+{
+    ADI_ADC_DEVICE *pDevice;
+    ISR_PROLOG();
+    
+    pDevice = (ADI_ADC_DEVICE *) AdcDevInfo[0].hDevice;
+    
+    if ((pDevice->pReg->STAT & 0x00FFu) != 0u) {
+        if (IS_NOT_IN_STATE(ADC_STATUS_COMPARATOR_EN)) {
+            pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INTERRUPT_PROCESS);
+        } else {
+            pDevice->pReg->STAT = pDevice->pReg->STAT & (0x00FFu);
+        }
+    }
+    if ((uint16_t)(pDevice->pReg->STAT & 0xFF00u) != 0u) {
+        if ((pDevice->pReg->STAT & BITM_ADC_STAT_RDY) != 0u) {
+            SET_STATE(ADC_STATUS_SUB_SYSTEM_READY);
+            pDevice->pReg->STAT = BITM_ADC_STAT_RDY;
+            if (pDevice->pfCallback != NULL) {
+                pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_ADC_READY, NULL);
+            }
+        }
+        if ((pDevice->pReg->STAT & BITM_ADC_STAT_CALDONE) != 0u) {
+            SET_STATE(ADC_STATUS_CALIBRATION_DONE);
+            pDevice->pReg->STAT = BITM_ADC_STAT_CALDONE;
+            if (pDevice->pfCallback != NULL) {
+                pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_CALIBRATION_DONE, NULL);
+            }
+        }
+        if ((pDevice->pReg->STAT & BITM_ADC_STAT_BATDONE) != 0u) {
+            SET_STATE(ADC_STATUS_BATTERY_DONE);
+            pDevice->pReg->STAT = BITM_ADC_STAT_BATDONE;
+        }	
+        
+        if ((pDevice->pReg->STAT & BITM_ADC_STAT_TMPDONE) != 0u) {
+            SET_STATE(ADC_STATUS_TMP_DONE);
+            pDevice->pReg->STAT = BITM_ADC_STAT_TMPDONE;
+        }	
+        
+        if ((pDevice->pReg->STAT & BITM_ADC_STAT_TMP2DONE) != 0u) {
+            SET_STATE(ADC_STATUS_TMP2_DONE);
+            pDevice->pReg->STAT = BITM_ADC_STAT_TMP2DONE;
+        }	
+    }
+    if (pDevice->pReg->OVF) {
+        uint16_t nOvrFlowValue = pDevice->pReg->OVF;
+        if (IS_NOT_IN_STATE(ADC_STATUS_COMPARATOR_EN)) {
+            pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INTERRUPT_OVERFLOW);
+        }
+        pDevice->pReg->OVF = nOvrFlowValue;
+    }
+    if (pDevice->pReg->ALERT) {
+      uint32_t nAlertValue = pDevice->pReg->ALERT;
+      uint32_t channel;
+      if (IS_IN_STATE(ADC_STATUS_COMPARATOR_EN) && (pDevice->pfCallback != NULL)) {
+        for (channel = 0u; channel < (NUM_ADC_COMPARATOR_CHANNELS); channel++) {
+          /* Alert bit positions: hi limits are 0b01, 
+          *                      lo limit alerts are 0b10.
+          */
+          if((nAlertValue & (1u << (2u * channel))) > 0u) {
+            pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_HIGH_LIMIT_CROSSED, (void*)channel);
+          }
+          if((nAlertValue & (1u << ((2u * channel) + ((uint32_t)1u)))) > 0u)
+          {
+            pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_LOW_LIMIT_CROSSED, (void*)channel);
+          }
+        }
+      }
+      pDevice->pReg->ALERT = (uint16_t)nAlertValue;
+    }
+    ISR_EPILOG();     
+}
+
+
+/*! \endcond */
+
+#endif /* ADI_ADC_C */
+
+/*****/
+
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_data.c
new file mode 100755
index 00000000000..169378ea0fd
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_data.c
@@ -0,0 +1,20 @@
+#ifndef ADI_ADC_DATA_C
+#define ADI_ADC_DATA_C
+
+#include <drivers/adc/adi_adc.h>
+#include <drivers/dma/adi_dma.h>
+#include <adi_processor.h>
+#include "adi_adc_def.h"
+
+/*! \cond PRIVATE */
+
+static ADI_ADC_INFO AdcDevInfo[] = {
+    {
+        NULL,
+        (ADI_ADC_TypeDef*)REG_ADC0_CFG
+    }
+};
+
+/*! \endcond */
+
+#endif /* ADI_ADC_DATA_C */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_def.h
new file mode 100755
index 00000000000..6568f6f277e
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_def.h
@@ -0,0 +1,120 @@
+/*! \cond PRIVATE */
+
+#ifndef ADI_ADC_DEF
+#define ADI_ADC_DEF
+
+#include <drivers/adc/adi_adc.h>
+#include <adi_processor.h>
+
+#if defined(__ECC__)
+#define ALIGN
+#define ALIGN4  _Pragma("align(4)")
+#elif defined(__ICCARM__)
+#define ALIGN   _Pragma("pack()")
+#define ALIGN4  _Pragma("pack(4)")
+#elif defined (__GNUC__)
+#define ALIGN   _Pragma("pack()")
+#define ALIGN4  _Pragma("pack(4)")
+#endif
+
+
+#define IS_IN_STATE(X)         ((pDevice->nDriverStatus & (uint32_t)(X)) == (uint32_t)(X))
+#define IS_NOT_IN_STATE(X)     ((pDevice->nDriverStatus & (uint32_t)(X)) == 0u)
+#define IS_IN_ALL_STATES(X)    ((pDevice->nDriverStatus & (uint32_t)(X)) == (uint32_t)(X))
+#define IS_IN_ANY_STATE(X)     ((pDevice->nDriverStatus & (uint32_t)(X)) != 0u)
+#define IS_NOT_IN_ANY_STATE(X) ((pDevice->nDriverStatus & (uint32_t)(X)) == 0u)
+
+#define SET_STATE(X)  (pDevice->nDriverStatus |= (uint32_t)(X))
+#define CLR_STATE(X)  (pDevice->nDriverStatus &= ~((uint32_t)(X)))
+
+#define NUM_ADC_CHANNELS      			(8u)
+#define NUM_ADC_COMPARATOR_CHANNELS             (4u)
+
+/* To keep state for the driver for error checking */
+typedef enum __ADC_STATUS {
+    ADC_STATUS_POWERED_UP            = (1u << 0),
+    ADC_STATUS_SUB_SYSTEM_EN         = (1u << 1),
+    ADC_STATUS_SUB_SYSTEM_READY      = (1u << 2),
+    
+    ADC_STATUS_NON_BLOCKING_EN       = (1u << 3),
+    ADC_STATUS_BLOCKING_EN           = (1u << 4), 
+    ADC_STATUS_COMPARATOR_EN         = (1u << 5),
+    
+    ADC_STATUS_SAMPLING_IN_PROGRESS  = (1u << 6),
+    ADC_STATUS_CALIBRATION_EN        = (1u << 7),
+    ADC_STATUS_CALIBRATION_DONE      = (1u << 8),
+    
+    ADC_STATUS_BATTERY_DONE          = (1u << 9),
+    
+    ADC_STATUS_OVERSAMPLING_EN       = (1u << 10),
+    ADC_STATUS_AVGERAGING_EN         = (1u << 11),
+    
+    ADC_STATUS_TEMP_SENSOR_EN        = (1u << 12),
+    
+    ADC_STATUS_TMP_DONE              = (1u << 13),
+    ADC_STATUS_TMP2_DONE             = (1u << 14),
+} ADC_STATUS;
+
+typedef enum __ADC_FIFO_MODE {
+    ADC_FIFO_MODE_INIT,
+    ADC_FIFO_MODE_ENABLED,
+    ADC_FIFO_MODE_INTERRUPT_PROCESS,
+    ADC_FIFO_MODE_INTERRUPT_OVERFLOW,
+    ADC_FIFO_MODE_DMA_BUFFER_PROCESS,
+    ADC_FIFO_MODE_DMA_INVALID_DESC,
+    ADC_FIFO_MODE_ABORT
+} ADC_FIFO_MODE;
+
+typedef enum __ADC_BUFFER_CONFIG {
+    ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN = ((uint32_t)1u << 1u),
+    ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN   = ((uint32_t)1u << 0u),
+} ADC_BUFFER_CONFIG;
+
+
+typedef enum __ADC_BUFFER_STATUS {
+    ADC_BUFFER_STATUS_OK        = ((uint32_t)1u << 0u),
+    ADC_BUFFER_STATUS_OVERFLOW  = ((uint32_t)1u << 1u)
+} ADC_BUFFER_STATUS;
+
+typedef struct __ADC_INT_BUFFER {
+    uint16_t                  nConfig;
+    uint16_t                  nStatus;
+    ADI_ADC_BUFFER           *pUserBuffer;
+    uint16_t*                 pCurDataBuffer;
+    uint32_t                  nNumSamplesRemaining;
+    uint32_t                  nChannels;
+} ADC_INT_BUFFER;
+
+typedef struct __ADC_ACTIVE_DATA {
+    uint32_t nCurChannel;
+} ADC_ACTIVE_DATA;
+
+typedef ADI_ADC_RESULT (*ADC_MANAGE_FIFO_FUNC)(struct __ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode);
+
+typedef struct __ADI_ADC_DEVICE
+{
+    volatile uint32_t    nDriverStatus;
+    ADI_ADC_TypeDef      *pReg;
+    void*                pCBParam;
+    ADI_CALLBACK         pfCallback;
+
+    ADC_ACTIVE_DATA      ActData;
+    ADC_MANAGE_FIFO_FUNC pfManageFifo;
+
+    ADC_INT_BUFFER       s_Buffer;
+    uint8_t              ComparitorHi;
+    uint8_t              ComparitorLo;
+    uint8_t              ComparitorHys;
+    
+    SEM_VAR_DECLR
+} ADI_ADC_DEVICE;
+
+typedef struct __ADI_ADC_INFO
+{
+    ADI_ADC_HANDLE     hDevice;
+    ADI_ADC_TypeDef*   pReg;
+} ADI_ADC_INFO;
+
+#endif /* ADI_ADC_DEF */
+
+/*! \endcond */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_callback.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_callback.h
new file mode 100755
index 00000000000..fd2e04f282b
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_callback.h
@@ -0,0 +1,60 @@
+/*!
+ *****************************************************************************
+   @file:    adi_callback.h
+   @brief:   callback APIs.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+/*****************************************************************************/
+
+#ifndef ADI_CALLBACK_H
+#define ADI_CALLBACK_H
+
+#include <stdint.h>
+
+/**
+ * @brief Device Drivers Callback function definition
+ */
+typedef void (* ADI_CALLBACK) (  /*!< Callback function pointer */
+    void      *pCBParam,         /*!< Client supplied callback param */
+    uint32_t   Event,            /*!< Event ID specific to the Driver/Service */
+    void      *pArg);            /*!< Pointer to the event specific argument */
+    
+#endif /* ADI_CALLBACK_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_cyclecount.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_cyclecount.h
new file mode 100755
index 00000000000..a2b5807a628
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_cyclecount.h
@@ -0,0 +1,137 @@
+/*
+ *******************************************************************************
+ * @brief:   Framework to preform cycle count measurements
+ *
+ * @details  this is a framework for monitoring the cycle counts
+ *           for ISRs and APIs. The framework uses systick.
+
+*******************************************************************************
+
+ Copyright(c) 2016 Analog Devices, Inc. All Rights Reserved.
+
+ This software is proprietary and confidential.  By using this software you agree
+ to the terms of the associated Analog Devices License Agreement.
+
+ ******************************************************************************/
+
+#ifndef ADI_CYCLECOUNT_H
+#define ADI_CYCLECOUNT_H
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <adi_cycle_counting_config.h>
+
+
+ /** @addtogroup  cyclecount_logging Cycle Counting Framework
+ *   @{
+ */
+
+/*!
+ * 64-bit integer to record cycle counts.
+ * Since UINT32_MAX = 4,294,967,296 cycles
+ * at 26 MHz this would allow us to record for 165 seconds
+ * before the system would wrap around.
+ * By moving to a 64-bit integer we can record for 11,248 years.
+ */
+typedef uint64_t  adi_cyclecount_t;
+
+
+/*!
+ * The systick timer is a 24-bit count down timer
+ * The initial value can, therefore,  be up to 0xFFFFFF
+ * The larger the value the fewer interrupts that will be taken
+ * and the less impact cycle counting will have on the system
+ */
+#define ADI_CYCLECOUNT_SYSTICKS        (0xFFFFFFu)
+
+/*!
+ * Cycle counting nesting is supported via a cycle counting stack. The initial
+ * value of the stack index is one less than the starting stack
+ * index (0)
+ */
+#define ADI_CYCLECOUNT_INITIAL_STACK_INDEX (-1)
+
+/*!
+ * Cycle Count API function return values.
+ */
+typedef enum {
+
+    ADI_CYCLECOUNT_SUCCESS,              /*!< API completed successfully */
+    ADI_CYCLECOUNT_ADD_ENTITY_FAILURE,   /*!< There is not enough space in the cycle counting entity array. Consider increasing the size via the #ADI_CYCLECOUNT_NUMBER_USER_DEFINED_APIS static configuration macro   */
+    ADI_CYCLECOUNT_INVALID_ID,           /*!< The API/ISR ID is invalid. */
+    ADI_CYCLECOUNT_FAILURE               /*!< API did not complete successfully. */
+} ADI_CYCLECOUNT_RESULT;
+
+
+/*!
+ * List of cycle counting IDs for the ISRs and APIs that can record cycle counts.
+ * Items enumerated here must be aligned with adi_cyclecounting_identifiers
+ *
+ * Note that the ID numbering starts at 1. ID==0 is not used.
+ * Note that the application can extend this list via static configuration (see adi_cycle_counting_config.h) and
+ * via the adi_cyclecount_addEntity() API.
+ */
+#define    ADI_CYCLECOUNT_ISR_EXT_3         1u      /*!< Cycle count ID for EXT3 Interrupt Handler. */
+#define    ADI_CYCLECOUNT_ISR_UART          2u      /*!< Cycle count ID for UART Interrupt Handler. */
+#define    ADI_CYCLECOUNT_ISR_DMA_UART_TX   3u      /*!< Cycle count ID for UART DMA TX Interrupt Handler. */
+#define    ADI_CYCLECOUNT_ISR_DMA_UART_RX   4u      /*!< Cycle count ID for UART DMA RX Interrupt Handler. */
+#define    ADI_CYCLECOUNT_ISR_TMR_COMMON    5u      /*!< Cycle count ID for Timer Interrupt Handler. */
+#define    ADI_CYCLECOUNT_ISR_RTC           6u      /*!< Cycle count ID for RTC Interrupt Handler.*/
+#define    ADI_CYCLECOUNT_ISR_SPI           7u      /*!< Cycle count ID for SPI Interrupt Handler. */
+#define    ADI_CYCLECOUNT_ISR_CRC           8u      /*!< Cycle count ID for CRC Interrupt Handler. */
+#define    ADI_CYCLECOUNT_ISR_SPORT         9u      /*!< Cycle count ID for SPORT Interrupt Handler. */
+#define    ADI_CYCLECOUNT_ID_COUNT         10u      /*!< Number of cycle count ISRs and APIs. Must be one greater than the last ID. */
+
+
+/*!
+ * The following are tracked when cycle counting
+ *    Maximum number of cycle counts
+ *    Minimum number of cycle counts
+ *    Average number of cycle counts
+ */
+typedef struct
+{
+  adi_cyclecount_t max_cycles_adjusted;         /*!< Tracks the adjusted max cycle count */
+  adi_cyclecount_t min_cycles_adjusted;         /*!< Tracks the adjusted min cycle count */
+  adi_cyclecount_t average_cycles_adjusted;     /*!< Tracks the adjusted average cycle count */
+
+  adi_cyclecount_t max_cycles_unadjusted;       /*!< Tracks the unadjusted max cycle count */
+  adi_cyclecount_t min_cycles_unadjusted;       /*!< Tracks the unadjusted min cycle count */
+  adi_cyclecount_t average_cycles_unadjusted;   /*!< Tracks the unadjusted average cycle count */
+
+  uint32_t         sample_count;                /*!< Number of cycle count samples recorded, used to compute the average */
+
+} ADI_CYCLECOUNT_LOG;
+
+/*!
+ * Cycle counting has to be enabled in the cycle counting configuration file
+ * If enabled then cycle counting related macros map to the cycle counting APIs.
+ * If not enabled, then the macros maps to a NOP
+ */
+#if defined(ADI_CYCLECOUNT_ENABLED) && (ADI_CYCLECOUNT_ENABLED == 1u)
+
+  #define ADI_CYCLECOUNT_INITIALIZE()        adi_cyclecount_init()      /*!< Initialize the cycle counting data structures */
+  #define ADI_CYCLECOUNT_STORE(id)          adi_cyclecount_store(id)    /*!< Record the number of cycles for the specified ISR or API */
+  #define ADI_CYCLECOUNT_REPORT()           adi_cyclecount_report()     /*!< Generate a cycle counting report */
+
+#else
+
+  #define ADI_CYCLECOUNT_INITIALIZE()       do{}while(0)      /*!< Initialize the cycle counting data structures */
+  #define ADI_CYCLECOUNT_STORE(id)          do{}while(0)      /*!< Record the number of cycles for the specified ISR or API */
+  #define ADI_CYCLECOUNT_REPORT()           do{}while(0)      /*!< Generate a cycle counting report */
+#endif
+
+
+/* Forward API declarations */
+extern ADI_CYCLECOUNT_RESULT  adi_cyclecount_start(void);
+extern ADI_CYCLECOUNT_RESULT  adi_cyclecount_stop(void);
+extern adi_cyclecount_t       adi_cyclecount_get(void);
+extern ADI_CYCLECOUNT_RESULT  adi_cyclecount_store(uint32_t id);
+extern void                   adi_cyclecount_init(void);
+extern void                   adi_cyclecount_report(void);
+extern ADI_CYCLECOUNT_RESULT  adi_cyclecount_addEntity(const char *EntityName, uint32_t *pid);
+
+/**@}*/
+
+#endif /* ADI_CYCLECOUNT_H */
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_processor.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_processor.h
new file mode 100755
index 00000000000..3032a13ac10
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_processor.h
@@ -0,0 +1,67 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_processor.h
+ * @brief:   Include appropriate CMSIS device header.
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef __ADI_PROCESSOR_H__
+#define __ADI_PROCESSOR_H__
+
+/* Default to ADuCM4050 if no processor macro is defined. */
+
+#if !defined(__ADUCM4050__)
+  #define __ADUCM4050__
+#endif
+
+/* Define a family macro */
+
+#if !defined(__ADUCM4x50__)
+  #define __ADUCM4x50__
+#endif
+
+/* Include CMSIS device header for selected target processor. */
+
+#if defined(__ADUCM4050__)
+#include <ADuCM4050.h>
+#endif
+
+#endif /* __ADI_PROCESSOR_H__ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_types.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_types.h
new file mode 100755
index 00000000000..ca221b8360a
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_types.h
@@ -0,0 +1,18 @@
+#ifndef __ADI_TYPES_H__
+#define __ADI_TYPES_H__
+
+/* obtain integer types ... */
+#include <stdint.h>
+
+/* obtain boolean types ... */
+#include <stdbool.h>
+
+/* define required types that are not provided by stdint.h or stdbool.h ... */
+typedef bool                bool_t;
+typedef char                char_t;
+typedef float               float32_t;
+#if !defined(__NO_FLOAT64)
+typedef long double         float64_t;
+#endif
+
+#endif /* __ADI_TYPES_H__ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_version.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_version.h
new file mode 100755
index 00000000000..6dd08f49bb7
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_version.h
@@ -0,0 +1,63 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_version.h
+ * @brief:   Version macros for ADI ADuCMxxx Device Series
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+	THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+	EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+	TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+	NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+	INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+	(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+	PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+	OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+	THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+	NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+	EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef __ADI_VERSION_H__
+#define __ADI_VERSION_H__
+
+/* use a 32-bit versioning scheme that supports numerical compares */
+#define ADI_VERSION_MAJOR     1u     /* must be <= 255 */
+#define ADI_VERSION_MINOR     0u     /* must be <= 255 */
+#define ADI_VERSION_BUILD     0u     /* must be <= 255 */
+#define ADI_VERSION_PATCH     0u     /* must be <= 255 */
+
+#define ADI_CONSTRUCT_VERSION(a,b,c,d)  (((a) << 24u) | ((b) << 16u) | ((c) << 8u) | (d))
+
+/* known versions */
+#define ADI_VERSION_1_0_0_0   ADI_CONSTRUCT_VERSION(1u,0u,0u,0u)
+
+/* test current version against known predefines (see SystemInit() example in system.c) */
+#define ADI_VERSION_CURRENT   ADI_CONSTRUCT_VERSION(ADI_VERSION_MAJOR, ADI_VERSION_MINOR, ADI_VERSION_BUILD, ADI_VERSION_PATCH)
+
+#endif /* __ADI_VERSION_H__ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/beep/adi_beep.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/beep/adi_beep.c
new file mode 100755
index 00000000000..0d0054c432e
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/beep/adi_beep.c
@@ -0,0 +1,751 @@
+/*! *****************************************************************************
+ * @file:    adi_beep.c
+ * @brief:   BEEP device driver global file.
+ * @details: This a global file which includes a specific file based on the processor family.
+ *           This included file will be  containing  BEEP device driver functions.
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#include <adi_processor.h>
+
+#include <stddef.h>
+#include <assert.h>
+
+#include <drivers/beep/adi_beep.h>
+#include <rtos_map/adi_rtos_map.h>
+#include "adi_beep_def.h"
+
+/** @addtogroup BEEP_Driver BEEP Driver
+ *  @{
+ * @brief Beeper Driver
+ * @note The application must include drivers/beep/adi_beep.h to use this driver.
+ */
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
+*   This isn't a header as such.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit.
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function.
+*   Multiple returns are used for error handling.
+*
+* Pm050 (rule 14.2): a null statement shall only occur on a line by itself
+*   Needed for null expansion of ADI_INSTALL_HANDLER and others.
+*
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   Required for MMR addresses and callback parameters.
+*
+* Pm031: (MISRA C 2004 rule 12.7)  bitwise operations shall not be performed on signed integer types
+*    Required for MMR manipulations.
+* 
+* Pm152: (MISRA C 2004 rule 17.4)  array indexing shall only be applied to objects defined as an array type  
+*    Required for adi_beep_PlaySequence() to access the user-supplied array of notes.
+* 
+* Pm141: (MISRA C 2004 rule 11.4) a cast should not be performed between a pointer to object type and a 
+*     different pointer to object type, this casts from type.
+*    Required to store a an array of varying size in a device structure. 
+* 
+*    Required for adi_beep_PlaySequence() to access the user-supplied array of notes.
+*/
+#pragma diag_suppress=Pm123,Pm073,Pm143,Pm050,Pm140,Pm031,Pm152,Pm141
+#endif /* __ICCARM__ */
+
+/*==========  D A T A  ==========*/
+static ADI_BEEP_DRIVER adi_beep_Device[1];
+
+/*! \cond PRIVATE */
+/* Handler for the BEEP interrupt */
+void Beep_Int_Handler(void);
+
+/* debug handle checker */
+#ifdef ADI_DEBUG
+#define ADI_BEEP_INVALID_HANDLE(h) (&adi_beep_Device[0] != (h))
+#endif
+
+/* definition for the BEEP IRQ - there is only ever one instance of the 
+ * BEEP driver, so reducing space by using a #define rather than including
+ * it in the device structure. */
+#define BEEP_IRQ (BEEP_EVT_IRQn)
+
+#if ADI_BEEP_CFG_SEQUENCE_REPEAT_VALUE == 0
+/* A single note is requested.  Only enable the AEND int. */
+#define INTERRUPT_ON_SEQEND  (0)
+#define INTERRUPT_ON_AEND    (1)
+#else
+/* A two-tone sequence is requested.  Only enable the SEQEND int. */
+#define INTERRUPT_ON_SEQEND  (1)
+#define INTERRUPT_ON_AEND    (0)
+#endif
+
+/*! \endcond */
+
+static const ADI_BEEP_STATIC_INIT gBeeperStaticConfigData[ADI_BEEP_MAX_DEVID] = {
+	/* single instance of Beeper device */
+	{
+		/* configuration register */
+		( (INTERRUPT_ON_SEQEND                             << BITP_BEEP_CFG_SEQATENDIRQ)
+		| (INTERRUPT_ON_AEND                               << BITP_BEEP_CFG_AENDIRQ)
+		| (ADI_BEEP_CFG_SEQUENCE_REPEAT_VALUE              << BITP_BEEP_CFG_SEQREPEAT)
+		),
+
+		/* Status register (interrupt clears) */
+		(ADI_BEEP_ALL_INTERRUPTS),
+
+		/* ToneA control register */
+		( ((uint32_t)ADI_BEEP_TONEA_DISABLE                << BITP_BEEP_TONEA_DIS)
+		| ((uint32_t)ADI_BEEP_TONEA_FREQUENCY              << BITP_BEEP_TONEA_FREQ)
+		| ((uint32_t)ADI_BEEP_TONEA_DURATION               << BITP_BEEP_TONEA_DUR)
+		),
+
+		/* ToneB control register */
+		( ((uint32_t)ADI_BEEP_TONEB_DISABLE                << BITP_BEEP_TONEB_DIS)
+		| ((uint32_t)ADI_BEEP_TONEB_FREQUENCY              << BITP_BEEP_TONEB_FREQ)
+		| ((uint32_t)ADI_BEEP_TONEB_DURATION               << BITP_BEEP_TONEB_DUR)
+		)
+	}
+};
+
+/*! \endcond */
+
+
+/*!
+ *  @brief BEEP Initialization
+ *
+ *  @param[in] DeviceNum    Integer specifying the ID of Beeper to use.
+ *  @param[in] pMemory      Pointer to the memory to be used by the driver.
+ *                          Size of the memory should be at least #ADI_BEEP_MEMORY_SIZE bytes.
+ *  @param[in] MemorySize   Size of the memory passed in pMemory parameter.
+ *  @param[out] phDevice    Pointer to a location that the device data pointer
+ *                          will be written upon successful initialization.
+ *
+ *  @return    Status
+ *             - #ADI_BEEP_SUCCESS                  Success: BEEP device driver initialized successfully.
+ *             - #ADI_BEEP_SEMAPHORE_FAILED         The BEEP sempahore could not be created.
+ *             - #ADI_BEEP_ALREADY_INITIALIZED [D]  The BEEP is already initialized.
+ *             - #ADI_BEEP_NULL_PTR [D]              Null pointer.
+ *             - #ADI_BEEP_BAD_DEV_ID [D]           The device number is invalid.
+ *
+ *  Initialize the BEEP device for use.  The core NVIC BEEP interrupt is enabled.  This API
+ *  must preceed all other beeper API calls and the handle returned must be passed to all other beeper API
+ *  calls.
+ *
+ *
+ *  @note      The contents of \a phDevice will be set to NULL upon failure.\n\n
+ *
+ *  @note      The BEEP device driver will clear all pending interrupts and disable all beeper
+ *             interrupts during beeper device initialization.
+ *
+ *  @note      CALLBACKS: If a callback is registered, it will be called on 
+ *             completion of the note or sequence. The "Event" parameter will
+ *             contain which event occurred, either ADI_BEEP_INTERRUPT_SEQUENCE_END
+ *             or ADI_BEEP_INTERRUPT_NOTE_END.
+ *
+ *  @warning   This API will put the beeper in preconfigured mode as defined in 
+ *             adi_beep_config.h file.
+ *             Refer adi_beep_config.h file to see which all features can be preconfigured.
+ *
+ *  @sa    adi_beep_Close().
+ */
+ADI_BEEP_RESULT adi_beep_Open(ADI_BEEP_DEV_ID          const DeviceNum,
+                              void*                    const pMemory,
+                              uint32_t                 const MemorySize,
+                              ADI_BEEP_HANDLE*         const phDevice)
+{
+    ADI_BEEP_DRIVER    *pDevice;
+    ADI_BEEP_DEV_DATA  *pData;
+    /* store a bad handle in case of failure */
+    *phDevice = (ADI_BEEP_HANDLE) NULL;
+
+#ifdef ADI_DEBUG
+    if (DeviceNum >= ADI_BEEP_MAX_DEVID)
+    {
+        return ADI_BEEP_BAD_DEV_ID;
+    }
+
+    if (pMemory == NULL)
+    {
+        return ADI_BEEP_NULL_PTR;
+    }
+    
+    assert (MemorySize >= sizeof(ADI_BEEP_DRIVER));
+#endif
+
+    /* local pointer to instance data */
+    pDevice = &adi_beep_Device[DeviceNum];
+    pDevice->pReg = pADI_BEEP0;
+    pDevice->pData = (ADI_BEEP_DEV_DATA*)pMemory;
+    pData = pDevice->pData;
+
+#ifdef ADI_DEBUG
+    if (ADI_BEEP_STATE_UNINITIALIZED != adi_beep_Device[DeviceNum].pData->state)
+    {
+        return ADI_BEEP_ALREADY_INITIALIZED;
+    }
+#endif
+
+    pData->cbFunc  = NULL;
+    pData->cbParam = NULL;
+    SEM_CREATE(pDevice->pData, "BEEP_SEM", ADI_BEEP_SEMAPHORE_FAILED);
+    
+    /* set statically configured initialization data */
+    ADI_BEEP_STATIC_INIT const* pInitData = &gBeeperStaticConfigData[DeviceNum];
+    ADI_BEEP_TypeDef   *pReg = pDevice->pReg;
+
+    pReg->CFG   = pInitData->BEEP_CFG;
+    pReg->STAT  = pInitData->BEEP_STAT;
+    pReg->TONEA = pInitData->BEEP_TONEA;
+    pReg->TONEB = pInitData->BEEP_TONEB;
+
+    /* enable beeper interrupts in NVIC */
+    NVIC_EnableIRQ(BEEP_IRQ);
+
+    /* mark driver initialized */
+    pData->state = ADI_BEEP_STATE_INITIALIZED;
+
+    /* store handle at application handle pointer */
+    *phDevice = (ADI_BEEP_HANDLE)pDevice;
+            
+    return ADI_BEEP_SUCCESS;            /* initialized */
+}
+
+
+/*!
+ * @brief  Uninitialize and deallocate a BEEP device.
+ *
+* @param[in]   hDevice    Device handle obtained from #adi_beep_Open().
+ *
+ * @return      Status
+ *                - #ADI_BEEP_SUCCESS                Success: Call completed successfully.
+ *                - #ADI_BEEP_BAD_DEV_HANDLE [D]     Error: Invalid device handle parameter.
+ *                - #ADI_BEEP_NOT_INITIALIZED [D]    Error: Device has not been initialized for use, see #adi_beep_Open().
+ *
+ * Uninitialize and release an allocated BEEP device for other use.  The core NVIC BEEP interrupt is disabled.
+ *
+ * @sa        adi_beep_Open().
+ */
+ADI_BEEP_RESULT adi_beep_Close(ADI_BEEP_HANDLE const hDevice)
+{
+
+    ADI_BEEP_DRIVER    *pDevice;
+    ADI_BEEP_DEV_DATA  *pData;
+    ADI_BEEP_TypeDef   *pReg;
+
+    pDevice = (ADI_BEEP_DRIVER*)hDevice;
+    pData = pDevice->pData;
+    pReg =  pDevice->pReg;
+
+#ifdef ADI_DEBUG
+    if (ADI_BEEP_INVALID_HANDLE(hDevice))
+	{
+          return ADI_BEEP_BAD_DEV_HANDLE;
+	}
+    if (ADI_BEEP_STATE_UNINITIALIZED == pData->state)
+	{
+          return ADI_BEEP_NOT_INITIALIZED;
+	}
+#endif
+
+    /* uninitialize */
+    NVIC_DisableIRQ(BEEP_IRQ);
+
+    pData->state     = ADI_BEEP_STATE_UNINITIALIZED;
+    pData->cbFunc    = NULL;
+    pReg->CFG   = 0u;
+    pReg->STAT  = 0u;
+    pReg->TONEA = 0u;
+    pReg->TONEB = 0u;
+    SEM_DELETE(pDevice->pData, ADI_BEEP_SEMAPHORE_FAILED);
+    return ADI_BEEP_SUCCESS;
+}
+
+/*!
+ * @brief  Register a callback for the beeper driver.
+ *
+ * @param[in]  hDevice        Device handle obtained from #adi_beep_Open().
+ * @param[in]  pfCallback     The application supplied callback which will be called to notify device
+ *                            related events.  
+ * @param[in]  pCBParam       The application supplied callback parameter which can be passed back in
+ *                            the callback function.
+ *
+ * @return      Status
+ *                - #ADI_BEEP_SUCCESS                Call completed successfully.
+ *                - #ADI_BEEP_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_BEEP_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_beep_Open().
+ *
+ * Registers a callback for the beeper interrupts.  When an interrupt occurs, the 
+ * driver will handle any required interaction with the hardware and then call 
+ * the registered callback. 
+ *
+ * @sa        adi_beep_Open().
+ */
+ADI_BEEP_RESULT adi_beep_RegisterCallback(ADI_BEEP_HANDLE const hDevice, 
+                                          ADI_CALLBACK          pfCallback,
+                                          void* const           pCBParam)
+{
+    ADI_BEEP_DRIVER    *pDevice = (ADI_BEEP_DRIVER*)hDevice;
+        
+    ADI_INT_STATUS_ALLOC();   
+ 
+#ifdef ADI_DEBUG
+    if (ADI_BEEP_INVALID_HANDLE(hDevice)) {
+        return ADI_BEEP_BAD_DEV_HANDLE;
+    }
+    
+    if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) {
+        return ADI_BEEP_NOT_INITIALIZED;
+    }
+#endif
+    /* Assign the callback within a critical region. */
+    ADI_ENTER_CRITICAL_REGION();        
+    pDevice->pData->cbFunc  = pfCallback;
+    pDevice->pData->cbParam = pCBParam;    
+    ADI_EXIT_CRITICAL_REGION();
+    
+    return ADI_BEEP_SUCCESS; 
+}
+
+
+#if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1
+/*!
+ * @brief  Play a beeper tone sequence.
+ *
+ * @param[in]   hDevice       Device handle obtained from #adi_beep_Open().
+ * @param[in]   aSequence     The sequence of notes to be played by the beeper.
+ * @param[in]   count         The number of notes in the sequence, must be a multiple
+ *                            of two, and a maximum size of 254 notes.
+ *
+ * @return      Status
+ *                - #ADI_BEEP_SUCCESS                Success: Call completed successfully.
+ *                - #ADI_BEEP_INVALID_COUNT          Sequence count must be multiples of two.
+ *                - #ADI_BEEP_NULL_PTR [D]           Null pointer.
+ *                - #ADI_BEEP_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_BEEP_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_beep_Open().
+ *
+ * Programs the A/B tone pair to play a sequence of notes.  The sequnce can be 
+ * stopped by calling adi_beep_Enable(..., false).  The beeper will be enabled
+ * and disabled internally by the driver. This code, and supporting data, can
+ * be removed by setting ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 0 in the 
+ * adi_beep_config.h configuration file.
+ *
+ * @sa        adi_beep_Open().
+ * @sa        adi_beep_Enable()
+ */
+ADI_BEEP_RESULT adi_beep_PlaySequence(ADI_BEEP_HANDLE const hDevice, 
+                                      ADI_BEEP_NOTE aSequence[], 
+                                      uint8_t count)
+{
+    ADI_BEEP_DRIVER    *pDevice = (ADI_BEEP_DRIVER*)hDevice;
+    ADI_BEEP_TypeDef   *pReg    = pDevice->pReg;
+    uint16_t           nSeqCnt = 0u;
+    
+    ADI_INT_STATUS_ALLOC();
+    
+#ifdef ADI_DEBUG
+    if (ADI_BEEP_INVALID_HANDLE(hDevice)) {
+        return ADI_BEEP_BAD_DEV_HANDLE;
+    }
+    
+    if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) {
+        return ADI_BEEP_NOT_INITIALIZED;
+    }
+    
+    if (NULL == aSequence) {
+        return ADI_BEEP_NULL_PTR;
+    }
+    
+    /* The sequence count must be a multiple of two, be greater than 1 
+     * and must be a maximum of (127 * 2) notes in length.  The hardware supports a 
+     * sequence of up to 127, and there are two notes associated with that. */
+    if (((127u * 2u) < count) || 
+        ((count % 2u) != 0u)  ||
+        (count < 2u)) {
+        return ADI_BEEP_INVALID_COUNT;
+    }
+#endif
+
+    /* Two notes are loaded at a time, and the sequence count refers to 
+     * the number of times that both tone registers should be played. */
+    nSeqCnt = ((uint16_t)count) >> 1u;
+    
+    ADI_ENTER_CRITICAL_REGION();
+
+    /* make a hole, and disable the beeper */
+    pReg->CFG &= (uint16_t)~(BITM_BEEP_CFG_SEQREPEAT | BITM_BEEP_CFG_AENDIRQ | BITM_BEEP_CFG_EN);
+
+    pReg->TONEA =  (  (uint16_t)((uint16_t)aSequence[0].frequency << ADI_BEEP_TONE_FREQ_BITPOS)
+                   |(uint16_t)((uint16_t)aSequence[0].duration << ADI_BEEP_TONE_DUR_BITPOS)   );
+   
+    pReg->TONEB =  (  (uint16_t)((uint16_t)aSequence[1].frequency << ADI_BEEP_TONE_FREQ_BITPOS)
+                   |(uint16_t)((uint16_t)aSequence[1].duration << ADI_BEEP_TONE_DUR_BITPOS)   );
+    
+
+    /* program new sequence count, while preserving everything else */
+    pReg->CFG |= (BITM_BEEP_CFG_EN | 
+                  BITM_BEEP_CFG_BSTARTIRQ | 
+                  BITM_BEEP_CFG_SEQATENDIRQ | 
+                  (uint16_t)((uint16_t)(nSeqCnt) << BITP_BEEP_CFG_SEQREPEAT));
+
+    pDevice->pData->pSeqArray  = (ADI_BEEP_NOTE(*)[])aSequence; 
+    pDevice->pData->nSeqMax    = count;
+    pDevice->pData->nSeqIndex  = 2u;  
+    
+    /* We're now playing, but not blocked */
+    pDevice->pData->state |= (ADI_BEEP_STATE_PLAYING);
+    
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_BEEP_SUCCESS;
+}
+#endif
+
+/*!
+ * @brief  Play a single note/beep.
+ *
+* @param[in]   hDevice       Device handle obtained from #adi_beep_Open().
+ * @param[in]   note          The note to play.
+ *
+ * @return      Status
+ *                - #ADI_BEEP_SUCCESS                Success: Call completed successfully.
+ *                - #ADI_BEEP_BAD_DEV_HANDLE [D]     Error: Invalid device handle parameter.
+ *                - #ADI_BEEP_NOT_INITIALIZED [D]    Error: Device has not been initialized for use, see #adi_beep_Open().
+ *
+ * Programs the A tone to play a single note.
+ *
+ * @sa        adi_beep_Open().
+ */
+ADI_BEEP_RESULT adi_beep_PlayNote(ADI_BEEP_HANDLE const hDevice, 
+                                  ADI_BEEP_NOTE   note)
+{
+    ADI_BEEP_DRIVER    *pDevice;
+    ADI_BEEP_TypeDef   *pReg;
+    ADI_INT_STATUS_ALLOC();
+    
+    pDevice = (ADI_BEEP_DRIVER*)hDevice;
+    pReg = pDevice->pReg;
+
+#ifdef ADI_DEBUG
+    if (ADI_BEEP_INVALID_HANDLE(hDevice)) {
+        return ADI_BEEP_BAD_DEV_HANDLE;
+    }
+    
+    if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) {
+        return ADI_BEEP_NOT_INITIALIZED;
+    }
+#endif
+
+    ADI_ENTER_CRITICAL_REGION();
+
+    /* Clear any previous sequence setup, and disable the beeper */
+    pReg->CFG &= (uint16_t)~(BITM_BEEP_CFG_SEQREPEAT | BITM_BEEP_CFG_EN);
+
+    /* Set Tone A */
+    pReg->TONEA =  (  (uint16_t)((uint16_t)note.frequency << ADI_BEEP_TONE_FREQ_BITPOS)
+                   |(uint16_t)((uint16_t)note.duration << ADI_BEEP_TONE_DUR_BITPOS)   );
+
+    /* program new sequence count, while preserving everything else */
+    pReg->CFG |= (BITM_BEEP_CFG_EN | BITM_BEEP_CFG_AENDIRQ);
+    
+    /* We're now playing but not blocked */
+    pDevice->pData->state |= (ADI_BEEP_STATE_PLAYING);
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_BEEP_SUCCESS;
+}
+
+
+/*!
+ * @brief  Play a a repeating two-tone beep. Similar to an alarm.
+ *
+* @param[in]   hDevice       Device handle obtained from #adi_beep_Open().
+ * @param[in]   noteA         The note to play first.
+ * @param[in]   noteB         The note to play second.
+ * @param[in]   count         The number of times to repeat the two-note signal,
+ *                            maximum of 127.
+ * 
+ *
+ * @return      Status
+ *                - #ADI_BEEP_SUCCESS                Success: Call completed successfully.
+ *                - #ADI_BEEP_BAD_DEV_HANDLE [D]     Error: Invalid device handle parameter.
+ *                - #ADI_BEEP_NOT_INITIALIZED [D]    Error: Device has not been initialized for use, see #adi_beep_Open().
+ *
+ * Programs the beeper to play a repeating two-tone signal.
+ * The count argument refers to the number of iterations of both notes, not 
+ * just a single note.
+ *
+ * @sa        adi_beep_Open().
+ * @sa        adi_beep_PlayNote().
+ * @sa        adi_beep_PlayNSequence().
+ */
+ADI_BEEP_RESULT adi_beep_PlayTwoTone(ADI_BEEP_HANDLE const hDevice, 
+                                      ADI_BEEP_NOTE   noteA,
+                                      ADI_BEEP_NOTE   noteB,
+                                      uint8_t         count)
+{
+    ADI_BEEP_DRIVER    *pDevice;
+    ADI_BEEP_TypeDef   *pReg;
+    ADI_INT_STATUS_ALLOC();
+    
+    pDevice = (ADI_BEEP_DRIVER*)hDevice;
+    pReg = pDevice->pReg;
+
+#ifdef ADI_DEBUG
+    if (ADI_BEEP_INVALID_HANDLE(hDevice)) {
+        return ADI_BEEP_BAD_DEV_HANDLE;
+    }
+    
+    if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) {
+        return ADI_BEEP_NOT_INITIALIZED;
+    }
+#endif
+
+    ADI_ENTER_CRITICAL_REGION();
+
+    /* make a hole, and disable the beeper */
+    pReg->CFG &= (uint16_t)~(BITM_BEEP_CFG_SEQREPEAT | BITM_BEEP_CFG_AENDIRQ |BITM_BEEP_CFG_EN);
+
+    pReg->TONEA =  (  (uint16_t)((uint16_t)noteA.frequency << ADI_BEEP_TONE_FREQ_BITPOS)
+                   |(uint16_t)((uint16_t)noteA.duration << ADI_BEEP_TONE_DUR_BITPOS)   );
+
+    pReg->TONEB =  (  (uint16_t)((uint16_t)noteB.frequency << ADI_BEEP_TONE_FREQ_BITPOS)
+                   |(uint16_t)((uint16_t)noteB.duration << ADI_BEEP_TONE_DUR_BITPOS)   );
+    
+    /* program new sequence count, while preserving everything else */
+    pReg->CFG |= (BITM_BEEP_CFG_EN | BITM_BEEP_CFG_SEQATENDIRQ |(uint16_t)((uint16_t)count << BITP_BEEP_CFG_SEQREPEAT));
+
+    /* We're now playing but not blocked */
+    pDevice->pData->state |= (ADI_BEEP_STATE_PLAYING);
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_BEEP_SUCCESS;
+}
+
+/*!
+ * @brief  Enable or disable the beeper. Other APIs will automatically enable the beeper if required,
+ *         so this function is best used in the following situations:
+ *            - when only using static configuration, i.e. start playing the notes
+ *              set up in static adi_beep_config.h.  
+ *            - Otherwise, this can be used to stop the beeper during playback, 
+ *              when started from any other API.
+ *
+ * @param[in]   hDevice       Device handle obtained from #adi_beep_Open().
+ * @param[in]   bFlag         true to enable the device, false to stop playback.
+ *
+ * @return      Status
+ *                - #ADI_BEEP_SUCCESS                Success: Call completed successfully.
+ *                - #ADI_BEEP_BAD_DEV_HANDLE [D]     Error: Invalid device handle parameter.
+ *                - #ADI_BEEP_NOT_INITIALIZED [D]    Error: Device has not been initialized for use, see #adi_beep_Open().
+ *
+ * @sa        adi_beep_Open().
+ */
+ADI_BEEP_RESULT adi_beep_Enable(ADI_BEEP_HANDLE const hDevice, bool   const bFlag)
+{
+    ADI_BEEP_DRIVER    *pDevice;
+    ADI_BEEP_TypeDef   *pReg;
+    ADI_INT_STATUS_ALLOC();
+    
+    pDevice = (ADI_BEEP_DRIVER*)hDevice;
+    pReg = pDevice->pReg;
+
+#ifdef ADI_DEBUG
+    if (ADI_BEEP_INVALID_HANDLE(hDevice)) {
+        return ADI_BEEP_BAD_DEV_HANDLE;
+    }
+    
+    if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) {
+        return ADI_BEEP_NOT_INITIALIZED;
+    }
+#endif
+
+    ADI_ENTER_CRITICAL_REGION();
+
+    if (bFlag == true) {
+      /* All the registers should already be set - just enable the beep */
+      pReg->CFG |= BITM_BEEP_CFG_EN;
+      pDevice->pData->state |= (ADI_BEEP_STATE_PLAYING);
+    } 
+    else {
+      pReg->CFG &= (uint16_t)~(BITM_BEEP_CFG_EN);
+      pDevice->pData->state &= ~(ADI_BEEP_STATE_PLAYING);
+    }
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_BEEP_SUCCESS;
+}
+
+/*!
+ * @brief  Wait for the current playback to finish.  This is a blocking call,
+ *         that will not return until the current playback (if any) has finished.
+ *         If there is no current playback, it will return immediately.
+ *
+* @param[in]   hDevice       Device handle obtained from #adi_beep_Open().
+ *
+ * @return      Status
+ *                - #ADI_BEEP_SUCCESS                Success: Call completed successfully.
+ *                - #ADI_BEEP_FAILURE                Error: Semaphore failure.
+ *                - #ADI_BEEP_BAD_DEV_HANDLE [D]     Error: Invalid device handle parameter.
+ *                - #ADI_BEEP_NOT_INITIALIZED [D]    Error: Device has not been initialized for use, see #adi_beep_Open().
+ *
+ * @sa        adi_beep_Open().
+ */
+ADI_BEEP_RESULT adi_beep_Wait(ADI_BEEP_HANDLE const hDevice)
+{
+    ADI_BEEP_DRIVER    *pDevice;
+    bool               wait = false;
+    ADI_INT_STATUS_ALLOC();
+    
+    pDevice = (ADI_BEEP_DRIVER*)hDevice;
+
+#ifdef ADI_DEBUG
+    if (ADI_BEEP_INVALID_HANDLE(hDevice)) {
+        return ADI_BEEP_BAD_DEV_HANDLE;
+    }
+    
+    if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) {
+        return ADI_BEEP_NOT_INITIALIZED;
+    }
+#endif
+
+    ADI_ENTER_CRITICAL_REGION();
+    
+    if((pDevice->pData->state | ADI_BEEP_STATE_PLAYING) > 0u) {
+       /* We are going to pend on the semaphore, no matter what. */
+       pDevice->pData->state |= ADI_BEEP_STATE_BLOCKED;
+       wait = true;
+    }
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    if(wait == true) {
+       /* Wait for the completion interrupt to post */
+       SEM_PEND(pDevice->pData, ADI_BEEP_SEMAPHORE_FAILED);
+    }
+    
+    return ADI_BEEP_SUCCESS;
+}
+
+/*! \cond PRIVATE */
+
+/*! @brief  BEEP device driver interrupt handler.  Overrides weakly-bound 
+ *  default interrupt handler in the startup file. */
+void Beep_Int_Handler(void)
+{
+    ISR_PROLOG();    
+#if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1
+    ADI_BEEP_DEV_DATA  *pData;
+    ADI_BEEP_NOTE       noteA, noteB;
+#endif
+    ADI_BEEP_DRIVER *pDevice = &adi_beep_Device[ADI_BEEP_DEVID_0];  /* so far, there is only one BEEP, so this is safe */
+    ADI_BEEP_TypeDef *pReg = pDevice->pReg;
+    uint16_t          fired = ADI_BEEP_ALL_INTERRUPTS;
+    register uint16_t candidate;
+    
+    /* Make sure our driver is up and running. */
+    if (ADI_BEEP_STATE_UNINITIALIZED != pDevice->pData->state) {
+        
+        /* read both status and mask registers */
+        candidate = pReg->CFG & ADI_BEEP_ALL_INTERRUPTS;  /* Take the fired interrupts */
+        fired = candidate;                                /* ...and a copy. */
+        candidate = candidate & pReg->STAT;               /* ...and remove the unused set interrupt bits */
+        
+        /* From this driver's perspective, there are only two states
+         * to watch for - finished playing, or continuing the playing sequence.  
+         * Finished will be handled here. */
+        if((candidate & (BITM_BEEP_CFG_SEQATENDIRQ | BITM_BEEP_CFG_AENDIRQ)) > 0u) { 
+          
+          /* If we are blocked, unblock by posting the semaphore */
+          if((pDevice->pData->state | ADI_BEEP_STATE_BLOCKED) > 0u) {
+            SEM_POST(pDevice->pData);
+          }
+          
+          /* Reset the device playing status. */
+          pDevice->pData->state &= ~(ADI_BEEP_STATE_PLAYING | ADI_BEEP_STATE_BLOCKED);
+            
+          /* ...and disable the device. */
+          pReg->CFG &= (uint16_t)(~(BITM_BEEP_CFG_EN));
+          
+          /* forward the interrupt to the user if they are watching it and it has fired */
+          /* pass the interrupt as the event. */
+          if (pDevice->pData->cbFunc != NULL) {
+              pDevice->pData->cbFunc (pDevice->pData->cbParam, (uint32_t)candidate, NULL);
+          }
+        }
+            
+ #if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1
+        /* The second state is if we are playing a longer sequence, so this 
+         * interrupt may be to move the sequence along.  */
+        if ((BITM_BEEP_CFG_BSTARTIRQ & candidate) != 0u) {
+                
+               /* Get a local copy of data, to shorten the following code. */ 
+                pData = pDevice->pData;     
+                
+                /* If there's still data to play */
+                if(pData->nSeqIndex < pData->nSeqMax) {
+                  /* Move the sequence along.*/
+                  noteA = (*pData->pSeqArray)[pData->nSeqIndex];
+                  pData->nSeqIndex++;
+                  noteB = (*pData->pSeqArray)[pData->nSeqIndex];
+                  pData->nSeqIndex++;
+                  
+                  /* Any values written will not impact the current tones,
+                   * they will take effect after the current tone is completed */
+                  pReg->TONEA =  (  (uint16_t)((uint16_t)noteA.frequency << ADI_BEEP_TONE_FREQ_BITPOS)
+                                  | (uint16_t)((uint16_t)noteA.duration << ADI_BEEP_TONE_DUR_BITPOS)   );
+   
+                  pReg->TONEB =  (  (uint16_t)((uint16_t)noteB.frequency << ADI_BEEP_TONE_FREQ_BITPOS)
+                                  | (uint16_t)((uint16_t)noteB.duration << ADI_BEEP_TONE_DUR_BITPOS)   );
+                }
+        }
+#endif
+    }
+
+    /* clear the watched interrupt(s) that fired */
+    pReg->STAT |= (uint16_t)(fired & ADI_BEEP_ALL_INTERRUPTS);  /* only write allowed interrupt bits */
+    ISR_EPILOG();    
+}
+/*! \endcond */
+
+/*@}*/
+
+
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/beep/adi_beep_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/beep/adi_beep_def.h
new file mode 100755
index 00000000000..22e0b3a949c
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/beep/adi_beep_def.h
@@ -0,0 +1,128 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_beep_def.h
+ * @brief:   BEEP Device Driver definition
+ *-----------------------------------------------------------------------------
+ *
+ * Copyright (c) 2016 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright notice,
+ *   this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ *   this list of conditions and the following disclaimer in the documentation
+ *   and/or other materials provided with the distribution.
+ * - Modified versions of the software must be conspicuously marked as such.
+ * - This software is licensed solely and exclusively for use with processors
+ *   manufactured by or for Analog Devices, Inc.
+ * - This software may not be combined or merged with other code in any manner
+ *   that would cause the software to become subject to terms and conditions
+ *   which differ from those listed here.
+ * - Neither the name of Analog Devices, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ * - The use of this software may or may not infringe the patent rights of one
+ *   or more patent holders.  This license does not release you from the
+ *   requirement that you obtain separate licenses from these patent holders
+ *   to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+ * PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef _ADI_BEEP_DEF_H_
+#define _ADI_BEEP_DEF_H_
+
+/*! \cond PRIVATE */
+#include <drivers/beep/adi_beep.h>
+
+/*!
+ *****************************************************************************
+ * An interrupt mask covering all Beeper interrupts.
+ *****************************************************************************/
+#define ADI_BEEP_ALL_INTERRUPTS ( BITM_BEEP_CFG_SEQATENDIRQ         \
+                                | BITM_BEEP_CFG_SEQNEARENDIRQ    \
+                                | BITM_BEEP_CFG_BENDIRQ       \
+                                | BITM_BEEP_CFG_BSTARTIRQ     \
+                                | BITM_BEEP_CFG_AENDIRQ       \
+                                | BITM_BEEP_CFG_ASTARTIRQ)
+
+#define ADI_BEEP_TONE_DISABLE               (BITM_BEEP_TONEA_DIS)       /*!<  Beeper tone disable bit                          */
+
+#define ADI_BEEP_TONE_FREQ_BITPOS           (BITP_BEEP_TONEA_FREQ)      /*!<  Beeper tone frequency bitfield position          */
+#define ADI_BEEP_TONE_DUR_BITPOS            (BITP_BEEP_TONEA_DUR)       /*!<  Beeper tone duration bitfield position           */
+
+#define ADI_BEEP_TONE_FREQ_MASK             (BITM_BEEP_TONEA_FREQ)      /*!<  Beeper tone frequency bitfield mask              */
+#define ADI_BEEP_TONE_DUR_MASK              (BITM_BEEP_TONEA_DUR)       /*!<  Beeper tone duration bitfield mask               */
+
+/*!
+ *****************************************************************************
+ * ADI_BEEP_STATE
+ *
+ * BEEP driver state.  Used for internal tracking of the BEEP device initialization
+ * progress during the adi_beep_Open().  Also used to insure the BEEP device has been
+ * properly initialized as a prerequisite to using the balance of the BEEP API.
+ *
+ *****************************************************************************/
+typedef uint8_t ADI_BEEP_STATE;
+#define ADI_BEEP_STATE_UNINITIALIZED  0u               /*!< BEEP is not initialized.              */
+#define ADI_BEEP_STATE_INITIALIZED    (1u << 1u)       /*!< BEEP is initialized.                  */
+#define ADI_BEEP_STATE_PLAYING        (1u << 2u)       /*!< BEEP is currently playing.            */
+#define ADI_BEEP_STATE_BLOCKED        (1u << 3u)       /*!< BEEP has blocked, waiting completion. */
+
+/*!
+ * \struct ADI_BEEP_DEV_DATA
+ * Beeper device internal instance data structure.
+ */
+typedef struct _ADI_BEEP_DEV_DATA
+{
+    volatile ADI_BEEP_STATE   state;          /*!< Device state                */
+    ADI_CALLBACK              cbFunc;         /*!< Callback function           */
+    void                      *cbParam;       /*!< Callback parameter          */
+#if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1
+    ADI_BEEP_NOTE             (*pSeqArray)[];   /*!< Pointer to a user-allocated array of notes. */
+    volatile uint8_t            nSeqIndex;      /*!< Index for incrementing sequence */
+    uint8_t                     nSeqMax;        /*!< Size of the sequence */
+#endif
+    SEM_VAR_DECLR      
+} ADI_BEEP_DEV_DATA;
+
+
+/*! \struct ADI_BEEP_DRIVER_STRUCT
+ *  BEEP Device Structure
+ */
+typedef struct _ADI_BEEP_DRIVER_STRUCT
+{
+    ADI_BEEP_TypeDef   *pReg;          /*!< Pointer to register base           */
+    ADI_BEEP_DEV_DATA  *pData;         /*!< Pointer to device data structure   */  
+} ADI_BEEP_DRIVER_STRUCT;
+
+/*! \struct ADI_BEEP_STATIC_INIT
+ *  conditionally create static initialization data based on adi_beep_config.h settings
+ */
+typedef struct {
+	uint16_t BEEP_CFG;   /*!< Beeper configuration register */
+	uint16_t BEEP_STAT;  /*!< Beeper status register */
+	uint16_t BEEP_TONEA; /*!< Beeper ToneA register */
+	uint16_t BEEP_TONEB; /*!< Beeper ToneB register */
+} ADI_BEEP_STATIC_INIT;
+
+/* alias for the actual device structure */
+typedef ADI_BEEP_DRIVER_STRUCT      ADI_BEEP_DRIVER;
+
+/*! \endcond */
+
+#endif /* _ADI_BEEP_DEF_H_ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/common.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/common.h
new file mode 100755
index 00000000000..e35f0bd8c2a
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/common.h
@@ -0,0 +1,127 @@
+/*!
+ *****************************************************************************
+ * @file:    common.h
+ * @brief:   Common include file for all example 
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+
+#ifndef COMMON_H
+#define COMMON_H
+
+#ifdef __ICCARM__
+/*
+* Pm106 (rule 20.9): the input/output library <stdio.h> shall not be used in
+                     production code
+*   The purpose of this header is to provide I/O facilities based on stdio.
+*/
+#pragma diag_suppress=Pm106
+#endif /* __ICCARM__ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <string.h>
+
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm011 (rule 6.3): The basic types of char, int, short, long, float shall not be used.
+* Pm064 (rule 16.1): functions with variable number of arguments shall not be used.
+*/
+#pragma diag_suppress=Pm011,Pm064
+#endif /* __ICCARM__ */
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Enable REDIRECT_OUTPUT_TO_UART to send the output to UART terminal. */
+/* #define REDIRECT_OUTPUT_TO_UART */
+
+extern char aDebugString[150]; 
+
+#ifdef __ICCARM__
+/*
+* Pm154 (rule 19.10): in the definition of a function-like macro, each instance
+*                     of a parameter shall be enclosed in parentheses
+*   The __VA_ARGS__ macro cannot be enclosed in parentheses.
+*/
+#pragma diag_suppress=Pm154
+#endif /* __ICCARM__ */
+
+#define DEBUG_MESSAGE(...) \
+  do { \
+    sprintf(aDebugString,__VA_ARGS__); \
+    common_Perf(aDebugString); \
+  } while(0)
+
+#ifdef __ICCARM__
+#pragma diag_default=Pm154
+#endif /* __ICCARM__ */
+
+#define DEBUG_RESULT(s,result,expected_value) \
+  do { \
+    if ((result) != (expected_value)) { \
+      sprintf(aDebugString,"%s  %d", __FILE__,__LINE__); \
+      common_Fail(aDebugString); \
+      sprintf(aDebugString,"%s Error Code: 0x%08X\n\rFailed\n\r",(s),(result)); \
+      common_Perf(aDebugString); \
+      exit(0); \
+    } \
+  } while (0)
+
+/********************************************************************************
+* API function prototypes
+*********************************************************************************/
+void common_Init(void);
+void common_Pass(void);
+void common_Fail(char *FailureReason);
+void common_Perf(char *InfoString);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* COMMON_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_adc_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_adc_config.h
new file mode 100755
index 00000000000..733f75771c6
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_adc_config.h
@@ -0,0 +1,342 @@
+/*!
+ *****************************************************************************
+   @file:    adi_adc_config.h
+   @brief:   Configuration options for ADC driver.
+             This is specific to the ADC driver and will be included by the driver.
+             It is not required for the application to include this header file.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_ADC_CONFIG_H
+#define ADI_ADC_CONFIG_H
+#include <adi_global_config.h>
+/** @defgroup ADC_Driver_Cfg Static Configuration
+ *  @ingroup ADC_Driver
+ */
+
+/** @addtogroup ADC_Driver_Cfg Static Configuration
+*  @{
+*/
+
+/************* ADC Driver configurations ***************/
+
+
+/*! Configure the default ADC configuration. Oversampling support must be enabled for resolution >12-bits.\n
+    Valid values are 12 to 16
+*/    
+#define ADI_ADC_CFG_RESOLUTION                               (12)
+
+/*! Configure the default Vref\n
+    3 - External Reference
+    2 - Battery Voltage
+    1 - 2.5V  Internal Reference\n
+    0 - 1.25V Internal Reference\n
+
+*/    
+#define ADI_ADC_CFG_VREF                                      (1)
+
+/*! Enable/Disable MULTI acquisitions of ADC data.
+    When enabled, DMA will be used for ADC readings which is
+    the preferred transfer method for multiple transactions.
+    Otherwise all will be interrupt driven. \n
+    1 - Enable MULTI (DMA) acquisitions \n
+    0 - Disable MULTI (use Interrupt) acquisitions \n
+*/ 
+#define ADI_ADC_ENABLE_MULTI_ACQUIRE              (1)
+
+/*! Enable/Disable HI/LO Digital Comparator limits \n
+    1 - Enable HI/LO Digital Comparator limits\n
+    0 - Disable HI/LO Digital Comparator limits\n
+*/    
+#define ADI_ADC_ENABLE_STATIC_COMPARATOR           (1)
+
+/*! Enable/Disable Channel0 limit comparator \n
+    1 - Enable HI Digital Comparator limit\n
+    0 - Disable HI Digital Comparator limit\n
+*/
+#define ADI_ADC_COMPARATOR_AIN0_HI_EN              (0)    /* 0 or 1 */
+
+/*! Set the Channel0 limit comparator value \n
+    Sets the HI limit value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN0_HI_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN0_HI_VAL             (4095) /* Range: 0 to 4095 */
+
+/*! Enable/Disable Channel0 limit comparator \n
+    1 - Enable LO Digital Comparator limit\n
+    0 - Disable LO Digital Comparator limit\n 
+*/
+#define ADI_ADC_COMPARATOR_AIN0_LO_EN              (1)    /* 0 or 1 */
+
+/*! Set the Channel0 limit comparator value. \n
+    Sets the LO limit value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN0_LO_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN0_LO_VAL             (0)    /* Range: 0 to 4095 */
+
+/*! Enable/Disable Channel0 hysteresis and monitor cycles \n
+    1 - Enable hysteresis and monitor cycles\n
+    0 - Disable hysteresis and monitor cycles\n 
+*/
+#define ADI_ADC_COMPARATOR_AIN0_HYS_EN             (1)   /* 0 or 1 */
+
+/*! Set the Channel0 limit comparator hysteresis value. \n
+    Sets the hysteresis value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN0_HYS_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN0_HYS_VAL            (0)   /* 9 bits, 0 to 511 */
+
+/*! Set the Channel0 limit comparator hysteresis monitor value. \n
+    Sets the monitor value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN0_HYS_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN0_HYS_CYC            (0)   /* 3 bits, 0 to 7 */
+
+/*! Enable/Disable Channel1 limit comparator \n
+    1 - Enable HI Digital Comparator limit\n
+    0 - Disable HI Digital Comparator limit\n
+*/
+#define ADI_ADC_COMPARATOR_AIN1_HI_EN              (0)    /* 0 or 1 */
+
+/*! Set the Channel1 limit comparator value \n
+    Sets the HI limit value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN1_HI_EN is set to 1. \n
+*/
+#define ADI_ADC_COMPARATOR_AIN1_HI_VAL             (4095) /* Range: 0 to 4095 */
+
+/*! Enable/Disable Channel1 limit comparator \n
+    1 - Enable LO Digital Comparator limit\n
+    0 - Disable LO Digital Comparator limit\n 
+*/
+#define ADI_ADC_COMPARATOR_AIN1_LO_EN              (0)    /* 0 or 1 */
+
+/*! Set the Channel1 limit comparator value. \n
+    Sets the LO limit value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN1_LO_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN1_LO_VAL             (0)    /* Range: 0 to 4095 */
+
+/*! Enable/Disable Channel1 hysteresis and monitor cycles \n
+    1 - Enable hysteresis and monitor cycles\n
+    0 - Disable hysteresis and monitor cycles\n 
+*/
+#define ADI_ADC_COMPARATOR_AIN1_HYS_EN             (0)    /* 0 or 1 */
+
+/*! Set the Channel1 limit comparator hysteresis value. \n
+    Sets the hysteresis value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN1_HYS_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN1_HYS_VAL            (0)    /* 9 bits, 0 to 511 */
+
+/*! Set the Channel1 limit comparator hysteresis monitor value. \n
+    Sets the monitor value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN1_HYS_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN1_HYS_CYC            (0)    /* 3 bits, 0 to 7 */
+
+/*! Enable/Disable Channel2 limit comparator \n
+    1 - Enable HI Digital Comparator limit\n
+    0 - Disable HI Digital Comparator limit\n
+*/
+#define ADI_ADC_COMPARATOR_AIN2_HI_EN              (0)    /* 0 or 1 */
+
+/*! Set the Channel2 limit comparator value \n
+    Sets the HI limit value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN2_HI_EN is set to 1. \n
+*/
+#define ADI_ADC_COMPARATOR_AIN2_HI_VAL             (4095) /* Range: 0 to 4095 */
+
+/*! Enable/Disable Channel2 limit comparator \n
+    1 - Enable LO Digital Comparator limit\n
+    0 - Disable LO Digital Comparator limit\n 
+*/
+#define ADI_ADC_COMPARATOR_AIN2_LO_EN              (0)    /* 0 or 1 */
+
+/*! Set the Channel2 limit comparator value. \n
+    Sets the LO limit value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN2_LO_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN2_LO_VAL             (0)    /* Range: 0 to 4095 */
+
+/*! Enable/Disable Channel2 hysteresis and monitor cycles \n
+    1 - Enable hysteresis and monitor cycles\n
+    0 - Disable hysteresis and monitor cycles\n 
+*/
+#define ADI_ADC_COMPARATOR_AIN2_HYS_EN             (0)    /* 0 or 1 */
+
+/*! Set the Channel2 limit comparator hysteresis value. \n
+    Sets the hysteresis value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN2_HYS_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN2_HYS_VAL            (0)    /* 9 bits, 0 to 511 */
+
+/*! Set the Channel2 limit comparator hysteresis monitor value. \n
+    Sets the monitor value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN2_HYS_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN2_HYS_CYC            (0)    /* 3 bits, 0 to 7 */
+
+/*! Enable/Disable Channel3 limit comparator \n
+    1 - Enable HI Digital Comparator limit\n
+    0 - Disable HI Digital Comparator limit\n
+*/
+#define ADI_ADC_COMPARATOR_AIN3_HI_EN              (0)    /* 0 or 1 */
+
+/*! Set the Channel3 limit comparator value \n
+    Sets the HI limit value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN3_HI_EN is set to 1. \n
+*/
+#define ADI_ADC_COMPARATOR_AIN3_HI_VAL             (4095) /* Range: 0 to 4095 */
+
+/*! Enable/Disable Channel3 limit comparator \n
+    1 - Enable LO Digital Comparator limit\n
+    0 - Disable LO Digital Comparator limit\n 
+*/
+#define ADI_ADC_COMPARATOR_AIN3_LO_EN              (0)   /* 0 or 1 */
+
+/*! Set the Channel3 limit comparator value. \n
+    Sets the LO limit value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN3_LO_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN3_LO_VAL             (0)   /* Range: 0 to 4095 */
+
+/*! Enable/Disable Channel3 hysteresis and monitor cycles \n
+    1 - Enable hysteresis and monitor cycles\n
+    0 - Disable hysteresis and monitor cycles\n 
+*/
+#define ADI_ADC_COMPARATOR_AIN3_HYS_EN             (0)   /* 0 or 1 */
+
+/*! Set the Channel3 limit comparator hysteresis value. \n
+    Sets the hysteresis value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN3_HYS_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN3_HYS_VAL            (0)   /* 9 bits, 0 to 511 */
+
+/*! Set the Channel3 limit comparator hysteresis monitor value. \n
+    Sets the monitor value for the channel, only \n
+    relevant if ADI_ADC_COMPARATOR_AIN3_HYS_EN is set to 1.\n
+*/
+#define ADI_ADC_COMPARATOR_AIN3_HYS_CYC            (0)   /* 3 bits, 0 to 7 */
+   
+
+/************** Macro validation *****************************/
+
+#if (ADI_ADC_CFG_RESOLUTION < 12) || (ADI_ADC_CFG_RESOLUTION > 16)
+#error "ADI_ADC_CFG_RESOLUTION is invalid"
+#endif
+
+#if (ADI_ADC_CFG_VREF < 0) || (ADI_ADC_CFG_VREF > 3)
+#error "ADI_ADC_CFG_VREF is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN0_HI_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN0_HI_VAL > (4095))
+#error "ADI_ADC_COMPARATOR_AIN0_HI_VAL is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN1_HI_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN1_HI_VAL > (4095))
+#error "ADI_ADC_COMPARATOR_AIN1_HI_VAL is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN2_HI_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN2_HI_VAL > (4095))
+#error "ADI_ADC_COMPARATOR_AIN2_HI_VAL is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN3_HI_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN3_HI_VAL > (4095))
+#error "ADI_ADC_COMPARATOR_AIN3_HI_VAL is invalid"
+#endif
+
+
+#if (ADI_ADC_COMPARATOR_AIN0_LO_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN0_LO_VAL > (4095))
+#error "ADI_ADC_COMPARATOR_AIN0_LO_VAL is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN1_LO_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN1_LO_VAL > (4095))
+#error "ADI_ADC_COMPARATOR_AIN1_LO_VAL is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN2_LO_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN2_LO_VAL > (4095))
+#error "ADI_ADC_COMPARATOR_AIN2_LO_VAL is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN3_LO_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN3_LO_VAL > (4095))
+#error "ADI_ADC_COMPARATOR_AIN3_HI_VAL is invalid"
+#endif
+
+
+#if (ADI_ADC_COMPARATOR_AIN0_HYS_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN0_HYS_VAL > (511))
+#error "ADI_ADC_COMPARATOR_AIN0_HYS_VAL is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN1_HYS_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN1_HYS_VAL > (511))
+#error "ADI_ADC_COMPARATOR_AIN1_HYS_VAL is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN2_HYS_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN2_HYS_VAL > (511))
+#error "ADI_ADC_COMPARATOR_AIN2_HYS_VAL is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN3_HYS_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN3_HYS_VAL > (511))
+#error "ADI_ADC_COMPARATOR_AIN3_HYS_VAL is invalid"
+#endif
+
+
+#if (ADI_ADC_COMPARATOR_AIN0_HYS_CYC < (0)) || (ADI_ADC_COMPARATOR_AIN0_HYS_CYC > (7))
+#error "ADI_ADC_COMPARATOR_AIN0_HYS_CYC is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN1_HYS_CYC < (0)) || (ADI_ADC_COMPARATOR_AIN1_HYS_CYC > (7))
+#error "ADI_ADC_COMPARATOR_AIN1_HYS_CYC is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN2_HYS_CYC < (0)) || (ADI_ADC_COMPARATOR_AIN2_HYS_CYC > (7))
+#error "ADI_ADC_COMPARATOR_AIN2_HYS_CYC is invalid"
+#endif
+
+#if (ADI_ADC_COMPARATOR_AIN3_HYS_CYC < (0)) || (ADI_ADC_COMPARATOR_AIN3_HYS_CYC > (7))
+#error "ADI_ADC_COMPARATOR_AIN3_HYS_CYC is invalid"
+#endif
+
+
+
+
+/*! @} */
+
+#endif /* ADI_ADC_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_beep_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_beep_config.h
new file mode 100755
index 00000000000..a78814b0c72
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_beep_config.h
@@ -0,0 +1,164 @@
+/*!
+ *****************************************************************************
+   @file:    adi_beep_config.h
+   @brief:   Configuration options for BEEP driver.
+             This is specific to the BEEP driver and will be included by the driver.
+             It is not required for the application to include this header file.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_BEEP_CONFIG_H
+#define ADI_BEEP_CONFIG_H
+#include <adi_global_config.h>
+
+#ifdef __ICCARM__
+/* IAR MISRA C 2004 error suppressions.
+ *
+ * Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters.
+ *   IAR compiler supports longer identifiers.
+ */
+#pragma diag_suppress=Pm009
+#endif /* __ICCARM__ */
+
+/** @addtogroup BEEP_Driver_Config Static Configuration
+ *  @ingroup BEEP_Driver
+ *  @{
+ */
+
+/************* BEEP Driver configurations ***************/
+/*! Enable the inclusion of adi_beep_PlaySequence().  This    \n
+    API requires more data in the device structures to manage \n
+    the longer playing sequences, along with extra code in    \n
+    the interrupt handler.                                    \n
+    0 -  adi_beep_PlaySequence() omitted.\n
+    1 -  adi_beep_PlaySequence() is included. */
+#define ADI_BEEP_INCLUDE_PLAY_SEQUENCE                         1
+   
+/************* BEEP controller static configurations ***************/
+
+/*! Configure beeper disable.\n
+    0 -  Beeper enabled.\n
+    1 -  Beeper disabled. */
+#define ADI_BEEP_CFG_BEEPER_DISABLE                            0
+
+/*! Configure beeper sequence, when using static configuration. \n
+    0     -  Single note (Tone A only).\n
+    1-255 -  Sequence mode repeat count (Tone A then B sequentially). */
+#define ADI_BEEP_CFG_SEQUENCE_REPEAT_VALUE                     5
+
+
+/* TONEA CONTROL REGISTER */
+
+/*! Initial ToneA Disable.\n
+    0 -  ToneA Enabled.\n
+    1 -  ToneA Disabled. */
+#define ADI_BEEP_TONEA_DISABLE                                 0
+
+/*! Initial ToneA Frequency.\n
+    0-3   -  Rest Tone (no oscillation).\n
+    4-127 -  Oscillate at 32kHz/freq Hz. */
+#define ADI_BEEP_TONEA_FREQUENCY                               20
+
+/*! Initial ToneA Duration.\n
+    0-254 -  Play for 4ms*duration.\n
+    255   -  Play for infinite duration. */
+#define ADI_BEEP_TONEA_DURATION                                2
+
+
+
+/* TONEB CONTROL REGISTER */
+
+/*! Initial ToneB Disable.\n
+    0 -  ToneB Enabled.\n
+    1 -  ToneB Disabled. */
+#define ADI_BEEP_TONEB_DISABLE                                 0
+
+/*! Initial ToneB Frequency. \n
+    0-3   -  Rest Tone (no oscillation).\n
+    4-127 -  Oscillate at 32kHz/freq Hz. */
+#define ADI_BEEP_TONEB_FREQUENCY                               50
+
+/*! Initial ToneB Duration.\n
+    0-254 -  Play for 4ms*duration.\n
+    255   -  Play for infinite duration. */
+#define ADI_BEEP_TONEB_DURATION                                2
+
+
+
+#ifdef __ICCARM__
+/*
+* Pm085 (rule 19.11): identifiers in pre-processor directives should be defined before use
+*   The macros in the the following #if directives are defined to enum constants by default.
+*/
+#pragma diag_suppress=Pm085
+#endif /* __ICCARM__ */
+
+#if (ADI_BEEP_TONEA_DISABLE > 1)
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_BEEP_TONEA_FREQUENCY  > 127 )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_BEEP_TONEA_DURATION > 255 )
+#error "Invalid configuration"
+#endif
+
+#if (ADI_BEEP_TONEB_DISABLE > 1)
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_BEEP_TONEB_FREQUENCY > 127 )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_BEEP_TONEB_DURATION  >  255 )
+#error "Invalid configuration"
+#endif
+
+#ifdef __ICCARM__
+#pragma diag_default=Pm009,Pm085
+#endif /* __ICCARM__ */
+
+/*! @} */
+
+#endif /* ADI_BEEP_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_crc_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_crc_config.h
new file mode 100755
index 00000000000..19737e3a883
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_crc_config.h
@@ -0,0 +1,100 @@
+/*!
+ *****************************************************************************
+   @file:    adi_crc_config.h
+   @brief:   Configuration options for CRC driver.
+             This is specific to the CRC driver and will be included by the driver.
+             It is not required for the application to include this header file.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders. This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_CRC_CONFIG_H
+#define ADI_CRC_CONFIG_H
+
+#include <adi_global_config.h>
+
+/** @defgroup CRC_Driver_Cfg Static Configuration
+ *  @ingroup CRC_Driver
+ */
+
+/** @addtogroup CRC_Driver_Cfg Static Configuration
+*  @{
+*/
+
+/************* CRC Driver configurations ***************/
+/*!
+   Enable DMA support in the driver code.\n
+   1 -  To have the DMA support code in the driver.\n
+   0 -  To eliminate the DMA support. Operates in core mode.\n
+*/
+#define ADI_CRC_CFG_ENABLE_DMA_SUPPORT         0
+
+/*!
+   Enable Byte mirroring option\n
+   1 -  To enable byte mirroring \n
+   0 -  To disable the byte mirroring.
+*/
+#define ADI_CFG_CRC_ENABLE_BYTE_MIRRORING      0
+/*!
+   Enable Bit mirroring option\n
+   1 -  To enable bit mirroring \n
+   0 -  To disable the bit mirroring.
+*/
+#define ADI_CFG_CRC_ENABLE_BIT_MIRRORING       0
+
+/*!
+   To specify the seed value for CRC computation
+*/
+
+#define ADI_CFG_CRC_SEED_VALUE                 (0xFFFFFFFFu)
+
+/*!
+   To specify the polynomial to be used for CRC computation
+*/
+#define ADI_CFG_CRC_POLYNOMIAL                 (0x04C11DB7u)
+
+/*!
+   To specify the Software DMA channel to be used for the CRC computation
+   0 -> DMA channel SIP0, ..., 7 -> DMA channel SIP7
+*/
+#define ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID     7
+
+#endif /* ADI_CRC_CONFIG_H */
+/*! @} */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_crypto_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_crypto_config.h
new file mode 100755
index 00000000000..d67f6ab81c1
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_crypto_config.h
@@ -0,0 +1,138 @@
+/*!
+ *****************************************************************************
+   @file:    adi_crypto_config.h
+   @brief:   Configuration options for Crypto driver.
+             This is specific to the Crypto driver and will be included by the driver.
+             It is not required for the application to include this header file.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2014-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef __ADI_CRYPTO_CONFIG_H__
+#define __ADI_CRYPTO_CONFIG_H__
+#include <adi_global_config.h>
+
+/** @addtogroup Crypto_Driver_Config Static Configuration
+ *  @ingroup Crypto_Driver
+ *  @{
+ */
+
+/************* Crypto Driver configurations ***************/
+
+/*! Enable/Disable ECB Support\n
+    1 - Enable ECB Support\n
+    0 - Disable ECB Support\n
+*/
+#define ADI_CRYPTO_ENABLE_ECB_SUPPORT            (1)
+
+/*! Enable/Disable CTR Support\n
+    1 - Enable CTR Support\n
+    0 - Disable CTR Support\n
+*/
+#define ADI_CRYPTO_ENABLE_CTR_SUPPORT            (1)
+
+/*! Enable/Disable CBC Support\n
+    1 - Enable CBC Support\n
+    0 - Disable CBC Support\n
+*/
+#define ADI_CRYPTO_ENABLE_CBC_SUPPORT            (1)
+
+/*! Enable/Disable CCM Support\n
+    1 - Enable CCM Support\n
+    0 - Disable CCM Support\n
+*/
+#define ADI_CRYPTO_ENABLE_CCM_SUPPORT            (1)
+
+/*! Enable/Disable CMAC Support\n
+    1 - Enable CMAC Support\n
+    0 - Disable CMAC Support\n
+*/
+#define ADI_CRYPTO_ENABLE_CMAC_SUPPORT           (1)
+
+/*! Enable/Disable HMAC Support\n
+    1 - Enable HMAC Support\n
+    0 - Disable HMAC Support\n
+*/
+#define ADI_CRYPTO_ENABLE_HMAC_SUPPORT           (1)
+
+/*! Enable/Disable SHA Support\n
+    1 - Enable SHA Support\n
+    0 - Disable SHA Support\n
+*/
+#define ADI_CRYPTO_ENABLE_SHA_SUPPORT            (1)
+
+
+/*! Enable/Disable DMA Support\n
+    1 - Enable DMA Support\n
+    0 - Disable DMA Support
+*/
+#define ADI_CRYPTO_ENABLE_DMA_SUPPORT            (1)
+
+/*! Enable/Disable DMA Transfer by default\n
+    1 - Enable DMA \n
+    0 - Disable DMA
+*/
+#define ADI_CRYPTO_ENABLE_DMA                    (1)
+
+/*! SHA output format\n
+    1 - Big-Endian \n
+    0 - Little-Endian
+*/
+#define ADI_CRYPTO_SHA_OUTPUT_FORMAT             (1)
+
+
+
+/************** Macro validation *****************************/
+
+#if ((ADI_CRYPTO_ENABLE_DMA_SUPPORT != 0) && (ADI_CRYPTO_ENABLE_DMA_SUPPORT != 1))
+#error "ADI_CRYPTO_ENABLE_DMA_SUPPORT is invalid"
+#endif
+
+#if ((ADI_CRYPTO_ENABLE_DMA != 0) && (ADI_CRYPTO_ENABLE_DMA != 1))
+#error "ADI_CRYPTO_ENABLE_DMA is invalid"
+#endif
+
+#if ((ADI_CRYPTO_ENABLE_DMA == 1) && (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 0))
+#error "DMA cannot be enabled if DMA support is disabled"
+#endif
+
+/*! @} */
+
+#endif /* __ADI_CRYPTO_CONFIG_H__ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_cycle_counting_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_cycle_counting_config.h
new file mode 100755
index 00000000000..4b83c46fd7b
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_cycle_counting_config.h
@@ -0,0 +1,105 @@
+/*! *****************************************************************************
+ * @file    adi_cycle_counting_config.h
+ * @brief   Cycle Counting Framework configuration
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+
+#ifndef ADI_CYCLE_COUNTING_CONFIG_H
+#define ADI_CYCLE_COUNTING_CONFIG_H
+
+/** @addtogroup CYCLE_COUNTING_Config Static Configuration
+ *  @ingroup cyclecount_logging
+ *  @{
+ */
+
+
+/************* Cycle Counting Configuration ***************/
+
+/*! Global enable. This must be enabled for any other functionality to work\n
+    0u disabled
+	1u enabled
+*/
+#define ADI_CYCLECOUNT_ENABLED                          (0u)
+
+/*! SPI Interrupt Mode ISR Cycle Counting Enabled\n
+   0 -  Disables the recording of SPI ISR cycle counting.
+   1 -  Enables the recording of SPI ISR cycle counting.
+*/
+#define ADI_CYCLECOUNT_SPI_ISR_ENABLED                  (0u)
+
+
+/*! CRC Interrupt Mode ISR Cycle Counting Enabled\n
+   0 -  Disables the recording of CRC ISR cycle counting.
+   1 -  Enables the recording of CRC ISR cycle counting.
+*/
+#define ADI_CYCLECOUNT_CRC_ISR_ENABLED                  (0u)
+
+
+/*! SPORT Interrupt Mode ISR Cycle Counting Enabled\n
+   0 -  Disables the recording of SPORT ISR cycle counting.
+   1 -  Enables the recording of SPORT ISR cycle counting.
+*/
+#define ADI_CYCLECOUNT_SPORT_ISR_ENABLED                (0u)
+
+/*! UART Interrupt Mode ISR Cycle Counting Enabled\n
+   0 -  Disables the recording of UART ISR cycle counting.
+   1 -  Enables the recording of UART ISR cycle counting.
+*/
+#define ADI_CYCLECOUNT_UART_ISR_ENABLED                 (0u)
+
+
+/*! A user application may desire/require cycle counting in an application defined API
+    or ISR. Set this macro to the number of required.
+*/
+#define ADI_CYCLECOUNT_NUMBER_USER_DEFINED_APIS         (0u)
+
+/*!
+ * Cycle count 'stack' nesting depth. Adjust as needed.
+ * This should map to the maximum number of nested interrupts an application might experience.
+ */
+#define ADI_CYCLECOUNT_STACK_SIZE 10
+
+/**
+ *  @}
+ */
+
+#endif /* ADI_CYCLE_COUNTING_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_flash_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_flash_config.h
new file mode 100755
index 00000000000..5eb4e5a779f
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_flash_config.h
@@ -0,0 +1,299 @@
+/*!
+ *****************************************************************************
+   @file:    adi_flash_config.h
+   @brief:   Configuration options for flash driver.
+             This is specific to the flash driver and will be included by the driver.
+             It is not required for the application to include this header file.
+   @version: $Revision: 33205 $
+   @date:    $Date: 2016-01-11 05:46:07 -0500 (Mon, 11 Jan 2016) $
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_FLASH_CONFIG_H
+#define ADI_FLASH_CONFIG_H
+#include <adi_global_config.h>
+
+/** @addtogroup Flash_Driver_Config Static Configuration
+ *  @ingroup Flash_Driver
+ *  @{
+ */
+
+
+/****SETTINGS THAT LIVE IN FEE INTERRUPT ENABLE (IEN) REGISTER****/
+
+
+/*!
+ * Configure a response to the 2-bit ECC ERROR events (in IEN).
+ * - 0 Do not generate a response to ECC Error Events.
+ * - 1 Generate Bus Errors in response to ECC Error Events.
+ * - 2 Generate IRQs in response to ECC Error Events.
+ */
+#define ADI_FEE_CFG_ECC_ERROR_RESPONSE          (1u)
+/*!
+ * Configure a response to the 1-bit ECC CORRECTION events (in IEN).
+ * - 0 Do not generate a response to ECC correction Events.
+ * - 1 Generate Bus Errors in response to ECC correction Events.
+ * - 2 Generate IRQs in response to ECC correction Events.
+ */
+#define ADI_FEE_CFG_ECC_CORRECTION_RESPONSE     (2u)
+
+
+
+/****SETTINGS THAT LIVE IN FEE TIME PARAMETER 0 (TIME_PARAM0) REGISTER****/
+
+
+/* It is recommended to NOT MODIFY flash timing parameters without keen insight and caution */
+/*!
+ * Configure flash non-volatile mass erase hold time.\n
+ * Upper 4-bits of 11-bit value.\n
+ * (Lower bits are hard-coded to 0x14.)\n
+ * Hardware default value is 0xb.
+ */
+#define ADI_FEE_CFG_PARAM0_TNVH1          (0xbu)
+
+/*!
+ * Configure flash erase time.\n
+ * Upper 4-bits of 19-bit value.\n
+ * (Lower bits are hard-coded to 0x7370.)\n
+ * Hardware default value is 0x8.
+ */
+#define ADI_FEE_CFG_PARAM0_TERASE          (0x8u)
+
+/*!
+ * Configure flash recovery time.\n
+ * Upper 4-bits of 8-bit value.\n
+ * (Lower bits are hard-coded to 0x2.)\n
+ * Hardware default value is 0x9.
+ */
+#define ADI_FEE_CFG_PARAM0_TRCV          (0x9u)
+
+/*!
+ * Configure flash non-volatile hold time.\n
+ * Upper 4-bits of 8-bit value.\n
+ * (Lower bits are hard-coded to 0x1.)\n
+ * Hardware default value is 0x5.
+ */
+#define ADI_FEE_CFG_PARAM0_TNVH          (0x5u)
+
+/*!
+ * Configure flash program time.\n
+ * Upper 4-bits of 10-bit value.\n
+ * (Lower bits are hard-coded to 0x7.)\n
+ * Hardware default value is 0x0.
+ */
+#define ADI_FEE_CFG_PARAM0_TPROG          (0x0u)
+
+/*!
+ * Configure flash NVSTR-to-program setup time.\n
+ * Upper 4-bits of 8-bit value.\n
+ * (Lower bits are hard-coded to 0x2.)\n
+ * Hardware default value is 0x9.
+ */
+#define ADI_FEE_CFG_PARAM0_TPGS          (0x9u)
+
+/*!
+ * Configure flash program/erase-to-NVSTR setup time.\n
+ * Upper 4-bits of 8-bit value.\n
+ * (Lower bits are hard-coded to 0x1.)\n
+ * Hardware default value is 0x5.
+ */
+#define ADI_FEE_CFG_PARAM0_TNVS          (0x5u)
+
+/*!
+ * Configure flash reference clock divide-by-2 setting.\n
+ * All timing parameters are referenced to this parameter.
+ * - 0 Reference clock is not divided.
+ * - 1 Reference clock is divided by 2.\n
+ * Hardware default value is 0x0.
+ */
+#define ADI_FEE_CFG_PARAM0_CLKDIV          (0x0u)
+
+
+
+/****SETTINGS THAT LIVE IN FEE TIME PARAMETER 1 (TIME_PARAM1) REGISTER****/
+
+
+/* It is recommended to NOT MODIFY flash timing parameters without keen insight and caution */
+/*!
+ * Configure flash read access wait states.\n
+ * Number of 3-bit read access wait states to use.\n
+ * Maximum allowed value is 0x4.\n
+ * Hardware default value is 0x0.
+ */
+#define ADI_FEE_CFG_PARAM1_WAITESTATES          (0x0u)
+
+/*!
+ * Configure flash sleep mode wake-up time.\n
+ * Upper 4-bits of 8-bit value.\n
+ * (Lower bits are hard-coded to 0xb.)\n
+ * Hardware default value is 0x4.
+ */
+#define ADI_FEE_CFG_PARAM1_TWK          (0x4u)
+
+
+
+/****SETTINGS THAT LIVE IN FEE SYSTEM ABOUT ENABLE (ABOUT_EN_XX) REGISTERS****/
+
+
+/*!
+ * Configure lower (0-31) flash system interrupt abort enables.\n
+ * Allows system interrupts to abort an ongoing flash command.\n
+ * Only 64 system interrupts are supported.\n
+ * Lower interrupts (0-31) are encoded in ADI_FEE_CFG_ABORT_EN_LO,
+ * - 0 Corresponding interrupt is prevented from aborting flash command.
+ * - 1 Corresponding interrupt is allowed to abort flash command.\n
+ * Hardware default value is 0x0.
+ */
+#define ADI_FEE_CFG_ABORT_EN_LO          (0x0u)
+
+/*!
+ * Configure upper (32-63) flash system interrupt abort enables.\n
+ * Allows system interrupts to abort an ongoing flash command.\n
+ * Only 64 system interrupts are supported.\n
+ * Upper interrupts (32-63) are encoded in ADI_FEE_CFG_ABORT_EN_HI.
+ * - 0 Corresponding interrupt is prevented from aborting flash command.
+ * - 1 Corresponding interrupt is allowed to abort flash command.\n
+ * Hardware default value is 0x0.
+ */
+#define ADI_FEE_CFG_ABORT_EN_HI          (0x0u)
+
+
+
+/****SETTINGS THAT LIVE IN ECC CONFIG REGISTER (ECC_CFG) REGISTER****/
+
+
+/*!
+ * ECC Start Page Pointer (in ECC_CFG).
+ */
+#define ADI_FEE_CFG_ECC_START_PAGE              (0u)
+
+/*!
+ * Enable/Disable ECC for info space (in ECC_CFG).
+ * - 1 Enable Info Space.
+ * - 0 Disable Info Space.
+ */
+#define ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE   (0u)
+
+/*!
+ * Enable/Disable ECC (in ECC_CFG).
+ * - 1 Enable ECC.
+ * - 0 Disable ECC.
+ */
+#define ADI_FEE_CFG_ENABLE_ECC                  (0u)
+
+
+
+/************* Flash Driver Configuration Settings Checkers ***************/
+
+
+
+/* IEN CHECKS */
+#if ((ADI_FEE_CFG_ECC_ERROR_RESPONSE < 0u) || (ADI_FEE_CFG_ECC_ERROR_RESPONSE > 2u))
+#error "ADI_FEE_CFG_ECC_ERROR_RESPONSE should be in the range 0-2."
+#endif
+#if ((ADI_FEE_CFG_ECC_CORRECTION_RESPONSE < 0u) || (ADI_FEE_CFG_ECC_CORRECTION_RESPONSE > 2u))
+#error "ADI_FEE_CFG_ECC_CORRECTION_RESPONSE should be in the range 0-2."
+#endif
+
+
+
+/* PARAM0 CHECKS */
+#if ((ADI_FEE_CFG_PARAM0_TNVH1 < 0u) || (ADI_FEE_CFG_PARAM0_TNVH1 > 15u))
+#error "ADI_FEE_CFG_PARAM0_TNVH1 should be in the range 0-15."
+#endif
+#if ((ADI_FEE_CFG_PARAM0_TERASE < 0u) || (ADI_FEE_CFG_PARAM0_TERASE > 15u))
+#error "ADI_FEE_CFG_PARAM0_TERASE should be in the range 0-15."
+#endif
+#if ((ADI_FEE_CFG_PARAM0_TRCV < 0u) || (ADI_FEE_CFG_PARAM0_TRCV > 15u))
+#error "ADI_FEE_CFG_PARAM0_TRCV should be in the range 0-15."
+#endif
+#if ((ADI_FEE_CFG_PARAM0_TNVH1 < 0u) || (ADI_FEE_CFG_PARAM0_TNVH1 > 15u))
+#error "ADI_FEE_CFG_PARAM0_TNVH1 should be in the range 0-15."
+#endif
+#if ((ADI_FEE_CFG_PARAM0_TPROG < 0u) || (ADI_FEE_CFG_PARAM0_TPROG > 15u))
+#error "ADI_FEE_CFG_PARAM0_TPROG should be in the range 0-15."
+#endif
+#if ((ADI_FEE_CFG_PARAM0_TPGS < 0u) || (ADI_FEE_CFG_PARAM0_TPGS > 15u))
+#error "ADI_FEE_CFG_PARAM0_TPGS should be in the range 0-15."
+#endif
+#if ((ADI_FEE_CFG_PARAM0_TNVS < 0u) || (ADI_FEE_CFG_PARAM0_TNVS > 15u))
+#error "ADI_FEE_CFG_PARAM0_TNVS should be in the range 0-15."
+#endif
+#if ((ADI_FEE_CFG_PARAM0_CLKDIV < 0u) || (ADI_FEE_CFG_PARAM0_CLKDIV > 1u))
+#error "ADI_FEE_CFG_PARAM0_CLKDIV should be in the range 0-1."
+#endif
+
+
+
+/* PARAM1 CHECKS */
+#if ((ADI_FEE_CFG_PARAM1_WAITESTATES < 0u) || (ADI_FEE_CFG_PARAM1_WAITESTATES > 4u))
+#error "ADI_FEE_CFG_PARAM1_WAITESTATES should be in the range 0-4."
+#endif
+#if ((ADI_FEE_CFG_PARAM1_TWK < 0u) || (ADI_FEE_CFG_PARAM1_TWK > 15u))
+#error "ADI_FEE_CFG_PARAM1_TWK should be in the range 0-15."
+#endif
+
+
+
+/* ABORT_EN_XX CHECKS */
+#if ((ADI_FEE_CFG_ABORT_EN_LO < 0u) || (ADI_FEE_CFG_ABORT_EN_LO > 0XFFFFu))
+#error "ADI_FEE_CFG_ABORT_EN_LO should be in 32-bit range."
+#endif
+#if ((ADI_FEE_CFG_ABORT_EN_HI < 0u) || (ADI_FEE_CFG_ABORT_EN_HI > 0XFFFFu))
+#error "ADI_FEE_CFG_ABORT_EN_HI should be in 32-bit range."
+#endif
+
+
+
+/* ECC_CFG CHECKS */
+#if (((ADI_FEE_CFG_ECC_START_PAGE >> 8u) << 8) != ADI_FEE_CFG_ECC_START_PAGE)
+#error "ADI_FEE_CFG_ECC_START_PAGE has invalid  bits set in lower 8-bits."
+#endif
+#if ((ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE != 0u) && (ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE != 1u))
+#error "ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE should be 1 or 0."
+#endif
+#if ((ADI_FEE_CFG_ENABLE_ECC != 0u) && (ADI_FEE_CFG_ENABLE_ECC != 1u))
+#error "ADI_FEE_CFG_ENABLE_ECC should be 1 or 0."
+#endif
+
+/*! @} */
+
+#endif /* ADI_FLASH_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_global_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_global_config.h
new file mode 100755
index 00000000000..6d205577a3b
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_global_config.h
@@ -0,0 +1,131 @@
+/*!
+ *****************************************************************************
+   @file:    adi_global_config.h
+   @brief:   Configuration options for all the drivers.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_GLOBAL_CONFIG_H
+#define ADI_GLOBAL_CONFIG_H
+
+/** @addtogroup GLOBAL_Driver_Config Global Static Configuration
+ *  @brief   Configuration options for all the drivers.
+ *  @{
+ */
+
+/*! @name RTOS used
+ * In order to be used in a multi-threaded application, the device drivers
+ * may require the use of some RTOS-specific signals like semaphores or actions
+ * may be required when entering/exiting an interrupt. By specifying the RTOS
+ * that the application uses, the drivers can map their requirements to the
+ * specific RTOS, without requiring an OS abstraction layer.
+ * @note This macros do not add the RTOS sources to the application, users need
+ *       to set up the source and include paths in their application themselves
+ * @note If the RTOS specified is not in the list of supported RTOS the build
+ *       mechanism fails
+ */
+/**@{*/
+
+/*! @hideinitializer Indicates that no RTOS is used (bare-metal applications) */
+#define ADI_CFG_RTOS_NO_OS              (1)
+/*! @hideinitializer Indicates that Micrium uCOS-III is used  */
+#define ADI_CFG_RTOS_MICRIUM_III        (2)
+/*! @hideinitializer Indicates that Micrium FreeRTOS is used */
+#define ADI_CFG_RTOS_FREERTOS           (3)
+
+/*! Configure the RTOS required across the project.
+    It can be configured to one of the following macros:
+    - #ADI_CFG_RTOS_NO_OS
+    - #ADI_CFG_RTOS_MICRIUM_III
+    - #ADI_CFG_RTOS_FREERTOS
+ */
+#define ADI_CFG_RTOS    ADI_CFG_RTOS_NO_OS
+
+/**@}*/
+
+/*! @name Low power mode support
+    All applications may have to block when a buffer is being processed. In the
+    case of an RTOS application, when a task is blocked waiting for a buffer, a
+    different task can run. If no tasks are available then the idle task runs.
+    In many RTOS the idle task can be configured so it perform actions like
+    entering low power modes.
+
+    In the case of a bare-metal (no RTOS) application, since there are no other
+    tasks to be run, the driver can enter low power modes itself when it blocks.
+   */
+
+/*! Configures the drivers to enter low power mode (Flexi mode)
+    when waiting for a buffer to be processed. This macro is applicable
+    only when the drivers are operating in the bare metal mode (No RTOS).
+
+    The possible values it can be configured to are:
+
+    - 1 : Low power mode support required.
+    - 0 : Low power mode support not required.
+*/
+#define ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT      (1)
+/**@}*/
+
+
+
+/*
+** Verify the macro configuration
+*/
+#if ((ADI_CFG_RTOS != ADI_CFG_RTOS_NO_OS)       && \
+     (ADI_CFG_RTOS != ADI_CFG_RTOS_MICRIUM_III)  && \
+     (ADI_CFG_RTOS != ADI_CFG_RTOS_FREERTOS))
+#error "ADI_CFG_RTOS macro wrongly configured"
+#endif /* ADI_CFG_RTOS verification */
+
+#if ((ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT != 0) && \
+     (ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT != 1))
+#error "ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT macro is wrongly configured"
+#endif
+
+#if ((ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT == 1) && \
+     (ADI_CFG_RTOS != ADI_CFG_RTOS_NO_OS))
+#error "ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT cannot be set to 1 in multi-threaded applications"
+#endif
+/**
+ *  @}
+ */
+
+#endif /* ADI_GLOBAL_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_i2c_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_i2c_config.h
new file mode 100755
index 00000000000..0f6bbca875a
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_i2c_config.h
@@ -0,0 +1,226 @@
+/*!
+ *****************************************************************************
+   @file:    adi_i2c_config.h
+   @brief:   Configuration options for I2C driver.
+             This is specific to the I2C driver and will be included by the driver.
+             It is not required for the application to include this header file.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_I2C_CONFIG_H
+#define ADI_I2C_CONFIG_H
+#include <adi_global_config.h>
+
+/** @addtogroup I2C_Driver_Config Static Configuration
+ *  @ingroup I2C_Driver
+ *  @{
+ */
+
+/************* I2C Driver configurations ***************/
+
+/*! Master control register TX FIFO decrement control bit.\n
+    1 - Decrement master TX FIFO status when a byte has been fully serialized.\n
+    0 - Decrement master TX FIFO status when a byte is unloaded from the TX FIFO,
+        but not yet serialized on the bus. */
+#define ADI_I2C_CFG_MCTL_MXMITDEC               (0)
+
+/*! Master control register STOP condition interrupt enable.\n
+    1 - Enable completion interrupt when a STOP condition is detected.\n
+    0 - Disable completion interrupt when a STOP condition is detected. */
+#define ADI_I2C_CFG_MCTL_IENCMP                 (1)
+
+/*! Master control register NACK (NotACKnowledge) interrupt enable.\n
+    1 - Enable NACK interrupt when an acknowledge is not received.\n
+    0 - Disable NACK interrupt when an acknowledge is not received. */
+#define ADI_I2C_CFG_MCTL_IENACK                 (1)
+
+/*! Master control register ALOST (Arbitration LOST) interrupt enable.\n
+    1 - Enable ALOST interrupt when bus arbitration is lost.\n
+    0 - Disable ALOST interrupt when bus arbitration is lost. */
+#define ADI_I2C_CFG_MCTL_IENALOST               (1)
+
+/*! Master control register clock stretch enable.\n
+    1 - Enable clock stretch by slave device.\n
+    0 - Disable clock stretch by slave device. */
+#define ADI_I2C_CFG_MCTL_STRETCHSCL             (0)
+
+/*! Master control register internal loopback enable.\n
+    1 - Enable internal looping of SCL and SDA outputs onto their corresponding inputs.\n
+    0 - Disable internal looping of SCL and SDA outputs onto their corresponding inputs. */
+#define ADI_I2C_CFG_MCTL_LOOPBACK               (0)
+
+/*! Master control register start condition back-off disable.\n
+    1 - Enables controller to compete for bus ownership even if another device is driving a START condition.\n
+    0 - Disables controller to compete for bus ownership even if another device is driving a START condition. */
+#define ADI_I2C_CFG_MCTL_COMPLETE               (0)
+
+/*! Master control register device enable.\n
+    1 - Enable controller as a Master device.\n
+    0 - Disables controller as a Master device. */
+#define ADI_I2C_CFG_MCTL_MASEN                  (0)
+
+/*!
+ * Standard Clock divider Clock-HI settings.
+ * Assuming a 26 MHz core clock, the following settings
+ * will be useful:                                           \n
+ *     - For STANDARD (100 kHz) rate, use: HI= 25, LO= 31.   \n
+ *     - For FAST (400 kHz) rate, use:     HI=123, LO=129.   \n
+ *                                                           \n
+ * @note The clock high setting varies with pull-up loading,
+ * board layout, slew-rate, etc., so exact settings are somewhat
+ * empirical.  The clock high counter does not start until
+ * a logic high transition is sensed on the clock line, so
+ * variability in this logic transaction will alter the
+ * effective clock rate.  This results from the internal
+ * clock-stretch hardware feature supporting a slave slow device
+ * that may hold off the master by holding the clock line low.
+ *
+ * @sa ADI_I2C_CFG_DIV_LOW
+ */
+#define ADI_I2C_CFG_DIV_HIGH                    (25)
+
+/*! Standard Clock divider Clock-LO setting
+ *
+ * @sa ADI_I2C_CFG_DIV_HIGH
+ */
+#define ADI_I2C_CFG_DIV_LOW                     (31)
+
+/*! Shared control reset START/STOP detect circuit.\n
+    1 - Reset the SCL and SDA synchronizers, START/STOP detect logic, and LINEBUSY detect logic.\n
+    0 - Do nothing. */
+#define ADI_I2C_CFG_SHCTL_RST                   (0)
+
+/*! Timing control filter disable.\n
+    1 - Disable digital input clock filter.\n
+    0 - Enable digital input clock filter (1 PCLK). */
+#define ADI_I2C_CFG_TCTL_FILTEROFF              (0)
+
+/*! Timing control data input hold time requirement to recognize START/STOP condition (5-bit max).\n
+    Value - Minimum data input hold time count in units of PCLK period.  (Value = Thd/PCLK-period) */
+#define ADI_I2C_CFG_TCTL_THDATIN                (1)
+
+/*! Master automatic stretch mode duration (4-bit), e.g., (in binary):\n
+    - 0b0000 - No SCL clock stretching.\n
+    - 0b0001 - Timeout after hold SCL LOW 2^1 = 2 bit-times.\n
+    - 0b0010 - Timeout after hold SCL LOW 2^2 = 4 bit-times.\n
+    - ...\n
+    - 0b1110 - Timeout after hold SCL LOW 2^14 = 16,384 bit-times.\n
+    - 0b1111 - Hold SCL LOW with no timeout.\n
+\n
+    Where "bit-time" is computed by CLKDIV values and incoming UCLK (see HRM). */
+#define ADI_I2C_CFG_ASTRETCH_MST                (0)
+
+/*! Unformatted, 7-bit max width I2C "7-bit Addressing" slave device address value (unshifted and excluding R/W direction bit).\n
+    For example, the value:\n
+        0x50 - Is the "raw" (unencoded) slave address for the "Aardvark Activity Board" ATMEL AT24C02 I2C slave EEPROM device.\n
+            It is encoded (upshifted by one and ORed with R/W direction bit) on the I2C bus as:\n
+                - 0xA0 for write operations, or\n
+                - 0xA1 for read operations */
+#define ADI_I2C_CFG_SLAVE_ADDRESS              (0x50)
+
+
+/***********************************\
+|* Check for overflowing values... *|
+\***********************************/
+
+#if (ADI_I2C_CFG_MCTL_MXMITDEC >> 1)
+#error "Decrement TX FIFO status config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_MCTL_IENCMP >> 1)
+#error "Transaction complete (STOP) interrupt enable config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_MCTL_IENACK >> 1)
+#error "NACK interrupt enable config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_MCTL_IENALOST >> 1)
+#error "ALOST interrupt enable config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_MCTL_STRETCHSCL >> 1)
+#error "Clock stretch enable config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_MCTL_LOOPBACK >> 1)
+#error "Loopback enable config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_MCTL_COMPLETE >> 1)
+#error "Start back-off disable config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_MCTL_MASEN >> 1)
+#error "Master device enable config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_DIV_HIGH >> 8)
+#error "Clock HIGH time config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_DIV_LOW >> 8)
+#error "Clock LOW time config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_SHCTL_RST >> 1)
+#error "Shared control reset config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_TCTL_FILTEROFF >> 1)
+#error "Timing control filter-off config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_TCTL_THDATIN >> 5)
+#error "Timing control filter-off config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_ASTRETCH_MST >> 4)
+#error "Master clock stretch config value too wide"
+#endif
+
+#if (ADI_I2C_CFG_SLAVE_ADDRESS >> 7)
+#error "Slave address config value too wide"
+#endif
+
+/*! @} */
+
+#endif /* ADI_I2C_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_pwr_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_pwr_config.h
new file mode 100755
index 00000000000..11207b99478
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_pwr_config.h
@@ -0,0 +1,638 @@
+/*
+ *****************************************************************************
+   @file:    adi_pwr_config.h
+   @brief:   Configuration options for PWR driver.
+             This is specific to the PWR driver and will be included by the source file.
+             It is not required for the application to include this header file.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_PWR_CONFIG_H
+#define ADI_PWR_CONFIG_H
+#include <adi_global_config.h>
+#ifdef __ICCARM__
+/* IAR MISRA C 2004 error suppressions.
+*
+* Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters.
+*   The YODA-generated headers rely on more. The IAR compiler supports that.
+*/
+#pragma diag_suppress=Pm009
+#endif /* __ICCARM__ */
+
+/** @addtogroup PWR_Driver_Config Static Configuration
+ *  @ingroup Power_Driver
+ *  @{
+ */
+
+/*! Enable the code to support input clock through the GPIO pin
+    0 - No support for input clock through the GPIO pin.
+    1 - Support for input clock through the GPIO pin.
+
+*/
+#define ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO                    0
+
+/*-------------------------------------------------------------------------------
+           Set of MACROs for configuring the clock
+--------------------------------------------------------------------------------*/
+/* Oscillator Control Register */
+
+/*!
+    32 KHz clock select mux.  This clock connects to beeper, RTC.\n
+   0 -  Internal 32 KHz oscillator is selected.\n
+   1 -  External 32 KHz crystal is selected..
+*/
+#define ADI_PWR_LF_CLOCK_MUX                                    0
+
+
+/*!
+    High frequency internal oscillator enable\n
+   0 -  The HFOSC oscillator is disabled and placed in a low power state\n
+   1 -  The HFOSC oscillator is enabled.
+*/
+#define ADI_PWR_HFOSC_CLOCK_ENABLE                              1
+
+/*!
+   Low  frequency external oscillator enable and placed in a low power state\n
+   0 -  The LFXTAL oscillator is disabled\n
+   1 -  The LFXTAL oscillator is enabled.
+*/
+#define ADI_PWR_LFXTAL_CLOCK_ENABLE                             0
+
+/*!
+    High frequency external  oscillator enable\n
+   0 -  The HFXTAL  oscillator is disabled and placed in a low power state\n
+   1 -  The HFXTAL  oscillator is enabled.
+*/
+#define ADI_PWR_HFXTAL_CLOCK_ENABLE                              0
+
+/*!
+   Low frequency external clock fail interrupt enable \n
+   0 -  The LFXTAL clock monitor and clock fail interrupt disabled \n
+   1 -  The LFXTAL clock monitor and clock fail interrupt enabled.
+*/
+#define ADI_PWR_LFXTAL_CLOCK_MON_ENABLE                         0
+
+/*!
+   Automatic switching of the LF Mux to LF Oscillator on LFXTAL failure.  \n
+   0 -  Disables Automatic switching of LF Mux to LF Oscillator on LFXTAL failure \n
+   1 -  Disables Automatic switching of LF Mux to LF Oscillator on LFXTAL failure.
+*/
+#define ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE                  0
+
+/*!
+   Low frequency crystal Robust mode enable. The Robust mode enables the LFXTAL oscillator to work also when an
+   additional resistive load is placed between the crystal pins and GND. \n
+   0 -  Selects Normal mode \n
+   1 -  Selects Robust mode
+*/
+#define ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE                       0
+
+/*!
+   Low frequency crystal Robust mode load select. The amount of loading tolerated when robust mode is enabled. \n
+   0 -  No Trim, and big resistive loads not tolerated. \n
+   1 -  20 Mohm load mode, greater than 20 Mohm load allowed. \n
+   2 -  10 Mohm load mode, greater than 10 Mohm load allowed. \n
+   3 -  5 Mohm load mode, 5 Mohm load allowed on both IO pins.
+*/
+#define ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT                       0
+
+
+/*!
+   Root clock monitor and Clock Fail interrupt enable.
+   0 - Disable Root Clock Monitor and Clock Fail interrupt.
+   1 - Enable Root Clock Monitor and Clock Fail interrupt.
+*/
+#define ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE                       0
+
+
+/*!
+   Enable Auto switch to High Frequency Oscillator (HFOSC) when Root Clock Fails.
+   0 - Disable Automatic switching of the Root Clock.
+   1 - Enable Automatic switching of the Root Clock.
+*/
+#define ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE               0
+
+
+/********** Miscellaneous clock setting register CTL0 *************/
+
+/*!
+    Selecting the input clock for  Root Clock mux.  Determines which single shared clock source
+    is used by the PCLK,  and HCLK dividers. \n
+    0 -  HFOSC High frequency internal oscillator \n
+    1 -  HFXTAL High frequency external oscillator\n
+    2 -  SPLL  Output of System PLL is selected\n
+    3 -  External GPIO port is selected
+*/
+#define ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX                         0
+
+/*!
+    GPIO clock out select. Selects the clock to be routed to the GPIO clock out pin. \n
+    0  -  Root Clock (ROOT_CLK)\n
+    1  -  Low Frequency Clock (LF_CLK) \n
+    2  -  ADC Clock (ACLK) \n
+    3  -  HCLK_BUS \n
+    4  -  HCLK_CORE \n
+    5  -  Peripheral Clock (PCLK)
+    6  -  Reference Clock for Flash controller timer (RCLK)\n
+    7  -  Mux of HFOSC, HFXTAL clock (RHP_CLK)\n
+    8  -  GP Timer 0 clock (GPT0_CLK)\n
+    9  -  GP Timer 1 clock (GPT1_CLK)\n
+    10 -  Peripherals operating at HCLK (HCLK_P)\n
+    11 -  PLL Clock out (PCLK)\n
+    12 -  RTC0 Clock \n
+    13 -  HP Buck Clock (HPBUCK_CLK)\n
+    14 -  HP Buck Non overlap clock\n
+    15 -  RTC1 generated clock
+*/
+#define ADI_PWR_GPIO_CLOCK_OUT_SELECT                           0
+
+/*!
+    Flash reference clock and HPBUCK clock source mux.  \n
+    0 -  sourcing from HFOSC (High frequency internal oscillator) \n
+    2 -  sourcing from external HFXTAL(  High frequency external oscillator 26M Hz )\n
+    3 -  sourcing from external HFXTAL(  High frequency external oscillator 16M Hz )
+
+*/
+#define ADI_PWR_INPUT_TO_RCLK_MUX                               0
+
+/*!
+    Selecting the input clock for the system PLL clock.  \n
+    0 -  sourcing from  HFOSC (High frequency internal oscillator) \n
+    1 -  sourcing from  HFXTAL(High frequency external oscillator) \n
+    2 -  GPIO Input clock. \n
+    3 -  GPIO Input clock.
+*/
+#define ADI_PWR_INPUT_TO_SPLL_MUX                               0
+
+/*!
+    External Low frequency crystal interrupt enable.\n
+    0 -  Disable the interrupt for LF clock \n
+    1 -  Enable the interrupt for LF clock
+*/
+#define ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE                   0
+
+/*!
+    External Hight frequency crystal interrupt enable.\n
+    0 -  Disable the interrupt for HFXTAL clock \n
+    1 -  Enable the interrupt for  HFXTAL clock
+*/
+#define ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE                    0
+
+
+
+/********** Clock divider register CTL1 ***************/
+
+/*!
+    HCLK divide count.Determines the HCLK rate based on the following equation: HCLK = ROOT_CLK/HCLKDIVCNT.
+    0 - 63 is valid range.
+*/
+#define ADI_PWR_HCLK_DIVIDE_COUNT                               4
+
+/*!
+    PCLK divide count.Determines the PCLK rate based on the following equation: PCLK = ROOT_CLK/PCLKDIVCNT.
+    0 - 63 is valid range.
+*/
+#define ADI_PWR_PCLK_DIVIDE_COUNT                               4
+
+/*!
+    ACLK divide count.Determines the ACLK rate based on the following equation: ACLK = ROOT_CLK/ACLKDIVCNT.
+    0 - 63 is valid range.
+*/
+#define ADI_PWR_ACLK_DIVIDE_COUNT                               16
+
+
+/************* HF Oscillator divide clock select register CTL2 ***********/
+
+/*!
+    HF Oscillator auto divide by one clock selection during wakeup from Flexi power mode.
+
+    When enabled enabled (Set to 1), the frequency undivided 26MHz HF oscillator clock itself will be used during the wake up.
+    The undivided HFOSC clock is selected automatically by clearing  the HFOSCDIVCLKSEL register content to 0, which selects the HFOSC/1 clock.This updated divided by 1 clock selection will remain same until the new divider value is written to this register.
+
+    When disabled (Set to 0), this fast wake up feature will be disabled and the HFOSCDIVCLKSEL register will remain unchanged
+    during the wakeup.
+
+    0 -  Auto select HFOSC/1 clock during wakeup from Flexi mode is disable.
+    1 -  Auto select HFOSC/1 clock during wakeup from Flexi mode is enabled.
+*/
+#define ADI_PWR_HFOSC_AUTO_DIV_BY_1                              0
+
+/*!
+    HF Oscillator divide select.
+    0 -  HFOSC/1. \n
+    1 -  HFOSC/2. \n
+    2 -  HFOSC/4. \n
+    3 -  HFOSC/8. \n
+    4 -  HFOSC/16. \n
+    5 -  HFOSC/32.
+*/
+#define ADI_PWR_HFOSC_DIVIDE_SELECT                              0
+
+
+
+/****** System PLL Register CTL3 *****/
+/*!
+    System PLL N multiplier(SPLL_NSEL).  Sets the N value used to obtain the multiplication
+    factor N/M of the PLL.
+    8 - 31 is valid range.
+*/
+#define ADI_PWR_SPLL_MUL_FACTOR                                 26
+
+/*!
+    System PLL division by 2.  Controls if an optional divide by two is placed on the PLL output.\n
+    0 -  The System PLL is not divided. Its output frequency equals that selected by the N/M ratio \n
+    1 -  The System PLL is divided by two. Its output frequency equals that selected by the N/M ratio
+         with an additional divide by 2
+*/
+#define ADI_PWR_SPLL_ENABLE_DIV2                                0
+
+/*!
+    System PLL enable.  Controls if the PLL should be enabled or placed in its low power state. \n
+    0 - The system PLL is disabled and is in its power down state\n
+    1 - The system  PLL is enabled.
+*/
+#define ADI_PWR_SPLL_ENABLE                                     0
+
+/*!
+    System PLL interrupt enable.Controls if the core should be interrupted on a PLL lock/PLL unlock or no interrupt generated.\n
+    0 - Disable the SPLL interrupt generation\n
+    1 - Enable the SPLL interrupt generation
+*/
+#define ADI_PWR_SPLL_INTERRUPT_ENABLE                           0
+
+/*!
+    System PLL M Divider(SPLL_MSEL).  Sets the M value used to obtain the multiplication
+    factor N/M of the PLL.
+    2 - 15 is valid range.
+*/
+#define ADI_PWR_SPLL_DIV_FACTOR                                 13
+
+/*!
+    system PLL multiply by 2.  This bit is used to configure if the VCO clock frequency should be multiplied by 2 or 1.\n
+    0 -  The System PLL is multiplied by 1.\n
+    1 -  The System PLL is multiplied by 2.
+*/
+#define ADI_PWR_SPLL_ENABLE_MUL2                                0
+
+
+/********** User Clock Gating Control CTL5 ********************/
+
+/*!
+    This can be  used to enable/disable clock to GPT0.  \n
+    0 - Disable  the clock to GPT0\n
+    1 - Enable the clock to GPT0
+*/
+#define ADI_PWR_GPT0_CLOCK_ENABLE                               1
+
+/*!
+    This can be  used to enable/disable clock to GPT1.  \n
+    0 - Disable  the clock to GPT1\n
+    1 - Enable the clock to   GPT1
+*/
+#define ADI_PWR_GPT1_CLOCK_ENABLE                               1
+/*!
+    This can be  used to enable/disable clock to GPT2.  \n
+    0 - Disable  the clock to GPT2\n
+    1 - Enable the clock to   GPT2
+*/
+#define ADI_PWR_GPT2_CLOCK_ENABLE                               1
+
+/*!
+    This can be  used to enable/disable clock to I2C.  \n
+    0 - Disable  the clock to I2C\n
+    1 - Enable the clock to   I2C
+*/
+#define ADI_PWR_I2C_CLOCK_ENABLE                                1
+
+/*!
+    This can be used to enable/disable clock to GPIO.  \n
+    0 - Disable the clock to GPIO\n
+    1 - Enable the clock to  GPIO
+*/
+#define ADI_PWR_GPIO_CLOCK_ENABLE                               1
+
+
+/*!
+    This can be used to enable/disable all clocks connected to peripherals.  \n
+    0 - Disable  the Clock supply to  peripherals\n
+    1 - Enable the Clock supply to  peripherals
+*/
+#define ADI_PWR_PCLK_ENABLE                                     0
+
+
+/*!
+    This can be used to enable/disable clocks to Timer RGB.  \n
+    0 - Disable the Clock supply to Timer RGB \n
+    1 - Enable the Clock supply to Timer RGB
+*/
+#define ADI_PWR_TIMER_RGB_ENABLE                                 1
+
+/*-------------------------------------------------------------------------------
+           Set of macros for configuring the power management module
+--------------------------------------------------------------------------------*/
+
+/********* Interrupt enable register IEN ********/
+
+/*!
+    Enabling the interrupt if the  Battery  voltage falls below 1.8V.\n
+   0 -  Disable Battery voltage interrupt \n
+   1 -  Enable Battery voltage interrupt.
+*/
+#define ADI_PWR_ENABLE_VBAT_INTERRUPT                           0
+
+/*!
+    Enabling the interrupt for under VREG voltage (i.e less than 1V).\n
+   0 -  Disable VREG under voltage  interrupt \n
+   1 -  Enable VREG under voltage  interrupt.
+*/
+#define ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT             0
+
+/*!
+    Enabling the interrupt for over  VREG voltage (i.e above  than 1.32V).\n
+   0 -  Disable VREG over  voltage  interrupt \n
+   1 -  Enable VREG  over voltage  interrupt.
+*/
+#define ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT              0
+
+/*!
+    Enabling the interrupt for Battery range.\n
+   0 -  Disable battery voltage range  interrupt \n
+   1 -  Enable battery voltage range  interrupt
+*/
+#define ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT          0
+
+/*!
+    Battery voltage range for generating the interrupt.\n
+   0 - Configure to generate interrupt if VBAT > 2.75V \n
+   1 - Configure to generate interrupt if VBAT is between 2.75 and 1.6V  \n
+   2 - Configure to generate interrupt if VBAT is between 2.3V and 1.6V
+*/
+#define ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT             0
+
+/********* HP Buck control register CTL1 ********/
+/*!
+    Enable or disable HP Buck.\n
+    0 - Disable HP Buck.
+    1 - Enable HP Buck.
+*/
+#define ADI_PWR_HP_BUCK_ENABLE                                  0
+
+/*!
+    HP Buck Load mode.\n
+    0 - HP Buck low load mode. Can be set when the system is running at
+        less than 26 Mhz. \n
+    1 - HP Buck High load mode. Can be set when the system is running at
+        more than 26 Mh.
+*/
+#define ADI_PWR_HP_BUCK_LOAD_MODE                               0
+
+/*!
+    HP Buck low power mode.\n
+    The HPBUCK Low Power mode can be selected, when the  Chip is in Flexi Power mode
+    and low power modules such as Timer, Beeper only are enabled
+
+    0 - HPBUCK Low power mode is disabled. \n
+    1 - HPBUCK Low power mode is enabled.
+*/
+#define ADI_PWR_HP_BUCK_LOW_POWER_MODE                           0
+
+
+/********* Power mode register ********/
+
+/*!
+    Enable or disable monitoring battery voltage (VBAT) during HIBERNATE Mode. \n
+    0 - Battery voltage monitoring is enabled.
+    1 - Battery voltage monitoring is disabled.
+
+    By default battery voltage monitoring during hibernate is enabled.
+*/
+#define ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING                0
+
+
+/*******************************************************************************
+                        M A C R O   V A L I D A T I O N
+*******************************************************************************/
+
+#if ( ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO > 1 )
+#error "Invalid configuration set for ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO"
+#endif
+
+#if ( ADI_PWR_LF_CLOCK_MUX > 1 )
+#error "Invalid configuration set for ADI_PWR_LF_CLOCK_MUX"
+#endif
+
+#if ( ADI_PWR_HFOSC_CLOCK_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_HFOSC_CLOCK_ENABLE"
+#endif
+
+#if ( ADI_PWR_LFXTAL_CLOCK_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_LFXTAL_CLOCK_ENABLE"
+#endif
+
+#if ( ADI_PWR_HFXTAL_CLOCK_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_HFXTAL_CLOCK_ENABLE"
+#endif
+
+#if ( ADI_PWR_LFXTAL_CLOCK_MON_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_LFXTAL_CLOCK_MON_ENABLE"
+#endif
+
+#if ( ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE"
+#endif
+
+#if ( ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE"
+#endif
+
+#if ( ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT > 3 )
+#error "Invalid configuration set for ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT"
+#endif
+
+#if ( ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE"
+#endif
+
+#if ( ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE"
+#endif
+
+#if ( ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX > 3 )
+#error "Invalid configuration set for ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX"
+#endif
+
+#if ( ADI_PWR_GPIO_CLOCK_OUT_SELECT > 15 )
+#error "Invalid configuration set for ADI_PWR_GPIO_CLOCK_OUT_SELECT"
+#endif
+
+#if ( ADI_PWR_INPUT_TO_RCLK_MUX > 3 )
+#error "Invalid configuration set for ADI_PWR_INPUT_TO_RCLK_MUX"
+#endif
+
+#if ( ADI_PWR_INPUT_TO_SPLL_MUX > 3 )
+#error "Invalid configuration set for ADI_PWR_INPUT_TO_SPLL_MUX"
+#endif
+
+#if ( ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE"
+#endif
+
+#if ( ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE"
+#endif
+
+#if ( ADI_PWR_HCLK_DIVIDE_COUNT > 63 )
+#error "Invalid configuration set for ADI_PWR_HCLK_DIVIDE_COUNT"
+#endif
+
+#if ( ADI_PWR_PCLK_DIVIDE_COUNT > 63 )
+#error "Invalid configuration set for ADI_PWR_PCLK_DIVIDE_COUNT"
+#endif
+
+#if ( ADI_PWR_ACLK_DIVIDE_COUNT > 63 )
+#error "Invalid configuration set for ADI_PWR_ACLK_DIVIDE_COUNT"
+#endif
+
+#if ( ADI_PWR_HFOSC_AUTO_DIV_BY_1 > 1 )
+#error "Invalid configuration set for ADI_PWR_HFOSC_AUTO_DIV_BY_1"
+#endif
+
+#if ( ADI_PWR_HFOSC_DIVIDE_SELECT > 5 )
+#error "Invalid configuration set for ADI_PWR_HFOSC_DIVIDE_SELECT"
+#endif
+
+#if ( ADI_PWR_SPLL_MUL_FACTOR < 8 || ADI_PWR_SPLL_MUL_FACTOR > 31 )
+#error "Invalid configuration set for ADI_PWR_SPLL_MUL_FACTOR"
+#endif
+
+#if ( ADI_PWR_SPLL_ENABLE_DIV2 > 1 )
+#error "Invalid configuration set for ADI_PWR_SPLL_ENABLE_DIV2"
+#endif
+
+#if ( ADI_PWR_SPLL_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_SPLL_ENABLE"
+#endif
+
+#if ( ADI_PWR_SPLL_INTERRUPT_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_SPLL_INTERRUPT_ENABLE"
+#endif
+
+#if ( ADI_PWR_SPLL_DIV_FACTOR < 2 || ADI_PWR_SPLL_DIV_FACTOR > 15 )
+#error "Invalid configuration set for ADI_PWR_SPLL_DIV_FACTOR"
+#endif
+
+#if ( ADI_PWR_SPLL_ENABLE_MUL2 > 1 )
+#error "Invalid configuration set for ADI_PWR_SPLL_ENABLE_MUL2"
+#endif
+
+#if ( ADI_PWR_GPT0_CLOCK_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_GPT0_CLOCK_ENABLE"
+#endif
+
+#if ( ADI_PWR_GPT1_CLOCK_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_GPT1_CLOCK_ENABLE"
+#endif
+
+#if ( ADI_PWR_GPT2_CLOCK_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_GPT2_CLOCK_ENABLE"
+#endif
+
+#if ( ADI_PWR_I2C_CLOCK_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_I2C_CLOCK_ENABLE"
+#endif
+
+#if ( ADI_PWR_GPIO_CLOCK_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_GPIO_CLOCK_ENABLE"
+#endif
+
+#if ( ADI_PWR_PCLK_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_PCLK_ENABLE"
+#endif
+
+#if ( ADI_PWR_TIMER_RGB_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_TIMER_RGB_ENABLE"
+#endif
+
+#if ( ADI_PWR_ENABLE_VBAT_INTERRUPT > 1 )
+#error "Invalid configuration set for ADI_PWR_ENABLE_VBAT_INTERRUPT"
+#endif
+
+#if ( ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT > 1 )
+#error "Invalid configuration set for ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT"
+#endif
+
+#if ( ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT > 1 )
+#error "Invalid configuration set for ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT"
+#endif
+
+#if ( ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT > 1 )
+#error "Invalid configuration set for ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT"
+#endif
+
+#if ( ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT > 2 )
+#error "Invalid configuration set for ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT"
+#endif
+
+#if ( ADI_PWR_HP_BUCK_ENABLE > 1 )
+#error "Invalid configuration set for ADI_PWR_HP_BUCK_ENABLE"
+#endif
+
+#if ( ADI_PWR_HP_BUCK_LOAD_MODE > 1 )
+#error "Invalid configuration set for ADI_PWR_HP_BUCK_LOAD_MODE"
+#endif
+
+#if ( ADI_PWR_HP_BUCK_LOW_POWER_MODE > 1 )
+#error "Invalid configuration set for ADI_PWR_HP_BUCK_LOW_POWER_MODE"
+#endif
+
+#if ( ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING > 1 )
+#error "Invalid configuration set for ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING"
+#endif
+
+
+
+/*! @} */
+
+#ifdef __ICCARM__
+#pragma diag_default=Pm009
+#endif /* __ICCARM__ */
+
+#endif /* ADI_PWR_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rng_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rng_config.h
new file mode 100755
index 00000000000..76afe147cfb
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rng_config.h
@@ -0,0 +1,106 @@
+/*!
+ *****************************************************************************
+   @file:    adi_rng_config.h
+   @brief:   Configuration options for RNG driver.
+             This is specific to the RNG driver and will be included by the driver.
+             It is not required for the application to include this header file.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2012-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_RNG_CONFIG_H__
+#define ADI_RNG_CONFIG_H__
+#include <adi_global_config.h>
+/** @defgroup RNG_Driver_Cfg RNG Driver Configuration
+ *  @ingroup RNG_Driver
+
+ */
+
+/*! \addtogroup  RNG_Driver_Cfg RNG Driver Configuration
+ *  @{
+ */
+
+/************* RNG Driver configurations ***************/
+
+/************* RNG controller configurations ***************/
+
+/*! RNG Control Register, bit 3\n
+    Enable only 8-bit generation\n
+    0 -  Generate 32-bit random number\n
+    1 -  Generate only 8-bit random number
+*/
+#define RNG0_CFG_ONLY_8_BIT                             1
+
+/*! RNG Sample Length Register, bits [11:0]\n
+    The register defines the number of samples to accumulate in the
+    CRC register when generating a random number.\n
+
+    Bits [11:0] contains the reload value of the sample counter
+
+    */
+#define RNG0_CFG_LENGTH_RELOAD                          256u
+
+/*! RNG Sample Length Register, bits [15:12]\n
+    The register defines the number of samples to accumulate in the
+    CRC register when generating a random number. The number of values
+    accumulated in the counter reload value is scaled by 2^prescaler.\n
+
+    Bits [15:12] contains the prescaler for the sample counter
+
+    */
+#define RNG0_CFG_LENGTH_PRESCALER                       0u
+
+/************** Macro validation *****************************/
+
+#if ( RNG0_CFG_ONLY_8_BIT > 1 )
+#error "Invalid configuration"
+#endif
+
+#if ( RNG0_CFG_LENGTH_RELOAD > 4095u )
+#error "Invalid value for reload"
+#endif
+
+#if ( RNG0_CFG_LENGTH_PRESCALER > 10u )
+#error "Invalid value for prescaler"
+#endif
+
+/*! @} */
+
+#endif /* __ADI_RNG_CONFIG_H__ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rtc_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rtc_config.h
new file mode 100755
index 00000000000..ef97a3b0a48
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rtc_config.h
@@ -0,0 +1,397 @@
+/*!
+ *****************************************************************************
+   @file:    adi_rtc_config.h
+   @brief:   Configuration options for Real Time Clock  device  driver.
+             This is specific to the RTC driver and will be included by the driver.
+             It is not required for the application to include this header file.
+   @version: $Revision: 33005 $
+   @date:    $Date: 2015-12-12 10:43:13 -0500 (Sat, 12 Dec 2015) $
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2012-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_RTC_CONFIG_H__
+#define ADI_RTC_CONFIG_H__
+#include <adi_global_config.h>
+
+/** @addtogroup RTC_Driver_Config Static Configuration
+ *  @ingroup RTC_Driver
+ *  @{
+ */
+
+/*!
+ * The safe write mode insures any pending writes that have not yet synchronized between the faster core clock
+ * domain and the internal RTC 32kHz clock domain are reconciled before multiple writes to the same RTC register
+ * are allowed
+*/
+
+#define ADI_RTC_CFG_ENABLE_SAFE_WRITE 1    
+
+
+/** @addtogroup RTC_Driver_Config_RTC0 RTC0 Static Configuration
+ *  @ingroup RTC_Driver_Config
+ *  @{
+ */
+
+/*
+===================================================================
+ ------------------------RTC-0 CONFIGURATION MACRO-----------------
+===================================================================
+*/
+/*! Enable the Alarm */
+#define RTC0_CFG_ENABLE_ALARM                  0     
+
+/*! Enable the Alarm interrupt*/
+#define RTC0_CFG_ENABLE_ALARM_INTERRUPT        0     
+
+/*! Enable the Trim */
+#define RTC0_CFG_ENABLE_TRIM                    0     
+
+/*! Enable the PENDERROR interrupt*/
+#define RTC0_CFG_ENABLE_PENDERROR_INTERRUPT     0     
+
+/*! Enable the write sync  interrupt*/
+#define RTC0_CFG_ENABLE_WSYNC_INTERRUPT         0     
+
+/*! Enable the pend write interrupt*/
+#define RTC0_CFG_ENABLE_WRITEPEND_INTERRUPT     0     
+
+/*! Initial the count Value*/
+#define RTC0_CFG_COUNT_VALUE                    0     
+
+/*! Initial the count Value-0*/
+#define RTC0_CFG_COUNT_VALUE_0                  0     
+
+/*! Initial the count Value-1*/
+#define RTC0_CFG_COUNT_VALUE_1                  0     
+
+/*! Alarm-0  Value*/
+#define RTC0_CFG_ALARM_VALUE_0                  0     
+
+/*! Alarm-1  Value*/
+#define RTC0_CFG_ALARM_VALUE_1                  0     
+
+/*! Trim interval*/
+#define RTC0_CFG_TRIM_INTERVAL                  0     
+
+/*! Trim interval with power of 2*/
+#define RTC0_CFG_POW2_TRIM_INTERVAL             0     
+
+/*! Trim operation to be performed for RTC0*/
+#define RTC0_CFG_TRIM_OPERATION                 0     
+
+/*! Trim  Value for RTC-0*/
+#define RTC0_CFG_TRIM_VALUE                     0     
+
+/*! GPIO Sample around Rising Edge of Sensor Strobe Channel 3. 
+ * Enables sampling of Sensor Strobe GPIO inputs around rising edge of Sensor Strobe Channel 3 pulse.
+ *
+ *  0 No sampling of input around rising edge.
+ *  1 Input sampled one clock cycle before rising edge of Sensor Strobe.
+ * 10 Input sampled at rising edge of Sensor Strobe.
+ * 11 Input sampled one clock cycle after rising edge of Sensor Strobe.
+ */
+#define RTC0_SS3_SMPONRE                          0
+
+/*! GPIO Sample around Falling Edge of Sensor Strobe Channel 3. 
+ *  Enables sampling of Sensor Strobe GPIO inputs around falling edge of Sensor Strobe Channel 3 pulse. 
+ *
+ *  0	No sampling of input around rising edge.		
+ *  1	Input sampled one clock cycle before rising edge of Sensor Strobe.		
+ * 10	Input sampled at rising edge of Sensor Strobe.
+ * 11	Input sampled one clock cycle after rising edge of Sensor Strobe.		
+ */
+#define RTC0_SS3_SMPONFE                          0
+/*! GPIO Sample around Falling Edge of Sensor Strobe Channel 2.  */
+#define RTC0_SS2_SMPONFE                          0
+/*! GPIO Sample around Rising Edge of Sensor Strobe Channel 1.   */ 
+#define RTC0_SS1_SMPONRE                          0
+/*! GPIO Sample around Falling Edge of Sensor Strobe Channel 1.  */
+#define RTC0_SS1_SMPONFE                          0
+
+
+/*! Sensor Strobe's GP Input Sampling Mux
+ *  SS 2 GPIO Pin 1
+ *
+ * GPMUX0/1.SSxGPINySEL	3�b000	3�b001	3�b010	3�b011	3�b100	3�b101	3�b110	3�b111
+ * RTCSSxGPIny           p0[12] p2[0]    p0[9]  p0[8]   p1[13]   p1[2]   p2[7]   p2[9]
+ */
+#define RTC0_SS2_GPIN1SEL                       0x4
+/*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 0*/
+#define RTC0_SS2_GPIN0SEL                       0x3
+/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 2*/
+#define RTC0_SS1_GPIN2SEL                       0x2
+/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 1*/
+#define RTC0_SS1_GPIN1SEL                       0x1
+/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 0*/
+#define RTC0_SS1_GPIN0SEL                       0x0
+/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 2*/
+#define RTC0_SS3_GPIN2SEL                       0x0
+/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 1*/
+#define RTC0_SS3_GPIN1SEL                       0x7
+/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 0*/
+#define RTC0_SS3_GPIN0SEL                       0x6
+/*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 2*/
+#define RTC0_SS2_GPIN2SEL                       0x5
+
+/*! Differential output option for Sensor Strobe channel 3.
+ *  Sensor Strobe channel3 is used as differential signal, actual RTC_SS3 out 
+ *  for this channel is available in corresponding GPIO. 
+ *  RTC_SS4 of Sensor Strobe channel 4 is used to provided inverted signal of RTC_SS3.
+ */
+#define RTC0_SS3_DIFFOUT                           0
+/*! Differential output option for Sensor Strobe channel 1.
+ *  Sensor Strobe channel 1 is used as differential signal, actual RTC_SS1 out 
+ *  for this channel is available in corresponding GPIO. 
+ *  RTC_SS1 of Sensor Strobe channel 2 is used to provided inverted signal of RTC_SS1.
+ */
+#define RTC0_SS1_DIFFOUT                           0
+
+
+
+/*! @} */
+
+/*
+===================================================================
+ ------------------------RTC-1 CONFIGURATION MACRO-----------------
+===================================================================
+*/
+
+/** @addtogroup RTC_Driver_Config_RTC1 RTC1 Static Configuration
+ *  @ingroup RTC_Driver_Config
+ *  @{
+ */
+
+
+   
+/*! Enable the Alarm */
+#define RTC1_CFG_ENABLE_ALARM                       0     
+
+/*! Enable the Alarm interrupt*/
+#define RTC1_CFG_ENABLE_ALARM_INTERRUPT             0     
+
+/*! Enable the Trim */
+#define RTC1_CFG_ENABLE_TRIM                        0     
+
+/*! Enable the mod-60 Alarm */
+#define RTC1_CFG_ENABLE_MOD60_ALARM                 0     
+
+/*! Enable the mod-60 Alarm  period*/
+#define RTC1_CFG_ENABLE_MOD60_ALARM_PERIOD          0     
+
+/*! Enable the Alarm interrupt*/
+#define RTC1_CFG_ENABLE_MOD60_ALARM_INTERRUPT       0     
+
+/*! Enable the ISOINT interrupt*/
+#define RTC1_CFG_ENABLE_ISO_INTERRUPT               0     
+
+/*! Enable the PENDERROR interrupt*/
+#define RTC1_CFG_ENABLE_PENDERROR_INTERRUPT         0     
+
+/*! Enable the write sync  interrupt*/
+#define RTC1_CFG_ENABLE_WSYNC_INTERRUPT             0     
+
+/*! Enable the pend write interrupt*/
+#define RTC1_CFG_ENABLE_WRITEPEND_INTERRUPT         0     
+
+/*! Enable the RTC count interrupt*/
+#define RTC1_CFG_ENABLE_COUNT_INTERRUPT             0     
+
+/*! Enable the prescaled modulo-1 interrupt*/
+#define RTC1_CFG_ENABLE_MOD1_COUNT_INTERRUPT        0     
+
+/*! Enable the Trim interrupt*/
+#define RTC1_CFG_ENABLE_TRIM_INTERRUPT              0     
+
+/*! Enable the Mod60 roll over  interrupt*/
+#define RTC1_CFG_CNT_MOD60_ROLLLOVER_INTERRUPT      0     
+
+/*! Prescale value for the RTC1*/
+#define RTC1_CFG_PRESCALE                           0     
+
+/*! Enable the counter roll over  interrupt*/
+#define RTC1_CFG_CNT_ROLLLOVER_INTERRUPT            0     
+
+/*! Initial the count Value-0*/
+#define RTC1_CFG_COUNT_VALUE_0                      0     
+
+/*! Initial the count Value-1*/
+#define RTC1_CFG_COUNT_VALUE_1                      0     
+
+/*! Alarm  Value-0*/
+#define RTC1_CFG_ALARM_VALUE_0                      0     
+
+/*! Alarm  Value-1*/
+#define RTC1_CFG_ALARM_VALUE_1                      0     
+
+/*! Alarm  Value-2*/
+#define RTC1_CFG_ALARM_VALUE_2                      0     
+
+/*! Trim interval*/
+#define RTC1_CFG_TRIM_INTERVAL                      0     
+
+/*! Trim interval with power of 2*/
+#define RTC1_CFG_POW2_TRIM_INTERVAL                 0     
+
+/*! Trim operation to be performed for RTC1*/
+#define RTC1_CFG_TRIM_OPERATION                     0     
+
+/*! Trim  Value for RTC-1*/
+#define RTC1_CFG_TRIM_VALUE                         0     
+
+/*! Enable the input capture channel-0*/
+#define RTC1_CFG_IC0_ENABLE                         0     
+
+/*! Enable the input capture channel-2*/
+#define RTC1_CFG_IC2_ENABLE                         0     
+
+/*! Enable the input capture channel-3*/
+#define RTC1_CFG_IC3_ENABLE                         0     
+
+/*! Enable the input capture channel-4*/
+#define RTC1_CFG_IC4_ENABLE                         0     
+
+/*! Enable the Sensor Strobe channel-1*/
+#define RTC1_CFG_SS1_ENABLE                         0     
+/*! Enable the Sensor Strobe channel-2*/
+#define RTC1_CFG_SS2_ENABLE                         0     
+/*! Enable the Sensor Strobe channel-3*/
+#define RTC1_CFG_SS3_ENABLE                         0     
+/*! Enable the Sensor Strobe channel-4*/
+#define RTC1_CFG_SS4_ENABLE                         0     
+
+/*! Enable the interrupt for input capture channel-0*/
+#define RTC1_CFG_IC0_INT_ENABLE                     0     
+
+/*! Enable the interrupt for input capture channel-2*/
+#define RTC1_CFG_IC2_INT_ENABLE                     0     
+
+/*! Enable the interrupt for input capture channel-3*/
+#define RTC1_CFG_IC3_INT_ENABLE                     0     
+
+/*! Enable the interrupt for input capture channel-4*/
+#define RTC1_CFG_IC4_INT_ENABLE                     0     
+
+/*! Enable the over write input capture channels*/
+#define RTC1_CFG_IC_OVER_WRITE_ENABLE               0    
+
+/*! Polarity for  input capture channel-0*/
+#define RTC1_CFG_IC0_EDGE_POLARITY                  0     
+
+/*! Polarity for  input capture channel-2*/
+#define RTC1_CFG_IC2_EDGE_POLARITY                  0     
+
+/*! Polarity for  input capture channel-3*/
+#define RTC1_CFG_IC3_EDGE_POLARITY                  0     
+
+/*! Polarity for  input capture channel-4*/
+#define RTC1_CFG_IC4_EDGE_POLARITY                  0     
+
+/*! Enable the interrupt for Sensor Strobe channel-1*/
+#define RTC1_CFG_SS1_INT_ENABLE                     0     
+/*! Enable the interrupt for Sensor Strobe channel-2*/
+#define RTC1_CFG_SS2_INT_ENABLE                     0     
+/*! Enable the interrupt for Sensor Strobe channel-3*/
+#define RTC1_CFG_SS3_INT_ENABLE                     0     
+/*! Enable the interrupt for Sensor Strobe channel-4*/
+#define RTC1_CFG_SS4_INT_ENABLE                     0    
+
+/*! Enable the masking for Sensor Strobe channel-1*/
+#define RTC1_CFG_SS1_MASK_ENABLE                    0     
+/*! Enable the masking for Sensor Strobe channel-2*/
+#define RTC1_CFG_SS2_MASK_ENABLE                    0     
+/*! Enable the masking for Sensor Strobe channel-3*/
+#define RTC1_CFG_SS3_MASK_ENABLE                    0     
+/*! Enable the masking for Sensor Strobe channel-4*/
+#define RTC1_CFG_SS4_MASK_ENABLE                    0     
+
+/*! Enable the auto-reloading for Sensor Strobe channel-0*/
+#define RTC1_CFG_SS1_AUTO_RELOADING_ENABLE          0     
+
+/*! Mask for Sensor Strobe channel-0 */
+#define RTC1_CFG_SS1_MASK_VALUE                     0     
+
+
+/*! Auto reload value  for Sensor Strobe channel-0 */
+#define RTC1_CFG_SS1_AUTO_RELOAD_VALUE              32768/2
+
+
+/*! Sensor Strobe GP Input Sampling Mux
+ *  SS2 GPIO Pin 1
+ *
+ * GPMUX0/1.SSxGPINySEL	3�b000	3�b001	3�b010	3�b011	3�b100	3�b101	3�b110	3�b111
+ * RTCSSxGPIny           p0[12] p2[0]    p0[9]  p0[8]   p1[13]   p1[2]   p2[7]   p2[9]
+ */
+#define RTC1_SS2_GPIN1SEL                       0x4
+/*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 0*/
+#define RTC1_SS2_GPIN0SEL                       0x3
+/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 2*/
+#define RTC1_SS1_GPIN2SEL                       0x2
+/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 1*/
+#define RTC1_SS1_GPIN1SEL                       0x1
+/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 0*/
+#define RTC1_SS1_GPIN0SEL                       0x0
+/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 2*/
+#define RTC1_SS3_GPIN2SEL                       0x0
+/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 1*/
+#define RTC1_SS3_GPIN1SEL                       0x7
+/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 0*/
+#define RTC1_SS3_GPIN0SEL                       0x6
+/*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 2*/
+#define RTC1_SS2_GPIN2SEL                       0x5
+
+/*! Differential output option for Sensor Strobe channel 3.
+ *  Sensor Strobe channel3 is used as differential signal, actual RTC_SS3 out 
+ *  for this channel is available in corresponding GPIO. 
+ *  RTC_SS4 of Sensor Strobe channel 4 is used to provided inverted signal of RTC_SS3.
+ */
+#define RTC1_SS3_DIFFOUT                           0
+/*! Differential output option for Sensor Strobe channel 1.
+ *  Sensor Strobe channel 1 is used as differential signal, actual RTC_SS1 out 
+ *  for this channel is available in corresponding GPIO. 
+ *  RTC_SS1 of Sensor Strobe channel 2 is used to provided inverted signal of RTC_SS1.
+ */
+#define RTC1_SS1_DIFFOUT                           0
+
+
+/*! @} */
+
+/*! @} */
+#endif /* ADI_RTC_CONFIG_H__ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_spi_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_spi_config.h
new file mode 100755
index 00000000000..e2a8ccd572b
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_spi_config.h
@@ -0,0 +1,592 @@
+/*!
+ *****************************************************************************
+   @file:    adi_spi_config.h
+   @brief:   Configuration options for SPI driver.
+             This is specific to the SPI driver and will be included by the driver.
+             It is not required for the application to include this header file.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_SPI_CONFIG_H__
+#define ADI_SPI_CONFIG_H__
+#include <adi_global_config.h>
+/** @addtogroup SPI_Driver_Config Static Configuration
+ *  @ingroup SPI_Driver
+ *  @{
+ */
+
+
+/*! Set this macro to the system clock frequency in hertz*/
+#define ADI_CFG_SYSTEM_CLOCK_HZ                    (26000000u)
+
+/************* SPI controller configurations ***************/
+
+/* There are three SPI instances SPI0, SPI1 and SPI2       */
+/* Each SPI has its own configuration macros                */
+
+
+/*----------------------------------------------------------*/
+/* -------------------- SPI0 -------------------------------*/
+/*----------------------------------------------------------*/
+
+/** @addtogroup SPI_Driver_Config_SPI0 SPI0 Static Configuration
+ *  @ingroup SPI_Driver_Config
+ *  @{
+ */
+
+ /*! If using SPI0 in master mode set this macro to 1. For slave mode set this macro to 0. */
+#define ADI_SPI0_MASTER_MODE               (1u)
+
+
+/*! Set this macro to the SPI0 bit rate in hertz */
+#define ADI_SPI0_CFG_BIT_RATE               (2000000u)
+
+/*! SPI0 enable\n
+    SPI configuration register: Bit[0]\n
+    1 -  Enable SPI\n
+    0 -  Disable SPI */
+#define ADI_SPI0_CFG_ENABLE                         (0u)
+
+/*! SPI0 clock phase mode\n
+    SPI configuration register: Bit[2]\n
+    1 - Serial clock pulses at the beginning of each serial bit transfer.\n
+    0 - Serial clock pulses at the end of each serial bit transfer. */
+#define ADI_SPI0_CFG_CLK_PHASE                      (0u)
+
+
+
+
+
+/*! SPI0 clock polarity\n
+    SPI configuration register: Bit[3]\n
+    1 - Serial clock idles high.\n
+    0 - Serial clock idles low. */
+#define ADI_SPI0_CFG_CLK_POLARITY                   (0u)
+
+
+/*! SPI0 wired OR mode\n
+    SPI configuration register: Bit[4]\n
+    1 - Enables open circuit output enable.\n
+    0 - Normal output levels. */
+#define ADI_SPI0_CFG_WIRED_OR                       (0u)
+
+
+/*! SPI0 LSB/MSB\n
+    SPI configuration register: Bit[5]\n
+    1 - MSB transmitted first.\n
+    0 - LSB transmitted first. */
+#define ADI_SPI0_CFG_LSB_MSB                        (0u)
+
+
+/*! SPI0 transfer initiate\n
+    SPI configuration register: Bit[6]\n
+    1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n
+    0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/
+#define ADI_SPI0_CFG_TRANSFER_INITIATE              (0u)
+
+
+/*! SPI0 Tx FIFO transfers zeros or last bit upon underflow\n
+    SPI configuration register: Bit[7]\n
+    1 - Tx FIFO sends zeros upon underflow.\n
+    0 - Tx FIFO repeats last bit upon underflow. */
+#define ADI_SPI0_CFG_TX_UNDERFLOW                   (0u)
+
+
+/*! SPI0 Rx FIFO overflows with received data or data is discarded\n
+    SPI configuration register: Bit[8]\n
+    1 - Rx FIFO receives data upon overflow.\n
+    0 - Rx FIFO discards received data upon overflow. */
+#define ADI_SPI0_CFG_RX_OVERFLOW                    (0u)
+
+
+/*! SPI0 slave mode MISO enable\n
+    SPI configuration register: Bit[9]\n
+    1 - MISO operates as normal in slave mode.\n
+    0 - MISO is disabled in slave mode. */
+#define ADI_SPI0_CFG_MISO_ENABLE                    (0u)
+
+
+/*! SPI0 internal loopback enable\n
+    SPI configuration register: Bit[10]\n
+    1 - MISO and MOSI is loopbacked internally.\n
+    0 - MISO and MOSI operates normally. */
+#define ADI_SPI0_CFG_LOOPBACK                       (0u)
+
+/*! SPI0 transfer and interrupt mode\n
+    SPI configuration register: Bit[11]\n
+    1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n
+    0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/
+#define ADI_SPI0_CFG_CONTINUOUS                     (0u)
+
+/*! SPI0 Rx FIFO flush enable\n
+    SPI configuration register: Bit[12]\n
+    1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n
+    0 - Rx FIFO flush is disabled. */
+#define ADI_SPI0_CFG_RX_FLUSH                       (0u)
+
+
+/*! SPI0 Tx FIFO flush enable\n
+    SPI configuration register: Bit[13]\n
+    1 - Tx FIFO is flushed.\n
+    0 - Tx FIFO flush is disabled. */
+#define ADI_SPI0_CFG_TX_FLUSH                       (0u)
+
+
+/*! Reset Mode for CSERR.       \n
+    SPI0 configuration register: Bit[14]\n
+    0 -  To  continue from where it stopped. SPI can receive the remaining bits
+         when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n
+    1 -  To enable resetting the bit counter and  reset if there is  a
+         CS error condition and the Cortex is expected to clear the SPI_EN bit.
+*/
+#define ADI_SPI0_CFG_CSERR_RESET                       (0u)
+
+
+/*! SPI0 clock divide\n
+    SPI baud rate selection register: Bit[0:5]\n
+    Value between 0-63 that is used to divide the UCLK to generate
+    the SPI serial clock. */
+#define ADI_SPI0_CFG_CLK_DIV                        (0u)
+
+
+/*! SPI0 high frequency mode\n
+    SPI baud rate selection register: Bit[6]\n
+    1 - High frequency mode enabled.\n
+    0 - High frequency mode disabled. */
+#define ADI_SPI0_CFG_HFM                            (0u)
+
+
+/*! SPI0 reset mode for CSERR\n
+    SPI baud rate selection register: Bit[7]\n
+    1 - clear bit counter on CS error.\n
+    0 - do not clear bit counter on CS error. */
+#define ADI_SPI0_CFG_CS_ERR                         (0u)
+
+
+/*! SPI0 CS interrupt\n
+    SPI baud rate selection register: Bit[8]\n
+    1 - In continuous mode, generate interrupt on CS.\n
+    0 - In continuous mode, do not generate interrupt on CS. */
+#define ADI_SPI0_CFG_CS_IRQ                         (0u)
+
+
+/*! @} */
+
+/*----------------------------------------------------------*/
+/* -------------------- SPI1 -------------------------------*/
+/*----------------------------------------------------------*/
+
+/** @addtogroup SPI_Driver_Config_SPI1 SPI1 Static Configuration
+ *  @ingroup SPI_Driver_Config
+ *  @{
+ */
+
+ /*! If using SPI1 in master mode set this macro to 1. For slave mode set this macro to 0. */
+#define ADI_SPI1_MASTER_MODE               (1u)
+ 
+/*! Set this macro to the SPI1 bit rate in hertz */
+#define ADI_SPI1_CFG_BIT_RATE               (2000000u)
+
+/*! SPI1 enable\n
+    SPI configuration register: Bit[0]\n
+    1 -  Enable SPI\n
+    0 -  Disable SPI */
+#define ADI_SPI1_CFG_ENABLE                         (0u)
+
+/*! SPI1 clock phase mode\n
+    SPI configuration register: Bit[2]\n
+    1 - Serial clock pulses at the beginning of each serial bit transfer.\n
+    0 - Serial clock pulses at the end of each serial bit transfer. */
+#define ADI_SPI1_CFG_CLK_PHASE                      (0u)
+
+
+
+
+
+/*! SPI1 clock polarity\n
+    SPI configuration register: Bit[3]\n
+    1 - Serial clock idles high.\n
+    0 - Serial clock idles low. */
+#define ADI_SPI1_CFG_CLK_POLARITY                   (0u)
+
+
+/*! SPI1 wired OR mode\n
+    SPI configuration register: Bit[4]\n
+    1 - Enables open circuit output enable.\n
+    0 - Normal output levels. */
+#define ADI_SPI1_CFG_WIRED_OR                       (0u)
+
+
+/*! SPI1 LSB/MSB\n
+    SPI configuration register: Bit[5]\n
+    1 - MSB transmitted first.\n
+    0 - LSB transmitted first. */
+#define ADI_SPI1_CFG_LSB_MSB                        (0u)
+
+
+/*! SPI1 transfer initiate\n
+    SPI configuration register: Bit[6]\n
+    1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n
+    0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/
+#define ADI_SPI1_CFG_TRANSFER_INITIATE              (0u)
+
+
+/*! SPI1 Tx FIFO transfers zeros or last bit upon underflow\n
+    SPI configuration register: Bit[7]\n
+    1 - Tx FIFO sends zeros upon underflow.\n
+    0 - Tx FIFO repeats last bit upon underflow. */
+#define ADI_SPI1_CFG_TX_UNDERFLOW                   (0u)
+
+
+/*! SPI1 Rx FIFO overflows with received data or data is discarded\n
+    SPI configuration register: Bit[8]\n
+    1 - Rx FIFO receives data upon overflow.\n
+    0 - Rx FIFO discards received data upon overflow. */
+#define ADI_SPI1_CFG_RX_OVERFLOW                    (0u)
+
+
+/*! SPI1 slave mode MISO enable\n
+    SPI configuration register: Bit[9]\n
+    1 - MISO operates as normal in slave mode.\n
+    0 - MISO is disabled in slave mode. */
+#define ADI_SPI1_CFG_MISO_ENABLE                    (0u)
+
+
+/*! SPI1 internal loopback enable\n
+    SPI configuration register: Bit[10]\n
+    1 - MISO and MOSI is loopbacked internally.\n
+    0 - MISO and MOSI operates normally. */
+#define ADI_SPI1_CFG_LOOPBACK                       (0u)
+
+/*! SPI1 transfer and interrupt mode\n
+    SPI configuration register: Bit[11]\n
+    1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n
+    0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/
+#define ADI_SPI1_CFG_CONTINUOUS                     (0u)
+
+/*! SPI1 Rx FIFO flush enable\n
+    SPI configuration register: Bit[12]\n
+    1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n
+    0 - Rx FIFO flush is disabled. */
+#define ADI_SPI1_CFG_RX_FLUSH                       (0u)
+
+
+/*! SPI1 Tx FIFO flush enable\n
+    SPI configuration register: Bit[13]\n
+    1 - Tx FIFO is flushed.\n
+    0 - Tx FIFO flush is disabled. */
+#define ADI_SPI1_CFG_TX_FLUSH                       (0u)
+
+
+/*! Reset Mode for CSERR.       \n
+    SPI1 configuration register: Bit[14]\n
+    0 -  To  continue from where it stopped. SPI can receive the remaining bits
+         when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n
+    1 -  To enable resetting the bit counter and  reset if there is  a
+         CS error condition and the Cortex is expected to clear the SPI_EN bit.
+*/
+#define ADI_SPI1_CFG_CSERR_RESET                       (0u)
+
+
+/*! SPI1 clock divide\n
+    SPI baud rate selection register: Bit[0:5]\n
+    Value between 0-63 that is used to divide the UCLK to generate
+    the SPI serial clock. */
+#define ADI_SPI1_CFG_CLK_DIV                        (0u)
+
+
+/*! SPI1 high frequency mode\n
+    SPI baud rate selection register: Bit[6]\n
+    1 - High frequency mode enabled.\n
+    0 - High frequency mode disabled. */
+#define ADI_SPI1_CFG_HFM                            (0u)
+
+
+/*! SPI1 reset mode for CSERR\n
+    SPI baud rate selection register: Bit[7]\n
+    1 - clear bit counter on CS error.\n
+    0 - do not clear bit counter on CS error. */
+#define ADI_SPI1_CFG_CS_ERR                         (0u)
+
+
+/*! SPI1 CS interrupt\n
+    SPI baud rate selection register: Bit[8]\n
+    1 - In continuous mode, generate interrupt on CS.\n
+    0 - In continuous mode, do not generate interrupt on CS. */
+#define ADI_SPI1_CFG_CS_IRQ  
+
+/*! @} */
+
+/*----------------------------------------------------------*/
+/* -------------------- SPI2 -------------------------------*/
+/*----------------------------------------------------------*/
+
+/** @addtogroup SPI_Driver_Config_SPI2 SPI2 Static Configuration
+ *  @ingroup SP2_Driver_Config
+ *  @{
+ */
+
+/*! If using SPI2 in master mode set this macro to 1. For slave mode set this macro to 0. */
+#define ADI_SPI2_MASTER_MODE               (1u)
+
+/*! Set this macro to the SPI2 bit rate in hertz */
+#define ADI_SPI2_CFG_BIT_RATE               (2000000u)
+
+/*! SPI2 enable\n
+    SPI configuration register: Bit[0]\n
+    1 -  Enable SPI\n
+    0 -  Disable SPI */
+#define ADI_SPI2_CFG_ENABLE                         (0u)
+
+/*! SPI2 clock phase mode\n
+    SPI configuration register: Bit[2]\n
+    1 - Serial clock pulses at the beginning of each serial bit transfer.\n
+    0 - Serial clock pulses at the end of each serial bit transfer. */
+#define ADI_SPI2_CFG_CLK_PHASE                      (0u)
+
+
+
+
+
+/*! SPI2 clock polarity\n
+    SPI configuration register: Bit[3]\n
+    1 - Serial clock idles high.\n
+    0 - Serial clock idles low. */
+#define ADI_SPI2_CFG_CLK_POLARITY                   (0u)
+
+
+/*! SPI2 wired OR mode\n
+    SPI configuration register: Bit[4]\n
+    1 - Enables open circuit output enable.\n
+    0 - Normal output levels. */
+#define ADI_SPI2_CFG_WIRED_OR                       (0u)
+
+
+/*! SPI2 LSB/MSB\n
+    SPI configuration register: Bit[5]\n
+    1 - MSB transmitted first.\n
+    0 - LSB transmitted first. */
+#define ADI_SPI2_CFG_LSB_MSB                        (0u)
+
+
+/*! SPI2 transfer initiate\n
+    SPI configuration register: Bit[6]\n
+    1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n
+    0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/
+#define ADI_SPI2_CFG_TRANSFER_INITIATE              (0u)
+
+
+/*! SPI2 Tx FIFO transfers zeros or last bit upon underflow\n
+    SPI configuration register: Bit[7]\n
+    1 - Tx FIFO sends zeros upon underflow.\n
+    0 - Tx FIFO repeats last bit upon underflow. */
+#define ADI_SPI2_CFG_TX_UNDERFLOW                   (0u)
+
+
+/*! SPI2 Rx FIFO overflows with received data or data is discarded\n
+    SPI configuration register: Bit[8]\n
+    1 - Rx FIFO receives data upon overflow.\n
+    0 - Rx FIFO discards received data upon overflow. */
+#define ADI_SPI2_CFG_RX_OVERFLOW                    (0u)
+
+
+/*! SPI2 slave mode MISO enable\n
+    SPI configuration register: Bit[9]\n
+    1 - MISO operates as normal in slave mode.\n
+    0 - MISO is disabled in slave mode. */
+#define ADI_SPI2_CFG_MISO_ENABLE                    (0u)
+
+
+/*! SPI2 internal loopback enable\n
+    SPI configuration register: Bit[10]\n
+    1 - MISO and MOSI is loopbacked internally.\n
+    0 - MISO and MOSI operates normally. */
+#define ADI_SPI2_CFG_LOOPBACK                       (0u)
+
+/*! SPI2 transfer and interrupt mode\n
+    SPI configuration register: Bit[11]\n
+    1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n
+    0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/
+#define ADI_SPI2_CFG_CONTINUOUS                     (0u)
+
+/*! SPI2 Rx FIFO flush enable\n
+    SPI configuration register: Bit[12]\n
+    1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n
+    0 - Rx FIFO flush is disabled. */
+#define ADI_SPI2_CFG_RX_FLUSH                       (0u)
+
+
+/*! SPI2 Tx FIFO flush enable\n
+    SPI configuration register: Bit[13]\n
+    1 - Tx FIFO is flushed.\n
+    0 - Tx FIFO flush is disabled. */
+#define ADI_SPI2_CFG_TX_FLUSH                       (0u)
+
+
+/*! Reset Mode for CSERR.       \n
+    SPI2 configuration register: Bit[14]\n
+    0 -  To  continue from where it stopped. SPI can receive the remaining bits
+         when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n
+    1 -  To enable resetting the bit counter and  reset if there is  a
+         CS error condition and the Cortex is expected to clear the SPI_EN bit.
+*/
+#define ADI_SPI2_CFG_CSERR_RESET                       (0u)
+
+
+/*! SPI2 clock divide\n
+    SPI baud rate selection register: Bit[0:5]\n
+    Value between 0-63 that is used to divide the UCLK to generate
+    the SPI serial clock. */
+#define ADI_SPI2_CFG_CLK_DIV                        (0u)
+
+
+/*! SPI2 high frequency mode\n
+    SPI baud rate selection register: Bit[6]\n
+    1 - High frequency mode enabled.\n
+    0 - High frequency mode disabled. */
+#define ADI_SPI2_CFG_HFM                            (0u)
+
+
+/*! SPI2 reset mode for CSERR\n
+    SPI baud rate selection register: Bit[7]\n
+    1 - clear bit counter on CS error.\n
+    0 - do not clear bit counter on CS error. */
+#define ADI_SPI2_CFG_CS_ERR                         (0u)
+
+
+/*! SPI2 CS interrupt\n
+    SPI baud rate selection register: Bit[8]\n
+    1 - In continuous mode, generate interrupt on CS.\n
+    0 - In continuous mode, do not generate interrupt on CS. */
+#define ADI_SPI2_CFG_CS_IRQ  
+
+/*! @} */
+
+/************** Macro validation *****************************/
+
+#if ( ADI_SPI0_CFG_BIT_RATE > (13000000u) ) || \
+    ( ADI_SPI0_CFG_BIT_RATE > (13000000u) ) || \
+    ( ADI_SPI0_CFG_BIT_RATE > (13000000u) )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_ENABLE > 1u ) || \
+    ( ADI_SPI1_CFG_ENABLE > 1u ) || \
+    ( ADI_SPI2_CFG_ENABLE > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_CLK_PHASE > 1u ) || \
+    ( ADI_SPI1_CFG_CLK_PHASE > 1u ) || \
+    ( ADI_SPI2_CFG_CLK_PHASE > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_CLK_POLARITY > 1u ) || \
+    ( ADI_SPI1_CFG_CLK_POLARITY > 1u ) || \
+    ( ADI_SPI2_CFG_CLK_POLARITY > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_WIRED_OR > 1u ) || \
+    ( ADI_SPI1_CFG_WIRED_OR > 1u ) || \
+    ( ADI_SPI2_CFG_WIRED_OR > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_LSB_MSB > 1u ) || \
+    ( ADI_SPI1_CFG_LSB_MSB > 1u ) || \
+    ( ADI_SPI2_CFG_LSB_MSB > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_TRANSFER_INITIATE > 1u ) || \
+    ( ADI_SPI1_CFG_TRANSFER_INITIATE > 1u ) || \
+    ( ADI_SPI2_CFG_TRANSFER_INITIATE > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_TX_UNDERFLOW > 1u ) || \
+    ( ADI_SPI1_CFG_TX_UNDERFLOW > 1u ) || \
+    ( ADI_SPI2_CFG_TX_UNDERFLOW > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_RX_OVERFLOW > 1u ) || \
+    ( ADI_SPI1_CFG_RX_OVERFLOW > 1u ) || \
+    ( ADI_SPI2_CFG_RX_OVERFLOW > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_MISO_ENABLE > 1u ) || \
+    ( ADI_SPI1_CFG_MISO_ENABLE > 1u ) || \
+    ( ADI_SPI2_CFG_MISO_ENABLE > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_LOOPBACK > 1u ) || \
+    ( ADI_SPI1_CFG_LOOPBACK > 1u ) || \
+    ( ADI_SPI2_CFG_LOOPBACK > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_CONTINUOUS > 1u ) || \
+    ( ADI_SPI1_CFG_CONTINUOUS > 1u ) || \
+    ( ADI_SPI2_CFG_CONTINUOUS > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_RX_FLUSH > 1u ) || \
+    ( ADI_SPI1_CFG_RX_FLUSH > 1u ) || \
+    ( ADI_SPI2_CFG_RX_FLUSH > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_SPI0_CFG_TX_FLUSH > 1u ) || \
+    ( ADI_SPI1_CFG_TX_FLUSH > 1u ) || \
+    ( ADI_SPI2_CFG_TX_FLUSH > 1u )
+#error "Invalid configuration"
+#endif
+
+
+/*! @} */
+
+#endif /* ADI_SPI_CONFIG_H__ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_sport_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_sport_config.h
new file mode 100755
index 00000000000..db0fdb6636a
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_sport_config.h
@@ -0,0 +1,355 @@
+/*! ****************************************************************************
+ * @file    adi_sport_config.h
+ * @brief   Configuration options for SPORT driver.
+ * @details This is specific to the SPORT driver and will be included by the
+ *          driver. It is not required for the application to include this
+ *          header file.
+  -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef ADI_SPORT_CONFIG_H
+#define ADI_SPORT_CONFIG_H
+#include <adi_global_config.h>
+
+/** @addtogroup SPORT_Driver_Config Static Configuration
+ *  @ingroup SPORT_Driver
+ *  @{
+ */
+
+/************* SPORT Driver configurations FOR SPORT-0-A ***************/
+/*!
+   Frame Sync Multiplexer Select.\n
+   0 - Disable frame sync multiplexing\n
+   1 - Enable frame sync multiplexing.
+*/
+#define ADI_CFG_SPORT0A_ENABLE_FSMUXSEL             (0u)
+
+/*!
+   Clock Multiplexer Select.\n
+   0 - Disable serial clock multiplexing\n
+   1 - Enable serial clock multiplexing.
+*/
+#define ADI_CFG_SPORT0A_ENABLE_CKMUXSEL             (1u)
+
+/*!
+   Least-Significant Bit First.\n
+   0 - MSB first sent/received.\n
+   1 - LSB first sent/received.
+*/
+#define ADI_CFG_SPORT0A_LSB_FIRST                   (0u)
+
+
+/*!
+   Serial Word Length in bits.\n
+   1 - 32 - SPORT word length
+*/
+#define ADI_CFG_SPORT0A_SERIAL_WLEN                 (32u)
+
+
+/*!
+   Internal Clock.\n
+   0 - External clock.\n
+   1 - Internal clock.
+*/
+#define ADI_CFG_SPORT0A_INTERNAL_CLK                (1u)
+
+/*!
+   Operation Mode\n
+   0 - DSP standard.\n
+   1 - Timer_enable mode.
+*/
+#define ADI_CFG_SPORT0A_OPERATION_MODE              (0u)
+
+
+/*!
+   Clock Rising Edge\n
+   0 - Clock falling edge\n
+   1 - Clock rising edge.
+*/
+#define ADI_CFG_SPORT0A_CLOCK_EDGE                  (0u)
+
+/*!
+   Frame Sync Required\n
+   0 - No frame sync required \n
+   1 - Frame sync required.
+*/
+#define ADI_CFG_SPORT0A_FS_REQUIRED                 (1u)
+
+/*!
+   Internal Frame Sync\n
+   0 - External frame sync\n
+   1 - Internal frame sync
+*/
+#define ADI_CFG_SPORT0A_INTERNAL_FS                 (0u)
+
+
+/*!
+   Data-Independent Frame Sync\n
+   0 - Data-dependent frame sync\n
+   1 - Data-independent frame 
+*/
+#define ADI_CFG_SPORT0A_DATA_INDEPENDENT_FS         (0u)
+
+/*!
+   Active-Low Frame Sync\n
+   0 - Active high frame sync\n
+   1 - Active low frame sync 
+*/
+#define ADI_CFG_SPORT0A_ACTIVE_LOW_FS               (0u)
+
+/*!
+   Late Frame Sync\n
+   0 - Early frame sync\n
+   1 - Late frame sync
+*/
+#define ADI_CFG_SPORT0A_LATE_FS                     (0u)
+
+/*!
+   Enable Packing \n
+   0 - Disable\n
+   1 - 8-bit packing enable\n
+   2 - 16-bit packing enable
+*/
+#define ADI_CFG_SPORT0A_ENABLE_PACKING              (0u)
+
+/*!
+   Frame Sync Error Operation
+   0 - Flag the Frame Sync error\n
+   1 - When frame Sync error occurs, discard the receive data
+*/
+#define ADI_CFG_SPORT0A_FS_ERROR_OPERATION          (1u)
+
+/*!
+   Enabling Gated Clock\n
+   0 - Disable Gated Clock\n
+   1 - Enable Gated Clock
+*/
+#define ADI_CFG_SPORT0A_GATED_CLOCK                 (0u)
+
+/*!
+   Serial Clock divisor.\n
+   0 - 65535 -   Serial Clock Divisor which  SPORT device use to  calculate the serial 
+                 clock (ACLK) from the processor system clock (PCLK).
+*/
+#define ADI_CFG_SPORT0A_CLOCK_DIVISOR               (2u)
+
+/*!
+   Frame Sync Divisor.\n
+   0 - 128 -    Frame Sync Divisor which select the number of transmit or receive clock
+                cycles that the half SPORT counts before generating a frame sync pulse.
+*/
+#define ADI_CFG_SPORT0A_FS_DIVISOR                  (0x40u)
+
+
+/*!
+   CONVT to FS duration.\n
+   0 - 128 -    Specify the value of the number of clocks which would be programmed 
+                corresponding to the desired time duration from assertion of CONVT 
+                signal to Frame sync signal
+*/
+#define ADI_CFG_SPORT0A_CONVT_FS_DURATION           (1u)
+
+/*!
+   Polarity of the Convt signal.\n
+   0 - Active High Polarity\n
+   1 - Active low Polarity
+*/
+#define ADI_CFG_SPORT0A_CONVT_POLARITY              (0u)
+
+/*!
+   CONVT signal width.\n
+   0 - 15 -     Specify the value of the number of serial clocks for which CONVT
+                signal should be active
+   
+*/
+#define ADI_CFG_SPORT0A_CONVT_WIDTH                 (1u)
+
+#if defined(ADI_CFG_SPORT0A_SERIAL_WLEN)
+#if (ADI_CFG_SPORT0A_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0A_SERIAL_WLEN > 32u)
+#error "Invalid word length : it must be between 4 and 32"
+#endif
+#else
+#error "ADI_CFG_SPORT0A_SERIAL_WLEN undefined!!! "
+#endif
+
+/************* SPORT Driver configurations FOR SPORT-0-B ***************/
+/*!
+   Least-Significant Bit First.\n
+   0 - MSB first sent/received.\n
+   1 - LSB first sent/received.
+*/
+#define ADI_CFG_SPORT0B_LSB_FIRST                   (0u)
+
+
+/*!
+   Serial Word Length in bits.\n
+   1 - 32 - SPORT word length
+*/
+#define ADI_CFG_SPORT0B_SERIAL_WLEN                 (32u)
+
+
+/*!
+   Internal Clock.\n
+   0 - External clock.\n
+   1 - Internal clock.
+*/
+#define ADI_CFG_SPORT0B_INTERNAL_CLK                (1u)
+
+/*!
+   Operation Mode\n
+   0 - DSP standard.\n
+   1 - Timer_enable mode.
+*/
+#define ADI_CFG_SPORT0B_OPERATION_MODE              (0u)
+
+
+/*!
+   Clock Rising Edge\n
+   0 - Clock falling edge\n
+   1 - Clock rising edge.
+*/
+#define ADI_CFG_SPORT0B_CLOCK_EDGE                  (0u)
+
+/*!
+   Frame Sync Required\n
+   0 - No frame sync required \n
+   1 - Frame sync required.
+*/
+#define ADI_CFG_SPORT0B_FS_REQUIRED                 (1u)
+
+/*!
+   Internal Frame Sync\n
+   0 - External frame sync\n
+   1 - Internal frame sync
+*/
+#define ADI_CFG_SPORT0B_INTERNAL_FS                 (1u)
+
+
+/*!
+   Data-Independent Frame Sync\n
+   0 - Data-dependent frame sync\n
+   1 - Data-independent frame 
+*/
+#define ADI_CFG_SPORT0B_DATA_INDEPENDENT_FS         (0u)
+
+/*!
+   Active-Low Frame Sync\n
+   0 - Active high frame sync\n
+   1 - Active low frame sync 
+*/
+#define ADI_CFG_SPORT0B_ACTIVE_LOW_FS               (0u)
+
+/*!
+   Late Frame Sync\n
+   0 - Early frame sync\n
+   1 - Late frame sync
+*/
+#define ADI_CFG_SPORT0B_LATE_FS                     (0u)
+
+/*!
+   Enable Packing \n
+   0 - Disable\n
+   1 - 8-bit packing enable\n
+   2 - 16-bit packing enable\n
+*/
+#define ADI_CFG_SPORT0B_ENABLE_PACKING              (0u)
+
+/*!
+   Frame Sync Error Operation\n
+   0 - Flag the Frame Sync error\n
+   1 - When frame Sync error occurs, discard the receive data
+*/
+#define ADI_CFG_SPORT0B_FS_ERROR_OPERATION          (1u)
+
+/*!
+   Enabling Gated Clock\n
+   0 - Disable Gated Clock\n
+   1 - Enable Gated Clock
+*/
+#define ADI_CFG_SPORT0B_GATED_CLOCK                 (0u)
+
+/*!
+   Serial Clock divisor.\n
+   0 - 65535 -   Serial Clock Divisor which SPORT device use to calculate the serial 
+                 clock (ACLK) from the processor system clock (PCLK).
+*/
+#define ADI_CFG_SPORT0B_CLOCK_DIVISOR               (2u)
+
+/*!
+   Frame Sync Divisor.\n
+   0 - 128 -    Frame Sync Divisor which select the number of transmit or receive clock
+                cycles that the half SPORT counts before generating a frame sync pulse.
+*/
+#define ADI_CFG_SPORT0B_FS_DIVISOR                  (0x40u)
+
+
+/*!
+   CONVT to FS duration.\n
+   0 - 128 -    Specify the value of the number of clocks which would be programmed 
+                corresponding to the desired time duration from assertion of CONVT 
+                signal to Frame sync signal
+*/
+#define ADI_CFG_SPORT0B_CONVT_FS_DURATION           (1u)
+
+/*!
+   Polarity of the Convt signal.\n
+   0 - Active High Polarity\n
+   1 - Active low Polarity
+*/
+#define ADI_CFG_SPORT0B_CONVT_POLARITY              (0u)
+
+/*!
+   CONVT signal width.\n
+   0-15 -       Specify the value of the number of serial clocks for which CONVT
+                signal should be active
+   
+*/
+#define ADI_CFG_SPORT0B_CONVT_WIDTH                 (1u)
+
+#if defined(ADI_CFG_SPORT0B_SERIAL_WLEN)
+#if (ADI_CFG_SPORT0B_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0B_SERIAL_WLEN > 32u)
+#error "Invalid word length : it must be between 4 and 32"
+#endif
+#else
+#error "ADI_CFG_SPORT0B_SERIAL_WLEN undefined!!! "
+#endif
+
+/*! @} */
+
+#endif /* ADI_SPORT_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_tmr_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_tmr_config.h
new file mode 100755
index 00000000000..8d6ee10347f
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_tmr_config.h
@@ -0,0 +1,902 @@
+/*! *****************************************************************************
+ * @file    adi_tmr_config.h
+ * @brief   GP and RGB timer device driver configuration
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+
+#ifndef ADI_TMR_CONFIG_H
+#define ADI_TMR_CONFIG_H
+
+
+#include <adi_global_config.h>
+
+
+/** @addtogroup TMR_Driver_Config Static Configuration
+ *  @ingroup TMR_Driver
+ *  @{
+ */
+
+
+/*! Static configuration allows all 3 GP timers and the RGB timer to be configured
+    with the parameters in this file by simply calling #adi_tmr_Init. The user can
+    then call any of the configuration API's to override the static configuration,
+    or simply call #adi_tmr_Enable to start the timer. Since all of these parameters
+    must be stored in arrays for abstraction, using static configuration will increase the 
+    data footprint. If the user doesn't call any of the runtime configuration API's, the
+    linker will throw them out and the code footprint will be reduced significantly. Using
+    static configuration also reduces cycle count and simplifies the user application. 
+    Static configuration should be used if the timers need to be configured once and do not 
+    need to be changed during the system lifetime.
+
+    0 - Disable static confiscation support. User must call #adi_tmr_ConfigTimer and other
+        configuration API's after calling #adi_tmr_Init and prior to calling #adi_tmr_Enable
+        in order to set up the timer.
+
+    1 - Enable static configuration support. The timer registers will be set based on the 
+        settings in this file when #adi_tmr_Init is called.
+*/
+#define ADI_TIMER_ENABLE_STATIC_CONFIG_SUPPORT          (0u)
+
+
+/*************************************************************
+                        GP Timer 0 Configuration
+ *************************************************************/
+
+ /** @addtogroup GPTimer0_Driver_Config GP Timer 0 Static Configuration
+ *  @ingroup TMR_Driver_Config
+ *  @{
+ */
+
+ 
+/*! Count up or down. Used to control whether the timer increments (counts up)
+    or decrements (counts down) the Up/Down counter, it can be set to\n
+    0 -  Timer is set to count down.\n
+    1 -  Timer is set to count up.
+*/
+#define TMR0_CFG_COUNT_UP                               (0u)
+
+/*! Timer mode. Used to control whether the timer runs in periodic or
+    free running mode, it can be set to\n
+    0 -  Timer is in free running mode.\n
+    1 -  Timer is in periodic mode.
+*/
+#define TMR0_CFG_MODE                                   (1u)
+
+/*! Prescale factor. Controls the prescaler division factor
+    to the timer's selected clock. It can be set to\n
+
+    0 - source_clock/[1 or 4]\n
+    1 - source_clock/16\n
+    2 - source_clock/64\n
+    3 - source_clock/256
+*/
+#define TMR0_CFG_PRESCALE_FACTOR                        (0u)
+
+/*! Timer clock source. Used to select a timer clock from the four
+    available clock sources, it can be set to\n
+    0 - Select PCLK\n
+    1 - Select HFOSC\n
+    2 - Select LFOSC\n
+    3 - Select LFXTAL
+*/
+#define TMR0_CFG_CLOCK_SOURCE                           (0u)
+
+/*! Timer load value. The Up/Down counter is periodically loaded with this
+    value if periodic mode is selected. LOAD writes during Up/Down counter timeout events
+    are delayed until the event has passed. It can be set to any value from 0 to 65535.
+
+*/
+#define TMR0_CFG_LOAD_VALUE                             (0x8F9Cu)
+
+/*! Timer asynchrounous load value. The Up/Down counter is periodically loaded with
+    this value if periodic mode is selected. Writing Asynchronous Load value takes
+    advantage of having the timer run on PCLK by bypassing clock synchronization
+    logic otherwise required. It can be set to any value from 0 to 65535.
+
+*/
+#define TMR0_CFG_ASYNC_LOAD_VALUE                       (0x8F9Cu)
+
+/*! Reload control. This allows the user to select whether the Up/Down counter should be
+    reset only on a timeout event or also when interrupt is cleared. It can be set to\n
+    0 - Up/down counter is only reset on a time out event.\n
+    1 - Resets the up/down counter when the interrupt is cleared.
+*/
+#define TMR0_CFG_ENABLE_RELOADING                       (0u)
+
+/*! Enable or disable Synchronization bypass\n
+    0 - Disable Synchronization bypass.\n
+    1 - Enable Synchronization bypass.
+*/
+#define TMR0_CFG_ENABLE_SYNC_BYPASS                     (0u)
+
+/*************************************************************
+                        GP Timer 0 Event Configuration
+ *************************************************************/
+
+/*! Enable or disable event capture. It can be set to\n
+    0 - Disable event capturing.\n
+    1 - Enable event capturing.
+*/
+#define TMR0_CFG_ENABLE_EVENT_CAPTURE                   (1u)
+
+/*! Enable or disable prescale reset\n
+    0 - Disable rescale reset.\n
+    1 - Enable rescale reset.
+*/
+#define TMR0_CFG_ENABLE_PRESCALE_RESET                  (0u)    
+
+/*! Event to be captured. One of the selected 40 events associated
+    with a general purpose time can be captured. It can be set to
+    a value of 0 - 39. Please refer hardware reference manual to know
+    which events can be captured by a particular GP timer.
+*/
+#define TMR0_CFG_EVENT_CAPTURE                          (27u)
+
+/*************************************************************
+                        GP Timer 0 PWM0 Configuration
+ *************************************************************/
+
+/*! Timer PWM Enable Match. This will control PWM operation mode of the timer.
+    Toggle mode provides a 50% duty cycle and match mode provides a configurable
+    duty cycle by using the match value. This vlaue can be set to\n
+    0 - PWM in toggle mode.\n
+    1 - PWM in match mode.
+*/
+#define TMR0_CFG_ENABLE_PWM0_MATCH_MODE                 (1u)
+
+
+/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n
+    0 - PWM idles low.\n
+    1 - PWM idles high.
+*/
+#define TMR0_CFG_PWM0_IDLE_STATE                        (1u)
+
+
+/*! PWM Match value. The value is used when the PWM is operating in match mode.
+    The PWM output is asserted when the Up/Down counter is equal to this match value.
+    PWM output is deasserted again when a timeout event occurs.
+    If the match value is never reached, or occurs simultaneous to a timeout event,
+    the PWM output remains idle. It can be any value from 0 to 65535.
+*/
+#define TMR0_CFG_PWM0_MATCH_VALUE                       (0x0E5Cu)
+
+/*! @} */
+
+
+/*************************************************************
+                        GP Timer 1 Configuration
+ *************************************************************/
+
+ /** @addtogroup GPTimer1_Driver_Config GP Timer 1 Static Configuration
+ *  @ingroup TMR_Driver_Config
+ *  @{
+ */
+
+ 
+/*! Count up or down. Used to control whether the timer increments (counts up)
+    or decrements (counts down) the Up/Down counter, it can be set to\n
+    0 -  Timer is set to count down.\n
+    1 -  Timer is set to count up.
+*/
+#define TMR1_CFG_COUNT_UP                               (0u)
+
+/*! Timer mode. Used to control whether the timer runs in periodic or
+    free running mode, it can be set to\n
+    0 -  Timer is in free running mode.\n
+    1 -  Timer is in periodic mode.
+*/
+#define TMR1_CFG_MODE                                   (1u)
+
+/*! Prescale factor. Controls the prescaler division factor
+    to the timer's selected clock. It can be set to\n
+
+    0 - source_clock/[1 or 4]\n
+    1 - source_clock/16\n
+    2 - source_clock/64\n
+    3 - source_clock/256
+*/
+#define TMR1_CFG_PRESCALE_FACTOR                        (0u)
+
+/*! Timer clock source. Used to select a timer clock from the four
+    available clock sources, it can be set to\n
+    0 - Select PCLK\n
+    1 - Select HFOSC\n
+    2 - Select LFOSC\n
+    3 - Select LFXTAL
+*/
+#define TMR1_CFG_CLOCK_SOURCE                           (0u)
+
+/*! Timer load value. The Up/Down counter is periodically loaded with this
+    value if periodic mode is selected. LOAD writes during Up/Down counter timeout events
+    are delayed until the event has passed. It can be set to any value from 0 to 65535.
+
+*/
+#define TMR1_CFG_LOAD_VALUE                             (0x23E7u)
+
+/*! Timer asynchronous load value. The Up/Down counter is periodically loaded with
+    this value if periodic mode is selected. Writing Asynchronous Load value takes
+    advantage of having the timer run on PCLK by bypassing clock synchronization
+    logic otherwise required. It can be set to any value from 0 to 65535.
+
+*/
+#define TMR1_CFG_ASYNC_LOAD_VALUE                       (0x23E7u)
+
+/*! Reload control. This allows the user to select whether the Up/Down counter should be
+    reset only on a timeout event or also when interrupt is cleared. It can be set to\n
+    0 - Up/down counter is only reset on a time out event.\n
+    1 - Resets the up/down counter when the interrupt is cleared.
+*/
+#define TMR1_CFG_ENABLE_RELOADING                       (0u)
+
+/*! Enable or disable Synchronization bypass\n
+    0 - Disable Synchronization bypass.\n
+    1 - Enable Synchronization bypass.
+*/
+#define TMR1_CFG_ENABLE_SYNC_BYPASS                     (0u)
+
+
+/*************************************************************
+                        GP Timer 1 Event Configuration
+ *************************************************************/
+ 
+/*! Enable or disable event capture. It can be set to\n
+    0 - Disable event capturing.\n
+    1 - Enable event capturing.
+*/
+#define TMR1_CFG_ENABLE_EVENT_CAPTURE                   (1u)
+
+/*! Enable or disable prescale reset\n
+    0 - Disable rescale reset.\n
+    1 - Enable rescale reset.
+*/
+#define TMR1_CFG_ENABLE_PRESCALE_RESET                  (0u)
+
+/*! Event to be captured. One of the selected 40 events associated
+    with a general purpose time can be captured. It can be set to
+    a value of 0 - 39. Please refer hardware reference manual to know
+    which events can be captured by a particular GP timer.
+*/
+#define TMR1_CFG_EVENT_CAPTURE                          (28u)
+
+/*************************************************************
+                        GP Timer 1 PWM0 Configuration
+ *************************************************************/
+
+/*! Timer PWM Enable Match. This will control PWM operation mode of the timer.
+    Toggle mode provides a 50% duty cycle and match mode provides a configurable
+    duty cycle by using the match value. This value can be set to\n
+    0 - PWM in toggle mode.\n
+    1 - PWM in match mode.
+*/
+#define TMR1_CFG_ENABLE_PWM0_MATCH_MODE                 (1u)
+
+
+/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n
+    0 - PWM idles low.\n
+    1 - PWM idles high.
+*/
+#define TMR1_CFG_PWM0_IDLE_STATE                        (1u)
+
+
+/*! PWM Match value. The value is used when the PWM is operating in match mode.
+    The PWM output is asserted when the Up/Down counter is equal to this match value.
+    PWM output is deasserted again when a timeout event occurs.
+    If the match value is never reached, or occurs simultaneous to a timeout event,
+    the PWM output remains idle. It can be any value from 0 to 65535.
+*/
+#define TMR1_CFG_PWM0_MATCH_VALUE                       (0x08F9u)
+
+/*! @} */
+
+/*************************************************************
+                        GP Timer 2 Configuration
+ *************************************************************/
+
+ /** @addtogroup GPTimer2_Driver_Config GP Timer 2 Static Configuration
+ *  @ingroup TMR_Driver_Config
+ *  @{
+ */
+
+ 
+/*! Count up or down. Used to control whether the timer increments (counts up)
+    or decrements (counts down) the Up/Down counter, it can be set to\n
+    0 -  Timer is set to count down.\n
+    1 -  Timer is set to count up.
+*/
+#define TMR2_CFG_COUNT_UP                               (0u)
+
+/*! Timer mode. Used to control whether the timer runs in periodic or
+    free running mode, it can be set to\n
+    0 -  Timer is in free running mode.\n
+    1 -  Timer is in periodic mode.
+*/
+#define TMR2_CFG_MODE                                   (1u)
+
+/*! Prescale factor. Controls the prescaler division factor
+    to the timer's selected clock. It can be set to\n
+
+    0 - source_clock/[1 or 4]\n
+    1 - source_clock/16\n
+    2 - source_clock/64\n
+    3 - source_clock/256
+*/
+#define TMR2_CFG_PRESCALE_FACTOR                        (0u)
+
+/*! Timer clock source. Used to select a timer clock from the four
+    available clock sources, it can be set to\n
+    0 - Select PCLK\n
+    1 - Select HFOSC\n
+    2 - Select LFOSC\n
+    3 - Select LFXTAL
+*/
+#define TMR2_CFG_CLOCK_SOURCE                           (0u)
+
+/*! Timer load value. The Up/Down counter is periodically loaded with this
+    value if periodic mode is selected. LOAD writes during Up/Down counter timeout events
+    are delayed until the event has passed. It can be set to any value from 0 to 65535.
+
+*/
+#define TMR2_CFG_LOAD_VALUE                             (0x0E5Cu)
+
+/*! Timer asynchronous load value. The Up/Down counter is periodically loaded with
+    this value if periodic mode is selected. Writing Asynchronous Load value takes
+    advantage of having the timer run on PCLK by bypassing clock synchronization
+    logic otherwise required. It can be set to any value from 0 to 65535.
+
+*/
+#define TMR2_CFG_ASYNC_LOAD_VALUE                       (0x0E5Cu)
+
+/*! Reload control. This allows the user to select whether the Up/Down counter should be
+    reset only on a timeout event or also when interrupt is cleared. It can be set to\n
+    0 - Up/down counter is only reset on a time out event.\n
+    1 - Resets the up/down counter when the interrupt is cleared.
+*/
+#define TMR2_CFG_ENABLE_RELOADING                       (0u)
+
+/*! Enable or disable Synchronization bypass\n
+    0 - Disable Synchronization bypass.\n
+    1 - Enable Synchronization bypass.
+*/
+#define TMR2_CFG_ENABLE_SYNC_BYPASS                     (0u)
+
+/*************************************************************
+                        GP Timer 2 Event Configuration
+ *************************************************************/
+
+/*! Enable or disable event capture. It can be set to\n
+    0 - Disable event capturing.\n
+    1 - Enable event capturing.
+*/
+#define TMR2_CFG_ENABLE_EVENT_CAPTURE                   (1u)
+
+/*! Enable or disable prescale reset\n
+    0 - Disable rescale reset.\n
+    1 - Enable rescale reset.
+*/
+#define TMR2_CFG_ENABLE_PRESCALE_RESET                  (0u)
+
+/*! Event to be captured. One of the selected 40 events associated
+    with a general purpose time can be captured. It can be set to
+    a value of 0 - 39. Please refer hardware reference manual to know
+    which events can be captured by a particular GP timer.
+*/
+#define TMR2_CFG_EVENT_CAPTURE                          (27u)
+
+/*************************************************************
+                        GP Timer 2 PWM0 Configuration
+ *************************************************************/
+
+/*! Timer PWM Enable Match. This will control PWM operation mode of the timer.
+    Toggle mode provides a 50% duty cycle and match mode provides a configurable
+    duty cycle by using the match value. This value can be set to\n
+    0 - PWM in toggle mode.\n
+    1 - PWM in match mode.
+*/
+#define TMR2_CFG_ENABLE_PWM0_MATCH_MODE                 (1u)
+
+
+/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n
+    0 - PWM idles low.\n
+    1 - PWM idles high.
+*/
+#define TMR2_CFG_PWM0_IDLE_STATE                        (1u)
+
+
+/*! PWM Match value. The value is used when the PWM is operating in match mode.
+    The PWM output is asserted when the Up/Down counter is equal to this match value.
+    PWM output is deasserted again when a timeout event occurs.
+    If the match value is never reached, or occurs simultaneous to a timeout event,
+    the PWM output remains idle. It can be any value from 0 to 65535.
+*/
+#define TMR2_CFG_PWM0_MATCH_VALUE                       (0x02DFu)
+
+/*! @} */
+
+
+/*************************************************************
+                        RGB Timer Configuration
+ *************************************************************/
+
+/** @addtogroup RGBTimer_Driver_Config RGB Timer Static Configuration
+ *  @ingroup TMR_Driver_Config
+ *  @{
+ */
+
+ 
+/*! Count up or down. Used to control whether the timer increments (counts up)
+    or decrements (counts down) the Up/Down counter, it can be set to\n
+    0 -  Timer is set to count down.\n
+    1 -  Timer is set to count up.
+*/
+#define TMR3_CFG_COUNT_UP                               (0u)
+
+/*! Timer mode. Used to control whether the timer runs in periodic or
+    free running mode, it can be set to\n
+    0 -  Timer is in free running mode.\n
+    1 -  Timer is in periodic mode.
+*/
+#define TMR3_CFG_MODE                                   (1u)
+
+/*! Prescale factor. Controls the prescaler division factor
+    to the timer's selected clock. It can be set to\n
+
+    0 - source_clock/[1 or 4]\n
+    1 - source_clock/16\n
+    2 - source_clock/64\n
+    3 - source_clock/256
+*/
+#define TMR3_CFG_PRESCALE_FACTOR                        (0u)
+
+/*! Timer clock source. Used to select a timer clock from the four
+    available clock sources, it can be set to\n
+    0 - Select PCLK\n
+    1 - Select HFOSC\n
+    2 - Select LFOSC\n
+    3 - Select LFXTAL
+*/
+#define TMR3_CFG_CLOCK_SOURCE                           (0u)
+
+/*! Timer load value. The Up/Down counter is periodically loaded with this
+    value if periodic mode is selected. LOAD writes during Up/Down counter timeout events
+    are delayed until the event has passed. It can be set to any value from 0 to 65535.
+
+*/
+#define TMR3_CFG_LOAD_VALUE                             (0x47CEu)
+
+/*! Timer asynchronous load value. The Up/Down counter is periodically loaded with
+    this value if periodic mode is selected. Writing asynchronous Load value takes
+    advantage of having the timer run on PCLK by bypassing clock synchronization
+    logic otherwise required. It can be set to any value from 0 to 65535.
+
+*/
+#define TMR3_CFG_ASYNC_LOAD_VALUE                       (0x47CEu)
+
+/*! Reload control. This allows the user to select whether the Up/Down counter should be
+    reset only on a timeout event or also when interrupt is cleared. It can be set to\n
+    0 - Up/down counter is only reset on a time out event.\n
+    1 - Resets the up/down counter when the interrupt is cleared.
+*/
+#define TMR3_CFG_ENABLE_RELOADING                       (0u)
+
+/*! Enable or disable Synchronization bypass\n
+    0 - Disable Synchronization bypass.\n
+    1 - Enable Synchronization bypass.
+*/
+#define TMR3_CFG_ENABLE_SYNC_BYPASS                     (0u)
+
+/*************************************************************
+                        RGB Timer Event Configuration
+ *************************************************************/
+
+/*! Enable or disable event capture. It can be set to\n
+    0 - Disable event capturing.\n
+    1 - Enable event capturing.
+*/
+#define TMR3_CFG_ENABLE_EVENT_CAPTURE                   (1u)
+
+/*! Enable or disable prescale reset\n
+    0 - Disable rescale reset.\n
+    1 - Enable rescale reset.
+*/
+#define TMR3_CFG_ENABLE_PRESCALE_RESET                  (0u)
+
+/*! Event to be captured. One of the selected 40 events associated
+    with a general purpose time can be captured. It can be set to
+    a value of 0 - 39. Please refer hardware reference manual to know
+    which events can be captured by a particular GP timer.
+*/
+#define TMR3_CFG_EVENT_CAPTURE                          (28u)
+
+/*************************************************************
+                        RGB Timer PWM0 Configuration
+ *************************************************************/
+
+/*! Timer PWM Enable Match. This will control PWM operation mode of the timer.
+    Toggle mode provides a 50% duty cycle and match mode provides a configurable
+    duty cycle by using the match value. This value can be set to\n
+    0 - PWM in toggle mode.\n
+    1 - PWM in match mode.
+*/
+#define TMR3_CFG_ENABLE_PWM0_MATCH_MODE                 (1u)
+
+
+/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n
+    0 - PWM idles low.\n
+    1 - PWM idles high.
+*/
+#define TMR3_CFG_PWM0_IDLE_STATE                        (1u)
+
+
+/*! PWM Match value. The value is used when the PWM is operating in match mode.
+    The PWM output is asserted when the Up/Down counter is equal to this match value.
+    PWM output is deasserted again when a timeout event occurs.
+    If the match value is never reached, or occurs simultaneous to a timeout event,
+    the PWM output remains idle. It can be any value from 0 to 65535.
+*/
+#define TMR3_CFG_PWM0_MATCH_VALUE                       (0x23E7u)
+
+/*************************************************************
+                        RGB Timer PWM1 Configuration
+ *************************************************************/
+
+/*! Timer PWM Enable Match. This will control PWM operation mode of the timer.
+    Toggle mode provides a 50% duty cycle and match mode provides a configurable
+    duty cycle by using the match value. This value can be set to\n
+    0 - PWM in toggle mode.\n
+    1 - PWM in match mode.
+*/
+#define TMR3_CFG_ENABLE_PWM1_MATCH_MODE                 (0u)
+
+
+/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n
+    0 - PWM idles low.\n
+    1 - PWM idles high.
+*/
+#define TMR3_CFG_PWM1_IDLE_STATE                        (0u)
+
+
+/*! PWM Match value. The value is used when the PWM is operating in match mode.
+    The PWM output is asserted when the Up/Down counter is equal to this match value.
+    PWM output is deasserted again when a timeout event occurs.
+    If the match value is never reached, or occurs simultaneous to a timeout event,
+    the PWM output remains idle. It can be any value from 0 to 65535.
+*/
+#define TMR3_CFG_PWM1_MATCH_VALUE                       (0u)
+
+/*************************************************************
+                        RGB Timer PWM2 Configuration
+ *************************************************************/
+
+/*! Timer PWM Enable Match. This will control PWM operation mode of the timer.
+    Toggle mode provides a 50% duty cycle and match mode provides a configurable
+    duty cycle by using the match value. This value can be set to\n
+    0 - PWM in toggle mode.\n
+    1 - PWM in match mode.
+*/
+#define TMR3_CFG_ENABLE_PWM2_MATCH_MODE                 (0u)
+
+
+/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n
+    0 - PWM idles low.\n
+    1 - PWM idles high.
+*/
+#define TMR3_CFG_PWM2_IDLE_STATE                        (0u)
+
+
+/*! PWM Match value. The value is used when the PWM is operating in match mode.
+    The PWM output is asserted when the Up/Down counter is equal to this match value.
+    PWM output is deasserted again when a timeout event occurs.
+    If the match value is never reached, or occurs simultaneous to a timeout event,
+    the PWM output remains idle. It can be any value from 0 to 65535.
+*/
+#define TMR3_CFG_PWM2_MATCH_VALUE                       (0u)
+
+/*! @} */
+
+/*************************************************************
+                        GP Timer 0 Macro Validation
+**************************************************************/
+
+#if TMR0_CFG_COUNT_UP > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR0_CFG_MODE > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR0_CFG_PRESCALE_FACTOR > 3u
+#error "Invalid configuration"
+#endif
+
+#if TMR0_CFG_CLOCK_SOURCE > 3u
+#error "Invalid configuration"
+#endif
+
+#if TMR0_CFG_LOAD_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif
+
+#if TMR0_CFG_ASYNC_LOAD_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif
+
+#if TMR0_CFG_ENABLE_RELOADING > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR0_CFG_ENABLE_SYNC_BYPASS > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR0_CFG_ENABLE_PRESCALE_RESET > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR0_CFG_ENABLE_EVENT_CAPTURE > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR0_CFG_EVENT_CAPTURE > 39u
+#error "Invalid configuration"
+#endif
+
+#if TMR0_CFG_ENABLE_PWM0_MATCH_MODE > 1u
+#error "Invalid configuration"
+#endif                   
+
+#if TMR0_CFG_PWM0_IDLE_STATE > 1u
+#error "Invalid configuration"
+#endif  
+
+#if TMR0_CFG_PWM0_MATCH_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif 
+
+/*************************************************************
+                        GP Timer 1 Macro Validation
+**************************************************************/
+
+#if TMR1_CFG_COUNT_UP > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR1_CFG_MODE > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR1_CFG_PRESCALE_FACTOR > 3u
+#error "Invalid configuration"
+#endif
+
+#if TMR1_CFG_CLOCK_SOURCE > 3u
+#error "Invalid configuration"
+#endif
+
+#if TMR1_CFG_LOAD_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif
+
+#if TMR1_CFG_ASYNC_LOAD_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif
+
+#if TMR1_CFG_ENABLE_RELOADING > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR1_CFG_ENABLE_SYNC_BYPASS > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR1_CFG_ENABLE_PRESCALE_RESET > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR1_CFG_ENABLE_EVENT_CAPTURE > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR1_CFG_EVENT_CAPTURE > 39u
+#error "Invalid configuration"
+#endif
+
+#if TMR1_CFG_ENABLE_PWM0_MATCH_MODE > 1u
+#error "Invalid configuration"
+#endif                   
+
+#if TMR1_CFG_PWM0_IDLE_STATE > 1u
+#error "Invalid configuration"
+#endif  
+
+#if TMR1_CFG_PWM0_MATCH_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif 
+
+/*************************************************************
+                        GP Timer 2 Macro Validation
+**************************************************************/
+
+#if TMR2_CFG_COUNT_UP > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR2_CFG_MODE > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR2_CFG_PRESCALE_FACTOR > 3u
+#error "Invalid configuration"
+#endif
+
+#if TMR2_CFG_CLOCK_SOURCE > 3u
+#error "Invalid configuration"
+#endif
+
+#if TMR2_CFG_LOAD_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif
+
+#if TMR2_CFG_ASYNC_LOAD_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif
+
+#if TMR2_CFG_ENABLE_RELOADING > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR2_CFG_ENABLE_SYNC_BYPASS > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR2_CFG_ENABLE_PRESCALE_RESET > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR2_CFG_ENABLE_EVENT_CAPTURE > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR2_CFG_EVENT_CAPTURE > 39u
+#error "Invalid configuration"
+#endif
+
+#if TMR2_CFG_ENABLE_PWM0_MATCH_MODE > 1u
+#error "Invalid configuration"
+#endif                   
+
+#if TMR2_CFG_PWM0_IDLE_STATE > 1u
+#error "Invalid configuration"
+#endif  
+
+#if TMR2_CFG_PWM0_MATCH_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif 
+
+/*************************************************************
+                        RGB Timer Macro Validation
+**************************************************************/
+
+#if TMR3_CFG_COUNT_UP > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_MODE > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_PRESCALE_FACTOR > 3u
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_CLOCK_SOURCE > 3u
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_LOAD_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_ASYNC_LOAD_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_ENABLE_RELOADING > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_ENABLE_SYNC_BYPASS > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_ENABLE_PRESCALE_RESET > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_ENABLE_EVENT_CAPTURE > 1u
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_EVENT_CAPTURE > 39u
+#error "Invalid configuration"
+#endif
+
+#if TMR3_CFG_ENABLE_PWM0_MATCH_MODE > 1u
+#error "Invalid configuration"
+#endif                   
+
+#if TMR3_CFG_PWM0_IDLE_STATE > 1u
+#error "Invalid configuration"
+#endif  
+
+#if TMR3_CFG_PWM0_MATCH_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif 
+
+#if TMR3_CFG_ENABLE_PWM1_MATCH_MODE > 1u
+#error "Invalid configuration"
+#endif                   
+
+#if TMR3_CFG_PWM1_IDLE_STATE > 1u
+#error "Invalid configuration"
+#endif  
+
+#if TMR3_CFG_PWM1_MATCH_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif 
+
+#if TMR3_CFG_ENABLE_PWM2_MATCH_MODE > 1u
+#error "Invalid configuration"
+#endif                   
+
+#if TMR3_CFG_PWM2_IDLE_STATE > 1u
+#error "Invalid configuration"
+#endif  
+
+#if TMR3_CFG_PWM2_MATCH_VALUE > 0xFFFFu
+#error "Invalid configuration"
+#endif 
+
+/*! @} */
+
+
+#endif /* ADI_TMR_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_uart_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_uart_config.h
new file mode 100755
index 00000000000..1cf72a4b91a
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_uart_config.h
@@ -0,0 +1,496 @@
+/*!
+ *****************************************************************************
+   @file:    adi_uart_config.h
+   @brief:   Configuration options for UART driver.
+             This is specific to the UART driver and will be included by the driver.
+             It is not required for the application to include this header file.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_UART_CONFIG_H
+#define ADI_UART_CONFIG_H
+
+/** @addtogroup UART_Driver_Config Static Configuration
+ *  @ingroup UART_Driver
+ *  @{
+ */
+
+
+#include <adi_global_config.h>
+
+/************** Common UART Driver configurations ************** */ 
+/*!
+   Enable the autobaud detection. \n
+   Range: 0 to 1.
+*/
+#define ADI_UART_CFG_ENABLE_AUTOBAUD                 1
+
+
+/** @addtogroup UART0_Driver_Config UART0 Static Configuration
+ *  @ingroup UART_Driver_Config
+ *  @{
+ */
+ 
+/************** UART Driver configurations FOR UART 0 ************** */
+/*!
+   Word length Select. \n
+   0 -  5 Bits word length. \n
+   1 -  6 Bits word length. \n
+   2 -  7 Bits word length. \n
+   3 -  8 Bits word length.
+*/
+#define ADI_UART0_CFG_WORD_LENGTH                  3
+
+
+/*!
+   Stop bit selection. \n
+   0 -  Send 1 stop bit regardless of the word length. \n
+   1 -  Send a number of stop bits based on the word length. \n
+        WORD-LENGTH 5 Bits       => 1.5 Stop Bits. \n
+        WORD-LENGTH (6/7/8) Bits => 2   Stop Bits.
+*/
+#define ADI_UART0_CFG_STOP_BIT                      1
+
+
+/*!
+   Parity Enable. Used to control the parity bit. \n
+   0 -  Parity will not be transmitted or checked. \n
+   1 -  Parity will be transmitted and checked.
+*/
+#define ADI_UART0_CFG_ENABLE_PARITY                 0
+
+
+/*!
+   Parity Select. This bit only has meaning if parity is enabled. \n
+   0 - Odd parity will be transmitted and checked. \n
+   1 - Even parity will be transmitted and checked.
+*/
+#define ADI_UART0_CFG_PARITY_SELECTION              0
+
+
+/*!
+   Stick Parity. Used to force parity to defined values. \n
+   0 -  Parity will not be forced. \n
+   1 -  Set parity based on the following bit settings: \n
+        EPS = 1 and PEN = 1, parity will be forced to 0. \n
+        EPS = 0 and PEN = 1, parity will be forced to 1. \n
+        EPS = 1/0 and PEN = 0, no parity will be transmitted.
+*/
+#define ADI_UART0_CFG_ENABLE_STICKY_PARITY          0
+
+
+/*
+  Table 21-2: Baud Rate Examples Based on 26 MHz PCLK
+  Baud Rate OSR COMDIV DIVM DIVN
+  9600        3 24     3    1078
+  19200       3 12     3    1078
+  38400       3 8      2    1321
+  57600       3 4      3    1078
+  115200      3 4      1    1563
+  230400      3 2      1    1563
+  460800      3 1      1    1563
+  921,600     2 1      1    1563
+  1,000,000   2 1      1    1280
+  1,500,000   2 1      1    171
+
+These are calculated with the UarDivCalculator tool.
+*/
+
+/*!
+   Fractional baud rate N divide value. \n
+   Range: 0 to 2047.
+*/
+#define ADI_UART0_CFG_DIVN                           1078
+
+
+/*!
+   Fractional baud rate M divide value. \n
+   Range: 1 to 3.
+*/
+#define ADI_UART0_CFG_DIVM                           3
+
+
+/*!
+   Fractional baud rate C divide value. \n
+   Range: 1 to 65535.
+*/
+#define ADI_UART0_CFG_DIVC                           24
+
+
+/*!
+   Over Sample Rate value. \n
+   Range: 0 to 3. \n
+   0 - Over sample by 4. \n
+   1 - Over sample by 8. \n
+   2 - Over sample by 16. \n
+   3 - Over sample by 32.
+
+*/
+#define ADI_UART0_CFG_OSR                            3
+
+
+/*!
+   Enable Internal FIFO. \n
+   Range: 0 to 1.
+*/
+#define ADI_UART0_CFG_ENABLE_FIFO                    1
+
+
+/*!
+   TRIG Level for  UART device. \n
+   Range: 0 to 3. \n
+   0 - 1 byte to trig RX interrupt. \n
+   1 - 4 bytes to trig RX interrupt. \n
+   2 - 8 bytes to trig RX interrupt. \n
+   3 - 14 bytes to trig RX interrupt.
+*/
+#define ADI_UART0_CFG_TRIG_LEVEL                     0
+
+
+/*!
+   Hold TX while RX is active.  \n
+   Range: 0 to 1.
+*/
+#define ADI_UART0_CFG_HOLD_TX                        0
+
+
+/*!
+   Disable RX when TX is active. \n
+   Range: 0 to 1. \n
+   0 - 1 byte to trig RX interrupt. \n
+   1 - 4 bytes to trig RX interrupt.
+*/
+#define ADI_UART0_CFG_DISABLE_RX                     0
+
+
+/*!
+   Configure the SOUT de-assertion earlier than full stop bit(s). \n
+   Range: 0 to 1. \n
+   0 - SOUT_EN de-assert same time as full stop bit(s). \n
+   1 - SOUT_EN de-assert half-bit earlier than full stop bit(s).
+*/
+#define ADI_UART0_CFG_DEASSERTION                     0
+
+
+/*!
+   Set the SOUT polarity low. \n
+   Range: 0 to 1. \n
+   0 - Active high. \n
+   1 - Active low.
+*/
+#define ADI_UART0_CFG_SOUT_POLARITY                   0
+
+/*!
+   Enable the RX status interrupt. \n
+   Range: 0 to 1.
+*/
+#define ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT      1
+
+
+/*!
+   Enable the Modem status interrupt. \n
+   Range: 0 to 1.
+*/
+#define ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT   0
+
+/*! @} */
+
+
+/***************  UART Driver configurations FOR UART 1 **************/
+
+/** @addtogroup UART1_Driver_Config UART1 Static Configuration
+ *  @ingroup UART_Driver_Config
+ *  @{
+ */
+
+/*!
+   Word length Select. \n
+   0 -  5 Bits word length. \n
+   1 -  6 Bits word length. \n
+   2 -  7 Bits word length. \n
+   3 -  8 Bits word length.
+*/
+#define ADI_UART1_CFG_WORD_LENGTH                     3
+
+
+/*!
+   Stop bit selection.\n
+   0 -  Send 1 stop bit regardless of the word length. \n
+   1 -  Send a number of stop bits based on the word length. \n
+        WORD-LENGTH 5 Bits       => 1.5 Stop Bits. \n
+        WORD-LENGTH (6/7/8) Bits => 2   Stop Bits.
+*/
+#define ADI_UART1_CFG_STOP_BIT                        1
+
+
+/*!
+   Parity Enable. Used to control the parity bit. \n
+   0 -  Parity will not be transmitted or checked. \n
+   1 -  Parity will be transmitted and checked.
+*/
+#define ADI_UART1_CFG_ENABLE_PARITY                   0
+
+
+/*!
+   Parity Select. This bit only has meaning if parity is enabled. \n
+   0 - Odd parity will be transmitted and checked. \n
+   1 - Even parity will be transmitted and checked.
+*/
+#define ADI_UART1_CFG_PARITY_SELECTION                0
+
+
+/*!
+   Stick Parity. Used to force parity to defined values. \n
+   0 -  Parity will not be forced. \n
+   1 -  Set parity based on the following bit settings: \n
+        EPS = 1 and PEN = 1, parity will be forced to 0. \n
+        EPS = 0 and PEN = 1, parity will be forced to 1. \n
+        EPS = 1/0 and PEN = 0, no parity will be transmitted.
+*/
+#define ADI_UART1_CFG_ENABLE_STICKY_PARITY            0
+
+
+/*
+  Table 21-2: Baud Rate Examples Based on 26 MHz PCLK
+  Baud Rate OSR COMDIV DIVM DIVN
+  9600        3 24     3    1078
+  19200       3 12     3    1078
+  38400       3 8      2    1321
+  57600       3 4      3    1078
+  115200      3 4      1    1563
+  230400      3 2      1    1563
+  460800      3 1      1    1563
+  921,600     2 1      1    1563
+  1,000,000   2 1      1    1280
+  1,500,000   2 1      1    171
+
+These are calculated with the UarDivCalculator tool.
+*/
+
+/*!
+   Fractional baud rate N divide value. \n
+   Range: 0 to 2047.
+*/
+#define ADI_UART1_CFG_DIVN                              1563
+
+
+/*!
+   Fractional baud rate M divide value. \n
+   Range: 1 to 3.
+*/
+#define ADI_UART1_CFG_DIVM                             1
+
+
+/*!
+   Fractional baud rate C divide value. \n
+   Range: 1 to 65535.
+*/
+#define ADI_UART1_CFG_DIVC                             1
+
+
+/*!
+   Over Sample Rate value. \n
+   Range: 0 to 3. \n
+   0 - Over sample by 4. \n
+   1 - Over sample by 8. \n
+   2 - Over sample by 16. \n
+   3 - Over sample by 32.
+
+*/
+#define ADI_UART1_CFG_OSR                              3
+
+
+/*!
+   Enable Internal FIFO. \n
+   Range: 0 to 1.
+*/
+#define ADI_UART1_CFG_ENABLE_FIFO                      1
+
+
+/*!
+   TRIG Level for  UART device. \n
+   Range: 0 to 3. \n
+   0 - 1 byte to trig RX interrupt. \n
+   1 - 4 bytes to trig RX interrupt. \n
+   2 - 8 bytes to trig RX interrupt. \n
+   3 - 14 bytes to trig RX interrupt.
+*/
+#define ADI_UART1_CFG_TRIG_LEVEL                       0
+
+
+/*!
+   Hold TX while RX is active.  \n
+   Range: 0 to 1.
+*/
+#define ADI_UART1_CFG_HOLD_TX                          0
+
+
+/*!
+   Disable RX when TX is active. \n
+   Range: 0 to 1. \n
+   0 - 1 byte to trig RX interrupt. \n
+   1 - 4 bytes to trig RX interrupt.
+*/
+#define ADI_UART1_CFG_DISABLE_RX                       0
+
+
+/*!
+   Configure the SOUT de-assertion earlier than full stop bit(s). \n
+   Range: 0 to 1. \n
+   0 - SOUT_EN de-assert same time as full stop bit(s). \n
+   1 - SOUT_EN de-assert half-bit earlier than full stop bit(s).
+*/
+#define ADI_UART1_CFG_DEASSERTION                     0
+
+
+/*!
+   Set the SOUT polarity low. \n
+   Range: 0 to 1. \n
+   0 - Active high. \n
+   1 - Active low.
+*/
+#define ADI_UART1_CFG_SOUT_POLARITY                   0
+
+/*!
+   Enable the RX status interrupt. \n
+   Range: 0 to 1.
+*/
+#define ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT       1
+
+
+/*!
+   Enable the Modem status interrupt. \n
+   Range: 0 to 1.
+*/
+#define ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT    0
+/*! @} */
+
+/*! @} */
+
+
+/***************  UART Driver Debug Checks ************** */
+
+/* Check word length */
+#if (((ADI_UART0_CFG_WORD_LENGTH < 0) || (ADI_UART0_CFG_WORD_LENGTH > 3))  || ((ADI_UART1_CFG_WORD_LENGTH < 0) || (ADI_UART1_CFG_WORD_LENGTH > 3)))
+#error "Word length needs to be between 0 and 3"
+#endif
+
+/* Check stop bit */
+#if (((ADI_UART0_CFG_STOP_BIT < 0) || (ADI_UART0_CFG_STOP_BIT > 1))  || ((ADI_UART1_CFG_STOP_BIT < 0) || (ADI_UART1_CFG_STOP_BIT > 1)))
+#error "Stop bit selection needs to be 0 or 1"
+#endif
+
+/* Check parity enable  */
+#if (((ADI_UART0_CFG_ENABLE_PARITY < 0) || (ADI_UART0_CFG_ENABLE_PARITY > 1))  || ((ADI_UART1_CFG_ENABLE_PARITY < 0) || (ADI_UART1_CFG_ENABLE_PARITY > 1)))
+#error "Parity Enable bit needs to be 0 or 1"
+#endif
+
+/* Check parity select */
+#if (((ADI_UART0_CFG_PARITY_SELECTION < 0) || (ADI_UART0_CFG_PARITY_SELECTION > 1))  || ((ADI_UART1_CFG_PARITY_SELECTION < 0) || (ADI_UART1_CFG_PARITY_SELECTION > 1)))
+#error "Parity bit selection needs to be 0 or 1"
+#endif
+
+/* Check enable sticky parity */
+#if (((ADI_UART0_CFG_ENABLE_STICKY_PARITY < 0) || (ADI_UART0_CFG_ENABLE_STICKY_PARITY > 1))  || ((ADI_UART1_CFG_ENABLE_STICKY_PARITY < 0) || (ADI_UART1_CFG_ENABLE_STICKY_PARITY > 1)))
+#error "Sticky parity enable needs to be 0 or 1"
+#endif
+
+/* Check fractional baudrate N divider value */
+#if (((ADI_UART0_CFG_DIVN < 0) || (ADI_UART0_CFG_DIVN > 2047))  || ((ADI_UART1_CFG_DIVN < 0) || (ADI_UART1_CFG_DIVN > 2047)))
+#error "Fractional baudrate N divider value needs to be between 0 and 2047"
+#endif
+
+/* Check fractional baudrate M divider value */
+#if (((ADI_UART0_CFG_DIVM < 1) || (ADI_UART0_CFG_DIVM > 3))  || ((ADI_UART1_CFG_DIVM < 1) || (ADI_UART1_CFG_DIVM > 3)))
+#error "Fractional baudrate M divider value needs to be between 1 and 3"
+#endif
+
+/* Check fractional baudrate C divider value */
+#if (((ADI_UART0_CFG_DIVC < 1) || (ADI_UART0_CFG_DIVC > 65535))  || ((ADI_UART1_CFG_DIVC < 1) || (ADI_UART1_CFG_DIVC > 65535)))
+#error "Fractional baudrate C divider value needs to be between 1 and 65535"
+#endif
+
+/* Check over same rate value */
+#if (((ADI_UART0_CFG_OSR < 0) || (ADI_UART0_CFG_OSR > 3))  || ((ADI_UART1_CFG_OSR < 0) || (ADI_UART1_CFG_OSR > 3)))
+#error "over sample rate value needs to be between 0 and 3"
+#endif
+
+/* Check enable internal FIFO */
+#if (((ADI_UART0_CFG_ENABLE_FIFO < 0) || (ADI_UART0_CFG_ENABLE_FIFO > 1))  || ((ADI_UART1_CFG_ENABLE_FIFO < 0) || (ADI_UART1_CFG_ENABLE_FIFO > 1)))
+#error "Enable internal FIFO needs to be 0 or 1"
+#endif
+
+/* Check UART trig level */
+#if (((ADI_UART0_CFG_TRIG_LEVEL < 0) || (ADI_UART0_CFG_TRIG_LEVEL > 3))  || ((ADI_UART1_CFG_TRIG_LEVEL < 0) || (ADI_UART1_CFG_TRIG_LEVEL > 3)))
+#error "Trig level for the UART device needs to be 0 or 1"
+#endif
+
+/* Check value for holding tx while rx is active */
+#if (((ADI_UART0_CFG_HOLD_TX < 0) || (ADI_UART0_CFG_HOLD_TX > 1))  || ((ADI_UART1_CFG_HOLD_TX < 0) || (ADI_UART1_CFG_HOLD_TX > 1)))
+#error "Value for holding Tx while Rx is active needs to be 0 or 1"
+#endif
+
+/* Check value de-assertion */
+#if (((ADI_UART0_CFG_DEASSERTION < 0) || (ADI_UART0_CFG_DEASSERTION > 1))  || ((ADI_UART1_CFG_DEASSERTION < 0) || (ADI_UART1_CFG_DEASSERTION > 1)))
+#error "Value for de-assertion needs to be 0 or 1"
+#endif
+
+/* Check value for SOUT polarity */
+#if (((ADI_UART0_CFG_SOUT_POLARITY < 0) || (ADI_UART0_CFG_SOUT_POLARITY > 1))  || ((ADI_UART1_CFG_SOUT_POLARITY < 0) || (ADI_UART1_CFG_SOUT_POLARITY > 1)))
+#error "Value for SOUT polarity needs to be 0 or 1"
+#endif
+
+/* Check value to enable autobaud detection */
+#if ((ADI_UART_CFG_ENABLE_AUTOBAUD < 0) || (ADI_UART_CFG_ENABLE_AUTOBAUD > 1))
+#error "Value for autobaud enable needs to be 0 or 1"
+#endif
+
+/* Check value to enable Rx status interrupt */
+#if (((ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT < 0) || (ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT > 1))  || ((ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT < 0) || (ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT > 1)))
+#error "Value to enable Rx status interrupt needs to be 0 or 1"
+#endif
+
+/* Check value to enable modem status interrupt */
+#if (((ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT < 0) || (ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT > 1))  || ((ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT < 0) || (ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT > 1)))
+#error "Value to enable modem status interrupt needs to be 0 or 1"
+#endif
+
+#endif /* ADI_UART_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_wdt_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_wdt_config.h
new file mode 100755
index 00000000000..25e47a78509
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_wdt_config.h
@@ -0,0 +1,119 @@
+/*! *****************************************************************************
+ * @file    adi_wdt_config.h
+ * @brief   WDT device driver configuration
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+
+#ifndef ADI_WDT_CONFIG_H
+#define ADI_WDT_CONFIG_H
+
+
+/** @addtogroup WDT_Driver_Config Static Configuration
+ *  @ingroup WDT_Driver
+ *  @{
+ */
+
+
+/************* WDT Static Configuration ***************/
+
+/*! WDT Timer Reload Value\n
+    Value used to reload the WDT count register after count expires.\n
+   0-65535 - WDT reload value (default is 0x0100).
+*/
+#define ADI_WDT_LOAD_VALUE                                  (0x1000u)
+
+/*! WDT Timer Mode\n
+   Selects WDT operating mode.\n
+   0 -  WDT operates in free-running mode.\n
+   1 -  WDT operates in periodic mode (default).
+*/
+#define ADI_WDT_CONTROL_TIMER_MODE                               (1u)
+
+/*! WDT Clock Prescaler\n
+   Controls WDT clock prescale.\n
+   0 -  WDT operates at (source clock)/1.\n
+   1 -  WDT operates at (source clock)/16.\n
+   2 -  WDT operates at (source clock)/256 (default).\n
+*/
+#define ADI_WDT_CONTROL_CLOCK_PRESCALER                          (2u)
+
+/*! WDT Timeout Mode\n
+   Controls WDT timeout behaviour.\n
+   0 -  WDT issues RESET on timeout (default).\n
+   1 -  WDT issues INTERRUPT on timeout.
+*/
+#define ADI_WDT_CONTROL_TIMEOUT_MODE                             (0u)
+
+/*! WDT Power Mode Disable\n
+   Controls WDT countdown in hibernate or halted mode.\n
+   0 -  WDT continues to count down when core is halted or in hibernate.\n
+   1 -  WDT pauses count down when core is halted or in hibernate (default).\n
+*/
+#define ADI_WDT_CONTROL_POWER_MODE                               (1u)
+
+/************** Macro Validation *****************************/
+
+#if ( ADI_WDT_LOAD_VALUE  > 65535u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_WDT_CONTROL_TIMER_MODE > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_WDT_CONTROL_CLOCK_PRESCALER > 2u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_WDT_CONTROL_TIMEOUT_MODE > 1u )
+#error "Invalid configuration"
+#endif
+
+#if ( ADI_WDT_CONTROL_POWER_MODE > 1u )
+#error "Invalid configuration"
+#endif
+
+/**
+ *  @}
+ */
+
+#endif /* ADI_WDT_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crc/adi_crc.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crc/adi_crc.c
new file mode 100755
index 00000000000..4ea2233205c
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crc/adi_crc.c
@@ -0,0 +1,1279 @@
+/*! ****************************************************************************
+ * @file:    adi_crc.c
+ * @brief:   CRC device driver global file.
+ * @details: This file contain the CRC device driver impelementation.
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders. This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#include <adi_processor.h>
+#include <rtos_map/adi_rtos_map.h>
+
+
+/** @addtogroup  CRC_Driver CRC Device Driver
+ *  @{
+
+@brief <b>Cyclic Redundancy Check (CRC) peripheral driver</b>
+@details
+
+The CRC peripheral is used to perform the Cyclic Redundancy Check (CRC) of the
+block of data that is presented to the peripheral. The peripheral provides a
+means to periodically verify the integrity of the system memory and it is based
+on a CRC32 engine that computes the signature of 32-bit data presented to the
+hardware engine. CRC operations can be core driven or DMA driven depending on
+static configuration.
+
+    - #ADI_CRC_CFG_ENABLE_DMA_SUPPORT set to 0 defines a core driven CRC driver
+    - #ADI_CRC_CFG_ENABLE_DMA_SUPPORT set to a non 0 value defines a DMA driven
+      CRC driver
+
+<b>Core driven CRC operations</b>
+
+The adi_crc_Compute function executes core driven CRC operations to calculate the
+CRC on the buffer input with the CRC parameters set in the driver. In this mode,
+data in the submitted buffer is transmitted to the CRC directly by the core.
+
+<b>Memory DMA driver CRC operations</b>
+
+The adi_crc_Compute function executes DMA driven CRC operations to calculate the
+CRC on the buffer input with the CRC parameters set in the driver. In this mode,
+data in the submitted buffer is transmitted to the CRC through DMA transfers.
+
+The software DMA channel reserved for the CRC driver is defined by a macro,
+ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID, which can take a value between 0 and 7.
+If this macro is not defined, e.g. in a configuration file, then its value
+is defaulted to 7: in this case, DMA channel SIP7 is used by the CRC driver
+and DMA_SIP7_Int_Handler becomes the interrupt used by the DMA when a transfer
+to the CRC is complete.
+
+<em><b>Computing CRC</b></em>
+
+The CRC engine performs a 32-bit CRC operation on the incoming data stream.
+
+Sequence of function calls for Computing CRC :\n
+    - #adi_crc_Open() to open CRC device and get a valid CRC handle.
+    - #adi_crc_SetPolynomialVal() to set the polynomial value to be used in CRC operations.
+    - #adi_crc_SetBitMirroring() to enable/disable bit mirroring
+    - #adi_crc_SetByteMirroring() to enable/disable byte mirroring
+    - #adi_crc_SetLSBFirst() to indicate if data is Big or Little Endian.
+    - #adi_crc_IsCrcInProgress() to poll the current status of CRC operation or
+      wait for callback event.
+    - #adi_crc_GetFinalCrcVal() to get the CRC value of the data stream if its
+      CRC value is unknown. (Note that #adi_crc_GetFinalCrcVal resets the CRC
+      seed to the #ADI_CFG_CRC_SEED_VALUE default value.)
+
+      Note that using statically configured parameters such as
+      #ADI_CFG_CRC_ENABLE_BYTE_MIRRORING, #ADI_CFG_CRC_ENABLE_BIT_MIRRORING,
+      #ADI_CFG_CRC_POLYNOMIAL and #ADI_CFG_CRC_SEED_VALUE, functions
+      #adi_crc_SetBitMirroring, #adi_crc_SetByteMirroring, #adi_crc_SetPolynomialVal
+      and #adi_crc_SetBitMirroring don't need to be called explicitly in your
+      application: the parameters will be assigned when opening the driver.
+
+  @note - The application must include drivers/crc/adi_crc.h to use this driver.
+  @note - This driver also requires the DMA driver.  The application must include
+          the DMA driver sources to avoid link errors.
+ */
+
+/*! \cond PRIVATE */
+/*=============  I N C L U D E S   =============*/
+
+#include <drivers/crc/adi_crc.h>
+#include <adi_cyclecount.h>
+#include "adi_crc_def.h"
+
+/*=============  M I S R A  =============*/
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
+*   This isn't a header as such.
+*
+* Pm088 (rule 17.4): pointer arithmetic should not be used.
+* Pm152 (rule 17.4): array indexing shall only be applied to objects defined as an array type
+*   Relying on pointer arithmetic for buffer handling.
+*
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   Casts from pointer to uint32_t needed to determine pointer alignment.
+*/
+#pragma diag_suppress=Pm123,Pm088,Pm152,Pm140
+#endif /* __ICCARM__ */
+
+/*==============  D E F I N E S  ===============*/
+
+/* CRC Peripheral specific information */
+#define ADI_CRC_NUM_DEVICES             (1u)
+
+/*! \endcond */
+
+#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT != 0)
+
+/**
+ * If a DMA channel has not been configured for the CRC driver,
+* then a default software DMA channel is assigned: SIP7.
+ */
+
+#ifndef ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID
+#define ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID 7
+#pragma message("ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID implicitly defaulted to 7!")
+#endif
+
+/**
+ * The following macros define
+ * - the Software DMA channel identifier to be used in CRC DMA driven operations
+ * - the ISR used by the CRC, which depends on the Software DMA channel
+ *   selected to drive the CRC in DMA driven CRC operations.
+ * - the interrupt identifier mapped to the software DMA channel; selected for
+ *   the CRC operations
+ */
+#if   (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 0)
+#define ADI_CFG_CRC_DMA_CHANNEL         SIP0_CHANn
+#define ADI_DMA_CRC_ISR                 DMA_SIP0_Int_Handler
+#define ADI_CRC_IRQ_ID                  DMA0_CH16_DONE_IRQn
+#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 1)
+#define ADI_CFG_CRC_DMA_CHANNEL         SIP1_CHANn
+#define ADI_DMA_CRC_ISR                 DMA_SIP1_Int_Handler
+#define ADI_CRC_IRQ_ID                  DMA0_CH17_DONE_IRQn
+#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 2)
+#define ADI_CFG_CRC_DMA_CHANNEL         SIP2_CHANn
+#define ADI_DMA_CRC_ISR                 DMA_SIP2_Int_Handler
+#define ADI_CRC_IRQ_ID                  DMA0_CH18_DONE_IRQn
+#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 3)
+#define ADI_CFG_CRC_DMA_CHANNEL         SIP3_CHANn
+#define ADI_DMA_CRC_ISR                 DMA_SIP3_Int_Handler
+#define ADI_CRC_IRQ_ID                  DMA0_CH19_DONE_IRQn
+#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 4)
+#define ADI_CFG_CRC_DMA_CHANNEL         SIP4_CHANn
+#define ADI_DMA_CRC_ISR                 DMA_SIP4_Int_Handler
+#define ADI_CRC_IRQ_ID                  DMA0_CH20_DONE_IRQn
+#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 5)
+#define ADI_CFG_CRC_DMA_CHANNEL         SIP5_CHANn
+#define ADI_DMA_CRC_ISR                 DMA_SIP5_Int_Handler
+#define ADI_CRC_IRQ_ID                  DMA0_CH21_DONE_IRQn
+#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 6)
+#define ADI_CFG_CRC_DMA_CHANNEL         SIP6_CHANn
+#define ADI_DMA_CRC_ISR                 DMA_SIP6_Int_Handler
+#define ADI_CRC_IRQ_ID                  DMA0_CH22_DONE_IRQn
+#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 7)
+#define ADI_CFG_CRC_DMA_CHANNEL         SIP7_CHANn
+#define ADI_DMA_CRC_ISR                 DMA_SIP7_Int_Handler
+#define ADI_CRC_IRQ_ID                  DMA0_CH23_DONE_IRQn
+#else
+#error "Invalid Software DMA channel identifier ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID: it must be between 0 and 7"
+#endif
+
+#endif  /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */
+
+/*! \cond PRIVATE */
+
+/** Check the validity of a CRC device identifier */
+#define ADI_CRC_VALID_DEVICE_ID(DEVNUM)         ((DEVNUM)<(ADI_CRC_NUM_DEVICES))
+
+/** Check that a CRC driver is in idle state */
+#define ADI_CRC_DEVICE_IS_IDLE(DEV)             (((DEV)->eCrcOpStatus == ADI_CRC_OP_IDLE) ? true : false)
+
+/*==============  D A T A  ===============*/
+
+/**
+ * Information for managing all the CRC devices available
+ */
+static ADI_CRC_INFO crc_device_info[ADI_CRC_NUM_DEVICES] =
+{
+   { pADI_CRC0,  NULL }      /* CRC  0 */
+};
+
+/*==============  M O R E   D E F I N E S  ===============*/
+
+/** Check the validity of a CRC handle for debug mode */
+#define ADI_CRC_INVALID_HANDLE(h)               ((NULL == (h)) || (crc_device_info[0].hDevice != (h)))
+
+/** Condition used to indicate if a CRC driver is already in use */
+#define ADI_CRC_DEVICE_IN_USE(DEVNUM)           ((NULL) != crc_device_info[(DEVNUM)].hDevice)
+
+#ifdef ADI_DEBUG
+#define HDL_TO_DEVICE_PTR(HDL) ((ADI_CRC_INVALID_HANDLE(HDL)) ? (NULL) : ((ADI_CRC_DEVICE*) (HDL)))
+#else
+#define HDL_TO_DEVICE_PTR(HDL) ((ADI_CRC_DEVICE*) (HDL))
+#endif
+
+/*=============  C O D E  =============*/
+
+#if (ADI_CRC_NUM_DEVICES!=1u)
+#error "!!! Current CRC driver implementation can deal with a unique CRC instance !!!"
+#endif
+
+/*=============  L O C A L   F U N C T I O N S =============*/
+
+/* Prototypes for static functions (required by MISRA-C:2004 Rule 8.1)  */
+
+static ADI_CRC_INFO *crc_DeviceInfo(ADI_CRC_HANDLE hDevice);
+
+static void crc_ResetRegisters (ADI_CRC_DEVICE *pDevice);
+
+#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT == 0)
+
+/* Functions specific to core driven CRC operations */
+
+static ADI_CRC_RESULT crc_ExecuteCoreDrivenOperation (ADI_CRC_DEVICE *pDevice, void *pCrcBuf, uint32_t NumBytes, uint32_t NumBits);
+
+#else
+
+/* Functions specific to DMA driven CRC operations */
+
+static ADI_CRC_RESULT crc_ExecuteDmaDrivenOperation(ADI_CRC_DEVICE *pDevice, void *pCrcBuf, uint32_t NumBytes, uint32_t NumBits);
+static void crc_CalculateCrcForRemaining(ADI_CRC_DEVICE *pDevice, uint8_t *pData, uint32_t NumBytes, uint32_t NumBits);
+static void CRC_Callback_For_DMA_Err_Int_Handler(void *pcbparam, uint32_t nEvent, void *pArg);
+void ADI_DMA_CRC_ISR(void);
+
+#endif  /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */
+
+
+/**
+ * @brief       return a pointer to the CRC device information mapped to the CRC
+ *              device identified by a handle
+ *
+ * @param [in]  hDevice         CRC device handle
+ *
+ * @return      pointer to CRC device information identified by hDevice
+ *              (NULL if the CRC device handle is invalid)
+ */
+static ADI_CRC_INFO *crc_DeviceInfo(ADI_CRC_HANDLE hDevice)
+{
+    ADI_CRC_INFO *pCrcInfo = (ADI_CRC_INVALID_HANDLE(hDevice))
+                           ? NULL
+                           : (&(crc_device_info[0]));
+    return pCrcInfo;
+}
+
+
+/**
+ * @brief       Reset CRC registers to default values
+ *
+ * @details     Reset CRC registers to default values as defined in configuration.
+ *
+ * @param [in]  pDevice         Pointer to CRC device
+ *
+ * @return      None
+ */
+static void crc_ResetRegisters(ADI_CRC_DEVICE *pDevice)
+{
+    /* Cast the values to be assigned to the targetted types */
+    const uint32_t byte_mirroring_val = (uint32_t) ADI_CFG_CRC_ENABLE_BYTE_MIRRORING;
+    const uint32_t byte_mirroring_pos = (uint32_t) BITP_CRC_CTL_BYTMIRR;
+    const uint32_t bit_mirroring_val  = (uint32_t) ADI_CFG_CRC_ENABLE_BIT_MIRRORING;
+    const uint32_t bit_mirroring_pos  = (uint32_t) BITP_CRC_CTL_BITMIRR;
+    const uint32_t seed_value = (uint32_t) ADI_CFG_CRC_SEED_VALUE;
+    const uint32_t polynomial = (uint32_t) ADI_CFG_CRC_POLYNOMIAL;
+
+    /* Set byte mirroring and bit mirroring in CTL register as configured */
+    pDevice->pReg->CTL = ( (byte_mirroring_val << byte_mirroring_pos)
+                         | (bit_mirroring_val << bit_mirroring_pos)
+                         );
+    pDevice->pReg->RESULT = seed_value;
+    pDevice->pReg->POLY   = polynomial;
+}
+
+#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT == 0)
+
+/*
+ * @brief       Starts core driven CRC operation.
+ *
+ * @param [in]  pDevice         Pointer to CRC device
+ * @param [in]  pCrcBuf         Address of data buffer.
+ * @param [in]  NumBytes        Number of bytes in data buffer.
+ * @param [in]  NumBits         Number of bits, 0 to 7, in the last partial byte
+ *                              in CRC data buffer
+ *
+ * @return      Status
+ *              - ADI_CRC_SUCCESS: Successfully set expected CRC result.
+ */
+static ADI_CRC_RESULT crc_ExecuteCoreDrivenOperation(
+    ADI_CRC_DEVICE      *pDevice,
+    void                *pCrcBuf,
+    uint32_t            NumBytes,
+    uint32_t            NumBits)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    uint8_t *pData = (uint8_t *)pCrcBuf;        /* initialize the pointer to data to the start of the data buffer */
+    uint32_t lsbFirst = pDevice->pReg->CTL & BITM_CRC_CTL_LSBFIRST;
+
+    pDevice->pReg->CTL |= (BITM_CRC_CTL_EN);    /*! enable CRC peripheral */
+
+    if (((uint32_t)pData & 0x3u) != 0u)         /* If the buffer is not 4-byte aligned */
+    {
+        /* feed the CRC byte per byte as long as there are data in the input buffer AND
+         * the data left in the buffer are not 4-byte aligned */
+        while ((NumBytes > 0u) && (((uint32_t)pData & 0x3u) != 0u))
+        {
+            pDevice->pReg->IPBYTE = *pData;     /* feed the CRC with the first byte in the buffer */
+            pData++;                            /* get the next byte to feed into CRC */
+            NumBytes--;                         /* decrease the number of bytes to be processed */
+        }
+    }
+
+    /* data left in the input buffer are now 4-byte aligned */
+
+    while (NumBytes >= 4u)                      /* if the number of bytes left is greater than 4 bytes */
+    {                                           /* feed CRC peripheral with 4-byte data */
+        uint32_t nData;                         /* 32-bit variable to be used to feed the CRC peripheral */
+
+        /*
+         * Here we assume memory is little endian. We need change the following
+         * code if we produce a Cortex-M processor with big endian memory.
+         */
+        if (lsbFirst != 0u)
+        {
+            nData = pData[3];
+            nData = (nData << 8) | pData[2];
+            nData = (nData << 8) | pData[1];
+            nData = (nData << 8) | pData[0];
+        }
+        else
+        {
+            nData = pData[0];
+            nData = (nData << 8) | pData[1];
+            nData = (nData << 8) | pData[2];
+            nData = (nData << 8) | pData[3];
+        }
+        pDevice->pReg->IPDATA = nData;          /* feed the CRC peripheral with 32-bit data input */
+        pData += 4;                             /* move the data pointer in the data buffer */
+        NumBytes -= 4u;                         /* decrease the number of data to be processed */
+    }
+
+    while (NumBytes > 0u)                       /* if the number of data left in the input buffer is smaller than 4 */
+    {
+        pDevice->pReg->IPBYTE = *pData;         /* feed the CRC peripheral with the remaining bytes */
+        pData++;                                /* move the pointer to the next byte in input data buffer */
+        NumBytes--;                             /* decrease the number of data to be fed into the CRC peripheral */
+    }
+
+    if (NumBits > 0u)                           /* if the last byte is a partial byte containing less than 8 bits */
+    {
+        pDevice->pReg->IPBITS[NumBits] = *pData;/* feed the CRC peripheral with the remaining bits (use IPBITS[N] to feed N bits) */
+    }
+
+    pDevice->pReg->CTL &= ~(BITM_CRC_CTL_EN);   /* All the data have been fed into the CRC peripheral : disable it */
+    pDevice->eCrcOpStatus = ADI_CRC_OP_IDLE;    /* CRC back in idle state */
+    return result;
+}
+
+#else   /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */
+
+/**
+ * @brief       Send a Memory DMA request to the CRC, which triggers a DMA driven
+ *              CRC operation.
+ *
+ * @param [in]  pDevice         Pointer to CRC device
+ * @param [in]  pCrcBuf         Address of data buffer.
+ * @param [in]  NumBytes        Number of whole bytes in data buffer.
+ * @param [in]  NumBits         Number of bits, 0 to 7, in the last partial byte
+ *                              in CRC data buffer
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Successfully set expected CRC result.
+ *              - #ADI_CRC_INVALID_DMA_CHANNEL: DMA channel cannot be used with CRC
+ */
+static ADI_CRC_RESULT crc_ExecuteDmaDrivenOperation(
+    ADI_CRC_DEVICE      *pDevice,
+    void                *pCrcBuf,
+    uint32_t            NumBytes,
+    uint32_t            NumBits)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    uint8_t *pData = (uint8_t *)pCrcBuf;
+    bool bUseDma = false;                               /* assume core driven CRC by default */
+
+#ifdef ADI_DEBUG
+    if (!ADI_CRC_VALID_DMA_CHANNEL(ADI_CFG_CRC_DMA_CHANNEL))
+    {
+        /* Report error as Memory DMA not open */
+        result = ADI_CRC_INVALID_DMA_CHANNEL;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        /* If LSBFIRST, it's easy. */
+        if ((pDevice->pReg->CTL & BITM_CRC_CTL_LSBFIRST) != 0u)
+        {
+            /* If the buffer is not 4-byte aligned */
+            if (((uint32_t)pData & 0x3u) != 0u)
+            {
+                /* process the first bytes until a 4-byte aligned data location is reached */
+                pDevice->pReg->CTL |= (BITM_CRC_CTL_EN);        /* enable CRC */
+                while ((NumBytes > 0u) && (((uint32_t)pData & 0x3u) != 0u))
+                {
+                    pDevice->pReg->IPBYTE = *pData;             /* feed byte into CRC */
+                    pData++;                                    /* get to the next byte */
+                    NumBytes--;                                 /* decrease the number of bytes still to be processed */
+                }
+                pDevice->pReg->CTL &= ~(BITM_CRC_CTL_EN);       /* disable CRC */
+            }
+
+            /* 4-byte aligned data transfer */
+            if (NumBytes >= 4u)
+            {
+                /* there are enough data for kicking off a DMA driven CRC operation */
+                const uint32_t channelId = (uint32_t) ADI_CFG_CRC_DMA_CHANNEL;
+                const uint32_t channelBit = 1ul << channelId;           /* get a value with the bit set at position identified by channelId */
+                const uint32_t numData = NumBytes / 4u;                 /* number of 4-byte data to be transferred */
+                const uint32_t src = (uint32_t) pData;                  /* DMA source address */
+                const uint32_t dst = (uint32_t) &pDevice->pReg->IPDATA; /* destination is CRC IPDATA 32-bit register */
+                const uint32_t numTransData = ( (numData > DMA_TRANSFER_LIMIT)
+                                              ? DMA_TRANSFER_LIMIT
+                                              : numData
+                                               );
+                const uint32_t numTransBytes = (numTransData << 2u);
+                const uint32_t lastDataPos = (numTransBytes - 4u);      /* position of last 32-bit data to be transferred in current DMA request */
+
+                pDevice->pReg->CTL |= ((uint32_t) BITM_CRC_CTL_EN);     /* enable CRC (leave other bits unmodified) */
+
+                pADI_DMA0->EN_SET = channelBit;                         /* Enable the channel */
+                pADI_DMA0->ALT_CLR = channelBit;                        /* Set the primary as the current DMA descriptor */
+                pADI_DMA0->SRCADDR_CLR = channelBit;                    /* Ensure decrement for source is cleared */
+                pADI_DMA0->DSTADDR_CLR = channelBit;                    /* Ensure decrement for destination is cleared */
+
+                pPrimaryCCD[channelId].DMADSTEND = dst;                 /* destination is CRC IPDATA 32-bit register */
+                pPrimaryCCD[channelId].DMASRCEND = src + lastDataPos;   /* source end address */
+
+                pPrimaryCCD[channelId].DMACDC =
+                    ( (((uint32_t) ADI_DMA_INCR_NONE)    << ((uint32_t) DMA_BITP_CTL_DST_INC))  /* destination address not incremented */
+                    | (((uint32_t) ADI_DMA_INCR_4_BYTE)  << ((uint32_t) DMA_BITP_CTL_SRC_INC))  /* source address incremented by 4 bytes */
+                    | (((uint32_t) ADI_DMA_WIDTH_4_BYTE) << ((uint32_t) DMA_BITP_CTL_SRC_SIZE)) /* source data size is 4-byte */
+                    | ((numTransData - 1u)               << ((uint32_t) DMA_BITP_CTL_N_MINUS_1))/* number of DMA transfers (minus 1) */
+                    | (DMA_ENUM_CTL_CYCLE_CTL_AUTO_REQ << DMA_BITP_CTL_CYCLE_CTL)               /* DMA Auto Request transmission */
+                    );
+                pDevice->pRemainingData = (void*)(src + numTransBytes); /* remaining data start address */
+                pDevice->RemainingBytes = NumBytes - numTransBytes;     /* remaining bytes that cannot be processed in this DMA batch */
+                pDevice->RemainingBits = NumBits;                       /* remaining bits if last byte is a partial byte */
+                bUseDma = true;                                         /* there are enough data to run 4-byte DMA transfers to CRC */
+            }
+        }
+        /*
+        * If ! LSBFIRST, we need the DMA controller support byte swap for fixed destination address.
+        * But we don't have such luck, although it supports byte swap for fixed source address.
+        * So we have to set DMA size to one byte, which is slower.
+        *
+        * Another option is using mirroring feature of CRC unit, which would be more complicated.
+        */
+        else
+        {
+            if (NumBytes > 0u)
+            {
+                /**
+                 * There are enough data for kicking off a DMA driven CRC operation.
+                 * DMA transfers are limited to 1024 bytes : if the buffer is larger
+                 * than 1024 then generate repeated DMA request through the CRC DMA
+                 * interrupt handler, i.e. the interrupt handler used by the software
+                 * DMA channel driving the CRC operations.
+                 */
+                const uint32_t channelId = (uint32_t) ADI_CFG_CRC_DMA_CHANNEL;
+                const uint32_t channelBit = 1ul << channelId;           /* get a value with the bit set at position identified by channelId */
+                const uint32_t src = (uint32_t) pData;                  /* DMA source address */
+                const uint32_t dst = (uint32_t) &pDevice->pReg->IPBYTE; /* destination is CRC IPBYTE 8-bit register */
+                const uint32_t numTransData = ( (NumBytes > DMA_TRANSFER_LIMIT)
+                                              ? DMA_TRANSFER_LIMIT
+                                              : NumBytes
+                                              );
+                const uint32_t lastDataPos = (numTransData - 1u);       /* position of last data to be transferred in buffer */
+
+                pDevice->pReg->CTL |= (BITM_CRC_CTL_EN);                /* enable CRC (leave other bits unmodified) */
+
+                pADI_DMA0->EN_SET = channelBit;                         /* Enable the channel */
+                pADI_DMA0->ALT_CLR = channelBit;                        /* Set the primary as the current DMA descriptor */
+                pADI_DMA0->SRCADDR_CLR = channelBit;                    /* Ensure decrement for source is cleared */
+                pADI_DMA0->DSTADDR_CLR = channelBit;                    /* Ensure decrement for destination is cleared */
+
+                pPrimaryCCD[channelId].DMADSTEND = dst;                 /* destination is CRC IPBYTE 8-bit register */
+                pPrimaryCCD[channelId].DMASRCEND = src + lastDataPos;   /* source end address */
+                pPrimaryCCD[channelId].DMACDC =
+                    ( (((uint32_t) ADI_DMA_INCR_NONE)    << ((uint32_t) DMA_BITP_CTL_DST_INC))  /* destination address not incremented */
+                    | (((uint32_t) ADI_DMA_INCR_1_BYTE)  << ((uint32_t) DMA_BITP_CTL_SRC_INC))  /* source address incremented by 1 byte */
+                    | (((uint32_t) ADI_DMA_WIDTH_1_BYTE) << ((uint32_t) DMA_BITP_CTL_SRC_SIZE)) /* source data size is 1-byte */
+                    | ((numTransData - 1u)               << ((uint32_t) DMA_BITP_CTL_N_MINUS_1))/* number of DMA transfers (minus 1) */
+                    | (DMA_ENUM_CTL_CYCLE_CTL_AUTO_REQ   << DMA_BITP_CTL_CYCLE_CTL)             /* DMA Auto Request transmission */
+                    );
+                pDevice->pRemainingData = (void*) (src + numTransData); /* remaining data start address */
+                pDevice->RemainingBytes = NumBytes - numTransData;      /* remaining bytes */
+                pDevice->RemainingBits = NumBits;                       /* remaining bits if last byte is a partial byte */
+                bUseDma = true;                                         /* there are enough data to run 4-byte DMA transfers to CRC */
+            }
+        }
+
+        /* if we are in a position to use the DMA to transfer data to the CRC */
+        if (bUseDma== true)
+        {
+            const uint32_t channelId = (uint32_t) ADI_CFG_CRC_DMA_CHANNEL;
+            const uint32_t channelBit = 1ul << channelId;       /* get a value with the bit set at position identified by channelId */
+            pADI_DMA0->SWREQ = channelBit;                      /* Issue a software DMA request */
+        }
+        else
+        {
+            pDevice->pReg->CTL |= (BITM_CRC_CTL_EN);
+            crc_CalculateCrcForRemaining(pDevice, pData, NumBytes, NumBits);
+            pDevice->pReg->CTL &= ~(BITM_CRC_CTL_EN);
+            if(pDevice->pfCallback != NULL)
+            {
+                pDevice->pfCallback(pDevice->pCBParam, (uint32_t) ADI_CRC_EVENT_BUFFER_PROCESSED, pData);
+            }
+            pDevice->eCrcOpStatus = ADI_CRC_OP_IDLE;            /* CRC calculation completed */
+        }
+    }
+    return result;
+}
+
+/**
+ * @brief       Completes a DMA driven CRC operation by dealing with remaining
+ *              data, usually when the number of bytes left is smaller than 4.
+ *
+ * @param [in]  pDevice         Pointer to CRC device
+ * @param [in]  pData           Address of data buffer.
+ * @param [in]  NumBytes        Number of whole bytes in data buffer.
+ * @param [in]  NumBits         Number of bits, 0 to 7, in the last partial byte
+ *                              in CRC data buffer
+ */
+static void crc_CalculateCrcForRemaining(ADI_CRC_DEVICE *pDevice, uint8_t *pData, uint32_t NumBytes, uint32_t NumBits)
+{
+    /* process the remaining bytes */
+    while (NumBytes > 0u)
+    {
+        pDevice->pReg->IPBYTE = *pData;
+        pData++;
+        NumBytes--;
+    }
+
+    /* process the remaining bits in the last byte if the number of bits is smaller than 8 */
+    if (NumBits > 0u)
+    {
+        pDevice->pReg->IPBITS[NumBits] = *pData;
+    }
+}
+
+/**
+ * @brief       Callback function used by the DMA when a DMA error occurs
+ *
+ * @details     Callback function used by the DMA when a DMA error must be reported
+ *              to the CRC driver because it affects the DMA channel driving the CRC.
+ */
+static void CRC_Callback_For_DMA_Err_Int_Handler(void *pcbparam, uint32_t nEvent, void *pArg)
+{
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(pcbparam);
+
+    if (NULL != pDevice)
+    {
+        /* DMA error detected */
+        pDevice->eCrcOpStatus = ADI_CRC_OP_IDLE;                /* mark the CRC peripheral as IDLE */
+        pDevice->pReg->CTL &= (uint32_t)(~(BITM_CRC_CTL_EN));   /* disable CRC peripheral */
+    }
+}
+
+/**
+ * @brief       interrupt handler used by the software DMA channel driving the CRC
+ *
+ * @details     interrupt handler used by the software DMA channel driving the CRC
+ *              ADI_DMA_CRC_ISR is a macro with the final interrupt handler name
+ *              being DMA_SIP0_Int_Handler, ..., DMA_SIP7_Int_Handler, depending
+ *              on the software DMA channel driving the CRC.
+ */
+void ADI_DMA_CRC_ISR(void)
+{
+    ISR_PROLOG();
+
+    if (ADI_CRC_DEVICE_IN_USE(0))
+    {
+        ADI_CRC_DEVICE * pDevice = HDL_TO_DEVICE_PTR(crc_device_info[0].hDevice);
+        if (NULL != pDevice)
+        {
+            uint8_t *pData = (uint8_t *)(pDevice->pRemainingData);
+            uint32_t NumBytes = pDevice->RemainingBytes;
+            uint32_t NumBits = pDevice->RemainingBits;
+            bool finishing = (NumBytes < 4u);
+
+            if (!finishing)
+            {
+                /* there's enough data left for another DMA transfer */
+                ADI_CRC_RESULT result = pDevice->pfSubmitBuffer(pDevice, pData, NumBytes, NumBits);
+                if (ADI_CRC_SUCCESS != result)
+                {
+                    /* buffer submission failed: complete the task through core driven operations */
+                    finishing = true;
+                }
+            }
+
+            if (finishing)
+            {
+                /* There are a very few bytes/bits left to be processed or
+                 * a DMA transfer request could not be sent */
+                crc_CalculateCrcForRemaining(pDevice, pData, NumBytes, NumBits);
+
+                /* if a callback function is registered with the interrupt handler
+                 * associated with the software DMA channel driving the CRC */
+                if(pDevice->pfCallback != NULL)
+                {
+                    pDevice->pfCallback(pDevice->pCBParam, (uint32_t) ADI_CRC_EVENT_BUFFER_PROCESSED, NULL);
+                }
+                pDevice->eCrcOpStatus = ADI_CRC_OP_IDLE;        /* CRC back in idle state */
+
+            }
+        }
+    }
+
+#if defined(ADI_CYCLECOUNT_CRC_ISR_ENABLED) && (ADI_CYCLECOUNT_CRC_ISR_ENABLED == 1u)
+    ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_CRC);    
+#endif
+
+    ISR_EPILOG();
+}
+
+#endif  /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */
+
+/*! \endcond */
+
+/*=============  P U B L I C   F U N C T I O N S =============*/
+
+/**
+ * @brief       Opens a CRC device instance.
+ *
+ * @param [in]  DeviceNum       Number identifying the CRC Device to open.
+ * @param [in]  pMemory         Pointer to a #ADI_CRC_MEMORY_SIZE.
+ *                              sized buffer to manage the device instance.
+ * @param [in]  MemorySize      Size of the buffer to which "pMemory" points.
+ * @param [out] phDevice        Pointer to a location where CRC device handle to be written.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Successfully opened a CRC device.
+ *              - #ADI_CRC_BAD_DEVICE_NUMBER [D]: Supplied CRC Device ID is invalid.
+ *              - #ADI_CRC_IN_USE [D]: Supplied CRC Device ID is already in use.
+ *              - #ADI_CRC_INSUFFICIENT_MEMORY [D]: Supplied memory is not sufficient to handle a CRC device instance.
+ *              - #ADI_CRC_FAILURE [D]: callback registration failed for CRC function used by DMA Error Interrupt Handler.
+ *
+ * @note        For the device memory should be of size #ADI_CRC_MEMORY_SIZE.
+ *
+ */
+ADI_CRC_RESULT adi_crc_Open(
+	uint32_t            DeviceNum,
+	void                *pMemory,
+	uint32_t            MemorySize,
+	ADI_CRC_HANDLE      *phDevice)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = (ADI_CRC_DEVICE*) pMemory;/* memory block to be used to manage a CRC driver instance */
+
+#ifdef ADI_DEBUG                                        /* IF (Debug information enabled) */
+    if (!ADI_CRC_VALID_DEVICE_ID(DeviceNum))            /* IF (This is not a valid CRC device number) */
+    {
+        result = ADI_CRC_BAD_DEVICE_NUMBER;             /* Report failure as bad device number */
+    }
+    else if (ADI_CRC_DEVICE_IN_USE(DeviceNum))          /* IF (The device is in use) */
+    {
+        result = ADI_CRC_IN_USE;                        /* return CRC Device in use error */
+    }
+    else if (  (MemorySize < ADI_CRC_MEMORY_SIZE)       /* IF (Supplied memory size is insufficient) */
+            || (ADI_CRC_MEMORY_SIZE < sizeof(ADI_CRC_DEVICE))
+            )
+    {
+        result = ADI_CRC_INSUFFICIENT_MEMORY;           /* Report failure as insufficient memory */
+    }
+    else
+#endif  /* ADI_DEBUG */
+    {
+        /* check that ADI_CRC_MEMORY_SIZE is accurately defined */
+        assert(ADI_CRC_MEMORY_SIZE == sizeof(ADI_CRC_DEVICE));
+
+        memset(pMemory, 0, MemorySize);                 /* Clear the given memory */
+
+        ADI_INT_STATUS_ALLOC();
+        ADI_ENTER_CRITICAL_REGION();                    /* Entering critical region, disable interrupts */
+
+            /* Save the supplied device memory address */
+            crc_device_info[DeviceNum].hDevice = (ADI_CRC_HANDLE)pDevice;
+            pDevice->pReg = crc_device_info[DeviceNum].pReg;
+
+        ADI_EXIT_CRITICAL_REGION();                     /* Re-enable interrupts */
+
+        crc_ResetRegisters(pDevice);                    /* Reset CRC registers */
+        *phDevice = crc_device_info[DeviceNum].hDevice; /* Pass a valid handle to this CRC device */
+
+#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT == 0)
+
+        pDevice->pfSubmitBuffer = &crc_ExecuteCoreDrivenOperation;
+
+#else   /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */
+
+        pDevice->pfSubmitBuffer = &crc_ExecuteDmaDrivenOperation;
+        adi_dma_Init();
+
+        /* Register CRC DMA callback */
+#ifdef ADI_DEBUG                                        /* IF (Debug information enabled) */
+        if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(ADI_CFG_CRC_DMA_CHANNEL,CRC_Callback_For_DMA_Err_Int_Handler,pDevice))
+        {
+            result = ADI_CRC_FAILURE;
+        }
+#else
+        adi_dma_RegisterCallback(ADI_CFG_CRC_DMA_CHANNEL,CRC_Callback_For_DMA_Err_Int_Handler,pDevice);
+#endif
+        NVIC_EnableIRQ(ADI_CRC_IRQ_ID);                 /* Enable the interrupt for the DMA channel used by CRC */
+#endif  /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */
+    }
+    return result;
+}
+
+/**
+ * @brief       Closes CRC device instance opened for use.
+ *
+ * @param [in]  hDevice         Handle to CRC Device instance to close.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Successfully closed CRC device.
+ *              - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid.
+ *              - #ADI_CRC_FAILURE [D]: callback un-registration failed for CRC function used by DMA Error Interrupt Handler.
+ */
+ADI_CRC_RESULT adi_crc_Close(ADI_CRC_HANDLE const hDevice)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_INFO *pCrcInfo = crc_DeviceInfo(hDevice);   /* get CRC info pointer from CRC handle */
+#ifdef ADI_DEBUG
+    if (NULL == pCrcInfo)
+    {
+        result = ADI_CRC_BAD_HANDLE;                    /* invalid CRC handle being used */
+    }
+    else
+#endif
+    {
+#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT != 0)
+        NVIC_DisableIRQ(ADI_CRC_IRQ_ID);                /* Disable the interrupt for the DMA channel used by CRC. */
+        /* Register CRC DMA callback */
+#ifdef ADI_DEBUG                                        /* IF (Debug information enabled) */
+        if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(ADI_CFG_CRC_DMA_CHANNEL,NULL,NULL))
+        {
+            result = ADI_CRC_FAILURE;
+        }
+#else
+        adi_dma_RegisterCallback(ADI_CFG_CRC_DMA_CHANNEL,NULL,NULL);
+#endif
+#endif
+        pCrcInfo->hDevice = NULL;                       /* Mark CRC driver as closed */
+    }
+    return result;
+}
+/*!
+ * @brief       Set the bit mirroring. This function should be called only when device is idle,
+ *              i.e. when no data are being processd by the CRC.
+ *
+ * @param[in]   hDevice     Device handle obtained from adi_crc_Open().
+ * @param[in]   bEnable     Boolean flag to enable/disable bit mirroring.
+ *                          true : To Enable bit mirroring.
+ *                          false :  To Disable bit mirroring.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Call completed successfully.
+ *              - #ADI_CRC_BAD_HANDLE [D] :Invalid device handle parameter.
+ *              - #ADI_CRC_FN_NOT_PERMITTED [D]: CRC is executing a request, its parameters cannot be altered.
+ *
+ * @sa          adi_crc_SetByteMirroring().
+ * @sa          adi_crc_SetWordSwap().
+ */
+ADI_CRC_RESULT adi_crc_SetBitMirroring(ADI_CRC_HANDLE const hDevice, const bool bEnable)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);       /* get CRC device pointer from CRC handle */
+
+#ifdef ADI_DEBUG
+    if (NULL == pDevice)                                        /* IF (CRC device handle is invalid) */
+    {
+        result = ADI_CRC_BAD_HANDLE;
+    }
+    else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice))                  /* IF (CRC in progress) */
+    {
+        result = ADI_CRC_FN_NOT_PERMITTED;                      /* Function not permitted when CRC operation is in progress */
+    }
+    else
+#endif
+    if(bEnable == true)
+    {
+        pDevice->pReg->CTL |= (BITM_CRC_CTL_BITMIRR);                   /* enable bit mirroring */
+    }
+    else
+    {
+        pDevice->pReg->CTL &= (uint32_t)(~(BITM_CRC_CTL_BITMIRR));      /* disable bit mirroring */
+    }
+    return result;
+}
+/*!
+ * @brief       Set the byte mirroring. This function should be called only when device is disabled.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_crc_Open().
+ * @param[in]   bEnable    Boolean flag to enable/disable byte mirroring.
+ *                         true  : To Enable byte mirroring.
+ *                         false : To Disable byte mirroring.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Call completed successfully.
+ *              - #ADI_CRC_BAD_HANDLE [D]: Invalid device handle parameter.
+ *              - #ADI_CRC_FN_NOT_PERMITTED [D]: CRC is executing a request, its parameters cannot be altered.
+ *
+ *
+ * @sa        adi_crc_EnableBitMirroring().
+ * @sa        adi_crc_EnableWordSwap().
+ */
+ADI_CRC_RESULT  adi_crc_SetByteMirroring(ADI_CRC_HANDLE const hDevice, const bool bEnable)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);       /* get CRC device pointer from CRC handle */
+
+#ifdef ADI_DEBUG
+    if (NULL == pDevice)                                        /* IF (CRC device handle is invalid) */
+    {
+        result = ADI_CRC_BAD_HANDLE;
+    }
+    else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice))                  /* IF (CRC in progress) */
+    {
+        result = ADI_CRC_FN_NOT_PERMITTED;                      /* Function not permitted when CRC operation is in progress */
+    }
+    else
+#endif
+    if(bEnable == true)
+    {
+       pDevice->pReg->CTL |= (BITM_CRC_CTL_BYTMIRR);                    /* enable byte mirroring */
+    }
+    else
+    {
+       pDevice->pReg->CTL &= (uint32_t)(~(BITM_CRC_CTL_BYTMIRR));       /* disable byte mirroring */
+    }
+    return result;
+}
+
+/*!
+ * @brief       Enable the LSB first.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_crc_Open().
+ * @param[in]   bEnable    Boolean flag which indicate whether LSB first OR MSB first for CRC calculation.
+ *                         true  : For LSB First CRC calculation
+ *                         false : For MSB First CRC calculation
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Call completed successfully.
+ *              - #ADI_CRC_BAD_HANDLE [D]: Invalid device handle parameter.
+ *              - #ADI_CRC_FN_NOT_PERMITTED [D]: CRC is executing a request, its parameters cannot be altered.
+ *
+ *
+ * @sa          adi_crc_EnableBitmirroring().
+ * @sa          adi_crc_EnableWordSwap().
+ */
+
+ADI_CRC_RESULT  adi_crc_SetLSBFirst(ADI_CRC_HANDLE const hDevice, const bool bEnable)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);       /* get CRC device pointer from CRC handle */
+
+#ifdef ADI_DEBUG
+    if (NULL == pDevice)                                        /* IF (CRC device handle is invalid) */
+    {
+        result =  ADI_CRC_BAD_HANDLE;
+    }
+    else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice))                  /* IF (CRC in progress) */
+    {
+        result = ADI_CRC_FN_NOT_PERMITTED;                      /* function not permitted when CRC operation is in progress */
+    }
+    else
+#endif
+    if(bEnable == true)
+    {
+       pDevice->pReg->CTL |= (BITM_CRC_CTL_LSBFIRST);           /* enable LSB first (MSB first disable) */
+    }
+    else
+    {
+       pDevice->pReg->CTL &= ~(BITM_CRC_CTL_LSBFIRST);          /* disable LSB first (MSB first enable) */
+    }
+    return result;
+}
+/*!
+ * @brief       To enable/disable the word Swap. This function should be called only when device is disabled.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_crc_Open().
+ * @param[in]   bEnable    Boolean flag to enable/disable word swap.
+ *                         true  : To Enable word swap.
+ *                         false : To Disable word swap.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Call completed successfully.
+ *              - #ADI_CRC_BAD_HANDLE [D]: Invalid device handle parameter.
+ *              - #ADI_CRC_FN_NOT_PERMITTED [D]: CRC is executing a request, its parameters cannot be altered.
+ *
+ *
+ * @sa          adi_crc_SetBitMirroring().
+ * @sa          adi_crc_SetByteMirroring().
+ */
+ADI_CRC_RESULT adi_crc_EnableWordSwap(ADI_CRC_HANDLE const hDevice, const bool bEnable)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);
+
+#ifdef ADI_DEBUG
+    if (NULL == pDevice)                                /* IF (CRC device handle is invalid) */
+    {
+        result = ADI_CRC_BAD_HANDLE;
+    }
+    else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice))          /* IF (CRC in progress) */
+    {
+        result = ADI_CRC_FN_NOT_PERMITTED;              /* function not permitted when CRC operation is in progress */
+    }
+    else
+#endif
+    if(bEnable == true)
+    {
+       pDevice->pReg->CTL |= BITM_CRC_CTL_W16SWP;       /* enable word swap */
+    }
+    else
+    {
+       pDevice->pReg->CTL &= ~BITM_CRC_CTL_W16SWP;      /* disable word swap */
+    }
+
+    return result;
+}
+/**
+ * @brief       Sets the initial seed value for the CRC operation that is about to take place.
+ *
+ * @param [in]  hDevice         Handle to CRC device instance to work on.
+ * @param [in]  CrcSeedVal      Initial seed value for the CRC operation that is about to take place.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Successfully set CRC seed value.
+ *              - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid.
+ *              - #ADI_CRC_FN_NOT_PERMITTED [D] : Function not permitted when CRC operation is in progress.
+ *
+ */
+ADI_CRC_RESULT adi_crc_SetCrcSeedVal(
+    ADI_CRC_HANDLE const    hDevice,
+    uint32_t                CrcSeedVal)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);
+
+#ifdef ADI_DEBUG
+    if (NULL == pDevice)                                /* IF (CRC device handle is invalid) */
+    {
+        result = ADI_CRC_BAD_HANDLE;
+    }
+    else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice))          /* IF (CRC in progress) */
+    {
+        result = ADI_CRC_FN_NOT_PERMITTED;              /* function not permitted when CRC operation is in progress */
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        pDevice->pReg->RESULT = CrcSeedVal;             /* Load the CRC seed value */
+    }
+    return result;
+}
+
+/**
+ * @brief       Sets the 32-bit polynomial for CRC operations.
+ *
+ * @param [in]  hDevice         Handle to CRC device instance to work on.
+ * @param [in]  PolynomialVal   32-bit CRC polynomial to use for CRC operation.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Successfully set polynomial value.
+ *              - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid.
+ *              - #ADI_CRC_FN_NOT_PERMITTED [D]: Function not permitted when CRC operation is in progress.
+ *
+ */
+ADI_CRC_RESULT adi_crc_SetPolynomialVal(
+    ADI_CRC_HANDLE const    hDevice,
+    uint32_t                PolynomialVal)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);
+
+#ifdef ADI_DEBUG
+    if (NULL == pDevice)                                /* IF (CRC device handle is invalid) */
+    {
+        result = ADI_CRC_BAD_HANDLE;
+    }
+    else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice))          /* IF (CRC in progress) */
+    {
+        result = ADI_CRC_FN_NOT_PERMITTED;              /* function not permitted when CRC operation is in progress */
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        pDevice->pReg->POLY = PolynomialVal;            /* Load Polynomial value */
+    }
+    return result;
+}
+
+/**
+ * @brief       Submits data buffer for CRC computation
+ *
+ * @details     This API can be used to submit data buffer for CRC computation.
+ *              If NumBits is in [0..7] then the number of bytes to be processed
+ *              is NumBytes plus one partial byte containing NumBits bits.
+ *              If DMA mode of operation is selected, buffer is processed using
+ *              the specified DMA channel.
+ *
+ * @param [in]  hDevice         Handle of CRC device
+ * @param [in]  pCrcBuf         Address of CRC data buffer
+ * @param [in]  NumBytes        Number of whole bytes in CRC data buffer
+ * @param [in]  NumBits         Number of bits, 0 to 7, in the last partial byte
+ *                              in CRC data buffer
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Successfully submitted data buffer.
+ *              - #ADI_CRC_INVALID_PARAMETER [D]: one of the parameter used is invalid.
+ *              - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid.
+ *              - #ADI_CRC_FN_NOT_SUPPORTED [D]: Function not supported by this CRC revision.
+ *              - #ADI_CRC_FN_NOT_PERMITTED [D]: Function not permitted when CRC operation is in progress.
+ *              - #ADI_CRC_INVALID_DMA_CHANNEL: DMA channel cannot be used with CRC (from crc_DmaDrivenOperation)
+ */
+ADI_CRC_RESULT adi_crc_Compute(
+    ADI_CRC_HANDLE const    hDevice,
+    void                    *pCrcBuf,
+    uint32_t                NumBytes,
+    uint32_t                NumBits)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);
+#ifdef ADI_DEBUG
+    if (NumBits >= 8u)
+    {
+        result = ADI_CRC_INVALID_PARAMETER;
+    }
+    else if (NULL == pDevice)
+    {
+        result = ADI_CRC_BAD_HANDLE;
+    }
+    else if (((pDevice->pReg->CTL & BITM_CRC_CTL_REVID) == 0u) && (NumBits != 0u))
+    {
+        result = ADI_CRC_FN_NOT_SUPPORTED;      /* Partial byte needs CRC unit revision 1 or up */
+    }
+    else
+    if (!ADI_CRC_DEVICE_IS_IDLE(pDevice))       /* IF (CRC in progress) */
+    {
+        result = ADI_CRC_FN_NOT_PERMITTED;      /* function not permitted when CRC operation is in progress */
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        pDevice->eCrcOpStatus = ADI_CRC_OP_IN_PROGRESS; /* mark the CRC as in progress */
+        result = pDevice->pfSubmitBuffer(pDevice, pCrcBuf, NumBytes, NumBits);
+
+        /* CRC returns in IDLE mode when it has processed all its data, not after submitting a request */
+    }
+    return result;
+}
+
+/**
+ * @brief       Gets the current CRC peripheral status.
+ *
+ * @param [in]  hDevice         Handle to CRC device instance to work on
+ * @param [in]  pbCrcInProgress Pointer to location to store the current status of CRC peripheral.
+ *                              'true' when CRC peripheral is in currently performing a CRC operation.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Successfully set expected CRC result.
+ *              - #ADI_CRC_BAD_HANDLE [D}: Supplied CRC handle is invalid.
+ *
+ * @note        This function is valid only when device is operating in DMA mode.
+ *
+ */
+ADI_CRC_RESULT adi_crc_IsCrcInProgress(
+    ADI_CRC_HANDLE const    hDevice,
+    bool                    *pbCrcInProgress)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);
+
+#ifdef ADI_DEBUG
+    if (NULL == pDevice)        /* IF (CRC device handle is invalid) */
+    {
+        result = ADI_CRC_BAD_HANDLE;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+
+      if ((pDevice)->eCrcOpStatus == ADI_CRC_OP_IN_PROGRESS) 
+      {
+                *pbCrcInProgress = true;
+
+      } 
+      else 
+      {
+                *pbCrcInProgress = false;
+
+      }
+    }
+    return result;
+}
+
+/**
+ * @brief       Gets the final CRC result computed for a data stream
+ *
+ * @details     This API gets the final CRC result computed for a data stream
+ *              and clears the current and final CRC results register.
+ *              The CRC Current result register holds the current or
+ *              intermediate CRC result. Whenever a CRC operation is initiated,
+ *              the CRC peripheral takes the CRC Current register value as
+ *              initial seed for CRC computation. This API clears both results
+ *              register to start a fresh CRC computation.
+ *              Use the adi_crc_GetCurrentCrcVal() API to get an intermediate
+ *              CRC result without clearing the results register.
+ *
+ * @param [in]  hDevice         Handle to CRC device instance to work on
+ * @param [out] pFinalCrcVal    Pointer to location where the final CRC result of
+ *                              a data stream to be processed will be written.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Successfully read final CRC result.
+ *              - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid.
+ */
+ADI_CRC_RESULT adi_crc_GetFinalCrcVal(
+    ADI_CRC_HANDLE const    hDevice,
+    uint32_t               *pFinalCrcVal)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);
+
+#ifdef ADI_DEBUG
+    if (NULL == pDevice)        /* IF (CRC device handle is invalid) */
+    {
+        result = ADI_CRC_BAD_HANDLE;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        const uint32_t seed_value = (uint32_t) ADI_CFG_CRC_SEED_VALUE;
+        *pFinalCrcVal = pDevice->pReg->RESULT;  /* Get the final CRC result */
+        pDevice->pReg->RESULT = seed_value;
+    }
+    return result;
+}
+
+/**
+ * @brief       Gets the current/intermediate CRC result computed for a data stream.
+ *
+ * @param [in]  hDevice           Handle to CRC device instance to work on
+ * @param [out] pCurrentCrcVal    Pointer to location where the intermediate CRC result of
+ *                                a data stream to be processed will be written.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Successfully read current CRC result.
+ *              - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid.
+ */
+ADI_CRC_RESULT adi_crc_GetCurrentCrcVal(
+    ADI_CRC_HANDLE const    hDevice,
+    uint32_t                *pCurrentCrcVal)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);
+
+#ifdef ADI_DEBUG
+    if (NULL == pDevice)                                /* IF (CRC device handle is invalid) */
+    {
+        result = ADI_CRC_BAD_HANDLE;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        *pCurrentCrcVal = pDevice->pReg->RESULT;        /* Get the current CRC result */
+    }
+
+    return result;
+}
+
+/**
+ * @brief       Registers or unregisters a callback with the CRC device
+ *
+ * @details     It is not required to register a callback for the operation of the
+ *              driver. Data compare or DMA error will be notified via the
+ *              adi_crc_IsCrcInProgress() API. But if an application requires the
+ *              errors/events to be notified immediately it can register a callback
+ *              with the driver which will be called to notify errors/events.
+ *
+ *              When a callback is registered the API adi_crc_IsCrcInProgress()
+ *              will not return error.
+ *
+ * @param  [in]  hDevice        Handle to CRC device instance to work on
+ * @param  [in]  pfCallback     Pointer to application callback function. The callback function
+ *                              has the prototype
+ *                              void callback(void *pCBParam, uint32_t nEvent, void *pArg)
+ *                              To unregister a callback pass the the pointer to the callback
+ *                              function as NULL.
+ * @param  [in]  pCBParam       Callback parameter which will be returned back to the
+ *                              application when the callback function is called.
+ *
+ * @return      Status
+ *              - #ADI_CRC_SUCCESS: Successfully registered callback.
+ *              - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid.
+ */
+ADI_CRC_RESULT adi_crc_RegisterCallback(
+    ADI_CRC_HANDLE const    hDevice,
+    ADI_CALLBACK            pfCallback,
+    void *const             pCBParam)
+{
+    ADI_CRC_RESULT result = ADI_CRC_SUCCESS;
+    ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice);
+
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();                /* Entering critical region, disable interrupts */
+
+#ifdef ADI_DEBUG
+    if (NULL == pDevice)                        /* IF (CRC device handle is invalid) */
+    {
+        result = ADI_CRC_BAD_HANDLE;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        /* Update CRC Callback information */
+        pDevice->pfCallback = pfCallback;
+        pDevice->pCBParam   = pCBParam;
+    }
+
+    ADI_EXIT_CRITICAL_REGION();                 /* Re-enable interrupts */
+
+    return result;
+}
+
+
+/*****/
+
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crc/adi_crc_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crc/adi_crc_def.h
new file mode 100755
index 00000000000..1558146d56f
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crc/adi_crc_def.h
@@ -0,0 +1,92 @@
+/*! *****************************************************************************
+ * @file:    adi_crc_def.h
+ * @brief:   Private header file for for CRC driver.
+ * @details
+ *           This is a private header file for the CRC driver,
+ *           which contains the API declarations, data and
+ *           constant definitions used in driver implementation
+ -----------------------------------------------------------------------------
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_CRC_DEF_H
+#define ADI_CRC_DEF_H
+
+/* CRC Driver includes */
+#include <drivers/crc/adi_crc.h>
+
+/*! \cond PRIVATE */
+
+typedef struct __ADI_CRC_DEVICE ADI_CRC_DEVICE;
+typedef ADI_CRC_RESULT (*CRC_BUFFER_SUBMIT) (ADI_CRC_DEVICE *pDevice, void *pBuffer, uint32_t NumBytes, uint32_t NumBits);
+
+/* Enumeration of CRC operation status */
+typedef enum
+{
+    ADI_CRC_OP_IDLE             = 0u,           /* CRC idle */
+    ADI_CRC_OP_IN_PROGRESS      = 0x01u,        /* CRC operation in progress */
+} ADI_CRC_OP_STATUS;
+
+
+#pragma pack()
+
+/* Structure to handle CRC Peripheral instance */
+struct __ADI_CRC_DEVICE
+{
+    volatile ADI_CRC_TypeDef    *pReg;
+    CRC_BUFFER_SUBMIT           pfSubmitBuffer;         /* Function for submitting CRC data buffer for calculation */
+    ADI_CALLBACK                pfCallback;             /* Client supplied callback function */
+    void                        *pCBParam;              /* Client supplied callback parameter */
+    void                        *pRemainingData;        /* Pointer to the buffer containing remaining bytes */
+    uint32_t                    RemainingBytes;         /* Remaining bytes */
+    uint32_t                    RemainingBits;          /* Remaining bits */
+    ADI_CRC_OP_STATUS           eCrcOpStatus;           /* Current status of the CRC Operation */
+};
+
+/* Structure to hold CRC device specific information */
+typedef struct
+{
+    volatile ADI_CRC_TypeDef    *pReg;        /* CRC peripheral Registers */
+    ADI_CRC_HANDLE              hDevice;      /* CRC device handle */
+} ADI_CRC_INFO;
+
+/*! \endcond */
+
+#endif  /* ADI_CRC_DEF_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto.c
new file mode 100755
index 00000000000..f46d62d45ea
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto.c
@@ -0,0 +1,1577 @@
+/*! *****************************************************************************
+ * @file:    adi_crypto.c
+ * @brief:   CRYPTO device driver source file.
+ * @details: This is the Crypto driver implementation file.
+ -----------------------------------------------------------------------------
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+/*! \addtogroup Crypto_Driver Crypto Driver
+ *  @{
+ *
+ *  @brief <b>Crypto Driver</b>
+ *
+ *  @details
+ *
+ *  The Crypto controller provides hardware acceleration of various AES cryptographic
+ *  cipher modes, including: ECB, CBC, CTR, CMAC, CCM, and SGA-256.  The Crypto block
+ *  works most efficiently in DMA mode due to the large about of data I/O which would
+ *  otherwise incur a lot of PIO-mode interrupt traffic to manually pump data.
+ *
+ *  <b>Crypto Driver Static Configuration</b>
+ *
+ *  A number of Crypto cipher modes are able to be configured statically, such that
+ *  if particular mode(s) are not required, the resulting driver footprint can be reduced
+ *  internally by blocking out chunks of code that are not needed.
+ *
+ * @note - The application must include drivers/crypto/adi_crypto.h to use this driver.
+ * @note - This driver optionally uses the DMA driver if DMA is selected and active.
+ *         In this case, the application must include the DMA driver sources to resolve
+ *         DMA symbols.
+ */
+
+
+/*========  I N C L U D E  ========*/
+
+/*! \cond PRIVATE */
+#include <adi_processor.h>
+#include <assert.h>
+#include <string.h>
+
+/* main crypto include file */
+#include <drivers/crypto/adi_crypto.h>
+
+/* private crypto defines */
+#include "adi_crypto_def.h"
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+/* dma interface */
+#include <drivers/dma/adi_dma.h>
+#endif
+
+
+/*========  D E F I N E S   ========*/
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm123 (rule  8.5): there shall be no definition of objects or functions in a header file
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+* Pm050 (rule 14.2): a null statement shall only occur on a line by itself
+* Pm088 (rule 17.4): pointer arithmetic should not be used.
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+* Pm152 (rule 17.4): array indexing shall only be applied to objects defined as an array type
+*/
+#pragma diag_suppress=Pm123,Pm140,Pm050,Pm088,Pm073,Pm143,Pm152
+#endif /* __ICCARM__ */
+
+/* Utility Macros */
+#define CLR_BITS(REG,BITS)                        ((REG) &= ~(BITS))
+#define SET_BITS(REG,BITS)                        ((REG) |= (BITS))
+#define IS_ANY_BIT_SET(REG,BITS)                  (((REG) & (BITS)) != 0u)
+
+
+/* Number of crypto device for the given processor */
+#define NUM_DEVICES                               (1u)
+
+/* Compiler-specific mapping of assebbly-level byte-swap instruction
+   IAR is "__REV", and we think Keil is "__rev", but lets see how that
+   goes when it is undefined for Keil.
+*/
+#if defined ( __ICCARM__ )
+#define __ADI_BYTE_SWAP(X)                        __REV(X)
+#elif defined (__GNUC__)
+#define __ADI_BYTE_SWAP(X)                        __builtin_bswap32(X)
+#elif defined (__ARMCC_VERSION)
+#define __ADI_BYTE_SWAP(X)                        __rev(X)
+#else
+#error "This toolchain is not supported"
+#endif
+
+
+/*========  L O C A L    F U N C    D E C L  ========*/
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+static void dmaCallback                      (void *pCBParam, uint32_t Event, void *pArg);
+#endif
+
+#ifdef ADI_DEBUG
+/* Validatation routines */
+static ADI_CRYPTO_RESULT ValidateHandle      (ADI_CRYPTO_HANDLE const hDevice);
+static ADI_CRYPTO_RESULT ValidateUserBuffer  (ADI_CRYPTO_TRANSACTION * const pBuffer);
+#endif
+
+/* Generate a uint32_t value from a pointer to a uint8_t buffer */
+static uint32_t u32FromU8p                   (uint8_t * const pData);
+
+/* Initialize the internal device handle object (user memory) */
+static void InitializeDevData                (ADI_CRYPTO_HANDLE const hDevice);
+
+/* Initiate the computation for a buffer */
+static void StartCompute                     (ADI_CRYPTO_HANDLE const hDevice);
+
+/* Stop the device */
+static void StopCompute                      (ADI_CRYPTO_HANDLE const hDevice);
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+static void programDMA                       (ADI_CRYPTO_HANDLE const hDevice);
+#endif
+
+/* PIO mode write input data */
+static void writePioInputData                (ADI_CRYPTO_HANDLE const hDevice, uint32_t const status);
+
+/* PIO mode read output data */
+static void readPioOutputData                (ADI_CRYPTO_HANDLE const hDevice, uint32_t const status);
+
+/* Flush the input and output buffers */
+static void FlushInputOutputRegisters        (ADI_CRYPTO_HANDLE const hDevice);
+
+
+/* pre-defined Crypto interrupt handler prototypes, as linked in IVT */
+void Crypto_Int_Handler(void);
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+void DMA_AES0_IN_Int_Handler (void);
+void DMA_AES0_OUT_Int_Handler (void);
+#endif
+
+
+/*========  D A T A  ========*/
+/* Internal device structure */
+
+static CRYPTO_INFO CryptoDevInfo[] = {
+    {pADI_CRYPT0,          /* physical device controller pointer */
+     NULL,                 /* hDevice */
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+     DMA0_CH13_DONE_IRQn,  /* DMA input interrupt number */
+     DMA0_CH14_DONE_IRQn,  /* DMA output interrupt number */
+     AES0_IN_CHANn,        /* DMA input channel */
+     AES0_OUT_CHANn,       /* DMA output channel */
+     ADI_CRYPTO_SUCCESS,   /* DMA error state */
+#endif
+    }
+};
+
+/*! \endcond */
+
+/*========  C O D E  ========*/
+
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+
+/* Internal Crypto registered DMA Callback for receiving DMA
+   fault notifications from the shared DMA error handler */
+static void dmaCallback(void *pCBParam, uint32_t Event, void *pArg)
+{
+    /* recover device handle */
+    ADI_CRYPTO_HANDLE hDevice = CryptoDevInfo[0].hDevice;
+
+    /* recover failing channel number */
+    uint32_t failingChannel = (uint32_t)pCBParam;
+
+    /* save the DMA error */
+    switch (Event) {
+        case ADI_DMA_EVENT_ERR_BUS:
+            hDevice->dmaErrorCode = ADI_CRYPTO_ERR_DMA_BUS_FAULT;
+            break;
+        case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR:
+            hDevice->dmaErrorCode = ADI_CRYPTO_ERR_DMA_INVALID_DESCR;
+            break;
+        default:
+            hDevice->dmaErrorCode = ADI_CRYPTO_ERR_DMA_UNKNOWN_ERROR;
+            break;
+    }
+
+    /* transfer is toast... post semaphore to unblock any waiters */
+    SEM_POST(hDevice);
+
+    /* call user's callback */
+    if (0u != hDevice->pfCallback) {
+        hDevice->pfCallback (hDevice->pCBParam, (uint32_t)hDevice->dmaErrorCode, (void*)failingChannel);
+    }
+
+    /* game over... */
+    StopCompute(hDevice);
+}
+#endif
+
+
+#ifdef ADI_DEBUG
+/* Validate the given handle */
+static ADI_CRYPTO_RESULT ValidateHandle(ADI_CRYPTO_HANDLE const hDevice)
+{
+    ADI_CRYPTO_RESULT result = ADI_CRYPTO_ERR_BAD_DEV_HANDLE;
+    uint32_t x;
+
+    for (x = 0u; x < NUM_DEVICES; x++) {
+        if (CryptoDevInfo[x].hDevice == hDevice) {
+            result = ADI_CRYPTO_SUCCESS;
+            break;
+        }
+    }
+
+    return result;
+}
+#endif
+
+
+#ifdef ADI_DEBUG
+static ADI_CRYPTO_RESULT ValidateUserBuffer(ADI_CRYPTO_TRANSACTION * const pBuffer)
+{
+
+    /* null pointer and zero count checks */
+    if (
+           (pBuffer->pInputData     == NULL)
+        || (pBuffer->numInputBytes  == 0u)
+        || (pBuffer->pOutputData    == NULL)
+        || (pBuffer->numOutputBytes == 0u)
+        || (
+               (pBuffer->eAesByteSwap != ADI_CRYPTO_AES_LITTLE_ENDIAN)
+            && (pBuffer->eAesByteSwap != ADI_CRYPTO_AES_BIG_ENDIAN))
+            )
+    {
+        return ADI_CRYPTO_ERR_BAD_BUFFER;
+    }
+
+    /* check buffer pointers for 32-bit alignment */
+    if ( (0u != (3u & (uint32_t)pBuffer->pAuthData)) || (0u != (3u & (uint32_t)pBuffer->pInputData)) || (0u != (3u & (uint32_t)pBuffer->pOutputData)) ) {
+        return ADI_CRYPTO_ERR_BAD_BUFFER;
+    }
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+    /* check buffer sizes for max DMA size */
+    if ((MAX_CRYPTO_DMA_BYTES < pBuffer->numAuthBytes) || (MAX_CRYPTO_DMA_BYTES < pBuffer->numInputBytes) || (MAX_CRYPTO_DMA_BYTES < pBuffer->numOutputBytes)) {
+        return ADI_CRYPTO_ERR_BAD_BUFFER;
+    }
+#endif
+
+#if ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1
+    if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_SHA)
+    {
+        /* SHA output digest is 256-bit and hence the output buffer size should be at least 32 bytes */
+        if (pBuffer->numOutputBytes < SHA_OUTPUT_SIZE_IN_BYTES) {
+            return ADI_CRYPTO_ERR_BAD_BUFFER;
+        }
+    }
+    else
+#endif
+    {
+
+#if ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1
+        if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_CMAC) {
+            /* CMAC output is always a 128-bit block */
+            if (pBuffer->numOutputBytes < CRYPTO_INPUT_SIZE_IN_BYTES) {
+                return ADI_CRYPTO_ERR_BAD_BUFFER;
+            }
+        }
+        else
+#endif
+        {
+            if (
+                   (pBuffer->pKey == NULL)
+                || (   (pBuffer->eAesKeyLen  != ADI_CRYPTO_AES_KEY_LEN_128_BIT)
+                    && (pBuffer->eAesKeyLen  != ADI_CRYPTO_AES_KEY_LEN_256_BIT))
+                || (   (pBuffer->eCodingMode != ADI_CRYPTO_ENCODE)
+                    && (pBuffer->eCodingMode != ADI_CRYPTO_DECODE)))
+            {
+                return ADI_CRYPTO_ERR_BAD_CONFIG;
+            }
+
+#if ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1
+            if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_CTR)
+            {
+                if ((pBuffer->CounterInit & (0xFFF00000u)) != 0u) {
+                    return ADI_CRYPTO_ERR_BAD_BUFFER;
+                }
+            }
+#endif
+
+#if ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1
+            if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_CCM)
+            {
+                if ( ((pBuffer->CounterInit & (0xFFFF0000u)) != 0u)
+                    ||  (   (pBuffer->pAuthData != NULL)
+                                && (
+                                       (pBuffer->numAuthBytes == 0u)
+                                    || (pBuffer->numValidBytes == 0u)
+                                    || (pBuffer->numValidBytes > CRYPTO_INPUT_SIZE_IN_BYTES)
+                                    || (pBuffer->numOutputBytes < (pBuffer->numInputBytes + CRYPTO_INPUT_SIZE_IN_BYTES))
+                                    )
+                        )
+                 )
+                {
+                    return ADI_CRYPTO_ERR_BAD_BUFFER;
+                }
+            }
+            else
+#endif
+            {
+                if (pBuffer->numOutputBytes < pBuffer->numInputBytes)
+                {
+                    return ADI_CRYPTO_ERR_BAD_BUFFER;
+                }
+            }
+        }
+    }
+
+/* FIXME: Issue http://labrea.ad.analog.com/browse/MSKEW-299 describes missing support
+   for HMAC mode, so reject HMAC submits until support for this mode is implimented.
+   ***REMOVE THIS BLOCK WHEN HMAC SUPPORT IS ADDED***
+*/
+#if ADI_CRYPTO_ENABLE_HMAC_SUPPORT == 1
+	if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_HMAC)
+	{
+		return ADI_CRYPTO_ERR_BAD_BUFFER;
+	}
+#endif
+
+    return ADI_CRYPTO_SUCCESS;
+}
+#endif
+
+
+/**
+ * @brief    Opens a Crypto device instance.
+ *
+ * @param [in]  nDeviceNum   Device number to open.
+ * @param [in]  pMemory      Pointer to a #ADI_CRYPTO_MEMORY_SIZE sized buffer to manage the device
+ *                           instance.
+ * @param [in]  nMemorySize  Size of the buffer to which "pMemory" points.
+ * @param [out] phDevice     Pointer to a location where the Crypto device handle is to be written.
+ *
+ * @return   Status
+ *           - #ADI_CRYPTO_SUCCESS                      Call completed successfully.
+ *           - #ADI_CRYPTO_ERR_BAD_DEVICE_NUM       [D] Error: The device number is invalid.
+ *           - #ADI_CRYPTO_ERR_INVALID_PARAM        [D] Error: A parameter is invalid.
+ *           - #ADI_CRYPTO_ERR_INSUFFICIENT_MEM     [D] Error: The memory passed to the device is insufficient.
+ *           - #ADI_CRYPTO_ERR_ALREADY_INITIALIZED  [D] Error: The device is already opened.
+ *           - #ADI_CRYPTO_ERR_SEMAPHORE_FAILED         Error: Unable to create semaphore.
+ *           - #ADI_CRYPTO_ERR_DMA_REGISTER             Error: Unable to register DMA error callback function.
+ *
+ * @sa adi_crypto_Close().
+ */
+ADI_CRYPTO_RESULT adi_crypto_Open (uint32_t const nDeviceNum, void * const pMemory, uint32_t const nMemorySize, ADI_CRYPTO_HANDLE * const phDevice)
+{
+    ADI_CRYPTO_HANDLE hDevice = NULL;
+
+#ifdef ADI_DEBUG
+    if (nDeviceNum >= NUM_DEVICES) {
+        return ADI_CRYPTO_ERR_BAD_DEVICE_NUM;
+    }
+
+    if ((pMemory == NULL) || (phDevice == NULL)) {
+        return ADI_CRYPTO_ERR_INVALID_PARAM;
+    }
+
+    if (nMemorySize < ADI_CRYPTO_MEMORY_SIZE) {
+        return ADI_CRYPTO_ERR_INSUFFICIENT_MEM;
+    }
+
+    if (CryptoDevInfo[nDeviceNum].hDevice != NULL) {
+        return ADI_CRYPTO_ERR_ALREADY_INITIALIZED;
+    }
+
+    /* reality checks */
+    assert (ADI_CRYPTO_MEMORY_SIZE == sizeof(ADI_CRYPTO_DEV_DATA_TYPE));
+    assert (sizeof(ADI_CRYPTO_TRANSACTION) == sizeof(CRYPTO_COMPUTE));
+
+#endif /* ADI_DEBUG */
+
+    /* store a bad handle in case of failure */
+    *phDevice = NULL;
+
+    /* point local device handle to the user memory */
+    hDevice = (ADI_CRYPTO_HANDLE)pMemory;
+
+    /* link CRYPTO controller register set */
+    hDevice->pDev = CryptoDevInfo[nDeviceNum].pDev;
+
+    /* link device info */
+    hDevice->pDevInfo = CryptoDevInfo;
+
+    /* cross-link device handle into device info */
+    CryptoDevInfo[nDeviceNum].hDevice = hDevice;
+
+    /* Initialize the driver internals */
+    InitializeDevData(hDevice);
+
+    /* create the semaphore */
+    SEM_CREATE(hDevice, "crypto_sem", ADI_CRYPTO_ERR_SEMAPHORE_FAILED);
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+    /* initialize DMA core */
+    adi_dma_Init();
+
+    /* register DMA error callback for INPUT channel */
+    if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pDevInfo->dmaInputChanNum, dmaCallback, (void*)hDevice)) {
+        /* uninitialize crypto driver and fail */
+        adi_crypto_Close(hDevice);
+        return  ADI_CRYPTO_ERR_DMA_REGISTER;
+    }
+    /* register DMA error callback for OUTPUT channel */
+    if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pDevInfo->dmaOutputChanNum, dmaCallback, (void*)hDevice)) {
+        /* uninitialize crypto driver and fail */
+        adi_crypto_Close(hDevice);
+        return  ADI_CRYPTO_ERR_DMA_REGISTER;
+    }
+#endif
+
+    /* Give the handle back to the application */
+    *phDevice = hDevice;
+
+    /* Return success */
+    return ADI_CRYPTO_SUCCESS;
+}
+
+/**
+ * @brief    Close the given device instance.
+ *
+ * @param [in]  hDevice  Handle to the device instance.
+ *
+ * @return   Status
+ *           - #ADI_CRYPTO_SUCCESS                  Successfully closed the device.
+ *           - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE   [D] Error: Handle Passed is invalid.
+ *           - #ADI_CRYPTO_ERR_SEMAPHORE_FAILED     Error: Unable to delete semaphore.
+ *
+ * @sa adi_crypto_Open().
+ */
+ADI_CRYPTO_RESULT adi_crypto_Close (ADI_CRYPTO_HANDLE const hDevice)
+{
+    uint32_t x;
+    ADI_CRYPTO_RESULT result;
+
+#ifdef ADI_DEBUG
+    if ((result = ValidateHandle(hDevice)) != ADI_CRYPTO_SUCCESS) {
+        return result;
+    }
+#endif /* ADI_DEBUG */
+
+    /* IF (The device is enabled) */
+    if (hDevice->bDeviceEnabled) {
+        result = adi_crypto_Enable(hDevice, false);
+        if (result != ADI_CRYPTO_SUCCESS) {
+            return result;
+        }
+    }
+
+    /* Destroy the semaphore */
+    SEM_DELETE(hDevice, ADI_CRYPTO_ERR_SEMAPHORE_FAILED);
+
+    /* Close the device */
+    for (x=0u; x < NUM_DEVICES; x++) {
+        if (CryptoDevInfo[x].hDevice == hDevice) {
+            CryptoDevInfo[x].hDevice = NULL;
+            break;
+        }
+    }
+
+    return ADI_CRYPTO_SUCCESS;
+}
+
+
+/**
+ * @brief   Register a user callback function.
+ *
+ * @param [in]  hDevice     Handle to the device instance.
+ * @param [in]  pfCallback  Function pointer to user callback function. Passing a NULL pointer will
+ *                          unregister the callback function.
+ * @param [in]  pCBParam    Callback function parameter.
+ *
+ * @details  This function registers a user callback function.  The registered function will be called when
+ *           the given computation is over.  Registering an active user callback function implies use of the
+ *           (non-blocking) CALLBACK mode during which any subsequent calls to the (blocking-mode)
+ *           #adi_crypto_GetBuffer() API will be rejected.
+ *
+ *
+ * @return   Status
+ *           - #ADI_CRYPTO_SUCCESS                  Successfully registerd the callback.
+ *           - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE   [D] Error: Handle Passed is invalid.
+ */
+ ADI_CRYPTO_RESULT adi_crypto_RegisterCallback (ADI_CRYPTO_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void * const pCBParam)
+{
+#ifdef ADI_DEBUG
+    ADI_CRYPTO_RESULT result;
+
+    if ((result = ValidateHandle(hDevice)) != ADI_CRYPTO_SUCCESS) {
+        return result;
+    }
+#endif /* ADI_DEBUG */
+
+    /* store user's callback values (critical section) */
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+		hDevice->pfCallback = pfCallback;
+		hDevice->pCBParam = pCBParam;
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_CRYPTO_SUCCESS;
+}
+
+
+/**
+ * @brief    Submit a Crypto transaction buffer for processing.
+ *
+ * @param [in]  hDevice   Handle to the device instance.
+ * @param [in]  pBuffer   Pointer to the #ADI_CRYPTO_TRANSACTION structure which contains details
+ *                        of the cipher-dependent buffer elements required by the driver.
+ *
+ * @return  Status
+ *           - #ADI_CRYPTO_SUCCESS                  Successfully submitted the buffer.
+ *           - #ADI_CRYPTO_ERR_COMPUTE_ACTIVE       Error: Buffer already submitted.
+ *           - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE   [D] Error: Handle Passed is invalid.
+ *           - #ADI_CRYPTO_ERR_BAD_BUFFER       [D] Error: The buffer passed to the device is invalid or unsupported.
+ *
+ * The buffer submitted is queued for eventual CRYPTO processing.  A single buffer may be submitted
+ * prior to initiating CRYPTO buffer processing.  Buffer processing is initiated with the
+ * #adi_crypto_Enable() call.  As buffer processing is completed, the buffer (and result info)
+ * is retrieved with the #adi_crypto_GetBuffer() API or through the user callback notification.
+ *
+ * @note    The driver takes ownership of the ADI_CRYPTO_TRANSACTION structure passed to the driver.
+ *          The application must insure the structure is not used and its scope is valid untill
+ *          the structure is returned back to the application.
+ *
+ * @warning    The #ADI_CRYPTO_TRANSACTION buffer is a common superset of all possible cipher mode parameters.
+ *          As such, not all parameters pertain to each cipher mode.  It is recommended users clear unused
+ *          parameters prior to configuration for the particular cipher mode.  The example provided
+ *          illustrates this with a call to: "memset(&Buffer, 0, sizeof(ADI_CRYPTO_TRANSACTION));"
+ *          before configuring and then submitting each transaction.
+ *
+ * @sa adi_crypto_Enable().
+ * @sa adi_crypto_GetBuffer().
+ * @sa adi_crypto_IsBufferAvailable().
+ */
+ ADI_CRYPTO_RESULT adi_crypto_SubmitBuffer (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_TRANSACTION * const pBuffer)
+{
+    ADI_CRYPTO_RESULT result = ADI_CRYPTO_SUCCESS;
+
+    /* reject if we already have a user buffer */
+    if (NULL != hDevice->pUserBuffer) {
+        /* computation already active */
+        return ADI_CRYPTO_ERR_COMPUTE_ACTIVE;
+    }
+
+#ifdef ADI_DEBUG
+    if (ADI_CRYPTO_SUCCESS != (result = ValidateHandle(hDevice))) {
+        return result;
+    }
+
+    /* validate user Buffer */
+    if (ADI_CRYPTO_SUCCESS != (result = ValidateUserBuffer(pBuffer))) {
+        return result;
+    }
+#endif
+
+    /* store user buffer pointer to return later */
+    hDevice->pUserBuffer = pBuffer;
+
+    /* initialize internal compute state from user buffer */
+    memcpy(&hDevice->Computation, pBuffer, sizeof(ADI_CRYPTO_TRANSACTION));
+
+    /* don't initiate transaction until we get adi_crypto_Enable() */
+
+	/* reset dma error code */
+	hDevice->dmaErrorCode = ADI_CRYPTO_SUCCESS;
+
+    return result;
+}
+
+
+/**
+ * @brief   Get the submitted transaction buffer back from the driver.
+ *
+ * @param [in]  hDevice    Handle to the device instance.
+ * @param [out] ppBuffer   Pointer to a location to which the address of the buffer structure is written.
+ *
+ * @return   Status
+ *           - #ADI_CRYPTO_SUCCESS                      Successfully got a buffer.
+ *           - #ADI_CRYPTO_ERR_INVALID_PARAM        [D] Error: Pointer to the buffer is NULL.
+ *           - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE       [D] Error: Handle Passed is invalid.
+ *           - #ADI_CRYPTO_ERR_DMA_BUS_FAULT            Error: DMA bus fault was reported.
+ *           - #ADI_CRYPTO_ERR_DMA_INVALID_DESCR        Error: Invalid DMA descriptor was reported.
+ *           - #ADI_CRYPTO_ERR_DMA_UNKNOWN_ERROR        Error: An unexpected DMA error was reported.
+ *           - #ADI_CRYPTO_ERR_SEMAPHORE_FAILED         Error: Semaphore pend request failed.
+ *           - #ADI_CRYPTO_ERR_INVALID_STATE            Error: Invalid call when using callback mode.
+ *
+ *  This is a blocking call and will await transaction completion (if not already).
+ *  This function should not be called if a callback function is registered.
+ *
+ * @sa adi_crypto_SubmitBuffer().
+ * @sa adi_crypto_IsBufferAvailable().
+ */
+ADI_CRYPTO_RESULT adi_crypto_GetBuffer (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_TRANSACTION ** const ppBuffer)
+{
+    ADI_CRYPTO_RESULT result = ADI_CRYPTO_SUCCESS;
+
+#ifdef ADI_DEBUG
+
+    if (ppBuffer == NULL) {
+        return ADI_CRYPTO_ERR_INVALID_PARAM;
+    }
+    if (ADI_CRYPTO_SUCCESS != (result = ValidateHandle(hDevice))) {
+        return result;
+    }
+#endif /* ADI_DEBUG */
+
+	if (NULL != hDevice->pfCallback) {
+		return ADI_CRYPTO_ERR_INVALID_STATE;
+	}
+
+    /* pend on completion (even if already complete) */
+    SEM_PEND(hDevice, ADI_CRYPTO_ERR_SEMAPHORE_FAILED);
+
+    /* give back the user's buffer */
+    *ppBuffer = hDevice->pUserBuffer;
+
+    /* clear internal user buffer pointer */
+    hDevice->pUserBuffer = NULL;
+
+	/* if we had a DMA error, return that instead of success */
+	if (ADI_CRYPTO_SUCCESS != hDevice->dmaErrorCode) {
+		result = hDevice->dmaErrorCode;
+	}
+
+    return result;
+}
+
+
+/**
+ * @brief    Peek function to know whether a submitted transaction is complete.
+ *
+ * @param [in]  hDevice       Handle to the device instance.
+ * @param [in]  pbAvailable   Pointer to a Boolean variable. Set to "true" if there is a completed
+ *                            buffer and a call to adi_crypto_GetBuffer is ensured to be successful.
+ *                            Set to "false" if there is no completed buffer.
+ *
+ * @return   Status
+ *           - #ADI_CRYPTO_SUCCESS                  Successfully peeked for a buffer.
+ *           - #ADI_CRYPTO_ERR_INVALID_PARAM    [D] Error: The pointer passed is NULL.
+ *           - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE   [D] Error: Handle Passed is invalid.
+ *           - #ADI_CRYPTO_ERR_DMA_BUS_FAULT        Error: DMA bus fault was reported.
+ *           - #ADI_CRYPTO_ERR_DMA_INVALID_DESCR    Error: Invalid DMA descriptor was reported.
+ *           - #ADI_CRYPTO_ERR_DMA_UNKNOWN_ERROR    Error: An unexpected DMA error was reported.
+ *
+ * @sa adi_crypto_SubmitBuffer().
+ * @sa adi_crypto_GetBuffer().
+ */
+ADI_CRYPTO_RESULT adi_crypto_IsBufferAvailable (ADI_CRYPTO_HANDLE const hDevice, bool * const pbAvailable)
+{
+    ADI_CRYPTO_RESULT result = ADI_CRYPTO_SUCCESS;
+
+#ifdef ADI_DEBUG
+    if (pbAvailable == NULL)
+    {
+        return ADI_CRYPTO_ERR_INVALID_PARAM;
+    }
+    if (ADI_CRYPTO_SUCCESS != (result = ValidateHandle(hDevice))) {
+        return result;
+    }
+#endif /* ADI_DEBUG */
+
+    /* let the respective PIO/DMA interrupts drive completion... just return that state here */
+    *pbAvailable = hDevice->bCompletion;
+
+	/* if we had a DMA error, return that instead of success */
+	if (ADI_CRYPTO_SUCCESS != hDevice->dmaErrorCode) {
+		result = hDevice->dmaErrorCode;
+	}
+
+    return result;
+}
+
+
+/**
+ * @brief    Enable/Disable the device.  Enabling the device causes the submitted buffer to be processed.
+ *
+ * @param [in]  hDevice   Handle to the device instance.
+ * @param [in]  bEnable   'true' to enable and 'false' to disable the device.
+ *
+ * @return   Status
+ *           - #ADI_CRYPTO_SUCCESS                  Successfully enabled/disabled the device.
+ *           - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE   [D] Error: Handle Passed is invalid.
+ *           - #ADI_CRYPTO_ERR_INVALID_STATE    [D] Error: Calling enable when device is already enabled or
+ *                                                         disable when the device is already disabled.
+ *
+ */
+ADI_CRYPTO_RESULT adi_crypto_Enable (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable)
+{
+    ADI_CRYPTO_RESULT result = ADI_CRYPTO_SUCCESS;
+
+#ifdef ADI_DEBUG
+
+    if (ADI_CRYPTO_SUCCESS != (result = ValidateHandle(hDevice))) {
+        return result;
+    }
+    if (bEnable == hDevice->bDeviceEnabled) {
+        return ADI_CRYPTO_ERR_INVALID_STATE;
+    }
+#endif /* ADI_DEBUG */
+
+    if (true == bEnable) {
+
+        /* device enable */
+
+        /* Enable the IRQs */
+        NVIC_EnableIRQ(CRYPT_EVT_IRQn);
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+        /* Enable the DMA interrupts */
+        NVIC_EnableIRQ(hDevice->pDevInfo->dmaInputIrqNum);
+        NVIC_EnableIRQ(hDevice->pDevInfo->dmaOutputIrqNum);
+#endif
+
+        /* Mark the device as enabled */
+        hDevice->bDeviceEnabled = true;
+
+        /* Start processing buffer */
+        StartCompute(hDevice);
+
+    } else {
+
+        /* device disable */
+
+        /* Disable the IRQs */
+        NVIC_DisableIRQ(CRYPT_EVT_IRQn);
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+        /* Enable the DMA interrupts */
+        NVIC_DisableIRQ(hDevice->pDevInfo->dmaInputIrqNum);
+        NVIC_DisableIRQ(hDevice->pDevInfo->dmaOutputIrqNum);
+#endif
+
+        /* Stop the device */
+        StopCompute(hDevice);
+
+        /* if we had a DMA error, return that instead of success */
+        if (ADI_CRYPTO_SUCCESS != hDevice->dmaErrorCode) {
+			result = hDevice->dmaErrorCode;
+		}
+    }
+
+    /* Return success */
+    return result;
+}
+
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+/**
+ * @brief   Dynamically Enable/Disable DMA mode for the device.
+ *
+ * @param [in]  hDevice   Handle to the device instance.
+ * @param [in]  bEnable   'true' will enable DMA and 'false' disables the DMA.
+ *
+ * @return   Status
+ *           - #ADI_CRYPTO_SUCCESS                  Successfully enabled/disabled the DMA.
+ *           - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE   [D] Error: Handle Passed is invalid.
+ *           - #ADI_CRYPTO_ERR_INVALID_STATE    [D] Error: DMA cannot be enabled or disabled when the device is already enabled.
+ *
+ * Manage use of DMA mode dynamically.  Presupposes DMA support has been enabled statically
+ * in the static configuration files via the ADI_CRYPTO_ENABLE_DMA_SUPPORT macro.
+ *
+ * @note In addition to requiring that DMA support is enabled (see ADI_CRYPTO_ENABLE_DMA_SUPPORT static
+ * configuration macro) for #adi_crypto_EnableDmaMode() to be available, use of DMA mode may
+ * also be statically configured (see ADI_CRYPTO_ENABLE_DMA).  Both these macros may be set statically
+ * to both enable DMA support and to activate the DMA mode in a fully static manner, without need of
+ * calling adi_crypto_EnableDmaMode() at all (in which case, this function may be eliminated by the linker).
+ */
+ADI_CRYPTO_RESULT adi_crypto_EnableDmaMode (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable)
+{
+#ifdef ADI_DEBUG
+    ADI_CRYPTO_RESULT result;
+
+    if ((result = ValidateHandle(hDevice)) != ADI_CRYPTO_SUCCESS) {
+        return result;
+    }
+    if (hDevice->bDeviceEnabled) {
+        return ADI_CRYPTO_ERR_INVALID_STATE;
+    }
+#endif /* ADI_DEBUG */
+
+    if (bEnable)
+    {
+        /* Enable DMA and map data pump handler */
+        hDevice->bDmaEnabled = true;
+
+        /* Enable the DMA interrupts */
+        NVIC_EnableIRQ(hDevice->pDevInfo->dmaInputIrqNum);
+        NVIC_EnableIRQ(hDevice->pDevInfo->dmaOutputIrqNum);
+    }
+    else
+    {
+        /* Disable DMA and map data pump handler */
+        hDevice->bDmaEnabled = false;
+
+        /* Disable the DMA interrupts */
+        NVIC_DisableIRQ(hDevice->pDevInfo->dmaInputIrqNum);
+        NVIC_DisableIRQ(hDevice->pDevInfo->dmaOutputIrqNum);
+    }
+
+    /* Return success */
+    return ADI_CRYPTO_SUCCESS;
+}
+#endif
+
+
+
+/*! \cond PRIVATE */
+
+/*========  L O C A L    F U N C T I O N    D E F I N I T I O N S  ========*/
+
+/* Generate a u32 from a pointer to u8 buffer */
+static uint32_t u32FromU8p(uint8_t * const pData)
+{
+    int32_t x = 0;
+    uint32_t nValue = pData[3];
+
+    for (x = 2; x >= 0; x--) {
+        nValue = (nValue << 8u) | pData[x];
+    }
+    return nValue;
+}
+
+
+/* Initialize the device structure */
+static void InitializeDevData (ADI_CRYPTO_HANDLE const hDevice)
+{
+    /* Clear the device structure */
+    memset(hDevice, 0, sizeof(ADI_CRYPTO_HANDLE));
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+    #if (ADI_CRYPTO_ENABLE_DMA == 1)
+        hDevice->bDmaEnabled = true;
+        NVIC_EnableIRQ(hDevice->pDevInfo->dmaInputIrqNum);
+        NVIC_EnableIRQ(hDevice->pDevInfo->dmaOutputIrqNum);
+    #else
+        hDevice->bDmaEnabled = false;
+        NVIC_DisableIRQ(hDevice->pDevInfo->dmaInputIrqNum);
+        NVIC_DisableIRQ(hDevice->pDevInfo->dmaOutputIrqNum);
+    #endif
+#else
+    /* no DMA support */
+    hDevice->bDmaEnabled = false;
+#endif
+}
+
+
+/* initiate buffer processing (called from crypto enable) */
+static void StartCompute(ADI_CRYPTO_HANDLE const hDevice)
+{
+    /* clear completion flag */
+    hDevice->bCompletion = false;
+
+    /* Get pointer to the compute buffer */
+    CRYPTO_COMPUTE* pCompute = &hDevice->Computation;
+
+    /* Clear any pending interrupts (all are R/W1C) */
+    hDevice->pDev->STAT = hDevice->pDev->STAT;
+
+    /* reset crypto config register */
+    hDevice->pDev->CFG = 0u;
+
+#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1)
+    /* reset SHA hardware machine state */
+    if (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) {
+        SET_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_SHAINIT);
+    }
+#endif
+
+    /* program main config register settings */
+    SET_BITS(hDevice->pDev->CFG,
+            ( (uint32_t)pCompute->eCipherMode   /* cipher mode    */
+            | (uint32_t)pCompute->eKeyByteSwap  /* KEY endianness */
+            | (uint32_t)pCompute->eShaByteSwap  /* SHA endianness */
+            | (uint32_t)pCompute->eAesByteSwap  /* AES endianness */
+            | (uint32_t)pCompute->eAesKeyLen    /* AES key length */
+            | (uint32_t)pCompute->eCodingMode   /* encode mode    */
+            )
+        );
+
+#if (CRYPTO_SUPPORT_KEY_REQUIRED)
+    if (NULL != pCompute->pKey) {
+
+        /* program user key */
+        uint32_t volatile *pKeyReg = &hDevice->pDev->AESKEY0;
+        uint8_t *pUserKey = pCompute->pKey;
+        uint32_t numKeyWords;
+
+        /* set key length register */
+        SET_BITS(hDevice->pDev->CFG, (uint32_t)pCompute->eAesKeyLen);
+
+        /* Set the number of keywords to write to the 32-bit keyword registers */
+        switch (pCompute->eAesKeyLen) {
+            case ADI_CRYPTO_AES_KEY_LEN_128_BIT:
+                numKeyWords = 4u;
+                break;
+            case ADI_CRYPTO_AES_KEY_LEN_256_BIT:
+                numKeyWords = 8u;
+                break;
+            default:
+                numKeyWords = 0u;  /* hardware only supports only 128-bit and 256-bit key length (no 192-bit) */
+                break;
+        }
+
+        /* load the key (key registers have write-no-read attribute) */
+        for (uint32_t count = 0u; count < numKeyWords; count++) {
+            *pKeyReg = u32FromU8p(pUserKey);
+            pKeyReg++;
+            pUserKey += sizeof(uint32_t);
+        }
+    }
+#endif  /* (CRYPTO_SUPPORT_KEY_REQUIRED) */
+
+#if (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1)
+    if (ADI_CRYPTO_MODE_CMAC == pCompute->eCipherMode) {
+        /* program CMAC-specific registers */
+        /* DATALEN in CMAC mode is number of 128 bit pages (or 16, 8 byte pages) */
+        hDevice->pDev->DATALEN             = pCompute->numInputBytesRemaining  / CRYPTO_INPUT_SIZE_IN_BYTES;
+    }
+#endif  /* (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) */
+
+#if (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1)
+    if (ADI_CRYPTO_MODE_CCM == pCompute->eCipherMode) {
+        /* program CMM-specific registers */
+        hDevice->pDev->PREFIXLEN           = pCompute->numAuthBytesRemaining / CRYPTO_INPUT_SIZE_IN_BYTES;
+        hDevice->pDev->DATALEN             = pCompute->numInputBytesRemaining  / CRYPTO_INPUT_SIZE_IN_BYTES;
+        hDevice->pDev->CCM_NUM_VALID_BYTES = pCompute->numValidBytes;
+    }
+#endif  /* (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) */
+
+#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1)
+
+    if ( (ADI_CRYPTO_MODE_CBC == pCompute->eCipherMode) || (ADI_CRYPTO_MODE_CCM == pCompute->eCipherMode) || (ADI_CRYPTO_MODE_CTR == pCompute->eCipherMode) )
+    {
+        /* program NONCE/IV for CBC, CCM and CTR modes */
+        assert (NULL != pCompute->pNonceIV);
+
+        /* Configure Counter Init and NONCE values */
+        hDevice->pDev->CNTRINIT = pCompute->CounterInit;
+
+        hDevice->pDev->NONCE0 = u32FromU8p(&pCompute->pNonceIV[0]);
+        hDevice->pDev->NONCE1 = u32FromU8p(&pCompute->pNonceIV[4]);
+        hDevice->pDev->NONCE2 = u32FromU8p(&pCompute->pNonceIV[8]);
+
+        hDevice->pDev->NONCE3 = ((uint32_t)pCompute->pNonceIV[12] <<  0u) | ((uint32_t)pCompute->pNonceIV[13] <<  8u);
+
+#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1)
+        if (ADI_CRYPTO_MODE_CBC == pCompute->eCipherMode) {
+
+            /* additionally, CBC mode requires remaining IV data */
+            hDevice->pDev->NONCE3 |= ( ((uint32_t)pCompute->pNonceIV[14] << 16u) | ((uint32_t)pCompute->pNonceIV[15] << 24u) );
+        }
+#endif    /* (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) */
+    }
+#endif    /* (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) */
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+
+    /* onle enable DMA for non-SHA mode or SHA mode with > 4 bytes of input... */
+    if ( ((true == hDevice->bDmaEnabled) && (ADI_CRYPTO_MODE_SHA != pCompute->eCipherMode))
+        || ((true == hDevice->bDmaEnabled) && (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) && (4u < pCompute->numInputBytesRemaining)) )
+    {
+
+        /* DMA startup... */
+        programDMA(hDevice);
+
+        /* mode-specific DMA interrupt enables */
+        switch (pCompute->eCipherMode) {
+            case ADI_CRYPTO_MODE_HMAC:
+                /* enable HMAC done and overrun interrupts (via PIO handler) */
+                SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_HMACDONEEN | BITM_CRYPT_INTEN_INOVREN));
+                break;
+            case ADI_CRYPTO_MODE_SHA:
+                /* enable SHA done and overrun interrupts */
+                SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_SHADONEN | BITM_CRYPT_INTEN_INOVREN));
+                SET_BITS(hDevice->pDev->CFG, (BITM_CRYPT_CFG_INDMAEN));
+                break;
+            default:
+                /* enable DMA I/O interrupts */
+                SET_BITS(hDevice->pDev->CFG, (BITM_CRYPT_CFG_OUTDMAEN | BITM_CRYPT_CFG_INDMAEN));
+                break;
+        }
+
+        /* crypto hardware enable */
+        SET_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_BLKEN);
+
+    } else
+#endif
+    {
+        /* mode-specific PIO interrupt enables */
+        switch (pCompute->eCipherMode) {
+            case ADI_CRYPTO_MODE_HMAC:
+                /* HMAC done interrupts via PIO handler (do NOT use INRDY in HMAC mode) */
+                SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_HMACDONEEN | BITM_CRYPT_INTEN_OUTRDYEN | BITM_CRYPT_INTEN_INOVREN));
+                break;
+            case ADI_CRYPTO_MODE_SHA:
+                /* SHA done interrupts via PIO handler (do NOT use INRDY in SHA mode) */
+                SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_SHADONEN | BITM_CRYPT_INTEN_INOVREN));
+                break;
+            default:
+                SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_INOVREN | BITM_CRYPT_INTEN_OUTRDYEN | BITM_CRYPT_INTEN_INRDYEN));
+                break;
+        }
+
+        /* crypto hardware enable */
+        SET_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_BLKEN);
+
+        /* manual write of 1st input data batch... (interrupt-driven hereafter...) */
+        writePioInputData(hDevice, hDevice->pDev->STAT);
+    }
+}
+
+
+/* halt computation */
+static void StopCompute (ADI_CRYPTO_HANDLE const hDevice)
+{
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+    /* disable Crypto DMA */
+    CLR_BITS(hDevice->pDev->CFG, (BITM_CRYPT_CFG_INDMAEN | BITM_CRYPT_CFG_OUTDMAEN));
+#endif
+
+    /* clear all interrupt enables */
+    hDevice->pDev->INTEN = 0u;
+
+    /* Flush the buffers */
+    FlushInputOutputRegisters(hDevice);
+
+    /* device disable */
+    CLR_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_BLKEN);
+
+    /* Mark the device as disabled */
+    hDevice->bDeviceEnabled = false;
+}
+
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+static void programDMA(ADI_CRYPTO_HANDLE const hDevice)
+{
+    CRYPTO_COMPUTE* pCompute = &hDevice->Computation;
+    ADI_DCC_TypeDef* pCCD;  /* pointer to DMA Control Data Descriptor */
+    uint32_t channelBit;
+    uint32_t num32BitWords;
+
+    /* start with INPUT channel */
+    channelBit = 1u << hDevice->pDevInfo->dmaInputChanNum;
+
+    /* disable various stuff */
+    pADI_DMA0->SRCADDR_CLR = channelBit;  /* disable src endpointer decrement mode */
+    pADI_DMA0->DSTADDR_CLR = channelBit;  /* disable dst endpointer decrement mode */
+    pADI_DMA0->EN_SET      = channelBit;  /* channel enable */
+    pADI_DMA0->RMSK_CLR    = channelBit;  /* allow Crypto to request DMA service */
+
+#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1)
+    /* program input descriptor(s) */
+    if (0u != pCompute->pNextAuthInput) {
+
+        /* schedule authentication data into primary descriptor (USING ping-pong mode) */
+
+        pADI_DMA0->ALT_CLR = channelBit;  /* activate PRIMARY descriptor */
+        pCCD = pPrimaryCCD + hDevice->pDevInfo->dmaInputChanNum;  /* point to primary INPUT descriptor */
+
+        /* setup the endpoints (point to input register & last 4 bytes of input array) */
+        pCCD->DMASRCEND = (uint32_t)pCompute->pNextAuthInput + sizeof(uint32_t) * (pCompute->numAuthBytesRemaining / FIFO_WIDTH_IN_BYTES - 1u);
+        pCCD->DMADSTEND = (uint32_t)&hDevice->pDev->INBUF;
+
+        /* program DMA Control Data Config register */
+        num32BitWords = pCompute->numAuthBytesRemaining / sizeof(uint32_t);
+        pCCD->DMACDC =
+            ( ((uint32_t)ADI_DMA_INCR_NONE                << DMA_BITP_CTL_DST_INC)
+            | ((uint32_t)ADI_DMA_INCR_4_BYTE              << DMA_BITP_CTL_SRC_INC)
+            | ((uint32_t)ADI_DMA_WIDTH_4_BYTE             << DMA_BITP_CTL_SRC_SIZE)
+            | ((uint32_t)ADI_DMA_RPOWER_4                 << DMA_BITP_CTL_R_POWER)
+            | (uint32_t)((num32BitWords - 1u)             << DMA_BITP_CTL_N_MINUS_1)
+            | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_PING_PONG << DMA_BITP_CTL_CYCLE_CTL) );
+
+
+        /* schedule input data into alternate descriptor (in basic mode) */
+        pADI_DMA0->PRI_CLR = channelBit;  /* activate ALTERNATE descriptor */
+        pCCD = pAlternateCCD + hDevice->pDevInfo->dmaInputChanNum;  /* point to alternate INPUT descriptor */
+
+        /* setup the endpoints (point to input register & last 4 bytes of input array) */
+        pCCD->DMASRCEND = (uint32_t)pCompute->pNextInput + sizeof(uint32_t) * (pCompute->numInputBytesRemaining / FIFO_WIDTH_IN_BYTES - 1u);
+        pCCD->DMADSTEND = (uint32_t)&hDevice->pDev->INBUF;
+
+        /* program DMA Control Data Config register */
+        num32BitWords = pCompute->numInputBytesRemaining / sizeof(uint32_t);
+        pCCD->DMACDC =
+            ( ((uint32_t)ADI_DMA_INCR_NONE                << DMA_BITP_CTL_DST_INC)
+            | ((uint32_t)ADI_DMA_INCR_4_BYTE              << DMA_BITP_CTL_SRC_INC)
+            | ((uint32_t)ADI_DMA_WIDTH_4_BYTE             << DMA_BITP_CTL_SRC_SIZE)
+            | ((uint32_t)ADI_DMA_RPOWER_4                 << DMA_BITP_CTL_R_POWER)
+            | (uint32_t)((num32BitWords - 1u)             << DMA_BITP_CTL_N_MINUS_1)
+            | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC     << DMA_BITP_CTL_CYCLE_CTL) );
+
+    } else
+#endif  /* #if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) */
+    {
+
+        /* no authentication data, just schedule input data into primary descriptor (in basic mode) */
+
+        pADI_DMA0->ALT_CLR = channelBit;  /* activate PRIMARY descriptor */
+        pCCD = pPrimaryCCD + hDevice->pDevInfo->dmaInputChanNum;  /* point to primary INPUT descriptor */
+
+        /* setup the endpoints (point to input register & last 4 bytes of input array) */
+#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1)
+        if (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) {
+            
+            /* Stop SHA-mode input writes one short of last 32-bit word so the DMA input interrupt
+               can manually call PIO write function to handle SHA end flag and last write manually. */
+            pCCD->DMASRCEND = (uint32_t)pCompute->pNextInput + sizeof(uint32_t) * (pCompute->numInputBytesRemaining  / FIFO_WIDTH_IN_BYTES - 2u);
+            num32BitWords = (pCompute->numInputBytesRemaining - (pCompute->numInputBytesRemaining % sizeof(uint32_t))) / sizeof(uint32_t) - 1u;  /* count - 1 */
+        }
+        else
+#endif
+        {
+            /* stop at last write end */
+            pCCD->DMASRCEND = (uint32_t)pCompute->pNextInput + sizeof(uint32_t) * ( pCompute->numInputBytesRemaining / FIFO_WIDTH_IN_BYTES - 1u);
+            num32BitWords = pCompute->numInputBytesRemaining / sizeof(uint32_t); /* count */
+        }
+
+        pCCD->DMADSTEND = (uint32_t)&hDevice->pDev->INBUF;
+
+        /* program DMA Control Data Config register */
+        pCCD->DMACDC =
+            ( ((uint32_t)ADI_DMA_INCR_NONE                << DMA_BITP_CTL_DST_INC)
+            | ((uint32_t)ADI_DMA_INCR_4_BYTE              << DMA_BITP_CTL_SRC_INC)
+            | ((uint32_t)ADI_DMA_WIDTH_4_BYTE             << DMA_BITP_CTL_SRC_SIZE)
+            | ((uint32_t)ADI_DMA_RPOWER_4                 << DMA_BITP_CTL_R_POWER)
+            | (uint32_t)((num32BitWords - 1u)             << DMA_BITP_CTL_N_MINUS_1)
+            | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC     << DMA_BITP_CTL_CYCLE_CTL) );
+    }
+
+/* don't program output DMA in SHA mode... */
+#if CRYPTO_SUPPORT_MODE_ANY_NON_SHA
+
+    if (ADI_CRYPTO_MODE_SHA != pCompute->eCipherMode) {
+
+        /* switch to OUTPUT channel */
+        channelBit = 1u << hDevice->pDevInfo->dmaOutputChanNum;
+
+        /* disable various stuff */
+        pADI_DMA0->SRCADDR_CLR = channelBit;  /* disable src endpointer decrement mode */
+        pADI_DMA0->DSTADDR_CLR = channelBit;  /* disable dst endpointer decrement mode */
+        pADI_DMA0->EN_SET      = channelBit;  /* channel enable */
+        pADI_DMA0->RMSK_CLR    = channelBit;  /* allow Crypto to request DMA service */
+
+        pADI_DMA0->ALT_CLR = channelBit;  /* activate primary descriptor */
+        pCCD = pPrimaryCCD + hDevice->pDevInfo->dmaOutputChanNum;  /* point to crypto OUTPUT descriptor */
+
+
+        /* setup the endpoints (point to output register & last 4 bytes of output array) */
+        pCCD->DMASRCEND = (uint32_t)&hDevice->pDev->OUTBUF;
+        pCCD->DMADSTEND = (uint32_t)pCompute->pNextOutput + sizeof(uint32_t) * (pCompute->numOutputBytesRemaining / FIFO_WIDTH_IN_BYTES - 1u);
+
+        /* program DMA Control Data Config register */
+        num32BitWords = pCompute->numOutputBytesRemaining / sizeof(uint32_t);
+        pCCD->DMACDC =
+            ( ((uint32_t)ADI_DMA_INCR_4_BYTE           << DMA_BITP_CTL_DST_INC)
+            | ((uint32_t)ADI_DMA_INCR_NONE             << DMA_BITP_CTL_SRC_INC)
+            | ((uint32_t)ADI_DMA_WIDTH_4_BYTE          << DMA_BITP_CTL_SRC_SIZE)
+            | ((uint32_t)ADI_DMA_RPOWER_4              << DMA_BITP_CTL_R_POWER)
+            | (uint32_t)((num32BitWords - 1u)          << DMA_BITP_CTL_N_MINUS_1)
+            | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC  << DMA_BITP_CTL_CYCLE_CTL) );
+
+    }  /* end non-SHA mode */
+
+#endif  /* CRYPTO_SUPPORT_MODE_ANY_NON_SHA */
+}
+#endif  /* #if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) */
+
+
+static void writePioInputData(ADI_CRYPTO_HANDLE const hDevice, uint32_t const status)
+{
+    CRYPTO_COMPUTE* pCompute = &hDevice->Computation;
+    uint32_t numWritable = FIFO_DEPTH - ((status & BITM_CRYPT_STAT_INWORDS) >> BITP_CRYPT_STAT_INWORDS);
+
+#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1)
+    /* always send authentication data before input payload is sent */
+    if (0u != pCompute->numAuthBytesRemaining) {
+
+        /* fill input FIFO with 32-bit authentication data */
+        while ((0u != numWritable) && (0u != pCompute->numAuthBytesRemaining)) {
+            hDevice->pDev->INBUF = *pCompute->pNextAuthInput;
+            pCompute->pNextAuthInput++;
+            pCompute->numAuthBytesRemaining -= FIFO_WIDTH_IN_BYTES;
+            numWritable--;
+        }
+    } else
+#endif  /* #if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) */
+    {
+        /* no authentication data, process payload input data */
+
+#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1)
+        if (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) {
+
+            /* Drive up to a full "chunk" of SHA input message data.
+               Chunk size is limited to 512-bits (64-bytes) by AES
+               hardware compute block.
+            */
+
+            if (pCompute->numInputBytesRemaining >= SHA_CHUNK_MAX_BYTES)
+            {
+                /* This is the simple case, load up an entire chunk and let it go */
+                for (uint8_t i = 0u; i < SHA_CHUNK_MAX_WORDS; i++) {
+                    hDevice->pDev->INBUF = *pCompute->pNextInput;
+                    pCompute->pNextInput++;                    
+                }
+
+                pCompute->numShaBitsRemaining    -= SHA_CHUNK_MAX_BITS;
+                pCompute->numInputBytesRemaining -= SHA_CHUNK_MAX_BYTES;       
+            }
+            else
+            {
+                /* The final case, we load up any bytes less than a full chunk and trigger the last word */
+                while (FIFO_WIDTH_IN_BITS <= pCompute->numShaBitsRemaining) {
+                    hDevice->pDev->INBUF = *pCompute->pNextInput;
+                    pCompute->pNextInput++;
+                    pCompute->numShaBitsRemaining -= FIFO_WIDTH_IN_BITS;
+                }
+
+                hDevice->pDev->SHA_LAST_WORD = (pCompute->numShaBitsRemaining << BITP_CRYPT_SHA_LAST_WORD_O_BITS_VALID) | BITM_CRYPT_SHA_LAST_WORD_O_LAST_WORD;
+
+                /* Last write is dummy or not, depending on remaining bit count */
+                if (0u == pCompute->numShaBitsRemaining) {
+                    /* dummy write */
+                    hDevice->pDev->INBUF = 0u;
+                } else {
+                    /* partial data (last remaining message data word) */
+                    hDevice->pDev->INBUF = *pCompute->pNextInput;
+                    pCompute->pNextInput++;
+                }
+
+                pCompute->numShaBitsRemaining     = 0u;
+                pCompute->numInputBytesRemaining  = 0u;
+
+                /* Use output bytes as a way of confirming that we are really done (can't use input bytes/bits) */
+                pCompute->numOutputBytesRemaining -= SHA_OUTPUT_SIZE_IN_BYTES;
+            }
+        }  /* end of SHA mode */
+        else
+#endif
+        {
+            /* full input FIFO with normal payload write (non-SHA) */
+            while ((0u != numWritable) && (0u != pCompute->numInputBytesRemaining)) {
+                hDevice->pDev->INBUF = *pCompute->pNextInput;
+                pCompute->pNextInput++;
+                pCompute->numInputBytesRemaining -= FIFO_WIDTH_IN_BYTES;
+                numWritable--;
+            }
+        }
+    }
+}
+
+
+static void readPioOutputData(ADI_CRYPTO_HANDLE const hDevice, uint32_t const status)
+{
+    CRYPTO_COMPUTE *pCompute = &hDevice->Computation;
+    uint32_t numReadable;
+
+#if  ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1
+    /* Copy the SHA output if enabled */
+    if (pCompute->eCipherMode == ADI_CRYPTO_MODE_SHA)
+    {
+        if (IS_ANY_BIT_SET(status, BITM_CRYPT_STAT_SHADONE)) {
+
+			/* Get 1 SHADONE per block + 1 SHADONE when we trigger the last word */
+			if (0u == pCompute->numOutputBytesRemaining) {
+#if ADI_CRYPTO_SHA_OUTPUT_FORMAT == 0 /* Little Endian */
+				pCompute->pNextOutput[0] = hDevice->pDev->SHAH7;
+				pCompute->pNextOutput[1] = hDevice->pDev->SHAH6;
+				pCompute->pNextOutput[2] = hDevice->pDev->SHAH5;
+				pCompute->pNextOutput[3] = hDevice->pDev->SHAH4;
+				pCompute->pNextOutput[4] = hDevice->pDev->SHAH3;
+				pCompute->pNextOutput[5] = hDevice->pDev->SHAH2;
+				pCompute->pNextOutput[6] = hDevice->pDev->SHAH1;
+				pCompute->pNextOutput[7] = hDevice->pDev->SHAH0;
+#else
+				pCompute->pNextOutput[0] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH0);
+				pCompute->pNextOutput[1] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH1);
+				pCompute->pNextOutput[2] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH2);
+				pCompute->pNextOutput[3] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH3);
+				pCompute->pNextOutput[4] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH4);
+				pCompute->pNextOutput[5] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH5);
+				pCompute->pNextOutput[6] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH6);
+				pCompute->pNextOutput[7] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH7);
+#endif
+			}
+        }
+    }
+    else
+#endif
+    {
+        /* read any ready non-SHA output from output FIFO */
+        if (IS_ANY_BIT_SET(status, BITM_CRYPT_STAT_OUTRDY)) {
+            numReadable = ((status & BITM_CRYPT_STAT_OUTWORDS) >> BITP_CRYPT_STAT_OUTWORDS);
+            while ((0u != numReadable) && (0u != pCompute->numOutputBytesRemaining)) {
+                *pCompute->pNextOutput = hDevice->pDev->OUTBUF;
+                pCompute->pNextOutput++;
+                pCompute->numOutputBytesRemaining -= FIFO_WIDTH_IN_BYTES;
+                numReadable--;
+            }
+        }
+    }
+
+    /* if output count has gone to zero, set completion flag */
+    if (0u == pCompute->numOutputBytesRemaining) {
+        hDevice->bCompletion = true;
+    }
+}
+
+
+/* Flush the Crypto input and output buffers */
+static void FlushInputOutputRegisters(ADI_CRYPTO_HANDLE const hDevice)
+{
+    /* Set and clear the flush bits to flush the input and output buffers */
+    SET_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_INFLUSH | BITM_CRYPT_CFG_OUTFLUSH);
+    CLR_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_INFLUSH | BITM_CRYPT_CFG_OUTFLUSH);
+}
+
+
+/*================ INTERRUPT HANDELING ==================*/
+
+/* native PIO-mode (non-DMA) interrupt handler */
+void Crypto_Int_Handler(void)
+{
+    ISR_PROLOG();
+
+    ADI_CRYPTO_HANDLE hDevice = CryptoDevInfo[0].hDevice;
+    CRYPTO_COMPUTE *pCompute  = &hDevice->Computation;
+    uint32_t status = hDevice->pDev->STAT;
+    uint32_t event;
+
+    /* clear status */
+    hDevice->pDev->STAT = status;
+
+    /* check for overflow */
+    if (IS_ANY_BIT_SET(status, BITM_CRYPT_STAT_INOVR)) {
+
+        /* call user's callback */
+        if (0u != hDevice->pfCallback) {
+            hDevice->pfCallback(hDevice->pCBParam, ADI_CRYPTO_EVENT_STATUS_INPUT_OVERFLOW, (void *)status);
+        }
+
+        /* stop */
+        StopCompute(hDevice);
+
+        /* post the semaphore */
+        SEM_POST(hDevice);
+
+        return;
+    }
+
+    /* pull outputs (updates completion flag) */
+    readPioOutputData(hDevice, status);
+
+    if (false == hDevice->bCompletion) {
+
+        /* push more inputs, but not in SHA DMA mode (except for when its perfectly aligned block) */
+        if ((pCompute->eCipherMode != ADI_CRYPTO_MODE_SHA) || (hDevice->bDmaEnabled == false) || (pCompute->numInputBytesRemaining == 0u))
+        {
+            writePioInputData(hDevice, status);
+        }
+
+    } else {
+
+        /* we're done */
+
+        /* dispatch to user callback if we have one */
+        if (0u != hDevice->pfCallback) {
+
+            /* check for overflow first */
+            if (0u != (BITM_CRYPT_STAT_INOVR & status)) {
+                event = ADI_CRYPTO_EVENT_STATUS_INPUT_OVERFLOW;
+            } else {
+                /* completion message depends on mode */
+                switch (hDevice->Computation.eCipherMode) {
+#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1)
+                    case ADI_CRYPTO_MODE_CBC:  event = ADI_CRYPTO_EVENT_STATUS_CBC_DONE;  break;
+#endif
+#if (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1)
+                    case ADI_CRYPTO_MODE_CCM:  event = ADI_CRYPTO_EVENT_STATUS_CCM_DONE;  break;
+#endif
+#if (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1)
+                    case ADI_CRYPTO_MODE_CMAC: event = ADI_CRYPTO_EVENT_STATUS_CMAC_DONE; break;
+#endif
+#if (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1)
+                    case ADI_CRYPTO_MODE_CTR:  event = ADI_CRYPTO_EVENT_STATUS_CTR_DONE;  break;
+#endif
+#if (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1)
+					case ADI_CRYPTO_MODE_ECB:  event = ADI_CRYPTO_EVENT_STATUS_ECB_DONE;  break;
+#endif
+#if (ADI_CRYPTO_ENABLE_HMAC_SUPPORT == 1)
+                    case ADI_CRYPTO_MODE_HMAC: event = ADI_CRYPTO_EVENT_STATUS_HMAC_DONE; break;
+#endif
+#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1)
+                    case ADI_CRYPTO_MODE_SHA:  event = ADI_CRYPTO_EVENT_STATUS_SHA_DONE;  break;
+#endif
+                    default:                   event = ADI_CRYPTO_EVENT_STATUS_UNKNOWN;   break;
+                }
+            }
+
+            /* call user's callback and give back buffer pointer */
+            hDevice->pfCallback(hDevice->pCBParam, event, (void*)hDevice->pUserBuffer);
+
+            /* clear private copy of user buffer pointer */
+            /* (this is done in GetBuffer in non-Callback mode) */
+            hDevice->pUserBuffer = NULL;
+        }
+
+        /* disable interrupts */
+        hDevice->pDev->INTEN = 0u;
+
+        /* post the semaphore */
+        SEM_POST(hDevice);
+    }
+
+    ISR_EPILOG();
+}
+
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+/* native DMA input interrupt handler */
+void DMA_AES0_IN_Int_Handler (void)
+{
+    ISR_PROLOG();
+
+    ADI_CRYPTO_HANDLE hDevice = CryptoDevInfo[0].hDevice;
+    CRYPTO_COMPUTE *pCompute  = &hDevice->Computation;
+
+#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1)
+    if (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) {
+        
+        /* Update the compute structure to reflect the "post DMA" state of the transaction */
+        uint32_t numTotalBytes            = pCompute->numInputBytesRemaining;
+        uint32_t num32BitWords            = (numTotalBytes - (numTotalBytes % sizeof(uint32_t))) / sizeof(uint32_t) - 1u;
+        pCompute->numInputBytesRemaining -= num32BitWords*4u;
+        pCompute->numShaBitsRemaining    -= num32BitWords*32u;
+        pCompute->pNextInput             += num32BitWords;
+
+        if ((numTotalBytes % SHA_CHUNK_MAX_BYTES) == 0u)
+        {
+            /* For perfect block sizes, need to write the last word WITHOUT triggering SHA_LAST_WORD */
+            hDevice->pDev->INBUF = *pCompute->pNextInput;
+
+            pCompute->numInputBytesRemaining = 0u;
+            pCompute->numShaBitsRemaining    = 0u;
+        }
+        else
+        {
+            /* Go ahead and write the remaining word, and its okay to trigger SHA_LAST_WORD */
+            writePioInputData(hDevice, hDevice->pDev->STAT);
+        }
+    }
+#endif
+
+    /* defer post to output interrupt... */
+
+    ISR_EPILOG();
+}
+#endif
+
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+/* native DMA output interrupt handler */
+void DMA_AES0_OUT_Int_Handler (void)
+{
+    ISR_PROLOG();
+    ADI_CRYPTO_HANDLE hDevice = CryptoDevInfo[0].hDevice;
+    uint32_t status = hDevice->pDev->STAT;
+    uint32_t event;
+
+    /* by the time we get here, everything should be complete */
+
+    /* dispatch to user callback if we have one */
+    if (0u != hDevice->pfCallback) {
+
+        /* check for overflow first */
+        if (0u != (BITM_CRYPT_STAT_INOVR & status)) {
+            event = ADI_CRYPTO_EVENT_STATUS_INPUT_OVERFLOW;
+        } else {
+            /* completion message depends on mode */
+            switch (hDevice->Computation.eCipherMode) {
+#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1)
+                case ADI_CRYPTO_MODE_CBC:  event = ADI_CRYPTO_EVENT_STATUS_CBC_DONE;  break;
+#endif
+#if (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1)
+                case ADI_CRYPTO_MODE_CCM:  event = ADI_CRYPTO_EVENT_STATUS_CCM_DONE;  break;
+#endif
+#if (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1)
+                case ADI_CRYPTO_MODE_CMAC: event = ADI_CRYPTO_EVENT_STATUS_CMAC_DONE; break;
+#endif
+#if (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1)
+                case ADI_CRYPTO_MODE_CTR:  event = ADI_CRYPTO_EVENT_STATUS_CTR_DONE;  break;
+#endif
+#if (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1)
+                case ADI_CRYPTO_MODE_ECB:  event = ADI_CRYPTO_EVENT_STATUS_ECB_DONE;  break;
+#endif
+#if (ADI_CRYPTO_ENABLE_HMAC_SUPPORT == 1)
+                case ADI_CRYPTO_MODE_HMAC: event = ADI_CRYPTO_EVENT_STATUS_HMAC_DONE; break;
+#endif
+#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1)
+                case ADI_CRYPTO_MODE_SHA:  event = ADI_CRYPTO_EVENT_STATUS_SHA_DONE;  break;
+#endif
+                default:                   event = ADI_CRYPTO_EVENT_STATUS_UNKNOWN;   break;
+            }
+        }
+
+        /* call user's callback and give back buffer pointer */
+        hDevice->pfCallback(hDevice->pCBParam, event, (void*)hDevice->pUserBuffer);
+
+        /* clear private copy of user buffer pointer */
+          /* this is done in GetBuffer in non-Callback mode */
+        hDevice->pUserBuffer = NULL;
+    }
+
+    /* mark completion */
+    hDevice->bCompletion = true;
+
+    /* clear status */
+    hDevice->pDev->STAT = status;
+
+    /* post the semaphore */
+    SEM_POST(hDevice);
+
+    ISR_EPILOG();
+}
+#endif
+
+/*! \endcond */
+
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto_def.h
new file mode 100755
index 00000000000..b9e82e14b36
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto_def.h
@@ -0,0 +1,209 @@
+/*!
+ *****************************************************************************
+ @file:    adi_crypto_def.h
+ @brief:   Crypto Device Driver definitions for ADuCM4x50 processor
+ -----------------------------------------------------------------------------
+Copyright (c) 2012-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#ifndef ADI_CRYPTO_DEF_H
+#define ADI_CRYPTO_DEF_H
+
+/*! \cond PRIVATE */
+
+#include <drivers/dma/adi_dma.h>
+#include <adi_crypto_config.h>
+
+/* pick up compiler-specific alignment directives */
+#include <drivers/general/adi_drivers_general.h>
+#define ALIGN4 ALIGNED_PRAGMA(4)
+
+/* Support Check MACROS */
+#define CRYPTO_SUPPORT_KEY_REQUIRED  (                                                  \
+                                               (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1)    \
+                                            )
+
+#define CRYPTO_SUPPORT_MODE_CCM_ONLY       (                                             \
+                                               (ADI_CRYPTO_ENABLE_ECB_SUPPORT  != 1)     \
+                                            && (ADI_CRYPTO_ENABLE_CTR_SUPPORT  != 1)     \
+                                            && (ADI_CRYPTO_ENABLE_CBC_SUPPORT  != 1)     \
+                                            && (ADI_CRYPTO_ENABLE_CCM_SUPPORT  == 1)     \
+                                            && (ADI_CRYPTO_ENABLE_CMAC_SUPPORT != 1)     \
+                                            && (ADI_CRYPTO_ENABLE_SHA_SUPPORT  != 1)     \
+                                            )
+
+#define CRYPTO_SUPPORT_MODE_ANY_NON_CCM    (                                             \
+                                               (ADI_CRYPTO_ENABLE_ECB_SUPPORT  == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CTR_SUPPORT  == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CBC_SUPPORT  == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_SHA_SUPPORT  == 1)     \
+                                            )
+
+#define CRYPTO_SUPPORT_MODE_ANY_NON_SHA    (                                             \
+                                               (ADI_CRYPTO_ENABLE_ECB_SUPPORT  == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CTR_SUPPORT  == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CBC_SUPPORT  == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1)     \
+                                            || (ADI_CRYPTO_ENABLE_CCM_SUPPORT  == 1)     \
+                                            )
+
+/* define local MIN/MAX macros, if not already... */
+#ifndef MIN
+#define MIN(a,b) (((a)<(b))?(a):(b))
+#endif
+#ifndef MAX
+#define MAX(a,b) (((a)>(b))?(a):(b))
+#endif
+
+/* various size macros */
+#define MAX_CRYPTO_DMA_BYTES        (DMA_TRANSFER_LIMIT * sizeof(uint32_t))
+
+/* SHA hardware max chunk size attributes */
+#define SHA_CHUNK_MAX_BYTES         (64u)
+#define SHA_CHUNK_MAX_BITS          (SHA_CHUNK_MAX_BYTES * 8U)
+#define SHA_CHUNK_MAX_WORDS         (16u)
+
+#define FIFO_WIDTH_IN_BITS          (32u)
+#define FIFO_WIDTH_IN_BYTES         (FIFO_WIDTH_IN_BITS/8u)
+#define FIFO_DEPTH                  (4u)
+
+#define CRYPTO_INPUT_SIZE_IN_BITS   (128u)
+#define CRYPTO_INPUT_SIZE_IN_BYTES  (CRYPTO_INPUT_SIZE_IN_BITS/8u)
+
+#define SHA_OUTPUT_SIZE_IN_BITS     (256u)
+#define SHA_OUTPUT_SIZE_IN_BYTES    (SHA_OUTPUT_SIZE_IN_BITS/8u)
+
+
+/* MAKE SURE THIS STRUCT REMAINS *******PERFECTLY ALIGNED******* WITH USER
+   ADI_CRYPTO_TRANSACTION BECAUSE WE USE BCOPY TO INITIALIZE EACH NEW SUBMIT!
+
+   Internal compute structure reflecting mostly, user ADI_CRYPTO_TRANSACTION,
+   except for moving data pointers and remaining counts.  Contents initialized
+   directly from from ADI_CRYPTO_TRANSACTION during buffer submit.
+*/
+typedef struct _CRYPTO_COMPUTE {
+	ADI_CRYPTO_CIPHER_MODE    eCipherMode;              /*!< Cipher mode to use */
+    ADI_CRYPTO_CODING_MODE    eCodingMode;              /*!< Coding Mode (Encryption or Decryption) */
+
+    ADI_CRYPTO_KEY_BYTE_SWAP  eKeyByteSwap;             /*!< KEY endianness */
+    ADI_CRYPTO_SHA_BYTE_SWAP  eShaByteSwap;             /*!< SHA endianness */
+    ADI_CRYPTO_AES_BYTE_SWAP  eAesByteSwap;             /*!< AES endianness */
+
+    uint8_t                  *pKey;                     /*!< Pointer to the key data pre-formatted as a byte array, according to eAesKeyLen. */
+    ADI_CRYPTO_AES_KEY_LEN    eAesKeyLen;               /*!< The length of the key */
+
+    uint32_t                 *pNextAuthInput;           /* CCM mode: pointer to user prefix buffer */
+    uint32_t                  numAuthBytesRemaining;    /* Length of the prefix buffer in bytes (should be a multiple of 16 bytes) */
+
+    uint32_t                 *pNextInput;               /* Pointer to next user 32-bit input location */
+    uint32_t                  numInputBytesRemaining;   /* Number of input bytes remaining */
+
+    uint32_t                 *pNextOutput;              /* Pointer to next user 32-bit output location */
+    uint32_t                  numOutputBytesRemaining;  /* Number of output bytes remaining */
+
+    uint8_t                  *pNonceIV;                 /*!< Pointer to user 16-byte array containing one of three values, depending on cipher mode:
+                                                                 CTR mode = 108-bit NONCE
+                                                                 CCM mode = 112-bit NONCE
+                                                                 CBC mode = 128-bit IV (Initialization Vector)
+                                                             NONCE and IV assume little endian format, for example: CTR NONCE packing is:
+                                                                NONCE[0]            ->   7:0
+                                                                NONCE[1]            ->  15:8
+                                                                  ...
+                                                                NONCE[13]           -> 103:96
+                                                                NONCE[14](Bits 3:0) -> 107:104 */
+    uint32_t                  CounterInit;              /*!< CTR/CCM mode: Counter Initialization Value (CTR=20-bit, CCM=16-bit) */
+    uint32_t                  numValidBytes;            /*!< CCM mode: Number of valid bytes in the last (padding) block (1-16) */
+    uint32_t                  numShaBitsRemaining;      /*!< SHA mode: Number of bits remaining in the SHA payload, which may be odd-sized */
+} CRYPTO_COMPUTE;
+
+
+/* Crypto device attributes */
+typedef struct _CRYPTO_INFO {
+    ADI_CRYPT_TypeDef          *pDev;				/* Pointer to physical Crypto controller */
+    ADI_CRYPTO_HANDLE           hDevice;			/* Device Handle */
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+    IRQn_Type                   dmaInputIrqNum;
+    IRQn_Type                   dmaOutputIrqNum;
+    DMA_CHANn_TypeDef           dmaInputChanNum;
+    DMA_CHANn_TypeDef           dmaOutputChanNum;
+    volatile ADI_CRYPTO_RESULT  dmaError;			/* DMA error collector. */
+#endif
+} CRYPTO_INFO;
+
+
+#ifdef __ICCARM__
+/*
+* Pm123 (RULE 8.5) there shall be no definition of objects or functions in a header file.
+* Exception is to allow the Crypto device data type and instance to be declared simultaniously.
+*/
+#pragma diag_suppress=Pm123
+#endif /* __ICCARM__ */
+
+/* Crypto driver internal data */
+struct __ADI_CRYPTO_DEV_DATA_TYPE {
+    bool                     bDeviceEnabled;         /* Boolean flag to signify whether the device is enable/disabled */
+    bool                     bDmaEnabled;            /* Boolean flag to signify whether the DMA is enable/disabled */
+    bool                     bCompletion;            /* Boolean flag to signify whether a transaction is complete */
+
+    ADI_CRYPT_TypeDef       *pDev;                   /* Pointer to physical Crypto controller */
+
+    CRYPTO_INFO             *pDevInfo;               /* access to device info */
+
+    CRYPTO_COMPUTE           Computation;            /* Active computation structure */
+
+	ADI_CRYPTO_TRANSACTION  *pUserBuffer;            /* saved user buffer pointer from submit */
+    ADI_CALLBACK             pfCallback;             /* User defined callback function */
+    void                    *pCBParam;               /* User defined callback param */
+    ADI_CRYPTO_RESULT        dmaErrorCode;           /* saved DMA error code to return via user API */
+
+
+    SEM_VAR_DECLR        /* Blocking object abstraction: "Semaphore" for rtos,  "bLowPowerExitFlag" for non-rtos, etc.    */
+} ADI_CRYPTO_DEV_DATA_TYPE;
+
+#ifdef __ICCARM__
+#pragma diag_default=Pm123
+#endif /* __ICCARM__ */
+
+/*! \endcond */
+
+#endif /* ADI_CRYPTO_DEF_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/dma/adi_dma.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/dma/adi_dma.c
new file mode 100755
index 00000000000..66474469ea6
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/dma/adi_dma.c
@@ -0,0 +1,346 @@
+/*! *****************************************************************************
+ * @file:    adi_dma.c
+ * @brief:   DMA manager global file.
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+
+
+/*! \addtogroup DMA_Driver DMA Driver
+ *  uDMA Device Driver.
+ *  @{
+ */
+
+/*=============  I N C L U D E S   =============*/
+#include <adi_processor.h>
+#include <drivers/dma/adi_dma.h>
+#include <adi_callback.h>
+#include <rtos_map/adi_rtos_map.h>
+#include <drivers/general/adi_drivers_general.h>
+
+/*! \cond PRIVATE */
+
+/*=============  M I S R A   =============*/
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm011 (rule 6.3): he basic types of char, int, short, long, float, and double should not be used
+*   Need to use bool.
+*
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   The rule makes an exception for memory-mapped register accesses.
+*/
+#pragma diag_suppress=Pm011,Pm140
+#endif /* __ICCARM__ */
+
+/*=============  D E F I N E S  =============*/
+
+/* CCD array allocation macros */
+#define CCD_ALIGN (0x400) /* Memory alignment required for CCD array */
+#define CCD_SIZE (32u)    /* Configure CCD allocation as an integral power of two,
+                            i.e., 24 channels is allocated as 32 */
+
+/*=============  R E G I S T E R    D E F I N E S  =============*/
+
+
+
+
+/*=============  T Y P E    D E F I N E S  =============*/
+
+/*! DMA Channel callback information structure */
+typedef struct _DMA_CHANNEL {
+    ADI_CALLBACK        pfCallback;             /*!< Pointer to the callback func */
+    void*               pCBParam;               /*!< Application Callback param */
+} DMA_CHANNEL_CALLBACK_INFO;
+
+/*! \struct ADI_DMA_DEV_DATA
+ * DMA Device instance data structure
+ *
+ * CallbackInfo[NUM_DMA_CHANNELSn]
+ * The semantics of indexes used to access CallbackInfo elements is defined by the semantics
+ * of the bits in registers DMA_ERRCHNL_CLR and DMA_INVALIDDESC_CLR. The position of these
+ * bits define the channel nodes of the peripheral they map to, e.g. bit N maps to channel
+ * node N.
+ */
+typedef struct {
+    bool                        Initialized;    /*!< track initialization state. See function adi_dma_Init) */
+    DMA_CHANNEL_CALLBACK_INFO   CallbackInfo[NUM_DMA_CHANNELSn];
+    uint32_t                    ChannelsInUse;  /*!< bits 0 to 26 record active channels */
+} ADI_DMA_DEV_DATA;
+
+
+/*=============  D A T A  =============*/
+
+/* DMA descriptor arrays must be contiguous */
+/* AND impose strict alignment requirements */
+/* Each compiler has different alignment directives */
+
+/* ALIGNED: DMA channel control data array declaration */
+ADI_ALIGNED_PRAGMA(CCD_ALIGN)
+static ADI_DCC_TypeDef gChannelControlDataArray[CCD_SIZE * 2u] ADI_ALIGNED_ATTRIBUTE(CCD_ALIGN)
+
+#ifdef ADI_DMA_DESCRIPTORS_IN_VOLATILE_MEMORY
+	/* conditional placement of DMA descriptor table to volatile memory */
+	@ "volatile_ram";
+#else
+	/* default placement to non-volatile memory (no override) */
+	;
+#endif
+
+
+/* pointer to the primary CCD array */
+ADI_DCC_TypeDef* const pPrimaryCCD = &gChannelControlDataArray[0];
+
+/* pointer to the alternate CCD array */
+ADI_DCC_TypeDef* const pAlternateCCD = &gChannelControlDataArray[CCD_SIZE];
+
+
+/*! DMA Device Driver Data instance
+ * 32 Channel Handles initialized to {0, 0}, i.e. call-back function pointer
+ * set to NULL and call-back function parameters set to NULL
+ */
+static ADI_DMA_DEV_DATA DMA_DevData = {
+
+    false,                      /*!< DMA device data not initialized. (See adi_dma_Init) */
+    {{0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0},
+     {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0},
+     {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0},
+     {0,0}, {0,0}, {0,0}},
+    0ul                         /*!< channels-in-use bitfield */
+};
+
+/*! pointer to the DMA Device Driver Data instance */
+static ADI_DMA_DEV_DATA* const pDMA_DevData = &DMA_DevData;
+
+/*=============  Local function declarations  =============*/
+
+/*==========  DMA HANDLERS  ==========*/
+
+/*! DMA Error Handler */
+void DMA_Err_Int_Handler(void);
+
+/*==========  U T I L I T Y    M A C R O S  ==========*/
+
+/*! \endcond*/
+/*=============  A P I    I M P L E M E N T A T I O N S  =============*/
+
+/*!
+ * @brief  Initialize the DMA peripheral
+ *
+ * @return         none
+ *
+ * The application must call this API once
+ *
+ */
+void adi_dma_Init(void)
+{
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+
+    if( false == pDMA_DevData->Initialized )
+    {
+        pDMA_DevData->Initialized = true;
+
+        /* Enable the DMA Controller */
+        pADI_DMA0->CFG |= BITM_DMA_CFG_MEN;
+
+        /* Set descriptor memory base pointer on DMA controller */
+        pADI_DMA0->PDBPTR = (uint32_t)pPrimaryCCD;
+
+        /* Enable the DMA Error Interrupt */
+        NVIC_EnableIRQ(DMA_CHAN_ERR_IRQn);
+
+        /* Reset per-channel, bitmapped control registers (W1C) */
+        const uint32_t w1r_value = (uint32_t) ((1 << NUM_DMA_CHANNELSn) - 1);
+        pADI_DMA0->RMSK_SET        = w1r_value;
+        pADI_DMA0->EN_CLR          = w1r_value;
+        pADI_DMA0->ALT_CLR         = w1r_value;
+        pADI_DMA0->PRI_CLR         = w1r_value;
+        pADI_DMA0->ERRCHNL_CLR     = w1r_value;
+        pADI_DMA0->ERR_CLR         = w1r_value;
+        pADI_DMA0->INVALIDDESC_CLR = w1r_value;
+    }
+
+    ADI_EXIT_CRITICAL_REGION();
+}
+
+/**
+ * @brief    Register a call-back function for a DMA channel.
+ *
+ * @param [in]  eChannelID    The ID of the DMA channel being assigned a call-back function.
+ * @param [in]  pfCallback    Pointer to the application callback function.
+ * @param [in]  pCBParam      Application callback parameter.
+ *
+ * @details  The function registers a call-back function for the DMA channel node
+ * identified by eChannelID and stores the extra parameters this call-back function
+ * may require. A NULL callback function pointer means "DMA channel unused".
+ *
+ * @return   Status
+ *              - #ADI_DMA_SUCCESS                      Successfully registered a call-back function for the given DMA channel node.
+ *              - #ADI_DMA_ERR_NOT_INITIALIZED          [D] adi_dma_Init must be called prior registering a call-back function.
+ *              - #ADI_DMA_ERR_INVALID_PARAMETER        [D] Some parameter(s) passed to the function is invalid.
+ */
+ADI_DMA_RESULT adi_dma_RegisterCallback (
+    DMA_CHANn_TypeDef   const eChannelID,
+    ADI_CALLBACK        const pfCallback,
+    void*               const pCBParam
+    )
+{
+    ADI_DMA_RESULT result = ADI_DMA_SUCCESS;
+
+#ifdef ADI_DEBUG
+    /* DMA must be initialized first */
+    if (false == pDMA_DevData->Initialized) {
+        result = ADI_DMA_ERR_NOT_INITIALIZED;
+    }else{
+        const size_t numChannelId = sizeof(pDMA_DevData->CallbackInfo) / sizeof(DMA_CHANNEL_CALLBACK_INFO);
+        if (numChannelId <= eChannelID)                 /*!< pDMA_DevData->CallbackInfo definition is invalid */
+        {
+            result = ADI_DMA_ERR_INVALID_PARAMETER;
+        }
+    }
+    if (ADI_DMA_SUCCESS == result)              /* if no errors previously detected */
+#endif
+    {
+        /* eChannelID cannot be out of range by definition (we use DMA_CHANn_TypeDef) */
+        DMA_CHANNEL_CALLBACK_INFO * pChannel = &pDMA_DevData->CallbackInfo[eChannelID];
+
+        /* Set the callback parameters */
+        pChannel->pfCallback = pfCallback;      /* assign the pointer to a callback function */
+        pChannel->pCBParam   = pCBParam;        /* store the parameters to be used with the callback function */
+
+        const uint32_t nChannelBit = (1u << eChannelID);
+        if (NULL != pfCallback) {
+            pDMA_DevData->ChannelsInUse |= nChannelBit;         /* set the bit to mark the channel as "being used" */
+        }else{
+            pDMA_DevData->ChannelsInUse &= (~nChannelBit);      /* clear the bit to mark the channel as "not being used" */
+        }
+    }
+    return result;
+}
+
+/*! \cond PRIVATE */
+
+
+#if defined(__ICCARM__)
+
+/* ARM Cortex-M3/M4, IAR compiler (CMSIS standard) */
+#define ADI_CLZ(X)     __CLZ(X)
+
+#elif defined(__GNUC__)
+
+/* ARM Cortex-M3/M4, GNU-ARM compiler */
+#define ADI_CLZ(X)     __builtin_clz(X)
+
+#elif defined(__ARMCC_VERSION)
+
+/* ARM Cortex-M3/M4, Keil compiler */
+#define ADI_CLZ(X)    __clz(X)
+
+#else
+
+#error "Macro ADI_CLZ undefined!!!"
+
+#endif
+
+/*! DMA Error Handler
+ *
+ * The DMA Error handler looks at the channels in use which are flagged in register ERRCHNL_CLR
+ * or INVALIDDESC_CLR and calls the associated call-back functions, if defined. If a call-back
+ * function is undefined (NULL pointer) then it means the associated driver ignores these errors.
+ *
+ * Then, all the bits set in ERRCHNL_CLR and INVALIDDESC_CLR at the time the handler is called
+ * are cleared.
+ */
+void DMA_Err_Int_Handler(void)
+{
+    ISR_PROLOG()
+
+    const uint32_t nErrClr = pADI_DMA0->ERR_CLR;                /* get all the bits set in ERR_CLR */
+    const uint32_t nErrChnClr = pADI_DMA0->ERRCHNL_CLR;         /* get all the bits set in ERRCHNL_CLR */
+    const uint32_t nInvdDescClr = pADI_DMA0->INVALIDDESC_CLR;   /* get all the bits set in INVALIDDESC_CLR */
+
+    /* if there are invalid channel descriptors or channel errors amongts the channels in use */
+    uint32_t functionsToBeCalled = pDMA_DevData->ChannelsInUse & (nErrChnClr | nInvdDescClr);
+
+    if (functionsToBeCalled > 0u)
+    {
+        const uint32_t numBits = sizeof(uint32_t) << 3; /* maximum number of bits to be considered */
+        uint32_t nlz;                                   /* number of leading zeroes in functionsToBeCalled */
+
+        /* For all the bits set in functionsToBeCalled, starting from the MSB */
+        for (nlz = (uint32_t) ADI_CLZ(functionsToBeCalled); nlz < numBits; nlz = (uint32_t) ADI_CLZ(functionsToBeCalled))
+        {
+            const uint32_t bitSet = numBits - nlz - 1u; /* bit position in functionsToBeCalled */
+            const uint32_t selected_bit = ((uint32_t)1u << bitSet);
+            DMA_CHANNEL_CALLBACK_INFO* pChannel = &pDMA_DevData->CallbackInfo[bitSet];
+
+            /* if there's a callback function to be called */
+            if (NULL != pChannel->pfCallback)
+            {
+                /* define the nature of the error: DMA bus error or else invalid descriptor */
+                uint32_t nEvent = ((nErrChnClr & selected_bit) != 0u)
+                                ? (uint32_t)ADI_DMA_EVENT_ERR_BUS
+                                : (uint32_t)ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR;
+
+                /* report the error to the peripheral through the callback function */
+                pChannel->pfCallback (pChannel->pCBParam, nEvent, NULL );
+            }
+
+            functionsToBeCalled &= ~selected_bit;       /* clear bit in functionsToBeCalled */
+        }
+    }
+
+    /* Clear the errors processed in the loop above */
+    pADI_DMA0->ERRCHNL_CLR = nErrChnClr;        /* W1C: clear only all the bits set in nErrChnClr */
+    pADI_DMA0->INVALIDDESC_CLR = nInvdDescClr;  /* W1C: clear only all the bits set in nInvdDescClr */
+    pADI_DMA0->ERR_CLR = nErrClr;               /* W1C: clear only all the bits set in nErrClr */
+
+    ISR_EPILOG()
+}
+
+/*! \endcond*/
+
+/**@}*/
+
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/adc/adi_adc.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/adc/adi_adc.h
new file mode 100755
index 00000000000..1794f4ab2c4
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/adc/adi_adc.h
@@ -0,0 +1,346 @@
+/*! *****************************************************************************
+ * @file    adi_adc.h
+ * @brief   Main include file for ADC Device driver definitions
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_ADC_H
+#define ADI_ADC_H
+
+#include <adi_processor.h>
+#include <adi_callback.h>
+#include <adi_adc_config.h>
+#include <rtos_map/adi_rtos_map.h>  /* for ADI_SEM_SIZE */
+
+/** @addtogroup  ADC_Driver ADC Driver
+*  @{
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! Amount of memory(In bytes) required by the ADC device driver for managing the operation
+ *  of a ADC controller. The memory is passed to the driver when the driver is opended.
+ * The memory is completely owned by the driver till the the driver is closed.
+ *
+ */
+#define ADI_ADC_MEMORY_SIZE (48u + ADI_SEM_SIZE)          /*!< Memory Size of the buffer required by the ADC driver */
+
+
+/*!
+ * \enum ADI_ADC_RESULT
+ * ADC API return codes
+ */
+typedef enum {
+    ADI_ADC_SUCCESS                  = 0,     /*!< No Error, API suceeded */
+    ADI_ADC_INVALID_DEVICE_NUM,               /*!< Invalid device number passed */
+    ADI_ADC_INVALID_DEVICE_HANDLE,            /*!< Invalid device handle passed */
+    ADI_ADC_INVALID_STATE,                    /*!< Invalid State */
+    ADI_ADC_INSUFFICIENT_MEMORY,              /*!< Insufficient memory passed to the driver */
+    ADI_ADC_IN_USE,                           /*!< ADC is alreaady in use */
+    ADI_ADC_INVALID_PARAMETER,                /*!< Invalid parameter passed to the driver */
+    ADI_ADC_NULL_POINTER,                     /*!< Null pointer passed when expecting a valid pointer */
+    ADI_ADC_FAILURE,                          /*!< General ADC Failure */
+    ADI_ADC_INVALID_SEQUENCE,                 /*!< Invalid sequence of API calls */
+    ADI_ADC_ERR_RTOS,                         /*!< RTOS error occurred */
+    ADI_ADC_INVALID_OPERATION,                /*!< API call is an invalid operation */
+    ADI_ADC_INVALID_BUFFER,                   /*!< Buffer passed to the application is invalid */
+    ADI_ADC_BUFFER_OVERFLOW,                  /*!< Buffer overflow occurred */
+    ADI_ADC_DMA_ERROR,			      /*!< DMA Error occurred */
+    ADI_ADC_BAD_SYS_CLOCK,                    /*!< Could not retrieve core clock value. */
+} ADI_ADC_RESULT;
+
+/*!
+ * \enum ADI_ADC_VREF_SRC
+ * Voltage Reference source selection.
+ */
+typedef enum {
+    ADI_ADC_VREF_SRC_INT_1_25_V,        /*!< 1.25V Internal Voltage Reference */
+    ADI_ADC_VREF_SRC_INT_2_50_V,        /*!< 2.50V Internal Voltage Reference */
+    ADI_ADC_VREF_SRC_EXT,               /*!< External Voltage Reference */
+    ADI_ADC_VREF_SRC_VBAT,              /*!< Battery Voltage as Voltage Reference source */
+} ADI_ADC_VREF_SRC;
+
+/*!
+ * \enum ADI_ADC_RESOLUTION
+ * Resolution of the ADC.
+ */
+typedef enum {
+    ADI_ADC_RESOLUTION_12_BIT,      /*!< 12-bit ADC Resolution */
+    ADI_ADC_RESOLUTION_13_BIT,      /*!< 13-bit ADC Resolution */
+    ADI_ADC_RESOLUTION_14_BIT,      /*!< 14-bit ADC Resolution */
+    ADI_ADC_RESOLUTION_15_BIT,      /*!< 15-bit ADC Resolution */
+    ADI_ADC_RESOLUTION_16_BIT       /*!< 16-bit ADC Resolution */
+} ADI_ADC_RESOLUTION;
+
+/*!
+ * \typedef ADI_ADC_CHANNEL
+ * Typedef for ADC Channels
+ */
+typedef uint32_t ADI_ADC_CHANNEL;
+
+/*!
+ * defines for ADC Channels
+ */
+#define    ADI_ADC_CHANNEL_0  (1u << 0u) /*!< ADC Channel 0 */
+#define    ADI_ADC_CHANNEL_1  (1u << 1u) /*!< ADC Channel 1 */
+#define    ADI_ADC_CHANNEL_2  (1u << 2u) /*!< ADC Channel 2 */
+#define    ADI_ADC_CHANNEL_3  (1u << 3u) /*!< ADC Channel 3 */
+#define    ADI_ADC_CHANNEL_4  (1u << 4u) /*!< ADC Channel 4 */
+#define    ADI_ADC_CHANNEL_5  (1u << 5u) /*!< ADC Channel 5 */
+#define    ADI_ADC_CHANNEL_6  (1u << 6u) /*!< ADC Channel 6 */
+#define    ADI_ADC_CHANNEL_7  (1u << 7u) /*!< ADC Channel 7 */
+
+/*!
+ * \enum ADI_ADC_EVENT
+ * Callback events from the ADC driver.
+ */
+typedef enum {
+    ADI_ADC_EVENT_CALIBRATION_DONE,         /*!< Calibration done event.   arg to the callback function will be NULL. */
+    ADI_ADC_EVENT_ADC_READY,	            /*!< ADC Ready event.          arg to the callback function will be null */
+    ADI_ADC_EVENT_OVERFLOW,                 /*!< Overflow event occurred.  The channel(#ADI_ADC_CHANNEL) for which the overflow occurred will be passed as arg to the callback function. */	
+    ADI_ADC_EVENT_HIGH_LIMIT_CROSSED,       /*!< High Limit crossed event. The channel(#ADI_ADC_CHANNEL) for which the limit is crossed will be passed as arg to the callback function. */
+    ADI_ADC_EVENT_LOW_LIMIT_CROSSED,        /*!< Low Limit crossed event.  The channel(#ADI_ADC_CHANNEL) for which the limit is crossed will be passed as arg to the callback function.  */
+} ADI_ADC_EVENT;
+
+/*! Structure which hold the details of the buffer and sampling details */
+typedef struct __ADI_ADC_BUFFER {
+    uint32_t  nChannels;                    /*!<    Channels to sample. Should be an ORed value of #ADI_ADC_CHANNEL enum */
+    void*     pDataBuffer;                  /*!<    Pointer to the Buffer to read the sample value into. If single channel(say Channel 0) is selected
+                                                    then the format of buffer will be <Chan0 conversion 0><Chan0 conversion 1><Chan0 conversion 2>.... but if
+                                                    multiple channels (say Channel 1 and Channel2) are selected then the format of buffer will be
+                                                    <Chan1 conversion 0><Chan2 conversion 0><Chan1 conversion 1><Chan2 conversion 1><Chan1 conversion 2><Chan2 conversion 2>....
+                                                    \n The pBuffer should be 2 byte aligned.
+                                                    \n
+                                                    \n If N is the number of channels selected then in single iteration mode the number of samples
+                                                       written to in the buffer will be N and for multiple iteration, the driver will try to fill the whole
+                                                       buffer with data and it is preferred that the nBuffSize be able to accommodate a multiple of N samples.
+                                              */
+    uint32_t  nNumConversionPasses; /*!< Num of conversion passes */
+    uint32_t  nBuffSize;            /*!< Size of the buffer supplied */
+} ADI_ADC_BUFFER;
+
+/* Type def for the ADC Handle. */
+typedef struct __ADI_ADC_DEVICE* ADI_ADC_HANDLE;  /*!< ADC Device Handler */
+
+
+/*=============  A P I   F U N C T I O N S    P R O T O T Y P E S  =============*/
+
+/* Opens an ADC device instance. */
+ADI_ADC_RESULT adi_adc_Open (
+        uint32_t        nDeviceNum,
+        void*           pMemory,
+        uint32_t        nMemorySize,
+        ADI_ADC_HANDLE* phDevice
+);
+
+/*  Close the given device instance */
+ADI_ADC_RESULT adi_adc_Close(ADI_ADC_HANDLE hDevice);
+
+/* Power up or power down the ADC */
+ADI_ADC_RESULT adi_adc_PowerUp (ADI_ADC_HANDLE hDevice, bool bPowerUp);
+
+/* Register the callback */
+ADI_ADC_RESULT adi_adc_RegisterCallback(
+    ADI_ADC_HANDLE     hDevice,
+    ADI_CALLBACK       pfCallback,
+    void              *pCBParam
+);
+
+/* Enables/Disables the ADC Subsystem */
+ ADI_ADC_RESULT adi_adc_EnableADCSubSystem (
+    ADI_ADC_HANDLE  hDevice,
+    bool            bEnable
+);
+
+/* Returns whether the ADC subsytem is ready */
+ADI_ADC_RESULT adi_adc_IsReady (
+     ADI_ADC_HANDLE  hDevice,
+     bool           *pbReady
+);
+
+/* Set the voltage reference source */
+ADI_ADC_RESULT adi_adc_SetVrefSource (
+    ADI_ADC_HANDLE    hDevice,
+    ADI_ADC_VREF_SRC  eVrefSrc
+);
+
+/* Enable/Disable current sink */
+ADI_ADC_RESULT adi_adc_SinkEnable (
+    ADI_ADC_HANDLE   hDevice,
+    bool             bEnable
+);
+
+/* Start the ADC Calibration */
+ADI_ADC_RESULT adi_adc_StartCalibration (
+    ADI_ADC_HANDLE hDevice
+);
+
+ ADI_ADC_RESULT adi_adc_IsCalibrationDone (
+     ADI_ADC_HANDLE hDevice,
+     bool*          pbCalibrationDone
+ );
+
+
+/* Set the acquisition time of ADC in ADC clock cycles */
+ADI_ADC_RESULT adi_adc_SetAcquisitionTime(
+    ADI_ADC_HANDLE hDevice,
+    uint32_t       nAcqTimeInAClkCycles
+);
+
+/* Set the delay time of ADC in ADC cycles for multi iteration mode */
+ADI_ADC_RESULT adi_adc_SetDelayTime(
+    ADI_ADC_HANDLE hDevice,
+    uint32_t       nDelayInAClkCycles
+);
+
+/* set the resolution of ADC. The default resolution of ADC is 12-bit and the ADC increases the resolution by oversampling */
+ADI_ADC_RESULT adi_adc_SetResolution (
+   ADI_ADC_HANDLE      hDevice,
+   ADI_ADC_RESOLUTION  eResolution
+);
+
+/* Enable Averaging for all ADC channels */
+ADI_ADC_RESULT adi_adc_EnableAveraging (
+    ADI_ADC_HANDLE  hDevice,
+    uint16_t        nAveragingSamples
+);
+
+/* Configure low limit for an ADC channel when it's used as a digital comparator. */
+ADI_ADC_RESULT adi_adc_SetLowLimit (
+    ADI_ADC_HANDLE   hDevice,
+    ADI_ADC_CHANNEL  eChannel,
+    bool             bEnable,
+    uint16_t         nLowLimit
+);
+
+/* Configure high limit for an ADC channel when it's used as a digital comparator. */
+ADI_ADC_RESULT adi_adc_SetHighLimit (
+    ADI_ADC_HANDLE   hDevice,
+    ADI_ADC_CHANNEL  eChannel,
+    bool             bEnable,
+    uint16_t         nHighLimit
+);
+
+
+/* Configure hysteresis for an ADC channel when it's used as a digital comparator. */
+ADI_ADC_RESULT adi_adc_SetHysteresis(
+    ADI_ADC_HANDLE   hDevice,
+    ADI_ADC_CHANNEL  eChannel,
+    bool             bEnable,
+    uint16_t         nHysteresis
+);
+
+/* Configure number of monitor cycles for an ADC channel when it's used as a digital comparator. */
+ADI_ADC_RESULT adi_adc_SetNumMonitorCycles(
+    ADI_ADC_HANDLE   hDevice,
+    ADI_ADC_CHANNEL  eChannel,
+    uint32_t         nNumMonitorCycles
+);
+
+/*  Enable/Disable digital comparator for the given channel(s) */
+ADI_ADC_RESULT adi_adc_EnableDigitalComparator (
+    ADI_ADC_HANDLE   hDevice,
+    bool             bEnableComparator
+);
+
+/* Submit buffer for sampling */
+ADI_ADC_RESULT adi_adc_SubmitBuffer (
+    ADI_ADC_HANDLE      hDevice,
+    ADI_ADC_BUFFER*     pBuffer
+);
+
+/* Get a completed buffer from the driver */
+ADI_ADC_RESULT adi_adc_GetBuffer(
+    ADI_ADC_HANDLE      hDevice,
+    ADI_ADC_BUFFER**    ppBuffer
+);
+
+/* Enable/Disable buffer processing */
+ADI_ADC_RESULT adi_adc_Enable (
+    ADI_ADC_HANDLE  hDevice,
+    bool            bEnable
+);
+
+/* Check whether a completed buffer is available in the driver */
+ADI_ADC_RESULT adi_adc_IsBufferAvailable(
+    ADI_ADC_HANDLE      hDevice,
+    bool*               pbIsBufferAvailable
+);
+
+/* Read the given channels. This will only return once the given amount of samples are collected */
+ADI_ADC_RESULT adi_adc_ReadChannels (
+    ADI_ADC_HANDLE   hDevice,
+    uint32_t         nChannels,
+    uint32_t         nNumConversionPasses,
+    void*            pBuffer,
+    uint32_t         nBuffLength
+);
+
+/* Get Battery Voltage */
+ADI_ADC_RESULT adi_adc_GetBatteryVoltage (
+    ADI_ADC_HANDLE  hDevice,
+    uint32_t        nRefVoltage,
+    uint32_t*       pnBatVoltage
+);
+
+/* Enable/Disable Temperature Sensor */
+ADI_ADC_RESULT adi_adc_EnableTemperatureSensor (
+    ADI_ADC_HANDLE hDevice,
+    bool           bEnable
+    );
+
+/* Get the Temperature Value */
+ADI_ADC_RESULT adi_adc_GetTemperature (
+    ADI_ADC_HANDLE  hDevice,
+    uint32_t        nRefVoltage,
+    int32_t*        pnTemperature
+    );
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+
+
+#endif /* ADI_ADC_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/beep/adi_beep.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/beep/adi_beep.h
new file mode 100755
index 00000000000..6fa441895ec
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/beep/adi_beep.h
@@ -0,0 +1,277 @@
+/*! *****************************************************************************
+ * @file    adi_beep.h
+ * @brief   Main include file for BEEP device driver definitions
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+/** @addtogroup BEEP_Driver BEEP Driver
+*  @{
+*/
+#ifndef ADI_BEEP_H
+#define ADI_BEEP_H
+
+#include "adi_processor.h"
+
+#include <adi_beep_config.h>
+#include <adi_callback.h>
+#include <rtos_map/adi_rtos_map.h> 
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+  
+/*! Amount of memory(In bytes) required by the Beep device driver for managing the operation.
+ * This memory is completely owned by the driver till the end of the operation.
+ */
+#if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1
+/*! @hideinitializer Indicates the size of the BEEP memory to be used */
+#define ADI_BEEP_MEMORY_SIZE        (20u + ADI_SEM_SIZE)
+#else
+/*! @hideinitializer Indicates the size of the BEEP memory to be used */
+#define ADI_BEEP_MEMORY_SIZE        (12u + ADI_SEM_SIZE)
+#endif
+   
+/*!
+ * \enum ADI_BEEP_RESULT
+ * Beeper API return codes
+ */
+typedef enum
+{
+    ADI_BEEP_SUCCESS = 0,            /*!<  No Error, API suceeded */
+
+    ADI_BEEP_FAILURE,                /*!<  An unknown error was detected */
+    ADI_BEEP_ALREADY_INITIALIZED,    /*!<  BEEP is already initialized */
+    ADI_BEEP_BAD_DEV_HANDLE,         /*!<  Invalid device handle passed */
+    ADI_BEEP_BAD_DEV_ID,             /*!<  Asking to initialize an unknown device num */
+    ADI_BEEP_NOT_INITIALIZED,        /*!<  BEEP not yet initialized */
+    ADI_BEEP_PARAM_OUT_OF_RANGE,     /*!<  Parameter is out of range. */
+    ADI_BEEP_INVALID_COUNT,          /*!<  Invalid count for supplied beep sequence */
+    ADI_BEEP_NULL_PTR,               /*!<  Null pointer supplied. */
+    ADI_BEEP_SEMAPHORE_FAILED,       /*!<  BEEP semaphore failure. */
+} ADI_BEEP_RESULT;
+
+
+/*!
+ * \enum ADI_BEEP_DEV_ID
+ *  @brief  Beeper Device IDs.
+ *  @details List of all Beeper Device IDs for the current part
+ */
+typedef enum
+{
+    ADI_BEEP_DEVID_0 = 0,       /*!<  BEEP Timer Device 0 */
+    ADI_BEEP_MAX_DEVID          /*!<  max number of BEEP devices */
+} ADI_BEEP_DEV_ID;
+
+/*!
+ * \enum ADI_BEEP_INTERRUPT
+ *  @brief  Beeper Interrupt Bits.
+ *  @details List of all Beeper interrupt (enables and status) bits.
+ */
+typedef enum
+{
+    ADI_BEEP_INTERRUPT_SEQUENCE_END            = BITM_BEEP_CFG_SEQATENDIRQ,   /*!<  Beeper sequence has finished      */
+    ADI_BEEP_INTERRUPT_NOTE_END                = BITM_BEEP_CFG_AENDIRQ,       /*!<  Beeper note has finished        */
+} ADI_BEEP_INTERRUPT;
+
+
+#define LFCLK_FREQ           32768.0f                                         /*!< Beeper main clock frequency.            */
+#define FREQUENCY_ENCODE(x) (uint8_t)(LFCLK_FREQ/(x) + 0.5f)                  /*!< Beeper tone frequency encoder macro     */
+
+/*!
+ * \enum ADI_BEEP_NOTE_FREQUENCY
+ *  @brief  Beeper tone frequency list.
+ *  @details List of possible Beeper tone frequencies.
+ */
+typedef enum {
+	/* Constants are pre-computed note frequencies (Hz).                 */
+	/* See http://www.phy.mtu.edu/~suits/notefreqs.html.                 */
+	/* Encodings are clock divider values for that note.                 */
+	/* Flats are the same as the lower sharp, so only sharps are listed. */
+	/* Even though octaves are simple frequency doublings/halvings       */
+	/* of adjuacient octaves, we pre-compute each constant (as opposed   */
+	/* to halving/doubling the encodings between octaves) to             */
+	/* minimize repeated doubling/halving errors across all octaves.     */
+	/* !!!ALL ENCODINGS MUST BE IN THE RANGE 4-127!!!                    */
+
+	ADI_BEEP_FREQ_REST = (0),                       /*!< silence */
+
+	ADI_BEEP_FREQ_C4  = FREQUENCY_ENCODE(261.63f),  /*!< Middle C (lowest representable frequency @ 32KHz) */
+	ADI_BEEP_FREQ_Cs4 = FREQUENCY_ENCODE(277.18f),
+	ADI_BEEP_FREQ_D4  = FREQUENCY_ENCODE(293.66f),
+	ADI_BEEP_FREQ_Ds4 = FREQUENCY_ENCODE(311.13f),
+	ADI_BEEP_FREQ_E4  = FREQUENCY_ENCODE(329.63f),
+	ADI_BEEP_FREQ_F4  = FREQUENCY_ENCODE(349.23f),
+	ADI_BEEP_FREQ_Fs4 = FREQUENCY_ENCODE(369.99f),
+	ADI_BEEP_FREQ_G4  = FREQUENCY_ENCODE(392.00f),
+	ADI_BEEP_FREQ_Gs4 = FREQUENCY_ENCODE(415.30f),
+	ADI_BEEP_FREQ_A4  = FREQUENCY_ENCODE(440.00f),
+	ADI_BEEP_FREQ_As4 = FREQUENCY_ENCODE(466.16f),
+	ADI_BEEP_FREQ_B4  = FREQUENCY_ENCODE(493.88f),
+
+	ADI_BEEP_FREQ_C5  = FREQUENCY_ENCODE(523.25f),
+	ADI_BEEP_FREQ_Cs5 = FREQUENCY_ENCODE(554.37f),
+	ADI_BEEP_FREQ_D5  = FREQUENCY_ENCODE(587.33f),
+	ADI_BEEP_FREQ_Ds5 = FREQUENCY_ENCODE(622.25f),
+	ADI_BEEP_FREQ_E5  = FREQUENCY_ENCODE(659.26f),
+	ADI_BEEP_FREQ_F5  = FREQUENCY_ENCODE(698.46f),
+	ADI_BEEP_FREQ_Fs5 = FREQUENCY_ENCODE(739.99f),
+	ADI_BEEP_FREQ_G5  = FREQUENCY_ENCODE(783.99f),
+	ADI_BEEP_FREQ_Gs5 = FREQUENCY_ENCODE(830.61f),
+	ADI_BEEP_FREQ_A5  = FREQUENCY_ENCODE(880.00f),
+	ADI_BEEP_FREQ_As5 = FREQUENCY_ENCODE(932.33f),
+	ADI_BEEP_FREQ_B5  = FREQUENCY_ENCODE(987.77f),
+
+	ADI_BEEP_FREQ_C6  = FREQUENCY_ENCODE(1046.50f),
+	ADI_BEEP_FREQ_Cs6 = FREQUENCY_ENCODE(1108.73f),
+	ADI_BEEP_FREQ_D6  = FREQUENCY_ENCODE(1174.66f),
+	ADI_BEEP_FREQ_Ds6 = FREQUENCY_ENCODE(1244.51f),
+	ADI_BEEP_FREQ_E6  = FREQUENCY_ENCODE(1318.51f),
+	ADI_BEEP_FREQ_F6  = FREQUENCY_ENCODE(1396.91f),
+	ADI_BEEP_FREQ_Fs6 = FREQUENCY_ENCODE(1479.98f),
+	ADI_BEEP_FREQ_G6  = FREQUENCY_ENCODE(1567.98f),
+	ADI_BEEP_FREQ_Gs6 = FREQUENCY_ENCODE(1661.22f),
+	ADI_BEEP_FREQ_A6  = FREQUENCY_ENCODE(1760.00f),
+	ADI_BEEP_FREQ_As6 = FREQUENCY_ENCODE(1864.66f),
+	ADI_BEEP_FREQ_B6  = FREQUENCY_ENCODE(1975.53f),
+
+	ADI_BEEP_FREQ_C7  = FREQUENCY_ENCODE(2093.00f),
+	ADI_BEEP_FREQ_Cs7 = FREQUENCY_ENCODE(2217.46f),
+	ADI_BEEP_FREQ_D7  = FREQUENCY_ENCODE(2349.32f),
+	ADI_BEEP_FREQ_Ds7 = FREQUENCY_ENCODE(2489.02f),
+	ADI_BEEP_FREQ_E7  = FREQUENCY_ENCODE(2637.02f),
+	ADI_BEEP_FREQ_F7  = FREQUENCY_ENCODE(2793.83f),
+	ADI_BEEP_FREQ_Fs7 = FREQUENCY_ENCODE(2959.96f),
+	ADI_BEEP_FREQ_G7  = FREQUENCY_ENCODE(3135.96f),
+	ADI_BEEP_FREQ_Gs7 = FREQUENCY_ENCODE(3322.44f),
+	ADI_BEEP_FREQ_A7  = FREQUENCY_ENCODE(3520.00f),
+	ADI_BEEP_FREQ_As7 = FREQUENCY_ENCODE(3729.31f),
+	ADI_BEEP_FREQ_B7  = FREQUENCY_ENCODE(3951.07f),
+
+	ADI_BEEP_FREQ_C8  = FREQUENCY_ENCODE(4186.01f),
+	ADI_BEEP_FREQ_Cs8 = FREQUENCY_ENCODE(4434.92f),
+	ADI_BEEP_FREQ_D8  = FREQUENCY_ENCODE(4698.64f),
+	ADI_BEEP_FREQ_Ds8 = FREQUENCY_ENCODE(4978.03f),
+	ADI_BEEP_FREQ_E8  = FREQUENCY_ENCODE(5274.04f),
+	ADI_BEEP_FREQ_F8  = FREQUENCY_ENCODE(5587.65f),
+	ADI_BEEP_FREQ_Fs8 = FREQUENCY_ENCODE(5919.91f),
+	ADI_BEEP_FREQ_G8  = FREQUENCY_ENCODE(6271.93f),
+} ADI_BEEP_NOTE_FREQUENCY;
+
+#define ADI_BEEP_DUR_ZERO      (0)                       /*!<  Beeper zero tone duration value          */
+#define ADI_BEEP_DUR_MIN       (1)                       /*!<  Beeper minimum tone duration value       */
+#define ADI_BEEP_DUR_MAX       (254)                     /*!<  Beeper maximum tone duration value       */
+#define ADI_BEEP_DUR_INFINITE  (255)                     /*!<  Beeper infinite tone duration value      */
+
+/*! A device handle used in all API functions to identify the BEEP device. */
+typedef void * ADI_BEEP_HANDLE;
+
+#define DURATION_ENCODE(x) (uint8_t)((float)ADI_BEEP_DUR_MAX/(float)(x) + 0.5f)    /*!<  Beeper tone duration encoder macro      */
+
+/*!
+ * \enum ADI_BEEP_NOTE_DURATION
+ *  @brief  Beeper tone duration list.
+ *  @details List of possible Beeper tone durations.
+ */
+typedef enum {
+	ADI_BEEP_DUR_0         = ADI_BEEP_DUR_ZERO,        /*!<  stop                       */
+	ADI_BEEP_DUR_32_32     = DURATION_ENCODE(1),       /*!<  whole note (1.016 seconds) */
+	ADI_BEEP_DUR_16_32     = DURATION_ENCODE(2),       /*!<  half note                  */
+	ADI_BEEP_DUR_12_32     = DURATION_ENCODE(8/3),     /*!<  three eights note          */
+	ADI_BEEP_DUR_8_32      = DURATION_ENCODE(4),       /*!<  one quarter note           */
+	ADI_BEEP_DUR_6_32      = DURATION_ENCODE(16/3),    /*!<  three sixteenth note       */
+	ADI_BEEP_DUR_4_32      = DURATION_ENCODE(8),       /*!<  one eighth note            */
+	ADI_BEEP_DUR_2_32      = DURATION_ENCODE(16),      /*!<  one sixteenth note         */
+	ADI_BEEP_DUR_1_32      = DURATION_ENCODE(32),      /*!<  one thirty-secondth note   */
+	ADI_BEEP_DUR_N         = ADI_BEEP_DUR_INFINITE,    /*!<  continuous play            */
+} ADI_BEEP_NOTE_DURATION;
+
+/*!
+ * \struct ADI_BEEP_NOTE
+ *  @brief  Beeper note structure.
+ *  @details Describes a note in terms of frequency and duration.
+ */
+typedef struct {
+   ADI_BEEP_NOTE_FREQUENCY frequency;  /*!<  Frequency of the note */
+   ADI_BEEP_NOTE_DURATION  duration;   /*!<  Duration of the note */
+} ADI_BEEP_NOTE;
+
+
+/*================ E X T E R N A L S ==================*/
+
+/*
+ * Beeper API
+ */
+
+ADI_BEEP_RESULT adi_beep_Open                   (ADI_BEEP_DEV_ID          const DeviceNum,
+                                                 void*                    const pMemory,
+                                                 uint32_t                 const MemorySize,
+                                                 ADI_BEEP_HANDLE*         const phDevice);
+
+ADI_BEEP_RESULT adi_beep_RegisterCallback       (ADI_BEEP_HANDLE const hDevice, 
+                                                 ADI_CALLBACK          pfCallback,
+                                                 void* const           pCBParam);
+
+ADI_BEEP_RESULT adi_beep_PlayNote               (ADI_BEEP_HANDLE          const hDevice,
+                                                 ADI_BEEP_NOTE            note);
+
+ADI_BEEP_RESULT adi_beep_PlayTwoTone            (ADI_BEEP_HANDLE          const hDevice, 
+                                                 ADI_BEEP_NOTE            noteA,
+                                                 ADI_BEEP_NOTE            noteB,
+                                                 uint8_t                  count);
+
+ADI_BEEP_RESULT adi_beep_PlaySequence           (ADI_BEEP_HANDLE const hDevice, 
+                                                 ADI_BEEP_NOTE aSequence[], 
+                                                 uint8_t count);
+
+ADI_BEEP_RESULT adi_beep_Enable                 (ADI_BEEP_HANDLE          const hDevice,
+                                                 bool                     const bFlag);
+
+ADI_BEEP_RESULT adi_beep_Wait                   (ADI_BEEP_HANDLE          const hDevice);
+
+ADI_BEEP_RESULT adi_beep_Close                  (ADI_BEEP_HANDLE          const hDevice);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* ADI_BEEP_H */
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/crc/adi_crc.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/crc/adi_crc.h
new file mode 100755
index 00000000000..9fddbc60858
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/crc/adi_crc.h
@@ -0,0 +1,236 @@
+/*! *****************************************************************************
+ * @file    adi_crc.h
+ * @brief   CRC (Cyclic Redundancy Check) Device driver global include file
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders. This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_CRC_H
+#define ADI_CRC_H
+
+/** @addtogroup CRC_Driver CRC Device Driver
+ *  @{
+ */
+
+#include <adi_processor.h>
+
+/*=============  I N C L U D E S   =============*/
+#include <string.h>
+/* Memory size check */
+#include <assert.h>
+
+/* DMA Manager includes */
+#include <drivers/dma/adi_dma.h>
+
+/* Include the config file for CRC */
+#include <adi_crc_config.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*==============  D E F I N E S  ===============*/
+
+#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT == 0)
+
+
+/**
+ * The size of types may vary between building tools (int, char, enumerator, etc.).
+ * This impacts the memory size required by a CRC driver.
+ * Consequently, ADI_CRC_MEMORY_SIZE is environment dependent.
+ */
+#if defined(__ICCARM__)
+/**
+ * The amount of application supplied memory required to operate a core driven CRC device
+ * using a CRC driver built in IAR environment.
+ */
+#define ADI_CRC_MEMORY_SIZE    (32u)
+#else
+/**
+ * The amount of application supplied memory required to operate a core driven CRC device
+ * using a CRC driver built in a generic built environment.
+ * Note: Create a new macro definition for your targetted development environment
+ *       if this generic value was not appropriate in your development environment.
+ */
+#define ADI_CRC_MEMORY_SIZE    (32u)
+#endif
+
+
+#else   /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */
+
+
+/**
+ * The size of types may vary between building tools (int, char, enumerator, etc.).
+ * This impacts the memory size required by a CRC driver.
+ * Consequently, ADI_CRC_MEMORY_SIZE is environment dependent.
+ */
+#if defined(__ICCARM__)
+/**
+ * The amount of application supplied memory required to operate a DMA driven CRC device
+ * using a CRC driver built in IAR environment.
+ */
+#define ADI_CRC_MEMORY_SIZE    (32u)
+#else
+/**
+ * The amount of application supplied memory required to operate a DMA driven CRC device
+ * using a CRC driver built in a generic built environment.
+ * Note: Create a new macro definition for your targetted development environment
+ *       if this generic value was not appropriate in your development environment.
+ */
+#define ADI_CRC_MEMORY_SIZE    (32u)
+#endif
+
+/** Check that a DMA channel can be used with CRC */
+#define ADI_CRC_VALID_DMA_CHANNEL(DMA_CHANNEL_ID) ((SIP0_CHANn<=(DMA_CHANNEL_ID)) && ((DMA_CHANNEL_ID)<=SIP7_CHANn))
+
+/**
+ * CRC events used in CRC callback functions to report
+ * - the completion of a DMA driven CRC request
+ * - errors detected when executing a DMA driven CRC request
+ */
+typedef enum __ADI_CRC_EVENT
+{
+    /*! DMA driven CRC peripheral has completed processing a request */
+    ADI_CRC_EVENT_BUFFER_PROCESSED = ADI_DMA_EVENT_BUFFER_PROCESSED,
+
+    /*! DMA driven CRC peripheral has encountered a problem when processing a request */
+    ADI_CRC_EVENT_ERROR
+} ADI_CRC_EVENT;
+
+#endif  /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */
+
+/**
+ * A device handle used in all API functions to identify a CRC device.
+ * This handle is obtained when opening a CRC driver using adi_crc_Open.
+ * It stops being valid after closing the CRC driver using adi_crc_Close.
+ */
+typedef struct __ADI_CRC_DEVICE*  ADI_CRC_HANDLE;
+
+/**
+ *  CRC driver return codes
+ */
+typedef enum
+{
+    ADI_CRC_SUCCESS = 0,                /*!< 0x00 - Generic success */
+    ADI_CRC_FAILURE,                    /*!< 0x01 - Generic failure */
+    ADI_CRC_IN_USE,                     /*!< 0x02 - Supplied CRC device number is already open and in use */
+    ADI_CRC_INSUFFICIENT_MEMORY,        /*!< 0x03 - Supplied memory is insufficient to operate the CRC device */
+    ADI_CRC_FN_NOT_SUPPORTED,           /*!< 0x04 - Function not supported */
+    ADI_CRC_FN_NOT_PERMITTED,           /*!< 0x05 - Function not permitted at current stage */
+    ADI_CRC_BAD_HANDLE,                 /*!< 0x06 - Bad CRC device handle (can be caused by a CRC device not opened)*/
+    ADI_CRC_BAD_DEVICE_NUMBER,          /*!< 0x07 - There is no CRC device identified by this number */
+    ADI_CRC_INVALID_DMA_CHANNEL,        /*!< 0x08 - Invalid DMA channel assigned to a CRC driver */
+    ADI_CRC_INVALID_PARAMETER,          /*!< 0x09 - Invalid parameter used in a CRC function */
+} ADI_CRC_RESULT;
+
+/*=======  P U B L I C   P R O T O T Y P E S  ========*/
+/*            (globally-scoped functions)             */
+
+/* Opens a CRC device instance */
+ADI_CRC_RESULT adi_crc_Open(
+    uint32_t                    DeviceNum,
+    void                        *pMemory,
+    uint32_t                    MemorySize,
+    ADI_CRC_HANDLE              *phDevice);
+
+/* Closes a CRC device instance */
+ADI_CRC_RESULT adi_crc_Close(
+    ADI_CRC_HANDLE const        hDevice);
+
+/* Registers or unregisters a callback, used by the CRC interrupt handler or with DMA driven operations, with the CRC device */
+ADI_CRC_RESULT adi_crc_RegisterCallback(
+    ADI_CRC_HANDLE const        hDevice,
+    ADI_CALLBACK                pfCallback,
+    void *const                 pCBParam);
+
+/* Sets the 32-bit polynomial for CRC operations */
+ADI_CRC_RESULT adi_crc_SetPolynomialVal(
+    ADI_CRC_HANDLE const        hDevice,
+    uint32_t                    PolynomialVal);
+
+/* Submits data buffer for CRC operation */
+ADI_CRC_RESULT adi_crc_Compute(
+    ADI_CRC_HANDLE const        hDevice,
+    void                        *pCrcBuf,
+    uint32_t                    NumBytes,
+    uint32_t                    NumBits);
+
+/* Gets the current CRC peripheral status */
+ADI_CRC_RESULT adi_crc_IsCrcInProgress(
+    ADI_CRC_HANDLE const        hDevice,
+    bool                        *pbCrcInProgress);
+
+/* Gets the final CRC result computed for a data stream */
+ADI_CRC_RESULT adi_crc_GetFinalCrcVal(
+    ADI_CRC_HANDLE const        hDevice,
+    uint32_t                    *pFinalCrcVal);
+
+/* Gets the current/intermediate CRC result computed for a data stream */
+ADI_CRC_RESULT adi_crc_GetCurrentCrcVal(
+    ADI_CRC_HANDLE const        hDevice,
+    uint32_t                    *pCurrentCrcVal);
+
+ADI_CRC_RESULT  adi_crc_SetBitMirroring(
+    ADI_CRC_HANDLE const        hDevice,
+    const bool                  bEnable);
+
+ADI_CRC_RESULT  adi_crc_SetByteMirroring(
+    ADI_CRC_HANDLE const        hDevice,
+    const bool                  bEnable);
+
+ADI_CRC_RESULT  adi_crc_EnableWordSwap(
+    ADI_CRC_HANDLE const        hDevice,
+    const bool                  bEnable);
+
+ADI_CRC_RESULT adi_crc_SetCrcSeedVal(
+    ADI_CRC_HANDLE const        hDevice,
+    uint32_t                    CrcSeedVal);
+
+ADI_CRC_RESULT  adi_crc_SetLSBFirst(
+    ADI_CRC_HANDLE const        hDevice,
+    const bool                  bEnable);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* ADI_CRC_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/crypto/adi_crypto.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/crypto/adi_crypto.h
new file mode 100755
index 00000000000..54971c2217a
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/crypto/adi_crypto.h
@@ -0,0 +1,235 @@
+/*! *****************************************************************************
+ * @file    adi_crypto.h
+ * @brief   Main include file for CRYPTO Device driver definitions
+ -----------------------------------------------------------------------------
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+
+/** @addtogroup Crypto_Driver Crypto Driver
+*  @{
+*/
+
+#ifndef ADI_CRYPTO_H
+#define ADI_CRYPTO_H
+
+ /*! \cond PRIVATE */
+#include <adi_processor.h>
+#include <adi_callback.h>
+#include <rtos_map/adi_rtos_map.h>  /* for ADI_SEM_SIZE */
+/*! \endcond */
+#include <adi_crypto_config.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * \enum ADI_CRYPTO_RESULT
+ * Crypto API return codes
+ */
+typedef enum
+{
+    ADI_CRYPTO_SUCCESS = 0,              /*!<  No Error, API suceeded.                                   */
+    ADI_CRYPTO_ERR_ALREADY_INITIALIZED,  /*!<  Crypto is already initialized.                            */
+    ADI_CRYPTO_ERR_BAD_BUFFER,           /*!<  Invalid buffer parameters.                                */
+    ADI_CRYPTO_ERR_BAD_CONFIG,           /*!<  Invalid device config parameters passed.                  */
+    ADI_CRYPTO_ERR_BAD_DEVICE_NUM,       /*!<  Invalid device instance number.                           */
+    ADI_CRYPTO_ERR_BAD_DEV_HANDLE,       /*!<  Invalid device handle passed.                             */
+    ADI_CRYPTO_ERR_COMPUTE_ACTIVE,       /*!<  Computation underway.                                     */
+    ADI_CRYPTO_ERR_DMA_BUS_FAULT,        /*!<  Runtime DMA bus fault detected.                           */
+    ADI_CRYPTO_ERR_DMA_INVALID_DESCR,    /*!<  Runtime DMA invalid descriptor detected.                  */
+    ADI_CRYPTO_ERR_DMA_REGISTER,         /*!<  Error registering DMA error callback function.            */
+    ADI_CRYPTO_ERR_DMA_UNKNOWN_ERROR,    /*!<  Unknown runtime DMA error detected.                       */
+    ADI_CRYPTO_ERR_INSUFFICIENT_MEM,     /*!<  Insufficient memory passed to the driver.                 */
+    ADI_CRYPTO_ERR_INVALID_PARAM,        /*!<  Invalid function parameter.                               */
+    ADI_CRYPTO_ERR_INVALID_STATE,        /*!<  Operation failed since the device is in an invalid state. */
+    ADI_CRYPTO_ERR_SEMAPHORE_FAILED,     /*!<  Failure in semaphore functions.                           */
+} ADI_CRYPTO_RESULT;
+
+/*!
+ * \enum ADI_CRYPTO_EVENT
+ * Crypto callback events
+ */
+typedef enum
+{
+    /* successful buffer completion events */
+    ADI_CRYPTO_EVENT_STATUS_CBC_DONE,        /*!<  CBC operation is complete.         */
+    ADI_CRYPTO_EVENT_STATUS_CCM_DONE,        /*!<  CCM operation is complete.         */
+    ADI_CRYPTO_EVENT_STATUS_CMAC_DONE,       /*!<  CMAC operation is complete.        */
+    ADI_CRYPTO_EVENT_STATUS_CTR_DONE,        /*!<  CTR operation is complete.         */
+    ADI_CRYPTO_EVENT_STATUS_ECB_DONE,        /*!<  ECB operation is complete.         */
+    ADI_CRYPTO_EVENT_STATUS_HMAC_DONE,       /*!<  HMAC operation is complete.        */
+    ADI_CRYPTO_EVENT_STATUS_SHA_DONE,        /*!<  SHA operation is complete.         */
+
+    /* other events */
+    ADI_CRYPTO_EVENT_DMA_BUS_ERROR,          /*!<  DMA bus error encountered.         */
+    ADI_CRYPTO_EVENT_DMA_DESCRIPTOR_ERROR,   /*!<  DMA descriptor error encountered.  */
+    ADI_CRYPTO_EVENT_DMA_UNKNOWN_ERROR,      /*!<  DMA unknown error encountered.     */
+    ADI_CRYPTO_EVENT_STATUS_INPUT_OVERFLOW,  /*!<  Input overflow error encountered.  */
+    ADI_CRYPTO_EVENT_STATUS_UNKNOWN,         /*!<  Unknown error encountered.         */
+} ADI_CRYPTO_EVENT;
+
+/*! The amount of application supplied memory used by the CRYPTO driver to store internal state. */
+#define ADI_CRYPTO_MEMORY_SIZE          (88u + ADI_SEM_SIZE)
+
+/*! A device handle used in all API functions to identify the flash device. */
+typedef struct __ADI_CRYPTO_DEV_DATA_TYPE* ADI_CRYPTO_HANDLE;
+
+/*! Number of bytes to allocate for SHA256 hash outputs */
+#define ADI_CRYPTO_SHA_HASH_BYTES        (256u/8u)
+
+/*! Computation mode(Encryption/Decryption) for given buffers */
+typedef enum
+{
+    ADI_CRYPTO_DECODE = (0u << BITP_CRYPT_CFG_ENCR),    /*!< Encoding mode is decryption. */
+    ADI_CRYPTO_ENCODE = (1u << BITP_CRYPT_CFG_ENCR),    /*!< Encoding mode is encryption. */
+} ADI_CRYPTO_CODING_MODE;
+
+/*! Enum for the AES KEY Length */
+typedef enum
+{
+    ADI_CRYPTO_AES_KEY_LEN_128_BIT = (0u << BITP_CRYPT_CFG_AESKEYLEN),     /*!< KEY length is 128 bits. */
+    ADI_CRYPTO_AES_KEY_LEN_256_BIT = (2u << BITP_CRYPT_CFG_AESKEYLEN),     /*!< KEY length is 256 bits. */
+} ADI_CRYPTO_AES_KEY_LEN;
+
+/*! Enable byte swapping for KEY writes */
+typedef enum
+{
+    ADI_CRYPTO_KEY_LITTLE_ENDIAN = (0u << BITP_CRYPT_CFG_KEY_BYTESWAP),    /*!< Do not apply KEY write byte swaps. */
+    ADI_CRYPTO_KEY_BIG_ENDIAN    = (1u << BITP_CRYPT_CFG_KEY_BYTESWAP),    /*!< Apply KEY write byte swaps.        */
+} ADI_CRYPTO_KEY_BYTE_SWAP;
+
+/*! Byte-swap the SHA Input Data */
+typedef enum
+{
+    ADI_CRYPTO_SHA_LITTLE_ENDIAN = (0u << BITP_CRYPT_CFG_SHA_BYTESWAP),    /*!< Do not apply SHA data write byte swaps. */
+    ADI_CRYPTO_SHA_BIG_ENDIAN    = (1u << BITP_CRYPT_CFG_SHA_BYTESWAP),    /*!< Apply SHA data write byte swaps. */
+} ADI_CRYPTO_SHA_BYTE_SWAP;
+
+/*! Byte-swap the AES Input Data */
+typedef enum
+{
+    ADI_CRYPTO_AES_LITTLE_ENDIAN = (0u << BITP_CRYPT_CFG_AES_BYTESWAP),    /*!< Do not apply AES data write byte swaps. */
+    ADI_CRYPTO_AES_BIG_ENDIAN    = (1u << BITP_CRYPT_CFG_AES_BYTESWAP),    /*!< Apply AES data write byte swaps. */
+} ADI_CRYPTO_AES_BYTE_SWAP;
+
+/*!
+ * \enum ADI_CRYPTO_CIPHER_MODE
+ * Enum for the cipher modes.
+ */
+typedef enum {
+    ADI_CRYPTO_MODE_CBC  = BITM_CRYPT_CFG_CBCEN,     /*!< Select CBC cipher mode. */
+    ADI_CRYPTO_MODE_CCM  = BITM_CRYPT_CFG_CCMEN,     /*!< Select CCM cipher mode. */
+    ADI_CRYPTO_MODE_CMAC = BITM_CRYPT_CFG_CMACEN,    /*!< Select CMAC cipher mode. */
+    ADI_CRYPTO_MODE_CTR  = BITM_CRYPT_CFG_CTREN,     /*!< Select CTR cipher mode. */
+    ADI_CRYPTO_MODE_ECB  = BITM_CRYPT_CFG_ECBEN,     /*!< Select ECB cipher mode. */
+    ADI_CRYPTO_MODE_HMAC = BITM_CRYPT_CFG_HMACEN,    /*!< Select HMAC cipher mode. */
+    ADI_CRYPTO_MODE_SHA  = BITM_CRYPT_CFG_SHA256EN,  /*!< Select SHA cipher mode. */
+} ADI_CRYPTO_CIPHER_MODE;
+
+/*! superset user Crypto transaction structure (different elements used for different modes) */
+typedef struct
+{
+    ADI_CRYPTO_CIPHER_MODE    eCipherMode;        /*!< Cipher mode to use */
+    ADI_CRYPTO_CODING_MODE    eCodingMode;        /*!< Coding Mode (Encryption or Decryption) */
+
+    ADI_CRYPTO_KEY_BYTE_SWAP  eKeyByteSwap;       /*!< KEY endianness */
+    ADI_CRYPTO_SHA_BYTE_SWAP  eShaByteSwap;       /*!< SHA endianness */
+    ADI_CRYPTO_AES_BYTE_SWAP  eAesByteSwap;       /*!< AES endianness */
+
+    uint8_t                  *pKey;               /*!< Pointer to the KEY data: pre-formatted as a byte array, according to eAesKeyLen. */
+    ADI_CRYPTO_AES_KEY_LEN    eAesKeyLen;         /*!< The length of the AES KEY */
+
+    uint32_t                 *pAuthData;          /*!< CCM mode: pointer to user prefix buffer */
+    uint32_t                  numAuthBytes;       /*!< Length of the prefix buffer in bytes (should be a multiple of 16 bytes) */
+
+    uint32_t                 *pInputData;         /*!< Pointer to user input data buffer */
+    uint32_t                  numInputBytes;      /*!< Length of the data buffer in bytes (should be a multiple of 16bytes) */
+
+    uint32_t                 *pOutputData;        /*!< Pointer to user output buffer */
+    uint32_t                  numOutputBytes;     /*!< Length of the output buffer in bytes (should be a multiple of 16bytes) */
+
+    uint8_t                  *pNonceIV;           /*!< Pointer to user 16-byte array containing one of three values, depending on cipher mode:\n
+                                                       - CTR mode = 108-bit NONCE\n
+                                                       - CCM mode = 112-bit NONCE\n
+                                                       - CBC mode = 128-bit IV (Initialization Vector)\n\n
+                                                       NONCE and IV assume little endian format, for example: CTR NONCE packing is:\n
+                                                       - NONCE[0]            ->   7:0\n
+                                                       - NONCE[1]            ->  15:8\n
+                                                       -   ...\n
+                                                       - NONCE[13]           -> 103:96\n
+                                                       - NONCE[14](Bits 3:0) -> 107:104\n
+                                                   */
+    uint32_t                  CounterInit;        /*!< CTR/CCM mode: Counter Initialization Value (CTR=20-bit, CCM=16-bit) */
+    uint32_t                  numValidBytes;      /*!< CCM mode: Number of valid bytes in the last (padding) block (1-16) */
+    uint32_t                  numShaBits;         /*!< SHA mode: Number of bits in the SHA payload, which may be odd-sized */
+} ADI_CRYPTO_TRANSACTION;
+
+
+/*================ PUBLIC API ==================*/
+
+
+ADI_CRYPTO_RESULT adi_crypto_Open                  (uint32_t const nDeviceNum, void * const pMemory, uint32_t const nMemorySize, ADI_CRYPTO_HANDLE * const phDevice);
+ADI_CRYPTO_RESULT adi_crypto_Close                 (ADI_CRYPTO_HANDLE const hDevice);
+ADI_CRYPTO_RESULT adi_crypto_RegisterCallback      (ADI_CRYPTO_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void * const pCBParam);
+ADI_CRYPTO_RESULT adi_crypto_Enable                (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable);
+
+ADI_CRYPTO_RESULT adi_crypto_SubmitBuffer          (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_TRANSACTION * const pBuffer);
+ADI_CRYPTO_RESULT adi_crypto_GetBuffer             (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_TRANSACTION ** const ppBuffer);
+ADI_CRYPTO_RESULT adi_crypto_IsBufferAvailable     (ADI_CRYPTO_HANDLE const hDevice, bool * const pbAvailable);
+
+#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1)
+ADI_CRYPTO_RESULT adi_crypto_EnableDmaMode         (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable);
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* include guard */
+
+/*
+** EOF
+*/
+
+/*@}*/
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/dma/adi_dma.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/dma/adi_dma.h
new file mode 100755
index 00000000000..63c3bb2cf9c
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/dma/adi_dma.h
@@ -0,0 +1,274 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_dma.h
+ * @brief:   DMA Device Definitions for ADuCxxx
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ADI_DMA_MODE_PING_PONG
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/*! \addtogroup DMA_Driver DMA Driver
+ *  @{
+ *  @brief DMA Driver
+ *  @details This driver is intended to be used only by the device drivers and not by the application.
+ *  @note The device drivers must include drivers/dma/adi_dma.h to use this driver     
+ */
+
+#ifndef ADI_DMA__H__
+#define ADI_DMA__H__
+
+#include <adi_callback.h>
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*=============  D E F I N E S  =============*/
+/*! Amount of memory(In bytes) required by the DMA manager for managing the operation
+ *  This memory is completely owned by the driver till the end of the operation.
+ */
+
+/*============= D A T A T Y P E S =============*/
+
+
+/*!
+ * Dma Data Increments
+ */
+typedef enum
+{
+    ADI_DMA_INCR_1_BYTE    = 0x00u,     /*!< Byte increment */
+    ADI_DMA_INCR_2_BYTE    = 0x01u,     /*!< Half word increment */
+    ADI_DMA_INCR_4_BYTE    = 0x02u,     /*!< Word increment */
+    ADI_DMA_INCR_NONE      = 0x03u,     /*!< No increment */
+
+    ADI_DMA_DECR_1_BYTE    = 0x10u,     /*!< Byte decrement */
+    ADI_DMA_DECR_2_BYTE    = 0x11u,     /*!< Half word decrement */
+    ADI_DMA_DECR_4_BYTE    = 0x12u      /*!< Word decrement */
+
+} ADI_DMA_INCR_TYPE;
+
+/*!
+ *  DMA Callback Events
+ */
+typedef enum
+{
+    ADI_DMA_EVENT_BUFFER_PROCESSED,          /*!< Buffer processed event */
+    ADI_DMA_EVENT_ERR_BUS,                   /*!< Bus Error Occurred Event */
+    ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR     /*!< Invalid Descriptor Event */
+} ADI_DMA_EVENT;
+
+
+/*!
+ * Dma Data Widths
+ */
+typedef enum
+{
+    ADI_DMA_WIDTH_1_BYTE      = 0x0,      /*!<  8-bit */
+    ADI_DMA_WIDTH_2_BYTE      = 0x1,      /*!< 16-bit */
+    ADI_DMA_WIDTH_4_BYTE      = 0x2       /*!< 32-bit */
+} ADI_DMA_WIDTH_TYPE;
+
+
+/*!
+ * Dma Rearbitration Intervals (chunk size between bus arbitrations)
+ */
+typedef enum
+{
+    ADI_DMA_RPOWER_1 = 0,                       /*!< Rearbitrate after    1 transfer */
+    ADI_DMA_RPOWER_2,                           /*!< Rearbitrate after    2 transfers */
+    ADI_DMA_RPOWER_4,                           /*!< Rearbitrate after    4 transfers */
+    ADI_DMA_RPOWER_8,                           /*!< Rearbitrate after    8 transfers */
+    ADI_DMA_RPOWER_16,                          /*!< Rearbitrate after   16 transfers */
+    ADI_DMA_RPOWER_32,                          /*!< Rearbitrate after   32 transfers */
+    ADI_DMA_RPOWER_64,                          /*!< Rearbitrate after   64 transfers */
+    ADI_DMA_RPOWER_128,                         /*!< Rearbitrate after  128 transfers */
+    ADI_DMA_RPOWER_256,                         /*!< Rearbitrate after  256 transfers */
+    ADI_DMA_RPOWER_512,                         /*!< Rearbitrate after  512 transfers */
+    ADI_DMA_RPOWER_1024                         /*!< Rearbitrate after 1024 transfers */
+} ADI_DMA_RPOWER;
+
+
+/*!
+ * Dma Transfer Modes
+ */
+typedef enum
+{
+    ADI_DMA_MODE_BASIC,                         /*!< Basic mode */
+    ADI_DMA_MODE_AUTO,                          /*!< Auto request mode */
+    ADI_DMA_MODE_PING_PONG,                     /*!< Ping pong mode */
+    ADI_DMA_MODE_MSG,                           /*!< Memory Scatter gather mode (not valid as no Memory DMA support) */
+    ADI_DMA_MODE_PSG                            /*!< Peripheral Scatter mode */
+} ADI_DMA_MODE;
+
+
+/*!
+ * Dma Channel Priority Settings (only HIGH or DEFAULT priority supported)
+ */
+typedef enum
+{
+    ADI_DMA_PRIORITY_DEFAULT = 0,                       /*!< Use DEFAULT channel priority */
+    ADI_DMA_PRIORITY_HIGH                              /*!< Elevate channel to HIGH priority */
+} ADI_DMA_PRIORITY;
+
+
+/*!
+ * Result Event Type
+ */
+typedef enum {
+    ADI_DMA_SUCCESS,                    /*!< Successfully Completed */
+    ADI_DMA_ERR_NOT_INITIALIZED,        /*!< DMA not initialized */
+    ADI_DMA_ERR_INVALID_PARAMETER,      /*!< Input parameter to the function is invalid */
+} ADI_DMA_RESULT;
+
+/*! \cond PRIVATE*/
+/*!
+ * \enum DMA_CHANn_TypeDef
+ * DMA Channel Assignments
+ */
+typedef enum
+{
+    SPI2_TX_CHANn       =  0,  /*!< SPI2 Transmit DMA channel                */
+    SPI2_RX_CHANn       =  1,  /*!< SPI2 Receive DMA channel                 */
+    SPORT0A_CHANn       =  2,  /*!< SPORT0-A  DMA channel                    */
+    SPORT0B_CHANn       =  3,  /*!< SPORT0-B  DMA channel                    */
+    SPI0_TX_CHANn       =  4,  /*!< SPI0 Transmit DMA channel                */
+    SPI0_RX_CHANn       =  5,  /*!< SPI0 Receive DMA channel                 */
+    SPI1_TX_CHANn       =  6,  /*!< SPI1 Transmit DMA channel                */
+    SPI1_RX_CHANn       =  7,  /*!< SPI1 Receive DMA channel                 */
+    UART0_TX_CHANn      =  8,  /*!< UART0 Transmit DMA channel               */
+    UART0_RX_CHANn      =  9,  /*!< UART0 Receive DMA channel                */
+    I2CS_TX_CHANn       = 10,  /*!< I2C Slave Transmit DMA channel           */
+    I2CS_RX_CHANn       = 11,  /*!< I2C Slave Receive DMA channel            */
+    I2CM_CHANn          = 12,  /*!< I2C Master DMA channel                   */
+    AES0_IN_CHANn       = 13,  /*!< AES0-IN DMA channel                      */
+    AES0_OUT_CHANn      = 14,  /*!< AES0-OUT DMA channel                     */
+    FLASH_CHANn         = 15,  /*!< FLASH DMA channel                        */
+    SIP0_CHANn          = 16,  /*!< SIP-0 DMA channel                        */
+    SIP1_CHANn          = 17,  /*!< SIP-1 DMA channel                        */
+    SIP2_CHANn          = 18,  /*!< SIP-2 DMA channel                        */
+    SIP3_CHANn          = 19,  /*!< SIP-3 DMA channel                        */
+    SIP4_CHANn          = 20,  /*!< SIP-4 DMA channel                        */
+    SIP5_CHANn          = 21,  /*!< SIP-5 DMA channel                        */
+    SIP6_CHANn          = 22,  /*!< SIP-6 DMA channel                        */
+    SIP7_CHANn          = 23,  /*!< SIP-7 DMA channel                        */
+    ADC0_CHANn          = 24,  /*!< ADC0  DMA channel                        */
+    UART1_TX_CHANn      = 25,  /*!< UART1 Transmit DMA channel               */
+    UART1_RX_CHANn      = 26,  /*!< UART1 Receive DMA channel                */
+    NUM_DMA_CHANNELSn   = 27   /*!< Total Number of DMA channels             */
+} DMA_CHANn_TypeDef;  /** typedef name for fixed DMA channel assignments */
+/*! \endcond */
+
+/*!
+ * \struct ADI_DCC_TypeDef
+ * DMA Channel Control MMR Access Template
+ */
+typedef struct
+{
+    __IO uint32_t DMASRCEND;      /*!< Source End Pointer                    */
+    __IO uint32_t DMADSTEND;      /*!< Destination End Pointer               */
+    __IO uint32_t DMACDC;         /*!< Channel Data Configuration            */
+         uint32_t RESERVED;       /*!< Address gap filler                    */
+} ADI_DCC_TypeDef;
+
+
+/*! \cond PRIVATE  */
+/* Bit Position for DMA Descriptor Control */
+#define DMA_BITP_CTL_DST_INC         (30u)
+#define DMA_BITP_CTL_SRC_INC         (26u)
+#define DMA_BITP_CTL_SRC_SIZE        (24u)
+#define DMA_BITP_CTL_R_POWER         (14u)
+#define DMA_BITP_CTL_N_MINUS_1        (4u)
+#define DMA_BITP_CTL_CYCLE_CTL        (0u)
+
+/* Bit Mask for DMA Descriptor Control */
+#define DMA_BITM_CTL_DST_INC         ((0x00000003u) << DMA_BITP_CTL_DST_INC)
+#define DMA_BITM_CTL_SRC_INC         ((0x00000003u) << DMA_BITP_CTL_SRC_INC)
+#define DMA_BITM_CTL_SRC_SIZE        ((0x00000003u) << DMA_BITP_CTL_SRC_SIZE)
+#define DMA_BITM_CTL_R_POWER         ((0x0000000Fu) << DMA_BITP_CTL_R_POWER)
+#define DMA_BITM_CTL_N_MINUS_1       ((0x000003FFu) << DMA_BITP_CTL_N_MINUS_1)
+#define DMA_BITM_CTL_CYCLE_CTL       ((0x00000007u) << DMA_BITP_CTL_CYCLE_CTL)
+
+/* Enum for the DMA Descriptor Cycle Control */
+#define DMA_ENUM_CTL_CYCLE_CTL_INVALID     (0u)
+#define DMA_ENUM_CTL_CYCLE_CTL_BASIC       (1u)
+#define DMA_ENUM_CTL_CYCLE_CTL_AUTO_REQ    (2u)
+#define DMA_ENUM_CTL_CYCLE_CTL_PING_PONG   (3u)
+#define DMA_ENUM_CTL_CYCLE_CTL_MSG_PRI     (4u)
+#define DMA_ENUM_CTL_CYCLE_CTL_MSG_ALT     (5u)
+#define DMA_ENUM_CTL_CYCLE_CTL_PSG_PRI     (6u)
+#define DMA_ENUM_CTL_CYCLE_CTL_PSG_ALT     (7u)
+
+
+#define DMA_BITM_INCR_TYPE_DECR            (0x10u)
+
+#define DMA_BITM_OCTL_SRC_DECR             (0x01u)
+#define DMA_BITM_OCTL_DST_DECR             (0x02u)
+
+#define DMA_BITM_OCTL_SRC_INCR             (0x04u)
+#define DMA_BITM_OCTL_DST_INCR             (0x08u)
+
+#define DMA_TRANSFER_LIMIT      (1024u) /*!< Maximum number of transfers handled by the DMA in one request */
+
+/* pointer to the primary CCD array */
+extern ADI_DCC_TypeDef* const pPrimaryCCD;
+/* pointer to the alternate CCD array */
+extern ADI_DCC_TypeDef* const pAlternateCCD;
+/*! \endcond  */
+/*==========  DMA API DECLARATIONS  ==========*/
+
+extern void adi_dma_Init(void);
+
+extern ADI_DMA_RESULT adi_dma_RegisterCallback (
+    DMA_CHANn_TypeDef   const eChannelID,
+    ADI_CALLBACK        const pfCallback,
+    void*               const pCBParam
+    );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* include guard */
+
+/*
+** EOF
+*/
+
+/**@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/flash/adi_flash.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/flash/adi_flash.h
new file mode 100755
index 00000000000..c72524e3e4d
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/flash/adi_flash.h
@@ -0,0 +1,185 @@
+/*!
+ *****************************************************************************
+ @file:    adi_flash.h
+ @brief:   Flash device driver definitions
+ @date:    $Date: 2016-07-05 00:49:46 -0400 (Tue, 05 Jul 2016) $
+ -----------------------------------------------------------------------------
+Copyright (c) 2012-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+/*! @addtogroup Flash_Driver Flash Driver
+ *  @{
+ */
+
+#ifndef ADI_FLASH_H
+#define ADI_FLASH_H
+
+ /*! \cond PRIVATE */
+#include <adi_processor.h>
+#include <adi_callback.h>
+#include <rtos_map/adi_rtos_map.h>  /* for ADI_SEM_SIZE */
+/*! \endcond */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * \enum ADI_FEE_RESULT
+ * Flash Controller return codes.
+ */
+ typedef enum {
+    ADI_FEE_SUCCESS = 0,                /*!< The function completed successfully.               */
+    ADI_FEE_ERR_ALIGNMENT,              /*!< The flash write source data pointer is misaligned. */
+    ADI_FEE_ERR_ALREADY_INITIALIZED,    /*!< The flash device driver is already initialized.    */
+    ADI_FEE_ERR_BAD_DEVICE_NUM,         /*!< Device number passed is invalid.                   */
+    ADI_FEE_ERR_BUFFER_ERR,             /*!< An error occurred while processing a write buffer. */
+    ADI_FEE_ERR_DEVICE_BUSY,            /*!< The device is busy.                                */
+    ADI_FEE_ERR_DMA_BUS_FAULT,          /*!< Runtime DMA bus fault detected.                    */
+    ADI_FEE_ERR_DMA_INVALID_DESCR,      /*!< Runtime DMA invalid descriptor detected.           */
+    ADI_FEE_ERR_DMA_REGISTER,           /*!< Error registering DMA error callback function.     */
+    ADI_FEE_ERR_DMA_UNKNOWN_ERROR,      /*!< Unknown runtime DMA error detected.                */
+    ADI_FEE_ERR_HW_ERROR_DETECTED,      /*!< An FEE hardware error occurred (pHwErrors param).  */
+    ADI_FEE_ERR_INSUFFICIENT_MEM,       /*!< The memory passed is undersized.                   */
+    ADI_FEE_ERR_INVALID_HANDLE,         /*!< Device Handle is invalid.                          */
+    ADI_FEE_ERR_INVALID_PARAM,          /*!< A function parameter is invalid.                   */
+    ADI_FEE_ERR_NO_DATA_TO_TRANSFER,    /*!< No transfer data detected.                         */
+    ADI_FEE_ERR_TRANSFER_IN_PROGRESS,   /*!< Operation already in progress.                     */
+    ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY, /*!< Unmatched read/write vs. submit/get API call.      */
+    ADI_FEE_ERR_SEMAPHORE_FAILED,       /*!< An semaphore operation failed.                     */
+ } ADI_FEE_RESULT;
+
+
+/*! A device handle used in all API functions to identify the flash device. */
+typedef struct __ADI_FEE_DEV_DATA_TYPE* ADI_FEE_HANDLE;
+
+
+/*! Applications use the "ADI_FEE_MEMORY_SIZE" macro to allocate
+    required flash driver memory.  This memory (and size) are passed
+    to the flash driver during the "adi_fee_Open()" driver initialization
+    call.  This memory is used to store internal flash driver state.
+*/
+#define ADI_FEE_MEMORY_SIZE            (44u + ADI_SEM_SIZE)
+
+
+/*!
+ * \enum ADI_FEE_CALLBACK_EVENT
+ * Enum for the callback events.
+ */
+typedef enum {
+     ADI_FEE_CALLBACK_EVENT_BUFFER_PROCESSED,    /*!< Buffer processed successfully event. */
+     ADI_FEE_CALLBACK_EVENT_DEVICE_ERROR,        /*!< Device error(s) detected during command. */
+} ADI_FEE_CALLBACK_EVENT;
+
+/*!
+ * \enum ADI_FEE_ECC_EVENT_TYPE
+ * Enum for the Error-Correction-Code event type.
+ */
+typedef enum {
+    ADI_FEE_ECC_EVENT_TYPE_ERROR,       /*!< ECC Error Event. */
+    ADI_FEE_ECC_EVENT_TYPE_CORRECT      /*!< ECC correction event. */
+} ADI_FEE_ECC_EVENT_TYPE;
+
+/*!
+ * \enum ADI_FEE_ECC_RESPONSE
+ * Error-Correction-Code configuration codes.
+ */
+typedef enum {
+    ADI_FEE_ECC_RESPONSE_NONE       = 0x0,      /*!< No Response. */
+    ADI_FEE_ECC_RESPONSE_BUS_ERROR  = 0x1,      /*!< Generate a Bus Error. */
+    ADI_FEE_ECC_RESPONSE_IRQ        = 0x2       /*!< Generate an IRQ. */
+} ADI_FEE_ECC_RESPONSE;
+
+
+/*!
+ * \struct ADI_FEE_TRANSACTION
+ * Flash write data transaction block.
+ */
+typedef struct {
+    uint32_t   *pWriteAddr;  /*!< Pointer to flash-space (destination) write location. */
+    uint32_t   *pWriteData;  /*!< Pointer to user-space (source) write Data.          */
+    uint32_t    nSize;       /*!< Write data size (in bytes).                          */
+    bool        bUseDma;     /*!< DMA flag controlling use of DMA or not.              */
+} ADI_FEE_TRANSACTION;
+
+
+/*================ E X T E R N A L S ==================*/
+/* Flash Controller API */
+
+ADI_FEE_RESULT adi_fee_Open              (uint32_t const nDeviceNum, void* const pMemory, uint32_t const nMemorySize, ADI_FEE_HANDLE* const phDevice);
+ADI_FEE_RESULT adi_fee_Close             (ADI_FEE_HANDLE const hDevice);
+ADI_FEE_RESULT adi_fee_RegisterCallback  (ADI_FEE_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void* const pCBParam);
+
+ADI_FEE_RESULT adi_fee_PageErase         (ADI_FEE_HANDLE const hDevice, uint32_t const nPageNumStart, uint32_t const nPageNumEnd, uint32_t* const pHwErrors);
+ADI_FEE_RESULT adi_fee_MassErase         (ADI_FEE_HANDLE const hDevice, uint32_t* const pHwErrors);
+
+ADI_FEE_RESULT adi_fee_Write             (ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION* const pTransaction, uint32_t* const pHwErrors);
+ADI_FEE_RESULT adi_fee_SubmitBuffer      (ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION* const pTransaction);
+
+ADI_FEE_RESULT adi_fee_IsBufferAvailable (ADI_FEE_HANDLE const hDevice, bool* const pbCompletionState);
+ADI_FEE_RESULT adi_fee_GetBuffer         (ADI_FEE_HANDLE const hDevice, uint32_t* const pHwErrors);
+
+ADI_FEE_RESULT adi_fee_GetPageNumber     (ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t* const pnPageNum);
+ADI_FEE_RESULT adi_fee_GetBlockNumber    (ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t* const pnBlockNum);
+
+ADI_FEE_RESULT adi_fee_VerifySignature   (ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, uint32_t const nEndPage, uint32_t* const pSigResult, uint32_t* const pHwErrors);
+ADI_FEE_RESULT adi_fee_WriteProtectBlock (ADI_FEE_HANDLE const hDevice, uint32_t const  nBlockNum);
+
+ADI_FEE_RESULT adi_fee_Sleep             (ADI_FEE_HANDLE const hDevice, bool const bSleep);
+ADI_FEE_RESULT adi_fee_Abort             (ADI_FEE_HANDLE const hDevice);
+ADI_FEE_RESULT adi_fee_GetAbortAddr      (ADI_FEE_HANDLE const hDevice, uint32_t* const pnAddress);
+
+ADI_FEE_RESULT adi_fee_ConfigECC         (ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, bool const bInfoECCEnable);
+ADI_FEE_RESULT adi_fee_EnableECC         (ADI_FEE_HANDLE const hDevice, bool const bEnable);
+ADI_FEE_RESULT adi_fee_ConfigECCEvents   (ADI_FEE_HANDLE const hDevice, ADI_FEE_ECC_EVENT_TYPE const eEvent, ADI_FEE_ECC_RESPONSE const eResponse);
+ADI_FEE_RESULT adi_fee_GetECCErrAddr     (ADI_FEE_HANDLE const hDevice, uint32_t* const pnAddress);
+ADI_FEE_RESULT adi_fee_GetECCCorrections (ADI_FEE_HANDLE const hDevice, uint32_t* const pnNumCorrections);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* include guard */
+
+/*
+** EOF
+*/
+
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_data_transfer.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_data_transfer.h
new file mode 100755
index 00000000000..89ab88d841e
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_data_transfer.h
@@ -0,0 +1,127 @@
+/*! ****************************************************************************
+ * @file    adi_data_transfer.h
+ * @brief   General data transfer types for drivers
+ * @details General data transfer types for drivers
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef ADI_DATA_TRANSFER_H
+#define ADI_DATA_TRANSFER_H
+
+/*=============  I N C L U D E S   =============*/
+
+#include <stdint.h>                             /* defines types such as uint32_t*/
+#include <rtos_map/adi_rtos_map.h>              /* needed for SEM_VAR_DECLR declaration */
+
+/*! \cond PRIVATE */
+/** @addtogroup Data_Transfer Common Data Transfer Structures
+*  @{
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*==============  D E F I N E S  ===============*/
+
+#define ADI_DT_BUFNUM   (2u)                    /*!< Number of buffers available for data transfers in each communication channel */
+
+/*!
+ *******************************************************************************
+ * \struct ADI_DT_BUFF_INFO
+ *  Structure for managing buffers submitted to drivers.
+ ******************************************************************************/
+struct _ADI_DT_BUFF_INFO;
+
+/*!
+ *******************************************************************************
+ *  Structure for managing buffers submitted to drivers.
+ ******************************************************************************/
+typedef struct _ADI_DT_BUFF_INFO
+{
+    void *                      pStartAddress;  /*!< Address of buffer passed down a driver.            */
+    uint32_t                    nCount;         /*!< Size of buffer in bytes.                           */
+    uint32_t                    nIndex;         /*!< Position of first byte to be transmitted.          */
+    bool                        bInUse;         /*!< Buffer in use flag.                                */
+    bool                        bDMA;           /*!< Transaction is using the DMA flag.                 */
+    struct _ADI_DT_BUFF_INFO *  pNextBuffer;    /*!< Pointer to the next buffer in the list.            */
+} ADI_DT_BUFF_INFO;
+
+/*!
+ *******************************************************************************
+ *  Enumeration of different data transfer modes supported by drivers.
+ ******************************************************************************/
+typedef enum _ADI_DT_MODE
+{
+    ADI_DT_MODE_NONE,           /*!< Mode of data transfer is not selected. */ 
+    ADI_DT_MODE_BLOCKING,       /*!< Only calls to adi_xxx_Read or adi_xxx_Write are allowed for transferring data. */
+    ADI_DT_MODE_NONBLOCKING     /*!< Only calls to adi_xxx_SubmitBuffer are allowed for transferring data. */
+} ADI_DT_MODE;
+
+typedef void * ADI_DEVICE_HANDLE;               /*!< Generic device handle */
+
+/*!
+ *******************************************************************************
+ *  Structure for managing pool of buffers submitted to drivers.
+ ******************************************************************************/
+typedef struct
+{
+    ADI_DT_BUFF_INFO    BufInfo[ADI_DT_BUFNUM]; /*!< Ping Pong Buffers.                                             */
+    ADI_DT_BUFF_INFO *  pFreeBuffer;            /*!< Pointer to free buffer. (Next buffer to submit).               */
+    ADI_DT_BUFF_INFO *  pFillBuffer;            /*!< Pointer to the next buffer to be filled. (Needed for the case
+                                                     where many buffers are "submitted" before a "get" is called.)  */
+    ADI_DT_BUFF_INFO *  pActiveBuffer;          /*!< Pointer to active buffer. (Next buffer waiting for completion.)*/
+    ADI_DT_MODE         eDataTranferMode;       /*!< Data transfer mode (blocking or non-blockig).                  */
+
+    SEM_VAR_DECLR
+} ADI_DT_CHANNEL;
+
+
+/*=============  P U B L I C   F U N C T I O N S =============*/
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+/*! \endcond */
+
+#endif /* ADI_DATA_TRANSFER_H */
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_drivers_general.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_drivers_general.h
new file mode 100755
index 00000000000..e6f8571f1b4
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_drivers_general.h
@@ -0,0 +1,98 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_drivers_general.h
+ * @brief:   Macros and types used in multiple drivers
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+#ifndef ADI_DRIVERS_GENERAL__H
+#define ADI_DRIVERS_GENERAL__H
+
+
+/* Macros related to alignment in the different toolchains supported */
+
+/* 
+ * These macros are designed to be used as follows:
+ * ADI_ALIGNED_PRAGMA(<required_alignment>)
+ * <variable_declaration> ADI_ALIGNED_ATTRIBUTE(<required_alignment>)
+ */
+
+#if defined ( __ICCARM__ )
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+*
+* Pm120 (rule 19.10): In the definition of a function-like macro each parameter
+*                     shall be enclosed in parenthesis. 
+*                     This is not possible in attributes and pragmas
+* Pm154 (rule 19.13): The # and ## preprocessor operators shall not be used.
+*                     We need to do this to abstract the macros for the 
+*                     different toolchains
+*/
+#pragma diag_suppress=Pm120,Pm154
+#endif
+
+#define PRAGMA(x) _Pragma(#x)
+#define ATTRIBUTE(x) __attribute__((x))
+
+#if defined (__GNUC__)
+  /* Gcc uses attributes */
+  #define ADI_ALIGNED_PRAGMA(num)
+  #define ADI_ALIGNED_ATTRIBUTE(num) ATTRIBUTE(aligned(num))
+  #define ADI_UNUSED_ATTRIBUTE ATTRIBUTE(unused)
+#elif defined ( __ICCARM__ )
+  /* IAR uses a pragma */
+  #define ADI_ALIGNED_ATTRIBUTE(num)
+  #define ADI_ALIGNED_PRAGMA(num) PRAGMA(data_alignment=num) 
+  #define ADI_UNUSED_ATTRIBUTE
+#elif defined (__ARMCC_VERSION)
+  /* Keil uses a decorator which is placed in the same position as pragmas */
+  #define ADI_ALIGNED_ATTRIBUTE(num)
+  #define ADI_ALIGNED_PRAGMA(num) __attribute__((aligned(num)))
+  #define ADI_UNUSED_ATTRIBUTE ATTRIBUTE(unused)
+#else
+#error "Toolchain not supported"
+#endif
+
+
+#if defined ( __ICCARM__ )
+#pragma diag_default=Pm120,Pm154
+#endif
+#endif /* ADI_DRIVERS_GENERAL__H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/gpio/adi_gpio.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/gpio/adi_gpio.h
new file mode 100755
index 00000000000..ad0673a2b50
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/gpio/adi_gpio.h
@@ -0,0 +1,174 @@
+/*
+ *****************************************************************************
+   @file:    adi_gpio.h
+   @brief:   GPIO definitions and API
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#ifndef ADI_GPIO_H
+#define ADI_GPIO_H
+
+#include <adi_processor.h>
+#include <adi_callback.h>
+
+#ifdef __ICCARM__
+/* IAR MISRA C 2004 error suppressions.
+ *
+ * Pm008 (rule 2.4): sections of code should not be 'commented out'.
+ *   Allow code example in doxygen comment.
+ * Pm011 (rule 6.3): The basic types of char, int, long, float cannot be used.
+ *   bool is used in the APIs as it is not affending the rule. Disabling this as IAR treats it as an error.
+ */
+#pragma diag_suppress=Pm008,Pm011
+#endif /* __ICCARM__ */
+
+/*! \addtogroup GPIO_Driver GPIO Driver
+ *  @{
+ */
+
+#ifdef __ICCARM__
+#pragma diag_default=Pm008
+#endif /* __ICCARM__ */
+
+/* C++ linkage */
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*! Amount of memory(in bytes) required by the GPIO device driver for its operation.
+ * This memory is completely owned by the driver till the end of the operation.
+ */
+#define ADI_GPIO_MEMORY_SIZE        (16u)
+
+/* typedefs for 16-bit Ports */
+typedef uint16_t ADI_GPIO_DATA;    /*!< pin data reg type */
+
+
+/*! GPIO API function return codes */
+typedef enum
+{
+    ADI_GPIO_SUCCESS = 0,                   /*!< No error detected. */
+    ADI_GPIO_FAILURE,                       /*!< The API call failed. */
+    ADI_GPIO_ALREADY_INITIALIZED,           /*!< GPIO device has already been initialized. */
+    ADI_GPIO_NOT_INITIALIZED,               /*!< GPIO device has not yet been initialized. */
+    ADI_GPIO_NULL_PARAMETER,                /*!< The given pointer is pointing to NULL. */
+    ADI_GPIO_INVALID_MEMORY_SIZE,           /*!< The given memory is not sufficient to operate the driver. */
+    ADI_GPIO_INVALID_PINS,                  /*!< Invalid pin combination. */
+    ADI_GPIO_INVALID_INTERRUPT,             /*!< Invalid interrupt number. */
+    ADI_GPIO_INVALID_TRIGGER,               /*!< Invalid trigger condition. */
+} ADI_GPIO_RESULT;
+
+
+/*! GPIO trigger condition enumerations */
+typedef enum {
+    ADI_GPIO_IRQ_RISING_EDGE    =(0x0),     /*!< Trigger an interrupt on a rising edge.    */
+    ADI_GPIO_IRQ_FALLING_EDGE   =(0x1),     /*!< Trigger an interrupt on a falling edge.   */
+    ADI_GPIO_IRQ_EITHER_EDGE    =(0x2),     /*!< Trigger an interrupt on either edge.      */
+    ADI_GPIO_IRQ_HIGH_LEVEL     =(0x3),     /*!< Trigger an interrupt on a high level.     */
+    ADI_GPIO_IRQ_LOW_LEVEL      =(0x4)      /*!< Trigger an interrupt on a low level.      */
+} ADI_GPIO_IRQ_TRIGGER_CONDITION;
+
+/*! GPIO IRQ enumeration */
+typedef enum {
+    ADI_GPIO_INTA_IRQ = SYS_GPIO_INTA_IRQn, /*!< GPIO Group Interrupt A.    */
+    ADI_GPIO_INTB_IRQ = SYS_GPIO_INTB_IRQn, /*!< GPIO Group Interrupt B.   */
+} ADI_GPIO_IRQ;
+
+
+/*! GPIO port enumerations */
+typedef enum {
+    ADI_GPIO_PORT0,      /*!< Port 0 */
+    ADI_GPIO_PORT1,      /*!< Port 1 */
+    ADI_GPIO_PORT2,      /*!< Port 2 */
+    ADI_GPIO_PORT3,      /*!< Port 3 */
+    ADI_GPIO_NUM_PORTS   /*!< maximum number of ports */
+} ADI_GPIO_PORT;
+
+/* 16-bit port pin defs */
+#define ADI_GPIO_PIN_0      ((ADI_GPIO_DATA)(0x0001)) /*!< Pin 0 */
+#define ADI_GPIO_PIN_1      ((ADI_GPIO_DATA)(0x0002)) /*!< Pin 1 */
+#define ADI_GPIO_PIN_2      ((ADI_GPIO_DATA)(0x0004)) /*!< Pin 2 */
+#define ADI_GPIO_PIN_3      ((ADI_GPIO_DATA)(0x0008)) /*!< Pin 3 */
+#define ADI_GPIO_PIN_4      ((ADI_GPIO_DATA)(0x0010)) /*!< Pin 4 */
+#define ADI_GPIO_PIN_5      ((ADI_GPIO_DATA)(0x0020)) /*!< Pin 5 */
+#define ADI_GPIO_PIN_6      ((ADI_GPIO_DATA)(0x0040)) /*!< Pin 6 */
+#define ADI_GPIO_PIN_7      ((ADI_GPIO_DATA)(0x0080)) /*!< Pin 7 */
+#define ADI_GPIO_PIN_8      ((ADI_GPIO_DATA)(0x0100)) /*!< Pin 8 */
+#define ADI_GPIO_PIN_9      ((ADI_GPIO_DATA)(0x0200)) /*!< Pin 9 */
+#define ADI_GPIO_PIN_10     ((ADI_GPIO_DATA)(0x0400)) /*!< Pin 10 */
+#define ADI_GPIO_PIN_11     ((ADI_GPIO_DATA)(0x0800)) /*!< Pin 11 */
+#define ADI_GPIO_PIN_12     ((ADI_GPIO_DATA)(0x1000)) /*!< Pin 12 */
+#define ADI_GPIO_PIN_13     ((ADI_GPIO_DATA)(0x2000)) /*!< Pin 13 */
+#define ADI_GPIO_PIN_14     ((ADI_GPIO_DATA)(0x4000)) /*!< Pin 14 */
+#define ADI_GPIO_PIN_15     ((ADI_GPIO_DATA)(0x8000)) /*!< Pin 15 */
+
+/* GPIO port pins availability mask */
+#define ADI_GPIO_PORT0_PIN_AVL    (0xFFFFu)           /*!< Port 0 pin mask (16 pins)*/
+#define ADI_GPIO_PORT1_PIN_AVL    (0xFFFFu)           /*!< Port 1 pin mask (16 pins)*/
+#define ADI_GPIO_PORT2_PIN_AVL    (0xFFFFu)           /*!< Port 2 pin mask (16 pins)*/
+#define ADI_GPIO_PORT3_PIN_AVL    (0x000Fu)           /*!< Port 2 pin mask (4 pins) */
+
+
+/* GPIO API functions */
+ADI_GPIO_RESULT  adi_gpio_Init                      (void* const pMemory, uint32_t const MemorySize);
+ADI_GPIO_RESULT  adi_gpio_UnInit                    (void);
+ADI_GPIO_RESULT  adi_gpio_RegisterCallback          (const ADI_GPIO_IRQ eIrq, ADI_CALLBACK const pfCallback, void *const pCBParam );
+ADI_GPIO_RESULT  adi_gpio_SetGroupInterruptPins     (const ADI_GPIO_PORT Port, const ADI_GPIO_IRQ eIrq, const ADI_GPIO_DATA Pins);
+ADI_GPIO_RESULT  adi_gpio_SetGroupInterruptPolarity (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins);
+ADI_GPIO_RESULT  adi_gpio_OutputEnable              (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag);
+ADI_GPIO_RESULT  adi_gpio_InputEnable               (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag);
+ADI_GPIO_RESULT  adi_gpio_PullUpEnable              (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag);
+ADI_GPIO_RESULT  adi_gpio_SetHigh                   (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins);
+ADI_GPIO_RESULT  adi_gpio_SetLow                    (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins);
+ADI_GPIO_RESULT  adi_gpio_Toggle                    (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins);
+ADI_GPIO_RESULT  adi_gpio_SetData                   (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins);
+ADI_GPIO_RESULT  adi_gpio_GetData                   (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, uint16_t* const pValue);
+
+#if defined (__ICCARM__)
+#pragma diag_default=Pm011
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+
+#endif /* ADI_GPIO_V1_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/i2c/adi_i2c.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/i2c/adi_i2c.h
new file mode 100755
index 00000000000..edd398f3f9b
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/i2c/adi_i2c.h
@@ -0,0 +1,243 @@
+/*!
+ *****************************************************************************
+ @file:    adi_i2c.h
+ @brief:   I2C device driver definitions
+ @details  This is the primary header file for the I2C driver, which contains the
+           API declarations, data and constant definitions used in the APIs.
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+
+#ifndef ADI_I2C_H
+#define ADI_I2C_H
+
+ /*! \cond PRIVATE */
+#include <adi_processor.h>
+#include <rtos_map/adi_rtos_map.h>  /* for ADI_SEM_SIZE */
+/*! \endcond */
+
+
+/** @addtogroup I2C_Driver I2C Driver
+ *  @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (__ICCARM__)
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm011 (rule 6.3): Types which specify sign and size should be used
+*   We use bool which is accepted by MISRA but the toolchain does not accept it
+*
+*/
+#pragma diag_suppress=Pm011
+
+#endif
+
+/*!
+ *****************************************************************************
+ * \enum ADI_I2C_RESULT
+ *
+ * I2C Device Error Codes.  #ADI_I2C_SUCCESS is always zero
+ * The return value of all I2C APIs returning #ADI_I2C_RESULT
+ * should always be tested at the application level for success or failure.
+ * Specific I2C bus error conditions are returned as elements of
+ * #ADI_I2C_RESULT.
+ *
+ *****************************************************************************/
+typedef enum
+{
+    ADI_I2C_SUCCESS = 0,                         /*!< The API call succeeded.                                  */
+    ADI_I2C_BAD_BITRATE,                         /*!< The bit rate is invalid.                                 */
+    ADI_I2C_BAD_DEVICE_HANDLE,                   /*!< The device handle is invalid.                            */
+    ADI_I2C_BAD_DEVICE_NUMBER,                   /*!< The device number is invalid.                            */
+    ADI_I2C_BAD_SYS_CLOCK,                       /*!< Unable to obtain system clock rate.                      */
+    ADI_I2C_DEVICE_IN_USE,                       /*!< The device is in use.                                    */
+    ADI_I2C_DEVICE_NOT_OPEN,                     /*!< The device is not open.                                  */
+    ADI_I2C_FAILURE,                             /*!< Generic API failure code.                                */
+    ADI_I2C_HW_ERROR_DETECTED,                   /*!< An I2C hardware error occurred.  See #ADI_I2C_HW_ERRORS. */
+    ADI_I2C_INSUFFICIENT_MEMORY,                 /*!< The application supplied memory size is insufficient.    */
+    ADI_I2C_INVALID_PARAMETER,                   /*!< An invalid parameter is passed to the function.          */
+    ADI_I2C_INVALID_SLAVE_ADDRESS,               /*!< The application supplied slave address is too wide.      */
+    ADI_I2C_INVALID_SUBMIT_API,                  /*!< Unmatched read/write vs. submit/get API call.            */
+    ADI_I2C_SEMAPHORE_FAILED                     /*!< Semaphore operation failed.                              */
+
+} ADI_I2C_RESULT;
+
+
+/*!
+ *****************************************************************************
+ * \enum ADI_I2C_HW_ERRORS
+ *
+ * I2C Device Hardware Error Codes.  Contains one or more hardware (I2C protocol)
+ * errors.  Use this enum to decode hardware errors when the main #ADI_I2C_RESULT
+ * return result value is #ADI_I2C_HW_ERROR_DETECTED.
+ *
+ *****************************************************************************/
+typedef enum
+{
+    ADI_I2C_HW_ERROR_NONE             = 0,         /*!< No hardware error.                                       */
+    ADI_I2C_HW_ERROR_NACK_ADDR        = 0x0001,    /*!< A no-acknowledgement occurred for the address.           */
+    ADI_I2C_HW_ERROR_NACK_DATA        = 0x0002,    /*!< A no-acknowledgement occurred for the data.              */
+    ADI_I2C_HW_ERROR_ARBITRATION_LOST = 0x0004,    /*!< I2C bus arbitration was Lost.                            */
+    ADI_I2C_HW_ERROR_UNEXPECTED_ERROR = 0x0008,    /*!< An unexpected error occurred.                            */
+
+} ADI_I2C_HW_ERRORS;
+
+
+/*! A device handle used in all API functions to identify the I2C device. */
+typedef struct __ADI_I2C_DEV_DATA_TYPE* ADI_I2C_HANDLE;
+
+/*! Use macro "ADI_I2C_MEMORY_SIZE" to know how much memory to
+   provide the i2c driver during the "adi_i2c_Open()" driver
+   initialization call.  This memory is used to store internal
+   driver state data.  Use map file to verify.
+*/
+#define ADI_I2C_MEMORY_SIZE (44u + ADI_SEM_SIZE)
+
+
+/*!
+  * \struct ADI_I2C_TRANSACTION
+  *****************************************************************************
+  * I2C Device Command/Data Transaction Structure.  This is the called-provided
+  * data structure used by the blocking #adi_i2c_ReadWrite() and non-blocking
+  * #adi_i2c_SubmitBuffer() calls to describe the caller's transaction parameters,
+  * consisting of prologue data and size (the addressing phase), transmit/receive
+  * data pointer and size (the data phase), and various transaction control parameters.
+  *
+  * Each transaction may optionally be prefaced with a prologue block, which may
+  * describe a read/write memory/register address, a slave-specific command, or
+  * some other slave-specific protocol that may precede the actual read/write
+  * data.  Set the prologue size to zero if no prologue is desired.
+  *
+  * Each call to #adi_i2c_ReadWrite or #adi_i2c_SubmitBuffer() must populate the
+  * following fields of the ADI_I2C_TRANSACTION block:
+  *
+  * @par pPrologue
+  * Byte pointer to an application-supplied prologue byte array. If the value is
+  * zero, prologue data is ignored.
+  *
+  * @par nPrologueSize
+  * The number of prologue bytes to be transmitted ahead of the data phase. If the
+  * value is zero, prologue data is ignored.
+  *
+  * @par pData
+  * Byte pointer to the application-supplied data byte array.  This buffer is
+  * either the source or destination address of the data being transmitted or
+  * received, respectively.
+  *
+  * @par nDataSize
+  * The number of data bytes to be transmitted or received during the data phase.
+  * If the value is zero, the data phase is ignored.
+  *
+  * @par bReadNotWrite
+  * Direction control for data phase.  If "true", data phase is a read (from
+  * the slave), if "false", data phase is a write (to the slave).  Pertains only
+  * to the data phase.  Any prologue data (addressing/command phase) is always
+  * transmitted (written to the slave) prior to the data phase.
+  *
+  * @par bRepeatStart
+  * Controls suppression of a Stop Condition between the addressing phase and the
+  * data phase of an I2C transaction.  After the prologue (if present), a
+  * unidirectional data stream (I2C is a half-duplex protocol) is either
+  * transmitted or received (depending on the transfer direction).  Frequently, a
+  * Repeat-Start Condition (in reality, just the absence of a Stop Condition
+  * following the prologue/addressing phase) is required between the addressing
+  * phase (prologue) and the data phase of a transaction to meet slave device
+  * protocol requirements.  The Repeat-Start requirement can be driven by the
+  * slave device communications protocol, or simply to just prevent any other
+  * I2C master from rearbitrating the bus between the prologue (addressing) and
+  * data phases of a so-called "COMBINED FORMAT" (write-followed-by-read).
+  * When bRepeatStart is set "true", the usual Stop Condition between the addressing
+  * phase and the data phase is suppressed and the I2C bus controller issues a
+  * second Start Condition (Repeat-Start) for the data phase.  Without
+  * Repeat-Start (bRepeatStart "false"), the addressing phase ends with a normal
+  * Stop Condition ahead of the data phase.  Repeat-Start conditions are used
+  * when "turning the bus around" as in writing a read address (for example),
+  * immediately followed by a data stream from that read address... without
+  * releasing bus arbitration.
+  *
+  *****************************************************************************/
+typedef struct {
+    uint8_t    *pPrologue;      /*!< Prologue pointer.                      */
+    uint16_t    nPrologueSize;  /*!< Prologue byte count.                   */
+    uint8_t    *pData;          /*!< Data pointer.                          */
+    uint16_t    nDataSize;      /*!< Data byte count.                       */
+    bool        bReadNotWrite;  /*!< Read/write flag.                       */
+    bool        bRepeatStart;   /*!< Repeat start flag.                     */
+} ADI_I2C_TRANSACTION;
+
+
+/*! Maximum supported bitrate is "FAST" mode (400 kHz). */
+#define ADI_I2C_MAX_RATE (400000u)
+
+/***************************************************************
+ * Eliminable user API that may be optimized out by the linker *
+ ***************************************************************/
+ADI_I2C_RESULT  adi_i2c_Open               (uint32_t const DeviceNum, void* const pMemory, uint32_t const MemorySize, ADI_I2C_HANDLE* const phDevice);
+ADI_I2C_RESULT  adi_i2c_Close              (ADI_I2C_HANDLE const hDevice);
+
+/* blocking calls... */
+ADI_I2C_RESULT  adi_i2c_ReadWrite          (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction, uint32_t* const pHwErrors);
+
+/* non-blocking calls... */
+ADI_I2C_RESULT  adi_i2c_SubmitBuffer       (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction);
+ADI_I2C_RESULT  adi_i2c_IsBufferAvailable  (ADI_I2C_HANDLE const hDevice, bool* const pbCompletionState);
+ADI_I2C_RESULT  adi_i2c_GetBuffer          (ADI_I2C_HANDLE const hDevice, uint32_t* const pHwErrors);
+
+/* other (blocking) calls... */
+ADI_I2C_RESULT  adi_i2c_Reset              (ADI_I2C_HANDLE const hDevice);
+ADI_I2C_RESULT  adi_i2c_SetBitRate         (ADI_I2C_HANDLE const hDevice, uint32_t const requestedBitRate32);
+ADI_I2C_RESULT  adi_i2c_SetSlaveAddress    (ADI_I2C_HANDLE const hDevice, uint16_t const SlaveAddress);
+ADI_I2C_RESULT  adi_i2c_IssueGeneralCall   (ADI_I2C_HANDLE const hDevice, uint8_t* const pData, uint8_t const nDataSize, uint32_t* const pHwErrors);
+
+
+#if defined (__ICCARM__)
+#pragma diag_default=Pm011
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+
+#endif /* ADI_I2C_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/pwr/adi_pwr.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/pwr/adi_pwr.h
new file mode 100755
index 00000000000..1bb8f41467f
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/pwr/adi_pwr.h
@@ -0,0 +1,689 @@
+/*
+ *****************************************************************************
+ * @file:    adi_pwr.h
+ * @brief:   System clock and power management driver.
+ *-----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+
+/*! \addtogroup Power_Driver Power Driver
+ *  @{
+ */
+
+#ifndef ADI_PWR_H
+#define ADI_PWR_H
+
+#include <adi_callback.h>
+#include <adi_processor.h>
+
+#ifdef __ICCARM__
+/* IAR MISRA C 2004 error suppressions.
+ *
+ * Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters.
+ *   IAR compiler supports longer identifiers.
+ * Pm011 (rule 6.3): The basic types of char, int, long, float cannot be used.
+ *   bool is used in the APIs as it is not affending the rule. Disabling this as IAR treats it as an error. 
+ */
+#pragma diag_suppress=Pm009,Pm011
+#endif /* __ICCARM__ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+   
+/*! Enumeration of clock sources for various peripherals. */
+typedef enum {
+    /*! Source for all peripherals SPI, SPORT, SIP, CRC, AES, SIP interface, I2C, UART, optionally for timers. */  
+    ADI_CLOCK_PCLK,    
+    /*! Source for Core,Bus etc. */    
+    ADI_CLOCK_HCLK,
+    /*! Source for the ADC. */
+    ADI_CLOCK_ACLK
+    
+} ADI_CLOCK_ID;
+
+/*! Enumeration of input clock sources */
+typedef enum {
+   /*! Clock ID for 16 MHz or 26 MHz external crystal oscillator called  HFXTAL. */    
+    ADI_CLOCK_SOURCE_HFXTAL,
+   /*! Clock ID 32 kHz external crystal oscillator called  LFXTAL. */
+    ADI_CLOCK_SOURCE_LFXTAL,
+   /*! Clock ID for 26 MHz internal oscillator called  HFOSC. */
+    ADI_CLOCK_SOURCE_HFOSC,
+   /*! Clock ID 32 kHz a 32 kHz internal oscillator called  LFXTAL. */
+    ADI_CLOCK_SOURCE_LFOSC,
+   /*! Clock ID for output clock for System PLL. */
+    ADI_CLOCK_SOURCE_SPLL,
+   /*! Clock ID for external clock from GPIO. */               
+    ADI_CLOCK_SOURCE_GPIO
+} ADI_CLOCK_SOURCE_ID;
+
+
+/*! 
+ * Enumeration of clock sources for each clock multiplexer.
+ * The processor has the following clock multiplexers.
+ * - SPLL Mux (System PLL).
+ * - Reference clock Mux.
+ * - Root Clock Mux.
+ */
+typedef enum  {
+
+    /*! Input clock for  system PLL mux is HFOSC. */
+    ADI_CLOCK_MUX_SPLL_HFOSC, 
+    /*! Input clock for  system PLL mux is HFXTAL. */
+    ADI_CLOCK_MUX_SPLL_HFXTAL,
+    /*! Input clock for  system PLL mux is provided through GPIO. */
+    ADI_CLOCK_MUX_SPLL_GPIO,
+    
+    /*! Input clock for  low frequency clock mux is LFOSC. */
+    ADI_CLOCK_MUX_LFCLK_LFOSC,
+    /*! Input clock for  low frequency clock mux is LFXTAL. */    
+    ADI_CLOCK_MUX_LFCLK_LFXTAL,
+
+    /*! Input clock to the multiplexer which provides reference clock for Flash 
+      and HPBUCK clock is HFOSC. */
+    ADI_CLOCK_MUX_REF_HFOSC_CLK,  
+    /*! Reserved. */
+    ADI_CLOCK_MUX_REF_RESERVED,    
+    /*! Input clock to the multiplexer which provides reference clock for Flash 
+      and HPBUCK clock is 26 MHz HFXTAL. */
+    ADI_CLOCK_MUX_REF_HFXTAL_26MHZ_CLK,
+    /*! Input clock to the multiplexer which provides reference clock for Flash 
+      and HPBUCK clock is 16 MHz HFXTAL. */
+    ADI_CLOCK_MUX_REF_HFXTAL_16MHZ_CLK,
+    
+    /*! Input clock to root multiplexer is HFOSC. */                                            
+    ADI_CLOCK_MUX_ROOT_HFOSC,
+    /*! Input clock to root multiplexer is HFXTAL. */                                                
+    ADI_CLOCK_MUX_ROOT_HFXTAL,
+    /*! Input clock to root multiplexer is SPLL. */                                                
+    ADI_CLOCK_MUX_ROOT_SPLL,
+    /*! Input clock to root multiplexer is from GPIO. */                                                
+    ADI_CLOCK_MUX_ROOT_GPIO
+    
+} ADI_CLOCK_MUX_ID;
+
+
+/*! 
+ * Enumeration of clock source status. 
+ */
+typedef enum {
+    /*! Specified clock source is disabled. */
+    ADI_CLOCK_SOURCE_DISABLED = 0,
+    /*! Specified clock source is not stable. */    
+    ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE,
+    /*! Specified clock source is enabled and  stable. */        
+    ADI_CLOCK_SOURCE_ENABLED_STABLE,
+    /*! Invalid clock ID. */
+    ADI_CLOCK_SOURCE_ID_NOT_VALID
+    
+} ADI_CLOCK_SOURCE_STATUS;
+
+/*! Clock output options through GPIO pin.
+    The GPIO clock output pin can be driven through one of these clocks.
+*/
+typedef enum
+{
+    /*! Root Clock (ROOT_CLK). */
+    ADI_CLOCK_OUTPUT_ROOT_CLK,
+    
+    /*! Low Frequency Clock (LF_CLK). */
+    ADI_CLOCK_OUTPUT_LF_CLK,
+    
+    /*! ADC Clock (ACLK). */
+    ADI_CLOCK_OUTPUT_ACLK,
+    
+    /*! HCLK_BUS. */
+    ADI_CLOCK_OUTPUT_HCLK_BUS,
+    
+    /*! HCLK_CORE. */
+    ADI_CLOCK_OUTPUT_HCLK_CORE,
+    
+    /*! Peripheral Clock (PCLK). */
+    ADI_CLOCK_OUTPUT_PCLK,
+    
+    /*! Reference Clock for Flash controller timer (RCLK). */
+    ADI_CLOCK_OUTPUT_RCLK,
+    
+    /*! Mux of HFOSC, HFXTAL clock (RHP_CLK). */
+    ADI_CLOCK_OUTPUT_RHP_CLK,
+    
+    /*! GP Timer 0 clock (GPT0_CLK). */
+    ADI_CLOCK_OUTPUT_GPT0_CLK,
+    
+    /*! GP Timer 1 clock (GPT1_CLK). */
+    ADI_CLOCK_OUTPUT_GPT1_CLK,
+    
+    /*! Peripherals operating at HCLK (HCLK_P). */
+    ADI_CLOCK_OUTPUT_HCLK_PERIPHERAL,
+    
+    /*! PLL Clock out. */
+    ADI_CLOCK_OUTPUT_PLL_OUTPUT,
+    
+    /*! RTC0 Clock. */
+    ADI_CLOCK_OUTPUT_RTC0_CLK,
+    
+    /*! HP Buck Clock (HPBUCK_CLK). */
+    ADI_CLOCK_OUTPUT_HPBUCK_CLK,
+    
+    /*! HP Buck Non overlap clock. */
+    ADI_CLOCK_OUTPUT_HPBUCK_NO_OVERLAP_CLK,
+    
+    /*! RTC1 generated clock. */
+    ADI_CLOCK_OUTPUT_RTC1_CLK
+    
+}ADI_CLOCK_OUTPUT_ID;
+ 
+
+/*! Enumeration of clock gates using which the clocks can be gated. */
+typedef enum {
+    /*! Clock Gate for the GP Timer-0. */    
+    ADI_CLOCK_GATE_GPT0_CLK     = 1 << BITP_CLKG_CLK_CTL5_GPTCLK0OFF,
+    /*! Clock Gate for the GP Timer-1. */        
+    ADI_CLOCK_GATE_GPT1_CLK     = 1 << BITP_CLKG_CLK_CTL5_GPTCLK1OFF,
+    /*! Clock Gate for the GP Timer-2. */        
+    ADI_CLOCK_GATE_GPT2_CLK     = 1 << BITP_CLKG_CLK_CTL5_GPTCLK2OFF,
+    /*! Clock Gate for the I2C. */        
+    ADI_CLOCK_GATE_I2C_CLK      = 1 << BITP_CLKG_CLK_CTL5_UCLKI2COFF,
+    /*! Clock Gate for the GPIO. */        
+    ADI_CLOCK_GATE_GPIO_CLK     = 1 << BITP_CLKG_CLK_CTL5_GPIOCLKOFF,    
+    /*! Clock Gate for the PCLK. */                
+    ADI_CLOCK_GATE_PCLK         = 1 << BITP_CLKG_CLK_CTL5_PERCLKOFF, 
+    /*! Clock Gate for the RGB Timer. */                
+    ADI_CLOCK_GATE_TMR_RGB_CLK  = 1 << BITP_CLKG_CLK_CTL5_TMRRGBCLKOFF 
+
+} ADI_CLOCK_GATE;
+
+/*!
+ *  Enumeration of HF oscillator clock divide factor.
+ */
+typedef enum 
+{
+    /*! Divide by 1. */
+    ADI_PWR_HFOSC_DIV_BY_1,
+    /*! Divide by 2. */
+    ADI_PWR_HFOSC_DIV_BY_2,
+    /*! Divide by 4. */
+    ADI_PWR_HFOSC_DIV_BY_4,
+    /*! Divide by 8. */
+    ADI_PWR_HFOSC_DIV_BY_8,
+    /*! Divide by 16. */
+    ADI_PWR_HFOSC_DIV_BY_16,
+    /*! Divide by 32. */
+    ADI_PWR_HFOSC_DIV_BY_32
+
+} ADI_PWR_HFOSC_DIV;
+
+ /*!
+ *****************************************************************************
+ * Power driver API return codes
+ *****************************************************************************/
+typedef enum
+{
+    /*! No error detected.                                    */  
+    ADI_PWR_SUCCESS = 0,              
+    /*! Generic unknown error occurred.                       */    
+    ADI_PWR_FAILURE,                  
+    /*! If the given pointer is pointing to NULL.             */    
+    ADI_PWR_NULL_POINTER,                  
+    /*! Requested divide value is out of range.               */    
+    ADI_PWR_INVALID_CLOCK_DIVIDER,    
+    /*! Invalid ADI_CLOCK_ID specified.                       */    
+    ADI_PWR_INVALID_CLOCK_ID,         
+    /*! PDIV:HDIV ratio must be integral.                     */    
+    ADI_PWR_INVALID_CLOCK_RATIO,      
+    /*! Invalid low-power mode requested.                     */    
+    ADI_PWR_INVALID_POWER_MODE,       
+    /*! Invalid clock speed.                                  */    
+    ADI_PWR_INVALID_CLOCK_SPEED,      
+    /*! Specified operation is not allowed.                   */    
+    ADI_PWR_OPERATION_NOT_ALLOWED,
+    /*! Parameter is out of range.                            */    
+    ADI_PWR_INVALID_PARAM,   
+    /*! System not initialized, call the API SystemInit.      */
+    ADI_PWR_SYSTEM_NOT_INITIALIZED
+    
+} ADI_PWR_RESULT;
+
+/*!
+ *   Enumeration of the power modes supported by the processor.
+ */
+typedef enum
+{
+    /*! Core Sleep power-down mode. */    
+    ADI_PWR_MODE_FLEXI          = 0 << BITP_PMG_PWRMOD_MODE,      
+    /*! Fully Active. (piggy-back on bitmode value "1", normally reserved) */    
+    ADI_PWR_MODE_ACTIVE         = 1 << BITP_PMG_PWRMOD_MODE,  
+    /*! Full Hibernate power-down mode. */    
+    ADI_PWR_MODE_HIBERNATE      = 2 << BITP_PMG_PWRMOD_MODE,        
+    /*! System Sleep power-down mode. */    
+    ADI_PWR_MODE_SHUTDOWN       = 3 << BITP_PMG_PWRMOD_MODE
+    
+} ADI_PWR_POWER_MODE;
+
+
+/*!
+ *   Enumeration of power management interrupts.
+ */
+typedef enum
+{
+    /*! Interrupt when battery voltage drops below 1.8V.*/    
+    ADI_PWR_LOW_BATTERY_VOLTAGE_IEN     = 1 << BITP_PMG_IEN_VBAT,       
+    /*! Interrupt when VREG under-voltage: below 1V. */    
+    ADI_PWR_UNDER_VOLATAGE_IEN          = 1 << BITP_PMG_IEN_VREGUNDR,   
+    /*! Interrupt when VREG over-voltage: over- 1.32V. */    
+    ADI_PWR_OVER_VOLATAGE_IEN           = 1 << BITP_PMG_IEN_VREGOVR,    
+    /*! Interrupt when battery voltage falls to the specified range.Please see #adi_pwr_SetVoltageRange.*/     
+    ADI_PWR_BATTERY_VOLTAGE_RANGE_IEN   = 1 << BITP_PMG_IEN_IENBAT
+    
+} ADI_PWR_PMG_IRQ;
+
+
+/*!
+ *   Enumeration of system clock module interrupts.
+ */
+typedef enum
+{
+    /*! Interrupt for root clock monitor and Clock Fail. */
+    ADI_PWR_ROOT_CLOCK_MON_IEN      = 1 << BITP_CLKG_OSC_CTL_ROOT_MON_EN,
+    /*! Interrupt for LFXTAL clock monitor and Clock Fail. */
+    ADI_PWR_LFXTAL_CLOCK_MON_IEN    = 1 << BITP_CLKG_OSC_CTL_LFX_MON_EN,
+    /*! Interrupt when LFXTAL clock becomes stable/unstable. */
+    ADI_PWR_LFXTAL_STATUS_IEN       = 1 << BITP_CLKG_CLK_CTL0_LFXTALIE,
+    /*! Interrupt when HFXTAL clock becomes stable/unstable. */     
+    ADI_PWR_HFXTAL_STATUS_IEN       = 1 << BITP_CLKG_CLK_CTL0_HFXTALIE,
+    /*! Interrupt when PLL-LOCK/PLL-UNLOCK.  */
+    ADI_PWR_PLL_STATUS_IEN          = 1 << BITP_CLKG_CLK_CTL3_SPLLIE
+      
+} ADI_PWR_CLOCK_IRQ;
+
+/**
+ * Enumeration of the power driver events notified through the callback.
+ */
+typedef enum 
+{
+    /*! Event for indicating Over voltage VREG  > 1.32v. */    
+    ADI_PWR_EVENT_VREG_OVER_VOLTAGE,            
+    /*! Event for indicating  under voltage VREG < 1V. */    
+    ADI_PWR_EVENT_VREG_UNDER_VOLTAGE,           
+    
+    /*! Event for indicating battery voltage below  1.8V. */
+    ADI_PWR_EVENT_BATTERY_VOLTAGE_LOW,
+    /*! Event for indicating battery voltage in specified range-1.VBAT range1 (> 2.75v). */ 
+    ADI_PWR_EVENT_BATTERY_VOLTAGE_RANGE_1,
+    /*! Event for indicating battery voltage in specified range-2.VBAT range2 (2.75v - 2.3v).   */    
+    ADI_PWR_EVENT_BATTERY_VOLTAGE_RANGE_2,
+    /*! Event for indicating battery voltage in specified range-3.VBAT range3 (2.3v - 1.6v).   */    
+    ADI_PWR_EVENT_BATTERY_VOLTAGE_RANGE_3,
+
+    /*! Event to indicate that LFXTAL failed and hardware automatically switched to LFOSC. */
+    ADI_PWR_EVENT_OSC_LFXTAL_AUTO_SWITCH,
+    /*! Event to indicate the LFXTAL clock is not stable. */
+    ADI_PWR_EVENT_OSC_LFXTAL_MON_FAIL,
+    /*! Event to indicate the Root clock is not stable. */
+    ADI_PWR_EVENT_OSC_ROOT_CLOCK_MON_FAIL,
+    /*! Event to indicate the Root clock failed and hardware automatically switched to HFOSC. */
+    ADI_PWR_EVENT_OSC_ROOT_CLOCK_FAIL_AUTO_SWITCH,
+ 
+    /*! Event to indicate HF crystal stable. */    
+    ADI_PWR_EVENT_OSC_HFXTAL_CLOCK_OK,
+    /*! Event to indicate HF crystal is not stable. */    
+    ADI_PWR_EVENT_OSC_HFXTAL_CLOCK_NO_OK,
+    /*! Event to indicate LF crystal is  stable. */    
+    ADI_PWR_EVENT_OSC_LFXTAL_CLOCK_OK,
+    /*! Event to indicate LF crystal is not stable. */    
+    ADI_PWR_EVENT_OSC_LFXTAL_CLOCK_NO_OK,
+    /*! Event for indicating PLL is locked. */    
+
+    ADI_PWR_EVENT_PLLC_LOCK,
+    /*! Event for indicating PLL is unlocked.  */    
+    ADI_PWR_EVENT_PLLC_UNLOCK
+    
+} ADI_PWR_EVENT;
+
+
+/*!
+ *   Enumeration of processor wake up status. 
+*/
+typedef enum
+{
+    /*! Interrupt from External Interrupt 0. */    
+    ADI_PWR_INT_EXT0,    
+    /*! Interrupt from External Interrupt 1. */    
+    ADI_PWR_INT_EXT1,    
+    /*! Interrupt from External Interrupt 2. */        
+    ADI_PWR_INT_EXT2,   
+    /*! Interrupt from RTC. */
+    ADI_PWR_INT_RTC     
+      
+} ADI_PWR_WAKEUP_STATUS;
+
+/*!
+ *   Enumeration of the battery voltage ranges for voltage monitoring interrupt generation.
+*/
+typedef enum
+{
+    /*! Voltage range is in safe region.  */
+    ADI_PWR_BAT_VOLTAGE_RANGE_SAFE,     
+    /*! Battery voltage is in the range of 2.2 to 2.75 V. */    
+    ADI_PWR_VOLTAGE_RANGE_2_2_TO_2_75,  
+    /*! Battery voltage is in the range of 1.6 to 2.2 V.  */        
+    ADI_PWR_VOLTAGE_RANGE_1_6_TO_2_2    
+} ADI_PWR_VOLTAGE_RANGE;
+
+/*!
+ *  Enumeration of LFXTAL Robust Mode Load select. The amount of loading tolerated when 
+ *  LFXTAL robust mode is selected, that is when LFXTAL robust mode is enabled.
+ */
+typedef enum
+{
+    /*! No Trim, and big resistive loads not tolerated. */
+    ADI_PWR_LFXTAL_LOAD_NONE,
+    /*! 20 MOHM Load mode, greater than 20 MOHM load allowed. */
+    ADI_PWR_LFXTAL_LOAD_20MOHM,
+    /*! 10 MOHM Load mode, greater than 10 MOHM load allowed. */
+    ADI_PWR_LFXTAL_LOAD_10MOHM,
+    /*! 5 MOHM load resistance allowed on both IO pins, the user can scale the current 
+        down if the load is expected to be smaller than 5 MOHM. */
+    ADI_PWR_LFXTAL_LOAD_5MOHM
+    
+}ADI_PWR_LFXTAL_LOAD;
+
+/*!
+* Enumeration of HP Buck load modes. The modes can be used to choose the loading capability 
+* of the HPBUCK. The low load mode and high load mode are based on the loading in the system.
+*/
+typedef enum
+{
+    /*! HPBUCK Low load mode.  This mode can be set if the maximum system clock(HCLK) frequency 
+        is 26 MHz. */   
+    ADI_PWR_HPBUCK_LD_MODE_LOW,
+    
+    /*! HPBUCK High load mode. This mode can be set if the  system clock(HCLK) frequency is greater 
+        than 26 MHz. */
+    ADI_PWR_HPBUCK_LD_MODE_HIGH
+    
+}ADI_PWR_HPBUCK_LD_MODE;
+
+/*  Related clock APIs */
+
+/* 
+ * Initialize the dynamic power management service 
+ */
+ADI_PWR_RESULT  adi_pwr_Init(void);
+
+/* 
+ * =================================================================
+ *  Clock Management related  APIs 
+ * =================================================================
+*/
+
+/*
+ *  Update the internal clock variable based on current configuration 
+ */
+ADI_PWR_RESULT adi_pwr_UpdateCoreClock(void);
+
+/* 
+ * Set the external clock frequency.
+ */
+ADI_PWR_RESULT adi_pwr_SetExtClkFreq(
+               const uint32_t ExtClkFreq
+               );
+
+/* 
+ * To Configure the root clock muxing 
+ */
+ADI_PWR_RESULT adi_pwr_SetRootClockMux(
+               const ADI_CLOCK_MUX_ID eClockID
+               );
+
+/*
+ * To Configure the root clock muxing 
+ */
+ADI_PWR_RESULT adi_pwr_SetPLLClockMux(
+               const ADI_CLOCK_MUX_ID eClockID
+               );
+
+/*
+ *  To Configure the root clock muxing 
+ */
+ADI_PWR_RESULT adi_pwr_SetLFClockMux(
+               const ADI_CLOCK_MUX_ID eClockID
+               );
+
+               
+/*
+ * To Enable/Disable the LFXTAL robust mode.
+ */
+ADI_PWR_RESULT adi_pwr_EnableLFXTALRobustMode(
+                const bool  bEnable
+                );
+
+/*
+ * To configure the LFXTAL robust mode load.
+ */
+ADI_PWR_RESULT adi_pwr_SetLFXTALRobustModeLoad(
+                const ADI_PWR_LFXTAL_LOAD eLoad
+                );
+
+/*
+ * To Enable/Disable the LFXTAL Fail Auto switch.
+ */
+ADI_PWR_RESULT adi_pwr_EnableLFXTALFailAutoSwitch(
+                const bool  bEnable
+                );                
+
+/*
+ *  To enable/disable auto switching of root clock to HFOSC upon detection
+ *  of Root clock failure.
+ */ 
+ADI_PWR_RESULT adi_pwr_EnableRootClockFailAutoSwitch(
+               const bool bEnable
+               );
+
+/*
+ *  To set the HF Oscillator divide factor
+ */ 
+ADI_PWR_RESULT adi_pwr_SetHFOscDivFactor(
+               const ADI_PWR_HFOSC_DIV    eDivFactor
+               );
+
+/*
+ *  To set the HF oscillator automatic divide by 1 during wakeup from Flexi mode
+ */ 
+ADI_PWR_RESULT adi_pwr_EnableHFOscAutoDivBy1(
+               const bool   bEnable
+               );
+               
+/* 
+ * To Configure the reference clock muxing 
+ */
+ADI_PWR_RESULT adi_pwr_SetRefClockMux(
+               const ADI_CLOCK_MUX_ID eClockID
+               );
+
+/*
+ *  Get external clock frequency. 
+ */
+ADI_PWR_RESULT adi_pwr_GetExtClkFreq(
+               uint32_t *pExtClock
+               );
+
+/* 
+ * Get current clock frequency. This API can be used to know PCLK, HCLK. 
+ */
+ADI_PWR_RESULT adi_pwr_GetClockFrequency(
+               const ADI_CLOCK_ID eClockId,
+               uint32_t *pClock
+               );
+/* 
+ * To enable/disable the specific clock. 
+ */
+ADI_PWR_RESULT adi_pwr_EnableClock(
+               const ADI_CLOCK_GATE eClockGate, 
+               const bool bEnable
+               );
+
+/* 
+ * To enable/disable the specific clock source. 
+ */
+ADI_PWR_RESULT adi_pwr_EnableClockSource(
+               const ADI_CLOCK_SOURCE_ID eClockSource, 
+               const bool bEnable
+               );
+/* 
+ * To set the specific clock divider. 
+*/
+ADI_PWR_RESULT adi_pwr_SetClockDivider(
+               const ADI_CLOCK_ID eClockId,
+               const uint16_t nDiv
+               );
+/* 
+ * To Get the clock status. 
+*/
+ADI_PWR_RESULT adi_pwr_GetClockStatus(
+               const ADI_CLOCK_SOURCE_ID eClockSource,
+               ADI_CLOCK_SOURCE_STATUS *peStatus
+               );
+/* 
+ * To configure the PLL to generate the SPLL
+*/
+ADI_PWR_RESULT adi_pwr_SetPll(
+                uint8_t  nDivFactor, 
+                const uint8_t  nMulFactor, 
+                const bool bDiv2,
+                const bool bMul2
+                );
+                
+/* To enable the interrupt for clock monitoring LFXTAL/HFXTAL/PLL.*/
+ADI_PWR_RESULT adi_pwr_EnableClockInterrupt(
+                const ADI_PWR_CLOCK_IRQ eIrq, 
+                const bool bEnable
+                );
+
+/* Enabling the LFXTAL bypass mode */
+ADI_PWR_RESULT  adi_pwr_EnableLFXTALBypass(
+                const bool bEnable
+                );
+
+
+/* Set the clock output through the GPIO */
+ADI_PWR_RESULT  adi_pwr_SetGPIOClockOutput(
+                const ADI_CLOCK_OUTPUT_ID eClockOutput
+                );
+                
+/* 
+ * =================================================================
+ *  Power Management related  APIs 
+ * =================================================================
+*/
+/* To enable the interrupt for voltage monitoring.*/
+ADI_PWR_RESULT adi_pwr_EnablePMGInterrupt(
+                const ADI_PWR_PMG_IRQ eIrq, 
+                const bool bEnable
+                );
+
+/*
+ * To know which is interrupt caused the processor to wake up from SHUTDOWN mode.
+ */
+ADI_PWR_RESULT adi_pwr_GetWakeUpStatus(
+               ADI_PWR_WAKEUP_STATUS *peStatus
+               );
+
+/*
+ * To select the voltage range of the battery for monitoring.
+*/
+ADI_PWR_RESULT adi_pwr_SetVoltageRange(
+               const ADI_PWR_VOLTAGE_RANGE eRange
+               );
+
+/*
+ *  For entering the low power mode.
+*/
+ADI_PWR_RESULT adi_pwr_EnterLowPowerMode(
+                const ADI_PWR_POWER_MODE PowerMode,
+                uint32_t volatile *        pnInterruptOccurred,
+                const uint8_t            PriorityMask
+                );
+
+/*
+ *  For exiting the low power mode.
+*/
+ADI_PWR_RESULT adi_pwr_ExitLowPowerMode(
+                uint32_t volatile *  pnInterruptOccurred
+                );
+
+/* To enable the HPBUCK */
+ADI_PWR_RESULT adi_pwr_EnableHPBuck(
+               const bool bEnable
+               );
+               
+
+/* To enable the HPBUCK Low Power mode */
+ADI_PWR_RESULT adi_pwr_EnableHPBuckLowPowerMode(
+               const bool bEnable
+               );
+               
+/* To enable the HPBUCK Load mode */
+ADI_PWR_RESULT adi_pwr_SetHPBuckLoadMode(
+               const ADI_PWR_HPBUCK_LD_MODE   eLoadMode
+               );
+               
+/* 
+ * For registering the call back function .
+*/
+ADI_PWR_RESULT adi_pwr_RegisterCallback(
+               const ADI_CALLBACK pfCallback,
+               void *pcbParam
+              );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ADI_PWR_H */
+
+
+/*@}*/
+
+/*
+** EOF
+*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/rng/adi_rng.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/rng/adi_rng.h
new file mode 100755
index 00000000000..f5101ef6901
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/rng/adi_rng.h
@@ -0,0 +1,204 @@
+/*!
+ *****************************************************************************
+ @file    adi_rng.h
+ @brief   Random Number Generator Driver
+ -----------------------------------------------------------------------------
+Copyright (c) 2012-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+/*! \addtogroup RNG_Driver RNG Driver
+ *  Random Number Generator Driver
+ *  @{
+ */
+
+#ifndef ADI_RNG_H
+#define ADI_RNG_H
+
+#include <adi_processor.h>
+#include <adi_callback.h>
+
+#ifndef __ADUCM4x50__
+#error "Unsupported processor"
+#endif
+
+#include <adi_rng_config.h>
+
+#ifdef __ICCARM__
+/* IAR MISRA C 2004 error suppressions.
+ *
+ * Pm011 (rule 6.3): The basic types of char, int, long, float cannot be used.
+ *   bool is used in the APIs as it is not affending the rule. Disabling this as IAR treats it as an error.
+ */
+#pragma diag_suppress=Pm011
+#endif /* __ICCARM__ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * \enum ADI_RNG_RESULT
+ * Random Number Generator API return codes
+ */
+typedef enum
+{
+    ADI_RNG_SUCCESS = 0,            /*!<  No Error, API suceeded */
+    ADI_RNG_UNKNOWN_ERROR,          /*!<  Unknown error detected */
+    ADI_RNG_ALREADY_INITIALIZED,    /*!<  RNG is already initialized */
+    ADI_RNG_INVALID_PARAM,          /*!<  Invalid function parameter */
+    ADI_RNG_BAD_DEV_HANDLE,         /*!<  Invalid device handle passed */
+    ADI_RNG_BAD_DEVICE_NUM,         /*!<  Invalid device instance */
+    ADI_RNG_NOT_INITIALIZED,        /*!<  RNG not yet initialized */
+    ADI_RNG_INVALID_STATE           /*!<  Device is in an invalid state */
+} ADI_RNG_RESULT;
+
+/*!
+ * \enum ADI_RNG_EVENT
+ * Random Number Generator callback events
+ */
+typedef enum
+{
+    ADI_RNG_EVENT_READY,               /*!< Random number ready event */
+    ADI_RNG_EVENT_STUCK                /*!< The ring oscillator got stuck event */
+} ADI_RNG_EVENT;
+
+
+/*! The amount of application supplied memory required by the RNG driver */
+#define ADI_RNG_MEMORY_SIZE        (12u)
+
+
+/*! RNG Device handle typedef */
+typedef void* ADI_RNG_HANDLE;
+
+/*================ E X T E R N A L S ==================*/
+
+/*
+ * RNG API
+ */
+
+/* Open a random number generator device */
+extern ADI_RNG_RESULT adi_rng_Open(
+                            uint32_t             const  nDeviceNum,
+                            void*                const  pMemory,
+                            uint32_t             const  MemorySize,
+                            ADI_RNG_HANDLE*      const  phDevice
+                            );
+
+/* Close the RNG Device */
+extern ADI_RNG_RESULT adi_rng_Close(ADI_RNG_HANDLE hDevice);
+
+/* Enable/Disable the device */
+extern ADI_RNG_RESULT adi_rng_Enable (
+                                      ADI_RNG_HANDLE const hDevice,
+                                      bool           const bFlag
+                                      );
+/* Enable/Disable buffering */
+extern ADI_RNG_RESULT adi_rng_EnableBuffering (
+                                               ADI_RNG_HANDLE const hDevice,
+                                               bool           const bFlag
+                                               );
+
+/* Set the sample length */
+extern ADI_RNG_RESULT adi_rng_SetSampleLen (
+                                            ADI_RNG_HANDLE const hDevice,
+                                            uint16_t       const nLenPrescaler,
+                                            uint16_t       const nLenReload
+                                            );
+
+/* Get whether the random number is ready */
+extern ADI_RNG_RESULT adi_rng_GetRdyStatus (
+                                            ADI_RNG_HANDLE const hDevice,
+                                            bool*          const pbFlag
+                                            );
+
+/* Get whether the ring oscillator output is stuck or not */
+extern ADI_RNG_RESULT adi_rng_GetStuckStatus (
+                                              ADI_RNG_HANDLE const hDevice,
+                                              bool*          const pbFlag
+                                              );
+
+/* Get the random number */
+extern ADI_RNG_RESULT adi_rng_GetRngData (
+                                          ADI_RNG_HANDLE const hDevice,
+                                          uint32_t*      const pRegData
+                                          );
+
+/* Get the oscillator count */
+extern ADI_RNG_RESULT adi_rng_GetOscCount (
+                                           ADI_RNG_HANDLE const hDevice,
+                                           uint32_t*      const pOscCount
+                                           );
+
+/* Get the oscillator count difference value */
+extern ADI_RNG_RESULT adi_rng_GetOscDiff (
+                                          ADI_RNG_HANDLE const hDevice,
+                                          uint32_t       const nIndex,
+                                          uint8_t*       const pOscDiff
+                                          );
+
+/* Register a callback */
+extern ADI_RNG_RESULT adi_rng_RegisterCallback (
+                                                ADI_RNG_HANDLE  hDevice,
+                                                ADI_CALLBACK    cbFunc,
+                                                void           *pCBParam
+                                                );
+
+/* Retrieve the current RNG sample length prescale and reload value configured in the device. */
+extern ADI_RNG_RESULT adi_rng_GetSampleLen (
+                                            ADI_RNG_HANDLE const hDevice,
+                                            uint16_t*      const pLenPrescaler,
+                                            uint16_t*      const pLenReload
+                                            );
+
+#ifdef __cplusplus
+}
+#endif
+
+#ifdef __ICCARM__
+#pragma diag_default=Pm011
+#endif /* __ICCARM__ */
+#endif /* include guard */
+
+/*
+** EOF
+*/
+
+/*@}*/
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/rtc/adi_rtc.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/rtc/adi_rtc.h
new file mode 100755
index 00000000000..739bc47dc0b
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/rtc/adi_rtc.h
@@ -0,0 +1,521 @@
+/*!
+ *****************************************************************************
+ @file    adi_rtc.h
+ @brief   Primary include file for Real Time Clock Services.
+ @version $Revision: 29004 $
+ @date    $Date: 2014-12-06 10:37:26 -0500 (Sat, 06 Dec 2014) $
+ -----------------------------------------------------------------------------
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#ifndef ADI_RTC_H__
+#define ADI_RTC_H__
+#include "adi_processor.h"
+
+#include <stdint.h>
+#include <adi_callback.h>
+#include <adi_rtc_config.h>
+
+/*! \addtogroup RTC_Driver RTC Driver
+ *  @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+
+/*! Amount of memory(In bytes) required by the RTC  device driver  for managing the operation.
+ * This memory is completely owned by the driver till the end of the operation.
+ */
+#define ADI_RTC_MEMORY_SIZE    (24u)
+
+/*! Emergency flush command to gatweay register */
+#define ADI_RTC_GATEWAY_FLUSH    0xa2c5
+
+/*! A device handle used in all API functions to identify the RTC device. */
+typedef void*   ADI_RTC_HANDLE;
+
+/*! Interrupt  bit position-1*/
+#define ADI_RTC_INTERRUPT_OFFSET                16
+
+/*! Interrupt  bit position-2*/
+#define ADI_RTC_INTERRUPT_OFFSET_IO_CAPTURE     21
+
+/*!
+ * RTC  API return codes
+ */
+typedef enum
+{
+    /*!  No Error, API succeeded */
+    ADI_RTC_SUCCESS,
+    /*!  Generic failure */
+    ADI_RTC_FAILURE,
+    /*!  RTC is in failsafe mode and not reliable */
+    ADI_RTC_CLOCK_FAILSAFE,
+    /*!  RTC is already initialized */
+    ADI_RTC_IN_USE,
+    /*!  Invalid device handle passed */
+    ADI_RTC_INVALID_HANDLE,
+    /*!  Asking to initialize an unknown instance */
+    ADI_RTC_INVALID_INSTANCE,
+    /*!  Parameter is out of range          */
+    ADI_RTC_INVALID_OPTION,
+    /*!  Specified operation not allowed */
+    ADI_RTC_OPERATION_NOT_ALLOWED,
+    /*!  One of the parameters is invalid */
+    ADI_RTC_INVALID_PARAM,
+    /*!  Input/SensorStrobe channel is invalid for the specified operation */
+    ADI_RTC_INVALID_CHANNEL
+    
+} ADI_RTC_RESULT;
+
+
+/*!
+ * RTC Interrupt Enable Bits.
+ */
+
+
+typedef uint32_t ADI_RTC_INT_TYPE;
+
+#define ADI_RTC_ALARM_INT                  0x00000001u    /*!< Alarm interrupt enable bit */
+#define ADI_RTC_MOD60ALM_INT               0x00000002u    /*!< modulo 60 Alarm interrupt enable */
+#define ADI_RTC_ISO_DONE_INT               0x00000004u    /*!< Power isolation done interrupt enable */
+#define ADI_RTC_WRITE_PENDERR_INT          0x00000008u    /*!< Write pend error interrupt enable */
+#define ADI_RTC_WRITE_SYNC_INT             0x00000010u    /*!< Write sync interrupt enable */
+#define ADI_RTC_WRITE_PEND_INT             0x00000020u    /*!< Write pend interrupt enable  */
+#define ADI_RTC_COUNT_INT                  0x00000040u    /*!< RTC count interrupt source enable */
+#define ADI_RTC_PSI_INT                    0x00000080u    /*!< Precaled Module 1 interrupt */
+#define ADI_RTC_TRIM_INT                   0x00000100u    /*!< Enable for the RTC trim interrupt source */
+#define ADI_RTC_COUNT_ROLLOVER_INT         0x00000200u    /*!< Enable for the RTC count roll-over interrupt source */
+#define ADI_RTC_MOD60_ROLLOVER_INT         0x00000400u    /*!< Enable for the RTC modulo-60 count roll-over interrupt source */
+#define ADI_RTC_SENSOR_STROBE_CH1_INT      0x00000800u    /*!< Enable interrupt for sensor strobe channel -1*/
+#define ADI_RTC_SENSOR_STROBE_CH2_INT      0x00001000u    /*!< Enable interrupt for sensor strobe channel -2*/
+#define ADI_RTC_SENSOR_STROBE_CH3_INT      0x00002000u    /*!< Enable interrupt for sensor strobe channel -3*/
+#define ADI_RTC_SENSOR_STROBE_CH4_INT      0x00004000u    /*!< Enable interrupt for sensor strobe channel -4*/
+#define ADI_RTC_INPUT_CAPTURE_CH0_INT      0x00008000u    /*!< Enable interrupt for input capture channel -0*/
+#define ADI_RTC_INPUT_CAPTURE_CH2_INT      0x00010000u    /*!< Enable interrupt for input capture channel -2*/
+#define ADI_RTC_INPUT_CAPTURE_CH3_INT      0x00020000u    /*!< Enable interrupt for input capture channel -3*/
+#define ADI_RTC_INPUT_CAPTURE_CH4_INT      0x00040000u    /*!< Enable interrupt for input capture channel -4*/
+#define ADI_RTC_LFXTL_FAILURE_INT          0x00080000u    /*!< Interrupt for LFXTL failure. LFXTL failure interrupt is mapped to RTC1 interrupt.*/
+#define ADI_RTC_RTCSS4_FE_INT              0x00100000u    /*!< Enable interrupt for Sensor Strobe channel 3*/
+#define ADI_RTC_RTCSS3_FE_INT              0x00200000u    /*!< Enable interrupt for Sensor Strobe channel 3*/
+#define ADI_RTC_RTCSS2_FE_INT              0x00400000u    /*!< Enable interrupt for Sensor Strobe channel 2*/
+#define ADI_RTC_RTCSS1_FE_INT              0x00800000u    /*!< Enable interrupt for Sensor Strobe channel 2*/
+#define ADI_RTC_RTCSS4MSKEN                0x01000000u    /*!< Enable interrupt for Sensor Strobe channel 4 Mask */
+#define ADI_RTC_RTCSS3MSKEN                0x02000000u    /*!< Enable interrupt for Sensor Strobe channel 3 Mask */
+#define ADI_RTC_RTCSS2MSKEN                0x04000000u    /*!< Enable interrupt for Sensor Strobe channel 2 Mask */
+#define ADI_RTC_RTCSS1MSKEN                0x08000000u    /*!< Enable interrupt for Sensor Strobe channel 1 Mask */
+#define ADI_RTC_CR5OCS_SS3SMPMTCHIRQEN     0x10000000u    /*!< Sample activity Interrupt enable for RTC Sensor Strobe Channel 3 */
+#define ADI_RTC_CR5OCS_SS2SMPMTCHIRQEN     0x20000000u    /*!< Sample activity Interrupt enable for RTC Sensor Strobe Channel 2 */
+#define ADI_RTC_CR5OCS_SS1SMPMTCHIRQEN     0x40000000u    /*!< Sample activity Interrupt enable for RTC Sensor Strobe Channel 1. */
+
+
+#define ADI_RTC_NUM_INTERRUPTS             31             /*!< Number of RTC interrupts. */
+
+
+/*!
+ * RTC Posted Write Status Bits.
+ */
+typedef enum
+{
+    /*!  Posted write control register-0 status bit */
+    ADI_RTC_WRITE_STATUS_CONTROL0      = 1 << BITP_RTC_SR0_WSYNCCR0,
+    /*!  Posted write status0 register status bit */
+    ADI_RTC_WRITE_STATUS_STATUS0       = 1 << BITP_RTC_SR0_WSYNCSR0,
+    /*!  Posted write count0 register status bit */
+    ADI_RTC_WRITE_STATUS_COUNT0        = 1 << BITP_RTC_SR0_WSYNCCNT0,
+    /*!  Posted write count1 register status bit */
+    ADI_RTC_WRITE_STATUS_COUNT1        = 1 << BITP_RTC_SR0_WSYNCCNT1,
+    /*!  Posted write alarm0 register status bit */
+    ADI_RTC_WRITE_STATUS_ALARM0        = 1 << BITP_RTC_SR0_WSYNCALM0,
+    /*!  Posted write alarm1 register status bit */
+    ADI_RTC_WRITE_STATUS_ALARM1        = 1 << BITP_RTC_SR0_WSYNCALM1,
+    /*!  Posted write trim register status bit */
+    ADI_RTC_WRITE_STATUS_TRIM          = 1 << BITP_RTC_SR0_WSYNCTRM
+} ADI_RTC_WRITE_STATUS;
+
+
+/*!
+ * RTC Trim intervals.
+ */
+typedef enum
+{
+    /*!  Trim interval is 2^2 seconds */
+    ADI_RTC_TRIM_INTERVAL_2           = (2 << BITP_RTC_TRM_IVL2EXPMIN    | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^3 seconds */
+    ADI_RTC_TRIM_INTERVAL_3           = (3 << BITP_RTC_TRM_IVL2EXPMIN    | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^4 seconds */
+    ADI_RTC_TRIM_INTERVAL_4           = (4 << BITP_RTC_TRM_IVL2EXPMIN    | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^5 seconds */
+    ADI_RTC_TRIM_INTERVAL_5           = (5 << BITP_RTC_TRM_IVL2EXPMIN    | 0x0 << BITP_RTC_TRM_IVL),
+      /*!  Trim interval is 2^6 seconds */
+    ADI_RTC_TRIM_INTERVAL_6           = (6 << BITP_RTC_TRM_IVL2EXPMIN    | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^7 seconds */
+    ADI_RTC_TRIM_INTERVAL_7           = (7 << BITP_RTC_TRM_IVL2EXPMIN    | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^8 seconds */
+    ADI_RTC_TRIM_INTERVAL_8           = (8 << BITP_RTC_TRM_IVL2EXPMIN    | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^9 seconds */
+    ADI_RTC_TRIM_INTERVAL_9           = (9 << BITP_RTC_TRM_IVL2EXPMIN    | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^10 seconds */
+    ADI_RTC_TRIM_INTERVAL_10           = (10 << BITP_RTC_TRM_IVL2EXPMIN  | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^11 seconds */
+    ADI_RTC_TRIM_INTERVAL_11           = (11 << BITP_RTC_TRM_IVL2EXPMIN  | 0x1 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^12 seconds */
+    ADI_RTC_TRIM_INTERVAL_12           = (12 << BITP_RTC_TRM_IVL2EXPMIN  | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^13 seconds */
+    ADI_RTC_TRIM_INTERVAL_13           = (13 << BITP_RTC_TRM_IVL2EXPMIN  | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^14 seconds */
+    ADI_RTC_TRIM_INTERVAL_14           = (14 << BITP_RTC_TRM_IVL2EXPMIN  | 0x0 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^15 seconds */
+    ADI_RTC_TRIM_INTERVAL_15           = (14 << BITP_RTC_TRM_IVL2EXPMIN  | 0x1 << BITP_RTC_TRM_IVL),
+    /*!  Trim interval is 2^16 seconds */
+    ADI_RTC_TRIM_INTERVAL_16           = (14 << BITP_RTC_TRM_IVL2EXPMIN  | 0x2 << BITP_RTC_TRM_IVL ),
+    /*!  Trim interval is 2^17 seconds */
+    ADI_RTC_TRIM_INTERVAL_17           = (14 << BITP_RTC_TRM_IVL2EXPMIN  | 0x3 << BITP_RTC_TRM_IVL)
+
+} ADI_RTC_TRIM_INTERVAL;
+
+/*!
+ * RTC input capture  channels.
+ */
+typedef enum
+{
+    /*!  Input capture channel-0  */
+    ADI_RTC_INPUT_CHANNEL_0           = 1 << BITP_RTC_CR2IC_IC0EN,
+    /*!  Input capture channel-2  */
+    ADI_RTC_INPUT_CHANNEL_2           = 1 << BITP_RTC_CR2IC_IC2EN,
+    /*!  Input capture channel-3  */
+    ADI_RTC_INPUT_CHANNEL_3           = 1 << BITP_RTC_CR2IC_IC3EN,
+    /*!  Input capture channel-4  */
+    ADI_RTC_INPUT_CHANNEL_4           = 1 << BITP_RTC_CR2IC_IC4EN
+
+}ADI_RTC_INPUT_CHANNEL;
+
+/*!
+ * RTC Sensor Strobe  channels.
+ */
+typedef enum
+{
+    /*!  Sensor Strobe channel-1  */
+    ADI_RTC_SS_CHANNEL_1               = 1 << BITP_RTC_CR3SS_SS1EN,
+    /*!  Sensor Strobe channel-2  */
+    ADI_RTC_SS_CHANNEL_2               = 1 << BITP_RTC_CR3SS_SS2EN,
+    /*!  Sensor Strobe channel-3  */
+    ADI_RTC_SS_CHANNEL_3               = 1 << BITP_RTC_CR3SS_SS3EN,
+    /*!  Sensor Strobe channel-4  */
+    ADI_RTC_SS_CHANNEL_4               = 1 << BITP_RTC_CR3SS_SS4EN,
+
+}ADI_RTC_SS_CHANNEL;
+
+/*!
+ * RTC Trim polarity.
+ */
+typedef enum
+{
+    /*!  Trim value is added every trim interval */
+    ADI_RTC_TRIM_ADD                   = (1 << BITP_RTC_TRM_ADD),
+    /*!  Trim value is subtracted every trim interval */
+    ADI_RTC_TRIM_SUB                   = (0 << BITP_RTC_TRM_ADD),
+} ADI_RTC_TRIM_POLARITY;
+
+/*!
+ * RTC Trim values.
+ */
+typedef enum
+{
+    /*!  Trim value is +/- 0 */
+    ADI_RTC_TRIM_0                     = (0 << BITP_RTC_TRM_VALUE),
+    /*!  Trim value is +/- 1 */
+    ADI_RTC_TRIM_1                     = (1 << BITP_RTC_TRM_VALUE),
+    /*!  Trim value is +/- 2 */
+    ADI_RTC_TRIM_2                     = (2 << BITP_RTC_TRM_VALUE),
+    /*!  Trim value is +/- 3 */
+    ADI_RTC_TRIM_3                     = (3 << BITP_RTC_TRM_VALUE),
+    /*!  Trim value is +/- 4 */
+    ADI_RTC_TRIM_4                     = (4 << BITP_RTC_TRM_VALUE),
+    /*!  Trim value is +/- 5 */
+    ADI_RTC_TRIM_5                     = (5 << BITP_RTC_TRM_VALUE),
+    /*!  Trim value is +/- 6 */
+    ADI_RTC_TRIM_6                     = (6 << BITP_RTC_TRM_VALUE),
+    /*!  Trim value is +/- 7 */
+    ADI_RTC_TRIM_7                     = (7 << BITP_RTC_TRM_VALUE)
+} ADI_RTC_TRIM_VALUE;
+
+/*!
+ * RTC control register set.
+ */
+typedef enum
+{
+  /*! Specify the RTC-Control register-0 */
+  ADI_RTC_CONTROL_REGISTER_0,
+  /*! Specify the RTC-Control register-1 */
+  ADI_RTC_CONTROL_REGISTER_1
+} ADI_RTC_CONTROL_REGISTER;
+
+/*================ E X T E R N A L S ==================*/
+
+/*
+ */
+
+/*************************************/
+/*    RTC API                       */
+/*************************************/
+ADI_RTC_RESULT adi_rtc_Open(
+               uint32_t         DeviceNumber,
+               void            *pDeviceMemory,
+               uint32_t         MemorySize,
+               ADI_RTC_HANDLE  *phDevice
+               );
+
+ADI_RTC_RESULT adi_rtc_Close(
+               ADI_RTC_HANDLE const hDevice
+               );
+
+/*************************************/
+/*    Enable APIs for RTC Device     */
+/*************************************/
+               
+ADI_RTC_RESULT adi_rtc_EnableAlarm(
+               ADI_RTC_HANDLE const hDevice,
+               bool bEnable
+               );
+
+ADI_RTC_RESULT adi_rtc_EnableMod60Alarm(
+               ADI_RTC_HANDLE const hDevice,
+               bool bEnable
+               );
+
+ADI_RTC_RESULT adi_rtc_Enable(
+               ADI_RTC_HANDLE const hDevice,
+               bool bEnable
+               );
+
+ADI_RTC_RESULT adi_rtc_EnableInterrupts(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_INT_TYPE Interrupts,
+               bool bEnable
+               );
+
+ADI_RTC_RESULT adi_rtc_EnableTrim(
+               ADI_RTC_HANDLE const hDevice,
+               bool bEnable
+               );
+               
+ADI_RTC_RESULT adi_rtc_EnableAutoReload(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_SS_CHANNEL   eSSChannel,
+               bool bEnable);
+
+ADI_RTC_RESULT adi_rtc_EnableSensorStrobeOutput (
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_SS_CHANNEL   eSSChannel, 
+               bool bEnable);
+
+ADI_RTC_RESULT adi_rtc_EnableInputCapture (
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_INPUT_CHANNEL eInpChannel,
+               bool bEnable);
+
+ADI_RTC_RESULT adi_rtc_EnableSensorStrobeChannelMask(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_SS_CHANNEL   eSSChannel, 
+               bool bEnable);
+               
+ADI_RTC_RESULT adi_rtc_EnableOverwriteSnapshot (
+               ADI_RTC_HANDLE const hDevice,
+               bool bEnable);
+               
+/*************************************/
+/*    Set APIs for RTC Device     */
+/*************************************/
+
+
+ADI_RTC_RESULT adi_rtc_SetMod60AlarmPeriod(
+               ADI_RTC_HANDLE const hDevice,
+               uint8_t nPeriod
+               );
+
+ADI_RTC_RESULT adi_rtc_SetAlarm(
+               ADI_RTC_HANDLE const hDevice,
+               uint32_t nAlarm
+               );
+
+ADI_RTC_RESULT adi_rtc_SetAlarmEx(
+               ADI_RTC_HANDLE const hDevice,
+               float  fAlarm
+               );
+
+
+ADI_RTC_RESULT adi_rtc_SetControlRegister(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_CONTROL_REGISTER eRegister,
+               uint32_t Control
+               );
+
+ADI_RTC_RESULT adi_rtc_SetCount(
+               ADI_RTC_HANDLE const hDevice,
+               uint32_t nCount
+               );
+
+ADI_RTC_RESULT adi_rtc_SetGateway(
+               ADI_RTC_HANDLE const hDevice,
+               uint16_t Command
+               );
+
+
+ADI_RTC_RESULT adi_rtc_SetPreScale(
+               ADI_RTC_HANDLE const hDevice,
+               uint8_t nPreScale
+               );
+
+ADI_RTC_RESULT adi_rtc_SetTrim(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_TRIM_INTERVAL eInterval,
+               ADI_RTC_TRIM_VALUE  eTrimValue,
+               ADI_RTC_TRIM_POLARITY eOperation
+               );
+               
+ADI_RTC_RESULT adi_rtc_SetSensorStrobeChannelMask(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_SS_CHANNEL   eSSChannel, 
+               uint8_t nMask);
+
+ADI_RTC_RESULT adi_rtc_SetAutoReloadValue(
+                ADI_RTC_HANDLE const hDevice,
+                ADI_RTC_SS_CHANNEL   eSSChannel, 
+                uint16_t nValue);
+                
+ADI_RTC_RESULT adi_rtc_SetInputCapturePolarity (
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_INPUT_CHANNEL eInpChannel,
+               bool bEnable);
+               
+ADI_RTC_RESULT adi_rtc_SetSensorStrobeValue(
+                ADI_RTC_HANDLE const hDevice,
+                ADI_RTC_SS_CHANNEL   eSSChannel, 
+                uint16_t nValue);
+
+/*************************************/
+/*    Get APIs for RTC Device     */
+/*************************************/
+
+ADI_RTC_RESULT adi_rtc_GetAlarm (
+               ADI_RTC_HANDLE hDevice,
+               uint32_t *pAlarm
+               );
+
+ADI_RTC_RESULT adi_rtc_GetAlarmEx (
+               ADI_RTC_HANDLE hDevice,
+               float *pAlarm);
+
+ADI_RTC_RESULT adi_rtc_GetControl (
+               ADI_RTC_HANDLE hDevice,
+               ADI_RTC_CONTROL_REGISTER eRegister ,
+               uint32_t *pControl);
+               
+ADI_RTC_RESULT adi_rtc_GetTrim(
+               ADI_RTC_HANDLE hDevice,
+               ADI_RTC_TRIM_VALUE *peTrim
+               );
+               
+ADI_RTC_RESULT adi_rtc_GetCount(
+               ADI_RTC_HANDLE const hDevice,
+               uint32_t *pCount
+               );
+
+ADI_RTC_RESULT adi_rtc_GetCountEx(
+               ADI_RTC_HANDLE const hDevice,
+               float *pfCount
+               );
+
+ADI_RTC_RESULT adi_rtc_GetSnapShot(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_INPUT_CHANNEL eChannel, 
+               uint32_t *pValue,
+               uint16_t *pFraction);
+
+ADI_RTC_RESULT adi_rtc_GetInputCaptureValue(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_INPUT_CHANNEL eChannel,
+               uint16_t *pValue);
+
+ADI_RTC_RESULT adi_rtc_GetWritePendStatus(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_WRITE_STATUS *pPendBits
+               );
+
+ADI_RTC_RESULT adi_rtc_GetWriteSyncStatus(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_WRITE_STATUS *pSyncBits
+               );
+               
+ADI_RTC_RESULT adi_rtc_GetSensorStrobeValue(
+               ADI_RTC_HANDLE const hDevice,
+               ADI_RTC_SS_CHANNEL   eSSChannel, 
+               uint16_t *pValue);
+               
+ADI_RTC_RESULT adi_rtc_GetCountRegs(
+               ADI_RTC_HANDLE const hDevice, 
+               uint32_t *pnCount,
+               uint32_t *pfCount);        
+/************************************************/
+/*    RTC APIs for managing interrupt/sync     */
+/***********************************************/
+               
+ADI_RTC_RESULT adi_rtc_SynchronizeAllWrites(
+               ADI_RTC_HANDLE const hDevice
+               );
+
+ADI_RTC_RESULT adi_rtc_RegisterCallback(
+               ADI_RTC_HANDLE const  hDevice,
+               ADI_CALLBACK   const   pfCallback,
+               void        *const     pCBparam
+               );
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+
+#endif /* ADI_RTC_H__ */
+
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/spi/adi_spi.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/spi/adi_spi.h
new file mode 100755
index 00000000000..f3aa1118c2a
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/spi/adi_spi.h
@@ -0,0 +1,386 @@
+/*! *****************************************************************************
+ * @file    adi_spi.h
+ * @brief   Main include file for SPI Device driver definitions
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.ADI_SEM_SIZE
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+
+#ifndef ADI_SPI_H__
+#define ADI_SPI_H__
+
+#include <adi_processor.h>
+#include <rtos_map/adi_rtos_map.h>
+#include <adi_spi_config.h>
+
+/** @addtogroup SPI_Driver SPI Driver
+ *  @{
+ */
+
+
+#include <adi_spi_config.h>
+#include <adi_callback.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/*! Amount of memory(In bytes) required by the SPI device driver for managing the operation
+ *  of a SPI controller. The memory is passed to the driver when the driver is opened.
+ * The memory is completely owned by the driver till the the driver is closed.
+ *                                               
+ */
+   
+#define ADI_SPI_MEMORY_SIZE (40u + ADI_SEM_SIZE)
+        
+
+/*!
+ *****************************************************************************
+ * \enum ADI_SPI_RESULT
+ *
+ * SPI Device Error Codes.  #ADI_SPI_SUCCESS is always zero
+ * The return value of all SPI APIs returning #ADI_SPI_RESULT
+ * should always be tested at the application level for success or failure.
+ *
+ *****************************************************************************/
+typedef enum
+{
+    /*! Generic success.                    */
+    ADI_SPI_SUCCESS,
+    /*! Generic Failure.                      */
+    ADI_SPI_FAILURE,
+    /*! SPI device is already initialized.  */
+    ADI_SPI_IN_USE,
+    /*! Invalid device handle.              */
+    ADI_SPI_INVALID_HANDLE,
+    /*! Invalid device ID.                  */
+    ADI_SPI_INVALID_DEVICE_NUM,
+    /*! DMA configuration failure.          */
+    ADI_SPI_DMA_ERROR     ,
+    /*! NULL data pointer not allowed.      */
+    ADI_SPI_INVALID_POINTER,
+    /*! Parameter is out of range.          */
+    ADI_SPI_INVALID_PARAM,
+    /*! Unsupported mode of operation.      */
+    ADI_SPI_UNSUPPORTED_MODE,
+    /*! Semaphore in error           .      */
+    ADI_SPI_SEMAPHORE_FAILED,
+    /*! Invalid operation       */
+    ADI_SPI_INVALID_OPERATION,
+    /*! Buffer Not submitted */
+    ADI_SPI_BUFFER_NOT_SUBMITTED,
+    /*! Could not obtain the system clock */
+    ADI_SPI_BAD_SYS_CLOCK,
+    /*! Blocking PEND failed */
+    ADI_SPI_PEND_FAILED,
+    /*! DMA callback register failed */
+    ADI_SPI_DMA_REG_FAILED,
+    /*! Hardware error occurred */
+    ADI_SPI_HW_ERROR_OCCURRED
+} ADI_SPI_RESULT;
+
+/*!
+ *****************************************************************************
+ * \enum ADI_SPI_HW_ERRORS
+ *
+ * Enumeration of events notified in the application provided callback.
+ * More than one event can be recorded at a time so the enumerator symbols
+ * have to be assigned values of 2^N
+ *****************************************************************************/
+typedef enum
+{
+    /*!< The given buffer is processed. Application can use this event to submit
+         the next buffer to be transmitted. */
+    ADI_SPI_HW_ERROR_NONE                       = 0u,
+   /*!  Tx-underflow interrupt enable */
+    ADI_SPI_HW_ERROR_TX_UNDERFLOW               = 1u,
+    /*!  Rx-overflow interrupt enable */
+    ADI_SPI_HW_ERROR_RX_OVERFLOW                = 2u,
+    /*!  Rx DMA channel bus fault detected */
+    ADI_SPI_HW_ERROR_RX_CHAN_DMA_BUS_FAULT      = 4u,
+    /*!  Tx DMA channel bus fault detected */
+    ADI_SPI_HW_ERROR_TX_CHAN_DMA_BUS_FAULT      = 8u,
+    /*!  Rx DMA channel bus fault detected */
+    ADI_SPI_HW_ERROR_RX_CHAN_DMA_INVALID_DESCR  = 16u,
+    /*!  Tx DMA channel bus fault detected */
+    ADI_SPI_HW_ERROR_TX_CHAN_DMA_INVALID_DESCR  = 32u,
+    /*!  Rx DMA channel unkown error detected */
+    ADI_SPI_HW_ERROR_RX_CHAN_DMA_UNKNOWN_ERROR  = 64u,
+    /*!  Tx DMA channel unkown error detected */
+    ADI_SPI_HW_ERROR_TX_CHAN_DMA_UNKNOWN_ERROR  = 128u          
+
+} ADI_SPI_HW_ERRORS;
+
+/*!
+ *****************************************************************************
+ * \enum ADI_SPI_CHIP_SELECT
+ *
+ * SPI Device Chip Select Enumeration.  Allows designation of an external
+ * SPI slave device chip select pin to be driven by the SPI controller.
+ * Multiple external slave SPI devices may be present on a shared SPI bus,
+ * and the chip select pin allows each of them to be assigned dedicated selects.
+ * Use the #adi_spi_SetChipSelect() API to configure the active chip select.
+ * Note that SPI0 is an internal channel dedicated to the UHF controller and
+ * hence, has a dedicated SPI0 chip select pin that is not available externally.
+ *
+ *****************************************************************************/
+typedef enum
+{
+   /*! No  Slave Chip Select for SPI.               */
+    ADI_SPI_CS_NONE = 0,
+    /*! CS0 Slave Chip Select for SPI.               */
+    ADI_SPI_CS0 = 1,
+   /*! CS1 Slave Chip Select for SPI.               */
+    ADI_SPI_CS1 = 2,
+    /*! CS2 Slave Chip Select for SPI.               */
+    ADI_SPI_CS2 = 4,
+    /*! CS3 Slave Chip Select for SPI.               */
+    ADI_SPI_CS3 = 8
+} ADI_SPI_CHIP_SELECT;
+
+
+/*! SPI Device instance private data handle typedef. */
+typedef       struct __ADI_SPI_DEV_DATA_TYPE*  ADI_SPI_HANDLE;
+/*! SPI Device instance private data handle typedef. 'const' version */
+typedef const struct __ADI_SPI_DEV_DATA_TYPE*  ADI_SPI_CONST_HANDLE;
+
+
+/*!
+  * \struct ADI_SPI_TRANSCEIVER
+ *****************************************************************************
+ * SPI Device Command/Data Transceiver Structure.  Data structure used by
+ * the #adi_spi_MasterReadWrite(),#adi_spi_MasterSubmitBuffer()
+ * API to convey all parameters, consisting of
+ * prologue, transmit and receive data and size, and buffer increment flags.
+ * DMA and Half-Duplex operation are also specified in this structure as T/F.
+ *
+ * Each call to #adi_spi_MasterReadWrite or #adi_spi_MasterSubmitBuffer() must populate the following fields of the
+ * ADI_SPI_TRANSCEIVER block:
+ *
+ * @par TransmitterBytes
+ * The number of  bytes to be transmitted. If the value is zero, data will not be transmitted from the
+ * buffer pointed by pTransmitter.
+ *
+ * @par ReceiverBytes
+ * The number of  bytes to be received. If the value is zero, data will not be stored in the
+ * buffer pointed by pReceiver.
+ *
+ * @par pTransmitter
+ * Pointer to the application-defined transmit data buffer.  This is the data sent out
+ * over the SPI transmit wire (MOSI for Master-mode, MISO for Slave-mode) during the SPI transaction.
+ * For  SPI DMA mode (which is 16-bit based), the transmit buffer must be 16-bit aligned.
+ *
+ * @par pReceiver
+ * Pointer to the application-defined receive data buffer.  This is where the receive data
+ * will be stored from the SPI receive wire (MISO for Master-mode, MOSI for Slave-mode)
+ * during the SPI transaction.
+ * For SPI DMA mode (which is 16-bit based), the receive buffer must be 16-bit aligned.
+ *
+ * @par bTxIncrement
+ * Increment to be done for the transmit buffer after every transaction . The transmit data buffer
+ * pointer is advanced as each byte is sent.  If it is set to zero, the transmit data pointer is stationary.
+ * A stationary buffer pointer is useful for sending the same data to an external device or if
+ * the source data is from a fixed memory address.
+ *
+ * @par bRxIncrement
+ * Increment to be done for the receive buffer.   The transmit data buffer
+ * pointer is advanced as each byte is sent. If it is value is set to zero, the receive
+ * data pointer is stationary.  A stationary buffer pointer is useful for monitoring commands
+ * from an external device or if the receive data is going to a fixed memory address.
+ *
+ * @par bDMA
+ * Indicate whether the transaction is to use DMA (true) or not (false). If using DMA SPI
+ * transactions are limited to 2048 bytes. If more than 2048 bytes are needed then the application
+ * must use multiple transactions (DMA ping pong mode is not supported in the driver).
+ * For  SPI DMA mode (which is 16-bit based), TransmitterBytes/ReceiverBytes is rounded up to an
+ * even number by the SPI driver before submitting to DMA.
+ * Please align the buffer to 16 bit word boundary since the data transfer is 16bit.
+ *
+ *
+ * @par bRD_CTL
+ * Indicate whether the transaction should enable RD_CTL (true) or not (false).
+ * RD_CTL effectively provides half-duplex operation as outlined in the HRM.
+
+ *****************************************************************************/
+typedef struct
+{
+    /*! Pointer to transmit data.        */
+    uint8_t*    pTransmitter;
+    /*! Pointer to receive data.         */
+    uint8_t*    pReceiver;
+   /*! Data size  for TX(bytes).          */
+    uint16_t    TransmitterBytes;
+    /*! Data size  for RX(bytes).          */
+    uint16_t    ReceiverBytes;
+   /*!  Transmit pointer increment flag. */
+    uint8_t     nTxIncrement;
+   /*! Receive pointer increment flag.  */
+    uint8_t     nRxIncrement;
+    /*! DMA mode operation */
+    bool        bDMA;
+    /*! RD_CTL, half-duplex, operation */
+    bool        bRD_CTL;
+
+} ADI_SPI_TRANSCEIVER;
+
+
+
+/******************************************************************************
+ * SPI Device External API function prototypes
+ *****************************************************************************/
+
+/* Device Initialization and Uninitialization Interfaces */
+ADI_SPI_RESULT adi_spi_Open(
+               uint32_t nDeviceNum,
+               void *pDevMemory,
+               uint32_t nMemorySize,
+               ADI_SPI_HANDLE* const phDevice
+               );
+
+ADI_SPI_RESULT adi_spi_Close(
+               ADI_SPI_HANDLE const hDevice
+               );
+
+/******************************************************************
+ * Eliminatable functions that may be optimized out by the linker *
+ *****************************************************************/
+
+ADI_SPI_RESULT adi_spi_MasterReadWrite(
+               ADI_SPI_HANDLE const       hDevice,
+               const ADI_SPI_TRANSCEIVER* const pXfr
+               );
+
+
+ADI_SPI_RESULT adi_spi_SetMasterMode(
+               ADI_SPI_CONST_HANDLE const hDevice,
+               const bool bFlag
+               );
+
+/* Slave Mode APIs */
+ADI_SPI_RESULT adi_spi_SlaveReadWrite(
+               ADI_SPI_HANDLE const hDevice,
+               const ADI_SPI_TRANSCEIVER* const pXfr
+               );
+
+/* Command/Data transceiver API */
+ADI_SPI_RESULT adi_spi_MasterSubmitBuffer(
+              ADI_SPI_HANDLE const hDevice, 
+              const ADI_SPI_TRANSCEIVER* const pXfr
+                );
+
+ADI_SPI_RESULT adi_spi_SlaveSubmitBuffer(
+               ADI_SPI_HANDLE const hDevice, 
+               const ADI_SPI_TRANSCEIVER* 
+               const pXfr
+                 );
+
+ADI_SPI_RESULT adi_spi_RegisterCallback (
+               ADI_SPI_HANDLE const hDevice,  
+               ADI_CALLBACK const pfCallback, 
+               void *const pCBParam 
+                 );
+
+
+/* Turn a non-blocking call into a blocking call. Wait for the transaction to complete  */
+ADI_SPI_RESULT adi_spi_GetBuffer(
+               ADI_SPI_HANDLE const hDevice,
+               uint32_t * const pHWErrors
+               );
+			   
+/* Query function for the data transfer completion  */
+ADI_SPI_RESULT adi_spi_isBufferAvailable(
+               ADI_SPI_CONST_HANDLE const hDevice,
+               bool* const bComplete
+               );
+
+
+
+ADI_SPI_RESULT adi_spi_SetContinuousMode(
+               ADI_SPI_CONST_HANDLE const hDevice,
+               const bool bFlag
+               );
+
+
+ADI_SPI_RESULT adi_spi_SetLoopback(
+               ADI_SPI_CONST_HANDLE const hDevice,
+               const bool bFlag
+               );
+
+ADI_SPI_RESULT adi_spi_SetIrqmode (
+               ADI_SPI_CONST_HANDLE const hDevice, 
+               const uint8_t nMode);
+
+ADI_SPI_RESULT adi_spi_SetReceiveOverflow(
+               ADI_SPI_CONST_HANDLE const hDevice,
+               const bool bFlag
+               );
+
+ADI_SPI_RESULT adi_spi_SetTransmitUnderflow(
+               ADI_SPI_CONST_HANDLE const hDevice,
+               const bool bFlag
+               );
+
+/* Mode Configuration Interface */
+ADI_SPI_RESULT adi_spi_SetBitrate(
+               ADI_SPI_CONST_HANDLE const hDevice,
+               const uint32_t Hertz
+               );
+ADI_SPI_RESULT adi_spi_SetChipSelect(
+               ADI_SPI_HANDLE const hDevice,
+               const ADI_SPI_CHIP_SELECT eChipSelect
+               );
+
+ADI_SPI_RESULT adi_spi_GetBitrate(
+               ADI_SPI_CONST_HANDLE const hDevice,
+               uint32_t* const pnBitrate
+               );
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/**@}*/
+
+
+#endif /* ADI_SPI_H__ */
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/sport/adi_sport.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/sport/adi_sport.h
new file mode 100755
index 00000000000..aaf32f2cb0a
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/sport/adi_sport.h
@@ -0,0 +1,236 @@
+/*! ****************************************************************************
+ * @file    adi_sport.h
+ * @brief   SPORT (Serial Port) Device driver definitions
+ * @details Header File for the SPORT driver API functions and definitions
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef ADI_SPORT_H
+#define ADI_SPORT_H
+
+/*=============  I N C L U D E S   =============*/
+
+#include <adi_processor.h>
+#include <rtos_map/adi_rtos_map.h>
+#include <drivers/dma/adi_dma.h>
+#include <adi_callback.h>
+
+/** @addtogroup SPORT_Driver SPORT Driver
+*  @{
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/*==============  D E F I N E S  ===============*/
+
+/**
+ * Amount of memory (bytes) required by the SPORT device driver for managing
+ * the operation in interrupt mode. This memory is completely owned by the
+ * driver till the end of the operation.
+ */
+#define ADI_SPORT_MEMORY_SIZE   (76u + ADI_SEM_SIZE)
+
+typedef void*  ADI_SPORT_HANDLE;        /*!< Handle to the SPORT Device */
+
+/**
+ * Enumeration of different channels of the SPORT
+ */
+typedef enum
+{
+    ADI_HALF_SPORT_A = 0,               /*!< First half SPORT */
+    ADI_HALF_SPORT_B = 1                /*!< Second half SPORT */
+} ADI_SPORT_CHANNEL;
+
+/**
+ * Enumeration for the direction of operation.
+ */
+typedef enum
+{
+    ADI_SPORT_DIR_RX,                   /*!< Sport in Rx mode */
+    ADI_SPORT_DIR_TX                    /*!< Sport in Tx mode */
+} ADI_SPORT_DIRECTION;
+
+/**
+ * Enumeration for enabling packing.
+ */
+typedef enum
+{
+    ADI_SPORT_NO_PACKING = 0,                                   /*!< No Packing */
+    ADI_SPORT_8BIT_PACKING = ENUM_SPORT_CTL_A_CTL_PACK_8BIT,    /*!< 8-bit packing */
+    ADI_SPORT_16BIT_PACKING = ENUM_SPORT_CTL_A_CTL_PACK_16BIT   /*!< 16-Bit packing */
+} ADI_SPORT_PACKING_MODE;
+
+/**
+ * Enumeration for Hardware Error encountered by the SPORT device.
+ */
+ typedef enum
+{
+    ADI_SPORT_HW_NO_ERR                  = 0x00,  /*!< No Hardware error */
+    ADI_SPORT_HW_ERR_RX_OVERFLOW         = 0x02,  /*!< Data overflow  for Rx (same value as Tx underflow) */
+    ADI_SPORT_HW_ERR_TX_UNDERFLOW        = 0x02,  /*!< Data underflow for Tx (same value as Rx overflow) */
+    ADI_SPORT_HW_ERR_FS                  = 0x04,  /*!< Frame sync error */
+    ADI_SPORT_HW_ERR_SYSDATAERR          = 0x10,  /*!< System Data Error */
+
+    ADI_SPORT_EVENT_RX_BUFFER_PROCESSED  = 0x20,  /*!< Processed the submitted RX buffer  */
+    ADI_SPORT_EVENT_TX_BUFFER_PROCESSED  = 0x40,  /*!< Processed the submitted TX buffer  */
+
+    ADI_SPORT_DMA_ERR_BUS                = 0x100, /*!< SPORT DMA bus error detected  */
+    ADI_SPORT_DMA_ERR_INVALID_DESCRIPTOR = 0x200  /*!< SPORT DMA invalid descriptor error detected  */
+}ADI_SPORT_EVENT;
+
+
+/**
+ *  Enumeration for result code returned from the SPORT device driver functions.
+ */
+typedef enum
+{
+    ADI_SPORT_SUCCESS,                  /*!< Success */
+    ADI_SPORT_FAILED,                   /*!< Generic Failure to indicate a call to SPORT driver function returned unsuccessful */
+    ADI_SPORT_INVALID_DEVICE_NUM ,      /*!< Invalid device number */
+    ADI_SPORT_INVALID_NULL_POINTER,     /*!< Specified pointer is invalid */
+    ADI_SPORT_INVALID_HANDLE,           /*!< The given handle is invalid */
+    ADI_SPORT_INVALID_PARAMETER,        /*!< Specified parameter is not valid */
+    ADI_SPORT_DMA_REGISTER_FAILED,      /*!< Registering DMA error handler failed */
+    ADI_SPORT_DEVICE_IN_USE,            /*!< The specified SPORT channel is already open and in use */
+    ADI_SPORT_INVALID_CONFIGURATION,    /*!< The SPORT configuration is invalid */
+    ADI_SPORT_BUFFERS_NOT_SUBMITTED,    /*!< Buffer submission failed */
+    ADI_SPORT_INVALID_WORD_LENGTH,      /*!< Invalid word size */
+    ADI_SPORT_OPERATION_NOT_ALLOWED,    /*!< Specified operation is not allowed when SPORT is transmitting/receiving data */
+    ADI_SPORT_HW_ERROR                  /*!< SPORT hardware or DMA reports an error  */
+} ADI_SPORT_RESULT;
+
+/*=============  P U B L I C   F U N C T I O N S =============*/
+
+/* Opens a SPORT device */
+ADI_SPORT_RESULT adi_sport_Open(
+    const uint32_t              nDevNum,
+    const ADI_SPORT_CHANNEL     eChannel,
+    const ADI_SPORT_DIRECTION   eDirection,
+    void                        *pMemory,
+    const uint32_t              nMemSize,
+    ADI_SPORT_HANDLE * const    phDevice
+    );
+
+/* Closes a SPORT device */
+ADI_SPORT_RESULT adi_sport_Close(
+    ADI_SPORT_HANDLE const      hDevice
+    );
+
+/* Submits a buffer to the driver */
+ADI_SPORT_RESULT adi_sport_SubmitBuffer(
+    ADI_SPORT_HANDLE const hDevice,
+    void *           const pBuffer,
+    uint32_t         const nNumBytes,
+    bool             const bDMA
+    );
+
+/* Get the processed buffer from the driver */
+ADI_SPORT_RESULT adi_sport_GetBuffer(
+    ADI_SPORT_HANDLE const      hDevice,
+    void ** const               ppBuffer,
+    uint32_t *                  pHwError
+    );
+
+/* Peek function to know whether an processed buffer is avilable */
+ADI_SPORT_RESULT adi_sport_IsBufferAvailable(
+    ADI_SPORT_HANDLE const      hDevice,
+    bool   * const              pbAvailable
+    );
+
+/* To register the callback function */
+ADI_SPORT_RESULT adi_sport_RegisterCallback(
+    ADI_SPORT_HANDLE const      hDevice,
+    const ADI_CALLBACK          pfCallback,
+    void * const                pCBparam
+    );
+
+/* Configure the data */
+ADI_SPORT_RESULT adi_sport_ConfigData(
+    ADI_SPORT_HANDLE  const             hDevice,
+    const uint8_t                       nWordLength,
+    const ADI_SPORT_PACKING_MODE        ePackMode,
+    const bool                          bLSBFirst
+    );
+
+/* Configure the clock */
+ADI_SPORT_RESULT adi_sport_ConfigClock(
+    ADI_SPORT_HANDLE const      hDevice,
+    const uint16_t              nClockRatio,
+    const bool                  bUseIntlClock,
+    const bool                  bRisingEdge,
+    const bool                  bGatedClk
+    );
+
+/* Configure the frame sync */
+ADI_SPORT_RESULT adi_sport_ConfigFrameSync(
+    ADI_SPORT_HANDLE const      hDevice,
+    const uint16_t              nFsDivisor,
+    const bool                  bFSRequired,
+    const bool                  bInternalFS,
+    const bool                  bDataFS,
+    const bool                  bActiveLowFS,
+    const bool                  bLateFS,
+    const bool                  bFSErrorOperation
+    );
+
+/* To mux the half-SPORT; this makes the device to use FS and Clock from other half-SPORT */
+ADI_SPORT_RESULT adi_sport_MultiplexSportSignal(
+    ADI_SPORT_HANDLE const      hDevice,
+    const bool                  bUseOtherFS,
+    const bool                  bUseOtherClk
+    );
+
+/* To configure the SPORT in timer mode */
+ADI_SPORT_RESULT adi_sport_ConfigTimerMode(
+    ADI_SPORT_HANDLE const      hDevice,
+    const uint8_t               nFSDuration,
+    const uint8_t               nWidth,
+    const bool                  bActiveLow
+    );
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* ADI_SPORT_H */
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/tmr/adi_tmr.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/tmr/adi_tmr.h
new file mode 100755
index 00000000000..9331593a126
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/tmr/adi_tmr.h
@@ -0,0 +1,253 @@
+/*! *****************************************************************************
+ * @file    adi_tmr.h
+ * @brief   GP and RGB timer device driver public header file
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+
+#ifndef ADI_TMR_H
+#define ADI_TMR_H
+
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <adi_callback.h>
+
+
+/** @addtogroup TMR_Driver Timer Driver
+ *  @{
+ */
+
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_TMR_RESULT
+ *   Enumeration for result code returned from the timer device driver functions.
+ *   The return value of all timer APIs returning #ADI_TMR_RESULT should always 
+ *   be tested at the application level for success or failure.
+ *****************************************************************************/
+typedef enum {
+    /*! Successful operation */
+    ADI_TMR_SUCCESS,
+    /*! Bad device number supplied by user */
+    ADI_TMR_BAD_DEVICE_NUM,
+    /*! Bad PWM output number supplied by user to #adi_tmr_ConfigPwm */
+    ADI_TMR_BAD_PWM_NUM,
+    /*! Bad event number supplied by user to #adi_tmr_ConfigEvent */
+    ADI_TMR_BAD_EVENT_ID,
+    /*! Bad timer configuration, reloading and free running are mutually exclusive options */
+    ADI_TMR_BAD_RELOAD_CONFIGURATION,
+    /*! Setup or enable function called while the timer is running */
+    ADI_TMR_OPERATION_NOT_ALLOWED,
+    /*! Timeout while waiting for busy bit to clear before writing control register */
+    ADI_TMR_DEVICE_BUSY,
+    /*! User attempts to reload the timer when reloading has not been enabled */
+    ADI_TMR_RELOAD_DISABLED,
+    /*! User attempts to read the current or captured count with a NULL pointer */
+    ADI_TMR_NULL_POINTER
+} ADI_TMR_RESULT;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_TMR_DEVICE
+ *   Enumeration for the hardware peripheral being used during the API call
+ *****************************************************************************/
+typedef enum {
+    /*! General purpose timer 0 */
+    ADI_TMR_DEVICE_GP0 = 0u,
+    /*! General purpose timer 1 */
+    ADI_TMR_DEVICE_GP1 = 1u,
+    /*! General purpose timer 2 */
+    ADI_TMR_DEVICE_GP2 = 2u,
+    /*! RGB timer */
+    ADI_TMR_DEVICE_RGB = 3u,
+    /*! Total number of devices (private) */
+    ADI_TMR_DEVICE_NUM = 4u,
+} ADI_TMR_DEVICE;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_TMR_EVENT
+ *   Enumeration of events notified in the application provided callback.
+ *****************************************************************************/
+typedef enum {
+  /*! Timeout event occurred */
+  ADI_TMR_EVENT_TIMEOUT = 0x01,  
+  /*! Event capture event occurred */
+  ADI_TMR_EVENT_CAPTURE = 0x02,
+} ADI_TMR_EVENT;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_TMR_PRESCALER
+ *   Prescale options when configuring the timer
+ *****************************************************************************/
+typedef enum {
+    /*! Count every 1 source clock periods */
+    ADI_TMR_PRESCALER_1   = 0u,
+    /*! Count every 16 source clock periods */
+    ADI_TMR_PRESCALER_16  = 1u, 
+    /*! Count every 64 source clock periods */
+    ADI_TMR_PRESCALER_64  = 2u,
+    /*! Count every 256 source clock periods */
+    ADI_TMR_PRESCALER_256 = 3u,
+} ADI_TMR_PRESCALER;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_TMR_CLOCK_SOURCE
+ *   Source clock options when configuring the timer
+ *****************************************************************************/
+typedef enum {
+    /*! Use periphreal clock (PCLK) */
+    ADI_TMR_CLOCK_PCLK  = 0u, 
+    /*! Use internal high frequency clock (HFOSC) */
+    ADI_TMR_CLOCK_HFOSC = 1u, 
+    /*! Use internal low frequency clock (LFOSC) */
+    ADI_TMR_CLOCK_LFOSC = 2u, 
+    /*! Use external low frequency clock (LFXTAL) */
+    ADI_TMR_CLOCK_LFXTAL = 3u,
+} ADI_TMR_CLOCK_SOURCE;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_TMR_PWM_OUTPUT
+ *   RGB PWM outputs, used to specify which PWM output to configure. For the GP
+ *   timers only #ADI_TMR_PWM_OUTPUT_0 is allowed. The RGB timer has all three 
+ *   outputs.
+ *****************************************************************************/
+typedef enum {
+    /*! PWM output 0 */
+    ADI_TMR_PWM_OUTPUT_0   = 0u,
+    /*! PWM output 1 */
+    ADI_TMR_PWM_OUTPUT_1   = 1u,
+    /*! PWM output 2 */
+    ADI_TMR_PWM_OUTPUT_2   = 2u,
+    /*! Total number of outputs (private) */
+    ADI_TMR_PWM_OUTPUT_NUM = 3u,
+} ADI_TMR_PWM_OUTPUT;
+
+/*!
+ *****************************************************************************
+ *  \struct ADI_TMR_CONFIG
+ *   Configuration structure to fill and pass to #adi_tmr_ConfigTimer when  
+ *   configuring the GP or RGB timer
+ *****************************************************************************/
+typedef struct {
+    /*! True to count up, false to count down */
+    bool                 bCountingUp;
+    /*! True for periodic (specific load value), false for free running (0xFFFF) */
+    bool                 bPeriodic;
+    /*! Prescaler */
+    ADI_TMR_PRESCALER    ePrescaler;
+    /*! Clock source */
+    ADI_TMR_CLOCK_SOURCE eClockSource;
+    /*! Load value (only relent in periodic mode) */
+    uint16_t             nLoad;
+    /*! Asynchronous load value (only relevant in periodic mode, and when PCLK is used) */
+    uint16_t             nAsyncLoad;
+    /*! True to enable reloading, false to disable it (only relevant in periodic mode) */
+    bool                 bReloading;
+    /*! True to enable sync bypass, false to disable it */
+    bool                 bSyncBypass;
+} ADI_TMR_CONFIG;
+
+/*!
+ *****************************************************************************
+ *  \struct ADI_TMR_EVENT_CONFIG
+ *   Configuration structure to fill and pass to #adi_tmr_ConfigEvent when  
+ *   configuring event capture
+ *****************************************************************************/
+typedef struct {
+    /*! True to enable event capture, false to disable it */
+    bool    bEnable;
+    /*! True to reset the counter and prescaler when the selected event occurs, false to let it continue */
+    bool    bPrescaleReset;
+    /*! Event identifier, see hardware reference manual for details */
+    uint8_t nEventID;
+} ADI_TMR_EVENT_CONFIG;
+
+/*!
+ *****************************************************************************
+ *  \struct ADI_TMR_PWM_CONFIG
+ *   Configuration structure to fill and pass to #adi_tmr_ConfigPwm when  
+ *   configuring pulse width modulation output
+ *****************************************************************************/
+typedef struct {
+    /*! PWM output */
+    ADI_TMR_PWM_OUTPUT     eOutput;
+    /*! True if match mode (configurable duty cycle), false if toggle mode (50% duty cycle) */
+    bool                   bMatch;
+    /*! True for PWM idle high, false for PWM idle low */
+    bool                   bIdleHigh;
+    /*! Match value, only applicable if in match mode */
+    uint16_t               nMatchValue;
+} ADI_TMR_PWM_CONFIG;
+
+/******************************************************************************
+ * PUBLIC API
+ * 1.) Eliminate functions that may be optimized out by the linker
+ * 2.) Ordered by designed function call sequence
+ *****************************************************************************/
+
+/* Initialize timer driver */
+ADI_TMR_RESULT adi_tmr_Init            (ADI_TMR_DEVICE const eDevice, ADI_CALLBACK const pfCallback, void * const pCBParam, bool bEnableInt);
+
+/* Configuration interface functions */
+ADI_TMR_RESULT adi_tmr_ConfigTimer     (ADI_TMR_DEVICE const eDevice, ADI_TMR_CONFIG       timerConfig);
+ADI_TMR_RESULT adi_tmr_ConfigEvent     (ADI_TMR_DEVICE const eDevice, ADI_TMR_EVENT_CONFIG eventConfig);
+ADI_TMR_RESULT adi_tmr_ConfigPwm       (ADI_TMR_DEVICE const eDevice, ADI_TMR_PWM_CONFIG   pwmConfig  );
+
+/* Timer start and stop */
+ADI_TMR_RESULT adi_tmr_Enable          (ADI_TMR_DEVICE const eDevice, bool bEnable);
+
+/* Read functions */
+ADI_TMR_RESULT adi_tmr_GetCurrentCount (ADI_TMR_DEVICE const eDevice, uint16_t *pCount);
+ADI_TMR_RESULT adi_tmr_GetCaptureCount (ADI_TMR_DEVICE const eDevice, uint16_t *pCount);
+
+/* Reload function */
+ADI_TMR_RESULT adi_tmr_Reload          (ADI_TMR_DEVICE const eDevice);
+
+
+/*! @} */
+
+
+#endif /* ADI_TMR_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/uart/adi_uart.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/uart/adi_uart.h
new file mode 100755
index 00000000000..abb0bf3109a
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/uart/adi_uart.h
@@ -0,0 +1,498 @@
+/*! *****************************************************************************
+ * @file    adi_uart.h
+ * @brief   UART device driver global include file.
+ * @details This a global file which includes a specific file based on the processor family.
+ *          This included file will be containing UART device driver functions.
+ -----------------------------------------------------------------------------
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#ifndef ADI_UART_H
+#define ADI_UART_H
+
+/** @addtogroup UART_Driver UART Driver
+*  @{
+*/
+
+/*! \cond PRIVATE */
+
+/*=============  I N C L U D E S   =============*/
+
+#include <stdint.h>
+#include <stddef.h>
+#include <string.h>
+#include <assert.h>
+#include <adi_processor.h>
+#include <adi_uart_config.h>
+#include <rtos_map/adi_rtos_map.h>
+#include <drivers/dma/adi_dma.h>
+#include <drivers/pwr/adi_pwr.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*! \endcond */
+
+/*! Amount of memory(bytes) required by the UART device driver for operating unidirectionally(Either RX or TX).
+ *  This memory is completely owned by the driver until the end of the operation.
+ */
+#define ADI_UART_UNIDIR_MEMORY_SIZE  (48u + (60u + ADI_SEM_SIZE))
+
+/*! Amount of memory(bytes) required by the UART device driver for operating bidirectionally(Both RX and TX).
+ *  This memory is completely owned by the driver until the end of the operation.
+ */
+#define ADI_UART_BIDIR_MEMORY_SIZE  (48u + (60u + ADI_SEM_SIZE)*2u)
+
+/*!
+ * Handle for managing the UART device typedef.
+ */
+typedef struct _ADI_UART_DEVICE* ADI_UART_HANDLE;
+
+/*!
+ * Handle for managing the UART device typedef 'const' version.
+ */
+typedef const struct _ADI_UART_DEVICE* ADI_UART_CONST_HANDLE;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_UART_DIRECTION
+ *   Enumeration for the UART direction.
+ *****************************************************************************/
+typedef enum
+{
+    ADI_UART_DIR_TRANSMIT,                              /*!< UART is only transmitting.   */
+
+    ADI_UART_DIR_RECEIVE,                               /*!< UART is only receiving.      */
+
+    ADI_UART_DIR_BIDIRECTION                            /*!< UART in bidirectional.       */
+
+} ADI_UART_DIRECTION;
+
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_UART_EVENT
+ *   Enumeration of events notified in the application provided callback.
+ *****************************************************************************/
+ typedef enum
+{
+    ADI_UART_EVENT_RX_BUFFER_PROCESSED,                 /*!< Rx buffer is processed.                                   */
+
+    ADI_UART_EVENT_TX_BUFFER_PROCESSED,                 /*!< Tx buffer is processed.                                   */
+
+    ADI_UART_EVENT_NO_RX_BUFFER_EVENT,                  /*!< No Rx buffer but data is in FIFO.                         */
+
+    ADI_UART_EVENT_AUTOBAUD_COMPLETE,                   /*!< Autobaud is complete.                                     */
+
+    ADI_UART_EVENT_HW_ERROR_DETECTED,                   /*!< Hardware error detected.                                  */
+    
+    ADI_UART_EVENT_AUTOBAUD_ERROR_DETECTED              /*!< Autobaud error detected.                                  */
+    
+}ADI_UART_EVENT;
+
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_UART_RESULT
+ *   Enumeration for result code returned from the UART device driver functions.
+ *   The return value of all UART APIs returning #ADI_UART_RESULT
+ *   should always be tested at the application level for success or failure.
+ *****************************************************************************/
+ typedef enum
+{
+
+    ADI_UART_SUCCESS,                           /*!< Generic success.                                               */
+
+    ADI_UART_FAILED,                            /*!< Generic failure.                                               */
+
+    ADI_UART_SEMAPHORE_FAILED,                  /*!< Semaphore error.                                               */
+
+    ADI_UART_INVALID_HANDLE,                    /*!< Invalid device handle.                                         */
+
+    ADI_UART_DEVICE_IN_USE,                     /*!< UART device in use.                                            */
+
+    ADI_UART_INVALID_DEVICE_NUM,                /*!< Invalid device number.                                         */
+
+    ADI_UART_INVALID_POINTER,                   /*!< NULL data pointer is not allowed.                              */
+
+    ADI_UART_INSUFFICIENT_MEMORY,               /*!< Insufficent memory.                                            */
+
+    ADI_UART_INVALID_DIR,                       /*!< Invalid UART direction.                                        */
+
+    ADI_UART_OPERATION_NOT_ALLOWED,             /*!< Invalid operation.                                             */
+
+    ADI_UART_INVALID_PARAMETER,                 /*!< Invalid parameter.                                             */
+
+    ADI_UART_BUFFER_NOT_SUBMITTED,              /*!< Buffer not submitted.                                          */
+
+    ADI_UART_INVALID_DATA_TRANSFER_MODE,        /*!< Invalid transfer mode.
+                                                     Adi_uart_Read()/adi_uart_Write() is used in nonblocking mode
+                                                     or adi_uart_SubmitRxBuffer()/adi_uart_SubmitTxBuffer()
+                                                     is used in blocking mode.                                      */
+
+    ADI_UART_HW_ERROR_DETECTED,                 /*!< Hardware error detected.                                       */
+
+    ADI_UART_AUTOBAUD_ERROR_DETECTED,           /*!< Autobaud error detected.                                       */
+      
+    ADI_UART_ERR_DMA_REGISTER,                  /*!< Error while registering the DMA callback.                      */
+      
+    ADI_UART_INVALID_DATA_SIZE                  /*!< Invalid transfer size. Must be less than 1025 bytes            */
+
+} ADI_UART_RESULT;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_UART_HW_ERRORS
+ *   Enumeration for UART hardware errors. If hardware error(s) occur in
+ *   either callback or interrupt mode, they are mapped to #ADI_UART_HW_ERRORS.
+ *   Interpretation of the break condition is application specific.
+ *****************************************************************************/
+typedef enum
+{
+    ADI_UART_NO_HW_ERROR                     = 0x00,   /*!< No hardware error.                                             */
+
+    ADI_UART_HW_ERR_FRAMING                  = 0x10,   /*!< Rx framing error.                                              */
+
+    ADI_UART_HW_ERR_PARITY                   = 0x20,   /*!< Rx parity error.                                               */
+
+    ADI_UART_HW_ERR_OVERRUN                  = 0x40,   /*!< Receive overrun.                                               */
+ 
+    ADI_UART_BREAK_INTERRUPT                 = 0x80,   /*!< Break condition.                                               */
+      
+    ADI_UART_HW_ERR_RX_CHAN_DMA_BUS_FAULT     = 0x100,  /*!< Rx DMA channel bus fault detected.                             */
+    
+    ADI_UART_HW_ERR_TX_CHAN_DMA_BUS_FAULT     = 0x200,  /*!< Tx DMA channel bus fault detected.                             */
+   
+    ADI_UART_HW_ERR_RX_CHAN_DMA_INVALID_DESCR = 0x400,  /*!< Rx DMA channel invalid descriptor detected.                    */
+    
+    ADI_UART_HW_ERR_TX_CHAN_DMA_INVALID_DESCR = 0x800,  /*!< Tx DMA channel invalid descriptor detected.                    */
+    
+    ADI_UART_HW_ERR_RX_CHAN_DMA_UNKNOWN_ERROR = 0x1000, /*!< Rx DMA channel unknown error detected.                         */
+  
+    ADI_UART_HW_ERR_TX_CHAN_DMA_UNKNOWN_ERROR = 0x2000, /*!< Tx DMA channel unknown error detected.                         */
+
+}ADI_UART_HW_ERRORS;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_UART_AUTOBAUD_ERRORS
+ *   Enumeration for UART autobaud errors. If autobaud related error(s) occur
+ *   they are mapped to #ADI_UART_AUTOBAUD_ERRORS.
+ *****************************************************************************/
+typedef enum
+{
+    ADI_UART_AUTOBAUD_NO_ERROR              = 0x000,  /*!< No autobaud error.                                           */
+
+    ADI_UART_AUTOBAUD_TIMEOUT_NO_START_EDGE = 0x100,  /*!< Timeout due to no valid start edge found during autobaud.    */
+
+    ADI_UART_AUTOBAUD_TIMEOUT_LONGBREAK     = 0x200,  /*!< Timeout due to break condition detected during autobaud.     */
+
+    ADI_UART_AUTOBAUD_TIMEOUT_NO_END_EDGE   = 0x400   /*!< Timeout due to no valid end edge found during autobaud.      */
+
+}ADI_UART_AUTOBAUD_ERRORS;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_UART_TRIG_LEVEL
+ *   Enumeration for the FIFO trigger level.
+ *****************************************************************************/
+typedef enum
+{
+
+    ADI_UART_RX_FIFO_TRIG_LEVEL_1BYTE   =  0 << BITP_UART_FCR_RFTRIG,  /*!< 1-byte to trigger RX interrupt.  */
+
+    ADI_UART_RX_FIFO_TRIG_LEVEL_4BYTE   =  1 << BITP_UART_FCR_RFTRIG,  /*!< 4-byte to trigger RX interrupt.  */
+    
+    ADI_UART_RX_FIFO_TRIG_LEVEL_8BYTE   =  2 << BITP_UART_FCR_RFTRIG,  /*!< 8-byte to trigger RX interrupt.  */
+    
+    ADI_UART_RX_FIFO_TRIG_LEVEL_14BYTE  =  3 << BITP_UART_FCR_RFTRIG   /*!< 14-byte to trigger RX interrupt. */
+
+}ADI_UART_TRIG_LEVEL;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_UART_WORDLEN
+ *   Enumeration for data width. 
+ *****************************************************************************/
+typedef enum
+{
+    ADI_UART_WORDLEN_5BITS,             /*!< 5 bits wide. */
+
+    ADI_UART_WORDLEN_6BITS,             /*!< 6 bits wide. */
+
+    ADI_UART_WORDLEN_7BITS,             /*!< 7 bits wide. */
+
+    ADI_UART_WORDLEN_8BITS              /*!< 8 bits wide. */
+
+} ADI_UART_WORDLEN;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_UART_PARITY
+ *   Enumeration for parity check.
+ *****************************************************************************/
+typedef enum
+{
+    ADI_UART_NO_PARITY          =  0x0,  /*!< No parity.          */
+
+    ADI_UART_ODD_PARITY         =  0x8,  /*!< Odd parity.         */
+
+    ADI_UART_EVEN_PARITY        =  0x18, /*!< Even Parity.        */
+
+    ADI_UART_ODD_PARITY_STICKY  =  0x28, /*!< Sticky odd parity.  */
+
+    ADI_UART_EVEN_PARITY_STICKY =  0x38  /*!< Sticky even parity. */
+      
+} ADI_UART_PARITY;
+
+/*!
+ *****************************************************************************
+ *  \enum ADI_UART_STOPBITS
+ *   Enumeration for the number of stop bits.
+ *****************************************************************************/
+typedef enum
+{
+    
+    ADI_UART_ONE_STOPBIT               = 0x00,          /*! One stop bit regardless of the word length                           */
+   
+    ADI_UART_ONE_AND_HALF_TWO_STOPBITS = 0x04           /*! Number of stop bits based on word length. 1.5 stop bits 
+                                                            for word length of 5 bits and 2 for rest( 6,7,8 bit word length)     */
+      
+} ADI_UART_STOPBITS;
+
+/*!
+ *****************************************************************************
+ * \enum  ADI_UART_TRANSFER_MODE
+ *  Enumeration for data transfer mode.
+ *****************************************************************************/
+typedef enum
+{
+    
+    ADI_UART_DATA_TRANSFER_MODE_NONE,       /*! Mode of data transfer is not selected.                             */ 
+    
+    ADI_UART_DATA_TRANSFER_MODE_BLOCKING,   /*! Blocking mode. Only calls to adi_uart_Read or adi_uart_write  
+                                                are allowed for sending or receiving data.                         */
+    
+    ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING /*! Non-Blocking mode. Only calls to adi_uart_SubmitRxBuffer or
+                                                adi_uart_SubmitTxBuffer are allowed for sending or receiving data. */
+
+} ADI_UART_TRANSFER_MODE;
+
+
+/******************************************************************************
+ * UART Device external API function prototypes
+ *****************************************************************************/
+
+/*
+ * Device initialization and uninitialization interfaces.
+*/
+ADI_UART_RESULT adi_uart_Open(
+                uint32_t           const nDeviceNum,
+                ADI_UART_DIRECTION const eDirection,
+                void                    *pMemory,
+                uint32_t           const nMemSize,
+                ADI_UART_HANDLE   *const phDevice
+);
+
+ADI_UART_RESULT adi_uart_Close(
+                ADI_UART_HANDLE  const   hDevice
+);
+
+
+/******************************************************************************
+ * Eliminatable functions that may be optimized out by the linker
+ *****************************************************************************/
+
+/*
+ * Non-blocking mode functions.
+*/
+
+ADI_UART_RESULT adi_uart_SubmitTxBuffer(
+                ADI_UART_HANDLE const    hDevice,
+                void           *const    pBuffer,
+                uint32_t        const    nBufSize,
+                bool            const    bDMA
+);
+
+ADI_UART_RESULT adi_uart_SubmitRxBuffer(
+                ADI_UART_HANDLE const    hDevice,
+                void           *const    pBuffer,
+                uint32_t        const    nBufSize,
+                bool            const    bDMA
+);
+
+ADI_UART_RESULT adi_uart_GetTxBuffer(
+                ADI_UART_HANDLE const    hDevice,
+                void          **const    ppBuffer,
+                uint32_t                *pHwError
+);
+
+ADI_UART_RESULT adi_uart_GetRxBuffer(
+                ADI_UART_HANDLE const    hDevice,
+                void          **const    ppBuffer,
+                uint32_t                *pHwError
+);
+ADI_UART_RESULT adi_uart_IsTxBufferAvailable(
+                ADI_UART_HANDLE const    hDevice,
+                bool           *const    pbAvailable
+);
+
+ADI_UART_RESULT adi_uart_IsRxBufferAvailable(
+                ADI_UART_HANDLE const    hDevice,
+                bool           *const    pbAvailable
+);
+
+/*
+ * Blocking mode functions.
+*/
+
+ADI_UART_RESULT adi_uart_Write(
+                ADI_UART_HANDLE const    hDevice,
+                void           *const    pBuffer,
+                uint32_t        const    nBufSize,
+                bool            const    bDMA,
+                uint32_t                *pHwError
+);
+
+ADI_UART_RESULT adi_uart_Read(
+                ADI_UART_HANDLE const    hDevice,
+                void           *const    pBuffer,
+                uint32_t        const    nBufSize,
+                bool            const    bDMA,
+                uint32_t                *pHwError
+);
+
+
+/*
+ * Configuration interface functions.
+*/
+
+ADI_UART_RESULT adi_uart_EnableLoopBack(
+                ADI_UART_HANDLE const     hDevice,
+                bool            const     bEnable
+);
+
+ADI_UART_RESULT adi_uart_EnableAutobaud(
+                ADI_UART_HANDLE const     hDevice,
+                bool            const     bEnable,
+                bool            const     bAutobaudCallbackMode
+);
+
+ADI_UART_RESULT adi_uart_SetRxFifoTriggerLevel(
+                ADI_UART_CONST_HANDLE     const hDevice,
+                ADI_UART_TRIG_LEVEL       const eTriglevel
+);
+
+ADI_UART_RESULT adi_uart_EnableFifo(
+                ADI_UART_HANDLE const     hDevice,
+                bool            const     bEnable
+);
+
+ADI_UART_RESULT adi_uart_GetBaudRate(
+                ADI_UART_HANDLE const     hDevice,
+                uint32_t                 *pnBaudRate,
+                uint32_t                 *pAutobaudError
+);
+
+ADI_UART_RESULT adi_uart_ForceTxBreak(
+                ADI_UART_HANDLE const     hDevice,
+                bool            const     bEnable
+);
+
+ADI_UART_RESULT adi_uart_SetConfiguration(
+                ADI_UART_HANDLE   const  hDevice,
+                ADI_UART_PARITY   const  eParity,
+                ADI_UART_STOPBITS const  eStopBits,
+                ADI_UART_WORDLEN  const  eWordLength
+);
+
+ADI_UART_RESULT adi_uart_ConfigBaudRate(
+                ADI_UART_HANDLE   const hDevice,
+                uint16_t          const nDivC,
+                uint8_t           const nDivM,
+                uint16_t          const nDivN,
+                uint8_t           const nOSR  
+);
+
+/*
+ * Channel data control functions.
+*/
+
+ADI_UART_RESULT adi_uart_FlushTxFifo(
+                ADI_UART_CONST_HANDLE const  hDevice
+);
+
+ADI_UART_RESULT adi_uart_FlushRxFifo(
+                ADI_UART_CONST_HANDLE const  hDevice
+);
+
+ADI_UART_RESULT adi_uart_FlushRxChannel(
+                ADI_UART_CONST_HANDLE const  hDevice
+);
+
+
+ADI_UART_RESULT adi_uart_FlushTxChannel(
+                ADI_UART_CONST_HANDLE const  hDevice
+);
+
+ADI_UART_RESULT adi_uart_IsTxComplete(
+                ADI_UART_HANDLE const hDevice,
+                bool           *const pbComplete
+);
+
+/*
+ * Callback functions.
+*/
+
+ADI_UART_RESULT adi_uart_RegisterCallback(
+                ADI_UART_HANDLE const    hDevice,
+                const ADI_CALLBACK       pfCallback,
+                void           *const    pCBParam
+);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+/*@}*/
+
+#endif /* ADI_UART_H */
+
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/wdt/adi_wdt.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/wdt/adi_wdt.h
new file mode 100755
index 00000000000..834afee018d
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/wdt/adi_wdt.h
@@ -0,0 +1,77 @@
+/*! *****************************************************************************
+ * @file    adi_wdt.h
+ * @brief   WDT device driver public header
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_WDT_H
+#define ADI_WDT_H
+
+#include <adi_callback.h>
+
+/** @addtogroup WDT_Driver WDT Driver
+ *  @{
+ */
+
+/*! \enum ADI_WDT_RESULT Watchdog Device Error Codes. */
+typedef enum
+{
+    /*! Generic success. */
+    ADI_WDT_SUCCESS,
+    /*! Timer is locked. */
+    ADI_WDT_FAILURE_LOCKED
+} ADI_WDT_RESULT;
+
+
+/******************************************************************************
+ * PUBLIC API
+ * 1.) Eliminatable functions that may be optimized out by the linker
+ * 2.) Ordered by designed function call sequence
+ *****************************************************************************/
+
+ADI_WDT_RESULT adi_wdt_Enable  (bool const bEnable, ADI_CALLBACK const pfCallback);
+void           adi_wdt_Kick    (void);
+void           adi_wdt_GetCount(uint16_t * const pCurCount);
+
+
+/*! @} */
+
+#endif /* ADI_WDT_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/xint/adi_xint.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/xint/adi_xint.h
new file mode 100755
index 00000000000..ba76911f640
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/xint/adi_xint.h
@@ -0,0 +1,120 @@
+/*
+ *****************************************************************************
+   @file:    adi_xint.h
+   @brief:   External interrupt driver definitions and API
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#ifndef ADI_XINT_H
+#define ADI_XINT_H
+
+/*! \addtogroup XINT_Driver External Interrupt Driver
+ *  @{
+ */
+
+#ifdef __ICCARM__
+#pragma diag_default=Pm008
+#endif /* __ICCARM__ */
+
+#include <adi_callback.h>
+#include <adi_processor.h>
+
+#if !defined(__ADUCM4x50__)
+#error "Unknown processor family"
+#endif
+
+/* C++ linkage */
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*! Amount of memory(in bytes) required by the External Interrupt device driver for its operation.
+ * This memory is completely owned by the driver till the end of the operation.
+ */
+#define ADI_XINT_MEMORY_SIZE        (48u)
+
+/*! External Interrupt Driver API function return codes */
+typedef enum
+{
+    ADI_XINT_SUCCESS = 0,                       /*!< API successfully returned. */
+    ADI_XINT_FAILURE,                           /*!< The API call failed. */
+    ADI_XINT_ALREADY_INITIALIZED,               /*!< External interrupt driver has already been initialized. */
+    ADI_XINT_NOT_INITIALIZED,                   /*!< External interrupt driver has not yet been initialized. */
+    ADI_XINT_NULL_PARAMETER,                    /*!< The given pointer is pointing to NULL. */
+    ADI_XINT_INVALID_MEMORY_SIZE,               /*!< The given memory is not sufficient to operate the driver. */   
+    ADI_XINT_INVALID_INTERRUPT                  /*!< Invalid interrupt number. */
+} ADI_XINT_RESULT;
+
+
+/*! External interrupt trigger condition enumerations */
+typedef enum {
+    ADI_XINT_IRQ_RISING_EDGE    = 0x0,          /*!< Trigger an interrupt when a rising edge is detected.    */
+    ADI_XINT_IRQ_FALLING_EDGE   = 0x1,          /*!< Trigger an interrupt when on a falling edge is detected.   */
+    ADI_XINT_IRQ_EITHER_EDGE    = 0x2,          /*!< Trigger an interrupt on either falling or rising edge is detected. */
+    ADI_XINT_IRQ_HIGH_LEVEL     = 0x3,          /*!< Trigger an interrupt on a logic level high is detected.     */
+    ADI_XINT_IRQ_LOW_LEVEL      = 0x4           /*!< Trigger an interrupt on a logic level low is detected.  */
+} ADI_XINT_IRQ_MODE;
+
+/*! External interrupts. */
+typedef enum {
+    ADI_XINT_EVENT_INT0         = 0x0,          /*!< Event for external interrupt-0   */
+    ADI_XINT_EVENT_INT1         = 0x1,          /*!< Event for external interrupt-1   */
+    ADI_XINT_EVENT_INT2         = 0x2,          /*!< Event for external interrupt-2   */
+    ADI_XINT_EVENT_INT3         = 0x3,          /*!< Event for external interrupt-3   */
+    ADI_XINT_EVENT_RESERVED     = 0x4,          /*!< Event is reserved.   */
+    ADI_XINT_EVENT_UART_RX      = 0x5,          /*!< Event for UART Rx activity   */
+    ADI_XINT_EVENT_MAX          = 0x6           /*!< Number of external interrupt events */
+} ADI_XINT_EVENT;
+
+
+/* External Interrupt API functions */
+ADI_XINT_RESULT  adi_xint_Init                  (void* const pMemory, uint32_t const MemorySize);
+ADI_XINT_RESULT  adi_xint_UnInit                (void);
+ADI_XINT_RESULT  adi_xint_EnableIRQ             (const ADI_XINT_EVENT eEvent, const ADI_XINT_IRQ_MODE eMode);
+ADI_XINT_RESULT  adi_xint_DisableIRQ            (const ADI_XINT_EVENT eEvent); 
+ADI_XINT_RESULT  adi_xint_RegisterCallback      (const ADI_XINT_EVENT eEvent, ADI_CALLBACK const pfCallback, void *const pCBParam );
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+
+#endif /* ADI_XINT_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash.c
new file mode 100755
index 00000000000..66bc3cf1f69
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash.c
@@ -0,0 +1,1812 @@
+/*!
+ *****************************************************************************
+ @file:    adi_flash.c
+ @brief:   Flash Device Driver Implementation
+ @date:    $Date: 2016-06-30 08:06:37 -0400 (Thu, 30 Jun 2016) $
+ -----------------------------------------------------------------------------
+Copyright (c) 2012-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+/** @addtogroup Flash_Driver Flash Driver
+ *  @{
+ *
+ *  @brief <b>Flash (FEE) Driver</b>
+ *
+ *  @details
+ *
+ *  The flash controller provides access to the embedded flash memory. The embedded
+ *  flash has a 72-bit wide data bus providing for two 32-bit words of data and
+ *  one corresponding 8-bit ECC byte per access.
+ *
+ *  <b>Flash Driver Hardware Errors</b>
+ *
+ * Many of the Flash Controller APIs can result in hardware errors.  Each such API has a
+ * a hardware error parameter (pHwErrors), which is a pointer to an application-defined
+ * variable into which the failing API will store the failing hardware error status.\n
+ *
+ * APIs failing with hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED
+ * return code.\n
+ *
+ * Hardware error details may be decoded according to the flash controller status register
+ * ("STAT") bit-map, documented in the Hardware Reference Manual (HRM).  Flash hardware
+ * errors are separate and distinct from DMA errors, which have separate and distinct
+ * return codes (#ADI_FEE_ERR_DMA_BUS_FAULT, #ADI_FEE_ERR_DMA_INVALID_DESCR, and
+ * #ADI_FEE_ERR_DMA_UNKNOWN_ERROR).
+ *
+ *  <b>Flash Driver Static Configuration</b>
+ *
+ * A number of flash driver APIs manage configurations that very likely do not require
+ * dynamic (run-time) management.  Such cases are documented with the respective APIs.
+ * In all such cases, the user is encouraged to consider using the static configuration
+ * equivalents (provided in the adi_flash_config.h file) in lieu of the dynamic APIs.
+ * In so doing, linker elimination may reduce the resulting code image footprint
+ * (provided the API is not called).
+ *
+ * @note - The application must include drivers/flash/adi_flash.h to use this driver.
+ * @note - This driver also requires the DMA driver.  The application must include
+ *         the DMA driver sources to avoid link errors.
+ */
+
+/*========  I N C L U D E  ========*/
+
+ /*! \cond PRIVATE */
+#include <adi_processor.h>
+#include <assert.h>
+#include <string.h>     /* for "memset" */
+/*! \endcond */
+
+#include <drivers/flash/adi_flash.h>
+
+/*=============  M I S R A   =============*/
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
+*   This isn't a header as such.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+*
+* Pm050 (rule 14.2): a null statement shall only occur on a line by itself
+*   Needed for null expansion of ADI_INSTALL_HANDLER and others.
+*
+* Pm088 (rule 17.4): pointer arithmetic should not be used.
+*   Relying on pointer arithmetic for buffer handling.
+*
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   Required for MMR accesses, determining pointer alignment, and a callback argument.
+*
+* Pm026 (rule 12.4): the right hand operand of an && or || operator shall not contain side effects
+*   Side effects being mis-reported due to added volatile storage class.
+*/
+#pragma diag_suppress=Pm123,Pm073,Pm143,Pm050,Pm088,Pm140,Pm026
+#endif /* __ICCARM__ */
+
+/* pull in internal data structures */
+#include "adi_flash_data.c"
+
+/*========  D E F I N E S   ========*/
+
+/*! \cond PRIVATE */
+
+#ifdef ADI_DEBUG
+#define ASSERT(X)   assert(X)
+#else
+#define ASSERT(X)
+#endif
+
+/* internal utility macros */
+#define CLR_BITS(REG, BITS) ((REG) &= ~(BITS))
+#define SET_BITS(REG, BITS) ((REG) |= (BITS))
+
+#ifdef ADI_DEBUG
+/* Validate Device Handle */
+static bool IsDeviceHandle (ADI_FEE_HANDLE const hDevice);
+static bool IsDeviceHandle (ADI_FEE_HANDLE const hDevice)
+{
+    if ( (fee_device_info[0].hDevice == (hDevice)) && ((hDevice)->pDevInfo->hDevice != NULL) ) {
+        return true;
+    } else {
+        return false;
+    }
+}
+#endif
+
+/* Wait for specified flash status to be clear */
+static void BusyWait (ADI_FEE_HANDLE const hDevice, uint32_t const status);
+static void BusyWait (ADI_FEE_HANDLE const hDevice, uint32_t const status)
+{
+    while ((hDevice->pDev->STAT & status) != 0u) {}
+}
+
+/* Internal DMA Callback for receiving DMA faults from common DMA error handler */
+static void dmaCallback(void *pCBParam, uint32_t Event, void *pArg);
+static void dmaCallback(void *pCBParam, uint32_t Event, void *pArg) {
+
+    /* recover the device handle */
+    ADI_FEE_HANDLE hDevice = (ADI_FEE_HANDLE)pCBParam;
+
+    /* save the DMA error */
+    switch (Event) {
+        case ADI_DMA_EVENT_ERR_BUS:
+            hDevice->dmaError = ADI_FEE_ERR_DMA_BUS_FAULT;
+            break;
+        case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR:
+            hDevice->dmaError = ADI_FEE_ERR_DMA_INVALID_DESCR;
+            break;
+        default:
+            hDevice->dmaError = ADI_FEE_ERR_DMA_UNKNOWN_ERROR;
+            break;
+    }
+
+    /* transfer is toast... post and callback any waiters */
+
+    SEM_POST(hDevice);
+
+    if (0u != hDevice->pfCallback) {
+        hDevice->pfCallback (hDevice->pCBParam, (uint32_t)hDevice->dmaError, (void*)NULL);
+    }
+}
+
+/*! \endcond */
+
+
+/*========  C O D E  ========*/
+/*
+ * API Implementation
+ */
+
+
+/**
+ * @brief    Open the flash controller.
+ *
+ * @param [in]     nDeviceNum    The zero-based device instance number of flash controller to be opened.
+ * @param [in]     pMemory       Application supplied memory space for use by the driver.
+ * @param [in]     nMemorySize   Size of the application supplied memory (in bytes).
+ * @param [in,out] phDevice      The caller's device handle pointer for storing the initialized
+ *                               device instance data pointer.
+ *
+ * @return  Status
+ *          - #ADI_FEE_SUCCESS                      The device is opened successfully.
+ *          - #ADI_FEE_ERR_BAD_DEVICE_NUM       [D] The device number passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Some pointer(s) passed to the function is NULL.
+ *          - #ADI_FEE_ERR_ALREADY_INITIALIZED  [D] The device is already initialized and hence cannot be opened.
+ *          - #ADI_FEE_ERR_INSUFFICIENT_MEM     [D] The memory passed to the driver is insufficient.
+ *          - #ADI_FEE_ERR_DMA_REGISTER             The required DMA common error handler registration failed.
+ *          - #ADI_FEE_ERR_SEMAPHORE_FAILED         The semaphore create operation failed.
+ *
+ * Initialize an instance of the flash device driver using default user configuration settings
+ * (from adi_flash_config.h) and allocate the device for use.
+ *
+ * No other flash APIs may be called until the device open function is called.  The returned
+ * device handle is required to be passed to all subsequent flash API calls to identify the
+ * physical device instance in use.  The user device handle (pointed to by phDevice) is set
+ * to NULL on failure.
+ *
+ * @note Currently, only a singular flash physical device instance (device ID "0") exists.
+ *
+ * @sa      adi_fee_Close().
+ */
+ADI_FEE_RESULT adi_fee_Open (uint32_t const nDeviceNum, void* const pMemory, uint32_t const nMemorySize, ADI_FEE_HANDLE* const phDevice)
+{
+    ADI_FEE_HANDLE hDevice = NULL;  /* initially */
+
+#ifdef ADI_DEBUG
+    if (nDeviceNum >= ADI_FEE_NUM_INSTANCES) {
+        return ADI_FEE_ERR_BAD_DEVICE_NUM;
+    }
+
+    /* verify device is not already open */
+    if (fee_device_info[nDeviceNum].hDevice != NULL) {
+        return ADI_FEE_ERR_ALREADY_INITIALIZED;
+    }
+
+    if ((pMemory == NULL) || (phDevice == NULL)) {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+
+    if (nMemorySize < ADI_FEE_MEMORY_SIZE) {
+        return ADI_FEE_ERR_INSUFFICIENT_MEM;
+    }
+
+    assert (ADI_FEE_MEMORY_SIZE == sizeof(ADI_FEE_DEV_DATA_TYPE));
+#endif
+
+    /* store a bad handle in case of failure */
+    *phDevice = NULL;
+
+    /* Link user memory (handle) into ADI_FEE_DEVICE_INFO data structure.
+     *
+     *       ADI_FEE_DEVICE_INFO  <==>   ADI_FEE_HANDLE
+     */
+    fee_device_info[nDeviceNum].hDevice = (ADI_FEE_DEV_DATA_TYPE *)pMemory;
+
+    /* Clear the ADI_FEE_HANDLE memory. This also sets all bool
+     * structure members to false so we do not need to waste cycles
+     * setting these explicitly (e.g. hDevice->bUseDma = false)
+     */
+    memset(pMemory, 0, nMemorySize);
+
+    /* initialize local device handle and link up device info for this device instance */
+    hDevice = (ADI_FEE_HANDLE)pMemory;
+    hDevice->pDevInfo = &fee_device_info[nDeviceNum];
+
+    /* Although the ADI_FEE_DEVICE_INFO struct has the physical device pointer
+     * for this instance, copying it to the ADI_FEE_HANDLE struct (in user memory)
+     * will minimize the runtime footprint and cycle count when accessing the FEE
+     * registers.
+     */
+    hDevice->pDev = fee_device_info[nDeviceNum].pDev;
+
+    /* store a pointer to user's static configuration settings for this device instance */
+    hDevice->pDevInfo->pConfig = (ADI_FEE_CONFIG*)&gConfigInfo[nDeviceNum];
+
+    /* create the semaphore */
+    SEM_CREATE(hDevice, "fee_sem", ADI_FEE_ERR_SEMAPHORE_FAILED);
+
+    /* grant keyed access */
+    hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
+
+        /* apply the static initializers */
+        hDevice->pDev->IEN         = hDevice->pDevInfo->pConfig->eccIrqEnables;
+        hDevice->pDev->TIME_PARAM0 = hDevice->pDevInfo->pConfig->param0;
+        hDevice->pDev->TIME_PARAM1 = hDevice->pDevInfo->pConfig->param1;
+        hDevice->pDev->ABORT_EN_LO = hDevice->pDevInfo->pConfig->abortEnableLo;
+        hDevice->pDev->ABORT_EN_HI = hDevice->pDevInfo->pConfig->abortEnableHi;
+        hDevice->pDev->ECC_CFG     = hDevice->pDevInfo->pConfig->eccConfig;
+
+        /* clear auto-increment and dma enable bits */
+        CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN));
+
+    /* close keyed access */
+    hDevice->pDev->KEY = 0u;
+
+    /* store device handle into user handle */
+    *phDevice = (ADI_FEE_HANDLE)hDevice;
+
+    /* initialize DMA service */
+    adi_dma_Init();
+
+    if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pDevInfo->dmaChanNum, dmaCallback, (void*)hDevice)) {
+        /* uninitialize flash driver and fail */
+        adi_fee_Close(hDevice);
+        return  ADI_FEE_ERR_DMA_REGISTER;
+    }
+
+    /* NVIC enables */
+    NVIC_EnableIRQ(hDevice->pDevInfo->pioIrqNum);
+    NVIC_EnableIRQ(hDevice->pDevInfo->dmaIrqNum);
+
+    /* return success */
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Close the flash controller.
+ *
+ * @param [in] hDevice   The handle to the flash controller device
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The device is closed successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_SEMAPHORE_FAILED         The semaphore delete operation failed.
+ *
+ * Uninitialize and release an allocated flash device, and memory associated with it
+ * for other use.
+ *
+ * @note The user memory is released from use by the flash driver, but is not freed.
+ *
+ * @sa  adi_fee_Open().
+ */
+ADI_FEE_RESULT adi_fee_Close (ADI_FEE_HANDLE const hDevice)
+{
+    uint32_t dev;
+
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+#endif
+
+    /* Destroy the semaphore */
+    SEM_DELETE(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED);
+
+    /* Remove the device handle from the list of possible device instances */
+    for (dev = 0u; dev < ADI_FEE_NUM_INSTANCES; dev++)
+    {
+        if (fee_device_info[dev].hDevice == hDevice)
+        {
+            fee_device_info[dev].hDevice = NULL;
+            break;
+        }
+    }
+
+    /* NVIC disables */
+    NVIC_DisableIRQ(hDevice->pDevInfo->pioIrqNum);
+    NVIC_DisableIRQ(hDevice->pDevInfo->dmaIrqNum);
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief   Register an application-defined callback function.
+ *
+ * @param [in]  hDevice     The handle to the flash controller device.
+ * @param [in]  pfCallback  A pointer to an application-supplied calllback function
+ *                          which is called to notify the application of device-related
+ *                          events.  A value of NULL disables driver callbacks.
+ * @param [in]  pCBParam    An application-supplied callback parameter which will be passed
+ *                          back to the callback function.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The callback is registered successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] A flash write operation is in progress and
+ *                                                  the callback registration is ignored.
+ *
+ * Links the user-provided callback function into the #adi_fee_SubmitBuffer() API such that
+ * rather than polling for buffer completion (with #adi_fee_IsBufferAvailable()) and eventually
+ * reacquiring the buffer (with #adi_fee_GetBuffer()), the user can simply register a callback
+ * function that will be called upon buffer completion with no further action needed.\n
+ *
+ * Error conditions are also passed to the callback, including DMA errors if DMA is active.  Make sure
+ * to always check the event value passed to the callback, just as the various API return codes should
+ * always be checked.\n
+ *
+ * However, callbacks are always made in context of an interrupt, so applications are strongly encouraged
+ * to exit the callback as quickly as possible so normal interrupt processing is disrupted as little as
+ * possible.  This is also an argument for not using callbacks at at all.
+ *
+ * @note When using callbacks to reacquire buffers, DO NOT use the #adi_fee_GetBuffer() API.  The two
+ * methods are mutually exclusive.
+ *
+ * @sa adi_fee_SubmitBuffer().
+ * @sa adi_fee_IsBufferAvailable().
+ * @sa adi_fee_GetBuffer().
+ */
+ADI_FEE_RESULT adi_fee_RegisterCallback (ADI_FEE_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void* const pCBParam)
+{
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+#endif
+
+    /* Set the callback function and param in the device */
+    hDevice->pfCallback = pfCallback;
+    hDevice->pCBParam   = pCBParam;
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Erase the given range of (2kB) page(s) within the flash user space memory.  This is a blocking call.
+ *
+ * @param [in]     hDevice         The handle to the flash controller device.
+ * @param [in]     nPageNumStart   Start page number.
+ * @param [in]     nPageNumEnd     End page number.
+ * @param [in,out] pHwErrors       Pointer to user location into which any flash hardware errors are reported.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The page(s) is(are) cleared successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] The page(s) number(s) is(are) incorrect.
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is in progress.
+ *          - #ADI_FEE_ERR_HW_ERROR_DETECTED        An internal flash controller hardware error was detected.
+ *          - #ADI_FEE_ERR_SEMAPHORE_FAILED         The semaphore pend operation failed.
+ *
+ * Erases entire page(s).  Callers are expected to save/restore any partial page data prior
+ * to erasure, as needed.  Translate literal flash addresses into flash start and end page
+ * numbers with #adi_fee_GetPageNumber().
+ *
+ * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code.
+ * Flash hardware error details are written to the location pointed to by the pHwErrors parameter.
+ * Hardware error details may be decoded according to the flash controller status register ("STAT")
+ * bit-map, documented in the Hardware Reference Manual (HRM).
+ *
+ * @sa adi_fee_GetPageNumber().
+ * @sa adi_fee_MassErase().
+ */
+ADI_FEE_RESULT adi_fee_PageErase (ADI_FEE_HANDLE const hDevice, uint32_t const nPageNumStart, uint32_t const nPageNumEnd, uint32_t* const pHwErrors)
+
+{
+    ADI_FEE_RESULT result = ADI_FEE_SUCCESS;
+
+    uint32_t page;
+
+#ifdef ADI_DEBUG
+
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+
+    uint32_t nRelAddrStart = (nPageNumStart << FEE_PAGE_SHIFT);
+    uint32_t nRelAddrStop  = (nPageNumEnd   << FEE_PAGE_SHIFT);
+
+    if (   (nPageNumStart > nPageNumEnd)
+        || (nRelAddrStart >= FEE_FLASH_SIZE)
+        || (nRelAddrStop  >= FEE_FLASH_SIZE))
+    {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif /* defined (ADI_DEBUG) */
+
+    for (page = nPageNumStart; page <= nPageNumEnd; page++)
+    {
+        /* Wait until not busy */
+        BusyWait(hDevice, (BITM_FLCC_STAT_CMDBUSY | BITM_FLCC_STAT_WRCLOSE));
+
+        /* Set the page address */
+        hDevice->pDev->PAGE_ADDR0 = (page << FEE_PAGE_SHIFT);
+
+        /* Issue a page erase command */
+        result = SendCommand (hDevice, ENUM_FLCC_CMD_ERASEPAGE);
+
+        /* block on command */
+        SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED);
+
+        if (result != ADI_FEE_SUCCESS) {
+            break;
+        }
+    }
+
+    /* copy out any hardware errors... */
+    *pHwErrors = hDevice->feeError;
+    if (0u != hDevice->feeError) {
+        /* return the HW error return code */
+        return ADI_FEE_ERR_HW_ERROR_DETECTED;
+    }
+
+    return result;
+}
+
+
+/**
+ * @brief    Erase the entire flash user space memory.  This is a blocking call.
+ *
+ * @param [in]     hDevice    The handle to the flash controller device.
+ * @param [in,out] pHwErrors  Pointer to user location into which any flash hardware errors are reported.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The flash is cleared successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is in progress.
+ *          - #ADI_FEE_ERR_HW_ERROR_DETECTED        An internal flash controller hardware error was detected.
+ *          - #ADI_FEE_ERR_SEMAPHORE_FAILED         The semaphore pend operation failed.
+ *
+ * @note Do not call mass erase on or from code that is running from flash.  Doing so will leave
+ * an indeterminate machine state.
+ *
+ * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code.
+ * Flash hardware error details are written to the location pointed to by the pHwErrors parameter.
+ * Hardware error details may be decoded according to the flash controller status register ("STAT")
+ * bit-map, documented in the Hardware Reference Manual (HRM).
+ *
+ * @sa adi_fee_PageErase().
+ */
+ADI_FEE_RESULT adi_fee_MassErase (ADI_FEE_HANDLE const hDevice, uint32_t* const pHwErrors)
+{
+    ADI_FEE_RESULT result = ADI_FEE_SUCCESS;
+
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+#endif
+
+    /* Call the mass erase command */
+    result = SendCommand (hDevice, ENUM_FLCC_CMD_MASSERASE);
+
+    /* block on command */
+    SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED);
+
+    /* copy out any hardware errors... */
+    *pHwErrors = hDevice->feeError;
+    if (0u != hDevice->feeError) {
+        /* return the HW error return code */
+        return ADI_FEE_ERR_HW_ERROR_DETECTED;
+    }
+
+    return result;
+}
+
+
+/**
+ * @brief     Perform a blocking flash data write operation.
+ *
+ * @param [in]  hDevice         The handle to the flash controller device.
+ * @param [in]  pTransaction    Pointer to a user-defined control block describing the data to be transferred, containing:
+ *                                - pWriteAddr; Pointer to a 64-bit-aligned destination address in flash.
+ *                                - pWriteData; Pointer to a 32-bit-aligned source data buffer in user memory.
+ *                                - nSize;      Number of bytes to write (must be an integral multiple of 8).
+ *                                - bUseDma;    Flag controlling use of DMA to perform the write.
+ * @param [in,out] pHwErrors    Pointer to user location into which any flash hardware errors are reported.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The buffer is successfully written to the flash.
+ *          - #ADI_FEE_ERR_ALIGNMENT            [D] The flash write source data pointer is misaligned.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Buffer size is not a multiple of 8-bytes (or too large for DMA).
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress.
+ *          - #ADI_FEE_ERR_BUFFER_ERR               Error occurred in processing the buffer.
+ *          - #ADI_FEE_ERR_DEVICE_BUSY              The flash controller is busy.
+ *          - #ADI_FEE_ERR_DMA_BUS_FAULT            A runtime DMA bus fault was detected.
+ *          - #ADI_FEE_ERR_DMA_INVALID_DESCR        A runtime DMA invalid descriptor was detected.
+ *          - #ADI_FEE_ERR_DMA_UNKNOWN_ERROR        An unknown runtime DMA error was detected.
+ *          - #ADI_FEE_ERR_HW_ERROR_DETECTED        An internal flash controller hardware error was detected.
+ *          - #ADI_FEE_ERR_NO_DATA_TO_TRANSFER      Transfer ran out of write data unexpectedly.
+ *          - #ADI_FEE_ERR_SEMAPHORE_FAILED         The semaphore pend operation failed.
+ *
+ * Perform a blocking flash data write operation.  This API does not return until the write operation is completed.
+ *
+ * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code.
+ * Flash hardware error details are written to the location pointed to by the pHwErrors parameter.
+ * Hardware error details may be decoded according to the flash controller status register ("STAT")
+ * bit-map, documented in the Hardware Reference Manual (HRM).  Flash hardware errors are separate
+ * and distinct from DMA errors, which have separate and distinct return codes, as described above.
+ */
+ADI_FEE_RESULT adi_fee_Write (ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION* const pTransaction, uint32_t* const pHwErrors)
+{
+    ADI_FEE_RESULT result = ADI_FEE_SUCCESS;
+
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+
+	/* check address is 64-bit aligned and data pointer is 32-bit aligned */
+    if ( (((uint32_t)pTransaction->pWriteAddr & 0x7u) != 0u) || ((((uint32_t)pTransaction->pWriteData) & 0x3u) != 0u) )
+    {
+        return ADI_FEE_ERR_ALIGNMENT;
+    }
+
+	/* make sure size is a multiple of 8 */
+    if ((pTransaction->nSize & 0x7u) != 0u) {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+
+    if (true == pTransaction->bUseDma) {
+        /* check for max DMA units (32-bit chunks, i.e., 4 bytes at a whack) */
+        if (DMA_TRANSFER_LIMIT < (pTransaction->nSize / sizeof(uint32_t))) {
+            return ADI_FEE_ERR_INVALID_PARAM;
+        }
+    }
+#endif
+
+    /* reset submit/get safeguard flag */
+    hDevice->bSubmitCalled = false;
+
+    /* Fill in the transfer params */
+    hDevice->pNextWriteAddress = pTransaction->pWriteAddr;
+    hDevice->pNextReadAddress  = pTransaction->pWriteData;
+    hDevice->nRemainingBytes   = pTransaction->nSize;
+    hDevice->bUseDma           = pTransaction->bUseDma;
+
+    /* Initiate a transfer */
+    result = InitiateTransfer (hDevice);
+
+    /* Wait for the completed transfer */
+    SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED);
+
+    /* issue any flash DMA error status codes... */
+    if (0u != hDevice->dmaError) {
+        return hDevice->dmaError;
+    }
+
+    /* copy out any hardware errors... */
+    *pHwErrors = hDevice->feeError;
+    if (0u != hDevice->feeError) {
+        /* return the HW error return code */
+        return ADI_FEE_ERR_HW_ERROR_DETECTED;
+    }
+
+    /* Check for errors in buffer write */
+    if (hDevice->nRemainingBytes != 0u) {
+        return ADI_FEE_ERR_BUFFER_ERR;
+    }
+
+    return result;
+}
+
+
+/**
+ * @brief     Submit a non-blocking flash data write operation for background processing.
+ *
+ * @param [in]  hDevice         The handle to the flash controller device.
+ * @param [in]  pTransaction    Pointer to a user-defined control block describing the data to be transferred, containing:
+ *                                - pWriteAddr; Pointer to a 64-bit-aligned destination address in flash.
+ *                                - pWriteData; Pointer to a 32-bit-aligned source data buffer in user memory.
+ *                                - nSize;      Number of bytes to write (must be an integral multiple of 8).
+ *                                - bUseDma;    Flag controlling use of DMA to perform the write.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The buffer is successfully written to the flash.
+ *          - #ADI_FEE_ERR_ALIGNMENT            [D] The flash write source data pointer is misaligned.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Buffer size is not a multiple of 8-bytes (or too large for DMA).
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress.
+ *          - #ADI_FEE_ERR_BUFFER_ERR               Error occurred in processing the buffer.
+ *          - #ADI_FEE_ERR_DEVICE_BUSY              The flash controller is busy.
+ *          - #ADI_FEE_ERR_NO_DATA_TO_TRANSFER      Transfer ran out of write data unexpectedly.
+ *
+ * Submit a flash data write transaction. This is a non-blocking function which returns immediately.
+ * The application may either: poll for transaction completion through the non-blocking #adi_fee_IsBufferAvailable()
+ * API, and/or await transaction completion through the blocking mode #adi_fee_GetBuffer() API.  If an application
+ * callback has been registered, the application is advised of completion status through the callback.
+ *
+ * @note If using callback mode, DO NOT USE the #adi_fee_GetBuffer() API, which are mutually exclusive protocols.
+ *
+ * @sa adi_fee_IsBufferAvailable().
+ * @sa adi_fee_GetBuffer().
+ */
+ADI_FEE_RESULT adi_fee_SubmitBuffer (ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION* const pTransaction)
+{
+    ADI_FEE_RESULT result = ADI_FEE_SUCCESS;
+
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+
+	/* check address is 64-bit aligned and data pointer is 32-bit aligned */
+    if ( (((uint32_t)pTransaction->pWriteAddr & 0x7u) != 0u) || ((((uint32_t)pTransaction->pWriteData) & 0x3u) != 0u) )
+    {
+        return ADI_FEE_ERR_ALIGNMENT;
+    }
+
+	/* make sure size is a multiple of 8 */
+    if ((pTransaction->nSize & 0x7u) != 0u) {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+
+    if (true == pTransaction->bUseDma) {
+        /* check for max DMA units (32-bit channel width means 4 bytes at a whack) */
+        if (DMA_TRANSFER_LIMIT < (pTransaction->nSize / sizeof(uint32_t))) {
+            return ADI_FEE_ERR_INVALID_PARAM;
+        }
+    }
+#endif
+
+    /* set submit/get safeguard flag */
+    hDevice->bSubmitCalled = true;
+
+    /* Fill in the transfer params */
+    hDevice->pNextWriteAddress = pTransaction->pWriteAddr;
+    hDevice->pNextReadAddress  = pTransaction->pWriteData;
+    hDevice->nRemainingBytes   = pTransaction->nSize;
+    hDevice->bUseDma           = pTransaction->bUseDma;
+
+    /* initiate a transfer */
+    result = InitiateTransfer (hDevice);
+
+    /* no pend here... just return */
+
+    return result;
+}
+
+
+/**
+ * @brief   Non-blocking check if a write transaction complete.
+ *
+ * @param [in]      hDevice           The handle to the flash controller device.
+ * @param [in,out]  pbCompletionState True if transfer is complete, false if not.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The status of buffer is returned successfully.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Pointer passed is NULL.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY   No matching buffer submit call found.
+ *
+ * Check if a non-blocking write transaction that was submitted via adi_fee_SubmitBuffer() is complete.
+ *
+ * @sa adi_fee_SubmitBuffer().
+ * @sa adi_fee_GetBuffer().
+ */
+ADI_FEE_RESULT adi_fee_IsBufferAvailable (ADI_FEE_HANDLE const hDevice, bool* const pbCompletionState)
+
+{
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    if (pbCompletionState == NULL) {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif
+
+    /* fail if not a submit-based transaction */
+    if (false == hDevice->bSubmitCalled) {
+        return ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY;
+    }
+
+    if (true == hDevice->bTransferInProgress) {
+        *pbCompletionState = false;
+    } else {
+        *pbCompletionState = true;
+    }
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Blocking mode call to await transaction completion.
+ *
+ * @param [in]     hDevice    The handle to the flash controller device.
+ * @param [in,out] pHwErrors  Pointer to user location into which any flash hardware errors are reported.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The buffer is successfully written to the flash.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_BUFFER_ERR               Error occurred in processing the buffer.
+ *          - #ADI_FEE_ERR_DMA_BUS_FAULT            A runtime DMA bus fault was detected.
+ *          - #ADI_FEE_ERR_DMA_INVALID_DESCR        A runtime DMA invalid descriptor was detected.
+ *          - #ADI_FEE_ERR_DMA_UNKNOWN_ERROR        An unknown runtime DMA error was detected.
+ *          - #ADI_FEE_ERR_HW_ERROR_DETECTED        An internal flash controller hardware error was detected.
+ *          - #ADI_FEE_ERR_SEMAPHORE_FAILED         The semaphore pend operation failed.
+ *          - #ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY   No matching buffer submit call found.
+ *
+ * This function blocks until a previously-submitted flash write operation has completed.
+ *
+ * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code.
+ * Flash hardware error details are written to the location pointed to by the pHwErrors parameter.
+ * Hardware error details may be decoded according to the flash controller status register ("STAT")
+ * bit-map, documented in the Hardware Reference Manual (HRM).
+ *
+ * @sa adi_fee_SubmitBuffer().
+ * @sa adi_fee_IsBufferAvailable().
+ */
+ADI_FEE_RESULT adi_fee_GetBuffer (ADI_FEE_HANDLE const hDevice, uint32_t* const pHwErrors)
+
+{
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+#endif
+
+    /* fail if not a submit-based transaction */
+    if (false == hDevice->bSubmitCalled) {
+        return ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY;
+    }
+
+    /* Pend for the semaphore */
+    SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED);
+
+    /* issue any flash DMA error status codes... */
+    if (0u != hDevice->dmaError) {
+        return hDevice->dmaError;
+    }
+
+    /* copy out any hardware errors... */
+    *pHwErrors = hDevice->feeError;
+    if (0u != hDevice->feeError) {
+        /* return the HW error return code */
+        return ADI_FEE_ERR_HW_ERROR_DETECTED;
+    }
+
+    /* Check for errors in buffer write or transfer still in progress */
+    if ((0u != hDevice->nRemainingBytes) || (true == hDevice->bTransferInProgress)) {
+        return ADI_FEE_ERR_BUFFER_ERR;
+    }
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief   Get the (2kB) page number within which a flash address resides.
+ *
+ * @param [in]      hDevice     The handle to the flash controller device.
+ * @param [in]      nAddress    The flash address for which the page number is required.
+ * @param [in,out]  pnPageNum   Pointer to a variable into which the page number corresponding
+ *                              to the provided flash address is written.
+ *
+ * @return  Status
+ *          - #ADI_FEE_SUCCESS                      The page number is returned successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Parameter(s) are invalid.
+ *
+ * Translates a literal flash address into a page number for use with various page-based flash operations.
+ *
+ * @sa adi_fee_PageErase().
+ * @sa adi_fee_VerifySignature().
+ * @sa adi_fee_ConfigECC().
+ * @sa adi_fee_GetBlockNumber().
+ *
+ */
+ADI_FEE_RESULT adi_fee_GetPageNumber (ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t* const pnPageNum)
+{
+#ifdef ADI_DEBUG
+
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    if (   (pnPageNum == NULL)
+        || (nAddress >= FEE_FLASH_SIZE))
+    {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif
+
+    /* Set the page number for the given flash address */
+    *pnPageNum = (nAddress >> FEE_PAGE_SHIFT);
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Get the (16kB) block number within which a flash address resides.
+ *
+ * @param [in]      hDevice     The handle to the flash controller device.
+ * @param [in]      nAddress    The flash address for which the block number is required.
+ * @param [in,out]  pnBlockNum  Pointer to a variable into which the block number corresponding
+ *                              to the provided flash address is written.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The block number is returned successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Parameter(s) are invalid.
+ *
+ * Translates a literal flash address into a block number for use with setting flash write protection on a block.
+ *
+ * @sa adi_fee_WriteProtectBlock().
+ * @sa adi_fee_GetPageNumber().
+ */
+ADI_FEE_RESULT adi_fee_GetBlockNumber (ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t* const pnBlockNum)
+{
+#ifdef ADI_DEBUG
+
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    if (   (pnBlockNum == NULL)
+        || (nAddress >= FEE_FLASH_SIZE))
+    {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif
+
+    /* Set the block number */
+    *pnBlockNum = (nAddress >> FEE_BLOCK_SHIFT);
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Generate the CRC signature for a range of flash data page(s).  This is a blocking call.
+ *
+ * @param [in]     hDevice      The handle to the flash controller device.
+ * @param [in]     nStartPage   The lower page number of the signature range.
+ * @param [in]     nEndPage     The upper page number of the signature range.
+ * @param [in,out] pSigResult   Pointer to a variable into which the computed signature is stored.
+ * @param [in,out] pHwErrors    Pointer to user location into which any flash hardware errors are reported.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The signature is verified successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM       [D] The page(s) number(s) is(are) incorrect.
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] A flash write operation is in progress.
+ *          - #ADI_FEE_ERR_HW_ERROR_DETECTED        An internal flash controller hardware error was detected.
+ *          - #ADI_FEE_ERR_SEMAPHORE_FAILED         The semaphore pend operation failed.
+ *
+ * Compute and return a CRC over a range of contiguous whole flash memory pages(s).  The computed CRC
+ * signature may subsequently be written into the most-significant word of the region over which the
+ * signature was calculated.  This is done in context of enabling bootloader enforcement of CRC signature
+ * verification during system startup.  See HRM for signature storage programming requirements and
+ * bootloader operation.
+ *
+ * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code.
+ * Flash hardware error details are written to the location pointed to by the pHwErrors parameter.
+ * Hardware error details may be decoded according to the flash controller status register ("STAT")
+ * bit-map, documented in the Hardware Reference Manual (HRM).
+ *
+ * @sa adi_fee_GetPageNumber().
+ */
+ADI_FEE_RESULT adi_fee_VerifySignature (ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, uint32_t const nEndPage, uint32_t* const pSigResult, uint32_t* const pHwErrors)
+
+{
+    ADI_FEE_RESULT result = ADI_FEE_SUCCESS;
+
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+
+    if (   (pSigResult == NULL)
+        || (nStartPage >  nEndPage)
+        || (nStartPage >= FEE_MAX_NUM_PAGES)
+        || (nEndPage >= FEE_MAX_NUM_PAGES)
+        )
+    {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif
+
+    /* Wait until not busy */
+    BusyWait (hDevice, (BITM_FLCC_STAT_CMDBUSY | BITM_FLCC_STAT_WRCLOSE));
+
+    /* Set the lower and upper page */
+    hDevice->pDev->PAGE_ADDR0 = nStartPage << FEE_PAGE_SHIFT;
+    hDevice->pDev->PAGE_ADDR1 = nEndPage << FEE_PAGE_SHIFT;
+
+    /* Do a SIGN command */
+    result = SendCommand(hDevice, ENUM_FLCC_CMD_SIGN);
+
+    /* block on command */
+    SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED);
+
+    /* Return the signature to the application */
+    if (ADI_FEE_SUCCESS == result) {
+        *pSigResult = hDevice->pDev->SIGNATURE;
+    } else {
+        *pSigResult = 0u;
+    }
+
+    /* copy out any hardware errors... */
+    *pHwErrors = hDevice->feeError;
+    if (0u != hDevice->feeError) {
+        /* return the HW error return code */
+        return ADI_FEE_ERR_HW_ERROR_DETECTED;
+    }
+
+    return result;
+}
+
+
+/**
+ * @brief    Set write protection on an (16kB) block.
+ *
+ * @param [in]  hDevice     The handle to the flash controller device.
+ * @param [in]  nBlockNum   The block number.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The block is write protected successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Block number is invalid.
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress.
+ *
+ * Assert memory write-protection for specified block.  Note that only entire blocks are protectable,
+ * with each block spanning 8 pages.
+ *
+ * @note Blocks may only be write-protected during user run-time code.  Unprotecting is only
+ * possible with a power-on-reset or a mass erase; write-protection is not otherwise clearable.
+ *
+ * @warning Flash-based code that write-protects blocks will cause the write-protection (and data at
+ * time of write-protect assertion) to apparently not clear... even after a mass erase or power-on-reset.
+ * This apparently "stuck" write-protection results from the flash-based write-protect code running
+ * after reset (as usual), but still prior to the debugger halting the target through the debug
+ * interrupt.  The debugger target halt occurs WELL AFTER the flash code has already run, thereby
+ * relocking the block and making it appear the write-protection was never reset.  This can be difficult
+ * Catch-22 situation to recover from, requiring repeated hardware resets and reflashing new code that
+ * does not assert the write-protection.
+ *
+ * @sa adi_fee_GetBlockNumber().
+ */
+ADI_FEE_RESULT adi_fee_WriteProtectBlock (ADI_FEE_HANDLE const hDevice, uint32_t const nBlockNum)
+
+{
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+
+    if (nBlockNum > FEE_MAX_NUM_BLOCKS) {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif
+
+    /* Set the write protection (by clearing the bit) for the given block */
+    hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
+    CLR_BITS (hDevice->pDev->WRPROT, 1u << nBlockNum);
+    hDevice->pDev->KEY = 0u;
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Sleep or awake the flash controller.  This is a blocking call.
+ *
+ * @param [in]  hDevice   The handle to the flash controller device.
+ * @param [in]  bSleep    'true' to enable to sleep the flash device
+ *                        and 'false' to wake up the device.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The flash controller is moved to sleep/wake
+ *                                                  up sate successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress.
+ *          - #ADI_FEE_ERR_SEMAPHORE_FAILED         The semaphore pend operation failed.
+ *
+ * Places the flash controller into a low-power sleep mode - see details in Hardware Reference Manual (HRM).
+ * Default wakeup time is approximately 5us, and is configurable with static configuration parameter
+ * ADI_FEE_CFG_PARAM1_TWK in adi_flash_config.h file.
+ */
+ADI_FEE_RESULT adi_fee_Sleep (ADI_FEE_HANDLE const hDevice, bool const bSleep)
+{
+    ADI_FEE_RESULT result = ADI_FEE_SUCCESS;
+
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+#endif
+
+    /* TODO: Check that IDLE can take the controller
+     *       out of sleep
+     */
+
+    if (true == bSleep) {
+        result = SendCommand (hDevice, ENUM_FLCC_CMD_SLEEP);
+    } else {
+        result = SendCommand (hDevice, ENUM_FLCC_CMD_IDLE);
+    }
+
+    /* block on command */
+    SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED);
+
+    return result;
+}
+
+
+/**
+ * @brief    Forcefully ABORT an ongoing flash operation.  This is a blocking call.
+ *
+ * @param [in]  hDevice   The handle to the flash controller device.
+ *
+ * @return   Statuus
+ *          - #ADI_FEE_SUCCESS                      The command is successfully aborted.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid
+ *          - #ADI_FEE_ERR_SEMAPHORE_FAILED         The semaphore pend operation failed.
+ *
+ * @warning Use this command sparingly and as a last resort to satisfy critical
+ * time-sensitive events.  Aborting any flash command results in prematurely ending the
+ * current flash access and may result in corrupted flash data.
+ *
+ * @sa adi_fee_GetAbortAddr().
+ */
+ADI_FEE_RESULT adi_fee_Abort (ADI_FEE_HANDLE const hDevice)
+
+{
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+#endif
+    /* Issue the command (abort is keyed) directly */
+    /* (avoid SendCommand() here, as it does a busy wait, which may not clear if we're in a recovery mode) */
+    hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
+    hDevice->pDev->CMD = ENUM_FLCC_CMD_ABORT;
+    hDevice->pDev->KEY = 0u;
+
+    SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED);
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Get the address of recently aborted write command.
+ *
+ * @param [in]     hDevice     The handle to the flash controller device.
+ * @param [in,out] pnAddress   Pointer to which the address is written.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The abort address is retrieved successfully
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Pointer passed is NULL
+ *
+ * Users may use this result to determine the flash location(s) affected by a write abort command.
+ * Subsequent flash commands invalidate the write abort address register.
+ *
+ *
+ * @sa adi_fee_Abort().
+ */
+ADI_FEE_RESULT adi_fee_GetAbortAddr (ADI_FEE_HANDLE const hDevice, uint32_t* const pnAddress)
+{
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    if (pnAddress == NULL) {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif
+
+    /* Write the address of the last write abort to the pointer
+     * supplied by the application
+     */
+    *pnAddress = hDevice->pDev->WR_ABORT_ADDR;
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Configure ECC start page and enablement.
+ *
+ * @param [in]  hDevice         The handle to the flash controller device.
+ * @param [in]  nStartPage      The start page for which ECC will be performed.
+ * @param [in]  bInfoECCEnable  Info space ECC enable:
+ *                                  - 'true' to enable info space ECC, or
+ *                                  - 'false' to disable info space ECC.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The ECC was configured successfully
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Start page is invalid
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress.
+ *
+ * @note The settings this API manages are very likely not needed to be modified dynamically (at run-time).
+ * If so, consider using the static configuration equivalents (see adi_flash_config.h) in lieu of
+ * this API... which will reduce the resulting code image footprint through linker elimination.
+ *
+ * @warning This API leaves user space ECC disabled.  Use #adi_fee_EnableECC() to manage ECC enable/disable.
+ *
+ * @sa adi_fee_EnableECC().
+ * @sa adi_fee_ConfigECCEvents().
+ * @sa adi_fee_GetECCErrAddr().
+ * @sa adi_fee_GetECCCorrections().
+ */
+ADI_FEE_RESULT adi_fee_ConfigECC (ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, bool const bInfoECCEnable)
+{
+    uint32_t nRelAddress = nStartPage << FEE_PAGE_SHIFT;
+
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+
+    if (nStartPage >= FEE_MAX_NUM_PAGES) {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif
+
+    /* Clear the ECC config bits */
+    CLR_BITS (hDevice->pDev->ECC_CFG, (BITM_FLCC_ECC_CFG_PTR | BITM_FLCC_ECC_CFG_INFOEN));
+
+    /* Set the start page address in the ECC Cfg register */
+    hDevice->pDev->ECC_CFG |= (nRelAddress & BITM_FLCC_ECC_CFG_PTR);
+
+    /* enable ECC on info space... if requested */
+    if (true == bInfoECCEnable) {
+        SET_BITS (hDevice->pDev->ECC_CFG, BITM_FLCC_ECC_CFG_INFOEN);
+    }
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Enable/Disable user space ECC for the device.
+ *
+ * @param [in]  hDevice  The handle to the flash controller device.
+ * @param [in]  bEnable  User space ECC enable:
+ *                           - 'true' to enable user space ECC, or
+ *                           - 'false' to disable user space ECC.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The ECC is enabled/disabled successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress.
+ *
+ * Manage enablement of user space ECC function.
+ *
+ * @note The settings this API manages are very likely not needed to be modified dynamically (at run-time).
+ * If so, consider using the static configuration equivalents (see adi_flash_config.h) in lieu of
+ * this API... which will reduce the resulting code image footprint through linker elimination.
+ *
+ * @sa adi_fee_ConfigECC().
+ * @sa adi_fee_ConfigECCEvents().
+ * @sa adi_fee_GetECCErrAddr().
+ * @sa adi_fee_GetECCCorrections().
+ */
+ADI_FEE_RESULT adi_fee_EnableECC (ADI_FEE_HANDLE const hDevice, bool const bEnable)
+{
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+#endif
+
+    /* manage flash ECC enable */
+    if (true == bEnable) {
+        SET_BITS(hDevice->pDev->ECC_CFG, BITM_FLCC_ECC_CFG_EN);
+    } else {
+        CLR_BITS(hDevice->pDev->ECC_CFG, BITM_FLCC_ECC_CFG_EN);
+    }
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Confifure ECC event response.
+ *
+ * @param [in]  hDevice     The handle to the flash controller device.
+ * @param [in]  eEvent      ECC event - Either error or correction event.
+ * @param [in]  eResponse   The response to the eEvent - One of none, bus error, or interrupt.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The ECC events are configured successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Parameters are invalid.
+ *          - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress.
+ *
+ * Configures two major aspects of ECC event response:
+ *     - On ECC (2-bit) Error events, generate one of: no response, bus error, or flash interrupt.
+ *     - On ECC (1-bit) Correction events, generate one of: no response, bus error, or flash interrupt.
+ *
+ * @note The settings this API manages are very likely not needed to be modified dynamically (at run-time).
+ * If so, consider using the static configuration equivalents (see adi_flash_config.h) in lieu of
+ * this API... which will reduce the resulting code image footprint through linker elimination.
+ *
+ * @sa adi_fee_ConfigECC().
+ * @sa adi_fee_EnableECC().
+ * @sa adi_fee_GetECCErrAddr().
+ * @sa adi_fee_GetECCCorrections().
+ */
+ADI_FEE_RESULT adi_fee_ConfigECCEvents (ADI_FEE_HANDLE const hDevice, ADI_FEE_ECC_EVENT_TYPE const eEvent, ADI_FEE_ECC_RESPONSE const eResponse)
+
+{
+    uint32_t nBitMask;
+    int32_t nBitPos;
+
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    /* reject while a transfer is in progress */
+    if (true == hDevice->bTransferInProgress) {
+        return ADI_FEE_ERR_TRANSFER_IN_PROGRESS;
+    }
+
+    /* Check the function parameters */
+    if (   (   (eEvent != ADI_FEE_ECC_EVENT_TYPE_ERROR)
+            && (eEvent != ADI_FEE_ECC_EVENT_TYPE_CORRECT))
+
+        || (   (eResponse != ADI_FEE_ECC_RESPONSE_NONE)
+            && (eResponse != ADI_FEE_ECC_RESPONSE_BUS_ERROR)
+            && (eResponse != ADI_FEE_ECC_RESPONSE_IRQ))
+        )
+    {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif
+
+    /* Select the correct bit mask and bit pos for the event type */
+    if (eEvent == ADI_FEE_ECC_EVENT_TYPE_ERROR) {
+        nBitMask = BITM_FLCC_IEN_ECC_ERROR;
+        nBitPos  = BITP_FLCC_IEN_ECC_ERROR;
+    } else {
+        nBitMask = BITM_FLCC_IEN_ECC_CORRECT;
+        nBitPos  = BITP_FLCC_IEN_ECC_CORRECT;
+    }
+
+    /* clear the bits */
+    CLR_BITS (hDevice->pDev->IEN, nBitMask);
+
+    /* set the response */
+       SET_BITS (hDevice->pDev->IEN, ((uint32_t)eResponse) << nBitPos);
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * `@brief    Get the address for which the ECC event is detected.
+ *
+ * @param [in]      hDevice     The handle to the flash controller device.
+ * @param [in,out]  pnAddress   Pointer to which the address is written.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The ECC error address is retrieved successfully.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Parameters are invalid.
+ *
+ * Returns the address of the first ECC error or correction event to generate an
+ * interrupt since the last time ECC status bits were cleared (or since reset).
+ *
+ * @sa adi_fee_ConfigECC().
+ * @sa adi_fee_EnableECC().
+ * @sa adi_fee_ConfigECCEvents().
+ * @sa adi_fee_GetECCCorrections().
+ */
+ADI_FEE_RESULT adi_fee_GetECCErrAddr (ADI_FEE_HANDLE const hDevice, uint32_t* const pnAddress)
+
+{
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    if (pnAddress == NULL) {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif
+
+    /* Write the address of the last ECC error/correction */
+    *pnAddress = hDevice->pDev->ECC_ADDR;
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/**
+ * @brief    Get the number of 1-bit error corrections.
+ *
+ * @param [in]      hDevice            The handle to the flash controller device.
+ * @param [in,out]  pnNumCorrections   Pointer to which the number of corrections are written.
+ *
+ * @return   Status
+ *          - #ADI_FEE_SUCCESS                      The number of ECC corrections are successfully retrieved.
+ *          - #ADI_FEE_ERR_INVALID_HANDLE       [D] The device handle passed is invalid.
+ *          - #ADI_FEE_ERR_INVALID_PARAM        [D] Parameters are invalid.
+ *
+ * See HRM for details on how current ECC configuration affects this reporting.
+ *
+ * @sa adi_fee_ConfigECC().
+ * @sa adi_fee_EnableECC().
+ * @sa adi_fee_ConfigECCEvents().
+ * @sa adi_fee_GetECCErrAddr().
+ */
+ADI_FEE_RESULT adi_fee_GetECCCorrections (ADI_FEE_HANDLE const hDevice, uint32_t* const pnNumCorrections)
+{
+
+#ifdef ADI_DEBUG
+    if (true != IsDeviceHandle(hDevice)) {
+        return ADI_FEE_ERR_INVALID_HANDLE;
+    }
+
+    if (pnNumCorrections == NULL) {
+        return ADI_FEE_ERR_INVALID_PARAM;
+    }
+#endif
+
+    /* Get the number of ECC Error corrections */
+    *pnNumCorrections = (hDevice->pDev->STAT & BITM_FLCC_STAT_ECCERRCNT) >> BITP_FLCC_STAT_ECCERRCNT;
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/*========  L O C A L    F U N C T I O N    D E F I N I T I O N S  ========*/
+
+
+/* Send a command to the flash controller... bot don't block on it...
+ */
+static ADI_FEE_RESULT SendCommand (ADI_FEE_HANDLE const hDevice, uint32_t const cmd)
+{
+    /* Wait for the flash to be free */
+    BusyWait (hDevice, (BITM_FLCC_STAT_CMDBUSY | BITM_FLCC_STAT_WRCLOSE));
+
+    /* Clear the command completion status bit
+     * by acknowledging it
+     */
+    hDevice->pDev->STAT = BITM_FLCC_STAT_CMDCOMP;
+
+    /* Enable command-complete and command-fail interrupt */
+    SET_BITS(hDevice->pDev->IEN, (BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL));
+
+    /* Issue the command (most commands are keyed) */
+    hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
+    hDevice->pDev->CMD = cmd;
+    hDevice->pDev->KEY = 0u;
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+static ADI_FEE_RESULT InitiatePioTransfer (ADI_FEE_HANDLE const hDevice)
+{
+
+    /* use PIO interrupt mode in non-burst-mode (burst-mode only spans 256-bytes).
+       Initiate the 1st write here, then let the interrupt handler feed
+       the remaining data as we process "almost-complete" interrupts.
+    */
+
+    /* write the 1st 64-bits of data */
+    if (0u != hDevice->nRemainingBytes) {
+
+        /* enable command interrupts */
+        SET_BITS (hDevice->pDev->IEN, (BITM_FLCC_IEN_WRALCMPLT | BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL));
+
+        /* set initial write address*/
+        hDevice->pDev->KH_ADDR = (uint32_t)hDevice->pNextWriteAddress;
+        hDevice->pNextWriteAddress += 2;
+
+        /* set key-hole data registers */
+        hDevice->pDev->KH_DATA0 = *hDevice->pNextReadAddress;
+        hDevice->pNextReadAddress++;
+        hDevice->pDev->KH_DATA1 = *hDevice->pNextReadAddress;
+        hDevice->pNextReadAddress++;
+        hDevice->nRemainingBytes -= sizeof(uint64_t);
+
+        /* write the command register which launches the burst write */
+        hDevice->pDev->CMD = ENUM_FLCC_CMD_WRITE;
+
+    } else {
+        return ADI_FEE_ERR_NO_DATA_TO_TRANSFER;
+    }
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/* DMA Transfer to FIFO */
+static ADI_FEE_RESULT InitiateDmaTransfer (ADI_FEE_HANDLE const hDevice)
+{
+    ADI_DCC_TypeDef* pCCD = pPrimaryCCD;  /* pointer to primary DMA descriptor array */
+
+    if (0u != hDevice->nRemainingBytes) {
+
+        /* local channel number */
+        uint16_t chan = hDevice->pDevInfo->dmaChanNum;
+
+        /* disable endpointer decrement modes */
+        pADI_DMA0->SRCADDR_CLR =  1u << chan;
+        pADI_DMA0->DSTADDR_CLR =  1u << chan;
+
+        /* enable the channel */
+        pADI_DMA0->EN_SET = 1u << chan;
+
+        /* allow flash to request DMA service */
+        pADI_DMA0->RMSK_CLR = 1u << chan;
+
+        /* activate primary descriptor */
+        pADI_DMA0->ALT_CLR = 1u << chan;
+
+        /* Note: DMA width is 32-bit for the flash controller, but flash writes require
+           64-bit writes at a whack.  Set DMA R_Power (bus rearbitration rate) to two so
+           we get two uninterrupted 32-bit DMA writes to the flash with each DMA transfer.
+        */
+
+        /* set DMA source endpoint */
+        pCCD += chan;  /* offset descriptor pointer to flash channel */
+        pCCD->DMASRCEND = (uint32_t)hDevice->pNextReadAddress + hDevice->nRemainingBytes - sizeof(uint32_t);
+
+        /* set DMA destination endpoint (no increment) */
+        pCCD->DMADSTEND = (uint32_t)&hDevice->pDev->KH_DATA1;
+
+        /* set the initial write address */
+        hDevice->pDev->KH_ADDR = (uint32_t)hDevice->pNextWriteAddress;
+
+        /* set the DMA Control Data Configuration register */
+        pCCD->DMACDC =
+            ( ((uint32_t)ADI_DMA_INCR_NONE                                << DMA_BITP_CTL_DST_INC)
+            | ((uint32_t)ADI_DMA_INCR_4_BYTE                              << DMA_BITP_CTL_SRC_INC)
+            | ((uint32_t)ADI_DMA_WIDTH_4_BYTE                             << DMA_BITP_CTL_SRC_SIZE)
+            | ((uint32_t)ADI_DMA_RPOWER_2                                 << DMA_BITP_CTL_R_POWER)
+            | (uint32_t)((hDevice->nRemainingBytes/sizeof(uint32_t) - 1u) << DMA_BITP_CTL_N_MINUS_1)
+            | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC                     << DMA_BITP_CTL_CYCLE_CTL) );
+
+        /* set auto-increment and DMA enable bits, launching transder */
+        hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
+        SET_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN));
+        hDevice->pDev->KEY = 0u;
+
+    } else {
+        return ADI_FEE_ERR_NO_DATA_TO_TRANSFER;
+    }
+
+    return ADI_FEE_SUCCESS;
+}
+
+
+/* Initiate transfer */
+static ADI_FEE_RESULT InitiateTransfer (ADI_FEE_HANDLE const hDevice)
+{
+    ADI_FEE_RESULT result = ADI_FEE_SUCCESS;
+
+    /* If a transfer is in progress or if the pending buffers are empty
+     * the return as there is nothing to be done now
+     */
+    if (true == hDevice->bTransferInProgress)
+    {
+        return ADI_FEE_ERR_DEVICE_BUSY;
+    }
+
+    /* Wait for the flash to not be busy */
+    BusyWait (hDevice, BITM_FLCC_STAT_CMDBUSY);
+
+    /* clear internal errors */
+    hDevice->feeError = 0u;
+    hDevice->dmaError = ADI_FEE_SUCCESS;
+
+    /* Set the bool variable to signify that a transfer is in progress */
+    hDevice->bTransferInProgress = true;
+
+    /* clear any command interrupt enables */
+    CLR_BITS(hDevice->pDev->IEN,  (BITM_FLCC_IEN_WRALCMPLT | BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL));
+
+    /* clear any dangeling command-related status */
+    hDevice->pDev->STAT = BITM_FLCC_STAT_WRALCOMP | BITM_FLCC_STAT_CMDCOMP | BITM_FLCC_STAT_CMDFAIL;
+
+    /* clear auto-increment and dma enable bits */
+    hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
+    CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN));
+    hDevice->pDev->KEY = 0u;
+
+    /* Call the corresponding Transfer functions */
+    if (true == hDevice->bUseDma) {
+        result = InitiateDmaTransfer(hDevice);
+    } else {
+        result = InitiatePioTransfer(hDevice);
+    }
+
+    return result;
+}
+
+
+/* hide the interrupt handlers from DoxyGen */
+/*! \cond PRIVATE */
+
+/* Flash PIO interrupt handler */
+void Flash0_Int_Handler(void)
+{
+    ISR_PROLOG();
+
+    /* post flag */
+    bool bPost = false;
+    bool bError = false;
+
+    /* recover the driver handle */
+    ADI_FEE_HANDLE hDevice = fee_device_info[0].hDevice;
+
+#ifdef ADI_DEBUG
+    /* Return if the device is not opened - spurious interrupts */
+    if (hDevice == NULL) {
+        return;
+    }
+#endif
+
+    /* update status cache and clear it right away on the controller */
+    hDevice->FlashStatusCopy = hDevice->pDev->STAT;
+    hDevice->pDev->STAT = hDevice->FlashStatusCopy;
+
+    /* check for flash device errors */
+    hDevice->feeError = (ADI_FEE_STATUS_ERROR_MASK & hDevice->FlashStatusCopy);
+    if (0u != hDevice->feeError) {
+        bError = true;
+    }
+
+    /* if no errors */
+    if (false == bError) {
+
+        if (0u != (BITM_FLCC_STAT_WRALCOMP & hDevice->FlashStatusCopy)) {
+
+            /* write-almost-complete */
+
+            /* if more data to write... */
+            if (0u != hDevice->nRemainingBytes) {
+
+                /* set next write the address */
+                hDevice->pDev->KH_ADDR = (uint32_t)hDevice->pNextWriteAddress;
+                hDevice->pNextWriteAddress += 2;
+
+                /* set next key-hole data */
+                hDevice->pDev->KH_DATA0 = *hDevice->pNextReadAddress;
+                hDevice->pNextReadAddress++;
+                hDevice->pDev->KH_DATA1 = *hDevice->pNextReadAddress;
+                hDevice->pNextReadAddress++;
+                hDevice->nRemainingBytes -= sizeof(uint64_t);
+
+                /* initiate next write */
+                hDevice->pDev->CMD = ENUM_FLCC_CMD_WRITE;
+
+            } else {
+
+                /* no more data to write...
+                   wait for current write-almost-complete status to transition to not busy */
+                BusyWait (hDevice, BITM_FLCC_STAT_CMDBUSY);
+
+                /* set post flag */
+                bPost = true;
+            }
+
+        } else if (0u != (BITM_FLCC_STAT_CMDCOMP & hDevice->FlashStatusCopy)) {
+
+            /* command-complete */
+
+            /* this path is for blocking-mode commands (erase, verify, abort, etc.) */
+
+            /* set post flag */
+            bPost = true;
+
+        } else {
+            /* no other interrupt types expected */
+        }
+    } else {
+        /* error(s) detected... set the post flag */
+        bPost = true;
+    }
+
+    /* singular post */
+    if (true == bPost) {
+
+        /* clear the command interrupt enables */
+        CLR_BITS(hDevice->pDev->IEN,  (BITM_FLCC_IEN_WRALCMPLT | BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL));
+
+        /* clear auto-increment and dma enable bits */
+        hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
+        CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN));
+        hDevice->pDev->KEY = 0u;
+
+        /* mark transfer complete */
+        hDevice->bTransferInProgress = false;
+
+        /* dispatch callback (if we have one...) */
+        if (0u != hDevice->pfCallback) {
+            if (false == bError) {
+                /* no error, pass success flag to callback */
+                hDevice->pfCallback (hDevice->pCBParam, (uint32_t)ADI_FEE_CALLBACK_EVENT_BUFFER_PROCESSED, (void*)NULL);
+            } else {
+                /* error condition, pass error flag and error status to callback */
+                hDevice->pfCallback (hDevice->pCBParam, (uint32_t)ADI_FEE_CALLBACK_EVENT_DEVICE_ERROR, (void*)hDevice->feeError);
+            }
+        }
+
+        /* post the semaphore */
+        SEM_POST(hDevice);
+    }
+
+    ISR_EPILOG();
+}
+
+
+/* Flash DMA interrupt handler */
+void DMA_FLASH0_Int_Handler (void)
+{
+    /* rtos prologue */
+    ISR_PROLOG()
+        ;
+
+    /* recover the driver handle */
+    ADI_FEE_HANDLE hDevice = fee_device_info[0].hDevice;
+
+    /* update status cache and clear it right away on the controller */
+    hDevice->FlashStatusCopy = hDevice->pDev->STAT;
+    hDevice->pDev->STAT = hDevice->FlashStatusCopy;
+
+    /* capture any hw error status */
+    hDevice->feeError = (ADI_FEE_STATUS_ERROR_MASK & hDevice->FlashStatusCopy);
+
+    /* clear auto-increment and dma enable bits */
+    hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY;
+    CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN));
+    hDevice->pDev->KEY = 0u;
+
+    /* clear the remaining count, as it should all have gone in one swoop */
+    hDevice->nRemainingBytes = 0u;
+
+    /* mark transfer complete */
+    hDevice->bTransferInProgress = false;
+
+    /* dispatch callback (if we have one...) */
+    if (0u != hDevice->pfCallback) {
+
+        /* no errors, notify success */
+        if ((0u == hDevice->feeError) && (0u == hDevice->dmaError)) {
+            hDevice->pfCallback (hDevice->pCBParam, (uint32_t)ADI_FEE_CALLBACK_EVENT_BUFFER_PROCESSED, (void*)NULL);
+
+        /* flash hardware error */
+        } else if (0u == hDevice->feeError) {
+            hDevice->pfCallback (hDevice->pCBParam, (uint32_t)ADI_FEE_CALLBACK_EVENT_DEVICE_ERROR, (void*)hDevice->feeError);
+
+        /* flash dma error */
+        } else if (0u == hDevice->dmaError) {
+            /* DMA error */
+            hDevice->pfCallback (hDevice->pCBParam, (uint32_t)hDevice->dmaError, NULL);
+        } else {
+            /* no other cases... */
+        }
+    }
+
+    /* post the semaphore */
+    SEM_POST(hDevice);
+
+    ISR_EPILOG();
+}
+
+/*! \endcond */
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_data.c
new file mode 100755
index 00000000000..d5b6027573f
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_data.c
@@ -0,0 +1,116 @@
+/*
+ *****************************************************************************
+ * @file:    adi_flash_data.c
+ * @brief:   Data declaration for Flash Device Driver
+ * @date:    $Date$
+ *****************************************************************************
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be consciously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_FEE_DATA_C
+#define ADI_FEE_DATA_C
+
+ /*! \cond PRIVATE */
+
+#include <adi_processor.h>
+#include "adi_flash_def.h"
+#include "adi_flash_config.h"
+
+/* Stores the information about the specific device */
+static ADI_FEE_DEVICE_INFO fee_device_info [ADI_FEE_NUM_INSTANCES] =
+{
+    /* only one flash instance at this time */
+    {    pADI_FLCC0,            /* Flash controller pointer         */
+        FLCC_EVT_IRQn,          /* Flash PIO interrupt number       */
+        DMA0_CH15_DONE_IRQn,    /* Flash DMA interrupt number       */
+        FLASH_CHANn,            /* Flash DMA channel (15) number    */
+        NULL,                   /* Flash static config info         */
+        NULL                    /* Flash driver handle              */
+    },
+};
+
+
+/* build Flash Application configuration array */
+static ADI_FEE_CONFIG gConfigInfo[ADI_FEE_NUM_INSTANCES] =
+{
+    /* the one-and-only (so far) instance data for FEE0... */
+    {
+        /* ECC interrupt enable settings (IEN register) */
+        ( (ADI_FEE_CFG_ECC_ERROR_RESPONSE      << BITP_FLCC_IEN_ECC_ERROR)
+        | (ADI_FEE_CFG_ECC_CORRECTION_RESPONSE << BITP_FLCC_IEN_ECC_CORRECT)
+        ),
+
+        /* timing parameter settings (TIME_PARAM0 register) */
+        ( (ADI_FEE_CFG_PARAM0_TNVH1            << BITP_FLCC_TIME_PARAM0_TNVH1)
+        | (ADI_FEE_CFG_PARAM0_TERASE           << BITP_FLCC_TIME_PARAM0_TERASE)
+        | (ADI_FEE_CFG_PARAM0_TRCV             << BITP_FLCC_TIME_PARAM0_TRCV)
+        | (ADI_FEE_CFG_PARAM0_TNVH             << BITP_FLCC_TIME_PARAM0_TNVH)
+        | (ADI_FEE_CFG_PARAM0_TPROG            << BITP_FLCC_TIME_PARAM0_TPROG)
+        | (ADI_FEE_CFG_PARAM0_TPGS             << BITP_FLCC_TIME_PARAM0_TPGS)
+        | (ADI_FEE_CFG_PARAM0_TNVS             << BITP_FLCC_TIME_PARAM0_TNVS)
+        | (ADI_FEE_CFG_PARAM0_CLKDIV           << BITP_FLCC_TIME_PARAM0_DIVREFCLK)
+        ),
+
+        /* more timing parameter settings (TIME_PARAM1 register) */
+        ( (ADI_FEE_CFG_PARAM1_WAITESTATES      << BITP_FLCC_TIME_PARAM1_WAITSTATES)
+        | (ADI_FEE_CFG_PARAM1_TWK              << BITP_FLCC_TIME_PARAM1_TWK)
+        ),
+
+        /* system interrupt abort enables (ABORT_EN_XX registers) */
+        (ADI_FEE_CFG_ABORT_EN_LO),
+        (ADI_FEE_CFG_ABORT_EN_HI),
+
+        /* ECC configuration register settings (ECC_CFG register) */
+        (((ADI_FEE_CFG_ECC_START_PAGE          << FEE_PAGE_SHIFT) & BITM_FLCC_ECC_CFG_PTR)
+#if (ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE == 1u)
+        | (BITM_FLCC_ECC_CFG_INFOEN)
+#endif
+#if (ADI_FEE_CFG_ENABLE_ECC == 1u)
+        | (BITM_FLCC_ECC_CFG_EN)
+#endif
+        )
+    }  /* end device 0 settings */
+};
+
+/*! \endcond */
+
+
+#endif /* ADI_FEE_DATA_C */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_def.h
new file mode 100755
index 00000000000..c14be74be09
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_def.h
@@ -0,0 +1,181 @@
+/*!
+ *****************************************************************************
+ @file:    adi_flash_def.h
+ @brief:   Internal Flash device driver definitions and macros
+ @date:    $Date: 2014-11-28 01:48:03 -0500 (Fri, 28 Nov 2014) $
+ -----------------------------------------------------------------------------
+Copyright (c) 2012-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_FLASH_DEF_H
+#define ADI_FLASH_DEF_H
+
+/*! \cond PRIVATE */
+
+#include <drivers/dma/adi_dma.h>
+#include <config/adi_flash_config.h>
+
+#include <drivers/flash/adi_flash.h>
+
+/* fixed number of flash controllers */
+#define ADI_FEE_NUM_INSTANCES       (1u)
+
+/* STATUS register error mask */
+#define ADI_FEE_STATUS_ERROR_MASK ( BITM_FLCC_STAT_ACCESS_MODE    \
+                                  | BITM_FLCC_STAT_CACHESRAMPERR  \
+                                  | BITM_FLCC_STAT_ECCDCODE       \
+                                  | BITM_FLCC_STAT_ECCINFOSIGN    \
+                                  | BITM_FLCC_STAT_SIGNERR        \
+                                  | BITM_FLCC_STAT_OVERLAP        \
+                                  | BITM_FLCC_STAT_ECCRDERR       \
+                                  | BITM_FLCC_STAT_ECCERRCMD      \
+                                  | BITM_FLCC_STAT_SLEEPING       \
+                                  | BITM_FLCC_STAT_CMDFAIL)
+
+
+#if defined(__ECC__)
+#define ALIGN
+#define ALIGN4  _Pragma("align(4)")
+#elif defined(__ICCARM__)
+#define ALIGN   _Pragma("pack()")
+#define ALIGN4  _Pragma("pack(4)")
+#elif defined (__GNUC__)
+#define ALIGN   _Pragma("pack()")
+#define ALIGN4  _Pragma("pack(4)")
+#endif
+
+/* Flash Size and Page/Block macros:
+    512kB total user space, broken up as
+        256-pages, 2kB/page
+        32-blocks, 16kB/block
+        8 pages/block
+*/
+#define FEE_FLASH_SIZE     (0x80000u)                          /* 512kB total */
+#define FEE_PAGE_SHIFT     (11u)                               /* 2kB page size */
+#define FEE_BLOCK_SHIFT    (14u)                               /* 16kB block size */
+#define FEE_MAX_NUM_PAGES  (FEE_FLASH_SIZE >> FEE_PAGE_SHIFT)  /* max number of pages (256) */
+#define FEE_MAX_NUM_BLOCKS (FEE_FLASH_SIZE >> FEE_BLOCK_SHIFT) /* max number of blocks (32) */
+
+#if (ADI_FEE_CFG_ECC_START_PAGE >= FEE_MAX_NUM_PAGES)
+#error "ADI_FEE_CFG_ECC_START_PAGE range is invalid"
+#endif
+
+
+/* INTERNAL DRIVER STATIC FUNCTION PROTOTYPES */
+
+/* Send a command to the flash controller, but does no pend on it... */
+static ADI_FEE_RESULT SendCommand (ADI_FEE_HANDLE const hDevice, uint32_t const cmd);
+
+/* generic transfer initiator... dispatches to InitiatePioTransfer() or InitiateDmaTransfer() */
+static ADI_FEE_RESULT InitiateTransfer (ADI_FEE_HANDLE const hDevice);
+
+/* PIO initiator */
+static ADI_FEE_RESULT InitiatePioTransfer (ADI_FEE_HANDLE const hDevice);
+
+/* DMA initiator */
+static ADI_FEE_RESULT InitiateDmaTransfer (ADI_FEE_HANDLE const hDevice);
+
+/* interrupt handlers */
+void Flash0_Int_Handler(void);
+void DMA_FLASH0_Int_Handler (void);
+
+/* INTERNAL DRIVER DATATYPES */
+
+/*
+ *****************************************************************************
+ * FEE Configuration structure.
+ *****************************************************************************/
+typedef struct __ADI_FEE_CONFIG {
+    uint32_t eccIrqEnables;     	/* ECC interrupt enables.                      */
+    uint32_t param0;            	/* TIME_PARAM0 register.                       */
+    uint32_t param1;            	/* TIME_PARAM1 register.                       */
+    uint32_t abortEnableLo;     	/* Lower interrupt abort enables (IRQs 0-31).  */
+    uint32_t abortEnableHi;     	/* Upper interrupt abort enables (IRQs 32-63.) */
+    uint32_t eccConfig;         	/* ECC_CFG register.                           */
+} ADI_FEE_CONFIG;
+
+
+/* Flash physical device instance data */
+typedef struct __ADI_FEE_DEVICE_INFO {
+
+   ADI_FLCC_TypeDef *pDev;       	/* Pointer to the physical controller.         */
+   IRQn_Type         pioIrqNum;  	/* The flash controller PIO interrupt number.  */
+   IRQn_Type         dmaIrqNum;  	/* The flash controller DMA interrupt number.  */
+   DMA_CHANn_TypeDef dmaChanNum;	/* The flash controller DMA channel number.    */
+   ADI_FEE_CONFIG   *pConfig;    	/* Pointer to user config info.                */
+   ADI_FEE_HANDLE    hDevice;    	/* Pointer the device memory (supplied by the application). */
+
+} ADI_FEE_DEVICE_INFO;
+
+
+/* Flash driver instance data structure */
+typedef struct __ADI_FEE_DEV_DATA_TYPE {
+
+    /* make sure to synchronize ANY size changes with ADI_FLASH_MEMORY_SIZE macro in adi_flash.h */
+
+    /* NOTE: "volatile" storage class on all interrupt-modified valuables */
+
+    /* device attributes */
+    ADI_FLCC_TypeDef           *pDev;					/* Pointer top physical flash controller.        */
+    ADI_FEE_DEVICE_INFO        *pDevInfo;				/* Pointer to hardware device attributes.        */
+
+    /* callback info */
+    ADI_CALLBACK                pfCallback;				/* Registered callback function address.         */
+    void                       *pCBParam;				/* Registered callback user parameter.           */
+
+    /* internal driver state variables */
+    bool                        bUseDma;				/* DMA control flag (from user).                 */
+    bool                        bSubmitCalled;			/* Flag to identify if a buffer was "submitted". */
+    volatile uint32_t           FlashStatusCopy;		/* Clop of latest flash status register.         */
+    volatile uint32_t           feeError;				/* Flash error collector.                        */
+    volatile ADI_FEE_RESULT     dmaError;				/* DMA error collector.                          */
+    volatile bool               bTransferInProgress;	/* Flag indicating if a transfer is in progress. */
+
+    /* data info */
+    volatile uint32_t          *pNextWriteAddress;      /* Pointer to next write data in flash space.    */
+    volatile uint32_t          *pNextReadAddress;       /* Pointer to next read data in user buffer.     */
+    volatile uint32_t           nRemainingBytes;        /* Number of remaining bytes still to transfer.  */
+
+    SEM_VAR_DECLR        /* Blocking object: "Semaphore" for rtos,  "bLowPowerExitFlag" for non-rtos.    */
+
+} ADI_FEE_DEV_DATA_TYPE;
+
+/*! \endcond */
+
+#endif /* ADI_FLASH_DEF_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/gpio/adi_gpio.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/gpio/adi_gpio.c
new file mode 100755
index 00000000000..3725f72ead5
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/gpio/adi_gpio.c
@@ -0,0 +1,975 @@
+/*
+ *****************************************************************************
+   @file:    adi_gpio.c
+   @brief:   GPIO device driver implementation.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+/*****************************************************************************/
+
+#include <stddef.h>
+#include <string.h>
+#include <assert.h>
+#include <drivers/gpio/adi_gpio.h>
+#include <rtos_map/adi_rtos_map.h>
+#include "adi_gpio_def.h"
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
+*   This isn't a header as such.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+*
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   The rule makes an exception for memory-mapped register accesses.
+*/
+#pragma diag_suppress=Pm123,Pm073,Pm143,Pm140
+#endif /* __ICCARM__ */
+
+/* Debug function declarations */
+#ifdef ADI_DEBUG
+static bool ArePinsValid      (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins);   /*!< tests for pins validity */
+#endif /* ADI_DEBUG */
+
+
+static void CommonInterruptHandler  (const ADI_GPIO_IRQ_INDEX index, const IRQn_Type eIrq);
+void GPIO_A_Int_Handler(void);
+void GPIO_B_Int_Handler(void);
+
+/*==========  D A T A  ==========*/
+static ADI_GPIO_DRIVER adi_gpio_Device =
+{
+    {
+       pADI_GPIO0,       /* port 0 base address */
+       pADI_GPIO1,       /* port 1 base address */
+       pADI_GPIO2,       /* port 2 base address */
+	   pADI_GPIO3,		 /* port 3 base address */
+    },
+    
+    NULL
+};
+/*! \endcond */
+
+/*! \addtogroup GPIO_Driver GPIO Driver
+ *  @{
+
+  @brief    GPIO port and pin identifiers
+  @note The application must include drivers/gpio/adi_gpio.h to use this driver
+  @details  The documented macros can be passed to the following functions:
+      - adi_gpio_OutputEnable()
+      - adi_gpio_PullUpEnable()
+      - adi_gpio_SetHigh()
+      - adi_gpio_SetLow()
+      - adi_gpio_Toggle()
+      - adi_gpio_SetData()
+      - adi_gpio_GetData()
+
+      To control a single GPIO, these macros can be passed to the functions one
+      at a time. For example, to set the GPIO on port 2, pin 4 to a logical high
+      level, the following is used:
+
+      <pre>
+      adi_gpio_SetHigh(ADI_GPIO_PORT2, ADI_GPIO_PIN_4)
+      </pre>
+
+      Multiple GPIOs, so long as they reside on the same port, can be controlled
+      simultaneously. These macros can be OR-ed together and passed to the
+      functions. For example, to set the GPIOs on port 2, pins 3, 4 and 7 to
+      a logical low level, the following is used:
+
+      <pre>
+      adi_gpio_SetLow(ADI_GPIO_PORT2, ADI_GPIO_PIN_3 | ADI_GPIO_PIN_4 | ADI_GPIO_PIN_7)
+      </pre>
+
+      For the sensing, or adi_gpio_Getxxx, functions, the passed pValue parameter is written with
+      a packed value containing the status of the requested GPIO pins on the given port.
+
+      If information is required for a single pin, return value can be directly used
+      For example to see if pin 4 on port 2 has the pull up enabled, the following is used:
+      adi_gpio_GetData(ADI_GPIO_PORT2, ADI_GPIO_PIN_4, &pValue)
+      pValue will contain the required information.
+
+      If information is required for multiple pins, following method is required:
+      <pre>
+        adi_gpio_GetData(ADI_GPIO_PORT2, (ADI_GPIO_PIN_3 | ADI_GPIO_PIN_4 | ADI_GPIO_PIN_7), &pValue)
+      </pre>
+      To test if pin 4 on port 2 has pull up enabled, the following is used:
+      <pre>
+        if   (pValue & ADI_GPIO_PIN_4) {
+                    the pull up is enabled for pin 4 on port 2
+        } else {
+                    the pull up is disabled for pin 4 on port 2
+        }
+      </pre>
+
+ */
+
+/*!
+    @brief      Initializes the GPIO functions.
+
+    @details    This function initializes the GPIO driver. This function should be called before calling any of the GPIO
+                driver APIs.
+
+    @param[in] pMemory      Pointer to the memory required for the driver to operate.
+                            The size of the memory should be at least #ADI_GPIO_MEMORY_SIZE bytes.
+                            
+    @param[in] MemorySize   Size of the memory (in bytes) passed in pMemory parameter.
+
+    @return     Status
+                    - ADI_GPIO_SUCCESS                  If successfully initialized the GPIO driver.
+                    - ADI_GPIO_NULL_PARAMETER       [D] If the given pointer to the driver memory is pointing to NULL.
+                    - ADI_GPIO_INVALID_MEMORY_SIZE  [D] If the given memory size is not sufficient to operate the driver. 
+
+    @note       This function clears memory reserved for managing the callback function when it is called 
+                for the first time. It is expected from user to call "adi_gpio_UnInit" function when the GPIO service is no longer required.
+
+    @sa         adi_gpio_UnInit
+*/
+ADI_GPIO_RESULT adi_gpio_Init(
+    void*                const pMemory,
+    uint32_t             const MemorySize
+)
+{
+
+#ifdef ADI_DEBUG
+        /* Verify the given memory pointer */
+        if(NULL == pMemory)
+        {
+            return ADI_GPIO_NULL_PARAMETER;
+        }
+        /* Check if the memory size is sufficient to operate the driver */ 
+        if(MemorySize < ADI_GPIO_MEMORY_SIZE)
+        {
+            return ADI_GPIO_INVALID_MEMORY_SIZE;
+        }
+        assert(ADI_GPIO_MEMORY_SIZE == sizeof(ADI_GPIO_DEV_DATA));
+#endif
+
+    /* Only initialize on 1st init call, i.e., preserve callbacks on multiple inits */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        uint32_t i;
+
+        adi_gpio_Device.pData = (ADI_GPIO_DEV_DATA*)pMemory;
+
+        /* Initialize the callback table */
+        for (i = 0u; i < ADI_GPIO_NUM_INTERRUPTS; i++)
+        {
+            adi_gpio_Device.pData->CallbackTable[i].pfCallback = NULL;
+            adi_gpio_Device.pData->CallbackTable[i].pCBParam   = NULL;
+        }
+        
+        /* Enable the group interrupts */
+        NVIC_EnableIRQ(SYS_GPIO_INTA_IRQn);
+        NVIC_EnableIRQ(SYS_GPIO_INTB_IRQn);
+    }
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+    @brief      Un-initialize the GPIO driver.
+
+    @details    Terminates the GPIO functions, leaving everything unchanged.
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS if successfully uninitialized
+                    - #ADI_GPIO_NOT_INITIALIZED [D] if not yet initialized
+
+    @sa         adi_gpio_Init
+*/
+ADI_GPIO_RESULT adi_gpio_UnInit(void)
+{
+
+#ifdef ADI_DEBUG
+    /* IF (not initialized) */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        /* return error if not initialized */
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+#endif
+    
+    /* Clear the data pointer */
+    adi_gpio_Device.pData = NULL;
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+    @brief      Group the pins for the given group interrupt.
+
+    @details    Group the given pins for the Group A/B interrupt.
+                Applications can register/unregister a callback using the #adi_gpio_RegisterCallback API
+                to get a notification when the group interrupt occurs.
+
+    @param[in]  Port   GPIO port number to be operated on.
+    @param[in]  eIrq   Interrupt (Group A/B) to which the pin(s) are to be grouped.
+    @param[in]  Pins   The GPIO pins which needs to be grouped.
+                           Pin bits that are set enable the interrupt for the group A/B.
+                           Pin bits that are clear disable the interrupt for the group A/B.
+    @return     Status
+                    - #ADI_GPIO_SUCCESS                 If successfully grouped the given pins.
+                    - #ADI_GPIO_NOT_INITIALIZED     [D] If GPIO driver is not yet initialized.
+                    - #ADI_GPIO_INVALID_PINS        [D] The given pins are invalid.
+
+    @sa         adi_gpio_RegisterCallback
+    @sa         adi_gpio_SetGroupInterruptPolarity
+*/
+ADI_GPIO_RESULT adi_gpio_SetGroupInterruptPins(const ADI_GPIO_PORT Port, const ADI_GPIO_IRQ eIrq, const ADI_GPIO_DATA Pins)
+{
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+    ADI_INT_STATUS_ALLOC();
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+
+    /* validate the pins */
+    if (!ArePinsValid(Port, Pins))
+    {
+        return (ADI_GPIO_INVALID_PINS);
+    }
+#endif
+
+    pPort = adi_gpio_Device.pReg[Port];
+
+    ADI_ENTER_CRITICAL_REGION();
+    switch (eIrq)
+    {
+        case SYS_GPIO_INTA_IRQn:
+            pPort->IENA = Pins;
+            break;
+        case SYS_GPIO_INTB_IRQn:
+            pPort->IENB = Pins;
+            break;
+        default:
+            break; /* This shall never reach */
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+    @brief      Set the interrupt polarity for the given pins.
+
+    @details    Sets the interrupt polarity for the given pins for the given port.
+                When the corresponding bit is set an interrupt is generated when the pin transitions from low-to-high. When the corresponding bit is cleared an interrupt is generated when the pin transitions from high-to-low.
+
+    @param[in]  Port   GPIO port number to be operated on.
+    @param[in]  Pins   Pins whose polarity to be set.
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS             If successfully set the polarity.
+                    - #ADI_GPIO_NOT_INITIALIZED [D] If not yet initialized.
+                    - #ADI_GPIO_INVALID_PINS    [D] If the given pins are invalid.
+
+    @sa         adi_gpio_RegisterCallback
+    @sa         adi_gpio_SetGroupInterruptPins
+*/
+ADI_GPIO_RESULT adi_gpio_SetGroupInterruptPolarity(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins)
+{
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+
+    /* validate the pins */
+    if (!ArePinsValid(Port, Pins))
+    {
+        return (ADI_GPIO_INVALID_PINS);
+    }
+#endif
+
+    pPort = adi_gpio_Device.pReg[Port];
+
+    pPort->POL = Pins;
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+    @brief      Enables/Disables the Output Drivers for GPIO Pin(s)
+
+    @details    Enables/disables the output drivers for the given GPIO pin(s) on
+                the given port.
+
+    @param[in]  Port    The GPIO port to be configured.
+    @param[in]  Pins    One or more GPIO pins to be configured. GPIO
+                        pins can be passed one at a time or in combination. To
+                        configure a single GPIO pin, a single GPIO value is
+                        passed for this parameter. For example, #ADI_GPIO_PIN_4.
+                        Alternatively, multiple GPIO pins can be configured
+                        simultaneously by OR-ing together GPIO pin values and
+                        passing the resulting value for this parameter. For
+                        example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6.
+    @param[in]  bFlag   Boolean value describing the action to be taken
+                            - true      enables the output driver
+                            - false     disables the output driver
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS             If successfully configured
+                    - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized.
+                    - #ADI_GPIO_INVALID_PINS    [D] If the given pins are invalid.
+*/
+ADI_GPIO_RESULT adi_gpio_OutputEnable(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag)
+{
+
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+    ADI_INT_STATUS_ALLOC();
+    
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+
+    /* validate the pins */
+    if (!ArePinsValid(Port, Pins))
+    {
+        return (ADI_GPIO_INVALID_PINS);
+    }
+#endif
+
+    pPort = adi_gpio_Device.pReg[Port];
+
+    ADI_ENTER_CRITICAL_REGION();
+    if (bFlag)
+    {
+        /* enable output */
+        pPort->OEN |= Pins;
+    } else
+    {
+        /* disable output */
+        pPort->OEN &= (uint16_t)~Pins;
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+    @brief      Enables/Disables the Input Drivers for GPIO Pin(s)
+
+    @details    Enables/disables the input drivers for the given GPIO pin(s) on
+                the given port.
+
+    @param[in]  Port    The GPIO port to be configured.
+    @param[in]  Pins    One or more GPIO pins to be configured. GPIO
+                        pins can be passed one at a time or in combination. To
+                        configure a single GPIO pin, a single GPIO value is
+                        passed for this parameter. For example, #ADI_GPIO_PIN_4.
+                        Alternatively, multiple GPIO pins can be configured
+                        simultaneously by OR-ing together GPIO pin values and
+                        passing the resulting value for this parameter. For
+                        example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6.
+
+    @param[in]  bFlag   Boolean value describing the action to be taken
+                            - true      enables the input driver
+                            - false     disables the input driver
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS             If successfully configured.
+                    - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized.
+                    - #ADI_GPIO_INVALID_PINS    [D] If the given pins are invalid.
+*/
+ADI_GPIO_RESULT adi_gpio_InputEnable(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag)
+{
+
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+    ADI_INT_STATUS_ALLOC();
+    
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData) {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+
+    /* validate the pins */
+    if (!ArePinsValid(Port, Pins)) {
+        return (ADI_GPIO_INVALID_PINS);
+    }
+#endif
+
+    pPort = adi_gpio_Device.pReg[Port];
+
+    ADI_ENTER_CRITICAL_REGION();
+    if (bFlag)
+    {
+        /* enable input */
+        pPort->IEN |= Pins;
+    } else
+    {
+        /* disable input */
+        pPort->IEN &= (uint16_t)~Pins;
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+    @brief      Enables/Disables the Pull-Up for GPIO Pin(s)
+
+    @details    Enables/disables the internal pull-up for the given GPIO pin(s) on
+                the given port.  API simply enables/disables whatever the hard-wired
+                pulls (up/down) are.
+
+    @param[in]  Port    The GPIO port to be configured.
+    @param[in]  Pins    One or more GPIO pins to be configured. GPIO
+                        pins can be passed one at a time or in combination. To
+                        configure a single GPIO pin, a single GPIO value is
+                        passed for this parameter. For example, #ADI_GPIO_PIN_4.
+                        Alternatively, multiple GPIO pins can be configured
+                        simultaneously by OR-ing together GPIO pin values and
+                        passing the resulting value for this parameter. For
+                        example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6.
+    @param[in]  bFlag   Boolean value describing the action to be taken
+                            - true      enables the pull-up
+                            - false     disables the pull-up
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS             If successfully configured.
+                    - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized.
+                    - #ADI_GPIO_INVALID_PINS    [D] If the given pins are invalid.
+*/
+ADI_GPIO_RESULT adi_gpio_PullUpEnable(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag)
+{
+
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+    ADI_INT_STATUS_ALLOC();
+    
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+
+    /* validate the pins */
+    if (!ArePinsValid(Port, Pins))
+    {
+        return (ADI_GPIO_INVALID_PINS);
+    }
+#endif
+
+    pPort = adi_gpio_Device.pReg[Port];
+
+    ADI_ENTER_CRITICAL_REGION();
+    if (bFlag)
+    {
+        pPort->PE |= Pins;
+    } else
+    {
+        pPort->PE &= (uint16_t)(~Pins);
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+/*!
+
+    @brief      Sets the Given GPIO pin(s) to a Logical High Level
+
+    @details    Sets the given GPIO pin(s) on the given port to a logical high
+                level.
+
+    @param[in]  Port    GPIO port whose pins need to be set to logical high level.
+    @param[in]  Pins    One or more GPIO pins to be set to logical high. GPIO
+                        pins can be passed one at a time or in combination. To
+                        configure a single GPIO pin, a single GPIO value is
+                        passed for this parameter. For example, #ADI_GPIO_PIN_4.
+                        Alternatively, multiple GPIO pins can be configured
+                        simultaneously by OR-ing together GPIO pin values and
+                        passing the resulting value for this parameter. For
+                        example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6.
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS             If successfully configured.
+                    - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized.
+                    - #ADI_GPIO_INVALID_PINS    [D] If the given pins are invalid.
+
+    @sa         adi_gpio_SetLow, adi_gpio_Toggle, adi_gpio_SetData, adi_gpio_GetData
+*/
+ADI_GPIO_RESULT adi_gpio_SetHigh(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins)
+{
+
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+
+    /* validate the pins */
+    if (!ArePinsValid(Port, Pins))
+    {
+        return (ADI_GPIO_INVALID_PINS);
+    }
+#endif
+
+    pPort = adi_gpio_Device.pReg[Port];
+
+    /* set the given GPIOs high */
+    pPort->SET = Pins;
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+
+    @brief      Sets the Given GPIO pin(s) to a Logical Low Level
+
+    @details    Sets the given GPIO pin(s) on the given port to a logical low
+                level.
+
+    @param[in]  Port    The GPIO port whose pins need to be set to logical low level.
+    @param[in]  Pins    One or more GPIO pins to be whose logic level to be set. GPIO
+                        pins can be passed one at a time or in combination. To
+                        configure a single GPIO pin, a single GPIO value is
+                        passed for this parameter. For example, #ADI_GPIO_PIN_4.
+                        Alternatively, multiple GPIO pins can be configured
+                        simultaneously by OR-ing together GPIO pin values and
+                        passing the resulting value for this parameter. For
+                        example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6.
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS             If successfully configured.
+                    - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized.
+                    - #ADI_GPIO_INVALID_PINS    [D] If the given pins are invalid.
+
+    @sa         adi_gpio_SetHigh, adi_gpio_Toggle, adi_gpio_SetData, adi_gpio_GetData
+*/
+ADI_GPIO_RESULT adi_gpio_SetLow(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins)
+{
+
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+
+    /* validate the pins */
+    if (!ArePinsValid(Port, Pins))
+    {
+        return (ADI_GPIO_INVALID_PINS);
+    }
+#endif
+
+    pPort = adi_gpio_Device.pReg[Port];
+
+    /* set the given GPIOs low */
+    pPort->CLR = Pins;
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+
+    @brief      Toggles the Logical Level of the Given GPIO pin(s)
+
+    @details    Toggles the logical level of the given GPIO pin(s) on the given port.
+                If a given GPIO pin is at a logical low level, this function will
+                change the level to a logical high value. If a given GPIO pin is
+                at a logical high level, this function will change the level to a
+                logical low value.
+
+    @param[in]  Port    The GPIO port whose pins to be toggled.
+    @param[in]  Pins    The GPIO pins whose logic level to be toggled. GPIO
+                        pins can be passed one at a time or in combination. To
+                        configure a single GPIO pin, a single GPIO value is
+                        passed for this parameter. For example, #ADI_GPIO_PIN_4.
+                        Alternatively, multiple GPIO pins can be configured
+                        simultaneously by OR-ing together GPIO pin values and
+                        passing the resulting value for this parameter. For
+                        example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6.
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS             If successfully configured.
+                    - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized.
+                    - #ADI_GPIO_INVALID_PINS    [D] If the given pins are invalid.
+
+    @sa         adi_gpio_SetHigh, adi_gpio_SetLow, adi_gpio_SetData, adi_gpio_GetData
+*/
+ADI_GPIO_RESULT adi_gpio_Toggle(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins)
+{
+
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+
+    /* validate the pins */
+    if (!ArePinsValid(Port, Pins))
+    {
+        return (ADI_GPIO_INVALID_PINS);
+    }
+#endif
+
+    pPort = adi_gpio_Device.pReg[Port];
+
+    /* toggle the given GPIOs */
+    pPort->TGL = Pins;
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+
+    @brief      Sets the logic level of all GPIO pins on the given port to
+                a given logic level.
+
+    @details    Sets the logic level of all the GPIO pins on the given port to the
+                given value.
+
+    @param[in]  Port    The GPIO port whose pins logic level to be set.
+    @param[in]  Pins    The GPIO pins whose logic level to be set high. All other 
+                        GPIO pins on the port will be set to a logical low level. 
+                        For example, to set pins 0 and 1 to a logical high level and 
+                        all other pins to a logical low level, this parameter should 
+                        be passed as #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_1.
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS             If successfully set the given data.
+                    - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized.
+                    - #ADI_GPIO_INVALID_PINS    [D] If the given pins are invalid.
+
+    @sa         adi_gpio_SetHigh, adi_gpio_SetLow, adi_gpio_Toggle, adi_gpio_GetData
+*/
+ADI_GPIO_RESULT adi_gpio_SetData(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins)
+{
+
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+
+    /* validate the pins */
+    if (!ArePinsValid(Port, Pins))
+    {
+        return (ADI_GPIO_INVALID_PINS);
+    }
+#endif
+
+    pPort = adi_gpio_Device.pReg[Port];
+
+    /* set the GPIOs as directed */
+    pPort->OUT = Pins;
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+    @brief      Gets/Senses the input level of all GPIO Pins on the given port.
+
+    @details    Gets the level of all GPIO input pins on the given port.
+
+    @param[in]  Port    The GPIO port whose input level to be sensed.
+    @param[in]  Pins    The GPIO pins to be sensed. To sense a single GPIO pin, a single 
+                        GPIO value is passed for this parameter. For example, #ADI_GPIO_PIN_4.
+                        Alternatively, multiple GPIO pins can be configured
+                        simultaneously by OR-ing together GPIO pin values and
+                        passing the resulting value for this parameter. For
+                        example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6.
+    @param[out] pValue  The passed pValue parameter is written with a packed value containing
+                        the status of all the requested GPIO pins on the given port.
+
+    To get the status of a single GPIO pin, return value can be directly used.
+    For example to see if pin 4 on port 2 is a logical high level, the following is used:
+    <pre>
+        adi_gpio_GetData(#ADI_GPIO_PORT2, #ADI_GPIO_PIN_4, &pValue)
+    </pre>
+    pValue will contain the required information.
+
+    If information is required for multiple pins, following method is required:
+    <pre>
+        adi_gpio_GetData(#ADI_GPIO_PORT2, (#ADI_GPIO_PIN_3 | #ADI_GPIO_PIN_4 | #ADI_GPIO_PIN_7), &pValue)
+    </pre>
+
+    To test if pin 4 on port 2 is a logical high level, the following is used:
+    <pre>
+        if  (pValue & ADI_GPIO_PIN_4) {
+            pin 4 on port 2 is a logical high value
+        } else {
+            pin 4 on port 2 is a logical low value
+        }
+    </pre>
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS             If successfully sensed the input pins.
+                    - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized.
+                    - #ADI_GPIO_INVALID_PINS    [D] If the given pins are invalid.
+
+    @sa         adi_gpio_SetHigh, adi_gpio_SetLow, adi_gpio_Toggle, adi_gpio_SetData
+*/
+ADI_GPIO_RESULT adi_gpio_GetData (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, uint16_t* const pValue)
+{
+
+    ADI_GPIO_TypeDef    *pPort;     /* pointer to port registers */
+
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+
+    /* validate the pins */
+    if (!ArePinsValid(Port, Pins))
+    {
+        return (ADI_GPIO_INVALID_PINS);
+    }
+#endif
+
+    pPort = adi_gpio_Device.pReg[Port];
+
+    /* return the status of the GPIOs */
+    *pValue = (pPort->IN) & Pins;
+
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+/*!
+    @brief      Register or unregister an application callback function for group (A/B) interrupts.
+
+    @details    Applications may register a callback function that will be called when a
+                GPIO group (A/B) interrupt occurs. 
+                
+                The driver dispatches calls to registered callback functions when the
+                properly configured pin(s) latches an external interrupt input on the GPIO
+                pin(s).  The callback is dispatched with the following parameters, respectively:
+                    - application-provided callback parameter (\a pCBParam),
+                    - The GPIO Port,
+                    - The GPIO Pins.
+
+    @param[in]  eIrq            The interrupt for which the callback is being registered.
+    @param[in]  pfCallback      Pointer to the callback function. This can be passed as NULL to
+                                unregister the callback.
+    @param[in]  pCBParam        Callback parameter which will be passed back to the application
+                                when the callback is called..
+
+    @return     Status
+                    - #ADI_GPIO_SUCCESS if successfully registered the callback.
+                    - #ADI_GPIO_NOT_INITIALIZED [D] if not yet initialized
+                    - #ADI_GPIO_INVALID_INTERRUPT [D] if interrupt ID is invalid
+
+    @sa         adi_gpio_SetGroupInterruptPolarity
+*/
+ADI_GPIO_RESULT  adi_gpio_RegisterCallback (const ADI_GPIO_IRQ eIrq, ADI_CALLBACK const pfCallback, void *const pCBParam )
+{
+    uint16_t index = 0u;
+    ADI_INT_STATUS_ALLOC();
+    
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == adi_gpio_Device.pData)
+    {
+        return (ADI_GPIO_NOT_INITIALIZED);
+    }
+#endif
+
+    index = (uint16_t)eIrq - (uint16_t)SYS_GPIO_INTA_IRQn + ADI_GPIO_IRQ_GROUPA_INDEX;
+
+    ADI_ENTER_CRITICAL_REGION();
+    
+    adi_gpio_Device.pData->CallbackTable[index].pfCallback = pfCallback;
+    adi_gpio_Device.pData->CallbackTable[index].pCBParam = pCBParam;
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* return the status */
+    return (ADI_GPIO_SUCCESS);
+}
+
+
+
+/*@}*/
+
+/*! \cond PRIVATE */
+/* All of the following is excluded from the doxygen output... */
+
+/* Common group (A/B) interrupt handler */
+static void CommonInterruptHandler(const ADI_GPIO_IRQ_INDEX index, const IRQn_Type eIrq)
+{
+    ADI_GPIO_PORT Port;
+    ADI_GPIO_TypeDef *pPort;
+    ADI_GPIO_DATA Pins;
+    ADI_GPIO_DATA nIntEnabledPins;
+
+    ADI_GPIO_CALLBACK_INFO *pCallbackInfo = &adi_gpio_Device.pData->CallbackTable[index];
+
+    /* Loop over all the ports. */
+    for(Port=ADI_GPIO_PORT0; Port<ADI_GPIO_NUM_PORTS; Port++)
+    {
+        pPort = adi_gpio_Device.pReg[Port];
+
+        /* Is the interrupt is for GROUP A */
+        if(SYS_GPIO_INTA_IRQn == eIrq)
+        {
+            nIntEnabledPins =  pPort->IENA;
+        }
+        else  /* Is the interrupt is for GROUP B */
+        {
+            nIntEnabledPins =  pPort->IENB;
+        }
+
+        /* Clear only required interrupts */
+        Pins = ((pPort->INT) & nIntEnabledPins);
+        pPort->INT = Pins;
+
+        /* params list is: application-registered cbParam, Port number, and interrupt status */
+        if((pCallbackInfo->pfCallback != NULL) && (Pins != 0u))
+        {
+            pCallbackInfo->pfCallback (pCallbackInfo->pCBParam, (uint32_t)Port, &Pins);
+        }
+    }
+}
+
+/* Interrupt A handler */
+void GPIO_A_Int_Handler(void)
+{
+    ISR_PROLOG()
+    CommonInterruptHandler(ADI_GPIO_IRQ_GROUPA_INDEX, SYS_GPIO_INTA_IRQn);
+    ISR_EPILOG()
+}
+
+/* Interrupt B handler */
+void GPIO_B_Int_Handler (void)
+{
+    ISR_PROLOG()
+    CommonInterruptHandler(ADI_GPIO_IRQ_GROUPB_INDEX, SYS_GPIO_INTB_IRQn);
+    ISR_EPILOG()      
+}
+
+#ifdef ADI_DEBUG
+
+
+/*!
+    @brief      Tests a Pins Parameter for Validity
+
+    @details    A debug function that checks a Pins parameter for validity
+
+    @param[in]  Pins    Logical OR-ing of one or more ADI_GPIO_PIN_x values
+
+    @return     Status
+                    - true      the Pins value contains valid data
+                    - false     the Pins value contains invalid data
+*/
+static bool ArePinsValid(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins)
+{
+    uint32_t PinValid = 0u;
+
+    /* test for a valid pin */
+    switch (Port)
+    {
+        case ADI_GPIO_PORT0:
+            PinValid = ~ADI_GPIO_PORT0_PIN_AVL & Pins;
+            break;
+
+        case ADI_GPIO_PORT1:
+            PinValid = ~ADI_GPIO_PORT1_PIN_AVL & Pins;
+            break;
+
+        case ADI_GPIO_PORT2:
+            PinValid = ~ADI_GPIO_PORT2_PIN_AVL & Pins;
+            break;
+            
+        case ADI_GPIO_PORT3:
+            PinValid = ~ADI_GPIO_PORT3_PIN_AVL & Pins;
+            break;
+            
+        default:
+            break;
+    }
+
+    if (PinValid == 0u)
+    {
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+}
+#endif /* ADI_DEBUG */
+
+/*! \endcond  */
+
+/*
+** EOF
+*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/gpio/adi_gpio_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/gpio/adi_gpio_def.h
new file mode 100755
index 00000000000..90282625df8
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/gpio/adi_gpio_def.h
@@ -0,0 +1,94 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_gpio_def.h
+ * @brief:   GPIO Device Driver definition
+ *****************************************************************************
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#ifndef ADI_GPIO_DEF_H
+#define ADI_GPIO_DEF_H
+/*! \cond PRIVATE */
+
+
+/*! local enum for callback table indexing */
+typedef enum
+{
+    /* Group interrupts */
+    ADI_GPIO_IRQ_GROUPA_INDEX     = (0x0),   /*!< GroupA interrupt index.   */
+    ADI_GPIO_IRQ_GROUPB_INDEX     = (0x1),   /*!< GroupB interrupt index.   */
+
+    ADI_GPIO_NUM_INTERRUPTS       = (0x2),   /*!< Number of GPIO interrupts */
+
+} ADI_GPIO_IRQ_INDEX;
+
+
+/*! Structure to hold callback function and parameter */
+typedef struct _ADI_GPIO_CALLBACK_INFO
+{
+    ADI_CALLBACK         pfCallback;    /*!< Callback function pointer */
+    void                 *pCBParam;      /*!< Callback parameter */
+} ADI_GPIO_CALLBACK_INFO;
+
+/*! Structure to hold callback function and parameter */
+typedef struct _ADI_GPIO_DEV_DATA
+{
+    ADI_GPIO_CALLBACK_INFO  CallbackTable[ADI_GPIO_NUM_INTERRUPTS];  /*!< Callback Info for External interrupts */
+} ADI_GPIO_DEV_DATA;
+
+/*! \struct ADI_GPIO_DEVICE
+
+    GPIO instance data
+
+    This structure contains the "state" information for the
+    instance of the device.  For GPIO there is only one
+    of these objects.
+*/
+typedef struct _ADI_GPIO_DRIVER_STRUCT
+{
+	ADI_GPIO_TypeDef            *pReg[ADI_GPIO_NUM_PORTS];          /*!< GPIO Ports Register base          */
+	ADI_GPIO_DEV_DATA           *pData;                             /*!< Pointer to device data            */
+} ADI_GPIO_DRIVER_STRUCT;
+
+
+/* alias for the actual device structure */
+typedef ADI_GPIO_DRIVER_STRUCT      ADI_GPIO_DRIVER;
+
+/*! \endcond */
+#endif /* ADI_GPIO_DEF_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c.c
new file mode 100755
index 00000000000..cb8dba8001b
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c.c
@@ -0,0 +1,1169 @@
+/*! *****************************************************************************
+ * @file:    adi_i2c.c
+ * @brief:   I2C  device  driver global file.
+ * @details: This a global file which includes a specific file based on the processor family.
+ *           This file contains the I2C device driver functions.
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+/** @addtogroup I2C_Driver I2C Driver
+ *  @{
+ * @brief Inter-Integrated Circuit (I2C) Driver
+ * @details The I2C Master device driver manages the on-chip I2C hardware to
+ * control the external two-wire I2C Bus interface, allowing communication with
+ * multiple I2C slave devices through the I2C slave device addressing scheme.
+ * @note The application must include drivers/i2c/adi_i2c.h to use this driver
+ */
+
+ /*! \cond PRIVATE */
+#include <adi_processor.h>
+#include <assert.h>
+#include <string.h>     /* for "memset" */
+/*! \endcond */
+
+#include <drivers/general/adi_drivers_general.h>
+#include <drivers/i2c/adi_i2c.h>
+
+ /*! \cond PRIVATE */
+
+#include <drivers/pwr/adi_pwr.h>
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+*
+* Pm011 (rule 6.3): Types which specify sign and size should be used
+*   We use bool which is accepted by MISRA but the toolchain does not accept it
+*
+* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
+*   It is used in the _data.h file which isn't a header as such.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+*
+* Pm088 (rule 17.4): pointer arithmetic should not be used.
+*   Relying on pointer arithmetic for buffer handling.
+*
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   The rule makes an exception for memory-mapped register accesses.
+*/
+
+#pragma diag_suppress=Pm011,Pm123,Pm073,Pm143,Pm088,Pm140
+#endif /* __ICCARM__ */
+
+/* pull in internal data structures */
+#include "adi_i2c_data.c"
+
+
+/* handy type-safe zero */
+uint16_t uZero16 = 0u;
+
+/* central busy checker */
+#define I2C_BUSY (uZero16 != ((hDevice->pDev->MSTAT) & (uint16_t)(BITM_I2C_MSTAT_MBUSY | BITM_I2C_MSTAT_LINEBUSY)))
+
+/*!
+ * Read/write bit.
+ */
+ #define READ_NOT_WRITE (1u)
+
+/* Override "weak" default binding in startup.c */
+/*! \cond PRIVATE */
+extern void I2C0_Master_Int_Handler(void);
+/*! \endcond */
+
+#if defined(ADI_DEBUG)
+/*
+ * Verifies a pointer to a driver points to one of the driver
+ * struct's internal to this file.
+ */
+static bool IsDeviceHandle(ADI_I2C_HANDLE const hDevice);
+static bool IsDeviceHandle(ADI_I2C_HANDLE const hDevice)
+{
+    if ((i2c_device_info[0].hDevice != (hDevice)) && ((hDevice)->pDevInfo->hDevice != NULL)) {
+        return true;
+    } else {
+        return false;
+    }
+}
+#endif
+
+
+/*! \endcond */
+
+
+/**********************************************************************************\
+|**********************************USER INTERFACE**********************************|
+\**********************************************************************************/
+
+
+/*!
+ * @brief  Initialize and allocate an I2C device for use in Master Mode.
+ *
+ * @param[in]   DeviceNum    Zero-based device index designating the I2C device to initialize.
+ *
+ * @param [in]  pMemory      Pointer to a 32-bit aligned buffer of size ADI_I2C_MEMORY_SIZE
+ *                           required by the driver for the operation of specified I2C device.
+ *
+ * @param [in]  MemorySize   Size of the buffer to which "pMemory" points.
+ *
+ * @param[out]  phDevice     The caller's device handle pointer for storing the initialized
+ *                           device instance data pointer.
+ *
+ * @return            Status
+ *                    - #ADI_I2C_SUCCESS                    Call completed successfully.
+ *                    - #ADI_I2C_BAD_DEVICE_NUMBER [D]      Invalid device index.
+ *                    - #ADI_I2C_DEVICE_IN_USE [D]          Device is already opened.
+ *                    - #ADI_I2C_INSUFFICIENT_MEMORY [D]    Device memory is not sufficient.
+ *
+ * Initialize an I2C device using default user configuration settings (from adi_i2c_config.h)
+ * and allocate the device for use.  Device is opened in Master mode only.
+ *
+ * No other I2C APIs may be called until the device open function is called.  The returned
+ * device handle is required to be passed to all subsequent I2C API calls to identify the
+ * physical device instance to use.  The user device handle (pointed to by phDevice) is set
+ * to NULL on failure.
+ *
+ * @note Currently, only a singular I2C physical device instance (device ID "0") exists.
+ *
+ * @sa      adi_spi_Close().
+ */
+ADI_I2C_RESULT adi_i2c_Open (uint32_t const DeviceNum, void* const pMemory, uint32_t const MemorySize, ADI_I2C_HANDLE* const phDevice) {
+
+    /* make a device handle out of the user memory */
+    ADI_I2C_HANDLE hDevice = (ADI_I2C_HANDLE)pMemory;
+
+#if defined(ADI_DEBUG)
+    /* check requested device number */
+    if (DeviceNum >= (uint32_t)ADI_I2C_NUM_INSTANCES) {
+        return ADI_I2C_BAD_DEVICE_NUMBER;
+    }
+
+    /* verify device is not already open */
+    if (i2c_device_info[DeviceNum].hDevice != NULL) {
+        return ADI_I2C_DEVICE_IN_USE;
+    }
+
+    /* verify memory size macro value */
+    assert(ADI_I2C_MEMORY_SIZE == sizeof(ADI_I2C_DEV_DATA_TYPE));
+
+    /* verify user-provided memory meets requirement */
+    if ((NULL == pMemory) || (MemorySize < (uint32_t)ADI_I2C_MEMORY_SIZE)) {
+        return ADI_I2C_INSUFFICIENT_MEMORY;
+    }
+#endif
+
+    /* store a bad handle in case of failure */
+    *phDevice = NULL;
+
+    /*
+     * Link user memory (handle) to ADI_I2C_DEVICE_INFO data structure.
+     *
+     *       ADI_I2C_DEVICE_INFO  <==>   ADI_I2C_HANDLE
+     *
+     * Clear the ADI_I2C_HANDLE memory. This also sets all bool
+     * structure members to false so we do not need to waste cycles
+     * setting these explicitly (e.g. hDevice->bRepearStart = false)
+     */
+    i2c_device_info[DeviceNum].hDevice = (ADI_I2C_DEV_DATA_TYPE *)pMemory;
+    memset(pMemory, 0, MemorySize);
+
+    /* also link device handle within __ADI_I2C_DEV_DATA_TYPE data structure */
+    hDevice->pDevInfo = &i2c_device_info[DeviceNum];
+    /*
+     * Although the ADI_I2C_DEVICE_INFO struct has the physical device pointer
+     * for this instance, copying it to the ADI_I2C_HANDLE struct (in user memory)
+     * will minimize the runtime footprint and cycle count when accessing the I2C
+     * registers.
+     */
+    hDevice->pDev = i2c_device_info[DeviceNum].pDev;
+
+    /* store a pointer to user's static configuration settings */
+    hDevice->pDevInfo->pConfig = (ADI_I2C_CONFIG*)&gConfigInfo[DeviceNum];
+
+    /* create the semaphore */
+    SEM_CREATE(hDevice, "i2c_sem", ADI_I2C_SEMAPHORE_FAILED)
+        ;
+
+    /* reset the driver and HW state */
+    ADI_I2C_RESULT ignore ADI_UNUSED_ATTRIBUTE = i2cReset(hDevice);
+
+    /* store device handle into user handle */
+    *phDevice = (ADI_I2C_HANDLE)hDevice;
+
+    return ADI_I2C_SUCCESS;
+}
+
+
+/*!
+ * @brief  Uninitialize and deallocate an I2C device.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_spi_Open().
+ *
+ * @return      Status
+ *                - #ADI_I2C_SUCCESS                Call completed successfully.
+ *                - #ADI_I2C_BAD_DEVICE_HANDLE [D]  Invalid device handle parameter.
+ *
+ * Uninitialize and release an allocated I2C device, and memory associated with it
+ * for other use.
+ *
+ * @note The user memory is released from use by the I2C driver, but is not freed.
+ *
+ * @sa  adi_spi_Open().
+ */
+ADI_I2C_RESULT adi_i2c_Close (ADI_I2C_HANDLE const hDevice) {
+
+#ifdef ADI_DEBUG
+    if (IsDeviceHandle(hDevice)) {
+        return ADI_I2C_BAD_DEVICE_HANDLE;
+    }
+#endif
+
+    /* destroy semaphore */
+    SEM_DELETE(hDevice,ADI_I2C_SEMAPHORE_FAILED)
+        ;
+
+    /* reset the driver and HW state */
+    ADI_I2C_RESULT ignore ADI_UNUSED_ATTRIBUTE = i2cReset(hDevice);
+
+    /* stub handle */
+    hDevice->pDevInfo->hDevice = NULL;
+
+    return ADI_I2C_SUCCESS;
+}
+
+
+/*!
+ * @brief  Blocking I2C Master-Mode data read/write API.
+ *
+ * @param[in]    hDevice        Device handle obtained from adi_spi_Open().
+ * @param[in]    pTransaction   Pointer to I2C transaction data struct.
+ * @param[out]   pHwErrors      Pointer to hardware error return variable.
+ *
+ * @return       Status
+ *                - #ADI_I2C_SUCCESS                Call completed successfully.
+ *                - #ADI_I2C_BAD_DEVICE_HANDLE [D]  Invalid device handle parameter.
+ *                - #ADI_I2C_DEVICE_IN_USE [D]      An I2C transaction is already underway.
+ *                - #ADI_I2C_INVALID_PARAMETER [D]  Invalid data pointer or count is detected.
+ *                - #ADI_I2C_HW_ERROR_DETECTED      A hardware error occurred, check \a pHwErrors.
+ *
+ * Request a blocking I2C data transfer (read or write, not both as I2C is unidirectional bus)
+ * with or without preceding prologue transmitted.  Control is not returned to the calling
+ * application until the transfer is complete.  Buffer allocations are made by the calling code
+ * (the application).
+ *
+ * The optional prologue (if present) and MANDATORY transaction data pointers are used to read or
+ * write data over the I2C serial bus according to the prologue and data pointers and corresponding
+ * size information contained in the \a pTransaction parameter block.  The most recently set slave
+ * target address (set statically with user configuration settings contained in adi_i2c_config.h file
+ * or set dynamically (at run-time) via the #adi_i2c_SetSlaveAddress() API) is used to address the
+ * specific destination slave device on the I2C bus.
+ *
+ * If present, the prologue (typically, an addressing phase conveying a memory/register address or
+ * slave device command) is transmitted prior to the data read or write phase, with or without
+ * an intervening I2C STOP condition.  The prologue data is entirely slave device dependent.
+ *
+ * In the case of a prologue followed by a data read operation, the I2C bus direction must be
+ * reversed following the prologue transmit.  In this case, The usual I2C STOP condition following
+ * the prologue (if present) transmit may be suppressed by setting the \a bRepeatStart transaction
+ * parameter "true".  In this case, a second (repeat) START condition is "transmitted" between the
+ * addressing phase (prologue transmit) and the data phase of the read sequence... \a without an
+ * intervening STOP condition.  This is commonly referred to as the "combined format" in which the
+ * I2C bus direction is reversed halfway through the transaction without releasing control of the
+ * I2C bus arbitration.  The REPEAT-START condition is a common I2C bus protocol required by many
+ * I2C slave devices.
+ *
+ * In the case of a prologue followed by a data write operation, there is no need to turn the bus
+ * around and so the \a bRepeatStart parameter is ignored.
+ *
+ * @note Application must check the return code to verify if any I2C Bus errors occurred.  Hardware
+ * errors (I2C Protocol errors) are indicated with the #ADI_I2C_HW_ERROR_DETECTED return code, and
+ * the set of hardware errors (enum #ADI_I2C_HW_ERRORS) that occurred (there may be multiple) are
+ * indicated in the value set to user variable pointed to by \a pHwErrors.
+ *
+ * @sa adi_i2c_SetSlaveAddress().
+ * @sa adi_i2c_SubmitBuffer().
+ * @sa adi_i2c_IsBufferAvailable().
+ * @sa adi_i2c_GetBuffer().
+ * @sa ADI_I2C_TRANSACTION.
+ * @sa ADI_I2C_HW_ERRORS.
+ */
+ADI_I2C_RESULT adi_i2c_ReadWrite (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction, uint32_t* const pHwErrors) {
+
+#ifdef ADI_DEBUG
+    if (IsDeviceHandle(hDevice)) {
+        return ADI_I2C_BAD_DEVICE_HANDLE;
+    }
+    if (I2C_BUSY) {
+        return ADI_I2C_DEVICE_IN_USE;
+    }
+    /* NULL transaction data pointer or zero transaction data count */
+    if ((NULL == pTransaction->pData) || (0u == pTransaction->nDataSize)) {
+        return ADI_I2C_INVALID_PARAMETER;
+    }
+#endif
+
+    /* reset submit/get safeguard flag */
+    hDevice->bSubmitCalled = false;
+
+    /* submit/commence the transaction */
+    submitTransaction(hDevice, pTransaction);
+
+    /* block on internal transaction completion/error semaphore */
+    if (ADI_I2C_SUCCESS == hDevice->result) {
+
+        SEM_PEND(hDevice, ADI_I2C_SEMAPHORE_FAILED);
+
+        /* completion interrupt comes as FIFO unloads, but serialization may not be complete yet... */
+        /* must also wait for hardware busy status to clear before giving back control */
+        /* i.e., allow any transmit serialization to complete after last FIFO unload */
+        while (I2C_BUSY) {
+            ;
+        }
+    }
+
+    /* copy out any hardware errors... */
+    *pHwErrors = hDevice->hwErrors;
+    if (0u != hDevice->hwErrors) {
+        /* set the HW error return code */
+        hDevice->result = ADI_I2C_HW_ERROR_DETECTED;
+    }
+
+    /* return transaction result code */
+    return hDevice->result;
+}
+
+
+/*!
+ * @brief  Non-Blocking I2C Master-Mode data read or data write API.
+ *
+ * @param[in]    hDevice        Device handle obtained from adi_spi_Open().
+ * @param[in]    pTransaction   Pointer to I2C transaction data struct.
+ *
+ * @return       Status
+ *                - #ADI_I2C_SUCCESS                Call completed successfully.
+ *                - #ADI_I2C_BAD_DEVICE_HANDLE [D]  Invalid device handle parameter.
+ *                - #ADI_I2C_DEVICE_IN_USE [D]      An I2C transaction is already underway.
+ *                - #ADI_I2C_INVALID_PARAMETER [D]  Invalid data pointer or count is detected.
+ *
+ * Request a non-blocking I2C data transfer (read or write) with or without preceding prologue
+ * transmitted.  Control is returned to the calling application immediately, allowing the application
+ * process other tasks.  The transaction result code is retrieved by #adi_i2c_GetBuffer().
+ *
+ * The application may optionally poll the I2C driver via the #adi_i2c_IsBufferAvailable() API while
+ * the transaction is underway to determine if and when the submitted transaction is complete.
+ * Eventually, the application \a MUST call the \a MANDATORY #adi_i2c_GetBuffer() API to obtain the
+ * transaction result and complete the transaction.  Buffer allocations are made by the calling
+ * code (the application).
+ *
+ * The #adi_i2c_GetBuffer() API may be called at any time, even if the transaction is incomplete;
+ * the #adi_i2c_GetBuffer() call will simply block in incomplete transactions until the
+ * transaction does complete... at which point #adi_i2c_GetBuffer() returns control with
+ * the transaction result code.  Submitting background transactions is useful if the application has
+ * housekeeping chores to perform when the I2C transaction is started, but later the application
+ * decides to just block until the transaction is complete.
+ *
+ * The prologue and data buffers are handled as they are in the blocking #adi_i2c_ReadWrite() call,
+ * it's just that the #adi_i2c_SubmitBuffer() API does not block on the data phase.
+ *
+ * @note The non-blocking #adi_i2c_SubmitBuffer() call \a REQUIRES a matching #adi_i2c_GetBuffer() call
+ * to obtain the final transaction result code and to inform the driver that the application wants to
+ * regain ownership of the buffers.  The application should be prepared to wait for this ownership
+ * until the current transaction completes.  The matching #adi_i2c_GetBuffer() call is required even if
+ * the transaction may have already completed.  The #adi_i2c_GetBuffer() call allows the driver to block
+ * on completion or error events and then synchronize its internal blocking object.  The intermediate
+ * #adi_i2c_IsBufferAvailable() API is optional.\n\n
+ *
+ * @note The #adi_i2c_SubmitBuffer() API is singular, i.e., only a single transaction may be submitted
+ * at a time.  Simultaneous submits (e.g., ping-pong mode) are not supported by the I2C driver.
+ *
+ * @sa adi_i2c_ReadWrite().
+ * @sa adi_i2c_SetSlaveAddress().
+ * @sa adi_i2c_IsBufferAvailable().
+ * @sa adi_i2c_GetBuffer().
+ * @sa ADI_I2C_TRANSACTION.
+ */
+ADI_I2C_RESULT adi_i2c_SubmitBuffer (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction) {
+
+#ifdef ADI_DEBUG
+    if (IsDeviceHandle(hDevice)) {
+        return ADI_I2C_BAD_DEVICE_HANDLE;
+    }
+    if (I2C_BUSY) {
+        return ADI_I2C_DEVICE_IN_USE;
+    }
+    /* NULL transaction data pointer or zero transaction data count */
+    if ((NULL == pTransaction->pData) || (0u == pTransaction->nDataSize)) {
+        return ADI_I2C_INVALID_PARAMETER;
+    }
+#endif
+
+    /* set submit/get safeguard flag */
+    hDevice->bSubmitCalled = true;
+
+    /* submit/commence the transaction */
+    submitTransaction(hDevice, pTransaction);
+
+    /* no blocking on submit... just return the submit result */
+    return hDevice->result;
+}
+
+
+/*!
+ * @brief  Query if a non-blocking I2C transfer is complete.
+ *
+ * @param[in]     hDevice             Device handle obtained from adi_spi_Open().
+ * @param[out]    pbCompletionState   Pointer to Boolean into which the I2C bus state is written.
+ *
+ * @return         Status
+ *                - #ADI_I2C_SUCCESS                Call completed successfully.
+ *                - #ADI_I2C_BAD_DEVICE_HANDLE [D]  Invalid device handle parameter.
+ *                - #ADI_I2C_INVALID_SUBMIT_API     No matching submit call.
+ *
+ * Sets the application-provided Boolean variable pointed to by pbCompletionState either:
+ *     - true, when the non-blocking transactions is complete, or
+ *     - false, while the non-blocking transactions is still underway.
+ *
+ * This API is used in conjunction with a non-blocking #adi_i2c_SubmitBuffer() transfer to
+ * determine when the transaction is complete.  Typically, non-blocking calls are used when the
+ * calling application has other work to do while I2C controller serializes data over the I2C bus,
+ * which is an interrupt-driven process.  The transaction is submitted as a non-blocking call and
+ * the submitting API returns immediately, allowing the calling application to perform its other tasks.
+ * The I2C driver services the interrupts to transfer data while the application performs its
+ * other tasks.
+ *
+ * Non-blocking calls can be polled with this API for completion, or if the application has completed
+ * its other tasks and wants to just wait on the I2C completion without further polling, it may call
+ * the associated #adi_i2c_GetBuffer() API to convert the currently unblocked transaction to
+ * a blocking one.
+ *
+ * @note This API is inappropriate in context of blocking calls to #adi_i2c_ReadWrite().
+ *
+ * @sa adi_i2c_ReadWrite().
+ * @sa adi_i2c_SubmitBuffer().
+ * @sa adi_i2c_GetBuffer().
+ * @sa ADI_I2C_TRANSACTION.
+ */
+ADI_I2C_RESULT adi_i2c_IsBufferAvailable (ADI_I2C_HANDLE const hDevice, bool* const pbCompletionState) {
+
+#ifdef ADI_DEBUG
+    if (IsDeviceHandle(hDevice)) {
+        return ADI_I2C_BAD_DEVICE_HANDLE;
+    }
+#endif
+
+    /* fail if not a submit-based transaction */
+    if (false == hDevice->bSubmitCalled) {
+        return ADI_I2C_INVALID_SUBMIT_API;
+    }
+
+    /* return true when bus goes quiet */
+    if (I2C_BUSY) {
+        *pbCompletionState = false;
+    } else {
+        *pbCompletionState = true;
+    }
+
+    return ADI_I2C_SUCCESS;
+}
+
+
+/*!
+ * @brief  Request ownership of a submitted buffer.
+ *
+ * @param[in]     hDevice             Device handle obtained from adi_spi_Open().
+ * @param[out]    pHwErrors           Pointer to hardware error return variable.
+ *
+ * @return         Status
+ *                - #ADI_I2C_SUCCESS                Call completed successfully.
+ *                - #ADI_I2C_BAD_DEVICE_HANDLE [D]  Invalid device handle parameter.
+ *                - #ADI_I2C_INVALID_SUBMIT_API     No matching submit call.
+ *                - #ADI_I2C_HW_ERROR_DETECTED      A hardware error occurred, check \a pHwErrors.
+ *
+ * This is a potentially blocking MANDATORY call that the application MUST use to reclaim
+ * ownership of any "submitted" transaction (submitted via a previous #adi_i2c_SubmitBuffer()
+ * call) and obtain the transaction success/failure result code.  This API blocks until the
+ * transaction is complete and returns the transaction result code.  If the transaction is
+ * already complete, the blocking is trivial and control is returned immediately.
+ *
+ * Non-blocking calls can also be (optionally) polled with the non-blocking
+ * #adi_i2c_IsBufferAvailable() API to see if and when the transaction is complete.
+ *
+ * The #adi_i2c_GetBuffer() call is a MANDATORY compliment to #adi_i2c_SubmitBuffer() and
+ * allows the I2C driver to synchronize its internal blocking object.
+ *
+ * @note Application must check the return code to verify if any I2C Bus errors occurred.  Hardware
+ * errors (I2C Protocol errors) are indicated with the #ADI_I2C_HW_ERROR_DETECTED return code, and
+ * the set of hardware errors (enum #ADI_I2C_HW_ERRORS) that occurred (there may be multiple) are
+ * indicated in the value set to user variable pointed to by \a pHwErrors.
+ *
+ * @sa adi_i2c_ReadWrite().
+ * @sa adi_i2c_SubmitBuffer().
+ * @sa adi_i2c_IsBufferAvailable().
+ * @sa ADI_I2C_TRANSACTION.
+ * @sa ADI_I2C_HW_ERRORS.
+ */
+ADI_I2C_RESULT adi_i2c_GetBuffer (ADI_I2C_HANDLE const hDevice, uint32_t* const pHwErrors) {
+
+#ifdef ADI_DEBUG
+    if (IsDeviceHandle(hDevice)) {
+        return ADI_I2C_BAD_DEVICE_HANDLE;
+    }
+#endif
+
+    /* fail if not a submit-based transaction */
+    if (false == hDevice->bSubmitCalled) {
+        return ADI_I2C_INVALID_SUBMIT_API;
+    }
+
+    /* block until complete or error interrupt sets the semaphore */
+    SEM_PEND(hDevice, ADI_I2C_SEMAPHORE_FAILED);
+
+    /* delay until bus goes quiet */
+    while (I2C_BUSY) {
+        ;
+    }
+
+    /* copy out any hardware errors... */
+    *pHwErrors = hDevice->hwErrors;
+    if (0u != hDevice->hwErrors) {
+        /* set the HW error return code */
+        hDevice->result = ADI_I2C_HW_ERROR_DETECTED;
+    }
+
+    /* return transaction result code */
+    return hDevice->result;
+}
+
+/*!
+ * @brief  Reset an I2C device and driver instance.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_spi_Open().
+ *
+ * @return      Status
+ *                - #ADI_I2C_SUCCESS                Call completed successfully.
+ *                - #ADI_I2C_BAD_DEVICE_HANDLE [D]  Invalid device handle parameter.
+ *
+ * Reset the I2C physical controller and device driver internals.
+ */
+ADI_I2C_RESULT adi_i2c_Reset (ADI_I2C_HANDLE const hDevice) {
+
+#ifdef ADI_DEBUG
+    if (IsDeviceHandle(hDevice)) {
+        return ADI_I2C_BAD_DEVICE_HANDLE;
+    }
+#endif
+
+    /* destroy/recreate the semaphore to force a clear state */
+    SEM_DELETE(hDevice, ADI_I2C_SEMAPHORE_FAILED)
+        ;
+    SEM_CREATE(hDevice, "i2c_sem", ADI_I2C_SEMAPHORE_FAILED)
+        ;
+
+    /* reset the driver and HW state */
+    return i2cReset(hDevice);
+}
+
+
+/*!
+ * @brief  Set the I2C serial bus speed.
+ *
+ * @param[in]     hDevice             Device handle obtained from adi_spi_Open().
+ * @param[in]     requestedBitRate32  Requested I2C bus clock rate (in Hz).
+ *
+ * @return         Status
+ *                - #ADI_I2C_SUCCESS                Call completed successfully.
+ *                - #ADI_I2C_BAD_DEVICE_HANDLE [D]  Invalid device handle parameter.
+ *                - #ADI_I2C_DEVICE_IN_USE [D]      Device is busy.
+ *                - #ADI_I2C_BAD_SYS_CLOCK          Failure to obtain the current PCLK rate.
+ *                - #ADI_I2C_BAD_BITRATE            Requested clock speed exceeds operational specification.
+ *
+ * Sets the I2C bus clock speed to the requested user parameter, \a requestedBitRate.
+ *
+ * @note Any I2C Bus clock rate may be requested up to and including the "FAST" mode I2C clock
+ * rate (400 kHz), including the "STANDARD" mode (100 kHz).  Faster clock rates beyond "FAST"
+ * mode (e.g., "FAST+" or "HIGH-SPEED" modes) are not supported by the hardware.  Slower clock
+ * rates below approximately 55 kHz (assuming a 26 MHz system clock) are physically unrealizable
+ * due to the fixed 8-bit field-width of the 8-bit I2C clock rate divide register.\n\n
+ *
+ * @note Default clock rate may be specified statically in the default user configuration file,
+ * "adi_i2c_config.h".
+ */
+ADI_I2C_RESULT adi_i2c_SetBitRate (ADI_I2C_HANDLE const hDevice, uint32_t const requestedBitRate32) {
+
+    uint32_t clockFrequency32, halfClock32;
+    uint16_t halfClock16;
+    uint16_t highTime16, lowTime16;
+
+#ifdef ADI_DEBUG
+    if (IsDeviceHandle(hDevice)) {
+        return ADI_I2C_BAD_DEVICE_HANDLE;
+    }
+    if (I2C_BUSY) {
+        return ADI_I2C_DEVICE_IN_USE;
+    }
+#endif
+
+    /* get input clockrate from power service */
+    if (ADI_PWR_SUCCESS != adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &clockFrequency32)) {
+        return ADI_I2C_BAD_SYS_CLOCK;
+    }
+
+    /* block requests above max rated 400kHz operation */
+    if (ADI_I2C_MAX_RATE < requestedBitRate32) {
+        return ADI_I2C_BAD_BITRATE;
+    }
+
+    /* compute half-cycle period in 32-bits (">>1" is divide by 2) */
+    halfClock32 = (clockFrequency32 / requestedBitRate32) >> 1;  /* HRM equation */
+
+    /* downcast to 16-bit to match destination field */
+    halfClock16 = (uint16_t)(halfClock32 & 0x0000ffffu);
+
+    /* check for lost precision in conversion */
+    if (halfClock32 != halfClock16) {
+        return ADI_I2C_BAD_BITRATE;
+    }
+
+    /* adjust high and low durations per HRM */
+    highTime16 = halfClock16 - 7u;  /* empirical: varies with board layout, pullups, etc */
+    lowTime16  = halfClock16 - 1u;
+
+    /* shift values into their clock rate divider register positions */
+    highTime16 <<= BITP_I2C_DIV_HIGH;
+    lowTime16  <<= BITP_I2C_DIV_LOW;
+
+    /* check for divider overflows beyond designated (8-bit) field masks */
+    if (    (uZero16 != ((uint16_t)highTime16 & (uint16_t)(~(BITM_I2C_DIV_HIGH))))
+            ||
+            (uZero16 != ((uint16_t)lowTime16 & (uint16_t)(~(BITM_I2C_DIV_LOW))))
+       ) {
+       return ADI_I2C_BAD_BITRATE;
+    }
+
+    /* program new values */
+    hDevice->pDev->DIV = highTime16 | lowTime16;
+
+    return ADI_I2C_SUCCESS;
+}
+
+
+/*!
+ * @brief  Set the I2C serial bus slave address.
+ *
+ * @param[in]     hDevice             Device handle obtained from adi_spi_Open().
+ * @param[in]     SlaveAddress        New 7-bit address for targeting a slave device.
+ *
+ * @return         Status
+ *                - #ADI_I2C_SUCCESS                Call completed successfully.
+ *                - #ADI_I2C_BAD_DEVICE_HANDLE [D]  Invalid device handle parameter.
+ *                - #ADI_I2C_DEVICE_IN_USE [D]      Device is busy.
+ *                - #ADI_I2C_INVALID_SLAVE_ADDRESS  Slave address exceeds the 7-bit limit.
+ *
+ * Sets the 7-bit (unformatted) slave address for which all subsequent I2C bus traffic is directed.
+ * Read/write address formatting is performed by the driver, depending on bus direction.
+ *
+ * @note This driver does not support the I2C 10-bit extended addressing scheme.\n\n
+ *
+ * @note Default slave address may be specified statically in the default user configuration file,
+ * "adi_i2c_config.h".
+ */
+ADI_I2C_RESULT adi_i2c_SetSlaveAddress (ADI_I2C_HANDLE const hDevice, uint16_t const SlaveAddress) {
+
+#ifdef ADI_DEBUG
+    if (IsDeviceHandle(hDevice)) {
+        return ADI_I2C_BAD_DEVICE_HANDLE;
+    }
+    if (I2C_BUSY) {
+        return ADI_I2C_DEVICE_IN_USE;
+    }
+#endif
+
+    /* verify no slave address bits fall outside the 7-bit addressing model (10-bit addressing not supported) */
+    if (uZero16 != (SlaveAddress & (uint16_t)(~(BITM_I2C_ADDR1_VALUE >> 1)))) {
+        return ADI_I2C_INVALID_SLAVE_ADDRESS;
+    }
+
+    /* save new address */
+    hDevice->i2cDeviceAddress = SlaveAddress;
+
+    return ADI_I2C_SUCCESS;
+}
+
+
+/*!
+ * @brief  Transmit a General Call command to all slave devices on the I2C bus.
+ *
+ * @param[in]     hDevice            Device handle obtained from adi_spi_Open().
+ * @param[in]     pData              Pointer to data buffer to transmit.
+ * @param[in]     nDataSize          Size of data buffer to transmit.
+ * @param[out]    pHwErrors          Pointer to hardware error return variable.
+ *
+ * @return         Status
+ *                - #ADI_I2C_SUCCESS                Call completed successfully.
+ *                - #ADI_I2C_BAD_DEVICE_HANDLE [D]  Invalid device handle parameter.
+ *                - #ADI_I2C_DEVICE_IN_USE [D]      Device is busy.
+ *
+ * Broadcasts the given command buffer across the I2C bus to reserved General Call (GC)
+ * address (address zero).  All, some, or none of the slave devices on the I2C bus will
+ * respond, depending on their capabilities.  All responding slave devices will process
+ * the GC command according to their capabilities.
+ *
+ * The GC command is a blocking transaction.
+ *
+ * The application is responsible for formatting the GC command into the data buffer
+ * according to various Philips Semiconductor (now, NXP) documents, such as the 2014
+ * Revision 6 document: "UM10204 I2C-Bus Specification and User Manual"
+ * (see www.nxp.com/documents/user_manual/UM10204.pdf).
+ *
+ * No prologue precedes the GC command data; the GC command data is transmitted verbatim.
+ *
+ * @note The currently active slave address is saved and restored when transmitting GC
+ * commands to the reserved GC address (address zero).
+ *
+ */
+ADI_I2C_RESULT adi_i2c_IssueGeneralCall (ADI_I2C_HANDLE const hDevice, uint8_t* const pData, uint8_t const nDataSize, uint32_t* const pHwErrors) {
+
+	ADI_I2C_RESULT result;
+	ADI_I2C_TRANSACTION xfr;
+
+#ifdef ADI_DEBUG
+    if (IsDeviceHandle(hDevice)) {
+        return ADI_I2C_BAD_DEVICE_HANDLE;
+    }
+    if (I2C_BUSY) {
+        return ADI_I2C_DEVICE_IN_USE;
+    }
+#endif
+
+    /* force general call reserved target address of zero */
+    uint16_t savedSlaveAddress = hDevice->i2cDeviceAddress;
+    hDevice->i2cDeviceAddress = 0u;
+
+    /* setup the transfer */
+    xfr.pPrologue        = NULL;
+    xfr.nPrologueSize    = 0u;
+    xfr.pData            = pData;
+    xfr.nDataSize        = nDataSize;
+    xfr.bReadNotWrite    = false;
+    xfr.bRepeatStart     = false;
+
+    /* dispatch as a blocking transmit call */
+    result = adi_i2c_ReadWrite(hDevice, &xfr, pHwErrors);
+
+    /* always restore saved slave address */
+    hDevice->i2cDeviceAddress = savedSlaveAddress;
+
+    if (ADI_I2C_SUCCESS != result) {
+		return result;  /* read/write failure... */
+	} else {
+		return hDevice->result;  /* actual result */
+	}
+}
+
+
+ /*! \cond PRIVATE */
+
+
+/**********************************************************************************\
+|*****************************static helper functions******************************|
+\**********************************************************************************/
+
+static void submitTransaction(ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction) {
+
+    /* reset internal return code */
+    hDevice->result = ADI_I2C_SUCCESS;
+
+    /* reset hardware error code */
+    hDevice->hwErrors = ADI_I2C_HW_ERROR_NONE;
+
+    /* wait for HW to be ready */
+    while (I2C_BUSY) {
+        ;
+    }
+
+    /* save common user parameters */
+    hDevice->pNextPrologueByte      = pTransaction->pPrologue;
+    hDevice->remainingPrologueCount = pTransaction->nPrologueSize;
+    hDevice->bRepeatStart           = pTransaction->bRepeatStart;
+
+    /* encode (mask and upshift) the slave address, leaving room for the r/w control bit (LSB) */
+    hDevice->i2cEncodedDeviceAddress = (hDevice->i2cDeviceAddress & (BITM_I2C_ADDR1_VALUE >> 1)) << 1;
+
+    /* dispatch */
+    if (pTransaction->bReadNotWrite) {
+
+        /* setup read parameters */
+        hDevice->pNextReadByte           = pTransaction->pData;
+        hDevice->remainingReadCount      = pTransaction->nDataSize;
+        hDevice->pNextWriteByte          = NULL;
+        hDevice->remainingWriteCount     = 0u;
+
+        /* set read bit */
+        hDevice->i2cEncodedDeviceAddress |= READ_NOT_WRITE;
+
+        /* commence receive */
+        commenceReceive(hDevice);
+
+    } else {
+
+        /* setup write parameters */
+        hDevice->pNextReadByte           = NULL;
+        hDevice->remainingReadCount      = 0u;
+        hDevice->pNextWriteByte          = pTransaction->pData;
+        hDevice->remainingWriteCount     = pTransaction->nDataSize;
+
+        /* clear read bit */
+        hDevice->i2cEncodedDeviceAddress &= (~READ_NOT_WRITE);
+
+        /* commence transmit */
+        commenceTransmit(hDevice);
+    }
+}
+
+
+static void commenceTransmit(ADI_I2C_HANDLE const hDevice) {
+
+    /* transmit is always pure transmit, whether we have a prologue or not... */
+
+    /* enable PIO interrupts */
+    NVIC_EnableIRQ(hDevice->pDevInfo->pioIRQn);
+
+    /* enable i2c for PIO-based transmit interrupts */
+    hDevice->pDev->MCTL |= (BITM_I2C_MCTL_IENMTX | BITM_I2C_MCTL_MASEN);
+
+    /* how many bytes are available in the transmit FIFO (2-deep) */
+    uint16_t writableBytes = 2u - (hDevice->pDev->MSTAT & (uint16_t)BITM_I2C_MSTAT_MTXF);
+
+    /* prime transmit FIFO with any prologue data */
+    while ((0u < writableBytes) && (hDevice->remainingPrologueCount)) {
+        hDevice->pDev->MTX = *hDevice->pNextPrologueByte;
+        hDevice->pNextPrologueByte++;
+        hDevice->remainingPrologueCount--;
+        writableBytes--;
+    }
+
+    /* flesh out any remaining FIFO space with transmit data */
+    while ((0u < writableBytes) && (hDevice->remainingWriteCount)) {
+        hDevice->pDev->MTX = *hDevice->pNextWriteByte;
+        hDevice->pNextWriteByte++;
+        hDevice->remainingWriteCount--;
+        writableBytes--;
+    }
+
+    /* launch the transmit */
+    hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress;
+}
+
+
+/* initiate receive addressing phase */
+static void commenceReceive(ADI_I2C_HANDLE const hDevice) {
+
+    /* receive can be either pure receive (no prologue),
+       or a transmit (of prologue) followed by a receive */
+
+    /* enable PIO interrupts */
+    NVIC_EnableIRQ(hDevice->pDevInfo->pioIRQn);
+
+    /* enable i2c for PIO-based receive interrupts */
+    hDevice->pDev->MCTL |= (uint16_t)(BITM_I2C_MCTL_IENMRX | BITM_I2C_MCTL_MASEN);
+
+    /* program HW receive count */
+    if (hDevice->remainingReadCount  > BITM_I2C_MRXCNT_EXTEND) {
+        hDevice->pDev->MRXCNT        = BITM_I2C_MRXCNT_EXTEND;
+        hDevice->remainingReadCount -= BITM_I2C_MRXCNT_EXTEND;
+    } else {
+        hDevice->pDev->MRXCNT        = hDevice->remainingReadCount - 1u;
+        hDevice->remainingReadCount  = 0u;
+    }
+
+    /* if we have prologue (the dreaded "COMBINED FORMAT"), transmit the prologue prior to data receive... */
+    if (hDevice->remainingPrologueCount) {
+
+        /* -OR- in transmit interrupt enable if we have prologue data to send */
+        hDevice->pDev->MCTL |= BITM_I2C_MCTL_IENMTX;
+
+        /* how many bytes are available in the transmit FIFO (should be 2) */
+        uint16_t writableBytes = 2u - (hDevice->pDev->MSTAT & (uint16_t)BITM_I2C_MSTAT_MTXF);
+
+        /* prime transmit FIFO with any prologue data (memory address or command) first */
+        while ((0u < writableBytes) && (hDevice->remainingPrologueCount)) {
+            hDevice->pDev->MTX = *hDevice->pNextPrologueByte;
+            hDevice->pNextPrologueByte++;
+            hDevice->remainingPrologueCount--;
+            writableBytes--;
+        }
+
+        /* initiate prologue transmit with read bit cleared (for prologue write) */
+        /* (read sequence is initiated by transmit handler, *after* prologue is transmitted...) */
+        hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress & (uint16_t)(~READ_NOT_WRITE);
+
+    } else {
+
+        /* no prologue... initiate pure receive (read bit already set) */
+        hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress;
+    }
+}
+
+
+/* reset the I2C HW */
+static ADI_I2C_RESULT i2cReset(ADI_I2C_HANDLE const hDevice) {
+
+	volatile uint16_t temp;
+    /* disable interrupts */
+    NVIC_DisableIRQ(hDevice->pDevInfo->pioIRQn);
+
+    /* reset any pending interrupts and TX FIFO (W1C) */
+    temp = hDevice->pDev->MSTAT;
+    hDevice->pDev->MSTAT = temp;
+
+    /* discard any rogue RX FIFO data */
+    while (uZero16 != (hDevice->pDev->STAT & (uint16_t)BITM_I2C_STAT_MRXF)) {
+        volatile uint16_t delme ADI_UNUSED_ATTRIBUTE = hDevice->pDev->MTX;
+    }
+
+    /* reset i2c control register */
+    hDevice->pDev->MCTL = 0u;
+
+    /* reset repeat start logic */
+    hDevice->pDev->SHCTL = 1u;
+
+    /* (re)assert controller defaults from user config values */
+    hDevice->pDev->MCTL         = hDevice->pDevInfo->pConfig->MasterControlRegister;
+    hDevice->pDev->DIV          = hDevice->pDevInfo->pConfig->ClockDividerRegister;
+    hDevice->pDev->SHCTL        = hDevice->pDevInfo->pConfig->SharedControlRegister;
+    hDevice->pDev->TCTL         = hDevice->pDevInfo->pConfig->TimingControlRegister;
+    hDevice->pDev->ASTRETCH_SCL = hDevice->pDevInfo->pConfig->ClockStretchRegister;
+    hDevice->i2cDeviceAddress   = hDevice->pDevInfo->pConfig->TargetSlaveAddress;
+
+    return ADI_I2C_SUCCESS;
+}
+
+
+/**********************************************************************************\
+|********************************interrupt handlers********************************|
+\**********************************************************************************/
+
+
+/* transmit interrupt handler */
+static void transmitHandler(ADI_I2C_HANDLE const hDevice) {
+
+    /* how much room in transmit FIFO? */
+    /* DO ***NOT*** USE MSTAT:MTXF... FALSELY INDICATES MOSTLY FULL FIFO! */
+    uint16_t writableBytes = 2u - ((hDevice->pDev->STAT & (uint16_t)BITM_I2C_STAT_MTXF) >> BITP_I2C_STAT_MTXF);
+
+    /* for extended prologues, continue pushing prologue data out */
+    while ((0u < writableBytes) && (hDevice->remainingPrologueCount)) {
+        hDevice->pDev->MTX = *hDevice->pNextPrologueByte;
+        hDevice->pNextPrologueByte++;
+        hDevice->remainingPrologueCount--;
+        writableBytes--;
+    }
+
+    /* once the prologue is done... */
+    if (0u == hDevice->remainingPrologueCount) {
+
+        /* if we have a completed prologue associated with a read sequence...  */
+        if (0u < hDevice->remainingReadCount) {
+
+            /* initiate the read (subsequently driven by receive interrupt handler) */
+            hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress;
+
+        } else {
+
+            /* normal transmit interrupt: just push transmit data */
+            while ((0u < writableBytes) && (hDevice->remainingWriteCount)) {
+                hDevice->pDev->MTX = *hDevice->pNextWriteByte;
+                hDevice->pNextWriteByte++;
+                hDevice->remainingWriteCount--;
+                writableBytes--;
+            }
+        }
+    }
+
+    /* clear TX interrupt as we complete transmit writes */
+    if (0u == hDevice->remainingWriteCount) {
+        hDevice->pDev->MSTAT = BITM_I2C_MSTAT_MTXREQ;
+    }
+}
+
+
+/* receive interrupt handler */
+static void receiveHandler(ADI_I2C_HANDLE const hDevice) {
+
+    /* note: we never need to deal with prologue data here... it will already be transmitted... */
+
+    /* how many bytes in receive FIFO? */
+    uint16_t readableBytes = (hDevice->pDev->STAT & (uint16_t)BITM_I2C_STAT_MRXF) >> BITP_I2C_STAT_MRXF;
+
+    /* pull bytes from fifo */
+    while (0u < readableBytes) {
+
+        readableBytes--;
+
+        /* pull one byte */
+        *hDevice->pNextReadByte = (uint8_t)hDevice->pDev->MRX;
+        hDevice->pNextReadByte++;
+
+        if ((0u == hDevice->pDev->MCRXCNT) && (hDevice->remainingReadCount)) {
+
+            /* if HW read counter goes to zero with remaining data to read, reprogram read count */
+            if (hDevice->remainingReadCount  > BITM_I2C_MRXCNT_EXTEND) {
+                /* use extended count flag for large remaining counts... */
+                hDevice->pDev->MRXCNT        = BITM_I2C_MRXCNT_EXTEND;
+                hDevice->remainingReadCount -= BITM_I2C_MRXCNT_EXTEND;
+            } else {
+                /* new count fits... no need for extended count */
+                hDevice->pDev->MRXCNT        = hDevice->remainingReadCount - 1u;
+                hDevice->remainingReadCount  = 0u;
+            }
+        }
+    }
+}
+
+/* completion interrupt handler */
+static void completeHandler(ADI_I2C_HANDLE const hDevice) {
+
+    /* block on busy until all transmit data has both left
+       the fifo AND has been fully serialized to the bus. */
+    while (I2C_BUSY) {
+        ;
+    }
+
+    /* disable interrupts */
+    NVIC_DisableIRQ(hDevice->pDevInfo->pioIRQn);
+
+    /* reset controller to default user config state */
+    hDevice->pDev->MCTL = (uint16_t)gConfigInfo->MasterControlRegister;
+}
+
+
+/* error interrupt handler */
+static void errorHandler(ADI_I2C_HANDLE const hDevice) {
+
+    /* accumulate I2C bus errors */
+
+    if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_NACKADDR)) {
+        hDevice->hwErrors |= ADI_I2C_HW_ERROR_NACK_ADDR;
+    }
+
+    if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_NACKDATA)) {
+        hDevice->hwErrors |= ADI_I2C_HW_ERROR_NACK_DATA;
+    }
+
+    if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_ALOST)) {
+        hDevice->hwErrors |= ADI_I2C_HW_ERROR_ARBITRATION_LOST;
+    }
+
+    /* if no other errors exist, note we had an unexpected error */
+    if (hDevice->hwErrors == ADI_I2C_HW_ERROR_NONE) {
+        hDevice->hwErrors = ADI_I2C_HW_ERROR_UNEXPECTED_ERROR;
+    }
+}
+
+
+/**********************************************************************************\
+|*****************************I2C INTERRUPT HANDLER********************************|
+\**********************************************************************************/
+
+
+/* PIO mode I2C interrupt handler */
+void I2C0_Master_Int_Handler(void) {
+
+    bool bPost = false;
+
+    /* rtos prologue */
+    ISR_PROLOG()
+        ;
+
+    /* recover device handle */
+    ADI_I2C_HANDLE const hDevice = (ADI_I2C_HANDLE)i2c_device_info[0].hDevice;
+
+    /* save destructive status read... */
+    hDevice->hwStatus = hDevice->pDev->MSTAT;
+
+    /* if RepeatStart request is pending, rewrite address register ASAP (and only once) to block stop bit */
+    if (hDevice->bRepeatStart) {
+        hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress;
+        hDevice->bRepeatStart = false;  /* just do it once on 1st interrupt */
+    }
+
+    /* forward TX interrupts to TX handler */
+    if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_MTXREQ)) {
+        transmitHandler(hDevice);
+    }
+
+    /* forward RX interrupts to RX handler */
+    if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_MRXREQ)) {
+        receiveHandler(hDevice);
+    }
+
+    /* dispatch any errors */
+    if (uZero16 != (hDevice->hwStatus & ADI_I2C_STATUS_ERROR_MASK)) {
+        errorHandler(hDevice);
+
+      /* post on bus error */
+      bPost = true;
+    }
+
+    /* transmit complete */
+    if (uZero16 != (hDevice->hwStatus & BITM_I2C_MSTAT_TCOMP)) {
+        completeHandler(hDevice);
+
+      /* post on completion */
+      bPost = true;
+    }
+
+    /* just post once */
+    if (true == bPost) {
+        SEM_POST(hDevice);
+    }
+
+    /* rtos epilogue */
+    ISR_EPILOG()
+        ;
+}
+
+/*! \endcond */
+
+
+/* @} */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_data.c
new file mode 100755
index 00000000000..6d7a63801c8
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_data.c
@@ -0,0 +1,120 @@
+/*
+ *****************************************************************************
+ * @file:    adi_i2c_data.c
+ * @brief:   Data declaration for I2C Device Driver
+ *****************************************************************************
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be coni2ccuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef ADI_I2C_DATA_C
+#define ADI_I2C_DATA_C
+
+ /*! \cond PRIVATE */
+
+#include <adi_processor.h>
+#include "adi_i2c_def.h"
+#include "adi_i2c_config.h"
+
+/* Stores the information about the specific device */
+static ADI_I2C_DEVICE_INFO i2c_device_info [ADI_I2C_NUM_INSTANCES] =
+{
+    /* fixed instance data for the singular I2C0 controller */
+    {
+        I2C_MST_EVT_IRQn,              /* pio interrupt number         */
+        (ADI_I2C_TypeDef *)pADI_I2C0,  /* i2c controller pointer       */
+        NULL,                          /* pointer to user config data  */
+        NULL                           /* i2c device handle (user mem) */
+    },
+
+    /* no other i2c instances at this time */
+};
+
+/* build I2C Application configuration array */
+static ADI_I2C_CONFIG gConfigInfo[ADI_I2C_NUM_INSTANCES] =
+{
+    /* the one-and-only (so far) instance data for I2C, I2C0... */
+    {
+        /**** I2C_MCTL Master Control register *** */
+        (
+            /* note: Master IENMTX and IENMRX (transmit and receive interrupts) are managed dynamically */
+            ( ADI_I2C_CFG_MCTL_MXMITDEC     << BITP_I2C_MCTL_MXMITDEC     ) |
+            ( ADI_I2C_CFG_MCTL_IENCMP       << BITP_I2C_MCTL_IENCMP       ) |
+            ( ADI_I2C_CFG_MCTL_IENACK       << BITP_I2C_MCTL_IENACK       ) |
+            ( ADI_I2C_CFG_MCTL_IENALOST     << BITP_I2C_MCTL_IENALOST     ) |
+            ( ADI_I2C_CFG_MCTL_STRETCHSCL   << BITP_I2C_MCTL_STRETCHSCL   ) |
+            ( ADI_I2C_CFG_MCTL_LOOPBACK     << BITP_I2C_MCTL_LOOPBACK     ) |
+            ( ADI_I2C_CFG_MCTL_COMPLETE     << BITP_I2C_MCTL_COMPLETE     ) |
+            ( ADI_I2C_CFG_MCTL_MASEN        << BITP_I2C_MCTL_MASEN        )
+        ),
+
+        /**** I2C_DIV Clock Divider register *** */
+        (
+            ( ADI_I2C_CFG_DIV_HIGH          << BITP_I2C_DIV_HIGH          ) |
+            ( ADI_I2C_CFG_DIV_LOW           << BITP_I2C_DIV_LOW           )
+        ),
+
+        /**** I2C_SHCTL Shared Control register *** */
+        (
+            ( ADI_I2C_CFG_SHCTL_RST         << BITP_I2C_TCTL_FILTEROFF    )
+        ),
+
+        /**** I2C_TCTL Timing control register *** */
+        (
+            ( ADI_I2C_CFG_TCTL_FILTEROFF    << BITP_I2C_SHCTL_RST         ) |
+            ( ADI_I2C_CFG_TCTL_THDATIN      << BITP_I2C_TCTL_THDATIN      )
+        ),
+
+        /**** I2C_ASTRETCH Master Clock Stretch register *** */
+        (
+            ( ADI_I2C_CFG_ASTRETCH_MST      << BITP_I2C_ASTRETCH_SCL_MST  )
+        ),
+
+        /**** Target Slave configuration value (not a register) *** */
+        (
+            ( ADI_I2C_CFG_SLAVE_ADDRESS                                   )
+        ),
+    }
+};
+
+/*! \endcond */
+
+
+#endif /* ADI_I2C_DATA_C */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_def.h
new file mode 100755
index 00000000000..03ba0b5bf92
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_def.h
@@ -0,0 +1,129 @@
+/*!
+ *****************************************************************************
+ @file:    adi_i2c_def.h
+ @brief:   Internal I2C device driver definitions and macros
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+#ifndef ADI_I2C_DEF_H
+#define ADI_I2C_DEF_H
+
+/*! \cond PRIVATE */
+
+#include <drivers/i2c/adi_i2c.h>
+
+#define ADI_I2C_NUM_INSTANCES       (1u)
+#define ADI_I2C_STATUS_ERROR_MASK ( (1u << BITP_I2C_MSTAT_NACKADDR) \
+                                  | (1u << BITP_I2C_MSTAT_NACKDATA) \
+                                  | (1u << BITP_I2C_MSTAT_ALOST)    )
+
+/* Internal Actions */
+static void           submitTransaction  (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction);
+static void           commenceTransmit   (ADI_I2C_HANDLE const hDevice);
+static void           commenceReceive    (ADI_I2C_HANDLE const hDevice);
+static ADI_I2C_RESULT i2cReset           (ADI_I2C_HANDLE const hDevice);
+
+/* interrupt event handlers */
+static void           transmitHandler    (ADI_I2C_HANDLE const hDevice);
+static void           receiveHandler     (ADI_I2C_HANDLE const hDevice);
+static void           completeHandler    (ADI_I2C_HANDLE const hDevice);
+static void           errorHandler       (ADI_I2C_HANDLE const hDevice);
+
+
+/*
+ *****************************************************************************
+ * I2C Configuration structure.
+ *****************************************************************************/
+typedef struct __ADI_I2C_CONFIG {
+    uint16_t MasterControlRegister;  /* I2C_MCTL register configuration.      */
+    uint16_t ClockDividerRegister;   /* I2C_DIV  register.                    */
+    uint16_t SharedControlRegister;  /* I2C_DIV  register.                    */
+    uint16_t TimingControlRegister;  /* I2C_TCTL register.                    */
+    uint16_t ClockStretchRegister;   /* I2C_ASTRETCH register.                */
+    uint16_t TargetSlaveAddress;     /* slave address value (not a register). */
+} ADI_I2C_CONFIG;
+
+
+/* I2C physical device instance data */
+typedef struct __ADI_I2C_DEVICE_INFO {
+    IRQn_Type             pioIRQn;  /* PIO interrupt number                */
+    ADI_I2C_TypeDef      *pDev;     /* pointer to i2c controller           */
+    ADI_I2C_CONFIG       *pConfig;  /* pointer to user config info         */
+    ADI_I2C_HANDLE        hDevice;  /* I2C handle or NULL if uninitialized */
+} ADI_I2C_DEVICE_INFO;
+
+/* I2C driver instance data structure */
+typedef struct __ADI_I2C_DEV_DATA_TYPE {
+
+    /* make sure to synchronize ANY size changes with ADI_I2C_MEMORY_SIZE macro in adi_i2c.h */
+
+    /* device attributes */
+    ADI_I2C_TypeDef      *pDev;
+    ADI_I2C_DEVICE_INFO  *pDevInfo;
+
+
+    /* driver state */
+    uint16_t              hwStatus;
+    bool                  bRepeatStart;
+    uint16_t              i2cDeviceAddress;
+    uint16_t              i2cEncodedDeviceAddress;    /* encoded as 7-bit device address + r/w LSB */
+    bool                  bSubmitCalled;
+
+    /* prologue data */
+    volatile uint8_t     *pNextPrologueByte;
+    volatile uint16_t     remainingPrologueCount;
+
+    /* write data */
+    volatile uint8_t     *pNextWriteByte;
+    volatile uint16_t     remainingWriteCount;
+
+    /* read data */
+    volatile uint8_t     *pNextReadByte;
+    volatile uint16_t     remainingReadCount;
+
+    ADI_I2C_RESULT        result;    /* collector for return status */
+    ADI_I2C_HW_ERRORS     hwErrors;  /* collector for error status */
+
+    SEM_VAR_DECLR        /* blocking object: "Semaphore" for rtos,  "nLowPowerExitFlag" for non-rtos */
+
+} ADI_I2C_DEV_DATA_TYPE;
+
+/*! \endcond */
+
+#endif    /* end of ifndef ADI_I2C_DEF_H */
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/pwr/adi_pwr.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/pwr/adi_pwr.c
new file mode 100755
index 00000000000..a91c53e02ce
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/pwr/adi_pwr.c
@@ -0,0 +1,1904 @@
+/*
+ *****************************************************************************
+ * @file:    adi_pwr.c
+ * @brief:   Power Management driver implementation.
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/*! \addtogroup Power_Driver Power Driver
+ *  @{
+ *  @brief Power Management Driver
+ *  @note The application must include drivers/pwr/adi_pwr.h to use this driver
+ *  @note The API #adi_pwr_EnableClockSource requires the GPIO driver if
+ *  #ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO is set to 1. In that case the
+ *  application must include the GPIO driver sources to avoid link errors.
+ */
+
+
+#include <stdlib.h>     /* for 'NULL' */
+#include <adi_callback.h>
+#include "adi_pwr_def.h"
+#include <adi_pwr_config.h>
+#include <rtos_map/adi_rtos_map.h>
+#include <drivers/pwr/adi_pwr.h>
+#include <drivers/gpio/adi_gpio.h>
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm011 (rule 6.3): Types which specify sign and size should be used
+*   We use bool which is accepted by MISRA but the toolchain does not accept it
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   The rule makes an exception for memory-mapped register accesses.
+* Pm057 (rule 15.2): Every non-empty case clause in a switch statement shall be terminated with a break statement.
+*   In some cases we have return statement instead of break. It is not valid to both return and break in MISRA 2012.
+*/
+#pragma diag_suppress=Pm011,Pm073,Pm050,Pm140,Pm143,Pm057
+#endif /* __ICCARM__ */
+
+/*! \cond PRIVATE */
+
+/*----------------------------------------------------------------------------
+  Internal Clock Variables. The external ones are defined in system.c
+ *---------------------------------------------------------------------------*/
+#ifdef ADI_DEBUG
+/* not needed unless its debug mode */
+extern uint32_t lfClock;    /* "lf_clk" coming out of LF mux             */
+#endif
+
+extern uint32_t hfClock;    /* "root_clk" output of HF mux               */
+extern uint32_t gpioClock;  /* external GPIO clock                       */
+
+static ADI_CALLBACK  gpfCallbackFunction;
+static void *gpPowcbParam = NULL;
+static uint32_t gnLowPowerIntOccFlag = 0u;
+
+/*! \endcond */
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *---------------------------------------------------------------------------*/
+/**
+ * Initialize the clock configuration register with the default values.
+ *
+ * @return      Status
+ *    - #ADI_PWR_SUCCESS : Successfully initialized the power service.
+ */
+ADI_PWR_RESULT adi_pwr_Init (void)
+{
+    /* Enable internal HF oscillators */
+    pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+
+    pADI_CLKG0_OSC->CTL = OSCCTRL_CONFIG_VALUE;
+
+    gpfCallbackFunction = NULL;
+    pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+
+    /* Switch on the internal HF oscillator */
+    pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_HFOSC_EN;
+
+    /* wait for HF OSC to stabilize */
+    while ((pADI_CLKG0_OSC->CTL & (1U << BITP_CLKG_OSC_CTL_HFOSC_OK)) == 0u)
+    {
+    }
+
+    /* Switch over to the internal HF oscillator */
+    pADI_CLKG0_CLK->CTL0 &= ~(BITM_CLKG_CLK_CTL0_CLKMUX);
+
+    /* complete remaining reset sequence */
+    pADI_CLKG0_CLK->CTL0    = CLOCK_CTL0_CONFIG_VALUE;
+    pADI_CLKG0_CLK->CTL1    = CLOCK_CTL1_CONFIG_VALUE;
+    pADI_CLKG0_CLK->CTL2    = CLOCK_CTL2_CONFIG_VALUE;
+    pADI_CLKG0_CLK->CTL3    = CLOCK_CTL3_CONFIG_VALUE;
+    /* No CLK CTL4 */
+    pADI_CLKG0_CLK->CTL5    = CLOCK_CTL5_CONFIG_VALUE;
+
+    /*
+     * Configure the power management registers
+     */
+    pADI_PMG0->IEN          = PWM_INTERRUPT_CONFIG;
+    pADI_PMG0->PWRMOD       = PWM_PWRMOD_CONFIG;
+    pADI_PMG0->CTL1         = PWM_HPBUCK_CONTROL;
+    
+    /* disable external HF crystal oscillator */
+    /* (don't disable LF crystal or the RTC will lose time */
+    pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+    pADI_CLKG0_OSC->CTL &= ~BITM_CLKG_OSC_CTL_HFX_EN;
+
+    NVIC_EnableIRQ(PMG0_VREG_OVR_IRQn);
+    NVIC_EnableIRQ(PMG0_BATT_RANGE_IRQn);
+
+    NVIC_EnableIRQ(CLKG_XTAL_OSC_EVT_IRQn);
+    NVIC_EnableIRQ(CLKG_PLL_EVT_IRQn);
+
+    /* compute new internal clocks based on the newly reset controller */
+    SystemCoreClockUpdate();
+
+    return(ADI_PWR_SUCCESS);
+}
+
+
+/**
+ * @brief  Updates the internal SystemCoreClock variable with current core
+ *         Clock retrieved from cpu registers.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS : Updated core system core clock variables.
+ *
+ * Updates the internal SystemCoreClock variable with current core
+ * Clock retrieved from cpu registers.
+ *
+ * @sa adi_pwr_GetClockFrequency ()
+ */
+ADI_PWR_RESULT adi_pwr_UpdateCoreClock (void)
+{
+    SystemCoreClockUpdate();
+    return(ADI_PWR_SUCCESS);
+}
+
+/**
+ * @brief  Registers or unregister the callback function.
+ *
+ * @details Application can register or unregister the callback function which
+ *          will be called to notify the events from the driver.
+ *
+ * @param[in]  pfCallback   : Callback function pointer.
+ * @param[in]  pcbParam     : Callback parameter.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS            : Successfully installed the callback function.
+ *              - #ADI_PWR_NULL_POINTER [D]   : Failed to install the callback function since the call back function pointer is NULL.
+ */
+ADI_PWR_RESULT adi_pwr_RegisterCallback(
+               const ADI_CALLBACK pfCallback,
+               void *pcbParam
+           )
+{
+
+#ifdef ADI_DEBUG
+   if(pfCallback == NULL)
+   {
+      return(ADI_PWR_NULL_POINTER);
+   }
+#endif
+
+    gpfCallbackFunction = pfCallback;
+    gpPowcbParam        = pcbParam;
+
+    return ADI_PWR_SUCCESS;
+}
+
+/**
+ * @brief  Sets the system external clock frequency
+ *
+ * @param[in]  ExtClkFreq: External clock frequency in Hz
+
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS                : Successfully set the external clock as source.
+ *              - #ADI_PWR_INVALID_CLOCK_SPEED [D]: Specified clock is out of range.
+ *
+ * @sa adi_pwr_GetClockFrequency ()
+ */
+ADI_PWR_RESULT adi_pwr_SetExtClkFreq (const uint32_t ExtClkFreq)
+{
+#ifdef ADI_DEBUG
+    if(ExtClkFreq > MAXIMUM_EXT_CLOCK)
+    {
+         return(ADI_PWR_INVALID_CLOCK_SPEED);
+    }
+#endif
+    gpioClock = ExtClkFreq;
+    return(ADI_PWR_SUCCESS);
+}
+
+/**
+ * @brief  Sets the input clock source for PLL multiplexer.
+ *
+ * @param[in]  eClockID: Clock source to the System PLL multiplexer.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS              : Successfully set the PLL multiplexer clock source.
+ *              - #ADI_PWR_INVALID_CLOCK_ID [D] : Specified clock ID is invalid.
+ *
+ * @sa adi_pwr_SetLFClockMux()
+ */
+ADI_PWR_RESULT  adi_pwr_SetPLLClockMux(const ADI_CLOCK_MUX_ID eClockID)
+{
+    uint32_t tmp;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    /* Validate the given clock ID */
+    switch (eClockID)
+    {
+        case ADI_CLOCK_MUX_SPLL_HFOSC:
+        case ADI_CLOCK_MUX_SPLL_HFXTAL:
+        case ADI_CLOCK_MUX_SPLL_GPIO:
+            break;
+      /* Any other clock ID is not valid since we are configuring the SPLL clock multiplexer.
+       * Only valid input clock to the multiplexer is HFOSC, HFXTAL, GPIO */
+        default:
+            return(ADI_PWR_INVALID_CLOCK_ID);
+    }
+#endif /* ADI_DEBUG */
+
+    /* update the mux setting inside a critical region */
+    ADI_ENTER_CRITICAL_REGION();
+    tmp     =   (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_PLL_IPSEL);
+    tmp     |=  (( (uint32_t)eClockID - (uint32_t)ADI_CLOCK_MUX_SPLL_HFOSC) << BITP_CLKG_CLK_CTL0_PLL_IPSEL);
+    pADI_CLKG0_CLK->CTL0 = tmp;
+    ADI_EXIT_CRITICAL_REGION();
+
+    return(ADI_PWR_SUCCESS);
+}
+
+/**
+ * @brief  Sets the input clock for low frequency clock multiplexer.
+ *
+ * @param[in]  eClockID: Clock source to the low frequency clock multiplexer.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS                : Successfully LF clock multiplexer clock source.
+ *              - #ADI_PWR_INVALID_CLOCK_ID [D]   : Specified clock ID is invalid.
+ *
+ * @sa adi_pwr_SetRootClockMux()
+ * @sa adi_pwr_SetPLLClockMux()
+ */
+ADI_PWR_RESULT  adi_pwr_SetLFClockMux(const ADI_CLOCK_MUX_ID eClockID)
+{
+    uint32_t tmp;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    switch (eClockID)
+    {
+
+        case ADI_CLOCK_MUX_LFCLK_LFOSC:
+        case ADI_CLOCK_MUX_LFCLK_LFXTAL:
+            break;
+      /* Any other clock ID is not valid since we are configuring the Low frequency clock multiplexer.
+       * Only valid input clock to the multiplexer is LFOSC, LFXTAL */
+
+    default:
+        return(ADI_PWR_INVALID_CLOCK_ID);
+
+    }
+#endif /* ADI_DEBUG */
+
+    /* update the mux setting inside a critical region */
+    ADI_ENTER_CRITICAL_REGION();
+
+    pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+    tmp = (pADI_CLKG0_OSC->CTL & ~BITM_CLKG_OSC_CTL_LFCLK_MUX);
+    tmp |=(((uint32_t)eClockID - (uint32_t)ADI_CLOCK_MUX_LFCLK_LFOSC) << BITP_CLKG_OSC_CTL_LFCLK_MUX);
+    pADI_CLKG0_OSC->CTL = tmp;
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    return(ADI_PWR_SUCCESS);
+}
+
+/**
+ * @brief  Sets clock source for the Reference clock multiplexer.
+ *
+ * @param[in]  eClockID: Clock source to the reference clock multiplexer.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS                : Successfully set the source for reference clock multiplexer.
+ *              - #ADI_PWR_INVALID_CLOCK_ID [D]   : Specified clock ID is invalid.
+ *
+ * @sa adi_pwr_SetLFClockMux()
+ * @sa adi_pwr_SetRootClockMux()
+ * @sa adi_pwr_SetPLLClockMux()
+ */
+
+ADI_PWR_RESULT  adi_pwr_SetRefClockMux(const ADI_CLOCK_MUX_ID eClockID)
+{
+    uint32_t tmp;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    switch (eClockID)
+    {
+
+        case ADI_CLOCK_MUX_REF_HFOSC_CLK:
+        case ADI_CLOCK_MUX_REF_HFXTAL_26MHZ_CLK:
+        case ADI_CLOCK_MUX_REF_HFXTAL_16MHZ_CLK:
+            break;
+      /* Any other clock ID is not valid since we are configuring the out clock multiplexer.*/
+
+        default:
+            return(ADI_PWR_INVALID_CLOCK_ID);
+    }
+#endif /* ADI_DEBUG */
+
+    /* update the mux setting inside a critical region */
+    ADI_ENTER_CRITICAL_REGION();
+
+    tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_RCLKMUX);
+    tmp |=(((uint32_t)eClockID - (uint32_t)ADI_CLOCK_MUX_REF_HFOSC_CLK) << BITP_CLKG_CLK_CTL0_RCLKMUX);
+    pADI_CLKG0_CLK->CTL0 = tmp;
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    return(ADI_PWR_SUCCESS);
+}
+
+/**
+ * @brief  Sets the source for the root clock multiplexer.
+ *
+ * @param[in]  eClockID: Clock source to the root clock multiplexer.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS                : Successfully set the source for root clock multiplexer.
+ *              - #ADI_PWR_INVALID_CLOCK_ID [D]   : Specified clock ID is invalid.
+ *
+ * @sa adi_pwr_SetLFClockMux()
+ * @sa adi_pwr_SetPLLClockMux()
+ */
+ADI_PWR_RESULT  adi_pwr_SetRootClockMux(const ADI_CLOCK_MUX_ID eClockID)
+{
+    uint32_t tmp;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    switch (eClockID)
+    {
+       case ADI_CLOCK_MUX_ROOT_HFOSC:
+       case ADI_CLOCK_MUX_ROOT_HFXTAL:
+       case ADI_CLOCK_MUX_ROOT_SPLL:
+       case ADI_CLOCK_MUX_ROOT_GPIO:
+            break;
+		  /* Any other clock ID is not valid since we are configuring the root clock multiplexer.
+		   * Only valid input clock to the multiplexer is HFOSC, HFXTAL, SPLL, GPIO */
+		default:
+        	return(ADI_PWR_INVALID_CLOCK_ID);
+    }
+#endif /* ADI_DEBUG */
+
+    /* update the mux setting inside a critical region */
+    ADI_ENTER_CRITICAL_REGION();
+
+    tmp =  (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_CLKMUX);
+    tmp |= (((uint32_t)eClockID - (uint32_t)ADI_CLOCK_MUX_ROOT_HFOSC) << BITP_CLKG_CLK_CTL0_CLKMUX);
+    pADI_CLKG0_CLK->CTL0 = tmp;
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    return(ADI_PWR_SUCCESS);
+}
+
+
+/**
+ * @brief  Gets the system external clock frequency.
+ *         Gets the clock frequency of the source connected to the external GPIO clock input source.
+ *
+ * @param [in]  pExtClock : Pointer to write the external clock frequency.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS          : Successfully returning the external clock frequency.
+ *              - #ADI_PWR_NULL_POINTER [D] : If the given pointer is pointing to NULL.
+ *              - #ADI_PWR_FAILURE [D]      : The system is not initialized yet. Call SystemInit before calling this API.
+ */
+ADI_PWR_RESULT adi_pwr_GetExtClkFreq (uint32_t *pExtClock)
+{
+#ifdef ADI_DEBUG
+    /* Trap here if the app fails to set the external clock frequency. */
+    if (0u == gpioClock)
+    {
+        return (ADI_PWR_FAILURE);
+    }
+
+    if(pExtClock == NULL)
+    {
+        return (ADI_PWR_NULL_POINTER);
+    }
+#endif
+    *pExtClock = gpioClock;
+    return  ADI_PWR_SUCCESS;
+}
+
+
+/*!
+ * @brief      Get the frequency of the given clock.
+ *             Obtain individual peripheral clock frequencies
+ *
+ * @param[in]  eClockId : Clock identifier
+ * @param[out] pClock   : Pointer to a location to store the clock frequency.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS                      : Successfully returned the queried clock.
+ *              - #ADI_PWR_SYSTEM_NOT_INITIALIZED [D]   : The system is not initialized yet. Call SystemInit before calling this API.
+ *
+ * @sa adi_PWR_SetClockDivide
+ * @sa SystemSetClockDivider
+*/
+ADI_PWR_RESULT adi_pwr_GetClockFrequency (const ADI_CLOCK_ID eClockId, uint32_t *pClock )
+{
+    uint32_t src, nDiv;
+
+#ifdef ADI_DEBUG
+    /* trap here if the app fails to call SystemInit(). */
+    if ((0u == hfClock) || (0u == lfClock))
+    {
+        return ADI_PWR_SYSTEM_NOT_INITIALIZED;
+    }
+#endif
+
+    /* refresh internal clock variables */
+    SystemCoreClockUpdate();
+    src = hfClock;
+
+    switch (eClockId) {
+
+        /* HCLOCK domain */
+        case ADI_CLOCK_HCLK:
+            nDiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT;
+            break;
+
+        /* PCLOCK domain */
+        case ADI_CLOCK_PCLK:
+            nDiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_PCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_PCLKDIVCNT;
+            break;
+
+        default:
+            return ADI_PWR_INVALID_CLOCK_ID;
+    } /* end switch */
+
+    if(nDiv == 0u)
+    {
+        nDiv = 1u;
+    }
+
+    *pClock =  (src/nDiv);
+
+    return ADI_PWR_SUCCESS;
+}
+
+
+/*!
+    @brief      Enable/disable individual peripheral clocks.
+
+    @param[in]  eClockGate       Clock identifier
+    @param[in]  bEnable          Flag to indicate whether to enable/disable individual clock.
+                                 true  - to enable individual clock.
+                                 false - to disable individual clock.
+
+    @return     Status
+                    - #ADI_PWR_SUCCESS  if we have successfully enabled or disabled the clock.
+
+    @details    Manage individual peripheral clock gates to enable or disable the clocks to the peripheral.
+*/
+ADI_PWR_RESULT adi_pwr_EnableClock (const ADI_CLOCK_GATE eClockGate, const bool bEnable)
+{
+    uint32_t mask;
+    ADI_INT_STATUS_ALLOC();
+
+    mask = (uint16_t)eClockGate;
+    /* update the Clock Gate register in a critical region */
+    ADI_ENTER_CRITICAL_REGION();
+
+        /* NOTE NEGATIVE LOGIC!!! */
+        if (bEnable == true) {
+
+        /* clear disable bit */
+            pADI_CLKG0_CLK->CTL5 &= ~mask;
+        } else {
+            /* set disable bit */
+            pADI_CLKG0_CLK->CTL5 |= mask;
+        }
+
+    /* end critical region */
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_PWR_SUCCESS;
+}
+
+
+/*!
+    @brief      Sets the clock divide factor for an individual clock group.
+
+    @param[in]  eClockId   Clock domain identifier.
+    @param[in]  nDiv       Clock divide value to be set (right-justified uint16_t).
+
+    @return     Status
+                    - #ADI_PWR_SUCCESS                      if successfully set the given clock divide factor.
+                    - #ADI_PWR_INVALID_CLOCK_DIVIDER [D]    if the divider is out of range.
+                    - #ADI_PWR_INVALID_CLOCK_ID [D]         if the given clock is invalid.
+                    - #ADI_PWR_INVALID_CLOCK_RATIO [D]      if the given clock ratio invalid.
+
+    @details    Manage individual peripheral clock dividers.
+
+    @sa         SystemGetClockFrequency
+*/
+ADI_PWR_RESULT adi_pwr_SetClockDivider (const ADI_CLOCK_ID eClockId, const uint16_t nDiv)
+{
+    uint32_t mask;
+    uint32_t value;
+    uint32_t tmp;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    uint32_t hdiv, pdiv;
+#endif  /*ADI_DEBUG*/
+
+    switch (eClockId)
+    {
+        case ADI_CLOCK_HCLK:
+#ifdef ADI_DEBUG
+            /* Verify the divide factor is within the range */
+            if ((nDiv > CLOCK_MAX_DIV_VALUE) || (nDiv < CLOCK_MIN_DIV_VALUE))
+            {
+                return ADI_PWR_INVALID_CLOCK_DIVIDER;
+            }
+
+            /* verify PCLK freq is <= requested HCLK */
+            pdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_PCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_PCLKDIVCNT;
+            hdiv = nDiv;
+            if (hdiv > pdiv) {
+                return ADI_PWR_INVALID_CLOCK_SPEED;
+            }
+
+            /* verify new PDIV:HDIV ratio will be integral */
+            if ((pdiv % hdiv) != 0u) 
+            {
+                return ADI_PWR_INVALID_CLOCK_RATIO;
+            }
+#endif  /*ADI_DEBUG*/
+
+            mask = BITM_CLKG_CLK_CTL1_HCLKDIVCNT;
+            value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_HCLKDIVCNT;
+            break;
+
+        case ADI_CLOCK_PCLK:
+#ifdef ADI_DEBUG
+
+            /* Verify the divide factor is within the range */
+            if ((nDiv > CLOCK_MAX_DIV_VALUE) || (nDiv < CLOCK_MIN_DIV_VALUE))
+            {
+                return ADI_PWR_INVALID_CLOCK_DIVIDER;
+            }
+
+            /* verify requested PCLK freq is <= HCLK */
+            pdiv = nDiv;
+            hdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT;
+            if (hdiv > pdiv) {
+                return ADI_PWR_INVALID_CLOCK_SPEED;
+            }
+
+            /* verify new PDIV:HDIV ratio will be integral */
+            if ((pdiv % hdiv) != 0u) 
+            {
+                return ADI_PWR_INVALID_CLOCK_RATIO;
+            }
+#endif  /*ADI_DEBUG*/
+            mask = BITM_CLKG_CLK_CTL1_PCLKDIVCNT;
+            value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_PCLKDIVCNT;
+            break;
+
+        case ADI_CLOCK_ACLK:
+#ifdef ADI_DEBUG
+            /* Verify the divide factor is within the range */
+            if ((nDiv > ACLK_MAX_DIV_VALUE) || (nDiv < ACLK_MIN_DIV_VALUE))
+            {
+                return ADI_PWR_INVALID_CLOCK_DIVIDER;
+            }
+
+            /* verify requested ACLK freq is <= HCLK */
+            pdiv = nDiv;
+            hdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT;
+            if (hdiv > pdiv) {
+                return ADI_PWR_INVALID_CLOCK_SPEED;
+            }
+
+            /* verify new PDIV:HDIV ratio will be integral */
+            if ((pdiv % hdiv) != 0u)
+            {
+                return ADI_PWR_INVALID_CLOCK_RATIO;
+            }
+#endif  /*ADI_DEBUG*/
+
+            mask = BITM_CLKG_CLK_CTL1_ACLKDIVCNT;
+            value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_ACLKDIVCNT;
+            break;
+
+
+        default:
+            return ADI_PWR_INVALID_CLOCK_ID;
+    } /* end switch */
+
+    /* critical region */
+    ADI_ENTER_CRITICAL_REGION();
+
+    /* read-modify-write without any interrupts */
+    /* change in a tmp variable and write entire new value all at once */
+    tmp = pADI_CLKG0_CLK->CTL1;
+    tmp &= ~mask;                       /* blank the field */
+    tmp |= value;                       /* set the new value */
+    pADI_CLKG0_CLK->CTL1 = tmp;         /* write the new value */
+
+    /* end critical region */
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* refresh internal clock variables */
+    SystemCoreClockUpdate();
+
+    return ADI_PWR_SUCCESS;
+}
+
+/*!
+ * @brief       To Enable/disable clock sources.
+ *
+ * @param[in]   eClockSource :    Clock source identifier.
+ * @param[in]   bEnable      :    Enable (true) or disable (false) the clock source.
+ *
+ * @return      Status
+ *                  - #ADI_PWR_SUCCESS          if the clock source powers up successfully.
+ *                  - #ADI_PWR_INVALID_PARAM    if the clock source is not valid.
+ *
+ * @details    Enables or disables clock sources without additional checks, by writing a "1" or "0" to the enable bit.
+ *
+ */
+ADI_PWR_RESULT adi_pwr_EnableClockSource (const ADI_CLOCK_SOURCE_ID eClockSource, const bool bEnable)
+{
+    uint32_t val = 0u;
+    volatile uint32_t *pReg = NULL;
+    uint32_t nMask = 0u;
+    ADI_INT_STATUS_ALLOC();
+
+    /* This switch statement does not handle every value in the ADI_CLOCK_SOURCE_ID enumeration
+     * which results on a gcc warning. This is done intentionally:
+     * ADI_CLOCK_SOURCE_LFOSC is not checked  because it is enabled always and it cannot be disabled
+     * ADI_CLOCK_SOURCE_GPIO is only checked if a specific configuration macro is defined
+     */
+    switch(eClockSource)
+    {
+        case ADI_CLOCK_SOURCE_HFXTAL:
+            val     =   (1u << BITP_CLKG_OSC_CTL_HFX_EN);
+            pReg    =   &pADI_CLKG0_OSC->CTL;
+            nMask   =   BITM_CLKG_OSC_CTL_HFX_OK;
+            break;
+
+        case ADI_CLOCK_SOURCE_LFXTAL:
+            val     =   (1u << BITP_CLKG_OSC_CTL_LFX_EN);
+            pReg    =   &pADI_CLKG0_OSC->CTL;
+            nMask   =   BITM_CLKG_OSC_CTL_LFX_OK;
+            break;
+
+        case ADI_CLOCK_SOURCE_HFOSC:
+            val     =   (1u << BITP_CLKG_OSC_CTL_HFOSC_EN);
+            pReg    =   &pADI_CLKG0_OSC->CTL;
+            nMask   =   BITM_CLKG_OSC_CTL_HFOSC_OK;
+            break;
+
+        case ADI_CLOCK_SOURCE_SPLL:
+            val     =   (1u << BITP_CLKG_CLK_CTL3_SPLLEN);
+            pReg    =   &pADI_CLKG0_CLK->CTL3;
+            nMask   =   BITM_CLKG_CLK_CTL3_SPLLEN;
+            break;
+
+#if (ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO == 1)
+        case ADI_CLOCK_SOURCE_GPIO:
+            if(adi_gpio_PullUpEnable(ADI_GPIO_PORT1,ADI_GPIO_PIN_10,false) != ADI_GPIO_SUCCESS)
+            {
+               return(ADI_PWR_FAILURE);
+            }
+            if(adi_gpio_InputEnable(ADI_GPIO_PORT1,ADI_GPIO_PIN_10,true) != ADI_GPIO_SUCCESS)
+            {
+               return ADI_PWR_SUCCESS;
+            }
+            break;
+#endif
+
+        default:
+            return(ADI_PWR_INVALID_PARAM);
+
+    } /* end switch */
+
+    ADI_ENTER_CRITICAL_REGION();
+
+        pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+        if (bEnable == true)
+        {
+            *pReg |= val;
+        }
+        else
+        {
+            *pReg &= ~val;
+        }
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    if((nMask !=0u) && (bEnable == true))
+    {
+        while(0u== (pADI_CLKG0_OSC->CTL & nMask)){}
+    }
+
+    return (ADI_PWR_SUCCESS);
+}
+
+
+/*!
+ * @brief       Return the status of a clock source.
+ *
+ * @param[in]    eClockSource  : Clock source identifier.
+ * @param[out]   peStatus      : Pointer to variable of type  #ADI_CLOCK_SOURCE_STATUS for storing clock source status.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS               if the clock source is disabled.
+ *              - #ADI_PWR_NULL_POINTER [D]      if the given pointer is pointing to NULL.
+
+ *  @details    Return the status of a clock source.
+ *
+ */
+ADI_PWR_RESULT adi_pwr_GetClockStatus (const ADI_CLOCK_SOURCE_ID eClockSource, ADI_CLOCK_SOURCE_STATUS *peStatus)
+{
+    uint32_t val = pADI_CLKG0_OSC->CTL;
+
+#ifdef ADI_DEBUG
+    if(peStatus == NULL)
+    {
+        return ADI_PWR_NULL_POINTER;
+    }
+#endif /* ADI_DEBUG */
+
+    *peStatus = ADI_CLOCK_SOURCE_DISABLED;
+
+    switch(eClockSource)
+    {
+        case ADI_CLOCK_SOURCE_HFOSC:
+            if ((val & BITM_CLKG_OSC_CTL_HFOSC_EN) != 0u)
+            {
+                /* Clock source enabled, now check for stable */
+                if ((val & BITM_CLKG_OSC_CTL_HFOSC_OK) != 0u)
+                {
+                    *peStatus = ADI_CLOCK_SOURCE_ENABLED_STABLE;
+                }
+                else
+                {
+                    *peStatus  = ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE;
+                }
+            }
+            break;
+
+        case ADI_CLOCK_SOURCE_HFXTAL:
+            if ((val & BITM_CLKG_OSC_CTL_HFX_EN) != 0u)
+            {
+                /* Clock source enabled, now check for stable */
+                if ((val & BITM_CLKG_OSC_CTL_HFX_OK) != 0u)
+                {
+                    *peStatus  = ADI_CLOCK_SOURCE_ENABLED_STABLE;
+                }
+                else
+                {
+                    *peStatus  = ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE;
+                }
+            }
+            break;
+
+        case ADI_CLOCK_SOURCE_LFXTAL:
+            if ((val & BITM_CLKG_OSC_CTL_LFX_EN) != 0u)
+            {
+                /* Clock source enabled, now check for stable */
+                if ((val & BITM_CLKG_OSC_CTL_LFX_OK) != 0u)
+                {
+                    *peStatus  = ADI_CLOCK_SOURCE_ENABLED_STABLE;
+                }
+                else
+                {
+                    *peStatus  = ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE;
+                }
+            }
+            break;
+
+        case ADI_CLOCK_SOURCE_LFOSC:
+            /* Clock source enabled, now check for stable */
+            if ((val & BITM_CLKG_OSC_CTL_LFOSC_OK) != 0u)
+            {
+                *peStatus  = ADI_CLOCK_SOURCE_ENABLED_STABLE;
+            }
+            else
+            {
+                *peStatus  = ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE;
+            }
+            break;
+
+        /* Since the clock through GPIO is supplied externally we cannot get
+           the clock status for GPIO */
+        case ADI_CLOCK_SOURCE_GPIO:
+        default:
+            *peStatus  =  ADI_CLOCK_SOURCE_ID_NOT_VALID;
+             break;
+
+    } /* end switch */
+
+    return ADI_PWR_SUCCESS;
+}
+
+/*!
+ * @brief       Enable/Disable the clock interrupt to monitor status of LFXTAL, HFXTAL and PLL.
+ *
+ * @param[in]   eIrq    : Specify which interrupt need to be enable/disabled.
+   @param[in]   bEnable : Specifies to enable/disable the specified interrupt.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS  Enabled the specified interrupt.
+ *
+ * @sa adi_pwr_SetVoltageRange()
+ */
+
+ADI_PWR_RESULT adi_pwr_EnableClockInterrupt(const ADI_PWR_CLOCK_IRQ eIrq, const bool bEnable)
+{
+    ADI_INT_STATUS_ALLOC();
+    volatile uint32_t *pReg = NULL;
+    uint32_t tmp;
+
+    switch(eIrq)
+    {
+        /*! Interrupt for root clock monitor and Clock Fail */
+        case ADI_PWR_ROOT_CLOCK_MON_IEN:
+            pReg = &pADI_CLKG0_OSC->CTL;
+            break;
+
+        /*! Interrupt for LFXTAL clock monitor and Clock Fail */
+        case ADI_PWR_LFXTAL_CLOCK_MON_IEN:
+            pReg = &pADI_CLKG0_OSC->CTL;
+            break;
+
+        /*! Interrupt when LFXTAL clock becomes stable/unstable */
+        case ADI_PWR_LFXTAL_STATUS_IEN:
+            pReg = &pADI_CLKG0_CLK->CTL0;
+            break;
+
+        /*! Interrupt when HFXTAL clock becomes stable/unstable */
+        case ADI_PWR_HFXTAL_STATUS_IEN:
+            pReg = &pADI_CLKG0_CLK->CTL0;
+            break;
+
+        /*! Interrupt when PLL-LOCK/PLL-UNLOCK  */
+        case ADI_PWR_PLL_STATUS_IEN:
+            pReg = &pADI_CLKG0_CLK->CTL3;
+            break;
+
+        default:
+            break;
+    }
+
+    ADI_ENTER_CRITICAL_REGION();
+
+    tmp = *pReg;
+
+    if(bEnable == true)
+    {
+        tmp |= (uint32_t)eIrq;
+    }
+    else
+    {
+        tmp &= ~((uint32_t)eIrq);
+    }
+
+    /* If we have to write to oscillator control register unlock it */
+    if(pReg == &pADI_CLKG0_OSC->CTL)
+    {
+        pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+    }
+    *pReg = tmp;
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    return(ADI_PWR_SUCCESS);
+}
+
+
+/*!
+ * @brief       Program PLL frequency.
+ *
+ * @param[in]   nDivFactor   PLL divider(M).
+ * @param[in]   nMulFactor   PLL Multiplier(N)
+ * @param[in]   bDiv2        PLL DIV2 parameter.
+ * @param[in]   bMul2        PLL DIV2 parameter.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS                    if the PLL has been programmed successfully.
+ *              - #ADI_PWR_OPERATION_NOT_ALLOWED [D]  if trying to program SPLL and SPLL drives the system clock.
+ *              - #ADI_PWR_INVALID_CLOCK_ID [D]       if the clock identifier does not match either PLL.
+ *
+ *  @details    Program PLL frequency (parameters M, N, DIV2) forSystem PLL(SPLL).
+ *
+ *              SPLL = input clock * ["(N *  (1+ bMul2 )" / "((1+bDiv2)*M)" ]
+ *              where input clock can be HFOSC or HFXTAL.
+ */
+ADI_PWR_RESULT adi_pwr_SetPll(uint8_t  nDivFactor, const uint8_t  nMulFactor, const bool bDiv2, const bool bMul2)
+{
+    uint32_t                val, cfg = 0u;
+    uint8_t nTempDivFactor = nDivFactor, nTempMulFactor = nMulFactor;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    /* Check if multiplication factor and division factor is more than 6 bits */
+    if (((nMulFactor & ~0x3Fu) != 0u) || ((nDivFactor & ~0x3Fu) != 0u))
+    {
+        return ADI_PWR_INVALID_CLOCK_DIVIDER;
+    }
+
+    /* Check if the PLL is multipexed in as root clock source, parameters should not change in that case */
+    if((pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_CLKMUX) ==
+       ((uint32_t)((ADI_CLOCK_MUX_ROOT_SPLL - ADI_CLOCK_MUX_ROOT_HFOSC) << BITP_CLKG_CLK_CTL0_CLKMUX))) 
+    {
+         return ADI_PWR_OPERATION_NOT_ALLOWED;
+    }
+#endif
+
+     if(nTempDivFactor < MINIMUM_PLL_DIVIDER)
+     {
+         nTempDivFactor = MINIMUM_PLL_DIVIDER;
+     }
+     if(nTempMulFactor < MINIMUM_PLL_MULTIPLIER)
+     {
+         nTempMulFactor = MINIMUM_PLL_MULTIPLIER;
+     }
+
+    cfg =  (((uint32_t)nTempDivFactor) << BITP_CLKG_CLK_CTL3_SPLLMSEL)|( ((uint32_t) nTempMulFactor) << BITP_CLKG_CLK_CTL3_SPLLNSEL);
+
+    if(bDiv2 == true)
+    {
+      cfg |= (1u <<BITP_CLKG_CLK_CTL3_SPLLDIV2);
+    }
+    if(bMul2 == true)
+    {
+      cfg |= (1u <<BITP_CLKG_CLK_CTL3_SPLLMUL2);
+    }
+
+    /* critical region */
+    ADI_ENTER_CRITICAL_REGION();
+
+    val = pADI_CLKG0_CLK->CTL3;
+    val &= ~( BITM_CLKG_CLK_CTL3_SPLLMUL2 | BITM_CLKG_CLK_CTL3_SPLLMSEL | BITM_CLKG_CLK_CTL3_SPLLDIV2 | BITM_CLKG_CLK_CTL3_SPLLNSEL);
+    val |= cfg;
+    pADI_CLKG0_CLK->CTL3 = val;
+
+   /* end critical region */
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_PWR_SUCCESS;
+}
+
+
+/*!
+ * @brief       Enable/Disable the power management interrupt.
+ *
+ * @param[in]   eIrq    : Specify which interrupt need to be enable/disabled.
+   @param[in]   bEnable : Specifies to enable/disable  the interrupt.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS      Enabled the specified interrupt.
+ *              - #ADI_PWR_FAILURE [D]  Enabling the battery monitoring interrupt when range is set to safe range (VBAT > 2.75 ).
+ *
+ * @note : User should configure the appropriate voltage range before enabling the interrupt for battery voltage range.
+ *
+ * @sa adi_pwr_SetVoltageRange()
+ */
+ADI_PWR_RESULT adi_pwr_EnablePMGInterrupt(const ADI_PWR_PMG_IRQ eIrq, const bool bEnable)
+{
+   ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+   if(((pADI_PMG0->IEN & BITM_PMG_IEN_RANGEBAT) == 0u) || (eIrq != ADI_PWR_BATTERY_VOLTAGE_RANGE_IEN))
+   {
+       return(ADI_PWR_FAILURE);
+   }
+#endif
+
+  ADI_ENTER_CRITICAL_REGION();
+  if(bEnable == true)
+  {
+    pADI_PMG0->IEN  |= (uint32_t)eIrq;
+  }
+  else
+  {
+    pADI_PMG0->IEN  &= ~(uint32_t)(eIrq);
+  }
+  ADI_EXIT_CRITICAL_REGION();
+
+  return(ADI_PWR_SUCCESS);
+}
+
+
+
+/*!
+ * @brief       Enable/disable LFXTAL bypass mode.
+ *
+   @param[in]   bEnable : Specifies to enable/disable  the LFXTAL bypass mode
+ *\n                      true: To enable LFXTAL bypass mode.
+ * \n                     false: To disable LFXTAL bypass mode.
+ * @return      Status
+ *                     - #ADI_PWR_SUCCESS     Enabled/Disabled LFXTAL bypass mode.
+ *                     - #ADI_PWR_FAILURE[D]  Failed to Enable/Disable LFXTAL bypass mode.
+ *
+ */
+ADI_PWR_RESULT  adi_pwr_EnableLFXTALBypass(const bool bEnable)
+{
+    volatile uint32_t nDelay = 0xFFFFFFu;
+    if(bEnable == true)
+    {
+        /* Write the oscillator key */
+        pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+        /* Disable the LFXTAL */
+        pADI_CLKG0_OSC->CTL  &= ~(BITM_CLKG_OSC_CTL_LFX_EN);
+        /* Wait till status de-asserted. */
+        while(nDelay != 0u)
+        {
+            if((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK) == 0u)
+            {
+                break;
+            }
+            nDelay--;
+        }
+#ifdef ADI_DEBUG
+        if(nDelay == 0u)
+        {
+            return(ADI_PWR_FAILURE);
+        }
+#endif
+        pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+        /* Enable the BYPASS mode */
+        pADI_CLKG0_OSC->CTL  |= (BITM_CLKG_OSC_CTL_LFX_BYP);
+        /* Wait till status asserted. */
+        nDelay = 0xFFFFFFu;
+        while(nDelay != 0u)
+        {
+            if(((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK)== BITM_CLKG_OSC_CTL_LFX_OK))
+            {
+                break;
+            }
+            nDelay--;
+        }
+#ifdef ADI_DEBUG
+        if(nDelay == 0u)
+        {
+            return(ADI_PWR_FAILURE);
+        }
+#endif
+
+    }
+    else
+    {
+        /* Write the oscillator key */
+        pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+        /* Disable  the BYPASS mode */
+        pADI_CLKG0_OSC->CTL  &= ~(BITM_CLKG_OSC_CTL_LFX_BYP);
+        /* Wait till status de-asserted. */
+        while(nDelay != 0u)
+        {
+            if((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK) == 0u)
+            {
+                break;
+            }
+            nDelay--;
+        }
+#ifdef ADI_DEBUG
+        if(nDelay == 0u)
+        {
+            return(ADI_PWR_FAILURE);
+        }
+#endif
+    }
+
+    return(ADI_PWR_SUCCESS);
+}
+
+
+
+/*!
+ * @brief       Enables or disables the LFXTAL Robust mode.
+ *              The Robust mode enables the LFXTAL oscillator to work also when an additional resistive
+ *              load is placed between the crystal pins and GND. This feature is capable of tolerating
+ *              the presence of impurities on the PCB board, where these impurities allow a high-resistance
+ *              leakage path from the crystal pins to ground, which can cause problems to the circuit operation
+ *
+ *  @param[in]  bEnable  :  Flag which indicates whether to enable or disable LFXTAL Robust mode.
+                            true    - Enable Robust mode.
+                            false   - Disable Robust mode.
+ *  @return     Status
+ *                      - #ADI_PWR_SUCCESS     Enabled/Disabled LFXTAL Robust mode.
+ *
+ * @sa adi_pwr_SetLFXTALRobustModeLoad()
+ */
+ADI_PWR_RESULT adi_pwr_EnableLFXTALRobustMode( const bool bEnable )
+{
+    /* Write the oscillator key */
+    pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+
+    if(bEnable == true)
+    {
+        pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_LFX_ROBUST_EN;
+    }
+    else
+    {
+        pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_LFX_ROBUST_EN);
+    }
+
+    return(ADI_PWR_SUCCESS);
+}
+
+/*!
+ * @brief       Enable/Disable the LFXTAL Fail Auto switch.
+ *              Enables/Disable automatic Switching of the LF Mux to LF OSC on LF XTAL Failure.
+ *
+ *  @param[in]  bEnable   :  Flag which indicates whether to enable/disable LFXTAL Auto switch.
+ *                           true  - Enable LFXTAL Auto switch.
+ *                           false - Disable LFXTAL Auto switch.
+ *  @return     Status
+ *                - #ADI_PWR_SUCCESS     Enabled/Disabled LFXTAL Auto switch mode.
+ */
+ADI_PWR_RESULT adi_pwr_EnableLFXTALFailAutoSwitch( const bool  bEnable )
+{
+    /* Write the oscillator key */
+    pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+
+    if(bEnable == true)
+    {
+        pADI_CLKG0_OSC->CTL  |= BITM_CLKG_OSC_CTL_LFX_AUTSW_EN;
+    }
+    else
+    {
+        pADI_CLKG0_OSC->CTL  &= ~(BITM_CLKG_OSC_CTL_LFX_AUTSW_EN);
+    }
+    return(ADI_PWR_SUCCESS);
+}
+
+
+/*!
+ * @brief       Sets the LFXT Robust Mode Load.
+ *              Selects the amount of loading tolerated when LFXTAL robust mode is enabled.
+ *
+ *  @param[in]  eLoad   :  Amount of loading tolerance required.
+ *  @return     Status
+ *                 - #ADI_PWR_SUCCESS     Successfully set the load tolerance for LFXTAL Robust mode.
+ *
+ * @sa adi_pwr_EnableLFXTALRobustMode()
+ */
+ADI_PWR_RESULT adi_pwr_SetLFXTALRobustModeLoad( const ADI_PWR_LFXTAL_LOAD eLoad )
+{
+    uint32_t tmp;
+
+    tmp =   pADI_CLKG0_OSC->CTL & ~BITM_CLKG_OSC_CTL_LFX_ROBUST_LD;
+    tmp |=  ((uint32_t)eLoad) << BITP_CLKG_OSC_CTL_LFX_ROBUST_LD;
+
+    /* Write the oscillator key */
+    pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+    pADI_CLKG0_OSC->CTL = tmp;
+
+    return(ADI_PWR_SUCCESS);
+}
+
+/*!
+ * @brief       To enable/disable auto switching of root clock to HFOSC upon detection of Root clock failure.
+ *              This feature is valid only when the ROOT clock monitor is enabled. The root clock monitoring
+ *              can be enabled by using the API #adi_pwr_EnableClockInterrupt.
+ *
+ *  @param[in]  bEnable   :  Flag which indicates whether to enable or disable Root clock auto switch.
+ *                           true  - Enable Root clock auto switch.
+                             false - Disable Root clock auto switch.
+ *  @return     Status
+ *                 - #ADI_PWR_SUCCESS     Successfully set the load tolerance for LFXTAL Robust mode.
+ *
+ * @sa adi_pwr_EnableClockInterrupt()
+ */
+ADI_PWR_RESULT adi_pwr_EnableRootClockFailAutoSwitch( const bool bEnable )
+{
+    /* Write the oscillator key */
+    pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+
+    if(bEnable == true)
+    {
+        pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_ROOT_AUTSW_EN;
+    }
+    else
+    {
+        pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_ROOT_AUTSW_EN);
+    }
+
+    return(ADI_PWR_SUCCESS);
+}
+
+
+/*!
+ * @brief       Sets the HF Oscillator divide factor.
+ *
+ *              Sets the divide factor for the clocks derived from the HF oscillator clock.
+ *
+ * @param[in]  eDivFactor :  HF Clock divide factor to be set.
+ *
+ * @return     Status
+ *                 - #ADI_PWR_SUCCESS   Successfully set the clock divide factor for HF Oscillator.
+ *
+ * @note        When the HF Oscillator auto divide by 1 is set, the divide factor set is automatically
+ *              changed to 1 when coming out of Flexi mode. Application should set it back to the
+ *              required divide after coming out of Flexi mode.
+ *
+ * @sa adi_pwr_EnableHFOscAutoDivBy1()
+ */
+ADI_PWR_RESULT adi_pwr_SetHFOscDivFactor( const ADI_PWR_HFOSC_DIV  eDivFactor )
+{
+    uint32_t tmp;
+
+    tmp =  (pADI_CLKG0_CLK->CTL2 & ~BITM_CLKG_CLK_CTL2_HFOSCDIVCLKSEL);
+    tmp |= ((uint32_t) eDivFactor << BITP_CLKG_CLK_CTL2_HFOSCDIVCLKSEL);
+    pADI_CLKG0_CLK->CTL2 = tmp;
+
+    return(ADI_PWR_SUCCESS);
+}
+
+
+/*!
+ * @brief       Enable or disable the HF oscillator automatic divide by 1 during wakeup from Flexi mode.
+ *
+ *              This is used to enable/disable the fast wakeup from Flexi power mode. When the fast wakeup
+ *              from Flexi mode is enabled, the frequency undivided 26MHz HF oscillator clock itself will
+ *              be used during the wake up. The undivided HFOSC clock is selected automatically by setting
+ *              the HF oscillator divide factor to 1. This updated divided by 1 clock selection will remain
+ *              same until the new divider value is set.
+ *
+ *              When disabled the HF Oscillator divide factor will remain unchanged during the wakeup.
+ *
+ * @param[in]  bEnable :  Flag which indicates whether HF oscillator automatic divide by 1 is enabled/disabled.
+ *                        'true'  - To enable automatic divide by 1.
+ *                        'false' - To disable automatic divide by 1.
+ *
+ * @return     Status
+ *                 - #ADI_PWR_SUCCESS   Successfully enable/disabled HF Oscillator automatic divide by 1.
+ *
+ * @sa adi_pwr_SetHFOscDivFactor()
+ */
+ADI_PWR_RESULT adi_pwr_EnableHFOscAutoDivBy1( const bool bEnable )
+{
+    if(bEnable == true)
+    {
+        pADI_CLKG0_CLK->CTL2 |= BITM_CLKG_CLK_CTL2_HFOSCAUTODIV_EN;
+    }
+    else
+    {
+        pADI_CLKG0_CLK->CTL2 &= ~(BITM_CLKG_CLK_CTL2_HFOSCAUTODIV_EN);
+    }
+
+    return(ADI_PWR_SUCCESS);
+}
+
+
+/*!
+ * @brief       Set the clock output through the GPIO.
+ *
+ * @param[in]   eClockOutput : Clock to be output through the GPIO pin.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS  Successfully set the GPIO clock output.
+ */
+ADI_PWR_RESULT  adi_pwr_SetGPIOClockOutput( const ADI_CLOCK_OUTPUT_ID eClockOutput )
+{
+    uint32_t tmp;
+
+    tmp =  (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_CLKOUT);
+    tmp |= ((uint32_t)eClockOutput << BITP_CLKG_CLK_CTL0_CLKOUT);
+    pADI_CLKG0_CLK->CTL0 = tmp;
+
+    return(ADI_PWR_SUCCESS);
+}
+
+
+/*!
+ * @brief       Enables or disables the HP Buck.
+ *
+ * @param[in]   bEnable : Flag which indicates whether to enable or disable HPBuck
+ *                        'true'  - To enable HPBuck.
+ *                        'false' - To disable HPBuck.
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS  Successfully enabled or disabled HPBUCK successfully.
+ */
+ADI_PWR_RESULT  adi_pwr_EnableHPBuck(const bool bEnable)
+{
+  if(bEnable == true)
+  {
+    pADI_PMG0->CTL1  |= BITM_PMG_CTL1_HPBUCKEN;
+  }
+  else
+  {
+    pADI_PMG0->CTL1  &= ~(BITM_PMG_CTL1_HPBUCKEN);
+  }
+
+  return(ADI_PWR_SUCCESS);
+}
+
+
+/*!
+ * @brief       Enable or disable the HPBuck Low Power mode.
+ *              The HPBUCK Low Power mode can be selected, when the Chip is in Flexi Power mode
+ *              and low power modules such as Timer, Beeper only are enabled.
+ *
+ * @param[in]   bEnable : Flag which indicates whether to enable or disable HPBuck low power mode.
+ *                        'true'  - Enable HPBuck low power mode.
+ *                        'false' - Disable HPBuck low power mode.
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS  Successfully enabled or disabled the HPBuck low power mode.
+ */
+ADI_PWR_RESULT adi_pwr_EnableHPBuckLowPowerMode( const bool bEnable )
+{
+  if(bEnable == true)
+  {
+    pADI_PMG0->CTL1  |= BITM_PMG_CTL1_HPBUCK_LOWPWR_MODE;
+  }
+  else
+  {
+    pADI_PMG0->CTL1  &= ~(BITM_PMG_CTL1_HPBUCK_LOWPWR_MODE);
+  }
+
+  return(ADI_PWR_SUCCESS);
+}
+
+/*!
+ * @brief  Set the HP Buck load mode.
+ *
+ *         HP Buck load mode can be set based on the system load.
+ *         The low load mode can be set when the system is running below 26Mhz.
+ *         The High load mode can be set when the system is running at greater than 26Mhz.
+ *
+ * @param[in]   eLoadMode : Load mode to be set.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS  Successfully set the load mode.
+ */
+ADI_PWR_RESULT adi_pwr_SetHPBuckLoadMode( const ADI_PWR_HPBUCK_LD_MODE eLoadMode )
+{
+  if(eLoadMode == ADI_PWR_HPBUCK_LD_MODE_HIGH)
+  {
+    pADI_PMG0->CTL1  |= BITM_PMG_CTL1_HPBUCK_LD_MODE;
+  }
+  else
+  {
+    pADI_PMG0->CTL1  &= ~(BITM_PMG_CTL1_HPBUCK_LD_MODE);
+  }
+
+  return(ADI_PWR_SUCCESS);
+}
+
+
+/*!
+ * @brief       Function to retrieve the wakeup from shut down mode status.
+ *
+ * @param[in]   peStatus    : Pointer to #ADI_PWR_WAKEUP_STATUS for returning the wakeup status.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS: Successfully returned the shut down status.
+ */
+ADI_PWR_RESULT adi_pwr_GetWakeUpStatus(ADI_PWR_WAKEUP_STATUS  *peStatus)
+{
+    *peStatus =(ADI_PWR_WAKEUP_STATUS) pADI_PMG0->SHDN_STAT;
+    return(ADI_PWR_SUCCESS);
+}
+
+
+/*!
+ * @brief      To  Monitor voltage range of battery.
+ *
+ * @param[in]   eRange    : Specify the voltage range for the battery.
+ *
+ * @return      Status
+ *              - #ADI_PWR_SUCCESS: Successfully programmed battery range.
+ *  @details
+ *
+ */
+ADI_PWR_RESULT adi_pwr_SetVoltageRange(const ADI_PWR_VOLTAGE_RANGE eRange)
+{
+    uint32_t tmp;
+
+    tmp = (pADI_PMG0->IEN & ~BITM_PMG_IEN_RANGEBAT);
+    tmp |= ((uint32_t)eRange << BITP_PMG_IEN_RANGEBAT);
+    pADI_PMG0->IEN = tmp;
+
+    return(ADI_PWR_SUCCESS);
+}
+
+/*! \cond PRIVATE */
+
+/*
+ * Interrupt handler for PLL interrupts.
+ */
+void PLL_Int_Handler(void)
+{
+     ISR_PROLOG();
+
+    /* As the same status word is shared between two interrupts
+       Crystal_osc_Int_Handler and PLL_Int_Handler
+       check and clear status bits handled in this handler */
+     uint32_t nStatus = (pADI_CLKG0_CLK->STAT0 &
+                        (BITM_CLKG_CLK_STAT0_SPLLUNLK | BITM_CLKG_CLK_STAT0_SPLLLK));
+
+     /* If a callback is registered notify the events */
+     if(gpfCallbackFunction != NULL)
+     {
+        if((nStatus & BITM_CLKG_CLK_STAT0_SPLLUNLK ) != 0u)
+        {
+            /* PLL unlock event */
+            gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_PLLC_UNLOCK,(void *)0);
+        }
+        else if((nStatus & BITM_CLKG_CLK_STAT0_SPLLLK) != 0u)
+        {
+            /* PLL lock event */
+            gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_PLLC_LOCK,(void *)0);
+        }
+        else
+        {
+           /* Do nothing */
+        }
+     }
+
+     /* Clear the status bits */
+     pADI_CLKG0_CLK->STAT0 = nStatus;
+
+     ISR_EPILOG();
+}
+
+/*
+ * Interrupt handler for oscillator interrupts.
+ */
+void Crystal_osc_Int_Handler(void)
+{
+     ISR_PROLOG();
+
+     /* As the same status word is shared between two interrupts
+        Crystal_osc_Int_Handler and PLL_Int_Handler
+        check and clear status bits handled in this handler */
+     uint32_t nClkStatus = (pADI_CLKG0_CLK->STAT0 &
+                         (BITM_CLKG_CLK_STAT0_HFXTALNOK |
+                          BITM_CLKG_CLK_STAT0_HFXTALOK  |
+                          BITM_CLKG_CLK_STAT0_LFXTALOK  |
+                          BITM_CLKG_CLK_STAT0_LFXTALNOK));
+
+     /* Check if the interrupt was generated due to failure in Root Clock or LFXTAL */
+     uint32_t nOscStatus = (pADI_CLKG0_OSC->CTL &   (BITM_CLKG_OSC_CTL_LFX_FAIL_STA   |
+                                                     BITM_CLKG_OSC_CTL_ROOT_FAIL_STA  |
+                                                     BITM_CLKG_OSC_CTL_ROOT_AUTSW_STA |
+                                                     BITM_CLKG_OSC_CTL_LFX_AUTSW_STA ));
+
+     uint32_t nEvent = 0u;
+
+
+     if(gpfCallbackFunction != NULL)
+     {
+         /* Is the interrupt caused due to HFXTAL or LFXTAL status */
+         if(nClkStatus != 0u)
+         {
+                  if ((nClkStatus & BITM_CLKG_CLK_STAT0_HFXTALNOK) != 0u) { nEvent |= ADI_PWR_EVENT_OSC_HFXTAL_CLOCK_NO_OK;  }
+             else if ((nClkStatus & BITM_CLKG_CLK_STAT0_HFXTALOK)  != 0u) { nEvent |= ADI_PWR_EVENT_OSC_HFXTAL_CLOCK_OK; }
+             else if ((nClkStatus & BITM_CLKG_CLK_STAT0_LFXTALOK)  != 0u) { nEvent |= ADI_PWR_EVENT_OSC_LFXTAL_CLOCK_OK; }
+             else if ((nClkStatus & BITM_CLKG_CLK_STAT0_LFXTALNOK) != 0u) { nEvent |= ADI_PWR_EVENT_OSC_LFXTAL_CLOCK_NO_OK; }
+             else { /* do nothing */ }
+
+             if(nEvent != 0u)  { gpfCallbackFunction( gpPowcbParam, nEvent, (void *)0u); }
+
+         }
+         /* Or is the interrupt caused due to Root Clock or LFXTAL failure status */
+         else if(nOscStatus != 0u)
+         {
+            /* Did the LFXTAL failed */
+            if( (nOscStatus & BITM_CLKG_OSC_CTL_LFX_FAIL_STA) != 0u)
+            {
+                /* Notifiy LFXTAL failure */
+                gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_LFXTAL_MON_FAIL, (void *)0u);
+
+                /* Did the HW auto switched to LFOSC due to LFXTAL failure */
+                if((nOscStatus & BITM_CLKG_OSC_CTL_LFX_AUTSW_STA) != 0u)
+                {
+                   /* Notify about the auto switch to LFOSC */
+                   gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_LFXTAL_AUTO_SWITCH, (void *)0u);
+                }
+            }
+            /* Did the root clock failed */
+            else if((nOscStatus & BITM_CLKG_OSC_CTL_ROOT_FAIL_STA) != 0u)
+            {
+               /* Indicate about the root clock failure */
+               gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_ROOT_CLOCK_MON_FAIL, (void *)0u);
+
+               /* Did the HW auto switched to HFOSC due to root clock failure */
+               if((nOscStatus & BITM_CLKG_OSC_CTL_ROOT_AUTSW_STA) != 0u)
+               {
+                  /* Notify about auto switch to HFOSC */
+                  gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_ROOT_CLOCK_FAIL_AUTO_SWITCH, (void *)0u);
+               }
+            }
+            else
+            {
+               /* Do nothing */
+            }
+         }
+         else
+         {
+            /* Do nothing */
+         }
+     }
+
+    /* Clear the staus bits */
+    if(nClkStatus != 0u)
+    {
+      pADI_CLKG0_CLK->STAT0 = nClkStatus;
+    }
+    else if(nOscStatus  != 0u)
+    {
+        /* Write the oscillator key to clear the status bits */
+        pADI_CLKG0_OSC->KEY = ADI_OSC_KEY;
+
+        /* Clear only status bits */
+        pADI_CLKG0_OSC->CTL |= nOscStatus;
+    }
+    else
+    {
+        /* Do nothing */
+    }
+
+    ISR_EPILOG();
+}
+
+/*
+ * Interrupt handler for battery voltage interrupt.
+ */
+void Battery_Voltage_Int_Handler(void)
+{
+    ISR_PROLOG();
+    uint32_t nStatus = pADI_PMG0->PSM_STAT;
+
+     if ((nStatus & BITM_PMG_PSM_STAT_VBATUNDR) != 0u)
+     {
+     if(gpfCallbackFunction != NULL)
+     {
+             gpfCallbackFunction( gpPowcbParam, (uint32_t)nStatus, (void *)0);
+     }
+         pADI_PMG0->PSM_STAT |= (BITM_PMG_PSM_STAT_VBATUNDR);
+     }
+    ISR_EPILOG();
+}
+
+/*
+ * Interrupt handler for battery voltage interrupt.
+ */
+void Vreg_over_Int_Handler(void)
+{
+    ISR_PROLOG();
+     uint32_t nStatus = pADI_PMG0->PSM_STAT;
+
+     if(gpfCallbackFunction != NULL)
+     {
+        if ((nStatus & BITM_PMG_PSM_STAT_VREGOVR) != 0u)
+        {
+            gpfCallbackFunction(gpPowcbParam, (uint32_t)ADI_PWR_EVENT_VREG_OVER_VOLTAGE, NULL);
+        }
+        if ((nStatus & BITM_PMG_PSM_STAT_VREGUNDR) != 0u)
+        {
+            gpfCallbackFunction(gpPowcbParam, (uint32_t)ADI_PWR_EVENT_VREG_UNDER_VOLTAGE, NULL);
+        }
+     }
+     pADI_PMG0->PSM_STAT |= (nStatus &(BITM_PMG_PSM_STAT_VREGOVR | BITM_PMG_PSM_STAT_VREGUNDR));
+    ISR_EPILOG();
+}
+
+/*! \endcond */
+/*!
+    @brief      Puts the processor into given low power mode.
+
+    @param[in]  PowerMode          One of the ADI_PWR_POWER_MODE enum values, defining the specific
+                                   low-power modes to use.
+
+    @param[in,out] pnInterruptOccurred
+                                   Control parameter selection low-power operation.  Either a NULL pointer
+                                   for automatic hardware-based sleeping between interrupts, or a pointer
+                                   to uint32_t for software looping sleep between interrupts.
+
+                                   If a pointer to uint32_t is passed in, the integer must be \b 0 on entry,
+                                   and will be set to \b 0 on exit.
+
+                                   When a NULL is passed, it means the application wants the low-power
+                                   implementation to use the automatic "sleep-on-exit" hardware sleep
+                                   mode in which wakeup interrupts are dispatched and then automatically
+                                   put the processor back to sleep on exit.  All interrupts execute the
+                                   same WFI instruction (no looping) under hardware control, which results
+                                   in a faster re-sleep than the software mode.
+
+                                   When a non-NULL value is passed, it is interpreted as a pointer to a
+                                   shared integer application control variable allowing the wake-up
+                                   interrupts to control whether/when the control loop should re-sleep the
+                                   processor as each interrupt exits.  Any interrupt that sets the variable
+                                   will cause the sleep loop to exit.  Otherwise, exiting interrupts will
+                                   cause the core to re-sleep until the variable is set.  Each interrupt executes
+                                   a different WFI instruction inside a software loop (slower re-sleep).
+
+    @param[in]  PriorityMask       A right-justified (un shifted) wakeup interrupt priority mask, corresponding
+                                   to the programmable interrupt priority encoding scheme defined by the Cortex
+                                   NVIC controller.  The \a PriorityMask value blocks interrupts with an equal
+                                   or lower priority than the specified level, such that only higher-priority
+                                   interrupts (less in numerical value) than the priority mask awake the
+                                   processor.  A zero-valued \a PriorityMask disables interrupt masking.
+
+    @return     Status
+                    - #ADI_PWR_SUCCESS                    If successfully put the processor into low power mode.
+                    - #ADI_PWR_INVALID_PARAM[D]           PriorityMask contains unimplemented hardware bits.
+
+
+
+    Puts the processor into a low-power mode with interrupt-based wakeup(s).  Applications specify the low-power
+    mode, a pointer to an application-defined interrupt variable, and an interrupt priority mask controlling the
+    interrupt priority level that may awake the processor.
+
+    @par pnInterruptOccurred
+    When NULL, the processor is automatically put back to sleep as awaking interrupts exit.  This mode employs
+    the hardware "sleep-on-exit" system control register bit: SLEEPONEXIT_BIT in conjunction with the "wait-for-
+    interrupt" (WFI) instruction to implement a persistent sleep mode.
+
+    When non-Null, a software strategy is used to control sleeping.  As awakening interrupts are processed, they
+    can increment the interrupt controlling variable and thereby cause the sleep mode to be exited.  Note that all 
+    interrupts share a common variable and any interrupt that sets the variable will cause the sleep mode to be 
+    exited.
+
+    Use of the \a pnInterruptOccurred parameter provides a mechanism to resolve two potential hibernation trouble
+    spots: 1) the inherent race between the intended wakeup interrupt and the execution of the Wait-For-Interrupt
+    instruction (WFI) used to sleep the processor, and 2) unrelated interrupts (of sufficient priority)
+    that may terminate the wait prematurely.
+
+    In the first case of the race condition, the race is avoided by testing the \a pnInterruptOccurred variable prior
+    to the WFI within a common critical section.  This allows the #adi_pwr_EnterLowPowerMode() implementation
+    to insure the intended wakeup interrupt has not occurred already and control whether to sleep the processor.
+    This insures the intended wakeup interrupt has not already occurred prior to the wait, thereby eliminating the
+    race condition otherwise present.
+
+    In the second case of an unrelated interrupt terminating the sleep prematurely, the problem is solved by
+    requiring the interrupt handler(s) which is(are) intended to awake the sleeping processor to set the
+    application-defined \a pnInterruptOccurred variable in their respective interrupt handler(s).  This insures only those
+    interrupts that explicitly set the variable will break the sleeping processor out of the sleep cycle.  Other
+    (incidental) interrupts put the processor back to sleep after the interrupt because the variable would not have been set.
+    This is why there is a loop around the WFI instruction.
+
+    The \a pnInterruptOccurred variable must be initialized to zero before first use, and this should be done
+    prior to enabling any interrupt which may set it (otherwise interrupts may be missed). If this variable is
+    global or static then static initialization to zero or false will be sufficient.
+
+    The variable should only be set, from an interrupt handler, by calling adi_pwr_ExitLowPowerMode() and passing
+    the variable by reference. The variable should not be assigned to directly, other than for initialization.
+
+    #adi_pwr_EnterLowPowerMode() will always clear the variable again before returning, so it does not
+    need to be cleared by user code on each use. Explicitly clearing the variable, outside of #adi_pwr_EnterLowPowerMode()
+    runs the risk of missing interrupts.
+
+    @par PriorityMask
+    A zero-valued \a PriorityMask disables interrupt masking, leaving all interrupts eligible to awake the
+    sleeping processor.  This means that zero-valued interrupts cannot be masked.  A non-zero \a PriorityMask
+    limits interrupts that may awake the sleeping processor to those with a higher priority level (lower
+    numerically) than the specified \a PriorityMask value.
+
+    Each "programmable" peripheral interrupt has an associated priority-level register (which defaults to
+    zero) within the Nested Vectored Interrupt Controller (NVIC).  The number of interrupt priority encoding
+    bits is defined by constant __NVIC_PRIO_BITS and is a fixed silicon attribute configured during chip
+    design.  The interrupt priority-level registers range in width from 3 to 8 bits.
+
+    This processor uses 3-bit priority encoding, allowing priority levels ranging between 0 (the highest,
+    default programmable priority) and 7 (the lowest).  For example, if the \a PriorityMask parameter is
+    set to 3, only interrupts with assigned priority 0, 1, and 2 may awake the processor.  Since default
+    priority of all programmable interrupts is 0, setting up maskable interrupts requires that they be
+    demoted in priority (raised numerically) relative to interrupts that are intended to awake the processor.
+
+    @note    The number of priority levels is uncorrelated with the actual number of interrupts or their position
+             in the Interrupt Vector Table (IVT).  Interrupt priorities may be programmed individually.\n\n
+
+    @note    The priority levels are actually stored in the core as a left-justified value in an 8-bit field.
+             The #adi_pwr_EnterLowPowerMode() API takes care of aligning the passed \a PriorityMask value to the
+             core register (BASEPRI).\n\n
+
+    @note    The default priority level for all interrupts is zero, which implies it is impossible to mask interrupts
+             with a default zero-level priority encoding.  All interrupt priorities must be managed to create meaningful
+             interrupt masks for low-power wakeups, as described above.\n\n
+
+    @warning Do not modify the BASEPRI register (used for masking interrupt priority) during interrupts that take
+             the core out of low-power mode momentarily.  The BASEPRI register is saved/restored on low-power mode
+             entry/exit to honor user priority requests.  Interrupt-level changes to BASEPRI will be clobbered on
+             low-power exit as the saved value is restored.\n\n
+
+    @sa      adi_pwr_ExitLowPowerMode
+*/
+ADI_PWR_RESULT adi_pwr_EnterLowPowerMode ( const ADI_PWR_POWER_MODE PowerMode,
+                                           uint32_t volatile *      pnInterruptOccurred,
+                                           const uint8_t            PriorityMask
+                                         )
+{
+    uint32_t savedPriority;
+    uint32_t scrSetBits = 0u;
+    uint32_t scrClrBits = 0u;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+
+    /* verify the requested priority mask bits are right-justified and don't exceed __NVIC_PRIO_BITS in width */
+    if ((PriorityMask & ~((1u << __NVIC_PRIO_BITS) - 1u)) != 0u)
+    {
+        return ADI_PWR_INVALID_PARAM;
+    }
+
+#endif  /* ADI_DEBUG */
+
+    /* pre-calculate the sleep-on-exit set/clear bits */
+    if(NULL == pnInterruptOccurred) {
+        scrSetBits |= SCB_SCR_SLEEPONEXIT_Msk;
+
+        /* point to private control variable when in hardware (sleep-on-exit) mode */
+        pnInterruptOccurred = &gnLowPowerIntOccFlag;
+    }
+
+    /* pre-calculate the deepsleep and sleep-on-exit set/clear bits */
+    switch (PowerMode) {
+
+        case ADI_PWR_MODE_ACTIVE:    /* Note: this value is a "reserved" PWRMODE register code. */
+            return ADI_PWR_SUCCESS;  /* avoids the reserved value "1" being written to PWRMODE. */
+
+        case ADI_PWR_MODE_FLEXI:  /* wfi without deepsleep or sleep-on-exit */
+            scrClrBits |= (uint32_t)(BITM_NVIC_INTCON0_SLEEPDEEP | BITM_NVIC_INTCON0_SLEEPONEXIT);
+            break;
+
+        case ADI_PWR_MODE_HIBERNATE:  /* wfi with deepsleep and sleep-on-exit per pnInterruptOccurred setting */
+            scrSetBits |= BITM_NVIC_INTCON0_SLEEPDEEP;
+
+            break;
+
+        case ADI_PWR_MODE_SHUTDOWN:  /* wfi with both deepsleep and sleep-on-exit */
+            /* Note: sleep-on-exit causes WFI to never exit and wakeup is only through system reset. */
+            scrSetBits |= (uint32_t)(BITM_NVIC_INTCON0_SLEEPDEEP | BITM_NVIC_INTCON0_SLEEPONEXIT);
+            break;
+
+        default:
+            return ADI_PWR_INVALID_POWER_MODE;
+
+    } /* end switch */
+
+    /* put the power mode and system control mods, as well as the WFI loop inside a critical section */
+    ADI_ENTER_CRITICAL_REGION();
+
+        { /* these lines must be in a success-checking loop if they are not inside critical section */
+            /* Uninterruptable unlock sequence */
+            pADI_PMG0->PWRKEY = ADI_PMG_KEY;
+
+            /* Clear the previous mode and set new mode */
+            pADI_PMG0->PWRMOD = (uint32_t) ( ( pADI_PMG0->PWRMOD & (uint32_t) (~BITM_PMG_PWRMOD_MODE) ) | PowerMode );
+        }
+
+        /* Update the SCR (sleepdeep and sleep-on-exit bits) */
+        SCB->SCR = ((SCB->SCR | scrSetBits) & ~scrClrBits);
+
+        /* save/restore current Base Priority Level */
+        savedPriority = __get_BASEPRI();
+
+        /* assert caller's priority threshold (left-justified) */
+        __set_BASEPRI((uint32_t)PriorityMask << (8u -__NVIC_PRIO_BITS));
+        
+        /* if we are in the software looping mode, loop on the user's variable until set */
+        while (0u == *pnInterruptOccurred) {
+
+            __DSB();  /* bus sync to insure register writes from interrupt handlers are always complete before WFI */
+
+            /* NOTE: aggressive compiler optimizations can muck up critical timing here, so reduce if hangs are present */
+
+            /* The WFI loop MUST reside in a critical section because we need to insure that the interrupt
+               that is planned to take us out of WFI (via a call to adi_pwr_ExitLowPowerMode()) is not
+               dispatched until we get into the WFI.  If that interrupt sneaks in prior to our getting to the
+               WFI, then we may end up waiting (potentially forever) for an interrupt that has already occurred.
+            */
+            __WFI();
+
+            /* Recycle the critical section so that other (non-wakeup) interrupts are dispatched.
+               This allows *pnInterruptOccurred to be set from any interrupt context.
+             */
+            ADI_EXIT_CRITICAL_REGION();
+            /* nop */
+            ADI_ENTER_CRITICAL_REGION();
+
+        }  /* end while */
+
+        /* ...still within critical section... */
+
+        (*pnInterruptOccurred)--;       /* decrement the completion variable on exit */
+
+        /* Restore previous base priority */
+        __set_BASEPRI(savedPriority);
+
+        /* clear sleep-on-exit bit to avoid sleeping on exception return to thread level */
+        SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
+
+        __DSB(); /* bus sync before re-enabling interrupts */
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_PWR_SUCCESS;
+}
+
+
+/*!
+ * Companion function to #adi_pwr_EnterLowPowerMode() that allows interrupts to \n
+ * break out of the "FLEXI" mode in which the processor stays in \n
+ * sleep while peripherals are active. \n
+
+  @param[in,out] pnInterruptOccurred
+                                   Control parameter selection low-power operation. Either a NULL pointer \n
+                                   for hardware sleep-on-exit feature, or a pointer to uint32_t for software  \n
+                                   looping sleep between interrupts.
+    @return     Status
+                    - #ADI_PWR_SUCCESS                    If successfully exited from low power mode.
+
+ * @sa adi_pwr_EnterLowPowerMode
+ */
+ADI_PWR_RESULT adi_pwr_ExitLowPowerMode(uint32_t volatile * pnInterruptOccurred)
+{
+    ADI_INT_STATUS_ALLOC();
+
+    /* Manage the exit depending on pnInterruptOccurred convention... */
+    /* NULL pointer means we are using the hardware sleep-on-exit feature */
+    /* non-NULL pointer means we are using a software looping variable top sleep */
+
+    if (NULL == pnInterruptOccurred) {
+
+        pnInterruptOccurred = &gnLowPowerIntOccFlag;  /* point to private control variable in hardware mode */
+
+        /* clear hardware sleep-on-exit feature */
+        ADI_ENTER_CRITICAL_REGION();
+
+            SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
+            __DSB();  /* bus sync before interrupt exit */
+
+        ADI_EXIT_CRITICAL_REGION();
+    }
+
+    /* set control variable (whether hardware or software based) so WFI exits in SystemEnterLowPowerMode() */
+    (*pnInterruptOccurred)++;
+    return ADI_PWR_SUCCESS;
+}
+
+/*
+** EOF
+*/
+
+/*! @} */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/pwr/adi_pwr_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/pwr/adi_pwr_def.h
new file mode 100755
index 00000000000..c5f372ed340
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/pwr/adi_pwr_def.h
@@ -0,0 +1,172 @@
+/*
+ *****************************************************************************
+ * @file:    adi_pwr_def.h
+ * @brief:   Definitions for the system clock and power management.
+ *-----------------------------------------------------------------------------
+ *
+ * Copyright (c) 2016 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright notice,
+ *   this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ *   this list of conditions and the following disclaimer in the documentation
+ *   and/or other materials provided with the distribution.
+ * - Modified versions of the software must be conspicuously marked as such.
+ * - This software is licensed solely and exclusively for use with processors
+ *   manufactured by or for Analog Devices, Inc.
+ * - This software may not be combined or merged with other code in any manner
+ *   that would cause the software to become subject to terms and conditions
+ *   which differ from those listed here.
+ * - Neither the name of Analog Devices, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ * - The use of this software may or may not infringe the patent rights of one
+ *   or more patent holders.  This license does not release you from the
+ *   requirement that you obtain separate licenses from these patent holders
+ *   to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+ * PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef ADI_PWR_DEF_H
+#define ADI_PWR_DEF_H
+
+ /*Power control register access key */
+#define ADI_PMG_KEY             (0x4859u)
+
+ /*Osc control register access key */
+#define ADI_OSC_KEY             (0xCB14u)
+
+ /*HCLK/PCLK minimum Divider value */
+#define CLOCK_MIN_DIV_VALUE     (0x1u)
+
+ /*HCLK/PCLK maximum Divider value */
+#define CLOCK_MAX_DIV_VALUE     (32u)
+
+ /*ADC Clock minimum Divider value */
+#define ACLK_MIN_DIV_VALUE      (0x1u)
+
+ /*ADC Clock maximum Divider value */
+#define ACLK_MAX_DIV_VALUE      (511u)
+
+/* Minimum divider for PLL */
+#define MINIMUM_PLL_DIVIDER     (0x02u)
+
+/* Minimum multiplier for PLL */
+#define MINIMUM_PLL_MULTIPLIER  (0x08u)
+
+/* Maximum external clock */
+#define MAXIMUM_EXT_CLOCK       (26000000u)
+
+ /* Default osc  control register value */
+#define OSCCTRL_CONFIG_VALUE                                                                                              \
+          ( (uint32_t) ADI_PWR_LF_CLOCK_MUX                             << BITP_CLKG_OSC_CTL_LFCLK_MUX                  | \
+            (uint32_t) ADI_PWR_HFOSC_CLOCK_ENABLE                       << BITP_CLKG_OSC_CTL_HFOSC_EN                   | \
+            (uint32_t) ADI_PWR_LFXTAL_CLOCK_ENABLE                      << BITP_CLKG_OSC_CTL_LFX_EN                     | \
+            (uint32_t) ADI_PWR_HFXTAL_CLOCK_ENABLE                      << BITP_CLKG_OSC_CTL_HFX_EN                     | \
+            (uint32_t) ADI_PWR_LFXTAL_CLOCK_MON_ENABLE                  << BITP_CLKG_OSC_CTL_LFX_MON_EN                 | \
+            (uint32_t) ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE           << BITP_CLKG_OSC_CTL_LFX_AUTSW_EN               | \
+            (uint32_t) ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE                << BITP_CLKG_OSC_CTL_LFX_ROBUST_EN              | \
+            (uint32_t) ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT                << BITP_CLKG_OSC_CTL_LFX_ROBUST_LD              | \
+            (uint32_t) ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE                << BITP_CLKG_OSC_CTL_ROOT_MON_EN                | \
+            (uint32_t) ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE        << BITP_CLKG_OSC_CTL_ROOT_AUTSW_EN )
+
+ /* Default clock control register-0 value */
+#define CLOCK_CTL0_CONFIG_VALUE                                                                                           \
+          ( (uint32_t) ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX                  << BITP_CLKG_CLK_CTL0_CLKMUX                    | \
+            (uint32_t) ADI_PWR_GPIO_CLOCK_OUT_SELECT                    << BITP_CLKG_CLK_CTL0_CLKOUT                    | \
+            (uint32_t) ADI_PWR_INPUT_TO_RCLK_MUX                        << BITP_CLKG_CLK_CTL0_RCLKMUX                   | \
+            (uint32_t) ADI_PWR_INPUT_TO_SPLL_MUX                        << BITP_CLKG_CLK_CTL0_PLL_IPSEL                 | \
+            (uint32_t) ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE            << BITP_CLKG_CLK_CTL0_LFXTALIE                  | \
+            (uint32_t) ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE             << BITP_CLKG_CLK_CTL0_HFXTALIE )
+
+ /* Default clock control register-1 value */
+#define CLOCK_CTL1_CONFIG_VALUE                                                                                           \
+          ( (uint32_t) ADI_PWR_HCLK_DIVIDE_COUNT                        << BITP_CLKG_CLK_CTL1_HCLKDIVCNT                | \
+            (uint32_t) ADI_PWR_PCLK_DIVIDE_COUNT                        << BITP_CLKG_CLK_CTL1_PCLKDIVCNT                | \
+            (uint32_t) ADI_PWR_ACLK_DIVIDE_COUNT                        << BITP_CLKG_CLK_CTL1_ACLKDIVCNT )
+
+/* Default clock control register-2 value */
+#define CLOCK_CTL2_CONFIG_VALUE                                                                                           \
+          ( (uint32_t) ADI_PWR_HFOSC_AUTO_DIV_BY_1                      << BITP_CLKG_CLK_CTL2_HFOSCAUTODIV_EN           | \
+            (uint32_t) ADI_PWR_HFOSC_DIVIDE_SELECT                      << BITP_CLKG_CLK_CTL2_HFOSCDIVCLKSEL )
+
+ /* Default clock control register-3 value */
+#define CLOCK_CTL3_CONFIG_VALUE                                                                                           \
+          ( (uint32_t) ADI_PWR_SPLL_MUL_FACTOR                          << BITP_CLKG_CLK_CTL3_SPLLNSEL                  | \
+            (uint32_t) ADI_PWR_SPLL_ENABLE_DIV2                         << BITP_CLKG_CLK_CTL3_SPLLDIV2                  | \
+            (uint32_t) ADI_PWR_SPLL_ENABLE                              << BITP_CLKG_CLK_CTL3_SPLLEN                    | \
+            (uint32_t) ADI_PWR_SPLL_INTERRUPT_ENABLE                    << BITP_CLKG_CLK_CTL3_SPLLIE                    | \
+            (uint32_t) ADI_PWR_SPLL_DIV_FACTOR                          << BITP_CLKG_CLK_CTL3_SPLLMSEL                  | \
+            (uint32_t) ADI_PWR_SPLL_ENABLE_MUL2                         << BITP_CLKG_CLK_CTL3_SPLLMUL2 )
+
+ /* Default clock control register-5 value */
+#define CLOCK_CTL5_CONFIG_VALUE                                                                                           \
+          ( (uint32_t) ADI_PWR_GPT0_CLOCK_ENABLE                        << BITP_CLKG_CLK_CTL5_GPTCLK0OFF                | \
+            (uint32_t) ADI_PWR_GPT1_CLOCK_ENABLE                        << BITP_CLKG_CLK_CTL5_GPTCLK1OFF                | \
+            (uint32_t) ADI_PWR_GPT2_CLOCK_ENABLE                        << BITP_CLKG_CLK_CTL5_GPTCLK2OFF                | \
+            (uint32_t) ADI_PWR_I2C_CLOCK_ENABLE                         << BITP_CLKG_CLK_CTL5_UCLKI2COFF                | \
+            (uint32_t) ADI_PWR_GPIO_CLOCK_ENABLE                        << BITP_CLKG_CLK_CTL5_GPIOCLKOFF                | \
+            (uint32_t) ADI_PWR_PCLK_ENABLE                              << BITP_CLKG_CLK_CTL5_PERCLKOFF                 | \
+            (uint32_t) ADI_PWR_TIMER_RGB_ENABLE                         << BITP_CLKG_CLK_CTL5_TMRRGBCLKOFF )
+            
+/* Default configuration for Power supply monitor Interrupt Enable Register */            
+#define PWM_INTERRUPT_CONFIG                                                                                              \
+          ( (uint32_t) ADI_PWR_ENABLE_VBAT_INTERRUPT                    << BITP_PMG_IEN_VBAT                            | \
+            (uint32_t) ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT      << BITP_PMG_IEN_VREGUNDR                        | \
+            (uint32_t) ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT       << BITP_PMG_IEN_VREGOVR                         | \
+            (uint32_t) ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT   << BITP_PMG_IEN_IENBAT                          | \
+            (uint32_t) ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT      << BITP_PMG_IEN_RANGEBAT )
+            
+ /* Default configuration for Power Mode Register */            
+ #define PWM_PWRMOD_CONFIG                                                                                                \
+         (  (uint32_t) ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING        << BITP_PMG_PWRMOD_MONVBATN ) 
+ 
+/* Default configuration for HP Buck Control register */
+#define PWM_HPBUCK_CONTROL                                                                                                \
+         (  (uint32_t) ADI_PWR_HP_BUCK_ENABLE                           << BITP_PMG_CTL1_HPBUCKEN                       | \
+            (uint32_t) ADI_PWR_HP_BUCK_LOAD_MODE                        << BITP_PMG_CTL1_HPBUCK_LD_MODE                 | \
+            (uint32_t) ADI_PWR_HP_BUCK_LOW_POWER_MODE                   << BITP_PMG_CTL1_HPBUCK_LOWPWR_MODE )  
+           
+ /*Selecting HFOSC as input for generating root clock*/
+#define HFMUX_INTERNAL_OSC_VAL      (0u << BITP_CLKG_CLK_CTL0_CLKMUX)
+
+ /*Selecting HFXTAL as input for generating root clock*/
+#define HFMUX_EXTERNAL_XTAL_VAL     (1u << BITP_CLKG_CLK_CTL0_CLKMUX)
+
+ /*Selecting SPLL as input for generating root clock*/
+#define HFMUX_SYSTEM_SPLL_VAL       (2u << BITP_CLKG_CLK_CTL0_CLKMUX)
+
+ /*Selecting GPIO as input for generating root clock*/
+#define HFMUX_GPIO_VAL              (3u << BITP_CLKG_CLK_CTL0_CLKMUX)
+
+/* Interrupt handler for the battery voltage interrupt */
+void Battery_Voltage_Int_Handler(void);
+/* Interrupt handler for the VREG under/over voltage interrupt */
+void Vreg_over_Int_Handler(void);
+/* Interrupt handler for PLL interrupts. */
+void PLL_Int_Handler(void);     
+/*Interrupt handler for oscillator interrupts.*/                                 
+void Crystal_osc_Int_Handler(void);
+
+#endif /* ADI_PWR_DEF_H */
+
+
+/*
+** EOF
+*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/retarget_uart_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/retarget_uart_config.h
new file mode 100755
index 00000000000..a9f0e37275a
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/retarget_uart_config.h
@@ -0,0 +1,27 @@
+/*
+** I/O redirection support over UART, via SSL/DD.
+** Copyright (C) 2017 Analog Devices, Inc. All Rights Reserved.
+**
+** This file is intended for use with the ARM:Compiler:IO:*:User
+** components, which set up redirection of stdout and stderr.
+*/
+
+#ifndef RETARGET_UART_CONFIG_H
+#define RETARGET_UART_CONFIG_H
+
+// --- <<< Use Configuration Wizard in Context Menu >>> ---
+
+// <h>UART Configuration for STDOUT and STDERR
+
+// <q>Configure Pinmuxing for UART.
+// <i>Enable pinmux configuration for UART on first output.
+#define ADI_UART_SETUP_PINMUX 1
+
+// <q>Raise Breakpoint on exit()
+// <i>Cause a breakpoint event in exit() rather than looping forever.
+#define ADI_UART_EXIT_BREAKPOINT 1
+
+
+// </h>
+
+#endif /* RETARGET_UART_CONFIG_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rng/adi_rng.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rng/adi_rng.c
new file mode 100755
index 00000000000..75eb73a6cbd
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rng/adi_rng.c
@@ -0,0 +1,796 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_rng.c
+ * @brief:   Random Number Generator Driver
+ *----------------------------------------------------------------------------
+ *
+Copyright (c) 2012-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+/*! \addtogroup RNG_Driver RNG Driver
+ *  Random Number Generator Driver
+ *  @{
+ */
+
+ /*! \cond PRIVATE */
+
+#include <stdlib.h>  /* for 'NULL' definition */
+#include <assert.h>
+
+#include <adi_processor.h>
+#include <drivers/rng/adi_rng.h>
+#include "adi_rng_def.h"
+#include <rtos_map/adi_rtos_map.h>
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm011 (rule 6.3): Types which specify sign and size should be used
+*   We use bool which is accepted by MISRA but the toolchain does not accept it
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+*
+* Pm050 (rule 14.2): a null statement shall only occur on a line by itself
+*   Needed for null expansion of ISR_PROLOG in no-OS case and others.
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   The rule makes an exception for memory-mapped register accesses.
+*/
+#pragma diag_suppress=Pm011,Pm073,Pm143,Pm050
+#endif /* __ICCARM__ */
+
+#ifdef __ADUCM4x50__
+#define NUM_RNG_DEVICES       (1u)
+#else
+#error "Unsupported processor"
+#endif
+
+/*==============  D A T A  ===============*/
+
+/**
+ * Information for managing all the RNG devices available
+ */
+#ifdef __ICCARM__
+#pragma diag_suppress=Pm140
+#endif
+
+static ADI_RNG_DEV_TYPE gRNG_Device[NUM_RNG_DEVICES] =
+{
+  {(ADI_RNG_TypeDef*)pADI_RNG0,NULL} /* RNG0 */
+};
+#ifdef __ICCARM__
+#pragma diag_default=Pm140
+#endif
+
+/* Forward prototypes */
+void RNG_Int_Handler(void);
+
+/** Check the validity of a handle for debug mode */
+#ifdef ADI_DEBUG
+#define ADI_RNG_INVALID_HANDLE(h) (&gRNG_Device[0] != (h))
+#endif
+
+/*! \endcond */
+
+/*!
+    @brief Opena a Random Number Generator Device
+
+    @param[in]  nDeviceNum   Device number to be opened.
+    @param[in]  pMemory      Pointer to the memory to be used by the driver.
+                             Size of the memory should be at least #ADI_RNG_MEMORY_SIZE bytes.
+    @param[in]  MemorySize   Size of the memory passed in pMemory parameter.
+    @param[out] phDevice     Pointer to a location in the calling function memory space to which
+                             the device handle will be written upon successful driver initialization.
+
+    @return    Status
+               - #ADI_RNG_SUCCESS                      RNG device driver opened successfully.
+               - #ADI_RNG_INVALID_PARAM [D]            The memory passed to the API is either NULL or its size is not sufficient.
+               - #ADI_RNG_ALREADY_INITIALIZED [D]  The RNG is already initialized.
+               - #ADI_RNG_BAD_DEVICE_NUM [D]       The device number is invalid.
+
+    Initialize and allocate a RNG device for other use.  The core NVIC RNG interrupt is enabled.  This API
+    must preceed all other RNG API calls and the handle returned must be passed to all other RNG API calls.
+
+    @note   The contents of \a ppDevice will be set to NULL upon failure.\n\n
+
+    @note   The RNG device driver will clear all pending interrupts and disable all RNG
+            interrupts during RNG device initialization.
+
+    @sa    adi_rng_Close().
+*/
+ADI_RNG_RESULT adi_rng_Open(
+                            uint32_t             const  nDeviceNum,
+                            void*                const  pMemory,
+                            uint32_t             const  MemorySize,
+                            ADI_RNG_HANDLE*      const  phDevice
+                            )
+{
+    ADI_RNG_DEV_TYPE *pDevice;
+
+    /* store a bad handle in case of failure */
+    *phDevice = (ADI_RNG_HANDLE) NULL;
+
+#ifdef ADI_DEBUG
+    if (nDeviceNum >= NUM_RNG_DEVICES)
+    {
+        return ADI_RNG_BAD_DEVICE_NUM;
+    }
+
+    if ((NULL == pMemory) || ( MemorySize < (uint32_t) ADI_RNG_MEMORY_SIZE))
+    {
+        return ADI_RNG_INVALID_PARAM;
+    }
+    assert (ADI_RNG_MEMORY_SIZE == sizeof(ADI_RNG_DEV_DATA_TYPE));
+#endif
+
+    /* local pointer to instance data */
+    pDevice = &gRNG_Device[nDeviceNum];
+
+#ifdef ADI_DEBUG
+    if (NULL != pDevice->pData)
+    {
+        return ADI_RNG_ALREADY_INITIALIZED;
+    }
+#endif
+
+    /* Set the internal device data */
+    pDevice->pData = pMemory;
+
+    /* initialize internal device data */
+    pDevice->pData->IRQn    = RNG0_EVT_IRQn;
+    pDevice->pData->CBFunc  = NULL;
+
+    /* clear any pending interrupts. Both bits are write 1 to clear */
+    pDevice->pRNG->STAT = BITM_RNG_STAT_RNRDY | BITM_RNG_STAT_STUCK;
+
+    /* Set the RNG register based on static configuration */
+    pDevice->pRNG->CTL = (uint16_t)RNG0_CFG_ONLY_8_BIT << BITP_RNG_CTL_SINGLE;
+    pDevice->pRNG->LEN = (RNG0_CFG_LENGTH_RELOAD << BITP_RNG_LEN_RELOAD)
+                       | (RNG0_CFG_LENGTH_PRESCALER << BITP_RNG_LEN_PRESCALE);
+
+   /* The interrupt handler only gets used in the case of callback mode so its
+    * enabling only happens in the adi_rng_RegisterCallBack API.
+    */
+    NVIC_ClearPendingIRQ(pDevice->pData->IRQn);
+
+    /* store handle at application handle pointer */
+    *phDevice = pDevice;
+
+    return ADI_RNG_SUCCESS;
+}
+
+
+/*!
+ * @brief  Uninitializes and deallocates the RNG device.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rng_Open().
+ *
+ * @return      Status
+ *                - #ADI_RNG_SUCCESS                    Call completed successfully.
+ *                - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+ *
+ * Uninitialize and release an allocated RNG device for other use.  The core NVIC RNG interrupt is disabled.
+ *
+ * @sa        adi_rng_Open().
+ */
+ADI_RNG_RESULT adi_rng_Close(ADI_RNG_HANDLE hDevice)
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+
+#ifdef ADI_DEBUG
+    if (ADI_RNG_INVALID_HANDLE(pDevice)){
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (NULL == pDevice->pData) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+#endif
+
+    /* uninitialize */
+    NVIC_DisableIRQ(pDevice->pData->IRQn);
+    pDevice->pData = NULL;
+
+    return ADI_RNG_SUCCESS;
+}
+
+/*!
+ * @brief  Enables/Disables the RNG device.
+ *
+ * @param[in]   hDevice       Device handle obtained from adi_rng_Open().
+ * @param[in]   bFlag         Flag to specify whether to enable or disable RNG device.
+ *
+ * @return      Status
+ *                - #ADI_RNG_SUCCESS                    Call completed successfully.
+ *                - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+ *
+ * @sa        adi_rng_Open().
+ * @sa        adi_rng_RegisterCallback().
+ */
+ADI_RNG_RESULT adi_rng_Enable (ADI_RNG_HANDLE const hDevice, bool const bFlag)
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    if (ADI_RNG_INVALID_HANDLE(pDevice)) {
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (NULL == pDevice->pData) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+#endif
+
+    ADI_ENTER_CRITICAL_REGION();
+    if (true == bFlag) {
+        pDevice->pRNG->CTL |= BITM_RNG_CTL_EN;
+    } else {
+        pDevice->pRNG->CTL &= (uint16_t)~(BITM_RNG_CTL_EN);
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_RNG_SUCCESS;
+}
+
+/*!
+ * @brief  Enables/Disables Buffering for RNG.
+ *
+ * @param[in]   hDevice       Device handle obtained from adi_rng_Open().
+ * @param[in]   bFlag         Flag to specify whether to enable or disable buffering for RNG device.
+ *                            When buffering is enabled, adi_rng_GetRngData returns 32-bit values.
+ *                            When buffering is disabled the API returns 8-bit values.
+ *
+ * @return      Status
+ *                - #ADI_RNG_SUCCESS                    Call completed successfully.
+ *                - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+ *
+ * @sa        adi_rng_Open().
+ * @sa        adi_rng_RegisterCallback().
+ * @sa        adi_rng_GetRngData().
+ */
+ADI_RNG_RESULT adi_rng_EnableBuffering (ADI_RNG_HANDLE const hDevice, bool const bFlag)
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    if (ADI_RNG_INVALID_HANDLE(pDevice)) {
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (NULL == pDevice->pData) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+#endif
+
+    ADI_ENTER_CRITICAL_REGION();
+    if (true == bFlag) {
+        pDevice->pRNG->CTL &= (uint16_t)~(BITM_RNG_CTL_SINGLE);
+    } else {
+        pDevice->pRNG->CTL |= BITM_RNG_CTL_SINGLE;
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_RNG_SUCCESS;
+}
+
+/*!
+ * @brief  Sets the reload and prescale value for the sample counter.
+ *         The Sample Length will be nLenReload*2^nLenPrescaler.
+ *
+ * @param[in]   hDevice        Device handle obtained from adi_rng_Open().
+ * @param[in]   nLenPrescaler  Prescaler value for the sample counter (0-10).
+ * @param[in]   nLenReload     Reload value for the sample counter (0-4095)
+ *
+ * @return      Status
+ *                - #ADI_RNG_SUCCESS                    Call completed successfully.
+ *                - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+ *
+ * @sa        adi_rng_Open().
+ * @sa        adi_rng_RegisterCallback().
+ */
+ADI_RNG_RESULT adi_rng_SetSampleLen (
+                                     ADI_RNG_HANDLE const hDevice,
+                                     uint16_t       const nLenPrescaler,
+                                     uint16_t       const nLenReload
+                                     )
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    if (ADI_RNG_INVALID_HANDLE(pDevice)){
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (NULL == pDevice->pData) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+
+    if (   (nLenPrescaler > 10u)
+        || ((0u == nLenPrescaler) && (0u == nLenReload))
+        || (nLenReload > 4095u)) {
+        return ADI_RNG_INVALID_PARAM;
+    }
+#endif
+
+    ADI_ENTER_CRITICAL_REGION();
+    /* Set the sample reload and prescaler value */
+    pDevice->pRNG->LEN =   (uint16_t)((uint16_t)(nLenReload    << BITP_RNG_LEN_RELOAD)   & BITM_RNG_LEN_RELOAD)
+                         | (uint16_t)((uint16_t)(nLenPrescaler << BITP_RNG_LEN_PRESCALE) & BITM_RNG_LEN_PRESCALE);
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_RNG_SUCCESS;
+}
+
+
+/*!
+ * @brief  Retrieves the current state of RNG data/CRC accumulator register.
+ *
+ * @param[in]   hDevice       Device handle obtained from adi_rng_Open().
+ * @param[out]  pbFlag        Pointer to an application-defined boolean variable into which to write the result:
+ *                              - true  = RNG data is ready to be read.
+ *                              - false = RNG data is not ready.
+ *
+ * @return      Status
+ *                - #ADI_RNG_SUCCESS                    Call completed successfully.
+ *                - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+                  - #ADI_RNG_INVALID_PARAM [D]          Argument is incorrect.
+ *
+ * Retrieve the current state of RNG data/CRC accumulator register. The register holds the final entropy value
+ * accumulated by RNG and it should to read only when the data is ready.
+ *
+ * @sa        adi_rng_Open().
+ * @sa        adi_rng_GetRngData().
+ * @sa        adi_rng_RegisterCallback().
+ */
+ADI_RNG_RESULT adi_rng_GetRdyStatus (ADI_RNG_HANDLE const hDevice, bool* const pbFlag)
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+
+#ifdef ADI_DEBUG
+    if (ADI_RNG_INVALID_HANDLE(pDevice)){
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (NULL == pDevice->pData) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+
+    if (NULL == pbFlag) {
+        return ADI_RNG_INVALID_PARAM;
+    }
+#endif
+
+    /* Get the RNG Ready status bit */
+    if ((pDevice->pRNG->STAT & BITM_RNG_STAT_RNRDY) != 0u)
+    {
+        *pbFlag = true;
+    }
+    else
+    {
+        *pbFlag = false;
+    }
+
+    return ADI_RNG_SUCCESS;
+}
+
+/*!
+ * @brief  Retrieve whether the RNG oscillator output is stuck at a constant value
+ *
+ * @param[in]   hDevice       Device handle obtained from adi_rng_Open().
+ * @param[out]  pbFlag        Pointer to an application-defined boolean variable into which to write the result:
+ *                              - true  = RNG oscillator is stuck at a constant value.
+ *                              - false = RNG oscillator is not stuck at a constant value.
+ *
+ * @return      Status
+ *                - #ADI_RNG_SUCCESS                    Call completed successfully.
+ *                - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+                  - #ADI_RNG_INVALID_PARAM [D]          Argument is incorrect.
+ *
+ * @sa        adi_rng_Open().
+ * @sa        adi_rng_GetRngData().
+ * @sa        adi_rng_RegisterCallback().
+ */
+ADI_RNG_RESULT adi_rng_GetStuckStatus (
+                                       ADI_RNG_HANDLE const hDevice,
+                                       bool* const pbFlag
+                                       )
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+
+#ifdef ADI_DEBUG
+    if (ADI_RNG_INVALID_HANDLE(pDevice)){
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (pDevice->pData == NULL) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+
+    if (NULL == pbFlag) {
+        return ADI_RNG_INVALID_PARAM;
+    }
+#endif
+
+    /* Get the stuck status bit */
+    if ((pDevice->pRNG->STAT & BITM_RNG_STAT_STUCK) != 0u)
+    {
+        *pbFlag = true;
+    }
+    else
+    {
+        *pbFlag = false;
+    }
+
+    return ADI_RNG_SUCCESS;
+}
+
+
+/*!
+ * @brief  Retrieve the current value of the RNG data register.
+ *
+ * @param[in]   hDevice       Device handle obtained from adi_rng_Open().
+ * @param[in]   pRegData      Pointer to an application-defined variable into which to write the result.
+ *                            Only lower 8-bit is valid if buffering is not enabled
+ *
+ * @return      Status
+ *                - #ADI_RNG_SUCCESS                    Call completed successfully.
+ *                - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+ *                - #ADI_RNG_INVALID_PARAM [D]      pRegData is a NULL pointer.
+ *                - #ADI_RNG_INVALID_STATE[D]       Random number ready status is not set
+ *
+ * Retrieve the current value of RNG data register. If the buffering is enabled all 32-bit of value written to
+ * pRegData is valid else only the lower 8-bit is valid.
+ *
+ * @sa        adi_rng_Open().
+ * @sa        adi_rng_GetRdyStatus().
+ * @sa        adi_rng_RegisterCallback().
+ */
+ADI_RNG_RESULT adi_rng_GetRngData (ADI_RNG_HANDLE const hDevice, uint32_t* const pRegData)
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+
+#ifdef ADI_DEBUG
+    if (ADI_RNG_INVALID_HANDLE(pDevice)){
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (NULL == pDevice->pData) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+
+    if (NULL == pRegData) {
+        return ADI_RNG_INVALID_PARAM;
+    }
+
+    if ((pDevice->pRNG->STAT & BITM_RNG_STAT_RNRDY) == 0u) {
+        return ADI_RNG_INVALID_STATE;
+    }
+#endif
+
+    /* Get the RNG CRC accumulator value */
+    *pRegData = pDevice->pRNG->DATA;
+
+    return ADI_RNG_SUCCESS;
+}
+
+
+/*!
+ * @brief  Retrieve the current RNG Oscillator count.
+ *
+ * @param[in]   hDevice       Device handle obtained from adi_rng_Open().
+ * @param[in]   pOscCount     Pointer to an application-defined variable into which to write the result.
+ *
+ * @return      Status
+ *                - #ADI_RNG_SUCCESS                    Call completed successfully.
+ *                - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+ *                - #ADI_RNG_INVALID_STATE[D]       Random number ready status is not set
+                  - #ADI_RNG_INVALID_PARAM [D]          Argument is incorrect.
+ *
+ * @sa        adi_rng_Open().
+ * @sa        adi_rng_RegisterCallback().
+ */
+ADI_RNG_RESULT adi_rng_GetOscCount (ADI_RNG_HANDLE const hDevice, uint32_t* const pOscCount)
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+
+#ifdef ADI_DEBUG
+   if (ADI_RNG_INVALID_HANDLE(pDevice)){
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (NULL == pDevice->pData) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+
+    if (NULL == pOscCount) {
+        return (ADI_RNG_INVALID_PARAM);
+    }
+
+    if ((pDevice->pRNG->STAT & BITM_RNG_STAT_RNRDY) == 0u) {
+        return ADI_RNG_INVALID_STATE;
+    }
+#endif
+
+    /* Get the oscillator count high count */
+    *pOscCount = pDevice->pRNG->OSCCNT;
+
+    return ADI_RNG_SUCCESS;
+}
+
+/*!
+ * @brief  Retrieve the current RNG Oscillator difference value for the given index.
+ *
+ * @param[in]   hDevice     Device handle obtained from adi_rng_Open().
+ * @param[in]   nIndex      Index of the difference register.
+ * @param[out]  pOscDiff    Pointer to an application-defined variable into which to
+ *                          write the oscillator difference value for the given index.
+ *
+ * @return      Status
+ *              - #ADI_RNG_SUCCESS                    Call completed successfully.
+ *              - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *              - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+ *              - #ADI_RNG_INVALID_STATE[D]       Random number ready status is not set
+                - #ADI_RNG_INVALID_PARAM [D]          Argument is incorrect.
+ *
+ * @sa        adi_rng_Open().
+ * @sa        adi_Rng_RegisterCallback().
+ */
+ADI_RNG_RESULT adi_rng_GetOscDiff (
+                                   ADI_RNG_HANDLE const hDevice,
+                                   uint32_t       const nIndex,
+                                   uint8_t*       const pOscDiff
+                                   )
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+
+#ifdef ADI_DEBUG
+   if (ADI_RNG_INVALID_HANDLE(pDevice)){
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (NULL == pDevice->pData) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+
+    if ((NULL == pOscDiff) || (nIndex > 3u)) {
+        return( ADI_RNG_INVALID_PARAM );
+    }
+
+    if ((pDevice->pRNG->STAT & BITM_RNG_STAT_RNRDY) == 0u) {
+        return ADI_RNG_INVALID_STATE;
+    }
+#endif
+
+    /* Get the Osc Difference Register */
+    *pOscDiff = (uint8_t)pDevice->pRNG->OSCDIFF[nIndex];
+
+    return ADI_RNG_SUCCESS;
+}
+
+/*!
+ * @brief  Retrieve the current RNG sample length prescale and reload value configured in the device.
+ *
+ * @param[in]   hDevice        Device handle obtained from adi_rng_Open().
+ * @param[out]  pLenPrescaler  Pointer to an application-defined variable into which the prescaler value is written.
+ * @param[out]  pLenReload     Pointer to an application-defined variable into which the reload value for the sample counter is written.
+ *
+ * @return      Status
+ *                - #ADI_RNG_SUCCESS                    Call completed successfully.
+ *                - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+ *                - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+                  - #ADI_RNG_INVALID_PARAM [D]          Argument is incorrect.
+ *
+ *
+ * @sa        adi_rng_Open().
+ * @sa        adi_rng_RegisterCallback().
+ */
+ADI_RNG_RESULT adi_rng_GetSampleLen (
+                                     ADI_RNG_HANDLE const hDevice,
+                                     uint16_t*      const pLenPrescaler,
+                                     uint16_t*      const pLenReload
+                                     )
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+
+#ifdef ADI_DEBUG
+   if (ADI_RNG_INVALID_HANDLE(pDevice)){
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (NULL == pDevice->pData) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+
+    if ((NULL == pLenPrescaler) || (NULL == pLenReload)) {
+        return ADI_RNG_INVALID_PARAM;
+    }
+#endif
+
+    *pLenPrescaler = (pDevice->pRNG->LEN & BITM_RNG_LEN_PRESCALE) >> BITP_RNG_LEN_PRESCALE;
+    *pLenReload    = (pDevice->pRNG->LEN & BITM_RNG_LEN_RELOAD)   >> BITP_RNG_LEN_RELOAD;
+
+    return ADI_RNG_SUCCESS;
+}
+
+
+/*************************************************************************************************
+**************************************************************************************************
+*****************************************   CALLBACKS   ******************************************
+*****************************************      AND      ******************************************
+*****************************************   INTERRUPT   ******************************************
+**************************************************************************************************
+*************************************************************************************************/
+
+
+/*!
+    @brief RNG Application callback registration API.
+
+    @param[in]   hDevice     Device handle obtained from #adi_rng_Open().
+    @param[in]   cbFunc      Application callback address; the function to call on the interrupt.
+    @param[in]   pCBParam    Application handle to be passed in the call back.
+
+    @return    Status
+               - #ADI_RNG_SUCCESS                    The callback is successfully registered.
+               - #ADI_RNG_BAD_DEV_HANDLE [D]     Invalid device handle parameter.
+               - #ADI_RNG_NOT_INITIALIZED [D]    Device has not been initialized for use, see #adi_rng_Open().
+
+    Registers an application-defined callback \a cbFunc function address of type ADI_CALLBACK with the RNG device driver.
+    Callbacks are made in response to received RNG interrupts.
+
+    The callback to the application is made in context of the originating interrupt (i.e., the RNG driver's
+    RNG interrupt handler that is registered in the system's interrupt vector table).  Extended processing
+    during the callback (an extension of the RNG's interrupt handler) is discouraged so as to avoid lower-priority
+    interrupt blocking.  Also, any register read-modify-write operations should be protected using the
+    ADI_ENTER_CRITICAL_REGION()/ADI_EXIT_CRITICAL_REGION() pair to prevent higher-priority interrupts from modifying
+    said register during the read-modify-write operation.
+
+    @note   CALLBACKS: RNG interrupt callbacks are \b disabled by default during RNG device driver
+            initialization (#adi_rng_Open()).  The application uses the #adi_rng_RegisterCallback()
+            API to request an application-defined callback from the RNG device driver. The RNG device
+            driver clears the interrupt when the callback exits.
+            The application callback should <b>avoid extended processing</b>
+            during callbacks as the callback is executing context of the initiating interrupt and will
+            block lower-priority interrupts.  If extended application-level interrupt processing is
+            required, the application should schedule it for the main application loop and exit the
+            callback as soon as possible.\n
+
+
+    @sa    adi_rng_Open().
+*/
+ADI_RNG_RESULT adi_rng_RegisterCallback (
+                                         ADI_RNG_HANDLE  hDevice,
+                                         ADI_CALLBACK    cbFunc,
+                                         void           *pCBParam)
+{
+    ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice;
+
+#ifdef ADI_DEBUG
+   if (ADI_RNG_INVALID_HANDLE(pDevice)){
+        return ADI_RNG_BAD_DEV_HANDLE;
+    }
+
+    if (NULL == pDevice->pData) {
+        return ADI_RNG_NOT_INITIALIZED;
+    }
+#endif
+
+    /* save the callback info */
+    pDevice->pData->CBFunc   = cbFunc;
+    pDevice->pData->pCBParam = pCBParam;
+
+    if (NULL != cbFunc) {
+        /* enable RNG interrupts in NVIC */
+        NVIC_EnableIRQ(pDevice->pData->IRQn);
+    } else {
+        NVIC_DisableIRQ(pDevice->pData->IRQn);
+    }
+
+    return ADI_RNG_SUCCESS;
+}
+
+/*! \cond PRIVATE */
+/* RNG driver interrupt handler. Overrides weak default handler in startup file */
+void RNG_Int_Handler(void)
+{
+    ISR_PROLOG();
+    ADI_RNG_DEV_TYPE *pDevice = &gRNG_Device[0];
+    register uint16_t candidate;
+
+    /* if we have an initialized driver... */
+    if (NULL != pDevice->pData)
+    {
+        /* if we have a registered callback */
+        if (NULL != pDevice->pData->CBFunc)
+        {
+            ADI_INT_STATUS_ALLOC();
+
+            ADI_ENTER_CRITICAL_REGION();
+            /* read status register without other interrupts in between */
+            candidate = pDevice->pRNG->STAT;
+            ADI_EXIT_CRITICAL_REGION();
+
+            /* Only have bits in stat that are necessary */
+            candidate = candidate & (BITM_RNG_STAT_STUCK | BITM_RNG_STAT_RNRDY);
+
+            while (0u != candidate) {
+                uint32_t nEvent;
+
+                if (0u != (candidate & BITM_RNG_STAT_RNRDY)) {
+                    nEvent = ADI_RNG_EVENT_READY;
+                    candidate &= (uint16_t)~BITM_RNG_STAT_RNRDY;
+                } else if (0u != (candidate & BITM_RNG_STAT_STUCK)) {
+                    nEvent = ADI_RNG_EVENT_STUCK;
+                    candidate &= (uint16_t)~BITM_RNG_STAT_STUCK;
+                } else {
+                    break;
+                }
+
+                pDevice->pData->CBFunc (
+                                        pDevice->pData->pCBParam,
+                                        nEvent,
+                                        NULL
+                                        );
+            }
+
+            pDevice->pRNG->STAT = BITM_RNG_STAT_RNRDY | BITM_RNG_STAT_STUCK;
+        }
+    }
+    ISR_EPILOG();
+}
+/*! \endcond */
+
+/*
+** EOF
+*/
+
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rng/adi_rng_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rng/adi_rng_def.h
new file mode 100755
index 00000000000..462861d976a
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rng/adi_rng_def.h
@@ -0,0 +1,69 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_rng_def.h
+ * @brief:   Random Number Generator Driver private data structures
+ *----------------------------------------------------------------------------
+ *
+Copyright (c) 2012-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#ifndef ADI_RNG_DEF_H
+#define ADI_RNG_DEF_H
+
+ /*! \cond PRIVATE */
+
+
+/*! RNG device internal instance data structure */
+typedef struct __ADI_RNG_DEV_DATA_TYPE
+{
+    IRQn_Type                      IRQn;      /*!< RNG interrupt number       */
+    ADI_CALLBACK                   CBFunc;    /*!< Callback function          */
+    void                          *pCBParam;  /*!< Callback parameter         */
+} ADI_RNG_DEV_DATA_TYPE;
+
+/*! RNG device internal data structure */
+typedef struct __ADI_RNG_DEV_TYPE
+{
+    volatile ADI_RNG_TypeDef      *pRNG;      /*!< MMR address for this RNG   */
+    ADI_RNG_DEV_DATA_TYPE         *pData;     /*!< Pointer to instance data   */
+} ADI_RNG_DEV_TYPE;
+
+
+/*! \endcond */
+#endif /* ADI_RNG_DEF_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc.c
new file mode 100755
index 00000000000..f4b91d4adbb
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc.c
@@ -0,0 +1,2608 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_rtc.c
+ * @brief:   Real-Time Clock Device Implementations.
+ * @version: $Revision: 35155 $
+ * @date:    $Date: 2016-07-26 13:09:22 -0400 (Tue, 26 Jul 2016) $
+ *----------------------------------------------------------------------------
+ *
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+/*! \addtogroup RTC_Driver RTC Driver
+ *  @{
+ * @brief Real Time Clock (RTC) Driver
+ * @details The RTC driver manages all instances of the RTC peripheral.
+ * @note The application must include drivers/rtc/adi_rtc.h to use this driver
+ */
+
+
+/*! \cond PRIVATE */
+
+
+#if defined ( __ADSPGCC__ )
+#define UNUSED __attribute__ ((unused))
+#else
+#define UNUSED
+#endif
+
+#include <stdlib.h>  /* for 'NULL" definition */
+#include <assert.h>
+#include <string.h>
+#include <rtos_map/adi_rtos_map.h>
+
+
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm011 (rule 6.3): Types which specify sign and size should be used
+*   We use bool which is accepted by MISRA but the toolchain does not accept it
+*
+* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
+*   This isn't a header as such.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+*
+* Pm050 (rule 14.2): a null statement shall only occur on a line by itself
+*   Needed for null expansion of ADI_INSTALL_HANDLER and others.
+*
+* Pm109 (rule 20.12): the time handling functions of library <time.h> shall not be used
+* Pm150 (rule 20.2): the names of standard library macros, objects and function shall not be reused
+*   Needed to implement the <time.h> functions here.
+*
+* Pm129 (rule 12.7): bitwise operations shall not be performed on signed integer types 
+*   The rule makes an exception for valid expressions.
+*
+* Pm029: this bitwise operation is in a boolean context - logical operators should not be confused with bitwise operators 
+*   The rule is suppressed as the bitwise and logical operators are being used correctly and are not being confused
+*
+* Pm126: if the bitwise operators ~ and << are applied to an operand of underlying type 'unsigned char' or 'unsigned short', the result shall be immediately cast to the underlying type of the operand
+*   The behaviour as described is correct
+*
+* Pm031: bitwise operations shall not be performed on signed integer types 
+*   Device drivers often require bit banging on MMRs that are defined as signed
+
+*/
+#pragma diag_suppress=Pm011,Pm123,Pm073,Pm143,Pm050,Pm109,Pm150,Pm140,Pm129,Pm029,Pm126,Pm031
+#endif /* __ICCARM__ */
+/*! \endcond */
+   
+   
+#include <drivers/rtc/adi_rtc.h>
+
+   
+/*! \cond PRIVATE */
+
+
+#include "adi_rtc_data.c"
+
+
+
+
+/* Forward prototypes */
+void RTC0_Int_Handler(void);
+void RTC1_Int_Handler(void);
+
+
+
+#ifdef ADI_DEBUG
+static ADI_RTC_RESULT ValidateHandle( ADI_RTC_DEVICE *pInDevice)
+{
+    /* Return code */
+    ADI_RTC_RESULT    nResult = ADI_RTC_INVALID_HANDLE;
+    uint32_t i;
+    for(i = 0u; i < ADI_RTC_NUM_INSTANCE; i++)
+    {
+        if(aRTCDeviceInfo[i].hDevice == pInDevice)
+        {
+            return(ADI_RTC_SUCCESS);
+        }
+    }
+    return (nResult);
+}
+#endif
+/*! \endcond */
+
+/*!
+    @brief RTC Initialization
+
+ * @param[in]   DeviceNumber    The RTC device instance number to be opened.
+ * @param[in]   pDeviceMemory   The pointer to the device  memory passed by application.
+ * @param[in]   MemorySize      The memory size passed by application.
+ * @param[out]  phDevice        The pointer to a location where the handle to the opened RTC device is written.
+    @return    Status
+               - #ADI_RTC_SUCCESS                   RTC device driver initialized successfully.
+               - #ADI_RTC_INVALID_INSTANCE [D]         The RTC instance number is invalid.
+               - #ADI_RTC_FAILURE                      General RTC initialization failure.
+
+            The RTC controller interrupt enable state is unaltered during driver initialization.
+            Use the #adi_rtc_EnableInterrupts API to manage interrupting.
+
+    @note   The contents of phDevice will be set to NULL upon failure.\n\n
+
+    @note   On #ADI_RTC_SUCCESS the RTC device driver is initialized and made ready for use,
+            though pending interrupts may be latched.  During initialization, the content of the
+            various RTC control, count, alarm and status registers are untouched to preserve prior
+            RTC initializations and operation.  The core NVIC RTC interrupt is enabled.\n\n
+
+
+    @note   SAFE WRITES: The "safe write" mode is enabled by default and can be changed using the macro
+                         "ADI_RTC_CFG_ENABLE_SAFE_WRITE" defined in adi_rtc_config.h file.
+
+    @sa    adi_rtc_Enable().
+    @sa    adi_rtc_EnableInterrupts().
+    @sa    adi_rtc_SetCount().
+    @sa    adi_rtc_Close()
+*/
+ADI_RTC_RESULT adi_rtc_Open(
+               uint32_t         DeviceNumber,
+               void            *pDeviceMemory,
+               uint32_t         MemorySize,
+               ADI_RTC_HANDLE  *phDevice
+               )
+{
+    ADI_RTC_DEVICE *pDevice = pDeviceMemory;
+
+    /* store a bad handle in case of failure */
+    *phDevice = (ADI_RTC_HANDLE) NULL;
+
+#ifdef ADI_DEBUG
+    if ( DeviceNumber >= ADI_RTC_NUM_INSTANCE)
+    {
+        return ADI_RTC_INVALID_INSTANCE;
+    }
+    assert(ADI_RTC_MEMORY_SIZE == sizeof(ADI_RTC_DEVICE));
+    if (aRTCDeviceInfo[DeviceNumber].hDevice != NULL)
+    {
+        return ADI_RTC_IN_USE;
+    }
+    if(MemorySize < ADI_RTC_MEMORY_SIZE)
+    {
+      return(ADI_RTC_FAILURE);
+    }
+#endif
+
+    memset(pDeviceMemory,0,MemorySize);
+    /* initialize device data entries */
+    pDevice->pRTCRegs    = aRTCDeviceInfo[DeviceNumber].pRTCRegs;
+    
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
+
+    pDevice->pRTCRegs->CR0 = 0u;
+    pDevice->pRTCRegs->CR1 = 0u;
+    
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)    
+
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDSR0)
+
+    pDevice->pRTCRegs->SR0 = ADI_RTC_SR3_IRQ_STATUS_MASK;
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCSR0)    
+    
+    pDevice->pRTCRegs->CNT0 = 0u;
+    pDevice->pRTCRegs->CNT1 = 0u;
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCNT0)    
+    
+    /* local pointer to instance data */
+    aRTCDeviceInfo[DeviceNumber].hDevice = pDevice;
+    pDevice->pDeviceInfo = &aRTCDeviceInfo[DeviceNumber];
+
+    /* Use static configuration to initialize the RTC */
+    rtc_init(pDevice,&aRTCConfig[DeviceNumber]);
+   
+    /* store handle at application handle pointer */
+    *phDevice = pDevice;
+    pDevice->eIRQn =  aRTCDeviceInfo[DeviceNumber].eIRQn;
+    /* Enable RTC interrupts in NVIC */
+    NVIC_EnableIRQ((IRQn_Type)(pDevice->eIRQn));
+
+    return ADI_RTC_SUCCESS;            /* initialized */
+}
+
+
+/*!
+ * @brief  Uninitialize and deallocate an RTC device.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS              Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * Uninitialize and release an allocated RTC device for other use.  The core NVIC RTC interrupt is disabled.
+ *
+ * @sa        adi_rtc_Open().
+ */
+ADI_RTC_RESULT adi_rtc_Close(ADI_RTC_HANDLE const hDevice)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+
+    /* uninitialize */
+    NVIC_DisableIRQ( pDevice->eIRQn);
+
+    pDevice->pRTCRegs   = NULL;
+    pDevice->pfCallback = NULL;
+    pDevice->pCBParam   = NULL;
+    pDevice->cbWatch    = 0u;
+   
+    pDevice->pDeviceInfo->hDevice = NULL;
+    return ADI_RTC_SUCCESS;
+}
+
+
+/*************************************************************************************************
+**************************************************************************************************
+****************************************  ENABLE APIS  *******************************************
+**************************************************************************************************
+*************************************************************************************************/
+
+
+/*!
+ * @brief  Enable RTC alarm.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   bEnable    boolean Flag to enable/disable  alarm logic.
+ *              - true  :   Enable alarm logic.
+ *              - false :   Disable alarm logic.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]     Invalid device handle parameter.
+ *
+ * Enable/disable operation of RTC internal alarm logic.
+ *
+ * Alarm events and interrupt notifications are gated by enabling the alarm logic.
+ * RTC alarm interrupts require both RTC device and RTC alarm interrupt to be enabled
+ * to have been set.
+ *
+ * The alarm is relative to some future alarm value match against the RTC counter.
+ *
+ * @note The RTC device driver does not modify the alarm enable on the hardware except through use of this API.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ * @sa        adi_rtc_EnableInterrupts().
+ * @sa        adi_rtc_GetAlarm().
+ * @sa        adi_rtc_GetCount().
+ * @sa        adi_rtc_SetAlarm().
+ * @sa        adi_rtc_SetCount().
+ */
+ADI_RTC_RESULT adi_rtc_EnableAlarm(ADI_RTC_HANDLE const hDevice, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
+      
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* set/clear RTC alarm enable */
+    if (bEnable)
+    {
+        pDevice->pRTCRegs->CR0  |= BITM_RTC_CR0_ALMEN;
+    }
+    else
+    {
+        pDevice->pRTCRegs->CR0 &= (uint16_t)(~BITM_RTC_CR0_ALMEN);
+    }
+    ADI_EXIT_CRITICAL_REGION();
+    
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)    
+
+    return ADI_RTC_SUCCESS;
+}
+
+/*!
+ * @brief  Enable MOD60 RTC alarm.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   bEnable    boolean Flag for enable/disable mod60  alarm logic.
+ *               - true   :  Enable mod60 alarm logic.
+ *               - false  :  Disable mod60 alarm logic.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * Enable/disable operation of RTC internal MOD60 alarm logic.
+ *
+ * Alarm events and interrupt notifications are gated by enabling the alarm logic.
+ * RTC alarm interrupts require both RTC device and RTC alarm interrupt to be enabled
+ * to have been set.
+ *
+ * The alarm is relative to some future alarm value match against the RTC counter.
+ *
+ * @note The RTC device driver does not modify the alarm enable on the hardware except through use of this API.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ * @sa        adi_rtc_EnableInterrupts().
+ * @sa        adi_rtc_GetAlarm().
+ * @sa        adi_rtc_GetCount().
+ * @sa        adi_rtc_SetAlarm().
+ * @sa        adi_rtc_SetCount().
+ */
+ADI_RTC_RESULT adi_rtc_EnableMod60Alarm(ADI_RTC_HANDLE const hDevice, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+    /* Mod-60 Alarm is present only in RTC-1 */
+    if(pDevice->pRTCRegs == pADI_RTC0)
+    {
+        return(ADI_RTC_OPERATION_NOT_ALLOWED);
+    }
+
+#endif
+
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
+
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* set/clear RTC alarm enable */
+    if (bEnable)
+    {
+        pDevice->pRTCRegs->CR0  |= BITM_RTC_CR0_MOD60ALMEN;
+    }
+    else
+    {
+        pDevice->pRTCRegs->CR0 &= (uint16_t)(~BITM_RTC_CR0_MOD60ALMEN);
+    }
+    ADI_EXIT_CRITICAL_REGION();
+    
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)    
+
+    return ADI_RTC_SUCCESS;
+}
+
+/*!
+ * @brief  Enable RTC device.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   bEnable    boolean Flag for enabling/disabling  the RTC device.
+ *                - true   :     Enable RTC device.
+ *                - false  :     Disable RTC device.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * Global enable/disable of the RTC controller.  Enables counting of elapsed real time and acts
+ * as a master enable for the RTC.
+ *
+ * @note When enabled, the RTC input clock pre-scaler and trim interval  are realigned.
+ *
+ * @note The RTC device driver does not modify the device enable on the hardware except through use of this API.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_EnableAlarm().
+ */
+
+ADI_RTC_RESULT adi_rtc_Enable(ADI_RTC_HANDLE const hDevice, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
+    
+
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* set/clear RTC device enable */
+    if (bEnable)
+    {
+         pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_CNTEN;
+    }
+    else
+    {
+        pDevice->pRTCRegs->CR0 &=(uint16_t)(~BITM_RTC_CR0_CNTEN);
+    }
+    ADI_EXIT_CRITICAL_REGION();
+    
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)    
+      
+    return ADI_RTC_SUCCESS;
+}
+
+
+/* Data structures used to manage the enabling of all RTC interrupts */
+static uint16_t cr0 = 0u, cr1 = 0u, cr3oc = 0u, cr4oc = 0u, cr2ic = 0u, cr5ocs = 0u;
+
+static struct xxx
+{
+  uint16_t *cr;
+  uint16_t  bitPositionl; 
+} 
+Interrupt_Details[ADI_RTC_NUM_INTERRUPTS] =
+{
+  { &cr0, BITP_RTC_CR0_ALMINTEN }, 
+  { &cr0, BITP_RTC_CR0_MOD60ALMINTEN }, 
+  { &cr0, BITP_RTC_CR0_ISOINTEN },
+  { &cr0, BITP_RTC_CR0_WPNDERRINTEN },
+  { &cr0, BITP_RTC_CR0_WSYNCINTEN },
+  { &cr0, BITP_RTC_CR0_WPNDINTEN },
+  { &cr1, BITP_RTC_CR1_CNTINTEN },
+  { &cr1, BITP_RTC_CR1_PSINTEN },
+  { &cr1, BITP_RTC_CR1_TRMINTEN },
+  { &cr1, BITP_RTC_CR1_CNTROLLINTEN },
+  { &cr1, BITP_RTC_CR1_CNTMOD60ROLLINTEN },
+  { &cr3oc, BITP_RTC_CR3SS_SS1IRQEN },
+  { &cr3oc, BITP_RTC_CR3SS_SS2IRQEN },
+  { &cr3oc, BITP_RTC_CR3SS_SS2IRQEN },
+  { &cr3oc, BITP_RTC_CR3SS_SS4IRQEN },
+  { &cr2ic, BITP_RTC_CR2IC_IC0IRQEN },
+  { &cr2ic, BITP_RTC_CR2IC_IC2IRQEN },
+  { &cr2ic, BITP_RTC_CR2IC_IC3IRQEN },
+  { &cr2ic, BITP_RTC_CR2IC_IC4IRQEN },
+  { &cr2ic, BITP_CLKG_OSC_CTL_LFX_FAIL_STA },
+  { &cr3oc, BITM_RTC_CR3SS_SS4FEIRQEN},
+  { &cr3oc, BITM_RTC_CR3SS_SS3FEIRQEN},  
+  { &cr3oc, BITM_RTC_CR3SS_SS2FEIRQEN},  
+  { &cr3oc, BITM_RTC_CR3SS_SS1FEIRQEN}, 
+  { &cr4oc, BITP_RTC_CR4SS_SS4MSKEN},  
+  { &cr4oc, BITP_RTC_CR4SS_SS3MSKEN},  
+  { &cr4oc, BITP_RTC_CR4SS_SS2MSKEN},  
+  { &cr4oc, BITP_RTC_CR4SS_SS1MSKEN},  
+  { &cr5ocs, BITP_RTC_CR5SSS_SS3SMPMTCHIRQEN},  
+  { &cr5ocs, BITP_RTC_CR5SSS_SS2SMPMTCHIRQEN},  
+  { &cr5ocs, BITP_RTC_CR5SSS_SS1SMPMTCHIRQEN}
+  
+};
+
+
+/*!
+ * @brief  Manage interrupt enable/disable in the RTC and NVIC controller.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   Interrupts Conveys which interrupts are affected.
+ * @param[in]   bEnable     Flag which controls whether to enable or disable RTC interrupt.
+ *               - true  :  Enable RTC interrupts.
+ *               - false :  Disable RTC interrupts.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * Enable/disable RTC interrupt as well as manage global NVIC enable/disable for the RTC.
+ * Input parameter \a Interrupts is a interrupt ID of type #ADI_RTC_INT_TYPE designating the 
+ * interrupt to be enabled or disabled.  The interrupt parameter may be zero, which will then simply
+ * manage the NVIC RTC enable and leave the individual RTC interrupt enables unchanged.
+ * Input parameter \a bEnable controls whether to enable or disable the designated set of interrupts.
+ *
+ * @note The RTC device driver does not modify the interrupt enables on the hardware except through use of this API.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ */
+ADI_RTC_RESULT adi_rtc_EnableInterrupts (ADI_RTC_HANDLE const hDevice, ADI_RTC_INT_TYPE Interrupts, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+    if( (pDevice->pRTCRegs == pADI_RTC0) &&(((uint16_t)((ADI_RTC_MOD60ALM_INT | ADI_RTC_ISO_DONE_INT|
+                                             ADI_RTC_COUNT_INT    | 
+                                             ADI_RTC_TRIM_INT    | ADI_RTC_COUNT_ROLLOVER_INT |
+                                             ADI_RTC_MOD60_ROLLOVER_INT
+                                             )) & (uint16_t)Interrupts) != 0u))
+    {
+        return(ADI_RTC_INVALID_PARAM);
+    }
+    
+    assert(sizeof(Interrupt_Details)/sizeof(Interrupt_Details[0]) == ADI_RTC_NUM_INTERRUPTS);
+#endif
+    
+    /* TODO - more sync for new registers */
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
+    PEND_BEFORE_WRITE(SR2,BITM_RTC_SR2_WPNDCR1MIR)
+    
+    uint8_t ndx = 0u;
+    cr0 = 0u; cr1 = 0u; cr3oc = 0u; cr4oc = 0u; cr2ic = 0u; cr5ocs = 0u;
+
+    while( Interrupts )
+    {
+      if( 0u != (Interrupts & 1u) )
+      {
+        uint16_t *cr = Interrupt_Details[ndx].cr;
+        uint16_t  enableBitPosition = Interrupt_Details[ndx].bitPositionl;
+        *cr = *cr | (1u << enableBitPosition);
+      }
+      Interrupts >>= 1;
+      ndx++;
+    }
+    /* set/clear interrupt enable bit(s) in control register */
+    if (bEnable)
+    {
+        pDevice->pRTCRegs->CR0 |= cr0;
+        pDevice->pRTCRegs->CR1 |= cr1;
+        pDevice->pRTCRegs->CR3SS |= cr3oc;
+        pDevice->pRTCRegs->CR4SS |= cr4oc;
+        pDevice->pRTCRegs->CR2IC |= cr2ic;
+        pDevice->pRTCRegs->CR5SSS |= cr5ocs;
+       
+    } 
+    else
+    {
+        pDevice->pRTCRegs->CR0 &= ~cr0;
+        pDevice->pRTCRegs->CR1 &= ~cr1;
+        pDevice->pRTCRegs->CR3SS &= ~cr3oc;
+        pDevice->pRTCRegs->CR4SS &= ~cr4oc;
+        pDevice->pRTCRegs->CR2IC &= ~cr2ic;
+        pDevice->pRTCRegs->CR5SSS &= ~cr5ocs;
+    }
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)    
+    SYNC_AFTER_WRITE(SR2,BITM_RTC_SR2_WSYNCCR1MIR)        
+    return ADI_RTC_SUCCESS;
+}
+
+
+/*!
+ * @brief  Enable RTC automatic clock trimming.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   bEnable      Flag controlling RTC enabling trim.
+ *                - true     Enable RTC trimming.
+ *                - false    Disable RTC trimming.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * Enable/disable automatic application of trim values to the main RTC clock.  Allows application
+ * of periodic real-time RTC clock adjustments to correct for drift.  Trim values are pre-calibrated
+ * and stored at manufacture.  Trim values may be recalibrated by monitoring the RTC clock externally
+ * and computing/storing new trim values (see #adi_rtc_SetTrim).
+ *
+ * @note The trim interval is reset with device enable, #adi_rtc_Enable().
+ *
+ * @note The RTC device driver does not modify the trim enable on the hardware except through use of this API.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ * @sa        adi_rtc_GetTrim().
+ * @sa        adi_rtc_SetTrim().
+ */
+ADI_RTC_RESULT adi_rtc_EnableTrim (ADI_RTC_HANDLE const hDevice, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
+    
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* set/clear trim enable bit(s) in control register */
+    if (bEnable)
+    {
+        pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_TRMEN;
+    }
+    else
+    {
+        pDevice->pRTCRegs->CR0 &=(uint16_t)(~BITM_RTC_CR0_TRMEN);
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)    
+    
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Enable input capture for the specified channel.
+ *
+ * @param[in]   hDevice       Device handle obtained from adi_rtc_Open().
+ * @param[in]   eInpChannel   Specify input compare channel. 
+ * @param[in]   bEnable      Flag for enabling  RTC input capture for specified channel.
+ *                - true     Enable input capture.
+ *                - false    Disable input capture.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ */
+ADI_RTC_RESULT adi_rtc_EnableInputCapture (ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eInpChannel, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC)
+    
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* set/clear trim input capture enable for specified channel*/
+    if (bEnable)
+    {
+        pDevice->pRTCRegs->CR2IC |=(uint16_t)eInpChannel;
+    }
+    else
+    {
+        pDevice->pRTCRegs->CR2IC &= (uint16_t)(~(uint16_t)eInpChannel);
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC)    
+    
+    return ADI_RTC_SUCCESS;
+}
+
+/*!
+ * @brief  Enable Overwrite of Unread Snapshots for all RTC Input Capture Channels.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   bEnable      Flag for enabling  overwriting the unread snapshot.
+ *                - true     Enable overwrite snapshot.
+ *                - false    Disable overwrite of snapshot.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ */
+ADI_RTC_RESULT adi_rtc_EnableOverwriteSnapshot (ADI_RTC_HANDLE const hDevice, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC)
+    
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* set/clear trim input capture enable for specified channel*/
+    if (bEnable)
+    {
+        pDevice->pRTCRegs->CR2IC |= BITM_RTC_CR2IC_ICOWUSEN;
+    }
+    else
+    {
+        pDevice->pRTCRegs->CR2IC &= (uint16_t)~BITM_RTC_CR2IC_ICOWUSEN;
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC)    
+    
+    return ADI_RTC_SUCCESS;
+}
+
+/*!
+ * @brief  Set  input capture polarity  for the specified channel.
+ *
+ * @param[in]   hDevice        Device handle obtained from adi_rtc_Open().
+ * @param[in]   eInpChannel    Specify which input capture  channel.  
+ * @param[in]   bEnable        Flag for selecting   RTC input capture polarity.
+ *                - false     channel uses a *high-to-low* transition on its GPIO pin to signal an input capture event
+ *                - true      channel uses a *low-to-high* transition on its GPIO pin to signal an input capture event.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ */
+ADI_RTC_RESULT adi_rtc_SetInputCapturePolarity (ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eInpChannel, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+    uint32_t nInpChannel = (uint16_t)eInpChannel;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC)
+    
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* set/clear trim input capture enable for specified channel*/
+    if (bEnable)
+    {
+        pDevice->pRTCRegs->CR2IC |= (uint16_t)(nInpChannel << BITP_RTC_CR2IC_IC0LH);
+    }
+    else
+    {
+        pDevice->pRTCRegs->CR2IC &= (uint16_t)~(nInpChannel << BITP_RTC_CR2IC_IC0LH);
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC)    
+    
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Enable output for the specified Sensor Strobe Channel.
+ *
+ * @param[in]   hDevice      Device handle obtained from adi_rtc_Open().
+ * @param[in]   eSSChannel   Specify which Sensor Strobe channel.
+ * @param[in]   bEnable      Flag for enabling  output for specified Sensor Strobe channel.
+ *                - true     Enable output.
+ *                - false    Disable output.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ */
+ADI_RTC_RESULT adi_rtc_EnableSensorStrobeOutput (ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR3SS)
+    
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* set/clear Sensor Strobe enable for specified channel*/
+    if (bEnable)
+    {
+        pDevice->pRTCRegs->CR3SS |=(uint16_t)eSSChannel;
+    }
+    else
+    {
+        pDevice->pRTCRegs->CR3SS &= (uint16_t)(~(uint16_t)eSSChannel);
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR3SS)    
+    
+    return ADI_RTC_SUCCESS;
+}
+
+/*!
+ * @brief  Enable auto reload for given Sensor Strobe Channel.
+ *
+ * @param[in]   hDevice        Device handle obtained from adi_rtc_Open().
+ * @param[in]   eSSChannel     Sensor Strobe Channel number.
+ * @param[in]   bEnable        Flag to enable auto reload for given Sensor Strobe Channel.
+ *                - true       Enable auto reload.
+ *                - false      Disable auto reload.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ */
+ADI_RTC_RESULT adi_rtc_EnableAutoReload(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR4SS)
+    
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* set/clear auto reload enable options */
+    /* Note that channel 4 does not have this feature */
+    if (bEnable)
+    {
+      switch( eSSChannel)
+      {
+      case ADI_RTC_SS_CHANNEL_1:
+        pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS1ARLEN;
+        break;
+      case ADI_RTC_SS_CHANNEL_2:
+        pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS2ARLEN;
+        break;
+      case ADI_RTC_SS_CHANNEL_3:
+        pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS3ARLEN;
+        break;
+      default:
+        return ADI_RTC_FAILURE;
+      }
+        
+    }
+    else
+    {
+      switch( eSSChannel)
+      {
+      case ADI_RTC_SS_CHANNEL_1:
+        pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS1ARLEN;
+        break;
+      case ADI_RTC_SS_CHANNEL_2:
+        pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS2ARLEN;
+        break;
+      case ADI_RTC_SS_CHANNEL_3:
+        pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS3ARLEN;
+        break;
+      default:
+        return ADI_RTC_FAILURE;
+      }
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR4SS)    
+    
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Set auto reload value for the given Sensor Strobe channel.
+ *
+ * @param[in]   hDevice     Device handle obtained from adi_rtc_Open().
+ * @param[in]   eSSChannel  Sensor Strobe channel for which auto reload to be set. 
+ * @param[in]   nValue      Auto reload value to be set.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ * 
+ *
+ */
+ADI_RTC_RESULT adi_rtc_SetAutoReloadValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t nValue)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    
+    switch( eSSChannel )
+    {
+        case ADI_RTC_SS_CHANNEL_1:
+            /* Wait till previously posted write to Control Register to complete */ 
+            PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1)
+            pDevice->pRTCRegs->SS1 = nValue;
+            /* Wait till  write to Control Register to take effect */    
+            SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS1)    
+            break;
+     
+        case ADI_RTC_SS_CHANNEL_2:
+            /* Wait till previously posted write to Control Register to complete */ 
+            PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2)
+            pDevice->pRTCRegs->SS2 = nValue;
+            /* Wait till  write to Control Register to take effect */    
+            SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS2)    
+            break;
+          
+        case ADI_RTC_SS_CHANNEL_3:
+            /* Wait till previously posted write to Control Register to complete */ 
+            PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3)
+            pDevice->pRTCRegs->SS3 = nValue;
+            /* Wait till  write to Control Register to take effect */    
+            SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS3)    
+            break;
+
+        case ADI_RTC_SS_CHANNEL_4:
+            PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS4)
+            pDevice->pRTCRegs->SS4 = nValue;
+            /* Wait till  write to Control Register to take effect */    
+            SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS4)    
+            break;
+            
+        default:
+            return ADI_RTC_FAILURE;
+
+    }
+    
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Enable or disable thermometer-code masking for the given Sensor Strobe Channel.
+ *
+ * @param[in]   hDevice         Device handle obtained from adi_rtc_Open().
+ * @param[in]   eSSChannel      Sensor Strobe channel for which thermometer-code masking to be enabled or disabled. 
+ * @param[in]   bEnable         Flag to enable or disable masking for the given Sensor Strobe channel.
+ *                - true        Enable masking .
+ *                - false       Disable masking.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ */
+ADI_RTC_RESULT adi_rtc_EnableSensorStrobeChannelMask(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR5, BITM_RTC_SR5_WPENDCR4SS)
+    
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();    
+    /* set/clear auto reload enable options */
+    if (bEnable)
+    {
+        pDevice->pRTCRegs->CR4SS |= (uint16_t)eSSChannel;
+    }
+    else
+    {
+        pDevice->pRTCRegs->CR4SS &= (uint16_t)~(uint16_t)eSSChannel;
+    }
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR4SS)    
+    
+    return ADI_RTC_SUCCESS;
+}
+
+/*!
+ * @brief  To set channel mask for the given Sensor Strobe channel.
+ *
+ * @param[in]   hDevice      Device handle obtained from adi_rtc_Open().
+ * @param[in]   eSSChannel   Sensor Strobe Channel for which the mask to be set. 
+ * @param[in]   nMask        Channel Mask to be set for Sensor Strobe channel.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_CHANNEL         The given channel is invalid.
+ */
+ADI_RTC_RESULT adi_rtc_SetSensorStrobeChannelMask(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint8_t nMask)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+    uint16_t        MaskPos = 0u;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    
+    switch( eSSChannel )
+    {
+        case ADI_RTC_SS_CHANNEL_1:
+            MaskPos  = (uint16_t)BITP_RTC_SSMSK_SS1MSK;
+            break;
+     
+        case ADI_RTC_SS_CHANNEL_2:
+            MaskPos  = (uint16_t)BITP_RTC_SSMSK_SS2MSK;
+            break;
+          
+        case ADI_RTC_SS_CHANNEL_3:
+            MaskPos  = (uint16_t)BITP_RTC_SSMSK_SS3MSK;
+            break;
+
+        case ADI_RTC_SS_CHANNEL_4:
+            MaskPos  = (uint16_t)BITP_RTC_SSMSK_SS4MSK; 
+            break;
+            
+        default:
+            return ADI_RTC_INVALID_CHANNEL;
+    }
+
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR5, BITM_RTC_SR5_WPENDSSMSK)
+    
+    pDevice->pRTCRegs->SSMSK = ((uint16_t)nMask & 0xFu) << MaskPos;
+
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR4, BITM_RTC_SR4_WSYNCSSMSK)    
+    
+    return ADI_RTC_SUCCESS;
+}
+
+/*************************************************************************************************
+**************************************************************************************************
+******************************************   GET APIS   ******************************************
+**************************************************************************************************
+*************************************************************************************************/
+
+
+/*!
+ * @brief  Get current RTC alarm value.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[out]  pAlarm     Pointer to application memory where the alarm value is written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ * Read the currently programmed 32-bit RTC alarm value and write it to the address provided by parameter \a pAlarm.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_SetAlarm().
+ */
+ADI_RTC_RESULT adi_rtc_GetAlarm (ADI_RTC_HANDLE hDevice, uint32_t *pAlarm)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+    uint32_t nAlarm;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
+
+    /* disable interrupts during paired read */
+    NVIC_DisableIRQ(pDevice->eIRQn);
+        nAlarm  =(uint32_t) pDevice->pRTCRegs->ALM1 << 16u;
+        nAlarm |= (uint32_t)pDevice->pRTCRegs->ALM0;
+    NVIC_EnableIRQ((IRQn_Type)(pDevice->eIRQn));
+
+    *pAlarm = nAlarm;
+
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Get current RTC alarm value  with fractional part also.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[out]  pAlarm     Pointer to application memory where the alarm value is written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ * Read the currently programmed 32-bit RTC alarm value and write it to the address provided by parameter \a pAlarm.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_SetAlarm().
+ */
+ADI_RTC_RESULT adi_rtc_GetAlarmEx (ADI_RTC_HANDLE hDevice, float *pAlarm)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+    uint32_t nAlarm,nTemp;
+    uint16_t nPreScale;
+    float fFraction;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
+    nPreScale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP;
+    /* disable interrupts during paired read */
+    NVIC_DisableIRQ(pDevice->eIRQn);
+    nAlarm  = (uint32_t)pDevice->pRTCRegs->ALM1 << 16u;
+    nAlarm |= (uint32_t)pDevice->pRTCRegs->ALM0;
+    NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn);
+    nTemp = 1lu<<nPreScale;
+    fFraction = (float)pDevice->pRTCRegs->ALM2 /(float)(nTemp);
+
+    *pAlarm = (float)nAlarm+fFraction;
+
+    return ADI_RTC_SUCCESS;
+}
+
+
+/*!
+ * @brief  Get current RTC control register value.
+ *
+ * @param[in]   hDevice      Device handle obtained from adi_rtc_Open().
+ * @param[in]   eRegister    Specify which register content need to be returned.
+ *
+ * @param[out]  pControl   Pointer to application memory where the control register value is written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ * Read the currently programmed 16-bit RTC control register value and write it to the address provided by parameter \a pControl.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtcSetControl().
+ */
+ADI_RTC_RESULT adi_rtc_GetControl (ADI_RTC_HANDLE hDevice, ADI_RTC_CONTROL_REGISTER eRegister ,uint32_t *pControl)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
+
+     switch(eRegister)
+     {
+     case ADI_RTC_CONTROL_REGISTER_0:
+         *pControl = pDevice->pRTCRegs->CR0;
+         break;
+     case ADI_RTC_CONTROL_REGISTER_1:
+         *pControl = pDevice->pRTCRegs->CR1;
+         break;
+     default:
+         return(ADI_RTC_FAILURE);
+     }
+    return ADI_RTC_SUCCESS;
+}
+
+
+/*!
+ * @brief  Get current RTC count value.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[out]  pCount     Pointer to application memory where the count value is written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ * Read the current 32-bit RTC count value and write it to the address provided by parameter \a pCount.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ * @sa        adi_rtc_SetCount().
+ */
+ADI_RTC_RESULT adi_rtc_GetCount(ADI_RTC_HANDLE const hDevice, uint32_t *pCount)
+{
+    uint32_t nCount;
+    ADI_RTC_DEVICE *pDevice = hDevice;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+
+    /* Wait till previously posted write to couunt Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1))
+
+    /* disable interrupts during paired read */
+    NVIC_DisableIRQ(pDevice->eIRQn);
+    nCount  = (uint32_t)pDevice->pRTCRegs->CNT1 << 16u;
+    nCount |= pDevice->pRTCRegs->CNT0;
+    *pCount = nCount;
+    NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn);
+
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Get current RTC count value with fraction.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[out]  pfCount    Pointer to application memory where the count(with fraction) value is written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ * Read the current 32-bit RTC count value and write it to the address provided by parameter \a pCount.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ * @sa        adi_rtc_SetCount().
+ */
+ADI_RTC_RESULT adi_rtc_GetCountEx(ADI_RTC_HANDLE const hDevice, float *pfCount)
+{
+    uint32_t nCount,nTemp;
+    uint16_t nPrescale;
+    ADI_RTC_DEVICE *pDevice = hDevice;
+    float fFraction;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to couunt Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1))
+    nPrescale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP;
+    /* disable interrupts during paired read */
+    NVIC_DisableIRQ(pDevice->eIRQn);
+    nCount  = (uint32_t)pDevice->pRTCRegs->CNT1 << 16u;
+    nCount |= pDevice->pRTCRegs->CNT0;
+    nTemp = (1lu<<nPrescale);
+    fFraction = (float)pDevice->pRTCRegs->CNT2/(float)(nTemp); 
+    NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn);
+    *pfCount = (float)nCount+ fFraction;
+
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Get current RTC count value of all registers.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[out]  pnCount    Pointer to application memory where the count's 32 MSB are written.
+ * @param[out]  pfCount    Pointer to application memory where the count's 16 LSB are written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]  NULL pointer for input parameter.
+ *
+ * Read the current 32-bit RTC count integer value and fractional value in the integer format.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ * @sa        adi_rtc_SetCount().
+ */
+ADI_RTC_RESULT adi_rtc_GetCountRegs(ADI_RTC_HANDLE const hDevice, uint32_t *pnCount, uint32_t *pfCount)
+{
+    uint32_t nCount;
+    ADI_RTC_DEVICE *pDevice = hDevice;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to couunt Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1))
+    /* disable interrupts during paired read */
+    NVIC_DisableIRQ(pDevice->eIRQn);
+    nCount  = (uint32_t)pDevice->pRTCRegs->CNT1 << 16u;
+    nCount |= pDevice->pRTCRegs->CNT0;
+    *pnCount= nCount;
+    *pfCount = (uint32_t)pDevice->pRTCRegs->CNT2; 
+    NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn);
+    return ADI_RTC_SUCCESS;
+}
+
+
+
+/*!
+ * @brief  Get current RTC clock trim value.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[out]  peTrim     Pointer to #ADI_RTC_TRIM_VALUE where the  trim value is to be  written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS              Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ * Read the current 16-bit RTC trim value and write it to the address provided by parameter \a pTrim.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_EnableInterrupts().
+ * @sa        adi_rtc_EnableTrim().
+ * @sa        adi_rtc_GetWritePendStatus().
+ * @sa        adi_rtc_GetWriteSyncStatus().
+ * @sa        adi_rtc_SetTrim().
+ */
+ADI_RTC_RESULT adi_rtc_GetTrim (ADI_RTC_HANDLE hDevice, ADI_RTC_TRIM_VALUE *peTrim)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+    if(peTrim == NULL)
+    {
+        return( ADI_RTC_INVALID_PARAM);
+    }
+#endif
+
+    /* Wait till previously posted write to couunt Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDTRM);
+
+    *peTrim =(ADI_RTC_TRIM_VALUE)(pDevice->pRTCRegs->TRM & BITM_RTC_TRM_VALUE);
+
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Get Sensor Strobe value for the given Sensor Strobe channel.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   eSSChannel Sensor Strobe Channel whose value to be read.
+ * @param[out]  pValue     Pointer to application memory where the Sensor Strobe value to be written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ * @sa        adi_rtc_SetCount().
+ */
+ADI_RTC_RESULT adi_rtc_GetSensorStrobeValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t *pValue)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+    
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    switch( eSSChannel )
+    {
+    case ADI_RTC_SS_CHANNEL_1:
+      PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1)
+      *pValue = pDevice->pRTCRegs->SS1;
+      break;
+      
+    case ADI_RTC_SS_CHANNEL_2:
+      /* Wait till previously posted write to Control Register to complete */ 
+      PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2)
+      *pValue = pDevice->pRTCRegs->SS2;
+      break;
+      
+    case ADI_RTC_SS_CHANNEL_3:
+      /* Wait till previously posted write to Control Register to complete */ 
+      PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3)
+      *pValue = pDevice->pRTCRegs->SS3;
+      break;
+      
+    case ADI_RTC_SS_CHANNEL_4:
+      PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS4)
+      *pValue = pDevice->pRTCRegs->SS4;
+      break;
+      
+    default:
+      return ADI_RTC_FAILURE;
+    }
+    
+    
+    
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Set Sensor Strobe value for the given Sensor Strobe channel.
+ *
+ * @param[in]   hDevice         Device handle obtained from adi_rtc_Open().
+ * @param[in]   eSSChannel      Sensor Strobe Channel. 
+ * @param[out]  nValue          Sensor Strobe value to be set for the given Sensor Strobe channel .
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ * @sa        adi_rtc_SetCount().
+ */
+ADI_RTC_RESULT adi_rtc_SetSensorStrobeValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t nValue)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    
+    switch( eSSChannel )
+    {
+    case ADI_RTC_SS_CHANNEL_1:
+      /* Wait till previously posted write to Control Register to complete */ 
+      PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1)
+      pDevice->pRTCRegs->SS1 = nValue;
+      /* Wait till  write to Control Register to take effect */    
+      SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS1)    
+      break;
+      
+    case ADI_RTC_SS_CHANNEL_2:
+      /* Wait till previously posted write to Control Register to complete */ 
+      PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2)
+      pDevice->pRTCRegs->SS2 = nValue;
+      /* Wait till  write to Control Register to take effect */    
+      SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS2)    
+      break;
+      
+    case ADI_RTC_SS_CHANNEL_3:
+      /* Wait till previously posted write to Control Register to complete */ 
+      PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3)
+      pDevice->pRTCRegs->SS3 = nValue;
+      /* Wait till  write to Control Register to take effect */    
+      SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS3)    
+      break;
+      
+    case ADI_RTC_SS_CHANNEL_4:
+      /* Wait till previously posted write to Control Register to complete */ 
+      PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS4)
+      pDevice->pRTCRegs->SS4 = nValue;
+      /* Wait till  write to Control Register to take effect */    
+      SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS4)    
+      break;
+      
+    default:
+      return ADI_RTC_FAILURE;
+    }
+      
+    return ADI_RTC_SUCCESS;
+}
+
+/*!
+ * @brief  Get input capture value for specified input channel.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   eChannel   Specify which input capture  channel. 
+ * @param[out]  pValue     Pointer to application memory where the input capture value to be written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS              Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *                - #ADI_RTC_INVALID_CHANNEL [D]     Input channel-0 is not valid for this operation since 
+ *                                                   channel-0 can provide precise (47bit) capture value.
+ *
+ *
+ *
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ * @sa        adi_rtc_SetCount().
+ */
+ADI_RTC_RESULT adi_rtc_GetInputCaptureValue(ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eChannel, uint16_t *pValue)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+    ADI_RTC_RESULT eResult= ADI_RTC_SUCCESS;
+    
+#ifdef ADI_DEBUG
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    switch(eChannel)
+    {
+        case ADI_RTC_INPUT_CHANNEL_2:
+           *pValue = pDevice->pRTCRegs->IC2;
+            break;
+        case ADI_RTC_INPUT_CHANNEL_3:
+           *pValue = pDevice->pRTCRegs->IC3;
+            break;
+          
+        case ADI_RTC_INPUT_CHANNEL_4:
+           *pValue = pDevice->pRTCRegs->IC4;
+            break;
+        default:  
+           eResult = ADI_RTC_INVALID_CHANNEL;
+           break;
+    }
+    return(eResult);
+}
+/*!
+ * @brief  Get snapshot of the value of RTC .
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   eChannel   Specify input channel from which captured value to be obtained.
+ * @param[in]   pFraction  Pointer to application memory where the  fractional part of snap shot value to be written.
+ * @param[out]  pValue     Pointer to application memory where the snap shot value  of RTC  to be written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS              Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ *
+ *
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_Enable().
+ * @sa        adi_rtc_SetCount().
+ */
+ADI_RTC_RESULT adi_rtc_GetSnapShot(ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eChannel, uint32_t *pValue, uint16_t *pFraction)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+    ADI_RTC_RESULT eResult= ADI_RTC_SUCCESS;
+    uint32_t nCount = 0u;
+#ifdef ADI_DEBUG
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* disable interrupts during paired read */
+    NVIC_DisableIRQ(pDevice->eIRQn);
+    nCount  = (uint32_t)pDevice->pRTCRegs->SNAP1 << 16u;
+    nCount |= pDevice->pRTCRegs->SNAP0;
+    *pFraction = pDevice->pRTCRegs->SNAP2;
+    *pValue = nCount;
+    NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn);
+    return(eResult);
+}
+
+
+/*!
+ * @brief  Get current RTC posted write pending status.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[out]  pPendBits  Pointer to application memory where the posted write status is written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS              Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ *
+ * \b Pending \b Writes: Register writes to internal RTC registers take time to complete because the RTC controller
+ * clock is running at a much slower (32kHz) rate than the core processor clock.  So each RTC write register has a
+ * one-deep FIFO to hold write values until the RTC can effect them.  This gives rise to the notion of a \a pending
+ * \a write state: if a write is already pending and another write from the core comes along before the first (pending)
+ * write has cleared to its destination register, the second write may be lost because the FIFO is full already.
+ *
+ * To avoid data loss, the user may tell the RTC device driver to enforce safe writes with the configuration switch
+ *  ADI_RTC_CFG_ENABLE_SAFE_WRITE.  Enabeling safe writes (on be default) insures write data is never lost by
+ * detecting and pausing on pending writes prior writing new data.  The penalty in using safe writes is the stall
+ * overhead in execution (which is not incurred if there is nothing pending).  Additionally, \a all pending writes
+ * may also be synchronized manually with the #adi_rtc_SynchronizeAllWrites() API, which will pause until all
+ * pending RTC writes have completed.
+ *
+ * The distinction between "pend" status (#adi_rtc_GetWritePendStatus()) and "sync" (#adi_rtc_GetWriteSyncStatus())
+ * status is that the \a pend state is normally clear and is set only while no room remains in a register's write FIFO,
+ * whereas \a sync state is normally set and is clear only while the effects of the write are not yet apparent.
+ *
+ * Each write error
+ * source may be configured to interrupt the core by enabling the appropriate
+ * write error interrupt mask bit in the RTC control register (see the
+ * #adi_rtc_EnableInterrupts() API), at which time, the RTC interrupt handler
+ * will be dispatched.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        #adi_rtc_EnableInterrupts().
+ * @sa        adi_rtc_GetWriteSyncStatus().
+ * @sa        adi_rtc_SynchronizeAllWrites().
+ */
+ADI_RTC_RESULT adi_rtc_GetWritePendStatus (ADI_RTC_HANDLE const hDevice, ADI_RTC_WRITE_STATUS *pPendBits)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+    uint16_t nPendBits;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* get the value */
+    nPendBits = pDevice->pRTCRegs->SR1 & ADI_RTC_WRITE_STATUS_MASK;
+    *pPendBits = (ADI_RTC_WRITE_STATUS)nPendBits;
+
+    return ADI_RTC_SUCCESS;
+}
+
+
+/*!
+ * @brief  Get current RTC posted write synchronization status.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[out]  pSyncBits  Pointer to application memory where the posted write status is written.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS              Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       NULL pointer for input parameter.
+ *
+ *
+ * \b Pending \b Writes: Register writes to internal RTC registers take time to complete because the RTC controller
+ * clock is running at a much slower (32kHz) rate than the core processor clock.  So each RTC write register has a
+ * one-deep FIFO to hold write values until the RTC can effect them.  This gives rise to the notion of a \a pending
+ * \a write state: if a write is already pending and another write from the core comes along before the first (pending)
+ * write has cleared to its destination register, the second write may be lost because the FIFO is full already.
+ *
+ * To avoid data loss, the user may tell the RTC device driver to enforce safe writes with the
+ * #ADI_RTC_CFG_ENABLE_SAFE_WRITE switch.  Enabling safe writes (on be default) insures write data is never lost by
+ * detecting and pausing on pending writes prior writing new data.  The penalty in using safe writes is the stall
+ * overhead in execution (which is not incurred if there is nothing pending).  Additionally, \a all pending writes
+ * may also be synchronized manually with the #adi_rtc_SynchronizeAllWrites() API, which will pause until all
+ * pending RTC writes have completed.
+ *
+ * The distinction between "pend" status (#adi_rtc_GetWritePendStatus()) and "sync" (#adi_rtc_GetWriteSyncStatus())
+ * status is that the \a pend state is normally clear is set only while no room remains in a register's write FIFO,
+ * whereas \a sync state is normally set and is clear only while the effects of the write are not yet apparent.
+ *
+ * Each write error source may be configured to interrupt the core by enabling
+ * the appropriate write error interrupt mask bit in the RTC control register
+ * (see the #adi_rtc_EnableInterrupts() API), at which time, the RTC interrupt
+ * handler will be dispatched.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        #adi_rtc_EnableInterrupts().
+ * @sa        adi_rtc_GetWritePendStatus().
+ * @sa        adi_rtcStallOnPendingWrites().
+ * @sa        adi_rtc_SynchronizeAllWrites().
+ */
+ADI_RTC_RESULT  adi_rtc_GetWriteSyncStatus (ADI_RTC_HANDLE const hDevice, ADI_RTC_WRITE_STATUS *pSyncBits)
+{
+   ADI_RTC_DEVICE *pDevice = hDevice;
+   uint16_t nSyncBits;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to couunt Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDSR0);
+
+    /* get the value */
+    nSyncBits = pDevice->pRTCRegs->SR0 & ADI_RTC_WRITE_STATUS_MASK;
+    *pSyncBits = (ADI_RTC_WRITE_STATUS)nSyncBits;
+
+    return ADI_RTC_SUCCESS;
+}
+
+
+/*************************************************************************************************
+**************************************************************************************************
+******************************************   SET APIS   ******************************************
+**************************************************************************************************
+*************************************************************************************************/
+
+
+/*!
+ * @brief  Set a new RTC alarm value.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   nAlarm     New alarm value to set.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * Writes the 32-bit RTC alarm comparator with the value provided by \a Alarm.
+ *
+ * Honours the safe write mode if set.  Otherwise, it is the application's responsibility to
+ * synchronize any multiple writes to the same register.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_GetAlarm().
+ * @sa        adi_rtc_EnableAlarm().
+ * @sa        adi_rtc_GetWritePendStatus().
+ * @sa        adi_rtc_SynchronizeAllWrites().
+ */
+ADI_RTC_RESULT adi_rtc_SetAlarm (ADI_RTC_HANDLE const  hDevice, uint32_t nAlarm)
+{
+   ADI_RTC_DEVICE *pDevice = hDevice;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+
+    /* Wait till previously posted write to Alram Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
+
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* RTC hardware insures paired write, so no need to disable interrupts */
+    pDevice->pRTCRegs->ALM0 = (uint16_t)nAlarm;
+    pDevice->pRTCRegs->ALM1 = (uint16_t)(nAlarm >> 16);
+    pDevice->pRTCRegs->ALM2 = 0u;
+    ADI_EXIT_CRITICAL_REGION();
+    
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1))    
+
+    return ADI_RTC_SUCCESS;
+}
+
+/*!
+ * @brief  Set Prescale. This is  power of 2 division factor for the RTC base clock.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   nPreScale  Prescale value to be set. if "nPreScale" is 5, RTC base clock is
+                           divided by 32.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_GetAlarm().
+ * @sa        adi_rtc_EnableAlarm().
+ * @sa        adi_rtc_GetWritePendStatus().
+ * @sa        adi_rtc_SynchronizeAllWrites().
+ */
+ADI_RTC_RESULT adi_rtc_SetPreScale(ADI_RTC_HANDLE const  hDevice, uint8_t nPreScale )
+{
+   ADI_RTC_DEVICE *pDevice = hDevice;
+   uint16_t nTemp;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+    /* Pre scale is invalid for RTC0 */
+    if(pDevice->pRTCRegs == pADI_RTC0)
+    {
+        return(ADI_RTC_OPERATION_NOT_ALLOWED);
+    }
+#endif
+    PEND_BEFORE_WRITE(SR2,BITM_RTC_SR2_WPNDCR1MIR)
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* RTC hardware insures paired write, so no need to disable interrupts */
+    /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/
+    nTemp = pDevice->pRTCRegs->CR1 & (uint16_t)~BITM_RTC_CR1_PRESCALE2EXP;
+    nTemp |= (uint16_t)((uint16_t)nPreScale << BITP_RTC_CR1_PRESCALE2EXP);
+    pDevice->pRTCRegs->CR1 = nTemp;
+    ADI_EXIT_CRITICAL_REGION();
+    
+    SYNC_AFTER_WRITE(SR2,BITM_RTC_SR2_WSYNCCR1MIR)   
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Set the pre-scale. This is  power of 2 division factor for the RTC base clock.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   nPeriod    Periodic, modulo-60 alarm time in pre-scaled RTC time units beyond a modulo-60 boundary.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ *  @note     This API helps  the CPU to position a periodic (repeating) alarm interrupt from the RTC at any integer number of pre-scaled RTC time units from a modulo-60 boundary (roll-over event) of the value of count.
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_GetAlarm().
+ * @sa        adi_rtc_EnableAlarm().
+ * @sa        adi_rtc_GetWritePendStatus().
+ * @sa        adi_rtc_SynchronizeAllWrites().
+ */
+ADI_RTC_RESULT adi_rtc_SetMod60AlarmPeriod(ADI_RTC_HANDLE const hDevice, uint8_t nPeriod )
+{
+   ADI_RTC_DEVICE *pDevice = hDevice;
+   uint16_t nTemp;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+
+    /* Mod60 Alarm is valid only in RTC-1 */
+    if(pDevice->pRTCRegs == pADI_RTC0)
+    {
+        return(ADI_RTC_OPERATION_NOT_ALLOWED);
+    }
+
+#endif
+
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
+
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* RTC hardware insures paired write, so no need to disable interrupts */
+    /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/
+    nTemp = pDevice->pRTCRegs->CR0 & BITM_RTC_CR0_MOD60ALM;
+    nTemp |= (uint16_t)((uint16_t)nPeriod << BITP_RTC_CR0_MOD60ALM);
+    pDevice->pRTCRegs->CR0 = nTemp;
+    ADI_EXIT_CRITICAL_REGION();
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)    
+
+    return ADI_RTC_SUCCESS;
+}
+/*!
+ * @brief  Set a new RTC alarm value with fractional value.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   fAlarm     New alarm value to set.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * Writes the 32-bit RTC alarm comparator with the value provided by \a Alarm.
+ *
+ * Honours the safe write mode if set.  Otherwise, it is the application's responsibility to
+ * synchronize any multiple writes to the same register.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_GetAlarm().
+ * @sa        adi_rtc_EnableAlarm().
+ * @sa        adi_rtc_GetWritePendStatus().
+ * @sa        adi_rtc_SynchronizeAllWrites().
+ */
+ADI_RTC_RESULT adi_rtc_SetAlarmEx(ADI_RTC_HANDLE const hDevice, float fAlarm)
+{
+   ADI_RTC_DEVICE *pDevice = hDevice;
+   uint32_t nAlarm = (uint32_t)fAlarm,nTemp;
+   uint16_t nPreScale;
+   float fFraction;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+    /* Only 1Hz clocking is supported in RTC-0.So no fractional Alarm. */
+    if(pDevice->pRTCRegs == pADI_RTC0)
+    {
+        return(ADI_RTC_OPERATION_NOT_ALLOWED);
+    }
+
+#endif
+
+    /* Wait till previously posted write to Alarm Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1))
+    nPreScale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP;
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* RTC hardware insures paired write, so no need to disable interrupts */
+    /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/
+    pDevice->pRTCRegs->ALM0 = (uint16_t)nAlarm;
+    pDevice->pRTCRegs->ALM1 = (uint16_t)(nAlarm >> 16);
+    nTemp = 1lu<<nPreScale;
+    fFraction = (fAlarm - (float)nAlarm) *(float)(nTemp);
+    pDevice->pRTCRegs->ALM2 = (uint16_t)(fFraction);
+    ADI_EXIT_CRITICAL_REGION();
+    /* Wait till  write to Alarm Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1))    
+
+    return ADI_RTC_SUCCESS;
+}
+
+/*!
+ * @brief  Set a new RTC control register value.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   eRegister  Specify which register need to be initialized.
+ * @param[in]   Control    New control register value to set.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * Writes the 16-bit RTC control register with the value provided by \a Control.
+ *
+ * Honours the safe write mode if set.  Otherwise, it is the application's responsibility to
+ * synchronize any multiple writes to the same register.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_GetControlRegister().
+ * @sa        adi_rtc_GetWritePendStatus().
+ * @sa        adi_rtc_SynchronizeAllWrites().
+ */
+ADI_RTC_RESULT adi_rtc_SetControlRegister(ADI_RTC_HANDLE const hDevice,ADI_RTC_CONTROL_REGISTER eRegister, uint32_t Control)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0)
+
+     switch(eRegister)
+     {
+     case ADI_RTC_CONTROL_REGISTER_0:
+          pDevice->pRTCRegs->CR0 = (uint16_t)Control;
+         break;
+     case ADI_RTC_CONTROL_REGISTER_1:
+         pDevice->pRTCRegs->CR1 = (uint16_t)Control;
+         break;
+     default:
+         return(ADI_RTC_FAILURE);
+     }
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0)    
+    
+    return ADI_RTC_SUCCESS;
+
+}
+
+/*!
+ * @brief      Registers a Callback function with the RTC device driver. The registered call
+ *              back function will be called when an event is detected.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param [in]  pfCallback  Function pointer to Callback function. Passing a NULL pointer will
+ *                          unregister the call back function.
+ *
+ * @param [in]  pCBparam    Call back function parameter.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS              Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * @sa        adi_rtc_Open().
+ */
+ADI_RTC_RESULT adi_rtc_RegisterCallback(
+               ADI_RTC_HANDLE const  hDevice,
+               ADI_CALLBACK   const   pfCallback,
+               void        *const     pCBparam
+               )
+
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+
+#if (ADI_RTC_CFG_ENABLE_SAFE_WRITE == 1)
+    /* pause on pending writes to CR to avoid data loss */
+        while((pDevice->pRTCRegs->SR1 & (uint32_t)ADI_RTC_WRITE_STATUS_CONTROL0)!=0u)
+        {
+        }
+#endif
+    /* Store the address of the callback function */
+    pDevice->pfCallback =  pfCallback;
+    /* Store the call back parameter */
+    pDevice->pCBParam    =  pCBparam;
+
+    return ADI_RTC_SUCCESS;
+
+}
+
+/*!
+ * @brief  Set a new RTC count value.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   nCount     New count value to set.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * Writes the main 32-bit RTC counter with the value provided by \a Count.
+ *
+ * Honours the safe write mode if set.  Otherwise, it is the application's responsibility to
+ * synchronize any multiple writes to the same register.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_SetCount().
+ * @sa        adi_rtc_GetWritePendStatus().
+ * @sa        adi_rtc_SynchronizeAllWrites().
+ */
+ADI_RTC_RESULT adi_rtc_SetCount (ADI_RTC_HANDLE const hDevice, uint32_t nCount)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+
+#if (ADI_RTC_CFG_ENABLE_SAFE_WRITE == 1)
+    /* pause on pending writes to CR to avoid data loss */
+        while((pDevice->pRTCRegs->SR1 & (uint32_t)(ADI_RTC_WRITE_STATUS_COUNT0 | ADI_RTC_WRITE_STATUS_COUNT1)) !=0u)
+        {
+
+        }
+#endif
+
+    /* Wait till previously posted write to count Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1))
+
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    /* RTC hardware insures paired write, so no need to disable interrupts */
+    pDevice->pRTCRegs->CNT0 = (uint16_t)nCount;
+    pDevice->pRTCRegs->CNT1 = (uint16_t)(nCount >> 16);
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* Wait till  write to count Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCCNT0|BITM_RTC_SR0_WSYNCCNT1))    
+
+    return ADI_RTC_SUCCESS;
+}
+
+
+/*!
+ * @brief  Set an RTC gateway command.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ * @param[in]   Command    Gateway command value.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *
+ * Writes the 16-bit RTC gateway register with the command provided by \a Command.
+ *
+ * The gateway register is used to force the RTC to perform some urgent action.
+ *
+ * Currently, only the #ADI_RTC_GATEWAY_FLUSH command is defined, which will cancel all
+ * RTC register write transactions, both pending and executing.  It is intended to truncate
+ * all core interactions in preparation for an imminent power loss when the RTC power
+ * isolation barrier will be activated.
+ *
+ * @sa        adi_rtc_Open().
+ */
+ADI_RTC_RESULT adi_rtc_SetGateway(ADI_RTC_HANDLE const hDevice, uint16_t Command)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+#endif
+    /* set the command */
+    pDevice->pRTCRegs->GWY = Command;
+    return ADI_RTC_SUCCESS;
+}
+
+
+
+/*!
+ * @brief  Set a new RTC trim value.
+ *
+ * @param[in]   hDevice      Device handle obtained from adi_rtc_Open().
+ * @param[in]   eInterval    Specify the trimming interval and will always in the range of (2^2 to S^17 pre-scaled RTC clock ).
+ * @param[in]   eTrimValue   Specify the trimming value.
+ * @param[in]   eOperation   Specify the operation(Add or subtract) need to be performed for trimming.
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]      Invalid device handle parameter.
+ *                - #ADI_RTC_INVALID_PARAM [D]       Input parameter out of range.
+ *
+ * The RTC hardware has the ability to automatically trim the clock to compensate for variations
+ * in oscillator tolerance .   Automatic trimming is enabled with the #adi_rtc_EnableTrim() API.
+ *
+ * @note Alarms are not affected by automatic trim operations.
+ *
+ * @note The trim boundary (interval) alignment is reset when new trim values are written.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_EnableTrim().
+ * @sa        adi_rtc_GetTrim().
+ */
+ADI_RTC_RESULT adi_rtc_SetTrim(ADI_RTC_HANDLE const hDevice,  ADI_RTC_TRIM_INTERVAL eInterval, ADI_RTC_TRIM_VALUE  eTrimValue, ADI_RTC_TRIM_POLARITY eOperation)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+    uint32_t trm = (uint32_t)eInterval | (uint32_t)eTrimValue | (uint32_t)eOperation;
+
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+
+#endif
+
+    /* Wait till previously posted write to Control Register to complete */ 
+    PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDTRM)
+
+    pDevice->pRTCRegs->TRM = (uint16_t)trm;
+    
+    /* Wait till  write to Control Register to take effect */    
+    SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCTRM)    
+
+    return ADI_RTC_SUCCESS;
+}
+
+
+/*************************************************************************************************
+**************************************************************************************************
+************************************   SYNCHRONIZATION API   *************************************
+**************************************************************************************************
+*************************************************************************************************/
+
+
+/*!
+ * @brief  Force synchronization of all pending writes.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_rtc_Open().
+ *
+ * @return      Status
+ *                - #ADI_RTC_SUCCESS                 Call completed successfully.
+ *                - #ADI_RTC_INVALID_HANDLE [D]     Invalid device handle parameter.
+ *
+ * Blocking call to coerce all outstanding posted RTC register writes to fully flush and synchronize.
+ *
+ * @sa        adi_rtc_Open().
+ * @sa        adi_rtc_GetWritePendStatus().
+ * @sa        adi_rtc_GetWriteSyncStatus().
+*/
+ADI_RTC_RESULT adi_rtc_SynchronizeAllWrites (ADI_RTC_HANDLE const hDevice)
+{
+    ADI_RTC_DEVICE *pDevice = hDevice;
+#ifdef ADI_DEBUG
+    ADI_RTC_RESULT eResult;
+    if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS)
+    {
+        return eResult;
+    }
+
+#endif
+
+    /* forced block until all SYNC bits are set (ignore bSafe) */
+    while (ADI_RTC_WRITE_STATUS_MASK != (pDevice->pRTCRegs->SR0 & ADI_RTC_WRITE_STATUS_MASK))
+    {
+
+    }
+
+    return ADI_RTC_SUCCESS;
+}
+
+
+/*! \cond PRIVATE */
+
+/*
+ * @brief       Initializes the device  using static configuration 
+ *
+ * @param[in]   pDevice    Pointer to RTC device .
+                pConfig    Pointer to static configuration device structure.
+ *
+*/
+
+static void rtc_init(ADI_RTC_DEVICE *pDevice,ADI_RTC_CONFIG *pConfig)
+{
+  
+  /* FIXME - static init is even more now */
+  
+    /* Control register -0 which controls all main stream activity of RTC0 */
+    pDevice->pRTCRegs->CR0  =   pConfig->CR0;
+    /* Control register -1  which is  granularity of RTC control register */    
+    pDevice->pRTCRegs->CR1  =   pConfig->CR1;
+    /*CNT0 contains the lower 16 bits of the RTC counter  */    
+    pDevice->pRTCRegs->CNT0 =   pConfig->CNT0;
+    /*CNT1 contains the lower 16 bits of the RTC counter  */        
+    pDevice->pRTCRegs->CNT1 =   pConfig->CNT1;
+    /* ALM0 contains the lower 16 bits of the Alarm register */
+    pDevice->pRTCRegs->ALM0 =   pConfig->ALM0;
+    /* ALM1 contains the upper  16 bits of the Alarm register */
+    pDevice->pRTCRegs->ALM1 =   pConfig->ALM1;
+     /* ALM1 contains the fractional part of  the Alarm register */
+    pDevice->pRTCRegs->ALM2 =   pConfig->ALM2;
+    /* Set Input capture/sensor strobe registers only for RTC1 */
+    if(pDevice->pRTCRegs == pADI_RTC1)
+    {
+        pDevice->pRTCRegs->CR2IC  =   pConfig->CR2IC;
+        pDevice->pRTCRegs->CR3SS  =   pConfig->CR3SS;
+        pDevice->pRTCRegs->CR4SS  =   pConfig->CR4SS;
+        pDevice->pRTCRegs->SSMSK  =   pConfig->SSMSK;
+        pDevice->pRTCRegs->SS1    =   pConfig->SS1;
+        pDevice->pRTCRegs->CR5SSS =   pConfig->CR5SSS;
+        pDevice->pRTCRegs->CR6SSS =   pConfig->CR6SSS;
+        pDevice->pRTCRegs->CR7SSS =   pConfig->CR7SSS;
+        pDevice->pRTCRegs->GPMUX0 =   pConfig->GPMUX0;
+        pDevice->pRTCRegs->GPMUX1 =   pConfig->GPMUX1;
+    }
+}
+
+
+
+/*! @brief  RTC device driver interrupt handler.  Overrides weakly-bound default interrupt handler in <Device>_startup.c. */
+void RTC0_Int_Handler(void)
+{
+    ISR_PROLOG();    
+    uint16_t nIntSrc0, nIntSrc2, nIntSrc3;
+    uint32_t fired = 0u, enables = 0u;
+    ADI_RTC_DEVICE *pDevice = aRTCDeviceInfo[0].hDevice;
+
+    /* determine qualified interrupt source(s) */
+    /* need to test each interrupt source and whether it is enabled before notifying */
+    /* because each source is latched regardless of whether it is enabled or not :-( */
+
+    /* CR0   SR0 */
+    enables = (uint32_t)pDevice->pRTCRegs->CR0  & ADI_RTC_INT_ENA_MASK_CR0;
+    nIntSrc0 = pDevice->pRTCRegs->SR0 & ADI_RTC_INT_SOURCE_MASK_SR0;
+    if( nIntSrc0 && enables )
+    {
+      if( (enables & BITM_RTC_CR0_MOD60ALMEN) && (nIntSrc0 & BITM_RTC_SR0_MOD60ALMINT))
+      {
+        fired |= ADI_RTC_MOD60ALM_INT;
+      }
+      if( (enables & BITM_RTC_CR0_ALMINTEN) && (nIntSrc0 & BITM_RTC_SR0_ALMINT))
+      {
+        fired |= ADI_RTC_ALARM_INT;
+      }
+      if( (enables & BITM_RTC_CR0_ISOINTEN) && (nIntSrc0 & BITM_RTC_SR0_ISOINT))
+      {
+        fired |= ADI_RTC_ISO_DONE_INT;
+      }
+      if( (enables & BITM_RTC_CR0_WPNDINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDINT))
+      {
+        fired |= ADI_RTC_WRITE_PEND_INT;
+      }
+      if( (enables & BITM_RTC_CR0_WSYNCINTEN) && (nIntSrc0 & BITM_RTC_SR0_WSYNCINT))
+      {
+        fired |= ADI_RTC_WRITE_SYNC_INT;
+      }
+      if( (enables & BITM_RTC_CR0_WPNDERRINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDERRINT))
+      {
+        fired |= ADI_RTC_WRITE_PENDERR_INT;
+      }
+    }
+      
+    /* CR1  SR2 */
+    enables = (uint32_t)pDevice->pRTCRegs->CR1  & ADI_RTC_INT_ENA_MASK_CR1;
+    nIntSrc2 = pDevice->pRTCRegs->SR2 & ADI_RTC_INT_SOURCE_MASK_SR2;
+    if( nIntSrc2 && enables )
+    {
+      if( (enables & BITM_RTC_CR1_CNTMOD60ROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTMOD60ROLLINT))
+      {
+        fired |= ADI_RTC_MOD60_ROLLOVER_INT;
+      }
+      if( (enables & BITM_RTC_CR1_CNTROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTROLLINT))
+      {
+        fired |= ADI_RTC_COUNT_ROLLOVER_INT;
+      }
+      if( (enables & BITM_RTC_CR1_TRMINTEN) && (nIntSrc2 & BITM_RTC_SR2_TRMINT))
+      {
+        fired |= ADI_RTC_TRIM_INT;
+      }
+      if( (enables & BITM_RTC_CR1_PSINTEN) && (nIntSrc2 & BITM_RTC_SR2_PSINT))
+      {
+        fired |= ADI_RTC_PSI_INT;
+      }
+      if( (enables & BITM_RTC_CR1_CNTINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTINT))
+      {
+        fired |= ADI_RTC_COUNT_INT;
+      }
+    }
+    
+    /* CR3OC, CR2IC  SR3*/
+    enables = pDevice->pRTCRegs->CR3SS  &  (uint16_t)ADI_RTC_INT_ENA_MASK_CR3SS;
+    nIntSrc3 = pDevice->pRTCRegs->SR3 & ADI_RTC_SR3_IRQ_STATUS_MASK;
+    if( nIntSrc3 && enables )
+    {
+      if( (enables & BITM_RTC_CR3SS_SS4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4IRQ))
+      {
+        fired |= ADI_RTC_SENSOR_STROBE_CH4_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3IRQ))
+      {
+        fired |= ADI_RTC_SENSOR_STROBE_CH3_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2IRQ))
+      {
+        fired |= ADI_RTC_SENSOR_STROBE_CH2_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS1IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1IRQ))
+      {
+        fired |= ADI_RTC_SENSOR_STROBE_CH1_INT;
+      }
+      
+      if( (enables & BITM_RTC_CR3SS_SS4FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4FEIRQ))
+      {
+        fired |= ADI_RTC_RTCSS4_FE_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS3FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2FEIRQ))
+      {
+        fired |= ADI_RTC_RTCSS3_FE_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS2FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3FEIRQ))
+      {
+        fired |= ADI_RTC_RTCSS2_FE_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS1FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1FEIRQ))
+      {
+        fired |= ADI_RTC_RTCSS1_FE_INT;
+      }
+   }
+   enables = pDevice->pRTCRegs->CR3SS  & (uint16_t)ADI_RTC_INT_ENA_MASK_CR2IC;
+   if( nIntSrc3 && enables )
+   {
+      if( (enables & BITM_RTC_CR2IC_IC4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC4IRQ))
+      {
+        fired |= ADI_RTC_INPUT_CAPTURE_CH4_INT;
+      }
+      if( (enables & BITM_RTC_CR2IC_IC3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC3IRQ))
+      {
+        fired |= ADI_RTC_INPUT_CAPTURE_CH3_INT;
+      }
+      if( (enables & BITM_RTC_CR2IC_IC2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC2IRQ))
+      {
+        fired |= ADI_RTC_INPUT_CAPTURE_CH2_INT;
+      }
+      if( (enables & BITM_RTC_CR2IC_IC0IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC0IRQ))
+      {
+        fired |= ADI_RTC_INPUT_CAPTURE_CH0_INT;
+      }
+   }
+   
+    
+    if (pDevice->pfCallback != NULL) {
+
+        /* forward to the user if he is watching this interrupt */
+        /* pass the "fired" value as the event.  argument param is not used */
+        if ( fired)
+        {
+            pDevice->pfCallback (pDevice->pCBParam, fired, NULL);
+        }
+    }
+    
+    /* Write 1 to clear the interrupts */ 
+    pDevice->pRTCRegs->SR0 |= nIntSrc0;
+    pDevice->pRTCRegs->SR2 |= nIntSrc2;
+    pDevice->pRTCRegs->SR3 |= nIntSrc3;
+    ISR_EPILOG();        
+}
+
+/*! @brief  RTC device driver interrupt handler.  Overrides weakly-bound default interrupt handler in <Device>_startup.c. */
+void RTC1_Int_Handler(void)
+{
+    ISR_PROLOG();    
+    uint16_t nIntSrc0, nIntSrc2, nIntSrc3;
+    uint32_t fired = 0u, enables = 0u;
+    ADI_RTC_DEVICE *pDevice = aRTCDeviceInfo[1].hDevice;
+
+    /* determine qualified interrupt source(s) */
+    /* need to test each interrupt source and whether it is enabled before notifying */
+    /* because each source is latched regardless of whether it is enabled or not :-( */
+
+    /* CR0   SR0 */
+    enables = (uint32_t)pDevice->pRTCRegs->CR0  & ADI_RTC_INT_ENA_MASK_CR0;
+    nIntSrc0 = pDevice->pRTCRegs->SR0 & ADI_RTC_INT_SOURCE_MASK_SR0;
+    if( nIntSrc0 && enables )
+    {
+      if( (enables & BITM_RTC_CR0_MOD60ALMEN) && (nIntSrc0 & BITM_RTC_SR0_MOD60ALMINT))
+      {
+        fired |= ADI_RTC_MOD60ALM_INT;
+      }
+      if( (enables & BITM_RTC_CR0_ALMINTEN) && (nIntSrc0 & BITM_RTC_SR0_ALMINT))
+      {
+        fired |= ADI_RTC_ALARM_INT;
+      }
+      if( (enables & BITM_RTC_CR0_ISOINTEN) && (nIntSrc0 & BITM_RTC_SR0_ISOINT))
+      {
+        fired |= ADI_RTC_ISO_DONE_INT;
+      }
+      if( (enables & BITM_RTC_CR0_WPNDINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDINT))
+      {
+        fired |= ADI_RTC_WRITE_PEND_INT;
+      }
+      if( (enables & BITM_RTC_CR0_WSYNCINTEN) && (nIntSrc0 & BITM_RTC_SR0_WSYNCINT))
+      {
+        fired |= ADI_RTC_WRITE_SYNC_INT;
+      }
+      if( (enables & BITM_RTC_CR0_WPNDERRINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDERRINT))
+      {
+        fired |= ADI_RTC_WRITE_PENDERR_INT;
+      }
+    }
+      
+    /* CR1  SR2 */
+    enables = (uint32_t)pDevice->pRTCRegs->CR1  & ADI_RTC_INT_ENA_MASK_CR1;
+    nIntSrc2 = pDevice->pRTCRegs->SR2 & ADI_RTC_INT_SOURCE_MASK_SR2;
+    if( nIntSrc2 && enables )
+    {
+      if( (enables & BITM_RTC_CR1_CNTMOD60ROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTMOD60ROLLINT))
+      {
+        fired |= ADI_RTC_MOD60_ROLLOVER_INT;
+      }
+      if( (enables & BITM_RTC_CR1_CNTROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTROLLINT))
+      {
+        fired |= ADI_RTC_COUNT_ROLLOVER_INT;
+      }
+      if( (enables & BITM_RTC_CR1_TRMINTEN) && (nIntSrc2 & BITM_RTC_SR2_TRMINT))
+      {
+        fired |= ADI_RTC_TRIM_INT;
+      }
+      if( (enables & BITM_RTC_CR1_PSINTEN) && (nIntSrc2 & BITM_RTC_SR2_PSINT))
+      {
+        fired |= ADI_RTC_PSI_INT;
+      }
+      if( (enables & BITM_RTC_CR1_CNTINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTINT))
+      {
+        fired |= ADI_RTC_COUNT_INT;
+      }
+    }
+    
+    /* CR3OC, CR2IC  SR3*/
+    enables = pDevice->pRTCRegs->CR3SS  & (uint32_t)ADI_RTC_INT_ENA_MASK_CR3SS;
+    nIntSrc3 = pDevice->pRTCRegs->SR3 & ADI_RTC_SR3_IRQ_STATUS_MASK;
+    if( nIntSrc3 && enables )
+    {
+      if( (enables & BITM_RTC_CR3SS_SS4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4IRQ))
+      {
+        fired |= ADI_RTC_SENSOR_STROBE_CH4_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3IRQ))
+      {
+        fired |= ADI_RTC_SENSOR_STROBE_CH3_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2IRQ))
+      {
+        fired |= ADI_RTC_SENSOR_STROBE_CH2_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS1IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1IRQ))
+      {
+        fired |= ADI_RTC_SENSOR_STROBE_CH1_INT;
+      }
+      
+      if( (enables & BITM_RTC_CR3SS_SS4FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4FEIRQ))
+      {
+        fired |= ADI_RTC_RTCSS4_FE_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS3FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2FEIRQ))
+      {
+        fired |= ADI_RTC_RTCSS3_FE_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS2FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3FEIRQ))
+      {
+        fired |= ADI_RTC_RTCSS2_FE_INT;
+      }
+      if( (enables & BITM_RTC_CR3SS_SS1FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1FEIRQ))
+      {
+        fired |= ADI_RTC_RTCSS1_FE_INT;
+      }
+   }
+   enables = pDevice->pRTCRegs->CR2IC  & (uint32_t)ADI_RTC_INT_ENA_MASK_CR2IC;
+   if( nIntSrc3 && enables )
+   {
+      if( (enables & BITM_RTC_CR2IC_IC4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC4IRQ))
+      {
+        fired |= ADI_RTC_INPUT_CAPTURE_CH4_INT;
+      }
+      if( (enables & BITM_RTC_CR2IC_IC3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC3IRQ))
+      {
+        fired |= ADI_RTC_INPUT_CAPTURE_CH3_INT;
+      }
+      if( (enables & BITM_RTC_CR2IC_IC2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC2IRQ))
+      {
+        fired |= ADI_RTC_INPUT_CAPTURE_CH2_INT;
+      }
+      if( (enables & BITM_RTC_CR2IC_IC0IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC0IRQ))
+      {
+        fired |= ADI_RTC_INPUT_CAPTURE_CH0_INT;
+      }
+   }
+   
+    if (pDevice->pfCallback != NULL) {
+
+        /* forward to the user if he is watching this interrupt */
+        /* pass the "fired" value as the event.  argument param is not used */
+        if ( fired)
+        {
+            pDevice->pfCallback (pDevice->pCBParam, fired, NULL);
+        }
+    }
+    
+    /* Write 1 to clear the interrupts */ 
+    pDevice->pRTCRegs->SR0 |= nIntSrc0;
+    pDevice->pRTCRegs->SR2 |= nIntSrc2;
+    pDevice->pRTCRegs->SR3 |= nIntSrc3;
+    
+    ISR_EPILOG();        
+}
+
+/*! \endcond */
+
+/* @} */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_data.c
new file mode 100755
index 00000000000..624b8d30309
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_data.c
@@ -0,0 +1,192 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_rtc_data.c
+ * @brief:   rtc device data file
+ * @version: $Revision: 34933 $
+ * @date:    $Date: 2016-06-28 07:11:25 -0400 (Tue, 28 Jun 2016) $
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/*! \cond PRIVATE */
+#ifndef ADI_RTC_DATA_C_
+#define ADI_RTC_DATA_C_
+
+#include <stdlib.h>
+#include <adi_processor.h>
+#include "adi_rtc_def.h"
+
+
+static ADI_RTC_DEVICE_INFO aRTCDeviceInfo[ADI_RTC_NUM_INSTANCE] =
+{
+     {
+	(ADI_RTC_TypeDef *)pADI_RTC0,RTC0_EVT_IRQn, NULL
+     },
+     {
+	(ADI_RTC_TypeDef *)pADI_RTC1,RTC1_EVT_IRQn,NULL,
+     }
+};
+
+
+static ADI_RTC_CONFIG aRTCConfig[ADI_RTC_NUM_INSTANCE] =
+{
+  {
+    /* CR0 */
+   RTC0_CFG_ENABLE_ALARM                    <<  BITP_RTC_CR0_ALMEN         |
+   RTC0_CFG_ENABLE_ALARM_INTERRUPT          <<  BITP_RTC_CR0_ALMINTEN      |
+   RTC0_CFG_ENABLE_TRIM                      <<  BITP_RTC_CR0_TRMEN         |
+   RTC0_CFG_ENABLE_PENDERROR_INTERRUPT       <<  BITP_RTC_CR0_WPNDERRINTEN  |
+   RTC0_CFG_ENABLE_WSYNC_INTERRUPT           <<  BITP_RTC_CR0_WSYNCINTEN    |
+   RTC0_CFG_ENABLE_WRITEPEND_INTERRUPT       <<  BITP_RTC_CR0_WPNDINTEN ,
+   /* CR1 */
+   0,
+   /* CNT0 */
+   RTC0_CFG_COUNT_VALUE_0,
+   /* CNT1 */
+   RTC0_CFG_COUNT_VALUE_1,
+   /* ALM0 */
+   RTC0_CFG_ALARM_VALUE_0,
+   /* ALM1 */
+   RTC0_CFG_ALARM_VALUE_1,
+   /* ALM2 */
+   0,
+   /* TRIM */
+   RTC0_CFG_POW2_TRIM_INTERVAL               << BITP_RTC_TRM_IVL2EXPMIN   |
+   RTC0_CFG_TRIM_INTERVAL                    << BITP_RTC_TRM_IVL          |
+   RTC0_CFG_TRIM_OPERATION                   << BITP_RTC_TRM_ADD          |
+   RTC0_CFG_TRIM_VALUE                       << BITP_RTC_TRM_VALUE,
+   0,     /* CR2IC */
+   0,     /* CR3SS */
+   0,     /* CR4SS */
+   0,     /* SSMSK */
+   0,     /* SS1 */
+   0,     /* CR5SSS */
+   0,     /* CR6SSS */
+   0,     /* CR7SSS */
+   0,     /* GPMUX0 */
+   0     /* GPMUX1 */
+
+  },
+  /* RTC-1 */
+  {
+    /* CR0 */
+   RTC1_CFG_ENABLE_ALARM                    <<  BITP_RTC_CR0_ALMEN         |
+   RTC1_CFG_ENABLE_ALARM_INTERRUPT          <<  BITP_RTC_CR0_ALMINTEN      |
+   RTC1_CFG_ENABLE_TRIM                      <<  BITP_RTC_CR0_TRMEN         |
+   RTC1_CFG_ENABLE_MOD60_ALARM              <<  BITP_RTC_CR0_MOD60ALMEN    |
+   RTC1_CFG_ENABLE_MOD60_ALARM_PERIOD       <<  BITP_RTC_CR0_MOD60ALM      |
+   RTC1_CFG_ENABLE_MOD60_ALARM_INTERRUPT    <<  BITP_RTC_CR0_MOD60ALMINTEN |
+   RTC1_CFG_ENABLE_ISO_INTERRUPT             <<  BITP_RTC_CR0_ISOINTEN      |
+   RTC1_CFG_ENABLE_PENDERROR_INTERRUPT       <<  BITP_RTC_CR0_WPNDERRINTEN  |
+   RTC1_CFG_ENABLE_WSYNC_INTERRUPT           <<  BITP_RTC_CR0_WSYNCINTEN    |
+   RTC1_CFG_ENABLE_WRITEPEND_INTERRUPT       <<  BITP_RTC_CR0_WPNDINTEN ,
+    /* CR1 */
+   RTC1_CFG_ENABLE_COUNT_INTERRUPT           <<  BITP_RTC_CR1_CNTINTEN       |
+   RTC1_CFG_ENABLE_MOD1_COUNT_INTERRUPT      <<  BITP_RTC_CR1_PSINTEN        |
+   RTC1_CFG_ENABLE_TRIM_INTERRUPT            <<  BITP_RTC_CR1_TRMINTEN    |
+   RTC1_CFG_CNT_MOD60_ROLLLOVER_INTERRUPT    <<  BITP_RTC_CR1_CNTROLLINTEN   |
+   RTC1_CFG_PRESCALE                         <<  BITP_RTC_CR1_PRESCALE2EXP   |
+   RTC1_CFG_CNT_ROLLLOVER_INTERRUPT          <<  BITP_RTC_CR1_CNTMOD60ROLLINTEN ,
+   /* CNT0 */
+   RTC1_CFG_COUNT_VALUE_0,
+   /* CNT1 */
+   RTC1_CFG_COUNT_VALUE_1,
+
+   /* ALM[123] */
+   RTC1_CFG_ALARM_VALUE_0,
+   RTC1_CFG_ALARM_VALUE_1,
+   RTC1_CFG_ALARM_VALUE_2,
+
+   /* TRIM */
+   RTC1_CFG_POW2_TRIM_INTERVAL               << BITP_RTC_TRM_IVL2EXPMIN  |
+   RTC1_CFG_TRIM_INTERVAL                    << BITP_RTC_TRM_IVL         |
+   RTC1_CFG_TRIM_OPERATION                   << BITP_RTC_TRM_ADD         |
+   RTC1_CFG_TRIM_VALUE                       << BITP_RTC_TRM_VALUE,
+
+   /* CR2IC */
+   RTC1_CFG_IC0_ENABLE                       <<  BITP_RTC_CR2IC_IC0EN    |
+   RTC1_CFG_IC2_ENABLE                       <<  BITP_RTC_CR2IC_IC2EN    |
+   RTC1_CFG_IC3_ENABLE                       <<  BITP_RTC_CR2IC_IC3EN    |
+   RTC1_CFG_IC4_ENABLE                       <<  BITP_RTC_CR2IC_IC4EN    |
+   RTC1_CFG_IC0_INT_ENABLE                   <<  BITP_RTC_CR2IC_IC0IRQEN |
+   RTC1_CFG_IC0_INT_ENABLE                   <<  BITP_RTC_CR2IC_IC2IRQEN |
+   RTC1_CFG_IC0_INT_ENABLE                   <<  BITP_RTC_CR2IC_IC3IRQEN |
+   RTC1_CFG_IC0_INT_ENABLE                   <<  BITP_RTC_CR2IC_IC4IRQEN |
+   RTC1_CFG_IC0_EDGE_POLARITY                <<  BITP_RTC_CR2IC_IC0LH    |
+   RTC1_CFG_IC2_EDGE_POLARITY                <<  BITP_RTC_CR2IC_IC2LH    |
+   RTC1_CFG_IC3_EDGE_POLARITY                <<  BITP_RTC_CR2IC_IC3LH    |
+   RTC1_CFG_IC4_EDGE_POLARITY                <<  BITP_RTC_CR2IC_IC4LH    |
+   RTC1_CFG_IC_OVER_WRITE_ENABLE             <<  BITP_RTC_CR2IC_ICOWUSEN,
+
+   /* CR3SS */
+   RTC1_CFG_SS1_ENABLE                       <<  BITP_RTC_CR3SS_SS1EN    |
+   RTC1_CFG_SS2_ENABLE                       <<  BITP_RTC_CR3SS_SS2EN    |
+   RTC1_CFG_SS3_ENABLE                       <<  BITP_RTC_CR3SS_SS3EN    |
+   RTC1_CFG_SS4_ENABLE                       <<  BITP_RTC_CR3SS_SS4EN    |
+   RTC1_CFG_SS1_INT_ENABLE                   <<  BITP_RTC_CR3SS_SS1IRQEN |
+   RTC1_CFG_SS2_INT_ENABLE                   <<  BITP_RTC_CR3SS_SS2IRQEN |
+   RTC1_CFG_SS3_INT_ENABLE                   <<  BITP_RTC_CR3SS_SS3IRQEN |
+   RTC1_CFG_SS4_INT_ENABLE                   <<  BITP_RTC_CR3SS_SS4IRQEN,
+
+   /* CR4SS */
+   RTC1_CFG_SS1_MASK_ENABLE                  <<  BITP_RTC_CR4SS_SS1MSKEN |
+   RTC1_CFG_SS2_MASK_ENABLE                  <<  BITP_RTC_CR4SS_SS2MSKEN |
+   RTC1_CFG_SS3_MASK_ENABLE                  <<  BITP_RTC_CR4SS_SS3MSKEN |
+   RTC1_CFG_SS4_MASK_ENABLE                  <<  BITP_RTC_CR4SS_SS4MSKEN |
+   RTC1_CFG_SS1_AUTO_RELOADING_ENABLE        <<  BITP_RTC_CR4SS_SS1ARLEN,
+
+   /* SSMSK */
+   RTC1_CFG_SS1_MASK_VALUE,
+
+   /* SS1 */
+   RTC1_CFG_SS1_AUTO_RELOAD_VALUE,
+
+   0,      /* CR5SSS */                      /* TODO: Add the following to the static configuration macros */
+   0,      /* CR6SSS */
+   0,      /* CR7SSS */
+   0x4688, /* GPMUX0 */
+   0x01F5, /* GPMUX1 */
+
+  }
+
+};
+
+#endif
+/*! \endcond */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_def.h
new file mode 100755
index 00000000000..a6fca0e37b5
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_def.h
@@ -0,0 +1,165 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_rtc_def.h
+ * @brief:   RTC def file
+ * @version: $Revision: 33205 $
+ * @date:    $Date: 2016-01-11 05:46:07 -0500 (Mon, 11 Jan 2016) $
+ *-----------------------------------------------------------------------------
+ *
+ * Copyright (c) 2010-2016 Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright notice,
+ *   this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ *   this list of conditions and the following disclaimer in the documentation
+ *   and/or other materials provided with the distribution.
+ * - Modified versions of the software must be conspicuously marked as such.
+ * - This software is licensed solely and exclusively for use with processors
+ *   manufactured by or for Analog Devices, Inc.
+ * - This software may not be combined or merged with other code in any manner
+ *   that would cause the software to become subject to terms and conditions
+ *   which differ from those listed here.
+ * - Neither the name of Analog Devices, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ * - The use of this software may or may not infringe the patent rights of one
+ *   or more patent holders.  This license does not release you from the
+ *   requirement that you obtain separate licenses from these patent holders
+ *   to use this software.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+ * PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef ADI_RTC_DEF_H__
+#define ADI_RTC_DEF_H__
+
+#include <drivers/rtc/adi_rtc.h>
+
+/*! \cond PRIVATE */
+#define ADI_RTC_NUM_INSTANCE 2u
+
+
+
+#define ADI_RTC_INT_ENA_MASK_CR0         0XF804u
+
+#define ADI_RTC_INT_ENA_MASK_CR1         0X1Fu
+
+#define ADI_RTC_INT_ENA_MASK_CR2IC       0xF41C
+#define ADI_RTC_INT_ENA_MASK_CR3SS       0x1FFE
+#define ADI_RTC_INT_ENA_MASK_CR4SS       0x0E0E
+#define ADI_RTC_INT_ENA_MASK_CR5SSS      0x0FFF
+
+#define ADI_RTC_INT_SOURCE_MASK_SR0      0x007Eu
+#define ADI_RTC_INT_SOURCE_MASK_SR2      0x001Fu
+
+#define ADI_RTC_WRITE_STATUS_MASK        0XCF8u
+#define ADI_RTC_SR2_IRQ_STATUS_MASK      0X1Fu
+#define ADI_RTC_SR3_IRQ_STATUS_MASK      0X1FFFu
+
+
+
+#define ADI_RTC_TRIM_MASK (BITM_RTC_TRM_VALUE | BITM_RTC_TRM_ADD|BITM_RTC_TRM_IVL | BITM_RTC_TRM_IVL2EXPMIN )
+
+#if (ADI_RTC_CFG_ENABLE_SAFE_WRITE == 1)
+    /* pause on pending writes to CR to avoid data loss */
+
+#ifdef __ICCARM__
+/*
+* Pm154 (rule 19.10): in the definition of a function-like macro, each instance
+*                     of a parameter shall be enclosed in parentheses
+*   Parameter use without parentheses needed for struct field name in register access macro.
+*/
+#pragma diag_suppress=Pm154
+#endif /* __ICCARM__ */
+
+#define  PEND_BEFORE_WRITE(reg,mask) while((pDevice->pRTCRegs->reg&(mask))!=0u)\
+        {\
+        }
+
+#define  SYNC_AFTER_WRITE(reg,mask) while((pDevice->pRTCRegs->reg&(mask))==0u)\
+        {\
+        }
+
+#ifdef __ICCARM__
+#pragma diag_default=Pm154
+#endif /* __ICCARM__ */
+
+#else
+    /* pause on pending writes to CR to avoid data loss */
+#define  PEND_BEFORE_WRITE(reg,mask)
+#define  SYNC_AFTER_WRITE(reg,mask)
+#endif
+
+/*
+ * The following is used for static configuration
+ */
+typedef struct
+{
+    uint16_t    CR0;             /*!< CR0 16 bit control register-0 value */
+    uint16_t    CR1;             /*!< CR1 16 bit control register-1 value */
+    uint16_t    CNT0;            /*!< CNT0 16 bit count register value */
+    uint16_t    CNT1;            /*!< CNT1 16 bit count register value */
+
+    uint16_t    ALM0;            /*!< ALM0 16 bit integer part of alarm value */
+    uint16_t    ALM1;            /*!< ALM1 16 bit integer part of alarm value */
+    uint16_t    ALM2;            /*!< ALM2 16 bit integer part of alarm value */
+    uint16_t    TRIM;              /*!< 16 bit trim register value */
+    uint16_t    CR2IC;           /*!< CR2IC 16 bit control (which controls the input capture ) register-2 value */
+    uint16_t    CR3SS;           /*!< CR3SS 16 bit control ( Controls enabling sensor strobe /IRQ etc )register-3 value */
+    uint16_t    CR4SS;           /*!< CR4SS 16 bit control ( controls Auto reload  and mask for sensor strobe  ) register-4 value */
+    uint16_t    SSMSK;           /*!< OCMSK Mask register for sensor strobe channel */
+    uint16_t    SS1;             /*!< 16 bit Auto reload value */
+
+    uint16_t    CR5SSS;         /*!< Configure Sensor Strobe Channel GPIO Sampling Register */
+    uint16_t    CR6SSS;         /*!< Configure Sensor Strobe Channel GPIO Sampling Register */
+    uint16_t    CR7SSS;         /*!< Configure Sensor Strobe Channel GPIO Sampling Register */
+    uint16_t    GPMUX0;         /*!< Control register for selecting a GPIO (pin) as data to be sampled by a Sensor Strobe  channel */
+    uint16_t    GPMUX1;         /*!< Control register for selecting a GPIO (pin) as data to be sampled by a Sensor Strobe  channel */
+}ADI_RTC_CONFIG;
+
+/* Device information structure */
+typedef struct _ADI_RTC_DEVICE_INFO
+{
+    volatile ADI_RTC_TypeDef  *pRTCRegs;   /* Base address of the  SPORT registers */
+    const IRQn_Type            eIRQn;      /* IRQn */
+    ADI_RTC_HANDLE             hDevice;    /* RTC handle */
+}ADI_RTC_DEVICE_INFO;
+
+/*! RTC driver instance data */
+typedef struct _ADI_RTC_DEVICE
+{
+    volatile ADI_RTC_TypeDef *pRTCRegs;    /* Pointer to RTC Memory Mapped Registers */
+
+    ADI_CALLBACK              pfCallback;  /*  Function pointer for callback function. */
+
+    void                     *pCBParam;    /*  Parameter to callback function. */
+    IRQn_Type                eIRQn;        /* IRQn */
+    uint32_t  cbWatch;
+    ADI_RTC_DEVICE_INFO     *pDeviceInfo;  /*  Parameter to callback function. */
+
+} ADI_RTC_DEVICE;
+
+
+static void rtc_init(ADI_RTC_DEVICE *pDevice,ADI_RTC_CONFIG *pConfig);
+
+#ifdef ADI_DEBUG
+static ADI_RTC_RESULT ValidateHandle( ADI_RTC_DEVICE *pInDevice);
+#endif
+/*! \endcond */
+#endif /* ADI_RTC_DEF_H__ */
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map.h
new file mode 100755
index 00000000000..7224c14faa4
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map.h
@@ -0,0 +1,71 @@
+/*!
+ *****************************************************************************
+ @file:    adi_rtos_map.h
+ @brief:   RTOS API mapping file.
+           This is the main RTOS mapping header file which will include other
+           RTOS mapping files based on the RTOS selection.
+           
+           The purpose of RTOS mapping file is for mapping the abstracted
+           RTOS macros to the RTOS API calls based on the chosen RTOS.
+           
+           NOTE: This file is intended to be used by only the drivers. Not at 
+                 the application level.
+           
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+#ifndef ADI_RTOS_MAP_H
+#define ADI_RTOS_MAP_H
+
+#include <adi_global_config.h>
+
+#if   (ADI_CFG_RTOS == ADI_CFG_RTOS_MICRIUM_III)
+    
+#include "rtos_map/adi_rtos_map_ucos_iii.h"
+
+#elif (ADI_CFG_RTOS == ADI_CFG_RTOS_FREERTOS)
+    
+#include "rtos_map/adi_rtos_map_freertos.h"    
+
+#else 
+    
+#include "rtos_map/adi_rtos_map_noos.h"
+
+#endif /* ADI_CFG_RTOS_MICRIUM_III */ 
+
+#endif /* ADI_RTOS_MAP_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_freertos.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_freertos.h
new file mode 100755
index 00000000000..97cbcaeeb78
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_freertos.h
@@ -0,0 +1,144 @@
+/*!
+ *****************************************************************************
+ @file:    adi_rtos_map_freertos.h
+ @brief:   FreeRTOS RTOS API mapping file.
+
+           This file maps the RTOS macros to FreeRTOS APIs
+           
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+
+#ifndef ADI_RTOS_MAP_FREERTOS_H
+#define ADI_RTOS_MAP_FREERTOS_H
+
+/* If building a c file */
+#if defined(__STDC__)
+
+#include <FreeRTOS.h>
+#include "semphr.h"
+
+extern BaseType_t xHigherPriorityTaskWoken;
+  
+/*! Macro that declares the semaphore type that the drivers use. 
+    The macro should be used within the device data structure.
+    It should not be used to declare the semaphore as a global variable. */
+#define SEM_VAR_DECLR                                                                    \
+                            StaticQueue_t hSemaphore;                                  
+                            
+/*! Memory required for semaphore in terms bytes. This size is used to compute 
+    the total memory required for the operation of the driver. FreeRtos does not 
+    require semaphore memory to be passed by application. But memory is required
+    to store the handle. */
+#define ADI_SEM_SIZE        (sizeof(StaticQueue_t))                            
+
+/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */
+
+                        /*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */
+#define SEM_CREATE(DEV, name, error)                                                     \
+                   do {                                                                  \
+                         xSemaphoreCreateBinaryStatic(&(DEV)->hSemaphore);                \
+                      } while (0)
+
+/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */
+#define SEM_DELETE(DEV, error)                                                           \
+                   do {                                                                  \
+                            vSemaphoreDelete (&(DEV)->hSemaphore);                        \
+                      } while (0)
+
+
+/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the device driver structure that contains the semaphore handle.*/
+#define SEM_PEND(DEV, error)                                                             \
+                 do {                                                                    \
+                       if(xSemaphoreTake (&(DEV)->hSemaphore, portMAX_DELAY) != pdTRUE)   \
+                       return((error));                                                  \
+                    } while (0)
+
+/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */
+/* Note that priority inversion is supported */
+#define SEM_POST(DEV)                                                                     \
+        do {                                                                              \
+          /* Assume that a higher priority task can be schedule in */                     \
+          BaseType_t xHigherPriorityTaskWoken = pdTRUE;                                   \
+          xSemaphoreGiveFromISR(&(DEV)->hSemaphore, &xHigherPriorityTaskWoken);           \
+        } while (0)                        
+
+/*! Defines a local variable where interrupt status register value is stored. 
+    This macro should be used within a function in which critical section
+    macros ADI_ENTER_CRITICAL_REGION and ADI_EXIT_CRITICAL_REGION are 
+    used. 
+    
+    @sa ADI_ENTER_CRITICAL_REGION()
+    @sa ADI_EXIT_CRITICAL_REGION()
+    */
+#define ADI_INT_STATUS_ALLOC()
+
+/*! Macro to enter critical section. To use this macro, the
+    interrupt status variable should be defined (ADI_INT_STATUS_ALLOC)
+    in the same scope. 
+    
+    @sa ADI_INT_STATUS_ALLOC()
+*/
+#define ADI_ENTER_CRITICAL_REGION()  vPortEnterCritical()
+
+/*! Macro to exit critical section.To use this macro, the
+    interrupt status variable should be defined (ADI_INT_STATUS_ALLOC)
+    in the same scope. 
+
+    @sa  ADI_INT_STATUS_ALLOC()   
+*/ 
+#define ADI_EXIT_CRITICAL_REGION() vPortExitCritical()
+
+/*! Code that uCOS requires to be run in the beginning of an interrupt handler. 
+    @sa ISR_EPILOG()
+*/
+#define ISR_PROLOG()            
+
+/*! Code that uCOS requires to be run in the end of an interrupt handler. 
+    @sa ISR_PROLOG()
+*/
+#define ISR_EPILOG()   portYIELD()         
+     
+#endif /* __STDC__  */
+
+#define PENDSV_HANDLER   xPortPendSVHandler
+#define SYSTICK_HANDLER  xPortSysTickHandler
+#define SVC_HANDLER      vPortSVCHandler
+
+
+#endif /* ADI_RTOS_MAP_FREERTOS_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_noos.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_noos.h
new file mode 100755
index 00000000000..e508f1ccf57
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_noos.h
@@ -0,0 +1,180 @@
+/*!
+ *****************************************************************************
+ @file:    adi_rtos_map_noos.h
+ @brief:   No OS API mapping file.
+
+           This file maps the RTOS macros to No OS APIs
+
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+
+#ifndef ADI_RTOS_MAP_NOOS_H
+#define ADI_RTOS_MAP_NOOS_H
+
+/* If building a c file */
+#if defined(__STDC__)
+
+#include <stdint.h>
+#include <stddef.h>
+#include <drivers/pwr/adi_pwr.h>
+#include <adi_cyclecount.h>
+
+/*! Defines a local variable where interrupt status register value is stored.
+    This macro should be used within a function in which critical section
+    macros ADI_ENTER_CRITICAL_REGION and ADI_EXIT_CRITICAL_REGION are
+    used.
+
+    @sa ADI_ENTER_CRITICAL_REGION()
+    @sa ADI_EXIT_CRITICAL_REGION()
+    */
+#define ADI_INT_STATUS_ALLOC()      uint32_t IntStatus = 0u
+
+/*! Macro to enter critical section. To use this macro, the
+    interrupt status variable should be defined (ADI_INT_STATUS_ALLOC)
+    in the same scope.
+
+    @sa ADI_INT_STATUS_ALLOC()
+*/
+#define ADI_ENTER_CRITICAL_REGION()                                                \
+do {                                                                               \
+      IntStatus  = __get_PRIMASK();                                                \
+    __disable_irq();                                                               \
+} while (0)
+
+
+/*! Macro to exit critical section.To use this macro, the
+    interrupt status variable should be defined (ADI_INT_STATUS_ALLOC)
+    in the same scope.
+
+    @sa  ADI_INT_STATUS_ALLOC()
+*/
+#define ADI_EXIT_CRITICAL_REGION()                                                 \
+do {                                                                               \
+  __set_PRIMASK(IntStatus);                                                        \
+} while (0)
+
+
+/*! Memory required for semaphore in terms bytes. This size is used to compute
+    the total memory required for the operation of the driver. */
+#define ADI_SEM_SIZE        (sizeof(uint32_t))
+    
+/*! Code that uCOS requires to be run in the beginning of an interrupt handler.
+    @sa ISR_EPILOG()
+*/
+#if defined(ADI_CYCLECOUNT_ENABLED) && (ADI_CYCLECOUNT_ENABLED == 1u)
+#define  ISR_PROLOG() adi_cyclecount_start();
+#else
+#define  ISR_PROLOG()
+#endif
+
+
+/*! Code that uCOS requires to be run in the end of an interrupt handler.
+    @sa ISR_PROLOG()
+*/
+#if defined(ADI_CYCLECOUNT_ENABLED) && (ADI_CYCLECOUNT_ENABLED == 1u)
+#define  ISR_EPILOG() adi_cyclecount_stop();
+#else
+#define  ISR_EPILOG()
+#endif
+
+#if (ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT == 1)
+
+/*! Macro that declares the semaphore type that the drivers use.
+    The macro should be used within the device data structure.
+    It should not be used to declare the semaphore as a global variable. */
+#define SEM_VAR_DECLR         volatile uint32_t nLowPowerExitFlag;
+
+/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */
+#define SEM_CREATE(DEV, name, error) \
+    (DEV)->nLowPowerExitFlag = 0u
+    
+/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */
+#define SEM_DELETE(DEV, error) do { } while(0)
+
+/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the   device driver structure that contains the semaphore handle. */
+#define SEM_PEND(DEV, error)                                                                    \
+   do {                                                                                         \
+        ADI_PWR_RESULT eResult;                                                                 \
+        eResult = adi_pwr_EnterLowPowerMode(ADI_PWR_MODE_FLEXI, &(DEV)->nLowPowerExitFlag, 0u); \
+        if(eResult != ADI_PWR_SUCCESS) { return ((error)); }                                    \
+   } while(0)
+
+
+/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */
+#define SEM_POST(DEV)                                                              \
+   do {                                                                            \
+        adi_pwr_ExitLowPowerMode(&(DEV)->nLowPowerExitFlag);                       \
+   } while(0)
+
+
+#else /* ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT == 0 */
+
+/*! Macro that declares the semaphore type that the drivers use.
+    The macro should be used within the device data structure.
+    It should not be used to declare the semaphore as a global variable. */
+#define SEM_VAR_DECLR       volatile uint32_t nSemCount;
+
+/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */
+#define SEM_CREATE(DEV, name, error) \
+   (DEV)->nSemCount = 0
+    
+/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */
+#define SEM_DELETE(DEV, error)  do { } while(0)
+
+/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the   device driver structure that contains the semaphore handle. */
+#define SEM_PEND(DEV, error)                                                       \
+    while ((DEV)->nSemCount == 0u) {}                                              \
+    (DEV)->nSemCount--
+
+/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */
+#define SEM_POST(DEV) {                                                            \
+    (DEV)->nSemCount++;                                                            \
+}
+
+#endif /* ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT */
+
+#endif /* __STDC__ */
+
+#define PENDSV_HANDLER      PendSV_Handler
+#define SYSTICK_HANDLER     SysTick_Handler
+#define SVC_HANDLER         SVC_Handler
+
+
+#endif /* ADI_RTOS_MAP_NOOS_H */
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_ucos_ii.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_ucos_ii.h
new file mode 100755
index 00000000000..20ee60f610f
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_ucos_ii.h
@@ -0,0 +1,149 @@
+/*!
+ *****************************************************************************
+ @file:    adi_rtos_map_ucos_ii.h
+ @brief:   uCOS-III RTOS API mapping file.
+
+           This file maps the RTOS macros to uCOS-II APIs
+           
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+
+#ifndef ADI_RTOS_MAP_UCOS_II_H
+#define ADI_RTOS_MAP_UCOS_II_H
+
+/* If building a c file */
+#if defined(__STDC__)
+
+#include <ucos_ii.h>
+#include <cpu.h>
+#include <stdint.h>
+#include <stddef.h>
+
+/*! Macro that declares the semaphore type that the drivers use. 
+    The macro should be used within the device data structure.
+    It should not be used to declare the semaphore as a global variable. */
+#define SEM_VAR_DECLR                                                                    \
+                            OS_EVENT  *hSemaphore;                      
+
+/*! Memory size required for semaphore in terms bytes. This size is used to compute 
+    the total memory required for the operation of the driver. In case of uCOS-II
+    there is no requirement to provide the memory to create the semaphore, but
+    memory is required to store the handle */
+#define ADI_SEM_SIZE        sizeof(OS_EVENT)
+
+/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */
+#define SEM_CREATE(DEV, name, error)                                                     \
+                   do {                                                                  \
+                        ((DEV)->hSemaphore) = OSSemCreate(0u);                           \
+                        if((DEV)->hSemaphore == NULL) {return((error));}                 \
+                      } while (0)
+
+/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */
+#define SEM_DELETE(DEV, error)                                                           \
+                   do {                                                                  \
+                          INT8U os_error;                                                \
+                          OSSemDel( (DEV)->hSemaphore, OS_DEL_NO_PEND, &os_error );      \
+                          if(os_error != OS_ERR_NONE) {return((error));}                 \
+                      } while (0)
+
+
+/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the device driver structure that contains the semaphore handle. */
+#define SEM_PEND(DEV, error)                                                             \
+                    do {                                                                 \
+                          INT8U  os_error;                                               \
+                          OSSemPend    ((DEV)->hSemaphore, 0u, &os_error);               \
+                          if(os_error != OS_ERR_NONE) {return((error));}                 \
+                       } while (0)
+
+/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */
+#define SEM_POST(DEV)                                                                    \
+        do {                                                                             \
+          OSSemPost((DEV)->hSemaphore );                                                 \
+        } while (0)
+
+/*! Defines a local variable where interrupt status register value is stored. 
+    This macro should be used within a function in which critical section
+    macros ADI_ENTER_CRITICAL_REGION and ADI_EXIT_CRITICAL_REGION are 
+    used. 
+    
+    @sa ADI_ENTER_CRITICAL_REGION()
+    @sa ADI_EXIT_CRITICAL_REGION()
+    */
+#define ADI_INT_STATUS_ALLOC()     CPU_SR_ALLOC()
+
+/*! Macro to enter critical section. To use this macro, the
+    interrupt status variable should be defined (ADI_INT_STATUS_ALLOC)
+    in the same scope. 
+    
+    @sa ADI_INT_STATUS_ALLOC()
+*/ 
+#define ADI_ENTER_CRITICAL_REGION()  CPU_CRITICAL_ENTER()
+
+/*! Macro to exit critical section.To use this macro, the
+    interrupt status variable should be defined (ADI_INT_STATUS_ALLOC)
+    in the same scope. 
+
+    @sa  ADI_INT_STATUS_ALLOC()   
+*/  
+#define ADI_EXIT_CRITICAL_REGION() CPU_CRITICAL_EXIT()
+
+/*! Code that uCOS requires to be run in the beginning of an interrupt handler. 
+    @sa ISR_EPILOG()
+*/
+#define ISR_PROLOG()                                                                     \
+                    do {                                                                 \
+                           CPU_SR_ALLOC();                                               \
+                           CPU_CRITICAL_ENTER();                                         \
+                           OSIntEnter();                                                 \
+                           CPU_CRITICAL_EXIT();                                          \
+                       } while (0);
+
+/*! Code that uCOS requires to be run in the end of an interrupt handler. 
+    @sa ISR_PROLOG()
+*/
+#define ISR_EPILOG() OSIntExit(); 
+     
+#endif /* __STDC__ */
+
+#define PENDSV_HANDLER   OS_CPU_PendSVHandler
+#define SYSTICK_HANDLER  OS_CPU_SysTickHandler
+#define SVC_HANDLER      SVC_Handler
+
+
+#endif /* ADI_RTOS_MAP_UCOS_II_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_ucos_iii.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_ucos_iii.h
new file mode 100755
index 00000000000..e055b7010fb
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_ucos_iii.h
@@ -0,0 +1,167 @@
+/*!
+ *****************************************************************************
+ @file:    adi_rtos_map_ucos_iii.h
+ @brief:   uCOS-III RTOS API mapping file.
+
+           This file maps the RTOS macros to uCOS-III APIs
+           
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+*****************************************************************************/
+
+#ifndef ADI_RTOS_MAP_UCOS_III_H
+#define ADI_RTOS_MAP_UCOS_III_H
+
+/* If building a c file */
+#if defined(__STDC__)
+
+#include <cpu.h>
+#include <os.h>
+#include <stdint.h>
+#include <stddef.h>
+
+/*! Macro that declares the semaphore type that the drivers use. 
+    The macro should be used within the device data structure.
+    It should not be used to declare the semaphore as a global variable. */
+#define SEM_VAR_DECLR                                                                           \
+                    OS_SEM Semaphore;                                  
+
+/*! Memory required for semaphore in terms bytes. This size is used to compute 
+    the total memory required for the operation of the driver. uCOS-III requires
+    semaphore memory to be passed by application. But there is no memory required
+    to store the handle. For every semaphore related call the same memory pointer 
+    that was used during create will be passed. */
+#define ADI_SEM_SIZE        (sizeof(OS_SEM))
+                                        
+/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */
+#define SEM_CREATE(DEV, name, error)                                                            \
+                   do {                                                                         \
+                         OS_ERR os_error;                                                       \
+                         OSSemCreate(&((DEV)->Semaphore), name ,0u, &os_error);                 \
+                         if(OS_ERR_NONE != os_error) {return((error));}                         \
+                      } while (0)
+
+/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */
+#define SEM_DELETE(DEV, error)                                                                  \
+                   do {                                                                         \
+                         OS_ERR os_error;                                                       \
+                         OSSemDel( &((DEV)->Semaphore), OS_OPT_DEL_NO_PEND, &os_error );        \
+                         if(OS_ERR_NONE != os_error) {return((error));}                         \
+                      } while (0)
+
+
+/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the device driver structure that contains the semaphore handle.*/
+#define SEM_PEND(DEV, error)                                                                    \
+        do {                                                                                    \
+              OS_ERR  os_error;                                                                 \
+              OSSemPend    (&((DEV)->Semaphore), 0u, OS_OPT_PEND_BLOCKING , NULL, &os_error);   \
+              if(OS_ERR_NONE != os_error) {return((error));}                                    \
+           } while (0)
+               
+/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */
+#define SEM_POST(DEV)                                                                           \
+        do {                                                                                    \
+          OS_ERR  os_error;                                                                     \
+          OSSemPost(&((DEV)->Semaphore), OS_OPT_POST_1, &os_error);                             \
+        } while (0)
+          
+
+/*! Defines a local variable where interrupt status register value is stored. 
+    This macro should be used within a function in which critical section
+    macros ADI_ENTER_CRITICAL_REGION and ADI_EXIT_CRITICAL_REGION are 
+    used. 
+    
+    @sa ADI_ENTER_CRITICAL_REGION()
+    @sa ADI_EXIT_CRITICAL_REGION()
+*/
+#define ADI_INT_STATUS_ALLOC()     CPU_SR_ALLOC()
+    
+/*! Macro to enter critical section. To use this macro, the
+    interrupt status variable should be defined (ADI_INT_STATUS_ALLOC)
+    in the same scope. 
+    
+    @sa ADI_INT_STATUS_ALLOC()
+*/
+#define ADI_ENTER_CRITICAL_REGION()  CPU_CRITICAL_ENTER()
+
+/*! Macro to exit critical section.To use this macro, the
+    interrupt status variable should be defined (ADI_INT_STATUS_ALLOC)
+    in the same scope. 
+
+    @sa  ADI_INT_STATUS_ALLOC()   
+*/ 
+#define ADI_EXIT_CRITICAL_REGION() CPU_CRITICAL_EXIT()
+
+
+/*! Code that uCOS requires to be run in the beginning of an interrupt handler. 
+    @sa ISR_EPILOG()
+*/
+#if defined(ADI_CYCLECOUNT_ENABLED) && (ADI_CYCLECOUNT_ENABLED == 1)
+#define ADI_RTOS_UCOS_III_CYCLECOUNT_START adi_cyclecount_start();
+#define ADI_RTOS_UCOS_III_CYCLECOUNT_STOP  adi_cyclecount_stop();
+#else
+#define ADI_RTOS_UCOS_III_CYCLECOUNT_START 
+#define ADI_RTOS_UCOS_III_CYCLECOUNT_STOP  
+#endif
+
+#define ISR_PROLOG()                                                                            \
+                            do {                                                                \
+                                    CPU_SR_ALLOC();                                             \
+                                    CPU_CRITICAL_ENTER();                                       \
+                                    OSIntEnter();                                               \
+                                    CPU_CRITICAL_EXIT();                                        \
+                                    ADI_RTOS_UCOS_III_CYCLECOUNT_START                          \
+                               } while (0);
+
+/*! Code that uCOS requires to be run in the end of an interrupt handler. 
+    @sa ISR_PROLOG()
+*/
+#define ISR_EPILOG()                                                                            \
+                            do {                                                                \
+                                   ADI_RTOS_UCOS_III_CYCLECOUNT_STOP                            \
+                                   OSIntExit();                                                 \
+                            } while (0);                                                        \
+
+#endif /* __STDC__ */
+
+#define PENDSV_HANDLER   OS_CPU_PendSVHandler
+#define SYSTICK_HANDLER  OS_CPU_SysTickHandler
+#define SVC_HANDLER      SVC_Handler
+          
+
+#endif /* ADI_RTOS_MAP_UCOS_III_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi.c
new file mode 100755
index 00000000000..7c8c0e30229
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi.c
@@ -0,0 +1,1892 @@
+/*! *****************************************************************************
+ * @file:    adi_spi.c
+ * @brief:   SPI  device  driver global file.
+ * @details: This a global file which includes a specific file based on the processor family.
+ *           This included file will be  containing  SPI device  driver functions.
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+/** @addtogroup SPI_Driver SPI Driver
+ *  @{
+ * @brief Serial Peripheral Interface (SPI) Driver
+ * @details The SPI driver manages all instances of the SPI peripheral.
+ * @note The application must include drivers/spi/adi_spi.h to use this driver.
+ * @note This driver requires the DMA driver.The application must include the DMA driver sources to avoid link errors.
+ * @note Also note that the SPI will be configured by default to operate in Master mode. 
+ * @note To configure the driver to operate in slave mode the static configuration file adi_spi_config.h must be modified. 
+ * @note Specifically, the macro ADI_SPIx_MASTER_MODE must be set to '0' to indicate that slave mode functionality is needed. 
+ * @note Since there are three SPI devices there are three macros, ADI_SPI0_MASTER_MODE, ADI_SPI1_MASTER_MODE and ADI_SPI2_MASTER_MODE to control the functionality of each SPI controller. 
+ * @note Each instance of the SPI operates independently from all other instances.
+ * @note
+ * @note When operating the SPI at high bit rates the application may need to modify the IRQ interrupt mode. The API adi_spi_SetIrqmode() can be used for this.
+ * @note At higher bit rates the ISR could mask a TX/RX interrupt. Specifically, it is possible that while servicing a TX/RX event another TX/RX event could occur. It is
+ * @note possible, therefore, that when the ISR clears the interrupt status it will not only be clearing the current TX event but the next TX/RX event as well. The result
+ * @note could that a final TX/RX event will not be processed. One way to work around this would be to set IRQMODE such that TX/RX events will occur only after N bytes
+ * @note are in the FIFO. This will only work for short bursts less than the size of the FIFO. For larger transfer DMA mode, which will not have any of these issues,  should be used.
+ * @note Finally, if interrupt mode is required at hight bit rates note that the SPI ISR has been designed with minimal cycle count as the highest priority. 
+ * @note The ISR could certainly be modified to re-examine the FIFO before existing at the cost of additional cycles.
+ */
+
+ /*! \cond PRIVATE */
+#include <adi_processor.h>
+/*! \endcond */
+
+#include <stdlib.h>  /* for 'NULL" definition */
+#include <string.h>
+
+#include <drivers/spi/adi_spi.h>
+#include <drivers/pwr/adi_pwr.h>
+#include <drivers/general/adi_drivers_general.h>
+#include <adi_callback.h>
+#include <rtos_map/adi_rtos_map.h>
+#include "adi_spi_config.h"
+#include <adi_cyclecount.h>
+
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
+*   This isn't a header as such.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+*
+* Pm088 (rule 17.4): pointer arithmetic should not be used.
+*   Relying on pointer arithmetic for buffer handling.
+*
+* Pm152: (MISRA C 2004 rule 17.4) array indexing shall only be applied to objects defined as an array type  
+*   Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors
+*
+* Pm151 (rule 17.4): array indexing shall only be applied to objects of array type
+* Pm123 (rule 18.5): there shall be no definition of objects in a header file
+*
+* Pm50: (MISRA C 2004 rule 14.3) a null statement shall only occur on a line by itself, and shall not have any other text on the same line
+*    Some Macros, such as ISR_PROLOGUE, may not have any expansion resulting in just the terminating ';'
+*
+*Pm140: (MISRA C 2004 rule 11.3) a cast should not be performed between a pointer type and an integral type
+*    MMR addresses are defined as simple constants. Accessing the MMR requires casting to a pointer type
+*
+* Pm031: (MISRA C 2004 rule 12.7)  bitwise operations shall not be performed on signed integer types 
+*    MMR macros are beyond the control of the driver.
+*
+*/
+#pragma diag_suppress=Pm050,Pm073,Pm088,Pm123,Pm143,Pm152,Pm140,Pm031
+
+#endif /* __ICCARM__ */
+
+#include "adi_spi_data.c"
+
+/*! \cond PRIVATE */
+
+/* handle checker for debug mode */
+#define ADI_SPI_VALIDATE_HANDLE(h) ((spi_device_info[0].hDevice != (h)) && (spi_device_info[1].hDevice != (h)) && (spi_device_info[2].hDevice != (h)))
+
+/*! \endcond */
+
+/*
+ * Local prototypes
+ */
+static void common_SPI_Int_Handler (ADI_SPI_DEV_DATA_TYPE* pDD);
+static void StartTransaction       (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr);
+static void TxDmaErrorCallback     (void *pCBParam, uint32_t Event, void *pArg);
+static void RxDmaErrorCallback     (void *pCBParam, uint32_t Event, void *pArg);
+
+/* ISR forward declarations */
+/*! \cond PRIVATE */
+void SPI0_Int_Handler(void);
+void SPI1_Int_Handler(void);
+void SPI2_Int_Handler(void);
+void DMA_SPI0_TX_Int_Handler(void);
+void DMA_SPI0_RX_Int_Handler(void);
+void DMA_SPI1_TX_Int_Handler(void);
+void DMA_SPI1_RX_Int_Handler(void);
+void DMA_SPIH_TX_Int_Handler(void);
+void DMA_SPIH_RX_Int_Handler(void);
+/*! \endcond */
+
+/*
+    //////////////////////////////////////////////////////////////////////////////
+    //////////////////////   API IMPLEMENTATIONS   ///////////////////////////////
+    //////////////////////////////////////////////////////////////////////////////
+*/
+
+/*!
+ * @brief  Initialize and allocate an SPI device for use in Master Mode.
+ *
+ * @param[in]   nDeviceNum   Zero-based device index designating which device to initialize.
+ *\n
+ * @param [in]  pDevMemory   Pointer to a buffer of size ADI_SPI_MEMORY_SIZE
+ *\n                         required by the driver for the operation of specified SPI device.
+ *
+ * @param [in]  nMemorySize  Size of the buffer to which "pMemory" points. 
+ *
+ * @param[out]  phDevice     The caller's device handle pointer for storing the initialized device instance data pointer.
+ *
+ * @return            Status
+ *                    - #ADI_SPI_INVALID_DEVICE_NUM [D]     Invalid device index.
+ *                    - #ADI_SPI_INVALID_PARAM [D]          Invalid parameter.
+ *                    - #ADI_SPI_SEMAPHORE_FAILED           Semaphore creation failed.
+ *                    - #ADI_SPI_DMA_REG_FAILED             Failed to register DMA callbacks with common DMA service.
+ *                    - #ADI_SPI_IN_USE                     SPI is already open and in use.
+ *                    - #ADI_SPI_SUCCESS                    Call completed successfully.
+ *
+* @note :  No other SPI APIs may be called until the device open function is called.
+ *\n       Initialize an SPI device using internal default configuration settings and allocate the
+ *\n       device for use.The returned device handle is required to be passed to all subsequent
+ *\n       calls to convey which device instance to operate on.
+ *\n       The contents of phDevice will be set to NULL upon failure. Device is opened in Master mode.
+ *\n
+ * @sa      adi_spi_SetMasterMode()
+ * @sa      adi_spi_Close().
+ */
+ADI_SPI_RESULT adi_spi_Open(uint32_t nDeviceNum,
+                            void *pDevMemory,
+                            uint32_t nMemorySize,
+                            ADI_SPI_HANDLE* const phDevice)
+{
+
+#ifdef ADI_DEBUG
+
+    if (nDeviceNum >= ADI_SPI_NUM_INSTANCES)
+    {
+        return ADI_SPI_INVALID_DEVICE_NUM;
+    }
+
+    if (nMemorySize != sizeof(struct __ADI_SPI_DEV_DATA_TYPE))
+    {
+        return ADI_SPI_INVALID_PARAM;
+    }
+    
+    if( spi_device_info[nDeviceNum].hDevice != NULL )
+    {
+        return ADI_SPI_IN_USE;
+    }
+
+#endif
+
+    ADI_SPI_HANDLE hDevice = pDevMemory;
+    
+    /* 
+     * Link the two data structures together.
+     *   
+     *         ADI_SPI_DEVICE_INFO  <==>   ADI_SPI_HANDLE
+     *
+     * Clear the ADI_SPI_HANDLE memory. This also sets all bool 
+     * structure members to false so we do not need to waste cycles 
+     * setting these explicitly (e.g. hDevice->bDMA = false)
+     *
+     * Other fields, such as callback related fields, are also zeroed
+     * and therefore properly initialized.
+     */
+    
+    spi_device_info[nDeviceNum].hDevice = (ADI_SPI_DEV_DATA_TYPE *)pDevMemory;
+    memset(pDevMemory,0,nMemorySize);
+    hDevice->pDevInfo =  &spi_device_info[nDeviceNum];
+
+
+    /* 
+     * Although the ADI_SPI_DEVICE_INFO struct has the address of the SPI registers
+     * for this instance, copying it to the ADI_SPI_HANDLE struct will minimize
+     * the runtime footprint and cycle count when accessing the SPI registers
+     */
+    hDevice->pSpi = spi_device_info[nDeviceNum].pSpiRegs;
+
+    SEM_CREATE(hDevice, "SPI_SEM", ADI_SPI_SEMAPHORE_FAILED);
+
+   /* Static Configuration */
+    /* Initialize the device based on the given configuration parameters */
+    ADI_SPI_CFG_TYPE const* pSPICfg = &gSPICfg[nDeviceNum];
+    hDevice->pSpi->CTL = pSPICfg->SPI_CTL;
+    hDevice->pSpi->DIV = pSPICfg->SPI_DIV;
+
+    /* write the device data pointer into the caller's handle */
+    *phDevice = hDevice;
+    hDevice->pSpi->CTL |= BITM_SPI_CTL_SPIEN;
+    
+    /* Make sure the DMA controller and its SRAM based descriptors are initialized */
+    adi_dma_Init();
+
+    /* Setup the DMA TX callback */
+    if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback((DMA_CHANn_TypeDef) hDevice->pDevInfo->dmaTxChannelNumber, TxDmaErrorCallback, (void *) hDevice)) 
+    {
+         return  ADI_SPI_DMA_REG_FAILED;
+    }
+
+    /* Setup the DMA RX callback */
+    if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback((DMA_CHANn_TypeDef) hDevice->pDevInfo->dmaRxChannelNumber, RxDmaErrorCallback, (void *) hDevice)) 
+    {
+         return  ADI_SPI_DMA_REG_FAILED;
+    }
+
+    return ADI_SPI_SUCCESS;
+}
+
+
+/*!
+ * @brief  Uninitialize and deallocate an SPI device.
+ *
+ * @param[in]   hDevice    Device handle obtained from adi_spi_Open().
+ *
+ * @return      Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]       Invalid device handle parameter.
+ *                - #ADI_SPI_SUCCESS                  Call completed successfully.
+ *
+ * Uninitialize and release an allocated SPI device,and memory associated with it for other use.
+ *
+ * @sa  adi_spi_Open().
+ */
+ADI_SPI_RESULT adi_spi_Close (ADI_SPI_HANDLE const hDevice)
+{
+
+    ADI_SPI_RESULT result = ADI_SPI_SUCCESS;
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+
+#endif
+    
+    
+    /* disable Interrupt    */
+    NVIC_DisableIRQ(hDevice->pDevInfo->eIRQn);
+
+    
+     /* destroy semaphore */
+    SEM_DELETE((ADI_SPI_HANDLE) hDevice,ADI_SPI_SEMAPHORE_FAILED);
+
+    /* invalidate initialization state */
+    hDevice->pDevInfo->hDevice  = NULL;
+    return result;
+}
+
+
+/*!
+ * @brief  Register or unregister the callback.
+ *
+ * @param [in]   hDevice        Device handle obtained from adi_spi_Open().
+ * @param [in]   pfCallback     Pointer to the callback function. Can be passed as NULL to unregister the
+ *\n                            previously registered callback.
+ * @param [in]   pCBParam       Callback parameter which will be passed back to the application when the
+ *\n                            callback is called.
+ *
+ * @return      Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]  Invalid device handle parameter.
+ *                - #ADI_SPI_SUCCESS                    Call completed successfully.
+ */
+ADI_SPI_RESULT adi_spi_RegisterCallback (ADI_SPI_HANDLE const hDevice,  ADI_CALLBACK const pfCallback, void *const pCBParam )
+{
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice)) {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+
+#endif
+    /* Save the application provided callback and callback parameters */
+    hDevice->pfCallback = pfCallback;
+    hDevice->pCBParam   = pCBParam;
+
+    return ADI_SPI_SUCCESS;
+}
+
+/*!
+ * @brief  Set the IRQ mode.
+ *
+ * @param[in]    hDevice      Device handle obtained from adi_spi_Open().
+ * @param[in]    nMode        IRQ mode value to set.
+*                - true     Set continuous transfer mode.
+*                - false    Clear continuous transfer mode.
+ *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *                - #ADI_SPI_SUCCESS                        Call completed successfully.
+ *
+ * These bits configure when the Tx/Rx interrupts occur in a transfer. 
+ * For DMA Rxtransfer, these bits should be 0. 
+ * Value values are 0-7
+ *      Tx interrupt occurs when (nMode+1) byte(s) has been transferred.
+ *      Rx interrupt occurs when (nMode+1) or more bytes have been received into the FIFO.
+ *
+ *  @note The application will have to carefully manage IRQMODE relative to a transaction's buffer size.
+ *  @note Specifically, the application must ensure that the last byte causes an interrupt else the 
+ *  @note transaction will not terminate. As explained in the SPI driver overview, this functionality
+ *  @note is typically needed when operating in interrupt mode with a high SPI bit rate (typically issues
+ *  @note are seen at SPI clock rates of 4MHz or greater). The max clock rate will vary depending on the application.
+ *  @note The max clock rate is a function of the SPI ISR cycle count plus any other delay that might be caused
+ *  @note by other parts of the system. Finally, please note that while sustaining interrupt mode SPI transaction
+ *  @note at high bit rates will work buffers that are the size of the SPI FIFO or less, transactions that are 
+ *  @note larger that the size of the FIFO may run into issues associated with masked/lost interrupts. If this
+ *  @note does prove to be an issue for an applicatoon then the SPI ISR could be modified to examine the FIFO
+ *  @note status on a continuous basis in the ISR (as opposed to examining the FIFO status just once at the start
+ *  @note of the ISR). However, adding this functionality to the ISR will increase the ISR cycle count and footprint. 
+ *
+ */
+ADI_SPI_RESULT adi_spi_SetIrqmode (ADI_SPI_CONST_HANDLE const hDevice, const uint8_t nMode)
+{
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice)) {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+
+#endif
+    
+    uint16_t ien = hDevice->pSpi->IEN;
+    ien = ien & (uint16_t)~BITM_SPI_IEN_IRQMODE;
+    ien = ien | (nMode & BITM_SPI_IEN_IRQMODE);
+    hDevice->pSpi->IEN = ien;
+
+    return ADI_SPI_SUCCESS;
+}
+
+
+/*!
+ * @brief  Set the continuous transfer mode.
+ *
+ * @param[in]    hDevice      Device handle obtained from adi_spi_Open().
+ * @param[in]    bFlag        Flag to manage SPI continuous transfer mode.
+*                - true     Set continuous transfer mode.
+*                - false    Clear continuous transfer mode.
+ *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *                - #ADI_SPI_SUCCESS                        Call completed successfully.
+ *
+ * Setting this mode causes the SPI controller to drive the Chip Select signal continuously until the transaction
+ * is complete.  Clearing it causes Chip Select to cycle between bytes.
+ *
+ *
+ */
+ADI_SPI_RESULT adi_spi_SetContinuousMode (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag)
+{
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice)) {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+
+#endif
+
+    if (true == bFlag) {
+        hDevice->pSpi->CTL |= (BITM_SPI_CTL_CON);
+    } else {
+        hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CON;
+    }
+
+    return ADI_SPI_SUCCESS;
+}
+
+/*!
+ * @brief  Set the internal loopback mode.
+ *
+ * @param[in]    hDevice      Device handle obtained from adi_spi_Open().
+ * @param[in]    bFlag        Flag to manage internal SPI loopback mode.
+ *                - true     Set internal loopback mode.
+ *                - false    Clear internal loopback mode.
+ *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *                - #ADI_SPI_SUCCESS                        Call completed successfully.
+ *
+ * Set or clear the internal SPI loopback mode.  Primarily used for testing.
+ *
+ */
+ADI_SPI_RESULT adi_spi_SetLoopback (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag)
+{
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+
+#endif
+
+    if (true == bFlag) {
+        hDevice->pSpi->CTL |= (BITM_SPI_CTL_LOOPBACK);
+    } else {
+        hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_LOOPBACK;
+    }
+
+    return ADI_SPI_SUCCESS;
+}
+
+/*!
+ * @brief  Set SPI Master-Mode operation.
+ *
+ * @param[in]    hDevice      Device handle obtained from adi_spi_Open().
+ * @param[in]    bFlag        Flag to select either Master-Mode or Slave-Mode operation.
+ *\n                - true     Enable Master-Mode. Default.
+ *\n                - false    Enable Slave-Mode.
+ *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *                - #ADI_SPI_SUCCESS                        Call completed successfully.
+ *
+ * Controls SPI Master/Slave mode of operation, set for Master-Mode, clear for Slave-Mode.
+ *
+ */
+ADI_SPI_RESULT adi_spi_SetMasterMode (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag)
+{
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+
+#endif
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+    if (true == bFlag) {        /* hardware default */
+        hDevice->pSpi->CTL |= (ADI_SPI_MASTERCON_INITIALIZER);
+   } else {
+        hDevice->pSpi->CNT = 0u;
+        hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_MASEN;
+        hDevice->pSpi->CTL |= (ADI_SPI_SLAVECON_INITIALIZER);
+    }
+    ADI_EXIT_CRITICAL_REGION();
+    return ADI_SPI_SUCCESS;
+}
+
+
+/*!
+ * @brief  Set the SPI receive FIFO overflow mode.
+ *
+ * @param[in]    hDevice      Device handle obtained from adi_spi_Open().
+ * @param[in]    bFlag        Flag to manage receive FIFO overflow behaviour.
+ *\n              - true     Discard old data on receive FIFO overflow.
+ *\n              - false    Discard new data on receive FIFO overflow.
+ *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *                - #ADI_SPI_SUCCESS                        Call completed successfully.
+ *
+ * Controls what to do with excess incoming data when the receive FIFO becomes full.
+ * Either the new data or the old data is discarded.  Set the receive FIFO overflow mode
+ * to replace data in the RX register (top of receive FIFO) with the incoming new data.
+ * Clear it to discard incoming new data and preserve old unread data.
+
+ *
+ */
+ADI_SPI_RESULT adi_spi_SetReceiveOverflow (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag)
+{
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+
+#endif
+
+    if (true == bFlag) {
+        hDevice->pSpi->CTL |= (BITM_SPI_CTL_RXOF);
+    } else {
+        hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_RXOF;
+    }
+
+    return ADI_SPI_SUCCESS;
+}
+
+
+/*!
+ * @brief  Set the SPI transmit FIFO underflow mode.
+ *
+ * @param[in]    hDevice      Device handle obtained from adi_spi_Open().
+ * @param[in]    bFlag        Flag to manage transmit FIFO underflow behaviour.
+ *\n               - true     Send zeroes on transmit FIFO underflow.
+ *\n               - false    Resend last data on transmit FIFO underflow.
+ *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *                - #ADI_SPI_SUCCESS                        Call completed successfully.
+ *
+ *\n  Controls what to transmit when lacking valid data because the transmit FIFO is empty.
+ *\n  Either zeros or the last valid data are transmitted.  Set transmit FIFO underflow mode to send zeros.
+ *\n Clear it to resend the last transmitted data.
+ *
+ */
+ADI_SPI_RESULT adi_spi_SetTransmitUnderflow (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag)
+{
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+#endif
+
+    if (true == bFlag) {
+        hDevice->pSpi->CTL |= (BITM_SPI_CTL_ZEN);
+    } else {
+        hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_ZEN;
+    }
+
+    return ADI_SPI_SUCCESS;
+}
+
+
+
+
+
+
+/*!
+ * @brief  Set the SPI serial clock frequency.
+ *
+ * @param[in]    hDevice      Device handle obtained from adi_spi_Open()
+ * @param[in]    Hertz        Target frequency (in Hz) for SPI bitrate.
+ *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *                - #ADI_SPI_INVALID_PARAM              Specified frequency is out of range.
+ *                - #ADI_SPI_BAD_SYS_CLOCK              Unable to obtain PCLK which is needed to calculate the new bit rate.
+ *                - #ADI_SPI_SUCCESS                    Call completed successfully.
+ *
+ * Compute and set the internal SPI clock rate divider register to produce
+ *\n the desired serial clock frequency.  Resulting frequency is subject to arithmetic rounding errors.
+ *\n Use #adi_spi_GetBitrate() to obtain the exact frequency produced, including rounding errors.
+ *
+ * @sa        adi_spi_GetBitrate().
+ */
+ADI_SPI_RESULT adi_spi_SetBitrate (ADI_SPI_CONST_HANDLE const hDevice, const uint32_t Hertz)
+{
+    uint32_t incoming_clock;
+    uint16_t Div;
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+#endif
+
+    if( adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &incoming_clock) != ADI_PWR_SUCCESS)
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+
+    /* requested rate needs to be 2x or less than incoming clock */
+    if ((2U * Hertz) > incoming_clock)
+    {
+        return ADI_SPI_BAD_SYS_CLOCK;
+    }
+
+     /* compute the SPI divider value */
+     Div = (uint16_t) ((incoming_clock / Hertz) >> 1U) - 1U;  /* '>>1' is really a divide by 2 */
+
+    /* range check that computed divider fits */
+    if (Div != (Div & BITM_SPI_DIV_VALUE))
+    {
+        return ADI_SPI_INVALID_PARAM;
+    }
+
+    /* store it in core */
+    hDevice->pSpi->DIV = Div;
+
+    return ADI_SPI_SUCCESS;
+}
+
+
+/*!
+ * @brief  Get the SPI serial clock frequency.
+ *
+ * @param[in]    hDevice     Device handle obtained from adi_spi_Open()
+ * \n
+ * @param[out]    pnBitrate   Pointer to the location where Bitrate need to be written.
+ *
+ * @return
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *                - #ADI_SPI_SUCCESS                        Call completed successfully.
+ *
+ * Get the current serial clock frequency.  The returned value is exact but
+ *\n may not exactly match the value set with #adi_spi_SetBitrate() due to
+ *\n computational round-off errors resulting from fixed register size and
+ *\n finite-precision arithmetic.
+ *
+ * @sa        adi_spi_SetBitrate().
+ */
+ADI_SPI_RESULT adi_spi_GetBitrate (ADI_SPI_CONST_HANDLE const hDevice, uint32_t* const pnBitrate)
+{
+    uint32_t incoming_clock;
+    ADI_PWR_RESULT ePwrResult;
+    uint32_t Div;
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+#endif
+    Div = hDevice->pSpi->DIV;  /* assumes this is always a right-justified value */
+
+    ePwrResult = adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &incoming_clock);
+    if(ePwrResult != ADI_PWR_SUCCESS)
+    {
+        *pnBitrate= 0u;
+         return(ADI_SPI_FAILURE);
+    }
+    *pnBitrate= (incoming_clock / (Div + 1U)) >> 1U;  /* '>>1' is divide by 2 */
+     return(ADI_SPI_SUCCESS);
+
+}
+
+
+/*!
+ * @brief  Set the chip select.
+ *
+ * @param[in]    hDevice       Device handle obtained from adi_spi_Open().
+ * @param[in]    eChipSelect   An enum value representing the requested Chip Select.
+ *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *                - #ADI_SPI_SUCCESS                        Call completed successfully.
+ *
+ * Sets the desired chip select to use for activating an external slave device.
+ *
+ * @note      Chip select \a ADI_SPI0_CSn is reserved for SPI device 0 (SPI0) internal chip select line
+ *            dedicated for communications with the UHF device.
+ *
+ */
+ADI_SPI_RESULT adi_spi_SetChipSelect (ADI_SPI_HANDLE const hDevice, const ADI_SPI_CHIP_SELECT eChipSelect)
+{
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+#endif
+
+    hDevice->ChipSelect = eChipSelect;
+
+    return ADI_SPI_SUCCESS;
+}
+
+/*!
+ * @brief  Submit data buffers for SPI Master-Mode transaction in "Blocking mode".This function
+ *\n          returns only after the data transfer is complete
+ *
+ * @param[in]     hDevice     Device handle obtained from adi_spi_Open().
+ * @param[in]     pXfr        Pointer to transfer data struct #ADI_SPI_TRANSCEIVER.
+  *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]        Invalid device handle parameter.
+ *                - #ADI_SPI_BUFFER_NOT_SUBMITTED [D]  Failed to submit the buffer.
+ *                - #ADI_SPI_INVALID_POINTER [D]       Invalid data pointer detected (NULL).
+ *                - #ADI_SPI_INVALID_PARAM [D]         Invalid size parameter detected (0).
+ *                - #ADI_SPI_SUCCESS                   Call completed successfully.
+ *
+ *\n
+ *\n Request a non-blocking mode transmit and receive of multiple data bytes
+ *\n over the SPI serial channel.  
+ *\n Buffer allocations are made by the calling code (the application).
+ *\n
+ *\n The transmit buffer is sent and the receive buffer is written according
+ *\n to the size and increment information contained by the \a pXft transfer
+ *\n data structure parameter.
+ *\n
+ *\n
+ * @sa adi_spi_MasterSubmitBuffer().
+ * @sa ADI_SPI_TRANSCEIVER
+ */
+ADI_SPI_RESULT adi_spi_MasterReadWrite (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr)
+{
+    ADI_SPI_RESULT eResult;
+    hDevice->bBlockingMode = true;
+    eResult = adi_spi_MasterSubmitBuffer(hDevice,pXfr);
+    hDevice->bBlockingMode = false;
+    if( (eResult == ADI_SPI_SUCCESS) && (hDevice->HWErrors != 0u))
+    {
+      eResult = ADI_SPI_HW_ERROR_OCCURRED;
+    }
+    return(eResult);
+}
+
+/*!
+ * @brief  Submit data buffers for SPI Master-Mode transaction.
+ *
+ * @param[in]     hDevice     Device handle obtained from adi_spi_Open().
+ * @param[in]     pXfr        Pointer to transfer data struct.
+  *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]        Invalid device handle parameter.
+ *                - #ADI_SPI_IN_USE [D]    DMA transaction already under way.
+ *                - #ADI_SPI_INVALID_POINTER [D]     Invalid data pointer detected (NULL).
+ *                - #ADI_SPI_INVALID_PARAM [D]    Invalid size parameter detected (0).
+ *                - #ADI_SPI_SUCCESS                       Call completed successfully.
+ *
+ *\n Request a blocking mode transmit and receive of multiple data bytes
+ *\n over the SPI serial channel.  
+ *\n Buffer allocations are made by the calling code (the application).
+ *\n
+ *\n The transmit buffer is sent and the receive buffer is written according
+ *\n to the size and increment information contained by the \a pXft transfer
+ *\n data structure parameter.
+ *
+ *
+ * @sa adi_spi_MasterReadWrite().
+ * @sa adi_spi_isBufferAvailable()
+ * @sa ADI_SPI_TRANSCEIVER
+ */
+
+ADI_SPI_RESULT adi_spi_MasterSubmitBuffer (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr)
+{
+    ADI_SPI_RESULT result = ADI_SPI_SUCCESS;
+    volatile uint16_t nStatus;
+
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+
+    if ((NULL == pXfr->pTransmitter) && (NULL == pXfr->pReceiver))
+    {
+        return ADI_SPI_INVALID_POINTER;
+    }
+    
+    if( (pXfr->bRD_CTL == true) && (pXfr->TransmitterBytes > 16u))
+    {
+      return ADI_SPI_INVALID_PARAM;
+    }
+
+#endif /* ADI_DEBUG */
+
+    /* Initialize the transaction. 'hDevice' must hold the transaction values as pXfr is owned by the application */
+    hDevice->pTxBuffer    = pXfr->pTransmitter;
+    hDevice->pRxBuffer    = pXfr->pReceiver;
+    hDevice->TxRemaining  = pXfr->TransmitterBytes;
+    hDevice->RxRemaining  = pXfr->ReceiverBytes;
+    hDevice->TxIncrement  = (uint8_t)pXfr->nTxIncrement;
+    hDevice->RxIncrement  = (uint8_t)pXfr->nRxIncrement;
+    hDevice->bDmaMode     = pXfr->bDMA;
+    hDevice->bRdCtlMode   = pXfr->bRD_CTL;
+    hDevice->bTransferComplete   = false;
+    hDevice->HWErrors            = ADI_SPI_HW_ERROR_NONE;
+
+    
+    /* 
+     *
+     * TIM
+     *   If set:   initiate transfer with write to SPI_TX register
+     *   If clear:  initiate transfer with a read from SPI_RX register
+     *
+     * RFLUSH
+     *   Clear this bit to ensure that incoming data is ignored
+     *
+     * TFLUSH
+     *   Clear this not to ensure that transmitted data is not a zero (if SPI_CTL.ZEN is set) or last transmitted byte
+     *
+     */
+    
+
+    hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_TIM | BITM_SPI_CTL_RFLUSH | BITM_SPI_CTL_TFLUSH);
+
+    /*
+     * If in DMA mode then make sure XFRDONE interrupt is not set. DMA mode will generate three interrupts
+     *   TX DMA
+     *   RX DMA
+     *   XFRDONE
+     *
+     * There is a race condition between XFRDONE and DMA interrupts. They are on different clocks.
+     * 
+     * SPI XfrDone is counted on SPI clock (SCL) edge, which is a fixed timing related to SPI bit protocol. 
+     * But the DMA works upon system clock (HCLK) and it could finish on various timing upon SCL/HCLK ratio.
+     * And bus bandwidth (e.g., DMA hold off until processor frees up the bus). So SPI RX DMA done interrupt 
+     * could be issued earlier or later than SPI XferDone interrupt.
+     *
+     */
+    if( hDevice->bDmaMode==true ) {
+      /* The race condition has been between RX and XFRDONE. If there are no bytes to receive then */
+      /* do not clear XFRDONE                                                                      */
+      if( hDevice->RxRemaining != 0u) {
+        hDevice->pSpi->IEN &= (uint16_t)~(BITM_SPI_IEN_XFRDONE);
+      } else {
+        hDevice->pSpi->IEN |= (BITM_SPI_IEN_XFRDONE);
+      }
+      
+    } else {
+      
+      /* In interrupt mode always enable XFRDONE */
+      uint16_t activeInterrupts = BITM_SPI_IEN_XFRDONE;
+      /* Enable underflow on;y if sending bytes */
+      if( hDevice->TxRemaining ) {
+        activeInterrupts |= BITM_SPI_IEN_TXUNDR;
+      }
+      /* Enable overflow only if receiving bytes */
+      if( hDevice->RxRemaining ) {
+        activeInterrupts |= BITM_SPI_IEN_RXOVR;
+      }
+      
+      hDevice->pSpi->IEN |= activeInterrupts;
+      
+      /* 
+       * In interrupt mode, when there is nothing to receive, need to initiate a transaction
+       * on an TX write only. Initiating on an RX read will start the transaction, but just for
+       * a single byte (and we're not sure why this is true)
+       */
+      
+      if( hDevice->RxRemaining == 0u) {
+        hDevice->pSpi->CTL |= ( BITM_SPI_CTL_TIM ); 
+      }
+        
+    }
+
+
+    /* STAT bits are cleared by writing a '1' to them. Clear any residual status*/
+    nStatus = hDevice->pSpi->STAT;
+    hDevice->pSpi->STAT = nStatus;
+
+    /* Make sure we are in master mode */
+    hDevice->pSpi->CTL |= ( BITM_SPI_CTL_MASEN);
+
+    /* Set ChipSelect */
+    hDevice->pSpi->CS_CTL  = hDevice->ChipSelect;
+  
+    StartTransaction(hDevice, pXfr);
+    
+    
+    /* block if required  */
+    if (hDevice->bBlockingMode == true)
+    {
+	SEM_PEND(hDevice,ADI_SPI_PEND_FAILED);
+    }
+    
+    return result;
+}
+
+/*********************************************************************************************************/
+/*                                                                                                       */
+/*                        SPI DRIVER Master Mode transaction start                                       */
+/*                                                                                                       */
+/*********************************************************************************************************/
+
+static void StartTransaction(ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr)
+{ 
+    /* Transaction completion is determined by the number of bytes to be received */
+    uint16_t nCount;
+    
+    /* Effectively flush the FIFOs before the start of the next transaction */
+    hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH);
+    hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH);
+
+    /* Disable any prior notion of DMA */    
+    hDevice->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
+
+   
+    /*
+     * If the transaction is DMA based then set up the DMA descriptors for this transaction
+     */
+
+    uint16_t dmaFlags = 0u;
+    
+    if( hDevice->bDmaMode == true) 
+    {
+      dmaFlags = BITM_SPI_DMA_EN;
+
+      uint16_t sz = pXfr->TransmitterBytes;
+      if( sz )
+      {
+        uint16_t TxChanNum = hDevice->pDevInfo->dmaTxChannelNumber;
+    
+        /* Enable the interrupt for the given DMA */
+        NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaTxIrqNumber));
+
+        /* Disables source address decrement for TX channel */
+        pADI_DMA0->SRCADDR_CLR = 1U << TxChanNum;
+      
+        /* Enable the channel */
+        pADI_DMA0->EN_SET = 1U << TxChanNum;
+          
+        /* Enables SPI peripheral to generate DMA requests. */
+        pADI_DMA0->RMSK_CLR = 1U << TxChanNum;
+
+        /* Set the primary as the current DMA descriptor */
+        pADI_DMA0->ALT_CLR = 1U << TxChanNum;
+     
+        /* fill in the DMA RAM descriptors */
+        if( (sz & 1U) != 0u )
+        {
+          /* DMA is performed on 16-bit data. Make sure the DMA engine is properly aligned to even counts */
+          /* The SPI_CNT register will hold the "real" transfer count                                     */
+          sz++;
+        }
+        
+        pPrimaryCCD[TxChanNum].DMASRCEND =   (uint32_t)(pXfr->pTransmitter + (sz - 2U));
+              
+        pPrimaryCCD[TxChanNum].DMADSTEND =   (uint32_t)&hDevice->pSpi->TX;
+
+        pPrimaryCCD[TxChanNum].DMACDC = ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) |
+                              (ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_SRC_INC) |
+                              (ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) |
+                              ((sz/2U -1U)<< DMA_BITP_CTL_N_MINUS_1) |
+                              (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
+      
+        dmaFlags |= (BITM_SPI_DMA_TXEN);
+      }
+
+      sz = pXfr->ReceiverBytes;
+      if( sz )
+      {
+        
+        uint16_t RxChanNum = hDevice->pDevInfo->dmaRxChannelNumber;
+        NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaRxIrqNumber));
+
+        /* Disables destination address decrement for RX channel */
+        pADI_DMA0->DSTADDR_CLR = 1U << RxChanNum;
+        
+        /* Enable the channel */
+        pADI_DMA0->EN_SET = 1U << RxChanNum;
+        
+        /* Enables SPI peripheral to generate DMA requests. */
+        pADI_DMA0->RMSK_CLR = 1U << RxChanNum;
+
+        /* Set the primary as the current DMA descriptor */
+        pADI_DMA0->ALT_CLR = 1U << RxChanNum;
+        
+        if( (sz & 1U) != 0u )
+        {
+          /* DMA is performed on 16-bit data. Make sure the DMA engine is properly aligned to even counts */
+          /* The SPI_CNT register will hold the "real" transfer count                                     */
+          sz++;
+        }
+        
+        pPrimaryCCD[RxChanNum].DMASRCEND =   (uint32_t)&hDevice->pSpi->RX;
+              
+        pPrimaryCCD[RxChanNum].DMADSTEND =   (uint32_t)(pXfr->pReceiver + (sz - 2U));
+
+        pPrimaryCCD[RxChanNum].DMACDC = (ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_DST_INC) |
+                              (ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) |
+                              (ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) |
+                              ((sz/2U -1U) << DMA_BITP_CTL_N_MINUS_1) |
+                              (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
+        
+        dmaFlags |= (BITM_SPI_DMA_RXEN );
+
+      }
+    }
+
+    /*
+     * SPI CNT register
+     *     Non Read Mode:  Size of the entire transactions
+     *     Read Mode: Size of the RX transaction 
+     *
+     * RD_CTL.SZ
+     *     Read Mode: Size of the TX transaction
+     */
+    
+    hDevice->pSpi->RD_CTL = 0u;
+    if( hDevice->bRdCtlMode)
+    {
+      /* "Half Duplex Mode" */
+      
+      /* The number of bytes to be transmitted */
+      uint32_t nBytes = hDevice->TxRemaining - 1U;
+      
+      /* Enable RD_CTL and set the TX count for the half-duplex mode of operation */
+      hDevice->pSpi->RD_CTL &=  (uint16_t)~((uint16_t)(BITM_SPI_RD_CTL_TXBYTES <<  BITP_SPI_RD_CTL_TXBYTES));
+
+      hDevice->pSpi->RD_CTL |=  (uint16_t)( (uint16_t)(nBytes << BITP_SPI_RD_CTL_TXBYTES) |
+                                            (uint16_t)(1 << BITP_SPI_RD_CTL_CMDEN));
+      
+      /* RD_CTL requires continuous mode operation. */
+      hDevice->pSpi->CTL |= (BITM_SPI_CTL_CON);
+
+      /* CNT represent the number of bytes to receive */
+      hDevice->pSpi->CNT =  hDevice->RxRemaining;
+      
+    }
+    else
+    {
+      /* Full duplex mode of operation */
+      if(hDevice->RxRemaining == 0u)
+      {
+        /* There is nothing to receive. Flush the RX FIFO and to ignore all incoming data */
+         hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH);
+      } 
+      else if(hDevice->TxRemaining == 0u)
+      {
+        /* If there is nothing to transmit then clear the TX FIFO */
+        hDevice->pSpi->CTL |= (BITM_SPI_CTL_TFLUSH);
+      }
+      else
+      {
+        /* Misra compliance: All if/else chains should end with a final else clause */
+      }
+      
+      /* Set CNT to MAX of RX/TX */
+
+      nCount = hDevice->RxRemaining >  hDevice->TxRemaining ? hDevice->RxRemaining : hDevice->TxRemaining;
+      hDevice->pSpi->CNT = (uint16_t)nCount;
+
+    }
+    
+    
+    if( hDevice->bDmaMode == false) 
+    {
+      /* Make sure that the application passed in a TX Buffer */
+      if( hDevice->pTxBuffer != NULL)
+      {
+        /* interrupt mode: Fill in the FIFO  */
+        nCount = 0u;
+        while((nCount < ADI_SPI_FIFO_SIZE) && (hDevice->TxRemaining != 0u))
+        {
+            /* grab the lead byte */
+            hDevice->pSpi->TX = *hDevice->pTxBuffer;
+            /* modify tx pointer and buffer count prior to interrupt */
+            hDevice->pTxBuffer += hDevice->TxIncrement;
+            /* decrement the byte count */
+            hDevice->TxRemaining--;
+            nCount++;
+        }
+      }
+      
+    } else {
+      
+      hDevice->pSpi->DMA |= dmaFlags;
+    }
+    
+    if((hDevice->pSpi->CTL & BITM_SPI_CTL_TIM) != BITM_SPI_CTL_TIM)
+    {
+      uint16_t byte ADI_UNUSED_ATTRIBUTE = hDevice->pSpi->RX;
+    }
+    
+    
+    NVIC_EnableIRQ(hDevice->pDevInfo->eIRQn);
+   
+    return;
+}
+
+/*!
+ * @brief  Block until the SPI transaction is complete.
+ *
+ * @param[in]     hDevice      Device handle obtained from adi_spi_Open().
+ *\n
+ * @param[out]   pHWErrors     Pointer to hardware error return variable.
+ *\n
+ * @return         Status
+ *                - #ADI_SPI_SUCCESS                    Call completed successfully.
+ *                - #ADI_SPI_SEMAPHORE_FAILED           Semaphore Pend failed
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *
+ * @sa        adi_spi_MasterSubmitBuffer().
+ * @sa        adi_spi_SlaveSubmitBuffer().
+ */
+ADI_SPI_RESULT adi_spi_GetBuffer(
+               ADI_SPI_HANDLE const hDevice,
+               uint32_t * const pHWErrors
+              )
+{
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        *pHWErrors = ADI_SPI_HW_ERROR_NONE;
+        return ADI_SPI_INVALID_HANDLE;
+    }
+#endif
+
+    SEM_PEND(hDevice,ADI_SPI_SEMAPHORE_FAILED);
+    *pHWErrors = hDevice->HWErrors;
+    return(ADI_SPI_SUCCESS);
+}
+
+/*!
+ * @brief  Get the SPI transaction completion status.
+ *
+ * @param[in]     hDevice      Device handle obtained from adi_spi_Open().
+ *\n
+ * @param[out] bComplete      Pointer to boolean variable that indicates
+ *\n                - true    DMA transmit sequence is complete.
+ *\n                - false   DMA transmit sequence is incomplete.
+ *\n
+ * @return         Status
+ *                - #ADI_SPI_SUCCESS                    Call completed successfully.
+ *                - #ADI_SPI_INVALID_HANDLE [D]         Invalid device handle parameter.
+ *
+ * @sa        adi_spi_MasterSubmitBuffer().
+ * @sa        adi_spi_SlaveSubmitBuffer().
+ */
+
+ADI_SPI_RESULT  adi_spi_isBufferAvailable(ADI_SPI_CONST_HANDLE const hDevice,  bool* const bComplete)
+{
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+#endif
+
+    *bComplete = hDevice->bTransferComplete;
+    return(ADI_SPI_SUCCESS);
+}
+
+/*!
+ * @brief  Submit data buffers for SPI Slave-Mode transaction.
+ *
+ * @param[in]     hDevice     Device handle obtained from adi_spi_Open().
+ * @param[in]     pXfr        Pointer to transfer data struct.
+  *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]        Invalid device handle parameter.
+ *                - #ADI_SPI_IN_USE [D]    DMA transaction already under way.
+ *                - #ADI_SPI_INVALID_POINTER [D]     Invalid data pointer detected (NULL).
+ *                - #ADI_SPI_INVALID_PARAM [D]    Invalid size parameter detected (0).
+ *                - #ADI_SPI_SUCCESS                       Call completed successfully.
+ *
+ *\n Request a non-blocking transmit and receive of multiple data bytes
+ *\n over the SPI serial channel.  Honours current blocking and DMA modes.
+ *\n Buffer allocations are made by the calling code (the application).
+ *\n
+ *\n The transmit buffer is sent and the receive buffer is written according
+ *\n to the size and increment information contained by the \a pXft transfer
+ *\n data structure parameter.
+ *\n
+ *\n The application must make a call to adi_spi_GetBuffer() to retrieve the buffer
+ *\n
+ *\n @note:
+ *
+ * @sa adi_spi_MasterReadWrite().
+ * @sa adi_spi_EnableDmaMode().
+ * @sa adi_spi_isBufferAvailable().
+ * @sa adi_spi_GetBuffer().
+ */
+ADI_SPI_RESULT adi_spi_SlaveSubmitBuffer (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr)
+{
+    volatile uint16_t ADI_UNUSED_ATTRIBUTE byte;
+    uint32_t nCount = 0u;
+    
+#ifdef ADI_DEBUG
+    if (ADI_SPI_VALIDATE_HANDLE(hDevice))
+    {
+        return ADI_SPI_INVALID_HANDLE;
+    }
+    if ((NULL == pXfr->pTransmitter) && (NULL == pXfr->pReceiver))
+    {
+        return ADI_SPI_INVALID_POINTER;
+    }
+    
+    if ((0u == pXfr->pTransmitter) && (0u == pXfr->pReceiver) )
+    {
+        return ADI_SPI_INVALID_PARAM;
+    }
+    /* Return error if the RX buffer is not null and count is equal to zero or vice versa.*/
+    if (((pXfr->pReceiver != NULL) && (pXfr->ReceiverBytes == 0u)) || ((pXfr->pReceiver == NULL) && ((pXfr->ReceiverBytes > 0u))))
+    {
+        return ADI_SPI_INVALID_PARAM;
+    }
+    
+    /* Return error if the Tx buffer is not null and count is equal to zero or vice versa.*/
+    if (((pXfr->pTransmitter != NULL) && (pXfr->TransmitterBytes == 0u)) || ((pXfr->pTransmitter == NULL) && (pXfr->TransmitterBytes > 0u)))
+    {
+        return ADI_SPI_INVALID_PARAM;
+    }
+
+    /* DMA count register is only 8 bits, so block size is limited to 255 */
+    if ((pXfr->bDMA==true) && (pXfr->TransmitterBytes != 0u) &&(((uint32_t)pXfr->pTransmitter&0x1U) !=0u ) )
+    {
+        return ADI_SPI_INVALID_PARAM;
+    }
+
+#endif /* ADI_DEBUG */
+
+    /* Effectively flush the FIFOs before the start of the next transaction */
+    hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH);
+    hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH);
+
+    /* Shut down any DMA enables that are still lingering from a prior transaction */
+    hDevice->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
+    
+    hDevice->bTransferComplete   = false;
+    hDevice->pTxBuffer           = pXfr->pTransmitter;
+    hDevice->pRxBuffer           = pXfr->pReceiver;
+    hDevice->TxRemaining         = pXfr->TransmitterBytes;
+    hDevice->RxRemaining         = pXfr->ReceiverBytes;
+    hDevice->TxIncrement         = (uint8_t)pXfr->nTxIncrement;
+    hDevice->RxIncrement         = (uint8_t)pXfr->nRxIncrement;
+    hDevice->pSpi->CNT           = (uint16_t)nCount;
+    hDevice->bDmaMode            = pXfr->bDMA;
+    hDevice->bRdCtlMode          = pXfr->bRD_CTL;
+    hDevice->HWErrors            = ADI_SPI_HW_ERROR_NONE;
+
+    
+    /* Configure SPI. First step is to clear CTL bits that may have been set previously  */
+    hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_TIM | BITM_SPI_CTL_RFLUSH | BITM_SPI_CTL_TFLUSH | BITM_SPI_CTL_CON);
+    if( hDevice->TxRemaining == 0u )
+    {
+      /* This will prevent TX underflow interrupts from occurring */
+      hDevice->pSpi->CTL |= BITM_SPI_CTL_TFLUSH;
+    }
+    if( hDevice->RxRemaining == 0u )
+    {
+      /* This will prevent data from entering RX. Also prevents overflow interrupts from occurring */
+      hDevice->pSpi->CTL |= BITM_SPI_CTL_RFLUSH;
+      
+      /* If SPI_CTL.TIM is set, the Tx FIFO status causes the interrupt. */
+      if( hDevice->bDmaMode != true) {
+        hDevice->pSpi->CTL |= BITM_SPI_CTL_TIM;
+      }
+      
+    }
+      
+    hDevice->pSpi->CNT    = (uint16_t) hDevice->TxRemaining > hDevice->RxRemaining ? hDevice->TxRemaining : hDevice->RxRemaining;
+    
+    uint16_t nDMAFlags = 0u;
+      
+    if( hDevice->bDmaMode == true) 
+    {
+      uint16_t sz = pXfr->TransmitterBytes;
+      if( sz )
+      {
+        uint16_t TxChanNum = hDevice->pDevInfo->dmaTxChannelNumber;
+    
+        /* Enable the interrupt for the given DMA */
+        NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaTxIrqNumber));
+
+        /* Disables source address decrement for TX channel */
+        pADI_DMA0->SRCADDR_CLR = 1U << TxChanNum;
+      
+        /* Enable the channel */
+        pADI_DMA0->EN_SET = 1U << TxChanNum;
+          
+        /* Enables SPI peripheral to generate DMA requests. */
+        pADI_DMA0->RMSK_CLR = 1U << TxChanNum;
+
+        /* Set the primary as the current DMA descriptor */
+        pADI_DMA0->ALT_CLR = 1U << TxChanNum;
+     
+        /* fill in the DMA RAM descriptors */
+        if( (sz & 1U) != 0u )
+        {
+          /* DMA is performed on 16-bit data. Make sure the DMA engine is properly aligned to even counts */
+          /* The SPI_CNT register will hold the "real" transfer count                                     */
+          sz++;
+        }
+        
+        pPrimaryCCD[TxChanNum].DMASRCEND =   (uint32_t)(pXfr->pTransmitter + (sz - 2U));
+              
+        pPrimaryCCD[TxChanNum].DMADSTEND =   (uint32_t)&hDevice->pSpi->TX;
+
+        pPrimaryCCD[TxChanNum].DMACDC = ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) |
+                              (ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_SRC_INC) |
+                              (ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) |
+                              ((sz/2U -1U)<< DMA_BITP_CTL_N_MINUS_1) |
+                              (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
+      
+        nDMAFlags |= (BITM_SPI_DMA_TXEN);
+      }
+
+      sz = pXfr->ReceiverBytes;
+      if( sz )
+      {
+        
+        uint16_t RxChanNum = hDevice->pDevInfo->dmaRxChannelNumber;
+        NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaRxIrqNumber));
+
+        /* Disables destination address decrement for RX channel */
+        pADI_DMA0->DSTADDR_CLR = 1U << RxChanNum;
+        
+        /* Enable the channel */
+        pADI_DMA0->EN_SET = 1U << RxChanNum;
+        
+        /* Enables SPI peripheral to generate DMA requests. */
+        pADI_DMA0->RMSK_CLR = 1U << RxChanNum;
+
+        /* Set the primary as the current DMA descriptor */
+        pADI_DMA0->ALT_CLR = 1U << RxChanNum;
+        
+        if( (sz & 1U) != 0u )
+        {
+          /* DMA is performed on 16-bit data. Make sure the DMA engine is properly aligned to even counts */
+          /* The SPI_CNT register will hold the "real" transfer count                                     */
+          sz++;
+        }
+        
+        pPrimaryCCD[RxChanNum].DMASRCEND =   (uint32_t)&hDevice->pSpi->RX;
+              
+        pPrimaryCCD[RxChanNum].DMADSTEND =   (uint32_t)(pXfr->pReceiver + (sz - 2U));
+
+        pPrimaryCCD[RxChanNum].DMACDC = (ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_DST_INC) |
+                              (ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) |
+                              (ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) |
+                              ((sz/2U -1U) << DMA_BITP_CTL_N_MINUS_1) |
+                              (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
+        
+        nDMAFlags |= (BITM_SPI_DMA_RXEN );
+
+      }
+    }
+
+    /* Make sure XFRDONE is shut down. This IEN has no affect in slave mode */
+    hDevice->pSpi->IEN &= (uint16_t)~BITM_SPI_IEN_XFRDONE;
+
+    if( hDevice->bDmaMode == false) {
+      /* Make sure we are not in continuous mode from a prior DMA transaction  */
+      hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CON;
+
+    
+      /* interrupt mode: Enable the UNDERFLOW and OVERFLOW interrupts */
+      /* XFRDONE is invalid in slave mode */
+      uint16_t activeInterrupts = 0u;
+      /* Enable underflow on;y if sending bytes */
+      if( hDevice->TxRemaining ) {
+        activeInterrupts |= BITM_SPI_IEN_TXUNDR;
+      }
+      /* Enable overflow only if receiving bytes */
+      if( hDevice->RxRemaining ) {
+        activeInterrupts |= BITM_SPI_IEN_RXOVR;
+      }
+      hDevice->pSpi->IEN |= activeInterrupts;
+
+      /* interrupt mode: Fill in the FIFO and enable the TX by a dummy read. */
+      while((nCount < ADI_SPI_FIFO_SIZE) && (hDevice->TxRemaining != 0u))
+      {
+          /* grab the lead byte */
+          hDevice->pSpi->TX = *hDevice->pTxBuffer;
+          /* modify tx pointer and buffer count prior to interrupt */
+          hDevice->pTxBuffer += hDevice->TxIncrement;
+          /* decrement the byte count */
+          hDevice->TxRemaining--;
+          nCount++;
+      }
+    } else {
+
+      /* DMA mode. Enable the controller */
+      hDevice->pSpi->DMA |= (uint16_t)(BITM_SPI_DMA_EN | nDMAFlags);
+    }
+     
+    if((hDevice->pSpi->CTL & BITM_SPI_CTL_TIM) != BITM_SPI_CTL_TIM)
+    {
+         byte = hDevice->pSpi->RX;    
+    }
+    NVIC_EnableIRQ(hDevice->pDevInfo->eIRQn);
+
+    if (hDevice->bBlockingMode == true)
+    {
+	SEM_PEND(hDevice,ADI_SPI_SEMAPHORE_FAILED);
+    }
+
+    return ADI_SPI_SUCCESS;
+}
+
+
+
+/*!
+ * @brief  Submit data buffers for SPI Slave-Mode transaction in "Blocking mode".This function
+ *\n          returns only after the data transfer is complete
+ *
+ * @param[in]     hDevice     Device handle obtained from adi_spi_Open().
+ * @param[in]     pXfr        Pointer to transfer data struct #ADI_SPI_TRANSCEIVER.
+  *
+ * @return         Status
+ *                - #ADI_SPI_INVALID_HANDLE [D]        Invalid device handle parameter.
+ *                - #ADI_SPI_BUFFER_NOT_SUBMITTED [D]  Failed to submit the buffer.
+ *                - #ADI_SPI_INVALID_POINTER [D]       Invalid data pointer detected (NULL).
+ *                - #ADI_SPI_INVALID_PARAM [D]         Invalid size parameter detected (0).
+ *                - #ADI_SPI_SUCCESS                   Call completed successfully.
+ *
+ *\n
+ *\n Request a non-blocking mode transmit and receive of multiple data bytes
+ *\n over the SPI serial channel.  
+ *\n Buffer allocations are made by the calling code (the application).
+ *\n
+ *\n The transmit buffer is sent and the receive buffer is written according
+ *\n to the size and increment information contained by the \a pXft transfer
+ *\n data structure parameter.
+ *\n
+ *\n
+ * @sa adi_spi_SlaveSubmitBuffer().
+ * @sa ADI_SPI_TRANSCEIVER
+ */
+ADI_SPI_RESULT adi_spi_SlaveReadWrite (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr)
+{
+    ADI_SPI_RESULT eResult;
+    hDevice->bBlockingMode = true;
+    eResult = adi_spi_SlaveSubmitBuffer(hDevice,pXfr);
+    hDevice->bBlockingMode = false;
+    if( (eResult == ADI_SPI_SUCCESS) && (hDevice->HWErrors != 0u))
+    {
+      eResult = ADI_SPI_HW_ERROR_OCCURRED;
+    }
+    return(eResult);
+}
+
+/*
+ *****************************************************************************
+ * SPI Internal Static Support Functions
+ *****************************************************************************/
+
+
+ /*! \cond PRIVATE */
+
+
+/*-----------------------------------------------------------------------------
+ *
+ * SPI ISR
+ *
+ *----------------------------------------------------------------------------*/
+
+
+
+static void common_SPI_Int_Handler (ADI_SPI_DEV_DATA_TYPE* pDD)
+{
+   
+  /* read status register - first thing */
+  volatile  uint16_t nFifoStatus = pDD->pSpi->FIFO_STAT;
+  uint16_t nErrorStatus = pDD->pSpi->STAT;
+
+  uint16_t writableBytes;
+  uint16_t readableBytes;
+
+
+  
+  /* Trap overflow/underflow errors and terminate the current transaction if there is an error. */
+  if(  BITM_SPI_STAT_RXOVR == (BITM_SPI_STAT_RXOVR & nErrorStatus)) {
+      pDD->HWErrors |= (uint32_t)ADI_SPI_HW_ERROR_RX_OVERFLOW;
+  } else if( BITM_SPI_STAT_TXUNDR == (BITM_SPI_STAT_TXUNDR & nErrorStatus)) {
+      pDD->HWErrors |= (uint32_t)ADI_SPI_HW_ERROR_TX_UNDERFLOW;
+  }
+  else
+  {
+    
+    /* calculate number of bytes that can be written to tx fifo */
+    writableBytes = ADI_SPI_FIFO_SIZE - ((BITM_SPI_FIFO_STAT_TX & nFifoStatus) >> BITP_SPI_FIFO_STAT_TX);
+    /* calculate number of bytes to read from rx fifo */
+    readableBytes = ((BITM_SPI_FIFO_STAT_RX & nFifoStatus) >> BITP_SPI_FIFO_STAT_RX);
+    
+    /* fill tx fifo */
+    while ((writableBytes != 0u) && (pDD->TxRemaining != 0u))
+    {
+      pDD->pSpi->TX = *pDD->pTxBuffer;
+      pDD->pTxBuffer  += pDD->TxIncrement;
+      pDD->TxRemaining--;
+      writableBytes--;
+    }
+    
+    /*
+     * Now focus on the RX FIFO but only if we are not in RD_CTL mode OR, if we
+     * are in RD_CTL mode, TX bytes are all transmitted 
+     */
+    
+    if( (pDD->bRdCtlMode==false) || (pDD->TxRemaining==0u) )
+    {
+      /* empty rx fifo */
+      while ((readableBytes != 0u) &&(pDD->RxRemaining != 0u))
+      {
+      
+        *pDD->pRxBuffer = (uint8_t) pDD->pSpi->RX;
+        pDD->pRxBuffer += pDD->RxIncrement;
+        pDD->RxRemaining--;
+        readableBytes--;
+      }
+    }
+  }
+
+  
+  /* Terminate the transaction and notify the caller 
+   *   1) Master mode: If there are no more bytes to RX or TX and XFRDONE is set
+   *   2) Slave mode: If there are no more bytes to RX or TX  (XFRDONE is invalid in slave mode)
+   *   3) If there was a HW error 
+   */
+  bool terminate = false;
+  if( (pDD->RxRemaining == 0u) && (pDD->TxRemaining == 0u))
+  {
+    if( BITM_SPI_CTL_MASEN == (pDD->pSpi->CTL & BITM_SPI_CTL_MASEN ))
+    {
+      /* Master mode */
+      if( BITM_SPI_STAT_XFRDONE == (pDD->pSpi->STAT & BITM_SPI_STAT_XFRDONE ))
+      {
+        /* Master mode XFRDONE */
+        terminate = true;
+      }
+    } else {
+      /* Slave mode - we're all done here */
+        terminate = true;
+    }
+  }
+
+  if( terminate || (pDD->HWErrors != (uint32_t)ADI_SPI_HW_ERROR_NONE))  
+  {
+      
+    /* Clear possible interrupt sources: XFRDONE and underflow and overflow */  
+    pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR);  
+    pDD->bTransferComplete  = true;
+    NVIC_DisableIRQ(pDD->pDevInfo->eIRQn);
+    
+    /* If a callback is registered notify the buffer processed event to the application */
+    if(NULL != pDD->pfCallback ){
+        pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
+    }
+    else
+    {
+        SEM_POST(pDD);
+    }
+      
+  }
+  
+  /* All interrupts are cleared by a write of 1 to the status register bits (W1C)  */
+  pDD->pSpi->STAT = nErrorStatus;
+
+#if defined(ADI_CYCLECOUNT_SPI_ISR_ENABLED) && (ADI_CYCLECOUNT_SPI_ISR_ENABLED == 1u)
+  ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_SPI);    
+#endif
+
+
+  
+}
+
+
+/* Internal DMA Callback for receiving DMA faults from common DMA error handler. */
+static void RxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) {
+
+    /* Recover the device handle. */
+    ADI_SPI_HANDLE hDevice = (ADI_SPI_HANDLE) pCBParam;
+
+    /* Save the DMA error. */
+    switch (Event) {
+        case ADI_DMA_EVENT_ERR_BUS:
+            hDevice->HWErrors |= ADI_SPI_HW_ERROR_RX_CHAN_DMA_BUS_FAULT;
+            break;
+        case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR:
+            hDevice->HWErrors |= ADI_SPI_HW_ERROR_RX_CHAN_DMA_INVALID_DESCR;
+            break;
+        default:
+            hDevice->HWErrors |= ADI_SPI_HW_ERROR_RX_CHAN_DMA_UNKNOWN_ERROR;
+            break;
+    }
+}
+
+
+/* Internal DMA Callback for receiving DMA faults from common DMA error handler. */
+static void TxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) {
+
+    /* Recover the device handle. */
+    ADI_SPI_HANDLE hDevice = (ADI_SPI_HANDLE) pArg;
+
+    /* Save the DMA error. */
+    switch (Event) {
+        case ADI_DMA_EVENT_ERR_BUS:
+            hDevice->HWErrors |= ADI_SPI_HW_ERROR_TX_CHAN_DMA_BUS_FAULT;
+            break;
+        case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR:
+            hDevice->HWErrors |= ADI_SPI_HW_ERROR_TX_CHAN_DMA_INVALID_DESCR;
+            break;
+        default:
+            hDevice->HWErrors |= ADI_SPI_HW_ERROR_TX_CHAN_DMA_UNKNOWN_ERROR;
+            break;
+    }   
+}
+
+
+/*!
+ * @brief  SPI0 Interrupt Handler.
+ *
+ * @return void.
+ *
+ * Overrides default SPI0 interrupt handler.
+ */
+void SPI0_Int_Handler(void) {
+    ISR_PROLOG();
+    common_SPI_Int_Handler(spi_device_info[0].hDevice );
+    ISR_EPILOG();
+}
+
+
+/*!
+ * @brief  SPI1 Interrupt Handler.
+ *
+ * @return void.
+ *
+ * Overrides default SPI1 interrupt handler.
+ */
+void SPI1_Int_Handler(void) {
+    ISR_PROLOG();
+    common_SPI_Int_Handler(spi_device_info[1].hDevice);
+    ISR_EPILOG();
+}
+
+/*!
+ * @brief  SPI2 Interrupt Handler.
+ *
+ * @return void.
+ *
+ * Overrides default SPI2 interrupt handler.
+ */
+void SPI2_Int_Handler(void) {
+    ISR_PROLOG();    
+    common_SPI_Int_Handler(spi_device_info[2].hDevice );
+    ISR_EPILOG();
+}
+
+
+/*
+    //////////////////////////////////////////////////////////////////////////////
+    //////////////////////////   DMA-RELATED   ///////////////////////////////////
+    //////////////////////////////////////////////////////////////////////////////
+*/
+
+
+/*
+ * SPI DMA interrupt handlers
+ */
+
+
+#if defined(ADI_SPI0_MASTER_MODE) && (ADI_SPI0_MASTER_MODE==1u)
+void DMA_SPI0_TX_Int_Handler(void)  
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[0].hDevice;
+   pDD->TxRemaining = 0u;
+   ISR_EPILOG();       
+}
+
+/* Master mode DMA ISR */
+void DMA_SPI0_RX_Int_Handler(void)  
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[0].hDevice;
+   pDD->RxRemaining = 0u;
+   /* Disable DMA */
+   pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
+   /* Master mode: Now allow the XFRDONE interrupt to occur. It's the SPI ISR that really ends the transaction */
+   /* The slave mode is not affected by this setting */
+   pDD->pSpi->IEN |= BITM_SPI_IEN_XFRDONE;
+   ISR_EPILOG();       
+}
+#endif
+#if defined(ADI_SPI0_MASTER_MODE) && (ADI_SPI0_MASTER_MODE==0u)
+/* Slave mode DMA ISRs */
+void DMA_SPI0_TX_Int_Handler(void)  
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[0].hDevice;
+   pDD->TxRemaining = 0u;
+   if( pDD->RxRemaining == 0)
+   {
+     /* If a callback is registered notify the buffer processed event to the application */
+     if(NULL != pDD->pfCallback ){
+         pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
+     }
+     else
+     {
+         SEM_POST(pDD);
+     }
+   }
+   ISR_EPILOG();       
+}
+void DMA_SPI0_RX_Int_Handler(void)  
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[0].hDevice;
+   pDD->RxRemaining = 0u;
+   /* Disable DMA */
+   pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
+   pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR);  
+   pDD->bTransferComplete  = true;
+   NVIC_DisableIRQ(pDD->pDevInfo->eIRQn);
+    
+   /* If a callback is registered notify the buffer processed event to the application */
+   if(NULL != pDD->pfCallback ){
+       pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
+   }
+   else
+   {
+       SEM_POST(pDD);
+   }
+   ISR_EPILOG();       
+}
+#endif
+
+
+
+
+#if defined(ADI_SPI1_MASTER_MODE) && (ADI_SPI1_MASTER_MODE==1u)
+/* Master mode DMA ISR */
+void DMA_SPI1_TX_Int_Handler(void) 
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[1].hDevice;
+   pDD->TxRemaining = 0u;
+   ISR_EPILOG();       
+}
+
+void DMA_SPI1_RX_Int_Handler(void)  
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[1].hDevice;
+   pDD->RxRemaining = 0u;
+   /* Disable DMA */
+   pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
+   /* Master mode: Now allow the XFRDONE interrupt to occur. It's the SPI ISR that really ends the transaction */
+   /* The slave mode is not affected by this setting */
+   pDD->pSpi->IEN |= BITM_SPI_IEN_XFRDONE;
+   ISR_EPILOG();       
+}
+#endif
+
+
+#if defined(ADI_SPI1_MASTER_MODE) && (ADI_SPI1_MASTER_MODE==0u)
+/* Slave mode DMA ISRs */
+void DMA_SPI1_TX_Int_Handler(void) 
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[1].hDevice;
+   pDD->TxRemaining = 0u;
+   if( pDD->RxRemaining == 0)
+   {
+     /* If a callback is registered notify the buffer processed event to the application */
+     if(NULL != pDD->pfCallback ){
+         pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
+     }
+     else
+     {
+         SEM_POST(pDD);
+     }
+   }
+   ISR_EPILOG();       
+}
+
+
+void DMA_SPI1_RX_Int_Handler(void)  
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[1].hDevice;
+   pDD->RxRemaining = 0u;
+   /* Disable DMA */
+   pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
+   pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR);  
+   pDD->bTransferComplete  = true;
+   NVIC_DisableIRQ(pDD->pDevInfo->eIRQn);
+    
+   /* If a callback is registered notify the buffer processed event to the application */
+   if(NULL != pDD->pfCallback ){
+       pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
+   }
+   else
+   {
+       SEM_POST(pDD);
+   }
+   ISR_EPILOG();       
+}
+#endif
+
+
+#if defined(ADI_SPI2_MASTER_MODE) && (ADI_SPI2_MASTER_MODE==1u)
+/* Master mode DMA ISR */
+
+void DMA_SPIH_TX_Int_Handler(void)  
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[2].hDevice;
+   pDD->TxRemaining = 0u;
+   ISR_EPILOG();       
+}
+
+void DMA_SPIH_RX_Int_Handler(void)  
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[2].hDevice;
+   pDD->RxRemaining = 0u;
+   /* Disable DMA */
+   pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
+   /* Master mode: Now allow the XFRDONE interrupt to occur. It's the SPI ISR that really ends the transaction */
+   /* The slave mode is not affected by this setting */
+   pDD->pSpi->IEN |= BITM_SPI_IEN_XFRDONE;
+   ISR_EPILOG();       
+}
+#endif
+#if defined(ADI_SPI2_MASTER_MODE) && (ADI_SPI2_MASTER_MODE==0u)
+/* Master mode DMA ISRs */
+
+void DMA_SPIH_TX_Int_Handler(void)  
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[2].hDevice;
+   pDD->TxRemaining = 0u;
+   ISR_EPILOG();       
+   if( pDD->RxRemaining == 0)
+   {
+     /* If a callback is registered notify the buffer processed event to the application */
+     if(NULL != pDD->pfCallback ){
+         pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
+     }
+     else
+     {
+         SEM_POST(pDD);
+     }
+   }
+   ISR_EPILOG();   
+}
+
+void DMA_SPIH_RX_Int_Handler(void)  
+{ 
+   ISR_PROLOG(); 
+   ADI_SPI_HANDLE pDD = spi_device_info[2].hDevice;
+   pDD->RxRemaining = 0u;
+   /* Disable DMA */
+   pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN);
+   pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR);  
+   pDD->bTransferComplete  = true;
+   NVIC_DisableIRQ(pDD->pDevInfo->eIRQn);
+    
+   /* If a callback is registered notify the buffer processed event to the application */
+   if(NULL != pDD->pfCallback ){
+       pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL);
+   }
+   else
+   {
+       SEM_POST(pDD);
+   }
+   ISR_EPILOG();       
+}
+#endif
+
+
+
+
+/*! \endcond */
+
+
+/* @} */
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_data.c
new file mode 100755
index 00000000000..ecbcb00b62e
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_data.c
@@ -0,0 +1,163 @@
+/*
+ *****************************************************************************
+ * @file:    adi_spi_data.c
+ * @brief:   Data declaration for SPORT Device Driver
+ *****************************************************************************
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifndef _ADI_SPI_DATA_C_
+#define _ADI_SPI_DATA_C_
+
+ /*! \cond PRIVATE */
+
+#include <adi_processor.h>
+#include "adi_spi_def.h"
+#include "adi_spi_config.h"
+#include <drivers/dma/adi_dma.h>
+
+/* Stores the information about the specific device */
+static  ADI_SPI_DEVICE_INFO spi_device_info [ADI_SPI_NUM_INSTANCES]=
+{
+    {
+             DMA0_CH4_DONE_IRQn,
+             SPI0_TX_CHANn,
+	     DMA0_CH5_DONE_IRQn,
+             SPI0_RX_CHANn,
+	     (volatile ADI_SPI_TypeDef *)pADI_SPI0,
+	     SPI0_EVT_IRQn,
+	     NULL
+    },
+    {
+             DMA0_CH6_DONE_IRQn,
+             SPI1_TX_CHANn,
+	     DMA0_CH7_DONE_IRQn,
+             SPI1_RX_CHANn,
+	     (volatile ADI_SPI_TypeDef *)pADI_SPI1,
+	     SPI1_EVT_IRQn,
+	     NULL
+    },
+
+    {
+             DMA0_CH0_DONE_IRQn,
+             SPI2_TX_CHANn,
+   	     DMA0_CH1_DONE_IRQn,
+             SPI2_RX_CHANn,
+   	     (volatile ADI_SPI_TypeDef *)pADI_SPI2,
+	     SPI2_EVT_IRQn,
+	     NULL
+    }
+};
+
+/* SPI Application configuration array */
+static const ADI_SPI_CFG_TYPE gSPICfg[ADI_SPI_NUM_INSTANCES] =
+{
+  /* Initialize SPI0 Instance configuration. */
+  {
+       /**** SPI_CFG register configuration *** */
+       (( ADI_SPI0_CFG_ENABLE               << BITP_SPI_CTL_SPIEN         ) |
+        ( ADI_SPI0_CFG_CLK_PHASE            << BITP_SPI_CTL_CPHA          ) |
+        ( ADI_SPI0_CFG_CLK_POLARITY         << BITP_SPI_CTL_CPOL          ) |
+        ( ADI_SPI0_CFG_WIRED_OR             << BITP_SPI_CTL_WOM           ) |
+        ( ADI_SPI0_CFG_LSB_MSB              << BITP_SPI_CTL_LSB           ) |
+        ( ADI_SPI0_CFG_TRANSFER_INITIATE    << BITP_SPI_CTL_TIM           ) |
+        ( ADI_SPI0_CFG_TX_UNDERFLOW         << BITP_SPI_CTL_ZEN           ) |
+        ( ADI_SPI0_CFG_RX_OVERFLOW          << BITP_SPI_CTL_RXOF          ) |
+        ( ADI_SPI0_CFG_MISO_ENABLE          << BITP_SPI_CTL_OEN           ) |
+        ( ADI_SPI0_CFG_LOOPBACK             << BITP_SPI_CTL_LOOPBACK      ) |
+        ( ADI_SPI0_CFG_CONTINUOUS           << BITP_SPI_CTL_CON           ) |
+        ( ADI_SPI0_CFG_RX_FLUSH             << BITP_SPI_CTL_RFLUSH        ) |
+        ( ADI_SPI0_CFG_TX_FLUSH             << BITP_SPI_CTL_TFLUSH        ) |
+        ( ADI_SPI0_CFG_CSERR_RESET          << BITP_SPI_CTL_CSRST         )),
+
+       /**** SPI_DIV buad rate selection register *** */
+       (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI0_CFG_BIT_RATE)) >>1u)-1u))\
+                                        << BITP_SPI_DIV_VALUE           )
+    },
+  /* Initialize SPI1 Instance configuration. */
+  {
+       /**** SPI_CFG register configuration *** */
+       (( ADI_SPI1_CFG_ENABLE               << BITP_SPI_CTL_SPIEN            ) |
+        ( ADI_SPI1_CFG_CLK_PHASE            << BITP_SPI_CTL_CPHA          ) |
+        ( ADI_SPI1_CFG_CLK_POLARITY         << BITP_SPI_CTL_CPOL          ) |
+        ( ADI_SPI1_CFG_WIRED_OR             << BITP_SPI_CTL_WOM           ) |
+        ( ADI_SPI1_CFG_LSB_MSB              << BITP_SPI_CTL_LSB           ) |
+        ( ADI_SPI1_CFG_TRANSFER_INITIATE    << BITP_SPI_CTL_TIM           ) |
+        ( ADI_SPI1_CFG_TX_UNDERFLOW         << BITP_SPI_CTL_ZEN           ) |
+        ( ADI_SPI1_CFG_RX_OVERFLOW          << BITP_SPI_CTL_RXOF          ) |
+        ( ADI_SPI1_CFG_MISO_ENABLE          << BITP_SPI_CTL_OEN           ) |
+        ( ADI_SPI1_CFG_LOOPBACK             << BITP_SPI_CTL_LOOPBACK      ) |
+        ( ADI_SPI1_CFG_CONTINUOUS           << BITP_SPI_CTL_CON           ) |
+        ( ADI_SPI1_CFG_RX_FLUSH             << BITP_SPI_CTL_RFLUSH        ) |
+        ( ADI_SPI1_CFG_TX_FLUSH             << BITP_SPI_CTL_TFLUSH        ) |
+        ( ADI_SPI1_CFG_CSERR_RESET          << BITP_SPI_CTL_CSRST         )),
+
+       /**** SPI_DIV buad rate selection register *** */
+       (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI1_CFG_BIT_RATE)) >>1u)-1u))\
+                                        << BITP_SPI_DIV_VALUE           )
+    },
+  /* Initialize SPI2 Instance configuration. */
+  {
+       /**** SPI_CFG register configuration *** */
+       (( ADI_SPI2_CFG_ENABLE               << BITP_SPI_CTL_SPIEN            ) |
+        ( ADI_SPI2_CFG_CLK_PHASE            << BITP_SPI_CTL_CPHA          ) |
+        ( ADI_SPI2_CFG_CLK_POLARITY         << BITP_SPI_CTL_CPOL          ) |
+        ( ADI_SPI2_CFG_WIRED_OR             << BITP_SPI_CTL_WOM           ) |
+        ( ADI_SPI2_CFG_LSB_MSB              << BITP_SPI_CTL_LSB           ) |
+        ( ADI_SPI2_CFG_TRANSFER_INITIATE    << BITP_SPI_CTL_TIM           ) |
+        ( ADI_SPI2_CFG_TX_UNDERFLOW         << BITP_SPI_CTL_ZEN           ) |
+        ( ADI_SPI2_CFG_RX_OVERFLOW          << BITP_SPI_CTL_RXOF          ) |
+        ( ADI_SPI2_CFG_MISO_ENABLE          << BITP_SPI_CTL_OEN           ) |
+        ( ADI_SPI2_CFG_LOOPBACK             << BITP_SPI_CTL_LOOPBACK      ) |
+        ( ADI_SPI2_CFG_CONTINUOUS           << BITP_SPI_CTL_CON           ) |
+        ( ADI_SPI2_CFG_RX_FLUSH             << BITP_SPI_CTL_RFLUSH        ) |
+        ( ADI_SPI2_CFG_TX_FLUSH             << BITP_SPI_CTL_TFLUSH        ) |
+        ( ADI_SPI2_CFG_CSERR_RESET          << BITP_SPI_CTL_CSRST         )),
+
+       /**** SPI_DIV buad rate selection register *** */
+       (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI2_CFG_BIT_RATE)) >>1u)-1u))\
+                                        << BITP_SPI_DIV_VALUE           )
+    }
+};
+
+/*! \endcond */
+
+#endif /* _ADI_SPI_DATA_C_ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_def.h
new file mode 100755
index 00000000000..8cbbf1b8d7e
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_def.h
@@ -0,0 +1,148 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_spi_def.h
+ * @brief:   SPI Device Driver definition 
+ *****************************************************************************
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#ifndef ADI_SPI_DEF_H_
+#define ADI_SPI_DEF_H_
+
+
+
+#include <drivers/spi/adi_spi.h>
+
+#define ADI_SPI_NUM_INSTANCES         (3u)
+#define ADI_SPI_FIFO_SIZE             (8u)
+
+
+ /*! \cond PRIVATE */
+
+/*
+ *****************************************************************************
+ * SPI Bitrate Initializer.  Sets a default serial clockrate for the SPI channel.
+ *****************************************************************************/
+/* #define ADI_SPI_BITRATE_INITIALIZER   4000000 // 4MHz default bitrate */
+#define ADI_SPI_BITRATE_INITIALIZER      250000u  /* depends on processor */
+
+/*
+ *****************************************************************************
+ * SPI0/SPI1 Control Register Initializer.  This macro configures default
+ * settings for the SPI configuration control register when operated in Master-mode.
+ *****************************************************************************/
+/* SPI master DMA mode control configuration */
+#define ADI_SPI_MASTERCON_INITIALIZER      BITM_SPI_CTL_MASEN
+
+/*
+ *****************************************************************************
+ * SPI0/SPI1 Control Register Initializer.  This macro configures default
+ * settings for the SPI configuration control register when operated in Slave-mode.
+ *****************************************************************************/
+ #define ADI_SPI_SLAVECON_INITIALIZER  BITM_SPI_CTL_OEN           \
+                                     | BITM_SPI_CTL_ZEN           \
+                                     | BITM_SPI_CTL_SPIEN
+
+/* 16-bit DMA... (two-byte size and increment) */
+#define ADI_DMA_DATA_WIDTH      ADI_DMA_WIDTH_2_BYTE  /*!< DMA data attribute */
+#define ADI_DMA_DATA_INCREMENT  ADI_DMA_INCR_HALFWORD   /*!< DMA data attribute */
+
+
+
+/*!
+ *****************************************************************************
+ * SPI Configuration structure.
+ *****************************************************************************/
+typedef struct ADI_SPI_CONFIG
+{
+    uint16_t SPI_CTL;                          /*!< SPI_CTL register configuration. */
+    uint16_t SPI_DIV;                          /*!< SPI_DIV  register.     */
+} ADI_SPI_CFG_TYPE;
+
+/*! SPI device information */
+
+typedef struct __ADI_SPI_DEVICE_INFO
+{
+    const uint16_t               dmaTxIrqNumber;     /*  DMA channel ID-Tx */
+    const uint16_t               dmaTxChannelNumber; /*  Tx */
+    const uint16_t               dmaRxIrqNumber;     /*  DMA channel ID-Rx */    
+    const uint16_t               dmaRxChannelNumber; /*  DMA channel ID-Rx */    
+    volatile ADI_SPI_TypeDef     *pSpiRegs;          /*  Base address of the  SPI registers */
+    const IRQn_Type              eIRQn;              /*  IRQn */   
+    ADI_SPI_HANDLE               hDevice;            /*  SPI handle */
+}ADI_SPI_DEVICE_INFO;
+
+
+/*! \struct ADI_SPI_DEV_DATA_TYPE SPI Device instance data structure */
+typedef struct __ADI_SPI_DEV_DATA_TYPE
+{
+
+    /* device attributes */
+    volatile ADI_SPI_TypeDef *pSpi;              /*!< track MMR device pointer   */
+    ADI_SPI_DEVICE_INFO      *pDevInfo;
+
+    /* Callback and Callback parameters */
+    ADI_CALLBACK             pfCallback;         /*!< Callback address          */
+    void *                   pCBParam;           /*!< Callback parameter        */
+    /* The last recorded SPI event */
+    uint32_t                 HWErrors;           /*!< HW transaction status */
+
+    uint8_t*                 pTxBuffer;          /*!< Transmit Buffer           */
+    uint8_t*                 pRxBuffer;          /*!< Receive Buffer            */
+    uint16_t                 TxRemaining;        /*!< Transmit Count            */
+    uint16_t                 RxRemaining;        /*!< Receive Count             */
+    uint8_t                  TxIncrement;        /*!< Transmit Increment        */
+    uint8_t                  RxIncrement;        /*!< Receive Increment         */
+    
+    volatile bool            bTransferComplete;  /*!< Transfer Complete Flag    */
+
+    bool                     bDmaMode;           /*!< DMA mode flag              */
+    bool                     bRdCtlMode;         /* Use half duplex read control feature */
+    bool                     bBlockingMode;      /*!< blocking mode flag         */
+    ADI_SPI_CHIP_SELECT      ChipSelect;         /*!< track chip select          */
+    
+    SEM_VAR_DECLR
+} ADI_SPI_DEV_DATA_TYPE;
+
+
+
+/*! \endcond */
+
+#endif	/* ADI_SPI_DEF_H__ */
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sport/adi_sport.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sport/adi_sport.c
new file mode 100755
index 00000000000..5c352c2bc50
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sport/adi_sport.c
@@ -0,0 +1,1771 @@
+/*! ****************************************************************************
+ * @file:    adi_sport.c
+ * @brief:   SPORT (Serial Port) device driver source file.
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/** @addtogroup SPORT_Driver SPORT Driver
+ *  @{
+ */
+
+/*! \cond PRIVATE */
+
+/*=============  I N C L U D E S   =============*/
+
+#include <assert.h>
+#include <string.h>     /* memset declaration */
+
+#include <drivers/general/adi_drivers_general.h>
+#include <adi_sport_config.h>
+#include <drivers/sport/adi_sport.h>
+#include <adi_cyclecount.h>
+#include "adi_sport_def.h"
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
+*   This isn't a header as such.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+*
+* Pm050 (rule 14.2): a null statement shall only occur on a line by itself
+*   Needed for null expansion of ADI_INSTALL_HANDLER and others.
+*
+* Pm088 (rule 17.4): pointer arithmetic should not be used.
+*   Relying on pointer arithmetic for buffer handling.
+*
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   The rule makes an exception for memory-mapped register accesses.
+*
+* Pm152: (MISRA C 2004 rule 17.4) array indexing shall only be applied to objects defined as an array type
+*   Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors
+
+*/
+#pragma diag_suppress=Pm026,Pm050,Pm073,Pm088,Pm123,Pm140,Pm143,Pm152,Pm153
+#endif /* __ICCARM__ */
+
+/*==============  D A T A  ===============*/
+
+#define SPORT0_A_REGS   ((volatile ADI_SPORT_TypeDef*)REG_SPORT0_CTL_A)
+#define SPORT0_B_REGS   ((volatile ADI_SPORT_TypeDef*)REG_SPORT0_CTL_B)
+
+#define SPORT0_A_CFG    { 0u, 0u, 0u, 0u, 0u }
+#define SPORT0_B_CFG    { 0u, 0u, 0u, 0u, 0u }
+
+#define DXS_FIFO_IS_FULL(STAT)  (((STAT) & BITM_SPORT_STAT_A_DXS) == BITM_SPORT_STAT_A_DXS)
+#define DXS_FIFO_IS_EMPTY(STAT) (((STAT) & BITM_SPORT_STAT_A_DXS) == 0u)
+
+static  ADI_SPORT_DEVICE_INFO gSportDevInfo [ADI_SPORT_NUM_INSTANCES][ADI_SPORT_NUM_CHANNELS] =
+{
+    {/* registers       configuration  initial state                  DMA channel    DMA IRQ             SPORT IRQ         handle */
+        {SPORT0_A_REGS, SPORT0_A_CFG,  ADI_SPORT_STATE_UNINITIALIZED, SPORT0A_CHANn, DMA0_CH2_DONE_IRQn, SPORT_A_EVT_IRQn, NULL},
+        {SPORT0_B_REGS, SPORT0_B_CFG,  ADI_SPORT_STATE_UNINITIALIZED, SPORT0B_CHANn, DMA0_CH3_DONE_IRQn, SPORT_B_EVT_IRQn, NULL},
+    },
+};
+
+
+static const ADI_SPORT_CONFIG gSportCfg[ADI_SPORT_NUM_INSTANCES][ADI_SPORT_NUM_CHANNELS] =
+{
+  { /* configuration for SPORT 0 */
+     /* Configuration for half-SPORT A */
+     { /* SPORT_CTL register */
+       ((ADI_CFG_SPORT0A_ENABLE_FSMUXSEL)       << BITP_SPORT_CTL_A_FSMUXSEL)   |
+       ((ADI_CFG_SPORT0A_ENABLE_CKMUXSEL)       << BITP_SPORT_CTL_A_CKMUXSEL)   |
+       ((ADI_CFG_SPORT0A_LSB_FIRST)             << BITP_SPORT_CTL_A_LSBF)       |
+       ((ADI_CFG_SPORT0A_SERIAL_WLEN - 1u)      << BITP_SPORT_CTL_A_SLEN)       |
+       ((ADI_CFG_SPORT0A_INTERNAL_CLK)          << BITP_SPORT_CTL_A_ICLK)       |
+       ((ADI_CFG_SPORT0A_OPERATION_MODE)        << BITP_SPORT_CTL_A_OPMODE)     |
+       ((ADI_CFG_SPORT0A_CLOCK_EDGE)            << BITP_SPORT_CTL_A_CKRE)       |
+       ((ADI_CFG_SPORT0A_FS_REQUIRED)           << BITP_SPORT_CTL_A_FSR)        |
+       ((ADI_CFG_SPORT0A_INTERNAL_FS)           << BITP_SPORT_CTL_A_IFS)        |
+       ((ADI_CFG_SPORT0A_DATA_INDEPENDENT_FS)   << BITP_SPORT_CTL_A_DIFS)       |
+       ((ADI_CFG_SPORT0A_ACTIVE_LOW_FS)         << BITP_SPORT_CTL_A_LFS)        |
+       ((ADI_CFG_SPORT0A_LATE_FS)               << BITP_SPORT_CTL_A_LAFS)       |
+       ((ADI_CFG_SPORT0A_ENABLE_PACKING)        << BITP_SPORT_CTL_A_PACK)       |
+       ((ADI_CFG_SPORT0A_FS_ERROR_OPERATION)    << BITP_SPORT_CTL_A_FSERRMODE)  |
+       ((ADI_CFG_SPORT0A_GATED_CLOCK)           << BITP_SPORT_CTL_A_GCLKEN),
+
+        /* SPORT_DIV register */
+       ((ADI_CFG_SPORT0A_CLOCK_DIVISOR)         << BITP_SPORT_DIV_A_CLKDIV)     |
+       ((ADI_CFG_SPORT0A_FS_DIVISOR)            << BITP_SPORT_DIV_A_FSDIV),
+
+        /* SPORT_CONVT register */
+       ((ADI_CFG_SPORT0A_CONVT_WIDTH)           << BITP_SPORT_CNVT_A_WID)       |
+       ((ADI_CFG_SPORT0A_CONVT_POLARITY)        << BITP_SPORT_CNVT_A_POL)       |
+       ((ADI_CFG_SPORT0A_CONVT_FS_DURATION)     << BITP_SPORT_CNVT_A_CNVT2FS),
+
+       /* Default DMA data size for SPORT */
+       ADI_DMA_WIDTH_4_BYTE,
+
+       /* Default DMA data increment for SPORT */
+       ADI_DMA_INCR_4_BYTE
+     },
+
+     /* Configuration for half-SPORT B */
+     { /* SPORT_CTL register */
+       ((ADI_CFG_SPORT0B_LSB_FIRST)             << BITP_SPORT_CTL_B_LSBF)       |
+       ((ADI_CFG_SPORT0B_SERIAL_WLEN - 1u)      << BITP_SPORT_CTL_B_SLEN)       |
+       ((ADI_CFG_SPORT0B_INTERNAL_CLK)          << BITP_SPORT_CTL_B_ICLK)       |
+       ((ADI_CFG_SPORT0B_OPERATION_MODE)        << BITP_SPORT_CTL_B_OPMODE)     |
+       ((ADI_CFG_SPORT0B_CLOCK_EDGE)            << BITP_SPORT_CTL_B_CKRE)       |
+       ((ADI_CFG_SPORT0B_FS_REQUIRED)           << BITP_SPORT_CTL_B_FSR)        |
+       ((ADI_CFG_SPORT0B_INTERNAL_FS)           << BITP_SPORT_CTL_B_IFS)        |
+       ((ADI_CFG_SPORT0B_DATA_INDEPENDENT_FS)   << BITP_SPORT_CTL_B_DIFS)       |
+       ((ADI_CFG_SPORT0B_ACTIVE_LOW_FS)         << BITP_SPORT_CTL_B_LFS)        |
+       ((ADI_CFG_SPORT0B_LATE_FS)               << BITP_SPORT_CTL_B_LAFS)       |
+       ((ADI_CFG_SPORT0B_ENABLE_PACKING)        << BITP_SPORT_CTL_B_PACK)       |
+       ((ADI_CFG_SPORT0B_FS_ERROR_OPERATION)    << BITP_SPORT_CTL_B_FSERRMODE)  |
+       ((ADI_CFG_SPORT0B_GATED_CLOCK)           << BITP_SPORT_CTL_B_GCLKEN),
+
+        /* SPORT_DIV register */
+       ((ADI_CFG_SPORT0B_CLOCK_DIVISOR)         << BITP_SPORT_DIV_B_CLKDIV)     |
+       ((ADI_CFG_SPORT0B_FS_DIVISOR)            << BITP_SPORT_DIV_B_FSDIV),
+
+        /* SPORT_CONVT register */
+       ((ADI_CFG_SPORT0B_CONVT_WIDTH)           << BITP_SPORT_CNVT_B_WID)       |
+       ((ADI_CFG_SPORT0B_CONVT_POLARITY)        << BITP_SPORT_CNVT_B_POL)       |
+       ((ADI_CFG_SPORT0B_CONVT_FS_DURATION)     << BITP_SPORT_CNVT_B_CNVT2FS),
+
+       /* Default DMA data size for SPORT */
+       ADI_DMA_WIDTH_4_BYTE,
+
+       /* Default DMA data increment for SPORT */
+       ADI_DMA_INCR_4_BYTE
+     }
+  }
+};
+
+/*! \endcond */
+
+/*=============  C O D E  =============*/
+
+extern void SPORT0A_Int_Handler(void);          /*!< Interrupt handler for the SPORT0-A */
+extern void SPORT0B_Int_Handler(void);          /*!< Interrupt handler for the SPORT0-B */
+extern void DMA_SPORT0A_Int_Handler(void);      /*!< DMA handler for the SPORT0-A */
+extern void DMA_SPORT0B_Int_Handler(void);      /*!< DMA handler for the SPORT0-B */
+
+/*=============  L O C A L   F U N C T I O N S =============*/
+
+/*=============  P U B L I C   F U N C T I O N S =============*/
+
+/**
+ * @brief       Initialization function for SPORT device.
+ * @details     Initialization function for SPORT device. This function must be
+ *              called before operating any SPORT device.
+ *
+ * @param [in]  nDevNum         SPORT Device instance to be opened.
+ * @param [in]  eChannel        Channel ID of the SPORT device (A or B)
+ * @param [in]  eDirection      Direction of the SPORT operation (i.e Rx or Tx)
+ * @param [in]  pMemory         Pointer to a 32 bit aligned buffer containing
+ *                              ADI_SPORT_MEMORY_SIZE bytes. This buffer is
+ *                              required by the SPORT driver for its operations.
+ *                              The "ADI_SPORT_MEMORY_SIZE" varies based on the
+ *                              configuration.
+ * @param [in]  nMemSize        Size of the buffer to which "pMemory" points.
+ * @param [out] phDevice        Pointer to a location where a handle to the
+ *                              opened SPORT driver can be stored. This handle
+ *                              will be used to identity a SPORT device when
+ *                              calling SPORT management functions.
+ *
+ * @return      Status
+ * - #ADI_SPORT_SUCCESS                 Successful device initialization.
+ * - #ADI_SPORT_DEVICE_IN_USE           Device already initialized.
+ * - #ADI_SPORT_FAILED                  Failed initialize a semaphore for managing device.
+ * - #ADI_SPORT_INVALID_DEVICE_NUM      Invalid SPORT device identifier
+ * - #ADI_SPORT_INVALID_NULL_POINTER    Invalid pointer (callback function or device handle).
+ *
+ * @sa  adi_sport_Close()
+ */
+ADI_SPORT_RESULT adi_sport_Open(
+    const uint32_t              nDevNum,
+    const ADI_SPORT_CHANNEL     eChannel,
+    const ADI_SPORT_DIRECTION   eDirection,
+    void                        *pMemory,
+    const uint32_t              nMemSize,
+    ADI_SPORT_HANDLE * const    phDevice
+    )
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+
+    assert(ADI_SPORT_MEMORY_SIZE == sizeof(ADI_SPORT_DEVICE));  /* validate the memory size macro */
+#ifdef ADI_DEBUG
+    if (nDevNum >= ADI_SPORT_NUM_INSTANCES)
+    {
+        result = ADI_SPORT_INVALID_DEVICE_NUM;          /* SPORT identifier must be within [0..ADI_SPORT_NUM_INSTANCES-1] */
+    }
+    else if (phDevice == NULL)
+    {
+        result = ADI_SPORT_INVALID_NULL_POINTER;        /* the pointer to device handle must be valid */
+    }
+    else if (ADI_SPORT_MEMORY_SIZE != nMemSize)
+    {
+        result = ADI_SPORT_FAILED;
+    }
+    else if (ADI_SPORT_STATE_UNINITIALIZED != gSportDevInfo[nDevNum][eChannel].eState)
+    {
+        result = ADI_SPORT_DEVICE_IN_USE;               /* the device instance must not be in use */
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        ADI_SPORT_DEVICE * pDevice = pMemory;           /* Pointer to the SPORT device instance (from supplied memory) */
+        ADI_SPORT_DEVICE_INFO * sportInfo = &gSportDevInfo[nDevNum][eChannel];  /* SPORT info for HSPORT A or HSPORT B */
+        ADI_SPORT_CONFIG const * sportCfg = &gSportCfg[nDevNum][eChannel];      /* SPORT configuration for HSPORT A or HSPORT B */
+
+        assert(eChannel < ADI_SPORT_NUM_CHANNELS);
+
+        memset(pMemory, 0, nMemSize);           /* clear the device instance data before initializing it */
+
+        pDevice->pSportInfo = sportInfo;        /* Initialize the pointer which provides the device information (HSPORT A or HSPORT B). */
+        pDevice->eDirection = eDirection;       /* Initialize the direction (BEFORE calling sport_Configure)*/
+        pDevice->nHwError = (uint32_t) ADI_SPORT_HW_NO_ERR;
+
+        adi_dma_Init();                         /* Set up the DMA Controller. */
+        sport_Init(pDevice);                    /* Initialize the data transmission buffers */
+        sport_Configure(pDevice,sportCfg);      /* Configure the SPORT */
+
+        if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(sportInfo->eDMAChnlID, sport_DmaErrorCallback, pDevice))
+        {
+            adi_sport_Close(pDevice);
+            result = ADI_SPORT_DMA_REGISTER_FAILED;
+        }
+
+        if (ADI_SPORT_SUCCESS == result)
+        {
+            ADI_SPORT_DEVICE_INFO * devInfo = &gSportDevInfo[nDevNum][eChannel];
+
+            /* Create a "semaphore" (varies per OS) used for blocking buffer resource management. */
+            if (ADI_HALF_SPORT_A == eChannel)
+            {
+                SEM_CREATE(&pDevice->sportChannel, "SPORT0_A_SEM", ADI_SPORT_FAILED);
+            }else{
+                SEM_CREATE(&pDevice->sportChannel, "SPORT0_B_SEM", ADI_SPORT_FAILED);
+            }
+
+            /* Change the state of the specified device */
+            ADI_INT_STATUS_ALLOC();
+            ADI_ENTER_CRITICAL_REGION();
+                devInfo->eState = ADI_SPORT_STATE_INITIALIZED;
+                devInfo->hDevice = pDevice;
+            ADI_EXIT_CRITICAL_REGION();
+            *phDevice = pDevice;                /* Return the device handle to the application */
+        }
+    }
+
+    return result;
+}
+
+/**
+ * @brief       Closes the operation of specified SPORT device.
+ *
+ * @details     Closes the operation of specified SPORT device.
+ *              Device need to be opened again for any further use.
+ *
+ * @param [in]  hDevice SPORT device handle whose operation is to be closed.
+ *                      This handle was obtained when a SPORT device is opened
+ *                      successfully.
+ *
+ * @return      Status
+ *
+ *      - #ADI_SPORT_SUCCESS            Successfully closed the specified device.
+ *      - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle.
+ *      - #ADI_SPORT_FAILED         [D] SPORT device internal error.
+ *
+ * @note        It is user's responsibility to free/reuse the memory supplied
+ *              during the opening of the device.
+ *
+ * @sa          adi_sport_Open()
+ */
+ADI_SPORT_RESULT adi_sport_Close(ADI_SPORT_HANDLE const hDevice)
+{
+    ADI_SPORT_RESULT    result = ADI_SPORT_SUCCESS;             /* return code */
+    ADI_SPORT_DEVICE *  pDevice = (ADI_SPORT_DEVICE *) hDevice; /* Pointer to SPORT device instance */
+#ifdef ADI_DEBUG
+    if (ADI_SPORT_SUCCESS == (result=ValidateHandle(pDevice)))  /* Validate the given handle */
+#endif /* ADI_DEBUG */
+    {
+        ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo;
+
+        /* Free up the device */
+        ADI_INT_STATUS_ALLOC();
+        ADI_ENTER_CRITICAL_REGION();
+            NVIC_DisableIRQ(pSportInfo->eIRQn);                 /* Disable SPORT event interrupts. */
+            NVIC_DisableIRQ(pSportInfo->eDMAn);                 /* Disable DMA SPORT interrupts. */
+            pSportInfo->eState  = ADI_SPORT_STATE_UNINITIALIZED;
+            pSportInfo->hDevice = NULL;                         /* Free up the device memory. */
+        ADI_EXIT_CRITICAL_REGION();
+
+        SEM_DELETE(&pDevice->sportChannel, ADI_SPORT_FAILED);   /* Delete SPORT channel semaphore. */
+
+        adi_dma_RegisterCallback(pSportInfo->eDMAChnlID, NULL, NULL);   /* unregister the callback function in the DMA error handler */
+
+        pSportInfo->pSportRegs->CTL_A = 0u;
+    }
+    return result;
+}
+
+/**
+ * @brief       Submit the buffer for transmitting/receiving the data. This function can
+ *              be used to submit the buffers for both transmitting and receiving. It will
+ *              be returned after successfully submitting the buffer for transmitting data.
+ *              User will be notified if a call back function is registered with an event code
+ *              #ADI_SPORT_EVENT_RX_BUFFER_PROCESSED or #ADI_SPORT_EVENT_TX_BUFFER_PROCESSED"
+ *              depending on the direction in which device is operating.
+ *
+ * @param [in]  hDevice   Device handle to SPORT device is obtained when a SPORT device is opened
+ *                        successfully.
+ *
+ * @param [in]  pBuffer   Pointer to buffer from where data need to be transmitted OR to which
+ *                        received data need to to be written.
+ *
+ * @param [in]  nNumBytes Size in bytes of the data to be transmitted/received.
+ * @param [in]  bDMA      True if the buffer must be processed through DMA-driven SPORT operations.
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                        Buffer successfully submitted to the specified SPORT.
+ *  - #ADI_SPORT_INVALID_HANDLE                 Invalid SPORT device handle.
+ *  - #ADI_SPORT_INVALID_PARAMETER              Number of bytes is too large for a SPORT transfer or the buffer is mis-aligned
+ *  - #ADI_SPORT_BUFFERS_NOT_SUBMITTED          All the SPORT buffers are already being used
+ *
+ * @sa          adi_sport_GetBuffer()
+ *
+ */
+ADI_SPORT_RESULT adi_sport_SubmitBuffer(ADI_SPORT_HANDLE const hDevice,
+                                        void *           const pBuffer,
+                                        uint32_t         const nNumBytes,
+                                        bool             const bDMA
+                                        )
+{
+    ADI_SPORT_DEVICE *  pDevice = (ADI_SPORT_DEVICE *) hDevice;         /* pointer to SPORT device instance */
+    ADI_SPORT_RESULT    result = ADI_SPORT_SUCCESS;                     /* return code */
+
+#ifdef ADI_DEBUG
+    ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg;      /* short cut to SPORT configuration */
+
+    if(ADI_SPORT_SUCCESS != (result=ValidateHandle(hDevice)))           /* validate the given handle */
+    {
+    }
+    else if (  ((2u >= nNumBytes) && ((pDevice->pSportInfo->pSportRegs->CTL_A & BITM_SPORT_CTL_A_OPMODE) != 0u))
+            || (0u != (nNumBytes & ~(BITM_SPORT_NUMTRAN_A_VALUE)))      /* buffer size limited by SPORT transmission capabilities */
+            )
+    {
+        result = ADI_SPORT_INVALID_PARAMETER;
+    }
+    else
+#endif /* ADI_DEBUG */
+    /* Check that there is a free buffer to use for this transmit operation. pFreeBuffer
+       is the next buffer available, so if it is in use we can make the assumption that
+       there are no buffers available. The start address is set to NULL once the buffer
+       has finished being processed in "adi_sport_GetBuffer()".
+    */
+    if (NULL != pDevice->sportChannel.pFreeBuffer->pStartAddress)
+    {
+        result = ADI_SPORT_BUFFERS_NOT_SUBMITTED;
+    }
+    else
+    {
+#ifdef ADI_DEBUG
+        const uint32_t addr = (uint32_t) pBuffer;
+
+        if (true == bDMA)
+        {
+            /**
+             * Using SPORT configuration data, let's define information such as data
+             * size in bytes, data number, number of data and bytes in the DMA transfer
+             * being prepared, last byte position for the DMA transfer
+             *
+             * It's important to keep in mind that for buffer that contain too many data
+             * multiple DMA transfers are needed: it's up to the application to split the
+             * DMA requests in requests which have an appropriate number of data.
+             */
+            const uint32_t dataSizeInBytes = GetBytesPerSportData(pSportCfg->CTL);
+            const uint32_t full = nNumBytes / dataSizeInBytes;          /* number of full data to transmit/receive */
+            const uint32_t partial = nNumBytes % dataSizeInBytes;       /* number of partial data to transmit/receive */
+            const uint32_t misaligned = addr % dataSizeInBytes;         /* number of data to transmit/receive */
+
+            if (  (full > DMA_TRANSFER_LIMIT)                           /* number of data to process too large for DMA */
+               || (0u != partial)                                       /* buffer size not a multiple of dataSizeInBytes */
+               || (0u != misaligned)                                    /* buffer mis-aligned */
+               )
+            {
+                result = ADI_SPORT_INVALID_PARAMETER;
+            }
+        } else {
+            const uint32_t misAligned = addr % 4u;
+            const uint32_t invalidNum = nNumBytes % 4u;
+
+            if (  (0u != misAligned)                                    /* mis-aligned buffer */
+               || (0u != invalidNum)                                    /* number of bytes not a multiple of 32-bit  */
+               )
+            {
+                result = ADI_SPORT_INVALID_PARAMETER;                   /* reject the buffer submission */
+            }
+        }
+        if (ADI_SPORT_SUCCESS == result)
+#endif /* ADI_DEBUG */
+        {
+            ADI_DT_CHANNEL * pSportChnl = &pDevice->sportChannel;
+
+            pSportChnl->pFreeBuffer->pStartAddress = pBuffer;   /* Set the start address of the data buffer */
+            pSportChnl->pFreeBuffer->nCount        = nNumBytes; /* Set the buffer size */
+            pSportChnl->pFreeBuffer->nIndex        = 0u;        /* Initialize the buffer index to zero (1st data in buffer) */
+            pSportChnl->pFreeBuffer->bDMA          = bDMA;      /* Set the DMA boolean value. */
+            pSportChnl->pFreeBuffer->bInUse        = true;      /* this buffer is now being used by the SPORT */
+
+            /* Now that this "pFreeBuffer" is no longer free for use, update the
+            "pFreeBuffer" to the next buffer. "pFreeBuffer" will only be updated
+            during the process of submitting a buffer or a read/write operation.
+            */
+            pSportChnl->pFreeBuffer = pSportChnl->pFreeBuffer->pNextBuffer;
+
+            /* Set the data transfer mode in case it was #ADI_DT_MODE_NONE. This
+            will be set back to #ADI_DT_MODE_NONE once this transaction is complete.
+            Then, if a buffer is not currently active, set up the interrupts for
+            this transaction. Otherwise if a buffer is currently active, this will
+            be taken care of in the ISR.
+            */
+            if (pSportChnl->eDataTranferMode == ADI_DT_MODE_NONE)   /* if the SPORT is available for a transmission */
+            {
+                pSportChnl->eDataTranferMode = ADI_DT_MODE_NONBLOCKING;
+
+                /* call an appropriate function based on mode in which device is operating */
+                if (true == bDMA)                                   /* select a DMA driven or a core driven non-blocking transmission */
+                {
+                    result = sport_SubmitBufferDmaMode(pDevice, pSportChnl->pFillBuffer);
+                } else {
+                    result = sport_SubmitBufferIntMode(pDevice, pSportChnl->pFillBuffer);
+                }
+            }
+
+            if(ADI_SPORT_SUCCESS != result)                             /* if an error occurred...*/
+            {
+                pSportChnl->eDataTranferMode = ADI_DT_MODE_NONE;        /* SPORT is available */
+            }
+        }
+    }
+
+    return result;
+}
+
+/*
+ * @brief       Submit a buffer for SPORT Rx or Tx DMA driven transmission.
+ *
+ * @param [in]  pDevice Pointer to SPORT device.
+ *
+ * @param [in]  pBuffer Pointer to data transfer buffer information.
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                 buffer successfully submitted to the DMA associated with the SPORT.
+ *  - #ADI_SPORT_BUFFERS_NOT_SUBMITTED   Failed to submit the buffer to the DMA associated with the SPORT.
+ */
+/** Function prototype for submitting a buffer for SPORT Rx or Tx DMA driven transmission */
+static ADI_SPORT_RESULT sport_SubmitBufferDmaMode(ADI_SPORT_DEVICE * pDevice,
+                                                  ADI_DT_BUFF_INFO * pBuff)
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+    ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo;           /* short cut to SPORT information */
+    ADI_SPORT_CONFIG * pSportCfg = &pSportInfo->sportCfg;               /* short cut to SPORT configuration */
+
+#ifdef ADI_DEBUG
+    if (  (pBuff != pDevice->sportChannel.pFillBuffer)                  /* a submitted buffer should always be the current fill buffer */
+       || (true != pBuff->bInUse)                                       /* Processed buffers should already be marked as being used */
+       || (0u != pBuff->nIndex)                                         /* processing should start from index 0 */
+       )
+    {
+        result = ADI_SPORT_FAILED;
+    }
+    else
+#endif
+    {
+        volatile ADI_SPORT_TypeDef* pSportRegs = pSportInfo->pSportRegs;/* short cut to SPORT registers */
+        const uint32_t dmaChnlId = (uint32_t) pSportInfo->eDMAChnlID;   /* identifier for the DMA channel to be used */
+        const uint32_t dmaChnlBit = (1u << dmaChnlId);                  /* bit representing the DMA channel to be used */
+
+        /**
+         * Using SPORT configuration data, let's define information such as data
+         * size in bytes, data number, number of data and bytes in the DMA transfer
+         * being prepared, last byte position for the DMA transfer
+         *
+         * It's important to keep in mind that for buffer that contain too many data
+         * multiple DMA transfers are needed, so a buffer may have had part of its
+         * content already DMA-transferred: nIndex defines the position of the first
+         * byte in a buffer that has not been DMA-transferred yet.
+         */
+        const uint32_t dmaIncNone = (uint32_t) ADI_DMA_INCR_NONE;
+        const uint32_t dmaDcc = (uint32_t) DMA_ENUM_CTL_CYCLE_CTL_BASIC;
+        const uint32_t bytesPerData = GetBytesPerSportData(pSportCfg->CTL);
+
+        const uint32_t dataSizeInBytes = (1u << pSportCfg->DMA_WIDTH);  /* number of bytes in each data to transmit/receive */
+              uint32_t numDmaData = pBuff->nCount / dataSizeInBytes;    /* number of DMA data to transmit/receive */
+        const uint32_t dmaDataEnd = (pBuff->nCount - dataSizeInBytes);  /* position of last <8,16,32>-bit data in the DMA transfer being setup */
+        const uint32_t startAddress = (uint32_t) pBuff->pStartAddress;  /* address of the first byte in the data buffer */
+        const uint32_t numSportData = pBuff->nCount / bytesPerData;     /* number of SPORT data to transmit/receive */
+
+        assert(pBuff->nCount == (numSportData * bytesPerData));
+        assert(numSportData <= 0xFFFu);
+        assert(0u == (pBuff->nCount % dataSizeInBytes));
+        assert(numDmaData <= DMA_TRANSFER_LIMIT);
+        assert((ADI_SPORT_DIR_RX == pDevice->eDirection) || (ADI_SPORT_DIR_TX == pDevice->eDirection));
+        SPORT_CHECK_CFG_CTL(pSportCfg->CTL);
+
+        pSportRegs->CTL_A = 0u;                                         /* make sure SPORT is disable */
+        pADI_DMA0->SRCADDR_CLR = dmaChnlBit;                             /* Clear source address decrement for TX channel DMA. */
+        pADI_DMA0->EN_SET = dmaChnlBit;                                 /* Enable channel DMA. */
+        pADI_DMA0->RMSK_CLR = dmaChnlBit;                               /* Enable SPORT peripheral to generate DMA requests. */
+        pADI_DMA0->ALT_CLR = dmaChnlBit;                                /* Set the primary control data structure as the current DMA descriptor. */
+        pADI_DMA0->PRI_SET = dmaChnlBit;
+
+        if (ADI_SPORT_DIR_RX == pDevice->eDirection)
+        {
+            pPrimaryCCD[dmaChnlId].DMASRCEND = (uint32_t) &pSportRegs->RX_A;    /* address of the last src data in the DMA transfer being setup */
+            pPrimaryCCD[dmaChnlId].DMADSTEND = startAddress + dmaDataEnd;       /* address of the last dst data in the DMA transfer being setup */
+            pPrimaryCCD[dmaChnlId].DMACDC    =
+              (pSportCfg->DMA_INC << ((uint32_t)DMA_BITP_CTL_DST_INC))  |       /* destination address incremented by N bytes */
+              (dmaIncNone         << ((uint32_t)DMA_BITP_CTL_SRC_INC));         /* source address not incremented */
+        }
+        else                                                                    /* ADI_SPORT_DIR_TX */
+        {
+            pPrimaryCCD[dmaChnlId].DMASRCEND = startAddress + dmaDataEnd;       /* address of the last src data in the DMA transfer being setup */
+            pPrimaryCCD[dmaChnlId].DMADSTEND = (uint32_t) &pSportRegs->TX_A;    /* address of the last dst data in the DMA transfer being setup */
+            pPrimaryCCD[dmaChnlId].DMACDC    =
+              (dmaIncNone         << ((uint32_t)DMA_BITP_CTL_DST_INC))  |       /* destination address not incremented */
+              (pSportCfg->DMA_INC << ((uint32_t)DMA_BITP_CTL_SRC_INC));         /* source address incremented by N byte */
+
+            /**
+             * Fix for data transmission when DMA is used with packed data.
+             */
+            if (numDmaData < numSportData)
+            {
+                pPrimaryCCD[dmaChnlId].DMASRCEND = startAddress + dmaDataEnd + dataSizeInBytes;       /* address of the last src data in the DMA transfer being setup */
+                numDmaData++;
+            }
+        }
+        pPrimaryCCD[dmaChnlId].DMACDC |=
+          (pSportCfg->DMA_WIDTH << ((uint32_t)DMA_BITP_CTL_SRC_SIZE))   |       /* source data size in bytes */
+          (0u                   << ((uint32_t) DMA_BITP_CTL_R_POWER))   |
+          ((numDmaData - 1u)    << ((uint32_t)DMA_BITP_CTL_N_MINUS_1))  |       /* number of DMA transfers (minus 1) */
+          (dmaDcc               << ((uint32_t)DMA_BITP_CTL_CYCLE_CTL));
+
+        ADI_INT_STATUS_ALLOC();
+        ADI_ENTER_CRITICAL_REGION();
+            pDevice->pSportInfo->eState = ADI_SPORT_STATE_DATA_FLOW_ENABLED;
+            pSportRegs->NUMTRAN_A = numSportData;
+
+            /* Enable SPORT DMA request interrupt for the SPORT tx channel. */
+            NVIC_ClearPendingIRQ(pSportInfo->eIRQn);
+            NVIC_ClearPendingIRQ(pSportInfo->eDMAn);
+
+            uint32_t ien_a = ((uint32_t)BITM_SPORT_IEN_A_SYSDATERR) |
+                             ((uint32_t)BITM_SPORT_IEN_A_FSERRMSK) |
+                             ((uint32_t)BITM_SPORT_IEN_A_DERRMSK);
+            if (ADI_SPORT_DIR_RX == pDevice->eDirection)
+            {
+                /* Allow SPORT DMA interrupt handling to mark SPORT Rx as complete */
+                NVIC_EnableIRQ(pSportInfo->eDMAn);
+            }
+            else
+            {
+              /* SPORT DMA Tx is complete when TFI is raised: enable TFI */
+                ien_a |= ((uint32_t)BITM_SPORT_IEN_A_TF);
+            }
+
+            NVIC_EnableIRQ(pSportInfo->eIRQn);
+            
+            pSportRegs->IEN_A = ien_a;
+            pSportRegs->CTL_A = pSportCfg->CTL |
+                                ((uint32_t)BITM_SPORT_CTL_A_SPEN) |
+                                ((uint32_t)BITM_SPORT_CTL_A_DMAEN);
+        ADI_EXIT_CRITICAL_REGION();
+
+        SPORT_CHECK_CFG_CTL(pSportCfg->CTL);
+    }
+    return result;
+}
+
+/** Function prototype for  */
+/*
+ * @brief       Submit a buffer for SPORT Rx or Tx core driven transmission.
+ *
+ * @details     Submit a buffer for SPORT Rx or Tx core driven transmission.
+ *              The buffer must be 32-bit aligned and contain N * 32-bit data.
+ *
+ * @param [in]  pDevice Pointer to SPORT device.
+ *
+ * @param [in]  pBuffer Pointer to data transfer buffer information.
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                   Successfully submitted the buffer for data transfer.
+ *
+ *  - #ADI_SPORT_BUFFERS_NOT_SUBMITTED     No free descriptor for data transfer.
+ *
+ *
+ */
+static ADI_SPORT_RESULT sport_SubmitBufferIntMode(ADI_SPORT_DEVICE * pDevice, ADI_DT_BUFF_INFO * pBuff)
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+#ifdef ADI_DEBUG
+    if (  (pBuff != pDevice->sportChannel.pFillBuffer)  /* a submitted buffer should always be the current fill buffer */
+       || (true != pBuff->bInUse)                       /* Processed buffers should already be marked as being used */
+       || (0u != pBuff->nIndex)                         /* processing should start from index 0 */
+       )
+    {
+        result = ADI_SPORT_FAILED;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg;
+        volatile ADI_SPORT_TypeDef * pSportRegs = pDevice->pSportInfo->pSportRegs;
+        uint32_t ctl = pSportCfg->CTL;
+        uint32_t bytesPerData = GetBytesPerSportData(ctl);
+
+        /**
+         * Buffer can be too large for being processed in one submission.
+         * Consequently, if pBuff->nCount requires more than than 12-bit,
+         * multiple buffer submissions will be required by the application;
+         * the SPORT driver cannot process large buffers implicitly.
+         * The number of bytes in submitted buffers must be a multiple of 4
+         * because data are processed by the SPORT driver as 32-bit data.
+         */
+
+        /* use the SPORT configuration to setup the SPORT registers */
+
+        pBuff->nCount /= bytesPerData;                  /* number of data to be transmitted */
+
+#ifdef ADI_DEBUG
+        uint32_t pack = SPORT_GET_PACKEN(pSportCfg->CTL);
+        assert( ((9u > bytesPerData) && (1u == pack)) || ((17u > bytesPerData) && (2u == pack)) || (0u == pack));
+#endif
+        assert(pBuff->nCount <= 0xFFFu);
+        SPORT_CHECK_CFG_CTL(pSportCfg->CTL);
+
+        ADI_INT_STATUS_ALLOC();
+        ADI_ENTER_CRITICAL_REGION();
+            pSportRegs->CTL_A = 0u;                     /* make sure SPORT is disable */
+            pSportRegs->NUMTRAN_A = pBuff->nCount;
+            pDevice->pSportInfo->eState = ADI_SPORT_STATE_DATA_FLOW_ENABLED;
+
+            /* Enable SPORT Interrupt. */
+            NVIC_ClearPendingIRQ(pDevice->pSportInfo->eIRQn);
+            NVIC_EnableIRQ(pDevice->pSportInfo->eIRQn);
+            pSportRegs->IEN_A |= ((uint32_t) ( BITM_SPORT_IEN_A_DATA
+                                             | BITM_SPORT_IEN_A_SYSDATERR
+                                             | BITM_SPORT_IEN_A_FSERRMSK
+                                             | BITM_SPORT_IEN_A_DERRMSK
+                                             | BITM_SPORT_IEN_A_TF
+                                             )
+                                 );
+            pSportRegs->CTL_A =  pSportCfg->CTL | ((uint32_t)BITM_SPORT_CTL_A_SPEN);
+        ADI_EXIT_CRITICAL_REGION();
+    }
+    return result;
+}
+
+/**
+ * @brief       This function returns the address of a processed buffer. This
+ *              is a blocking function: it waits until a buffer has been dealt
+ *              with. This function returns an error if a callback function is
+ *              registered. #adi_sport_IsBufferAvailable can be used as a peek
+ *              function to know whether a buffer is available.
+ *
+ * @param [in]  hDevice  Device handle to SPORT device, obtained when a SPORT
+ *                       device is openedsuccessfully.
+ *
+ * @param [out] ppBuffer Pointer to a location where the the address of the
+ *                       buffer is to be written. Contains the address of an
+ *                       "empty" buffer (i.e the content of the buffer is
+ *                       transmitted) OR "filled" buffer which contains the
+ *                       received data.
+ *
+ * @param [out] pHwError Pointer to 32-bit value reporting SPORT/DMA events
+ *                       that can occur when processing buffer ppBuffer.
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                Successfully returned. ppBuffer points
+ *                                      to the address of the buffer.
+ *
+ *  - #ADI_SPORT_FAILED                 Failed to get the buffer since device
+ *                                      is operating in call back mode.
+ *                                      ppBuffer points NULL.
+ *
+ *  - #ADI_SPORT_HW_ERROR               SPORT hardware or DMA error detected
+ *
+ *  - #ADI_SPORT_INVALID_HANDLE   [D]   Invalid SPORT device handle.
+ *
+ * @sa          adi_sport_SubmitBuffer()
+ * @sa          adi_sport_IsBufferAvailable()
+ *
+ */
+ADI_SPORT_RESULT adi_sport_GetBuffer(ADI_SPORT_HANDLE   const hDevice,
+                                     void **            const ppBuffer,
+                                     uint32_t *               pHwError)
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+    ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE*) hDevice;   /* Pointer to SPORT device instance */
+
+    *ppBuffer = NULL;
+#ifdef ADI_DEBUG
+    if (ADI_SPORT_SUCCESS != (result=ValidateHandle(pDevice)))  /* Validate the given handle */
+    {
+    }
+    else
+#endif /* ADI_DEBUG */
+    if (NULL != pDevice->pfCallback)
+    {
+        result = ADI_SPORT_FAILED;
+    } else {
+        ADI_DT_CHANNEL * pSportChnl = &pDevice->sportChannel;
+
+        SEM_PEND(pSportChnl,ADI_SPORT_FAILED);                          /* wait for a submitted buffer to be processed */
+
+        ADI_INT_STATUS_ALLOC();
+        ADI_ENTER_CRITICAL_REGION();
+            *pHwError = pDevice->nHwError;
+            pDevice->nHwError = 0u;
+            *ppBuffer  = pSportChnl->pActiveBuffer->pStartAddress;      /* return the buffer start address in *ppBuffer */
+            pSportChnl->pActiveBuffer->pStartAddress = NULL;            /* clear the free buffer address */
+            pSportChnl->pActiveBuffer = pSportChnl->pActiveBuffer->pNextBuffer;
+        ADI_EXIT_CRITICAL_REGION();
+        if (0u != *pHwError)
+        {
+            result = ADI_SPORT_HW_ERROR;
+        }
+    }
+    return result;
+}
+
+/**
+ * @brief       Peek function to know whether an empty/filled buffer is available. Call to this
+ *              function is valid only if the call back function is not registered. Call to this
+ *              function results in error if a call back function is registered.
+ *
+ * @param [in]  hDevice      Device handle to SPORT device obtained when a SPORT device is opened
+ *                           successfully.
+ *
+ * @param [out] pbAvailable  Pointer to a boolean variable. Contains "True" if there is an
+ *                           empty/filled buffer and a call to #adi_sport_GetBuffer is ensured to be
+ *                           successful. Contains "false" if there is no empty buffer.
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                Successfully retrieved the status of availability of the buffer.
+ *  - #ADI_SPORT_INVALID_HANDLE         Failed to retrieve the status of the buffer availability.
+ *  - #ADI_SPORT_OPERATION_NOT_ALLOWED  Function cannot be called (no buffer to be processed or callback function registered).
+ *  - ADI_SPORT_PERIPHERAL_ERROR        Hardware error detected
+ *
+ * @sa          adi_sport_GetBuffer()
+ * @sa          adi_sport_GetBuffer()
+ *
+ */
+ADI_SPORT_RESULT adi_sport_IsBufferAvailable(ADI_SPORT_HANDLE const hDevice,
+                                             bool *           const pbAvailable)
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+    ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE*) hDevice;   /* Pointer to SPORT device instance */
+
+    *pbAvailable = false;
+#ifdef ADI_DEBUG
+    if (ADI_SPORT_SUCCESS != (result=ValidateHandle(pDevice)))  /* Validate the given handle */
+    {
+    }
+    else
+#endif /* ADI_DEBUG */
+    if (NULL != pDevice->pfCallback)
+    {
+        result = ADI_SPORT_OPERATION_NOT_ALLOWED;
+    }
+    else
+    {
+        ADI_DT_BUFF_INFO * pActiveBuffer = pDevice->sportChannel.pActiveBuffer;
+
+        if (pActiveBuffer->pStartAddress == NULL)
+        {
+            result = ADI_SPORT_OPERATION_NOT_ALLOWED;
+        }
+        else if (false == pActiveBuffer->bInUse)                /* this buffer has been processed by the SPORT */
+        {
+            *pbAvailable = true;
+        }
+        else
+        {
+        }
+    }
+    return result;
+}
+
+/**
+ * @brief       Register and unregister a Callback function with the SPORT device driver.
+ *              A registered call back function will be called, if not NULL, when a buffer
+ *              is processed OR hardware error(s) encountered.
+ *
+ * @param [in]  hDevice     Device handle to SPORT device is obtained when a SPORT device is opened
+ *                          successfully.
+ *
+ * @param [in]  pfCallback  Function pointer to Callback function. Passing a NULL pointer will
+ *                          unregister the call back function.
+ *
+ * @param [in]  pCBparam    Call back function parameter.
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                    Successfully registered specified callback function.
+ *
+ *  - #ADI_SPORT_INVALID_HANDLE        [D]  Invalid SPORT device handle.
+ *
+ *  - #ADI_SPORT_OPERATION_NOT_ALLOWED [D]  Operation is not allowed when data flow is enabled.
+ *
+ */
+ADI_SPORT_RESULT adi_sport_RegisterCallback(ADI_SPORT_HANDLE    const hDevice,
+                                            ADI_CALLBACK        const pfCallback,
+                                            void *              const pCBparam)
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+    ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice;   /* Pointer to SPORT device instance */
+#ifdef ADI_DEBUG
+    /* Validate the given handle */
+    if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice)))
+    {
+    }
+    /* Check if the data flow is already enabled */
+    else if (ADI_SPORT_STATE_DATA_FLOW_ENABLED == pDevice->pSportInfo->eState)
+    {
+        /* Not allowed to register a callback if the data flow is enabled. */
+        result = ADI_SPORT_OPERATION_NOT_ALLOWED;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        ADI_INT_STATUS_ALLOC();
+        ADI_ENTER_CRITICAL_REGION();
+            pDevice->pfCallback = pfCallback;   /* Store the address of the callback function */
+            pDevice->pCBParam   = pCBparam;     /* Store the call back parameter */
+        ADI_EXIT_CRITICAL_REGION();
+    }
+    return result;
+}
+
+/**
+ * @brief       Sets data format for the specified SPORT device.
+ *
+ * @details     Sets data type,Big endian (MSB first) OR Little endian (LSB first) and word
+ *              length(in bits) for the specified SPORT device.This function return error if the
+ *              device is already enabled.
+ *
+ * @param [in]  hDevice              Device handle to SPORT device.
+ *
+ * @param [in]  nWordLength          Specify the word size of the data. Valid range is from
+ *                                   4(nWordLength = 3) to 32(nWordLength =31).
+ *
+ * @param [in]  bLSBFirst            Configure the specified SPORT device to operate either LSB
+ *                                   first or MSB first.
+ * \n
+ * \n                                true : LSB first (Little endian) .
+ * \n
+ * \n                                false : MSB first (Big endian)
+ *
+ * @param [in]  ePackMode            Mode of packging need to configured. Please refer #ADI_SPORT_PACKING_MODE.
+ *
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                    Successfully configured the device to operate in
+ *                                          specified data format.
+ *
+ *  - #ADI_SPORT_INVALID_HANDLE        [D]  Invalid SPORT device handle.
+ *
+ *  - #ADI_SPORT_INVALID_WORD_LENGTH   [D]  Invalid word size.
+ *
+ *  - #ADI_SPORT_OPERATION_NOT_ALLOWED [D]  Operation is not allowed when data flow is enabled.
+ *
+ */
+ADI_SPORT_RESULT adi_sport_ConfigData(ADI_SPORT_HANDLE const            hDevice,
+                                      const uint8_t                     nWordLength,
+                                      const ADI_SPORT_PACKING_MODE      ePackMode,
+                                      const bool                        bLSBFirst
+                                      )
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+    ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice;                  /* Pointer to SPORT device instance */
+#ifdef ADI_DEBUG
+    if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice)))
+    {
+    }
+    if(pDevice->pSportInfo->eState == ADI_SPORT_STATE_DATA_FLOW_ENABLED)        /* Not allowed to change when data flow is enabled */
+    {
+        result = ADI_SPORT_OPERATION_NOT_ALLOWED;
+    }
+    else
+#endif /* ADI_DEBUG */
+    if (nWordLength > SPORT_WORD_TRANSFER_LENGTH)
+    {
+        result = ADI_SPORT_INVALID_WORD_LENGTH;
+    }
+    else
+    {
+        ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo;               /* short cut to SPORT information */
+        ADI_SPORT_CONFIG * pSportCfg = &pSportInfo->sportCfg;                   /* short cut to SPORT configuration */
+        const uint32_t bytesPerData = ((nWordLength < 9u) ? (1u) : ((nWordLength < 17u) ? (2u) : (4u)));
+
+        const uint32_t wordPos = (uint32_t) BITP_SPORT_CTL_A_SLEN;
+        const uint32_t wordLen = (uint32_t) nWordLength;
+        const uint32_t ctlSlen = (wordLen - 1u) << wordPos;
+        const uint32_t packMode = (uint32_t) ePackMode;
+        const uint32_t ctlSlenBits = (0x1Fu  << wordPos);
+        const uint32_t ctlDataMask = ~(BITM_SPORT_DATA_CONFIG | ctlSlenBits | BITM_SPORT_CTL_A_LSBF);
+
+        uint32_t ctl = pDevice->pSportInfo->sportCfg.CTL;
+        ctl &= ctlDataMask;                             /* clear all the fields(i.e Set to "0" ) */
+        ctl |= (packMode | ctlSlen);                    /* assign packing and slen information */
+        if (true == bLSBFirst)
+        {
+            ctl |= BITM_SPORT_CTL_A_LSBF;               /* set the the LSB first field */
+        }
+        pDevice->pSportInfo->sportCfg.CTL = ctl;        /* CTL value set - CTL_A is assigned when submitting a buffer */
+
+        SPORT_CHECK_CFG_CTL(pDevice->pSportInfo->sportCfg.CTL);
+
+        switch (bytesPerData)
+        {
+        case 1u:
+            if (((uint32_t) ADI_SPORT_8BIT_PACKING) == packMode)
+            {
+                pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE;
+                pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE;
+            } else {
+                pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_1_BYTE;
+                pSportCfg->DMA_INC = ADI_DMA_INCR_1_BYTE;
+
+                assert(((uint32_t) ADI_SPORT_NO_PACKING) == packMode);
+            }
+            break;
+
+        case 2u:
+          if (((uint32_t) ADI_SPORT_16BIT_PACKING) == packMode)
+          {
+              pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE;
+              pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE;
+          } else {
+              pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_2_BYTE;
+              pSportCfg->DMA_INC = ADI_DMA_INCR_2_BYTE;
+
+              assert(((uint32_t) ADI_SPORT_NO_PACKING) == packMode);
+          }
+          break;
+
+        default:
+            pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE;
+            pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE;
+            assert((4u == bytesPerData) || (((uint32_t) ADI_SPORT_NO_PACKING) == packMode));
+            break;
+        }
+    }
+    return result;
+}
+
+/**
+ * @brief       Configure the clock for the specified SPORT device.
+ *
+ * @details     Configure the SPORT device to use the "internal/external " rising/falling clock
+ *              edge,clock edge and for enabling the gated Clock Mode.
+ *
+ * @details     fspclk = fsclk/(2*( nClockRatio + 1))
+ *
+ * @details     fspclk: frequency of SPORT clock
+ *
+ * @param [in]  hDevice        Device handle to SPORT device.
+ *
+ * @param [in]  nClockRatio    The value which determines the ratio between System clock and SPORT
+ *                             clock as explained above.
+ *
+ *
+ * @param [in]  bUseIntlClock  Boolean flag to indicate whether to use internal clock or external
+ *                             clock for data transmission. By default, device is configured to use
+ *                             the external clock.
+ * \n
+ * \n                          true : Device configured to use Internal clock.
+ * \n
+ * \n                          false : Device configured to use external clock..
+ *
+ * @param [in]  bRisingEdge     Boolean flag to indicate whether to drive data and internal frame
+ *                             sync with rising edge OR falling edge of SP clock.
+ * \n
+ * \n                          true : Use falling edge of the clock.
+ * \n
+ * \n                          false : Use rising edge of the clock.
+ *
+ * @param [in]  bGatedClk      Boolean flag to indicate whether to enable/disable gated clock for
+ *                             the specified SPORT channel.Ignored in Multi channel mode. Clock will
+ *                             be active only when active data is getting transmitted or received
+ *                             when this mode is enabled.
+ * \n                          true : Enable gated clock mode.
+ * \n
+ * \n                          false : Disable gated clock mode.
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                    Successfully configured clock for the specified device.
+ *
+ *  - #ADI_SPORT_INVALID_HANDLE        [D]  Invalid SPORT device handle.
+ *
+ *  - #ADI_SPORT_OPERATION_NOT_ALLOWED [D]  Operation is not allowed when data flow is enabled.
+ *
+ */
+ADI_SPORT_RESULT adi_sport_ConfigClock(ADI_SPORT_HANDLE const      hDevice,
+                                       const uint16_t              nClockRatio,
+                                       const bool                  bUseIntlClock,
+                                       const bool                  bRisingEdge,
+                                       const bool                  bGatedClk)
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+    ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice;  /* Pointer to SPORT device instance */
+
+#ifdef ADI_DEBUG
+    if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice)))
+    {
+    }
+    else if (ADI_SPORT_STATE_DATA_FLOW_ENABLED == pDevice->pSportInfo->eState)
+    {
+        result = ADI_SPORT_OPERATION_NOT_ALLOWED;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg;
+        uint32_t clockRatio = (uint32_t) nClockRatio;
+
+        uint32_t ctl = pSportCfg->CTL;
+        uint32_t dv = pSportCfg->DIV;
+
+        ctl &= ~BITM_SPORT_CLOCK_CONFIG;                /* clear all clock configuration fields */
+
+        dv &= ~BITM_SPORT_DIV_A_CLKDIV;
+        dv |= (clockRatio & BITM_SPORT_DIV_A_CLKDIV);   /* update the clock divisior value */
+
+        if (true == bUseIntlClock)
+        {
+            ctl  |= BITM_SPORT_CTL_A_ICLK;              /* select the internal clock */
+        }
+        if (true == bRisingEdge)
+        {
+            ctl |= BITM_SPORT_CTL_A_CKRE;               /* select the rising edge of the  clock */
+        }
+        if (true == bGatedClk)
+        {
+            ctl |= BITM_SPORT_CTL_A_GCLKEN;             /* Enable the Gated clock */
+        }
+        pDevice->pSportInfo->pSportRegs->DIV_A = pSportCfg->DIV = dv;  /* DIV value set */
+        pSportCfg->CTL = ctl;                           /* CTL value set - CTL_A is assigned when submitting a buffer */
+
+        SPORT_CHECK_CFG_CTL(pSportCfg->CTL);
+    }
+    return result;
+}
+
+/**
+ * @brief       Frame Sync(FS) configuration for the specified SPORT.
+ *
+ * @details     Configure the SPORT to use internal/external frame sync,level/edge sensitive
+ *              early/late frame sync etc.
+ *
+ * @param [in]  hDevice           Device handle to SPORT device.
+ *
+ * @param [in]  nFsDivisor        The value which decides the number of SPORT clock cycles between
+ *                                each frame count.
+ *
+ * @param [in]  bFSRequired       Boolean flag to indicate whether frame sync required OR not to
+ *                                the frame sync for the data transfer.
+ * \n
+ * \n                             true : Device requires a frame sync for its operation.
+ * \n
+ * \n                             false : Device does not requires a frame sync for its operation
+ * \n
+ * \n
+ *
+ * @param [in]  bInternalFS       Boolean flag to indicate whether to configure the specified SPORT
+ *                                device to use the internal frame sync OR external frame sync as
+ *                                below.
+ * \n
+ * \n                             true : Use internal frame sync.
+ * \n
+ * \n                             false : Use external frame sync
+ * \n
+ * \n
+ *
+ * @param [in]  bDataFS           Boolean flag to indicate whether to configure the specified SPORT
+ *                                device to use the data-independent frame sync OR Serial port uses
+ *                                a data-dependent frame sync. Valid only if the specified device is
+ *                                in "transmit"(TX)mode . Ignored if the device is opened in
+ *                                "receive"(RX) mode.
+ * \n
+ * \n                             true : Use data-independent frame sync.
+ * \n
+ * \n                             false : Use data-dependent frame sync.
+ * \n
+ * \n
+ *
+ * @param [in]  bActiveLowFS      Boolean flag to indicate whether to configure the specified SPORT
+ *                                device for active low frame sync OR active high frame sync. Call
+ *                                to this function will return error if SPORT is configured in I2S
+ *                                mode.
+ * \n
+ * \n                             true : Use active low frame sync.
+ * \n
+ * \n                             false : Use active high frame sync.
+ * \n
+ * \n
+ *
+ * @param [in]  bLateFS           Boolean flag to indicate whether to use the late frame sync OR
+ *                                Early frame sync.
+ * \n
+ * \n                             true : Use late frame sync.
+ * \n
+ * \n                             false : Use Early frame sync.
+ * \n
+ * \n
+ *
+* @param [in]  bFSErrorOperation  Frame Sync Error Operation.  This
+ *\n                              decides the way the SPORT responds when a frame sync error occurs.
+ * \n
+ * \n                             true : When frame Sync error occurs, discard the receive data.
+ * \n
+ * \n                             false : Flag the Frame Sync error and continue normal operation
+    * \n
+ * \n
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                    Successfully configured the frame sync requirement.
+ *
+ *  - #ADI_SPORT_INVALID_HANDLE        [D]  Invalid SPORT device handle.
+ *
+ *  - #ADI_SPORT_OPERATION_NOT_ALLOWED [D]  Operation is not allowed when data flow is enabled.
+ *
+ */
+ADI_SPORT_RESULT adi_sport_ConfigFrameSync(ADI_SPORT_HANDLE const       hDevice,
+                                           const uint16_t               nFsDivisor,
+                                           const bool                   bFSRequired,
+                                           const bool                   bInternalFS,
+                                           const bool                   bDataFS,
+                                           const bool                   bActiveLowFS,
+                                           const bool                   bLateFS,
+                                           const bool                   bFSErrorOperation)
+{
+    ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice;          /* Pointer to SPORT device instance */
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+
+#ifdef ADI_DEBUG
+    /* Validate the given handle */
+    if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice)))
+    {
+    }
+    else if(pDevice->pSportInfo->eState == ADI_SPORT_STATE_DATA_FLOW_ENABLED)
+    {
+        result = ADI_SPORT_OPERATION_NOT_ALLOWED;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg;
+        const uint32_t fsDivisor = (uint32_t) nFsDivisor;
+
+        uint32_t ctl = pSportCfg->CTL;
+        uint32_t dv = pSportCfg->DIV;
+
+        dv &= ~BITM_SPORT_DIV_A_FSDIV;                  /* clear all the fields of frame sync */
+        dv |= (fsDivisor << BITP_SPORT_DIV_A_FSDIV);
+
+        ctl &= ~BITM_SPORT_FS_CONFIG;                   /* clear all the fields of frame sync */
+
+        if ((ADI_SPORT_DIR_RX == pDevice->eDirection) || (true == bDataFS))
+        {
+            ctl |= BITM_SPORT_CTL_A_DIFS;               /* Set this bit when SPORT is opened in RX mode */
+        }
+        if (true == bFSRequired)                        /* "Frame sync required" is reserved when device */
+        {                                               /* is operating in I2S and MC mode */
+            ctl |= BITM_SPORT_CTL_A_FSR;                /* Frame Sync(FS) is required */
+        }
+        if (true == bInternalFS)
+        {
+            ctl |= BITM_SPORT_CTL_A_IFS;                /* Select the internal Frame Sync(FS)*/
+        }
+        if (true == bActiveLowFS)
+        {
+            ctl |= BITM_SPORT_CTL_A_LFS;                /* Select the Active High Frame Sync(FS)*/
+        }
+        if (true == bLateFS)
+        {
+            ctl |= BITM_SPORT_CTL_A_LAFS;               /* Select the Late Frame Sync(FS)*/
+        }
+        if (true == bFSErrorOperation)
+        {
+            ctl |= BITM_SPORT_CTL_A_FSERRMODE;          /* Select the edge sensitive Frame Sync(FS)*/
+        }
+        pDevice->pSportInfo->pSportRegs->DIV_A = pSportCfg->DIV = dv;   /* DIV value set */
+        pSportCfg->CTL = ctl;                           /* CTL value set - CTL_A is assigned when submitting a buffer */
+
+        SPORT_CHECK_CFG_CTL(pSportCfg->CTL);
+    }
+    return result;
+}
+
+/**
+ * @brief       Configure the SPORT use the Clocks and Frame Sync of other Half-Sport
+ *
+ * @param [in]  hDevice       Device handle to SPORT device.
+ *
+ * @param [in]  bUseOtherFS   Boolean flag to indicate whether to use own Frame Sync(false) OR to
+ *                            use frame sync of other half SPORT (true).
+ * \n
+ * \n                         true : Use frame sync of other half SPORT device.
+ * \n
+ * \n                         false : Use own frame sync.
+ *
+ * @param [in]  bUseOtherClk  Boolean flag to indicate whether to use own clock clock(false) OR to
+ *                            use clock of other half SPORT(true).
+ * \n
+ * \n                         true : Use clock of other half SPORT device.
+ * \n
+ * \n                         false : Use own clock.
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                    Successfully enabled the specified SPORT to use the clk
+ *                                          and FS of other half SPORT.
+ *
+ *  - #ADI_SPORT_INVALID_HANDLE        [D]  Invalid SPORT device handle.
+ *
+ *  - #ADI_SPORT_OPERATION_NOT_ALLOWED [D]  Operation is not allowed when data flow is enabled.
+ *
+ */
+ADI_SPORT_RESULT adi_sport_MultiplexSportSignal(ADI_SPORT_HANDLE const  hDevice,
+                                                const bool              bUseOtherFS,
+                                                const bool              bUseOtherClk)
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+    ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *)hDevice;   /* Pointer to SPORT device instance */
+#ifdef ADI_DEBUG
+    if((result = ValidateHandle(pDevice)) != ADI_SPORT_SUCCESS) /* Validate the given handle */
+    {
+    }
+    else if (pDevice->pSportInfo->eState == ADI_SPORT_STATE_DATA_FLOW_ENABLED)
+    {
+        result = ADI_SPORT_OPERATION_NOT_ALLOWED;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg;
+        uint32_t ctl = pSportCfg->CTL;
+
+        /* clear the muxing fields of the control register 2 */
+        ctl &= (uint32_t)(~(BITM_SPORT_CTL_A_CKMUXSEL | BITM_SPORT_CTL_A_FSMUXSEL));
+        if (true == bUseOtherFS)
+        {
+            ctl |= BITM_SPORT_CTL_A_FSMUXSEL;   /* Use the  the frame sync of  other half sport*/
+        }
+        if(bUseOtherClk  == true)
+        {
+            ctl |= BITM_SPORT_CTL_A_CKMUXSEL;   /* Use the  the clock of  other half sport*/
+        }
+        pSportCfg->CTL = ctl;                   /* CTL value set - CTL_A is assigned when submitting a buffer */
+
+        SPORT_CHECK_CFG_CTL(pSportCfg->CTL);
+    }
+
+    return result;
+}
+/**
+ * @brief       Configure the SPORT use the Clocks and Frame Sync of other Half-Sport
+ *
+ * @param [in]  hDevice       Device handle to SPORT device.
+ *
+ * @param [in]  nFSDuration  Specify the value of the number of clocks which would be programmed corresponding to the
+ *                           desired time duration from assertion of CONVT signal to Frame sync signal
+ *
+ * @param [in]  nWidth       Specify the value of the number of serial clocks for which CONVT signal should be active.
+
+ *
+ * @param [in]  bActiveLow    Boolean flag to indicate the polarity of the Convt signal.
+ * \n
+ * \n                         true :  Active low Polarity.
+ * \n
+ * \n                         false : Active High Polarity.
+ *
+ * @return      Status
+ *
+ *  - #ADI_SPORT_SUCCESS                    Successfully enabled the specified SPORT to use the clk
+ *                                          and FS of other half SPORT.
+ *
+ *  - #ADI_SPORT_INVALID_HANDLE        [D]  Invalid SPORT device handle.
+ *
+ *  - #ADI_SPORT_OPERATION_NOT_ALLOWED [D]  Operation is not allowed when data flow is enabled.
+ *
+ */
+ADI_SPORT_RESULT adi_sport_ConfigTimerMode(ADI_SPORT_HANDLE const       hDevice,
+                                           const uint8_t                nFSDuration,
+                                           const uint8_t                nWidth,
+                                           const bool                   bActiveLow)
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS;
+    ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE*) hDevice;   /* Pointer to SPORT device instance */
+
+#ifdef ADI_DEBUG    /* Validate the given handle */
+    if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice)))
+    {
+    }
+    else if (ADI_SPORT_STATE_DATA_FLOW_ENABLED == pDevice->pSportInfo->eState)
+    {
+        result = ADI_SPORT_OPERATION_NOT_ALLOWED;
+    }
+    else
+#endif /* ADI_DEBUG */
+    {
+        ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg;
+        uint32_t cnvt = pSportCfg->TIM_CONVT;
+
+        /* clear the muxing fields of the control register 2 */
+        cnvt &= (uint32_t)(~(BITM_SPORT_CNVT_A_POL |  BITM_SPORT_CNVT_A_WID | BITM_SPORT_CNVT_A_CNVT2FS ));
+        cnvt |= (((uint32_t) nFSDuration << ((uint32_t) BITP_SPORT_CNVT_A_CNVT2FS)) | ((uint32_t) nWidth));
+        if(bActiveLow == true)
+        {
+          cnvt |= ((uint32_t) BITM_SPORT_CNVT_A_POL);   /* Use the  the clock of  other half sport*/
+        }
+        pDevice->pSportInfo->pSportRegs->CNVT_A = pSportCfg->TIM_CONVT = cnvt;
+    }
+    return result;
+}
+
+/*! \cond PRIVATE */
+
+/**
+ * @brief       Create a circular linked list for buffer management.
+ *
+ * @details     Create a circular linked list for buffer management and
+ *              initialize the free buffer, the fill buffer and he active
+ *              buffer with the first buffer in this circular array.
+ *
+ * @param [in]  hDevice  Device handle to SPORT device.
+ *
+ * @param [in]  NumDesc  Number of descriptorS.
+ *
+ */
+static inline void sport_Init (ADI_SPORT_DEVICE *pDevice)
+{
+    uint32_t            i;
+    ADI_DT_CHANNEL      *pChannel = &pDevice->sportChannel;
+    ADI_DT_BUFF_INFO    *pBufInfo = &pChannel->BufInfo[0];              /* initialize this variable with the first array element */
+    ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo;           /* short cut to SPORT information */
+    ADI_SPORT_CONFIG * pSportCfg = &pSportInfo->sportCfg;               /* short cut to SPORT configuration */
+    const uint32_t bytesPerData = GetBytesPerSportData(pSportCfg->CTL); /* number of bytes in SPORT data (1, 2, or 4) */
+    const uint32_t packMode = SPORT_GET_PACKEN(pSportCfg->CTL);         /* SPORT data pack mode */
+
+    /* Initialize the all descriptors. Make it circular. */
+    for(i = 0u; i < ADI_DT_BUFNUM; i++)
+    {
+        pBufInfo[i].pStartAddress  =   NULL;
+        pBufInfo[i].nCount         =   0u;
+        pBufInfo[i].nIndex         =   0u;
+        pBufInfo[i].pNextBuffer    =   &pBufInfo[(i+1u) % ADI_DT_BUFNUM];       /* link the buffers in a circular way */
+    }
+    pChannel->pFreeBuffer   =  &pChannel->BufInfo[0u];  /* the first free buffer is the first array element */
+    pChannel->pActiveBuffer =  &pChannel->BufInfo[0u];  /* the first active buffer is the first array element */
+    pChannel->pFillBuffer   =  &pChannel->BufInfo[0u];  /* the first fill buffer is the first array element */
+
+    switch (bytesPerData)
+    {
+    case 1u:
+        if (SPORT_BIT_PACK_8 == packMode)
+        {
+            pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE;
+            pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE;
+        } else {
+            pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_1_BYTE;
+            pSportCfg->DMA_INC = ADI_DMA_INCR_1_BYTE;
+
+            assert(SPORT_BIT_PACK_NONE == packMode);
+        }
+        break;
+
+    case 2u:
+        if (SPORT_BIT_PACK_16 == packMode)
+        {
+            pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE;
+            pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE;
+        } else {
+            pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_2_BYTE;
+            pSportCfg->DMA_INC = ADI_DMA_INCR_2_BYTE;
+
+            assert(SPORT_BIT_PACK_NONE == packMode);
+        }
+        break;
+
+  default:
+        pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE;
+        pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE;
+        assert((4u == bytesPerData) || (SPORT_BIT_PACK_NONE == packMode));
+        break;
+    }
+}
+
+/*
+ * @brief       Configure the registers with the half-SPORT
+ *
+ * @param [in]  hDevice         Device handle to SPORT device.
+ * @param [in]  sportCfg     SPORT configuration to be used.
+ *
+ * @return      None
+ */
+static inline void sport_Configure (ADI_SPORT_DEVICE *pDevice, ADI_SPORT_CONFIG const * sportCfg)
+{
+    /* Configure the SPORT device using static configuration parameters.
+     * pSportInfo is mapped to one of the half-SPORT available; this is the
+     * half-SPORT configured. (CTL_A, DIV_A, CNVT_A and NUMTRAN_A map either
+     * to half-SPORT A registers or half-SPORT B registers, depending on
+     * sportRegs.)
+     */
+    volatile ADI_SPORT_TypeDef * sportRegs = pDevice->pSportInfo->pSportRegs;
+    ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg;
+
+    /* record the SPORT default configuration */
+    memcpy(pSportCfg, sportCfg, sizeof(ADI_SPORT_CONFIG));
+
+    switch (pDevice->eDirection)        /* Set the direction of operation */
+    {
+    case ADI_SPORT_DIR_RX:
+        pSportCfg->CTL &= ~BITM_SPORT_CTL_A_SPTRAN;
+        break;
+    case ADI_SPORT_DIR_TX:
+        pSportCfg->CTL |= BITM_SPORT_CTL_A_SPTRAN;
+        break;
+    default:
+        assert(0);
+        break;
+    }
+    /* use the SPORT configuration to setup the SPORT registers */
+    sportRegs->CTL_A      = pSportCfg->CTL;
+    sportRegs->DIV_A      = pSportCfg->DIV;
+    sportRegs->CNVT_A     = pSportCfg->TIM_CONVT;
+    sportRegs->NUMTRAN_A  = 0u;
+
+    SPORT_CHECK_CFG_CTL(pSportCfg->CTL);
+}
+
+#ifdef ADI_DEBUG
+static ADI_SPORT_RESULT ValidateHandle(ADI_SPORT_HANDLE const hDevice)
+{
+    ADI_SPORT_RESULT result = ADI_SPORT_INVALID_HANDLE;
+    ADI_SPORT_DEVICE * pInDevice = (ADI_SPORT_DEVICE*) hDevice;
+    ADI_SPORT_DEVICE_INFO *poDeviceInfo = &gSportDevInfo[0][0];
+    uint32_t i;
+
+    /* Pointer to SPORT device instance */
+    for (i=0u; i<(ADI_SPORT_NUM_INSTANCES << 1u); i++)        /* 2 half-devices per SPORT */
+    {
+        if (pInDevice == poDeviceInfo->hDevice)
+        {
+            result = ADI_SPORT_SUCCESS;
+            break;
+        }
+        poDeviceInfo++;
+    }
+    return result;
+}
+#endif /* ADI_DEBUG */
+
+/* mask for events to be recorded in the driver HW error */
+#define recEvt  ((uint32_t) (BITM_SPORT_STAT_A_SYSDATERR | BITM_SPORT_STAT_A_FSERR | BITM_SPORT_STAT_A_DERR))
+
+/* bits to be cleared by the ISR */
+#define clrEvt  ((recEvt | BITM_SPORT_STAT_A_TFI))
+
+static void sport_Terminate(ADI_SPORT_DEVICE * pDevice)
+{
+    ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo;           /* get SPORT device information */
+    volatile ADI_SPORT_TypeDef * pRegs = pSportInfo->pSportRegs;        /* access SPORT registers */
+
+    ADI_DT_CHANNEL * pSportChnl = &pDevice->sportChannel;
+    ADI_DT_BUFF_INFO * pBuff = pSportChnl->pFillBuffer;
+
+    pRegs->CTL_A &= ~BITM_SPORT_CTL_A_SPEN;                             /* disable SPORT */
+    pRegs->IEN_A &= ~(BITM_SPORT_IEN_A_TF | BITM_SPORT_IEN_A_DATA);     /* disable SPORT interrupts */
+    pRegs->NUMTRAN_A = 0u;
+
+#ifdef ADI_DEBUG
+    {
+        /* ============================================= */
+        /* Check the number of data transmitted/received */
+        /* nIndex is incremented each time a data packed */
+        /* or unpacked in received. The size in bytes of */
+        /* each data depends on the SPORT configuration. */
+        /* In core driven operations, nCount represents  */
+        /* the number of 32-bit words transmitted.       */
+        /* In DMA driven operations, nCount represents   */
+        /* the number of DMA data transmitted            */
+        /* ============================================= */
+        const uint32_t ctl = pRegs->CTL_A;
+        const uint32_t bytesPerData = GetBytesPerSportData(ctl);
+        const uint32_t nIndex = pBuff->nIndex * (4u / bytesPerData);
+        assert((nIndex>=pBuff->nCount)||(true==pBuff->bDMA));           /* buffer must be fully processed */
+    }
+#endif
+
+    pBuff->bInUse = false;                                              /* mark buffer as ready */
+
+    NVIC_DisableIRQ(pSportInfo->eIRQn);                                 /* suspend SPORT Interrupt */
+    NVIC_DisableIRQ(pSportInfo->eDMAn);                                 /* suspend SPORT DMA interrupt */
+
+    pDevice->pSportInfo->eState = ADI_SPORT_STATE_PAUSED;
+
+    if(NULL != pDevice->pfCallback)                                     /* Call the callback function if one is registered. */
+    {
+        uint32_t evt = ( (ADI_SPORT_DIR_RX == pDevice->eDirection)
+                       ? ((uint32_t) ADI_SPORT_EVENT_RX_BUFFER_PROCESSED)
+                       : ((uint32_t) ADI_SPORT_EVENT_TX_BUFFER_PROCESSED)
+                       );
+
+        pDevice->pfCallback(pDevice->pCBParam,evt,pBuff->pStartAddress);
+        pBuff->pStartAddress = NULL;                                    /* No need to keep the processed buffer address */
+    }
+    else
+    {
+        SEM_POST(pSportChnl);                                           /* signal the buffer availability through a semaphore */
+    }
+    pRegs->STAT_A = clrEvt;                                             /* clear status register bits (W1C) */
+    pSportChnl->eDataTranferMode = ADI_DT_MODE_NONE;                    /* SPORT is available */
+    pBuff = pBuff->pNextBuffer;                                         /* point to the next buffer to process */
+    pSportChnl->pFillBuffer = pBuff;                                    /* this is the new pFillBuffer */
+
+    if ((0u != pBuff->pStartAddress) && (true == pBuff->bInUse))        /* valid buffer not being processed yet */
+    {
+        ADI_SPORT_RESULT result;
+
+        pSportChnl->eDataTranferMode = ADI_DT_MODE_NONBLOCKING;
+        if (true == pBuff->bDMA)
+        {
+            result = sport_SubmitBufferDmaMode(pDevice, pBuff);
+        }
+        else
+        {
+            result = sport_SubmitBufferIntMode(pDevice, pBuff);
+        }
+        
+        if(ADI_SPORT_SUCCESS != result)                                 /* if an error occurred...*/
+        {
+            pSportChnl->eDataTranferMode = ADI_DT_MODE_NONE;            /* SPORT is available */
+        }
+    }
+}
+
+/*
+ * @brief       Common SPORT interrupt handler function called by SPORT0 A and SPORT0 B ISRs.
+ *
+ * @details     Process SPORT0 A and B interrupts, recording HW errors that must be reported,
+ *              reading/writing transmitted data, launching new SPORT transmissions if more
+ *              buffers are to be processed, and deactivating the SPORT device if there are
+ *              no pending requests. (Common fucntion for both core driven and DMA driven
+ *              SPORT operations.)
+ *
+ * @param [in]  pDevice         Sport device pointer related to the calling ISR.
+ */
+static void sport_InterruptHandler(ADI_SPORT_DEVICE * pDevice)
+{
+    ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo;           /* get SPORT device information */
+    volatile ADI_SPORT_TypeDef * pRegs = pSportInfo->pSportRegs;        /* access SPORT registers */
+    const uint32_t sportStatus = pRegs->STAT_A;                         /* read SPORT status */
+    const uint32_t dataRequest = (sportStatus & BITM_SPORT_STAT_A_DATA);/* set if any data to be processed by the SPORT */
+    const uint32_t hwEvents = sportStatus & recEvt;                     /* HW events to be recorded in the driver */
+
+
+    /* This implementation assumes an identity mapping between BITM_SPORT_STAT values
+     * and their equivalent event in ADI_SPORT_EVENT, e.g. ADI_SPORT_HW_ERR_FS and
+     * BITM_SPORT_STAT_A_FSERR share the same value. This simplifies event processing
+     * and reports. */
+    assert(((uint32_t) ADI_SPORT_HW_ERR_RX_OVERFLOW) == BITM_SPORT_STAT_A_DERR);
+    assert(((uint32_t) ADI_SPORT_HW_ERR_TX_UNDERFLOW) == BITM_SPORT_STAT_A_DERR);
+    assert(((uint32_t) ADI_SPORT_HW_ERR_FS) == BITM_SPORT_STAT_A_FSERR);
+    assert(((uint32_t) ADI_SPORT_HW_ERR_SYSDATAERR) == BITM_SPORT_STAT_A_SYSDATERR);
+
+    if (0u != hwEvents)                                                 /* any event recorded? */
+    {
+        if (NULL != pDevice->pfCallback)                                /* if a callback has been registered ? */
+        {
+            pDevice->pfCallback(pDevice->pCBParam,hwEvents,NULL);       /* then call it */
+        } else {
+            pDevice->nHwError |= hwEvents;                              /* else set the driver HW error */
+            SEM_POST(&pDevice->sportChannel);                           /* and signal this through a semaphore */
+        }
+    }
+
+    if (0u != dataRequest)                                              /* Tx FIFO is not full or Rx FIFO is not empty */
+    {
+        ADI_DT_BUFF_INFO * pBuff = pDevice->sportChannel.pFillBuffer;
+        uint32_t * pNextWord = (uint32_t*) pBuff->pStartAddress;
+
+        if ((NULL != pNextWord) && (pBuff->nIndex < pBuff->nCount))     /* This buffer has not been fully processed yet */
+        {
+            if (ADI_SPORT_DIR_RX == pDevice->eDirection)
+            {
+                pNextWord[pBuff->nIndex++] = pRegs->RX_A;               /* Read the data received in RX and increment the index */
+                while (!DXS_FIFO_IS_EMPTY(pRegs->STAT_A))               /* and if there are more data available in the FIFO */
+                {
+                    pNextWord[pBuff->nIndex++] = pRegs->RX_A;           /* Read remaining data received in RX and increment the index */
+                }
+            }
+            else
+            {
+                pRegs->TX_A = pNextWord[pBuff->nIndex++];               /* Write the data to be sent into TX and increment the index */
+                while (  (pBuff->nIndex < pBuff->nCount)                /* and if there are more data to be sent */
+                      && (!DXS_FIFO_IS_FULL(pRegs->STAT_A))             /* and there is still room in the FIFO */
+                      )
+                {
+                    pRegs->TX_A = pNextWord[pBuff->nIndex++];           /* then write more data to be sent into TX and increment the index */
+                }
+            }
+        }
+    }
+
+    /* ========================================================== */
+    /* Common to core driven operations and DMA driven operations */
+    /* ========================================================== */
+    if (0u != (pRegs->STAT_A & BITM_SPORT_STAT_A_TFI))                  /* If a SPORT Tx/Rx request has finished */
+    {
+        sport_Terminate(pDevice);
+    }
+
+#if defined(ADI_CYCLECOUNT_SPORT_ISR_ENABLED) && (ADI_CYCLECOUNT_SPORT_ISR_ENABLED == 1u)
+    ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_SPORT);    
+#endif
+}
+
+/** Interrupt handler for SPORT0 A */
+void SPORT0A_Int_Handler(void)
+{
+    ISR_PROLOG();
+        sport_InterruptHandler(gSportDevInfo[0][ADI_HALF_SPORT_A].hDevice);
+    ISR_EPILOG();
+}
+
+/** Interrupt handler for SPORT0 B */
+void SPORT0B_Int_Handler(void)
+{
+    ISR_PROLOG();
+        sport_InterruptHandler(gSportDevInfo[0][ADI_HALF_SPORT_B].hDevice);
+    ISR_EPILOG();
+}
+
+void DMA_SPORT0A_Int_Handler(void)
+{
+    ISR_PROLOG();
+        /**
+         * if SPORT is in Rx mode, then the DMA interrupt is the signal for
+         * end of transmission: buffer is ready. (In Tx mode, the signal is
+         * the TFI event and SPORT DMA interrup is not enabled).
+         */
+        sport_Terminate(gSportDevInfo[0][ADI_HALF_SPORT_A].hDevice);
+#if defined(ADI_CYCLECOUNT_SPORT_ISR_ENABLED) && (ADI_CYCLECOUNT_SPORT_ISR_ENABLED == 1u)
+        ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_SPORT);    
+#endif
+    ISR_EPILOG();
+}
+
+void DMA_SPORT0B_Int_Handler(void)
+{
+    ISR_PROLOG();
+        /**
+         * if SPORT is in Rx mode, then the DMA interrupt is the signal for
+         * end of transmission: buffer is ready. (In Tx mode, the signal is
+         * the TFI event and SPORT DMA interrup is not enabled).
+         */
+        sport_Terminate(gSportDevInfo[0][ADI_HALF_SPORT_B].hDevice);
+#if defined(ADI_CYCLECOUNT_SPORT_ISR_ENABLED) && (ADI_CYCLECOUNT_SPORT_ISR_ENABLED == 1u)
+        ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_SPORT);    
+#endif
+    ISR_EPILOG();
+}
+
+static void sport_DmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg)
+{
+    ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE*) pCBParam;          /* Recover the device handle. */
+    ADI_DT_BUFF_INFO * pFillBuffer = pDevice->sportChannel.pFillBuffer;
+    ADI_DT_BUFF_INFO * pNextBuffer = pFillBuffer->pNextBuffer;
+    uint32_t nEvent = 0u;
+
+    if (ADI_DMA_EVENT_ERR_BUS == Event)
+    {
+        nEvent = (uint32_t) ADI_SPORT_DMA_ERR_BUS;                      /* SPORT DMA bus error detected  */
+    } else {
+        assert(ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR == Event);
+        nEvent = (uint32_t) ADI_SPORT_DMA_ERR_INVALID_DESCRIPTOR;       /* SPORT DMA invalid descriptor error detected  */
+    }
+
+    pDevice->nHwError |= nEvent;
+    sport_InterruptHandler(pDevice);
+
+    while (  (NULL != pNextBuffer->pStartAddress)
+          && (true == pNextBuffer->bInUse)
+          && (true == pNextBuffer->bDMA)
+          )                                                             /* another buffer is pending for a DMA driven request */
+    {
+        pDevice->nHwError |= nEvent;
+        pNextBuffer->bInUse = false;
+        sport_InterruptHandler(pDevice);
+        pNextBuffer = pNextBuffer->pNextBuffer;
+    }
+}
+
+static inline uint32_t GetBytesPerSportData(const uint32_t ctlVal)
+{
+    const uint32_t wlen = SPORT_GET_WLEN(ctlVal);
+    const uint32_t bytesPerData = ((wlen < 9u) ? (1u) : ((wlen < 17u) ? (2u) : (4u)));
+    return bytesPerData;
+}
+
+/*! \endcond */
+
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sport/adi_sport_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sport/adi_sport_def.h
new file mode 100755
index 00000000000..7244562e9ae
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sport/adi_sport_def.h
@@ -0,0 +1,193 @@
+/*! *****************************************************************************
+ * @file:    adi_sport_def.h
+ * @brief:   UART Device Driver definition for processor
+ -----------------------------------------------------------------------------
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+/*! \cond PRIVATE */
+#ifndef ADI_SPORT_DEF_H
+#define ADI_SPORT_DEF_H
+
+#include <drivers/general/adi_data_transfer.h>
+
+#if defined(ADI_CFG_SPORT0A_SERIAL_WLEN)
+#if (ADI_CFG_SPORT0A_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0A_SERIAL_WLEN > 32u)
+#error "Invalid word length : it must be between 4 and 32"
+#endif
+#else
+#error "ADI_CFG_SPORT0A_SERIAL_WLEN undefined!!! "
+#endif
+
+#if defined(ADI_CFG_SPORT0B_SERIAL_WLEN)
+#if (ADI_CFG_SPORT0B_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0B_SERIAL_WLEN > 32u)
+#error "Invalid word length : it must be between 4 and 32"
+#endif
+#else
+#error "ADI_CFG_SPORT0B_SERIAL_WLEN undefined!!! "
+#endif
+
+#define ADI_SPORT_NUM_INSTANCES         (1u)    /*!< Number of SPORT devices available */
+#define ADI_SPORT_NUM_CHANNELS          (2u)    /*!< Number of SPORT channel for each SPORT devcie */
+
+#define BITM_SPORT_DATA_CONFIG  ( BITM_SPORT_CTL_A_LSBF \
+                                | BITM_SPORT_CTL_A_PACK)
+
+#define BITM_SPORT_CLOCK_CONFIG ( BITM_SPORT_CTL_A_ICLK \
+                                | BITM_SPORT_CTL_A_CKRE \
+                                | BITM_SPORT_CTL_A_GCLKEN)
+
+#define BITM_SPORT_FS_CONFIG    ( BITM_SPORT_CTL_A_FSR \
+                                | BITM_SPORT_CTL_A_IFS \
+                                | BITM_SPORT_CTL_A_DIFS \
+                                | BITM_SPORT_CTL_A_LFS \
+                                | BITM_SPORT_CTL_A_LAFS \
+                                | BITM_SPORT_CTL_A_FSERRMODE)
+
+#define SPORT_BYTE_TRANSFER_LENGTH      (8u)
+#define SPORT_HALFWORD_TRANSFER_LENGTH  (16u)
+#define SPORT_WORD_TRANSFER_LENGTH      (32u)
+
+#define SPORT_GET_WLEN(ctlVal)          ((((ctlVal) & (uint32_t) BITM_SPORT_CTL_A_SLEN) >> ((uint32_t) BITP_SPORT_CTL_A_SLEN)) + 1u)
+#define SPORT_GET_PACKEN(ctlVal)        ((ctlVal) & (uint32_t) BITM_SPORT_CTL_A_PACK) >> ((uint32_t) BITP_SPORT_CTL_A_PACK)
+
+#define SPORT_CHECK_CFG_CTL(CFG)        assert(0u == ((CFG) & (((uint32_t)BITM_SPORT_CTL_A_SPEN) | ((uint32_t)BITM_SPORT_CTL_A_DMAEN))))
+
+
+#define SPORT_BIT_PACK_NONE     (((uint32_t) ADI_SPORT_NO_PACKING)    >> ((uint32_t) BITP_SPORT_CTL_A_PACK))
+#define SPORT_BIT_PACK_8        (((uint32_t) ADI_SPORT_8BIT_PACKING)  >> ((uint32_t) BITP_SPORT_CTL_A_PACK))
+#define SPORT_BIT_PACK_16       (((uint32_t) ADI_SPORT_16BIT_PACKING) >> ((uint32_t) BITP_SPORT_CTL_A_PACK))
+
+/*!
+ *****************************************************************************
+ * \struct  ADI_SPORT_STATE
+ *  Enumeration of different SPORT states.
+ *****************************************************************************/
+typedef enum
+{
+    ADI_SPORT_STATE_UNINITIALIZED = 0,  /*!< SPORT is not yet initialized */
+    ADI_SPORT_STATE_INITIALIZED,        /*!< SPORT is initialized */
+    ADI_SPORT_STATE_DATA_FLOW_ENABLED,  /*!< SPORT Tx or Rx data flow is enabled (SPORT peripheral cannot be re-configured) */
+    ADI_SPORT_STATE_DATA_FLOW_DISABLED, /*!< SPORT Tx or Rx data flow is disabled (SPORT peripheral can be re-configured) */
+    ADI_SPORT_STATE_PAUSED
+} ADI_SPORT_STATE;
+
+/*!
+ *****************************************************************************
+ * \struct  ADI_SPORT_CONFIG
+ *  Structure for initializing the static config.
+ *****************************************************************************/
+
+typedef struct _ADI_SPORT_CONFIG
+{
+    uint32_t    CTL;            /*!< SPORT_CTL register. */
+    uint32_t    DIV;            /*!< SPORT_DIV register. */
+    uint32_t    TIM_CONVT;      /*!< TIM_CONVT Register. */
+    uint32_t    DMA_WIDTH;      /*!< DMA_WIDTH */
+    uint32_t    DMA_INC;        /*!< DMA_INC */
+} ADI_SPORT_CONFIG;
+
+/*!
+ *****************************************************************************
+ * \struct  ADI_SPORT_DEVICE_INFO
+ *  SPORT device information.
+ *****************************************************************************/
+typedef struct _ADI_SPORT_DEVICE_INFO
+{
+    volatile ADI_SPORT_TypeDef* pSportRegs;     /*!< Base address of the SPORT registers */
+    ADI_SPORT_CONFIG            sportCfg;       /*!< SPORT configuration data */
+    ADI_SPORT_STATE             eState;         /*!< To indicate the state of the device */
+    const DMA_CHANn_TypeDef     eDMAChnlID;     /*!< DMA channel ID */
+    const IRQn_Type             eDMAn;          /*!< DMA channel IRQ identifier */
+    const IRQn_Type             eIRQn;          /*!< SPORT IRQ identifier */
+    ADI_SPORT_HANDLE            hDevice;        /*!< SPORT handle */
+} ADI_SPORT_DEVICE_INFO;
+
+/******************************************************************************
+ * SPORT Device internal API function prototypes
+ *****************************************************************************/
+
+#define NUM_SPORT_BUFFER                (2u)
+
+/** SPORT driver instance data */
+typedef struct _ADI_SPORT_DEVICE
+{
+    ADI_SPORT_DEVICE_INFO *     pSportInfo;     /*!< pointer to the structure which stores the information about the SPORT instances.*/
+    ADI_SPORT_DIRECTION         eDirection;     /*!< Direction in which the SPORT is opened */
+    ADI_CALLBACK                pfCallback;     /*!< Function pointer for callback function. */
+    void *                      pCBParam;       /*!< Parameter to callback function. */
+    ADI_DT_CHANNEL              sportChannel;   /*!< SPORT channel to manage transmitted data buffers */
+    volatile uint32_t           nHwError;       /*!< variable to store the hardware status */
+} ADI_SPORT_DEVICE;
+
+/** Initialize a SPORT device */
+static inline void sport_Init (ADI_SPORT_DEVICE * pDevice);
+
+/** Configure a SPORT device */
+static inline void sport_Configure (ADI_SPORT_DEVICE *pDevice, ADI_SPORT_CONFIG const * sportCfg);
+
+/** Function prototype for submitting a buffer for SPORT Rx or Tx DMA driven transmission */
+static ADI_SPORT_RESULT sport_SubmitBufferDmaMode(ADI_SPORT_DEVICE * pDevice, ADI_DT_BUFF_INFO * pBuff);
+
+/** Function prototype for submitting a buffer for SPORT Rx or Tx core driven transmission */
+static ADI_SPORT_RESULT sport_SubmitBufferIntMode(ADI_SPORT_DEVICE * pDevice, ADI_DT_BUFF_INFO * pBuff);
+
+/** Fucntion prototype for completing a SPORT transmission (Rx or Tx) */
+static void sport_Terminate(ADI_SPORT_DEVICE * pDevice);
+
+/** Interrupt Handlers */
+
+/** SPORT interrupt handler */
+static void sport_InterruptHandler(ADI_SPORT_DEVICE * pDevice);
+
+static inline void sport_DmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg);
+
+static inline uint32_t GetBytesPerSportData(const uint32_t ctlVal);
+
+/*
+ * Handle Validation function
+*/
+#ifdef ADI_DEBUG
+static ADI_SPORT_RESULT ValidateHandle(ADI_SPORT_HANDLE const hDevice);
+#endif /* ADI_DEBUG */
+
+#endif  /* end of ifndef ADI_SPORT_DEF_H */
+/*! \endcond */
+
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050.h
new file mode 100755
index 00000000000..d2a7a908a41
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050.h
@@ -0,0 +1,5339 @@
+/* ================================================================================
+
+     Project      :   ADuCM4050
+     File         :   ADuCM4050.h
+     Description  :   Register Definitions
+
+     Date         :   Feb 7, 2017
+
+     Copyright (c) 2014-2017 Analog Devices, Inc.  All Rights Reserved.
+     This software is proprietary and confidential to Analog Devices, Inc. and
+     its licensors.
+
+     This file was auto-generated. Do not make local changes to this file.
+
+   ================================================================================ */
+
+#ifndef _DEF_ADUCM4050_H
+#define _DEF_ADUCM4050_H
+
+#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__))
+#include <stdint.h>
+#endif /* _LANGUAGE_C */
+
+
+#if defined (_MISRA_RULES)
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit")
+#pragma diag(suppress:misra_rule_19_7:"ADI header allows function-like macros")
+#pragma diag(suppress:misra_rule_19_13:"ADI headers can use the # and ## preprocessor operators")
+#endif /* _MISRA_RULES */
+
+/* _ADI_MSK_3 might be defined in wrapper includes - otherwise provide a default */
+#if !defined(_ADI_MSK_3)
+/* do not add casts to literal constants in assembly code */
+#if defined(_LANGUAGE_ASM) || defined(__ASSEMBLER__)
+/* Use unsuffixed literals for BITM macros */
+#define _ADI_MSK_3( mask, smask, type ) (mask) 
+#else
+/* Use casted suffixed literals for BITM macros */
+#define _ADI_MSK_3( mask, smask, type ) ((type)(smask))
+#endif
+#endif
+
+#ifndef __ADI_GENERATED_DEF_HEADERS__
+#define __ADI_GENERATED_DEF_HEADERS__    1
+#endif
+
+#define __ADI_HAS_ADC__            1
+#define __ADI_HAS_BEEP__           1
+#define __ADI_HAS_BUSM__           1
+#define __ADI_HAS_CLKG_OSC__       1
+#define __ADI_HAS_CLKG__           1
+#define __ADI_HAS_CLKG_CLK__       1
+#define __ADI_HAS_CRC__            1
+#define __ADI_HAS_CRYPT__          1
+#define __ADI_HAS_DMA__            1
+#define __ADI_HAS_XINT__           1
+#define __ADI_HAS_FLCC__           1
+#define __ADI_HAS_FLCC_CACHE__     1
+#define __ADI_HAS_FLCC_DFT__       1
+#define __ADI_HAS_FLCC_TEST__      1
+#define __ADI_HAS_GPIO__           1
+#define __ADI_HAS_TMR__            1
+#define __ADI_HAS_I2C__            1
+#define __ADI_HAS_NVIC__           1
+#define __ADI_HAS_PMG__            1
+#define __ADI_HAS_PMG_TST__        1
+#define __ADI_HAS_PTI__            1
+#define __ADI_HAS_RNG__            1
+#define __ADI_HAS_RTC__            1
+#define __ADI_HAS_SPI__            1
+#define __ADI_HAS_SPORT__          1
+#define __ADI_HAS_SYS__            1
+#define __ADI_HAS_TMR_RGB__        1
+#define __ADI_HAS_UART__           1
+#define __ADI_HAS_WDT__            1
+
+/* ============================================================================================================================
+        General Purpose Timer
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        TMR0
+   ============================================================================================================================ */
+#define REG_TMR0_LOAD                        0x40000000            /*  TMR0 16-bit Load Value */
+#define REG_TMR0_CURCNT                      0x40000004            /*  TMR0 16-bit Timer Value */
+#define REG_TMR0_CTL                         0x40000008            /*  TMR0 Control */
+#define REG_TMR0_CLRINT                      0x4000000C            /*  TMR0 Clear Interrupt */
+#define REG_TMR0_CAPTURE                     0x40000010            /*  TMR0 Capture */
+#define REG_TMR0_ALOAD                       0x40000014            /*  TMR0 16-bit Load Value, Asynchronous */
+#define REG_TMR0_ACURCNT                     0x40000018            /*  TMR0 16-bit Timer Value, Asynchronous */
+#define REG_TMR0_STAT                        0x4000001C            /*  TMR0 Status */
+#define REG_TMR0_PWMCTL                      0x40000020            /*  TMR0 PWM Control Register */
+#define REG_TMR0_PWMMATCH                    0x40000024            /*  TMR0 PWM Match Value */
+#define REG_TMR0_EVENTSELECT                 0x40000028            /*  TMR0 Timer Event Selection Register */
+
+/* ============================================================================================================================
+        TMR1
+   ============================================================================================================================ */
+#define REG_TMR1_LOAD                        0x40000400            /*  TMR1 16-bit Load Value */
+#define REG_TMR1_CURCNT                      0x40000404            /*  TMR1 16-bit Timer Value */
+#define REG_TMR1_CTL                         0x40000408            /*  TMR1 Control */
+#define REG_TMR1_CLRINT                      0x4000040C            /*  TMR1 Clear Interrupt */
+#define REG_TMR1_CAPTURE                     0x40000410            /*  TMR1 Capture */
+#define REG_TMR1_ALOAD                       0x40000414            /*  TMR1 16-bit Load Value, Asynchronous */
+#define REG_TMR1_ACURCNT                     0x40000418            /*  TMR1 16-bit Timer Value, Asynchronous */
+#define REG_TMR1_STAT                        0x4000041C            /*  TMR1 Status */
+#define REG_TMR1_PWMCTL                      0x40000420            /*  TMR1 PWM Control Register */
+#define REG_TMR1_PWMMATCH                    0x40000424            /*  TMR1 PWM Match Value */
+#define REG_TMR1_EVENTSELECT                 0x40000428            /*  TMR1 Timer Event Selection Register */
+
+/* ============================================================================================================================
+        TMR2
+   ============================================================================================================================ */
+#define REG_TMR2_LOAD                        0x40000800            /*  TMR2 16-bit Load Value */
+#define REG_TMR2_CURCNT                      0x40000804            /*  TMR2 16-bit Timer Value */
+#define REG_TMR2_CTL                         0x40000808            /*  TMR2 Control */
+#define REG_TMR2_CLRINT                      0x4000080C            /*  TMR2 Clear Interrupt */
+#define REG_TMR2_CAPTURE                     0x40000810            /*  TMR2 Capture */
+#define REG_TMR2_ALOAD                       0x40000814            /*  TMR2 16-bit Load Value, Asynchronous */
+#define REG_TMR2_ACURCNT                     0x40000818            /*  TMR2 16-bit Timer Value, Asynchronous */
+#define REG_TMR2_STAT                        0x4000081C            /*  TMR2 Status */
+#define REG_TMR2_PWMCTL                      0x40000820            /*  TMR2 PWM Control Register */
+#define REG_TMR2_PWMMATCH                    0x40000824            /*  TMR2 PWM Match Value */
+#define REG_TMR2_EVENTSELECT                 0x40000828            /*  TMR2 Timer Event Selection Register */
+
+/* ============================================================================================================================
+        TMR Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_LOAD                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_LOAD_VALUE                   0            /*  Load Value */
+#define BITM_TMR_LOAD_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Load Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_CURCNT                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_CURCNT_VALUE                 0            /*  Current Count */
+#define BITM_TMR_CURCNT_VALUE                (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Current Count */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_CTL                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_CTL_SYNCBYP                 15            /*  Synchronization Bypass */
+#define BITP_TMR_CTL_RSTEN                   14            /*  Counter and Prescale Reset Enable */
+#define BITP_TMR_CTL_EVTEN                   13            /*  Event Select */
+#define BITP_TMR_CTL_RLD                      7            /*  Reload Control */
+#define BITP_TMR_CTL_CLK                      5            /*  Clock Select */
+#define BITP_TMR_CTL_EN                       4            /*  Timer Enable */
+#define BITP_TMR_CTL_MODE                     3            /*  Timer Mode */
+#define BITP_TMR_CTL_UP                       2            /*  Count up */
+#define BITP_TMR_CTL_PRE                      0            /*  Prescaler */
+#define BITM_TMR_CTL_SYNCBYP                 (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Synchronization Bypass */
+#define BITM_TMR_CTL_RSTEN                   (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Counter and Prescale Reset Enable */
+#define BITM_TMR_CTL_EVTEN                   (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Event Select */
+#define BITM_TMR_CTL_RLD                     (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Reload Control */
+#define BITM_TMR_CTL_CLK                     (_ADI_MSK_3(0x00000060,0x00000060U, uint16_t  ))    /*  Clock Select */
+#define BITM_TMR_CTL_EN                      (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Timer Enable */
+#define BITM_TMR_CTL_MODE                    (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Timer Mode */
+#define BITM_TMR_CTL_UP                      (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Count up */
+#define BITM_TMR_CTL_PRE                     (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t  ))    /*  Prescaler */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_CLRINT                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_CLRINT_EVTCAPT               1            /*  Clear Captured Event Interrupt */
+#define BITP_TMR_CLRINT_TIMEOUT               0            /*  Clear Timeout Interrupt */
+#define BITM_TMR_CLRINT_EVTCAPT              (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Clear Captured Event Interrupt */
+#define BITM_TMR_CLRINT_TIMEOUT              (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Clear Timeout Interrupt */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_CAPTURE                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_CAPTURE_VALUE                0            /*  16-bit Captured Value */
+#define BITM_TMR_CAPTURE_VALUE               (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  16-bit Captured Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_ALOAD                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_ALOAD_VALUE                  0            /*  Load Value, Asynchronous */
+#define BITM_TMR_ALOAD_VALUE                 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Load Value, Asynchronous */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_ACURCNT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_ACURCNT_VALUE                0            /*  Counter Value */
+#define BITM_TMR_ACURCNT_VALUE               (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Counter Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_STAT                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_STAT_CNTRST                  8            /*  Counter Reset Occurring */
+#define BITP_TMR_STAT_PDOK                    7            /*  Clear Interrupt Register Synchronization */
+#define BITP_TMR_STAT_BUSY                    6            /*  Timer Busy */
+#define BITP_TMR_STAT_CAPTURE                 1            /*  Capture Event Pending */
+#define BITP_TMR_STAT_TIMEOUT                 0            /*  Timeout Event Occurred */
+#define BITM_TMR_STAT_CNTRST                 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Counter Reset Occurring */
+#define BITM_TMR_STAT_PDOK                   (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Clear Interrupt Register Synchronization */
+#define BITM_TMR_STAT_BUSY                   (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Timer Busy */
+#define BITM_TMR_STAT_CAPTURE                (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Capture Event Pending */
+#define BITM_TMR_STAT_TIMEOUT                (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Timeout Event Occurred */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_PWMCTL                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_PWMCTL_IDLESTATE             1            /*  PWM Idle State */
+#define BITP_TMR_PWMCTL_MATCH                 0            /*  PWM Match Enabled */
+#define BITM_TMR_PWMCTL_IDLESTATE            (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  PWM Idle State */
+#define BITM_TMR_PWMCTL_MATCH                (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  PWM Match Enabled */
+#define ENUM_TMR_PWMCTL_IDLE_LOW             (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  IDLESTATE: PWM idles low */
+#define ENUM_TMR_PWMCTL_IDLE_HIGH            (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  IDLESTATE: PWM idles high */
+#define ENUM_TMR_PWMCTL_PWM_TOGGLE           (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  MATCH: PWM in toggle mode */
+#define ENUM_TMR_PWMCTL_PWM_MATCH            (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  MATCH: PWM in match mode */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_PWMMATCH                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_PWMMATCH_VALUE               0            /*  PWM Match Value */
+#define BITM_TMR_PWMMATCH_VALUE              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  PWM Match Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_EVENTSELECT                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_EVENTSELECT_EVTRANGE         0            /*  Event Select Range */
+#define BITM_TMR_EVENTSELECT_EVTRANGE        (_ADI_MSK_3(0x0000003F,0x0000003FU, uint16_t  ))    /*  Event Select Range */
+
+
+/* ============================================================================================================================
+        Timer_RGB with 3 PWM outputs
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        TMR_RGB
+   ============================================================================================================================ */
+#define REG_TMR_RGB_LOAD                     0x40000C00            /*  TMR_RGB 16-bit load value */
+#define REG_TMR_RGB_CURCNT                   0x40000C04            /*  TMR_RGB 16-bit timer value */
+#define REG_TMR_RGB_CTL                      0x40000C08            /*  TMR_RGB Control */
+#define REG_TMR_RGB_CLRINT                   0x40000C0C            /*  TMR_RGB Clear interrupt */
+#define REG_TMR_RGB_CAPTURE                  0x40000C10            /*  TMR_RGB Capture */
+#define REG_TMR_RGB_ALOAD                    0x40000C14            /*  TMR_RGB 16-bit load value, asynchronous */
+#define REG_TMR_RGB_ACURCNT                  0x40000C18            /*  TMR_RGB 16-bit timer value, asynchronous */
+#define REG_TMR_RGB_STAT                     0x40000C1C            /*  TMR_RGB Status */
+#define REG_TMR_RGB_PWM0CTL                  0x40000C20            /*  TMR_RGB PWM0 Control Register */
+#define REG_TMR_RGB_PWM0MATCH                0x40000C24            /*  TMR_RGB PWM0 Match Value */
+#define REG_TMR_RGB_EVENTSELECT              0x40000C28            /*  TMR_RGB Timer Event selection Register */
+#define REG_TMR_RGB_PWM1CTL                  0x40000C2C            /*  TMR_RGB PWM1 Control Register */
+#define REG_TMR_RGB_PWM1MATCH                0x40000C30            /*  TMR_RGB PWM1 Match Value */
+#define REG_TMR_RGB_PWM2CTL                  0x40000C34            /*  TMR_RGB PWM2 Control Register */
+#define REG_TMR_RGB_PWM2MATCH                0x40000C38            /*  TMR_RGB PWM2 Match Value */
+
+/* ============================================================================================================================
+        TMR_RGB Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_RGB_LOAD                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_RGB_LOAD_VALUE               0            /*  Load value */
+#define BITM_TMR_RGB_LOAD_VALUE              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Load value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_RGB_CURCNT                       Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_RGB_CURCNT_VALUE             0            /*  Current count */
+#define BITM_TMR_RGB_CURCNT_VALUE            (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Current count */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_RGB_CTL                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_RGB_CTL_SYNCBYP             15            /*  Synchronization bypass */
+#define BITP_TMR_RGB_CTL_RSTEN               14            /*  Counter and prescale reset enable */
+#define BITP_TMR_RGB_CTL_EVTEN               13            /*  Event select */
+#define BITP_TMR_RGB_CTL_RLD                  7            /*  Reload control */
+#define BITP_TMR_RGB_CTL_CLK                  5            /*  Clock select */
+#define BITP_TMR_RGB_CTL_EN                   4            /*  Timer enable */
+#define BITP_TMR_RGB_CTL_MODE                 3            /*  Timer mode */
+#define BITP_TMR_RGB_CTL_UP                   2            /*  Count up */
+#define BITP_TMR_RGB_CTL_PRE                  0            /*  Prescaler */
+#define BITM_TMR_RGB_CTL_SYNCBYP             (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Synchronization bypass */
+#define BITM_TMR_RGB_CTL_RSTEN               (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Counter and prescale reset enable */
+#define BITM_TMR_RGB_CTL_EVTEN               (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Event select */
+#define BITM_TMR_RGB_CTL_RLD                 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Reload control */
+#define BITM_TMR_RGB_CTL_CLK                 (_ADI_MSK_3(0x00000060,0x00000060U, uint16_t  ))    /*  Clock select */
+#define BITM_TMR_RGB_CTL_EN                  (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Timer enable */
+#define BITM_TMR_RGB_CTL_MODE                (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Timer mode */
+#define BITM_TMR_RGB_CTL_UP                  (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Count up */
+#define BITM_TMR_RGB_CTL_PRE                 (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t  ))    /*  Prescaler */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_RGB_CLRINT                       Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_RGB_CLRINT_EVTCAPT           1            /*  Clear captured event interrupt */
+#define BITP_TMR_RGB_CLRINT_TIMEOUT           0            /*  Clear timeout interrupt */
+#define BITM_TMR_RGB_CLRINT_EVTCAPT          (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Clear captured event interrupt */
+#define BITM_TMR_RGB_CLRINT_TIMEOUT          (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Clear timeout interrupt */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_RGB_CAPTURE                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_RGB_CAPTURE_VALUE            0            /*  16-bit captured value */
+#define BITM_TMR_RGB_CAPTURE_VALUE           (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  16-bit captured value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_RGB_ALOAD                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_RGB_ALOAD_VALUE              0            /*  Load value, asynchronous */
+#define BITM_TMR_RGB_ALOAD_VALUE             (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Load value, asynchronous */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_RGB_ACURCNT                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_RGB_ACURCNT_VALUE            0            /*  Counter value */
+#define BITM_TMR_RGB_ACURCNT_VALUE           (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Counter value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_RGB_STAT                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_RGB_STAT_CNTRST              8            /*  Counter reset occurring */
+#define BITP_TMR_RGB_STAT_PDOK                7            /*  Clear Interrupt Register synchronization */
+#define BITP_TMR_RGB_STAT_BUSY                6            /*  Timer Busy */
+#define BITP_TMR_RGB_STAT_CAPTURE             1            /*  Capture event pending */
+#define BITP_TMR_RGB_STAT_TIMEOUT             0            /*  Timeout event occurred */
+#define BITM_TMR_RGB_STAT_CNTRST             (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Counter reset occurring */
+#define BITM_TMR_RGB_STAT_PDOK               (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Clear Interrupt Register synchronization */
+#define BITM_TMR_RGB_STAT_BUSY               (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Timer Busy */
+#define BITM_TMR_RGB_STAT_CAPTURE            (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Capture event pending */
+#define BITM_TMR_RGB_STAT_TIMEOUT            (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Timeout event occurred */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_RGB_PWM0CTL                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_RGB_PWM0CTL_IDLESTATE        1            /*  PWM Idle State */
+#define BITP_TMR_RGB_PWM0CTL_MATCH            0            /*  PWM Match enabled */
+#define BITM_TMR_RGB_PWM0CTL_IDLESTATE       (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  PWM Idle State */
+#define BITM_TMR_RGB_PWM0CTL_MATCH           (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  PWM Match enabled */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_RGB_PWM0MATCH                    Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_RGB_PWM0MATCH_VALUE          0            /*  PWM Match Value */
+#define BITM_TMR_RGB_PWM0MATCH_VALUE         (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  PWM Match Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_RGB_EVENTSELECT                  Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_RGB_EVENTSELECT_EVTRANGE     0            /*  Event select range */
+#define BITM_TMR_RGB_EVENTSELECT_EVTRANGE    (_ADI_MSK_3(0x0000003F,0x0000003FU, uint16_t  ))    /*  Event select range */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_RGB_PWM1CTL                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_RGB_PWM1CTL_IDLESTATE        1            /*  PWM Idle State */
+#define BITP_TMR_RGB_PWM1CTL_MATCH            0            /*  PWM Match enabled */
+#define BITM_TMR_RGB_PWM1CTL_IDLESTATE       (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  PWM Idle State */
+#define BITM_TMR_RGB_PWM1CTL_MATCH           (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  PWM Match enabled */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_RGB_PWM1MATCH                    Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_RGB_PWM1MATCH_VALUE          0            /*  PWM Match Value */
+#define BITM_TMR_RGB_PWM1MATCH_VALUE         (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  PWM Match Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_RGB_PWM2CTL                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_RGB_PWM2CTL_IDLESTATE        1            /*  PWM Idle State */
+#define BITP_TMR_RGB_PWM2CTL_MATCH            0            /*  PWM Match enabled */
+#define BITM_TMR_RGB_PWM2CTL_IDLESTATE       (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  PWM Idle State */
+#define BITM_TMR_RGB_PWM2CTL_MATCH           (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  PWM Match enabled */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          TMR_RGB_PWM2MATCH                    Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_TMR_RGB_PWM2MATCH_VALUE          0            /*  PWM Match Value */
+#define BITM_TMR_RGB_PWM2MATCH_VALUE         (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  PWM Match Value */
+
+
+/* ============================================================================================================================
+        Real-Time Clock
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        RTC0
+   ============================================================================================================================ */
+#define REG_RTC0_CR0                         0x40001000            /*  RTC0 RTC Control 0 */
+#define REG_RTC0_SR0                         0x40001004            /*  RTC0 RTC Status 0 */
+#define REG_RTC0_SR1                         0x40001008            /*  RTC0 RTC Status 1 */
+#define REG_RTC0_CNT0                        0x4000100C            /*  RTC0 RTC Count 0 */
+#define REG_RTC0_CNT1                        0x40001010            /*  RTC0 RTC Count 1 */
+#define REG_RTC0_ALM0                        0x40001014            /*  RTC0 RTC Alarm 0 */
+#define REG_RTC0_ALM1                        0x40001018            /*  RTC0 RTC Alarm 1 */
+#define REG_RTC0_TRM                         0x4000101C            /*  RTC0 RTC Trim */
+#define REG_RTC0_GWY                         0x40001020            /*  RTC0 RTC Gateway */
+#define REG_RTC0_CR1                         0x40001028            /*  RTC0 RTC Control 1 */
+#define REG_RTC0_SR2                         0x4000102C            /*  RTC0 RTC Status 2 */
+#define REG_RTC0_SNAP0                       0x40001030            /*  RTC0 RTC Snapshot 0 */
+#define REG_RTC0_SNAP1                       0x40001034            /*  RTC0 RTC Snapshot 1 */
+#define REG_RTC0_SNAP2                       0x40001038            /*  RTC0 RTC Snapshot 2 */
+#define REG_RTC0_MOD                         0x4000103C            /*  RTC0 RTC Modulo */
+#define REG_RTC0_CNT2                        0x40001040            /*  RTC0 RTC Count 2 */
+#define REG_RTC0_ALM2                        0x40001044            /*  RTC0 RTC Alarm 2 */
+#define REG_RTC0_SR3                         0x40001048            /*  RTC0 RTC Status 3 */
+#define REG_RTC0_CR2IC                       0x4000104C            /*  RTC0 RTC Control 2 for Configuring Input Capture Channels */
+#define REG_RTC0_CR3SS                       0x40001050            /*  RTC0 RTC Control 3 for Configuring SensorStrobe Channel */
+#define REG_RTC0_CR4SS                       0x40001054            /*  RTC0 RTC Control 4 for Configuring SensorStrobe Channel */
+#define REG_RTC0_SSMSK                       0x40001058            /*  RTC0 RTC Mask for SensorStrobe Channel */
+#define REG_RTC0_IC2                         0x40001064            /*  RTC0 RTC Input Capture Channel 2 */
+#define REG_RTC0_IC3                         0x40001068            /*  RTC0 RTC Input Capture Channel 3 */
+#define REG_RTC0_IC4                         0x4000106C            /*  RTC0 RTC Input Capture Channel 4 */
+#define REG_RTC0_SS1                         0x40001070            /*  RTC0 RTC SensorStrobe Channel 1 */
+#define REG_RTC0_SS2                         0x40001074            /*  RTC0 RTC SensorStrobe Channel 2 */
+#define REG_RTC0_SS3                         0x40001078            /*  RTC0 RTC SensorStrobe Channel 3 */
+#define REG_RTC0_SS4                         0x4000107C            /*  RTC0 RTC SensorStrobe Channel 4 */
+#define REG_RTC0_SR4                         0x40001080            /*  RTC0 RTC Status 4 */
+#define REG_RTC0_SR5                         0x40001084            /*  RTC0 RTC Status 5 */
+#define REG_RTC0_SR6                         0x40001088            /*  RTC0 RTC Status 6 */
+#define REG_RTC0_SS1TGT                      0x4000108C            /*  RTC0 RTC SensorStrobe Channel 1 Target */
+#define REG_RTC0_FRZCNT                      0x40001090            /*  RTC0 RTC Freeze Count */
+#define REG_RTC0_SS2TGT                      0x40001094            /*  RTC0 RTC SensorStrobe Channel 2 Target */
+#define REG_RTC0_SS3TGT                      0x40001098            /*  RTC0 RTC SensorStrobe Channel 3 Target */
+#define REG_RTC0_SS1LOWDUR                   0x400010A0            /*  RTC0 RTC Auto-Reload Low Duration for SensorStrobe Channel 1 */
+#define REG_RTC0_SS2LOWDUR                   0x400010A4            /*  RTC0 RTC Auto-Reload Low Duration for SensorStrobe Channel 2 */
+#define REG_RTC0_SS3LOWDUR                   0x400010A8            /*  RTC0 RTC Auto-Reload Low Duration for SensorStrobe Channel 3 */
+#define REG_RTC0_SS1HIGHDUR                  0x400010B0            /*  RTC0 RTC Auto-Reload High Duration for SensorStrobe Channel 1 */
+#define REG_RTC0_SS2HIGHDUR                  0x400010B4            /*  RTC0 RTC Auto-Reload High Duration for SensorStrobe Channel 2 */
+#define REG_RTC0_SS3HIGHDUR                  0x400010B8            /*  RTC0 RTC Auto-Reload High Duration for SensorStrobe Channel 3 */
+#define REG_RTC0_SSMSKOT                     0x400010C0            /*  RTC0 RTC Masks for SensorStrobe Channels on Time Control */
+#define REG_RTC0_CR5SSS                      0x400010C4            /*  RTC0 RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling */
+#define REG_RTC0_CR6SSS                      0x400010C8            /*  RTC0 RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge */
+#define REG_RTC0_CR7SSS                      0x400010CC            /*  RTC0 RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity */
+#define REG_RTC0_SR7                         0x400010D0            /*  RTC0 RTC Status 7 */
+#define REG_RTC0_SR8                         0x400010D4            /*  RTC0 RTC Status 8 */
+#define REG_RTC0_SR9                         0x400010D8            /*  RTC0 RTC Status 9 */
+#define REG_RTC0_GPMUX0                      0x400010E0            /*  RTC0 RTC GPIO Pin Mux Control Register 0 */
+#define REG_RTC0_GPMUX1                      0x400010E4            /*  RTC0 RTC GPIO Pin Mux Control Register 1 */
+
+/* ============================================================================================================================
+        RTC1
+   ============================================================================================================================ */
+#define REG_RTC1_CR0                         0x40001400            /*  RTC1 RTC Control 0 */
+#define REG_RTC1_SR0                         0x40001404            /*  RTC1 RTC Status 0 */
+#define REG_RTC1_SR1                         0x40001408            /*  RTC1 RTC Status 1 */
+#define REG_RTC1_CNT0                        0x4000140C            /*  RTC1 RTC Count 0 */
+#define REG_RTC1_CNT1                        0x40001410            /*  RTC1 RTC Count 1 */
+#define REG_RTC1_ALM0                        0x40001414            /*  RTC1 RTC Alarm 0 */
+#define REG_RTC1_ALM1                        0x40001418            /*  RTC1 RTC Alarm 1 */
+#define REG_RTC1_TRM                         0x4000141C            /*  RTC1 RTC Trim */
+#define REG_RTC1_GWY                         0x40001420            /*  RTC1 RTC Gateway */
+#define REG_RTC1_CR1                         0x40001428            /*  RTC1 RTC Control 1 */
+#define REG_RTC1_SR2                         0x4000142C            /*  RTC1 RTC Status 2 */
+#define REG_RTC1_SNAP0                       0x40001430            /*  RTC1 RTC Snapshot 0 */
+#define REG_RTC1_SNAP1                       0x40001434            /*  RTC1 RTC Snapshot 1 */
+#define REG_RTC1_SNAP2                       0x40001438            /*  RTC1 RTC Snapshot 2 */
+#define REG_RTC1_MOD                         0x4000143C            /*  RTC1 RTC Modulo */
+#define REG_RTC1_CNT2                        0x40001440            /*  RTC1 RTC Count 2 */
+#define REG_RTC1_ALM2                        0x40001444            /*  RTC1 RTC Alarm 2 */
+#define REG_RTC1_SR3                         0x40001448            /*  RTC1 RTC Status 3 */
+#define REG_RTC1_CR2IC                       0x4000144C            /*  RTC1 RTC Control 2 for Configuring Input Capture Channels */
+#define REG_RTC1_CR3SS                       0x40001450            /*  RTC1 RTC Control 3 for Configuring SensorStrobe Channel */
+#define REG_RTC1_CR4SS                       0x40001454            /*  RTC1 RTC Control 4 for Configuring SensorStrobe Channel */
+#define REG_RTC1_SSMSK                       0x40001458            /*  RTC1 RTC Mask for SensorStrobe Channel */
+#define REG_RTC1_IC2                         0x40001464            /*  RTC1 RTC Input Capture Channel 2 */
+#define REG_RTC1_IC3                         0x40001468            /*  RTC1 RTC Input Capture Channel 3 */
+#define REG_RTC1_IC4                         0x4000146C            /*  RTC1 RTC Input Capture Channel 4 */
+#define REG_RTC1_SS1                         0x40001470            /*  RTC1 RTC SensorStrobe Channel 1 */
+#define REG_RTC1_SS2                         0x40001474            /*  RTC1 RTC SensorStrobe Channel 2 */
+#define REG_RTC1_SS3                         0x40001478            /*  RTC1 RTC SensorStrobe Channel 3 */
+#define REG_RTC1_SS4                         0x4000147C            /*  RTC1 RTC SensorStrobe Channel 4 */
+#define REG_RTC1_SR4                         0x40001480            /*  RTC1 RTC Status 4 */
+#define REG_RTC1_SR5                         0x40001484            /*  RTC1 RTC Status 5 */
+#define REG_RTC1_SR6                         0x40001488            /*  RTC1 RTC Status 6 */
+#define REG_RTC1_SS1TGT                      0x4000148C            /*  RTC1 RTC SensorStrobe Channel 1 Target */
+#define REG_RTC1_FRZCNT                      0x40001490            /*  RTC1 RTC Freeze Count */
+#define REG_RTC1_SS2TGT                      0x40001494            /*  RTC1 RTC SensorStrobe Channel 2 Target */
+#define REG_RTC1_SS3TGT                      0x40001498            /*  RTC1 RTC SensorStrobe Channel 3 Target */
+#define REG_RTC1_SS1LOWDUR                   0x400014A0            /*  RTC1 RTC Auto-Reload Low Duration for SensorStrobe Channel 1 */
+#define REG_RTC1_SS2LOWDUR                   0x400014A4            /*  RTC1 RTC Auto-Reload Low Duration for SensorStrobe Channel 2 */
+#define REG_RTC1_SS3LOWDUR                   0x400014A8            /*  RTC1 RTC Auto-Reload Low Duration for SensorStrobe Channel 3 */
+#define REG_RTC1_SS1HIGHDUR                  0x400014B0            /*  RTC1 RTC Auto-Reload High Duration for SensorStrobe Channel 1 */
+#define REG_RTC1_SS2HIGHDUR                  0x400014B4            /*  RTC1 RTC Auto-Reload High Duration for SensorStrobe Channel 2 */
+#define REG_RTC1_SS3HIGHDUR                  0x400014B8            /*  RTC1 RTC Auto-Reload High Duration for SensorStrobe Channel 3 */
+#define REG_RTC1_SSMSKOT                     0x400014C0            /*  RTC1 RTC Masks for SensorStrobe Channels on Time Control */
+#define REG_RTC1_CR5SSS                      0x400014C4            /*  RTC1 RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling */
+#define REG_RTC1_CR6SSS                      0x400014C8            /*  RTC1 RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge */
+#define REG_RTC1_CR7SSS                      0x400014CC            /*  RTC1 RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity */
+#define REG_RTC1_SR7                         0x400014D0            /*  RTC1 RTC Status 7 */
+#define REG_RTC1_SR8                         0x400014D4            /*  RTC1 RTC Status 8 */
+#define REG_RTC1_SR9                         0x400014D8            /*  RTC1 RTC Status 9 */
+#define REG_RTC1_GPMUX0                      0x400014E0            /*  RTC1 RTC GPIO Pin Mux Control Register 0 */
+#define REG_RTC1_GPMUX1                      0x400014E4            /*  RTC1 RTC GPIO Pin Mux Control Register 1 */
+
+/* ============================================================================================================================
+        RTC Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_CR0                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_CR0_WPNDINTEN               15            /*  Enable Write Pending Sourced Interrupts to the CPU */
+#define BITP_RTC_CR0_WSYNCINTEN              14            /*  Enable Write Synchronization Sourced Interrupts to the CPU */
+#define BITP_RTC_CR0_WPNDERRINTEN            13            /*  Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Register-write Pending Error Occurs */
+#define BITP_RTC_CR0_ISOINTEN                12            /*  Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power Domain is Activated and Subsequently De-activated */
+#define BITP_RTC_CR0_MOD60ALMINTEN           11            /*  Enable Periodic Modulo-60 RTC Alarm  Sourced Interrupts to the CPU */
+#define BITP_RTC_CR0_MOD60ALM                 5            /*  Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60 Boundary */
+#define BITP_RTC_CR0_MOD60ALMEN               4            /*  Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary */
+#define BITP_RTC_CR0_TRMEN                    3            /*  Enable RTC Digital Trimming */
+#define BITP_RTC_CR0_ALMINTEN                 2            /*  Enable ALMINT Sourced Alarm Interrupts to the CPU */
+#define BITP_RTC_CR0_ALMEN                    1            /*  Enable the RTC Alarm (Absolute) Operation */
+#define BITP_RTC_CR0_CNTEN                    0            /*  Global Enable for the RTC */
+#define BITM_RTC_CR0_WPNDINTEN               (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Enable Write Pending Sourced Interrupts to the CPU */
+#define BITM_RTC_CR0_WSYNCINTEN              (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Enable Write Synchronization Sourced Interrupts to the CPU */
+#define BITM_RTC_CR0_WPNDERRINTEN            (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Register-write Pending Error Occurs */
+#define BITM_RTC_CR0_ISOINTEN                (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power Domain is Activated and Subsequently De-activated */
+#define BITM_RTC_CR0_MOD60ALMINTEN           (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Enable Periodic Modulo-60 RTC Alarm  Sourced Interrupts to the CPU */
+#define BITM_RTC_CR0_MOD60ALM                (_ADI_MSK_3(0x000007E0,0x000007E0U, uint16_t  ))    /*  Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60 Boundary */
+#define BITM_RTC_CR0_MOD60ALMEN              (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary */
+#define BITM_RTC_CR0_TRMEN                   (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Enable RTC Digital Trimming */
+#define BITM_RTC_CR0_ALMINTEN                (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Enable ALMINT Sourced Alarm Interrupts to the CPU */
+#define BITM_RTC_CR0_ALMEN                   (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Enable the RTC Alarm (Absolute) Operation */
+#define BITM_RTC_CR0_CNTEN                   (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Global Enable for the RTC */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SR0                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SR0_ISOENB                  14            /*  Visibility of 32kHz Sourced Registers */
+#define BITP_RTC_SR0_WSYNCTRM                13            /*  Synchronisation Status of Posted Writes to TRM */
+#define BITP_RTC_SR0_WSYNCALM1               12            /*  Synchronisation Status of Posted Writes to ALM1 */
+#define BITP_RTC_SR0_WSYNCALM0               11            /*  Synchronisation Status of Posted Writes to ALM0 */
+#define BITP_RTC_SR0_WSYNCCNT1               10            /*  Synchronisation Status of Posted Writes to CNT1 */
+#define BITP_RTC_SR0_WSYNCCNT0                9            /*  Synchronisation Status of Posted Writes to CNT0 */
+#define BITP_RTC_SR0_WSYNCSR0                 8            /*  Synchronisation Status of Posted Writes to SR0 */
+#define BITP_RTC_SR0_WSYNCCR0                 7            /*  Synchronisation Status of Posted Writes to CR0 */
+#define BITP_RTC_SR0_WPNDINT                  6            /*  Write Pending Interrupt */
+#define BITP_RTC_SR0_WSYNCINT                 5            /*  Write Synchronisation Interrupt */
+#define BITP_RTC_SR0_WPNDERRINT               4            /*  Write Pending Error Interrupt Source */
+#define BITP_RTC_SR0_ISOINT                   3            /*  RTC Power-Domain Isolation Interrupt Source */
+#define BITP_RTC_SR0_MOD60ALMINT              2            /*  Modulo-60 RTC Alarm Interrupt Source */
+#define BITP_RTC_SR0_ALMINT                   1            /*  Alarm Interrupt Source */
+#define BITM_RTC_SR0_ISOENB                  (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Visibility of 32kHz Sourced Registers */
+#define BITM_RTC_SR0_WSYNCTRM                (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to TRM */
+#define BITM_RTC_SR0_WSYNCALM1               (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to ALM1 */
+#define BITM_RTC_SR0_WSYNCALM0               (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to ALM0 */
+#define BITM_RTC_SR0_WSYNCCNT1               (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to CNT1 */
+#define BITM_RTC_SR0_WSYNCCNT0               (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to CNT0 */
+#define BITM_RTC_SR0_WSYNCSR0                (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to SR0 */
+#define BITM_RTC_SR0_WSYNCCR0                (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to CR0 */
+#define BITM_RTC_SR0_WPNDINT                 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Write Pending Interrupt */
+#define BITM_RTC_SR0_WSYNCINT                (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Write Synchronisation Interrupt */
+#define BITM_RTC_SR0_WPNDERRINT              (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Write Pending Error Interrupt Source */
+#define BITM_RTC_SR0_ISOINT                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  RTC Power-Domain Isolation Interrupt Source */
+#define BITM_RTC_SR0_MOD60ALMINT             (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Modulo-60 RTC Alarm Interrupt Source */
+#define BITM_RTC_SR0_ALMINT                  (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Alarm Interrupt Source */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SR1                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SR1_WPNDTRM                 13            /*  Pending Status of Posted Writes to TRM */
+#define BITP_RTC_SR1_WPNDALM1                12            /*  Pending Status of Posted Writes to ALM1 */
+#define BITP_RTC_SR1_WPNDALM0                11            /*  Pending Status of Posted Writes to ALM0 */
+#define BITP_RTC_SR1_WPNDCNT1                10            /*  Pending Status of Posted Writes to CNT1 */
+#define BITP_RTC_SR1_WPNDCNT0                 9            /*  Pending Status of Posted Writes to CNT0 */
+#define BITP_RTC_SR1_WPNDSR0                  8            /*  Pending Status of Posted Clearances of Interrupt Sources in SR0 */
+#define BITP_RTC_SR1_WPNDCR0                  7            /*  Pending Status of Posted Writes to CR0 */
+#define BITM_RTC_SR1_WPNDTRM                 (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Pending Status of Posted Writes to TRM */
+#define BITM_RTC_SR1_WPNDALM1                (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Pending Status of Posted Writes to ALM1 */
+#define BITM_RTC_SR1_WPNDALM0                (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Pending Status of Posted Writes to ALM0 */
+#define BITM_RTC_SR1_WPNDCNT1                (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Pending Status of Posted Writes to CNT1 */
+#define BITM_RTC_SR1_WPNDCNT0                (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Pending Status of Posted Writes to CNT0 */
+#define BITM_RTC_SR1_WPNDSR0                 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Pending Status of Posted Clearances of Interrupt Sources in SR0 */
+#define BITM_RTC_SR1_WPNDCR0                 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Pending Status of Posted Writes to CR0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_CNT0                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_CNT0_VALUE                   0            /*  Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */
+#define BITM_RTC_CNT0_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_CNT1                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_CNT1_VALUE                   0            /*  Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */
+#define BITM_RTC_CNT1_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_ALM0                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_ALM0_VALUE                   0            /*  Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time */
+#define BITM_RTC_ALM0_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_ALM1                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_ALM1_VALUE                   0            /*  Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time */
+#define BITM_RTC_ALM1_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_TRM                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_TRM_IVL2EXPMIN               6            /*  Minimum Power-of-two Interval of Prescaled RTC Time Units Which TRM:TRMIVL TRMIVL Can Select */
+#define BITP_RTC_TRM_IVL                      4            /*  Trim Interval in Prescaled RTC Time Units */
+#define BITP_RTC_TRM_ADD                      3            /*  Trim Polarity */
+#define BITP_RTC_TRM_VALUE                    0            /*  Trim Value in Prescaled RTC Time Units to Be Added or Subtracted from the RTC Count at the End of a Periodic Interval Selected by TRM:TRMIVL */
+#define BITM_RTC_TRM_IVL2EXPMIN              (_ADI_MSK_3(0x000003C0,0x000003C0U, uint16_t  ))    /*  Minimum Power-of-two Interval of Prescaled RTC Time Units Which TRM:TRMIVL TRMIVL Can Select */
+#define BITM_RTC_TRM_IVL                     (_ADI_MSK_3(0x00000030,0x00000030U, uint16_t  ))    /*  Trim Interval in Prescaled RTC Time Units */
+#define BITM_RTC_TRM_ADD                     (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Trim Polarity */
+#define BITM_RTC_TRM_VALUE                   (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t  ))    /*  Trim Value in Prescaled RTC Time Units to Be Added or Subtracted from the RTC Count at the End of a Periodic Interval Selected by TRM:TRMIVL */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_GWY                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_GWY_SWKEY                    0            /*  Software-keyed Command Issued by the CPU */
+#define BITM_RTC_GWY_SWKEY                   (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Software-keyed Command Issued by the CPU */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_CR1                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_CR1_PRESCALE2EXP             5            /*  Prescale Power of 2 Division Factor for the RTC Base Clock */
+#define BITP_RTC_CR1_CNTMOD60ROLLINTEN        4            /*  Enable for the RTC Modulo-60 Count Roll-Over Interrupt Source, in SR2:RTCCNTMOD60ROLLINT    */
+#define BITP_RTC_CR1_CNTROLLINTEN             3            /*  Enable for the RTC Count Roll-Over Interrupt Source, in SR2:RTCCNTROLLINT */
+#define BITP_RTC_CR1_TRMINTEN                 2            /*  Enable for the RTC Trim Interrupt Source, in SR2:RTCTRMINT */
+#define BITP_RTC_CR1_PSINTEN                  1            /*  Enable for the Prescaled, Modulo-1 Interrupt Source, in SR2:RTCPSINT */
+#define BITP_RTC_CR1_CNTINTEN                 0            /*  Enable for the RTC Count Interrupt Source */
+#define BITM_RTC_CR1_PRESCALE2EXP            (_ADI_MSK_3(0x000001E0,0x000001E0U, uint16_t  ))    /*  Prescale Power of 2 Division Factor for the RTC Base Clock */
+#define BITM_RTC_CR1_CNTMOD60ROLLINTEN       (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Enable for the RTC Modulo-60 Count Roll-Over Interrupt Source, in SR2:RTCCNTMOD60ROLLINT    */
+#define BITM_RTC_CR1_CNTROLLINTEN            (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Enable for the RTC Count Roll-Over Interrupt Source, in SR2:RTCCNTROLLINT */
+#define BITM_RTC_CR1_TRMINTEN                (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Enable for the RTC Trim Interrupt Source, in SR2:RTCTRMINT */
+#define BITM_RTC_CR1_PSINTEN                 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Enable for the Prescaled, Modulo-1 Interrupt Source, in SR2:RTCPSINT */
+#define BITM_RTC_CR1_CNTINTEN                (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Enable for the RTC Count Interrupt Source */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SR2                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SR2_WSYNCALM2MIR            15            /*  Synchronization Status of Posted Writes to ALM2 */
+#define BITP_RTC_SR2_WSYNCCR1MIR             14            /*  Synchronization Status of Posted Writes to CR1 */
+#define BITP_RTC_SR2_WPNDALM2MIR             13            /*  Pending Status of Posted Writes to ALM2 */
+#define BITP_RTC_SR2_WPNDCR1MIR              12            /*  Pending Status of Posted Writes to CR1 */
+#define BITP_RTC_SR2_TRMBDYMIR                7            /*  Mirror of MOD:RTCTRMBDY */
+#define BITP_RTC_SR2_CNTMOD60ROLL             6            /*  RTC Count Modulo-60 Roll-Over */
+#define BITP_RTC_SR2_CNTROLL                  5            /*  RTC Count Roll-Over */
+#define BITP_RTC_SR2_CNTMOD60ROLLINT          4            /*  RTC Modulo-60 Count Roll-Over Interrupt Source */
+#define BITP_RTC_SR2_CNTROLLINT               3            /*  RTC Count Roll-Over Interrupt Source */
+#define BITP_RTC_SR2_TRMINT                   2            /*  RTC Trim Interrupt Source */
+#define BITP_RTC_SR2_PSINT                    1            /*  RTC Prescaled, Modulo-1 Boundary Interrupt Source */
+#define BITP_RTC_SR2_CNTINT                   0            /*  RTC Count Interrupt Source */
+#define BITM_RTC_SR2_WSYNCALM2MIR            (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Synchronization Status of Posted Writes to ALM2 */
+#define BITM_RTC_SR2_WSYNCCR1MIR             (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Synchronization Status of Posted Writes to CR1 */
+#define BITM_RTC_SR2_WPNDALM2MIR             (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Pending Status of Posted Writes to ALM2 */
+#define BITM_RTC_SR2_WPNDCR1MIR              (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Pending Status of Posted Writes to CR1 */
+#define BITM_RTC_SR2_TRMBDYMIR               (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Mirror of MOD:RTCTRMBDY */
+#define BITM_RTC_SR2_CNTMOD60ROLL            (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  RTC Count Modulo-60 Roll-Over */
+#define BITM_RTC_SR2_CNTROLL                 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  RTC Count Roll-Over */
+#define BITM_RTC_SR2_CNTMOD60ROLLINT         (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  RTC Modulo-60 Count Roll-Over Interrupt Source */
+#define BITM_RTC_SR2_CNTROLLINT              (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  RTC Count Roll-Over Interrupt Source */
+#define BITM_RTC_SR2_TRMINT                  (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  RTC Trim Interrupt Source */
+#define BITM_RTC_SR2_PSINT                   (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  RTC Prescaled, Modulo-1 Boundary Interrupt Source */
+#define BITM_RTC_SR2_CNTINT                  (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  RTC Count Interrupt Source */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SNAP0                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SNAP0_VALUE                  0            /*  Constituent Part of the 47-bit Input Capture Channel 0, Containing a Sticky Snapshot of  CNT0 */
+#define BITM_RTC_SNAP0_VALUE                 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Constituent Part of the 47-bit Input Capture Channel 0, Containing a Sticky Snapshot of  CNT0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SNAP1                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SNAP1_VALUE                  0            /*  Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of  CNT1 */
+#define BITM_RTC_SNAP1_VALUE                 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of  CNT1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SNAP2                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SNAP2_VALUE                  0            /*  Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT2 */
+#define BITM_RTC_SNAP2_VALUE                 (_ADI_MSK_3(0x00007FFF,0x00007FFFU, uint16_t  ))    /*  Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_MOD                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_MOD_CNT0_4TOZERO            11            /*  Mirror of CNT0[4:0] */
+#define BITP_RTC_MOD_TRMBDY                  10            /*  Trim Boundary Indicator */
+#define BITP_RTC_MOD_INCR                     6            /*  Most Recent Increment Value Added to the RTC Count in CNT1 and CNT0 */
+#define BITP_RTC_MOD_CNTMOD60                 0            /*  Modulo-60 Value of the RTC Count: CNT1 and CNT0 */
+#define BITM_RTC_MOD_CNT0_4TOZERO            (_ADI_MSK_3(0x0000F800,0x0000F800U, uint16_t  ))    /*  Mirror of CNT0[4:0] */
+#define BITM_RTC_MOD_TRMBDY                  (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Trim Boundary Indicator */
+#define BITM_RTC_MOD_INCR                    (_ADI_MSK_3(0x000003C0,0x000003C0U, uint16_t  ))    /*  Most Recent Increment Value Added to the RTC Count in CNT1 and CNT0 */
+#define BITM_RTC_MOD_CNTMOD60                (_ADI_MSK_3(0x0000003F,0x0000003FU, uint16_t  ))    /*  Modulo-60 Value of the RTC Count: CNT1 and CNT0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_CNT2                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_CNT2_VALUE                   0            /*  Fractional Bits of the RTC Real-Time Count */
+#define BITM_RTC_CNT2_VALUE                  (_ADI_MSK_3(0x00007FFF,0x00007FFFU, uint16_t  ))    /*  Fractional Bits of the RTC Real-Time Count */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_ALM2                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_ALM2_VALUE                   0            /*  Fractional Bits of the Alarm Target Time */
+#define BITM_RTC_ALM2_VALUE                  (_ADI_MSK_3(0x00007FFF,0x00007FFFU, uint16_t  ))    /*  Fractional Bits of the Alarm Target Time */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SR3                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SR3_ALMINTMIR               13            /*  Read-only Mirror of the SR0:ALMINT Interrupt Source */
+#define BITP_RTC_SR3_SS4IRQ                  12            /*  Sticky Interrupt Source for the SensorStrobe Channel 4 */
+#define BITP_RTC_SR3_SS3IRQ                  11            /*  Sticky Interrupt Source for the SensorStrobe Channel 3 */
+#define BITP_RTC_SR3_SS2IRQ                  10            /*  Sticky Interrupt Source for the SensorStrobe Channel 2 */
+#define BITP_RTC_SR3_SS1IRQ                   9            /*  Sticky Interrupt Source for SensorStrobe Channel 1 */
+#define BITP_RTC_SR3_SS4FEIRQ                 8            /*  Sticky Interrupt Source for the SensorStrobe Channel 4 Falling Edge */
+#define BITP_RTC_SR3_SS3FEIRQ                 7            /*  Sticky Interrupt Source for the SensorStrobe Channel 3 Falling Edge */
+#define BITP_RTC_SR3_SS2FEIRQ                 6            /*  Sticky Interrupt Source for the SensorStrobe Channel 2 Falling Edge */
+#define BITP_RTC_SR3_SS1FEIRQ                 5            /*  Sticky Interrupt Source for the SensorStrobe Channel 1 Falling Edge */
+#define BITP_RTC_SR3_IC4IRQ                   4            /*  Sticky Interrupt Source for the RTC Input Capture Channel 4 */
+#define BITP_RTC_SR3_IC3IRQ                   3            /*  Sticky Interrupt Source for the RTC Input Capture Channel 3 */
+#define BITP_RTC_SR3_IC2IRQ                   2            /*  Sticky Interrupt Source for the RTC Input Capture Channel 2 */
+#define BITP_RTC_SR3_IC0IRQ                   0            /*  Sticky Interrupt Source for the RTC Input Capture Channel 0 */
+#define BITM_RTC_SR3_ALMINTMIR               (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Read-only Mirror of the SR0:ALMINT Interrupt Source */
+#define BITM_RTC_SR3_SS4IRQ                  (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Sticky Interrupt Source for the SensorStrobe Channel 4 */
+#define BITM_RTC_SR3_SS3IRQ                  (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Sticky Interrupt Source for the SensorStrobe Channel 3 */
+#define BITM_RTC_SR3_SS2IRQ                  (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Sticky Interrupt Source for the SensorStrobe Channel 2 */
+#define BITM_RTC_SR3_SS1IRQ                  (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Sticky Interrupt Source for SensorStrobe Channel 1 */
+#define BITM_RTC_SR3_SS4FEIRQ                (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Sticky Interrupt Source for the SensorStrobe Channel 4 Falling Edge */
+#define BITM_RTC_SR3_SS3FEIRQ                (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Sticky Interrupt Source for the SensorStrobe Channel 3 Falling Edge */
+#define BITM_RTC_SR3_SS2FEIRQ                (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Sticky Interrupt Source for the SensorStrobe Channel 2 Falling Edge */
+#define BITM_RTC_SR3_SS1FEIRQ                (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Sticky Interrupt Source for the SensorStrobe Channel 1 Falling Edge */
+#define BITM_RTC_SR3_IC4IRQ                  (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Sticky Interrupt Source for the RTC Input Capture Channel 4 */
+#define BITM_RTC_SR3_IC3IRQ                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Sticky Interrupt Source for the RTC Input Capture Channel 3 */
+#define BITM_RTC_SR3_IC2IRQ                  (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Sticky Interrupt Source for the RTC Input Capture Channel 2 */
+#define BITM_RTC_SR3_IC0IRQ                  (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Sticky Interrupt Source for the RTC Input Capture Channel 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_CR2IC                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_CR2IC_ICOWUSEN              15            /*  Enable Overwrite of Unread Snapshots for All Input Capture Channels */
+#define BITP_RTC_CR2IC_IC4IRQEN              14            /*  Interrupt Enable for the RTC Input Capture Channel 4 */
+#define BITP_RTC_CR2IC_IC3IRQEN              13            /*  Interrupt Enable for the RTC Input Capture Channel 3 */
+#define BITP_RTC_CR2IC_IC2IRQEN              12            /*  Interrupt Enable for the RTC Input Capture Channel 2 */
+#define BITP_RTC_CR2IC_IC0IRQEN              10            /*  Interrupt Enable for the RTC Input Capture Channel 0 */
+#define BITP_RTC_CR2IC_IC4LH                  9            /*  Polarity of the Active-going Capture Edge for the Input Capture Channel 4 */
+#define BITP_RTC_CR2IC_IC3LH                  8            /*  Polarity of the Active-going Capture Edge for the Input Capture Channel 3 */
+#define BITP_RTC_CR2IC_IC2LH                  7            /*  Polarity of the Active-going Capture Edge for the Input Capture Channel 2 */
+#define BITP_RTC_CR2IC_IC0LH                  5            /*  Polarity of the Active-Going Capture Edge for the RTC Input Capture Channel 0 */
+#define BITP_RTC_CR2IC_IC4EN                  4            /*  Enable for the RTC Input Capture Channel 4 */
+#define BITP_RTC_CR2IC_IC3EN                  3            /*  Enable for the RTC Input Capture Channel 3 */
+#define BITP_RTC_CR2IC_IC2EN                  2            /*  Enable for the RTC Input Capture Channel 2 */
+#define BITP_RTC_CR2IC_IC0EN                  0            /*  Enable for the RTC Input Capture Channel 0 */
+#define BITM_RTC_CR2IC_ICOWUSEN              (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Enable Overwrite of Unread Snapshots for All Input Capture Channels */
+#define BITM_RTC_CR2IC_IC4IRQEN              (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Interrupt Enable for the RTC Input Capture Channel 4 */
+#define BITM_RTC_CR2IC_IC3IRQEN              (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Interrupt Enable for the RTC Input Capture Channel 3 */
+#define BITM_RTC_CR2IC_IC2IRQEN              (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Interrupt Enable for the RTC Input Capture Channel 2 */
+#define BITM_RTC_CR2IC_IC0IRQEN              (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Interrupt Enable for the RTC Input Capture Channel 0 */
+#define BITM_RTC_CR2IC_IC4LH                 (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Polarity of the Active-going Capture Edge for the Input Capture Channel 4 */
+#define BITM_RTC_CR2IC_IC3LH                 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Polarity of the Active-going Capture Edge for the Input Capture Channel 3 */
+#define BITM_RTC_CR2IC_IC2LH                 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Polarity of the Active-going Capture Edge for the Input Capture Channel 2 */
+#define BITM_RTC_CR2IC_IC0LH                 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Polarity of the Active-Going Capture Edge for the RTC Input Capture Channel 0 */
+#define BITM_RTC_CR2IC_IC4EN                 (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Enable for the RTC Input Capture Channel 4 */
+#define BITM_RTC_CR2IC_IC3EN                 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Enable for the RTC Input Capture Channel 3 */
+#define BITM_RTC_CR2IC_IC2EN                 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Enable for the RTC Input Capture Channel 2 */
+#define BITM_RTC_CR2IC_IC0EN                 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Enable for the RTC Input Capture Channel 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_CR3SS                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_CR3SS_SS4IRQEN              12            /*  Posedge EdgeInterrupt Enable for the SensorStrobe Channel 4 */
+#define BITP_RTC_CR3SS_SS3IRQEN              11            /*  Posedge EdgeInterrupt Enable for the SensorStrobe Channel 3 */
+#define BITP_RTC_CR3SS_SS2IRQEN              10            /*  Posedge EdgeInterrupt Enable for the SensorStrobe Channel 2 */
+#define BITP_RTC_CR3SS_SS1IRQEN               9            /*  Interrupt Enable for SensorStrobe Channel 1 */
+#define BITP_RTC_CR3SS_SS4FEIRQEN             8            /*  Falling Edge Interrupt Enable for the SensorStrobe Channel 4 */
+#define BITP_RTC_CR3SS_SS3FEIRQEN             7            /*  Falling Edge Interrupt Enable for the SensorStrobe Channel 3 */
+#define BITP_RTC_CR3SS_SS2FEIRQEN             6            /*  Falling Edge Interrupt Enable for the SensorStrobe Channel 2 */
+#define BITP_RTC_CR3SS_SS1FEIRQEN             5            /*  Falling Edge Interrupt Enable for the SensorStrobe Channel 1 */
+#define BITP_RTC_CR3SS_SS4EN                  4            /*  Enable for the SensorStrobe Channel 4 */
+#define BITP_RTC_CR3SS_SS3EN                  3            /*  Enable for the SensorStrobe Channel 3 */
+#define BITP_RTC_CR3SS_SS2EN                  2            /*  Enable for the SensorStrobe Channel 2 */
+#define BITP_RTC_CR3SS_SS1EN                  1            /*  Enable for SensorStrobe Channel 1 */
+#define BITM_RTC_CR3SS_SS4IRQEN              (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Posedge EdgeInterrupt Enable for the SensorStrobe Channel 4 */
+#define BITM_RTC_CR3SS_SS3IRQEN              (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Posedge EdgeInterrupt Enable for the SensorStrobe Channel 3 */
+#define BITM_RTC_CR3SS_SS2IRQEN              (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Posedge EdgeInterrupt Enable for the SensorStrobe Channel 2 */
+#define BITM_RTC_CR3SS_SS1IRQEN              (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Interrupt Enable for SensorStrobe Channel 1 */
+#define BITM_RTC_CR3SS_SS4FEIRQEN            (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Falling Edge Interrupt Enable for the SensorStrobe Channel 4 */
+#define BITM_RTC_CR3SS_SS3FEIRQEN            (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Falling Edge Interrupt Enable for the SensorStrobe Channel 3 */
+#define BITM_RTC_CR3SS_SS2FEIRQEN            (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Falling Edge Interrupt Enable for the SensorStrobe Channel 2 */
+#define BITM_RTC_CR3SS_SS1FEIRQEN            (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Falling Edge Interrupt Enable for the SensorStrobe Channel 1 */
+#define BITM_RTC_CR3SS_SS4EN                 (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Enable for the SensorStrobe Channel 4 */
+#define BITM_RTC_CR3SS_SS3EN                 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Enable for the SensorStrobe Channel 3 */
+#define BITM_RTC_CR3SS_SS2EN                 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Enable for the SensorStrobe Channel 2 */
+#define BITM_RTC_CR3SS_SS1EN                 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Enable for SensorStrobe Channel 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_CR4SS                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_CR4SS_SS3ARLEN              11            /*  Enable for Fine Control on SensorStrobe Channel 3 Period and Duty Cycle */
+#define BITP_RTC_CR4SS_SS2ARLEN              10            /*  Enable for Fine Control on SensorStrobe Channel 2 Period and Duty Cycle */
+#define BITP_RTC_CR4SS_SS1ARLEN               9            /*  Enable for Fine Control on SensorStrobe Channel 1 Period and Duty Cycle */
+#define BITP_RTC_CR4SS_SS4POL                 8            /*  SensorStrobe Channel 4 Polarity Control */
+#define BITP_RTC_CR4SS_SS3POL                 7            /*  SensorStrobe Channel 3 Polarity Control */
+#define BITP_RTC_CR4SS_SS2POL                 6            /*  SensorStrobe Channel 2 Polarity Control */
+#define BITP_RTC_CR4SS_SS1POL                 5            /*  SensorSTrobe Channel 1 Polarity Control */
+#define BITP_RTC_CR4SS_SS4MSKEN               4            /*  Enable for Thermometer-Code Masking of the SensorStrobe Channel 4 */
+#define BITP_RTC_CR4SS_SS3MSKEN               3            /*  Enable for Thermometer-Code Masking of the SensorStrobe Channel 3 */
+#define BITP_RTC_CR4SS_SS2MSKEN               2            /*  Enable for Thermometer-Code Masking of the SensorStrobe Channel 2 */
+#define BITP_RTC_CR4SS_SS1MSKEN               1            /*  Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 */
+#define BITM_RTC_CR4SS_SS3ARLEN              (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Enable for Fine Control on SensorStrobe Channel 3 Period and Duty Cycle */
+#define BITM_RTC_CR4SS_SS2ARLEN              (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Enable for Fine Control on SensorStrobe Channel 2 Period and Duty Cycle */
+#define BITM_RTC_CR4SS_SS1ARLEN              (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Enable for Fine Control on SensorStrobe Channel 1 Period and Duty Cycle */
+#define BITM_RTC_CR4SS_SS4POL                (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  SensorStrobe Channel 4 Polarity Control */
+#define BITM_RTC_CR4SS_SS3POL                (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  SensorStrobe Channel 3 Polarity Control */
+#define BITM_RTC_CR4SS_SS2POL                (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  SensorStrobe Channel 2 Polarity Control */
+#define BITM_RTC_CR4SS_SS1POL                (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  SensorSTrobe Channel 1 Polarity Control */
+#define BITM_RTC_CR4SS_SS4MSKEN              (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Enable for Thermometer-Code Masking of the SensorStrobe Channel 4 */
+#define BITM_RTC_CR4SS_SS3MSKEN              (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Enable for Thermometer-Code Masking of the SensorStrobe Channel 3 */
+#define BITM_RTC_CR4SS_SS2MSKEN              (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Enable for Thermometer-Code Masking of the SensorStrobe Channel 2 */
+#define BITM_RTC_CR4SS_SS1MSKEN              (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 */
+#define ENUM_RTC_CR4SS_NO_MSK                (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  SS1MSKEN: Do not apply a mask to SensorStrobe Channel 1 Register */
+#define ENUM_RTC_CR4SS_THERM_MSK             (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  SS1MSKEN: Apply thermometer decoded mask */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SSMSK                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SSMSK_SS4MSK                12            /*  SensorStrobe Channel 4 Period Control */
+#define BITP_RTC_SSMSK_SS3MSK                 8            /*  SensorStrobe Channel 3 Period Control */
+#define BITP_RTC_SSMSK_SS2MSK                 4            /*  SensorStrobe Channel 2 Period Control */
+#define BITP_RTC_SSMSK_SS1MSK                 0            /*  Concatenation of Thermometer-Encoded Masks for the 16-bit SensorStrobe Channels */
+#define BITM_RTC_SSMSK_SS4MSK                (_ADI_MSK_3(0x0000F000,0x0000F000U, uint16_t  ))    /*  SensorStrobe Channel 4 Period Control */
+#define BITM_RTC_SSMSK_SS3MSK                (_ADI_MSK_3(0x00000F00,0x00000F00U, uint16_t  ))    /*  SensorStrobe Channel 3 Period Control */
+#define BITM_RTC_SSMSK_SS2MSK                (_ADI_MSK_3(0x000000F0,0x000000F0U, uint16_t  ))    /*  SensorStrobe Channel 2 Period Control */
+#define BITM_RTC_SSMSK_SS1MSK                (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t  ))    /*  Concatenation of Thermometer-Encoded Masks for the 16-bit SensorStrobe Channels */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_IC2                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_IC2_IC2                      0            /*  RTC Input Capture Channel 2 */
+#define BITM_RTC_IC2_IC2                     (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  RTC Input Capture Channel 2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_IC3                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_IC3_IC3                      0            /*  RTC Input Capture Channel 3 */
+#define BITM_RTC_IC3_IC3                     (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  RTC Input Capture Channel 3 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_IC4                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_IC4_IC4                      0            /*  RTC Input Capture Channel 4 */
+#define BITM_RTC_IC4_IC4                     (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  RTC Input Capture Channel 4 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SS1                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SS1_SS1                      0            /*  SensorStrobe Channel 1 */
+#define BITM_RTC_SS1_SS1                     (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  SensorStrobe Channel 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SS2                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SS2_SS2                      0            /*  SensorStrobe Channel 2 */
+#define BITM_RTC_SS2_SS2                     (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  SensorStrobe Channel 2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SS3                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SS3_SS3                      0            /*  SensorStrobe Channel 3 */
+#define BITM_RTC_SS3_SS3                     (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  SensorStrobe Channel 3 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SS4                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SS4_SS4                      0            /*  SensorStrobe Channel 4 */
+#define BITM_RTC_SS4_SS4                     (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  SensorStrobe Channel 4 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SR4                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SR4_WSYNCSSMSKOT            15            /*  Synchronization Status of Posted Reads Writes to Mask for SensorStrobe Channels on Time Control Register */
+#define BITP_RTC_SR4_RSYNCIC4                14            /*  Synchronization Status of Posted Reads of RTC Input Channel 4 */
+#define BITP_RTC_SR4_RSYNCIC3                13            /*  Synchronization Status of Posted Reads of RTC Input Channel 3 */
+#define BITP_RTC_SR4_RSYNCIC2                12            /*  Synchronization Status of Posted Reads of RTC Input Channel 2 */
+#define BITP_RTC_SR4_RSYNCIC0                10            /*  Synchronization Status of Posted Reads of RTC Input Channel 0 */
+#define BITP_RTC_SR4_WSYNCSS4                 9            /*  Synchronization Status of Posted Writes to SensorStrobe Channel 4 */
+#define BITP_RTC_SR4_WSYNCSS3                 8            /*  Synchronization Status of Posted Writes to SensorStrobe Channel 3 */
+#define BITP_RTC_SR4_WSYNCSS2                 7            /*  Synchronization Status of Posted Writes to SensorStrobe Channel 2 */
+#define BITP_RTC_SR4_WSYNCSS1                 6            /*  Synchronization Status of Posted Writes to SensorStrobe Channel 1 */
+#define BITP_RTC_SR4_WSYNCSSMSK               4            /*  Synchronization Status of Posted Writes to Masks for SensorStrobe Channel Register */
+#define BITP_RTC_SR4_WSYNCCR4SS               3            /*  Synchronization Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */
+#define BITP_RTC_SR4_WSYNCCR3SS               2            /*  Synchronization Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */
+#define BITP_RTC_SR4_WSYNCCR2IC               1            /*  Synchronization Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */
+#define BITP_RTC_SR4_WSYNCSR3                 0            /*  Synchronisation Status of Posted Writes to SR3 */
+#define BITM_RTC_SR4_WSYNCSSMSKOT            (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Synchronization Status of Posted Reads Writes to Mask for SensorStrobe Channels on Time Control Register */
+#define BITM_RTC_SR4_RSYNCIC4                (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Synchronization Status of Posted Reads of RTC Input Channel 4 */
+#define BITM_RTC_SR4_RSYNCIC3                (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Synchronization Status of Posted Reads of RTC Input Channel 3 */
+#define BITM_RTC_SR4_RSYNCIC2                (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Synchronization Status of Posted Reads of RTC Input Channel 2 */
+#define BITM_RTC_SR4_RSYNCIC0                (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Synchronization Status of Posted Reads of RTC Input Channel 0 */
+#define BITM_RTC_SR4_WSYNCSS4                (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Synchronization Status of Posted Writes to SensorStrobe Channel 4 */
+#define BITM_RTC_SR4_WSYNCSS3                (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Synchronization Status of Posted Writes to SensorStrobe Channel 3 */
+#define BITM_RTC_SR4_WSYNCSS2                (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Synchronization Status of Posted Writes to SensorStrobe Channel 2 */
+#define BITM_RTC_SR4_WSYNCSS1                (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Synchronization Status of Posted Writes to SensorStrobe Channel 1 */
+#define BITM_RTC_SR4_WSYNCSSMSK              (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Synchronization Status of Posted Writes to Masks for SensorStrobe Channel Register */
+#define BITM_RTC_SR4_WSYNCCR4SS              (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Synchronization Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */
+#define BITM_RTC_SR4_WSYNCCR3SS              (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Synchronization Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */
+#define BITM_RTC_SR4_WSYNCCR2IC              (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Synchronization Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */
+#define BITM_RTC_SR4_WSYNCSR3                (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to SR3 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SR5                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SR5_WPENDSSMSKOT            15            /*  Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */
+#define BITP_RTC_SR5_RPENDIC4                14            /*  Pending Status of Posted Reads of IC4 */
+#define BITP_RTC_SR5_RPENDIC3                13            /*  Pending Status of Posted Reads of IC3 */
+#define BITP_RTC_SR5_RPENDIC2                12            /*  Pending Status of Posted Reads of IC2 */
+#define BITP_RTC_SR5_RPENDIC0                10            /*  Pending Status of Posted Reads of Input Capture Channel 0 */
+#define BITP_RTC_SR5_WPENDSS4                 9            /*  Pending Status of Posted Writes to SensorStrobe Channel 4 */
+#define BITP_RTC_SR5_WPENDSS3                 8            /*  Pending Status of Posted Writes to SensorStrobe Channel 3 */
+#define BITP_RTC_SR5_WPENDSS2                 7            /*  Pending Status of Posted Writes to SensorStrobe Channel 2 */
+#define BITP_RTC_SR5_WPENDSS1                 6            /*  Pending Status of Posted Writes to SensorStrobe Channel 1 */
+#define BITP_RTC_SR5_WPENDSSMSK               4            /*  Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */
+#define BITP_RTC_SR5_WPENDCR4SS               3            /*  Pending Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */
+#define BITP_RTC_SR5_WPENDCR3SS               2            /*  Pending Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */
+#define BITP_RTC_SR5_WPENDCR2IC               1            /*  Pending Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */
+#define BITP_RTC_SR5_WPENDSR3                 0            /*  Pending Status of Posted Clearances of Interrupt Sources in RTC Status 3 Register */
+#define BITM_RTC_SR5_WPENDSSMSKOT            (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */
+#define BITM_RTC_SR5_RPENDIC4                (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Pending Status of Posted Reads of IC4 */
+#define BITM_RTC_SR5_RPENDIC3                (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Pending Status of Posted Reads of IC3 */
+#define BITM_RTC_SR5_RPENDIC2                (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Pending Status of Posted Reads of IC2 */
+#define BITM_RTC_SR5_RPENDIC0                (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Pending Status of Posted Reads of Input Capture Channel 0 */
+#define BITM_RTC_SR5_WPENDSS4                (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Pending Status of Posted Writes to SensorStrobe Channel 4 */
+#define BITM_RTC_SR5_WPENDSS3                (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Pending Status of Posted Writes to SensorStrobe Channel 3 */
+#define BITM_RTC_SR5_WPENDSS2                (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Pending Status of Posted Writes to SensorStrobe Channel 2 */
+#define BITM_RTC_SR5_WPENDSS1                (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Pending Status of Posted Writes to SensorStrobe Channel 1 */
+#define BITM_RTC_SR5_WPENDSSMSK              (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */
+#define BITM_RTC_SR5_WPENDCR4SS              (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Pending Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */
+#define BITM_RTC_SR5_WPENDCR3SS              (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Pending Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */
+#define BITM_RTC_SR5_WPENDCR2IC              (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Pending Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */
+#define BITM_RTC_SR5_WPENDSR3                (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Pending Status of Posted Clearances of Interrupt Sources in RTC Status 3 Register */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SR6                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SR6_FRZCNTPTR                9            /*  Pointer for the Triple-Read Sequence of FRZCNT */
+#define BITP_RTC_SR6_IC0SNAP                  8            /*  Confirmation That RTC Snapshot 0, 1, 2 Registers Reflect the Value of Input-Capture Channel RTC Input Capture Channel 0 */
+#define BITP_RTC_SR6_IC4UNR                   4            /*  Sticky Unread Status of the Input Capture Channel 4 */
+#define BITP_RTC_SR6_IC3UNR                   3            /*  Sticky Unread Status of the Input Capture Channel 3 */
+#define BITP_RTC_SR6_IC2UNR                   2            /*  Sticky Unread Status of the Input Capture Channel 2 */
+#define BITP_RTC_SR6_IC0UNR                   0            /*  Sticky Unread Status of the Input Capture Channel 0 */
+#define BITM_RTC_SR6_FRZCNTPTR               (_ADI_MSK_3(0x00000600,0x00000600U, uint16_t  ))    /*  Pointer for the Triple-Read Sequence of FRZCNT */
+#define BITM_RTC_SR6_IC0SNAP                 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Confirmation That RTC Snapshot 0, 1, 2 Registers Reflect the Value of Input-Capture Channel RTC Input Capture Channel 0 */
+#define BITM_RTC_SR6_IC4UNR                  (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Sticky Unread Status of the Input Capture Channel 4 */
+#define BITM_RTC_SR6_IC3UNR                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Sticky Unread Status of the Input Capture Channel 3 */
+#define BITM_RTC_SR6_IC2UNR                  (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Sticky Unread Status of the Input Capture Channel 2 */
+#define BITM_RTC_SR6_IC0UNR                  (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Sticky Unread Status of the Input Capture Channel 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SS1TGT                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SS1TGT_SS1TGT                0            /*  Current Target Value for the SensorStrobe Channel 1 */
+#define BITM_RTC_SS1TGT_SS1TGT               (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Current Target Value for the SensorStrobe Channel 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_FRZCNT                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_FRZCNT_FRZCNT                0            /*  RTC Freeze Count. Coherent, Triple 16-Bit Read of the 47-Bit RTC Count */
+#define BITM_RTC_FRZCNT_FRZCNT               (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  RTC Freeze Count. Coherent, Triple 16-Bit Read of the 47-Bit RTC Count */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SS2TGT                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SS2TGT_SS2TGT                0            /*  Current, Cumulative Target Time for SensorStrobe Channel 2, Taking Account of Any Auto-reloading */
+#define BITM_RTC_SS2TGT_SS2TGT               (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Current, Cumulative Target Time for SensorStrobe Channel 2, Taking Account of Any Auto-reloading */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SS3TGT                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SS3TGT_SS3TGT                0            /*  Current, Cumulative Target Time for SensorStrobe Channel 3, Taking Account of Any Auto-reloading */
+#define BITM_RTC_SS3TGT_SS3TGT               (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Current, Cumulative Target Time for SensorStrobe Channel 3, Taking Account of Any Auto-reloading */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SS1LOWDUR                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SS1LOWDUR_SS1LOWDUR          0            /*  Low Duration for SensorStrobe Channel 1. */
+#define BITM_RTC_SS1LOWDUR_SS1LOWDUR         (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Low Duration for SensorStrobe Channel 1. */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SS2LOWDUR                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SS2LOWDUR_SS2LOWDUR          0            /*  Low Duration for SensorStrobe Channel 2. */
+#define BITM_RTC_SS2LOWDUR_SS2LOWDUR         (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Low Duration for SensorStrobe Channel 2. */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SS3LOWDUR                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SS3LOWDUR_SS3LOWDUR          0            /*  Low Duration for SensorStrobe Channel 3. */
+#define BITM_RTC_SS3LOWDUR_SS3LOWDUR         (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Low Duration for SensorStrobe Channel 3. */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SS1HIGHDUR                       Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SS1HIGHDUR_SS1HIGHDUR        0            /*  High Duration for SensorStrobe Channel 1. */
+#define BITM_RTC_SS1HIGHDUR_SS1HIGHDUR       (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  High Duration for SensorStrobe Channel 1. */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SS2HIGHDUR                       Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SS2HIGHDUR_SS2HIGHDUR        0            /*  High Duration for SensorStrobe Channel 2. */
+#define BITM_RTC_SS2HIGHDUR_SS2HIGHDUR       (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  High Duration for SensorStrobe Channel 2. */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SS3HIGHDUR                       Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SS3HIGHDUR_SS3HIGHDUR        0            /*  High Duration for SensorStrobe Channel 3. */
+#define BITM_RTC_SS3HIGHDUR_SS3HIGHDUR       (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  High Duration for SensorStrobe Channel 3. */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SSMSKOT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SSMSKOT_SS4MSKOT            12            /*  SensorStrobe Channel 4 on Time Control */
+#define BITP_RTC_SSMSKOT_SS3MSKOT             8            /*  SensorStrobe Channel 3 on Time Control */
+#define BITP_RTC_SSMSKOT_SS2MSKOT             4            /*  SensorStrobe Channel 2 on Time Control */
+#define BITP_RTC_SSMSKOT_SS1MSKOT             0            /*  Concatenation of Thermometer-encoded Masks for the 16-bit SensorStrobe Channels */
+#define BITM_RTC_SSMSKOT_SS4MSKOT            (_ADI_MSK_3(0x0000F000,0x0000F000U, uint16_t  ))    /*  SensorStrobe Channel 4 on Time Control */
+#define BITM_RTC_SSMSKOT_SS3MSKOT            (_ADI_MSK_3(0x00000F00,0x00000F00U, uint16_t  ))    /*  SensorStrobe Channel 3 on Time Control */
+#define BITM_RTC_SSMSKOT_SS2MSKOT            (_ADI_MSK_3(0x000000F0,0x000000F0U, uint16_t  ))    /*  SensorStrobe Channel 2 on Time Control */
+#define BITM_RTC_SSMSKOT_SS1MSKOT            (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t  ))    /*  Concatenation of Thermometer-encoded Masks for the 16-bit SensorStrobe Channels */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_CR5SSS                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_CR5SSS_SS3SMPMTCHIRQEN      11            /*  Sample Activity Interrupt Enable for SensorStrobe Channel 3 */
+#define BITP_RTC_CR5SSS_SS3SMPEN              8            /*  GPIO Input Sample Enable for SensorStrobe Channel 3 */
+#define BITP_RTC_CR5SSS_SS2SMPMTCHIRQEN       7            /*  Sample Activity Interrupt Enable for SensorStrobe Channel 2 */
+#define BITP_RTC_CR5SSS_SS2SMPEN              4            /*  GPIO Input Sample Enable for SensorStrobe Channel 2 */
+#define BITP_RTC_CR5SSS_SS1SMPMTCHIRQEN       3            /*  Sample Activity Interrupt Enable for SensorStrobe Channel 1 */
+#define BITP_RTC_CR5SSS_SS1SMPEN              0            /*  GPIO Input Sample Enable for SensorStrobe Channel 1 */
+#define BITM_RTC_CR5SSS_SS3SMPMTCHIRQEN      (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Sample Activity Interrupt Enable for SensorStrobe Channel 3 */
+#define BITM_RTC_CR5SSS_SS3SMPEN             (_ADI_MSK_3(0x00000700,0x00000700U, uint16_t  ))    /*  GPIO Input Sample Enable for SensorStrobe Channel 3 */
+#define BITM_RTC_CR5SSS_SS2SMPMTCHIRQEN      (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Sample Activity Interrupt Enable for SensorStrobe Channel 2 */
+#define BITM_RTC_CR5SSS_SS2SMPEN             (_ADI_MSK_3(0x00000070,0x00000070U, uint16_t  ))    /*  GPIO Input Sample Enable for SensorStrobe Channel 2 */
+#define BITM_RTC_CR5SSS_SS1SMPMTCHIRQEN      (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Sample Activity Interrupt Enable for SensorStrobe Channel 1 */
+#define BITM_RTC_CR5SSS_SS1SMPEN             (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t  ))    /*  GPIO Input Sample Enable for SensorStrobe Channel 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_CR6SSS                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_CR6SSS_SS3SMPONRE           10            /*  GPIO Sample Around Rising Edge of SensorStrobe Channel 3 */
+#define BITP_RTC_CR6SSS_SS3SMPONFE            8            /*  GPIO Sample Around Falling Edge of SensorStrobe Channel 3 */
+#define BITP_RTC_CR6SSS_SS2SMPONRE            6            /*  GPIO Sample Around Rising Edge of SensorStrobe Channel 2 */
+#define BITP_RTC_CR6SSS_SS2SMPONFE            4            /*  GPIO Sample Around Falling Edge of SensorStrobe Channel 2 */
+#define BITP_RTC_CR6SSS_SS1SMPONRE            2            /*  GPIO Sample Around Rising Edge of SensorStrobe Channel 1 */
+#define BITP_RTC_CR6SSS_SS1SMPONFE            0            /*  GPIO Sample Around Falling Edge of SensorStrobe Channel 1 */
+#define BITM_RTC_CR6SSS_SS3SMPONRE           (_ADI_MSK_3(0x00000C00,0x00000C00U, uint16_t  ))    /*  GPIO Sample Around Rising Edge of SensorStrobe Channel 3 */
+#define BITM_RTC_CR6SSS_SS3SMPONFE           (_ADI_MSK_3(0x00000300,0x00000300U, uint16_t  ))    /*  GPIO Sample Around Falling Edge of SensorStrobe Channel 3 */
+#define BITM_RTC_CR6SSS_SS2SMPONRE           (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t  ))    /*  GPIO Sample Around Rising Edge of SensorStrobe Channel 2 */
+#define BITM_RTC_CR6SSS_SS2SMPONFE           (_ADI_MSK_3(0x00000030,0x00000030U, uint16_t  ))    /*  GPIO Sample Around Falling Edge of SensorStrobe Channel 2 */
+#define BITM_RTC_CR6SSS_SS1SMPONRE           (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t  ))    /*  GPIO Sample Around Rising Edge of SensorStrobe Channel 1 */
+#define BITM_RTC_CR6SSS_SS1SMPONFE           (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t  ))    /*  GPIO Sample Around Falling Edge of SensorStrobe Channel 1 */
+#define ENUM_RTC_CR6SSS_SS3NORES             (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  SS3SMPONRE: No sampling of input around rising edge */
+#define ENUM_RTC_CR6SSS_SS3BRES              (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  SS3SMPONRE: Input sampled one clock cycle before rising edge of the SensorStrobe channel 3 */
+#define ENUM_RTC_CR6SSS_SS3RES               (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  SS3SMPONRE: Input sampled at rising edge of the SensorStrobe channel 3 */
+#define ENUM_RTC_CR6SSS_SS3ARES              (_ADI_MSK_3(0x00000C00,0x00000C00U, uint16_t  ))    /*  SS3SMPONRE: Input sampled one clock cycle after rising edge of the SensorStrobe channel 3 */
+#define ENUM_RTC_CR6SSS_SS3NOFES             (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  SS3SMPONFE: No sampling of input around falling edge */
+#define ENUM_RTC_CR6SSS_SS3BFES              (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  SS3SMPONFE: Input sampled one clock cycle before falling edge of the SensorStrobe channel 3 */
+#define ENUM_RTC_CR6SSS_SS3FES               (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  SS3SMPONFE: Input sampled at falling edge of the SensorStrobe channel 3 */
+#define ENUM_RTC_CR6SSS_SS3AFES              (_ADI_MSK_3(0x00000300,0x00000300U, uint16_t  ))    /*  SS3SMPONFE: Input sampled one clock cycle after falling edge of the SensorStrobe channel 3 */
+#define ENUM_RTC_CR6SSS_SS2NORES             (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  SS2SMPONRE: No sampling of input around rising edge */
+#define ENUM_RTC_CR6SSS_SS2BRES              (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  SS2SMPONRE: Input sampled one clock cycle before rising edge of the SensorStrobe channel 2 */
+#define ENUM_RTC_CR6SSS_SS2RES               (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  SS2SMPONRE: Input sampled at rising edge of the SensorStrobe channel 2 */
+#define ENUM_RTC_CR6SSS_SS2ARES              (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t  ))    /*  SS2SMPONRE: Input sampled one clock cycle after rising edge of the SensorStrobe channel 2 */
+#define ENUM_RTC_CR6SSS_SS2NOFES             (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  SS2SMPONFE: No sampling of input around falling edge */
+#define ENUM_RTC_CR6SSS_SS2BFES              (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  SS2SMPONFE: Input sampled one clock cycle before falling edge of the SensorStrobe channel 2 */
+#define ENUM_RTC_CR6SSS_SS2FES               (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  SS2SMPONFE: Input sampled at falling edge of the SensorStrobe channel 2 */
+#define ENUM_RTC_CR6SSS_SS2AFES              (_ADI_MSK_3(0x00000030,0x00000030U, uint16_t  ))    /*  SS2SMPONFE: Input sampled one clock cycle after falling edge of the SensorStrobe channel 2 */
+#define ENUM_RTC_CR6SSS_SS1NORES             (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  SS1SMPONRE: No sampling of input around rising edge */
+#define ENUM_RTC_CR6SSS_SS1BRES              (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  SS1SMPONRE: Input sampled one clock cycle before rising edge of the SensorStrobe channel 1 */
+#define ENUM_RTC_CR6SSS_SS1RES               (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  SS1SMPONRE: Input sampled at rising edge of the SensorStrobe channel 1 */
+#define ENUM_RTC_CR6SSS_SS1ARES              (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t  ))    /*  SS1SMPONRE: Input sampled one clock cycle after rising edge of the SensorStrobe channel 1 */
+#define ENUM_RTC_CR6SSS_SS1NOFES             (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  SS1SMPONFE: No sampling of input around falling edge */
+#define ENUM_RTC_CR6SSS_SS1BFES              (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  SS1SMPONFE: Input sampled one clock cycle before falling edge of the SensorStrobe channel 1 */
+#define ENUM_RTC_CR6SSS_SS1FES               (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  SS1SMPONFE: Input sampled at falling edge of the SensorStrobe channel 1 */
+#define ENUM_RTC_CR6SSS_SS1AFES              (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t  ))    /*  SS1SMPONFE: Input sampled one clock cycle after falling edge of the SensorStrobe channel 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_CR7SSS                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_CR7SSS_SS3SMPPTRN           13            /*  Sample Activity Selection for SensorStrobe Channel 3 */
+#define BITP_RTC_CR7SSS_SS3SMPEXP            10            /*  Expected GPIO Sample for SensorStrobe Channel 3 */
+#define BITP_RTC_CR7SSS_SS2SMPPTRN            8            /*  Sample Activity Selection for SensorStrobe Channel 2 */
+#define BITP_RTC_CR7SSS_SS2SMPEXP             5            /*  Expected GPIO Sample for SensorStrobe Channel 2 */
+#define BITP_RTC_CR7SSS_SS1SMPPTRN            3            /*  Sample Activity Selection for SensorStrobe Channel 1 */
+#define BITP_RTC_CR7SSS_SS1SMPEXP             0            /*  Expected GPIO Sample for SensorStrobe Channel 1 */
+#define BITM_RTC_CR7SSS_SS3SMPPTRN           (_ADI_MSK_3(0x00006000,0x00006000U, uint16_t  ))    /*  Sample Activity Selection for SensorStrobe Channel 3 */
+#define BITM_RTC_CR7SSS_SS3SMPEXP            (_ADI_MSK_3(0x00001C00,0x00001C00U, uint16_t  ))    /*  Expected GPIO Sample for SensorStrobe Channel 3 */
+#define BITM_RTC_CR7SSS_SS2SMPPTRN           (_ADI_MSK_3(0x00000300,0x00000300U, uint16_t  ))    /*  Sample Activity Selection for SensorStrobe Channel 2 */
+#define BITM_RTC_CR7SSS_SS2SMPEXP            (_ADI_MSK_3(0x000000E0,0x000000E0U, uint16_t  ))    /*  Expected GPIO Sample for SensorStrobe Channel 2 */
+#define BITM_RTC_CR7SSS_SS1SMPPTRN           (_ADI_MSK_3(0x00000018,0x00000018U, uint16_t  ))    /*  Sample Activity Selection for SensorStrobe Channel 1 */
+#define BITM_RTC_CR7SSS_SS1SMPEXP            (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t  ))    /*  Expected GPIO Sample for SensorStrobe Channel 1 */
+#define ENUM_RTC_CR7SSS_SS3SMPCHNG           (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  SS3SMPPTRN: Current GPIO sample is not same as previous sample */
+#define ENUM_RTC_CR7SSS_SS3SMPSAME           (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  SS3SMPPTRN: Current GPIO sample is same as previous sample */
+#define ENUM_RTC_CR7SSS_SS3SMPMTCH           (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  SS3SMPPTRN: Current GPIO sample is same as expected sample */
+#define ENUM_RTC_CR7SSS_SS3SMPNOMTCH         (_ADI_MSK_3(0x00006000,0x00006000U, uint16_t  ))    /*  SS3SMPPTRN: Current GPIO sample is not same as expected sample */
+#define ENUM_RTC_CR7SSS_SS2SMPCHNG           (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  SS2SMPPTRN: Current GPIO sample is not same as previous sample */
+#define ENUM_RTC_CR7SSS_SS2SMPSAME           (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  SS2SMPPTRN: Current GPIO sample is same as previous sample */
+#define ENUM_RTC_CR7SSS_SS2SMPMTCH           (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  SS2SMPPTRN: Current GPIO sample is same as expected sample */
+#define ENUM_RTC_CR7SSS_SS2SMPNOMTCH         (_ADI_MSK_3(0x00000300,0x00000300U, uint16_t  ))    /*  SS2SMPPTRN: Current GPIO sample is not same as expected sample */
+#define ENUM_RTC_CR7SSS_SS1SMPCHNG           (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  SS1SMPPTRN: Current GPIO sample is not same as previous sample */
+#define ENUM_RTC_CR7SSS_SS1SMPSAME           (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  SS1SMPPTRN: Current GPIO sample is same as previous sample */
+#define ENUM_RTC_CR7SSS_SS1SMPMTCH           (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  SS1SMPPTRN: Current GPIO sample is same as expected sample */
+#define ENUM_RTC_CR7SSS_SS1SMPNOMTCH         (_ADI_MSK_3(0x00000018,0x00000018U, uint16_t  ))    /*  SS1SMPPTRN: Current GPIO sample is not same as expected sample */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SR7                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SR7_SS4OUT                  15            /*  Output Value for SensorStrobe Channel 4 */
+#define BITP_RTC_SR7_SS3OUT                  14            /*  Output Value for SensorStrobe Channel 3 */
+#define BITP_RTC_SR7_SS2OUT                  13            /*  Output Value for SensorStrobe Channel 2 */
+#define BITP_RTC_SR7_SS1OUT                  12            /*  Output Value for SensorStrobe Channel 1 */
+#define BITP_RTC_SR7_SS3SMPMTCHIRQ           11            /*  Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 3 */
+#define BITP_RTC_SR7_SS3SMP                   8            /*  Latest GPIO Sample for SensorStrobe Channel 3 */
+#define BITP_RTC_SR7_SS2SMPMTCHIRQ            7            /*  Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 2 */
+#define BITP_RTC_SR7_SS2SMP                   4            /*  Latest GPIO Sample for SensorStrobe Channel 2 */
+#define BITP_RTC_SR7_SS1SMPMTCHIRQ            3            /*  Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 1 */
+#define BITP_RTC_SR7_SS1SMP                   0            /*  Latest GPIO Sample for SensorStrobe Channel 1 */
+#define BITM_RTC_SR7_SS4OUT                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Output Value for SensorStrobe Channel 4 */
+#define BITM_RTC_SR7_SS3OUT                  (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Output Value for SensorStrobe Channel 3 */
+#define BITM_RTC_SR7_SS2OUT                  (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Output Value for SensorStrobe Channel 2 */
+#define BITM_RTC_SR7_SS1OUT                  (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Output Value for SensorStrobe Channel 1 */
+#define BITM_RTC_SR7_SS3SMPMTCHIRQ           (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 3 */
+#define BITM_RTC_SR7_SS3SMP                  (_ADI_MSK_3(0x00000700,0x00000700U, uint16_t  ))    /*  Latest GPIO Sample for SensorStrobe Channel 3 */
+#define BITM_RTC_SR7_SS2SMPMTCHIRQ           (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 2 */
+#define BITM_RTC_SR7_SS2SMP                  (_ADI_MSK_3(0x00000070,0x00000070U, uint16_t  ))    /*  Latest GPIO Sample for SensorStrobe Channel 2 */
+#define BITM_RTC_SR7_SS1SMPMTCHIRQ           (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 1 */
+#define BITM_RTC_SR7_SS1SMP                  (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t  ))    /*  Latest GPIO Sample for SensorStrobe Channel 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SR8                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SR8_WSYNCGPMUX1             13            /*  Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 1 */
+#define BITP_RTC_SR8_WSYNCGPMUX0             12            /*  Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 0 */
+#define BITP_RTC_SR8_WSYNCSR7                11            /*  Synchronisation Status of Posted Writes to Status 7 Register */
+#define BITP_RTC_SR8_WSYNCCR7SSS             10            /*  Synchronisation Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register */
+#define BITP_RTC_SR8_WSYNCCR6SSS              9            /*  Synchronisation Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register */
+#define BITP_RTC_SR8_WSYNCCR5SSS              8            /*  Synchronisation Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register */
+#define BITP_RTC_SR8_WSYNCSS3HIGHDUR          6            /*  Synchronisation Status of Posted Writes to SensorStrobe Channel 3 High Duration Register */
+#define BITP_RTC_SR8_WSYNCSS2HIGHDUR          5            /*  Synchronisation Status of Posted Writes to SensorStrobe Channel 2 High Duration Register */
+#define BITP_RTC_SR8_WSYNCSS1HIGHDUR          4            /*  Synchronisation Status of Posted Writes to SensorStrobe Channel 1 High Duration Register */
+#define BITP_RTC_SR8_WSYNCSS3LOWDUR           2            /*  Synchronisation Status of Posted Writes to SensorStrobe Channel 3 Low Duration Register */
+#define BITP_RTC_SR8_WSYNCSS2LOWDUR           1            /*  Synchronisation Status of Posted Writes to SensorStrobe Channel 2 Low Duration Register */
+#define BITP_RTC_SR8_WSYNCSS1LOWDUR           0            /*  Synchronisation Status of Posted Writes to SensorStrobe Channel 1 Low Duration Register */
+#define BITM_RTC_SR8_WSYNCGPMUX1             (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 1 */
+#define BITM_RTC_SR8_WSYNCGPMUX0             (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 0 */
+#define BITM_RTC_SR8_WSYNCSR7                (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to Status 7 Register */
+#define BITM_RTC_SR8_WSYNCCR7SSS             (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register */
+#define BITM_RTC_SR8_WSYNCCR6SSS             (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register */
+#define BITM_RTC_SR8_WSYNCCR5SSS             (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register */
+#define BITM_RTC_SR8_WSYNCSS3HIGHDUR         (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to SensorStrobe Channel 3 High Duration Register */
+#define BITM_RTC_SR8_WSYNCSS2HIGHDUR         (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to SensorStrobe Channel 2 High Duration Register */
+#define BITM_RTC_SR8_WSYNCSS1HIGHDUR         (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to SensorStrobe Channel 1 High Duration Register */
+#define BITM_RTC_SR8_WSYNCSS3LOWDUR          (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to SensorStrobe Channel 3 Low Duration Register */
+#define BITM_RTC_SR8_WSYNCSS2LOWDUR          (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to SensorStrobe Channel 2 Low Duration Register */
+#define BITM_RTC_SR8_WSYNCSS1LOWDUR          (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Synchronisation Status of Posted Writes to SensorStrobe Channel 1 Low Duration Register */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_SR9                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_SR9_WPENDGPMUX1             13            /*  Pending Status of Posted Writes to  GPMUX1 */
+#define BITP_RTC_SR9_WPENDGPMUX0             12            /*  Pending Status of Posted Writes to GPMUX0 */
+#define BITP_RTC_SR9_WPENDSR7                11            /*  Pending Status of Posted Writes to SR7 */
+#define BITP_RTC_SR9_WPENDCR7SSS             10            /*  Pending Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register */
+#define BITP_RTC_SR9_WPENDCR6SSS              9            /*  Pending Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register */
+#define BITP_RTC_SR9_WPENDCR5SSS              8            /*  Pending Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register */
+#define BITP_RTC_SR9_WPENDSS3HIGHDUR          6            /*  Pending Status of Posted Writes to SensortStrobe Channel 3 High Duration Register */
+#define BITP_RTC_SR9_WPENDSS2HIGHDUR          5            /*  Pending Status of Posted Writes to SensortStrobe Channel 2 High Duration Register */
+#define BITP_RTC_SR9_WPENDSS1HIGHDUR          4            /*  Pending Status of Posted Writes to SensortStrobe Channel 1 High Duration Register */
+#define BITP_RTC_SR9_WPENDSS3LOWDUR           2            /*  Pending Status of Posted Writes to SensortStrobe Channel 3 Low Duration Register */
+#define BITP_RTC_SR9_WPENDSS2LOWDUR           1            /*  Pending Status of Posted Writes to SensortStrobe Channel 2 Low Duration Register */
+#define BITP_RTC_SR9_WPENDSS1LOWDUR           0            /*  Pending Status of Posted Writes to SensortStrobe Channel 1 Low Duration Register */
+#define BITM_RTC_SR9_WPENDGPMUX1             (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Pending Status of Posted Writes to  GPMUX1 */
+#define BITM_RTC_SR9_WPENDGPMUX0             (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Pending Status of Posted Writes to GPMUX0 */
+#define BITM_RTC_SR9_WPENDSR7                (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Pending Status of Posted Writes to SR7 */
+#define BITM_RTC_SR9_WPENDCR7SSS             (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Pending Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register */
+#define BITM_RTC_SR9_WPENDCR6SSS             (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Pending Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register */
+#define BITM_RTC_SR9_WPENDCR5SSS             (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Pending Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register */
+#define BITM_RTC_SR9_WPENDSS3HIGHDUR         (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Pending Status of Posted Writes to SensortStrobe Channel 3 High Duration Register */
+#define BITM_RTC_SR9_WPENDSS2HIGHDUR         (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Pending Status of Posted Writes to SensortStrobe Channel 2 High Duration Register */
+#define BITM_RTC_SR9_WPENDSS1HIGHDUR         (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Pending Status of Posted Writes to SensortStrobe Channel 1 High Duration Register */
+#define BITM_RTC_SR9_WPENDSS3LOWDUR          (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Pending Status of Posted Writes to SensortStrobe Channel 3 Low Duration Register */
+#define BITM_RTC_SR9_WPENDSS2LOWDUR          (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Pending Status of Posted Writes to SensortStrobe Channel 2 Low Duration Register */
+#define BITM_RTC_SR9_WPENDSS1LOWDUR          (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Pending Status of Posted Writes to SensortStrobe Channel 1 Low Duration Register */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_GPMUX0                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_GPMUX0_SS2GPIN1SEL          12            /*  GPIO Mux Selection for SensorStrobe Channel 2 Input 1 */
+#define BITP_RTC_GPMUX0_SS2GPIN0SEL           9            /*  GPIO Mux Selection for SensorStrobe Channel 2 Input 0 */
+#define BITP_RTC_GPMUX0_SS1GPIN2SEL           6            /*  GPIO Mux Selection for SensorStrobe Channel 1 Input 2 */
+#define BITP_RTC_GPMUX0_SS1GPIN1SEL           3            /*  GPIO Mux Selection for SensorStrobe Channel 1 Input 1 */
+#define BITP_RTC_GPMUX0_SS1GPIN0SEL           0            /*  GPIO Mux Selection for SensorStrobe Channel 1 Input0 */
+#define BITM_RTC_GPMUX0_SS2GPIN1SEL          (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t  ))    /*  GPIO Mux Selection for SensorStrobe Channel 2 Input 1 */
+#define BITM_RTC_GPMUX0_SS2GPIN0SEL          (_ADI_MSK_3(0x00000E00,0x00000E00U, uint16_t  ))    /*  GPIO Mux Selection for SensorStrobe Channel 2 Input 0 */
+#define BITM_RTC_GPMUX0_SS1GPIN2SEL          (_ADI_MSK_3(0x000001C0,0x000001C0U, uint16_t  ))    /*  GPIO Mux Selection for SensorStrobe Channel 1 Input 2 */
+#define BITM_RTC_GPMUX0_SS1GPIN1SEL          (_ADI_MSK_3(0x00000038,0x00000038U, uint16_t  ))    /*  GPIO Mux Selection for SensorStrobe Channel 1 Input 1 */
+#define BITM_RTC_GPMUX0_SS1GPIN0SEL          (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t  ))    /*  GPIO Mux Selection for SensorStrobe Channel 1 Input0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RTC_GPMUX1                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RTC_GPMUX1_SS3DIFFOUT           15            /*  Differential SensorStrobe Out Option for SensorStrobe Channel 3 */
+#define BITP_RTC_GPMUX1_SS1DIFFOUT           14            /*  Differential SensorStrobe Out Option for SensorStrobe Channel 1 */
+#define BITP_RTC_GPMUX1_SS3GPIN2SEL           9            /*  GPIO Mux Selection for SensorStrobe Channel 3 Input 2 */
+#define BITP_RTC_GPMUX1_SS3GPIN1SEL           6            /*  GPIO Mux Selection for SensorStrobe Channel 3 Input 1 */
+#define BITP_RTC_GPMUX1_SS3GPIN0SEL           3            /*  GPIO Mux Selection for SensorStrobe Channel 3 Input 0 */
+#define BITP_RTC_GPMUX1_SS2GPIN2SEL           0            /*  GPIO Mux Selection for SensorStrobe Channel 2 Input 2 */
+#define BITM_RTC_GPMUX1_SS3DIFFOUT           (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Differential SensorStrobe Out Option for SensorStrobe Channel 3 */
+#define BITM_RTC_GPMUX1_SS1DIFFOUT           (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Differential SensorStrobe Out Option for SensorStrobe Channel 1 */
+#define BITM_RTC_GPMUX1_SS3GPIN2SEL          (_ADI_MSK_3(0x00000E00,0x00000E00U, uint16_t  ))    /*  GPIO Mux Selection for SensorStrobe Channel 3 Input 2 */
+#define BITM_RTC_GPMUX1_SS3GPIN1SEL          (_ADI_MSK_3(0x000001C0,0x000001C0U, uint16_t  ))    /*  GPIO Mux Selection for SensorStrobe Channel 3 Input 1 */
+#define BITM_RTC_GPMUX1_SS3GPIN0SEL          (_ADI_MSK_3(0x00000038,0x00000038U, uint16_t  ))    /*  GPIO Mux Selection for SensorStrobe Channel 3 Input 0 */
+#define BITM_RTC_GPMUX1_SS2GPIN2SEL          (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t  ))    /*  GPIO Mux Selection for SensorStrobe Channel 2 Input 2 */
+
+
+/* ============================================================================================================================
+        System Identification and Debug Enable
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        SYS
+   ============================================================================================================================ */
+#define REG_SYS_ADIID                        0x40002020            /*  SYS ADI Identification */
+#define REG_SYS_CHIPID                       0x40002024            /*  SYS Chip Identifier */
+#define REG_SYS_SWDEN                        0x40002040            /*  SYS Serial Wire Debug Enable */
+
+/* ============================================================================================================================
+        SYS Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          SYS_ADIID                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SYS_ADIID_VALUE                  0            /*  Reads a fixed value of 0x4144 to indicate to debuggers that they are connected to an Analog Devices implemented Cortex based part */
+#define BITM_SYS_ADIID_VALUE                 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Reads a fixed value of 0x4144 to indicate to debuggers that they are connected to an Analog Devices implemented Cortex based part */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SYS_CHIPID                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SYS_CHIPID_PARTID                4            /*  Part identifier */
+#define BITP_SYS_CHIPID_REV                   0            /*  Silicon revision */
+#define BITM_SYS_CHIPID_PARTID               (_ADI_MSK_3(0x0000FFF0,0x0000FFF0U, uint16_t  ))    /*  Part identifier */
+#define BITM_SYS_CHIPID_REV                  (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t  ))    /*  Silicon revision */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SYS_SWDEN                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SYS_SWDEN_VALUE                  0            /*  To enable SWD interface */
+#define BITM_SYS_SWDEN_VALUE                 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  To enable SWD interface */
+
+
+/* ============================================================================================================================
+        Watchdog Timer
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        WDT0
+   ============================================================================================================================ */
+#define REG_WDT0_LOAD                        0x40002C00            /*  WDT0 Load Value */
+#define REG_WDT0_CCNT                        0x40002C04            /*  WDT0 Current Count Value */
+#define REG_WDT0_CTL                         0x40002C08            /*  WDT0 Control */
+#define REG_WDT0_RESTART                     0x40002C0C            /*  WDT0 Clear Interrupt */
+#define REG_WDT0_STAT                        0x40002C18            /*  WDT0 Status */
+
+/* ============================================================================================================================
+        WDT Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          WDT_LOAD                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_WDT_LOAD_VALUE                   0            /*  Load Value */
+#define BITM_WDT_LOAD_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Load Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          WDT_CCNT                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_WDT_CCNT_VALUE                   0            /*  Current Count Value */
+#define BITM_WDT_CCNT_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Current Count Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          WDT_CTL                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_WDT_CTL_SPARE                    7            /*  Unused Spare Bit */
+#define BITP_WDT_CTL_MODE                     6            /*  Timer Mode */
+#define BITP_WDT_CTL_EN                       5            /*  Timer Enable */
+#define BITP_WDT_CTL_PRE                      2            /*  Prescaler */
+#define BITP_WDT_CTL_IRQ                      1            /*  Timer Interrupt */
+#define BITM_WDT_CTL_SPARE                   (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Unused Spare Bit */
+#define BITM_WDT_CTL_MODE                    (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Timer Mode */
+#define BITM_WDT_CTL_EN                      (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Timer Enable */
+#define BITM_WDT_CTL_PRE                     (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t  ))    /*  Prescaler */
+#define BITM_WDT_CTL_IRQ                     (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Timer Interrupt */
+#define ENUM_WDT_CTL_FREE_RUN                (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  MODE: Free running mode */
+#define ENUM_WDT_CTL_PERIODIC                (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  MODE: Periodic mode */
+#define ENUM_WDT_CTL_WDT_DIS                 (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  EN: WDT not enabled */
+#define ENUM_WDT_CTL_WDT_EN                  (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  EN: WDT enabled */
+#define ENUM_WDT_CTL_DIV1                    (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  PRE: Source clock/1 */
+#define ENUM_WDT_CTL_DIV16                   (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  PRE: Source clock/16 */
+#define ENUM_WDT_CTL_DIV256                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  PRE: Source clock/256 (default) */
+#define ENUM_WDT_CTL_RST                     (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  IRQ: WDT asserts reset when timed out */
+#define ENUM_WDT_CTL_INT                     (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  IRQ: WDT generates interrupt when timed out */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          WDT_RESTART                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_WDT_RESTART_CLRWORD              0            /*  Clear Watchdog */
+#define BITM_WDT_RESTART_CLRWORD             (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Clear Watchdog */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          WDT_STAT                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_WDT_STAT_RSTCTL                  5            /*  Reset Control Register Written and Locked */
+#define BITP_WDT_STAT_LOCKED                  4            /*  Lock Status Bit */
+#define BITP_WDT_STAT_COUNTING                3            /*  Control Register Write Sync in Progress */
+#define BITP_WDT_STAT_LOADING                 2            /*  Load Register Write Sync in Progress */
+#define BITP_WDT_STAT_CLRIRQ                  1            /*  Clear Interrupt Register Write Sync in Progress */
+#define BITP_WDT_STAT_IRQ                     0            /*  WDT Interrupt */
+#define BITM_WDT_STAT_RSTCTL                 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Reset Control Register Written and Locked */
+#define BITM_WDT_STAT_LOCKED                 (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Lock Status Bit */
+#define BITM_WDT_STAT_COUNTING               (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Control Register Write Sync in Progress */
+#define BITM_WDT_STAT_LOADING                (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Load Register Write Sync in Progress */
+#define BITM_WDT_STAT_CLRIRQ                 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Clear Interrupt Register Write Sync in Progress */
+#define BITM_WDT_STAT_IRQ                    (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  WDT Interrupt */
+
+
+/* ============================================================================================================================
+        I2C Master/Slave
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        I2C0
+   ============================================================================================================================ */
+#define REG_I2C0_MCTL                        0x40003000            /*  I2C0 Master Control */
+#define REG_I2C0_MSTAT                       0x40003004            /*  I2C0 Master Status */
+#define REG_I2C0_MRX                         0x40003008            /*  I2C0 Master Receive Data */
+#define REG_I2C0_MTX                         0x4000300C            /*  I2C0 Master Transmit Data */
+#define REG_I2C0_MRXCNT                      0x40003010            /*  I2C0 Master Receive Data Count */
+#define REG_I2C0_MCRXCNT                     0x40003014            /*  I2C0 Master Current Receive Data Count */
+#define REG_I2C0_ADDR1                       0x40003018            /*  I2C0 Master Address Byte 1 */
+#define REG_I2C0_ADDR2                       0x4000301C            /*  I2C0 Master Address Byte 2 */
+#define REG_I2C0_BYT                         0x40003020            /*  I2C0 Start Byte */
+#define REG_I2C0_DIV                         0x40003024            /*  I2C0 Serial Clock Period Divisor */
+#define REG_I2C0_SCTL                        0x40003028            /*  I2C0 Slave Control */
+#define REG_I2C0_SSTAT                       0x4000302C            /*  I2C0 Slave I2C Status/Error/IRQ */
+#define REG_I2C0_SRX                         0x40003030            /*  I2C0 Slave Receive */
+#define REG_I2C0_STX                         0x40003034            /*  I2C0 Slave Transmit */
+#define REG_I2C0_ALT                         0x40003038            /*  I2C0 Hardware General Call ID */
+#define REG_I2C0_ID0                         0x4000303C            /*  I2C0 First Slave Address Device ID */
+#define REG_I2C0_ID1                         0x40003040            /*  I2C0 Second Slave Address Device ID */
+#define REG_I2C0_ID2                         0x40003044            /*  I2C0 Third Slave Address Device ID */
+#define REG_I2C0_ID3                         0x40003048            /*  I2C0 Fourth Slave Address Device ID */
+#define REG_I2C0_STAT                        0x4000304C            /*  I2C0 Master and Slave FIFO Status */
+#define REG_I2C0_SHCTL                       0x40003050            /*  I2C0 Shared Control */
+#define REG_I2C0_TCTL                        0x40003054            /*  I2C0 Timing Control Register */
+#define REG_I2C0_ASTRETCH_SCL                0x40003058            /*  I2C0 Automatic Stretch SCL */
+
+/* ============================================================================================================================
+        I2C Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_MCTL                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_MCTL_STOPBUSCLR             13            /*  Prestop Bus Clear */
+#define BITP_I2C_MCTL_BUSCLR                 12            /*  Bus-Clear Enable */
+#define BITP_I2C_MCTL_MTXDMA                 11            /*  Enable Master Tx DMA Request */
+#define BITP_I2C_MCTL_MRXDMA                 10            /*  Enable Master Rx DMA Request */
+#define BITP_I2C_MCTL_MXMITDEC                9            /*  Decrement Master Tx FIFO Status When a Byte Txed */
+#define BITP_I2C_MCTL_IENCMP                  8            /*  Transaction Completed (or Stop Detected) Interrupt Enable */
+#define BITP_I2C_MCTL_IENACK                  7            /*  ACK Not Received Interrupt Enable */
+#define BITP_I2C_MCTL_IENALOST                6            /*  Arbitration Lost Interrupt Enable */
+#define BITP_I2C_MCTL_IENMTX                  5            /*  Transmit Request Interrupt Enable */
+#define BITP_I2C_MCTL_IENMRX                  4            /*  Receive Request Interrupt Enable */
+#define BITP_I2C_MCTL_STRETCHSCL              3            /*  Stretch SCL Enable */
+#define BITP_I2C_MCTL_LOOPBACK                2            /*  Internal Loopback Enable */
+#define BITP_I2C_MCTL_COMPLETE                1            /*  Start Back-off Disable */
+#define BITP_I2C_MCTL_MASEN                   0            /*  Master Enable */
+#define BITM_I2C_MCTL_STOPBUSCLR             (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Prestop Bus Clear */
+#define BITM_I2C_MCTL_BUSCLR                 (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Bus-Clear Enable */
+#define BITM_I2C_MCTL_MTXDMA                 (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Enable Master Tx DMA Request */
+#define BITM_I2C_MCTL_MRXDMA                 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Enable Master Rx DMA Request */
+#define BITM_I2C_MCTL_MXMITDEC               (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Decrement Master Tx FIFO Status When a Byte Txed */
+#define BITM_I2C_MCTL_IENCMP                 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Transaction Completed (or Stop Detected) Interrupt Enable */
+#define BITM_I2C_MCTL_IENACK                 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  ACK Not Received Interrupt Enable */
+#define BITM_I2C_MCTL_IENALOST               (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Arbitration Lost Interrupt Enable */
+#define BITM_I2C_MCTL_IENMTX                 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Transmit Request Interrupt Enable */
+#define BITM_I2C_MCTL_IENMRX                 (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Receive Request Interrupt Enable */
+#define BITM_I2C_MCTL_STRETCHSCL             (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Stretch SCL Enable */
+#define BITM_I2C_MCTL_LOOPBACK               (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Internal Loopback Enable */
+#define BITM_I2C_MCTL_COMPLETE               (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Start Back-off Disable */
+#define BITM_I2C_MCTL_MASEN                  (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Master Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_MSTAT                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_MSTAT_SCLFILT               14            /*  State of SCL Line */
+#define BITP_I2C_MSTAT_SDAFILT               13            /*  State of SDA Line */
+#define BITP_I2C_MSTAT_MTXUNDR               12            /*  Master Transmit Underflow */
+#define BITP_I2C_MSTAT_MSTOP                 11            /*  STOP Driven by This I2C Master */
+#define BITP_I2C_MSTAT_LINEBUSY              10            /*  Line is Busy */
+#define BITP_I2C_MSTAT_MRXOVR                 9            /*  Master Receive FIFO Overflow */
+#define BITP_I2C_MSTAT_TCOMP                  8            /*  Transaction Complete or Stop Detected */
+#define BITP_I2C_MSTAT_NACKDATA               7            /*  ACK Not Received in Response to Data Write */
+#define BITP_I2C_MSTAT_MBUSY                  6            /*  Master Busy */
+#define BITP_I2C_MSTAT_ALOST                  5            /*  Arbitration Lost */
+#define BITP_I2C_MSTAT_NACKADDR               4            /*  ACK Not Received in Response to an Address */
+#define BITP_I2C_MSTAT_MRXREQ                 3            /*  Master Receive Request */
+#define BITP_I2C_MSTAT_MTXREQ                 2            /*  Master Transmit Request/Clear Master Transmit Interrupt */
+#define BITP_I2C_MSTAT_MTXF                   0            /*  Master Transmit FIFO Status */
+#define BITM_I2C_MSTAT_SCLFILT               (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  State of SCL Line */
+#define BITM_I2C_MSTAT_SDAFILT               (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  State of SDA Line */
+#define BITM_I2C_MSTAT_MTXUNDR               (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Master Transmit Underflow */
+#define BITM_I2C_MSTAT_MSTOP                 (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  STOP Driven by This I2C Master */
+#define BITM_I2C_MSTAT_LINEBUSY              (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Line is Busy */
+#define BITM_I2C_MSTAT_MRXOVR                (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Master Receive FIFO Overflow */
+#define BITM_I2C_MSTAT_TCOMP                 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Transaction Complete or Stop Detected */
+#define BITM_I2C_MSTAT_NACKDATA              (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  ACK Not Received in Response to Data Write */
+#define BITM_I2C_MSTAT_MBUSY                 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Master Busy */
+#define BITM_I2C_MSTAT_ALOST                 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Arbitration Lost */
+#define BITM_I2C_MSTAT_NACKADDR              (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  ACK Not Received in Response to an Address */
+#define BITM_I2C_MSTAT_MRXREQ                (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Master Receive Request */
+#define BITM_I2C_MSTAT_MTXREQ                (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Master Transmit Request/Clear Master Transmit Interrupt */
+#define BITM_I2C_MSTAT_MTXF                  (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t  ))    /*  Master Transmit FIFO Status */
+#define ENUM_I2C_MSTAT_FIFO_EMPTY            (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  MTXF: FIFO Empty. */
+#define ENUM_I2C_MSTAT_FIFO_1BYTE            (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  MTXF: 1 byte in FIFO. */
+#define ENUM_I2C_MSTAT_FIFO_FULL             (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t  ))    /*  MTXF: FIFO Full. */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_MRX                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_MRX_VALUE                    0            /*  Master Receive Register */
+#define BITM_I2C_MRX_VALUE                   (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Master Receive Register */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_MTX                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_MTX_VALUE                    0            /*  Master Transmit Register */
+#define BITM_I2C_MTX_VALUE                   (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Master Transmit Register */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_MRXCNT                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_MRXCNT_EXTEND                8            /*  Extended Read */
+#define BITP_I2C_MRXCNT_VALUE                 0            /*  Receive Count */
+#define BITM_I2C_MRXCNT_EXTEND               (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Extended Read */
+#define BITM_I2C_MRXCNT_VALUE                (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Receive Count */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_MCRXCNT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_MCRXCNT_VALUE                0            /*  Current Receive Count */
+#define BITM_I2C_MCRXCNT_VALUE               (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Current Receive Count */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_ADDR1                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_ADDR1_VALUE                  0            /*  Address Byte 1 */
+#define BITM_I2C_ADDR1_VALUE                 (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Address Byte 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_ADDR2                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_ADDR2_VALUE                  0            /*  Address Byte 2 */
+#define BITM_I2C_ADDR2_VALUE                 (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Address Byte 2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_BYT                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_BYT_SBYTE                    0            /*  Start Byte */
+#define BITM_I2C_BYT_SBYTE                   (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Start Byte */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_DIV                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_DIV_HIGH                     8            /*  Serial Clock High Time */
+#define BITP_I2C_DIV_LOW                      0            /*  Serial Clock Low Time */
+#define BITM_I2C_DIV_HIGH                    (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t  ))    /*  Serial Clock High Time */
+#define BITM_I2C_DIV_LOW                     (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Serial Clock Low Time */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_SCTL                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_SCTL_STXDMA                 14            /*  Enable Slave Tx DMA Request */
+#define BITP_I2C_SCTL_SRXDMA                 13            /*  Enable Slave Rx DMA Request */
+#define BITP_I2C_SCTL_IENREPST               12            /*  Repeated Start Interrupt Enable */
+#define BITP_I2C_SCTL_STXDEC                 11            /*  Decrement Slave Tx FIFO Status When a Byte is Txed */
+#define BITP_I2C_SCTL_IENSTX                 10            /*  Slave Transmit Request Interrupt Enable */
+#define BITP_I2C_SCTL_IENSRX                  9            /*  Slave Receive Request Interrupt Enable */
+#define BITP_I2C_SCTL_IENSTOP                 8            /*  Stop Condition Detected Interrupt Enable */
+#define BITP_I2C_SCTL_NACK                    7            /*  NACK Next Communication */
+#define BITP_I2C_SCTL_EARLYTXR                5            /*  Early Transmit Request Mode */
+#define BITP_I2C_SCTL_GCSBCLR                 4            /*  General Call Status Bit Clear */
+#define BITP_I2C_SCTL_HGCEN                   3            /*  Hardware General Call Enable */
+#define BITP_I2C_SCTL_GCEN                    2            /*  General Call Enable */
+#define BITP_I2C_SCTL_ADR10EN                 1            /*  Enabled 10-bit Addressing */
+#define BITP_I2C_SCTL_SLVEN                   0            /*  Slave Enable */
+#define BITM_I2C_SCTL_STXDMA                 (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Enable Slave Tx DMA Request */
+#define BITM_I2C_SCTL_SRXDMA                 (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Enable Slave Rx DMA Request */
+#define BITM_I2C_SCTL_IENREPST               (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Repeated Start Interrupt Enable */
+#define BITM_I2C_SCTL_STXDEC                 (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Decrement Slave Tx FIFO Status When a Byte is Txed */
+#define BITM_I2C_SCTL_IENSTX                 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Slave Transmit Request Interrupt Enable */
+#define BITM_I2C_SCTL_IENSRX                 (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Slave Receive Request Interrupt Enable */
+#define BITM_I2C_SCTL_IENSTOP                (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Stop Condition Detected Interrupt Enable */
+#define BITM_I2C_SCTL_NACK                   (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  NACK Next Communication */
+#define BITM_I2C_SCTL_EARLYTXR               (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Early Transmit Request Mode */
+#define BITM_I2C_SCTL_GCSBCLR                (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  General Call Status Bit Clear */
+#define BITM_I2C_SCTL_HGCEN                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Hardware General Call Enable */
+#define BITM_I2C_SCTL_GCEN                   (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  General Call Enable */
+#define BITM_I2C_SCTL_ADR10EN                (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Enabled 10-bit Addressing */
+#define BITM_I2C_SCTL_SLVEN                  (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Slave Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_SSTAT                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_SSTAT_START                 14            /*  Start and Matching Address */
+#define BITP_I2C_SSTAT_REPSTART              13            /*  Repeated Start and Matching Address */
+#define BITP_I2C_SSTAT_IDMAT                 11            /*  Device ID Matched */
+#define BITP_I2C_SSTAT_STOP                  10            /*  Stop After Start and Matching Address */
+#define BITP_I2C_SSTAT_GCID                   8            /*  General ID */
+#define BITP_I2C_SSTAT_GCINT                  7            /*  General Call Interrupt */
+#define BITP_I2C_SSTAT_SBUSY                  6            /*  Slave Busy */
+#define BITP_I2C_SSTAT_NOACK                  5            /*  ACK Not Generated by the Slave */
+#define BITP_I2C_SSTAT_SRXOVR                 4            /*  Slave Receive FIFO Overflow */
+#define BITP_I2C_SSTAT_SRXREQ                 3            /*  Slave Receive Request */
+#define BITP_I2C_SSTAT_STXREQ                 2            /*  Slave Transmit Request/Slave Transmit Interrupt */
+#define BITP_I2C_SSTAT_STXUNDR                1            /*  Slave Transmit FIFO Underflow */
+#define BITP_I2C_SSTAT_STXFSEREQ              0            /*  Slave Tx FIFO Status or Early Request */
+#define BITM_I2C_SSTAT_START                 (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Start and Matching Address */
+#define BITM_I2C_SSTAT_REPSTART              (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Repeated Start and Matching Address */
+#define BITM_I2C_SSTAT_IDMAT                 (_ADI_MSK_3(0x00001800,0x00001800U, uint16_t  ))    /*  Device ID Matched */
+#define BITM_I2C_SSTAT_STOP                  (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Stop After Start and Matching Address */
+#define BITM_I2C_SSTAT_GCID                  (_ADI_MSK_3(0x00000300,0x00000300U, uint16_t  ))    /*  General ID */
+#define BITM_I2C_SSTAT_GCINT                 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  General Call Interrupt */
+#define BITM_I2C_SSTAT_SBUSY                 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Slave Busy */
+#define BITM_I2C_SSTAT_NOACK                 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  ACK Not Generated by the Slave */
+#define BITM_I2C_SSTAT_SRXOVR                (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Slave Receive FIFO Overflow */
+#define BITM_I2C_SSTAT_SRXREQ                (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Slave Receive Request */
+#define BITM_I2C_SSTAT_STXREQ                (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Slave Transmit Request/Slave Transmit Interrupt */
+#define BITM_I2C_SSTAT_STXUNDR               (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Slave Transmit FIFO Underflow */
+#define BITM_I2C_SSTAT_STXFSEREQ             (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Slave Tx FIFO Status or Early Request */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_SRX                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_SRX_VALUE                    0            /*  Slave Receive Register */
+#define BITM_I2C_SRX_VALUE                   (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Slave Receive Register */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_STX                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_STX_VALUE                    0            /*  Slave Transmit Register */
+#define BITM_I2C_STX_VALUE                   (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Slave Transmit Register */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_ALT                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_ALT_ID                       0            /*  Slave Alt */
+#define BITM_I2C_ALT_ID                      (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Slave Alt */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_ID0                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_ID0_VALUE                    0            /*  Slave Device ID 0 */
+#define BITM_I2C_ID0_VALUE                   (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Slave Device ID 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_ID1                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_ID1_VALUE                    0            /*  Slave Device ID 1 */
+#define BITM_I2C_ID1_VALUE                   (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Slave Device ID 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_ID2                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_ID2_VALUE                    0            /*  Slave Device ID 2 */
+#define BITM_I2C_ID2_VALUE                   (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Slave Device ID 2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_ID3                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_ID3_VALUE                    0            /*  Slave Device ID 3 */
+#define BITM_I2C_ID3_VALUE                   (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Slave Device ID 3 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_STAT                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_STAT_MFLUSH                  9            /*  Flush the Master Transmit FIFO */
+#define BITP_I2C_STAT_SFLUSH                  8            /*  Flush the Slave Transmit FIFO */
+#define BITP_I2C_STAT_MRXF                    6            /*  Master Receive FIFO Status */
+#define BITP_I2C_STAT_MTXF                    4            /*  Master Transmit FIFO Status */
+#define BITP_I2C_STAT_SRXF                    2            /*  Slave Receive FIFO Status */
+#define BITP_I2C_STAT_STXF                    0            /*  Slave Transmit FIFO Status */
+#define BITM_I2C_STAT_MFLUSH                 (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Flush the Master Transmit FIFO */
+#define BITM_I2C_STAT_SFLUSH                 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Flush the Slave Transmit FIFO */
+#define BITM_I2C_STAT_MRXF                   (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t  ))    /*  Master Receive FIFO Status */
+#define BITM_I2C_STAT_MTXF                   (_ADI_MSK_3(0x00000030,0x00000030U, uint16_t  ))    /*  Master Transmit FIFO Status */
+#define BITM_I2C_STAT_SRXF                   (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t  ))    /*  Slave Receive FIFO Status */
+#define BITM_I2C_STAT_STXF                   (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t  ))    /*  Slave Transmit FIFO Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_SHCTL                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_SHCTL_RST                    0            /*  Reset START STOP Detect Circuit */
+#define BITM_I2C_SHCTL_RST                   (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Reset START STOP Detect Circuit */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_TCTL                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_TCTL_FILTEROFF               8            /*  Input Filter Control */
+#define BITP_I2C_TCTL_THDATIN                 0            /*  Data in Hold Start */
+#define BITM_I2C_TCTL_FILTEROFF              (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Input Filter Control */
+#define BITM_I2C_TCTL_THDATIN                (_ADI_MSK_3(0x0000001F,0x0000001FU, uint16_t  ))    /*  Data in Hold Start */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          I2C_ASTRETCH_SCL                     Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_I2C_ASTRETCH_SCL_SLVTMO          9            /*  Slave Automatic Stretch Timeout */
+#define BITP_I2C_ASTRETCH_SCL_MSTTMO          8            /*  Master Automatic Stretch Timeout */
+#define BITP_I2C_ASTRETCH_SCL_SLV             4            /*  Slave Automatic Stretch Mode */
+#define BITP_I2C_ASTRETCH_SCL_MST             0            /*  Master Automatic Stretch Mode */
+#define BITM_I2C_ASTRETCH_SCL_SLVTMO         (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Slave Automatic Stretch Timeout */
+#define BITM_I2C_ASTRETCH_SCL_MSTTMO         (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Master Automatic Stretch Timeout */
+#define BITM_I2C_ASTRETCH_SCL_SLV            (_ADI_MSK_3(0x000000F0,0x000000F0U, uint16_t  ))    /*  Slave Automatic Stretch Mode */
+#define BITM_I2C_ASTRETCH_SCL_MST            (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t  ))    /*  Master Automatic Stretch Mode */
+
+
+/* ============================================================================================================================
+        Serial Peripheral Interface
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        SPI0
+   ============================================================================================================================ */
+#define REG_SPI0_STAT                        0x40004000            /*  SPI0 Status */
+#define REG_SPI0_RX                          0x40004004            /*  SPI0 Receive */
+#define REG_SPI0_TX                          0x40004008            /*  SPI0 Transmit */
+#define REG_SPI0_DIV                         0x4000400C            /*  SPI0 SPI Baud Rate Selection */
+#define REG_SPI0_CTL                         0x40004010            /*  SPI0 SPI Configuration */
+#define REG_SPI0_IEN                         0x40004014            /*  SPI0 SPI Interrupts Enable */
+#define REG_SPI0_CNT                         0x40004018            /*  SPI0 Transfer Byte Count */
+#define REG_SPI0_DMA                         0x4000401C            /*  SPI0 SPI DMA Enable */
+#define REG_SPI0_FIFO_STAT                   0x40004020            /*  SPI0 FIFO Status */
+#define REG_SPI0_RD_CTL                      0x40004024            /*  SPI0 Read Control */
+#define REG_SPI0_FLOW_CTL                    0x40004028            /*  SPI0 Flow Control */
+#define REG_SPI0_WAIT_TMR                    0x4000402C            /*  SPI0 Wait Timer for Flow Control */
+#define REG_SPI0_CS_CTL                      0x40004030            /*  SPI0 Chip Select Control for Multi-slave Connections */
+#define REG_SPI0_CS_OVERRIDE                 0x40004034            /*  SPI0 Chip Select Override */
+
+/* ============================================================================================================================
+        SPI1
+   ============================================================================================================================ */
+#define REG_SPI1_STAT                        0x40004400            /*  SPI1 Status */
+#define REG_SPI1_RX                          0x40004404            /*  SPI1 Receive */
+#define REG_SPI1_TX                          0x40004408            /*  SPI1 Transmit */
+#define REG_SPI1_DIV                         0x4000440C            /*  SPI1 SPI Baud Rate Selection */
+#define REG_SPI1_CTL                         0x40004410            /*  SPI1 SPI Configuration */
+#define REG_SPI1_IEN                         0x40004414            /*  SPI1 SPI Interrupts Enable */
+#define REG_SPI1_CNT                         0x40004418            /*  SPI1 Transfer Byte Count */
+#define REG_SPI1_DMA                         0x4000441C            /*  SPI1 SPI DMA Enable */
+#define REG_SPI1_FIFO_STAT                   0x40004420            /*  SPI1 FIFO Status */
+#define REG_SPI1_RD_CTL                      0x40004424            /*  SPI1 Read Control */
+#define REG_SPI1_FLOW_CTL                    0x40004428            /*  SPI1 Flow Control */
+#define REG_SPI1_WAIT_TMR                    0x4000442C            /*  SPI1 Wait Timer for Flow Control */
+#define REG_SPI1_CS_CTL                      0x40004430            /*  SPI1 Chip Select Control for Multi-slave Connections */
+#define REG_SPI1_CS_OVERRIDE                 0x40004434            /*  SPI1 Chip Select Override */
+
+/* ============================================================================================================================
+        SPI2
+   ============================================================================================================================ */
+#define REG_SPI2_STAT                        0x40024000            /*  SPI2 Status */
+#define REG_SPI2_RX                          0x40024004            /*  SPI2 Receive */
+#define REG_SPI2_TX                          0x40024008            /*  SPI2 Transmit */
+#define REG_SPI2_DIV                         0x4002400C            /*  SPI2 SPI Baud Rate Selection */
+#define REG_SPI2_CTL                         0x40024010            /*  SPI2 SPI Configuration */
+#define REG_SPI2_IEN                         0x40024014            /*  SPI2 SPI Interrupts Enable */
+#define REG_SPI2_CNT                         0x40024018            /*  SPI2 Transfer Byte Count */
+#define REG_SPI2_DMA                         0x4002401C            /*  SPI2 SPI DMA Enable */
+#define REG_SPI2_FIFO_STAT                   0x40024020            /*  SPI2 FIFO Status */
+#define REG_SPI2_RD_CTL                      0x40024024            /*  SPI2 Read Control */
+#define REG_SPI2_FLOW_CTL                    0x40024028            /*  SPI2 Flow Control */
+#define REG_SPI2_WAIT_TMR                    0x4002402C            /*  SPI2 Wait Timer for Flow Control */
+#define REG_SPI2_CS_CTL                      0x40024030            /*  SPI2 Chip Select Control for Multi-slave Connections */
+#define REG_SPI2_CS_OVERRIDE                 0x40024034            /*  SPI2 Chip Select Override */
+
+/* ============================================================================================================================
+        SPI Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_STAT                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_STAT_RDY                    15            /*  Detected an Edge on Ready Indicator for Flow Control */
+#define BITP_SPI_STAT_CSFALL                 14            /*  Detected a Falling Edge on CS, in Slave CON Mode */
+#define BITP_SPI_STAT_CSRISE                 13            /*  Detected a Rising Edge on CS, in Slave CON Mode */
+#define BITP_SPI_STAT_CSERR                  12            /*  Detected a CS Error Condition in Slave Mode */
+#define BITP_SPI_STAT_CS                     11            /*  CS Status */
+#define BITP_SPI_STAT_RXOVR                   7            /*  SPI Rx FIFO Overflow */
+#define BITP_SPI_STAT_RXIRQ                   6            /*  SPI Rx IRQ */
+#define BITP_SPI_STAT_TXIRQ                   5            /*  SPI Tx IRQ */
+#define BITP_SPI_STAT_TXUNDR                  4            /*  SPI Tx FIFO Underflow */
+#define BITP_SPI_STAT_TXDONE                  3            /*  SPI Tx Done in Read Command Mode */
+#define BITP_SPI_STAT_TXEMPTY                 2            /*  SPI Tx FIFO Empty Interrupt */
+#define BITP_SPI_STAT_XFRDONE                 1            /*  SPI Transfer Completion */
+#define BITP_SPI_STAT_IRQ                     0            /*  SPI Interrupt Status */
+#define BITM_SPI_STAT_RDY                    (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Detected an Edge on Ready Indicator for Flow Control */
+#define BITM_SPI_STAT_CSFALL                 (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Detected a Falling Edge on CS, in Slave CON Mode */
+#define BITM_SPI_STAT_CSRISE                 (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Detected a Rising Edge on CS, in Slave CON Mode */
+#define BITM_SPI_STAT_CSERR                  (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Detected a CS Error Condition in Slave Mode */
+#define BITM_SPI_STAT_CS                     (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  CS Status */
+#define BITM_SPI_STAT_RXOVR                  (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  SPI Rx FIFO Overflow */
+#define BITM_SPI_STAT_RXIRQ                  (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  SPI Rx IRQ */
+#define BITM_SPI_STAT_TXIRQ                  (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  SPI Tx IRQ */
+#define BITM_SPI_STAT_TXUNDR                 (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  SPI Tx FIFO Underflow */
+#define BITM_SPI_STAT_TXDONE                 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  SPI Tx Done in Read Command Mode */
+#define BITM_SPI_STAT_TXEMPTY                (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  SPI Tx FIFO Empty Interrupt */
+#define BITM_SPI_STAT_XFRDONE                (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  SPI Transfer Completion */
+#define BITM_SPI_STAT_IRQ                    (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  SPI Interrupt Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_RX                               Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_RX_BYTE2                     8            /*  8-bit Receive Buffer, Used Only in DMA Modes */
+#define BITP_SPI_RX_BYTE1                     0            /*  8-bit Receive Buffer */
+#define BITM_SPI_RX_BYTE2                    (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t  ))    /*  8-bit Receive Buffer, Used Only in DMA Modes */
+#define BITM_SPI_RX_BYTE1                    (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  8-bit Receive Buffer */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_TX                               Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_TX_BYTE2                     8            /*  8-bit Transmit Buffer, Used Only in DMA Modes */
+#define BITP_SPI_TX_BYTE1                     0            /*  8-bit Transmit Buffer */
+#define BITM_SPI_TX_BYTE2                    (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t  ))    /*  8-bit Transmit Buffer, Used Only in DMA Modes */
+#define BITM_SPI_TX_BYTE1                    (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  8-bit Transmit Buffer */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_DIV                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_DIV_VALUE                    0            /*  SPI Clock Divider */
+#define BITM_SPI_DIV_VALUE                   (_ADI_MSK_3(0x0000003F,0x0000003FU, uint16_t  ))    /*  SPI Clock Divider */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_CTL                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_CTL_CSRST                   14            /*  Reset Mode for CS Error Bit */
+#define BITP_SPI_CTL_TFLUSH                  13            /*  SPI Tx FIFO Flush Enable */
+#define BITP_SPI_CTL_RFLUSH                  12            /*  SPI Rx FIFO Flush Enable */
+#define BITP_SPI_CTL_CON                     11            /*  Continuous Transfer Enable */
+#define BITP_SPI_CTL_LOOPBACK                10            /*  Loopback Enable */
+#define BITP_SPI_CTL_OEN                      9            /*  Slave MISO Output Enable */
+#define BITP_SPI_CTL_RXOF                     8            /*  Rx Overflow Overwrite Enable */
+#define BITP_SPI_CTL_ZEN                      7            /*  Transmit Zeros Enable */
+#define BITP_SPI_CTL_TIM                      6            /*  SPI Transfer and Interrupt Mode */
+#define BITP_SPI_CTL_LSB                      5            /*  LSB First Transfer Enable */
+#define BITP_SPI_CTL_WOM                      4            /*  SPI Wired-OR Mode */
+#define BITP_SPI_CTL_CPOL                     3            /*  Serial Clock Polarity */
+#define BITP_SPI_CTL_CPHA                     2            /*  Serial Clock Phase Mode */
+#define BITP_SPI_CTL_MASEN                    1            /*  Master Mode Enable */
+#define BITP_SPI_CTL_SPIEN                    0            /*  SPI Enable */
+#define BITM_SPI_CTL_CSRST                   (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Reset Mode for CS Error Bit */
+#define BITM_SPI_CTL_TFLUSH                  (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  SPI Tx FIFO Flush Enable */
+#define BITM_SPI_CTL_RFLUSH                  (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  SPI Rx FIFO Flush Enable */
+#define BITM_SPI_CTL_CON                     (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Continuous Transfer Enable */
+#define BITM_SPI_CTL_LOOPBACK                (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Loopback Enable */
+#define BITM_SPI_CTL_OEN                     (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Slave MISO Output Enable */
+#define BITM_SPI_CTL_RXOF                    (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Rx Overflow Overwrite Enable */
+#define BITM_SPI_CTL_ZEN                     (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Transmit Zeros Enable */
+#define BITM_SPI_CTL_TIM                     (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  SPI Transfer and Interrupt Mode */
+#define BITM_SPI_CTL_LSB                     (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  LSB First Transfer Enable */
+#define BITM_SPI_CTL_WOM                     (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  SPI Wired-OR Mode */
+#define BITM_SPI_CTL_CPOL                    (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Serial Clock Polarity */
+#define BITM_SPI_CTL_CPHA                    (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Serial Clock Phase Mode */
+#define BITM_SPI_CTL_MASEN                   (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Master Mode Enable */
+#define BITM_SPI_CTL_SPIEN                   (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  SPI Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_IEN                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_IEN_TXEMPTY                 14            /*  Tx FIFO Empty Interrupt Enable */
+#define BITP_SPI_IEN_XFRDONE                 13            /*  SPI Transfer Completion Interrupt Enable */
+#define BITP_SPI_IEN_TXDONE                  12            /*  SPI Transmit Done Interrupt Enable */
+#define BITP_SPI_IEN_RDY                     11            /*  Ready Signal Edge Interrupt Enable */
+#define BITP_SPI_IEN_RXOVR                   10            /*  Rx Overflow Interrupt Enable */
+#define BITP_SPI_IEN_TXUNDR                   9            /*  Tx Underflow Interrupt Enable */
+#define BITP_SPI_IEN_CS                       8            /*  Enable Interrupt on Every CS Edge in Slave CON Mode */
+#define BITP_SPI_IEN_IRQMODE                  0            /*  SPI IRQ Mode Bits */
+#define BITM_SPI_IEN_TXEMPTY                 (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Tx FIFO Empty Interrupt Enable */
+#define BITM_SPI_IEN_XFRDONE                 (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  SPI Transfer Completion Interrupt Enable */
+#define BITM_SPI_IEN_TXDONE                  (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  SPI Transmit Done Interrupt Enable */
+#define BITM_SPI_IEN_RDY                     (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Ready Signal Edge Interrupt Enable */
+#define BITM_SPI_IEN_RXOVR                   (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Rx Overflow Interrupt Enable */
+#define BITM_SPI_IEN_TXUNDR                  (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Tx Underflow Interrupt Enable */
+#define BITM_SPI_IEN_CS                      (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Enable Interrupt on Every CS Edge in Slave CON Mode */
+#define BITM_SPI_IEN_IRQMODE                 (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t  ))    /*  SPI IRQ Mode Bits */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_CNT                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_CNT_FRAMECONT               15            /*  Continue Frame */
+#define BITP_SPI_CNT_VALUE                    0            /*  Transfer Byte Count */
+#define BITM_SPI_CNT_FRAMECONT               (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Continue Frame */
+#define BITM_SPI_CNT_VALUE                   (_ADI_MSK_3(0x00003FFF,0x00003FFFU, uint16_t  ))    /*  Transfer Byte Count */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_DMA                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_DMA_RXEN                     2            /*  Enable Receive DMA Request */
+#define BITP_SPI_DMA_TXEN                     1            /*  Enable Transmit DMA Request */
+#define BITP_SPI_DMA_EN                       0            /*  Enable DMA for Data Transfer */
+#define BITM_SPI_DMA_RXEN                    (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Enable Receive DMA Request */
+#define BITM_SPI_DMA_TXEN                    (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Enable Transmit DMA Request */
+#define BITM_SPI_DMA_EN                      (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Enable DMA for Data Transfer */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_FIFO_STAT                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_FIFO_STAT_RX                 8            /*  SPI Rx FIFO Dtatus */
+#define BITP_SPI_FIFO_STAT_TX                 0            /*  SPI Tx FIFO Status */
+#define BITM_SPI_FIFO_STAT_RX                (_ADI_MSK_3(0x00000F00,0x00000F00U, uint16_t  ))    /*  SPI Rx FIFO Dtatus */
+#define BITM_SPI_FIFO_STAT_TX                (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t  ))    /*  SPI Tx FIFO Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_RD_CTL                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_RD_CTL_THREEPIN              8            /*  Three Pin SPI Mode */
+#define BITP_SPI_RD_CTL_TXBYTES               2            /*  Transmit Byte Count - 1 (Read Command) */
+#define BITP_SPI_RD_CTL_OVERLAP               1            /*  Tx/Rx Overlap Mode */
+#define BITP_SPI_RD_CTL_CMDEN                 0            /*  Read Command Enable */
+#define BITM_SPI_RD_CTL_THREEPIN             (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Three Pin SPI Mode */
+#define BITM_SPI_RD_CTL_TXBYTES              (_ADI_MSK_3(0x0000003C,0x0000003CU, uint16_t  ))    /*  Transmit Byte Count - 1 (Read Command) */
+#define BITM_SPI_RD_CTL_OVERLAP              (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Tx/Rx Overlap Mode */
+#define BITM_SPI_RD_CTL_CMDEN                (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Read Command Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_FLOW_CTL                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_FLOW_CTL_RDBURSTSZ           6            /*  Read Data Burst Size - 1 */
+#define BITP_SPI_FLOW_CTL_RDYPOL              4            /*  Polarity of RDY/MISO Line */
+#define BITP_SPI_FLOW_CTL_MODE                0            /*  Flow Control Mode */
+#define BITM_SPI_FLOW_CTL_RDBURSTSZ          (_ADI_MSK_3(0x0000FFC0,0x0000FFC0U, uint16_t  ))    /*  Read Data Burst Size - 1 */
+#define BITM_SPI_FLOW_CTL_RDYPOL             (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Polarity of RDY/MISO Line */
+#define BITM_SPI_FLOW_CTL_MODE               (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t  ))    /*  Flow Control Mode */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_WAIT_TMR                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_WAIT_TMR_VALUE               0            /*  Wait Timer */
+#define BITM_SPI_WAIT_TMR_VALUE              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Wait Timer */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_CS_CTL                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_CS_CTL_SEL                   0            /*  Chip Select Control */
+#define BITM_SPI_CS_CTL_SEL                  (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t  ))    /*  Chip Select Control */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPI_CS_OVERRIDE                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPI_CS_OVERRIDE_CTL              0            /*  CS Override Control */
+#define BITM_SPI_CS_OVERRIDE_CTL             (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t  ))    /*  CS Override Control */
+
+
+/* ============================================================================================================================
+        
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        UART0
+   ============================================================================================================================ */
+#define REG_UART0_RX                         0x40005000            /*  UART0 Receive Buffer Register */
+#define REG_UART0_TX                         0x40005000            /*  UART0 Transmit Holding Register */
+#define REG_UART0_IEN                        0x40005004            /*  UART0 Interrupt Enable */
+#define REG_UART0_IIR                        0x40005008            /*  UART0 Interrupt ID */
+#define REG_UART0_LCR                        0x4000500C            /*  UART0 Line Control */
+#define REG_UART0_MCR                        0x40005010            /*  UART0 Modem Control */
+#define REG_UART0_LSR                        0x40005014            /*  UART0 Line Status */
+#define REG_UART0_MSR                        0x40005018            /*  UART0 Modem Status */
+#define REG_UART0_SCR                        0x4000501C            /*  UART0 Scratch Buffer */
+#define REG_UART0_FCR                        0x40005020            /*  UART0 FIFO Control */
+#define REG_UART0_FBR                        0x40005024            /*  UART0 Fractional Baud Rate */
+#define REG_UART0_DIV                        0x40005028            /*  UART0 Baud Rate Divider */
+#define REG_UART0_LCR2                       0x4000502C            /*  UART0 Second Line Control */
+#define REG_UART0_CTL                        0x40005030            /*  UART0 UART Control Register */
+#define REG_UART0_RFC                        0x40005034            /*  UART0 RX FIFO Byte Count */
+#define REG_UART0_TFC                        0x40005038            /*  UART0 TX FIFO Byte Count */
+#define REG_UART0_RSC                        0x4000503C            /*  UART0 RS485 Half-duplex Control */
+#define REG_UART0_ACR                        0x40005040            /*  UART0 Auto Baud Control */
+#define REG_UART0_ASRL                       0x40005044            /*  UART0 Auto Baud Status (Low) */
+#define REG_UART0_ASRH                       0x40005048            /*  UART0 Auto Baud Status (High) */
+
+/* ============================================================================================================================
+        UART1
+   ============================================================================================================================ */
+#define REG_UART1_RX                         0x40005400            /*  UART1 Receive Buffer Register */
+#define REG_UART1_TX                         0x40005400            /*  UART1 Transmit Holding Register */
+#define REG_UART1_IEN                        0x40005404            /*  UART1 Interrupt Enable */
+#define REG_UART1_IIR                        0x40005408            /*  UART1 Interrupt ID */
+#define REG_UART1_LCR                        0x4000540C            /*  UART1 Line Control */
+#define REG_UART1_MCR                        0x40005410            /*  UART1 Modem Control */
+#define REG_UART1_LSR                        0x40005414            /*  UART1 Line Status */
+#define REG_UART1_MSR                        0x40005418            /*  UART1 Modem Status */
+#define REG_UART1_SCR                        0x4000541C            /*  UART1 Scratch Buffer */
+#define REG_UART1_FCR                        0x40005420            /*  UART1 FIFO Control */
+#define REG_UART1_FBR                        0x40005424            /*  UART1 Fractional Baud Rate */
+#define REG_UART1_DIV                        0x40005428            /*  UART1 Baud Rate Divider */
+#define REG_UART1_LCR2                       0x4000542C            /*  UART1 Second Line Control */
+#define REG_UART1_CTL                        0x40005430            /*  UART1 UART Control Register */
+#define REG_UART1_RFC                        0x40005434            /*  UART1 RX FIFO Byte Count */
+#define REG_UART1_TFC                        0x40005438            /*  UART1 TX FIFO Byte Count */
+#define REG_UART1_RSC                        0x4000543C            /*  UART1 RS485 Half-duplex Control */
+#define REG_UART1_ACR                        0x40005440            /*  UART1 Auto Baud Control */
+#define REG_UART1_ASRL                       0x40005444            /*  UART1 Auto Baud Status (Low) */
+#define REG_UART1_ASRH                       0x40005448            /*  UART1 Auto Baud Status (High) */
+
+/* ============================================================================================================================
+        UART Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_RX                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_RX_RBR                      0            /*  Receive Buffer Register */
+#define BITM_UART_RX_RBR                     (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Receive Buffer Register */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_TX                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_TX_THR                      0            /*  Transmit Holding Register */
+#define BITM_UART_TX_THR                     (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Transmit Holding Register */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_IEN                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_IEN_EDMAR                   5            /*  DMA Requests in Receive Mode */
+#define BITP_UART_IEN_EDMAT                   4            /*  DMA Requests in Transmit Mode */
+#define BITP_UART_IEN_EDSSI                   3            /*  Modem Status Interrupt */
+#define BITP_UART_IEN_ELSI                    2            /*  Rx Status Interrupt */
+#define BITP_UART_IEN_ETBEI                   1            /*  Transmit Buffer Empty Interrupt */
+#define BITP_UART_IEN_ERBFI                   0            /*  Receive Buffer Full Interrupt */
+#define BITM_UART_IEN_EDMAR                  (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  DMA Requests in Receive Mode */
+#define BITM_UART_IEN_EDMAT                  (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  DMA Requests in Transmit Mode */
+#define BITM_UART_IEN_EDSSI                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Modem Status Interrupt */
+#define BITM_UART_IEN_ELSI                   (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Rx Status Interrupt */
+#define BITM_UART_IEN_ETBEI                  (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Transmit Buffer Empty Interrupt */
+#define BITM_UART_IEN_ERBFI                  (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Receive Buffer Full Interrupt */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_IIR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_IIR_FEND                    6            /*  FIFO Enabled */
+#define BITP_UART_IIR_STAT                    1            /*  Interrupt Status */
+#define BITP_UART_IIR_NIRQ                    0            /*  Interrupt Flag */
+#define BITM_UART_IIR_FEND                   (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t  ))    /*  FIFO Enabled */
+#define BITM_UART_IIR_STAT                   (_ADI_MSK_3(0x0000000E,0x0000000EU, uint16_t  ))    /*  Interrupt Status */
+#define BITM_UART_IIR_NIRQ                   (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Interrupt Flag */
+#define ENUM_UART_IIR_STAT_EDSSI             (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  STAT: Modem status interrupt (Read MSR register to clear) */
+#define ENUM_UART_IIR_STAT_ETBEI             (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  STAT: Transmit buffer empty interrupt (Write to Tx register or read IIR register to clear) */
+#define ENUM_UART_IIR_STAT_ERBFI             (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  STAT: Receive buffer full interrupt (Read Rx register to clear) */
+#define ENUM_UART_IIR_STAT_RLSI              (_ADI_MSK_3(0x00000006,0x00000006U, uint16_t  ))    /*  STAT: Receive line status interrupt (Read LSR register to clear) */
+#define ENUM_UART_IIR_STAT_RFTOI             (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t  ))    /*  STAT: Receive FIFO time-out interrupt (Read Rx register to clear) */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_LCR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_LCR_BRK                     6            /*  Set Break */
+#define BITP_UART_LCR_SP                      5            /*  Stick Parity */
+#define BITP_UART_LCR_EPS                     4            /*  Parity Select */
+#define BITP_UART_LCR_PEN                     3            /*  Parity Enable */
+#define BITP_UART_LCR_STOP                    2            /*  Stop Bit */
+#define BITP_UART_LCR_WLS                     0            /*  Word Length Select */
+#define BITM_UART_LCR_BRK                    (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Set Break */
+#define BITM_UART_LCR_SP                     (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Stick Parity */
+#define BITM_UART_LCR_EPS                    (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Parity Select */
+#define BITM_UART_LCR_PEN                    (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Parity Enable */
+#define BITM_UART_LCR_STOP                   (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Stop Bit */
+#define BITM_UART_LCR_WLS                    (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t  ))    /*  Word Length Select */
+#define ENUM_UART_LCR_PAR_NOTFORCED          (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  SP: Parity will not be forced based on Parity Select and Parity Enable bits. */
+#define ENUM_UART_LCR_PAR_FORCED             (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  SP: Parity forced based on Parity Select and Parity Enable bits. */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_MCR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_MCR_LOOPBACK                4            /*  Loopback Mode */
+#define BITP_UART_MCR_OUT2                    3            /*  Output 2 */
+#define BITP_UART_MCR_OUT1                    2            /*  Output 1 */
+#define BITP_UART_MCR_RTS                     1            /*  Request to Send */
+#define BITP_UART_MCR_DTR                     0            /*  Data Terminal Ready */
+#define BITM_UART_MCR_LOOPBACK               (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Loopback Mode */
+#define BITM_UART_MCR_OUT2                   (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Output 2 */
+#define BITM_UART_MCR_OUT1                   (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Output 1 */
+#define BITM_UART_MCR_RTS                    (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Request to Send */
+#define BITM_UART_MCR_DTR                    (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Data Terminal Ready */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_LSR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_LSR_FIFOERR                 7            /*  Rx FIFO Parity Error/Frame Error/Break Indication */
+#define BITP_UART_LSR_TEMT                    6            /*  Transmit and Shift Register Empty Status */
+#define BITP_UART_LSR_THRE                    5            /*  Transmit Register Empty */
+#define BITP_UART_LSR_BI                      4            /*  Break Indicator */
+#define BITP_UART_LSR_FE                      3            /*  Framing Error */
+#define BITP_UART_LSR_PE                      2            /*  Parity Error */
+#define BITP_UART_LSR_OE                      1            /*  Overrun Error */
+#define BITP_UART_LSR_DR                      0            /*  Data Ready */
+#define BITM_UART_LSR_FIFOERR                (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Rx FIFO Parity Error/Frame Error/Break Indication */
+#define BITM_UART_LSR_TEMT                   (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Transmit and Shift Register Empty Status */
+#define BITM_UART_LSR_THRE                   (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Transmit Register Empty */
+#define BITM_UART_LSR_BI                     (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Break Indicator */
+#define BITM_UART_LSR_FE                     (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Framing Error */
+#define BITM_UART_LSR_PE                     (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Parity Error */
+#define BITM_UART_LSR_OE                     (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Overrun Error */
+#define BITM_UART_LSR_DR                     (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Data Ready */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_MSR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_MSR_DCD                     7            /*  Data Carrier Detect */
+#define BITP_UART_MSR_RI                      6            /*  Ring Indicator */
+#define BITP_UART_MSR_DSR                     5            /*  Data Set Ready */
+#define BITP_UART_MSR_CTS                     4            /*  Clear to Send */
+#define BITP_UART_MSR_DDCD                    3            /*  Delta DCD */
+#define BITP_UART_MSR_TERI                    2            /*  Trailing Edge RI */
+#define BITP_UART_MSR_DDSR                    1            /*  Delta DSR */
+#define BITP_UART_MSR_DCTS                    0            /*  Delta CTS */
+#define BITM_UART_MSR_DCD                    (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Data Carrier Detect */
+#define BITM_UART_MSR_RI                     (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Ring Indicator */
+#define BITM_UART_MSR_DSR                    (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Data Set Ready */
+#define BITM_UART_MSR_CTS                    (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Clear to Send */
+#define BITM_UART_MSR_DDCD                   (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Delta DCD */
+#define BITM_UART_MSR_TERI                   (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Trailing Edge RI */
+#define BITM_UART_MSR_DDSR                   (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Delta DSR */
+#define BITM_UART_MSR_DCTS                   (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Delta CTS */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_SCR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_SCR_SCR                     0            /*  Scratch */
+#define BITM_UART_SCR_SCR                    (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Scratch */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_FCR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_FCR_RFTRIG                  6            /*  Rx FIFO Trigger Level */
+#define BITP_UART_FCR_FDMAMD                  3            /*  FIFO DMA Mode */
+#define BITP_UART_FCR_TFCLR                   2            /*  Clear Tx FIFO */
+#define BITP_UART_FCR_RFCLR                   1            /*  Clear Rx FIFO */
+#define BITP_UART_FCR_FIFOEN                  0            /*  FIFO Enable as to Work in 16550 Mode */
+#define BITM_UART_FCR_RFTRIG                 (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t  ))    /*  Rx FIFO Trigger Level */
+#define BITM_UART_FCR_FDMAMD                 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  FIFO DMA Mode */
+#define BITM_UART_FCR_TFCLR                  (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Clear Tx FIFO */
+#define BITM_UART_FCR_RFCLR                  (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Clear Rx FIFO */
+#define BITM_UART_FCR_FIFOEN                 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  FIFO Enable as to Work in 16550 Mode */
+#define ENUM_UART_FCR_MODE0                  (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  FDMAMD: In DMA mode 0, RX DMA request will be asserted whenever there's data in RBR or RX FIFO and de-assert whenever RBR or RX FIFO is empty; TX DMA request will be asserted whenever THR or TX FIFO is empty and de-assert whenever data written to. */
+#define ENUM_UART_FCR_MODE1                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  FDMAMD: in DMA mode 1, RX DMA request will be asserted whenever RX FIFO trig level or time out reached and de-assert thereafter when RX FIFO is empty; TX DMA request will be asserted whenever TX FIFO is empty and de-assert thereafter when TX FIFO is completely filled up full. */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_FBR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_FBR_FBEN                   15            /*  Fractional Baud Rate Generator Enable */
+#define BITP_UART_FBR_DIVM                   11            /*  Fractional Baud Rate M Divide Bits 1 to 3 */
+#define BITP_UART_FBR_DIVN                    0            /*  Fractional Baud Rate N Divide Bits 0 to 2047 */
+#define BITM_UART_FBR_FBEN                   (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Fractional Baud Rate Generator Enable */
+#define BITM_UART_FBR_DIVM                   (_ADI_MSK_3(0x00001800,0x00001800U, uint16_t  ))    /*  Fractional Baud Rate M Divide Bits 1 to 3 */
+#define BITM_UART_FBR_DIVN                   (_ADI_MSK_3(0x000007FF,0x000007FFU, uint16_t  ))    /*  Fractional Baud Rate N Divide Bits 0 to 2047 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_DIV                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_DIV_DIV                     0            /*  Baud Rate Divider */
+#define BITM_UART_DIV_DIV                    (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Baud Rate Divider */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_LCR2                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_LCR2_OSR                    0            /*  Over Sample Rate */
+#define BITM_UART_LCR2_OSR                   (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t  ))    /*  Over Sample Rate */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_CTL                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_CTL_REV                     8            /*  UART Revision ID */
+#define BITP_UART_CTL_RXINV                   4            /*  Invert Receiver Line */
+#define BITP_UART_CTL_FORCECLK                1            /*  Force UCLK on */
+#define BITM_UART_CTL_REV                    (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t  ))    /*  UART Revision ID */
+#define BITM_UART_CTL_RXINV                  (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Invert Receiver Line */
+#define BITM_UART_CTL_FORCECLK               (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Force UCLK on */
+#define ENUM_UART_CTL_NOTINV_RX              (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  RXINV: Don't invert receiver line (idling high). */
+#define ENUM_UART_CTL_INV_RX                 (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  RXINV: Invert receiver line (idling low). */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_RFC                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_RFC_RFC                     0            /*  Current Rx FIFO Data Bytes */
+#define BITM_UART_RFC_RFC                    (_ADI_MSK_3(0x0000001F,0x0000001FU, uint16_t  ))    /*  Current Rx FIFO Data Bytes */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_TFC                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_TFC_TFC                     0            /*  Current Tx FIFO Data Bytes */
+#define BITM_UART_TFC_TFC                    (_ADI_MSK_3(0x0000001F,0x0000001FU, uint16_t  ))    /*  Current Tx FIFO Data Bytes */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_RSC                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_RSC_DISTX                   3            /*  Hold off Tx When Receiving */
+#define BITP_UART_RSC_DISRX                   2            /*  Disable Rx When Transmitting */
+#define BITP_UART_RSC_OENSP                   1            /*  SOUT_EN De-assert Before Full Stop Bit(s) */
+#define BITP_UART_RSC_OENP                    0            /*  SOUT_EN Polarity */
+#define BITM_UART_RSC_DISTX                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Hold off Tx When Receiving */
+#define BITM_UART_RSC_DISRX                  (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Disable Rx When Transmitting */
+#define BITM_UART_RSC_OENSP                  (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  SOUT_EN De-assert Before Full Stop Bit(s) */
+#define BITM_UART_RSC_OENP                   (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  SOUT_EN Polarity */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_ACR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_ACR_EEC                     8            /*  Ending Edge Count */
+#define BITP_UART_ACR_SEC                     4            /*  Starting Edge Count */
+#define BITP_UART_ACR_TOIEN                   2            /*  Enable Time-out Interrupt */
+#define BITP_UART_ACR_DNIEN                   1            /*  Enable Done Interrupt */
+#define BITP_UART_ACR_ABE                     0            /*  Auto Baud Enable */
+#define BITM_UART_ACR_EEC                    (_ADI_MSK_3(0x00000F00,0x00000F00U, uint16_t  ))    /*  Ending Edge Count */
+#define BITM_UART_ACR_SEC                    (_ADI_MSK_3(0x00000070,0x00000070U, uint16_t  ))    /*  Starting Edge Count */
+#define BITM_UART_ACR_TOIEN                  (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Enable Time-out Interrupt */
+#define BITM_UART_ACR_DNIEN                  (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Enable Done Interrupt */
+#define BITM_UART_ACR_ABE                    (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Auto Baud Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_ASRL                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_ASRL_CNT                    4            /*  Auto Baud Counter Value */
+#define BITP_UART_ASRL_NEETO                  3            /*  Timed Out Due to No Valid Ending Edge Found */
+#define BITP_UART_ASRL_NSETO                  2            /*  Timed Out Due to No Valid Start Edge Found */
+#define BITP_UART_ASRL_BRKTO                  1            /*  Timed Out Due to Long Time Break Condition */
+#define BITP_UART_ASRL_DONE                   0            /*  Auto Baud Done Successfully */
+#define BITM_UART_ASRL_CNT                   (_ADI_MSK_3(0x0000FFF0,0x0000FFF0U, uint16_t  ))    /*  Auto Baud Counter Value */
+#define BITM_UART_ASRL_NEETO                 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Timed Out Due to No Valid Ending Edge Found */
+#define BITM_UART_ASRL_NSETO                 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Timed Out Due to No Valid Start Edge Found */
+#define BITM_UART_ASRL_BRKTO                 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Timed Out Due to Long Time Break Condition */
+#define BITM_UART_ASRL_DONE                  (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Auto Baud Done Successfully */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          UART_ASRH                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_UART_ASRH_CNT                    0            /*  Auto Baud Counter Value */
+#define BITM_UART_ASRH_CNT                   (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Auto Baud Counter Value */
+
+
+/* ============================================================================================================================
+        Beeper Driver
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        BEEP0
+   ============================================================================================================================ */
+#define REG_BEEP0_CFG                        0x40005C00            /*  BEEP0 Beeper Configuration */
+#define REG_BEEP0_STAT                       0x40005C04            /*  BEEP0 Beeper Status */
+#define REG_BEEP0_TONEA                      0x40005C08            /*  BEEP0 Tone A Data */
+#define REG_BEEP0_TONEB                      0x40005C0C            /*  BEEP0 Tone B Data */
+
+/* ============================================================================================================================
+        BEEP Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          BEEP_CFG                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_BEEP_CFG_SEQATENDIRQ            15            /*  Sequence End IRQ */
+#define BITP_BEEP_CFG_SEQNEARENDIRQ          14            /*  Sequence 1 Cycle from End IRQ */
+#define BITP_BEEP_CFG_BENDIRQ                13            /*  Tone B End IRQ */
+#define BITP_BEEP_CFG_BSTARTIRQ              12            /*  Tone B Start IRQ */
+#define BITP_BEEP_CFG_AENDIRQ                11            /*  Tone A End IRQ */
+#define BITP_BEEP_CFG_ASTARTIRQ              10            /*  Tone A Start IRQ */
+#define BITP_BEEP_CFG_EN                      8            /*  Beeper Enable */
+#define BITP_BEEP_CFG_SEQREPEAT               0            /*  Beeper Sequence Repeat Value */
+#define BITM_BEEP_CFG_SEQATENDIRQ            (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Sequence End IRQ */
+#define BITM_BEEP_CFG_SEQNEARENDIRQ          (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Sequence 1 Cycle from End IRQ */
+#define BITM_BEEP_CFG_BENDIRQ                (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Tone B End IRQ */
+#define BITM_BEEP_CFG_BSTARTIRQ              (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Tone B Start IRQ */
+#define BITM_BEEP_CFG_AENDIRQ                (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Tone A End IRQ */
+#define BITM_BEEP_CFG_ASTARTIRQ              (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Tone A Start IRQ */
+#define BITM_BEEP_CFG_EN                     (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Beeper Enable */
+#define BITM_BEEP_CFG_SEQREPEAT              (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Beeper Sequence Repeat Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          BEEP_STAT                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_BEEP_STAT_SEQENDED              15            /*  Sequencer Has Ended */
+#define BITP_BEEP_STAT_SEQNEAREND            14            /*  Sequencer Last Tone-pair Has Started */
+#define BITP_BEEP_STAT_BENDED                13            /*  Tone B Has Ended */
+#define BITP_BEEP_STAT_BSTARTED              12            /*  Tone B Has Started */
+#define BITP_BEEP_STAT_AENDED                11            /*  Tone A Has Ended */
+#define BITP_BEEP_STAT_ASTARTED              10            /*  Tone A Has Started */
+#define BITP_BEEP_STAT_BUSY                   8            /*  Beeper is Busy */
+#define BITP_BEEP_STAT_SEQREMAIN              0            /*  Remaining Tone-pair Iterations to Play in Sequence Mode */
+#define BITM_BEEP_STAT_SEQENDED              (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Sequencer Has Ended */
+#define BITM_BEEP_STAT_SEQNEAREND            (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Sequencer Last Tone-pair Has Started */
+#define BITM_BEEP_STAT_BENDED                (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Tone B Has Ended */
+#define BITM_BEEP_STAT_BSTARTED              (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Tone B Has Started */
+#define BITM_BEEP_STAT_AENDED                (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Tone A Has Ended */
+#define BITM_BEEP_STAT_ASTARTED              (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Tone A Has Started */
+#define BITM_BEEP_STAT_BUSY                  (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Beeper is Busy */
+#define BITM_BEEP_STAT_SEQREMAIN             (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Remaining Tone-pair Iterations to Play in Sequence Mode */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          BEEP_TONEA                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_BEEP_TONEA_DIS                  15            /*  Output Disable */
+#define BITP_BEEP_TONEA_FREQ                  8            /*  Tone Frequency */
+#define BITP_BEEP_TONEA_DUR                   0            /*  Tone Duration */
+#define BITM_BEEP_TONEA_DIS                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Output Disable */
+#define BITM_BEEP_TONEA_FREQ                 (_ADI_MSK_3(0x00007F00,0x00007F00U, uint16_t  ))    /*  Tone Frequency */
+#define BITM_BEEP_TONEA_DUR                  (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Tone Duration */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          BEEP_TONEB                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_BEEP_TONEB_DIS                  15            /*  Output Disable */
+#define BITP_BEEP_TONEB_FREQ                  8            /*  Tone Frequency */
+#define BITP_BEEP_TONEB_DUR                   0            /*  Tone Duration */
+#define BITM_BEEP_TONEB_DIS                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Output Disable */
+#define BITM_BEEP_TONEB_FREQ                 (_ADI_MSK_3(0x00007F00,0x00007F00U, uint16_t  ))    /*  Tone Frequency */
+#define BITM_BEEP_TONEB_DUR                  (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Tone Duration */
+
+
+/* ============================================================================================================================
+        
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        ADC0
+   ============================================================================================================================ */
+#define REG_ADC0_CFG                         0x40007000            /*  ADC0 ADC Configuration */
+#define REG_ADC0_PWRUP                       0x40007004            /*  ADC0 ADC Power-up Time */
+#define REG_ADC0_CAL_WORD                    0x40007008            /*  ADC0 Calibration Word */
+#define REG_ADC0_CNV_CFG                     0x4000700C            /*  ADC0 ADC Conversion Configuration */
+#define REG_ADC0_CNV_TIME                    0x40007010            /*  ADC0 ADC Conversion Time */
+#define REG_ADC0_AVG_CFG                     0x40007014            /*  ADC0 Averaging Configuration */
+#define REG_ADC0_IRQ_EN                      0x40007020            /*  ADC0 Interrupt Enable */
+#define REG_ADC0_STAT                        0x40007024            /*  ADC0 ADC Status */
+#define REG_ADC0_OVF                         0x40007028            /*  ADC0 Overflow of Output Registers */
+#define REG_ADC0_ALERT                       0x4000702C            /*  ADC0 Alert Indication */
+#define REG_ADC0_CH0_OUT                     0x40007030            /*  ADC0 Conversion Result Channel 0 */
+#define REG_ADC0_CH1_OUT                     0x40007034            /*  ADC0 Conversion Result Channel 1 */
+#define REG_ADC0_CH2_OUT                     0x40007038            /*  ADC0 Conversion Result Channel 2 */
+#define REG_ADC0_CH3_OUT                     0x4000703C            /*  ADC0 Conversion Result Channel 3 */
+#define REG_ADC0_CH4_OUT                     0x40007040            /*  ADC0 Conversion Result Channel 4 */
+#define REG_ADC0_CH5_OUT                     0x40007044            /*  ADC0 Conversion Result Channel 5 */
+#define REG_ADC0_CH6_OUT                     0x40007048            /*  ADC0 Conversion Result Channel 6 */
+#define REG_ADC0_CH7_OUT                     0x4000704C            /*  ADC0 Conversion Result Channel 7 */
+#define REG_ADC0_BAT_OUT                     0x40007050            /*  ADC0 Battery Monitoring Result */
+#define REG_ADC0_TMP_OUT                     0x40007054            /*  ADC0 Temperature Result */
+#define REG_ADC0_TMP2_OUT                    0x40007058            /*  ADC0 Temperature Result 2 */
+#define REG_ADC0_DMA_OUT                     0x4000705C            /*  ADC0 DMA Output Register */
+#define REG_ADC0_LIM0_LO                     0x40007060            /*  ADC0 Channel 0 Low Limit */
+#define REG_ADC0_LIM0_HI                     0x40007064            /*  ADC0 Channel 0 High Limit */
+#define REG_ADC0_HYS0                        0x40007068            /*  ADC0 Channel 0 Hysteresis */
+#define REG_ADC0_LIM1_LO                     0x40007070            /*  ADC0 Channel 1 Low Limit */
+#define REG_ADC0_LIM1_HI                     0x40007074            /*  ADC0 Channel 1 High Limit */
+#define REG_ADC0_HYS1                        0x40007078            /*  ADC0 Channel 1 Hysteresis */
+#define REG_ADC0_LIM2_LO                     0x40007080            /*  ADC0 Channel 2 Low Limit */
+#define REG_ADC0_LIM2_HI                     0x40007084            /*  ADC0 Channel 2 High Limit */
+#define REG_ADC0_HYS2                        0x40007088            /*  ADC0 Channel 2 Hysteresis */
+#define REG_ADC0_LIM3_LO                     0x40007090            /*  ADC0 Channel 3 Low Limit */
+#define REG_ADC0_LIM3_HI                     0x40007094            /*  ADC0 Channel 3 High Limit */
+#define REG_ADC0_HYS3                        0x40007098            /*  ADC0 Channel 3 Hysteresis */
+#define REG_ADC0_CFG1                        0x400070C0            /*  ADC0 Reference Buffer Low Power Mode */
+
+/* ============================================================================================================================
+        ADC Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CFG                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CFG_VREFVBAT_DEL            10            /*  Set to 1 after minimum delay of 700 us from VREFBAT field being set to 1 */
+#define BITP_ADC_CFG_FAST_DISCH               9            /*  For fast switchover of Vref from 2.5 V to 1.25 V */
+#define BITP_ADC_CFG_TMPEN                    8            /*  To power up temperature sensor */
+#define BITP_ADC_CFG_SINKEN                   7            /*  To enable additional 50 uA sink current capability @1.25 V, 100 uA current capability @2.5 V */
+#define BITP_ADC_CFG_RST                      6            /*  Resets internal buffers and registers when high */
+#define BITP_ADC_CFG_STARTCAL                 5            /*  To start a new offset calibration cycle */
+#define BITP_ADC_CFG_EN                       4            /*  To enable ADC subsystem */
+#define BITP_ADC_CFG_VREFVBAT                 3            /*  VRef VBAT */
+#define BITP_ADC_CFG_REFBUFEN                 2            /*  To enable internal reference buffer */
+#define BITP_ADC_CFG_VREFSEL                  1            /*  To select Vref as 1.25 V or 2.5 V */
+#define BITP_ADC_CFG_PWRUP                    0            /*  Powering up ADC */
+#define BITM_ADC_CFG_VREFVBAT_DEL            (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Set to 1 after minimum delay of 700 us from VREFBAT field being set to 1 */
+#define BITM_ADC_CFG_FAST_DISCH              (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  For fast switchover of Vref from 2.5 V to 1.25 V */
+#define BITM_ADC_CFG_TMPEN                   (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  To power up temperature sensor */
+#define BITM_ADC_CFG_SINKEN                  (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  To enable additional 50 uA sink current capability @1.25 V, 100 uA current capability @2.5 V */
+#define BITM_ADC_CFG_RST                     (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Resets internal buffers and registers when high */
+#define BITM_ADC_CFG_STARTCAL                (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  To start a new offset calibration cycle */
+#define BITM_ADC_CFG_EN                      (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  To enable ADC subsystem */
+#define BITM_ADC_CFG_VREFVBAT                (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  VRef VBAT */
+#define BITM_ADC_CFG_REFBUFEN                (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  To enable internal reference buffer */
+#define BITM_ADC_CFG_VREFSEL                 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  To select Vref as 1.25 V or 2.5 V */
+#define BITM_ADC_CFG_PWRUP                   (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Powering up ADC */
+#define ENUM_ADC_CFG_EXT_REF                 (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  REFBUFEN: External reference is used */
+#define ENUM_ADC_CFG_BUF_REF                 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  REFBUFEN: Reference buffer is enabled */
+#define ENUM_ADC_CFG_V_2P5                   (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  VREFSEL: Vref = 2.5 V */
+#define ENUM_ADC_CFG_V_1P25                  (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  VREFSEL: Vref = 1.25 V */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_PWRUP                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_PWRUP_WAIT                   0            /*  Program this count to generate 20us wait time with respect to the PCLK frequency */
+#define BITM_ADC_PWRUP_WAIT                  (_ADI_MSK_3(0x000007FF,0x000007FFU, uint16_t  ))    /*  Program this count to generate 20us wait time with respect to the PCLK frequency */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CAL_WORD                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CAL_WORD_VALUE               0            /*  Offset calibration word */
+#define BITM_ADC_CAL_WORD_VALUE              (_ADI_MSK_3(0x0000007F,0x0000007FU, uint16_t  ))    /*  Offset calibration word */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CNV_CFG                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CNV_CFG_MULTI               15            /*  Set to start multiple conversions */
+#define BITP_ADC_CNV_CFG_SINGLE              14            /*  Set to start single conversion */
+#define BITP_ADC_CNV_CFG_DMAEN               13            /*  To enable DMA channel */
+#define BITP_ADC_CNV_CFG_AUTOMODE            12            /*  To enable auto mode */
+#define BITP_ADC_CNV_CFG_TMP2                10            /*  To select temperature measurement 2 */
+#define BITP_ADC_CNV_CFG_TMP                  9            /*  To select temperature measurement 1 */
+#define BITP_ADC_CNV_CFG_BAT                  8            /*  To enable battery monitoring */
+#define BITP_ADC_CNV_CFG_SEL                  0            /*  To select channel(s) to convert */
+#define BITM_ADC_CNV_CFG_MULTI               (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Set to start multiple conversions */
+#define BITM_ADC_CNV_CFG_SINGLE              (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Set to start single conversion */
+#define BITM_ADC_CNV_CFG_DMAEN               (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  To enable DMA channel */
+#define BITM_ADC_CNV_CFG_AUTOMODE            (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  To enable auto mode */
+#define BITM_ADC_CNV_CFG_TMP2                (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  To select temperature measurement 2 */
+#define BITM_ADC_CNV_CFG_TMP                 (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  To select temperature measurement 1 */
+#define BITM_ADC_CNV_CFG_BAT                 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  To enable battery monitoring */
+#define BITM_ADC_CNV_CFG_SEL                 (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  To select channel(s) to convert */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CNV_TIME                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CNV_TIME_DLY                 8            /*  Delay between two consecutive conversions in terms of number of ACLK cycles */
+#define BITP_ADC_CNV_TIME_SAMPTIME            0            /*  Number of clock cycles (ACLK) required for sampling */
+#define BITM_ADC_CNV_TIME_DLY                (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t  ))    /*  Delay between two consecutive conversions in terms of number of ACLK cycles */
+#define BITM_ADC_CNV_TIME_SAMPTIME           (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Number of clock cycles (ACLK) required for sampling */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_AVG_CFG                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_AVG_CFG_EN                  15            /*  To enable averaging on Channels enabled in enable register */
+#define BITP_ADC_AVG_CFG_OS                  14            /*  Enable oversampling */
+#define BITP_ADC_AVG_CFG_FACTOR               0            /*  Program averaging factor for averaging enabled channels (1-256) */
+#define BITM_ADC_AVG_CFG_EN                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  To enable averaging on Channels enabled in enable register */
+#define BITM_ADC_AVG_CFG_OS                  (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Enable oversampling */
+#define BITM_ADC_AVG_CFG_FACTOR              (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t  ))    /*  Program averaging factor for averaging enabled channels (1-256) */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_IRQ_EN                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_IRQ_EN_RDY                  13            /*  Set to enable interrupt when ADC is ready to convert */
+#define BITP_ADC_IRQ_EN_ALERT                12            /*  Set to enable interrupt on crossing lower or higher limit */
+#define BITP_ADC_IRQ_EN_OVF                  11            /*  Set to enable interrupt in case of overflow */
+#define BITP_ADC_IRQ_EN_CALDONE              10            /*  Set it to enable interrupt for calibration done */
+#define BITP_ADC_IRQ_EN_CNVDONE               0            /*  Set it to enable interrupt after conversion is done */
+#define BITM_ADC_IRQ_EN_RDY                  (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t  ))    /*  Set to enable interrupt when ADC is ready to convert */
+#define BITM_ADC_IRQ_EN_ALERT                (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t  ))    /*  Set to enable interrupt on crossing lower or higher limit */
+#define BITM_ADC_IRQ_EN_OVF                  (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t  ))    /*  Set to enable interrupt in case of overflow */
+#define BITM_ADC_IRQ_EN_CALDONE              (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Set it to enable interrupt for calibration done */
+#define BITM_ADC_IRQ_EN_CNVDONE              (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Set it to enable interrupt after conversion is done */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_STAT                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_STAT_RDY                    15            /*  Indicates ADC is ready to start converting, when using external reference buffer */
+#define BITP_ADC_STAT_CALDONE                14            /*  Indicates calibration is done */
+#define BITP_ADC_STAT_TMP2DONE               10            /*  Indicates conversion is done for temperature sensing 2 */
+#define BITP_ADC_STAT_TMPDONE                 9            /*  Indicates conversion is done for temperature sensing */
+#define BITP_ADC_STAT_BATDONE                 8            /*  Indicates conversion done for battery monitoring */
+#define BITP_ADC_STAT_DONE7                   7            /*  Indicates conversion done on Channel 7 */
+#define BITP_ADC_STAT_DONE6                   6            /*  Indicates conversion done on Channel 6 */
+#define BITP_ADC_STAT_DONE5                   5            /*  Indicates conversion done on Channel 5 */
+#define BITP_ADC_STAT_DONE4                   4            /*  Indicates conversion done on Channel 4 */
+#define BITP_ADC_STAT_DONE3                   3            /*  Indicates conversion done on Channel 3 */
+#define BITP_ADC_STAT_DONE2                   2            /*  Indicates conversion done on Channel 2 */
+#define BITP_ADC_STAT_DONE1                   1            /*  Indicates conversion done on Channel 1 */
+#define BITP_ADC_STAT_DONE0                   0            /*  Indicates conversion done on Channel 0 */
+#define BITM_ADC_STAT_RDY                    (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  Indicates ADC is ready to start converting, when using external reference buffer */
+#define BITM_ADC_STAT_CALDONE                (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t  ))    /*  Indicates calibration is done */
+#define BITM_ADC_STAT_TMP2DONE               (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Indicates conversion is done for temperature sensing 2 */
+#define BITM_ADC_STAT_TMPDONE                (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Indicates conversion is done for temperature sensing */
+#define BITM_ADC_STAT_BATDONE                (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Indicates conversion done for battery monitoring */
+#define BITM_ADC_STAT_DONE7                  (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Indicates conversion done on Channel 7 */
+#define BITM_ADC_STAT_DONE6                  (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Indicates conversion done on Channel 6 */
+#define BITM_ADC_STAT_DONE5                  (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Indicates conversion done on Channel 5 */
+#define BITM_ADC_STAT_DONE4                  (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Indicates conversion done on Channel 4 */
+#define BITM_ADC_STAT_DONE3                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Indicates conversion done on Channel 3 */
+#define BITM_ADC_STAT_DONE2                  (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Indicates conversion done on Channel 2 */
+#define BITM_ADC_STAT_DONE1                  (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Indicates conversion done on Channel 1 */
+#define BITM_ADC_STAT_DONE0                  (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Indicates conversion done on Channel 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_OVF                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_OVF_TMP2                    10            /*  Indicates overflow in temperature 2 output register */
+#define BITP_ADC_OVF_TMP                      9            /*  Indicates overflow in temperature output register */
+#define BITP_ADC_OVF_BAT                      8            /*  Indicates overflow in battery monitoring output register */
+#define BITP_ADC_OVF_CH7                      7            /*  Indicates overflow in channel 7 output register */
+#define BITP_ADC_OVF_CH6                      6            /*  Indicates overflow in channel 6 output register */
+#define BITP_ADC_OVF_CH5                      5            /*  Indicates overflow in channel 5 output register */
+#define BITP_ADC_OVF_CH4                      4            /*  Indicates overflow in channel 4 output register */
+#define BITP_ADC_OVF_CH3                      3            /*  Indicates overflow in channel 3 output register */
+#define BITP_ADC_OVF_CH2                      2            /*  Indicates overflow in channel 2 output register */
+#define BITP_ADC_OVF_CH1                      1            /*  Indicates overflow in channel 1 output register */
+#define BITP_ADC_OVF_CH0                      0            /*  Indicates overflow in channel 0 output register */
+#define BITM_ADC_OVF_TMP2                    (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t  ))    /*  Indicates overflow in temperature 2 output register */
+#define BITM_ADC_OVF_TMP                     (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t  ))    /*  Indicates overflow in temperature output register */
+#define BITM_ADC_OVF_BAT                     (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t  ))    /*  Indicates overflow in battery monitoring output register */
+#define BITM_ADC_OVF_CH7                     (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Indicates overflow in channel 7 output register */
+#define BITM_ADC_OVF_CH6                     (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Indicates overflow in channel 6 output register */
+#define BITM_ADC_OVF_CH5                     (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Indicates overflow in channel 5 output register */
+#define BITM_ADC_OVF_CH4                     (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Indicates overflow in channel 4 output register */
+#define BITM_ADC_OVF_CH3                     (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Indicates overflow in channel 3 output register */
+#define BITM_ADC_OVF_CH2                     (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Indicates overflow in channel 2 output register */
+#define BITM_ADC_OVF_CH1                     (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Indicates overflow in channel 1 output register */
+#define BITM_ADC_OVF_CH0                     (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Indicates overflow in channel 0 output register */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_ALERT                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_ALERT_LO3                    7            /*  Channel 3 Low alert status */
+#define BITP_ADC_ALERT_HI3                    6            /*  Channel 3 High alert status */
+#define BITP_ADC_ALERT_LO2                    5            /*  Channel 2 Low alert status */
+#define BITP_ADC_ALERT_HI2                    4            /*  Channel 2 High alert status */
+#define BITP_ADC_ALERT_LO1                    3            /*  Channel 1 Low alert status */
+#define BITP_ADC_ALERT_HI1                    2            /*  Channel 1 High alert status */
+#define BITP_ADC_ALERT_LO0                    1            /*  Channel 0 Low alert status */
+#define BITP_ADC_ALERT_HI0                    0            /*  Channel 0 High alert status */
+#define BITM_ADC_ALERT_LO3                   (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t  ))    /*  Channel 3 Low alert status */
+#define BITM_ADC_ALERT_HI3                   (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t  ))    /*  Channel 3 High alert status */
+#define BITM_ADC_ALERT_LO2                   (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t  ))    /*  Channel 2 Low alert status */
+#define BITM_ADC_ALERT_HI2                   (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t  ))    /*  Channel 2 High alert status */
+#define BITM_ADC_ALERT_LO1                   (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Channel 1 Low alert status */
+#define BITM_ADC_ALERT_HI1                   (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  Channel 1 High alert status */
+#define BITM_ADC_ALERT_LO0                   (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Channel 0 Low alert status */
+#define BITM_ADC_ALERT_HI0                   (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Channel 0 High alert status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CH0_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CH0_OUT_RESULT               0            /*  Conversion result of channel 0 is stored here */
+#define BITM_ADC_CH0_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion result of channel 0 is stored here */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CH1_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CH1_OUT_RESULT               0            /*  Conversion result of channel 1 is stored here */
+#define BITM_ADC_CH1_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion result of channel 1 is stored here */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CH2_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CH2_OUT_RESULT               0            /*  Conversion result of channel 2 is stored here */
+#define BITM_ADC_CH2_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion result of channel 2 is stored here */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CH3_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CH3_OUT_RESULT               0            /*  Conversion result of channel 3 is stored here */
+#define BITM_ADC_CH3_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion result of channel 3 is stored here */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CH4_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CH4_OUT_RESULT               0            /*  Conversion result of channel 4 is stored here */
+#define BITM_ADC_CH4_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion result of channel 4 is stored here */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CH5_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CH5_OUT_RESULT               0            /*  Conversion result of channel 5 is stored here */
+#define BITM_ADC_CH5_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion result of channel 5 is stored here */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CH6_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CH6_OUT_RESULT               0            /*  Conversion result of channel 6 is stored here */
+#define BITM_ADC_CH6_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion result of channel 6 is stored here */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CH7_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CH7_OUT_RESULT               0            /*  Conversion result of channel 7 is stored here */
+#define BITM_ADC_CH7_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion result of channel 7 is stored here */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_BAT_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_BAT_OUT_RESULT               0            /*  Conversion result of battery monitoring is stored here */
+#define BITM_ADC_BAT_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion result of battery monitoring is stored here */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_TMP_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_TMP_OUT_RESULT               0            /*  Conversion result of Temperature measurement 1 is stored here */
+#define BITM_ADC_TMP_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion result of Temperature measurement 1 is stored here */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_TMP2_OUT                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_TMP2_OUT_RESULT              0            /*  Conversion result of Temperature measurement 2 is stored here */
+#define BITM_ADC_TMP2_OUT_RESULT             (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Conversion result of Temperature measurement 2 is stored here */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_DMA_OUT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_DMA_OUT_RESULT               0            /*  Register to store conversion result for DMA */
+#define BITM_ADC_DMA_OUT_RESULT              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Register to store conversion result for DMA */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_LIM0_LO                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_LIM0_LO_EN                  15            /*  To enable low limit comparison on Channel 0 */
+#define BITP_ADC_LIM0_LO_VALUE                0            /*  Low limit value for channel 0 */
+#define BITM_ADC_LIM0_LO_EN                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  To enable low limit comparison on Channel 0 */
+#define BITM_ADC_LIM0_LO_VALUE               (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t  ))    /*  Low limit value for channel 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_LIM0_HI                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_LIM0_HI_EN                  15            /*  To enable high limit comparison on Channel 0 */
+#define BITP_ADC_LIM0_HI_VALUE                0            /*  High limit value for channel 0 */
+#define BITM_ADC_LIM0_HI_EN                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  To enable high limit comparison on Channel 0 */
+#define BITM_ADC_LIM0_HI_VALUE               (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t  ))    /*  High limit value for channel 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_HYS0                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_HYS0_EN                     15            /*  To enable hysteresis for comparison on Channel 0 */
+#define BITP_ADC_HYS0_MONCYC                 12            /*  Program number of conversion cycles to monitor channel 0 before raising alert */
+#define BITP_ADC_HYS0_VALUE                   0            /*  Hysteresis value for Channel 0 */
+#define BITM_ADC_HYS0_EN                     (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  To enable hysteresis for comparison on Channel 0 */
+#define BITM_ADC_HYS0_MONCYC                 (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t  ))    /*  Program number of conversion cycles to monitor channel 0 before raising alert */
+#define BITM_ADC_HYS0_VALUE                  (_ADI_MSK_3(0x000001FF,0x000001FFU, uint16_t  ))    /*  Hysteresis value for Channel 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_LIM1_LO                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_LIM1_LO_EN                  15            /*  To enable low limit comparison on Channel 1 */
+#define BITP_ADC_LIM1_LO_VALUE                0            /*  Low limit value for channel 1 */
+#define BITM_ADC_LIM1_LO_EN                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  To enable low limit comparison on Channel 1 */
+#define BITM_ADC_LIM1_LO_VALUE               (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t  ))    /*  Low limit value for channel 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_LIM1_HI                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_LIM1_HI_EN                  15            /*  To enable high limit comparison on Channel 1 */
+#define BITP_ADC_LIM1_HI_VALUE                0            /*  High limit value for channel 1 */
+#define BITM_ADC_LIM1_HI_EN                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  To enable high limit comparison on Channel 1 */
+#define BITM_ADC_LIM1_HI_VALUE               (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t  ))    /*  High limit value for channel 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_HYS1                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_HYS1_EN                     15            /*  To enable hysteresis for comparison on Channel 1 */
+#define BITP_ADC_HYS1_MONCYC                 12            /*  Program number of conversion cycles to monitor channel 1 before raising alert */
+#define BITP_ADC_HYS1_VALUE                   0            /*  Hysteresis value for Channel 1 */
+#define BITM_ADC_HYS1_EN                     (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  To enable hysteresis for comparison on Channel 1 */
+#define BITM_ADC_HYS1_MONCYC                 (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t  ))    /*  Program number of conversion cycles to monitor channel 1 before raising alert */
+#define BITM_ADC_HYS1_VALUE                  (_ADI_MSK_3(0x000001FF,0x000001FFU, uint16_t  ))    /*  Hysteresis value for Channel 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_LIM2_LO                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_LIM2_LO_EN                  15            /*  To enable low limit comparison on Channel 2 */
+#define BITP_ADC_LIM2_LO_VALUE                0            /*  Low limit value for channel 2 */
+#define BITM_ADC_LIM2_LO_EN                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  To enable low limit comparison on Channel 2 */
+#define BITM_ADC_LIM2_LO_VALUE               (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t  ))    /*  Low limit value for channel 2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_LIM2_HI                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_LIM2_HI_EN                  15            /*  To enable high limit comparison on Channel 2 */
+#define BITP_ADC_LIM2_HI_VALUE                0            /*  High limit value for channel 2 */
+#define BITM_ADC_LIM2_HI_EN                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  To enable high limit comparison on Channel 2 */
+#define BITM_ADC_LIM2_HI_VALUE               (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t  ))    /*  High limit value for channel 2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_HYS2                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_HYS2_EN                     15            /*  To enable hysteresis for comparison on Channel 2 */
+#define BITP_ADC_HYS2_MONCYC                 12            /*  Program number of conversion cycles to monitor channel 2 before raising alert */
+#define BITP_ADC_HYS2_VALUE                   0            /*  Hysteresis value for Channel 2 */
+#define BITM_ADC_HYS2_EN                     (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  To enable hysteresis for comparison on Channel 2 */
+#define BITM_ADC_HYS2_MONCYC                 (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t  ))    /*  Program number of conversion cycles to monitor channel 2 before raising alert */
+#define BITM_ADC_HYS2_VALUE                  (_ADI_MSK_3(0x000001FF,0x000001FFU, uint16_t  ))    /*  Hysteresis value for Channel 2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_LIM3_LO                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_LIM3_LO_EN                  15            /*  To enable low limit comparison on Channel 3 */
+#define BITP_ADC_LIM3_LO_VALUE                0            /*  Low limit value for channel 3 */
+#define BITM_ADC_LIM3_LO_EN                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  To enable low limit comparison on Channel 3 */
+#define BITM_ADC_LIM3_LO_VALUE               (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t  ))    /*  Low limit value for channel 3 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_LIM3_HI                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_LIM3_HI_EN                  15            /*  To enable high limit comparison on Channel 3 */
+#define BITP_ADC_LIM3_HI_VALUE                0            /*  High limit value for channel 3 */
+#define BITM_ADC_LIM3_HI_EN                  (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  To enable high limit comparison on Channel 3 */
+#define BITM_ADC_LIM3_HI_VALUE               (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t  ))    /*  High limit value for channel 3 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_HYS3                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_HYS3_EN                     15            /*  To enable hysteresis for comparison on Channel 3 */
+#define BITP_ADC_HYS3_MONCYC                 12            /*  Program number of conversion cycles to monitor channel 3 before raising alert */
+#define BITP_ADC_HYS3_VALUE                   0            /*  Hysteresis value for Channel 3 */
+#define BITM_ADC_HYS3_EN                     (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t  ))    /*  To enable hysteresis for comparison on Channel 3 */
+#define BITM_ADC_HYS3_MONCYC                 (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t  ))    /*  Program number of conversion cycles to monitor channel 3 before raising alert */
+#define BITM_ADC_HYS3_VALUE                  (_ADI_MSK_3(0x000001FF,0x000001FFU, uint16_t  ))    /*  Hysteresis value for Channel 3 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          ADC_CFG1                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_ADC_CFG1_RBUFLP                  0            /*  Enable low power mode for reference buffer */
+#define BITM_ADC_CFG1_RBUFLP                 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Enable low power mode for reference buffer */
+
+
+/* ============================================================================================================================
+        DMA
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        DMA0
+   ============================================================================================================================ */
+#define REG_DMA0_STAT                        0x40010000            /*  DMA0 DMA Status */
+#define REG_DMA0_CFG                         0x40010004            /*  DMA0 DMA Configuration */
+#define REG_DMA0_PDBPTR                      0x40010008            /*  DMA0 DMA Channel Primary Control Database Pointer */
+#define REG_DMA0_ADBPTR                      0x4001000C            /*  DMA0 DMA Channel Alternate Control Database Pointer */
+#define REG_DMA0_SWREQ                       0x40010014            /*  DMA0 DMA Channel Software Request */
+#define REG_DMA0_RMSK_SET                    0x40010020            /*  DMA0 DMA Channel Request Mask Set */
+#define REG_DMA0_RMSK_CLR                    0x40010024            /*  DMA0 DMA Channel Request Mask Clear */
+#define REG_DMA0_EN_SET                      0x40010028            /*  DMA0 DMA Channel Enable Set */
+#define REG_DMA0_EN_CLR                      0x4001002C            /*  DMA0 DMA Channel Enable Clear */
+#define REG_DMA0_ALT_SET                     0x40010030            /*  DMA0 DMA Channel Primary Alternate Set */
+#define REG_DMA0_ALT_CLR                     0x40010034            /*  DMA0 DMA Channel Primary Alternate Clear */
+#define REG_DMA0_PRI_SET                     0x40010038            /*  DMA0 DMA Channel Priority Set */
+#define REG_DMA0_PRI_CLR                     0x4001003C            /*  DMA0 DMA Channel Priority Clear */
+#define REG_DMA0_ERRCHNL_CLR                 0x40010048            /*  DMA0 DMA per Channel Error Clear */
+#define REG_DMA0_ERR_CLR                     0x4001004C            /*  DMA0 DMA Bus Error Clear */
+#define REG_DMA0_INVALIDDESC_CLR             0x40010050            /*  DMA0 DMA per Channel Invalid Descriptor Clear */
+#define REG_DMA0_BS_SET                      0x40010800            /*  DMA0 DMA Channel Bytes Swap Enable Set */
+#define REG_DMA0_BS_CLR                      0x40010804            /*  DMA0 DMA Channel Bytes Swap Enable Clear */
+#define REG_DMA0_SRCADDR_SET                 0x40010810            /*  DMA0 DMA Channel Source Address Decrement Enable Set */
+#define REG_DMA0_SRCADDR_CLR                 0x40010814            /*  DMA0 DMA Channel Source Address Decrement Enable Clear */
+#define REG_DMA0_DSTADDR_SET                 0x40010818            /*  DMA0 DMA Channel Destination Address Decrement Enable Set */
+#define REG_DMA0_DSTADDR_CLR                 0x4001081C            /*  DMA0 DMA Channel Destination Address Decrement Enable Clear */
+#define REG_DMA0_REVID                       0x40010FE0            /*  DMA0 DMA Controller Revision ID */
+
+/* ============================================================================================================================
+        DMA Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_STAT                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_STAT_CHANM1                 16            /*  Number of Available DMA Channels Minus 1 */
+#define BITP_DMA_STAT_MEN                     0            /*  Enable Status of the Controller */
+#define BITM_DMA_STAT_CHANM1                 (_ADI_MSK_3(0x001F0000,0x001F0000UL, uint32_t  ))    /*  Number of Available DMA Channels Minus 1 */
+#define BITM_DMA_STAT_MEN                    (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Enable Status of the Controller */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_CFG                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_CFG_MEN                      0            /*  Controller Enable */
+#define BITM_DMA_CFG_MEN                     (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Controller Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_PDBPTR                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_PDBPTR_ADDR                  0            /*  Pointer to the Base Address of the Primary Data Structure */
+#define BITM_DMA_PDBPTR_ADDR                 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Pointer to the Base Address of the Primary Data Structure */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_ADBPTR                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_ADBPTR_ADDR                  0            /*  Base Address of the Alternate Data Structure */
+#define BITM_DMA_ADBPTR_ADDR                 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Base Address of the Alternate Data Structure */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_SWREQ                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_SWREQ_CHAN                   0            /*  Generate Software Request */
+#define BITM_DMA_SWREQ_CHAN                  (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t  ))    /*  Generate Software Request */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_RMSK_SET                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_RMSK_SET_CHAN                0            /*  Mask Requests from DMA Channels */
+#define BITM_DMA_RMSK_SET_CHAN               (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t  ))    /*  Mask Requests from DMA Channels */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_RMSK_CLR                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_RMSK_CLR_CHAN                0            /*  Clear Request Mask Set Bits */
+#define BITM_DMA_RMSK_CLR_CHAN               (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t  ))    /*  Clear Request Mask Set Bits */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_EN_SET                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_EN_SET_CHAN                  0            /*  Enable DMA Channels */
+#define BITM_DMA_EN_SET_CHAN                 (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t  ))    /*  Enable DMA Channels */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_EN_CLR                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_EN_CLR_CHAN                  0            /*  Disable DMA Channels */
+#define BITM_DMA_EN_CLR_CHAN                 (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t  ))    /*  Disable DMA Channels */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_ALT_SET                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_ALT_SET_CHAN                 0            /*  Control Structure Status / Select Alternate Structure */
+#define BITM_DMA_ALT_SET_CHAN                (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t  ))    /*  Control Structure Status / Select Alternate Structure */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_ALT_CLR                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_ALT_CLR_CHAN                 0            /*  Select Primary Data Structure */
+#define BITM_DMA_ALT_CLR_CHAN                (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t  ))    /*  Select Primary Data Structure */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_PRI_SET                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_PRI_SET_CHAN                 0            /*  Configure Channel for High Priority */
+#define BITM_DMA_PRI_SET_CHAN                (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t  ))    /*  Configure Channel for High Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_PRI_CLR                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_PRI_CLR_CHPRICLR             0            /*  Configure Channel for Default Priority Level */
+#define BITM_DMA_PRI_CLR_CHPRICLR            (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t  ))    /*  Configure Channel for Default Priority Level */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_ERRCHNL_CLR                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_ERRCHNL_CLR_CHAN             0            /*  Per Channel Bus Error Status/Clear */
+#define BITM_DMA_ERRCHNL_CLR_CHAN            (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t  ))    /*  Per Channel Bus Error Status/Clear */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_ERR_CLR                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_ERR_CLR_CHAN                 0            /*  Bus Error Status */
+#define BITM_DMA_ERR_CLR_CHAN                (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t  ))    /*  Bus Error Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_INVALIDDESC_CLR                  Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_INVALIDDESC_CLR_CHAN         0            /*  Per Channel Invalid Descriptor Status/Clear */
+#define BITM_DMA_INVALIDDESC_CLR_CHAN        (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t  ))    /*  Per Channel Invalid Descriptor Status/Clear */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_BS_SET                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_BS_SET_CHAN                  0            /*  Byte Swap Status */
+#define BITM_DMA_BS_SET_CHAN                 (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t  ))    /*  Byte Swap Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_BS_CLR                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_BS_CLR_CHAN                  0            /*  Disable Byte Swap */
+#define BITM_DMA_BS_CLR_CHAN                 (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t  ))    /*  Disable Byte Swap */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_SRCADDR_SET                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_SRCADDR_SET_CHAN             0            /*  Source Address Decrement Status */
+#define BITM_DMA_SRCADDR_SET_CHAN            (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t  ))    /*  Source Address Decrement Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_SRCADDR_CLR                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_SRCADDR_CLR_CHAN             0            /*  Disable Source Address Decrement */
+#define BITM_DMA_SRCADDR_CLR_CHAN            (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t  ))    /*  Disable Source Address Decrement */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_DSTADDR_SET                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_DSTADDR_SET_CHAN             0            /*  Destination Address Decrement Status */
+#define BITM_DMA_DSTADDR_SET_CHAN            (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t  ))    /*  Destination Address Decrement Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_DSTADDR_CLR                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_DSTADDR_CLR_CHAN             0            /*  Disable Destination Address Decrement */
+#define BITM_DMA_DSTADDR_CLR_CHAN            (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t  ))    /*  Disable Destination Address Decrement */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          DMA_REVID                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_DMA_REVID_VALUE                  0            /*  DMA Controller Revision ID */
+#define BITM_DMA_REVID_VALUE                 (_ADI_MSK_3(0x000000FF,0x000000FFUL, uint32_t  ))    /*  DMA Controller Revision ID */
+
+
+/* ============================================================================================================================
+        Flash Controller
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        FLCC0
+   ============================================================================================================================ */
+#define REG_FLCC0_STAT                       0x40018000            /*  FLCC0 Status */
+#define REG_FLCC0_IEN                        0x40018004            /*  FLCC0 Interrupt Enable */
+#define REG_FLCC0_CMD                        0x40018008            /*  FLCC0 Command */
+#define REG_FLCC0_KH_ADDR                    0x4001800C            /*  FLCC0 Write Address */
+#define REG_FLCC0_KH_DATA0                   0x40018010            /*  FLCC0 Write Lower Data */
+#define REG_FLCC0_KH_DATA1                   0x40018014            /*  FLCC0 Write Upper Data */
+#define REG_FLCC0_PAGE_ADDR0                 0x40018018            /*  FLCC0 Lower Page Address */
+#define REG_FLCC0_PAGE_ADDR1                 0x4001801C            /*  FLCC0 Upper Page Address */
+#define REG_FLCC0_KEY                        0x40018020            /*  FLCC0 Key */
+#define REG_FLCC0_WR_ABORT_ADDR              0x40018024            /*  FLCC0 Write Abort Address */
+#define REG_FLCC0_WRPROT                     0x40018028            /*  FLCC0 Write Protection */
+#define REG_FLCC0_SIGNATURE                  0x4001802C            /*  FLCC0 Signature */
+#define REG_FLCC0_UCFG                       0x40018030            /*  FLCC0 User Configuration */
+#define REG_FLCC0_TIME_PARAM0                0x40018034            /*  FLCC0 Time Parameter 0 */
+#define REG_FLCC0_TIME_PARAM1                0x40018038            /*  FLCC0 Time Parameter 1 */
+#define REG_FLCC0_ABORT_EN_LO                0x4001803C            /*  FLCC0 IRQ Abort Enable (Lower Bits) */
+#define REG_FLCC0_ABORT_EN_HI                0x40018040            /*  FLCC0 IRQ Abort Enable (Upper Bits) */
+#define REG_FLCC0_ECC_CFG                    0x40018044            /*  FLCC0 ECC Configuration */
+#define REG_FLCC0_ECC_ADDR                   0x40018048            /*  FLCC0 ECC Status (Address) */
+#define REG_FLCC0_POR_SEC                    0x40018050            /*  FLCC0 Flash Security */
+#define REG_FLCC0_VOL_CFG                    0x40018054            /*  FLCC0 Volatile Flash Configuration */
+
+/* ============================================================================================================================
+        FLCC Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_STAT                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_STAT_ACCESS_MODE           31            /*  Access Mode */
+#define BITP_FLCC_STAT_CACHESRAMPERR         29            /*  SRAM parity errors in Cache Controller */
+#define BITP_FLCC_STAT_ECCDCODE              27            /*  DCode AHB Bus Error ECC status */
+#define BITP_FLCC_STAT_ECCICODE              25            /*  ICode AHB Bus Error ECC status */
+#define BITP_FLCC_STAT_ECCERRCNT             17            /*  ECC correction counter */
+#define BITP_FLCC_STAT_ECCINFOSIGN           15            /*  ECC status of flash initialization */
+#define BITP_FLCC_STAT_INIT                  14            /*  Flash controller initialization in progress */
+#define BITP_FLCC_STAT_SIGNERR               13            /*  Signature check failure during initialization */
+#define BITP_FLCC_STAT_OVERLAP               11            /*  Overlapping Command */
+#define BITP_FLCC_STAT_ECCRDERR               9            /*  ECC IRQ cause */
+#define BITP_FLCC_STAT_ECCERRCMD              7            /*  ECC errors detected during user issued SIGN command */
+#define BITP_FLCC_STAT_SLEEPING               6            /*  Flash array is in low power (sleep) mode */
+#define BITP_FLCC_STAT_CMDFAIL                4            /*  Provides information on command failures */
+#define BITP_FLCC_STAT_WRALCOMP               3            /*  Write almost complete */
+#define BITP_FLCC_STAT_CMDCOMP                2            /*  Command complete */
+#define BITP_FLCC_STAT_WRCLOSE                1            /*  WRITE registers are closed */
+#define BITP_FLCC_STAT_CMDBUSY                0            /*  Command busy */
+#define BITM_FLCC_STAT_ACCESS_MODE           (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t  ))    /*  Access Mode */
+#define BITM_FLCC_STAT_CACHESRAMPERR         (_ADI_MSK_3(0x20000000,0x20000000UL, uint32_t  ))    /*  SRAM parity errors in Cache Controller */
+#define BITM_FLCC_STAT_ECCDCODE              (_ADI_MSK_3(0x18000000,0x18000000UL, uint32_t  ))    /*  DCode AHB Bus Error ECC status */
+#define BITM_FLCC_STAT_ECCICODE              (_ADI_MSK_3(0x06000000,0x06000000UL, uint32_t  ))    /*  ICode AHB Bus Error ECC status */
+#define BITM_FLCC_STAT_ECCERRCNT             (_ADI_MSK_3(0x000E0000,0x000E0000UL, uint32_t  ))    /*  ECC correction counter */
+#define BITM_FLCC_STAT_ECCINFOSIGN           (_ADI_MSK_3(0x00018000,0x00018000UL, uint32_t  ))    /*  ECC status of flash initialization */
+#define BITM_FLCC_STAT_INIT                  (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t  ))    /*  Flash controller initialization in progress */
+#define BITM_FLCC_STAT_SIGNERR               (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t  ))    /*  Signature check failure during initialization */
+#define BITM_FLCC_STAT_OVERLAP               (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t  ))    /*  Overlapping Command */
+#define BITM_FLCC_STAT_ECCRDERR              (_ADI_MSK_3(0x00000600,0x00000600UL, uint32_t  ))    /*  ECC IRQ cause */
+#define BITM_FLCC_STAT_ECCERRCMD             (_ADI_MSK_3(0x00000180,0x00000180UL, uint32_t  ))    /*  ECC errors detected during user issued SIGN command */
+#define BITM_FLCC_STAT_SLEEPING              (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t  ))    /*  Flash array is in low power (sleep) mode */
+#define BITM_FLCC_STAT_CMDFAIL               (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t  ))    /*  Provides information on command failures */
+#define BITM_FLCC_STAT_WRALCOMP              (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Write almost complete */
+#define BITM_FLCC_STAT_CMDCOMP               (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Command complete */
+#define BITM_FLCC_STAT_WRCLOSE               (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  WRITE registers are closed */
+#define BITM_FLCC_STAT_CMDBUSY               (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Command busy */
+#define ENUM_FLCC_STAT_DIRECT                (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  ACCESS_MODE: Flash controller is currently in Direct Access mode; user access to all registers is enabled */
+#define ENUM_FLCC_STAT_INDIRECT              (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t  ))    /*  ACCESS_MODE: Flash Controller is currently in Indirect Access mode; user access to registers is limited to read-only access of the status register. Full register access will be restored when the Cryptographic module releases control of the flash controller (crypto completes the ongoing operation within the protected key storage region) */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_IEN                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_IEN_ECC_ERROR               6            /*  Control whether to generate bus errors, interrupts, or neither in response to 2-bit ECC Error events */
+#define BITP_FLCC_IEN_ECC_CORRECT             4            /*  Control whether to generate bus errors, interrupts, or neither in response to 1-bit ECC Correction events */
+#define BITP_FLCC_IEN_CMDFAIL                 2            /*  Command fail interrupt enable */
+#define BITP_FLCC_IEN_WRALCMPLT               1            /*  Write almost complete interrupt enable */
+#define BITP_FLCC_IEN_CMDCMPLT                0            /*  Command complete interrupt enable */
+#define BITM_FLCC_IEN_ECC_ERROR              (_ADI_MSK_3(0x000000C0,0x000000C0UL, uint32_t  ))    /*  Control whether to generate bus errors, interrupts, or neither in response to 2-bit ECC Error events */
+#define BITM_FLCC_IEN_ECC_CORRECT            (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t  ))    /*  Control whether to generate bus errors, interrupts, or neither in response to 1-bit ECC Correction events */
+#define BITM_FLCC_IEN_CMDFAIL                (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Command fail interrupt enable */
+#define BITM_FLCC_IEN_WRALCMPLT              (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Write almost complete interrupt enable */
+#define BITM_FLCC_IEN_CMDCMPLT               (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Command complete interrupt enable */
+#define ENUM_FLCC_IEN_NONE_ERR               (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  ECC_ERROR: Do not generate a response to ECC events */
+#define ENUM_FLCC_IEN_BUS_ERR_ERR            (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t  ))    /*  ECC_ERROR: Generate Bus Errors in response to ECC events */
+#define ENUM_FLCC_IEN_IRQ_ERR                (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t  ))    /*  ECC_ERROR: Generate IRQs in response to ECC events */
+#define ENUM_FLCC_IEN_NONE_COR               (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  ECC_CORRECT: Do not generate a response to ECC events */
+#define ENUM_FLCC_IEN_BUS_ERR_COR            (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  ECC_CORRECT: Generate Bus Errors in response to ECC events */
+#define ENUM_FLCC_IEN_IRQ_COR                (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  ECC_CORRECT: Generate IRQs in response to ECC events */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_CMD                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_CMD_VALUE                   0            /*  Commands */
+#define BITM_FLCC_CMD_VALUE                  (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t  ))    /*  Commands */
+#define ENUM_FLCC_CMD_IDLE                   (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  VALUE: IDLE */
+#define ENUM_FLCC_CMD_ABORT                  (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  VALUE: ABORT */
+#define ENUM_FLCC_CMD_SLEEP                  (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  VALUE: Requests flash to enter Sleep mode */
+#define ENUM_FLCC_CMD_SIGN                   (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t  ))    /*  VALUE: SIGN */
+#define ENUM_FLCC_CMD_WRITE                  (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  VALUE: WRITE */
+#define ENUM_FLCC_CMD_BLANK_CHECK            (_ADI_MSK_3(0x00000005,0x00000005UL, uint32_t  ))    /*  VALUE: Checks all of User Space; fails if any bits in user space are cleared */
+#define ENUM_FLCC_CMD_ERASEPAGE              (_ADI_MSK_3(0x00000006,0x00000006UL, uint32_t  ))    /*  VALUE: ERASEPAGE */
+#define ENUM_FLCC_CMD_MASSERASE              (_ADI_MSK_3(0x00000007,0x00000007UL, uint32_t  ))    /*  VALUE: MASSERASE */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_KH_ADDR                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_KH_ADDR_VALUE               3            /*  Address to be written on a WRITE command */
+#define BITM_FLCC_KH_ADDR_VALUE              (_ADI_MSK_3(0x000FFFF8,0x000FFFF8UL, uint32_t  ))    /*  Address to be written on a WRITE command */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_KH_DATA0                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_KH_DATA0_VALUE              0            /*  Lower half of 64-bit dual word data to be written on a Write command */
+#define BITM_FLCC_KH_DATA0_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Lower half of 64-bit dual word data to be written on a Write command */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_KH_DATA1                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_KH_DATA1_VALUE              0            /*  Upper half of 64-bit dual word data to be written on a Write command */
+#define BITM_FLCC_KH_DATA1_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Upper half of 64-bit dual word data to be written on a Write command */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_PAGE_ADDR0                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_PAGE_ADDR0_VALUE           10            /*  Lower address bits of the page address */
+#define BITM_FLCC_PAGE_ADDR0_VALUE           (_ADI_MSK_3(0x000FFC00,0x000FFC00UL, uint32_t  ))    /*  Lower address bits of the page address */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_PAGE_ADDR1                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_PAGE_ADDR1_VALUE           10            /*  Upper address bits of the page address */
+#define BITM_FLCC_PAGE_ADDR1_VALUE           (_ADI_MSK_3(0x000FFC00,0x000FFC00UL, uint32_t  ))    /*  Upper address bits of the page address */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_KEY                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_KEY_VALUE                   0            /*  Key register */
+#define BITM_FLCC_KEY_VALUE                  (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Key register */
+#define ENUM_FLCC_KEY_USERKEY                (_ADI_MSK_3(0x676C7565,0x676C7565UL, uint32_t  ))    /*  VALUE: USERKEY */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_WR_ABORT_ADDR                   Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_WR_ABORT_ADDR_VALUE         0            /*  Address of recently aborted write command */
+#define BITM_FLCC_WR_ABORT_ADDR_VALUE        (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Address of recently aborted write command */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_WRPROT                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_WRPROT_WORD                 0            /*  Clear bits to write protect related groups of user space pages */
+#define BITM_FLCC_WRPROT_WORD                (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Clear bits to write protect related groups of user space pages */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_SIGNATURE                       Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_SIGNATURE_VALUE             0            /*  Read signature */
+#define BITM_FLCC_SIGNATURE_VALUE            (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Read signature */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_UCFG                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_UCFG_AUTOINCEN              1            /*  Auto Address Increment for Key Hole Access */
+#define BITP_FLCC_UCFG_KHDMAEN                0            /*  Key hole DMA enable */
+#define BITM_FLCC_UCFG_AUTOINCEN             (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Auto Address Increment for Key Hole Access */
+#define BITM_FLCC_UCFG_KHDMAEN               (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Key hole DMA enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_TIME_PARAM0                     Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_TIME_PARAM0_TNVH1          28            /*  NVSTR Hold time during Mass Erase */
+#define BITP_FLCC_TIME_PARAM0_TERASE         24            /*  Erase Time */
+#define BITP_FLCC_TIME_PARAM0_TRCV           20            /*  Recovery time */
+#define BITP_FLCC_TIME_PARAM0_TNVH           16            /*  NVSTR Hold time */
+#define BITP_FLCC_TIME_PARAM0_TPROG          12            /*  Program time */
+#define BITP_FLCC_TIME_PARAM0_TPGS            8            /*  NVSTR to Program setup time */
+#define BITP_FLCC_TIME_PARAM0_TNVS            4            /*  PROG/ERASE to NVSTR setup time */
+#define BITP_FLCC_TIME_PARAM0_DIVREFCLK       0            /*  Divide Reference Clock (by 2) */
+#define BITM_FLCC_TIME_PARAM0_TNVH1          (_ADI_MSK_3(0xF0000000,0xF0000000UL, uint32_t  ))    /*  NVSTR Hold time during Mass Erase */
+#define BITM_FLCC_TIME_PARAM0_TERASE         (_ADI_MSK_3(0x0F000000,0x0F000000UL, uint32_t  ))    /*  Erase Time */
+#define BITM_FLCC_TIME_PARAM0_TRCV           (_ADI_MSK_3(0x00F00000,0x00F00000UL, uint32_t  ))    /*  Recovery time */
+#define BITM_FLCC_TIME_PARAM0_TNVH           (_ADI_MSK_3(0x000F0000,0x000F0000UL, uint32_t  ))    /*  NVSTR Hold time */
+#define BITM_FLCC_TIME_PARAM0_TPROG          (_ADI_MSK_3(0x0000F000,0x0000F000UL, uint32_t  ))    /*  Program time */
+#define BITM_FLCC_TIME_PARAM0_TPGS           (_ADI_MSK_3(0x00000F00,0x00000F00UL, uint32_t  ))    /*  NVSTR to Program setup time */
+#define BITM_FLCC_TIME_PARAM0_TNVS           (_ADI_MSK_3(0x000000F0,0x000000F0UL, uint32_t  ))    /*  PROG/ERASE to NVSTR setup time */
+#define BITM_FLCC_TIME_PARAM0_DIVREFCLK      (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Divide Reference Clock (by 2) */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_TIME_PARAM1                     Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_TIME_PARAM1_CURWAITSTATES   8            /*  Current wait states [2:0] */
+#define BITP_FLCC_TIME_PARAM1_WAITSTATES      4            /*  Number of wait states to access flash */
+#define BITP_FLCC_TIME_PARAM1_TWK             0            /*  Wake up time */
+#define BITM_FLCC_TIME_PARAM1_CURWAITSTATES  (_ADI_MSK_3(0x00000700,0x00000700UL, uint32_t  ))    /*  Current wait states [2:0] */
+#define BITM_FLCC_TIME_PARAM1_WAITSTATES     (_ADI_MSK_3(0x00000070,0x00000070UL, uint32_t  ))    /*  Number of wait states to access flash */
+#define BITM_FLCC_TIME_PARAM1_TWK            (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t  ))    /*  Wake up time */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_ABORT_EN_LO                     Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_ABORT_EN_LO_VALUE           0            /*  Sys IRQ Abort Enable */
+#define BITM_FLCC_ABORT_EN_LO_VALUE          (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Sys IRQ Abort Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_ABORT_EN_HI                     Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_ABORT_EN_HI_VALUE           0            /*  Sys IRQ Abort Enable */
+#define BITM_FLCC_ABORT_EN_HI_VALUE          (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Sys IRQ Abort Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_ECC_CFG                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_ECC_CFG_PTR                 8            /*  ECC start page pointer */
+#define BITP_FLCC_ECC_CFG_INFOEN              1            /*  Info space ECC Enable bit */
+#define BITP_FLCC_ECC_CFG_EN                  0            /*  ECC Enable */
+#define BITM_FLCC_ECC_CFG_PTR                (_ADI_MSK_3(0xFFFFFF00,0xFFFFFF00UL, uint32_t  ))    /*  ECC start page pointer */
+#define BITM_FLCC_ECC_CFG_INFOEN             (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Info space ECC Enable bit */
+#define BITM_FLCC_ECC_CFG_EN                 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  ECC Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_ECC_ADDR                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_ECC_ADDR_VALUE              0            /*  This register has the address for which ECC error is detected */
+#define BITM_FLCC_ECC_ADDR_VALUE             (_ADI_MSK_3(0x000FFFFF,0x000FFFFFUL, uint32_t  ))    /*  This register has the address for which ECC error is detected */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_POR_SEC                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_POR_SEC_SECURE              0            /*  Set this bit to prevent read or write access to User Space (sticky when set) */
+#define BITM_FLCC_POR_SEC_SECURE             (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Set this bit to prevent read or write access to User Space (sticky when set) */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_VOL_CFG                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_VOL_CFG_INFO_REMAP          0            /*  Alias the info space to the base address of user space */
+#define BITM_FLCC_VOL_CFG_INFO_REMAP         (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Alias the info space to the base address of user space */
+
+
+/* ============================================================================================================================
+        Cache Controller
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        FLCC0_CACHE
+   ============================================================================================================================ */
+#define REG_FLCC0_CACHE_STAT                 0x40018058            /*  FLCC0_CACHE Cache Status Register */
+#define REG_FLCC0_CACHE_SETUP                0x4001805C            /*  FLCC0_CACHE Cache Setup Register */
+#define REG_FLCC0_CACHE_KEY                  0x40018060            /*  FLCC0_CACHE Cache Key Register */
+
+/* ============================================================================================================================
+        FLCC_CACHE Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_CACHE_STAT                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_CACHE_STAT_ICEN             0            /*  If this bit is set,  I-Cache is enabled */
+#define BITM_FLCC_CACHE_STAT_ICEN            (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  If this bit is set,  I-Cache is enabled */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_CACHE_SETUP                     Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_CACHE_SETUP_LCKIC           1            /*  If this bit is set, I-Cache contents are locked */
+#define BITP_FLCC_CACHE_SETUP_ICEN            0            /*  If this bit set, I-Cache is enabled for AHB accesses */
+#define BITM_FLCC_CACHE_SETUP_LCKIC          (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  If this bit is set, I-Cache contents are locked */
+#define BITM_FLCC_CACHE_SETUP_ICEN           (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  If this bit set, I-Cache is enabled for AHB accesses */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          FLCC_CACHE_KEY                       Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_FLCC_CACHE_KEY_VALUE             0            /*  Cache Key */
+#define BITM_FLCC_CACHE_KEY_VALUE            (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Cache Key */
+
+
+/* ============================================================================================================================
+        
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        GPIO0
+   ============================================================================================================================ */
+#define REG_GPIO0_CFG                        0x40020000            /*  GPIO0 Port  Configuration */
+#define REG_GPIO0_OEN                        0x40020004            /*  GPIO0 Port Output Enable */
+#define REG_GPIO0_PE                         0x40020008            /*  GPIO0 Port Output Pull-up/Pull-down Enable */
+#define REG_GPIO0_IEN                        0x4002000C            /*  GPIO0 Port  Input Path Enable */
+#define REG_GPIO0_IN                         0x40020010            /*  GPIO0 Port  Registered Data Input */
+#define REG_GPIO0_OUT                        0x40020014            /*  GPIO0 Port Data Output */
+#define REG_GPIO0_SET                        0x40020018            /*  GPIO0 Port Data Out Set */
+#define REG_GPIO0_CLR                        0x4002001C            /*  GPIO0 Port Data Out Clear */
+#define REG_GPIO0_TGL                        0x40020020            /*  GPIO0 Port Pin Toggle */
+#define REG_GPIO0_POL                        0x40020024            /*  GPIO0 Port Interrupt Polarity */
+#define REG_GPIO0_IENA                       0x40020028            /*  GPIO0 Port Interrupt A Enable */
+#define REG_GPIO0_IENB                       0x4002002C            /*  GPIO0 Port Interrupt B Enable */
+#define REG_GPIO0_INT                        0x40020030            /*  GPIO0 Port Interrupt Status */
+#define REG_GPIO0_DS                         0x40020034            /*  GPIO0 Port Drive Strength Select */
+
+/* ============================================================================================================================
+        GPIO1
+   ============================================================================================================================ */
+#define REG_GPIO1_CFG                        0x40020040            /*  GPIO1 Port  Configuration */
+#define REG_GPIO1_OEN                        0x40020044            /*  GPIO1 Port Output Enable */
+#define REG_GPIO1_PE                         0x40020048            /*  GPIO1 Port Output Pull-up/Pull-down Enable */
+#define REG_GPIO1_IEN                        0x4002004C            /*  GPIO1 Port  Input Path Enable */
+#define REG_GPIO1_IN                         0x40020050            /*  GPIO1 Port  Registered Data Input */
+#define REG_GPIO1_OUT                        0x40020054            /*  GPIO1 Port Data Output */
+#define REG_GPIO1_SET                        0x40020058            /*  GPIO1 Port Data Out Set */
+#define REG_GPIO1_CLR                        0x4002005C            /*  GPIO1 Port Data Out Clear */
+#define REG_GPIO1_TGL                        0x40020060            /*  GPIO1 Port Pin Toggle */
+#define REG_GPIO1_POL                        0x40020064            /*  GPIO1 Port Interrupt Polarity */
+#define REG_GPIO1_IENA                       0x40020068            /*  GPIO1 Port Interrupt A Enable */
+#define REG_GPIO1_IENB                       0x4002006C            /*  GPIO1 Port Interrupt B Enable */
+#define REG_GPIO1_INT                        0x40020070            /*  GPIO1 Port Interrupt Status */
+#define REG_GPIO1_DS                         0x40020074            /*  GPIO1 Port Drive Strength Select */
+
+/* ============================================================================================================================
+        GPIO2
+   ============================================================================================================================ */
+#define REG_GPIO2_CFG                        0x40020080            /*  GPIO2 Port  Configuration */
+#define REG_GPIO2_OEN                        0x40020084            /*  GPIO2 Port Output Enable */
+#define REG_GPIO2_PE                         0x40020088            /*  GPIO2 Port Output Pull-up/Pull-down Enable */
+#define REG_GPIO2_IEN                        0x4002008C            /*  GPIO2 Port  Input Path Enable */
+#define REG_GPIO2_IN                         0x40020090            /*  GPIO2 Port  Registered Data Input */
+#define REG_GPIO2_OUT                        0x40020094            /*  GPIO2 Port Data Output */
+#define REG_GPIO2_SET                        0x40020098            /*  GPIO2 Port Data Out Set */
+#define REG_GPIO2_CLR                        0x4002009C            /*  GPIO2 Port Data Out Clear */
+#define REG_GPIO2_TGL                        0x400200A0            /*  GPIO2 Port Pin Toggle */
+#define REG_GPIO2_POL                        0x400200A4            /*  GPIO2 Port Interrupt Polarity */
+#define REG_GPIO2_IENA                       0x400200A8            /*  GPIO2 Port Interrupt A Enable */
+#define REG_GPIO2_IENB                       0x400200AC            /*  GPIO2 Port Interrupt B Enable */
+#define REG_GPIO2_INT                        0x400200B0            /*  GPIO2 Port Interrupt Status */
+#define REG_GPIO2_DS                         0x400200B4            /*  GPIO2 Port Drive Strength Select */
+
+/* ============================================================================================================================
+        GPIO3
+   ============================================================================================================================ */
+#define REG_GPIO3_CFG                        0x400200C0            /*  GPIO3 Port  Configuration */
+#define REG_GPIO3_OEN                        0x400200C4            /*  GPIO3 Port Output Enable */
+#define REG_GPIO3_PE                         0x400200C8            /*  GPIO3 Port Output Pull-up/Pull-down Enable */
+#define REG_GPIO3_IEN                        0x400200CC            /*  GPIO3 Port  Input Path Enable */
+#define REG_GPIO3_IN                         0x400200D0            /*  GPIO3 Port  Registered Data Input */
+#define REG_GPIO3_OUT                        0x400200D4            /*  GPIO3 Port Data Output */
+#define REG_GPIO3_SET                        0x400200D8            /*  GPIO3 Port Data Out Set */
+#define REG_GPIO3_CLR                        0x400200DC            /*  GPIO3 Port Data Out Clear */
+#define REG_GPIO3_TGL                        0x400200E0            /*  GPIO3 Port Pin Toggle */
+#define REG_GPIO3_POL                        0x400200E4            /*  GPIO3 Port Interrupt Polarity */
+#define REG_GPIO3_IENA                       0x400200E8            /*  GPIO3 Port Interrupt A Enable */
+#define REG_GPIO3_IENB                       0x400200EC            /*  GPIO3 Port Interrupt B Enable */
+#define REG_GPIO3_INT                        0x400200F0            /*  GPIO3 Port Interrupt Status */
+#define REG_GPIO3_DS                         0x400200F4            /*  GPIO3 Port Drive Strength Select */
+
+/* ============================================================================================================================
+        GPIO Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_CFG                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_CFG_PIN15                  30            /*  Pin 15  configuration bits */
+#define BITP_GPIO_CFG_PIN14                  28            /*  Pin 14  configuration bits */
+#define BITP_GPIO_CFG_PIN13                  26            /*  Pin 13  configuration bits */
+#define BITP_GPIO_CFG_PIN12                  24            /*  Pin 12  configuration bits */
+#define BITP_GPIO_CFG_PIN11                  22            /*  Pin 11  configuration bits */
+#define BITP_GPIO_CFG_PIN10                  20            /*  Pin 10  configuration bits */
+#define BITP_GPIO_CFG_PIN09                  18            /*  Pin 9 configuration bits */
+#define BITP_GPIO_CFG_PIN08                  16            /*  Pin 8 configuration bits */
+#define BITP_GPIO_CFG_PIN07                  14            /*  Pin 7 configuration bits */
+#define BITP_GPIO_CFG_PIN06                  12            /*  Pin 6 configuration bits */
+#define BITP_GPIO_CFG_PIN05                  10            /*  Pin 5 configuration bits */
+#define BITP_GPIO_CFG_PIN04                   8            /*  Pin 4 configuration bits */
+#define BITP_GPIO_CFG_PIN03                   6            /*  Pin 3 configuration bits */
+#define BITP_GPIO_CFG_PIN02                   4            /*  Pin 2 configuration bits */
+#define BITP_GPIO_CFG_PIN01                   2            /*  Pin 1 configuration bits */
+#define BITP_GPIO_CFG_PIN00                   0            /*  Pin 0 configuration bits */
+#define BITM_GPIO_CFG_PIN15                  (_ADI_MSK_3(0xC0000000,0xC0000000UL, uint32_t  ))    /*  Pin 15  configuration bits */
+#define BITM_GPIO_CFG_PIN14                  (_ADI_MSK_3(0x30000000,0x30000000UL, uint32_t  ))    /*  Pin 14  configuration bits */
+#define BITM_GPIO_CFG_PIN13                  (_ADI_MSK_3(0x0C000000,0x0C000000UL, uint32_t  ))    /*  Pin 13  configuration bits */
+#define BITM_GPIO_CFG_PIN12                  (_ADI_MSK_3(0x03000000,0x03000000UL, uint32_t  ))    /*  Pin 12  configuration bits */
+#define BITM_GPIO_CFG_PIN11                  (_ADI_MSK_3(0x00C00000,0x00C00000UL, uint32_t  ))    /*  Pin 11  configuration bits */
+#define BITM_GPIO_CFG_PIN10                  (_ADI_MSK_3(0x00300000,0x00300000UL, uint32_t  ))    /*  Pin 10  configuration bits */
+#define BITM_GPIO_CFG_PIN09                  (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t  ))    /*  Pin 9 configuration bits */
+#define BITM_GPIO_CFG_PIN08                  (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t  ))    /*  Pin 8 configuration bits */
+#define BITM_GPIO_CFG_PIN07                  (_ADI_MSK_3(0x0000C000,0x0000C000UL, uint32_t  ))    /*  Pin 7 configuration bits */
+#define BITM_GPIO_CFG_PIN06                  (_ADI_MSK_3(0x00003000,0x00003000UL, uint32_t  ))    /*  Pin 6 configuration bits */
+#define BITM_GPIO_CFG_PIN05                  (_ADI_MSK_3(0x00000C00,0x00000C00UL, uint32_t  ))    /*  Pin 5 configuration bits */
+#define BITM_GPIO_CFG_PIN04                  (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t  ))    /*  Pin 4 configuration bits */
+#define BITM_GPIO_CFG_PIN03                  (_ADI_MSK_3(0x000000C0,0x000000C0UL, uint32_t  ))    /*  Pin 3 configuration bits */
+#define BITM_GPIO_CFG_PIN02                  (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t  ))    /*  Pin 2 configuration bits */
+#define BITM_GPIO_CFG_PIN01                  (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t  ))    /*  Pin 1 configuration bits */
+#define BITM_GPIO_CFG_PIN00                  (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t  ))    /*  Pin 0 configuration bits */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_OEN                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_OEN_VALUE                   0            /*  Pin Output Drive enable */
+#define BITM_GPIO_OEN_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Pin Output Drive enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_PE                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_PE_VALUE                    0            /*  Pin Pull enable */
+#define BITM_GPIO_PE_VALUE                   (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Pin Pull enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_IEN                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_IEN_VALUE                   0            /*  Input path enable */
+#define BITM_GPIO_IEN_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Input path enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_IN                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_IN_VALUE                    0            /*  Registered data input */
+#define BITM_GPIO_IN_VALUE                   (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Registered data input */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_OUT                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_OUT_VALUE                   0            /*  Data out */
+#define BITM_GPIO_OUT_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Data out */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_SET                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_SET_VALUE                   0            /*  Set the output HIGH for the pin */
+#define BITM_GPIO_SET_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Set the output HIGH for the pin */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_CLR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_CLR_VALUE                   0            /*  Set the output low  for the port pin */
+#define BITM_GPIO_CLR_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Set the output low  for the port pin */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_TGL                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_TGL_VALUE                   0            /*  Toggle the output of the port pin */
+#define BITM_GPIO_TGL_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Toggle the output of the port pin */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_POL                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_POL_VALUE                   0            /*  Interrupt polarity */
+#define BITM_GPIO_POL_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Interrupt polarity */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_IENA                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_IENA_VALUE                  0            /*  Interrupt A enable */
+#define BITM_GPIO_IENA_VALUE                 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Interrupt A enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_IENB                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_IENB_VALUE                  0            /*  Interrupt B enable */
+#define BITM_GPIO_IENB_VALUE                 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Interrupt B enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_INT                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_INT_VALUE                   0            /*  Interrupt Status */
+#define BITM_GPIO_INT_VALUE                  (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Interrupt Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          GPIO_DS                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_GPIO_DS_VALUE                    0            /*  Drive strength select */
+#define BITM_GPIO_DS_VALUE                   (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Drive strength select */
+
+
+/* ============================================================================================================================
+        Serial Port
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        SPORT0
+   ============================================================================================================================ */
+#define REG_SPORT0_CTL_A                     0x40038000            /*  SPORT0 Half SPORT 'A' Control Register */
+#define REG_SPORT0_DIV_A                     0x40038004            /*  SPORT0 Half SPORT 'A' Divisor Register */
+#define REG_SPORT0_IEN_A                     0x40038008            /*  SPORT0 Half SPORT A's Interrupt Enable register */
+#define REG_SPORT0_STAT_A                    0x4003800C            /*  SPORT0 Half SPORT 'A' Status register */
+#define REG_SPORT0_NUMTRAN_A                 0x40038010            /*  SPORT0 Half SPORT A Number of transfers register */
+#define REG_SPORT0_CNVT_A                    0x40038014            /*  SPORT0 Half SPORT 'A' CNV width */
+#define REG_SPORT0_TX_A                      0x40038020            /*  SPORT0 Half SPORT 'A' Tx Buffer Register */
+#define REG_SPORT0_RX_A                      0x40038028            /*  SPORT0 Half SPORT 'A' Rx Buffer Register */
+#define REG_SPORT0_CTL_B                     0x40038040            /*  SPORT0 Half SPORT 'B' Control Register */
+#define REG_SPORT0_DIV_B                     0x40038044            /*  SPORT0 Half SPORT 'B' Divisor Register */
+#define REG_SPORT0_IEN_B                     0x40038048            /*  SPORT0 Half SPORT B's Interrupt Enable register */
+#define REG_SPORT0_STAT_B                    0x4003804C            /*  SPORT0 Half SPORT 'B' Status register */
+#define REG_SPORT0_NUMTRAN_B                 0x40038050            /*  SPORT0 Half SPORT B Number of transfers register */
+#define REG_SPORT0_CNVT_B                    0x40038054            /*  SPORT0 Half SPORT 'B' CNV width register */
+#define REG_SPORT0_TX_B                      0x40038060            /*  SPORT0 Half SPORT 'B' Tx Buffer Register */
+#define REG_SPORT0_RX_B                      0x40038068            /*  SPORT0 Half SPORT 'B' Rx Buffer Register */
+
+/* ============================================================================================================================
+        SPORT Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_CTL_A                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_CTL_A_DMAEN               26            /*  DMA Enable */
+#define BITP_SPORT_CTL_A_SPTRAN              25            /*  Serial Port Transfer Direction */
+#define BITP_SPORT_CTL_A_GCLKEN              21            /*  Gated Clock Enable */
+#define BITP_SPORT_CTL_A_FSERRMODE           20            /*  Frame Sync Error Operation */
+#define BITP_SPORT_CTL_A_PACK                18            /*  Packing Enable */
+#define BITP_SPORT_CTL_A_LAFS                17            /*  Late Frame Sync */
+#define BITP_SPORT_CTL_A_LFS                 16            /*  Active-Low Frame Sync */
+#define BITP_SPORT_CTL_A_DIFS                15            /*  Data-Independent Frame Sync */
+#define BITP_SPORT_CTL_A_IFS                 14            /*  Internal Frame Sync */
+#define BITP_SPORT_CTL_A_FSR                 13            /*  Frame Sync Required */
+#define BITP_SPORT_CTL_A_CKRE                12            /*  Clock Rising Edge */
+#define BITP_SPORT_CTL_A_OPMODE              11            /*  Operation mode */
+#define BITP_SPORT_CTL_A_ICLK                10            /*  Internal Clock */
+#define BITP_SPORT_CTL_A_SLEN                 4            /*  Serial Word Length */
+#define BITP_SPORT_CTL_A_LSBF                 3            /*  Least-Significant Bit First */
+#define BITP_SPORT_CTL_A_CKMUXSEL             2            /*  Clock Multiplexer Select */
+#define BITP_SPORT_CTL_A_FSMUXSEL             1            /*  Frame Sync Multiplexer Select */
+#define BITP_SPORT_CTL_A_SPEN                 0            /*  Serial Port Enable */
+#define BITM_SPORT_CTL_A_DMAEN               (_ADI_MSK_3(0x04000000,0x04000000UL, uint32_t  ))    /*  DMA Enable */
+#define BITM_SPORT_CTL_A_SPTRAN              (_ADI_MSK_3(0x02000000,0x02000000UL, uint32_t  ))    /*  Serial Port Transfer Direction */
+#define BITM_SPORT_CTL_A_GCLKEN              (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t  ))    /*  Gated Clock Enable */
+#define BITM_SPORT_CTL_A_FSERRMODE           (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t  ))    /*  Frame Sync Error Operation */
+#define BITM_SPORT_CTL_A_PACK                (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t  ))    /*  Packing Enable */
+#define BITM_SPORT_CTL_A_LAFS                (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t  ))    /*  Late Frame Sync */
+#define BITM_SPORT_CTL_A_LFS                 (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t  ))    /*  Active-Low Frame Sync */
+#define BITM_SPORT_CTL_A_DIFS                (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t  ))    /*  Data-Independent Frame Sync */
+#define BITM_SPORT_CTL_A_IFS                 (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t  ))    /*  Internal Frame Sync */
+#define BITM_SPORT_CTL_A_FSR                 (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t  ))    /*  Frame Sync Required */
+#define BITM_SPORT_CTL_A_CKRE                (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t  ))    /*  Clock Rising Edge */
+#define BITM_SPORT_CTL_A_OPMODE              (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t  ))    /*  Operation mode */
+#define BITM_SPORT_CTL_A_ICLK                (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t  ))    /*  Internal Clock */
+#define BITM_SPORT_CTL_A_SLEN                (_ADI_MSK_3(0x000001F0,0x000001F0UL, uint32_t  ))    /*  Serial Word Length */
+#define BITM_SPORT_CTL_A_LSBF                (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Least-Significant Bit First */
+#define BITM_SPORT_CTL_A_CKMUXSEL            (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Clock Multiplexer Select */
+#define BITM_SPORT_CTL_A_FSMUXSEL            (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Frame Sync Multiplexer Select */
+#define BITM_SPORT_CTL_A_SPEN                (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Serial Port Enable */
+#define ENUM_SPORT_CTL_A_CTL_RX              (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  SPTRAN: Receive */
+#define ENUM_SPORT_CTL_A_CTL_TX              (_ADI_MSK_3(0x02000000,0x02000000UL, uint32_t  ))    /*  SPTRAN: Transmit */
+#define ENUM_SPORT_CTL_A_CTL_GCLK_DIS        (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  GCLKEN: Disable */
+#define ENUM_SPORT_CTL_A_CTL_GCLK_EN         (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t  ))    /*  GCLKEN: Enable */
+#define ENUM_SPORT_CTL_A_CTL_PACK_DIS        (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  PACK: Disable */
+#define ENUM_SPORT_CTL_A_CTL_PACK_8BIT       (_ADI_MSK_3(0x00040000,0x00040000UL, uint32_t  ))    /*  PACK: 8-bit packing enable */
+#define ENUM_SPORT_CTL_A_CTL_PACK_16BIT      (_ADI_MSK_3(0x00080000,0x00080000UL, uint32_t  ))    /*  PACK: 16-bit packing enable */
+#define ENUM_SPORT_CTL_A_CTL_EARLY_FS        (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  LAFS: Early frame sync */
+#define ENUM_SPORT_CTL_A_CTL_LATE_FS         (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t  ))    /*  LAFS: Late frame sync */
+#define ENUM_SPORT_CTL_A_CTL_FS_LO           (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  LFS: Active high frame sync */
+#define ENUM_SPORT_CTL_A_CTL_FS_HI           (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t  ))    /*  LFS: Active low frame sync */
+#define ENUM_SPORT_CTL_A_CTL_DATA_DEP_FS     (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  DIFS: Data-dependent frame sync */
+#define ENUM_SPORT_CTL_A_CTL_DATA_INDP_FS    (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t  ))    /*  DIFS: Data-independent frame sync */
+#define ENUM_SPORT_CTL_A_CTL_EXTERNAL_FS     (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  IFS: External frame sync */
+#define ENUM_SPORT_CTL_A_CTL_INTERNAL_FS     (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t  ))    /*  IFS: Internal frame sync */
+#define ENUM_SPORT_CTL_A_CTL_FS_NOT_REQ      (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  FSR: No frame sync required */
+#define ENUM_SPORT_CTL_A_CTL_FS_REQ          (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t  ))    /*  FSR: Frame sync required */
+#define ENUM_SPORT_CTL_A_CTL_CLK_FALL_EDGE   (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  CKRE: Clock falling edge */
+#define ENUM_SPORT_CTL_A_CTL_CLK_RISE_EDGE   (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t  ))    /*  CKRE: Clock rising edge */
+#define ENUM_SPORT_CTL_A_CTL_SERIAL          (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  OPMODE: DSP standard */
+#define ENUM_SPORT_CTL_A_CTL_TIMER_EN_MODE   (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t  ))    /*  OPMODE: Timer_enable mode */
+#define ENUM_SPORT_CTL_A_CTL_EXTERNAL_CLK    (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  ICLK: External clock */
+#define ENUM_SPORT_CTL_A_CTL_INTERNAL_CLK    (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t  ))    /*  ICLK: Internal clock */
+#define ENUM_SPORT_CTL_A_CTL_MSB_FIRST       (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  LSBF: MSB first sent/received */
+#define ENUM_SPORT_CTL_A_CTL_LSB_FIRST       (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  LSBF: LSB first sent/received */
+#define ENUM_SPORT_CTL_A_CTL_CLK_MUX_DIS     (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  CKMUXSEL: Disable serial clock multiplexing */
+#define ENUM_SPORT_CTL_A_CTL_CLK_MUX_EN      (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  CKMUXSEL: Enable serial clock multiplexing */
+#define ENUM_SPORT_CTL_A_CTL_FS_MUX_DIS      (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  FSMUXSEL: Disable frame sync multiplexing */
+#define ENUM_SPORT_CTL_A_CTL_FS_MUX_EN       (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  FSMUXSEL: Enable frame sync multiplexing */
+#define ENUM_SPORT_CTL_A_CTL_DIS             (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  SPEN: Disable */
+#define ENUM_SPORT_CTL_A_CTL_EN              (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  SPEN: Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_DIV_A                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_DIV_A_FSDIV               16            /*  Frame Sync Divisor */
+#define BITP_SPORT_DIV_A_CLKDIV               0            /*  Clock Divisor */
+#define BITM_SPORT_DIV_A_FSDIV               (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t  ))    /*  Frame Sync Divisor */
+#define BITM_SPORT_DIV_A_CLKDIV              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t  ))    /*  Clock Divisor */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_IEN_A                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_IEN_A_SYSDATERR            4            /*  Data error for system writes or reads */
+#define BITP_SPORT_IEN_A_DATA                 3            /*  Data request interrupt to the core */
+#define BITP_SPORT_IEN_A_FSERRMSK             2            /*  Frame Sync Error (Interrupt) Mask */
+#define BITP_SPORT_IEN_A_DERRMSK              1            /*  Data Error (Interrupt) Mask */
+#define BITP_SPORT_IEN_A_TF                   0            /*  Transfer Finish Interrupt Enable */
+#define BITM_SPORT_IEN_A_SYSDATERR           (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  Data error for system writes or reads */
+#define BITM_SPORT_IEN_A_DATA                (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Data request interrupt to the core */
+#define BITM_SPORT_IEN_A_FSERRMSK            (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Frame Sync Error (Interrupt) Mask */
+#define BITM_SPORT_IEN_A_DERRMSK             (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Data Error (Interrupt) Mask */
+#define BITM_SPORT_IEN_A_TF                  (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Transfer Finish Interrupt Enable */
+#define ENUM_SPORT_IEN_A_CTL_TXFIN_DIS       (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  TF: Transfer finish Interrupt is disabled */
+#define ENUM_SPORT_IEN_A_CTL_TXFIN_EN        (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  TF: Transfer Finish Interrupt is Enabled */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_STAT_A                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_STAT_A_DXS                 8            /*  Data Transfer Buffer Status */
+#define BITP_SPORT_STAT_A_SYSDATERR           4            /*  System Data Error Status */
+#define BITP_SPORT_STAT_A_DATA                3            /*  Data Buffer status */
+#define BITP_SPORT_STAT_A_FSERR               2            /*  Frame Sync Error Status */
+#define BITP_SPORT_STAT_A_DERR                1            /*  Data Error Status */
+#define BITP_SPORT_STAT_A_TFI                 0            /*  Transmit Finish Interrupt Status */
+#define BITM_SPORT_STAT_A_DXS                (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t  ))    /*  Data Transfer Buffer Status */
+#define BITM_SPORT_STAT_A_SYSDATERR          (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  System Data Error Status */
+#define BITM_SPORT_STAT_A_DATA               (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Data Buffer status */
+#define BITM_SPORT_STAT_A_FSERR              (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Frame Sync Error Status */
+#define BITM_SPORT_STAT_A_DERR               (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Data Error Status */
+#define BITM_SPORT_STAT_A_TFI                (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Transmit Finish Interrupt Status */
+#define ENUM_SPORT_STAT_A_CTL_EMPTY          (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  DXS: Empty */
+#define ENUM_SPORT_STAT_A_CTL_PART_FULL      (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t  ))    /*  DXS: Partially full */
+#define ENUM_SPORT_STAT_A_CTL_FULL           (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t  ))    /*  DXS: Full */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_NUMTRAN_A                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_NUMTRAN_A_VALUE            0            /*  Number of transfers (Half SPORT A) */
+#define BITM_SPORT_NUMTRAN_A_VALUE           (_ADI_MSK_3(0x00000FFF,0x00000FFFUL, uint32_t  ))    /*  Number of transfers (Half SPORT A) */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_CNVT_A                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_CNVT_A_CNVT2FS            16            /*  CNV to FS duration: Half SPORT A */
+#define BITP_SPORT_CNVT_A_POL                 8            /*  Polarity of the CNV signal */
+#define BITP_SPORT_CNVT_A_WID                 0            /*  CNV signal width: Half SPORT A */
+#define BITM_SPORT_CNVT_A_CNVT2FS            (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t  ))    /*  CNV to FS duration: Half SPORT A */
+#define BITM_SPORT_CNVT_A_POL                (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t  ))    /*  Polarity of the CNV signal */
+#define BITM_SPORT_CNVT_A_WID                (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t  ))    /*  CNV signal width: Half SPORT A */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_TX_A                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_TX_A_VALUE                 0            /*  Transmit Buffer */
+#define BITM_SPORT_TX_A_VALUE                (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Transmit Buffer */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_RX_A                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_RX_A_VALUE                 0            /*  Receive Buffer */
+#define BITM_SPORT_RX_A_VALUE                (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Receive Buffer */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_CTL_B                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_CTL_B_DMAEN               26            /*  DMA Enable */
+#define BITP_SPORT_CTL_B_SPTRAN              25            /*  Serial Port Transfer Direction */
+#define BITP_SPORT_CTL_B_GCLKEN              21            /*  Gated Clock Enable */
+#define BITP_SPORT_CTL_B_FSERRMODE           20            /*  Frame Sync Error Operation */
+#define BITP_SPORT_CTL_B_PACK                18            /*  Packing Enable */
+#define BITP_SPORT_CTL_B_LAFS                17            /*  Late Frame Sync */
+#define BITP_SPORT_CTL_B_LFS                 16            /*  Active-Low Frame Sync */
+#define BITP_SPORT_CTL_B_DIFS                15            /*  Data-Independent Frame Sync */
+#define BITP_SPORT_CTL_B_IFS                 14            /*  Internal Frame Sync */
+#define BITP_SPORT_CTL_B_FSR                 13            /*  Frame Sync Required */
+#define BITP_SPORT_CTL_B_CKRE                12            /*  Clock Rising Edge */
+#define BITP_SPORT_CTL_B_OPMODE              11            /*  Operation mode */
+#define BITP_SPORT_CTL_B_ICLK                10            /*  Internal Clock */
+#define BITP_SPORT_CTL_B_SLEN                 4            /*  Serial Word Length */
+#define BITP_SPORT_CTL_B_LSBF                 3            /*  Least-Significant Bit First */
+#define BITP_SPORT_CTL_B_SPEN                 0            /*  Serial Port Enable */
+#define BITM_SPORT_CTL_B_DMAEN               (_ADI_MSK_3(0x04000000,0x04000000UL, uint32_t  ))    /*  DMA Enable */
+#define BITM_SPORT_CTL_B_SPTRAN              (_ADI_MSK_3(0x02000000,0x02000000UL, uint32_t  ))    /*  Serial Port Transfer Direction */
+#define BITM_SPORT_CTL_B_GCLKEN              (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t  ))    /*  Gated Clock Enable */
+#define BITM_SPORT_CTL_B_FSERRMODE           (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t  ))    /*  Frame Sync Error Operation */
+#define BITM_SPORT_CTL_B_PACK                (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t  ))    /*  Packing Enable */
+#define BITM_SPORT_CTL_B_LAFS                (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t  ))    /*  Late Frame Sync */
+#define BITM_SPORT_CTL_B_LFS                 (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t  ))    /*  Active-Low Frame Sync */
+#define BITM_SPORT_CTL_B_DIFS                (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t  ))    /*  Data-Independent Frame Sync */
+#define BITM_SPORT_CTL_B_IFS                 (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t  ))    /*  Internal Frame Sync */
+#define BITM_SPORT_CTL_B_FSR                 (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t  ))    /*  Frame Sync Required */
+#define BITM_SPORT_CTL_B_CKRE                (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t  ))    /*  Clock Rising Edge */
+#define BITM_SPORT_CTL_B_OPMODE              (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t  ))    /*  Operation mode */
+#define BITM_SPORT_CTL_B_ICLK                (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t  ))    /*  Internal Clock */
+#define BITM_SPORT_CTL_B_SLEN                (_ADI_MSK_3(0x000001F0,0x000001F0UL, uint32_t  ))    /*  Serial Word Length */
+#define BITM_SPORT_CTL_B_LSBF                (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Least-Significant Bit First */
+#define BITM_SPORT_CTL_B_SPEN                (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Serial Port Enable */
+#define ENUM_SPORT_CTL_B_CTL_PACK_DIS        (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  PACK: Disable */
+#define ENUM_SPORT_CTL_B_CTL_PACK_8BIT       (_ADI_MSK_3(0x00040000,0x00040000UL, uint32_t  ))    /*  PACK: 8-bit packing enable */
+#define ENUM_SPORT_CTL_B_CTL_PACK_16BIT      (_ADI_MSK_3(0x00080000,0x00080000UL, uint32_t  ))    /*  PACK: 16-bit packing enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_DIV_B                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_DIV_B_FSDIV               16            /*  Frame Sync Divisor */
+#define BITP_SPORT_DIV_B_CLKDIV               0            /*  Clock Divisor */
+#define BITM_SPORT_DIV_B_FSDIV               (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t  ))    /*  Frame Sync Divisor */
+#define BITM_SPORT_DIV_B_CLKDIV              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t  ))    /*  Clock Divisor */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_IEN_B                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_IEN_B_SYSDATERR            4            /*  Data error for system writes or reads */
+#define BITP_SPORT_IEN_B_DATA                 3            /*  Data request interrupt to the core */
+#define BITP_SPORT_IEN_B_FSERRMSK             2            /*  Frame Sync Error (Interrupt) Mask */
+#define BITP_SPORT_IEN_B_DERRMSK              1            /*  Data Error (Interrupt) Mask */
+#define BITP_SPORT_IEN_B_TF                   0            /*  Transmit Finish Interrupt Enable */
+#define BITM_SPORT_IEN_B_SYSDATERR           (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  Data error for system writes or reads */
+#define BITM_SPORT_IEN_B_DATA                (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Data request interrupt to the core */
+#define BITM_SPORT_IEN_B_FSERRMSK            (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Frame Sync Error (Interrupt) Mask */
+#define BITM_SPORT_IEN_B_DERRMSK             (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Data Error (Interrupt) Mask */
+#define BITM_SPORT_IEN_B_TF                  (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Transmit Finish Interrupt Enable */
+#define ENUM_SPORT_IEN_B_CTL_TXFIN_DIS       (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  TF: Transfer Finish Interrupt is disabled */
+#define ENUM_SPORT_IEN_B_CTL_TXFIN_EN        (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  TF: Transfer Finish Interrupt is Enabled */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_STAT_B                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_STAT_B_DXS                 8            /*  Data Transfer Buffer Status */
+#define BITP_SPORT_STAT_B_SYSDATERR           4            /*  System Data Error Status */
+#define BITP_SPORT_STAT_B_DATA                3            /*  Data Buffer status */
+#define BITP_SPORT_STAT_B_FSERR               2            /*  Frame Sync Error Status */
+#define BITP_SPORT_STAT_B_DERR                1            /*  Data Error Status */
+#define BITP_SPORT_STAT_B_TFI                 0            /*  Transmit Finish Interrupt Status */
+#define BITM_SPORT_STAT_B_DXS                (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t  ))    /*  Data Transfer Buffer Status */
+#define BITM_SPORT_STAT_B_SYSDATERR          (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  System Data Error Status */
+#define BITM_SPORT_STAT_B_DATA               (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Data Buffer status */
+#define BITM_SPORT_STAT_B_FSERR              (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Frame Sync Error Status */
+#define BITM_SPORT_STAT_B_DERR               (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Data Error Status */
+#define BITM_SPORT_STAT_B_TFI                (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Transmit Finish Interrupt Status */
+#define ENUM_SPORT_STAT_B_CTL_EMPTY          (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  DXS: Empty */
+#define ENUM_SPORT_STAT_B_CTL_PART_FULL      (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t  ))    /*  DXS: Partially full */
+#define ENUM_SPORT_STAT_B_CTL_FULL           (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t  ))    /*  DXS: Full */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_NUMTRAN_B                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_NUMTRAN_B_VALUE            0            /*  Number of transfers (Half SPORT A) */
+#define BITM_SPORT_NUMTRAN_B_VALUE           (_ADI_MSK_3(0x00000FFF,0x00000FFFUL, uint32_t  ))    /*  Number of transfers (Half SPORT A) */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_CNVT_B                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_CNVT_B_CNVT2FS            16            /*  CNV to FS duration: Half SPORT B */
+#define BITP_SPORT_CNVT_B_POL                 8            /*  Polarity of the CNV signal */
+#define BITP_SPORT_CNVT_B_WID                 0            /*  CNV signal width: Half SPORT B */
+#define BITM_SPORT_CNVT_B_CNVT2FS            (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t  ))    /*  CNV to FS duration: Half SPORT B */
+#define BITM_SPORT_CNVT_B_POL                (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t  ))    /*  Polarity of the CNV signal */
+#define BITM_SPORT_CNVT_B_WID                (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t  ))    /*  CNV signal width: Half SPORT B */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_TX_B                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_TX_B_VALUE                 0            /*  Transmit Buffer */
+#define BITM_SPORT_TX_B_VALUE                (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Transmit Buffer */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          SPORT_RX_B                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_SPORT_RX_B_VALUE                 0            /*  Receive Buffer */
+#define BITM_SPORT_RX_B_VALUE                (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Receive Buffer */
+
+
+/* ============================================================================================================================
+        CRC Accelerator
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        CRC0
+   ============================================================================================================================ */
+#define REG_CRC0_CTL                         0x40040000            /*  CRC0 CRC Control */
+#define REG_CRC0_IPDATA                      0x40040004            /*  CRC0 Input Data Word */
+#define REG_CRC0_RESULT                      0x40040008            /*  CRC0 CRC Result */
+#define REG_CRC0_POLY                        0x4004000C            /*  CRC0 Programmable CRC Polynomial */
+#define REG_CRC0_IPBITS0                     0x40040010            /*  CRC0 Input Data Bits */
+#define REG_CRC0_IPBITS1                     0x40040011            /*  CRC0 Input Data Bits */
+#define REG_CRC0_IPBITS2                     0x40040012            /*  CRC0 Input Data Bits */
+#define REG_CRC0_IPBITS3                     0x40040013            /*  CRC0 Input Data Bits */
+#define REG_CRC0_IPBITS4                     0x40040014            /*  CRC0 Input Data Bits */
+#define REG_CRC0_IPBITS5                     0x40040015            /*  CRC0 Input Data Bits */
+#define REG_CRC0_IPBITS6                     0x40040016            /*  CRC0 Input Data Bits */
+#define REG_CRC0_IPBITS7                     0x40040017            /*  CRC0 Input Data Bits */
+#define REG_CRC0_IPBITSn(i)                  (REG_CRC0_IPBITS0 + ((i) * 1))
+#define REG_CRC0_IPBITSn_COUNT               8
+#define REG_CRC0_IPBYTE                      0x40040010            /*  CRC0 Input Data Byte */
+
+/* ============================================================================================================================
+        CRC Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRC_CTL                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRC_CTL_REVID                   28            /*  Revision ID */
+#define BITP_CRC_CTL_W16SWP                   4            /*  Word16 Swap */
+#define BITP_CRC_CTL_BYTMIRR                  3            /*  Byte Mirroring */
+#define BITP_CRC_CTL_BITMIRR                  2            /*  Bit Mirroring */
+#define BITP_CRC_CTL_LSBFIRST                 1            /*  LSB First Calculation Order */
+#define BITP_CRC_CTL_EN                       0            /*  CRC Peripheral Enable */
+#define BITM_CRC_CTL_REVID                   (_ADI_MSK_3(0xF0000000,0xF0000000UL, uint32_t  ))    /*  Revision ID */
+#define BITM_CRC_CTL_W16SWP                  (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  Word16 Swap */
+#define BITM_CRC_CTL_BYTMIRR                 (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Byte Mirroring */
+#define BITM_CRC_CTL_BITMIRR                 (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Bit Mirroring */
+#define BITM_CRC_CTL_LSBFIRST                (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  LSB First Calculation Order */
+#define BITM_CRC_CTL_EN                      (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  CRC Peripheral Enable */
+#define ENUM_CRC_CTL_W16SP_DIS               (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  W16SWP: Word16 Swap disabled */
+#define ENUM_CRC_CTL_W16SP_EN                (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  W16SWP: Word16 Swap enabled */
+#define ENUM_CRC_CTL_BYTEMIR_DIS             (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  BYTMIRR: Byte Mirroring is disabled */
+#define ENUM_CRC_CTL_BYTEMIR_EN              (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  BYTMIRR: Byte Mirroring is enabled */
+#define ENUM_CRC_CTL_BITMIRR_DIS             (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  BITMIRR: Bit Mirroring is disabled */
+#define ENUM_CRC_CTL_BITMIRR_EN              (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  BITMIRR: Bit Mirroring is enabled */
+#define ENUM_CRC_CTL_MSB_FIRST               (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  LSBFIRST: MSB First CRC calculation is done */
+#define ENUM_CRC_CTL_LSB_FIRST               (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  LSBFIRST: LSB First CRC calculation is done */
+#define ENUM_CRC_CTL_CRC_DIS                 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  EN: CRC peripheral is disabled */
+#define ENUM_CRC_CTL_CRC_EN                  (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  EN: CRC peripheral is enabled */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRC_IPDATA                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRC_IPDATA_VALUE                 0            /*  Data Input */
+#define BITM_CRC_IPDATA_VALUE                (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Data Input */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRC_RESULT                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRC_RESULT_VALUE                 0            /*  CRC Residue */
+#define BITM_CRC_RESULT_VALUE                (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  CRC Residue */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRC_POLY                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRC_POLY_VALUE                   0            /*  CRC Reduction Polynomial */
+#define BITM_CRC_POLY_VALUE                  (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  CRC Reduction Polynomial */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRC_IPBITS[n]                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRC_IPBITS_DATA_BITS             0            /*  Input Data Bits */
+#define BITM_CRC_IPBITS_DATA_BITS            (_ADI_MSK_3(0x000000FF,0x000000FFU, uint8_t   ))    /*  Input Data Bits */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRC_IPBYTE                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRC_IPBYTE_DATA_BYTE             0            /*  Input Data Byte */
+#define BITM_CRC_IPBYTE_DATA_BYTE            (_ADI_MSK_3(0x000000FF,0x000000FFU, uint8_t   ))    /*  Input Data Byte */
+
+
+/* ============================================================================================================================
+        Random Number Generator
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        RNG0
+   ============================================================================================================================ */
+#define REG_RNG0_CTL                         0x40040400            /*  RNG0 RNG Control Register */
+#define REG_RNG0_LEN                         0x40040404            /*  RNG0 RNG Sample Length Register */
+#define REG_RNG0_STAT                        0x40040408            /*  RNG0 RNG Status Register */
+#define REG_RNG0_DATA                        0x4004040C            /*  RNG0 RNG Data Register */
+#define REG_RNG0_OSCCNT                      0x40040410            /*  RNG0 Oscillator Count */
+#define REG_RNG0_OSCDIFF0                    0x40040414            /*  RNG0 Oscillator Difference */
+#define REG_RNG0_OSCDIFF1                    0x40040415            /*  RNG0 Oscillator Difference */
+#define REG_RNG0_OSCDIFF2                    0x40040416            /*  RNG0 Oscillator Difference */
+#define REG_RNG0_OSCDIFF3                    0x40040417            /*  RNG0 Oscillator Difference */
+#define REG_RNG0_OSCDIFFn(i)                 (REG_RNG0_OSCDIFF0 + ((i) * 1))
+#define REG_RNG0_OSCDIFFn_COUNT              4
+
+/* ============================================================================================================================
+        RNG Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          RNG_CTL                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RNG_CTL_SINGLE                   3            /*  Generate a Single Number */
+#define BITP_RNG_CTL_EN                       0            /*  RNG Enable */
+#define BITM_RNG_CTL_SINGLE                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  Generate a Single Number */
+#define BITM_RNG_CTL_EN                      (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  RNG Enable */
+#define ENUM_RNG_CTL_WORD                    (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  SINGLE: Buffer Word */
+#define ENUM_RNG_CTL_SINGLE                  (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t  ))    /*  SINGLE: Single Byte */
+#define ENUM_RNG_CTL_DISABLE                 (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t  ))    /*  EN: Disable the RNG */
+#define ENUM_RNG_CTL_ENABLE                  (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  EN: Enable the RNG */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RNG_LEN                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RNG_LEN_PRESCALE                12            /*  Prescaler for the Sample Counter */
+#define BITP_RNG_LEN_RELOAD                   0            /*  Reload Value for the Sample Counter */
+#define BITM_RNG_LEN_PRESCALE                (_ADI_MSK_3(0x0000F000,0x0000F000U, uint16_t  ))    /*  Prescaler for the Sample Counter */
+#define BITM_RNG_LEN_RELOAD                  (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t  ))    /*  Reload Value for the Sample Counter */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RNG_STAT                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RNG_STAT_STUCK                   1            /*  Sampled Data Stuck High or Low */
+#define BITP_RNG_STAT_RNRDY                   0            /*  Random Number Ready */
+#define BITM_RNG_STAT_STUCK                  (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Sampled Data Stuck High or Low */
+#define BITM_RNG_STAT_RNRDY                  (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t  ))    /*  Random Number Ready */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RNG_DATA                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RNG_DATA_BUFF                    8            /*  Buffer for RNG Data */
+#define BITP_RNG_DATA_VALUE                   0            /*  Value of the CRC Accumulator */
+#define BITM_RNG_DATA_BUFF                   (_ADI_MSK_3(0xFFFFFF00,0xFFFFFF00UL, uint32_t  ))    /*  Buffer for RNG Data */
+#define BITM_RNG_DATA_VALUE                  (_ADI_MSK_3(0x000000FF,0x000000FFUL, uint32_t  ))    /*  Value of the CRC Accumulator */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RNG_OSCCNT                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RNG_OSCCNT_VALUE                 0            /*  Oscillator Count */
+#define BITM_RNG_OSCCNT_VALUE                (_ADI_MSK_3(0x0FFFFFFF,0x0FFFFFFFUL, uint32_t  ))    /*  Oscillator Count */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          RNG_OSCDIFF[n]                       Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_RNG_OSCDIFF_DELTA                0            /*  Oscillator Count Difference */
+#define BITM_RNG_OSCDIFF_DELTA               (_ADI_MSK_3(0x000000FF,0x000000FF, int8_t    ))    /*  Oscillator Count Difference */
+
+
+/* ============================================================================================================================
+        Register Map for the Crypto Block
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        CRYPT0
+   ============================================================================================================================ */
+#define REG_CRYPT0_CFG                       0x40044000            /*  CRYPT0 Configuration Register */
+#define REG_CRYPT0_DATALEN                   0x40044004            /*  CRYPT0 Payload Data Length */
+#define REG_CRYPT0_PREFIXLEN                 0x40044008            /*  CRYPT0 Authentication Data Length */
+#define REG_CRYPT0_INTEN                     0x4004400C            /*  CRYPT0 Interrupt Enable Register */
+#define REG_CRYPT0_STAT                      0x40044010            /*  CRYPT0 Status Register */
+#define REG_CRYPT0_INBUF                     0x40044014            /*  CRYPT0 Input Buffer */
+#define REG_CRYPT0_OUTBUF                    0x40044018            /*  CRYPT0 Output Buffer */
+#define REG_CRYPT0_NONCE0                    0x4004401C            /*  CRYPT0 Nonce Bits [31:0] */
+#define REG_CRYPT0_NONCE1                    0x40044020            /*  CRYPT0 Nonce Bits [63:32] */
+#define REG_CRYPT0_NONCE2                    0x40044024            /*  CRYPT0 Nonce Bits [95:64] */
+#define REG_CRYPT0_NONCE3                    0x40044028            /*  CRYPT0 Nonce Bits [127:96] */
+#define REG_CRYPT0_AESKEY0                   0x4004402C            /*  CRYPT0 AES Key Bits [31:0] */
+#define REG_CRYPT0_AESKEY1                   0x40044030            /*  CRYPT0 AES Key Bits [63:32] */
+#define REG_CRYPT0_AESKEY2                   0x40044034            /*  CRYPT0 AES Key Bits [95:64] */
+#define REG_CRYPT0_AESKEY3                   0x40044038            /*  CRYPT0 AES Key Bits [127:96] */
+#define REG_CRYPT0_AESKEY4                   0x4004403C            /*  CRYPT0 AES Key Bits [159:128] */
+#define REG_CRYPT0_AESKEY5                   0x40044040            /*  CRYPT0 AES Key Bits [191:160] */
+#define REG_CRYPT0_AESKEY6                   0x40044044            /*  CRYPT0 AES Key Bits [223:192] */
+#define REG_CRYPT0_AESKEY7                   0x40044048            /*  CRYPT0 AES Key Bits [255:224] */
+#define REG_CRYPT0_CNTRINIT                  0x4004404C            /*  CRYPT0 Counter Initialization Vector */
+#define REG_CRYPT0_SHAH0                     0x40044050            /*  CRYPT0 SHA Bits [31:0] */
+#define REG_CRYPT0_SHAH1                     0x40044054            /*  CRYPT0 SHA Bits [63:32] */
+#define REG_CRYPT0_SHAH2                     0x40044058            /*  CRYPT0 SHA Bits [95:64] */
+#define REG_CRYPT0_SHAH3                     0x4004405C            /*  CRYPT0 SHA Bits [127:96] */
+#define REG_CRYPT0_SHAH4                     0x40044060            /*  CRYPT0 SHA Bits [159:128] */
+#define REG_CRYPT0_SHAH5                     0x40044064            /*  CRYPT0 SHA Bits [191:160] */
+#define REG_CRYPT0_SHAH6                     0x40044068            /*  CRYPT0 SHA Bits [223:192] */
+#define REG_CRYPT0_SHAH7                     0x4004406C            /*  CRYPT0 SHA Bits [255:224] */
+#define REG_CRYPT0_SHA_LAST_WORD             0x40044070            /*  CRYPT0 SHA Last Word and Valid Bits Information */
+#define REG_CRYPT0_CCM_NUM_VALID_BYTES       0x40044074            /*  CRYPT0 NUM_VALID_BYTES */
+#define REG_CRYPT0_PRKSTORCFG                0x40044078            /*  CRYPT0 PRKSTOR Configuration */
+#define REG_CRYPT0_KUW0                      0x40044080            /*  CRYPT0 Key Wrap Unwrap Register 0 */
+#define REG_CRYPT0_KUW1                      0x40044084            /*  CRYPT0 Key Wrap Unwrap Register 1 */
+#define REG_CRYPT0_KUW2                      0x40044088            /*  CRYPT0 Key Wrap Unwrap Register 2 */
+#define REG_CRYPT0_KUW3                      0x4004408C            /*  CRYPT0 Key Wrap Unwrap Register 3 */
+#define REG_CRYPT0_KUW4                      0x40044090            /*  CRYPT0 Key Wrap Unwrap Register 4 */
+#define REG_CRYPT0_KUW5                      0x40044094            /*  CRYPT0 Key Wrap Unwrap Register 5 */
+#define REG_CRYPT0_KUW6                      0x40044098            /*  CRYPT0 Key Wrap Unwrap Register 6 */
+#define REG_CRYPT0_KUW7                      0x4004409C            /*  CRYPT0 Key Wrap Unwrap Register 7 */
+#define REG_CRYPT0_KUW8                      0x400440A0            /*  CRYPT0 Key Wrap Unwrap Register 8 */
+#define REG_CRYPT0_KUW9                      0x400440A4            /*  CRYPT0 Key Wrap Unwrap Register 9 */
+#define REG_CRYPT0_KUW10                     0x400440A8            /*  CRYPT0 Key Wrap Unwrap Register 10 */
+#define REG_CRYPT0_KUW11                     0x400440AC            /*  CRYPT0 Key Wrap Unwrap Register 11 */
+#define REG_CRYPT0_KUW12                     0x400440B0            /*  CRYPT0 Key Wrap Unwrap Register 12 */
+#define REG_CRYPT0_KUW13                     0x400440B4            /*  CRYPT0 Key Wrap Unwrap Register 13 */
+#define REG_CRYPT0_KUW14                     0x400440B8            /*  CRYPT0 Key Wrap Unwrap Register 14 */
+#define REG_CRYPT0_KUW15                     0x400440BC            /*  CRYPT0 Key Wrap Unwrap Register 15 */
+#define REG_CRYPT0_KUWVALSTR1                0x400440C0            /*  CRYPT0 Key Wrap Unwrap Validation String [63:32] */
+#define REG_CRYPT0_KUWVALSTR2                0x400440C4            /*  CRYPT0 Key Wrap Unwrap Validation String [31:0] */
+
+/* ============================================================================================================================
+        CRYPT Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_CFG                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_CFG_REVID                 28            /*  Rev ID for Crypto */
+#define BITP_CRYPT_CFG_SHAINIT               26            /*  Restarts SHA Computation */
+#define BITP_CRYPT_CFG_SHA256EN              25            /*  Enable SHA-256 Operation */
+#define BITP_CRYPT_CFG_HMACEN                21            /*  HMAC Enable */
+#define BITP_CRYPT_CFG_CMACEN                20            /*  Enable CMAC Mode Operation */
+#define BITP_CRYPT_CFG_CCMEN                 19            /*  Enable CCM/CCM* Mode Operation */
+#define BITP_CRYPT_CFG_CBCEN                 18            /*  Enable CBC Mode Operation */
+#define BITP_CRYPT_CFG_CTREN                 17            /*  Enable CTR Mode Operation */
+#define BITP_CRYPT_CFG_ECBEN                 16            /*  Enable ECB Mode Operation */
+#define BITP_CRYPT_CFG_PRKSTOREN             15            /*  Enable PRKSTOR Commands */
+#define BITP_CRYPT_CFG_KEY_BYTESWAP          14            /*  Use Key Unwrap Before HMAC */
+#define BITP_CRYPT_CFG_SHA_BYTESWAP          13            /*  Enable Key Wrap */
+#define BITP_CRYPT_CFG_AES_BYTESWAP          12            /*  Byteswap for AES Input */
+#define BITP_CRYPT_CFG_KUWKEYLEN             10            /*  Key Length  Key Wrap Unwrap */
+#define BITP_CRYPT_CFG_AESKEYLEN              8            /*  Select Key Length for AES Cipher */
+#define BITP_CRYPT_CFG_OUTFLUSH               5            /*  Output Buffer Flush */
+#define BITP_CRYPT_CFG_INFLUSH                4            /*  Input Buffer Flush */
+#define BITP_CRYPT_CFG_OUTDMAEN               3            /*  Enable DMA Channel Request for Output Buffer */
+#define BITP_CRYPT_CFG_INDMAEN                2            /*  Enable DMA Channel Request for Input Buffer */
+#define BITP_CRYPT_CFG_ENCR                   1            /*  Encrypt or Decrypt */
+#define BITP_CRYPT_CFG_BLKEN                  0            /*  Enable Bit for Crypto Block */
+#define BITM_CRYPT_CFG_REVID                 (_ADI_MSK_3(0xF0000000,0xF0000000UL, uint32_t  ))    /*  Rev ID for Crypto */
+#define BITM_CRYPT_CFG_SHAINIT               (_ADI_MSK_3(0x04000000,0x04000000UL, uint32_t  ))    /*  Restarts SHA Computation */
+#define BITM_CRYPT_CFG_SHA256EN              (_ADI_MSK_3(0x02000000,0x02000000UL, uint32_t  ))    /*  Enable SHA-256 Operation */
+#define BITM_CRYPT_CFG_HMACEN                (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t  ))    /*  HMAC Enable */
+#define BITM_CRYPT_CFG_CMACEN                (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t  ))    /*  Enable CMAC Mode Operation */
+#define BITM_CRYPT_CFG_CCMEN                 (_ADI_MSK_3(0x00080000,0x00080000UL, uint32_t  ))    /*  Enable CCM/CCM* Mode Operation */
+#define BITM_CRYPT_CFG_CBCEN                 (_ADI_MSK_3(0x00040000,0x00040000UL, uint32_t  ))    /*  Enable CBC Mode Operation */
+#define BITM_CRYPT_CFG_CTREN                 (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t  ))    /*  Enable CTR Mode Operation */
+#define BITM_CRYPT_CFG_ECBEN                 (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t  ))    /*  Enable ECB Mode Operation */
+#define BITM_CRYPT_CFG_PRKSTOREN             (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t  ))    /*  Enable PRKSTOR Commands */
+#define BITM_CRYPT_CFG_KEY_BYTESWAP          (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t  ))    /*  Use Key Unwrap Before HMAC */
+#define BITM_CRYPT_CFG_SHA_BYTESWAP          (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t  ))    /*  Enable Key Wrap */
+#define BITM_CRYPT_CFG_AES_BYTESWAP          (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t  ))    /*  Byteswap for AES Input */
+#define BITM_CRYPT_CFG_KUWKEYLEN             (_ADI_MSK_3(0x00000C00,0x00000C00UL, uint32_t  ))    /*  Key Length  Key Wrap Unwrap */
+#define BITM_CRYPT_CFG_AESKEYLEN             (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t  ))    /*  Select Key Length for AES Cipher */
+#define BITM_CRYPT_CFG_OUTFLUSH              (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  Output Buffer Flush */
+#define BITM_CRYPT_CFG_INFLUSH               (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  Input Buffer Flush */
+#define BITM_CRYPT_CFG_OUTDMAEN              (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Enable DMA Channel Request for Output Buffer */
+#define BITM_CRYPT_CFG_INDMAEN               (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Enable DMA Channel Request for Input Buffer */
+#define BITM_CRYPT_CFG_ENCR                  (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Encrypt or Decrypt */
+#define BITM_CRYPT_CFG_BLKEN                 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Enable Bit for Crypto Block */
+#define ENUM_CRYPT_CFG_LEN128                (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t  ))    /*  KUWKeyLen: The key size of KUW key is 128 bits */
+#define ENUM_CRYPT_CFG_LEN256                (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t  ))    /*  KUWKeyLen: The key size of KUW key is 256 bits */
+#define ENUM_CRYPT_CFG_LEN512                (_ADI_MSK_3(0x00000C00,0x00000C00UL, uint32_t  ))    /*  KUWKeyLen: The key size of KUW key is 512 bits */
+#define ENUM_CRYPT_CFG_AESKEYLEN128          (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  AESKEYLEN: Uses 128-bit long key */
+#define ENUM_CRYPT_CFG_AESKEYLEN256          (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t  ))    /*  AESKEYLEN: Uses 256-bit long key */
+#define ENUM_CRYPT_CFG_DMA_DISABLE_OUTBUF    (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  OUTDMAEN: Disable DMA Requesting for Output Buffer */
+#define ENUM_CRYPT_CFG_DMA_ENABLE_OUTBUF     (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  OUTDMAEN: Enable DMA Requesting for Output Buffer */
+#define ENUM_CRYPT_CFG_DMA_DISABLE_INBUF     (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  INDMAEN: Disable DMA Requesting for Input Buffer */
+#define ENUM_CRYPT_CFG_DMA_ENABLE_INBUF      (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  INDMAEN: Enable DMA Requesting for Input Buffer */
+#define ENUM_CRYPT_CFG_ENABLE                (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  BLKEN: Enable Crypto Block */
+#define ENUM_CRYPT_CFG_DISABLE               (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  BLKEN: Disable Crypto Block */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_DATALEN                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_DATALEN_VALUE              0            /*  Length of Payload Data */
+#define BITM_CRYPT_DATALEN_VALUE             (_ADI_MSK_3(0x000FFFFF,0x000FFFFFUL, uint32_t  ))    /*  Length of Payload Data */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_PREFIXLEN                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_PREFIXLEN_VALUE            0            /*  Length of Associated Data */
+#define BITM_CRYPT_PREFIXLEN_VALUE           (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t  ))    /*  Length of Associated Data */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_INTEN                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_INTEN_PRKSTRCMDONEEN       8            /*  PRKSTOR CMD DONE INTEN */
+#define BITP_CRYPT_INTEN_HMACMSGRDYEN         7            /*  Status Bit for HMAC Message Input Ready */
+#define BITP_CRYPT_INTEN_HMACDONEEN           6            /*  Interrupt Enable for HMAC Done */
+#define BITP_CRYPT_INTEN_SHADONEN             5            /*  Enable SHA_Done Interrupt */
+#define BITP_CRYPT_INTEN_INOVREN              2            /*  Enable Input Overflow Interrupt */
+#define BITP_CRYPT_INTEN_OUTRDYEN             1            /*  Enables the Output Ready Interrupt */
+#define BITP_CRYPT_INTEN_INRDYEN              0            /*  Enable Input Ready Interrupt */
+#define BITM_CRYPT_INTEN_PRKSTRCMDONEEN      (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t  ))    /*  PRKSTOR CMD DONE INTEN */
+#define BITM_CRYPT_INTEN_HMACMSGRDYEN        (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t  ))    /*  Status Bit for HMAC Message Input Ready */
+#define BITM_CRYPT_INTEN_HMACDONEEN          (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t  ))    /*  Interrupt Enable for HMAC Done */
+#define BITM_CRYPT_INTEN_SHADONEN            (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  Enable SHA_Done Interrupt */
+#define BITM_CRYPT_INTEN_INOVREN             (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Enable Input Overflow Interrupt */
+#define BITM_CRYPT_INTEN_OUTRDYEN            (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Enables the Output Ready Interrupt */
+#define BITM_CRYPT_INTEN_INRDYEN             (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Enable Input Ready Interrupt */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_STAT                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_STAT_PRKSTOR_BUSY         31            /*  Indicates PrKSTOR is Busy */
+#define BITP_CRYPT_STAT_CMD_ISSUED           27            /*  Last Command Issued to PrKStor; */
+#define BITP_CRYPT_STAT_PRKSTOR_RET_STATUS   25            /*  ECC Errors in the PRKSTOR_RETRIEVE Command */
+#define BITP_CRYPT_STAT_PRKSTOR_CMD_FAIL     24            /*  Indicates Last Command Issued Failed */
+#define BITP_CRYPT_STAT_PRKSTOR_CMD_DONE     23            /*  Indicates Command Done for PrKStor */
+#define BITP_CRYPT_STAT_HMACMSGRDY           15            /*  Status Bit Indicates HMAC is Message Ready */
+#define BITP_CRYPT_STAT_HMACDONE             14            /*  Status Bit Indicates HMAC Done */
+#define BITP_CRYPT_STAT_HMACBUSY             13            /*  Status Bit Indicates HMAC Busy */
+#define BITP_CRYPT_STAT_OUTWORDS             10            /*  Number of Words in the Output Buffer */
+#define BITP_CRYPT_STAT_INWORDS               7            /*  Number of Words in the Input Buffer */
+#define BITP_CRYPT_STAT_SHABUSY               6            /*  SHA Busy. in Computation */
+#define BITP_CRYPT_STAT_SHADONE               5            /*  SHA Computation Complete */
+#define BITP_CRYPT_STAT_INOVR                 2            /*  Overflow in the Input Buffer */
+#define BITP_CRYPT_STAT_OUTRDY                1            /*  Output Data Ready */
+#define BITP_CRYPT_STAT_INRDY                 0            /*  Input Buffer Status */
+#define BITM_CRYPT_STAT_PRKSTOR_BUSY         (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t  ))    /*  Indicates PrKSTOR is Busy */
+#define BITM_CRYPT_STAT_CMD_ISSUED           (_ADI_MSK_3(0x78000000,0x78000000UL, uint32_t  ))    /*  Last Command Issued to PrKStor; */
+#define BITM_CRYPT_STAT_PRKSTOR_RET_STATUS   (_ADI_MSK_3(0x06000000,0x06000000UL, uint32_t  ))    /*  ECC Errors in the PRKSTOR_RETRIEVE Command */
+#define BITM_CRYPT_STAT_PRKSTOR_CMD_FAIL     (_ADI_MSK_3(0x01000000,0x01000000UL, uint32_t  ))    /*  Indicates Last Command Issued Failed */
+#define BITM_CRYPT_STAT_PRKSTOR_CMD_DONE     (_ADI_MSK_3(0x00800000,0x00800000UL, uint32_t  ))    /*  Indicates Command Done for PrKStor */
+#define BITM_CRYPT_STAT_HMACMSGRDY           (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t  ))    /*  Status Bit Indicates HMAC is Message Ready */
+#define BITM_CRYPT_STAT_HMACDONE             (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t  ))    /*  Status Bit Indicates HMAC Done */
+#define BITM_CRYPT_STAT_HMACBUSY             (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t  ))    /*  Status Bit Indicates HMAC Busy */
+#define BITM_CRYPT_STAT_OUTWORDS             (_ADI_MSK_3(0x00001C00,0x00001C00UL, uint32_t  ))    /*  Number of Words in the Output Buffer */
+#define BITM_CRYPT_STAT_INWORDS              (_ADI_MSK_3(0x00000380,0x00000380UL, uint32_t  ))    /*  Number of Words in the Input Buffer */
+#define BITM_CRYPT_STAT_SHABUSY              (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t  ))    /*  SHA Busy. in Computation */
+#define BITM_CRYPT_STAT_SHADONE              (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  SHA Computation Complete */
+#define BITM_CRYPT_STAT_INOVR                (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Overflow in the Input Buffer */
+#define BITM_CRYPT_STAT_OUTRDY               (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Output Data Ready */
+#define BITM_CRYPT_STAT_INRDY                (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Input Buffer Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_INBUF                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_INBUF_VALUE                0            /*  Input Buffer */
+#define BITM_CRYPT_INBUF_VALUE               (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Input Buffer */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_OUTBUF                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_OUTBUF_VALUE               0            /*  Output Buffer */
+#define BITM_CRYPT_OUTBUF_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Output Buffer */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_NONCE0                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_NONCE0_VALUE               0            /*  Word 0: Nonce Bits [31:0] */
+#define BITM_CRYPT_NONCE0_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 0: Nonce Bits [31:0] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_NONCE1                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_NONCE1_VALUE               0            /*  Word 1: Nonce Bits [63:32] */
+#define BITM_CRYPT_NONCE1_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 1: Nonce Bits [63:32] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_NONCE2                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_NONCE2_VALUE               0            /*  Word 2: Nonce Bits [95:64] */
+#define BITM_CRYPT_NONCE2_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 2: Nonce Bits [95:64] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_NONCE3                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_NONCE3_VALUE               0            /*  Word 3: Nonce Bits [127:96] */
+#define BITM_CRYPT_NONCE3_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 3: Nonce Bits [127:96] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_AESKEY0                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_AESKEY0_VALUE              0            /*  Key: Bytes [3:0] */
+#define BITM_CRYPT_AESKEY0_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Key: Bytes [3:0] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_AESKEY1                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_AESKEY1_VALUE              0            /*  Key: Bytes [7:4] */
+#define BITM_CRYPT_AESKEY1_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Key: Bytes [7:4] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_AESKEY2                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_AESKEY2_VALUE              0            /*  Key: Bytes [11:8] */
+#define BITM_CRYPT_AESKEY2_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Key: Bytes [11:8] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_AESKEY3                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_AESKEY3_VALUE              0            /*  Key: Bytes [15:12] */
+#define BITM_CRYPT_AESKEY3_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Key: Bytes [15:12] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_AESKEY4                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_AESKEY4_VALUE              0            /*  Key: Bytes [19:16] */
+#define BITM_CRYPT_AESKEY4_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Key: Bytes [19:16] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_AESKEY5                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_AESKEY5_VALUE              0            /*  Key: Bytes [23:20] */
+#define BITM_CRYPT_AESKEY5_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Key: Bytes [23:20] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_AESKEY6                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_AESKEY6_VALUE              0            /*  Key: Bytes [27:24] */
+#define BITM_CRYPT_AESKEY6_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Key: Bytes [27:24] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_AESKEY7                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_AESKEY7_VALUE              0            /*  Key: Bytes [31:28] */
+#define BITM_CRYPT_AESKEY7_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Key: Bytes [31:28] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_CNTRINIT                       Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_CNTRINIT_VALUE             0            /*  Counter Initialization Value */
+#define BITM_CRYPT_CNTRINIT_VALUE            (_ADI_MSK_3(0x000FFFFF,0x000FFFFFUL, uint32_t  ))    /*  Counter Initialization Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_SHAH0                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_SHAH0_SHAHASH0             0            /*  Word 0: SHA Hash */
+#define BITM_CRYPT_SHAH0_SHAHASH0            (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 0: SHA Hash */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_SHAH1                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_SHAH1_SHAHASH1             0            /*  Word 1: SHA Hash */
+#define BITM_CRYPT_SHAH1_SHAHASH1            (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 1: SHA Hash */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_SHAH2                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_SHAH2_SHAHASH2             0            /*  Word 2: SHA Hash */
+#define BITM_CRYPT_SHAH2_SHAHASH2            (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 2: SHA Hash */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_SHAH3                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_SHAH3_SHAHASH3             0            /*  Word 3: SHA Hash */
+#define BITM_CRYPT_SHAH3_SHAHASH3            (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 3: SHA Hash */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_SHAH4                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_SHAH4_SHAHASH4             0            /*  Word 4: SHA Hash */
+#define BITM_CRYPT_SHAH4_SHAHASH4            (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 4: SHA Hash */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_SHAH5                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_SHAH5_SHAHASH5             0            /*  Word 5: SHA Hash */
+#define BITM_CRYPT_SHAH5_SHAHASH5            (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 5: SHA Hash */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_SHAH6                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_SHAH6_SHAHASH6             0            /*  Word 6: SHA Hash */
+#define BITM_CRYPT_SHAH6_SHAHASH6            (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 6: SHA Hash */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_SHAH7                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_SHAH7_SHAHASH7             0            /*  Word 7: SHA Hash */
+#define BITM_CRYPT_SHAH7_SHAHASH7            (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Word 7: SHA Hash */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_SHA_LAST_WORD                  Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_SHA_LAST_WORD_O_BITS_VALID  1            /*  Bits Valid in SHA Last Word Input */
+#define BITP_CRYPT_SHA_LAST_WORD_O_LAST_WORD  0            /*  Last SHA Input Word */
+#define BITM_CRYPT_SHA_LAST_WORD_O_BITS_VALID (_ADI_MSK_3(0x0000003E,0x0000003EUL, uint32_t  ))    /*  Bits Valid in SHA Last Word Input */
+#define BITM_CRYPT_SHA_LAST_WORD_O_LAST_WORD (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Last SHA Input Word */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_CCM_NUM_VALID_BYTES            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_CCM_NUM_VALID_BYTES_NUM_VALID_BYTES  0            /*  Number of Valid Bytes in CCM Last Data */
+#define BITM_CRYPT_CCM_NUM_VALID_BYTES_NUM_VALID_BYTES (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t  ))    /*  Number of Valid Bytes in CCM Last Data */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_PRKSTORCFG                     Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_PRKSTORCFG_CMD             7            /*  Command Input for PRKSTOR */
+#define BITP_CRYPT_PRKSTORCFG_KEY_INDEX       0            /*  Index of Key in PRKSTOR */
+#define BITM_CRYPT_PRKSTORCFG_CMD            (_ADI_MSK_3(0x00000780,0x00000780UL, uint32_t  ))    /*  Command Input for PRKSTOR */
+#define BITM_CRYPT_PRKSTORCFG_KEY_INDEX      (_ADI_MSK_3(0x0000007F,0x0000007FUL, uint32_t  ))    /*  Index of Key in PRKSTOR */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_KUW0                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_KUW0_KUW0                  0            /*  KUW [31:0] */
+#define BITM_CRYPT_KUW0_KUW0                 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  KUW [31:0] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_KUW1                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_KUW1_KUW1                  0            /*  KUW [63:32] */
+#define BITM_CRYPT_KUW1_KUW1                 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  KUW [63:32] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_KUW2                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_KUW2_KUW2                  0            /*  KUW [95:64] */
+#define BITM_CRYPT_KUW2_KUW2                 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  KUW [95:64] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_KUW3                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_KUW3_KUW3                  0            /*  KUW [127:96] */
+#define BITM_CRYPT_KUW3_KUW3                 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  KUW [127:96] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_KUW4                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_KUW4_KUW4                  0            /*  KUW [159:128] */
+#define BITM_CRYPT_KUW4_KUW4                 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  KUW [159:128] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_KUW5                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_KUW5_KUW5                  0            /*  KUW [191:160] */
+#define BITM_CRYPT_KUW5_KUW5                 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  KUW [191:160] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_KUW6                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_KUW6_KUW6                  0            /*  KUW [223:192] */
+#define BITM_CRYPT_KUW6_KUW6                 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  KUW [223:192] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_KUW7                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_KUW7_KUW7                  0            /*  KUW [255:224] */
+#define BITM_CRYPT_KUW7_KUW7                 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  KUW [255:224] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_KUW8                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_KUW8_KUW8                  0            /*  KUW [287:256] */
+#define BITM_CRYPT_KUW8_KUW8                 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  KUW [287:256] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_KUW9                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_KUW9_KUW9                  0            /*  KUW [319:288] */
+#define BITM_CRYPT_KUW9_KUW9                 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  KUW [319:288] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_KUW10                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_KUW10_KUW10                0            /*  KUW [351:320] */
+#define BITM_CRYPT_KUW10_KUW10               (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  KUW [351:320] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_KUW11                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_KUW11_KUW11                0            /*  KUW [383:352] */
+#define BITM_CRYPT_KUW11_KUW11               (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  KUW [383:352] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_KUW12                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_KUW12_KUW12                0            /*  KUW [415:384] */
+#define BITM_CRYPT_KUW12_KUW12               (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  KUW [415:384] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_KUW13                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_KUW13_KUW13                0            /*  KUW [447:416] */
+#define BITM_CRYPT_KUW13_KUW13               (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  KUW [447:416] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_KUW14                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_KUW14_KUW14                0            /*  KUW [479:448] */
+#define BITM_CRYPT_KUW14_KUW14               (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  KUW [479:448] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_KUW15                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_KUW15_KUW15                0            /*  KUW [511:480] */
+#define BITM_CRYPT_KUW15_KUW15               (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  KUW [511:480] */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_KUWVALSTR1                     Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_KUWVALSTR1_INITALVALUE0    0            /*  Initial Value */
+#define BITM_CRYPT_KUWVALSTR1_INITALVALUE0   (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Initial Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CRYPT_KUWVALSTR2                     Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CRYPT_KUWVALSTR2_INITIALVALUE1   0            /*  Initial Value */
+#define BITM_CRYPT_KUWVALSTR2_INITIALVALUE1  (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Initial Value */
+
+
+/* ============================================================================================================================
+        Power Management Registers
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        PMG0
+   ============================================================================================================================ */
+#define REG_PMG0_IEN                         0x4004C000            /*  PMG0 Power Supply Monitor Interrupt Enable */
+#define REG_PMG0_PSM_STAT                    0x4004C004            /*  PMG0 Power Supply Monitor Status */
+#define REG_PMG0_PWRMOD                      0x4004C008            /*  PMG0 Power Mode Register */
+#define REG_PMG0_PWRKEY                      0x4004C00C            /*  PMG0 Key Protection for PWRMOD and  SRAMRET */
+#define REG_PMG0_SHDN_STAT                   0x4004C010            /*  PMG0 Shutdown Status Register */
+#define REG_PMG0_SRAMRET                     0x4004C014            /*  PMG0 Control for Retention SRAM in Hibernate Mode */
+#define REG_PMG0_TRIM                        0x4004C038            /*  PMG0 Trimming Bits */
+#define REG_PMG0_RST_STAT                    0x4004C040            /*  PMG0 Reset Status */
+#define REG_PMG0_CTL1                        0x4004C044            /*  PMG0 HPBUCK Control */
+
+/* ============================================================================================================================
+        PMG Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_IEN                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_IEN_IENBAT                  10            /*  Interrupt enable for VBAT range */
+#define BITP_PMG_IEN_RANGEBAT                 8            /*  Battery Monitor Range */
+#define BITP_PMG_IEN_VREGOVR                  2            /*  Enable Interrupt when VREG over-voltage (above 1.32 V) */
+#define BITP_PMG_IEN_VREGUNDR                 1            /*  Enable Interrupt when VREG under-voltage (below 1 V) */
+#define BITP_PMG_IEN_VBAT                     0            /*  Enable Interrupt for VBAT */
+#define BITM_PMG_IEN_IENBAT                  (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t  ))    /*  Interrupt enable for VBAT range */
+#define BITM_PMG_IEN_RANGEBAT                (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t  ))    /*  Battery Monitor Range */
+#define BITM_PMG_IEN_VREGOVR                 (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Enable Interrupt when VREG over-voltage (above 1.32 V) */
+#define BITM_PMG_IEN_VREGUNDR                (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Enable Interrupt when VREG under-voltage (below 1 V) */
+#define BITM_PMG_IEN_VBAT                    (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Enable Interrupt for VBAT */
+#define ENUM_PMG_IEN_REGION1                 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  RANGEBAT: Configure to generate interrupt if VBAT in Region1 */
+#define ENUM_PMG_IEN_REGION2                 (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t  ))    /*  RANGEBAT: Configure to generate interrupt if VBAT in Region2 */
+#define ENUM_PMG_IEN_REGION3                 (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t  ))    /*  RANGEBAT: Configure to generate interrupt if VBAT in Region3 */
+#define ENUM_PMG_IEN_NA                      (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t  ))    /*  RANGEBAT: NA */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_PSM_STAT                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_PSM_STAT_RORANGE3           15            /*  VBAT range3 */
+#define BITP_PMG_PSM_STAT_RORANGE2           14            /*  VBAT range2 */
+#define BITP_PMG_PSM_STAT_RORANGE1           13            /*  VBAT range1 */
+#define BITP_PMG_PSM_STAT_RANGE3             10            /*  VBAT range3 */
+#define BITP_PMG_PSM_STAT_RANGE2              9            /*  VBAT range2 */
+#define BITP_PMG_PSM_STAT_RANGE1              8            /*  VBAT range1 */
+#define BITP_PMG_PSM_STAT_WICENACK            7            /*  WIC Enable Acknowledge from Cortex */
+#define BITP_PMG_PSM_STAT_VREGOVR             2            /*  Status bit for alarm indicating Over Voltage for VREG */
+#define BITP_PMG_PSM_STAT_VREGUNDR            1            /*  Status bit for Alarm indicating VREG is below 1 V */
+#define BITP_PMG_PSM_STAT_VBATUNDR            0            /*  Status bit indicating an Alarm that battery is below 1.8 V */
+#define BITM_PMG_PSM_STAT_RORANGE3           (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t  ))    /*  VBAT range3 */
+#define BITM_PMG_PSM_STAT_RORANGE2           (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t  ))    /*  VBAT range2 */
+#define BITM_PMG_PSM_STAT_RORANGE1           (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t  ))    /*  VBAT range1 */
+#define BITM_PMG_PSM_STAT_RANGE3             (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t  ))    /*  VBAT range3 */
+#define BITM_PMG_PSM_STAT_RANGE2             (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t  ))    /*  VBAT range2 */
+#define BITM_PMG_PSM_STAT_RANGE1             (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t  ))    /*  VBAT range1 */
+#define BITM_PMG_PSM_STAT_WICENACK           (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t  ))    /*  WIC Enable Acknowledge from Cortex */
+#define BITM_PMG_PSM_STAT_VREGOVR            (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Status bit for alarm indicating Over Voltage for VREG */
+#define BITM_PMG_PSM_STAT_VREGUNDR           (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Status bit for Alarm indicating VREG is below 1 V */
+#define BITM_PMG_PSM_STAT_VBATUNDR           (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Status bit indicating an Alarm that battery is below 1.8 V */
+#define ENUM_PMG_PSM_STAT_BATSTAT1           (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  RORANGE1: VBAT NOT in the range specified */
+#define ENUM_PMG_PSM_STAT_BATSTAT0           (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t  ))    /*  RORANGE1: VBAT in the range specified */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_PWRMOD                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_PWRMOD_MONVBATN              3            /*  Monitor VBAT during Hibernate Mode. Monitors VBAT by default */
+#define BITP_PMG_PWRMOD_MODE                  0            /*  Power Mode Bits */
+#define BITM_PMG_PWRMOD_MONVBATN             (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Monitor VBAT during Hibernate Mode. Monitors VBAT by default */
+#define BITM_PMG_PWRMOD_MODE                 (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t  ))    /*  Power Mode Bits */
+#define ENUM_PMG_PWRMOD_FLEXI                (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  MODE: Flexi Mode */
+#define ENUM_PMG_PWRMOD_HIBERNATE            (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  MODE: Hibernate Mode */
+#define ENUM_PMG_PWRMOD_SHUTDOWN             (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t  ))    /*  MODE: Shutdown Mode */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_PWRKEY                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_PWRKEY_VALUE                 0            /*  Power Control Key */
+#define BITM_PMG_PWRKEY_VALUE                (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t  ))    /*  Power Control Key */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_SHDN_STAT                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_SHDN_STAT_RTC                3            /*  Interrupt from RTC */
+#define BITP_PMG_SHDN_STAT_EXTINT2            2            /*  Interrupt from External Interrupt 2 */
+#define BITP_PMG_SHDN_STAT_EXTINT1            1            /*  Interrupt from External Interrupt 1 */
+#define BITP_PMG_SHDN_STAT_EXTINT0            0            /*  Interrupt from External Interrupt 0 */
+#define BITM_PMG_SHDN_STAT_RTC               (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Interrupt from RTC */
+#define BITM_PMG_SHDN_STAT_EXTINT2           (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Interrupt from External Interrupt 2 */
+#define BITM_PMG_SHDN_STAT_EXTINT1           (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Interrupt from External Interrupt 1 */
+#define BITM_PMG_SHDN_STAT_EXTINT0           (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Interrupt from External Interrupt 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_SRAMRET                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_SRAMRET_HIBERNATE_SRAM_LOAD_MODE 23            /*  Hibernate mode SRAM load mode control */
+#define BITP_PMG_SRAMRET_RET4                 9            /*  Enable retention bank 6 and bank 7 (32 KB) */
+#define BITP_PMG_SRAMRET_RET3                 8            /*  Enable retention bank 5 (32 KB) */
+#define BITP_PMG_SRAMRET_RET2                 1            /*  Enable retention bank 3 and bank 4 (32 KB) */
+#define BITP_PMG_SRAMRET_RET1                 0            /*  Enable retention bank 1 (12 KB) */
+#define BITM_PMG_SRAMRET_HIBERNATE_SRAM_LOAD_MODE (_ADI_MSK_3(0x00800000,0x00800000UL, uint32_t  ))    /*  Hibernate mode SRAM load mode control */
+#define BITM_PMG_SRAMRET_RET4                (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t  ))    /*  Enable retention bank 6 and bank 7 (32 KB) */
+#define BITM_PMG_SRAMRET_RET3                (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t  ))    /*  Enable retention bank 5 (32 KB) */
+#define BITM_PMG_SRAMRET_RET2                (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Enable retention bank 3 and bank 4 (32 KB) */
+#define BITM_PMG_SRAMRET_RET1                (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Enable retention bank 1 (12 KB) */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_TRIM                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_TRIM_HIBERNATE_LOAD_MODE    29            /*  Hibernate mode load mode control */
+#define BITM_PMG_TRIM_HIBERNATE_LOAD_MODE    (_ADI_MSK_3(0xE0000000,0xE0000000UL, uint32_t  ))    /*  Hibernate mode load mode control */
+#define ENUM_PMG_TRIM_HIGH_LOAD              (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  hibernate_load_mode: High hibernate load */
+#define ENUM_PMG_TRIM_LOW_LOAD               (_ADI_MSK_3(0xE0000000,0xE0000000UL, uint32_t  ))    /*  hibernate_load_mode: Low hibernate load */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_RST_STAT                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_RST_STAT_PORSRC              4            /*  Power on reset Source */
+#define BITP_PMG_RST_STAT_SWRST               3            /*  Software reset */
+#define BITP_PMG_RST_STAT_WDRST               2            /*  Watchdog timeout */
+#define BITP_PMG_RST_STAT_EXTRST              1            /*  External reset */
+#define BITP_PMG_RST_STAT_POR                 0            /*  Power-on reset */
+#define BITM_PMG_RST_STAT_PORSRC             (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t  ))    /*  Power on reset Source */
+#define BITM_PMG_RST_STAT_SWRST              (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Software reset */
+#define BITM_PMG_RST_STAT_WDRST              (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Watchdog timeout */
+#define BITM_PMG_RST_STAT_EXTRST             (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  External reset */
+#define BITM_PMG_RST_STAT_POR                (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Power-on reset */
+#define ENUM_PMG_RST_STAT_FAILSAFE_HV        (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  PORSRC: POR triggered because VBAT drops below Fail Safe */
+#define ENUM_PMG_RST_STAT_RST_VBAT           (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  PORSRC: POR trigger because VBAT supply (VBAT < 1.7 V) */
+#define ENUM_PMG_RST_STAT_RST_VREG           (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  PORSRC: POR triggered because VDD supply (VDD < 1.08 V) */
+#define ENUM_PMG_RST_STAT_FAILSAFE_LV        (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t  ))    /*  PORSRC: POR triggered because VREG drops below Fail Safe */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_CTL1                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_CTL1_HPBUCK_LOWPWR_MODE      2            /*  HP Buck low power mode */
+#define BITP_PMG_CTL1_HPBUCK_LD_MODE          1            /*  HP Buck load mode */
+#define BITP_PMG_CTL1_HPBUCKEN                0            /*  Enable HP Buck */
+#define BITM_PMG_CTL1_HPBUCK_LOWPWR_MODE     (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  HP Buck low power mode */
+#define BITM_PMG_CTL1_HPBUCK_LD_MODE         (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  HP Buck load mode */
+#define BITM_PMG_CTL1_HPBUCKEN               (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Enable HP Buck */
+#define ENUM_PMG_CTL1_LOWPWRDISABLE          (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  HPBUCK_LOWPWR_MODE: HPBUCK Low power mode is disabled */
+#define ENUM_PMG_CTL1_LOWPWRENABLE           (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  HPBUCK_LOWPWR_MODE: HPBUCK Low power mode is enabled */
+#define ENUM_PMG_CTL1_HPBUCKLOWLOAD          (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  HPBUCK_LD_MODE: HPBUCK Low load mode is enabled */
+#define ENUM_PMG_CTL1_HPBUCKHIGHLOAD         (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  HPBUCK_LD_MODE: HPBUCK High load mode is enabled */
+
+
+/* ============================================================================================================================
+        External interrupt configuration
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        XINT0
+   ============================================================================================================================ */
+#define REG_XINT0_CFG0                       0x4004C080            /*  XINT0 External Interrupt configuration */
+#define REG_XINT0_EXT_STAT                   0x4004C084            /*  XINT0 External Wakeup Interrupt Status register */
+#define REG_XINT0_CLR                        0x4004C090            /*  XINT0 External Interrupt clear */
+#define REG_XINT0_NMICLR                     0x4004C094            /*  XINT0 Non-maskable interrupt clear */
+
+/* ============================================================================================================================
+        XINT Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          XINT_CFG0                            Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_XINT_CFG0_UART_RX_MDE           21            /*  External Interrupt using UART_RX wakeup Mode registers */
+#define BITP_XINT_CFG0_UART_RX_EN            20            /*  External Interrupt using SIP_UPDATE enable bit */
+#define BITP_XINT_CFG0_IRQ3EN                15            /*  External Interrupt 3 enable bit */
+#define BITP_XINT_CFG0_IRQ3MDE               12            /*  External Interrupt 3 Mode registers */
+#define BITP_XINT_CFG0_IRQ2EN                11            /*  External Interrupt 2 Enable bit */
+#define BITP_XINT_CFG0_IRQ2MDE                8            /*  External Interrupt 2 Mode registers */
+#define BITP_XINT_CFG0_IRQ1EN                 7            /*  External Interrupt 1 Enable bit */
+#define BITP_XINT_CFG0_IRQ1MDE                4            /*  External Interrupt 1 Mode registers */
+#define BITP_XINT_CFG0_IRQ0EN                 3            /*  External Interrupt 0 Enable bit */
+#define BITP_XINT_CFG0_IRQ0MDE                0            /*  External Interrupt 0 Mode registers */
+#define BITM_XINT_CFG0_UART_RX_MDE           (_ADI_MSK_3(0x00E00000,0x00E00000UL, uint32_t  ))    /*  External Interrupt using UART_RX wakeup Mode registers */
+#define BITM_XINT_CFG0_UART_RX_EN            (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t  ))    /*  External Interrupt using SIP_UPDATE enable bit */
+#define BITM_XINT_CFG0_IRQ3EN                (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t  ))    /*  External Interrupt 3 enable bit */
+#define BITM_XINT_CFG0_IRQ3MDE               (_ADI_MSK_3(0x00007000,0x00007000UL, uint32_t  ))    /*  External Interrupt 3 Mode registers */
+#define BITM_XINT_CFG0_IRQ2EN                (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t  ))    /*  External Interrupt 2 Enable bit */
+#define BITM_XINT_CFG0_IRQ2MDE               (_ADI_MSK_3(0x00000700,0x00000700UL, uint32_t  ))    /*  External Interrupt 2 Mode registers */
+#define BITM_XINT_CFG0_IRQ1EN                (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t  ))    /*  External Interrupt 1 Enable bit */
+#define BITM_XINT_CFG0_IRQ1MDE               (_ADI_MSK_3(0x00000070,0x00000070UL, uint32_t  ))    /*  External Interrupt 1 Mode registers */
+#define BITM_XINT_CFG0_IRQ0EN                (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  External Interrupt 0 Enable bit */
+#define BITM_XINT_CFG0_IRQ0MDE               (_ADI_MSK_3(0x00000007,0x00000007UL, uint32_t  ))    /*  External Interrupt 0 Mode registers */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          XINT_EXT_STAT                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_XINT_EXT_STAT_STAT_UART_RXWKUP   5            /*  Interrupt status bit for UART RX WAKEUP interrupt */
+#define BITP_XINT_EXT_STAT_STAT_EXTINT3       3            /*  Interrupt status bit for External Interrupt 3 */
+#define BITP_XINT_EXT_STAT_STAT_EXTINT2       2            /*  Interrupt status bit for External Interrupt 2 */
+#define BITP_XINT_EXT_STAT_STAT_EXTINT1       1            /*  Interrupt status bit for External Interrupt 1 */
+#define BITP_XINT_EXT_STAT_STAT_EXTINT0       0            /*  Interrupt status bit for External Interrupt 0 */
+#define BITM_XINT_EXT_STAT_STAT_UART_RXWKUP  (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  Interrupt status bit for UART RX WAKEUP interrupt */
+#define BITM_XINT_EXT_STAT_STAT_EXTINT3      (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Interrupt status bit for External Interrupt 3 */
+#define BITM_XINT_EXT_STAT_STAT_EXTINT2      (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Interrupt status bit for External Interrupt 2 */
+#define BITM_XINT_EXT_STAT_STAT_EXTINT1      (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Interrupt status bit for External Interrupt 1 */
+#define BITM_XINT_EXT_STAT_STAT_EXTINT0      (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Interrupt status bit for External Interrupt 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          XINT_CLR                             Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_XINT_CLR_UART_RX_CLR             5            /*  External interrupt Clear for UART_RX WAKEUP interrupt */
+#define BITP_XINT_CLR_IRQ3                    3            /*  External interrupt 3 */
+#define BITP_XINT_CLR_IRQ2                    2            /*  External interrupt 2 */
+#define BITP_XINT_CLR_IRQ1                    1            /*  External interrupt 1 */
+#define BITP_XINT_CLR_IRQ0                    0            /*  External interrupt 0 */
+#define BITM_XINT_CLR_UART_RX_CLR            (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  External interrupt Clear for UART_RX WAKEUP interrupt */
+#define BITM_XINT_CLR_IRQ3                   (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  External interrupt 3 */
+#define BITM_XINT_CLR_IRQ2                   (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  External interrupt 2 */
+#define BITM_XINT_CLR_IRQ1                   (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  External interrupt 1 */
+#define BITM_XINT_CLR_IRQ0                   (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  External interrupt 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          XINT_NMICLR                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_XINT_NMICLR_CLR                  0            /*  NMI clear */
+#define BITM_XINT_NMICLR_CLR                 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  NMI clear */
+
+
+/* ============================================================================================================================
+        Clocking registers
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        CLKG0_OSC
+   ============================================================================================================================ */
+#define REG_CLKG0_OSC_KEY                    0x4004C10C            /*  CLKG0_OSC Key Protection for OSCCTRL */
+#define REG_CLKG0_OSC_CTL                    0x4004C110            /*  CLKG0_OSC Oscillator Control */
+
+/* ============================================================================================================================
+        CLKG_OSC Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          CLKG_OSC_KEY                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CLKG_OSC_KEY_VALUE               0            /*  Oscillator key */
+#define BITM_CLKG_OSC_KEY_VALUE              (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t  ))    /*  Oscillator key */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CLKG_OSC_CTL                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CLKG_OSC_CTL_LFX_FAIL_STA       31            /*  LF XTAL (crystal clock) Not Stable */
+#define BITP_CLKG_OSC_CTL_ROOT_FAIL_STA      30            /*  Root clock (crystal clock) Not Stable */
+#define BITP_CLKG_OSC_CTL_ROOT_AUTSW_STA     22            /*  Status of automatic switching of the Root clock to HFOSC upon detection of Root clock failure */
+#define BITP_CLKG_OSC_CTL_ROOT_AUTSW_EN      21            /*  Enables automatic Switching of the Root clock  to HFOSC on Root clock Failure */
+#define BITP_CLKG_OSC_CTL_ROOT_MON_EN        20            /*  ROOT clock monitor and Clock FAIL interrupt enable */
+#define BITP_CLKG_OSC_CTL_LFX_ROBUST_LD      15            /*  LFXTAL Robust Mode Load select */
+#define BITP_CLKG_OSC_CTL_LFX_ROBUST_EN      14            /*  LFXTAL Mode select */
+#define BITP_CLKG_OSC_CTL_LFX_AUTSW_STA      13            /*  Status of automatic switching of the LF Mux to LFOSC upon detection of LFXTAL failure */
+#define BITP_CLKG_OSC_CTL_LFX_AUTSW_EN       12            /*  Enables automatic Switching of the LF Mux to LFOSC on LFXTAL Failure */
+#define BITP_CLKG_OSC_CTL_HFX_OK             11            /*  Status of HFXTAL oscillator */
+#define BITP_CLKG_OSC_CTL_LFX_OK             10            /*  Status of LFXTAL oscillator */
+#define BITP_CLKG_OSC_CTL_HFOSC_OK            9            /*  Status of HFOSC oscillator */
+#define BITP_CLKG_OSC_CTL_LFOSC_OK            8            /*  Status of LFOSC oscillator */
+#define BITP_CLKG_OSC_CTL_LFX_MON_EN          5            /*  LFXTAL clock monitor and Clock FAIL interrupt enable */
+#define BITP_CLKG_OSC_CTL_LFX_BYP             4            /*  Low frequency crystal oscillator Bypass */
+#define BITP_CLKG_OSC_CTL_HFX_EN              3            /*  High frequency crystal oscillator enable */
+#define BITP_CLKG_OSC_CTL_LFX_EN              2            /*  Low frequency crystal oscillator enable */
+#define BITP_CLKG_OSC_CTL_HFOSC_EN            1            /*  High frequency internal oscillator enable */
+#define BITP_CLKG_OSC_CTL_LFCLK_MUX           0            /*  32 kHz clock select mux */
+#define BITM_CLKG_OSC_CTL_LFX_FAIL_STA       (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t  ))    /*  LF XTAL (crystal clock) Not Stable */
+#define BITM_CLKG_OSC_CTL_ROOT_FAIL_STA      (_ADI_MSK_3(0x40000000,0x40000000UL, uint32_t  ))    /*  Root clock (crystal clock) Not Stable */
+#define BITM_CLKG_OSC_CTL_ROOT_AUTSW_STA     (_ADI_MSK_3(0x00400000,0x00400000UL, uint32_t  ))    /*  Status of automatic switching of the Root clock to HFOSC upon detection of Root clock failure */
+#define BITM_CLKG_OSC_CTL_ROOT_AUTSW_EN      (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t  ))    /*  Enables automatic Switching of the Root clock  to HFOSC on Root clock Failure */
+#define BITM_CLKG_OSC_CTL_ROOT_MON_EN        (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t  ))    /*  ROOT clock monitor and Clock FAIL interrupt enable */
+#define BITM_CLKG_OSC_CTL_LFX_ROBUST_LD      (_ADI_MSK_3(0x00018000,0x00018000UL, uint32_t  ))    /*  LFXTAL Robust Mode Load select */
+#define BITM_CLKG_OSC_CTL_LFX_ROBUST_EN      (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t  ))    /*  LFXTAL Mode select */
+#define BITM_CLKG_OSC_CTL_LFX_AUTSW_STA      (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t  ))    /*  Status of automatic switching of the LF Mux to LFOSC upon detection of LFXTAL failure */
+#define BITM_CLKG_OSC_CTL_LFX_AUTSW_EN       (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t  ))    /*  Enables automatic Switching of the LF Mux to LFOSC on LFXTAL Failure */
+#define BITM_CLKG_OSC_CTL_HFX_OK             (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t  ))    /*  Status of HFXTAL oscillator */
+#define BITM_CLKG_OSC_CTL_LFX_OK             (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t  ))    /*  Status of LFXTAL oscillator */
+#define BITM_CLKG_OSC_CTL_HFOSC_OK           (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t  ))    /*  Status of HFOSC oscillator */
+#define BITM_CLKG_OSC_CTL_LFOSC_OK           (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t  ))    /*  Status of LFOSC oscillator */
+#define BITM_CLKG_OSC_CTL_LFX_MON_EN         (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  LFXTAL clock monitor and Clock FAIL interrupt enable */
+#define BITM_CLKG_OSC_CTL_LFX_BYP            (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  Low frequency crystal oscillator Bypass */
+#define BITM_CLKG_OSC_CTL_HFX_EN             (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  High frequency crystal oscillator enable */
+#define BITM_CLKG_OSC_CTL_LFX_EN             (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Low frequency crystal oscillator enable */
+#define BITM_CLKG_OSC_CTL_HFOSC_EN           (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  High frequency internal oscillator enable */
+#define BITM_CLKG_OSC_CTL_LFCLK_MUX          (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  32 kHz clock select mux */
+
+
+/* ============================================================================================================================
+        Power Management Registers
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        PMG0_TST
+   ============================================================================================================================ */
+#define REG_PMG0_TST_SRAM_CTL                0x4004C260            /*  PMG0_TST Control for SRAM Parity and Instruction SRAM */
+#define REG_PMG0_TST_SRAM_INITSTAT           0x4004C264            /*  PMG0_TST Initialization Status Register */
+#define REG_PMG0_TST_CLR_LATCH_GPIOS         0x4004C268            /*  PMG0_TST Clear GPIO After Shutdown Mode */
+#define REG_PMG0_TST_SCRPAD_IMG              0x4004C26C            /*  PMG0_TST Scratch Pad Image */
+#define REG_PMG0_TST_SCRPAD_3V_RD            0x4004C270            /*  PMG0_TST Scratch Pad Saved in Battery Domain */
+#define REG_PMG0_TST_FAST_SHT_WAKEUP         0x4004C274            /*  PMG0_TST Fast Shutdown Wake-up Enable */
+
+/* ============================================================================================================================
+        PMG_TST Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_TST_SRAM_CTL                     Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_TST_SRAM_CTL_INSTREN        31            /*  Enables 32 KB instruction SRAM */
+#define BITP_PMG_TST_SRAM_CTL_PENBNK7        23            /*  Enable parity check */
+#define BITP_PMG_TST_SRAM_CTL_PENBNK6        22            /*  Enable parity check */
+#define BITP_PMG_TST_SRAM_CTL_PENBNK5        21            /*  Enable parity check */
+#define BITP_PMG_TST_SRAM_CTL_PENBNK4        20            /*  Enable parity check */
+#define BITP_PMG_TST_SRAM_CTL_PENBNK3        19            /*  Enable parity check */
+#define BITP_PMG_TST_SRAM_CTL_PENBNK2        18            /*  Enable parity check */
+#define BITP_PMG_TST_SRAM_CTL_PENBNK1        17            /*  Enable parity check */
+#define BITP_PMG_TST_SRAM_CTL_PENBNK0        16            /*  Enable parity check */
+#define BITP_PMG_TST_SRAM_CTL_ABTINIT        15            /*  Abort current initialization. Self-cleared */
+#define BITP_PMG_TST_SRAM_CTL_AUTOINIT       14            /*  Automatic initialization on wake up from hibernate mode */
+#define BITP_PMG_TST_SRAM_CTL_STARTINIT      13            /*  Write one to trigger initialization. Self-cleared */
+#define BITP_PMG_TST_SRAM_CTL_BNK7EN          7            /*  Enable initialization */
+#define BITP_PMG_TST_SRAM_CTL_BNK2EN          2            /*  Enable initialization */
+#define BITP_PMG_TST_SRAM_CTL_BNK1EN          1            /*  Enable initialization */
+#define BITM_PMG_TST_SRAM_CTL_INSTREN        (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t  ))    /*  Enables 32 KB instruction SRAM */
+#define BITM_PMG_TST_SRAM_CTL_PENBNK7        (_ADI_MSK_3(0x00800000,0x00800000UL, uint32_t  ))    /*  Enable parity check */
+#define BITM_PMG_TST_SRAM_CTL_PENBNK6        (_ADI_MSK_3(0x00400000,0x00400000UL, uint32_t  ))    /*  Enable parity check */
+#define BITM_PMG_TST_SRAM_CTL_PENBNK5        (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t  ))    /*  Enable parity check */
+#define BITM_PMG_TST_SRAM_CTL_PENBNK4        (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t  ))    /*  Enable parity check */
+#define BITM_PMG_TST_SRAM_CTL_PENBNK3        (_ADI_MSK_3(0x00080000,0x00080000UL, uint32_t  ))    /*  Enable parity check */
+#define BITM_PMG_TST_SRAM_CTL_PENBNK2        (_ADI_MSK_3(0x00040000,0x00040000UL, uint32_t  ))    /*  Enable parity check */
+#define BITM_PMG_TST_SRAM_CTL_PENBNK1        (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t  ))    /*  Enable parity check */
+#define BITM_PMG_TST_SRAM_CTL_PENBNK0        (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t  ))    /*  Enable parity check */
+#define BITM_PMG_TST_SRAM_CTL_ABTINIT        (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t  ))    /*  Abort current initialization. Self-cleared */
+#define BITM_PMG_TST_SRAM_CTL_AUTOINIT       (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t  ))    /*  Automatic initialization on wake up from hibernate mode */
+#define BITM_PMG_TST_SRAM_CTL_STARTINIT      (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t  ))    /*  Write one to trigger initialization. Self-cleared */
+#define BITM_PMG_TST_SRAM_CTL_BNK7EN         (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t  ))    /*  Enable initialization */
+#define BITM_PMG_TST_SRAM_CTL_BNK2EN         (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Enable initialization */
+#define BITM_PMG_TST_SRAM_CTL_BNK1EN         (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Enable initialization */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_TST_SRAM_INITSTAT                Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_TST_SRAM_INITSTAT_BNK7DONE   7            /*  Bank 7 initialization status */
+#define BITP_PMG_TST_SRAM_INITSTAT_BNK6DONE   6            /*  Bank 6 initialization status */
+#define BITP_PMG_TST_SRAM_INITSTAT_BNK5DONE   5            /*  Bank 5 initialization status */
+#define BITP_PMG_TST_SRAM_INITSTAT_BNK4DONE   4            /*  Bank 4 initialization status */
+#define BITP_PMG_TST_SRAM_INITSTAT_BNK3DONE   3            /*  Bank 3 initialization status */
+#define BITP_PMG_TST_SRAM_INITSTAT_BNK2DONE   2            /*  Bank 2 initialization status */
+#define BITP_PMG_TST_SRAM_INITSTAT_BNK1DONE   1            /*  Bank 1 initialization status */
+#define BITP_PMG_TST_SRAM_INITSTAT_BNK0DONE   0            /*  Bank 0 initialization status */
+#define BITM_PMG_TST_SRAM_INITSTAT_BNK7DONE  (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t  ))    /*  Bank 7 initialization status */
+#define BITM_PMG_TST_SRAM_INITSTAT_BNK6DONE  (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t  ))    /*  Bank 6 initialization status */
+#define BITM_PMG_TST_SRAM_INITSTAT_BNK5DONE  (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  Bank 5 initialization status */
+#define BITM_PMG_TST_SRAM_INITSTAT_BNK4DONE  (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  Bank 4 initialization status */
+#define BITM_PMG_TST_SRAM_INITSTAT_BNK3DONE  (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  Bank 3 initialization status */
+#define BITM_PMG_TST_SRAM_INITSTAT_BNK2DONE  (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  Bank 2 initialization status */
+#define BITM_PMG_TST_SRAM_INITSTAT_BNK1DONE  (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  Bank 1 initialization status */
+#define BITM_PMG_TST_SRAM_INITSTAT_BNK0DONE  (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Bank 0 initialization status */
+#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK7_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  BNK7DONE: Bank 7 not initialized */
+#define ENUM_PMG_TST_SRAM_INITSTAT_BANK7_INIT (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t  ))    /*  BNK7DONE: Bank 7 initialized */
+#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK6_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  BNK6DONE: Bank 6 not initialized */
+#define ENUM_PMG_TST_SRAM_INITSTAT_BANK6_INIT (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t  ))    /*  BNK6DONE: Bank 6 initialized */
+#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK5_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  BNK5DONE: Bank 5 not initialized */
+#define ENUM_PMG_TST_SRAM_INITSTAT_BANK5_INIT (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  BNK5DONE: Bank 5 initialized */
+#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK4_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  BNK4DONE: Bank 4 not initialized */
+#define ENUM_PMG_TST_SRAM_INITSTAT_BANK4_INIT (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  BNK4DONE: Bank 4 initialized */
+#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK3_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  BNK3DONE: Bank 3 not initialized */
+#define ENUM_PMG_TST_SRAM_INITSTAT_BANK3_INIT (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  BNK3DONE: Bank 3 initialized */
+#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK2_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  BNK2DONE: Bank 2 not initialized */
+#define ENUM_PMG_TST_SRAM_INITSTAT_BANK2_INIT (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  BNK2DONE: Bank 2 initialized */
+#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK1_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  BNK1DONE: Bank 1 not initialized */
+#define ENUM_PMG_TST_SRAM_INITSTAT_BANK1_INIT (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  BNK1DONE: Bank 1 initialized */
+#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK0_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t  ))    /*  BNK0DONE: Bank 0 not initialized */
+#define ENUM_PMG_TST_SRAM_INITSTAT_BANK0_INIT (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  BNK0DONE: Bank 0 initialized */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_TST_CLR_LATCH_GPIOS              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_TST_CLR_LATCH_GPIOS_VALUE    0            /*  Writing 0x58FA creates a pulse to clear the latches for the GPIOs */
+#define BITM_PMG_TST_CLR_LATCH_GPIOS_VALUE   (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t  ))    /*  Writing 0x58FA creates a pulse to clear the latches for the GPIOs */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_TST_SCRPAD_IMG                   Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_TST_SCRPAD_IMG_DATA          0            /*  Value written to this register is saved in 3 V when going to shutdown */
+#define BITM_PMG_TST_SCRPAD_IMG_DATA         (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Value written to this register is saved in 3 V when going to shutdown */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_TST_SCRPAD_3V_RD                 Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_TST_SCRPAD_3V_RD_DATA        0            /*  Reading the scratch pad stored in shutdown mode */
+#define BITM_PMG_TST_SCRPAD_3V_RD_DATA       (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Reading the scratch pad stored in shutdown mode */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PMG_TST_FAST_SHT_WAKEUP              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PMG_TST_FAST_SHT_WAKEUP_FAST_SHT_WAKEUP  0            /*  Enables fast shutdown wake-up */
+#define BITM_PMG_TST_FAST_SHT_WAKEUP_FAST_SHT_WAKEUP (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  Enables fast shutdown wake-up */
+
+
+/* ============================================================================================================================
+        Clocking registers
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        CLKG0_CLK
+   ============================================================================================================================ */
+#define REG_CLKG0_CLK_CTL0                   0x4004C300            /*  CLKG0_CLK Misc Clock Settings */
+#define REG_CLKG0_CLK_CTL1                   0x4004C304            /*  CLKG0_CLK Clock Dividers */
+#define REG_CLKG0_CLK_CTL2                   0x4004C308            /*  CLKG0_CLK HF Oscillator Divided Clock Select */
+#define REG_CLKG0_CLK_CTL3                   0x4004C30C            /*  CLKG0_CLK System PLL */
+#define REG_CLKG0_CLK_CTL5                   0x4004C314            /*  CLKG0_CLK User Clock Gating Control */
+#define REG_CLKG0_CLK_STAT0                  0x4004C318            /*  CLKG0_CLK Clocking Status */
+
+/* ============================================================================================================================
+        CLKG_CLK Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          CLKG_CLK_CTL0                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CLKG_CLK_CTL0_HFXTALIE          15            /*  High frequency crystal interrupt enable */
+#define BITP_CLKG_CLK_CTL0_LFXTALIE          14            /*  Low frequency crystal interrupt enable */
+#define BITP_CLKG_CLK_CTL0_PLL_IPSEL         11            /*  SPLL source select mux */
+#define BITP_CLKG_CLK_CTL0_RCLKMUX            8            /*  Flash reference clock and HPBUCK clock source mux */
+#define BITP_CLKG_CLK_CTL0_CLKOUT             3            /*  GPIO clock out select */
+#define BITP_CLKG_CLK_CTL0_CLKMUX             0            /*  Clock mux select */
+#define BITM_CLKG_CLK_CTL0_HFXTALIE          (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t  ))    /*  High frequency crystal interrupt enable */
+#define BITM_CLKG_CLK_CTL0_LFXTALIE          (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t  ))    /*  Low frequency crystal interrupt enable */
+#define BITM_CLKG_CLK_CTL0_PLL_IPSEL         (_ADI_MSK_3(0x00001800,0x00001800UL, uint32_t  ))    /*  SPLL source select mux */
+#define BITM_CLKG_CLK_CTL0_RCLKMUX           (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t  ))    /*  Flash reference clock and HPBUCK clock source mux */
+#define BITM_CLKG_CLK_CTL0_CLKOUT            (_ADI_MSK_3(0x00000078,0x00000078UL, uint32_t  ))    /*  GPIO clock out select */
+#define BITM_CLKG_CLK_CTL0_CLKMUX            (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t  ))    /*  Clock mux select */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CLKG_CLK_CTL1                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CLKG_CLK_CTL1_ACLKDIVCNT        16            /*  ACLK Divide Count */
+#define BITP_CLKG_CLK_CTL1_PCLKDIVCNT         8            /*  PCLK divide count */
+#define BITP_CLKG_CLK_CTL1_HCLKDIVCNT         0            /*  HCLK divide count */
+#define BITM_CLKG_CLK_CTL1_ACLKDIVCNT        (_ADI_MSK_3(0x01FF0000,0x01FF0000UL, uint32_t  ))    /*  ACLK Divide Count */
+#define BITM_CLKG_CLK_CTL1_PCLKDIVCNT        (_ADI_MSK_3(0x00003F00,0x00003F00UL, uint32_t  ))    /*  PCLK divide count */
+#define BITM_CLKG_CLK_CTL1_HCLKDIVCNT        (_ADI_MSK_3(0x0000003F,0x0000003FUL, uint32_t  ))    /*  HCLK divide count */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CLKG_CLK_CTL2                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CLKG_CLK_CTL2_HFOSCDIVCLKSEL     1            /*  HF Oscillator divided clock select */
+#define BITP_CLKG_CLK_CTL2_HFOSCAUTODIV_EN    0            /*  HF Oscillator auto divide by one clock selection during wakeup from Flexi power mode */
+#define BITM_CLKG_CLK_CTL2_HFOSCDIVCLKSEL    (_ADI_MSK_3(0x0000000E,0x0000000EUL, uint32_t  ))    /*  HF Oscillator divided clock select */
+#define BITM_CLKG_CLK_CTL2_HFOSCAUTODIV_EN   (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  HF Oscillator auto divide by one clock selection during wakeup from Flexi power mode */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CLKG_CLK_CTL3                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CLKG_CLK_CTL3_SPLLMUL2          16            /*  System PLL multiply by 2 */
+#define BITP_CLKG_CLK_CTL3_SPLLMSEL          11            /*  System PLL M Divider */
+#define BITP_CLKG_CLK_CTL3_SPLLIE            10            /*  System PLL interrupt enable */
+#define BITP_CLKG_CLK_CTL3_SPLLEN             9            /*  System PLL enable */
+#define BITP_CLKG_CLK_CTL3_SPLLDIV2           8            /*  System PLL division by 2 */
+#define BITP_CLKG_CLK_CTL3_SPLLNSEL           0            /*  System PLL N multiplier */
+#define BITM_CLKG_CLK_CTL3_SPLLMUL2          (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t  ))    /*  System PLL multiply by 2 */
+#define BITM_CLKG_CLK_CTL3_SPLLMSEL          (_ADI_MSK_3(0x00007800,0x00007800UL, uint32_t  ))    /*  System PLL M Divider */
+#define BITM_CLKG_CLK_CTL3_SPLLIE            (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t  ))    /*  System PLL interrupt enable */
+#define BITM_CLKG_CLK_CTL3_SPLLEN            (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t  ))    /*  System PLL enable */
+#define BITM_CLKG_CLK_CTL3_SPLLDIV2          (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t  ))    /*  System PLL division by 2 */
+#define BITM_CLKG_CLK_CTL3_SPLLNSEL          (_ADI_MSK_3(0x0000001F,0x0000001FUL, uint32_t  ))    /*  System PLL N multiplier */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CLKG_CLK_CTL5                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CLKG_CLK_CTL5_TMRRGBCLKOFF       6            /*  Timer RGB user control */
+#define BITP_CLKG_CLK_CTL5_PERCLKOFF          5            /*  This bit is used to disable all clocks connected to all peripherals */
+#define BITP_CLKG_CLK_CTL5_GPIOCLKOFF         4            /*  GPIO clock control */
+#define BITP_CLKG_CLK_CTL5_UCLKI2COFF         3            /*  I2C clock user control */
+#define BITP_CLKG_CLK_CTL5_GPTCLK2OFF         2            /*  GP Timer 2 user control */
+#define BITP_CLKG_CLK_CTL5_GPTCLK1OFF         1            /*  GP Timer 1 user control */
+#define BITP_CLKG_CLK_CTL5_GPTCLK0OFF         0            /*  GP Timer 0 user control */
+#define BITM_CLKG_CLK_CTL5_TMRRGBCLKOFF      (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t  ))    /*  Timer RGB user control */
+#define BITM_CLKG_CLK_CTL5_PERCLKOFF         (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t  ))    /*  This bit is used to disable all clocks connected to all peripherals */
+#define BITM_CLKG_CLK_CTL5_GPIOCLKOFF        (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t  ))    /*  GPIO clock control */
+#define BITM_CLKG_CLK_CTL5_UCLKI2COFF        (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t  ))    /*  I2C clock user control */
+#define BITM_CLKG_CLK_CTL5_GPTCLK2OFF        (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  GP Timer 2 user control */
+#define BITM_CLKG_CLK_CTL5_GPTCLK1OFF        (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  GP Timer 1 user control */
+#define BITM_CLKG_CLK_CTL5_GPTCLK0OFF        (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  GP Timer 0 user control */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          CLKG_CLK_STAT0                       Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CLKG_CLK_STAT0_HFXTALNOK        14            /*  HF crystal not stable */
+#define BITP_CLKG_CLK_STAT0_HFXTALOK         13            /*  HF crystal stable */
+#define BITP_CLKG_CLK_STAT0_HFXTAL           12            /*  HF crystal status */
+#define BITP_CLKG_CLK_STAT0_LFXTALNOK        10            /*  LF crystal not stable */
+#define BITP_CLKG_CLK_STAT0_LFXTALOK          9            /*  LF crystal stable */
+#define BITP_CLKG_CLK_STAT0_LFXTAL            8            /*  LF crystal status */
+#define BITP_CLKG_CLK_STAT0_SPLLUNLK          2            /*  System PLL unlock */
+#define BITP_CLKG_CLK_STAT0_SPLLLK            1            /*  System PLL lock */
+#define BITP_CLKG_CLK_STAT0_SPLL              0            /*  System PLL status */
+#define BITM_CLKG_CLK_STAT0_HFXTALNOK        (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t  ))    /*  HF crystal not stable */
+#define BITM_CLKG_CLK_STAT0_HFXTALOK         (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t  ))    /*  HF crystal stable */
+#define BITM_CLKG_CLK_STAT0_HFXTAL           (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t  ))    /*  HF crystal status */
+#define BITM_CLKG_CLK_STAT0_LFXTALNOK        (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t  ))    /*  LF crystal not stable */
+#define BITM_CLKG_CLK_STAT0_LFXTALOK         (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t  ))    /*  LF crystal stable */
+#define BITM_CLKG_CLK_STAT0_LFXTAL           (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t  ))    /*  LF crystal status */
+#define BITM_CLKG_CLK_STAT0_SPLLUNLK         (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t  ))    /*  System PLL unlock */
+#define BITM_CLKG_CLK_STAT0_SPLLLK           (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  System PLL lock */
+#define BITM_CLKG_CLK_STAT0_SPLL             (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  System PLL status */
+
+
+/* ============================================================================================================================
+        Bus matrix
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        BUSM0
+   ============================================================================================================================ */
+#define REG_BUSM0_ARBIT0                     0x4004C800            /*  BUSM0 Arbitration Priority Configuration for FLASH and SRAM0 */
+#define REG_BUSM0_ARBIT1                     0x4004C804            /*  BUSM0 Arbitration Priority Configuration for SRAM1 and SIP */
+#define REG_BUSM0_ARBIT2                     0x4004C808            /*  BUSM0 Arbitration Priority Configuration for APB32 and APB16 */
+#define REG_BUSM0_ARBIT3                     0x4004C80C            /*  BUSM0 Arbitration Priority Configuration for APB16 priority for core and for DMA1 */
+#define REG_BUSM0_ARBIT4                     0x4004C814            /*  BUSM0 Arbitration Priority Configuration for SRAM1 and SIP */
+
+/* ============================================================================================================================
+        BUSM Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          BUSM_ARBIT0                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_BUSM_ARBIT0_SRAM0_DMA0          20            /*  SRAM0 priority for DMA0 */
+#define BITP_BUSM_ARBIT0_SRAM0_SBUS          18            /*  SRAM0 priority for SBUS */
+#define BITP_BUSM_ARBIT0_SRAM0_DCODE         16            /*  SRAM0 priority for Dcode */
+#define BITP_BUSM_ARBIT0_FLSH_DMA0            4            /*  Flash priority for DMA0 */
+#define BITP_BUSM_ARBIT0_FLSH_SBUS            2            /*  Flash priority for SBUS */
+#define BITP_BUSM_ARBIT0_FLSH_DCODE           0            /*  Flash priority for DCODE */
+#define BITM_BUSM_ARBIT0_SRAM0_DMA0          (_ADI_MSK_3(0x00300000,0x00300000UL, uint32_t  ))    /*  SRAM0 priority for DMA0 */
+#define BITM_BUSM_ARBIT0_SRAM0_SBUS          (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t  ))    /*  SRAM0 priority for SBUS */
+#define BITM_BUSM_ARBIT0_SRAM0_DCODE         (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t  ))    /*  SRAM0 priority for Dcode */
+#define BITM_BUSM_ARBIT0_FLSH_DMA0           (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t  ))    /*  Flash priority for DMA0 */
+#define BITM_BUSM_ARBIT0_FLSH_SBUS           (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t  ))    /*  Flash priority for SBUS */
+#define BITM_BUSM_ARBIT0_FLSH_DCODE          (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t  ))    /*  Flash priority for DCODE */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          BUSM_ARBIT1                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_BUSM_ARBIT1_SIP_DMA0            20            /*  SIP priority for DMA0 */
+#define BITP_BUSM_ARBIT1_SIP_SBUS            18            /*  SIP priority for SBUS */
+#define BITP_BUSM_ARBIT1_SIP_DCODE           16            /*  SIP priority for DCODE */
+#define BITP_BUSM_ARBIT1_SRAM1_DMA0           4            /*  SRAM1 priority for DMA0 */
+#define BITP_BUSM_ARBIT1_SRAM1_SBUS           2            /*  SRAM1 priority for SBUS */
+#define BITP_BUSM_ARBIT1_SRAM1_DCODE          0            /*  SRAM1 priority for Dcode */
+#define BITM_BUSM_ARBIT1_SIP_DMA0            (_ADI_MSK_3(0x00300000,0x00300000UL, uint32_t  ))    /*  SIP priority for DMA0 */
+#define BITM_BUSM_ARBIT1_SIP_SBUS            (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t  ))    /*  SIP priority for SBUS */
+#define BITM_BUSM_ARBIT1_SIP_DCODE           (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t  ))    /*  SIP priority for DCODE */
+#define BITM_BUSM_ARBIT1_SRAM1_DMA0          (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t  ))    /*  SRAM1 priority for DMA0 */
+#define BITM_BUSM_ARBIT1_SRAM1_SBUS          (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t  ))    /*  SRAM1 priority for SBUS */
+#define BITM_BUSM_ARBIT1_SRAM1_DCODE         (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t  ))    /*  SRAM1 priority for Dcode */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          BUSM_ARBIT2                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_BUSM_ARBIT2_APB16_DMA0          20            /*  APB16 priority for DMA0 */
+#define BITP_BUSM_ARBIT2_APB16_SBUS          18            /*  APB16 priority for SBUS */
+#define BITP_BUSM_ARBIT2_APB16_DCODE         16            /*  APB16 priority for DCODE */
+#define BITP_BUSM_ARBIT2_APB32_DMA0           4            /*  APB32 priority for DMA0 */
+#define BITP_BUSM_ARBIT2_APB32_SBUS           2            /*  APB32 priority for SBUS */
+#define BITP_BUSM_ARBIT2_APB32_DCODE          0            /*  APB32 priority for DCODE */
+#define BITM_BUSM_ARBIT2_APB16_DMA0          (_ADI_MSK_3(0x00300000,0x00300000UL, uint32_t  ))    /*  APB16 priority for DMA0 */
+#define BITM_BUSM_ARBIT2_APB16_SBUS          (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t  ))    /*  APB16 priority for SBUS */
+#define BITM_BUSM_ARBIT2_APB16_DCODE         (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t  ))    /*  APB16 priority for DCODE */
+#define BITM_BUSM_ARBIT2_APB32_DMA0          (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t  ))    /*  APB32 priority for DMA0 */
+#define BITM_BUSM_ARBIT2_APB32_SBUS          (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t  ))    /*  APB32 priority for SBUS */
+#define BITM_BUSM_ARBIT2_APB32_DCODE         (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t  ))    /*  APB32 priority for DCODE */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          BUSM_ARBIT3                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_BUSM_ARBIT3_APB16_4DMA_DMA1     17            /*  APB16 for dma priority for DMA1 */
+#define BITP_BUSM_ARBIT3_APB16_4DMA_CORE     16            /*  APB16 for dma priority for CORE */
+#define BITP_BUSM_ARBIT3_APB16_DMA1           1            /*  APB16 priority for DMA1 */
+#define BITP_BUSM_ARBIT3_APB16_CORE           0            /*  APB16 priority for CORE */
+#define BITM_BUSM_ARBIT3_APB16_4DMA_DMA1     (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t  ))    /*  APB16 for dma priority for DMA1 */
+#define BITM_BUSM_ARBIT3_APB16_4DMA_CORE     (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t  ))    /*  APB16 for dma priority for CORE */
+#define BITM_BUSM_ARBIT3_APB16_DMA1          (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t  ))    /*  APB16 priority for DMA1 */
+#define BITM_BUSM_ARBIT3_APB16_CORE          (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))    /*  APB16 priority for CORE */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          BUSM_ARBIT4                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_BUSM_ARBIT4_SRAM2_DMA0           4            /*  SRAM2 priority for DMA0 */
+#define BITP_BUSM_ARBIT4_SRAM2_SBUS           2            /*  SRAM2 priority for SBUS */
+#define BITP_BUSM_ARBIT4_SRAM2_DCODE          0            /*  SRAM2 priority for Dcode */
+#define BITM_BUSM_ARBIT4_SRAM2_DMA0          (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t  ))    /*  SRAM2 priority for DMA0 */
+#define BITM_BUSM_ARBIT4_SRAM2_SBUS          (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t  ))    /*  SRAM2 priority for SBUS */
+#define BITM_BUSM_ARBIT4_SRAM2_DCODE         (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t  ))    /*  SRAM2 priority for Dcode */
+
+
+/* ============================================================================================================================
+        Parallel Test Interface
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        PTI0
+   ============================================================================================================================ */
+#define REG_PTI0_RST_ISR_STARTADDR           0x4004CD00            /*  PTI0 Reset ISR Start Address */
+#define REG_PTI0_RST_STACK_PTR               0x4004CD04            /*  PTI0 Reset Stack Pointer */
+#define REG_PTI0_CTL                         0x4004CD08            /*  PTI0 Parallel Test Interface Control Register */
+
+/* ============================================================================================================================
+        PTI Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          PTI_RST_ISR_STARTADDR                Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PTI_RST_ISR_STARTADDR_VALUE      0
+#define BITM_PTI_RST_ISR_STARTADDR_VALUE     (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PTI_RST_STACK_PTR                    Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PTI_RST_STACK_PTR_VALUE          0
+#define BITM_PTI_RST_STACK_PTR_VALUE         (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          PTI_CTL                              Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_PTI_CTL_EN                       0
+#define BITM_PTI_CTL_EN                      (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t  ))
+
+
+/* ============================================================================================================================
+        Cortex-M3 Interrupt Controller
+   ============================================================================================================================ */
+
+/* ============================================================================================================================
+        NVIC0
+   ============================================================================================================================ */
+#define REG_NVIC0_INTNUM                     0xE000E004            /*  NVIC0 Interrupt Control Type */
+#define REG_NVIC0_STKSTA                     0xE000E010            /*  NVIC0 Systick Control and Status */
+#define REG_NVIC0_STKLD                      0xE000E014            /*  NVIC0 Systick Reload Value */
+#define REG_NVIC0_STKVAL                     0xE000E018            /*  NVIC0 Systick Current Value */
+#define REG_NVIC0_STKCAL                     0xE000E01C            /*  NVIC0 Systick Calibration Value */
+#define REG_NVIC0_INTSETE0                   0xE000E100            /*  NVIC0 IRQ0..31 Set_Enable */
+#define REG_NVIC0_INTSETE1                   0xE000E104            /*  NVIC0 IRQ32..63 Set_Enable */
+#define REG_NVIC0_INTCLRE0                   0xE000E180            /*  NVIC0 IRQ0..31 Clear_Enable */
+#define REG_NVIC0_INTCLRE1                   0xE000E184            /*  NVIC0 IRQ32..63 Clear_Enable */
+#define REG_NVIC0_INTSETP0                   0xE000E200            /*  NVIC0 IRQ0..31 Set_Pending */
+#define REG_NVIC0_INTSETP1                   0xE000E204            /*  NVIC0 IRQ32..63 Set_Pending */
+#define REG_NVIC0_INTCLRP0                   0xE000E280            /*  NVIC0 IRQ0..31 Clear_Pending */
+#define REG_NVIC0_INTCLRP1                   0xE000E284            /*  NVIC0 IRQ32..63 Clear_Pending */
+#define REG_NVIC0_INTACT0                    0xE000E300            /*  NVIC0 IRQ0..31 Active Bit */
+#define REG_NVIC0_INTACT1                    0xE000E304            /*  NVIC0 IRQ32..63 Active Bit */
+#define REG_NVIC0_INTPRI0                    0xE000E400            /*  NVIC0 IRQ0..3 Priority */
+#define REG_NVIC0_INTPRI1                    0xE000E404            /*  NVIC0 IRQ4..7 Priority */
+#define REG_NVIC0_INTPRI2                    0xE000E408            /*  NVIC0 IRQ8..11 Priority */
+#define REG_NVIC0_INTPRI3                    0xE000E40C            /*  NVIC0 IRQ12..15 Priority */
+#define REG_NVIC0_INTPRI4                    0xE000E410            /*  NVIC0 IRQ16..19 Priority */
+#define REG_NVIC0_INTPRI5                    0xE000E414            /*  NVIC0 IRQ20..23 Priority */
+#define REG_NVIC0_INTPRI6                    0xE000E418            /*  NVIC0 IRQ24..27 Priority */
+#define REG_NVIC0_INTPRI7                    0xE000E41C            /*  NVIC0 IRQ28..31 Priority */
+#define REG_NVIC0_INTPRI8                    0xE000E420            /*  NVIC0 IRQ32..35 Priority */
+#define REG_NVIC0_INTPRI9                    0xE000E424            /*  NVIC0 IRQ36..39 Priority */
+#define REG_NVIC0_INTPRI10                   0xE000E428            /*  NVIC0 IRQ40..43 Priority */
+#define REG_NVIC0_INTCPID                    0xE000ED00            /*  NVIC0 CPUID Base */
+#define REG_NVIC0_INTSTA                     0xE000ED04            /*  NVIC0 Interrupt Control State */
+#define REG_NVIC0_INTVEC                     0xE000ED08            /*  NVIC0 Vector Table Offset */
+#define REG_NVIC0_INTAIRC                    0xE000ED0C            /*  NVIC0 Application Interrupt/Reset Control */
+#define REG_NVIC0_INTCON0                    0xE000ED10            /*  NVIC0 System Control */
+#define REG_NVIC0_INTCON1                    0xE000ED14            /*  NVIC0 Configuration Control */
+#define REG_NVIC0_INTSHPRIO0                 0xE000ED18            /*  NVIC0 System Handlers 4-7 Priority */
+#define REG_NVIC0_INTSHPRIO1                 0xE000ED1C            /*  NVIC0 System Handlers 8-11 Priority */
+#define REG_NVIC0_INTSHPRIO3                 0xE000ED20            /*  NVIC0 System Handlers 12-15 Priority */
+#define REG_NVIC0_INTSHCSR                   0xE000ED24            /*  NVIC0 System Handler Control and State */
+#define REG_NVIC0_INTCFSR                    0xE000ED28            /*  NVIC0 Configurable Fault Status */
+#define REG_NVIC0_INTHFSR                    0xE000ED2C            /*  NVIC0 Hard Fault Status */
+#define REG_NVIC0_INTDFSR                    0xE000ED30            /*  NVIC0 Debug Fault Status */
+#define REG_NVIC0_INTMMAR                    0xE000ED34            /*  NVIC0 Mem Manage Address */
+#define REG_NVIC0_INTBFAR                    0xE000ED38            /*  NVIC0 Bus Fault Address */
+#define REG_NVIC0_INTAFSR                    0xE000ED3C            /*  NVIC0 Auxiliary Fault Status */
+#define REG_NVIC0_INTPFR0                    0xE000ED40            /*  NVIC0 Processor Feature Register 0 */
+#define REG_NVIC0_INTPFR1                    0xE000ED44            /*  NVIC0 Processor Feature Register 1 */
+#define REG_NVIC0_INTDFR0                    0xE000ED48            /*  NVIC0 Debug Feature Register 0 */
+#define REG_NVIC0_INTAFR0                    0xE000ED4C            /*  NVIC0 Auxiliary Feature Register 0 */
+#define REG_NVIC0_INTMMFR0                   0xE000ED50            /*  NVIC0 Memory Model Feature Register 0 */
+#define REG_NVIC0_INTMMFR1                   0xE000ED54            /*  NVIC0 Memory Model Feature Register 1 */
+#define REG_NVIC0_INTMMFR2                   0xE000ED58            /*  NVIC0 Memory Model Feature Register 2 */
+#define REG_NVIC0_INTMMFR3                   0xE000ED5C            /*  NVIC0 Memory Model Feature Register 3 */
+#define REG_NVIC0_INTISAR0                   0xE000ED60            /*  NVIC0 ISA Feature Register 0 */
+#define REG_NVIC0_INTISAR1                   0xE000ED64            /*  NVIC0 ISA Feature Register 1 */
+#define REG_NVIC0_INTISAR2                   0xE000ED68            /*  NVIC0 ISA Feature Register 2 */
+#define REG_NVIC0_INTISAR3                   0xE000ED6C            /*  NVIC0 ISA Feature Register 3 */
+#define REG_NVIC0_INTISAR4                   0xE000ED70            /*  NVIC0 ISA Feature Register 4 */
+#define REG_NVIC0_INTTRGI                    0xE000EF00            /*  NVIC0 Software Trigger Interrupt Register */
+#define REG_NVIC0_INTPID4                    0xE000EFD0            /*  NVIC0 Peripheral Identification Register 4 */
+#define REG_NVIC0_INTPID5                    0xE000EFD4            /*  NVIC0 Peripheral Identification Register 5 */
+#define REG_NVIC0_INTPID6                    0xE000EFD8            /*  NVIC0 Peripheral Identification Register 6 */
+#define REG_NVIC0_INTPID7                    0xE000EFDC            /*  NVIC0 Peripheral Identification Register 7 */
+#define REG_NVIC0_INTPID0                    0xE000EFE0            /*  NVIC0 Peripheral Identification Bits7:0 */
+#define REG_NVIC0_INTPID1                    0xE000EFE4            /*  NVIC0 Peripheral Identification Bits15:8 */
+#define REG_NVIC0_INTPID2                    0xE000EFE8            /*  NVIC0 Peripheral Identification Bits16:23 */
+#define REG_NVIC0_INTPID3                    0xE000EFEC            /*  NVIC0 Peripheral Identification Bits24:31 */
+#define REG_NVIC0_INTCID0                    0xE000EFF0            /*  NVIC0 Component Identification Bits7:0 */
+#define REG_NVIC0_INTCID1                    0xE000EFF4            /*  NVIC0 Component Identification Bits15:8 */
+#define REG_NVIC0_INTCID2                    0xE000EFF8            /*  NVIC0 Component Identification Bits16:23 */
+#define REG_NVIC0_INTCID3                    0xE000EFFC            /*  NVIC0 Component Identification Bits24:31 */
+
+/* ============================================================================================================================
+        NVIC Register BitMasks, Positions & Enumerations 
+   ============================================================================================================================ */
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTNUM                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTNUM_VALUE                0            /*  Interrupt Control Type */
+#define BITM_NVIC_INTNUM_VALUE               (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Interrupt Control Type */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_STKSTA                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_STKSTA_VALUE                0            /*  Systick Control and Status */
+#define BITM_NVIC_STKSTA_VALUE               (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Systick Control and Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_STKLD                           Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_STKLD_VALUE                 0            /*  Systick Reload Value */
+#define BITM_NVIC_STKLD_VALUE                (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Systick Reload Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_STKVAL                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_STKVAL_VALUE                0            /*  Systick Current Value */
+#define BITM_NVIC_STKVAL_VALUE               (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Systick Current Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_STKCAL                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_STKCAL_VALUE                0            /*  Systick Calibration Value */
+#define BITM_NVIC_STKCAL_VALUE               (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Systick Calibration Value */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTSETE0                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTSETE0_VALUE              0            /*  IRQ0..31 Set_Enable */
+#define BITM_NVIC_INTSETE0_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ0..31 Set_Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTSETE1                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTSETE1_VALUE              0            /*  IRQ32..63 Set_Enable */
+#define BITM_NVIC_INTSETE1_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ32..63 Set_Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCLRE0                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCLRE0_VALUE              0            /*  IRQ0..31 Clear_Enable */
+#define BITM_NVIC_INTCLRE0_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ0..31 Clear_Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCLRE1                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCLRE1_VALUE              0            /*  IRQ32..63 Clear_Enable */
+#define BITM_NVIC_INTCLRE1_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ32..63 Clear_Enable */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTSETP0                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTSETP0_VALUE              0            /*  IRQ0..31 Set_Pending */
+#define BITM_NVIC_INTSETP0_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ0..31 Set_Pending */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTSETP1                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTSETP1_VALUE              0            /*  IRQ32..63 Set_Pending */
+#define BITM_NVIC_INTSETP1_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ32..63 Set_Pending */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCLRP0                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCLRP0_VALUE              0            /*  IRQ0..31 Clear_Pending */
+#define BITM_NVIC_INTCLRP0_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ0..31 Clear_Pending */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCLRP1                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCLRP1_VALUE              0            /*  IRQ32..63 Clear_Pending */
+#define BITM_NVIC_INTCLRP1_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ32..63 Clear_Pending */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTACT0                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTACT0_VALUE               0            /*  IRQ0..31 Active Bit */
+#define BITM_NVIC_INTACT0_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ0..31 Active Bit */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTACT1                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTACT1_VALUE               0            /*  IRQ32..63 Active Bit */
+#define BITM_NVIC_INTACT1_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ32..63 Active Bit */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI0                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI0_VALUE               0            /*  IRQ0..3 Priority */
+#define BITM_NVIC_INTPRI0_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ0..3 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI1                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI1_VALUE               0            /*  IRQ4..7 Priority */
+#define BITM_NVIC_INTPRI1_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ4..7 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI2                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI2_VALUE               0            /*  IRQ8..11 Priority */
+#define BITM_NVIC_INTPRI2_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ8..11 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI3                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI3_VALUE               0            /*  IRQ12..15 Priority */
+#define BITM_NVIC_INTPRI3_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ12..15 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI4                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI4_VALUE               0            /*  IRQ16..19 Priority */
+#define BITM_NVIC_INTPRI4_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ16..19 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI5                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI5_VALUE               0            /*  IRQ20..23 Priority */
+#define BITM_NVIC_INTPRI5_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ20..23 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI6                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI6_VALUE               0            /*  IRQ24..27 Priority */
+#define BITM_NVIC_INTPRI6_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ24..27 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI7                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI7_VALUE               0            /*  IRQ28..31 Priority */
+#define BITM_NVIC_INTPRI7_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ28..31 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI8                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI8_VALUE               0            /*  IRQ32..35 Priority */
+#define BITM_NVIC_INTPRI8_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ32..35 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI9                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI9_VALUE               0            /*  IRQ36..39 Priority */
+#define BITM_NVIC_INTPRI9_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ36..39 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPRI10                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPRI10_VALUE              0            /*  IRQ40..43 Priority */
+#define BITM_NVIC_INTPRI10_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  IRQ40..43 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCPID                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCPID_VALUE               0            /*  CPUID Base */
+#define BITM_NVIC_INTCPID_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  CPUID Base */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTSTA                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTSTA_VALUE                0            /*  Interrupt Control State */
+#define BITM_NVIC_INTSTA_VALUE               (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Interrupt Control State */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTVEC                          Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTVEC_VALUE                0            /*  Vector Table Offset */
+#define BITM_NVIC_INTVEC_VALUE               (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Vector Table Offset */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTAIRC                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTAIRC_VALUE               0            /*  Application Interrupt/Reset Control */
+#define BITM_NVIC_INTAIRC_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Application Interrupt/Reset Control */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCON0                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCON0_SLEEPDEEP           2            /*  deep sleep flag for HIBERNATE mode */
+#define BITP_NVIC_INTCON0_SLEEPONEXIT         1            /*  Sleeps the core on exit from an ISR */
+#define BITM_NVIC_INTCON0_SLEEPDEEP          (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t  ))    /*  deep sleep flag for HIBERNATE mode */
+#define BITM_NVIC_INTCON0_SLEEPONEXIT        (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t  ))    /*  Sleeps the core on exit from an ISR */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCON1                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCON1_VALUE               0            /*  Configuration Control */
+#define BITM_NVIC_INTCON1_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Configuration Control */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTSHPRIO0                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTSHPRIO0_VALUE            0            /*  System Handlers 4-7 Priority */
+#define BITM_NVIC_INTSHPRIO0_VALUE           (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  System Handlers 4-7 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTSHPRIO1                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTSHPRIO1_VALUE            0            /*  System Handlers 8-11 Priority */
+#define BITM_NVIC_INTSHPRIO1_VALUE           (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  System Handlers 8-11 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTSHPRIO3                      Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTSHPRIO3_VALUE            0            /*  System Handlers 12-15 Priority */
+#define BITM_NVIC_INTSHPRIO3_VALUE           (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  System Handlers 12-15 Priority */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTSHCSR                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTSHCSR_VALUE              0            /*  System Handler Control and State */
+#define BITM_NVIC_INTSHCSR_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  System Handler Control and State */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCFSR                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCFSR_VALUE               0            /*  Configurable Fault Status */
+#define BITM_NVIC_INTCFSR_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Configurable Fault Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTHFSR                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTHFSR_VALUE               0            /*  Hard Fault Status */
+#define BITM_NVIC_INTHFSR_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Hard Fault Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTDFSR                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTDFSR_VALUE               0            /*  Debug Fault Status */
+#define BITM_NVIC_INTDFSR_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Debug Fault Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTMMAR                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTMMAR_VALUE               0            /*  Mem Manage Address */
+#define BITM_NVIC_INTMMAR_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Mem Manage Address */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTBFAR                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTBFAR_VALUE               0            /*  Bus Fault Address */
+#define BITM_NVIC_INTBFAR_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Bus Fault Address */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTAFSR                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTAFSR_VALUE               0            /*  Auxiliary Fault Status */
+#define BITM_NVIC_INTAFSR_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Auxiliary Fault Status */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPFR0                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPFR0_VALUE               0            /*  Processor Feature Register 0 */
+#define BITM_NVIC_INTPFR0_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Processor Feature Register 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPFR1                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPFR1_VALUE               0            /*  Processor Feature Register 1 */
+#define BITM_NVIC_INTPFR1_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Processor Feature Register 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTDFR0                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTDFR0_VALUE               0            /*  Debug Feature Register 0 */
+#define BITM_NVIC_INTDFR0_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Debug Feature Register 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTAFR0                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTAFR0_VALUE               0            /*  Auxiliary Feature Register 0 */
+#define BITM_NVIC_INTAFR0_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Auxiliary Feature Register 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTMMFR0                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTMMFR0_VALUE              0            /*  Memory Model Feature Register 0 */
+#define BITM_NVIC_INTMMFR0_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Memory Model Feature Register 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTMMFR1                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTMMFR1_VALUE              0            /*  Memory Model Feature Register 1 */
+#define BITM_NVIC_INTMMFR1_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Memory Model Feature Register 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTMMFR2                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTMMFR2_VALUE              0            /*  Memory Model Feature Register 2 */
+#define BITM_NVIC_INTMMFR2_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Memory Model Feature Register 2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTMMFR3                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTMMFR3_VALUE              0            /*  Memory Model Feature Register 3 */
+#define BITM_NVIC_INTMMFR3_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Memory Model Feature Register 3 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTISAR0                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTISAR0_VALUE              0            /*  ISA Feature Register 0 */
+#define BITM_NVIC_INTISAR0_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  ISA Feature Register 0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTISAR1                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTISAR1_VALUE              0            /*  ISA Feature Register 1 */
+#define BITM_NVIC_INTISAR1_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  ISA Feature Register 1 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTISAR2                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTISAR2_VALUE              0            /*  ISA Feature Register 2 */
+#define BITM_NVIC_INTISAR2_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  ISA Feature Register 2 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTISAR3                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTISAR3_VALUE              0            /*  ISA Feature Register 3 */
+#define BITM_NVIC_INTISAR3_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  ISA Feature Register 3 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTISAR4                        Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTISAR4_VALUE              0            /*  ISA Feature Register 4 */
+#define BITM_NVIC_INTISAR4_VALUE             (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  ISA Feature Register 4 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTTRGI                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTTRGI_VALUE               0            /*  Software Trigger Interrupt Register */
+#define BITM_NVIC_INTTRGI_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Software Trigger Interrupt Register */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPID4                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPID4_VALUE               0            /*  Peripheral Identification Register 4 */
+#define BITM_NVIC_INTPID4_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Peripheral Identification Register 4 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPID5                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPID5_VALUE               0            /*  Peripheral Identification Register 5 */
+#define BITM_NVIC_INTPID5_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Peripheral Identification Register 5 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPID6                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPID6_VALUE               0            /*  Peripheral Identification Register 6 */
+#define BITM_NVIC_INTPID6_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Peripheral Identification Register 6 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPID7                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPID7_VALUE               0            /*  Peripheral Identification Register 7 */
+#define BITM_NVIC_INTPID7_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Peripheral Identification Register 7 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPID0                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPID0_VALUE               0            /*  Peripheral Identification Bits7:0 */
+#define BITM_NVIC_INTPID0_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Peripheral Identification Bits7:0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPID1                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPID1_VALUE               0            /*  Peripheral Identification Bits15:8 */
+#define BITM_NVIC_INTPID1_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Peripheral Identification Bits15:8 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPID2                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPID2_VALUE               0            /*  Peripheral Identification Bits16:23 */
+#define BITM_NVIC_INTPID2_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Peripheral Identification Bits16:23 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTPID3                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTPID3_VALUE               0            /*  Peripheral Identification Bits24:31 */
+#define BITM_NVIC_INTPID3_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Peripheral Identification Bits24:31 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCID0                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCID0_VALUE               0            /*  Component Identification Bits7:0 */
+#define BITM_NVIC_INTCID0_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Component Identification Bits7:0 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCID1                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCID1_VALUE               0            /*  Component Identification Bits15:8 */
+#define BITM_NVIC_INTCID1_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Component Identification Bits15:8 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCID2                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCID2_VALUE               0            /*  Component Identification Bits16:23 */
+#define BITM_NVIC_INTCID2_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Component Identification Bits16:23 */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+          NVIC_INTCID3                         Pos/Masks         Description
+   ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_NVIC_INTCID3_VALUE               0            /*  Component Identification Bits24:31 */
+#define BITM_NVIC_INTCID3_VALUE              (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t  ))    /*  Component Identification Bits24:31 */
+
+/* ====================================================================================================
+ *    Interrupt Definitions
+ * ==================================================================================================== */
+#define INTR_RESET                           (-15)		/* Cortex-M4 Reset */
+#define INTR_NonMaskableInt                  (-14)		/* Cortex-M4 Non-maskable Interrupt */
+#define INTR_HardFault                       (-13)		/* Cortex-M4 Hardware Fault */
+#define INTR_MemoryManagement                (-12)		/* Cortex-M4 Memory Management Interrupt */
+#define INTR_BusFault                        (-11)		/* Cortex-M4 Bus Fault */
+#define INTR_UsageFault                      (-10)		/* Cortex-M4 Usage Fault */
+#define INTR_SVCall                          ( -5)		/* Cortex-M4 SVCall Interrupt */
+#define INTR_DebugMonitor                    ( -4)		/* Cortex-M4 Debug Monitor */
+#define INTR_PendSV                          ( -2)		/* Cortex-M4 PendSV Interrupt */
+#define INTR_SysTick                         ( -1)		/* Cortex-M4 SysTick Interrupt */
+#define INTR_RTC1_EVT                          0		/* Event */
+#define INTR_XINT_EVT0                         1		/* External Wakeup Interrupt n */
+#define INTR_XINT_EVT1                         2		/* External Wakeup Interrupt n */
+#define INTR_XINT_EVT2                         3		/* External Wakeup Interrupt n */
+#define INTR_XINT_EVT3                         4		/* External Wakeup Interrupt n */
+#define INTR_WDT_EXP                           5		/* Expiration */
+#define INTR_PMG0_VREG_OVR                     6		/* Voltage Regulator (VREG) Overvoltage */
+#define INTR_PMG0_BATT_RANGE                   7		/* Battery Voltage (VBAT) Out of Range */
+#define INTR_RTC0_EVT                          8		/* Event */
+#define INTR_SYS_GPIO_INTA                     9		/* GPIO Interrupt A */
+#define INTR_SYS_GPIO_INTB                    10		/* GPIO Interrupt B */
+#define INTR_TMR0_EVT                         11		/* Event */
+#define INTR_TMR1_EVT                         12		/* Event */
+#define INTR_FLCC_EVT                         13		/* Event */
+#define INTR_UART0_EVT                        14		/* UART0 Event */
+#define INTR_SPI0_EVT                         15		/* Event */
+#define INTR_SPI2_EVT                         16		/* Event */
+#define INTR_I2C_SLV_EVT                      17		/* Slave Event */
+#define INTR_I2C_MST_EVT                      18		/* Master Event */
+#define INTR_DMA_CHAN_ERR                     19		/* Channel Error */
+#define INTR_DMA0_CH0_DONE                    20		/* Channel 0 Done */
+#define INTR_DMA0_CH1_DONE                    21		/* Channel 1 Done */
+#define INTR_DMA0_CH2_DONE                    22		/* Channel 2 Done */
+#define INTR_DMA0_CH3_DONE                    23		/* Channel 3 Done */
+#define INTR_DMA0_CH4_DONE                    24		/* Channel 4 Done */
+#define INTR_DMA0_CH5_DONE                    25		/* Channel 5 Done */
+#define INTR_DMA0_CH6_DONE                    26		/* Channel 6 Done */
+#define INTR_DMA0_CH7_DONE                    27		/* Channel 7 Done */
+#define INTR_DMA0_CH8_DONE                    28		/* Channel 8 Done */
+#define INTR_DMA0_CH9_DONE                    29		/* Channel 9 Done */
+#define INTR_DMA0_CH10_DONE                   30		/* Channel 10 Done */
+#define INTR_DMA0_CH11_DONE                   31		/* Channel 11 Done */
+#define INTR_DMA0_CH12_DONE                   32		/* Channel 12 Done */
+#define INTR_DMA0_CH13_DONE                   33		/* Channel 13 Done */
+#define INTR_DMA0_CH14_DONE                   34		/* Channel 14 Done */
+#define INTR_DMA0_CH15_DONE                   35		/* Channel 15 Done */
+#define INTR_SPORT_A_EVT                      36		/* Channel A Event */
+#define INTR_SPORT_B_EVT                      37		/* Channel B Event */
+#define INTR_CRYPT_EVT                        38		/* Event */
+#define INTR_DMA0_CH24_DONE                   39		/* Channel 24 Done */
+#define INTR_TMR2_EVT                         40		/* Event */
+#define INTR_CLKG_XTAL_OSC_EVT                41		/* Crystal Oscillator Event */
+#define INTR_SPI1_EVT                         42		/* Event */
+#define INTR_CLKG_PLL_EVT                     43		/* PLL Event */
+#define INTR_RNG0_EVT                         44		/* Event */
+#define INTR_BEEP_EVT                         45		/* Event */
+#define INTR_ADC0_EVT                         46		/* Event */
+#define INTR_DMA0_CH16_DONE                   56		/* Channel 16 Done */
+#define INTR_DMA0_CH17_DONE                   57		/* Channel 17 Done */
+#define INTR_DMA0_CH18_DONE                   58		/* Channel 18 Done */
+#define INTR_DMA0_CH19_DONE                   59		/* Channel 19 Done */
+#define INTR_DMA0_CH20_DONE                   60		/* Channel 20 Done */
+#define INTR_DMA0_CH21_DONE                   61		/* Channel 21 Done */
+#define INTR_DMA0_CH22_DONE                   62		/* Channel 22 Done */
+#define INTR_DMA0_CH23_DONE                   63		/* Channel 23 Done */
+#define INTR_UART1_EVT                        66		/* Event */
+#define INTR_DMA0_CH25_DONE                   67		/* Channel 25 Done */
+#define INTR_DMA0_CH26_DONE                   68		/* Channel 26 Done */
+#define INTR_TMR_RGB_EVT                      69		/* Event */
+#define INTR_CLKG_ROOTCLK_ERR                 71		/* Root Clock Error */
+
+
+#if defined (_MISRA_RULES)
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif	/* end ifndef _DEF_ADUCM4050_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_cdef.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_cdef.h
new file mode 100755
index 00000000000..067c0386a3d
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_cdef.h
@@ -0,0 +1,788 @@
+/* ================================================================================
+
+     Project      :   ADuCM4050
+     File         :   ADuCM4050_cdef.h
+     Description  :   C MMR Pointer Definitions
+
+     Date         :   Feb 7, 2017
+
+     Copyright (c) 2014-2017 Analog Devices, Inc.  All Rights Reserved.
+     This software is proprietary and confidential to Analog Devices, Inc. and
+     its licensors.
+
+     This file was auto-generated. Do not make local changes to this file.
+
+   ================================================================================ */
+
+#ifndef _ADUCM4050_CDEF_H
+#define _ADUCM4050_CDEF_H
+
+#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__))
+#include <stdint.h>
+#endif /* _LANGUAGE_C */
+
+/* pickup register bitfield and bit masks */
+#include "adi_ADuCM4050.h"
+
+
+#ifndef __IO
+#ifdef __cplusplus
+#define     __I     volatile      /* read-only */
+#define     __C
+#else
+#define     __I     volatile      /* read-only */
+#define     __C     const
+#endif
+#define     __O     volatile      /* write-only */
+#define     __IO    volatile      /* read-write */
+#endif
+#if defined (_MISRA_RULES)
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit")
+#pragma diag(suppress:misra_rule_19_7:"ADI header allows function-like macros")
+#pragma diag(suppress:misra_rule_19_13:"ADI headers can use the # and ## preprocessor operators")
+#endif /* _MISRA_RULES */
+
+
+/*  =================================================================================
+ *      General Purpose Timer (TMR0)
+ *  ================================================================================= */
+#define pREG_TMR0_LOAD                   ((__IO     uint16_t  *) REG_TMR0_LOAD)                   /*  16-bit Load Value */
+#define pREG_TMR0_CURCNT                 ((__I __C  uint16_t  *) REG_TMR0_CURCNT)                 /*  16-bit Timer Value */
+#define pREG_TMR0_CTL                    ((__IO     uint16_t  *) REG_TMR0_CTL)                    /*  Control */
+#define pREG_TMR0_CLRINT                 ((__O      uint16_t  *) REG_TMR0_CLRINT)                 /*  Clear Interrupt */
+#define pREG_TMR0_CAPTURE                ((__I __C  uint16_t  *) REG_TMR0_CAPTURE)                /*  Capture */
+#define pREG_TMR0_ALOAD                  ((__IO     uint16_t  *) REG_TMR0_ALOAD)                  /*  16-bit Load Value, Asynchronous */
+#define pREG_TMR0_ACURCNT                ((__I __C  uint16_t  *) REG_TMR0_ACURCNT)                /*  16-bit Timer Value, Asynchronous */
+#define pREG_TMR0_STAT                   ((__I __C  uint16_t  *) REG_TMR0_STAT)                   /*  Status */
+#define pREG_TMR0_PWMCTL                 ((__IO     uint16_t  *) REG_TMR0_PWMCTL)                 /*  PWM Control Register */
+#define pREG_TMR0_PWMMATCH               ((__IO     uint16_t  *) REG_TMR0_PWMMATCH)               /*  PWM Match Value */
+#define pREG_TMR0_EVENTSELECT            ((__IO     uint16_t  *) REG_TMR0_EVENTSELECT)            /*  Timer Event Selection Register */
+
+/*  =================================================================================
+ *      General Purpose Timer (TMR1)
+ *  ================================================================================= */
+#define pREG_TMR1_LOAD                   ((__IO     uint16_t  *) REG_TMR1_LOAD)                   /*  16-bit Load Value */
+#define pREG_TMR1_CURCNT                 ((__I __C  uint16_t  *) REG_TMR1_CURCNT)                 /*  16-bit Timer Value */
+#define pREG_TMR1_CTL                    ((__IO     uint16_t  *) REG_TMR1_CTL)                    /*  Control */
+#define pREG_TMR1_CLRINT                 ((__O      uint16_t  *) REG_TMR1_CLRINT)                 /*  Clear Interrupt */
+#define pREG_TMR1_CAPTURE                ((__I __C  uint16_t  *) REG_TMR1_CAPTURE)                /*  Capture */
+#define pREG_TMR1_ALOAD                  ((__IO     uint16_t  *) REG_TMR1_ALOAD)                  /*  16-bit Load Value, Asynchronous */
+#define pREG_TMR1_ACURCNT                ((__I __C  uint16_t  *) REG_TMR1_ACURCNT)                /*  16-bit Timer Value, Asynchronous */
+#define pREG_TMR1_STAT                   ((__I __C  uint16_t  *) REG_TMR1_STAT)                   /*  Status */
+#define pREG_TMR1_PWMCTL                 ((__IO     uint16_t  *) REG_TMR1_PWMCTL)                 /*  PWM Control Register */
+#define pREG_TMR1_PWMMATCH               ((__IO     uint16_t  *) REG_TMR1_PWMMATCH)               /*  PWM Match Value */
+#define pREG_TMR1_EVENTSELECT            ((__IO     uint16_t  *) REG_TMR1_EVENTSELECT)            /*  Timer Event Selection Register */
+
+/*  =================================================================================
+ *      General Purpose Timer (TMR2)
+ *  ================================================================================= */
+#define pREG_TMR2_LOAD                   ((__IO     uint16_t  *) REG_TMR2_LOAD)                   /*  16-bit Load Value */
+#define pREG_TMR2_CURCNT                 ((__I __C  uint16_t  *) REG_TMR2_CURCNT)                 /*  16-bit Timer Value */
+#define pREG_TMR2_CTL                    ((__IO     uint16_t  *) REG_TMR2_CTL)                    /*  Control */
+#define pREG_TMR2_CLRINT                 ((__O      uint16_t  *) REG_TMR2_CLRINT)                 /*  Clear Interrupt */
+#define pREG_TMR2_CAPTURE                ((__I __C  uint16_t  *) REG_TMR2_CAPTURE)                /*  Capture */
+#define pREG_TMR2_ALOAD                  ((__IO     uint16_t  *) REG_TMR2_ALOAD)                  /*  16-bit Load Value, Asynchronous */
+#define pREG_TMR2_ACURCNT                ((__I __C  uint16_t  *) REG_TMR2_ACURCNT)                /*  16-bit Timer Value, Asynchronous */
+#define pREG_TMR2_STAT                   ((__I __C  uint16_t  *) REG_TMR2_STAT)                   /*  Status */
+#define pREG_TMR2_PWMCTL                 ((__IO     uint16_t  *) REG_TMR2_PWMCTL)                 /*  PWM Control Register */
+#define pREG_TMR2_PWMMATCH               ((__IO     uint16_t  *) REG_TMR2_PWMMATCH)               /*  PWM Match Value */
+#define pREG_TMR2_EVENTSELECT            ((__IO     uint16_t  *) REG_TMR2_EVENTSELECT)            /*  Timer Event Selection Register */
+
+/*  =================================================================================
+ *      Timer_RGB with 3 PWM outputs (TMR_RGB)
+ *  ================================================================================= */
+#define pREG_TMR_RGB_LOAD                ((__IO     uint16_t  *) REG_TMR_RGB_LOAD)                /*  16-bit load value */
+#define pREG_TMR_RGB_CURCNT              ((__I __C  uint16_t  *) REG_TMR_RGB_CURCNT)              /*  16-bit timer value */
+#define pREG_TMR_RGB_CTL                 ((__IO     uint16_t  *) REG_TMR_RGB_CTL)                 /*  Control */
+#define pREG_TMR_RGB_CLRINT              ((__O      uint16_t  *) REG_TMR_RGB_CLRINT)              /*  Clear interrupt */
+#define pREG_TMR_RGB_CAPTURE             ((__I __C  uint16_t  *) REG_TMR_RGB_CAPTURE)             /*  Capture */
+#define pREG_TMR_RGB_ALOAD               ((__IO     uint16_t  *) REG_TMR_RGB_ALOAD)               /*  16-bit load value, asynchronous */
+#define pREG_TMR_RGB_ACURCNT             ((__I __C  uint16_t  *) REG_TMR_RGB_ACURCNT)             /*  16-bit timer value, asynchronous */
+#define pREG_TMR_RGB_STAT                ((__I __C  uint16_t  *) REG_TMR_RGB_STAT)                /*  Status */
+#define pREG_TMR_RGB_PWM0CTL             ((__IO     uint16_t  *) REG_TMR_RGB_PWM0CTL)             /*  PWM0 Control Register */
+#define pREG_TMR_RGB_PWM0MATCH           ((__IO     uint16_t  *) REG_TMR_RGB_PWM0MATCH)           /*  PWM0 Match Value */
+#define pREG_TMR_RGB_EVENTSELECT         ((__IO     uint16_t  *) REG_TMR_RGB_EVENTSELECT)         /*  Timer Event selection Register */
+#define pREG_TMR_RGB_PWM1CTL             ((__IO     uint16_t  *) REG_TMR_RGB_PWM1CTL)             /*  PWM1 Control Register */
+#define pREG_TMR_RGB_PWM1MATCH           ((__IO     uint16_t  *) REG_TMR_RGB_PWM1MATCH)           /*  PWM1 Match Value */
+#define pREG_TMR_RGB_PWM2CTL             ((__IO     uint16_t  *) REG_TMR_RGB_PWM2CTL)             /*  PWM2 Control Register */
+#define pREG_TMR_RGB_PWM2MATCH           ((__IO     uint16_t  *) REG_TMR_RGB_PWM2MATCH)           /*  PWM2 Match Value */
+
+/*  =================================================================================
+ *      Real-Time Clock (RTC0)
+ *  ================================================================================= */
+#define pREG_RTC0_CR0                    ((__IO     uint16_t  *) REG_RTC0_CR0)                    /*  RTC Control 0 */
+#define pREG_RTC0_SR0                    ((__IO     uint16_t  *) REG_RTC0_SR0)                    /*  RTC Status 0 */
+#define pREG_RTC0_SR1                    ((__I __C  uint16_t  *) REG_RTC0_SR1)                    /*  RTC Status 1 */
+#define pREG_RTC0_CNT0                   ((__IO     uint16_t  *) REG_RTC0_CNT0)                   /*  RTC Count 0 */
+#define pREG_RTC0_CNT1                   ((__IO     uint16_t  *) REG_RTC0_CNT1)                   /*  RTC Count 1 */
+#define pREG_RTC0_ALM0                   ((__IO     uint16_t  *) REG_RTC0_ALM0)                   /*  RTC Alarm 0 */
+#define pREG_RTC0_ALM1                   ((__IO     uint16_t  *) REG_RTC0_ALM1)                   /*  RTC Alarm 1 */
+#define pREG_RTC0_TRM                    ((__IO     uint16_t  *) REG_RTC0_TRM)                    /*  RTC Trim */
+#define pREG_RTC0_GWY                    ((__O      uint16_t  *) REG_RTC0_GWY)                    /*  RTC Gateway */
+#define pREG_RTC0_CR1                    ((__IO     uint16_t  *) REG_RTC0_CR1)                    /*  RTC Control 1 */
+#define pREG_RTC0_SR2                    ((__IO     uint16_t  *) REG_RTC0_SR2)                    /*  RTC Status 2 */
+#define pREG_RTC0_SNAP0                  ((__I __C  uint16_t  *) REG_RTC0_SNAP0)                  /*  RTC Snapshot 0 */
+#define pREG_RTC0_SNAP1                  ((__I __C  uint16_t  *) REG_RTC0_SNAP1)                  /*  RTC Snapshot 1 */
+#define pREG_RTC0_SNAP2                  ((__I __C  uint16_t  *) REG_RTC0_SNAP2)                  /*  RTC Snapshot 2 */
+#define pREG_RTC0_MOD                    ((__I __C  uint16_t  *) REG_RTC0_MOD)                    /*  RTC Modulo */
+#define pREG_RTC0_CNT2                   ((__I __C  uint16_t  *) REG_RTC0_CNT2)                   /*  RTC Count 2 */
+#define pREG_RTC0_ALM2                   ((__IO     uint16_t  *) REG_RTC0_ALM2)                   /*  RTC Alarm 2 */
+#define pREG_RTC0_SR3                    ((__IO     uint16_t  *) REG_RTC0_SR3)                    /*  RTC Status 3 */
+#define pREG_RTC0_CR2IC                  ((__IO     uint16_t  *) REG_RTC0_CR2IC)                  /*  RTC Control 2 for Configuring Input Capture Channels */
+#define pREG_RTC0_CR3SS                  ((__IO     uint16_t  *) REG_RTC0_CR3SS)                  /*  RTC Control 3 for Configuring SensorStrobe Channel */
+#define pREG_RTC0_CR4SS                  ((__IO     uint16_t  *) REG_RTC0_CR4SS)                  /*  RTC Control 4 for Configuring SensorStrobe Channel */
+#define pREG_RTC0_SSMSK                  ((__IO     uint16_t  *) REG_RTC0_SSMSK)                  /*  RTC Mask for SensorStrobe Channel */
+#define pREG_RTC0_IC2                    ((__I __C  uint16_t  *) REG_RTC0_IC2)                    /*  RTC Input Capture Channel 2 */
+#define pREG_RTC0_IC3                    ((__I __C  uint16_t  *) REG_RTC0_IC3)                    /*  RTC Input Capture Channel 3 */
+#define pREG_RTC0_IC4                    ((__I __C  uint16_t  *) REG_RTC0_IC4)                    /*  RTC Input Capture Channel 4 */
+#define pREG_RTC0_SS1                    ((__IO     uint16_t  *) REG_RTC0_SS1)                    /*  RTC SensorStrobe Channel 1 */
+#define pREG_RTC0_SS2                    ((__IO     uint16_t  *) REG_RTC0_SS2)                    /*  RTC SensorStrobe Channel 2 */
+#define pREG_RTC0_SS3                    ((__IO     uint16_t  *) REG_RTC0_SS3)                    /*  RTC SensorStrobe Channel 3 */
+#define pREG_RTC0_SS4                    ((__IO     uint16_t  *) REG_RTC0_SS4)                    /*  RTC SensorStrobe Channel 4 */
+#define pREG_RTC0_SR4                    ((__I __C  uint16_t  *) REG_RTC0_SR4)                    /*  RTC Status 4 */
+#define pREG_RTC0_SR5                    ((__I __C  uint16_t  *) REG_RTC0_SR5)                    /*  RTC Status 5 */
+#define pREG_RTC0_SR6                    ((__I __C  uint16_t  *) REG_RTC0_SR6)                    /*  RTC Status 6 */
+#define pREG_RTC0_SS1TGT                 ((__I __C  uint16_t  *) REG_RTC0_SS1TGT)                 /*  RTC SensorStrobe Channel 1 Target */
+#define pREG_RTC0_FRZCNT                 ((__I __C  uint16_t  *) REG_RTC0_FRZCNT)                 /*  RTC Freeze Count */
+#define pREG_RTC0_SS2TGT                 ((__I __C  uint16_t  *) REG_RTC0_SS2TGT)                 /*  RTC SensorStrobe Channel 2 Target */
+#define pREG_RTC0_SS3TGT                 ((__I __C  uint16_t  *) REG_RTC0_SS3TGT)                 /*  RTC SensorStrobe Channel 3 Target */
+#define pREG_RTC0_SS1LOWDUR              ((__IO     uint16_t  *) REG_RTC0_SS1LOWDUR)              /*  RTC Auto-Reload Low Duration for SensorStrobe Channel 1 */
+#define pREG_RTC0_SS2LOWDUR              ((__IO     uint16_t  *) REG_RTC0_SS2LOWDUR)              /*  RTC Auto-Reload Low Duration for SensorStrobe Channel 2 */
+#define pREG_RTC0_SS3LOWDUR              ((__IO     uint16_t  *) REG_RTC0_SS3LOWDUR)              /*  RTC Auto-Reload Low Duration for SensorStrobe Channel 3 */
+#define pREG_RTC0_SS1HIGHDUR             ((__IO     uint16_t  *) REG_RTC0_SS1HIGHDUR)             /*  RTC Auto-Reload High Duration for SensorStrobe Channel 1 */
+#define pREG_RTC0_SS2HIGHDUR             ((__IO     uint16_t  *) REG_RTC0_SS2HIGHDUR)             /*  RTC Auto-Reload High Duration for SensorStrobe Channel 2 */
+#define pREG_RTC0_SS3HIGHDUR             ((__IO     uint16_t  *) REG_RTC0_SS3HIGHDUR)             /*  RTC Auto-Reload High Duration for SensorStrobe Channel 3 */
+#define pREG_RTC0_SSMSKOT                ((__IO     uint16_t  *) REG_RTC0_SSMSKOT)                /*  RTC Masks for SensorStrobe Channels on Time Control */
+#define pREG_RTC0_CR5SSS                 ((__IO     uint16_t  *) REG_RTC0_CR5SSS)                 /*  RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling */
+#define pREG_RTC0_CR6SSS                 ((__IO     uint16_t  *) REG_RTC0_CR6SSS)                 /*  RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge */
+#define pREG_RTC0_CR7SSS                 ((__IO     uint16_t  *) REG_RTC0_CR7SSS)                 /*  RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity */
+#define pREG_RTC0_SR7                    ((__IO     uint16_t  *) REG_RTC0_SR7)                    /*  RTC Status 7 */
+#define pREG_RTC0_SR8                    ((__I __C  uint16_t  *) REG_RTC0_SR8)                    /*  RTC Status 8 */
+#define pREG_RTC0_SR9                    ((__I __C  uint16_t  *) REG_RTC0_SR9)                    /*  RTC Status 9 */
+#define pREG_RTC0_GPMUX0                 ((__IO     uint16_t  *) REG_RTC0_GPMUX0)                 /*  RTC GPIO Pin Mux Control Register 0 */
+#define pREG_RTC0_GPMUX1                 ((__IO     uint16_t  *) REG_RTC0_GPMUX1)                 /*  RTC GPIO Pin Mux Control Register 1 */
+
+/*  =================================================================================
+ *      Real-Time Clock (RTC1)
+ *  ================================================================================= */
+#define pREG_RTC1_CR0                    ((__IO     uint16_t  *) REG_RTC1_CR0)                    /*  RTC Control 0 */
+#define pREG_RTC1_SR0                    ((__IO     uint16_t  *) REG_RTC1_SR0)                    /*  RTC Status 0 */
+#define pREG_RTC1_SR1                    ((__I __C  uint16_t  *) REG_RTC1_SR1)                    /*  RTC Status 1 */
+#define pREG_RTC1_CNT0                   ((__IO     uint16_t  *) REG_RTC1_CNT0)                   /*  RTC Count 0 */
+#define pREG_RTC1_CNT1                   ((__IO     uint16_t  *) REG_RTC1_CNT1)                   /*  RTC Count 1 */
+#define pREG_RTC1_ALM0                   ((__IO     uint16_t  *) REG_RTC1_ALM0)                   /*  RTC Alarm 0 */
+#define pREG_RTC1_ALM1                   ((__IO     uint16_t  *) REG_RTC1_ALM1)                   /*  RTC Alarm 1 */
+#define pREG_RTC1_TRM                    ((__IO     uint16_t  *) REG_RTC1_TRM)                    /*  RTC Trim */
+#define pREG_RTC1_GWY                    ((__O      uint16_t  *) REG_RTC1_GWY)                    /*  RTC Gateway */
+#define pREG_RTC1_CR1                    ((__IO     uint16_t  *) REG_RTC1_CR1)                    /*  RTC Control 1 */
+#define pREG_RTC1_SR2                    ((__IO     uint16_t  *) REG_RTC1_SR2)                    /*  RTC Status 2 */
+#define pREG_RTC1_SNAP0                  ((__I __C  uint16_t  *) REG_RTC1_SNAP0)                  /*  RTC Snapshot 0 */
+#define pREG_RTC1_SNAP1                  ((__I __C  uint16_t  *) REG_RTC1_SNAP1)                  /*  RTC Snapshot 1 */
+#define pREG_RTC1_SNAP2                  ((__I __C  uint16_t  *) REG_RTC1_SNAP2)                  /*  RTC Snapshot 2 */
+#define pREG_RTC1_MOD                    ((__I __C  uint16_t  *) REG_RTC1_MOD)                    /*  RTC Modulo */
+#define pREG_RTC1_CNT2                   ((__I __C  uint16_t  *) REG_RTC1_CNT2)                   /*  RTC Count 2 */
+#define pREG_RTC1_ALM2                   ((__IO     uint16_t  *) REG_RTC1_ALM2)                   /*  RTC Alarm 2 */
+#define pREG_RTC1_SR3                    ((__IO     uint16_t  *) REG_RTC1_SR3)                    /*  RTC Status 3 */
+#define pREG_RTC1_CR2IC                  ((__IO     uint16_t  *) REG_RTC1_CR2IC)                  /*  RTC Control 2 for Configuring Input Capture Channels */
+#define pREG_RTC1_CR3SS                  ((__IO     uint16_t  *) REG_RTC1_CR3SS)                  /*  RTC Control 3 for Configuring SensorStrobe Channel */
+#define pREG_RTC1_CR4SS                  ((__IO     uint16_t  *) REG_RTC1_CR4SS)                  /*  RTC Control 4 for Configuring SensorStrobe Channel */
+#define pREG_RTC1_SSMSK                  ((__IO     uint16_t  *) REG_RTC1_SSMSK)                  /*  RTC Mask for SensorStrobe Channel */
+#define pREG_RTC1_IC2                    ((__I __C  uint16_t  *) REG_RTC1_IC2)                    /*  RTC Input Capture Channel 2 */
+#define pREG_RTC1_IC3                    ((__I __C  uint16_t  *) REG_RTC1_IC3)                    /*  RTC Input Capture Channel 3 */
+#define pREG_RTC1_IC4                    ((__I __C  uint16_t  *) REG_RTC1_IC4)                    /*  RTC Input Capture Channel 4 */
+#define pREG_RTC1_SS1                    ((__IO     uint16_t  *) REG_RTC1_SS1)                    /*  RTC SensorStrobe Channel 1 */
+#define pREG_RTC1_SS2                    ((__IO     uint16_t  *) REG_RTC1_SS2)                    /*  RTC SensorStrobe Channel 2 */
+#define pREG_RTC1_SS3                    ((__IO     uint16_t  *) REG_RTC1_SS3)                    /*  RTC SensorStrobe Channel 3 */
+#define pREG_RTC1_SS4                    ((__IO     uint16_t  *) REG_RTC1_SS4)                    /*  RTC SensorStrobe Channel 4 */
+#define pREG_RTC1_SR4                    ((__I __C  uint16_t  *) REG_RTC1_SR4)                    /*  RTC Status 4 */
+#define pREG_RTC1_SR5                    ((__I __C  uint16_t  *) REG_RTC1_SR5)                    /*  RTC Status 5 */
+#define pREG_RTC1_SR6                    ((__I __C  uint16_t  *) REG_RTC1_SR6)                    /*  RTC Status 6 */
+#define pREG_RTC1_SS1TGT                 ((__I __C  uint16_t  *) REG_RTC1_SS1TGT)                 /*  RTC SensorStrobe Channel 1 Target */
+#define pREG_RTC1_FRZCNT                 ((__I __C  uint16_t  *) REG_RTC1_FRZCNT)                 /*  RTC Freeze Count */
+#define pREG_RTC1_SS2TGT                 ((__I __C  uint16_t  *) REG_RTC1_SS2TGT)                 /*  RTC SensorStrobe Channel 2 Target */
+#define pREG_RTC1_SS3TGT                 ((__I __C  uint16_t  *) REG_RTC1_SS3TGT)                 /*  RTC SensorStrobe Channel 3 Target */
+#define pREG_RTC1_SS1LOWDUR              ((__IO     uint16_t  *) REG_RTC1_SS1LOWDUR)              /*  RTC Auto-Reload Low Duration for SensorStrobe Channel 1 */
+#define pREG_RTC1_SS2LOWDUR              ((__IO     uint16_t  *) REG_RTC1_SS2LOWDUR)              /*  RTC Auto-Reload Low Duration for SensorStrobe Channel 2 */
+#define pREG_RTC1_SS3LOWDUR              ((__IO     uint16_t  *) REG_RTC1_SS3LOWDUR)              /*  RTC Auto-Reload Low Duration for SensorStrobe Channel 3 */
+#define pREG_RTC1_SS1HIGHDUR             ((__IO     uint16_t  *) REG_RTC1_SS1HIGHDUR)             /*  RTC Auto-Reload High Duration for SensorStrobe Channel 1 */
+#define pREG_RTC1_SS2HIGHDUR             ((__IO     uint16_t  *) REG_RTC1_SS2HIGHDUR)             /*  RTC Auto-Reload High Duration for SensorStrobe Channel 2 */
+#define pREG_RTC1_SS3HIGHDUR             ((__IO     uint16_t  *) REG_RTC1_SS3HIGHDUR)             /*  RTC Auto-Reload High Duration for SensorStrobe Channel 3 */
+#define pREG_RTC1_SSMSKOT                ((__IO     uint16_t  *) REG_RTC1_SSMSKOT)                /*  RTC Masks for SensorStrobe Channels on Time Control */
+#define pREG_RTC1_CR5SSS                 ((__IO     uint16_t  *) REG_RTC1_CR5SSS)                 /*  RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling */
+#define pREG_RTC1_CR6SSS                 ((__IO     uint16_t  *) REG_RTC1_CR6SSS)                 /*  RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge */
+#define pREG_RTC1_CR7SSS                 ((__IO     uint16_t  *) REG_RTC1_CR7SSS)                 /*  RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity */
+#define pREG_RTC1_SR7                    ((__IO     uint16_t  *) REG_RTC1_SR7)                    /*  RTC Status 7 */
+#define pREG_RTC1_SR8                    ((__I __C  uint16_t  *) REG_RTC1_SR8)                    /*  RTC Status 8 */
+#define pREG_RTC1_SR9                    ((__I __C  uint16_t  *) REG_RTC1_SR9)                    /*  RTC Status 9 */
+#define pREG_RTC1_GPMUX0                 ((__IO     uint16_t  *) REG_RTC1_GPMUX0)                 /*  RTC GPIO Pin Mux Control Register 0 */
+#define pREG_RTC1_GPMUX1                 ((__IO     uint16_t  *) REG_RTC1_GPMUX1)                 /*  RTC GPIO Pin Mux Control Register 1 */
+
+/*  =================================================================================
+ *      System Identification and Debug Enable (SYS)
+ *  ================================================================================= */
+#define pREG_SYS_ADIID                   ((__I __C  uint16_t  *) REG_SYS_ADIID)                   /*  ADI Identification */
+#define pREG_SYS_CHIPID                  ((__I __C  uint16_t  *) REG_SYS_CHIPID)                  /*  Chip Identifier */
+#define pREG_SYS_SWDEN                   ((__O      uint16_t  *) REG_SYS_SWDEN)                   /*  Serial Wire Debug Enable */
+
+/*  =================================================================================
+ *      Watchdog Timer (WDT0)
+ *  ================================================================================= */
+#define pREG_WDT0_LOAD                   ((__IO     uint16_t  *) REG_WDT0_LOAD)                   /*  Load Value */
+#define pREG_WDT0_CCNT                   ((__I __C  uint16_t  *) REG_WDT0_CCNT)                   /*  Current Count Value */
+#define pREG_WDT0_CTL                    ((__IO     uint16_t  *) REG_WDT0_CTL)                    /*  Control */
+#define pREG_WDT0_RESTART                ((__O      uint16_t  *) REG_WDT0_RESTART)                /*  Clear Interrupt */
+#define pREG_WDT0_STAT                   ((__I __C  uint16_t  *) REG_WDT0_STAT)                   /*  Status */
+
+/*  =================================================================================
+ *      I2C Master/Slave (I2C0)
+ *  ================================================================================= */
+#define pREG_I2C0_MCTL                   ((__IO     uint16_t  *) REG_I2C0_MCTL)                   /*  Master Control */
+#define pREG_I2C0_MSTAT                  ((__IO     uint16_t  *) REG_I2C0_MSTAT)                  /*  Master Status */
+#define pREG_I2C0_MRX                    ((__I __C  uint16_t  *) REG_I2C0_MRX)                    /*  Master Receive Data */
+#define pREG_I2C0_MTX                    ((__IO     uint16_t  *) REG_I2C0_MTX)                    /*  Master Transmit Data */
+#define pREG_I2C0_MRXCNT                 ((__IO     uint16_t  *) REG_I2C0_MRXCNT)                 /*  Master Receive Data Count */
+#define pREG_I2C0_MCRXCNT                ((__I __C  uint16_t  *) REG_I2C0_MCRXCNT)                /*  Master Current Receive Data Count */
+#define pREG_I2C0_ADDR1                  ((__IO     uint16_t  *) REG_I2C0_ADDR1)                  /*  Master Address Byte 1 */
+#define pREG_I2C0_ADDR2                  ((__IO     uint16_t  *) REG_I2C0_ADDR2)                  /*  Master Address Byte 2 */
+#define pREG_I2C0_BYT                    ((__IO     uint16_t  *) REG_I2C0_BYT)                    /*  Start Byte */
+#define pREG_I2C0_DIV                    ((__IO     uint16_t  *) REG_I2C0_DIV)                    /*  Serial Clock Period Divisor */
+#define pREG_I2C0_SCTL                   ((__IO     uint16_t  *) REG_I2C0_SCTL)                   /*  Slave Control */
+#define pREG_I2C0_SSTAT                  ((__IO     uint16_t  *) REG_I2C0_SSTAT)                  /*  Slave I2C Status/Error/IRQ */
+#define pREG_I2C0_SRX                    ((__I __C  uint16_t  *) REG_I2C0_SRX)                    /*  Slave Receive */
+#define pREG_I2C0_STX                    ((__IO     uint16_t  *) REG_I2C0_STX)                    /*  Slave Transmit */
+#define pREG_I2C0_ALT                    ((__IO     uint16_t  *) REG_I2C0_ALT)                    /*  Hardware General Call ID */
+#define pREG_I2C0_ID0                    ((__IO     uint16_t  *) REG_I2C0_ID0)                    /*  First Slave Address Device ID */
+#define pREG_I2C0_ID1                    ((__IO     uint16_t  *) REG_I2C0_ID1)                    /*  Second Slave Address Device ID */
+#define pREG_I2C0_ID2                    ((__IO     uint16_t  *) REG_I2C0_ID2)                    /*  Third Slave Address Device ID */
+#define pREG_I2C0_ID3                    ((__IO     uint16_t  *) REG_I2C0_ID3)                    /*  Fourth Slave Address Device ID */
+#define pREG_I2C0_STAT                   ((__IO     uint16_t  *) REG_I2C0_STAT)                   /*  Master and Slave FIFO Status */
+#define pREG_I2C0_SHCTL                  ((__O      uint16_t  *) REG_I2C0_SHCTL)                  /*  Shared Control */
+#define pREG_I2C0_TCTL                   ((__IO     uint16_t  *) REG_I2C0_TCTL)                   /*  Timing Control Register */
+#define pREG_I2C0_ASTRETCH_SCL           ((__IO     uint16_t  *) REG_I2C0_ASTRETCH_SCL)           /*  Automatic Stretch SCL */
+
+/*  =================================================================================
+ *      Serial Peripheral Interface (SPI0)
+ *  ================================================================================= */
+#define pREG_SPI0_STAT                   ((__IO     uint16_t  *) REG_SPI0_STAT)                   /*  Status */
+#define pREG_SPI0_RX                     ((__I __C  uint16_t  *) REG_SPI0_RX)                     /*  Receive */
+#define pREG_SPI0_TX                     ((__O      uint16_t  *) REG_SPI0_TX)                     /*  Transmit */
+#define pREG_SPI0_DIV                    ((__IO     uint16_t  *) REG_SPI0_DIV)                    /*  SPI Baud Rate Selection */
+#define pREG_SPI0_CTL                    ((__IO     uint16_t  *) REG_SPI0_CTL)                    /*  SPI Configuration */
+#define pREG_SPI0_IEN                    ((__IO     uint16_t  *) REG_SPI0_IEN)                    /*  SPI Interrupts Enable */
+#define pREG_SPI0_CNT                    ((__IO     uint16_t  *) REG_SPI0_CNT)                    /*  Transfer Byte Count */
+#define pREG_SPI0_DMA                    ((__IO     uint16_t  *) REG_SPI0_DMA)                    /*  SPI DMA Enable */
+#define pREG_SPI0_FIFO_STAT              ((__I __C  uint16_t  *) REG_SPI0_FIFO_STAT)              /*  FIFO Status */
+#define pREG_SPI0_RD_CTL                 ((__IO     uint16_t  *) REG_SPI0_RD_CTL)                 /*  Read Control */
+#define pREG_SPI0_FLOW_CTL               ((__IO     uint16_t  *) REG_SPI0_FLOW_CTL)               /*  Flow Control */
+#define pREG_SPI0_WAIT_TMR               ((__IO     uint16_t  *) REG_SPI0_WAIT_TMR)               /*  Wait Timer for Flow Control */
+#define pREG_SPI0_CS_CTL                 ((__IO     uint16_t  *) REG_SPI0_CS_CTL)                 /*  Chip Select Control for Multi-slave Connections */
+#define pREG_SPI0_CS_OVERRIDE            ((__IO     uint16_t  *) REG_SPI0_CS_OVERRIDE)            /*  Chip Select Override */
+
+/*  =================================================================================
+ *      Serial Peripheral Interface (SPI1)
+ *  ================================================================================= */
+#define pREG_SPI1_STAT                   ((__IO     uint16_t  *) REG_SPI1_STAT)                   /*  Status */
+#define pREG_SPI1_RX                     ((__I __C  uint16_t  *) REG_SPI1_RX)                     /*  Receive */
+#define pREG_SPI1_TX                     ((__O      uint16_t  *) REG_SPI1_TX)                     /*  Transmit */
+#define pREG_SPI1_DIV                    ((__IO     uint16_t  *) REG_SPI1_DIV)                    /*  SPI Baud Rate Selection */
+#define pREG_SPI1_CTL                    ((__IO     uint16_t  *) REG_SPI1_CTL)                    /*  SPI Configuration */
+#define pREG_SPI1_IEN                    ((__IO     uint16_t  *) REG_SPI1_IEN)                    /*  SPI Interrupts Enable */
+#define pREG_SPI1_CNT                    ((__IO     uint16_t  *) REG_SPI1_CNT)                    /*  Transfer Byte Count */
+#define pREG_SPI1_DMA                    ((__IO     uint16_t  *) REG_SPI1_DMA)                    /*  SPI DMA Enable */
+#define pREG_SPI1_FIFO_STAT              ((__I __C  uint16_t  *) REG_SPI1_FIFO_STAT)              /*  FIFO Status */
+#define pREG_SPI1_RD_CTL                 ((__IO     uint16_t  *) REG_SPI1_RD_CTL)                 /*  Read Control */
+#define pREG_SPI1_FLOW_CTL               ((__IO     uint16_t  *) REG_SPI1_FLOW_CTL)               /*  Flow Control */
+#define pREG_SPI1_WAIT_TMR               ((__IO     uint16_t  *) REG_SPI1_WAIT_TMR)               /*  Wait Timer for Flow Control */
+#define pREG_SPI1_CS_CTL                 ((__IO     uint16_t  *) REG_SPI1_CS_CTL)                 /*  Chip Select Control for Multi-slave Connections */
+#define pREG_SPI1_CS_OVERRIDE            ((__IO     uint16_t  *) REG_SPI1_CS_OVERRIDE)            /*  Chip Select Override */
+
+/*  =================================================================================
+ *      Serial Peripheral Interface (SPI2)
+ *  ================================================================================= */
+#define pREG_SPI2_STAT                   ((__IO     uint16_t  *) REG_SPI2_STAT)                   /*  Status */
+#define pREG_SPI2_RX                     ((__I __C  uint16_t  *) REG_SPI2_RX)                     /*  Receive */
+#define pREG_SPI2_TX                     ((__O      uint16_t  *) REG_SPI2_TX)                     /*  Transmit */
+#define pREG_SPI2_DIV                    ((__IO     uint16_t  *) REG_SPI2_DIV)                    /*  SPI Baud Rate Selection */
+#define pREG_SPI2_CTL                    ((__IO     uint16_t  *) REG_SPI2_CTL)                    /*  SPI Configuration */
+#define pREG_SPI2_IEN                    ((__IO     uint16_t  *) REG_SPI2_IEN)                    /*  SPI Interrupts Enable */
+#define pREG_SPI2_CNT                    ((__IO     uint16_t  *) REG_SPI2_CNT)                    /*  Transfer Byte Count */
+#define pREG_SPI2_DMA                    ((__IO     uint16_t  *) REG_SPI2_DMA)                    /*  SPI DMA Enable */
+#define pREG_SPI2_FIFO_STAT              ((__I __C  uint16_t  *) REG_SPI2_FIFO_STAT)              /*  FIFO Status */
+#define pREG_SPI2_RD_CTL                 ((__IO     uint16_t  *) REG_SPI2_RD_CTL)                 /*  Read Control */
+#define pREG_SPI2_FLOW_CTL               ((__IO     uint16_t  *) REG_SPI2_FLOW_CTL)               /*  Flow Control */
+#define pREG_SPI2_WAIT_TMR               ((__IO     uint16_t  *) REG_SPI2_WAIT_TMR)               /*  Wait Timer for Flow Control */
+#define pREG_SPI2_CS_CTL                 ((__IO     uint16_t  *) REG_SPI2_CS_CTL)                 /*  Chip Select Control for Multi-slave Connections */
+#define pREG_SPI2_CS_OVERRIDE            ((__IO     uint16_t  *) REG_SPI2_CS_OVERRIDE)            /*  Chip Select Override */
+
+/*  =================================================================================
+ *       (UART0)
+ *  ================================================================================= */
+#define pREG_UART0_TX                    ((__O      uint16_t  *) REG_UART0_TX)                    /*  Transmit Holding Register */
+#define pREG_UART0_RX                    ((__I __C  uint16_t  *) REG_UART0_RX)                    /*  Receive Buffer Register */
+#define pREG_UART0_IEN                   ((__IO     uint16_t  *) REG_UART0_IEN)                   /*  Interrupt Enable */
+#define pREG_UART0_IIR                   ((__I __C  uint16_t  *) REG_UART0_IIR)                   /*  Interrupt ID */
+#define pREG_UART0_LCR                   ((__IO     uint16_t  *) REG_UART0_LCR)                   /*  Line Control */
+#define pREG_UART0_MCR                   ((__IO     uint16_t  *) REG_UART0_MCR)                   /*  Modem Control */
+#define pREG_UART0_LSR                   ((__I __C  uint16_t  *) REG_UART0_LSR)                   /*  Line Status */
+#define pREG_UART0_MSR                   ((__I __C  uint16_t  *) REG_UART0_MSR)                   /*  Modem Status */
+#define pREG_UART0_SCR                   ((__IO     uint16_t  *) REG_UART0_SCR)                   /*  Scratch Buffer */
+#define pREG_UART0_FCR                   ((__IO     uint16_t  *) REG_UART0_FCR)                   /*  FIFO Control */
+#define pREG_UART0_FBR                   ((__IO     uint16_t  *) REG_UART0_FBR)                   /*  Fractional Baud Rate */
+#define pREG_UART0_DIV                   ((__IO     uint16_t  *) REG_UART0_DIV)                   /*  Baud Rate Divider */
+#define pREG_UART0_LCR2                  ((__IO     uint16_t  *) REG_UART0_LCR2)                  /*  Second Line Control */
+#define pREG_UART0_CTL                   ((__IO     uint16_t  *) REG_UART0_CTL)                   /*  UART Control Register */
+#define pREG_UART0_RFC                   ((__I __C  uint16_t  *) REG_UART0_RFC)                   /*  RX FIFO Byte Count */
+#define pREG_UART0_TFC                   ((__I __C  uint16_t  *) REG_UART0_TFC)                   /*  TX FIFO Byte Count */
+#define pREG_UART0_RSC                   ((__IO     uint16_t  *) REG_UART0_RSC)                   /*  RS485 Half-duplex Control */
+#define pREG_UART0_ACR                   ((__IO     uint16_t  *) REG_UART0_ACR)                   /*  Auto Baud Control */
+#define pREG_UART0_ASRL                  ((__I __C  uint16_t  *) REG_UART0_ASRL)                  /*  Auto Baud Status (Low) */
+#define pREG_UART0_ASRH                  ((__I __C  uint16_t  *) REG_UART0_ASRH)                  /*  Auto Baud Status (High) */
+
+/*  =================================================================================
+ *       (UART1)
+ *  ================================================================================= */
+#define pREG_UART1_RX                    ((__I __C  uint16_t  *) REG_UART1_RX)                    /*  Receive Buffer Register */
+#define pREG_UART1_TX                    ((__O      uint16_t  *) REG_UART1_TX)                    /*  Transmit Holding Register */
+#define pREG_UART1_IEN                   ((__IO     uint16_t  *) REG_UART1_IEN)                   /*  Interrupt Enable */
+#define pREG_UART1_IIR                   ((__I __C  uint16_t  *) REG_UART1_IIR)                   /*  Interrupt ID */
+#define pREG_UART1_LCR                   ((__IO     uint16_t  *) REG_UART1_LCR)                   /*  Line Control */
+#define pREG_UART1_MCR                   ((__IO     uint16_t  *) REG_UART1_MCR)                   /*  Modem Control */
+#define pREG_UART1_LSR                   ((__I __C  uint16_t  *) REG_UART1_LSR)                   /*  Line Status */
+#define pREG_UART1_MSR                   ((__I __C  uint16_t  *) REG_UART1_MSR)                   /*  Modem Status */
+#define pREG_UART1_SCR                   ((__IO     uint16_t  *) REG_UART1_SCR)                   /*  Scratch Buffer */
+#define pREG_UART1_FCR                   ((__IO     uint16_t  *) REG_UART1_FCR)                   /*  FIFO Control */
+#define pREG_UART1_FBR                   ((__IO     uint16_t  *) REG_UART1_FBR)                   /*  Fractional Baud Rate */
+#define pREG_UART1_DIV                   ((__IO     uint16_t  *) REG_UART1_DIV)                   /*  Baud Rate Divider */
+#define pREG_UART1_LCR2                  ((__IO     uint16_t  *) REG_UART1_LCR2)                  /*  Second Line Control */
+#define pREG_UART1_CTL                   ((__IO     uint16_t  *) REG_UART1_CTL)                   /*  UART Control Register */
+#define pREG_UART1_RFC                   ((__I __C  uint16_t  *) REG_UART1_RFC)                   /*  RX FIFO Byte Count */
+#define pREG_UART1_TFC                   ((__I __C  uint16_t  *) REG_UART1_TFC)                   /*  TX FIFO Byte Count */
+#define pREG_UART1_RSC                   ((__IO     uint16_t  *) REG_UART1_RSC)                   /*  RS485 Half-duplex Control */
+#define pREG_UART1_ACR                   ((__IO     uint16_t  *) REG_UART1_ACR)                   /*  Auto Baud Control */
+#define pREG_UART1_ASRL                  ((__I __C  uint16_t  *) REG_UART1_ASRL)                  /*  Auto Baud Status (Low) */
+#define pREG_UART1_ASRH                  ((__I __C  uint16_t  *) REG_UART1_ASRH)                  /*  Auto Baud Status (High) */
+
+/*  =================================================================================
+ *      Beeper Driver (BEEP0)
+ *  ================================================================================= */
+#define pREG_BEEP0_CFG                   ((__IO     uint16_t  *) REG_BEEP0_CFG)                   /*  Beeper Configuration */
+#define pREG_BEEP0_STAT                  ((__IO     uint16_t  *) REG_BEEP0_STAT)                  /*  Beeper Status */
+#define pREG_BEEP0_TONEA                 ((__IO     uint16_t  *) REG_BEEP0_TONEA)                 /*  Tone A Data */
+#define pREG_BEEP0_TONEB                 ((__IO     uint16_t  *) REG_BEEP0_TONEB)                 /*  Tone B Data */
+
+/*  =================================================================================
+ *       (ADC0)
+ *  ================================================================================= */
+#define pREG_ADC0_CFG                    ((__IO     uint16_t  *) REG_ADC0_CFG)                    /*  ADC Configuration */
+#define pREG_ADC0_PWRUP                  ((__IO     uint16_t  *) REG_ADC0_PWRUP)                  /*  ADC Power-up Time */
+#define pREG_ADC0_CAL_WORD               ((__IO     uint16_t  *) REG_ADC0_CAL_WORD)               /*  Calibration Word */
+#define pREG_ADC0_CNV_CFG                ((__IO     uint16_t  *) REG_ADC0_CNV_CFG)                /*  ADC Conversion Configuration */
+#define pREG_ADC0_CNV_TIME               ((__IO     uint16_t  *) REG_ADC0_CNV_TIME)               /*  ADC Conversion Time */
+#define pREG_ADC0_AVG_CFG                ((__IO     uint16_t  *) REG_ADC0_AVG_CFG)                /*  Averaging Configuration */
+#define pREG_ADC0_IRQ_EN                 ((__IO     uint16_t  *) REG_ADC0_IRQ_EN)                 /*  Interrupt Enable */
+#define pREG_ADC0_STAT                   ((__IO     uint16_t  *) REG_ADC0_STAT)                   /*  ADC Status */
+#define pREG_ADC0_OVF                    ((__IO     uint16_t  *) REG_ADC0_OVF)                    /*  Overflow of Output Registers */
+#define pREG_ADC0_ALERT                  ((__IO     uint16_t  *) REG_ADC0_ALERT)                  /*  Alert Indication */
+#define pREG_ADC0_CH0_OUT                ((__I __C  uint16_t  *) REG_ADC0_CH0_OUT)                /*  Conversion Result Channel 0 */
+#define pREG_ADC0_CH1_OUT                ((__I __C  uint16_t  *) REG_ADC0_CH1_OUT)                /*  Conversion Result Channel 1 */
+#define pREG_ADC0_CH2_OUT                ((__I __C  uint16_t  *) REG_ADC0_CH2_OUT)                /*  Conversion Result Channel 2 */
+#define pREG_ADC0_CH3_OUT                ((__I __C  uint16_t  *) REG_ADC0_CH3_OUT)                /*  Conversion Result Channel 3 */
+#define pREG_ADC0_CH4_OUT                ((__I __C  uint16_t  *) REG_ADC0_CH4_OUT)                /*  Conversion Result Channel 4 */
+#define pREG_ADC0_CH5_OUT                ((__I __C  uint16_t  *) REG_ADC0_CH5_OUT)                /*  Conversion Result Channel 5 */
+#define pREG_ADC0_CH6_OUT                ((__I __C  uint16_t  *) REG_ADC0_CH6_OUT)                /*  Conversion Result Channel 6 */
+#define pREG_ADC0_CH7_OUT                ((__I __C  uint16_t  *) REG_ADC0_CH7_OUT)                /*  Conversion Result Channel 7 */
+#define pREG_ADC0_BAT_OUT                ((__I __C  uint16_t  *) REG_ADC0_BAT_OUT)                /*  Battery Monitoring Result */
+#define pREG_ADC0_TMP_OUT                ((__I __C  uint16_t  *) REG_ADC0_TMP_OUT)                /*  Temperature Result */
+#define pREG_ADC0_TMP2_OUT               ((__I __C  uint16_t  *) REG_ADC0_TMP2_OUT)               /*  Temperature Result 2 */
+#define pREG_ADC0_DMA_OUT                ((__I __C  uint16_t  *) REG_ADC0_DMA_OUT)                /*  DMA Output Register */
+#define pREG_ADC0_LIM0_LO                ((__IO     uint16_t  *) REG_ADC0_LIM0_LO)                /*  Channel 0 Low Limit */
+#define pREG_ADC0_LIM0_HI                ((__IO     uint16_t  *) REG_ADC0_LIM0_HI)                /*  Channel 0 High Limit */
+#define pREG_ADC0_HYS0                   ((__IO     uint16_t  *) REG_ADC0_HYS0)                   /*  Channel 0 Hysteresis */
+#define pREG_ADC0_LIM1_LO                ((__IO     uint16_t  *) REG_ADC0_LIM1_LO)                /*  Channel 1 Low Limit */
+#define pREG_ADC0_LIM1_HI                ((__IO     uint16_t  *) REG_ADC0_LIM1_HI)                /*  Channel 1 High Limit */
+#define pREG_ADC0_HYS1                   ((__IO     uint16_t  *) REG_ADC0_HYS1)                   /*  Channel 1 Hysteresis */
+#define pREG_ADC0_LIM2_LO                ((__IO     uint16_t  *) REG_ADC0_LIM2_LO)                /*  Channel 2 Low Limit */
+#define pREG_ADC0_LIM2_HI                ((__IO     uint16_t  *) REG_ADC0_LIM2_HI)                /*  Channel 2 High Limit */
+#define pREG_ADC0_HYS2                   ((__IO     uint16_t  *) REG_ADC0_HYS2)                   /*  Channel 2 Hysteresis */
+#define pREG_ADC0_LIM3_LO                ((__IO     uint16_t  *) REG_ADC0_LIM3_LO)                /*  Channel 3 Low Limit */
+#define pREG_ADC0_LIM3_HI                ((__IO     uint16_t  *) REG_ADC0_LIM3_HI)                /*  Channel 3 High Limit */
+#define pREG_ADC0_HYS3                   ((__IO     uint16_t  *) REG_ADC0_HYS3)                   /*  Channel 3 Hysteresis */
+#define pREG_ADC0_CFG1                   ((__IO     uint16_t  *) REG_ADC0_CFG1)                   /*  Reference Buffer Low Power Mode */
+
+/*  =================================================================================
+ *      DMA (DMA0)
+ *  ================================================================================= */
+#define pREG_DMA0_STAT                   ((__I __C  uint32_t  *) REG_DMA0_STAT)                   /*  DMA Status */
+#define pREG_DMA0_CFG                    ((__O      uint32_t  *) REG_DMA0_CFG)                    /*  DMA Configuration */
+#define pREG_DMA0_PDBPTR                 ((__IO     uint32_t  *) REG_DMA0_PDBPTR)                 /*  DMA Channel Primary Control Database Pointer */
+#define pREG_DMA0_ADBPTR                 ((__I __C  uint32_t  *) REG_DMA0_ADBPTR)                 /*  DMA Channel Alternate Control Database Pointer */
+#define pREG_DMA0_SWREQ                  ((__O      uint32_t  *) REG_DMA0_SWREQ)                  /*  DMA Channel Software Request */
+#define pREG_DMA0_RMSK_SET               ((__IO     uint32_t  *) REG_DMA0_RMSK_SET)               /*  DMA Channel Request Mask Set */
+#define pREG_DMA0_RMSK_CLR               ((__O      uint32_t  *) REG_DMA0_RMSK_CLR)               /*  DMA Channel Request Mask Clear */
+#define pREG_DMA0_EN_SET                 ((__IO     uint32_t  *) REG_DMA0_EN_SET)                 /*  DMA Channel Enable Set */
+#define pREG_DMA0_EN_CLR                 ((__O      uint32_t  *) REG_DMA0_EN_CLR)                 /*  DMA Channel Enable Clear */
+#define pREG_DMA0_ALT_SET                ((__IO     uint32_t  *) REG_DMA0_ALT_SET)                /*  DMA Channel Primary Alternate Set */
+#define pREG_DMA0_ALT_CLR                ((__O      uint32_t  *) REG_DMA0_ALT_CLR)                /*  DMA Channel Primary Alternate Clear */
+#define pREG_DMA0_PRI_SET                ((__O      uint32_t  *) REG_DMA0_PRI_SET)                /*  DMA Channel Priority Set */
+#define pREG_DMA0_PRI_CLR                ((__O      uint32_t  *) REG_DMA0_PRI_CLR)                /*  DMA Channel Priority Clear */
+#define pREG_DMA0_ERRCHNL_CLR            ((__IO     uint32_t  *) REG_DMA0_ERRCHNL_CLR)            /*  DMA per Channel Error Clear */
+#define pREG_DMA0_ERR_CLR                ((__IO     uint32_t  *) REG_DMA0_ERR_CLR)                /*  DMA Bus Error Clear */
+#define pREG_DMA0_INVALIDDESC_CLR        ((__IO     uint32_t  *) REG_DMA0_INVALIDDESC_CLR)        /*  DMA per Channel Invalid Descriptor Clear */
+#define pREG_DMA0_BS_SET                 ((__IO     uint32_t  *) REG_DMA0_BS_SET)                 /*  DMA Channel Bytes Swap Enable Set */
+#define pREG_DMA0_BS_CLR                 ((__O      uint32_t  *) REG_DMA0_BS_CLR)                 /*  DMA Channel Bytes Swap Enable Clear */
+#define pREG_DMA0_SRCADDR_SET            ((__IO     uint32_t  *) REG_DMA0_SRCADDR_SET)            /*  DMA Channel Source Address Decrement Enable Set */
+#define pREG_DMA0_SRCADDR_CLR            ((__O      uint32_t  *) REG_DMA0_SRCADDR_CLR)            /*  DMA Channel Source Address Decrement Enable Clear */
+#define pREG_DMA0_DSTADDR_SET            ((__IO     uint32_t  *) REG_DMA0_DSTADDR_SET)            /*  DMA Channel Destination Address Decrement Enable Set */
+#define pREG_DMA0_DSTADDR_CLR            ((__O      uint32_t  *) REG_DMA0_DSTADDR_CLR)            /*  DMA Channel Destination Address Decrement Enable Clear */
+#define pREG_DMA0_REVID                  ((__I __C  uint32_t  *) REG_DMA0_REVID)                  /*  DMA Controller Revision ID */
+
+/*  =================================================================================
+ *      Flash Controller (FLCC0)
+ *  ================================================================================= */
+#define pREG_FLCC0_STAT                  ((__IO     uint32_t  *) REG_FLCC0_STAT)                  /*  Status */
+#define pREG_FLCC0_IEN                   ((__IO     uint32_t  *) REG_FLCC0_IEN)                   /*  Interrupt Enable */
+#define pREG_FLCC0_CMD                   ((__IO     uint32_t  *) REG_FLCC0_CMD)                   /*  Command */
+#define pREG_FLCC0_KH_ADDR               ((__IO     uint32_t  *) REG_FLCC0_KH_ADDR)               /*  Write Address */
+#define pREG_FLCC0_KH_DATA0              ((__IO     uint32_t  *) REG_FLCC0_KH_DATA0)              /*  Write Lower Data */
+#define pREG_FLCC0_KH_DATA1              ((__IO     uint32_t  *) REG_FLCC0_KH_DATA1)              /*  Write Upper Data */
+#define pREG_FLCC0_PAGE_ADDR0            ((__IO     uint32_t  *) REG_FLCC0_PAGE_ADDR0)            /*  Lower Page Address */
+#define pREG_FLCC0_PAGE_ADDR1            ((__IO     uint32_t  *) REG_FLCC0_PAGE_ADDR1)            /*  Upper Page Address */
+#define pREG_FLCC0_KEY                   ((__O      uint32_t  *) REG_FLCC0_KEY)                   /*  Key */
+#define pREG_FLCC0_WR_ABORT_ADDR         ((__I __C  uint32_t  *) REG_FLCC0_WR_ABORT_ADDR)         /*  Write Abort Address */
+#define pREG_FLCC0_WRPROT                ((__IO     uint32_t  *) REG_FLCC0_WRPROT)                /*  Write Protection */
+#define pREG_FLCC0_SIGNATURE             ((__I __C  uint32_t  *) REG_FLCC0_SIGNATURE)             /*  Signature */
+#define pREG_FLCC0_UCFG                  ((__IO     uint32_t  *) REG_FLCC0_UCFG)                  /*  User Configuration */
+#define pREG_FLCC0_TIME_PARAM0           ((__IO     uint32_t  *) REG_FLCC0_TIME_PARAM0)           /*  Time Parameter 0 */
+#define pREG_FLCC0_TIME_PARAM1           ((__IO     uint32_t  *) REG_FLCC0_TIME_PARAM1)           /*  Time Parameter 1 */
+#define pREG_FLCC0_ABORT_EN_LO           ((__IO     uint32_t  *) REG_FLCC0_ABORT_EN_LO)           /*  IRQ Abort Enable (Lower Bits) */
+#define pREG_FLCC0_ABORT_EN_HI           ((__IO     uint32_t  *) REG_FLCC0_ABORT_EN_HI)           /*  IRQ Abort Enable (Upper Bits) */
+#define pREG_FLCC0_ECC_CFG               ((__IO     uint32_t  *) REG_FLCC0_ECC_CFG)               /*  ECC Configuration */
+#define pREG_FLCC0_ECC_ADDR              ((__I __C  uint32_t  *) REG_FLCC0_ECC_ADDR)              /*  ECC Status (Address) */
+#define pREG_FLCC0_POR_SEC               ((__IO     uint32_t  *) REG_FLCC0_POR_SEC)               /*  Flash Security */
+#define pREG_FLCC0_VOL_CFG               ((__IO     uint32_t  *) REG_FLCC0_VOL_CFG)               /*  Volatile Flash Configuration */
+
+/*  =================================================================================
+ *      Cache Controller (FLCC0_CACHE)
+ *  ================================================================================= */
+#define pREG_FLCC0_CACHE_STAT            ((__I __C  uint32_t  *) REG_FLCC0_CACHE_STAT)            /*  Cache Status Register */
+#define pREG_FLCC0_CACHE_SETUP           ((__IO     uint32_t  *) REG_FLCC0_CACHE_SETUP)           /*  Cache Setup Register */
+#define pREG_FLCC0_CACHE_KEY             ((__O      uint32_t  *) REG_FLCC0_CACHE_KEY)             /*  Cache Key Register */
+
+/*  =================================================================================
+ *       (GPIO0)
+ *  ================================================================================= */
+#define pREG_GPIO0_CFG                   ((__IO     uint32_t  *) REG_GPIO0_CFG)                   /*  Port  Configuration */
+#define pREG_GPIO0_OEN                   ((__IO     uint16_t  *) REG_GPIO0_OEN)                   /*  Port Output Enable */
+#define pREG_GPIO0_PE                    ((__IO     uint16_t  *) REG_GPIO0_PE)                    /*  Port Output Pull-up/Pull-down Enable */
+#define pREG_GPIO0_IEN                   ((__IO     uint16_t  *) REG_GPIO0_IEN)                   /*  Port  Input Path Enable */
+#define pREG_GPIO0_IN                    ((__I __C  uint16_t  *) REG_GPIO0_IN)                    /*  Port  Registered Data Input */
+#define pREG_GPIO0_OUT                   ((__IO     uint16_t  *) REG_GPIO0_OUT)                   /*  Port Data Output */
+#define pREG_GPIO0_SET                   ((__O      uint16_t  *) REG_GPIO0_SET)                   /*  Port Data Out Set */
+#define pREG_GPIO0_CLR                   ((__O      uint16_t  *) REG_GPIO0_CLR)                   /*  Port Data Out Clear */
+#define pREG_GPIO0_TGL                   ((__O      uint16_t  *) REG_GPIO0_TGL)                   /*  Port Pin Toggle */
+#define pREG_GPIO0_POL                   ((__IO     uint16_t  *) REG_GPIO0_POL)                   /*  Port Interrupt Polarity */
+#define pREG_GPIO0_IENA                  ((__IO     uint16_t  *) REG_GPIO0_IENA)                  /*  Port Interrupt A Enable */
+#define pREG_GPIO0_IENB                  ((__IO     uint16_t  *) REG_GPIO0_IENB)                  /*  Port Interrupt B Enable */
+#define pREG_GPIO0_INT                   ((__IO     uint16_t  *) REG_GPIO0_INT)                   /*  Port Interrupt Status */
+#define pREG_GPIO0_DS                    ((__IO     uint16_t  *) REG_GPIO0_DS)                    /*  Port Drive Strength Select */
+
+/*  =================================================================================
+ *       (GPIO1)
+ *  ================================================================================= */
+#define pREG_GPIO1_CFG                   ((__IO     uint32_t  *) REG_GPIO1_CFG)                   /*  Port  Configuration */
+#define pREG_GPIO1_OEN                   ((__IO     uint16_t  *) REG_GPIO1_OEN)                   /*  Port Output Enable */
+#define pREG_GPIO1_PE                    ((__IO     uint16_t  *) REG_GPIO1_PE)                    /*  Port Output Pull-up/Pull-down Enable */
+#define pREG_GPIO1_IEN                   ((__IO     uint16_t  *) REG_GPIO1_IEN)                   /*  Port  Input Path Enable */
+#define pREG_GPIO1_IN                    ((__I __C  uint16_t  *) REG_GPIO1_IN)                    /*  Port  Registered Data Input */
+#define pREG_GPIO1_OUT                   ((__IO     uint16_t  *) REG_GPIO1_OUT)                   /*  Port Data Output */
+#define pREG_GPIO1_SET                   ((__O      uint16_t  *) REG_GPIO1_SET)                   /*  Port Data Out Set */
+#define pREG_GPIO1_CLR                   ((__O      uint16_t  *) REG_GPIO1_CLR)                   /*  Port Data Out Clear */
+#define pREG_GPIO1_TGL                   ((__O      uint16_t  *) REG_GPIO1_TGL)                   /*  Port Pin Toggle */
+#define pREG_GPIO1_POL                   ((__IO     uint16_t  *) REG_GPIO1_POL)                   /*  Port Interrupt Polarity */
+#define pREG_GPIO1_IENA                  ((__IO     uint16_t  *) REG_GPIO1_IENA)                  /*  Port Interrupt A Enable */
+#define pREG_GPIO1_IENB                  ((__IO     uint16_t  *) REG_GPIO1_IENB)                  /*  Port Interrupt B Enable */
+#define pREG_GPIO1_INT                   ((__IO     uint16_t  *) REG_GPIO1_INT)                   /*  Port Interrupt Status */
+#define pREG_GPIO1_DS                    ((__IO     uint16_t  *) REG_GPIO1_DS)                    /*  Port Drive Strength Select */
+
+/*  =================================================================================
+ *       (GPIO2)
+ *  ================================================================================= */
+#define pREG_GPIO2_CFG                   ((__IO     uint32_t  *) REG_GPIO2_CFG)                   /*  Port  Configuration */
+#define pREG_GPIO2_OEN                   ((__IO     uint16_t  *) REG_GPIO2_OEN)                   /*  Port Output Enable */
+#define pREG_GPIO2_PE                    ((__IO     uint16_t  *) REG_GPIO2_PE)                    /*  Port Output Pull-up/Pull-down Enable */
+#define pREG_GPIO2_IEN                   ((__IO     uint16_t  *) REG_GPIO2_IEN)                   /*  Port  Input Path Enable */
+#define pREG_GPIO2_IN                    ((__I __C  uint16_t  *) REG_GPIO2_IN)                    /*  Port  Registered Data Input */
+#define pREG_GPIO2_OUT                   ((__IO     uint16_t  *) REG_GPIO2_OUT)                   /*  Port Data Output */
+#define pREG_GPIO2_SET                   ((__O      uint16_t  *) REG_GPIO2_SET)                   /*  Port Data Out Set */
+#define pREG_GPIO2_CLR                   ((__O      uint16_t  *) REG_GPIO2_CLR)                   /*  Port Data Out Clear */
+#define pREG_GPIO2_TGL                   ((__O      uint16_t  *) REG_GPIO2_TGL)                   /*  Port Pin Toggle */
+#define pREG_GPIO2_POL                   ((__IO     uint16_t  *) REG_GPIO2_POL)                   /*  Port Interrupt Polarity */
+#define pREG_GPIO2_IENA                  ((__IO     uint16_t  *) REG_GPIO2_IENA)                  /*  Port Interrupt A Enable */
+#define pREG_GPIO2_IENB                  ((__IO     uint16_t  *) REG_GPIO2_IENB)                  /*  Port Interrupt B Enable */
+#define pREG_GPIO2_INT                   ((__IO     uint16_t  *) REG_GPIO2_INT)                   /*  Port Interrupt Status */
+#define pREG_GPIO2_DS                    ((__IO     uint16_t  *) REG_GPIO2_DS)                    /*  Port Drive Strength Select */
+
+/*  =================================================================================
+ *       (GPIO3)
+ *  ================================================================================= */
+#define pREG_GPIO3_CFG                   ((__IO     uint32_t  *) REG_GPIO3_CFG)                   /*  Port  Configuration */
+#define pREG_GPIO3_OEN                   ((__IO     uint16_t  *) REG_GPIO3_OEN)                   /*  Port Output Enable */
+#define pREG_GPIO3_PE                    ((__IO     uint16_t  *) REG_GPIO3_PE)                    /*  Port Output Pull-up/Pull-down Enable */
+#define pREG_GPIO3_IEN                   ((__IO     uint16_t  *) REG_GPIO3_IEN)                   /*  Port  Input Path Enable */
+#define pREG_GPIO3_IN                    ((__I __C  uint16_t  *) REG_GPIO3_IN)                    /*  Port  Registered Data Input */
+#define pREG_GPIO3_OUT                   ((__IO     uint16_t  *) REG_GPIO3_OUT)                   /*  Port Data Output */
+#define pREG_GPIO3_SET                   ((__O      uint16_t  *) REG_GPIO3_SET)                   /*  Port Data Out Set */
+#define pREG_GPIO3_CLR                   ((__O      uint16_t  *) REG_GPIO3_CLR)                   /*  Port Data Out Clear */
+#define pREG_GPIO3_TGL                   ((__O      uint16_t  *) REG_GPIO3_TGL)                   /*  Port Pin Toggle */
+#define pREG_GPIO3_POL                   ((__IO     uint16_t  *) REG_GPIO3_POL)                   /*  Port Interrupt Polarity */
+#define pREG_GPIO3_IENA                  ((__IO     uint16_t  *) REG_GPIO3_IENA)                  /*  Port Interrupt A Enable */
+#define pREG_GPIO3_IENB                  ((__IO     uint16_t  *) REG_GPIO3_IENB)                  /*  Port Interrupt B Enable */
+#define pREG_GPIO3_INT                   ((__IO     uint16_t  *) REG_GPIO3_INT)                   /*  Port Interrupt Status */
+#define pREG_GPIO3_DS                    ((__IO     uint16_t  *) REG_GPIO3_DS)                    /*  Port Drive Strength Select */
+
+/*  =================================================================================
+ *      Serial Port (SPORT0)
+ *  ================================================================================= */
+#define pREG_SPORT0_CTL_A                ((__IO     uint32_t  *) REG_SPORT0_CTL_A)                /*  Half SPORT 'A' Control Register */
+#define pREG_SPORT0_DIV_A                ((__IO     uint32_t  *) REG_SPORT0_DIV_A)                /*  Half SPORT 'A' Divisor Register */
+#define pREG_SPORT0_IEN_A                ((__IO     uint32_t  *) REG_SPORT0_IEN_A)                /*  Half SPORT A's Interrupt Enable register */
+#define pREG_SPORT0_STAT_A               ((__IO     uint32_t  *) REG_SPORT0_STAT_A)               /*  Half SPORT 'A' Status register */
+#define pREG_SPORT0_NUMTRAN_A            ((__IO     uint32_t  *) REG_SPORT0_NUMTRAN_A)            /*  Half SPORT A Number of transfers register */
+#define pREG_SPORT0_CNVT_A               ((__IO     uint32_t  *) REG_SPORT0_CNVT_A)               /*  Half SPORT 'A' CNV width */
+#define pREG_SPORT0_TX_A                 ((__O      uint32_t  *) REG_SPORT0_TX_A)                 /*  Half SPORT 'A' Tx Buffer Register */
+#define pREG_SPORT0_RX_A                 ((__I __C  uint32_t  *) REG_SPORT0_RX_A)                 /*  Half SPORT 'A' Rx Buffer Register */
+#define pREG_SPORT0_CTL_B                ((__IO     uint32_t  *) REG_SPORT0_CTL_B)                /*  Half SPORT 'B' Control Register */
+#define pREG_SPORT0_DIV_B                ((__IO     uint32_t  *) REG_SPORT0_DIV_B)                /*  Half SPORT 'B' Divisor Register */
+#define pREG_SPORT0_IEN_B                ((__IO     uint32_t  *) REG_SPORT0_IEN_B)                /*  Half SPORT B's Interrupt Enable register */
+#define pREG_SPORT0_STAT_B               ((__IO     uint32_t  *) REG_SPORT0_STAT_B)               /*  Half SPORT 'B' Status register */
+#define pREG_SPORT0_NUMTRAN_B            ((__IO     uint32_t  *) REG_SPORT0_NUMTRAN_B)            /*  Half SPORT B Number of transfers register */
+#define pREG_SPORT0_CNVT_B               ((__IO     uint32_t  *) REG_SPORT0_CNVT_B)               /*  Half SPORT 'B' CNV width register */
+#define pREG_SPORT0_TX_B                 ((__O      uint32_t  *) REG_SPORT0_TX_B)                 /*  Half SPORT 'B' Tx Buffer Register */
+#define pREG_SPORT0_RX_B                 ((__I __C  uint32_t  *) REG_SPORT0_RX_B)                 /*  Half SPORT 'B' Rx Buffer Register */
+
+/*  =================================================================================
+ *      CRC Accelerator (CRC0)
+ *  ================================================================================= */
+#define pREG_CRC0_CTL                    ((__IO     uint32_t  *) REG_CRC0_CTL)                    /*  CRC Control */
+#define pREG_CRC0_IPDATA                 ((__O      uint32_t  *) REG_CRC0_IPDATA)                 /*  Input Data Word */
+#define pREG_CRC0_RESULT                 ((__IO     uint32_t  *) REG_CRC0_RESULT)                 /*  CRC Result */
+#define pREG_CRC0_POLY                   ((__IO     uint32_t  *) REG_CRC0_POLY)                   /*  Programmable CRC Polynomial */
+#define pREG_CRC0_IPBYTE                 ((__O      uint8_t   *) REG_CRC0_IPBYTE)                 /*  Input Data Byte */
+#define pREG_CRC0_IPBITS0                ((__O      uint8_t   *) REG_CRC0_IPBITS0)                /*  Input Data Bits */
+#define pREG_CRC0_IPBITS1                ((__O      uint8_t   *) REG_CRC0_IPBITS1)                /*  Input Data Bits */
+#define pREG_CRC0_IPBITS2                ((__O      uint8_t   *) REG_CRC0_IPBITS2)                /*  Input Data Bits */
+#define pREG_CRC0_IPBITS3                ((__O      uint8_t   *) REG_CRC0_IPBITS3)                /*  Input Data Bits */
+#define pREG_CRC0_IPBITS4                ((__O      uint8_t   *) REG_CRC0_IPBITS4)                /*  Input Data Bits */
+#define pREG_CRC0_IPBITS5                ((__O      uint8_t   *) REG_CRC0_IPBITS5)                /*  Input Data Bits */
+#define pREG_CRC0_IPBITS6                ((__O      uint8_t   *) REG_CRC0_IPBITS6)                /*  Input Data Bits */
+#define pREG_CRC0_IPBITS7                ((__O      uint8_t   *) REG_CRC0_IPBITS7)                /*  Input Data Bits */
+
+/*  =================================================================================
+ *      Random Number Generator (RNG0)
+ *  ================================================================================= */
+#define pREG_RNG0_CTL                    ((__IO     uint16_t  *) REG_RNG0_CTL)                    /*  RNG Control Register */
+#define pREG_RNG0_LEN                    ((__IO     uint16_t  *) REG_RNG0_LEN)                    /*  RNG Sample Length Register */
+#define pREG_RNG0_STAT                   ((__IO     uint16_t  *) REG_RNG0_STAT)                   /*  RNG Status Register */
+#define pREG_RNG0_DATA                   ((__I __C  uint32_t  *) REG_RNG0_DATA)                   /*  RNG Data Register */
+#define pREG_RNG0_OSCCNT                 ((__I __C  uint32_t  *) REG_RNG0_OSCCNT)                 /*  Oscillator Count */
+#define pREG_RNG0_OSCDIFF0               ((__I __C  int8_t    *) REG_RNG0_OSCDIFF0)               /*  Oscillator Difference */
+#define pREG_RNG0_OSCDIFF1               ((__I __C  int8_t    *) REG_RNG0_OSCDIFF1)               /*  Oscillator Difference */
+#define pREG_RNG0_OSCDIFF2               ((__I __C  int8_t    *) REG_RNG0_OSCDIFF2)               /*  Oscillator Difference */
+#define pREG_RNG0_OSCDIFF3               ((__I __C  int8_t    *) REG_RNG0_OSCDIFF3)               /*  Oscillator Difference */
+
+/*  =================================================================================
+ *      Register Map for the Crypto Block (CRYPT0)
+ *  ================================================================================= */
+#define pREG_CRYPT0_CFG                  ((__IO     uint32_t  *) REG_CRYPT0_CFG)                  /*  Configuration Register */
+#define pREG_CRYPT0_DATALEN              ((__IO     uint32_t  *) REG_CRYPT0_DATALEN)              /*  Payload Data Length */
+#define pREG_CRYPT0_PREFIXLEN            ((__IO     uint32_t  *) REG_CRYPT0_PREFIXLEN)            /*  Authentication Data Length */
+#define pREG_CRYPT0_INTEN                ((__IO     uint32_t  *) REG_CRYPT0_INTEN)                /*  Interrupt Enable Register */
+#define pREG_CRYPT0_STAT                 ((__IO     uint32_t  *) REG_CRYPT0_STAT)                 /*  Status Register */
+#define pREG_CRYPT0_INBUF                ((__O      uint32_t  *) REG_CRYPT0_INBUF)                /*  Input Buffer */
+#define pREG_CRYPT0_OUTBUF               ((__I __C  uint32_t  *) REG_CRYPT0_OUTBUF)               /*  Output Buffer */
+#define pREG_CRYPT0_NONCE0               ((__IO     uint32_t  *) REG_CRYPT0_NONCE0)               /*  Nonce Bits [31:0] */
+#define pREG_CRYPT0_NONCE1               ((__IO     uint32_t  *) REG_CRYPT0_NONCE1)               /*  Nonce Bits [63:32] */
+#define pREG_CRYPT0_NONCE2               ((__IO     uint32_t  *) REG_CRYPT0_NONCE2)               /*  Nonce Bits [95:64] */
+#define pREG_CRYPT0_NONCE3               ((__IO     uint32_t  *) REG_CRYPT0_NONCE3)               /*  Nonce Bits [127:96] */
+#define pREG_CRYPT0_AESKEY0              ((__O      uint32_t  *) REG_CRYPT0_AESKEY0)              /*  AES Key Bits [31:0] */
+#define pREG_CRYPT0_AESKEY1              ((__O      uint32_t  *) REG_CRYPT0_AESKEY1)              /*  AES Key Bits [63:32] */
+#define pREG_CRYPT0_AESKEY2              ((__O      uint32_t  *) REG_CRYPT0_AESKEY2)              /*  AES Key Bits [95:64] */
+#define pREG_CRYPT0_AESKEY3              ((__O      uint32_t  *) REG_CRYPT0_AESKEY3)              /*  AES Key Bits [127:96] */
+#define pREG_CRYPT0_AESKEY4              ((__O      uint32_t  *) REG_CRYPT0_AESKEY4)              /*  AES Key Bits [159:128] */
+#define pREG_CRYPT0_AESKEY5              ((__O      uint32_t  *) REG_CRYPT0_AESKEY5)              /*  AES Key Bits [191:160] */
+#define pREG_CRYPT0_AESKEY6              ((__O      uint32_t  *) REG_CRYPT0_AESKEY6)              /*  AES Key Bits [223:192] */
+#define pREG_CRYPT0_AESKEY7              ((__O      uint32_t  *) REG_CRYPT0_AESKEY7)              /*  AES Key Bits [255:224] */
+#define pREG_CRYPT0_CNTRINIT             ((__IO     uint32_t  *) REG_CRYPT0_CNTRINIT)             /*  Counter Initialization Vector */
+#define pREG_CRYPT0_SHAH0                ((__IO     uint32_t  *) REG_CRYPT0_SHAH0)                /*  SHA Bits [31:0] */
+#define pREG_CRYPT0_SHAH1                ((__IO     uint32_t  *) REG_CRYPT0_SHAH1)                /*  SHA Bits [63:32] */
+#define pREG_CRYPT0_SHAH2                ((__IO     uint32_t  *) REG_CRYPT0_SHAH2)                /*  SHA Bits [95:64] */
+#define pREG_CRYPT0_SHAH3                ((__IO     uint32_t  *) REG_CRYPT0_SHAH3)                /*  SHA Bits [127:96] */
+#define pREG_CRYPT0_SHAH4                ((__IO     uint32_t  *) REG_CRYPT0_SHAH4)                /*  SHA Bits [159:128] */
+#define pREG_CRYPT0_SHAH5                ((__IO     uint32_t  *) REG_CRYPT0_SHAH5)                /*  SHA Bits [191:160] */
+#define pREG_CRYPT0_SHAH6                ((__IO     uint32_t  *) REG_CRYPT0_SHAH6)                /*  SHA Bits [223:192] */
+#define pREG_CRYPT0_SHAH7                ((__IO     uint32_t  *) REG_CRYPT0_SHAH7)                /*  SHA Bits [255:224] */
+#define pREG_CRYPT0_SHA_LAST_WORD        ((__IO     uint32_t  *) REG_CRYPT0_SHA_LAST_WORD)        /*  SHA Last Word and Valid Bits Information */
+#define pREG_CRYPT0_CCM_NUM_VALID_BYTES  ((__IO     uint32_t  *) REG_CRYPT0_CCM_NUM_VALID_BYTES)  /*  NUM_VALID_BYTES */
+#define pREG_CRYPT0_PRKSTORCFG           ((__IO     uint32_t  *) REG_CRYPT0_PRKSTORCFG)           /*  PRKSTOR Configuration */
+#define pREG_CRYPT0_KUW0                 ((__O      uint32_t  *) REG_CRYPT0_KUW0)                 /*  Key Wrap Unwrap Register 0 */
+#define pREG_CRYPT0_KUW1                 ((__O      uint32_t  *) REG_CRYPT0_KUW1)                 /*  Key Wrap Unwrap Register 1 */
+#define pREG_CRYPT0_KUW2                 ((__O      uint32_t  *) REG_CRYPT0_KUW2)                 /*  Key Wrap Unwrap Register 2 */
+#define pREG_CRYPT0_KUW3                 ((__O      uint32_t  *) REG_CRYPT0_KUW3)                 /*  Key Wrap Unwrap Register 3 */
+#define pREG_CRYPT0_KUW4                 ((__O      uint32_t  *) REG_CRYPT0_KUW4)                 /*  Key Wrap Unwrap Register 4 */
+#define pREG_CRYPT0_KUW5                 ((__O      uint32_t  *) REG_CRYPT0_KUW5)                 /*  Key Wrap Unwrap Register 5 */
+#define pREG_CRYPT0_KUW6                 ((__O      uint32_t  *) REG_CRYPT0_KUW6)                 /*  Key Wrap Unwrap Register 6 */
+#define pREG_CRYPT0_KUW7                 ((__O      uint32_t  *) REG_CRYPT0_KUW7)                 /*  Key Wrap Unwrap Register 7 */
+#define pREG_CRYPT0_KUW8                 ((__O      uint32_t  *) REG_CRYPT0_KUW8)                 /*  Key Wrap Unwrap Register 8 */
+#define pREG_CRYPT0_KUW9                 ((__O      uint32_t  *) REG_CRYPT0_KUW9)                 /*  Key Wrap Unwrap Register 9 */
+#define pREG_CRYPT0_KUW10                ((__O      uint32_t  *) REG_CRYPT0_KUW10)                /*  Key Wrap Unwrap Register 10 */
+#define pREG_CRYPT0_KUW11                ((__O      uint32_t  *) REG_CRYPT0_KUW11)                /*  Key Wrap Unwrap Register 11 */
+#define pREG_CRYPT0_KUW12                ((__O      uint32_t  *) REG_CRYPT0_KUW12)                /*  Key Wrap Unwrap Register 12 */
+#define pREG_CRYPT0_KUW13                ((__O      uint32_t  *) REG_CRYPT0_KUW13)                /*  Key Wrap Unwrap Register 13 */
+#define pREG_CRYPT0_KUW14                ((__O      uint32_t  *) REG_CRYPT0_KUW14)                /*  Key Wrap Unwrap Register 14 */
+#define pREG_CRYPT0_KUW15                ((__O      uint32_t  *) REG_CRYPT0_KUW15)                /*  Key Wrap Unwrap Register 15 */
+#define pREG_CRYPT0_KUWVALSTR1           ((__O      uint32_t  *) REG_CRYPT0_KUWVALSTR1)           /*  Key Wrap Unwrap Validation String [63:32] */
+#define pREG_CRYPT0_KUWVALSTR2           ((__O      uint32_t  *) REG_CRYPT0_KUWVALSTR2)           /*  Key Wrap Unwrap Validation String [31:0] */
+
+/*  =================================================================================
+ *      Power Management  (PMG0)
+ *  ================================================================================= */
+#define pREG_PMG0_IEN                    ((__IO     uint32_t  *) REG_PMG0_IEN)                    /*  Power Supply Monitor Interrupt Enable */
+#define pREG_PMG0_PSM_STAT               ((__IO     uint32_t  *) REG_PMG0_PSM_STAT)               /*  Power Supply Monitor Status */
+#define pREG_PMG0_PWRMOD                 ((__IO     uint32_t  *) REG_PMG0_PWRMOD)                 /*  Power Mode Register */
+#define pREG_PMG0_PWRKEY                 ((__O      uint32_t  *) REG_PMG0_PWRKEY)                 /*  Key Protection for PWRMOD and  SRAMRET */
+#define pREG_PMG0_SHDN_STAT              ((__I __C  uint32_t  *) REG_PMG0_SHDN_STAT)              /*  Shutdown Status Register */
+#define pREG_PMG0_SRAMRET                ((__IO     uint32_t  *) REG_PMG0_SRAMRET)                /*  Control for Retention SRAM in Hibernate Mode */
+#define pREG_PMG0_TRIM                   ((__IO     uint32_t  *) REG_PMG0_TRIM)                   /*  Trimming Bits */
+#define pREG_PMG0_RST_STAT               ((__IO     uint32_t  *) REG_PMG0_RST_STAT)               /*  Reset Status */
+#define pREG_PMG0_CTL1                   ((__IO     uint32_t  *) REG_PMG0_CTL1)                   /*  HPBUCK Control */
+
+/*  =================================================================================
+ *      External interrupt configuration (XINT0)
+ *  ================================================================================= */
+#define pREG_XINT0_CFG0                  ((__IO     uint32_t  *) REG_XINT0_CFG0)                  /*  External Interrupt configuration */
+#define pREG_XINT0_EXT_STAT              ((__I __C  uint32_t  *) REG_XINT0_EXT_STAT)              /*  External Wakeup Interrupt Status register */
+#define pREG_XINT0_CLR                   ((__IO     uint32_t  *) REG_XINT0_CLR)                   /*  External Interrupt clear */
+#define pREG_XINT0_NMICLR                ((__IO     uint32_t  *) REG_XINT0_NMICLR)                /*  Non-maskable interrupt clear */
+
+/*  =================================================================================
+ *      Clocking  (CLKG0_OSC)
+ *  ================================================================================= */
+#define pREG_CLKG0_OSC_KEY               ((__O      uint32_t  *) REG_CLKG0_OSC_KEY)               /*  Key Protection for OSCCTRL */
+#define pREG_CLKG0_OSC_CTL               ((__IO     uint32_t  *) REG_CLKG0_OSC_CTL)               /*  Oscillator Control */
+
+/*  =================================================================================
+ *      Power Management  (PMG0_TST)
+ *  ================================================================================= */
+#define pREG_PMG0_TST_SRAM_CTL           ((__IO     uint32_t  *) REG_PMG0_TST_SRAM_CTL)           /*  Control for SRAM Parity and Instruction SRAM */
+#define pREG_PMG0_TST_SRAM_INITSTAT      ((__I __C  uint32_t  *) REG_PMG0_TST_SRAM_INITSTAT)      /*  Initialization Status Register */
+#define pREG_PMG0_TST_CLR_LATCH_GPIOS    ((__O      uint16_t  *) REG_PMG0_TST_CLR_LATCH_GPIOS)    /*  Clear GPIO After Shutdown Mode */
+#define pREG_PMG0_TST_SCRPAD_IMG         ((__IO     uint32_t  *) REG_PMG0_TST_SCRPAD_IMG)         /*  Scratch Pad Image */
+#define pREG_PMG0_TST_SCRPAD_3V_RD       ((__I __C  uint32_t  *) REG_PMG0_TST_SCRPAD_3V_RD)       /*  Scratch Pad Saved in Battery Domain */
+#define pREG_PMG0_TST_FAST_SHT_WAKEUP    ((__IO     uint32_t  *) REG_PMG0_TST_FAST_SHT_WAKEUP)    /*  Fast Shutdown Wake-up Enable */
+
+/*  =================================================================================
+ *      Clocking  (CLKG0_CLK)
+ *  ================================================================================= */
+#define pREG_CLKG0_CLK_CTL0              ((__IO     uint32_t  *) REG_CLKG0_CLK_CTL0)              /*  Misc Clock Settings */
+#define pREG_CLKG0_CLK_CTL1              ((__IO     uint32_t  *) REG_CLKG0_CLK_CTL1)              /*  Clock Dividers */
+#define pREG_CLKG0_CLK_CTL2              ((__IO     uint32_t  *) REG_CLKG0_CLK_CTL2)              /*  HF Oscillator Divided Clock Select */
+#define pREG_CLKG0_CLK_CTL3              ((__IO     uint32_t  *) REG_CLKG0_CLK_CTL3)              /*  System PLL */
+#define pREG_CLKG0_CLK_CTL5              ((__IO     uint32_t  *) REG_CLKG0_CLK_CTL5)              /*  User Clock Gating Control */
+#define pREG_CLKG0_CLK_STAT0             ((__IO     uint32_t  *) REG_CLKG0_CLK_STAT0)             /*  Clocking Status */
+
+/*  =================================================================================
+ *      Bus matrix (BUSM0)
+ *  ================================================================================= */
+#define pREG_BUSM0_ARBIT0                ((__IO     uint32_t  *) REG_BUSM0_ARBIT0)                /*  Arbitration Priority Configuration for FLASH and SRAM0 */
+#define pREG_BUSM0_ARBIT1                ((__IO     uint32_t  *) REG_BUSM0_ARBIT1)                /*  Arbitration Priority Configuration for SRAM1 and SIP */
+#define pREG_BUSM0_ARBIT2                ((__IO     uint32_t  *) REG_BUSM0_ARBIT2)                /*  Arbitration Priority Configuration for APB32 and APB16 */
+#define pREG_BUSM0_ARBIT3                ((__IO     uint32_t  *) REG_BUSM0_ARBIT3)                /*  Arbitration Priority Configuration for APB16 priority for core and for DMA1 */
+#define pREG_BUSM0_ARBIT4                ((__IO     uint32_t  *) REG_BUSM0_ARBIT4)                /*  Arbitration Priority Configuration for SRAM1 and SIP */
+
+/*  =================================================================================
+ *      Parallel Test Interface (PTI0)
+ *  ================================================================================= */
+#define pREG_PTI0_RST_ISR_STARTADDR      ((__IO     uint32_t  *) REG_PTI0_RST_ISR_STARTADDR)      /*  Reset ISR Start Address */
+#define pREG_PTI0_RST_STACK_PTR          ((__IO     uint32_t  *) REG_PTI0_RST_STACK_PTR)          /*  Reset Stack Pointer */
+#define pREG_PTI0_CTL                    ((__IO     uint32_t  *) REG_PTI0_CTL)                    /*  Parallel Test Interface Control Register */
+
+/*  =================================================================================
+ *      Cortex-M3 Interrupt Controller (NVIC0)
+ *  ================================================================================= */
+#define pREG_NVIC0_INTNUM                ((__IO     uint32_t  *) REG_NVIC0_INTNUM)                /*  Interrupt Control Type */
+#define pREG_NVIC0_STKSTA                ((__IO     uint32_t  *) REG_NVIC0_STKSTA)                /*  Systick Control and Status */
+#define pREG_NVIC0_STKLD                 ((__IO     uint32_t  *) REG_NVIC0_STKLD)                 /*  Systick Reload Value */
+#define pREG_NVIC0_STKVAL                ((__IO     uint32_t  *) REG_NVIC0_STKVAL)                /*  Systick Current Value */
+#define pREG_NVIC0_STKCAL                ((__IO     uint32_t  *) REG_NVIC0_STKCAL)                /*  Systick Calibration Value */
+#define pREG_NVIC0_INTSETE0              ((__IO     uint32_t  *) REG_NVIC0_INTSETE0)              /*  IRQ0..31 Set_Enable */
+#define pREG_NVIC0_INTSETE1              ((__IO     uint32_t  *) REG_NVIC0_INTSETE1)              /*  IRQ32..63 Set_Enable */
+#define pREG_NVIC0_INTCLRE0              ((__IO     uint32_t  *) REG_NVIC0_INTCLRE0)              /*  IRQ0..31 Clear_Enable */
+#define pREG_NVIC0_INTCLRE1              ((__IO     uint32_t  *) REG_NVIC0_INTCLRE1)              /*  IRQ32..63 Clear_Enable */
+#define pREG_NVIC0_INTSETP0              ((__IO     uint32_t  *) REG_NVIC0_INTSETP0)              /*  IRQ0..31 Set_Pending */
+#define pREG_NVIC0_INTSETP1              ((__IO     uint32_t  *) REG_NVIC0_INTSETP1)              /*  IRQ32..63 Set_Pending */
+#define pREG_NVIC0_INTCLRP0              ((__IO     uint32_t  *) REG_NVIC0_INTCLRP0)              /*  IRQ0..31 Clear_Pending */
+#define pREG_NVIC0_INTCLRP1              ((__IO     uint32_t  *) REG_NVIC0_INTCLRP1)              /*  IRQ32..63 Clear_Pending */
+#define pREG_NVIC0_INTACT0               ((__IO     uint32_t  *) REG_NVIC0_INTACT0)               /*  IRQ0..31 Active Bit */
+#define pREG_NVIC0_INTACT1               ((__IO     uint32_t  *) REG_NVIC0_INTACT1)               /*  IRQ32..63 Active Bit */
+#define pREG_NVIC0_INTPRI0               ((__IO     uint32_t  *) REG_NVIC0_INTPRI0)               /*  IRQ0..3 Priority */
+#define pREG_NVIC0_INTPRI1               ((__IO     uint32_t  *) REG_NVIC0_INTPRI1)               /*  IRQ4..7 Priority */
+#define pREG_NVIC0_INTPRI2               ((__IO     uint32_t  *) REG_NVIC0_INTPRI2)               /*  IRQ8..11 Priority */
+#define pREG_NVIC0_INTPRI3               ((__IO     uint32_t  *) REG_NVIC0_INTPRI3)               /*  IRQ12..15 Priority */
+#define pREG_NVIC0_INTPRI4               ((__IO     uint32_t  *) REG_NVIC0_INTPRI4)               /*  IRQ16..19 Priority */
+#define pREG_NVIC0_INTPRI5               ((__IO     uint32_t  *) REG_NVIC0_INTPRI5)               /*  IRQ20..23 Priority */
+#define pREG_NVIC0_INTPRI6               ((__IO     uint32_t  *) REG_NVIC0_INTPRI6)               /*  IRQ24..27 Priority */
+#define pREG_NVIC0_INTPRI7               ((__IO     uint32_t  *) REG_NVIC0_INTPRI7)               /*  IRQ28..31 Priority */
+#define pREG_NVIC0_INTPRI8               ((__IO     uint32_t  *) REG_NVIC0_INTPRI8)               /*  IRQ32..35 Priority */
+#define pREG_NVIC0_INTPRI9               ((__IO     uint32_t  *) REG_NVIC0_INTPRI9)               /*  IRQ36..39 Priority */
+#define pREG_NVIC0_INTPRI10              ((__IO     uint32_t  *) REG_NVIC0_INTPRI10)              /*  IRQ40..43 Priority */
+#define pREG_NVIC0_INTCPID               ((__IO     uint32_t  *) REG_NVIC0_INTCPID)               /*  CPUID Base */
+#define pREG_NVIC0_INTSTA                ((__IO     uint32_t  *) REG_NVIC0_INTSTA)                /*  Interrupt Control State */
+#define pREG_NVIC0_INTVEC                ((__IO     uint32_t  *) REG_NVIC0_INTVEC)                /*  Vector Table Offset */
+#define pREG_NVIC0_INTAIRC               ((__IO     uint32_t  *) REG_NVIC0_INTAIRC)               /*  Application Interrupt/Reset Control */
+#define pREG_NVIC0_INTCON0               ((__IO     uint16_t  *) REG_NVIC0_INTCON0)               /*  System Control */
+#define pREG_NVIC0_INTCON1               ((__IO     uint32_t  *) REG_NVIC0_INTCON1)               /*  Configuration Control */
+#define pREG_NVIC0_INTSHPRIO0            ((__IO     uint32_t  *) REG_NVIC0_INTSHPRIO0)            /*  System Handlers 4-7 Priority */
+#define pREG_NVIC0_INTSHPRIO1            ((__IO     uint32_t  *) REG_NVIC0_INTSHPRIO1)            /*  System Handlers 8-11 Priority */
+#define pREG_NVIC0_INTSHPRIO3            ((__IO     uint32_t  *) REG_NVIC0_INTSHPRIO3)            /*  System Handlers 12-15 Priority */
+#define pREG_NVIC0_INTSHCSR              ((__IO     uint32_t  *) REG_NVIC0_INTSHCSR)              /*  System Handler Control and State */
+#define pREG_NVIC0_INTCFSR               ((__IO     uint32_t  *) REG_NVIC0_INTCFSR)               /*  Configurable Fault Status */
+#define pREG_NVIC0_INTHFSR               ((__IO     uint32_t  *) REG_NVIC0_INTHFSR)               /*  Hard Fault Status */
+#define pREG_NVIC0_INTDFSR               ((__IO     uint32_t  *) REG_NVIC0_INTDFSR)               /*  Debug Fault Status */
+#define pREG_NVIC0_INTMMAR               ((__IO     uint32_t  *) REG_NVIC0_INTMMAR)               /*  Mem Manage Address */
+#define pREG_NVIC0_INTBFAR               ((__IO     uint32_t  *) REG_NVIC0_INTBFAR)               /*  Bus Fault Address */
+#define pREG_NVIC0_INTAFSR               ((__IO     uint32_t  *) REG_NVIC0_INTAFSR)               /*  Auxiliary Fault Status */
+#define pREG_NVIC0_INTPFR0               ((__IO     uint32_t  *) REG_NVIC0_INTPFR0)               /*  Processor Feature Register 0 */
+#define pREG_NVIC0_INTPFR1               ((__IO     uint32_t  *) REG_NVIC0_INTPFR1)               /*  Processor Feature Register 1 */
+#define pREG_NVIC0_INTDFR0               ((__IO     uint32_t  *) REG_NVIC0_INTDFR0)               /*  Debug Feature Register 0 */
+#define pREG_NVIC0_INTAFR0               ((__IO     uint32_t  *) REG_NVIC0_INTAFR0)               /*  Auxiliary Feature Register 0 */
+#define pREG_NVIC0_INTMMFR0              ((__IO     uint32_t  *) REG_NVIC0_INTMMFR0)              /*  Memory Model Feature Register 0 */
+#define pREG_NVIC0_INTMMFR1              ((__IO     uint32_t  *) REG_NVIC0_INTMMFR1)              /*  Memory Model Feature Register 1 */
+#define pREG_NVIC0_INTMMFR2              ((__IO     uint32_t  *) REG_NVIC0_INTMMFR2)              /*  Memory Model Feature Register 2 */
+#define pREG_NVIC0_INTMMFR3              ((__IO     uint32_t  *) REG_NVIC0_INTMMFR3)              /*  Memory Model Feature Register 3 */
+#define pREG_NVIC0_INTISAR0              ((__IO     uint32_t  *) REG_NVIC0_INTISAR0)              /*  ISA Feature Register 0 */
+#define pREG_NVIC0_INTISAR1              ((__IO     uint32_t  *) REG_NVIC0_INTISAR1)              /*  ISA Feature Register 1 */
+#define pREG_NVIC0_INTISAR2              ((__IO     uint32_t  *) REG_NVIC0_INTISAR2)              /*  ISA Feature Register 2 */
+#define pREG_NVIC0_INTISAR3              ((__IO     uint32_t  *) REG_NVIC0_INTISAR3)              /*  ISA Feature Register 3 */
+#define pREG_NVIC0_INTISAR4              ((__IO     uint32_t  *) REG_NVIC0_INTISAR4)              /*  ISA Feature Register 4 */
+#define pREG_NVIC0_INTTRGI               ((__IO     uint32_t  *) REG_NVIC0_INTTRGI)               /*  Software Trigger Interrupt Register */
+#define pREG_NVIC0_INTPID4               ((__IO     uint32_t  *) REG_NVIC0_INTPID4)               /*  Peripheral Identification Register 4 */
+#define pREG_NVIC0_INTPID5               ((__IO     uint32_t  *) REG_NVIC0_INTPID5)               /*  Peripheral Identification Register 5 */
+#define pREG_NVIC0_INTPID6               ((__IO     uint32_t  *) REG_NVIC0_INTPID6)               /*  Peripheral Identification Register 6 */
+#define pREG_NVIC0_INTPID7               ((__IO     uint32_t  *) REG_NVIC0_INTPID7)               /*  Peripheral Identification Register 7 */
+#define pREG_NVIC0_INTPID0               ((__IO     uint32_t  *) REG_NVIC0_INTPID0)               /*  Peripheral Identification Bits7:0 */
+#define pREG_NVIC0_INTPID1               ((__IO     uint32_t  *) REG_NVIC0_INTPID1)               /*  Peripheral Identification Bits15:8 */
+#define pREG_NVIC0_INTPID2               ((__IO     uint32_t  *) REG_NVIC0_INTPID2)               /*  Peripheral Identification Bits16:23 */
+#define pREG_NVIC0_INTPID3               ((__IO     uint32_t  *) REG_NVIC0_INTPID3)               /*  Peripheral Identification Bits24:31 */
+#define pREG_NVIC0_INTCID0               ((__IO     uint32_t  *) REG_NVIC0_INTCID0)               /*  Component Identification Bits7:0 */
+#define pREG_NVIC0_INTCID1               ((__IO     uint32_t  *) REG_NVIC0_INTCID1)               /*  Component Identification Bits15:8 */
+#define pREG_NVIC0_INTCID2               ((__IO     uint32_t  *) REG_NVIC0_INTCID2)               /*  Component Identification Bits16:23 */
+#define pREG_NVIC0_INTCID3               ((__IO     uint32_t  *) REG_NVIC0_INTCID3)               /*  Component Identification Bits24:31 */
+
+#if defined (_MISRA_RULES)
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+
+#endif
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_device.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_device.h
new file mode 100755
index 00000000000..3326f40824d
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_device.h
@@ -0,0 +1,1327 @@
+/* ================================================================================
+
+     Project      :   ADuCM4050
+     File         :   ADuCM4050_device.h
+     Description  :   C Register Definitions
+
+     Date         :   Feb 7, 2017
+
+     Copyright (c) 2014-2017 Analog Devices, Inc.  All Rights Reserved.
+     This software is proprietary and confidential to Analog Devices, Inc. and
+     its licensors.
+
+     This file was auto-generated. Do not make local changes to this file.
+
+   ================================================================================ */
+
+#ifndef _ADUCM4050_DEVICE_H
+#define _ADUCM4050_DEVICE_H
+
+/* pickup integer types */
+#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__))
+#include <stdint.h>
+#endif /* _LANGUAGE_C */
+
+/* pickup register bitfield and bit masks */
+#include "adi_ADuCM4050_typedefs.h"
+
+#ifndef __IO
+#ifdef __cplusplus
+#define     __I     volatile      /* read-only */
+#define     __C
+#else
+#define     __I     volatile      /* read-only */
+#define     __C     const
+#endif
+#define     __O     volatile      /* write-only */
+#define     __IO    volatile      /* read-write */
+#endif
+
+#if defined (_MISRA_RULES)
+/*
+  anonymous unions violate ISO 9899:1990 and therefore MISRA Rule 1.1.
+  Use of unions violates MISRA Rule 18.4.
+  Anonymous unions are required for this implementation.
+  Re-use of identifiers violates MISRA Rule 5.7.
+  Field names are repeated for the ADuCM4050 register map.
+*/
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_1_1:"Allow anonymous unions")
+#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit")
+#pragma diag(suppress:misra_rule_5_3:"Header will re-use typedef identifiers")
+#pragma diag(suppress:misra_rule_5_6:"Header will re-use identifiers in the same scope")
+#pragma diag(suppress:misra_rule_5_7:"Header will re-use identifiers")
+#pragma diag(suppress:misra_rule_18_4:"Allow the use of a union")
+#endif /* _MISRA_RULES */
+
+/** @defgroup TMR General Purpose Timer (TMR) Module
+ *  General Purpose Timer
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_TMR_TypeDef
+ *  \brief  General Purpose Timer
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_TypeDef__
+typedef struct _ADI_TMR_TypeDef
+{
+    __IO     uint16_t   LOAD;                          /*!< 16-bit Load Value */
+    __I __C  uint8_t  RESERVED0[2];
+    __I __C  uint16_t   CURCNT;                        /*!< 16-bit Timer Value */
+    __I __C  uint8_t  RESERVED1[2];
+    __IO     uint16_t   CTL;                           /*!< Control */
+    __I __C  uint8_t  RESERVED2[2];
+    __O      uint16_t   CLRINT;                        /*!< Clear Interrupt */
+    __I __C  uint8_t  RESERVED3[2];
+    __I __C  uint16_t   CAPTURE;                       /*!< Capture */
+    __I __C  uint8_t  RESERVED4[2];
+    __IO     uint16_t   ALOAD;                         /*!< 16-bit Load Value, Asynchronous */
+    __I __C  uint8_t  RESERVED5[2];
+    __I __C  uint16_t   ACURCNT;                       /*!< 16-bit Timer Value, Asynchronous */
+    __I __C  uint8_t  RESERVED6[2];
+    __I __C  uint16_t   STAT;                          /*!< Status */
+    __I __C  uint8_t  RESERVED7[2];
+    __IO     uint16_t   PWMCTL;                        /*!< PWM Control Register */
+    __I __C  uint8_t  RESERVED8[2];
+    __IO     uint16_t   PWMMATCH;                      /*!< PWM Match Value */
+    __I __C  uint8_t  RESERVED9[2];
+    __IO     uint16_t   EVENTSELECT;                   /*!< Timer Event Selection Register */
+} ADI_TMR_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup TMR_RGB Timer_RGB with 3 PWM outputs (TMR_RGB) Module
+ *  Timer_RGB with 3 PWM outputs
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_TMR_RGB_TypeDef
+ *  \brief  Timer_RGB with 3 PWM outputs
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_TypeDef__
+typedef struct _ADI_TMR_RGB_TypeDef
+{
+    __IO     uint16_t   LOAD;                          /*!< 16-bit load value */
+    __I __C  uint8_t  RESERVED0[2];
+    __I __C  uint16_t   CURCNT;                        /*!< 16-bit timer value */
+    __I __C  uint8_t  RESERVED1[2];
+    __IO     uint16_t   CTL;                           /*!< Control */
+    __I __C  uint8_t  RESERVED2[2];
+    __O      uint16_t   CLRINT;                        /*!< Clear interrupt */
+    __I __C  uint8_t  RESERVED3[2];
+    __I __C  uint16_t   CAPTURE;                       /*!< Capture */
+    __I __C  uint8_t  RESERVED4[2];
+    __IO     uint16_t   ALOAD;                         /*!< 16-bit load value, asynchronous */
+    __I __C  uint8_t  RESERVED5[2];
+    __I __C  uint16_t   ACURCNT;                       /*!< 16-bit timer value, asynchronous */
+    __I __C  uint8_t  RESERVED6[2];
+    __I __C  uint16_t   STAT;                          /*!< Status */
+    __I __C  uint8_t  RESERVED7[2];
+    __IO     uint16_t   PWM0CTL;                       /*!< PWM0 Control Register */
+    __I __C  uint8_t  RESERVED8[2];
+    __IO     uint16_t   PWM0MATCH;                     /*!< PWM0 Match Value */
+    __I __C  uint8_t  RESERVED9[2];
+    __IO     uint16_t   EVENTSELECT;                   /*!< Timer Event selection Register */
+    __I __C  uint8_t  RESERVED10[2];
+    __IO     uint16_t   PWM1CTL;                       /*!< PWM1 Control Register */
+    __I __C  uint8_t  RESERVED11[2];
+    __IO     uint16_t   PWM1MATCH;                     /*!< PWM1 Match Value */
+    __I __C  uint8_t  RESERVED12[2];
+    __IO     uint16_t   PWM2CTL;                       /*!< PWM2 Control Register */
+    __I __C  uint8_t  RESERVED13[2];
+    __IO     uint16_t   PWM2MATCH;                     /*!< PWM2 Match Value */
+} ADI_TMR_RGB_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup RTC Real-Time Clock (RTC) Module
+ *  Real-Time Clock
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_RTC_TypeDef
+ *  \brief  Real-Time Clock
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_TypeDef__
+typedef struct _ADI_RTC_TypeDef
+{
+    __IO     uint16_t   CR0;                           /*!< RTC Control 0 */
+    __I __C  uint8_t  RESERVED0[2];
+    __IO     uint16_t   SR0;                           /*!< RTC Status 0 */
+    __I __C  uint8_t  RESERVED1[2];
+    __I __C  uint16_t   SR1;                           /*!< RTC Status 1 */
+    __I __C  uint8_t  RESERVED2[2];
+    __IO     uint16_t   CNT0;                          /*!< RTC Count 0 */
+    __I __C  uint8_t  RESERVED3[2];
+    __IO     uint16_t   CNT1;                          /*!< RTC Count 1 */
+    __I __C  uint8_t  RESERVED4[2];
+    __IO     uint16_t   ALM0;                          /*!< RTC Alarm 0 */
+    __I __C  uint8_t  RESERVED5[2];
+    __IO     uint16_t   ALM1;                          /*!< RTC Alarm 1 */
+    __I __C  uint8_t  RESERVED6[2];
+    __IO     uint16_t   TRM;                           /*!< RTC Trim */
+    __I __C  uint8_t  RESERVED7[2];
+    __O      uint16_t   GWY;                           /*!< RTC Gateway */
+    __I __C  uint8_t  RESERVED8[6];
+    __IO     uint16_t   CR1;                           /*!< RTC Control 1 */
+    __I __C  uint8_t  RESERVED9[2];
+    __IO     uint16_t   SR2;                           /*!< RTC Status 2 */
+    __I __C  uint8_t  RESERVED10[2];
+    __I __C  uint16_t   SNAP0;                         /*!< RTC Snapshot 0 */
+    __I __C  uint8_t  RESERVED11[2];
+    __I __C  uint16_t   SNAP1;                         /*!< RTC Snapshot 1 */
+    __I __C  uint8_t  RESERVED12[2];
+    __I __C  uint16_t   SNAP2;                         /*!< RTC Snapshot 2 */
+    __I __C  uint8_t  RESERVED13[2];
+    __I __C  uint16_t   MOD;                           /*!< RTC Modulo */
+    __I __C  uint8_t  RESERVED14[2];
+    __I __C  uint16_t   CNT2;                          /*!< RTC Count 2 */
+    __I __C  uint8_t  RESERVED15[2];
+    __IO     uint16_t   ALM2;                          /*!< RTC Alarm 2 */
+    __I __C  uint8_t  RESERVED16[2];
+    __IO     uint16_t   SR3;                           /*!< RTC Status 3 */
+    __I __C  uint8_t  RESERVED17[2];
+    __IO     uint16_t   CR2IC;                         /*!< RTC Control 2 for Configuring Input Capture Channels */
+    __I __C  uint8_t  RESERVED18[2];
+    __IO     uint16_t   CR3SS;                         /*!< RTC Control 3 for Configuring SensorStrobe Channel */
+    __I __C  uint8_t  RESERVED19[2];
+    __IO     uint16_t   CR4SS;                         /*!< RTC Control 4 for Configuring SensorStrobe Channel */
+    __I __C  uint8_t  RESERVED20[2];
+    __IO     uint16_t   SSMSK;                         /*!< RTC Mask for SensorStrobe Channel */
+    __I __C  uint8_t  RESERVED21[10];
+    __I __C  uint16_t   IC2;                           /*!< RTC Input Capture Channel 2 */
+    __I __C  uint8_t  RESERVED22[2];
+    __I __C  uint16_t   IC3;                           /*!< RTC Input Capture Channel 3 */
+    __I __C  uint8_t  RESERVED23[2];
+    __I __C  uint16_t   IC4;                           /*!< RTC Input Capture Channel 4 */
+    __I __C  uint8_t  RESERVED24[2];
+    __IO     uint16_t   SS1;                           /*!< RTC SensorStrobe Channel 1 */
+    __I __C  uint8_t  RESERVED25[2];
+    __IO     uint16_t   SS2;                           /*!< RTC SensorStrobe Channel 2 */
+    __I __C  uint8_t  RESERVED26[2];
+    __IO     uint16_t   SS3;                           /*!< RTC SensorStrobe Channel 3 */
+    __I __C  uint8_t  RESERVED27[2];
+    __IO     uint16_t   SS4;                           /*!< RTC SensorStrobe Channel 4 */
+    __I __C  uint8_t  RESERVED28[2];
+    __I __C  uint16_t   SR4;                           /*!< RTC Status 4 */
+    __I __C  uint8_t  RESERVED29[2];
+    __I __C  uint16_t   SR5;                           /*!< RTC Status 5 */
+    __I __C  uint8_t  RESERVED30[2];
+    __I __C  uint16_t   SR6;                           /*!< RTC Status 6 */
+    __I __C  uint8_t  RESERVED31[2];
+    __I __C  uint16_t   SS1TGT;                        /*!< RTC SensorStrobe Channel 1 Target */
+    __I __C  uint8_t  RESERVED32[2];
+    __I __C  uint16_t   FRZCNT;                        /*!< RTC Freeze Count */
+    __I __C  uint8_t  RESERVED33[2];
+    __I __C  uint16_t   SS2TGT;                        /*!< RTC SensorStrobe Channel 2 Target */
+    __I __C  uint8_t  RESERVED34[2];
+    __I __C  uint16_t   SS3TGT;                        /*!< RTC SensorStrobe Channel 3 Target */
+    __I __C  uint8_t  RESERVED35[6];
+    __IO     uint16_t   SS1LOWDUR;                     /*!< RTC Auto-Reload Low Duration for SensorStrobe Channel 1 */
+    __I __C  uint8_t  RESERVED36[2];
+    __IO     uint16_t   SS2LOWDUR;                     /*!< RTC Auto-Reload Low Duration for SensorStrobe Channel 2 */
+    __I __C  uint8_t  RESERVED37[2];
+    __IO     uint16_t   SS3LOWDUR;                     /*!< RTC Auto-Reload Low Duration for SensorStrobe Channel 3 */
+    __I __C  uint8_t  RESERVED38[6];
+    __IO     uint16_t   SS1HIGHDUR;                    /*!< RTC Auto-Reload High Duration for SensorStrobe Channel 1 */
+    __I __C  uint8_t  RESERVED39[2];
+    __IO     uint16_t   SS2HIGHDUR;                    /*!< RTC Auto-Reload High Duration for SensorStrobe Channel 2 */
+    __I __C  uint8_t  RESERVED40[2];
+    __IO     uint16_t   SS3HIGHDUR;                    /*!< RTC Auto-Reload High Duration for SensorStrobe Channel 3 */
+    __I __C  uint8_t  RESERVED41[6];
+    __IO     uint16_t   SSMSKOT;                       /*!< RTC Masks for SensorStrobe Channels on Time Control */
+    __I __C  uint8_t  RESERVED42[2];
+    __IO     uint16_t   CR5SSS;                        /*!< RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling */
+    __I __C  uint8_t  RESERVED43[2];
+    __IO     uint16_t   CR6SSS;                        /*!< RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge */
+    __I __C  uint8_t  RESERVED44[2];
+    __IO     uint16_t   CR7SSS;                        /*!< RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity */
+    __I __C  uint8_t  RESERVED45[2];
+    __IO     uint16_t   SR7;                           /*!< RTC Status 7 */
+    __I __C  uint8_t  RESERVED46[2];
+    __I __C  uint16_t   SR8;                           /*!< RTC Status 8 */
+    __I __C  uint8_t  RESERVED47[2];
+    __I __C  uint16_t   SR9;                           /*!< RTC Status 9 */
+    __I __C  uint8_t  RESERVED48[6];
+    __IO     uint16_t   GPMUX0;                        /*!< RTC GPIO Pin Mux Control Register 0 */
+    __I __C  uint8_t  RESERVED49[2];
+    __IO     uint16_t   GPMUX1;                        /*!< RTC GPIO Pin Mux Control Register 1 */
+} ADI_RTC_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup SYS System Identification and Debug Enable (SYS) Module
+ *  System Identification and Debug Enable
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_SYS_TypeDef
+ *  \brief  System Identification and Debug Enable
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SYS_TypeDef__
+typedef struct _ADI_SYS_TypeDef
+{
+    __I __C  uint8_t  RESERVED0[32];
+    __I __C  uint16_t   ADIID;                         /*!< ADI Identification */
+    __I __C  uint8_t  RESERVED1[2];
+    __I __C  uint16_t   CHIPID;                        /*!< Chip Identifier */
+    __I __C  uint8_t  RESERVED2[26];
+    __O      uint16_t   SWDEN;                         /*!< Serial Wire Debug Enable */
+} ADI_SYS_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SYS_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup WDT Watchdog Timer (WDT) Module
+ *  Watchdog Timer
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_WDT_TypeDef
+ *  \brief  Watchdog Timer
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_TypeDef__
+typedef struct _ADI_WDT_TypeDef
+{
+    __IO     uint16_t   LOAD;                          /*!< Load Value */
+    __I __C  uint8_t  RESERVED0[2];
+    __I __C  uint16_t   CCNT;                          /*!< Current Count Value */
+    __I __C  uint8_t  RESERVED1[2];
+    __IO     uint16_t   CTL;                           /*!< Control */
+    __I __C  uint8_t  RESERVED2[2];
+    __O      uint16_t   RESTART;                       /*!< Clear Interrupt */
+    __I __C  uint8_t  RESERVED3[10];
+    __I __C  uint16_t   STAT;                          /*!< Status */
+} ADI_WDT_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup I2C I2C Master/Slave (I2C) Module
+ *  I2C Master/Slave
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_I2C_TypeDef
+ *  \brief  I2C Master/Slave
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_TypeDef__
+typedef struct _ADI_I2C_TypeDef
+{
+    __IO     uint16_t   MCTL;                          /*!< Master Control */
+    __I __C  uint8_t  RESERVED0[2];
+    __IO     uint16_t   MSTAT;                         /*!< Master Status */
+    __I __C  uint8_t  RESERVED1[2];
+    __I __C  uint16_t   MRX;                           /*!< Master Receive Data */
+    __I __C  uint8_t  RESERVED2[2];
+    __IO     uint16_t   MTX;                           /*!< Master Transmit Data */
+    __I __C  uint8_t  RESERVED3[2];
+    __IO     uint16_t   MRXCNT;                        /*!< Master Receive Data Count */
+    __I __C  uint8_t  RESERVED4[2];
+    __I __C  uint16_t   MCRXCNT;                       /*!< Master Current Receive Data Count */
+    __I __C  uint8_t  RESERVED5[2];
+    __IO     uint16_t   ADDR1;                         /*!< Master Address Byte 1 */
+    __I __C  uint8_t  RESERVED6[2];
+    __IO     uint16_t   ADDR2;                         /*!< Master Address Byte 2 */
+    __I __C  uint8_t  RESERVED7[2];
+    __IO     uint16_t   BYT;                           /*!< Start Byte */
+    __I __C  uint8_t  RESERVED8[2];
+    __IO     uint16_t   DIV;                           /*!< Serial Clock Period Divisor */
+    __I __C  uint8_t  RESERVED9[2];
+    __IO     uint16_t   SCTL;                          /*!< Slave Control */
+    __I __C  uint8_t  RESERVED10[2];
+    __IO     uint16_t   SSTAT;                         /*!< Slave I2C Status/Error/IRQ */
+    __I __C  uint8_t  RESERVED11[2];
+    __I __C  uint16_t   SRX;                           /*!< Slave Receive */
+    __I __C  uint8_t  RESERVED12[2];
+    __IO     uint16_t   STX;                           /*!< Slave Transmit */
+    __I __C  uint8_t  RESERVED13[2];
+    __IO     uint16_t   ALT;                           /*!< Hardware General Call ID */
+    __I __C  uint8_t  RESERVED14[2];
+    __IO     uint16_t   ID0;                           /*!< First Slave Address Device ID */
+    __I __C  uint8_t  RESERVED15[2];
+    __IO     uint16_t   ID1;                           /*!< Second Slave Address Device ID */
+    __I __C  uint8_t  RESERVED16[2];
+    __IO     uint16_t   ID2;                           /*!< Third Slave Address Device ID */
+    __I __C  uint8_t  RESERVED17[2];
+    __IO     uint16_t   ID3;                           /*!< Fourth Slave Address Device ID */
+    __I __C  uint8_t  RESERVED18[2];
+    __IO     uint16_t   STAT;                          /*!< Master and Slave FIFO Status */
+    __I __C  uint8_t  RESERVED19[2];
+    __O      uint16_t   SHCTL;                         /*!< Shared Control */
+    __I __C  uint8_t  RESERVED20[2];
+    __IO     uint16_t   TCTL;                          /*!< Timing Control Register */
+    __I __C  uint8_t  RESERVED21[2];
+    __IO     uint16_t   ASTRETCH_SCL;                  /*!< Automatic Stretch SCL */
+} ADI_I2C_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup SPI Serial Peripheral Interface (SPI) Module
+ *  Serial Peripheral Interface
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_SPI_TypeDef
+ *  \brief  Serial Peripheral Interface
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_TypeDef__
+typedef struct _ADI_SPI_TypeDef
+{
+    __IO     uint16_t   STAT;                          /*!< Status */
+    __I __C  uint8_t  RESERVED0[2];
+    __I __C  uint16_t   RX;                            /*!< Receive */
+    __I __C  uint8_t  RESERVED1[2];
+    __O      uint16_t   TX;                            /*!< Transmit */
+    __I __C  uint8_t  RESERVED2[2];
+    __IO     uint16_t   DIV;                           /*!< SPI Baud Rate Selection */
+    __I __C  uint8_t  RESERVED3[2];
+    __IO     uint16_t   CTL;                           /*!< SPI Configuration */
+    __I __C  uint8_t  RESERVED4[2];
+    __IO     uint16_t   IEN;                           /*!< SPI Interrupts Enable */
+    __I __C  uint8_t  RESERVED5[2];
+    __IO     uint16_t   CNT;                           /*!< Transfer Byte Count */
+    __I __C  uint8_t  RESERVED6[2];
+    __IO     uint16_t   DMA;                           /*!< SPI DMA Enable */
+    __I __C  uint8_t  RESERVED7[2];
+    __I __C  uint16_t   FIFO_STAT;                     /*!< FIFO Status */
+    __I __C  uint8_t  RESERVED8[2];
+    __IO     uint16_t   RD_CTL;                        /*!< Read Control */
+    __I __C  uint8_t  RESERVED9[2];
+    __IO     uint16_t   FLOW_CTL;                      /*!< Flow Control */
+    __I __C  uint8_t  RESERVED10[2];
+    __IO     uint16_t   WAIT_TMR;                      /*!< Wait Timer for Flow Control */
+    __I __C  uint8_t  RESERVED11[2];
+    __IO     uint16_t   CS_CTL;                        /*!< Chip Select Control for Multi-slave Connections */
+    __I __C  uint8_t  RESERVED12[2];
+    __IO     uint16_t   CS_OVERRIDE;                   /*!< Chip Select Override */
+    __I __C  uint8_t  RESERVED13[4];
+} ADI_SPI_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup UART  (UART) Module
+ *  
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_UART_TypeDef
+ *  \brief  
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_TypeDef__
+typedef struct _ADI_UART_TypeDef
+{
+    union {
+    __I __C  uint16_t   RX;                            /*!< Receive Buffer Register */
+    __O      uint16_t   TX;                            /*!< Transmit Holding Register */
+    };
+    __I __C  uint8_t  RESERVED0[2];
+    __IO     uint16_t   IEN;                           /*!< Interrupt Enable */
+    __I __C  uint8_t  RESERVED1[2];
+    __I __C  uint16_t   IIR;                           /*!< Interrupt ID */
+    __I __C  uint8_t  RESERVED2[2];
+    __IO     uint16_t   LCR;                           /*!< Line Control */
+    __I __C  uint8_t  RESERVED3[2];
+    __IO     uint16_t   MCR;                           /*!< Modem Control */
+    __I __C  uint8_t  RESERVED4[2];
+    __I __C  uint16_t   LSR;                           /*!< Line Status */
+    __I __C  uint8_t  RESERVED5[2];
+    __I __C  uint16_t   MSR;                           /*!< Modem Status */
+    __I __C  uint8_t  RESERVED6[2];
+    __IO     uint16_t   SCR;                           /*!< Scratch Buffer */
+    __I __C  uint8_t  RESERVED7[2];
+    __IO     uint16_t   FCR;                           /*!< FIFO Control */
+    __I __C  uint8_t  RESERVED8[2];
+    __IO     uint16_t   FBR;                           /*!< Fractional Baud Rate */
+    __I __C  uint8_t  RESERVED9[2];
+    __IO     uint16_t   DIV;                           /*!< Baud Rate Divider */
+    __I __C  uint8_t  RESERVED10[2];
+    __IO     uint16_t   LCR2;                          /*!< Second Line Control */
+    __I __C  uint8_t  RESERVED11[2];
+    __IO     uint16_t   CTL;                           /*!< UART Control Register */
+    __I __C  uint8_t  RESERVED12[2];
+    __I __C  uint16_t   RFC;                           /*!< RX FIFO Byte Count */
+    __I __C  uint8_t  RESERVED13[2];
+    __I __C  uint16_t   TFC;                           /*!< TX FIFO Byte Count */
+    __I __C  uint8_t  RESERVED14[2];
+    __IO     uint16_t   RSC;                           /*!< RS485 Half-duplex Control */
+    __I __C  uint8_t  RESERVED15[2];
+    __IO     uint16_t   ACR;                           /*!< Auto Baud Control */
+    __I __C  uint8_t  RESERVED16[2];
+    __I __C  uint16_t   ASRL;                          /*!< Auto Baud Status (Low) */
+    __I __C  uint8_t  RESERVED17[2];
+    __I __C  uint16_t   ASRH;                          /*!< Auto Baud Status (High) */
+} ADI_UART_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup BEEP Beeper Driver (BEEP) Module
+ *  Beeper Driver
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_BEEP_TypeDef
+ *  \brief  Beeper Driver
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_TypeDef__
+typedef struct _ADI_BEEP_TypeDef
+{
+    __IO     uint16_t   CFG;                           /*!< Beeper Configuration */
+    __I __C  uint8_t  RESERVED0[2];
+    __IO     uint16_t   STAT;                          /*!< Beeper Status */
+    __I __C  uint8_t  RESERVED1[2];
+    __IO     uint16_t   TONEA;                         /*!< Tone A Data */
+    __I __C  uint8_t  RESERVED2[2];
+    __IO     uint16_t   TONEB;                         /*!< Tone B Data */
+} ADI_BEEP_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup ADC  (ADC) Module
+ *  
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_ADC_TypeDef
+ *  \brief  
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_TypeDef__
+typedef struct _ADI_ADC_TypeDef
+{
+    __IO     uint16_t   CFG;                           /*!< ADC Configuration */
+    __I __C  uint8_t  RESERVED0[2];
+    __IO     uint16_t   PWRUP;                         /*!< ADC Power-up Time */
+    __I __C  uint8_t  RESERVED1[2];
+    __IO     uint16_t   CAL_WORD;                      /*!< Calibration Word */
+    __I __C  uint8_t  RESERVED2[2];
+    __IO     uint16_t   CNV_CFG;                       /*!< ADC Conversion Configuration */
+    __I __C  uint8_t  RESERVED3[2];
+    __IO     uint16_t   CNV_TIME;                      /*!< ADC Conversion Time */
+    __I __C  uint8_t  RESERVED4[2];
+    __IO     uint16_t   AVG_CFG;                       /*!< Averaging Configuration */
+    __I __C  uint8_t  RESERVED5[10];
+    __IO     uint16_t   IRQ_EN;                        /*!< Interrupt Enable */
+    __I __C  uint8_t  RESERVED6[2];
+    __IO     uint16_t   STAT;                          /*!< ADC Status */
+    __I __C  uint8_t  RESERVED7[2];
+    __IO     uint16_t   OVF;                           /*!< Overflow of Output Registers */
+    __I __C  uint8_t  RESERVED8[2];
+    __IO     uint16_t   ALERT;                         /*!< Alert Indication */
+    __I __C  uint8_t  RESERVED9[2];
+    __I __C  uint16_t   CH0_OUT;                       /*!< Conversion Result Channel 0 */
+    __I __C  uint8_t  RESERVED10[2];
+    __I __C  uint16_t   CH1_OUT;                       /*!< Conversion Result Channel 1 */
+    __I __C  uint8_t  RESERVED11[2];
+    __I __C  uint16_t   CH2_OUT;                       /*!< Conversion Result Channel 2 */
+    __I __C  uint8_t  RESERVED12[2];
+    __I __C  uint16_t   CH3_OUT;                       /*!< Conversion Result Channel 3 */
+    __I __C  uint8_t  RESERVED13[2];
+    __I __C  uint16_t   CH4_OUT;                       /*!< Conversion Result Channel 4 */
+    __I __C  uint8_t  RESERVED14[2];
+    __I __C  uint16_t   CH5_OUT;                       /*!< Conversion Result Channel 5 */
+    __I __C  uint8_t  RESERVED15[2];
+    __I __C  uint16_t   CH6_OUT;                       /*!< Conversion Result Channel 6 */
+    __I __C  uint8_t  RESERVED16[2];
+    __I __C  uint16_t   CH7_OUT;                       /*!< Conversion Result Channel 7 */
+    __I __C  uint8_t  RESERVED17[2];
+    __I __C  uint16_t   BAT_OUT;                       /*!< Battery Monitoring Result */
+    __I __C  uint8_t  RESERVED18[2];
+    __I __C  uint16_t   TMP_OUT;                       /*!< Temperature Result */
+    __I __C  uint8_t  RESERVED19[2];
+    __I __C  uint16_t   TMP2_OUT;                      /*!< Temperature Result 2 */
+    __I __C  uint8_t  RESERVED20[2];
+    __I __C  uint16_t   DMA_OUT;                       /*!< DMA Output Register */
+    __I __C  uint8_t  RESERVED21[2];
+    __IO     uint16_t   LIM0_LO;                       /*!< Channel 0 Low Limit */
+    __I __C  uint8_t  RESERVED22[2];
+    __IO     uint16_t   LIM0_HI;                       /*!< Channel 0 High Limit */
+    __I __C  uint8_t  RESERVED23[2];
+    __IO     uint16_t   HYS0;                          /*!< Channel 0 Hysteresis */
+    __I __C  uint8_t  RESERVED24[6];
+    __IO     uint16_t   LIM1_LO;                       /*!< Channel 1 Low Limit */
+    __I __C  uint8_t  RESERVED25[2];
+    __IO     uint16_t   LIM1_HI;                       /*!< Channel 1 High Limit */
+    __I __C  uint8_t  RESERVED26[2];
+    __IO     uint16_t   HYS1;                          /*!< Channel 1 Hysteresis */
+    __I __C  uint8_t  RESERVED27[6];
+    __IO     uint16_t   LIM2_LO;                       /*!< Channel 2 Low Limit */
+    __I __C  uint8_t  RESERVED28[2];
+    __IO     uint16_t   LIM2_HI;                       /*!< Channel 2 High Limit */
+    __I __C  uint8_t  RESERVED29[2];
+    __IO     uint16_t   HYS2;                          /*!< Channel 2 Hysteresis */
+    __I __C  uint8_t  RESERVED30[6];
+    __IO     uint16_t   LIM3_LO;                       /*!< Channel 3 Low Limit */
+    __I __C  uint8_t  RESERVED31[2];
+    __IO     uint16_t   LIM3_HI;                       /*!< Channel 3 High Limit */
+    __I __C  uint8_t  RESERVED32[2];
+    __IO     uint16_t   HYS3;                          /*!< Channel 3 Hysteresis */
+    __I __C  uint8_t  RESERVED33[38];
+    __IO     uint16_t   CFG1;                          /*!< Reference Buffer Low Power Mode */
+    __I __C  uint8_t  RESERVED34[576];
+} ADI_ADC_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup DMA DMA (DMA) Module
+ *  DMA
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_DMA_TypeDef
+ *  \brief  DMA
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_TypeDef__
+typedef struct _ADI_DMA_TypeDef
+{
+    __I __C  uint32_t   STAT;                          /*!< DMA Status */
+    __O      uint32_t   CFG;                           /*!< DMA Configuration */
+    __IO     uint32_t   PDBPTR;                        /*!< DMA Channel Primary Control Database Pointer */
+    __I __C  uint32_t   ADBPTR;                        /*!< DMA Channel Alternate Control Database Pointer */
+    __I __C  uint8_t  RESERVED0[4];
+    __O      uint32_t   SWREQ;                         /*!< DMA Channel Software Request */
+    __I __C  uint8_t  RESERVED1[8];
+    __IO     uint32_t   RMSK_SET;                      /*!< DMA Channel Request Mask Set */
+    __O      uint32_t   RMSK_CLR;                      /*!< DMA Channel Request Mask Clear */
+    __IO     uint32_t   EN_SET;                        /*!< DMA Channel Enable Set */
+    __O      uint32_t   EN_CLR;                        /*!< DMA Channel Enable Clear */
+    __IO     uint32_t   ALT_SET;                       /*!< DMA Channel Primary Alternate Set */
+    __O      uint32_t   ALT_CLR;                       /*!< DMA Channel Primary Alternate Clear */
+    __O      uint32_t   PRI_SET;                       /*!< DMA Channel Priority Set */
+    __O      uint32_t   PRI_CLR;                       /*!< DMA Channel Priority Clear */
+    __I __C  uint8_t  RESERVED2[8];
+    __IO     uint32_t   ERRCHNL_CLR;                   /*!< DMA per Channel Error Clear */
+    __IO     uint32_t   ERR_CLR;                       /*!< DMA Bus Error Clear */
+    __IO     uint32_t   INVALIDDESC_CLR;               /*!< DMA per Channel Invalid Descriptor Clear */
+    __I __C  uint8_t  RESERVED3[1964];
+    __IO     uint32_t   BS_SET;                        /*!< DMA Channel Bytes Swap Enable Set */
+    __O      uint32_t   BS_CLR;                        /*!< DMA Channel Bytes Swap Enable Clear */
+    __I __C  uint8_t  RESERVED4[8];
+    __IO     uint32_t   SRCADDR_SET;                   /*!< DMA Channel Source Address Decrement Enable Set */
+    __O      uint32_t   SRCADDR_CLR;                   /*!< DMA Channel Source Address Decrement Enable Clear */
+    __IO     uint32_t   DSTADDR_SET;                   /*!< DMA Channel Destination Address Decrement Enable Set */
+    __O      uint32_t   DSTADDR_CLR;                   /*!< DMA Channel Destination Address Decrement Enable Clear */
+    __I __C  uint8_t  RESERVED5[1984];
+    __I __C  uint32_t   REVID;                         /*!< DMA Controller Revision ID */
+} ADI_DMA_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup FLCC Flash Controller (FLCC) Module
+ *  Flash Controller
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_FLCC_TypeDef
+ *  \brief  Flash Controller
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_TypeDef__
+typedef struct _ADI_FLCC_TypeDef
+{
+    __IO     uint32_t   STAT;                          /*!< Status */
+    __IO     uint32_t   IEN;                           /*!< Interrupt Enable */
+    __IO     uint32_t   CMD;                           /*!< Command */
+    __IO     uint32_t   KH_ADDR;                       /*!< Write Address */
+    __IO     uint32_t   KH_DATA0;                      /*!< Write Lower Data */
+    __IO     uint32_t   KH_DATA1;                      /*!< Write Upper Data */
+    __IO     uint32_t   PAGE_ADDR0;                    /*!< Lower Page Address */
+    __IO     uint32_t   PAGE_ADDR1;                    /*!< Upper Page Address */
+    __O      uint32_t   KEY;                           /*!< Key */
+    __I __C  uint32_t   WR_ABORT_ADDR;                 /*!< Write Abort Address */
+    __IO     uint32_t   WRPROT;                        /*!< Write Protection */
+    __I __C  uint32_t   SIGNATURE;                     /*!< Signature */
+    __IO     uint32_t   UCFG;                          /*!< User Configuration */
+    __IO     uint32_t   TIME_PARAM0;                   /*!< Time Parameter 0 */
+    __IO     uint32_t   TIME_PARAM1;                   /*!< Time Parameter 1 */
+    __IO     uint32_t   ABORT_EN_LO;                   /*!< IRQ Abort Enable (Lower Bits) */
+    __IO     uint32_t   ABORT_EN_HI;                   /*!< IRQ Abort Enable (Upper Bits) */
+    __IO     uint32_t   ECC_CFG;                       /*!< ECC Configuration */
+    __I __C  uint32_t   ECC_ADDR;                      /*!< ECC Status (Address) */
+    __I __C  uint8_t  RESERVED0[4];
+    __IO     uint32_t   POR_SEC;                       /*!< Flash Security */
+    __IO     uint32_t   VOL_CFG;                       /*!< Volatile Flash Configuration */
+} ADI_FLCC_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup FLCC_CACHE Cache Controller (FLCC_CACHE) Module
+ *  Cache Controller
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_FLCC_CACHE_TypeDef
+ *  \brief  Cache Controller
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_TypeDef__
+typedef struct _ADI_FLCC_CACHE_TypeDef
+{
+    __I __C  uint32_t   STAT;                          /*!< Cache Status Register */
+    __IO     uint32_t   SETUP;                         /*!< Cache Setup Register */
+    __O      uint32_t   KEY;                           /*!< Cache Key Register */
+    __I __C  uint8_t  RESERVED0[40];
+} ADI_FLCC_CACHE_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup GPIO  (GPIO) Module
+ *  
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_GPIO_TypeDef
+ *  \brief  
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_TypeDef__
+typedef struct _ADI_GPIO_TypeDef
+{
+    __IO     uint32_t   CFG;                           /*!< Port  Configuration */
+    __IO     uint16_t   OEN;                           /*!< Port Output Enable */
+    __I __C  uint8_t  RESERVED0[2];
+    __IO     uint16_t   PE;                            /*!< Port Output Pull-up/Pull-down Enable */
+    __I __C  uint8_t  RESERVED1[2];
+    __IO     uint16_t   IEN;                           /*!< Port  Input Path Enable */
+    __I __C  uint8_t  RESERVED2[2];
+    __I __C  uint16_t   IN;                            /*!< Port  Registered Data Input */
+    __I __C  uint8_t  RESERVED3[2];
+    __IO     uint16_t   OUT;                           /*!< Port Data Output */
+    __I __C  uint8_t  RESERVED4[2];
+    __O      uint16_t   SET;                           /*!< Port Data Out Set */
+    __I __C  uint8_t  RESERVED5[2];
+    __O      uint16_t   CLR;                           /*!< Port Data Out Clear */
+    __I __C  uint8_t  RESERVED6[2];
+    __O      uint16_t   TGL;                           /*!< Port Pin Toggle */
+    __I __C  uint8_t  RESERVED7[2];
+    __IO     uint16_t   POL;                           /*!< Port Interrupt Polarity */
+    __I __C  uint8_t  RESERVED8[2];
+    __IO     uint16_t   IENA;                          /*!< Port Interrupt A Enable */
+    __I __C  uint8_t  RESERVED9[2];
+    __IO     uint16_t   IENB;                          /*!< Port Interrupt B Enable */
+    __I __C  uint8_t  RESERVED10[2];
+    __IO     uint16_t   INT;                           /*!< Port Interrupt Status */
+    __I __C  uint8_t  RESERVED11[2];
+    __IO     uint16_t   DS;                            /*!< Port Drive Strength Select */
+} ADI_GPIO_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup SPORT Serial Port (SPORT) Module
+ *  Serial Port
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_SPORT_TypeDef
+ *  \brief  Serial Port
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_TypeDef__
+typedef struct _ADI_SPORT_TypeDef
+{
+    __IO     uint32_t   CTL_A;                         /*!< Half SPORT 'A' Control Register */
+    __IO     uint32_t   DIV_A;                         /*!< Half SPORT 'A' Divisor Register */
+    __IO     uint32_t   IEN_A;                         /*!< Half SPORT A's Interrupt Enable register */
+    __IO     uint32_t   STAT_A;                        /*!< Half SPORT 'A' Status register */
+    __IO     uint32_t   NUMTRAN_A;                     /*!< Half SPORT A Number of transfers register */
+    __IO     uint32_t   CNVT_A;                        /*!< Half SPORT 'A' CNV width */
+    __I __C  uint8_t  RESERVED0[8];
+    __O      uint32_t   TX_A;                          /*!< Half SPORT 'A' Tx Buffer Register */
+    __I __C  uint8_t  RESERVED1[4];
+    __I __C  uint32_t   RX_A;                          /*!< Half SPORT 'A' Rx Buffer Register */
+    __I __C  uint8_t  RESERVED2[20];
+    __IO     uint32_t   CTL_B;                         /*!< Half SPORT 'B' Control Register */
+    __IO     uint32_t   DIV_B;                         /*!< Half SPORT 'B' Divisor Register */
+    __IO     uint32_t   IEN_B;                         /*!< Half SPORT B's Interrupt Enable register */
+    __IO     uint32_t   STAT_B;                        /*!< Half SPORT 'B' Status register */
+    __IO     uint32_t   NUMTRAN_B;                     /*!< Half SPORT B Number of transfers register */
+    __IO     uint32_t   CNVT_B;                        /*!< Half SPORT 'B' CNV width register */
+    __I __C  uint8_t  RESERVED3[8];
+    __O      uint32_t   TX_B;                          /*!< Half SPORT 'B' Tx Buffer Register */
+    __I __C  uint8_t  RESERVED4[4];
+    __I __C  uint32_t   RX_B;                          /*!< Half SPORT 'B' Rx Buffer Register */
+    __I __C  uint8_t  RESERVED5[16];
+} ADI_SPORT_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup CRC CRC Accelerator (CRC) Module
+ *  CRC Accelerator
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_CRC_TypeDef
+ *  \brief  CRC Accelerator
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_TypeDef__
+typedef struct _ADI_CRC_TypeDef
+{
+    __IO     uint32_t   CTL;                           /*!< CRC Control */
+    __O      uint32_t   IPDATA;                        /*!< Input Data Word */
+    __IO     uint32_t   RESULT;                        /*!< CRC Result */
+    __IO     uint32_t   POLY;                          /*!< Programmable CRC Polynomial */
+    union {
+    __O      uint8_t    IPBITS[8];                     /*!< Input Data Bits */
+    __O      uint8_t    IPBYTE;                        /*!< Input Data Byte */
+    };
+} ADI_CRC_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup RNG Random Number Generator (RNG) Module
+ *  Random Number Generator
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_RNG_TypeDef
+ *  \brief  Random Number Generator
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_TypeDef__
+typedef struct _ADI_RNG_TypeDef
+{
+    __IO     uint16_t   CTL;                           /*!< RNG Control Register */
+    __I __C  uint8_t  RESERVED0[2];
+    __IO     uint16_t   LEN;                           /*!< RNG Sample Length Register */
+    __I __C  uint8_t  RESERVED1[2];
+    __IO     uint16_t   STAT;                          /*!< RNG Status Register */
+    __I __C  uint8_t  RESERVED2[2];
+    __I __C  uint32_t   DATA;                          /*!< RNG Data Register */
+    __I __C  uint32_t   OSCCNT;                        /*!< Oscillator Count */
+    __I __C  int8_t     OSCDIFF[4];                    /*!< Oscillator Difference */
+} ADI_RNG_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup CRYPT Register Map for the Crypto Block (CRYPT) Module
+ *  Register Map for the Crypto Block
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_CRYPT_TypeDef
+ *  \brief  Register Map for the Crypto Block
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_TypeDef__
+typedef struct _ADI_CRYPT_TypeDef
+{
+    __IO     uint32_t   CFG;                           /*!< Configuration Register */
+    __IO     uint32_t   DATALEN;                       /*!< Payload Data Length */
+    __IO     uint32_t   PREFIXLEN;                     /*!< Authentication Data Length */
+    __IO     uint32_t   INTEN;                         /*!< Interrupt Enable Register */
+    __IO     uint32_t   STAT;                          /*!< Status Register */
+    __O      uint32_t   INBUF;                         /*!< Input Buffer */
+    __I __C  uint32_t   OUTBUF;                        /*!< Output Buffer */
+    __IO     uint32_t   NONCE0;                        /*!< Nonce Bits [31:0] */
+    __IO     uint32_t   NONCE1;                        /*!< Nonce Bits [63:32] */
+    __IO     uint32_t   NONCE2;                        /*!< Nonce Bits [95:64] */
+    __IO     uint32_t   NONCE3;                        /*!< Nonce Bits [127:96] */
+    __O      uint32_t   AESKEY0;                       /*!< AES Key Bits [31:0] */
+    __O      uint32_t   AESKEY1;                       /*!< AES Key Bits [63:32] */
+    __O      uint32_t   AESKEY2;                       /*!< AES Key Bits [95:64] */
+    __O      uint32_t   AESKEY3;                       /*!< AES Key Bits [127:96] */
+    __O      uint32_t   AESKEY4;                       /*!< AES Key Bits [159:128] */
+    __O      uint32_t   AESKEY5;                       /*!< AES Key Bits [191:160] */
+    __O      uint32_t   AESKEY6;                       /*!< AES Key Bits [223:192] */
+    __O      uint32_t   AESKEY7;                       /*!< AES Key Bits [255:224] */
+    __IO     uint32_t   CNTRINIT;                      /*!< Counter Initialization Vector */
+    __IO     uint32_t   SHAH0;                         /*!< SHA Bits [31:0] */
+    __IO     uint32_t   SHAH1;                         /*!< SHA Bits [63:32] */
+    __IO     uint32_t   SHAH2;                         /*!< SHA Bits [95:64] */
+    __IO     uint32_t   SHAH3;                         /*!< SHA Bits [127:96] */
+    __IO     uint32_t   SHAH4;                         /*!< SHA Bits [159:128] */
+    __IO     uint32_t   SHAH5;                         /*!< SHA Bits [191:160] */
+    __IO     uint32_t   SHAH6;                         /*!< SHA Bits [223:192] */
+    __IO     uint32_t   SHAH7;                         /*!< SHA Bits [255:224] */
+    __IO     uint32_t   SHA_LAST_WORD;                 /*!< SHA Last Word and Valid Bits Information */
+    __IO     uint32_t   CCM_NUM_VALID_BYTES;           /*!< NUM_VALID_BYTES */
+    __IO     uint32_t   PRKSTORCFG;                    /*!< PRKSTOR Configuration */
+    __I __C  uint8_t  RESERVED0[4];
+    __O      uint32_t   KUW0;                          /*!< Key Wrap Unwrap Register 0 */
+    __O      uint32_t   KUW1;                          /*!< Key Wrap Unwrap Register 1 */
+    __O      uint32_t   KUW2;                          /*!< Key Wrap Unwrap Register 2 */
+    __O      uint32_t   KUW3;                          /*!< Key Wrap Unwrap Register 3 */
+    __O      uint32_t   KUW4;                          /*!< Key Wrap Unwrap Register 4 */
+    __O      uint32_t   KUW5;                          /*!< Key Wrap Unwrap Register 5 */
+    __O      uint32_t   KUW6;                          /*!< Key Wrap Unwrap Register 6 */
+    __O      uint32_t   KUW7;                          /*!< Key Wrap Unwrap Register 7 */
+    __O      uint32_t   KUW8;                          /*!< Key Wrap Unwrap Register 8 */
+    __O      uint32_t   KUW9;                          /*!< Key Wrap Unwrap Register 9 */
+    __O      uint32_t   KUW10;                         /*!< Key Wrap Unwrap Register 10 */
+    __O      uint32_t   KUW11;                         /*!< Key Wrap Unwrap Register 11 */
+    __O      uint32_t   KUW12;                         /*!< Key Wrap Unwrap Register 12 */
+    __O      uint32_t   KUW13;                         /*!< Key Wrap Unwrap Register 13 */
+    __O      uint32_t   KUW14;                         /*!< Key Wrap Unwrap Register 14 */
+    __O      uint32_t   KUW15;                         /*!< Key Wrap Unwrap Register 15 */
+    __O      uint32_t   KUWVALSTR1;                    /*!< Key Wrap Unwrap Validation String [63:32] */
+    __O      uint32_t   KUWVALSTR2;                    /*!< Key Wrap Unwrap Validation String [31:0] */
+} ADI_CRYPT_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup PMG Power Management  (PMG) Module
+ *  Power Management 
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_PMG_TypeDef
+ *  \brief  Power Management 
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TypeDef__
+typedef struct _ADI_PMG_TypeDef
+{
+    __IO     uint32_t   IEN;                           /*!< Power Supply Monitor Interrupt Enable */
+    __IO     uint32_t   PSM_STAT;                      /*!< Power Supply Monitor Status */
+    __IO     uint32_t   PWRMOD;                        /*!< Power Mode Register */
+    __O      uint32_t   PWRKEY;                        /*!< Key Protection for PWRMOD and  SRAMRET */
+    __I __C  uint32_t   SHDN_STAT;                     /*!< Shutdown Status Register */
+    __IO     uint32_t   SRAMRET;                       /*!< Control for Retention SRAM in Hibernate Mode */
+    __I __C  uint8_t  RESERVED0[32];
+    __IO     uint32_t   TRIM;                          /*!< Trimming Bits */
+    __I __C  uint8_t  RESERVED1[4];
+    __IO     uint32_t   RST_STAT;                      /*!< Reset Status */
+    __IO     uint32_t   CTL1;                          /*!< HPBUCK Control */
+    __I __C  uint8_t  RESERVED2[20];
+} ADI_PMG_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup XINT External interrupt configuration (XINT) Module
+ *  External interrupt configuration
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_XINT_TypeDef
+ *  \brief  External interrupt configuration
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_TypeDef__
+typedef struct _ADI_XINT_TypeDef
+{
+    __IO     uint32_t   CFG0;                          /*!< External Interrupt configuration */
+    __I __C  uint32_t   EXT_STAT;                      /*!< External Wakeup Interrupt Status register */
+    __I __C  uint8_t  RESERVED0[8];
+    __IO     uint32_t   CLR;                           /*!< External Interrupt clear */
+    __IO     uint32_t   NMICLR;                        /*!< Non-maskable interrupt clear */
+} ADI_XINT_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup CLKG_OSC Clocking  (CLKG_OSC) Module
+ *  Clocking 
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_CLKG_OSC_TypeDef
+ *  \brief  Clocking 
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_TypeDef__
+typedef struct _ADI_CLKG_OSC_TypeDef
+{
+    __I __C  uint8_t  RESERVED0[12];
+    __O      uint32_t   KEY;                           /*!< Key Protection for OSCCTRL */
+    __IO     uint32_t   CTL;                           /*!< Oscillator Control */
+    __I __C  uint8_t  RESERVED1[8];
+} ADI_CLKG_OSC_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup PMG_TST Power Management  (PMG_TST) Module
+ *  Power Management 
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_PMG_TST_TypeDef
+ *  \brief  Power Management 
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_TypeDef__
+typedef struct _ADI_PMG_TST_TypeDef
+{
+    __I __C  uint8_t  RESERVED0[96];
+    __IO     uint32_t   SRAM_CTL;                      /*!< Control for SRAM Parity and Instruction SRAM */
+    __I __C  uint32_t   SRAM_INITSTAT;                 /*!< Initialization Status Register */
+    __O      uint16_t   CLR_LATCH_GPIOS;               /*!< Clear GPIO After Shutdown Mode */
+    __I __C  uint8_t  RESERVED1[2];
+    __IO     uint32_t   SCRPAD_IMG;                    /*!< Scratch Pad Image */
+    __I __C  uint32_t   SCRPAD_3V_RD;                  /*!< Scratch Pad Saved in Battery Domain */
+    __IO     uint32_t   FAST_SHT_WAKEUP;               /*!< Fast Shutdown Wake-up Enable */
+} ADI_PMG_TST_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup CLKG_CLK Clocking  (CLKG_CLK) Module
+ *  Clocking 
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_CLKG_CLK_TypeDef
+ *  \brief  Clocking 
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_TypeDef__
+typedef struct _ADI_CLKG_CLK_TypeDef
+{
+    __IO     uint32_t   CTL0;                          /*!< Misc Clock Settings */
+    __IO     uint32_t   CTL1;                          /*!< Clock Dividers */
+    __IO     uint32_t   CTL2;                          /*!< HF Oscillator Divided Clock Select */
+    __IO     uint32_t   CTL3;                          /*!< System PLL */
+    __I __C  uint8_t  RESERVED0[4];
+    __IO     uint32_t   CTL5;                          /*!< User Clock Gating Control */
+    __IO     uint32_t   STAT0;                         /*!< Clocking Status */
+    __I __C  uint8_t  RESERVED1[20];
+} ADI_CLKG_CLK_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup BUSM Bus matrix (BUSM) Module
+ *  Bus matrix
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_BUSM_TypeDef
+ *  \brief  Bus matrix
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_TypeDef__
+typedef struct _ADI_BUSM_TypeDef
+{
+    __IO     uint32_t   ARBIT0;                        /*!< Arbitration Priority Configuration for FLASH and SRAM0 */
+    __IO     uint32_t   ARBIT1;                        /*!< Arbitration Priority Configuration for SRAM1 and SIP */
+    __IO     uint32_t   ARBIT2;                        /*!< Arbitration Priority Configuration for APB32 and APB16 */
+    __IO     uint32_t   ARBIT3;                        /*!< Arbitration Priority Configuration for APB16 priority for core and for DMA1 */
+    __I __C  uint8_t  RESERVED0[4];
+    __IO     uint32_t   ARBIT4;                        /*!< Arbitration Priority Configuration for SRAM1 and SIP */
+} ADI_BUSM_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup PTI Parallel Test Interface (PTI) Module
+ *  Parallel Test Interface
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_PTI_TypeDef
+ *  \brief  Parallel Test Interface
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PTI_TypeDef__
+typedef struct _ADI_PTI_TypeDef
+{
+    __IO     uint32_t   RST_ISR_STARTADDR;             /*!< Reset ISR Start Address */
+    __IO     uint32_t   RST_STACK_PTR;                 /*!< Reset Stack Pointer */
+    __IO     uint32_t   CTL;                           /*!< Parallel Test Interface Control Register */
+} ADI_PTI_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PTI_TypeDef__ */
+
+/*!@}*/
+
+/** @defgroup NVIC Cortex-M3 Interrupt Controller (NVIC) Module
+ *  Cortex-M3 Interrupt Controller
+ *  @{
+ */
+
+/*! ==========================================================================
+ *  \struct ADI_NVIC_TypeDef
+ *  \brief  Cortex-M3 Interrupt Controller
+ *  ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_TypeDef__
+typedef struct _ADI_NVIC_TypeDef
+{
+    __I __C  uint8_t  RESERVED0[4];
+    __IO     uint32_t   INTNUM;                        /*!< Interrupt Control Type */
+    __I __C  uint8_t  RESERVED1[8];
+    __IO     uint32_t   STKSTA;                        /*!< Systick Control and Status */
+    __IO     uint32_t   STKLD;                         /*!< Systick Reload Value */
+    __IO     uint32_t   STKVAL;                        /*!< Systick Current Value */
+    __IO     uint32_t   STKCAL;                        /*!< Systick Calibration Value */
+    __I __C  uint8_t  RESERVED2[224];
+    __IO     uint32_t   INTSETE0;                      /*!< IRQ0..31 Set_Enable */
+    __IO     uint32_t   INTSETE1;                      /*!< IRQ32..63 Set_Enable */
+    __I __C  uint8_t  RESERVED3[120];
+    __IO     uint32_t   INTCLRE0;                      /*!< IRQ0..31 Clear_Enable */
+    __IO     uint32_t   INTCLRE1;                      /*!< IRQ32..63 Clear_Enable */
+    __I __C  uint8_t  RESERVED4[120];
+    __IO     uint32_t   INTSETP0;                      /*!< IRQ0..31 Set_Pending */
+    __IO     uint32_t   INTSETP1;                      /*!< IRQ32..63 Set_Pending */
+    __I __C  uint8_t  RESERVED5[120];
+    __IO     uint32_t   INTCLRP0;                      /*!< IRQ0..31 Clear_Pending */
+    __IO     uint32_t   INTCLRP1;                      /*!< IRQ32..63 Clear_Pending */
+    __I __C  uint8_t  RESERVED6[120];
+    __IO     uint32_t   INTACT0;                       /*!< IRQ0..31 Active Bit */
+    __IO     uint32_t   INTACT1;                       /*!< IRQ32..63 Active Bit */
+    __I __C  uint8_t  RESERVED7[248];
+    __IO     uint32_t   INTPRI0;                       /*!< IRQ0..3 Priority */
+    __IO     uint32_t   INTPRI1;                       /*!< IRQ4..7 Priority */
+    __IO     uint32_t   INTPRI2;                       /*!< IRQ8..11 Priority */
+    __IO     uint32_t   INTPRI3;                       /*!< IRQ12..15 Priority */
+    __IO     uint32_t   INTPRI4;                       /*!< IRQ16..19 Priority */
+    __IO     uint32_t   INTPRI5;                       /*!< IRQ20..23 Priority */
+    __IO     uint32_t   INTPRI6;                       /*!< IRQ24..27 Priority */
+    __IO     uint32_t   INTPRI7;                       /*!< IRQ28..31 Priority */
+    __IO     uint32_t   INTPRI8;                       /*!< IRQ32..35 Priority */
+    __IO     uint32_t   INTPRI9;                       /*!< IRQ36..39 Priority */
+    __IO     uint32_t   INTPRI10;                      /*!< IRQ40..43 Priority */
+    __I __C  uint8_t  RESERVED8[2260];
+    __IO     uint32_t   INTCPID;                       /*!< CPUID Base */
+    __IO     uint32_t   INTSTA;                        /*!< Interrupt Control State */
+    __IO     uint32_t   INTVEC;                        /*!< Vector Table Offset */
+    __IO     uint32_t   INTAIRC;                       /*!< Application Interrupt/Reset Control */
+    __IO     uint16_t   INTCON0;                       /*!< System Control */
+    __I __C  uint8_t  RESERVED9[2];
+    __IO     uint32_t   INTCON1;                       /*!< Configuration Control */
+    __IO     uint32_t   INTSHPRIO0;                    /*!< System Handlers 4-7 Priority */
+    __IO     uint32_t   INTSHPRIO1;                    /*!< System Handlers 8-11 Priority */
+    __IO     uint32_t   INTSHPRIO3;                    /*!< System Handlers 12-15 Priority */
+    __IO     uint32_t   INTSHCSR;                      /*!< System Handler Control and State */
+    __IO     uint32_t   INTCFSR;                       /*!< Configurable Fault Status */
+    __IO     uint32_t   INTHFSR;                       /*!< Hard Fault Status */
+    __IO     uint32_t   INTDFSR;                       /*!< Debug Fault Status */
+    __IO     uint32_t   INTMMAR;                       /*!< Mem Manage Address */
+    __IO     uint32_t   INTBFAR;                       /*!< Bus Fault Address */
+    __IO     uint32_t   INTAFSR;                       /*!< Auxiliary Fault Status */
+    __IO     uint32_t   INTPFR0;                       /*!< Processor Feature Register 0 */
+    __IO     uint32_t   INTPFR1;                       /*!< Processor Feature Register 1 */
+    __IO     uint32_t   INTDFR0;                       /*!< Debug Feature Register 0 */
+    __IO     uint32_t   INTAFR0;                       /*!< Auxiliary Feature Register 0 */
+    __IO     uint32_t   INTMMFR0;                      /*!< Memory Model Feature Register 0 */
+    __IO     uint32_t   INTMMFR1;                      /*!< Memory Model Feature Register 1 */
+    __IO     uint32_t   INTMMFR2;                      /*!< Memory Model Feature Register 2 */
+    __IO     uint32_t   INTMMFR3;                      /*!< Memory Model Feature Register 3 */
+    __IO     uint32_t   INTISAR0;                      /*!< ISA Feature Register 0 */
+    __IO     uint32_t   INTISAR1;                      /*!< ISA Feature Register 1 */
+    __IO     uint32_t   INTISAR2;                      /*!< ISA Feature Register 2 */
+    __IO     uint32_t   INTISAR3;                      /*!< ISA Feature Register 3 */
+    __IO     uint32_t   INTISAR4;                      /*!< ISA Feature Register 4 */
+    __I __C  uint8_t  RESERVED10[396];
+    __IO     uint32_t   INTTRGI;                       /*!< Software Trigger Interrupt Register */
+    __I __C  uint8_t  RESERVED11[204];
+    __IO     uint32_t   INTPID4;                       /*!< Peripheral Identification Register 4 */
+    __IO     uint32_t   INTPID5;                       /*!< Peripheral Identification Register 5 */
+    __IO     uint32_t   INTPID6;                       /*!< Peripheral Identification Register 6 */
+    __IO     uint32_t   INTPID7;                       /*!< Peripheral Identification Register 7 */
+    __IO     uint32_t   INTPID0;                       /*!< Peripheral Identification Bits7:0 */
+    __IO     uint32_t   INTPID1;                       /*!< Peripheral Identification Bits15:8 */
+    __IO     uint32_t   INTPID2;                       /*!< Peripheral Identification Bits16:23 */
+    __IO     uint32_t   INTPID3;                       /*!< Peripheral Identification Bits24:31 */
+    __IO     uint32_t   INTCID0;                       /*!< Component Identification Bits7:0 */
+    __IO     uint32_t   INTCID1;                       /*!< Component Identification Bits15:8 */
+    __IO     uint32_t   INTCID2;                       /*!< Component Identification Bits16:23 */
+    __IO     uint32_t   INTCID3;                       /*!< Component Identification Bits24:31 */
+} ADI_NVIC_TypeDef;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_TypeDef__ */
+
+/*!@}*/
+
+/* ******************************************************************************
+ *    Peripheral Memory Map Declarations
+ * *****************************************************************************/
+/*!    @defgroup PMEMMAPDEC Peripheral Memory Map Declarations
+ *     \addtogroup PMEMMAPDEC
+ *     @{ */
+#define ADI_TMR0_BASE                  0x40000000    /*!<  Base address of TMR0 */
+#define ADI_TMR1_BASE                  0x40000400    /*!<  Base address of TMR1 */
+#define ADI_TMR2_BASE                  0x40000800    /*!<  Base address of TMR2 */
+#define ADI_TMR_RGB_BASE               0x40000c00    /*!<  Base address of TMR_RGB */
+#define ADI_RTC0_BASE                  0x40001000    /*!<  Base address of RTC0 */
+#define ADI_RTC1_BASE                  0x40001400    /*!<  Base address of RTC1 */
+#define ADI_SYS_BASE                   0x40002000    /*!<  Base address of SYS */
+#define ADI_WDT0_BASE                  0x40002c00    /*!<  Base address of WDT0 */
+#define ADI_I2C0_BASE                  0x40003000    /*!<  Base address of I2C0 */
+#define ADI_SPI0_BASE                  0x40004000    /*!<  Base address of SPI0 */
+#define ADI_SPI1_BASE                  0x40004400    /*!<  Base address of SPI1 */
+#define ADI_SPI2_BASE                  0x40024000    /*!<  Base address of SPI2 */
+#define ADI_UART0_BASE                 0x40005000    /*!<  Base address of UART0 */
+#define ADI_UART1_BASE                 0x40005400    /*!<  Base address of UART1 */
+#define ADI_BEEP0_BASE                 0x40005c00    /*!<  Base address of BEEP0 */
+#define ADI_ADC0_BASE                  0x40007000    /*!<  Base address of ADC0 */
+#define ADI_DMA0_BASE                  0x40010000    /*!<  Base address of DMA0 */
+#define ADI_FLCC0_BASE                 0x40018000    /*!<  Base address of FLCC0 */
+#define ADI_FLCC0_CACHE_BASE           0x40018058    /*!<  Base address of FLCC0_CACHE */
+#define ADI_GPIO0_BASE                 0x40020000    /*!<  Base address of GPIO0 */
+#define ADI_GPIO1_BASE                 0x40020040    /*!<  Base address of GPIO1 */
+#define ADI_GPIO2_BASE                 0x40020080    /*!<  Base address of GPIO2 */
+#define ADI_GPIO3_BASE                 0x400200c0    /*!<  Base address of GPIO3 */
+#define ADI_SPORT0_BASE                0x40038000    /*!<  Base address of SPORT0 */
+#define ADI_CRC0_BASE                  0x40040000    /*!<  Base address of CRC0 */
+#define ADI_RNG0_BASE                  0x40040400    /*!<  Base address of RNG0 */
+#define ADI_CRYPT0_BASE                0x40044000    /*!<  Base address of CRYPT0 */
+#define ADI_PMG0_BASE                  0x4004c000    /*!<  Base address of PMG0 */
+#define ADI_XINT0_BASE                 0x4004c080    /*!<  Base address of XINT0 */
+#define ADI_CLKG0_OSC_BASE             0x4004c100    /*!<  Base address of CLKG0_OSC */
+#define ADI_PMG0_TST_BASE              0x4004c200    /*!<  Base address of PMG0_TST */
+#define ADI_CLKG0_CLK_BASE             0x4004c300    /*!<  Base address of CLKG0_CLK */
+#define ADI_BUSM0_BASE                 0x4004c800    /*!<  Base address of BUSM0 */
+#define ADI_PTI0_BASE                  0x4004cd00    /*!<  Base address of PTI0 */
+#define ADI_NVIC0_BASE                 0xe000e000    /*!<  Base address of NVIC0 */
+
+/*!    @} */
+
+/* ******************************************************************************
+ *    Peripheral Pointer Declarations
+ * *****************************************************************************/
+/*!    @Defgroup Pptrdec Peripheral Pointer Declarations
+ *     \Addtogroup Pptrdec
+ *     @{ */
+#define pADI_TMR0                      ((ADI_TMR_TypeDef      *) ADI_TMR0_BASE       ) /*!<  Pointer to General Purpose Timer (TMR0) */
+#define pADI_TMR1                      ((ADI_TMR_TypeDef      *) ADI_TMR1_BASE       ) /*!<  Pointer to General Purpose Timer (TMR1) */
+#define pADI_TMR2                      ((ADI_TMR_TypeDef      *) ADI_TMR2_BASE       ) /*!<  Pointer to General Purpose Timer (TMR2) */
+#define pADI_TMR_RGB                   ((ADI_TMR_RGB_TypeDef  *) ADI_TMR_RGB_BASE    ) /*!<  Pointer to Timer_RGB with 3 PWM outputs (TMR_RGB) */
+#define pADI_RTC0                      ((ADI_RTC_TypeDef      *) ADI_RTC0_BASE       ) /*!<  Pointer to Real-Time Clock (RTC0) */
+#define pADI_RTC1                      ((ADI_RTC_TypeDef      *) ADI_RTC1_BASE       ) /*!<  Pointer to Real-Time Clock (RTC1) */
+#define pADI_SYS                       ((ADI_SYS_TypeDef      *) ADI_SYS_BASE        ) /*!<  Pointer to System Identification and Debug Enable (SYS) */
+#define pADI_WDT0                      ((ADI_WDT_TypeDef      *) ADI_WDT0_BASE       ) /*!<  Pointer to Watchdog Timer (WDT0) */
+#define pADI_I2C0                      ((ADI_I2C_TypeDef      *) ADI_I2C0_BASE       ) /*!<  Pointer to I2C Master/Slave (I2C0) */
+#define pADI_SPI0                      ((ADI_SPI_TypeDef      *) ADI_SPI0_BASE       ) /*!<  Pointer to Serial Peripheral Interface (SPI0) */
+#define pADI_SPI1                      ((ADI_SPI_TypeDef      *) ADI_SPI1_BASE       ) /*!<  Pointer to Serial Peripheral Interface (SPI1) */
+#define pADI_SPI2                      ((ADI_SPI_TypeDef      *) ADI_SPI2_BASE       ) /*!<  Pointer to Serial Peripheral Interface (SPI2) */
+#define pADI_UART0                     ((ADI_UART_TypeDef     *) ADI_UART0_BASE      ) /*!<  Pointer to  (UART0) */
+#define pADI_UART1                     ((ADI_UART_TypeDef     *) ADI_UART1_BASE      ) /*!<  Pointer to  (UART1) */
+#define pADI_BEEP0                     ((ADI_BEEP_TypeDef     *) ADI_BEEP0_BASE      ) /*!<  Pointer to Beeper Driver (BEEP0) */
+#define pADI_ADC0                      ((ADI_ADC_TypeDef      *) ADI_ADC0_BASE       ) /*!<  Pointer to  (ADC0) */
+#define pADI_DMA0                      ((ADI_DMA_TypeDef      *) ADI_DMA0_BASE       ) /*!<  Pointer to DMA (DMA0) */
+#define pADI_FLCC0                     ((ADI_FLCC_TypeDef     *) ADI_FLCC0_BASE      ) /*!<  Pointer to Flash Controller (FLCC0) */
+#define pADI_FLCC0_CACHE               ((ADI_FLCC_CACHE_TypeDef *) ADI_FLCC0_CACHE_BASE) /*!<  Pointer to Cache Controller (FLCC0_CACHE) */
+#define pADI_GPIO0                     ((ADI_GPIO_TypeDef     *) ADI_GPIO0_BASE      ) /*!<  Pointer to  (GPIO0) */
+#define pADI_GPIO1                     ((ADI_GPIO_TypeDef     *) ADI_GPIO1_BASE      ) /*!<  Pointer to  (GPIO1) */
+#define pADI_GPIO2                     ((ADI_GPIO_TypeDef     *) ADI_GPIO2_BASE      ) /*!<  Pointer to  (GPIO2) */
+#define pADI_GPIO3                     ((ADI_GPIO_TypeDef     *) ADI_GPIO3_BASE      ) /*!<  Pointer to  (GPIO3) */
+#define pADI_SPORT0                    ((ADI_SPORT_TypeDef    *) ADI_SPORT0_BASE     ) /*!<  Pointer to Serial Port (SPORT0) */
+#define pADI_CRC0                      ((ADI_CRC_TypeDef      *) ADI_CRC0_BASE       ) /*!<  Pointer to CRC Accelerator (CRC0) */
+#define pADI_RNG0                      ((ADI_RNG_TypeDef      *) ADI_RNG0_BASE       ) /*!<  Pointer to Random Number Generator (RNG0) */
+#define pADI_CRYPT0                    ((ADI_CRYPT_TypeDef    *) ADI_CRYPT0_BASE     ) /*!<  Pointer to Register Map for the Crypto Block (CRYPT0) */
+#define pADI_PMG0                      ((ADI_PMG_TypeDef      *) ADI_PMG0_BASE       ) /*!<  Pointer to Power Management  (PMG0) */
+#define pADI_XINT0                     ((ADI_XINT_TypeDef     *) ADI_XINT0_BASE      ) /*!<  Pointer to External interrupt configuration (XINT0) */
+#define pADI_CLKG0_OSC                 ((ADI_CLKG_OSC_TypeDef *) ADI_CLKG0_OSC_BASE  ) /*!<  Pointer to Clocking  (CLKG0_OSC) */
+#define pADI_PMG0_TST                  ((ADI_PMG_TST_TypeDef  *) ADI_PMG0_TST_BASE   ) /*!<  Pointer to Power Management  (PMG0_TST) */
+#define pADI_CLKG0_CLK                 ((ADI_CLKG_CLK_TypeDef *) ADI_CLKG0_CLK_BASE  ) /*!<  Pointer to Clocking  (CLKG0_CLK) */
+#define pADI_BUSM0                     ((ADI_BUSM_TypeDef     *) ADI_BUSM0_BASE      ) /*!<  Pointer to Bus matrix (BUSM0) */
+#define pADI_PTI0                      ((ADI_PTI_TypeDef      *) ADI_PTI0_BASE       ) /*!<  Pointer to Parallel Test Interface (PTI0) */
+#define pADI_NVIC0                     ((ADI_NVIC_TypeDef     *) ADI_NVIC0_BASE      ) /*!<  Pointer to Cortex-M3 Interrupt Controller (NVIC0) */
+
+/*!    @} */
+
+
+/*  =========================================================================
+ *! \enum   IRQn_Type
+ *! \brief  Interrupt Number Assignments
+ *  ========================================================================= */
+#ifndef __ADI_NO_DECL_ENUM_IRQn_Type__
+
+typedef enum
+{
+  RESET_IRQn                     =   -15,    /*!< Cortex-M4 Reset */
+  NonMaskableInt_IRQn            =   -14,    /*!< Cortex-M4 Non-maskable Interrupt */
+  HardFault_IRQn                 =   -13,    /*!< Cortex-M4 Hardware Fault */
+  MemoryManagement_IRQn          =   -12,    /*!< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                  =   -11,    /*!< Cortex-M4 Bus Fault */
+  UsageFault_IRQn                =   -10,    /*!< Cortex-M4 Usage Fault */
+  SVCall_IRQn                    =    -5,    /*!< Cortex-M4 SVCall Interrupt */
+  DebugMonitor_IRQn              =    -4,    /*!< Cortex-M4 Debug Monitor */
+  PendSV_IRQn                    =    -2,    /*!< Cortex-M4 PendSV Interrupt */
+  SysTick_IRQn                   =    -1,    /*!< Cortex-M4 SysTick Interrupt */
+  RTC1_EVT_IRQn                  =     0,    /*!< Event */
+  XINT_EVT0_IRQn                 =     1,    /*!< External Wakeup Interrupt n */
+  XINT_EVT1_IRQn                 =     2,    /*!< External Wakeup Interrupt n */
+  XINT_EVT2_IRQn                 =     3,    /*!< External Wakeup Interrupt n */
+  XINT_EVT3_IRQn                 =     4,    /*!< External Wakeup Interrupt n */
+  WDT_EXP_IRQn                   =     5,    /*!< Expiration */
+  PMG0_VREG_OVR_IRQn             =     6,    /*!< Voltage Regulator (VREG) Overvoltage */
+  PMG0_BATT_RANGE_IRQn           =     7,    /*!< Battery Voltage (VBAT) Out of Range */
+  RTC0_EVT_IRQn                  =     8,    /*!< Event */
+  SYS_GPIO_INTA_IRQn             =     9,    /*!< GPIO Interrupt A */
+  SYS_GPIO_INTB_IRQn             =    10,    /*!< GPIO Interrupt B */
+  TMR0_EVT_IRQn                  =    11,    /*!< Event */
+  TMR1_EVT_IRQn                  =    12,    /*!< Event */
+  FLCC_EVT_IRQn                  =    13,    /*!< Event */
+  UART0_EVT_IRQn                 =    14,    /*!< UART0 Event */
+  SPI0_EVT_IRQn                  =    15,    /*!< Event */
+  SPI2_EVT_IRQn                  =    16,    /*!< Event */
+  I2C_SLV_EVT_IRQn               =    17,    /*!< Slave Event */
+  I2C_MST_EVT_IRQn               =    18,    /*!< Master Event */
+  DMA_CHAN_ERR_IRQn              =    19,    /*!< Channel Error */
+  DMA0_CH0_DONE_IRQn             =    20,    /*!< Channel 0 Done */
+  DMA0_CH1_DONE_IRQn             =    21,    /*!< Channel 1 Done */
+  DMA0_CH2_DONE_IRQn             =    22,    /*!< Channel 2 Done */
+  DMA0_CH3_DONE_IRQn             =    23,    /*!< Channel 3 Done */
+  DMA0_CH4_DONE_IRQn             =    24,    /*!< Channel 4 Done */
+  DMA0_CH5_DONE_IRQn             =    25,    /*!< Channel 5 Done */
+  DMA0_CH6_DONE_IRQn             =    26,    /*!< Channel 6 Done */
+  DMA0_CH7_DONE_IRQn             =    27,    /*!< Channel 7 Done */
+  DMA0_CH8_DONE_IRQn             =    28,    /*!< Channel 8 Done */
+  DMA0_CH9_DONE_IRQn             =    29,    /*!< Channel 9 Done */
+  DMA0_CH10_DONE_IRQn            =    30,    /*!< Channel 10 Done */
+  DMA0_CH11_DONE_IRQn            =    31,    /*!< Channel 11 Done */
+  DMA0_CH12_DONE_IRQn            =    32,    /*!< Channel 12 Done */
+  DMA0_CH13_DONE_IRQn            =    33,    /*!< Channel 13 Done */
+  DMA0_CH14_DONE_IRQn            =    34,    /*!< Channel 14 Done */
+  DMA0_CH15_DONE_IRQn            =    35,    /*!< Channel 15 Done */
+  SPORT_A_EVT_IRQn               =    36,    /*!< Channel A Event */
+  SPORT_B_EVT_IRQn               =    37,    /*!< Channel B Event */
+  CRYPT_EVT_IRQn                 =    38,    /*!< Event */
+  DMA0_CH24_DONE_IRQn            =    39,    /*!< Channel 24 Done */
+  TMR2_EVT_IRQn                  =    40,    /*!< Event */
+  CLKG_XTAL_OSC_EVT_IRQn         =    41,    /*!< Crystal Oscillator Event */
+  SPI1_EVT_IRQn                  =    42,    /*!< Event */
+  CLKG_PLL_EVT_IRQn              =    43,    /*!< PLL Event */
+  RNG0_EVT_IRQn                  =    44,    /*!< Event */
+  BEEP_EVT_IRQn                  =    45,    /*!< Event */
+  ADC0_EVT_IRQn                  =    46,    /*!< Event */
+  DMA0_CH16_DONE_IRQn            =    56,    /*!< Channel 16 Done */
+  DMA0_CH17_DONE_IRQn            =    57,    /*!< Channel 17 Done */
+  DMA0_CH18_DONE_IRQn            =    58,    /*!< Channel 18 Done */
+  DMA0_CH19_DONE_IRQn            =    59,    /*!< Channel 19 Done */
+  DMA0_CH20_DONE_IRQn            =    60,    /*!< Channel 20 Done */
+  DMA0_CH21_DONE_IRQn            =    61,    /*!< Channel 21 Done */
+  DMA0_CH22_DONE_IRQn            =    62,    /*!< Channel 22 Done */
+  DMA0_CH23_DONE_IRQn            =    63,    /*!< Channel 23 Done */
+  UART1_EVT_IRQn                 =    66,    /*!< Event */
+  DMA0_CH25_DONE_IRQn            =    67,    /*!< Channel 25 Done */
+  DMA0_CH26_DONE_IRQn            =    68,    /*!< Channel 26 Done */
+  TMR_RGB_EVT_IRQn               =    69,    /*!< Event */
+  CLKG_ROOTCLK_ERR_IRQn          =    71,    /*!< Root Clock Error */
+} IRQn_Type;  /* typedef name for fixed interrupt numbers */
+#endif /* !__ADI_NO_DECL_ENUM_IRQn_Type__ */
+
+
+
+#if defined (_MISRA_RULES)
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_typedefs.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_typedefs.h
new file mode 100755
index 00000000000..7872e766ded
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_typedefs.h
@@ -0,0 +1,11241 @@
+/* ================================================================================
+
+     Project      :   ADuCM4050
+     File         :   ADuCM4050_typedefs.h
+     Description  :   C Register Structures
+
+     Date         :   Feb 7, 2017
+
+     Copyright (c) 2014-2017 Analog Devices, Inc.  All Rights Reserved.
+     This software is proprietary and confidential to Analog Devices, Inc. and
+     its licensors.
+
+     This file was auto-generated. Do not make local changes to this file.
+
+   ================================================================================ */
+
+#ifndef _ADUCM4050_TYPEDEFS_H
+#define _ADUCM4050_TYPEDEFS_H
+
+/* pickup integer types */
+#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__))
+#include <stdint.h>
+#endif /* _LANGUAGE_C */
+
+#if defined (_MISRA_RULES)
+/*
+  anonymous unions violate ISO 9899:1990 and therefore MISRA Rule 1.1.
+  Use of unions violates MISRA Rule 18.4.
+  Anonymous unions are required for this implementation.
+  Re-use of identifiers violates MISRA Rule 5.7.
+  Field names are repeated for the ADuCM4050 register map.
+*/
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_1_1:"Allow anonymous unions")
+#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit")
+#pragma diag(suppress:misra_rule_5_3:"Header will re-use typedef identifiers")
+#pragma diag(suppress:misra_rule_5_6:"Header will re-use identifiers in the same scope")
+#pragma diag(suppress:misra_rule_5_7:"Header will re-use identifiers")
+#pragma diag(suppress:misra_rule_18_4:"Allow the use of a union")
+#endif /* _MISRA_RULES */
+
+/** @defgroup LOAD 16-bit Load Value (LOAD) Register
+ *  16-bit Load Value (LOAD) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_LOAD_Struct
+ *! \brief  16-bit Load Value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_LOAD_t__
+typedef struct _ADI_TMR_LOAD_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Load Value */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_LOAD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_LOAD_t__ */
+
+/*@}*/
+
+/** @defgroup CURCNT 16-bit Timer Value (CURCNT) Register
+ *  16-bit Timer Value (CURCNT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_CURCNT_Struct
+ *! \brief  16-bit Timer Value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CURCNT_t__
+typedef struct _ADI_TMR_CURCNT_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Current Count */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_CURCNT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CURCNT_t__ */
+
+/*@}*/
+
+/** @defgroup CTL Control (CTL) Register
+ *  Control (CTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_CTL_Struct
+ *! \brief  Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CTL_t__
+typedef struct _ADI_TMR_CTL_t {
+  union {
+    struct {
+      unsigned int PRE        :  2;  /**< Prescaler */
+      unsigned int UP         :  1;  /**< Count up */
+      unsigned int MODE       :  1;  /**< Timer Mode */
+      unsigned int EN         :  1;  /**< Timer Enable */
+      unsigned int CLK        :  2;  /**< Clock Select */
+      unsigned int RLD        :  1;  /**< Reload Control */
+      unsigned int reserved8  :  5;
+      unsigned int EVTEN      :  1;  /**< Event Select */
+      unsigned int RSTEN      :  1;  /**< Counter and Prescale Reset Enable */
+      unsigned int SYNCBYP    :  1;  /**< Synchronization Bypass */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup CLRINT Clear Interrupt (CLRINT) Register
+ *  Clear Interrupt (CLRINT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_CLRINT_Struct
+ *! \brief  Clear Interrupt Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CLRINT_t__
+typedef struct _ADI_TMR_CLRINT_t {
+  union {
+    struct {
+      unsigned int TIMEOUT    :  1;  /**< Clear Timeout Interrupt */
+      unsigned int EVTCAPT    :  1;  /**< Clear Captured Event Interrupt */
+      unsigned int reserved2  : 14;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_CLRINT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CLRINT_t__ */
+
+/*@}*/
+
+/** @defgroup CAPTURE Capture (CAPTURE) Register
+ *  Capture (CAPTURE) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_CAPTURE_Struct
+ *! \brief  Capture Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CAPTURE_t__
+typedef struct _ADI_TMR_CAPTURE_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< 16-bit Captured Value */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_CAPTURE_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CAPTURE_t__ */
+
+/*@}*/
+
+/** @defgroup ALOAD 16-bit Load Value, Asynchronous (ALOAD) Register
+ *  16-bit Load Value, Asynchronous (ALOAD) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_ALOAD_Struct
+ *! \brief  16-bit Load Value, Asynchronous Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_ALOAD_t__
+typedef struct _ADI_TMR_ALOAD_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Load Value, Asynchronous */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_ALOAD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_ALOAD_t__ */
+
+/*@}*/
+
+/** @defgroup ACURCNT 16-bit Timer Value, Asynchronous (ACURCNT) Register
+ *  16-bit Timer Value, Asynchronous (ACURCNT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_ACURCNT_Struct
+ *! \brief  16-bit Timer Value, Asynchronous Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_ACURCNT_t__
+typedef struct _ADI_TMR_ACURCNT_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Counter Value */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_ACURCNT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_ACURCNT_t__ */
+
+/*@}*/
+
+/** @defgroup STAT Status (STAT) Register
+ *  Status (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_STAT_Struct
+ *! \brief  Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_STAT_t__
+typedef struct _ADI_TMR_STAT_t {
+  union {
+    struct {
+      unsigned int TIMEOUT    :  1;  /**< Timeout Event Occurred */
+      unsigned int CAPTURE    :  1;  /**< Capture Event Pending */
+      unsigned int reserved2  :  4;
+      unsigned int BUSY       :  1;  /**< Timer Busy */
+      unsigned int PDOK       :  1;  /**< Clear Interrupt Register Synchronization */
+      unsigned int CNTRST     :  1;  /**< Counter Reset Occurring */
+      unsigned int reserved9  :  7;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup PWMCTL PWM Control Register (PWMCTL) Register
+ *  PWM Control Register (PWMCTL) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_TMR_PWMCTL_MATCH
+ *! \brief  PWM Match Enabled (MATCH) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  TMR_PWMCTL_PWM_TOGGLE = 0,  /**< PWM in toggle mode */
+  TMR_PWMCTL_PWM_MATCH  = 1   /**< PWM in match mode  */
+} ADI_TMR_PWMCTL_MATCH;
+
+
+/*  =========================================================================
+ *! \enum   ADI_TMR_PWMCTL_IDLESTATE
+ *! \brief  PWM Idle State (IDLESTATE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  TMR_PWMCTL_IDLE_LOW  = 0,  /**< PWM idles low  */
+  TMR_PWMCTL_IDLE_HIGH = 1   /**< PWM idles high */
+} ADI_TMR_PWMCTL_IDLESTATE;
+
+
+/* ==========================================================================
+ *! \struct ADI_TMR_PWMCTL_Struct
+ *! \brief  PWM Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_PWMCTL_t__
+typedef struct _ADI_TMR_PWMCTL_t {
+  union {
+    struct {
+      unsigned int MATCH      :  1;  /**< PWM Match Enabled */
+      unsigned int IDLESTATE  :  1;  /**< PWM Idle State */
+      unsigned int reserved2  : 14;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_PWMCTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_PWMCTL_t__ */
+
+/*@}*/
+
+/** @defgroup PWMMATCH PWM Match Value (PWMMATCH) Register
+ *  PWM Match Value (PWMMATCH) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_PWMMATCH_Struct
+ *! \brief  PWM Match Value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_PWMMATCH_t__
+typedef struct _ADI_TMR_PWMMATCH_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< PWM Match Value */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_PWMMATCH_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_PWMMATCH_t__ */
+
+/*@}*/
+
+/** @defgroup EVENTSELECT Timer Event Selection Register (EVENTSELECT) Register
+ *  Timer Event Selection Register (EVENTSELECT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_EVENTSELECT_Struct
+ *! \brief  Timer Event Selection Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_EVENTSELECT_t__
+typedef struct _ADI_TMR_EVENTSELECT_t {
+  union {
+    struct {
+      unsigned int EVTRANGE   :  6;  /**< Event Select Range */
+      unsigned int reserved6  : 10;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_EVENTSELECT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_EVENTSELECT_t__ */
+
+/*@}*/
+
+/** @defgroup LOAD 16-bit load value (LOAD) Register
+ *  16-bit load value (LOAD) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_RGB_LOAD_Struct
+ *! \brief  16-bit load value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_LOAD_t__
+typedef struct _ADI_TMR_RGB_LOAD_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Load value */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_RGB_LOAD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_LOAD_t__ */
+
+/*@}*/
+
+/** @defgroup CURCNT 16-bit timer value (CURCNT) Register
+ *  16-bit timer value (CURCNT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_RGB_CURCNT_Struct
+ *! \brief  16-bit timer value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CURCNT_t__
+typedef struct _ADI_TMR_RGB_CURCNT_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Current count */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_RGB_CURCNT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CURCNT_t__ */
+
+/*@}*/
+
+/** @defgroup CTL Control (CTL) Register
+ *  Control (CTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_RGB_CTL_Struct
+ *! \brief  Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CTL_t__
+typedef struct _ADI_TMR_RGB_CTL_t {
+  union {
+    struct {
+      unsigned int PRE        :  2;  /**< Prescaler */
+      unsigned int UP         :  1;  /**< Count up */
+      unsigned int MODE       :  1;  /**< Timer mode */
+      unsigned int EN         :  1;  /**< Timer enable */
+      unsigned int CLK        :  2;  /**< Clock select */
+      unsigned int RLD        :  1;  /**< Reload control */
+      unsigned int reserved8  :  5;
+      unsigned int EVTEN      :  1;  /**< Event select */
+      unsigned int RSTEN      :  1;  /**< Counter and prescale reset enable */
+      unsigned int SYNCBYP    :  1;  /**< Synchronization bypass */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_RGB_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup CLRINT Clear interrupt (CLRINT) Register
+ *  Clear interrupt (CLRINT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_RGB_CLRINT_Struct
+ *! \brief  Clear interrupt Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CLRINT_t__
+typedef struct _ADI_TMR_RGB_CLRINT_t {
+  union {
+    struct {
+      unsigned int TIMEOUT    :  1;  /**< Clear timeout interrupt */
+      unsigned int EVTCAPT    :  1;  /**< Clear captured event interrupt */
+      unsigned int reserved2  : 14;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_RGB_CLRINT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CLRINT_t__ */
+
+/*@}*/
+
+/** @defgroup CAPTURE Capture (CAPTURE) Register
+ *  Capture (CAPTURE) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_RGB_CAPTURE_Struct
+ *! \brief  Capture Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CAPTURE_t__
+typedef struct _ADI_TMR_RGB_CAPTURE_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< 16-bit captured value */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_RGB_CAPTURE_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CAPTURE_t__ */
+
+/*@}*/
+
+/** @defgroup ALOAD 16-bit load value, asynchronous (ALOAD) Register
+ *  16-bit load value, asynchronous (ALOAD) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_RGB_ALOAD_Struct
+ *! \brief  16-bit load value, asynchronous Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_ALOAD_t__
+typedef struct _ADI_TMR_RGB_ALOAD_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Load value, asynchronous */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_RGB_ALOAD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_ALOAD_t__ */
+
+/*@}*/
+
+/** @defgroup ACURCNT 16-bit timer value, asynchronous (ACURCNT) Register
+ *  16-bit timer value, asynchronous (ACURCNT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_RGB_ACURCNT_Struct
+ *! \brief  16-bit timer value, asynchronous Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_ACURCNT_t__
+typedef struct _ADI_TMR_RGB_ACURCNT_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Counter value */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_RGB_ACURCNT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_ACURCNT_t__ */
+
+/*@}*/
+
+/** @defgroup STAT Status (STAT) Register
+ *  Status (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_RGB_STAT_Struct
+ *! \brief  Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_STAT_t__
+typedef struct _ADI_TMR_RGB_STAT_t {
+  union {
+    struct {
+      unsigned int TIMEOUT    :  1;  /**< Timeout event occurred */
+      unsigned int CAPTURE    :  1;  /**< Capture event pending */
+      unsigned int reserved2  :  4;
+      unsigned int BUSY       :  1;  /**< Timer Busy */
+      unsigned int PDOK       :  1;  /**< Clear Interrupt Register synchronization */
+      unsigned int CNTRST     :  1;  /**< Counter reset occurring */
+      unsigned int reserved9  :  7;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_RGB_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup PWM0CTL PWM0 Control Register (PWM0CTL) Register
+ *  PWM0 Control Register (PWM0CTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_RGB_PWM0CTL_Struct
+ *! \brief  PWM0 Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM0CTL_t__
+typedef struct _ADI_TMR_RGB_PWM0CTL_t {
+  union {
+    struct {
+      unsigned int MATCH      :  1;  /**< PWM Match enabled */
+      unsigned int IDLESTATE  :  1;  /**< PWM Idle State */
+      unsigned int reserved2  : 14;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_RGB_PWM0CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM0CTL_t__ */
+
+/*@}*/
+
+/** @defgroup PWM0MATCH PWM0 Match Value (PWM0MATCH) Register
+ *  PWM0 Match Value (PWM0MATCH) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_RGB_PWM0MATCH_Struct
+ *! \brief  PWM0 Match Value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM0MATCH_t__
+typedef struct _ADI_TMR_RGB_PWM0MATCH_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< PWM Match Value */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_RGB_PWM0MATCH_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM0MATCH_t__ */
+
+/*@}*/
+
+/** @defgroup EVENTSELECT Timer Event selection Register (EVENTSELECT) Register
+ *  Timer Event selection Register (EVENTSELECT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_RGB_EVENTSELECT_Struct
+ *! \brief  Timer Event selection Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_EVENTSELECT_t__
+typedef struct _ADI_TMR_RGB_EVENTSELECT_t {
+  union {
+    struct {
+      unsigned int EVTRANGE   :  6;  /**< Event select range */
+      unsigned int reserved6  : 10;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_RGB_EVENTSELECT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_EVENTSELECT_t__ */
+
+/*@}*/
+
+/** @defgroup PWM1CTL PWM1 Control Register (PWM1CTL) Register
+ *  PWM1 Control Register (PWM1CTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_RGB_PWM1CTL_Struct
+ *! \brief  PWM1 Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM1CTL_t__
+typedef struct _ADI_TMR_RGB_PWM1CTL_t {
+  union {
+    struct {
+      unsigned int MATCH      :  1;  /**< PWM Match enabled */
+      unsigned int IDLESTATE  :  1;  /**< PWM Idle State */
+      unsigned int reserved2  : 14;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_RGB_PWM1CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM1CTL_t__ */
+
+/*@}*/
+
+/** @defgroup PWM1MATCH PWM1 Match Value (PWM1MATCH) Register
+ *  PWM1 Match Value (PWM1MATCH) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_RGB_PWM1MATCH_Struct
+ *! \brief  PWM1 Match Value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM1MATCH_t__
+typedef struct _ADI_TMR_RGB_PWM1MATCH_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< PWM Match Value */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_RGB_PWM1MATCH_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM1MATCH_t__ */
+
+/*@}*/
+
+/** @defgroup PWM2CTL PWM2 Control Register (PWM2CTL) Register
+ *  PWM2 Control Register (PWM2CTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_RGB_PWM2CTL_Struct
+ *! \brief  PWM2 Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM2CTL_t__
+typedef struct _ADI_TMR_RGB_PWM2CTL_t {
+  union {
+    struct {
+      unsigned int MATCH      :  1;  /**< PWM Match enabled */
+      unsigned int IDLESTATE  :  1;  /**< PWM Idle State */
+      unsigned int reserved2  : 14;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_RGB_PWM2CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM2CTL_t__ */
+
+/*@}*/
+
+/** @defgroup PWM2MATCH PWM2 Match Value (PWM2MATCH) Register
+ *  PWM2 Match Value (PWM2MATCH) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TMR_RGB_PWM2MATCH_Struct
+ *! \brief  PWM2 Match Value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM2MATCH_t__
+typedef struct _ADI_TMR_RGB_PWM2MATCH_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< PWM Match Value */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_TMR_RGB_PWM2MATCH_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM2MATCH_t__ */
+
+/*@}*/
+
+/** @defgroup CR0 RTC Control 0 (CR0) Register
+ *  RTC Control 0 (CR0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_CR0_Struct
+ *! \brief  RTC Control 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR0_t__
+typedef struct _ADI_RTC_CR0_t {
+  union {
+    struct {
+      unsigned int CNTEN      :  1;  /**< Global Enable for the RTC */
+      unsigned int ALMEN      :  1;  /**< Enable the RTC Alarm (Absolute) Operation */
+      unsigned int ALMINTEN   :  1;  /**< Enable ALMINT Sourced Alarm Interrupts to the CPU */
+      unsigned int TRMEN      :  1;  /**< Enable RTC Digital Trimming */
+      unsigned int MOD60ALMEN :  1;  /**< Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary */
+      unsigned int MOD60ALM   :  6;  /**< Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60 Boundary */
+      unsigned int MOD60ALMINTEN :  1;  /**< Enable Periodic Modulo-60 RTC Alarm  Sourced Interrupts to the CPU */
+      unsigned int ISOINTEN      :  1;  /**< Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power Domain is Activated and Subsequently De-activated */
+      unsigned int WPNDERRINTEN  :  1;  /**< Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Register-write Pending Error Occurs */
+      unsigned int WSYNCINTEN    :  1;  /**< Enable Write Synchronization Sourced Interrupts to the CPU */
+      unsigned int WPNDINTEN     :  1;  /**< Enable Write Pending Sourced Interrupts to the CPU */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_CR0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR0_t__ */
+
+/*@}*/
+
+/** @defgroup SR0 RTC Status 0 (SR0) Register
+ *  RTC Status 0 (SR0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SR0_Struct
+ *! \brief  RTC Status 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR0_t__
+typedef struct _ADI_RTC_SR0_t {
+  union {
+    struct {
+      unsigned int reserved0  :  1;
+      unsigned int ALMINT     :  1;  /**< Alarm Interrupt Source */
+      unsigned int MOD60ALMINT :  1;  /**< Modulo-60 RTC Alarm Interrupt Source */
+      unsigned int ISOINT      :  1;  /**< RTC Power-Domain Isolation Interrupt Source */
+      unsigned int WPNDERRINT  :  1;  /**< Write Pending Error Interrupt Source */
+      unsigned int WSYNCINT    :  1;  /**< Write Synchronisation Interrupt */
+      unsigned int WPNDINT     :  1;  /**< Write Pending Interrupt */
+      unsigned int WSYNCCR0    :  1;  /**< Synchronisation Status of Posted Writes to CR0 */
+      unsigned int WSYNCSR0    :  1;  /**< Synchronisation Status of Posted Writes to SR0 */
+      unsigned int WSYNCCNT0   :  1;  /**< Synchronisation Status of Posted Writes to CNT0 */
+      unsigned int WSYNCCNT1   :  1;  /**< Synchronisation Status of Posted Writes to CNT1 */
+      unsigned int WSYNCALM0   :  1;  /**< Synchronisation Status of Posted Writes to ALM0 */
+      unsigned int WSYNCALM1   :  1;  /**< Synchronisation Status of Posted Writes to ALM1 */
+      unsigned int WSYNCTRM    :  1;  /**< Synchronisation Status of Posted Writes to TRM */
+      unsigned int ISOENB      :  1;  /**< Visibility of 32kHz Sourced Registers */
+      unsigned int reserved15  :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SR0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR0_t__ */
+
+/*@}*/
+
+/** @defgroup SR1 RTC Status 1 (SR1) Register
+ *  RTC Status 1 (SR1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SR1_Struct
+ *! \brief  RTC Status 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR1_t__
+typedef struct _ADI_RTC_SR1_t {
+  union {
+    struct {
+      unsigned int reserved0  :  7;
+      unsigned int WPNDCR0    :  1;  /**< Pending Status of Posted Writes to CR0 */
+      unsigned int WPNDSR0    :  1;  /**< Pending Status of Posted Clearances of Interrupt Sources in SR0 */
+      unsigned int WPNDCNT0   :  1;  /**< Pending Status of Posted Writes to CNT0 */
+      unsigned int WPNDCNT1   :  1;  /**< Pending Status of Posted Writes to CNT1 */
+      unsigned int WPNDALM0   :  1;  /**< Pending Status of Posted Writes to ALM0 */
+      unsigned int WPNDALM1   :  1;  /**< Pending Status of Posted Writes to ALM1 */
+      unsigned int WPNDTRM    :  1;  /**< Pending Status of Posted Writes to TRM */
+      unsigned int reserved14 :  2;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SR1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR1_t__ */
+
+/*@}*/
+
+/** @defgroup CNT0 RTC Count 0 (CNT0) Register
+ *  RTC Count 0 (CNT0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_CNT0_Struct
+ *! \brief  RTC Count 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CNT0_t__
+typedef struct _ADI_RTC_CNT0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_CNT0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CNT0_t__ */
+
+/*@}*/
+
+/** @defgroup CNT1 RTC Count 1 (CNT1) Register
+ *  RTC Count 1 (CNT1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_CNT1_Struct
+ *! \brief  RTC Count 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CNT1_t__
+typedef struct _ADI_RTC_CNT1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_CNT1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CNT1_t__ */
+
+/*@}*/
+
+/** @defgroup ALM0 RTC Alarm 0 (ALM0) Register
+ *  RTC Alarm 0 (ALM0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_ALM0_Struct
+ *! \brief  RTC Alarm 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_ALM0_t__
+typedef struct _ADI_RTC_ALM0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_ALM0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_ALM0_t__ */
+
+/*@}*/
+
+/** @defgroup ALM1 RTC Alarm 1 (ALM1) Register
+ *  RTC Alarm 1 (ALM1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_ALM1_Struct
+ *! \brief  RTC Alarm 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_ALM1_t__
+typedef struct _ADI_RTC_ALM1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_ALM1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_ALM1_t__ */
+
+/*@}*/
+
+/** @defgroup TRM RTC Trim (TRM) Register
+ *  RTC Trim (TRM) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_TRM_Struct
+ *! \brief  RTC Trim Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_TRM_t__
+typedef struct _ADI_RTC_TRM_t {
+  union {
+    struct {
+      unsigned int VALUE      :  3;  /**< Trim Value in Prescaled RTC Time Units to Be Added or Subtracted from the RTC Count at the End of a Periodic Interval Selected by TRM:TRMIVL */
+      unsigned int ADD        :  1;  /**< Trim Polarity */
+      unsigned int IVL        :  2;  /**< Trim Interval in Prescaled RTC Time Units */
+      unsigned int IVL2EXPMIN :  4;  /**< Minimum Power-of-two Interval of Prescaled RTC Time Units Which TRM:TRMIVL TRMIVL Can Select */
+      unsigned int reserved10 :  6;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_TRM_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_TRM_t__ */
+
+/*@}*/
+
+/** @defgroup GWY RTC Gateway (GWY) Register
+ *  RTC Gateway (GWY) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_GWY_Struct
+ *! \brief  RTC Gateway Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_GWY_t__
+typedef struct _ADI_RTC_GWY_t {
+  union {
+    struct {
+      unsigned int SWKEY      : 16;  /**< Software-keyed Command Issued by the CPU */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_GWY_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_GWY_t__ */
+
+/*@}*/
+
+/** @defgroup CR1 RTC Control 1 (CR1) Register
+ *  RTC Control 1 (CR1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_CR1_Struct
+ *! \brief  RTC Control 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR1_t__
+typedef struct _ADI_RTC_CR1_t {
+  union {
+    struct {
+      unsigned int CNTINTEN   :  1;  /**< Enable for the RTC Count Interrupt Source */
+      unsigned int PSINTEN    :  1;  /**< Enable for the Prescaled, Modulo-1 Interrupt Source, in SR2:RTCPSINT */
+      unsigned int TRMINTEN   :  1;  /**< Enable for the RTC Trim Interrupt Source, in SR2:RTCTRMINT */
+      unsigned int CNTROLLINTEN :  1;  /**< Enable for the RTC Count Roll-Over Interrupt Source, in SR2:RTCCNTROLLINT */
+      unsigned int CNTMOD60ROLLINTEN :  1;  /**< Enable for the RTC Modulo-60 Count Roll-Over Interrupt Source, in SR2:RTCCNTMOD60ROLLINT    */
+      unsigned int PRESCALE2EXP      :  4;  /**< Prescale Power of 2 Division Factor for the RTC Base Clock */
+      unsigned int reserved9         :  7;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_CR1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR1_t__ */
+
+/*@}*/
+
+/** @defgroup SR2 RTC Status 2 (SR2) Register
+ *  RTC Status 2 (SR2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SR2_Struct
+ *! \brief  RTC Status 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR2_t__
+typedef struct _ADI_RTC_SR2_t {
+  union {
+    struct {
+      unsigned int CNTINT     :  1;  /**< RTC Count Interrupt Source */
+      unsigned int PSINT      :  1;  /**< RTC Prescaled, Modulo-1 Boundary Interrupt Source */
+      unsigned int TRMINT     :  1;  /**< RTC Trim Interrupt Source */
+      unsigned int CNTROLLINT :  1;  /**< RTC Count Roll-Over Interrupt Source */
+      unsigned int CNTMOD60ROLLINT :  1;  /**< RTC Modulo-60 Count Roll-Over Interrupt Source */
+      unsigned int CNTROLL         :  1;  /**< RTC Count Roll-Over */
+      unsigned int CNTMOD60ROLL    :  1;  /**< RTC Count Modulo-60 Roll-Over */
+      unsigned int TRMBDYMIR       :  1;  /**< Mirror of MOD:RTCTRMBDY */
+      unsigned int reserved8       :  4;
+      unsigned int WPNDCR1MIR      :  1;  /**< Pending Status of Posted Writes to CR1 */
+      unsigned int WPNDALM2MIR     :  1;  /**< Pending Status of Posted Writes to ALM2 */
+      unsigned int WSYNCCR1MIR     :  1;  /**< Synchronization Status of Posted Writes to CR1 */
+      unsigned int WSYNCALM2MIR    :  1;  /**< Synchronization Status of Posted Writes to ALM2 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SR2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR2_t__ */
+
+/*@}*/
+
+/** @defgroup SNAP0 RTC Snapshot 0 (SNAP0) Register
+ *  RTC Snapshot 0 (SNAP0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SNAP0_Struct
+ *! \brief  RTC Snapshot 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SNAP0_t__
+typedef struct _ADI_RTC_SNAP0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Constituent Part of the 47-bit Input Capture Channel 0, Containing a Sticky Snapshot of  CNT0 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SNAP0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SNAP0_t__ */
+
+/*@}*/
+
+/** @defgroup SNAP1 RTC Snapshot 1 (SNAP1) Register
+ *  RTC Snapshot 1 (SNAP1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SNAP1_Struct
+ *! \brief  RTC Snapshot 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SNAP1_t__
+typedef struct _ADI_RTC_SNAP1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of  CNT1 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SNAP1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SNAP1_t__ */
+
+/*@}*/
+
+/** @defgroup SNAP2 RTC Snapshot 2 (SNAP2) Register
+ *  RTC Snapshot 2 (SNAP2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SNAP2_Struct
+ *! \brief  RTC Snapshot 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SNAP2_t__
+typedef struct _ADI_RTC_SNAP2_t {
+  union {
+    struct {
+      unsigned int VALUE      : 15;  /**< Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT2 */
+      unsigned int reserved15 :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SNAP2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SNAP2_t__ */
+
+/*@}*/
+
+/** @defgroup MOD RTC Modulo (MOD) Register
+ *  RTC Modulo (MOD) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_MOD_Struct
+ *! \brief  RTC Modulo Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_MOD_t__
+typedef struct _ADI_RTC_MOD_t {
+  union {
+    struct {
+      unsigned int CNTMOD60   :  6;  /**< Modulo-60 Value of the RTC Count: CNT1 and CNT0 */
+      unsigned int INCR       :  4;  /**< Most Recent Increment Value Added to the RTC Count in CNT1 and CNT0 */
+      unsigned int TRMBDY     :  1;  /**< Trim Boundary Indicator */
+      unsigned int CNT0_4TOZERO :  5;  /**< Mirror of CNT0[4:0] */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_MOD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_MOD_t__ */
+
+/*@}*/
+
+/** @defgroup CNT2 RTC Count 2 (CNT2) Register
+ *  RTC Count 2 (CNT2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_CNT2_Struct
+ *! \brief  RTC Count 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CNT2_t__
+typedef struct _ADI_RTC_CNT2_t {
+  union {
+    struct {
+      unsigned int VALUE      : 15;  /**< Fractional Bits of the RTC Real-Time Count */
+      unsigned int reserved15 :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_CNT2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CNT2_t__ */
+
+/*@}*/
+
+/** @defgroup ALM2 RTC Alarm 2 (ALM2) Register
+ *  RTC Alarm 2 (ALM2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_ALM2_Struct
+ *! \brief  RTC Alarm 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_ALM2_t__
+typedef struct _ADI_RTC_ALM2_t {
+  union {
+    struct {
+      unsigned int VALUE      : 15;  /**< Fractional Bits of the Alarm Target Time */
+      unsigned int reserved15 :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_ALM2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_ALM2_t__ */
+
+/*@}*/
+
+/** @defgroup SR3 RTC Status 3 (SR3) Register
+ *  RTC Status 3 (SR3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SR3_Struct
+ *! \brief  RTC Status 3 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR3_t__
+typedef struct _ADI_RTC_SR3_t {
+  union {
+    struct {
+      unsigned int IC0IRQ     :  1;  /**< Sticky Interrupt Source for the RTC Input Capture Channel 0 */
+      unsigned int reserved1  :  1;
+      unsigned int IC2IRQ     :  1;  /**< Sticky Interrupt Source for the RTC Input Capture Channel 2 */
+      unsigned int IC3IRQ     :  1;  /**< Sticky Interrupt Source for the RTC Input Capture Channel 3 */
+      unsigned int IC4IRQ     :  1;  /**< Sticky Interrupt Source for the RTC Input Capture Channel 4 */
+      unsigned int SS1FEIRQ   :  1;  /**< Sticky Interrupt Source for the SensorStrobe Channel 1 Falling Edge */
+      unsigned int SS2FEIRQ   :  1;  /**< Sticky Interrupt Source for the SensorStrobe Channel 2 Falling Edge */
+      unsigned int SS3FEIRQ   :  1;  /**< Sticky Interrupt Source for the SensorStrobe Channel 3 Falling Edge */
+      unsigned int SS4FEIRQ   :  1;  /**< Sticky Interrupt Source for the SensorStrobe Channel 4 Falling Edge */
+      unsigned int SS1IRQ     :  1;  /**< Sticky Interrupt Source for SensorStrobe Channel 1 */
+      unsigned int SS2IRQ     :  1;  /**< Sticky Interrupt Source for the SensorStrobe Channel 2 */
+      unsigned int SS3IRQ     :  1;  /**< Sticky Interrupt Source for the SensorStrobe Channel 3 */
+      unsigned int SS4IRQ     :  1;  /**< Sticky Interrupt Source for the SensorStrobe Channel 4 */
+      unsigned int ALMINTMIR  :  1;  /**< Read-only Mirror of the SR0:ALMINT Interrupt Source */
+      unsigned int reserved14 :  2;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SR3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR3_t__ */
+
+/*@}*/
+
+/** @defgroup CR2IC RTC Control 2 for Configuring Input Capture Channels (CR2IC) Register
+ *  RTC Control 2 for Configuring Input Capture Channels (CR2IC) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_CR2IC_Struct
+ *! \brief  RTC Control 2 for Configuring Input Capture Channels Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR2IC_t__
+typedef struct _ADI_RTC_CR2IC_t {
+  union {
+    struct {
+      unsigned int IC0EN      :  1;  /**< Enable for the RTC Input Capture Channel 0 */
+      unsigned int reserved1  :  1;
+      unsigned int IC2EN      :  1;  /**< Enable for the RTC Input Capture Channel 2 */
+      unsigned int IC3EN      :  1;  /**< Enable for the RTC Input Capture Channel 3 */
+      unsigned int IC4EN      :  1;  /**< Enable for the RTC Input Capture Channel 4 */
+      unsigned int IC0LH      :  1;  /**< Polarity of the Active-Going Capture Edge for the RTC Input Capture Channel 0 */
+      unsigned int reserved6  :  1;
+      unsigned int IC2LH      :  1;  /**< Polarity of the Active-going Capture Edge for the Input Capture Channel 2 */
+      unsigned int IC3LH      :  1;  /**< Polarity of the Active-going Capture Edge for the Input Capture Channel 3 */
+      unsigned int IC4LH      :  1;  /**< Polarity of the Active-going Capture Edge for the Input Capture Channel 4 */
+      unsigned int IC0IRQEN   :  1;  /**< Interrupt Enable for the RTC Input Capture Channel 0 */
+      unsigned int reserved11 :  1;
+      unsigned int IC2IRQEN   :  1;  /**< Interrupt Enable for the RTC Input Capture Channel 2 */
+      unsigned int IC3IRQEN   :  1;  /**< Interrupt Enable for the RTC Input Capture Channel 3 */
+      unsigned int IC4IRQEN   :  1;  /**< Interrupt Enable for the RTC Input Capture Channel 4 */
+      unsigned int ICOWUSEN   :  1;  /**< Enable Overwrite of Unread Snapshots for All Input Capture Channels */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_CR2IC_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR2IC_t__ */
+
+/*@}*/
+
+/** @defgroup CR3SS RTC Control 3 for Configuring SensorStrobe Channel (CR3SS) Register
+ *  RTC Control 3 for Configuring SensorStrobe Channel (CR3SS) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_CR3SS_Struct
+ *! \brief  RTC Control 3 for Configuring SensorStrobe Channel Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR3SS_t__
+typedef struct _ADI_RTC_CR3SS_t {
+  union {
+    struct {
+      unsigned int reserved0  :  1;
+      unsigned int SS1EN      :  1;  /**< Enable for SensorStrobe Channel 1 */
+      unsigned int SS2EN      :  1;  /**< Enable for the SensorStrobe Channel 2 */
+      unsigned int SS3EN      :  1;  /**< Enable for the SensorStrobe Channel 3 */
+      unsigned int SS4EN      :  1;  /**< Enable for the SensorStrobe Channel 4 */
+      unsigned int SS1FEIRQEN :  1;  /**< Falling Edge Interrupt Enable for the SensorStrobe Channel 1 */
+      unsigned int SS2FEIRQEN :  1;  /**< Falling Edge Interrupt Enable for the SensorStrobe Channel 2 */
+      unsigned int SS3FEIRQEN :  1;  /**< Falling Edge Interrupt Enable for the SensorStrobe Channel 3 */
+      unsigned int SS4FEIRQEN :  1;  /**< Falling Edge Interrupt Enable for the SensorStrobe Channel 4 */
+      unsigned int SS1IRQEN   :  1;  /**< Interrupt Enable for SensorStrobe Channel 1 */
+      unsigned int SS2IRQEN   :  1;  /**< Posedge EdgeInterrupt Enable for the SensorStrobe Channel 2 */
+      unsigned int SS3IRQEN   :  1;  /**< Posedge EdgeInterrupt Enable for the SensorStrobe Channel 3 */
+      unsigned int SS4IRQEN   :  1;  /**< Posedge EdgeInterrupt Enable for the SensorStrobe Channel 4 */
+      unsigned int reserved13 :  3;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_CR3SS_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR3SS_t__ */
+
+/*@}*/
+
+/** @defgroup CR4SS RTC Control 4 for Configuring SensorStrobe Channel (CR4SS) Register
+ *  RTC Control 4 for Configuring SensorStrobe Channel (CR4SS) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_RTC_CR4SS_SS1MSKEN
+ *! \brief  Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 (SS1MSKEN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  RTC_CR4SS_NO_MSK    = 0,  /**< Do not apply a mask to SensorStrobe Channel 1 Register */
+  RTC_CR4SS_THERM_MSK = 1   /**< Apply thermometer decoded mask                         */
+} ADI_RTC_CR4SS_SS1MSKEN;
+
+
+/* ==========================================================================
+ *! \struct ADI_RTC_CR4SS_Struct
+ *! \brief  RTC Control 4 for Configuring SensorStrobe Channel Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR4SS_t__
+typedef struct _ADI_RTC_CR4SS_t {
+  union {
+    struct {
+      unsigned int reserved0  :  1;
+      unsigned int SS1MSKEN   :  1;  /**< Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 */
+      unsigned int SS2MSKEN   :  1;  /**< Enable for Thermometer-Code Masking of the SensorStrobe Channel 2 */
+      unsigned int SS3MSKEN   :  1;  /**< Enable for Thermometer-Code Masking of the SensorStrobe Channel 3 */
+      unsigned int SS4MSKEN   :  1;  /**< Enable for Thermometer-Code Masking of the SensorStrobe Channel 4 */
+      unsigned int SS1POL     :  1;  /**< SensorSTrobe Channel 1 Polarity Control */
+      unsigned int SS2POL     :  1;  /**< SensorStrobe Channel 2 Polarity Control */
+      unsigned int SS3POL     :  1;  /**< SensorStrobe Channel 3 Polarity Control */
+      unsigned int SS4POL     :  1;  /**< SensorStrobe Channel 4 Polarity Control */
+      unsigned int SS1ARLEN   :  1;  /**< Enable for Fine Control on SensorStrobe Channel 1 Period and Duty Cycle */
+      unsigned int SS2ARLEN   :  1;  /**< Enable for Fine Control on SensorStrobe Channel 2 Period and Duty Cycle */
+      unsigned int SS3ARLEN   :  1;  /**< Enable for Fine Control on SensorStrobe Channel 3 Period and Duty Cycle */
+      unsigned int reserved12 :  4;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_CR4SS_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR4SS_t__ */
+
+/*@}*/
+
+/** @defgroup SSMSK RTC Mask for SensorStrobe Channel (SSMSK) Register
+ *  RTC Mask for SensorStrobe Channel (SSMSK) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SSMSK_Struct
+ *! \brief  RTC Mask for SensorStrobe Channel Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SSMSK_t__
+typedef struct _ADI_RTC_SSMSK_t {
+  union {
+    struct {
+      unsigned int SS1MSK     :  4;  /**< Concatenation of Thermometer-Encoded Masks for the 16-bit SensorStrobe Channels */
+      unsigned int SS2MSK     :  4;  /**< SensorStrobe Channel 2 Period Control */
+      unsigned int SS3MSK     :  4;  /**< SensorStrobe Channel 3 Period Control */
+      unsigned int SS4MSK     :  4;  /**< SensorStrobe Channel 4 Period Control */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SSMSK_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SSMSK_t__ */
+
+/*@}*/
+
+/** @defgroup IC2 RTC Input Capture Channel 2 (IC2) Register
+ *  RTC Input Capture Channel 2 (IC2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_IC2_Struct
+ *! \brief  RTC Input Capture Channel 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_IC2_t__
+typedef struct _ADI_RTC_IC2_t {
+  union {
+    struct {
+      unsigned int IC2        : 16;  /**< RTC Input Capture Channel 2 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_IC2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_IC2_t__ */
+
+/*@}*/
+
+/** @defgroup IC3 RTC Input Capture Channel 3 (IC3) Register
+ *  RTC Input Capture Channel 3 (IC3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_IC3_Struct
+ *! \brief  RTC Input Capture Channel 3 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_IC3_t__
+typedef struct _ADI_RTC_IC3_t {
+  union {
+    struct {
+      unsigned int IC3        : 16;  /**< RTC Input Capture Channel 3 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_IC3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_IC3_t__ */
+
+/*@}*/
+
+/** @defgroup IC4 RTC Input Capture Channel 4 (IC4) Register
+ *  RTC Input Capture Channel 4 (IC4) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_IC4_Struct
+ *! \brief  RTC Input Capture Channel 4 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_IC4_t__
+typedef struct _ADI_RTC_IC4_t {
+  union {
+    struct {
+      unsigned int IC4        : 16;  /**< RTC Input Capture Channel 4 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_IC4_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_IC4_t__ */
+
+/*@}*/
+
+/** @defgroup SS1 RTC SensorStrobe Channel 1 (SS1) Register
+ *  RTC SensorStrobe Channel 1 (SS1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SS1_Struct
+ *! \brief  RTC SensorStrobe Channel 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS1_t__
+typedef struct _ADI_RTC_SS1_t {
+  union {
+    struct {
+      unsigned int SS1        : 16;  /**< SensorStrobe Channel 1 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SS1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS1_t__ */
+
+/*@}*/
+
+/** @defgroup SS2 RTC SensorStrobe Channel 2 (SS2) Register
+ *  RTC SensorStrobe Channel 2 (SS2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SS2_Struct
+ *! \brief  RTC SensorStrobe Channel 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS2_t__
+typedef struct _ADI_RTC_SS2_t {
+  union {
+    struct {
+      unsigned int SS2        : 16;  /**< SensorStrobe Channel 2 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SS2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS2_t__ */
+
+/*@}*/
+
+/** @defgroup SS3 RTC SensorStrobe Channel 3 (SS3) Register
+ *  RTC SensorStrobe Channel 3 (SS3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SS3_Struct
+ *! \brief  RTC SensorStrobe Channel 3 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS3_t__
+typedef struct _ADI_RTC_SS3_t {
+  union {
+    struct {
+      unsigned int SS3        : 16;  /**< SensorStrobe Channel 3 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SS3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS3_t__ */
+
+/*@}*/
+
+/** @defgroup SS4 RTC SensorStrobe Channel 4 (SS4) Register
+ *  RTC SensorStrobe Channel 4 (SS4) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SS4_Struct
+ *! \brief  RTC SensorStrobe Channel 4 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS4_t__
+typedef struct _ADI_RTC_SS4_t {
+  union {
+    struct {
+      unsigned int SS4        : 16;  /**< SensorStrobe Channel 4 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SS4_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS4_t__ */
+
+/*@}*/
+
+/** @defgroup SR4 RTC Status 4 (SR4) Register
+ *  RTC Status 4 (SR4) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SR4_Struct
+ *! \brief  RTC Status 4 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR4_t__
+typedef struct _ADI_RTC_SR4_t {
+  union {
+    struct {
+      unsigned int WSYNCSR3   :  1;  /**< Synchronisation Status of Posted Writes to SR3 */
+      unsigned int WSYNCCR2IC :  1;  /**< Synchronization Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */
+      unsigned int WSYNCCR3SS :  1;  /**< Synchronization Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */
+      unsigned int WSYNCCR4SS :  1;  /**< Synchronization Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */
+      unsigned int WSYNCSSMSK :  1;  /**< Synchronization Status of Posted Writes to Masks for SensorStrobe Channel Register */
+      unsigned int reserved5  :  1;
+      unsigned int WSYNCSS1   :  1;  /**< Synchronization Status of Posted Writes to SensorStrobe Channel 1 */
+      unsigned int WSYNCSS2   :  1;  /**< Synchronization Status of Posted Writes to SensorStrobe Channel 2 */
+      unsigned int WSYNCSS3   :  1;  /**< Synchronization Status of Posted Writes to SensorStrobe Channel 3 */
+      unsigned int WSYNCSS4   :  1;  /**< Synchronization Status of Posted Writes to SensorStrobe Channel 4 */
+      unsigned int RSYNCIC0   :  1;  /**< Synchronization Status of Posted Reads of RTC Input Channel 0 */
+      unsigned int reserved11 :  1;
+      unsigned int RSYNCIC2   :  1;  /**< Synchronization Status of Posted Reads of RTC Input Channel 2 */
+      unsigned int RSYNCIC3   :  1;  /**< Synchronization Status of Posted Reads of RTC Input Channel 3 */
+      unsigned int RSYNCIC4   :  1;  /**< Synchronization Status of Posted Reads of RTC Input Channel 4 */
+      unsigned int WSYNCSSMSKOT :  1;  /**< Synchronization Status of Posted Reads Writes to Mask for SensorStrobe Channels on Time Control Register */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SR4_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR4_t__ */
+
+/*@}*/
+
+/** @defgroup SR5 RTC Status 5 (SR5) Register
+ *  RTC Status 5 (SR5) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SR5_Struct
+ *! \brief  RTC Status 5 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR5_t__
+typedef struct _ADI_RTC_SR5_t {
+  union {
+    struct {
+      unsigned int WPENDSR3   :  1;  /**< Pending Status of Posted Clearances of Interrupt Sources in RTC Status 3 Register */
+      unsigned int WPENDCR2IC :  1;  /**< Pending Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */
+      unsigned int WPENDCR3SS :  1;  /**< Pending Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */
+      unsigned int WPENDCR4SS :  1;  /**< Pending Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */
+      unsigned int WPENDSSMSK :  1;  /**< Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */
+      unsigned int reserved5  :  1;
+      unsigned int WPENDSS1   :  1;  /**< Pending Status of Posted Writes to SensorStrobe Channel 1 */
+      unsigned int WPENDSS2   :  1;  /**< Pending Status of Posted Writes to SensorStrobe Channel 2 */
+      unsigned int WPENDSS3   :  1;  /**< Pending Status of Posted Writes to SensorStrobe Channel 3 */
+      unsigned int WPENDSS4   :  1;  /**< Pending Status of Posted Writes to SensorStrobe Channel 4 */
+      unsigned int RPENDIC0   :  1;  /**< Pending Status of Posted Reads of Input Capture Channel 0 */
+      unsigned int reserved11 :  1;
+      unsigned int RPENDIC2   :  1;  /**< Pending Status of Posted Reads of IC2 */
+      unsigned int RPENDIC3   :  1;  /**< Pending Status of Posted Reads of IC3 */
+      unsigned int RPENDIC4   :  1;  /**< Pending Status of Posted Reads of IC4 */
+      unsigned int WPENDSSMSKOT :  1;  /**< Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SR5_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR5_t__ */
+
+/*@}*/
+
+/** @defgroup SR6 RTC Status 6 (SR6) Register
+ *  RTC Status 6 (SR6) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SR6_Struct
+ *! \brief  RTC Status 6 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR6_t__
+typedef struct _ADI_RTC_SR6_t {
+  union {
+    struct {
+      unsigned int IC0UNR     :  1;  /**< Sticky Unread Status of the Input Capture Channel 0 */
+      unsigned int reserved1  :  1;
+      unsigned int IC2UNR     :  1;  /**< Sticky Unread Status of the Input Capture Channel 2 */
+      unsigned int IC3UNR     :  1;  /**< Sticky Unread Status of the Input Capture Channel 3 */
+      unsigned int IC4UNR     :  1;  /**< Sticky Unread Status of the Input Capture Channel 4 */
+      unsigned int reserved5  :  3;
+      unsigned int IC0SNAP    :  1;  /**< Confirmation That RTC Snapshot 0, 1, 2 Registers Reflect the Value of Input-Capture Channel RTC Input Capture Channel 0 */
+      unsigned int FRZCNTPTR  :  2;  /**< Pointer for the Triple-Read Sequence of FRZCNT */
+      unsigned int reserved11 :  5;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SR6_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR6_t__ */
+
+/*@}*/
+
+/** @defgroup SS1TGT RTC SensorStrobe Channel 1 Target (SS1TGT) Register
+ *  RTC SensorStrobe Channel 1 Target (SS1TGT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SS1TGT_Struct
+ *! \brief  RTC SensorStrobe Channel 1 Target Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS1TGT_t__
+typedef struct _ADI_RTC_SS1TGT_t {
+  union {
+    struct {
+      unsigned int SS1TGT     : 16;  /**< Current Target Value for the SensorStrobe Channel 1 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SS1TGT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS1TGT_t__ */
+
+/*@}*/
+
+/** @defgroup FRZCNT RTC Freeze Count (FRZCNT) Register
+ *  RTC Freeze Count (FRZCNT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_FRZCNT_Struct
+ *! \brief  RTC Freeze Count Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_FRZCNT_t__
+typedef struct _ADI_RTC_FRZCNT_t {
+  union {
+    struct {
+      unsigned int FRZCNT     : 16;  /**< RTC Freeze Count. Coherent, Triple 16-Bit Read of the 47-Bit RTC Count */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_FRZCNT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_FRZCNT_t__ */
+
+/*@}*/
+
+/** @defgroup SS2TGT RTC SensorStrobe Channel 2 Target (SS2TGT) Register
+ *  RTC SensorStrobe Channel 2 Target (SS2TGT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SS2TGT_Struct
+ *! \brief  RTC SensorStrobe Channel 2 Target Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS2TGT_t__
+typedef struct _ADI_RTC_SS2TGT_t {
+  union {
+    struct {
+      unsigned int SS2TGT     : 16;  /**< Current, Cumulative Target Time for SensorStrobe Channel 2, Taking Account of Any Auto-reloading */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SS2TGT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS2TGT_t__ */
+
+/*@}*/
+
+/** @defgroup SS3TGT RTC SensorStrobe Channel 3 Target (SS3TGT) Register
+ *  RTC SensorStrobe Channel 3 Target (SS3TGT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SS3TGT_Struct
+ *! \brief  RTC SensorStrobe Channel 3 Target Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS3TGT_t__
+typedef struct _ADI_RTC_SS3TGT_t {
+  union {
+    struct {
+      unsigned int SS3TGT     : 16;  /**< Current, Cumulative Target Time for SensorStrobe Channel 3, Taking Account of Any Auto-reloading */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SS3TGT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS3TGT_t__ */
+
+/*@}*/
+
+/** @defgroup SS1LOWDUR RTC Auto-Reload Low Duration for SensorStrobe Channel 1 (SS1LOWDUR) Register
+ *  RTC Auto-Reload Low Duration for SensorStrobe Channel 1 (SS1LOWDUR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SS1LOWDUR_Struct
+ *! \brief  RTC Auto-Reload Low Duration for SensorStrobe Channel 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS1LOWDUR_t__
+typedef struct _ADI_RTC_SS1LOWDUR_t {
+  union {
+    struct {
+      unsigned int SS1LOWDUR  : 16;  /**< Low Duration for SensorStrobe Channel 1. */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SS1LOWDUR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS1LOWDUR_t__ */
+
+/*@}*/
+
+/** @defgroup SS2LOWDUR RTC Auto-Reload Low Duration for SensorStrobe Channel 2 (SS2LOWDUR) Register
+ *  RTC Auto-Reload Low Duration for SensorStrobe Channel 2 (SS2LOWDUR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SS2LOWDUR_Struct
+ *! \brief  RTC Auto-Reload Low Duration for SensorStrobe Channel 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS2LOWDUR_t__
+typedef struct _ADI_RTC_SS2LOWDUR_t {
+  union {
+    struct {
+      unsigned int SS2LOWDUR  : 16;  /**< Low Duration for SensorStrobe Channel 2. */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SS2LOWDUR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS2LOWDUR_t__ */
+
+/*@}*/
+
+/** @defgroup SS3LOWDUR RTC Auto-Reload Low Duration for SensorStrobe Channel 3 (SS3LOWDUR) Register
+ *  RTC Auto-Reload Low Duration for SensorStrobe Channel 3 (SS3LOWDUR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SS3LOWDUR_Struct
+ *! \brief  RTC Auto-Reload Low Duration for SensorStrobe Channel 3 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS3LOWDUR_t__
+typedef struct _ADI_RTC_SS3LOWDUR_t {
+  union {
+    struct {
+      unsigned int SS3LOWDUR  : 16;  /**< Low Duration for SensorStrobe Channel 3. */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SS3LOWDUR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS3LOWDUR_t__ */
+
+/*@}*/
+
+/** @defgroup SS1HIGHDUR RTC Auto-Reload High Duration for SensorStrobe Channel 1 (SS1HIGHDUR) Register
+ *  RTC Auto-Reload High Duration for SensorStrobe Channel 1 (SS1HIGHDUR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SS1HIGHDUR_Struct
+ *! \brief  RTC Auto-Reload High Duration for SensorStrobe Channel 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS1HIGHDUR_t__
+typedef struct _ADI_RTC_SS1HIGHDUR_t {
+  union {
+    struct {
+      unsigned int SS1HIGHDUR : 16;  /**< High Duration for SensorStrobe Channel 1. */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SS1HIGHDUR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS1HIGHDUR_t__ */
+
+/*@}*/
+
+/** @defgroup SS2HIGHDUR RTC Auto-Reload High Duration for SensorStrobe Channel 2 (SS2HIGHDUR) Register
+ *  RTC Auto-Reload High Duration for SensorStrobe Channel 2 (SS2HIGHDUR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SS2HIGHDUR_Struct
+ *! \brief  RTC Auto-Reload High Duration for SensorStrobe Channel 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS2HIGHDUR_t__
+typedef struct _ADI_RTC_SS2HIGHDUR_t {
+  union {
+    struct {
+      unsigned int SS2HIGHDUR : 16;  /**< High Duration for SensorStrobe Channel 2. */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SS2HIGHDUR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS2HIGHDUR_t__ */
+
+/*@}*/
+
+/** @defgroup SS3HIGHDUR RTC Auto-Reload High Duration for SensorStrobe Channel 3 (SS3HIGHDUR) Register
+ *  RTC Auto-Reload High Duration for SensorStrobe Channel 3 (SS3HIGHDUR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SS3HIGHDUR_Struct
+ *! \brief  RTC Auto-Reload High Duration for SensorStrobe Channel 3 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS3HIGHDUR_t__
+typedef struct _ADI_RTC_SS3HIGHDUR_t {
+  union {
+    struct {
+      unsigned int SS3HIGHDUR : 16;  /**< High Duration for SensorStrobe Channel 3. */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SS3HIGHDUR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS3HIGHDUR_t__ */
+
+/*@}*/
+
+/** @defgroup SSMSKOT RTC Masks for SensorStrobe Channels on Time Control (SSMSKOT) Register
+ *  RTC Masks for SensorStrobe Channels on Time Control (SSMSKOT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SSMSKOT_Struct
+ *! \brief  RTC Masks for SensorStrobe Channels on Time Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SSMSKOT_t__
+typedef struct _ADI_RTC_SSMSKOT_t {
+  union {
+    struct {
+      unsigned int SS1MSKOT   :  4;  /**< Concatenation of Thermometer-encoded Masks for the 16-bit SensorStrobe Channels */
+      unsigned int SS2MSKOT   :  4;  /**< SensorStrobe Channel 2 on Time Control */
+      unsigned int SS3MSKOT   :  4;  /**< SensorStrobe Channel 3 on Time Control */
+      unsigned int SS4MSKOT   :  4;  /**< SensorStrobe Channel 4 on Time Control */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SSMSKOT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SSMSKOT_t__ */
+
+/*@}*/
+
+/** @defgroup CR5SSS RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling (CR5SSS) Register
+ *  RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling (CR5SSS) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_CR5SSS_Struct
+ *! \brief  RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR5SSS_t__
+typedef struct _ADI_RTC_CR5SSS_t {
+  union {
+    struct {
+      unsigned int SS1SMPEN   :  3;  /**< GPIO Input Sample Enable for SensorStrobe Channel 1 */
+      unsigned int SS1SMPMTCHIRQEN :  1;  /**< Sample Activity Interrupt Enable for SensorStrobe Channel 1 */
+      unsigned int SS2SMPEN        :  3;  /**< GPIO Input Sample Enable for SensorStrobe Channel 2 */
+      unsigned int SS2SMPMTCHIRQEN :  1;  /**< Sample Activity Interrupt Enable for SensorStrobe Channel 2 */
+      unsigned int SS3SMPEN        :  3;  /**< GPIO Input Sample Enable for SensorStrobe Channel 3 */
+      unsigned int SS3SMPMTCHIRQEN :  1;  /**< Sample Activity Interrupt Enable for SensorStrobe Channel 3 */
+      unsigned int reserved12      :  4;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_CR5SSS_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR5SSS_t__ */
+
+/*@}*/
+
+/** @defgroup CR6SSS RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge (CR6SSS) Register
+ *  RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge (CR6SSS) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_RTC_CR6SSS_SS1SMPONFE
+ *! \brief  GPIO Sample Around Falling Edge of SensorStrobe Channel 1 (SS1SMPONFE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  RTC_CR6SSS_SS1NOFES = 0,  /**< No sampling of input around falling edge                                        */
+  RTC_CR6SSS_SS1BFES  = 1,  /**< Input sampled one clock cycle before falling edge of the SensorStrobe channel 1 */
+  RTC_CR6SSS_SS1FES   = 2,  /**< Input sampled at falling edge of the SensorStrobe channel 1                     */
+  RTC_CR6SSS_SS1AFES  = 3   /**< Input sampled one clock cycle after falling edge of the SensorStrobe channel 1  */
+} ADI_RTC_CR6SSS_SS1SMPONFE;
+
+
+/*  =========================================================================
+ *! \enum   ADI_RTC_CR6SSS_SS1SMPONRE
+ *! \brief  GPIO Sample Around Rising Edge of SensorStrobe Channel 1 (SS1SMPONRE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  RTC_CR6SSS_SS1NORES = 0,  /**< No sampling of input around rising edge                                        */
+  RTC_CR6SSS_SS1BRES  = 1,  /**< Input sampled one clock cycle before rising edge of the SensorStrobe channel 1 */
+  RTC_CR6SSS_SS1RES   = 2,  /**< Input sampled at rising edge of the SensorStrobe channel 1                     */
+  RTC_CR6SSS_SS1ARES  = 3   /**< Input sampled one clock cycle after rising edge of the SensorStrobe channel 1  */
+} ADI_RTC_CR6SSS_SS1SMPONRE;
+
+
+/*  =========================================================================
+ *! \enum   ADI_RTC_CR6SSS_SS2SMPONFE
+ *! \brief  GPIO Sample Around Falling Edge of SensorStrobe Channel 2 (SS2SMPONFE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  RTC_CR6SSS_SS2NOFES = 0,  /**< No sampling of input around falling edge                                        */
+  RTC_CR6SSS_SS2BFES  = 1,  /**< Input sampled one clock cycle before falling edge of the SensorStrobe channel 2 */
+  RTC_CR6SSS_SS2FES   = 2,  /**< Input sampled at falling edge of the SensorStrobe channel 2                     */
+  RTC_CR6SSS_SS2AFES  = 3   /**< Input sampled one clock cycle after falling edge of the SensorStrobe channel 2  */
+} ADI_RTC_CR6SSS_SS2SMPONFE;
+
+
+/*  =========================================================================
+ *! \enum   ADI_RTC_CR6SSS_SS2SMPONRE
+ *! \brief  GPIO Sample Around Rising Edge of SensorStrobe Channel 2 (SS2SMPONRE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  RTC_CR6SSS_SS2NORES = 0,  /**< No sampling of input around rising edge                                        */
+  RTC_CR6SSS_SS2BRES  = 1,  /**< Input sampled one clock cycle before rising edge of the SensorStrobe channel 2 */
+  RTC_CR6SSS_SS2RES   = 2,  /**< Input sampled at rising edge of the SensorStrobe channel 2                     */
+  RTC_CR6SSS_SS2ARES  = 3   /**< Input sampled one clock cycle after rising edge of the SensorStrobe channel 2  */
+} ADI_RTC_CR6SSS_SS2SMPONRE;
+
+
+/*  =========================================================================
+ *! \enum   ADI_RTC_CR6SSS_SS3SMPONFE
+ *! \brief  GPIO Sample Around Falling Edge of SensorStrobe Channel 3 (SS3SMPONFE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  RTC_CR6SSS_SS3NOFES = 0,  /**< No sampling of input around falling edge                                        */
+  RTC_CR6SSS_SS3BFES  = 1,  /**< Input sampled one clock cycle before falling edge of the SensorStrobe channel 3 */
+  RTC_CR6SSS_SS3FES   = 2,  /**< Input sampled at falling edge of the SensorStrobe channel 3                     */
+  RTC_CR6SSS_SS3AFES  = 3   /**< Input sampled one clock cycle after falling edge of the SensorStrobe channel 3  */
+} ADI_RTC_CR6SSS_SS3SMPONFE;
+
+
+/*  =========================================================================
+ *! \enum   ADI_RTC_CR6SSS_SS3SMPONRE
+ *! \brief  GPIO Sample Around Rising Edge of SensorStrobe Channel 3 (SS3SMPONRE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  RTC_CR6SSS_SS3NORES = 0,  /**< No sampling of input around rising edge                                        */
+  RTC_CR6SSS_SS3BRES  = 1,  /**< Input sampled one clock cycle before rising edge of the SensorStrobe channel 3 */
+  RTC_CR6SSS_SS3RES   = 2,  /**< Input sampled at rising edge of the SensorStrobe channel 3                     */
+  RTC_CR6SSS_SS3ARES  = 3   /**< Input sampled one clock cycle after rising edge of the SensorStrobe channel 3  */
+} ADI_RTC_CR6SSS_SS3SMPONRE;
+
+
+/* ==========================================================================
+ *! \struct ADI_RTC_CR6SSS_Struct
+ *! \brief  RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR6SSS_t__
+typedef struct _ADI_RTC_CR6SSS_t {
+  union {
+    struct {
+      unsigned int SS1SMPONFE :  2;  /**< GPIO Sample Around Falling Edge of SensorStrobe Channel 1 */
+      unsigned int SS1SMPONRE :  2;  /**< GPIO Sample Around Rising Edge of SensorStrobe Channel 1 */
+      unsigned int SS2SMPONFE :  2;  /**< GPIO Sample Around Falling Edge of SensorStrobe Channel 2 */
+      unsigned int SS2SMPONRE :  2;  /**< GPIO Sample Around Rising Edge of SensorStrobe Channel 2 */
+      unsigned int SS3SMPONFE :  2;  /**< GPIO Sample Around Falling Edge of SensorStrobe Channel 3 */
+      unsigned int SS3SMPONRE :  2;  /**< GPIO Sample Around Rising Edge of SensorStrobe Channel 3 */
+      unsigned int reserved12 :  4;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_CR6SSS_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR6SSS_t__ */
+
+/*@}*/
+
+/** @defgroup CR7SSS RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity (CR7SSS) Register
+ *  RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity (CR7SSS) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_RTC_CR7SSS_SS1SMPPTRN
+ *! \brief  Sample Activity Selection for SensorStrobe Channel 1 (SS1SMPPTRN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  RTC_CR7SSS_SS1SMPCHNG   = 0,  /**< Current GPIO sample is not same as previous sample */
+  RTC_CR7SSS_SS1SMPSAME   = 1,  /**< Current GPIO sample is same as previous sample     */
+  RTC_CR7SSS_SS1SMPMTCH   = 2,  /**< Current GPIO sample is same as expected sample     */
+  RTC_CR7SSS_SS1SMPNOMTCH = 3   /**< Current GPIO sample is not same as expected sample */
+} ADI_RTC_CR7SSS_SS1SMPPTRN;
+
+
+/*  =========================================================================
+ *! \enum   ADI_RTC_CR7SSS_SS2SMPPTRN
+ *! \brief  Sample Activity Selection for SensorStrobe Channel 2 (SS2SMPPTRN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  RTC_CR7SSS_SS2SMPCHNG   = 0,  /**< Current GPIO sample is not same as previous sample */
+  RTC_CR7SSS_SS2SMPSAME   = 1,  /**< Current GPIO sample is same as previous sample     */
+  RTC_CR7SSS_SS2SMPMTCH   = 2,  /**< Current GPIO sample is same as expected sample     */
+  RTC_CR7SSS_SS2SMPNOMTCH = 3   /**< Current GPIO sample is not same as expected sample */
+} ADI_RTC_CR7SSS_SS2SMPPTRN;
+
+
+/*  =========================================================================
+ *! \enum   ADI_RTC_CR7SSS_SS3SMPPTRN
+ *! \brief  Sample Activity Selection for SensorStrobe Channel 3 (SS3SMPPTRN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  RTC_CR7SSS_SS3SMPCHNG   = 0,  /**< Current GPIO sample is not same as previous sample */
+  RTC_CR7SSS_SS3SMPSAME   = 1,  /**< Current GPIO sample is same as previous sample     */
+  RTC_CR7SSS_SS3SMPMTCH   = 2,  /**< Current GPIO sample is same as expected sample     */
+  RTC_CR7SSS_SS3SMPNOMTCH = 3   /**< Current GPIO sample is not same as expected sample */
+} ADI_RTC_CR7SSS_SS3SMPPTRN;
+
+
+/* ==========================================================================
+ *! \struct ADI_RTC_CR7SSS_Struct
+ *! \brief  RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR7SSS_t__
+typedef struct _ADI_RTC_CR7SSS_t {
+  union {
+    struct {
+      unsigned int SS1SMPEXP  :  3;  /**< Expected GPIO Sample for SensorStrobe Channel 1 */
+      unsigned int SS1SMPPTRN :  2;  /**< Sample Activity Selection for SensorStrobe Channel 1 */
+      unsigned int SS2SMPEXP  :  3;  /**< Expected GPIO Sample for SensorStrobe Channel 2 */
+      unsigned int SS2SMPPTRN :  2;  /**< Sample Activity Selection for SensorStrobe Channel 2 */
+      unsigned int SS3SMPEXP  :  3;  /**< Expected GPIO Sample for SensorStrobe Channel 3 */
+      unsigned int SS3SMPPTRN :  2;  /**< Sample Activity Selection for SensorStrobe Channel 3 */
+      unsigned int reserved15 :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_CR7SSS_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR7SSS_t__ */
+
+/*@}*/
+
+/** @defgroup SR7 RTC Status 7 (SR7) Register
+ *  RTC Status 7 (SR7) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SR7_Struct
+ *! \brief  RTC Status 7 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR7_t__
+typedef struct _ADI_RTC_SR7_t {
+  union {
+    struct {
+      unsigned int SS1SMP     :  3;  /**< Latest GPIO Sample for SensorStrobe Channel 1 */
+      unsigned int SS1SMPMTCHIRQ :  1;  /**< Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 1 */
+      unsigned int SS2SMP        :  3;  /**< Latest GPIO Sample for SensorStrobe Channel 2 */
+      unsigned int SS2SMPMTCHIRQ :  1;  /**< Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 2 */
+      unsigned int SS3SMP        :  3;  /**< Latest GPIO Sample for SensorStrobe Channel 3 */
+      unsigned int SS3SMPMTCHIRQ :  1;  /**< Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 3 */
+      unsigned int SS1OUT        :  1;  /**< Output Value for SensorStrobe Channel 1 */
+      unsigned int SS2OUT        :  1;  /**< Output Value for SensorStrobe Channel 2 */
+      unsigned int SS3OUT        :  1;  /**< Output Value for SensorStrobe Channel 3 */
+      unsigned int SS4OUT        :  1;  /**< Output Value for SensorStrobe Channel 4 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SR7_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR7_t__ */
+
+/*@}*/
+
+/** @defgroup SR8 RTC Status 8 (SR8) Register
+ *  RTC Status 8 (SR8) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SR8_Struct
+ *! \brief  RTC Status 8 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR8_t__
+typedef struct _ADI_RTC_SR8_t {
+  union {
+    struct {
+      unsigned int WSYNCSS1LOWDUR :  1;  /**< Synchronisation Status of Posted Writes to SensorStrobe Channel 1 Low Duration Register */
+      unsigned int WSYNCSS2LOWDUR :  1;  /**< Synchronisation Status of Posted Writes to SensorStrobe Channel 2 Low Duration Register */
+      unsigned int WSYNCSS3LOWDUR :  1;  /**< Synchronisation Status of Posted Writes to SensorStrobe Channel 3 Low Duration Register */
+      unsigned int reserved3       :  1;
+      unsigned int WSYNCSS1HIGHDUR :  1;  /**< Synchronisation Status of Posted Writes to SensorStrobe Channel 1 High Duration Register */
+      unsigned int WSYNCSS2HIGHDUR :  1;  /**< Synchronisation Status of Posted Writes to SensorStrobe Channel 2 High Duration Register */
+      unsigned int WSYNCSS3HIGHDUR :  1;  /**< Synchronisation Status of Posted Writes to SensorStrobe Channel 3 High Duration Register */
+      unsigned int reserved7       :  1;
+      unsigned int WSYNCCR5SSS     :  1;  /**< Synchronisation Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register */
+      unsigned int WSYNCCR6SSS     :  1;  /**< Synchronisation Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register */
+      unsigned int WSYNCCR7SSS     :  1;  /**< Synchronisation Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register */
+      unsigned int WSYNCSR7        :  1;  /**< Synchronisation Status of Posted Writes to Status 7 Register */
+      unsigned int WSYNCGPMUX0     :  1;  /**< Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 0 */
+      unsigned int WSYNCGPMUX1     :  1;  /**< Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 1 */
+      unsigned int reserved14      :  2;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SR8_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR8_t__ */
+
+/*@}*/
+
+/** @defgroup SR9 RTC Status 9 (SR9) Register
+ *  RTC Status 9 (SR9) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_SR9_Struct
+ *! \brief  RTC Status 9 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR9_t__
+typedef struct _ADI_RTC_SR9_t {
+  union {
+    struct {
+      unsigned int WPENDSS1LOWDUR :  1;  /**< Pending Status of Posted Writes to SensortStrobe Channel 1 Low Duration Register */
+      unsigned int WPENDSS2LOWDUR :  1;  /**< Pending Status of Posted Writes to SensortStrobe Channel 2 Low Duration Register */
+      unsigned int WPENDSS3LOWDUR :  1;  /**< Pending Status of Posted Writes to SensortStrobe Channel 3 Low Duration Register */
+      unsigned int reserved3       :  1;
+      unsigned int WPENDSS1HIGHDUR :  1;  /**< Pending Status of Posted Writes to SensortStrobe Channel 1 High Duration Register */
+      unsigned int WPENDSS2HIGHDUR :  1;  /**< Pending Status of Posted Writes to SensortStrobe Channel 2 High Duration Register */
+      unsigned int WPENDSS3HIGHDUR :  1;  /**< Pending Status of Posted Writes to SensortStrobe Channel 3 High Duration Register */
+      unsigned int reserved7       :  1;
+      unsigned int WPENDCR5SSS     :  1;  /**< Pending Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register */
+      unsigned int WPENDCR6SSS     :  1;  /**< Pending Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register */
+      unsigned int WPENDCR7SSS     :  1;  /**< Pending Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register */
+      unsigned int WPENDSR7        :  1;  /**< Pending Status of Posted Writes to SR7 */
+      unsigned int WPENDGPMUX0     :  1;  /**< Pending Status of Posted Writes to GPMUX0 */
+      unsigned int WPENDGPMUX1     :  1;  /**< Pending Status of Posted Writes to  GPMUX1 */
+      unsigned int reserved14      :  2;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_SR9_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR9_t__ */
+
+/*@}*/
+
+/** @defgroup GPMUX0 RTC GPIO Pin Mux Control Register 0 (GPMUX0) Register
+ *  RTC GPIO Pin Mux Control Register 0 (GPMUX0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_GPMUX0_Struct
+ *! \brief  RTC GPIO Pin Mux Control Register 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_GPMUX0_t__
+typedef struct _ADI_RTC_GPMUX0_t {
+  union {
+    struct {
+      unsigned int SS1GPIN0SEL :  3;  /**< GPIO Mux Selection for SensorStrobe Channel 1 Input0 */
+      unsigned int SS1GPIN1SEL :  3;  /**< GPIO Mux Selection for SensorStrobe Channel 1 Input 1 */
+      unsigned int SS1GPIN2SEL :  3;  /**< GPIO Mux Selection for SensorStrobe Channel 1 Input 2 */
+      unsigned int SS2GPIN0SEL :  3;  /**< GPIO Mux Selection for SensorStrobe Channel 2 Input 0 */
+      unsigned int SS2GPIN1SEL :  3;  /**< GPIO Mux Selection for SensorStrobe Channel 2 Input 1 */
+      unsigned int reserved15  :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_GPMUX0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_GPMUX0_t__ */
+
+/*@}*/
+
+/** @defgroup GPMUX1 RTC GPIO Pin Mux Control Register 1 (GPMUX1) Register
+ *  RTC GPIO Pin Mux Control Register 1 (GPMUX1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RTC_GPMUX1_Struct
+ *! \brief  RTC GPIO Pin Mux Control Register 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_GPMUX1_t__
+typedef struct _ADI_RTC_GPMUX1_t {
+  union {
+    struct {
+      unsigned int SS2GPIN2SEL :  3;  /**< GPIO Mux Selection for SensorStrobe Channel 2 Input 2 */
+      unsigned int SS3GPIN0SEL :  3;  /**< GPIO Mux Selection for SensorStrobe Channel 3 Input 0 */
+      unsigned int SS3GPIN1SEL :  3;  /**< GPIO Mux Selection for SensorStrobe Channel 3 Input 1 */
+      unsigned int SS3GPIN2SEL :  3;  /**< GPIO Mux Selection for SensorStrobe Channel 3 Input 2 */
+      unsigned int reserved12  :  2;
+      unsigned int SS1DIFFOUT  :  1;  /**< Differential SensorStrobe Out Option for SensorStrobe Channel 1 */
+      unsigned int SS3DIFFOUT  :  1;  /**< Differential SensorStrobe Out Option for SensorStrobe Channel 3 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RTC_GPMUX1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_GPMUX1_t__ */
+
+/*@}*/
+
+/** @defgroup ADIID ADI Identification (ADIID) Register
+ *  ADI Identification (ADIID) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SYS_ADIID_Struct
+ *! \brief  ADI Identification Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SYS_ADIID_t__
+typedef struct _ADI_SYS_ADIID_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Reads a fixed value of 0x4144 to indicate to debuggers that they are connected to an Analog Devices implemented Cortex based part */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SYS_ADIID_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SYS_ADIID_t__ */
+
+/*@}*/
+
+/** @defgroup CHIPID Chip Identifier (CHIPID) Register
+ *  Chip Identifier (CHIPID) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SYS_CHIPID_Struct
+ *! \brief  Chip Identifier Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SYS_CHIPID_t__
+typedef struct _ADI_SYS_CHIPID_t {
+  union {
+    struct {
+      unsigned int REV        :  4;  /**< Silicon revision */
+      unsigned int PARTID     : 12;  /**< Part identifier */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SYS_CHIPID_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SYS_CHIPID_t__ */
+
+/*@}*/
+
+/** @defgroup SWDEN Serial Wire Debug Enable (SWDEN) Register
+ *  Serial Wire Debug Enable (SWDEN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SYS_SWDEN_Struct
+ *! \brief  Serial Wire Debug Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SYS_SWDEN_t__
+typedef struct _ADI_SYS_SWDEN_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< To enable SWD interface */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SYS_SWDEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SYS_SWDEN_t__ */
+
+/*@}*/
+
+/** @defgroup LOAD Load Value (LOAD) Register
+ *  Load Value (LOAD) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_WDT_LOAD_Struct
+ *! \brief  Load Value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_LOAD_t__
+typedef struct _ADI_WDT_LOAD_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Load Value */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_WDT_LOAD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_LOAD_t__ */
+
+/*@}*/
+
+/** @defgroup CCNT Current Count Value (CCNT) Register
+ *  Current Count Value (CCNT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_WDT_CCNT_Struct
+ *! \brief  Current Count Value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_CCNT_t__
+typedef struct _ADI_WDT_CCNT_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Current Count Value */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_WDT_CCNT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_CCNT_t__ */
+
+/*@}*/
+
+/** @defgroup CTL Control (CTL) Register
+ *  Control (CTL) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_WDT_CTL_IRQ
+ *! \brief  Timer Interrupt (IRQ) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  WDT_CTL_RST = 0,  /**< WDT asserts reset when timed out       */
+  WDT_CTL_INT = 1   /**< WDT generates interrupt when timed out */
+} ADI_WDT_CTL_IRQ;
+
+
+/*  =========================================================================
+ *! \enum   ADI_WDT_CTL_PRE
+ *! \brief  Prescaler (PRE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  WDT_CTL_DIV1   = 0,  /**< Source clock/1             */
+  WDT_CTL_DIV16  = 1,  /**< Source clock/16            */
+  WDT_CTL_DIV256 = 2   /**< Source clock/256 (default) */
+} ADI_WDT_CTL_PRE;
+
+
+/*  =========================================================================
+ *! \enum   ADI_WDT_CTL_EN
+ *! \brief  Timer Enable (EN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  WDT_CTL_WDT_DIS = 0,  /**< WDT not enabled */
+  WDT_CTL_WDT_EN  = 1   /**< WDT enabled     */
+} ADI_WDT_CTL_EN;
+
+
+/*  =========================================================================
+ *! \enum   ADI_WDT_CTL_MODE
+ *! \brief  Timer Mode (MODE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  WDT_CTL_FREE_RUN = 0,  /**< Free running mode */
+  WDT_CTL_PERIODIC = 1   /**< Periodic mode     */
+} ADI_WDT_CTL_MODE;
+
+
+/* ==========================================================================
+ *! \struct ADI_WDT_CTL_Struct
+ *! \brief  Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_CTL_t__
+typedef struct _ADI_WDT_CTL_t {
+  union {
+    struct {
+      unsigned int reserved0  :  1;
+      unsigned int IRQ        :  1;  /**< Timer Interrupt */
+      unsigned int PRE        :  2;  /**< Prescaler */
+      unsigned int reserved4  :  1;
+      unsigned int EN         :  1;  /**< Timer Enable */
+      unsigned int MODE       :  1;  /**< Timer Mode */
+      unsigned int SPARE      :  1;  /**< Unused Spare Bit */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_WDT_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup RESTART Clear Interrupt (RESTART) Register
+ *  Clear Interrupt (RESTART) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_WDT_RESTART_Struct
+ *! \brief  Clear Interrupt Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_RESTART_t__
+typedef struct _ADI_WDT_RESTART_t {
+  union {
+    struct {
+      unsigned int CLRWORD    : 16;  /**< Clear Watchdog */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_WDT_RESTART_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_RESTART_t__ */
+
+/*@}*/
+
+/** @defgroup STAT Status (STAT) Register
+ *  Status (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_WDT_STAT_Struct
+ *! \brief  Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_STAT_t__
+typedef struct _ADI_WDT_STAT_t {
+  union {
+    struct {
+      unsigned int IRQ        :  1;  /**< WDT Interrupt */
+      unsigned int CLRIRQ     :  1;  /**< Clear Interrupt Register Write Sync in Progress */
+      unsigned int LOADING    :  1;  /**< Load Register Write Sync in Progress */
+      unsigned int COUNTING   :  1;  /**< Control Register Write Sync in Progress */
+      unsigned int LOCKED     :  1;  /**< Lock Status Bit */
+      unsigned int RSTCTL     :  1;  /**< Reset Control Register Written and Locked */
+      unsigned int reserved6  : 10;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_WDT_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup MCTL Master Control (MCTL) Register
+ *  Master Control (MCTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_MCTL_Struct
+ *! \brief  Master Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MCTL_t__
+typedef struct _ADI_I2C_MCTL_t {
+  union {
+    struct {
+      unsigned int MASEN      :  1;  /**< Master Enable */
+      unsigned int COMPLETE   :  1;  /**< Start Back-off Disable */
+      unsigned int LOOPBACK   :  1;  /**< Internal Loopback Enable */
+      unsigned int STRETCHSCL :  1;  /**< Stretch SCL Enable */
+      unsigned int IENMRX     :  1;  /**< Receive Request Interrupt Enable */
+      unsigned int IENMTX     :  1;  /**< Transmit Request Interrupt Enable */
+      unsigned int IENALOST   :  1;  /**< Arbitration Lost Interrupt Enable */
+      unsigned int IENACK     :  1;  /**< ACK Not Received Interrupt Enable */
+      unsigned int IENCMP     :  1;  /**< Transaction Completed (or Stop Detected) Interrupt Enable */
+      unsigned int MXMITDEC   :  1;  /**< Decrement Master Tx FIFO Status When a Byte Txed */
+      unsigned int MRXDMA     :  1;  /**< Enable Master Rx DMA Request */
+      unsigned int MTXDMA     :  1;  /**< Enable Master Tx DMA Request */
+      unsigned int BUSCLR     :  1;  /**< Bus-Clear Enable */
+      unsigned int STOPBUSCLR :  1;  /**< Prestop Bus Clear */
+      unsigned int reserved14 :  2;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_MCTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MCTL_t__ */
+
+/*@}*/
+
+/** @defgroup MSTAT Master Status (MSTAT) Register
+ *  Master Status (MSTAT) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_I2C_MSTAT_MTXF
+ *! \brief  Master Transmit FIFO Status (MTXF) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  I2C_MSTAT_FIFO_EMPTY = 0,  /**< FIFO Empty.     */
+  I2C_MSTAT_FIFO_1BYTE = 2,  /**< 1 byte in FIFO. */
+  I2C_MSTAT_FIFO_FULL  = 3   /**< FIFO Full.      */
+} ADI_I2C_MSTAT_MTXF;
+
+
+/* ==========================================================================
+ *! \struct ADI_I2C_MSTAT_Struct
+ *! \brief  Master Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MSTAT_t__
+typedef struct _ADI_I2C_MSTAT_t {
+  union {
+    struct {
+      unsigned int MTXF       :  2;  /**< Master Transmit FIFO Status */
+      unsigned int MTXREQ     :  1;  /**< Master Transmit Request/Clear Master Transmit Interrupt */
+      unsigned int MRXREQ     :  1;  /**< Master Receive Request */
+      unsigned int NACKADDR   :  1;  /**< ACK Not Received in Response to an Address */
+      unsigned int ALOST      :  1;  /**< Arbitration Lost */
+      unsigned int MBUSY      :  1;  /**< Master Busy */
+      unsigned int NACKDATA   :  1;  /**< ACK Not Received in Response to Data Write */
+      unsigned int TCOMP      :  1;  /**< Transaction Complete or Stop Detected */
+      unsigned int MRXOVR     :  1;  /**< Master Receive FIFO Overflow */
+      unsigned int LINEBUSY   :  1;  /**< Line is Busy */
+      unsigned int MSTOP      :  1;  /**< STOP Driven by This I2C Master */
+      unsigned int MTXUNDR    :  1;  /**< Master Transmit Underflow */
+      unsigned int SDAFILT    :  1;  /**< State of SDA Line */
+      unsigned int SCLFILT    :  1;  /**< State of SCL Line */
+      unsigned int reserved15 :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_MSTAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MSTAT_t__ */
+
+/*@}*/
+
+/** @defgroup MRX Master Receive Data (MRX) Register
+ *  Master Receive Data (MRX) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_MRX_Struct
+ *! \brief  Master Receive Data Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MRX_t__
+typedef struct _ADI_I2C_MRX_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Master Receive Register */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_MRX_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MRX_t__ */
+
+/*@}*/
+
+/** @defgroup MTX Master Transmit Data (MTX) Register
+ *  Master Transmit Data (MTX) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_MTX_Struct
+ *! \brief  Master Transmit Data Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MTX_t__
+typedef struct _ADI_I2C_MTX_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Master Transmit Register */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_MTX_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MTX_t__ */
+
+/*@}*/
+
+/** @defgroup MRXCNT Master Receive Data Count (MRXCNT) Register
+ *  Master Receive Data Count (MRXCNT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_MRXCNT_Struct
+ *! \brief  Master Receive Data Count Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MRXCNT_t__
+typedef struct _ADI_I2C_MRXCNT_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Receive Count */
+      unsigned int EXTEND     :  1;  /**< Extended Read */
+      unsigned int reserved9  :  7;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_MRXCNT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MRXCNT_t__ */
+
+/*@}*/
+
+/** @defgroup MCRXCNT Master Current Receive Data Count (MCRXCNT) Register
+ *  Master Current Receive Data Count (MCRXCNT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_MCRXCNT_Struct
+ *! \brief  Master Current Receive Data Count Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MCRXCNT_t__
+typedef struct _ADI_I2C_MCRXCNT_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Current Receive Count */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_MCRXCNT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MCRXCNT_t__ */
+
+/*@}*/
+
+/** @defgroup ADDR1 Master Address Byte 1 (ADDR1) Register
+ *  Master Address Byte 1 (ADDR1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_ADDR1_Struct
+ *! \brief  Master Address Byte 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ADDR1_t__
+typedef struct _ADI_I2C_ADDR1_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Address Byte 1 */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_ADDR1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ADDR1_t__ */
+
+/*@}*/
+
+/** @defgroup ADDR2 Master Address Byte 2 (ADDR2) Register
+ *  Master Address Byte 2 (ADDR2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_ADDR2_Struct
+ *! \brief  Master Address Byte 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ADDR2_t__
+typedef struct _ADI_I2C_ADDR2_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Address Byte 2 */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_ADDR2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ADDR2_t__ */
+
+/*@}*/
+
+/** @defgroup BYT Start Byte (BYT) Register
+ *  Start Byte (BYT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_BYT_Struct
+ *! \brief  Start Byte Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_BYT_t__
+typedef struct _ADI_I2C_BYT_t {
+  union {
+    struct {
+      unsigned int SBYTE      :  8;  /**< Start Byte */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_BYT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_BYT_t__ */
+
+/*@}*/
+
+/** @defgroup DIV Serial Clock Period Divisor (DIV) Register
+ *  Serial Clock Period Divisor (DIV) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_DIV_Struct
+ *! \brief  Serial Clock Period Divisor Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_DIV_t__
+typedef struct _ADI_I2C_DIV_t {
+  union {
+    struct {
+      unsigned int LOW        :  8;  /**< Serial Clock Low Time */
+      unsigned int HIGH       :  8;  /**< Serial Clock High Time */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_DIV_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_DIV_t__ */
+
+/*@}*/
+
+/** @defgroup SCTL Slave Control (SCTL) Register
+ *  Slave Control (SCTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_SCTL_Struct
+ *! \brief  Slave Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_SCTL_t__
+typedef struct _ADI_I2C_SCTL_t {
+  union {
+    struct {
+      unsigned int SLVEN      :  1;  /**< Slave Enable */
+      unsigned int ADR10EN    :  1;  /**< Enabled 10-bit Addressing */
+      unsigned int GCEN       :  1;  /**< General Call Enable */
+      unsigned int HGCEN      :  1;  /**< Hardware General Call Enable */
+      unsigned int GCSBCLR    :  1;  /**< General Call Status Bit Clear */
+      unsigned int EARLYTXR   :  1;  /**< Early Transmit Request Mode */
+      unsigned int reserved6  :  1;
+      unsigned int NACK       :  1;  /**< NACK Next Communication */
+      unsigned int IENSTOP    :  1;  /**< Stop Condition Detected Interrupt Enable */
+      unsigned int IENSRX     :  1;  /**< Slave Receive Request Interrupt Enable */
+      unsigned int IENSTX     :  1;  /**< Slave Transmit Request Interrupt Enable */
+      unsigned int STXDEC     :  1;  /**< Decrement Slave Tx FIFO Status When a Byte is Txed */
+      unsigned int IENREPST   :  1;  /**< Repeated Start Interrupt Enable */
+      unsigned int SRXDMA     :  1;  /**< Enable Slave Rx DMA Request */
+      unsigned int STXDMA     :  1;  /**< Enable Slave Tx DMA Request */
+      unsigned int reserved15 :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_SCTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_SCTL_t__ */
+
+/*@}*/
+
+/** @defgroup SSTAT Slave I2C Status/Error/IRQ (SSTAT) Register
+ *  Slave I2C Status/Error/IRQ (SSTAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_SSTAT_Struct
+ *! \brief  Slave I2C Status/Error/IRQ Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_SSTAT_t__
+typedef struct _ADI_I2C_SSTAT_t {
+  union {
+    struct {
+      unsigned int STXFSEREQ  :  1;  /**< Slave Tx FIFO Status or Early Request */
+      unsigned int STXUNDR    :  1;  /**< Slave Transmit FIFO Underflow */
+      unsigned int STXREQ     :  1;  /**< Slave Transmit Request/Slave Transmit Interrupt */
+      unsigned int SRXREQ     :  1;  /**< Slave Receive Request */
+      unsigned int SRXOVR     :  1;  /**< Slave Receive FIFO Overflow */
+      unsigned int NOACK      :  1;  /**< ACK Not Generated by the Slave */
+      unsigned int SBUSY      :  1;  /**< Slave Busy */
+      unsigned int GCINT      :  1;  /**< General Call Interrupt */
+      unsigned int GCID       :  2;  /**< General ID */
+      unsigned int STOP       :  1;  /**< Stop After Start and Matching Address */
+      unsigned int IDMAT      :  2;  /**< Device ID Matched */
+      unsigned int REPSTART   :  1;  /**< Repeated Start and Matching Address */
+      unsigned int START      :  1;  /**< Start and Matching Address */
+      unsigned int reserved15 :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_SSTAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_SSTAT_t__ */
+
+/*@}*/
+
+/** @defgroup SRX Slave Receive (SRX) Register
+ *  Slave Receive (SRX) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_SRX_Struct
+ *! \brief  Slave Receive Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_SRX_t__
+typedef struct _ADI_I2C_SRX_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Slave Receive Register */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_SRX_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_SRX_t__ */
+
+/*@}*/
+
+/** @defgroup STX Slave Transmit (STX) Register
+ *  Slave Transmit (STX) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_STX_Struct
+ *! \brief  Slave Transmit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_STX_t__
+typedef struct _ADI_I2C_STX_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Slave Transmit Register */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_STX_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_STX_t__ */
+
+/*@}*/
+
+/** @defgroup ALT Hardware General Call ID (ALT) Register
+ *  Hardware General Call ID (ALT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_ALT_Struct
+ *! \brief  Hardware General Call ID Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ALT_t__
+typedef struct _ADI_I2C_ALT_t {
+  union {
+    struct {
+      unsigned int ID         :  8;  /**< Slave Alt */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_ALT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ALT_t__ */
+
+/*@}*/
+
+/** @defgroup ID0 First Slave Address Device ID (ID0) Register
+ *  First Slave Address Device ID (ID0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_ID0_Struct
+ *! \brief  First Slave Address Device ID Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ID0_t__
+typedef struct _ADI_I2C_ID0_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Slave Device ID 0 */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_ID0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ID0_t__ */
+
+/*@}*/
+
+/** @defgroup ID1 Second Slave Address Device ID (ID1) Register
+ *  Second Slave Address Device ID (ID1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_ID1_Struct
+ *! \brief  Second Slave Address Device ID Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ID1_t__
+typedef struct _ADI_I2C_ID1_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Slave Device ID 1 */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_ID1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ID1_t__ */
+
+/*@}*/
+
+/** @defgroup ID2 Third Slave Address Device ID (ID2) Register
+ *  Third Slave Address Device ID (ID2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_ID2_Struct
+ *! \brief  Third Slave Address Device ID Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ID2_t__
+typedef struct _ADI_I2C_ID2_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Slave Device ID 2 */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_ID2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ID2_t__ */
+
+/*@}*/
+
+/** @defgroup ID3 Fourth Slave Address Device ID (ID3) Register
+ *  Fourth Slave Address Device ID (ID3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_ID3_Struct
+ *! \brief  Fourth Slave Address Device ID Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ID3_t__
+typedef struct _ADI_I2C_ID3_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Slave Device ID 3 */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_ID3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ID3_t__ */
+
+/*@}*/
+
+/** @defgroup STAT Master and Slave FIFO Status (STAT) Register
+ *  Master and Slave FIFO Status (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_STAT_Struct
+ *! \brief  Master and Slave FIFO Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_STAT_t__
+typedef struct _ADI_I2C_STAT_t {
+  union {
+    struct {
+      unsigned int STXF       :  2;  /**< Slave Transmit FIFO Status */
+      unsigned int SRXF       :  2;  /**< Slave Receive FIFO Status */
+      unsigned int MTXF       :  2;  /**< Master Transmit FIFO Status */
+      unsigned int MRXF       :  2;  /**< Master Receive FIFO Status */
+      unsigned int SFLUSH     :  1;  /**< Flush the Slave Transmit FIFO */
+      unsigned int MFLUSH     :  1;  /**< Flush the Master Transmit FIFO */
+      unsigned int reserved10 :  6;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup SHCTL Shared Control (SHCTL) Register
+ *  Shared Control (SHCTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_SHCTL_Struct
+ *! \brief  Shared Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_SHCTL_t__
+typedef struct _ADI_I2C_SHCTL_t {
+  union {
+    struct {
+      unsigned int RST        :  1;  /**< Reset START STOP Detect Circuit */
+      unsigned int reserved1  : 15;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_SHCTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_SHCTL_t__ */
+
+/*@}*/
+
+/** @defgroup TCTL Timing Control Register (TCTL) Register
+ *  Timing Control Register (TCTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_TCTL_Struct
+ *! \brief  Timing Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_TCTL_t__
+typedef struct _ADI_I2C_TCTL_t {
+  union {
+    struct {
+      unsigned int THDATIN    :  5;  /**< Data in Hold Start */
+      unsigned int reserved5  :  3;
+      unsigned int FILTEROFF  :  1;  /**< Input Filter Control */
+      unsigned int reserved9  :  7;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_TCTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_TCTL_t__ */
+
+/*@}*/
+
+/** @defgroup ASTRETCH_SCL Automatic Stretch SCL (ASTRETCH_SCL) Register
+ *  Automatic Stretch SCL (ASTRETCH_SCL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_I2C_ASTRETCH_SCL_Struct
+ *! \brief  Automatic Stretch SCL Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ASTRETCH_SCL_t__
+typedef struct _ADI_I2C_ASTRETCH_SCL_t {
+  union {
+    struct {
+      unsigned int MST        :  4;  /**< Master Automatic Stretch Mode */
+      unsigned int SLV        :  4;  /**< Slave Automatic Stretch Mode */
+      unsigned int MSTTMO     :  1;  /**< Master Automatic Stretch Timeout */
+      unsigned int SLVTMO     :  1;  /**< Slave Automatic Stretch Timeout */
+      unsigned int reserved10 :  6;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_I2C_ASTRETCH_SCL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ASTRETCH_SCL_t__ */
+
+/*@}*/
+
+/** @defgroup STAT Status (STAT) Register
+ *  Status (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_STAT_Struct
+ *! \brief  Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_STAT_t__
+typedef struct _ADI_SPI_STAT_t {
+  union {
+    struct {
+      unsigned int IRQ        :  1;  /**< SPI Interrupt Status */
+      unsigned int XFRDONE    :  1;  /**< SPI Transfer Completion */
+      unsigned int TXEMPTY    :  1;  /**< SPI Tx FIFO Empty Interrupt */
+      unsigned int TXDONE     :  1;  /**< SPI Tx Done in Read Command Mode */
+      unsigned int TXUNDR     :  1;  /**< SPI Tx FIFO Underflow */
+      unsigned int TXIRQ      :  1;  /**< SPI Tx IRQ */
+      unsigned int RXIRQ      :  1;  /**< SPI Rx IRQ */
+      unsigned int RXOVR      :  1;  /**< SPI Rx FIFO Overflow */
+      unsigned int reserved8  :  3;
+      unsigned int CS         :  1;  /**< CS Status */
+      unsigned int CSERR      :  1;  /**< Detected a CS Error Condition in Slave Mode */
+      unsigned int CSRISE     :  1;  /**< Detected a Rising Edge on CS, in Slave CON Mode */
+      unsigned int CSFALL     :  1;  /**< Detected a Falling Edge on CS, in Slave CON Mode */
+      unsigned int RDY        :  1;  /**< Detected an Edge on Ready Indicator for Flow Control */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup RX Receive (RX) Register
+ *  Receive (RX) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_RX_Struct
+ *! \brief  Receive Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_RX_t__
+typedef struct _ADI_SPI_RX_t {
+  union {
+    struct {
+      unsigned int BYTE1      :  8;  /**< 8-bit Receive Buffer */
+      unsigned int BYTE2      :  8;  /**< 8-bit Receive Buffer, Used Only in DMA Modes */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_RX_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_RX_t__ */
+
+/*@}*/
+
+/** @defgroup TX Transmit (TX) Register
+ *  Transmit (TX) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_TX_Struct
+ *! \brief  Transmit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_TX_t__
+typedef struct _ADI_SPI_TX_t {
+  union {
+    struct {
+      unsigned int BYTE1      :  8;  /**< 8-bit Transmit Buffer */
+      unsigned int BYTE2      :  8;  /**< 8-bit Transmit Buffer, Used Only in DMA Modes */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_TX_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_TX_t__ */
+
+/*@}*/
+
+/** @defgroup DIV SPI Baud Rate Selection (DIV) Register
+ *  SPI Baud Rate Selection (DIV) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_DIV_Struct
+ *! \brief  SPI Baud Rate Selection Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_DIV_t__
+typedef struct _ADI_SPI_DIV_t {
+  union {
+    struct {
+      unsigned int VALUE      :  6;  /**< SPI Clock Divider */
+      unsigned int reserved6  : 10;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_DIV_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_DIV_t__ */
+
+/*@}*/
+
+/** @defgroup CTL SPI Configuration (CTL) Register
+ *  SPI Configuration (CTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_CTL_Struct
+ *! \brief  SPI Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_CTL_t__
+typedef struct _ADI_SPI_CTL_t {
+  union {
+    struct {
+      unsigned int SPIEN      :  1;  /**< SPI Enable */
+      unsigned int MASEN      :  1;  /**< Master Mode Enable */
+      unsigned int CPHA       :  1;  /**< Serial Clock Phase Mode */
+      unsigned int CPOL       :  1;  /**< Serial Clock Polarity */
+      unsigned int WOM        :  1;  /**< SPI Wired-OR Mode */
+      unsigned int LSB        :  1;  /**< LSB First Transfer Enable */
+      unsigned int TIM        :  1;  /**< SPI Transfer and Interrupt Mode */
+      unsigned int ZEN        :  1;  /**< Transmit Zeros Enable */
+      unsigned int RXOF       :  1;  /**< Rx Overflow Overwrite Enable */
+      unsigned int OEN        :  1;  /**< Slave MISO Output Enable */
+      unsigned int LOOPBACK   :  1;  /**< Loopback Enable */
+      unsigned int CON        :  1;  /**< Continuous Transfer Enable */
+      unsigned int RFLUSH     :  1;  /**< SPI Rx FIFO Flush Enable */
+      unsigned int TFLUSH     :  1;  /**< SPI Tx FIFO Flush Enable */
+      unsigned int CSRST      :  1;  /**< Reset Mode for CS Error Bit */
+      unsigned int reserved15 :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup IEN SPI Interrupts Enable (IEN) Register
+ *  SPI Interrupts Enable (IEN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_IEN_Struct
+ *! \brief  SPI Interrupts Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_IEN_t__
+typedef struct _ADI_SPI_IEN_t {
+  union {
+    struct {
+      unsigned int IRQMODE    :  3;  /**< SPI IRQ Mode Bits */
+      unsigned int reserved3  :  5;
+      unsigned int CS         :  1;  /**< Enable Interrupt on Every CS Edge in Slave CON Mode */
+      unsigned int TXUNDR     :  1;  /**< Tx Underflow Interrupt Enable */
+      unsigned int RXOVR      :  1;  /**< Rx Overflow Interrupt Enable */
+      unsigned int RDY        :  1;  /**< Ready Signal Edge Interrupt Enable */
+      unsigned int TXDONE     :  1;  /**< SPI Transmit Done Interrupt Enable */
+      unsigned int XFRDONE    :  1;  /**< SPI Transfer Completion Interrupt Enable */
+      unsigned int TXEMPTY    :  1;  /**< Tx FIFO Empty Interrupt Enable */
+      unsigned int reserved15 :  1;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_IEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_IEN_t__ */
+
+/*@}*/
+
+/** @defgroup CNT Transfer Byte Count (CNT) Register
+ *  Transfer Byte Count (CNT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_CNT_Struct
+ *! \brief  Transfer Byte Count Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_CNT_t__
+typedef struct _ADI_SPI_CNT_t {
+  union {
+    struct {
+      unsigned int VALUE      : 14;  /**< Transfer Byte Count */
+      unsigned int reserved14 :  1;
+      unsigned int FRAMECONT  :  1;  /**< Continue Frame */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_CNT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_CNT_t__ */
+
+/*@}*/
+
+/** @defgroup DMA SPI DMA Enable (DMA) Register
+ *  SPI DMA Enable (DMA) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_DMA_Struct
+ *! \brief  SPI DMA Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_DMA_t__
+typedef struct _ADI_SPI_DMA_t {
+  union {
+    struct {
+      unsigned int EN         :  1;  /**< Enable DMA for Data Transfer */
+      unsigned int TXEN       :  1;  /**< Enable Transmit DMA Request */
+      unsigned int RXEN       :  1;  /**< Enable Receive DMA Request */
+      unsigned int reserved3  : 13;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_DMA_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_DMA_t__ */
+
+/*@}*/
+
+/** @defgroup FIFO_STAT FIFO Status (FIFO_STAT) Register
+ *  FIFO Status (FIFO_STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_FIFO_STAT_Struct
+ *! \brief  FIFO Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_FIFO_STAT_t__
+typedef struct _ADI_SPI_FIFO_STAT_t {
+  union {
+    struct {
+      unsigned int TX         :  4;  /**< SPI Tx FIFO Status */
+      unsigned int reserved4  :  4;
+      unsigned int RX         :  4;  /**< SPI Rx FIFO Dtatus */
+      unsigned int reserved12 :  4;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_FIFO_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_FIFO_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup RD_CTL Read Control (RD_CTL) Register
+ *  Read Control (RD_CTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_RD_CTL_Struct
+ *! \brief  Read Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_RD_CTL_t__
+typedef struct _ADI_SPI_RD_CTL_t {
+  union {
+    struct {
+      unsigned int CMDEN      :  1;  /**< Read Command Enable */
+      unsigned int OVERLAP    :  1;  /**< Tx/Rx Overlap Mode */
+      unsigned int TXBYTES    :  4;  /**< Transmit Byte Count - 1 (Read Command) */
+      unsigned int reserved6  :  2;
+      unsigned int THREEPIN   :  1;  /**< Three Pin SPI Mode */
+      unsigned int reserved9  :  7;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_RD_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_RD_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup FLOW_CTL Flow Control (FLOW_CTL) Register
+ *  Flow Control (FLOW_CTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_FLOW_CTL_Struct
+ *! \brief  Flow Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_FLOW_CTL_t__
+typedef struct _ADI_SPI_FLOW_CTL_t {
+  union {
+    struct {
+      unsigned int MODE       :  2;  /**< Flow Control Mode */
+      unsigned int reserved2  :  2;
+      unsigned int RDYPOL     :  1;  /**< Polarity of RDY/MISO Line */
+      unsigned int reserved5  :  1;
+      unsigned int RDBURSTSZ  : 10;  /**< Read Data Burst Size - 1 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_FLOW_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_FLOW_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup WAIT_TMR Wait Timer for Flow Control (WAIT_TMR) Register
+ *  Wait Timer for Flow Control (WAIT_TMR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_WAIT_TMR_Struct
+ *! \brief  Wait Timer for Flow Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_WAIT_TMR_t__
+typedef struct _ADI_SPI_WAIT_TMR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Wait Timer */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_WAIT_TMR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_WAIT_TMR_t__ */
+
+/*@}*/
+
+/** @defgroup CS_CTL Chip Select Control for Multi-slave Connections (CS_CTL) Register
+ *  Chip Select Control for Multi-slave Connections (CS_CTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_CS_CTL_Struct
+ *! \brief  Chip Select Control for Multi-slave Connections Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_CS_CTL_t__
+typedef struct _ADI_SPI_CS_CTL_t {
+  union {
+    struct {
+      unsigned int SEL        :  4;  /**< Chip Select Control */
+      unsigned int reserved4  : 12;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_CS_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_CS_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup CS_OVERRIDE Chip Select Override (CS_OVERRIDE) Register
+ *  Chip Select Override (CS_OVERRIDE) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_CS_OVERRIDE_Struct
+ *! \brief  Chip Select Override Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_CS_OVERRIDE_t__
+typedef struct _ADI_SPI_CS_OVERRIDE_t {
+  union {
+    struct {
+      unsigned int CTL        :  2;  /**< CS Override Control */
+      unsigned int reserved2  : 14;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_SPI_CS_OVERRIDE_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_CS_OVERRIDE_t__ */
+
+/*@}*/
+
+/** @defgroup RX Receive Buffer Register (RX) Register
+ *  Receive Buffer Register (RX) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_RX_Struct
+ *! \brief  Receive Buffer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_RX_t__
+typedef struct _ADI_UART_RX_t {
+  union {
+    struct {
+      unsigned int RBR        :  8;  /**< Receive Buffer Register */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_RX_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_RX_t__ */
+
+/*@}*/
+
+/** @defgroup TX Transmit Holding Register (TX) Register
+ *  Transmit Holding Register (TX) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_TX_Struct
+ *! \brief  Transmit Holding Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_TX_t__
+typedef struct _ADI_UART_TX_t {
+  union {
+    struct {
+      unsigned int THR        :  8;  /**< Transmit Holding Register */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_TX_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_TX_t__ */
+
+/*@}*/
+
+/** @defgroup IEN Interrupt Enable (IEN) Register
+ *  Interrupt Enable (IEN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_IEN_Struct
+ *! \brief  Interrupt Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_IEN_t__
+typedef struct _ADI_UART_IEN_t {
+  union {
+    struct {
+      unsigned int ERBFI      :  1;  /**< Receive Buffer Full Interrupt */
+      unsigned int ETBEI      :  1;  /**< Transmit Buffer Empty Interrupt */
+      unsigned int ELSI       :  1;  /**< Rx Status Interrupt */
+      unsigned int EDSSI      :  1;  /**< Modem Status Interrupt */
+      unsigned int EDMAT      :  1;  /**< DMA Requests in Transmit Mode */
+      unsigned int EDMAR      :  1;  /**< DMA Requests in Receive Mode */
+      unsigned int reserved6  : 10;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_IEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_IEN_t__ */
+
+/*@}*/
+
+/** @defgroup IIR Interrupt ID (IIR) Register
+ *  Interrupt ID (IIR) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_UART_IIR_STAT
+ *! \brief  Interrupt Status (STAT) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  UART_IIR_STAT_EDSSI = 0,  /**< Modem status interrupt (Read MSR register to clear)                                  */
+  UART_IIR_STAT_ETBEI = 1,  /**< Transmit buffer empty interrupt (Write to Tx register or read IIR register to clear) */
+  UART_IIR_STAT_ERBFI = 2,  /**< Receive buffer full interrupt (Read Rx register to clear)                            */
+  UART_IIR_STAT_RLSI  = 3,  /**< Receive line status interrupt (Read LSR register to clear)                           */
+  UART_IIR_STAT_RFTOI = 6   /**< Receive FIFO time-out interrupt (Read Rx register to clear)                          */
+} ADI_UART_IIR_STAT;
+
+
+/* ==========================================================================
+ *! \struct ADI_UART_IIR_Struct
+ *! \brief  Interrupt ID Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_IIR_t__
+typedef struct _ADI_UART_IIR_t {
+  union {
+    struct {
+      unsigned int NIRQ       :  1;  /**< Interrupt Flag */
+      unsigned int STAT       :  3;  /**< Interrupt Status */
+      unsigned int reserved4  :  2;
+      unsigned int FEND       :  2;  /**< FIFO Enabled */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_IIR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_IIR_t__ */
+
+/*@}*/
+
+/** @defgroup LCR Line Control (LCR) Register
+ *  Line Control (LCR) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_UART_LCR_SP
+ *! \brief  Stick Parity (SP) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  UART_LCR_PAR_NOTFORCED = 0,  /**< Parity will not be forced based on Parity Select and Parity Enable bits. */
+  UART_LCR_PAR_FORCED    = 1   /**< Parity forced based on Parity Select and Parity Enable bits.             */
+} ADI_UART_LCR_SP;
+
+
+/* ==========================================================================
+ *! \struct ADI_UART_LCR_Struct
+ *! \brief  Line Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_LCR_t__
+typedef struct _ADI_UART_LCR_t {
+  union {
+    struct {
+      unsigned int WLS        :  2;  /**< Word Length Select */
+      unsigned int STOP       :  1;  /**< Stop Bit */
+      unsigned int PEN        :  1;  /**< Parity Enable */
+      unsigned int EPS        :  1;  /**< Parity Select */
+      unsigned int SP         :  1;  /**< Stick Parity */
+      unsigned int BRK        :  1;  /**< Set Break */
+      unsigned int reserved7  :  9;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_LCR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_LCR_t__ */
+
+/*@}*/
+
+/** @defgroup MCR Modem Control (MCR) Register
+ *  Modem Control (MCR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_MCR_Struct
+ *! \brief  Modem Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_MCR_t__
+typedef struct _ADI_UART_MCR_t {
+  union {
+    struct {
+      unsigned int DTR        :  1;  /**< Data Terminal Ready */
+      unsigned int RTS        :  1;  /**< Request to Send */
+      unsigned int OUT1       :  1;  /**< Output 1 */
+      unsigned int OUT2       :  1;  /**< Output 2 */
+      unsigned int LOOPBACK   :  1;  /**< Loopback Mode */
+      unsigned int reserved5  : 11;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_MCR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_MCR_t__ */
+
+/*@}*/
+
+/** @defgroup LSR Line Status (LSR) Register
+ *  Line Status (LSR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_LSR_Struct
+ *! \brief  Line Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_LSR_t__
+typedef struct _ADI_UART_LSR_t {
+  union {
+    struct {
+      unsigned int DR         :  1;  /**< Data Ready */
+      unsigned int OE         :  1;  /**< Overrun Error */
+      unsigned int PE         :  1;  /**< Parity Error */
+      unsigned int FE         :  1;  /**< Framing Error */
+      unsigned int BI         :  1;  /**< Break Indicator */
+      unsigned int THRE       :  1;  /**< Transmit Register Empty */
+      unsigned int TEMT       :  1;  /**< Transmit and Shift Register Empty Status */
+      unsigned int FIFOERR    :  1;  /**< Rx FIFO Parity Error/Frame Error/Break Indication */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_LSR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_LSR_t__ */
+
+/*@}*/
+
+/** @defgroup MSR Modem Status (MSR) Register
+ *  Modem Status (MSR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_MSR_Struct
+ *! \brief  Modem Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_MSR_t__
+typedef struct _ADI_UART_MSR_t {
+  union {
+    struct {
+      unsigned int DCTS       :  1;  /**< Delta CTS */
+      unsigned int DDSR       :  1;  /**< Delta DSR */
+      unsigned int TERI       :  1;  /**< Trailing Edge RI */
+      unsigned int DDCD       :  1;  /**< Delta DCD */
+      unsigned int CTS        :  1;  /**< Clear to Send */
+      unsigned int DSR        :  1;  /**< Data Set Ready */
+      unsigned int RI         :  1;  /**< Ring Indicator */
+      unsigned int DCD        :  1;  /**< Data Carrier Detect */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_MSR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_MSR_t__ */
+
+/*@}*/
+
+/** @defgroup SCR Scratch Buffer (SCR) Register
+ *  Scratch Buffer (SCR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_SCR_Struct
+ *! \brief  Scratch Buffer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_SCR_t__
+typedef struct _ADI_UART_SCR_t {
+  union {
+    struct {
+      unsigned int SCR        :  8;  /**< Scratch */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_SCR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_SCR_t__ */
+
+/*@}*/
+
+/** @defgroup FCR FIFO Control (FCR) Register
+ *  FIFO Control (FCR) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_UART_FCR_FDMAMD
+ *! \brief  FIFO DMA Mode (FDMAMD) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  UART_FCR_MODE0 = 0,  /**< In DMA mode 0, RX DMA request will be asserted whenever there's data in RBR or RX FIFO and de-assert whenever RBR or RX FIFO is empty; TX DMA request will be asserted whenever THR or TX FIFO is empty and de-assert whenever data written to.                              */
+  UART_FCR_MODE1 = 1   /**< in DMA mode 1, RX DMA request will be asserted whenever RX FIFO trig level or time out reached and de-assert thereafter when RX FIFO is empty; TX DMA request will be asserted whenever TX FIFO is empty and de-assert thereafter when TX FIFO is completely filled up full. */
+} ADI_UART_FCR_FDMAMD;
+
+
+/* ==========================================================================
+ *! \struct ADI_UART_FCR_Struct
+ *! \brief  FIFO Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_FCR_t__
+typedef struct _ADI_UART_FCR_t {
+  union {
+    struct {
+      unsigned int FIFOEN     :  1;  /**< FIFO Enable as to Work in 16550 Mode */
+      unsigned int RFCLR      :  1;  /**< Clear Rx FIFO */
+      unsigned int TFCLR      :  1;  /**< Clear Tx FIFO */
+      unsigned int FDMAMD     :  1;  /**< FIFO DMA Mode */
+      unsigned int reserved4  :  2;
+      unsigned int RFTRIG     :  2;  /**< Rx FIFO Trigger Level */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_FCR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_FCR_t__ */
+
+/*@}*/
+
+/** @defgroup FBR Fractional Baud Rate (FBR) Register
+ *  Fractional Baud Rate (FBR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_FBR_Struct
+ *! \brief  Fractional Baud Rate Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_FBR_t__
+typedef struct _ADI_UART_FBR_t {
+  union {
+    struct {
+      unsigned int DIVN       : 11;  /**< Fractional Baud Rate N Divide Bits 0 to 2047 */
+      unsigned int DIVM       :  2;  /**< Fractional Baud Rate M Divide Bits 1 to 3 */
+      unsigned int reserved13 :  2;
+      unsigned int FBEN       :  1;  /**< Fractional Baud Rate Generator Enable */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_FBR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_FBR_t__ */
+
+/*@}*/
+
+/** @defgroup DIV Baud Rate Divider (DIV) Register
+ *  Baud Rate Divider (DIV) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_DIV_Struct
+ *! \brief  Baud Rate Divider Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_DIV_t__
+typedef struct _ADI_UART_DIV_t {
+  union {
+    struct {
+      unsigned int DIV        : 16;  /**< Baud Rate Divider */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_DIV_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_DIV_t__ */
+
+/*@}*/
+
+/** @defgroup LCR2 Second Line Control (LCR2) Register
+ *  Second Line Control (LCR2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_LCR2_Struct
+ *! \brief  Second Line Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_LCR2_t__
+typedef struct _ADI_UART_LCR2_t {
+  union {
+    struct {
+      unsigned int OSR        :  2;  /**< Over Sample Rate */
+      unsigned int reserved2  : 14;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_LCR2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_LCR2_t__ */
+
+/*@}*/
+
+/** @defgroup CTL UART Control Register (CTL) Register
+ *  UART Control Register (CTL) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_UART_CTL_RXINV
+ *! \brief  Invert Receiver Line (RXINV) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  UART_CTL_NOTINV_RX = 0,  /**< Don't invert receiver line (idling high). */
+  UART_CTL_INV_RX    = 1   /**< Invert receiver line (idling low).        */
+} ADI_UART_CTL_RXINV;
+
+
+/* ==========================================================================
+ *! \struct ADI_UART_CTL_Struct
+ *! \brief  UART Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_CTL_t__
+typedef struct _ADI_UART_CTL_t {
+  union {
+    struct {
+      unsigned int reserved0  :  1;
+      unsigned int FORCECLK   :  1;  /**< Force UCLK on */
+      unsigned int reserved2  :  2;
+      unsigned int RXINV      :  1;  /**< Invert Receiver Line */
+      unsigned int reserved5  :  3;
+      unsigned int REV        :  8;  /**< UART Revision ID */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup RFC RX FIFO Byte Count (RFC) Register
+ *  RX FIFO Byte Count (RFC) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_RFC_Struct
+ *! \brief  RX FIFO Byte Count Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_RFC_t__
+typedef struct _ADI_UART_RFC_t {
+  union {
+    struct {
+      unsigned int RFC        :  5;  /**< Current Rx FIFO Data Bytes */
+      unsigned int reserved5  : 11;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_RFC_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_RFC_t__ */
+
+/*@}*/
+
+/** @defgroup TFC TX FIFO Byte Count (TFC) Register
+ *  TX FIFO Byte Count (TFC) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_TFC_Struct
+ *! \brief  TX FIFO Byte Count Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_TFC_t__
+typedef struct _ADI_UART_TFC_t {
+  union {
+    struct {
+      unsigned int TFC        :  5;  /**< Current Tx FIFO Data Bytes */
+      unsigned int reserved5  : 11;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_TFC_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_TFC_t__ */
+
+/*@}*/
+
+/** @defgroup RSC RS485 Half-duplex Control (RSC) Register
+ *  RS485 Half-duplex Control (RSC) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_RSC_Struct
+ *! \brief  RS485 Half-duplex Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_RSC_t__
+typedef struct _ADI_UART_RSC_t {
+  union {
+    struct {
+      unsigned int OENP       :  1;  /**< SOUT_EN Polarity */
+      unsigned int OENSP      :  1;  /**< SOUT_EN De-assert Before Full Stop Bit(s) */
+      unsigned int DISRX      :  1;  /**< Disable Rx When Transmitting */
+      unsigned int DISTX      :  1;  /**< Hold off Tx When Receiving */
+      unsigned int reserved4  : 12;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_RSC_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_RSC_t__ */
+
+/*@}*/
+
+/** @defgroup ACR Auto Baud Control (ACR) Register
+ *  Auto Baud Control (ACR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_ACR_Struct
+ *! \brief  Auto Baud Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_ACR_t__
+typedef struct _ADI_UART_ACR_t {
+  union {
+    struct {
+      unsigned int ABE        :  1;  /**< Auto Baud Enable */
+      unsigned int DNIEN      :  1;  /**< Enable Done Interrupt */
+      unsigned int TOIEN      :  1;  /**< Enable Time-out Interrupt */
+      unsigned int reserved3  :  1;
+      unsigned int SEC        :  3;  /**< Starting Edge Count */
+      unsigned int reserved7  :  1;
+      unsigned int EEC        :  4;  /**< Ending Edge Count */
+      unsigned int reserved12 :  4;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_ACR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_ACR_t__ */
+
+/*@}*/
+
+/** @defgroup ASRL Auto Baud Status (Low) (ASRL) Register
+ *  Auto Baud Status (Low) (ASRL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_ASRL_Struct
+ *! \brief  Auto Baud Status (Low) Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_ASRL_t__
+typedef struct _ADI_UART_ASRL_t {
+  union {
+    struct {
+      unsigned int DONE       :  1;  /**< Auto Baud Done Successfully */
+      unsigned int BRKTO      :  1;  /**< Timed Out Due to Long Time Break Condition */
+      unsigned int NSETO      :  1;  /**< Timed Out Due to No Valid Start Edge Found */
+      unsigned int NEETO      :  1;  /**< Timed Out Due to No Valid Ending Edge Found */
+      unsigned int CNT        : 12;  /**< CNT[11:0] Auto Baud Counter Value */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_ASRL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_ASRL_t__ */
+
+/*@}*/
+
+/** @defgroup ASRH Auto Baud Status (High) (ASRH) Register
+ *  Auto Baud Status (High) (ASRH) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_UART_ASRH_Struct
+ *! \brief  Auto Baud Status (High) Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_ASRH_t__
+typedef struct _ADI_UART_ASRH_t {
+  union {
+    struct {
+      unsigned int CNT        :  8;  /**< CNT[19:12] Auto Baud Counter Value */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_UART_ASRH_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_ASRH_t__ */
+
+/*@}*/
+
+/** @defgroup CFG Beeper Configuration (CFG) Register
+ *  Beeper Configuration (CFG) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_BEEP_CFG_Struct
+ *! \brief  Beeper Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_CFG_t__
+typedef struct _ADI_BEEP_CFG_t {
+  union {
+    struct {
+      unsigned int SEQREPEAT  :  8;  /**< Beeper Sequence Repeat Value */
+      unsigned int EN         :  1;  /**< Beeper Enable */
+      unsigned int reserved9  :  1;
+      unsigned int ASTARTIRQ  :  1;  /**< Tone A Start IRQ */
+      unsigned int AENDIRQ    :  1;  /**< Tone A End IRQ */
+      unsigned int BSTARTIRQ  :  1;  /**< Tone B Start IRQ */
+      unsigned int BENDIRQ    :  1;  /**< Tone B End IRQ */
+      unsigned int SEQNEARENDIRQ :  1;  /**< Sequence 1 Cycle from End IRQ */
+      unsigned int SEQATENDIRQ   :  1;  /**< Sequence End IRQ */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_BEEP_CFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_CFG_t__ */
+
+/*@}*/
+
+/** @defgroup STAT Beeper Status (STAT) Register
+ *  Beeper Status (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_BEEP_STAT_Struct
+ *! \brief  Beeper Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_STAT_t__
+typedef struct _ADI_BEEP_STAT_t {
+  union {
+    struct {
+      unsigned int SEQREMAIN  :  8;  /**< Remaining Tone-pair Iterations to Play in Sequence Mode */
+      unsigned int BUSY       :  1;  /**< Beeper is Busy */
+      unsigned int reserved9  :  1;
+      unsigned int ASTARTED   :  1;  /**< Tone A Has Started */
+      unsigned int AENDED     :  1;  /**< Tone A Has Ended */
+      unsigned int BSTARTED   :  1;  /**< Tone B Has Started */
+      unsigned int BENDED     :  1;  /**< Tone B Has Ended */
+      unsigned int SEQNEAREND :  1;  /**< Sequencer Last Tone-pair Has Started */
+      unsigned int SEQENDED   :  1;  /**< Sequencer Has Ended */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_BEEP_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup TONEA Tone A Data (TONEA) Register
+ *  Tone A Data (TONEA) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_BEEP_TONEA_Struct
+ *! \brief  Tone A Data Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_TONEA_t__
+typedef struct _ADI_BEEP_TONEA_t {
+  union {
+    struct {
+      unsigned int DUR        :  8;  /**< Tone Duration */
+      unsigned int FREQ       :  7;  /**< Tone Frequency */
+      unsigned int DIS        :  1;  /**< Output Disable */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_BEEP_TONEA_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_TONEA_t__ */
+
+/*@}*/
+
+/** @defgroup TONEB Tone B Data (TONEB) Register
+ *  Tone B Data (TONEB) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_BEEP_TONEB_Struct
+ *! \brief  Tone B Data Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_TONEB_t__
+typedef struct _ADI_BEEP_TONEB_t {
+  union {
+    struct {
+      unsigned int DUR        :  8;  /**< Tone Duration */
+      unsigned int FREQ       :  7;  /**< Tone Frequency */
+      unsigned int DIS        :  1;  /**< Output Disable */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_BEEP_TONEB_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_TONEB_t__ */
+
+/*@}*/
+
+/** @defgroup CFG ADC Configuration (CFG) Register
+ *  ADC Configuration (CFG) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_ADC_CFG_VREFSEL
+ *! \brief  To select Vref as 1.25 V or 2.5 V (VREFSEL) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  ADC_CFG_V_2P5  = 0,  /**< Vref = 2.5 V  */
+  ADC_CFG_V_1P25 = 1   /**< Vref = 1.25 V */
+} ADI_ADC_CFG_VREFSEL;
+
+
+/*  =========================================================================
+ *! \enum   ADI_ADC_CFG_REFBUFEN
+ *! \brief  To enable internal reference buffer (REFBUFEN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  ADC_CFG_EXT_REF = 0,  /**< External reference is used  */
+  ADC_CFG_BUF_REF = 1   /**< Reference buffer is enabled */
+} ADI_ADC_CFG_REFBUFEN;
+
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CFG_Struct
+ *! \brief  ADC Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CFG_t__
+typedef struct _ADI_ADC_CFG_t {
+  union {
+    struct {
+      unsigned int PWRUP      :  1;  /**< Powering up ADC */
+      unsigned int VREFSEL    :  1;  /**< To select Vref as 1.25 V or 2.5 V */
+      unsigned int REFBUFEN   :  1;  /**< To enable internal reference buffer */
+      unsigned int VREFVBAT   :  1;  /**< VRef VBAT */
+      unsigned int EN         :  1;  /**< To enable ADC subsystem */
+      unsigned int STARTCAL   :  1;  /**< To start a new offset calibration cycle */
+      unsigned int RST        :  1;  /**< Resets internal buffers and registers when high */
+      unsigned int SINKEN     :  1;  /**< To enable additional 50 uA sink current capability @1.25 V, 100 uA current capability @2.5 V */
+      unsigned int TMPEN      :  1;  /**< To power up temperature sensor */
+      unsigned int FAST_DISCH :  1;  /**< For fast switchover of Vref from 2.5 V to 1.25 V */
+      unsigned int VREFVBAT_DEL :  1;  /**< Set to 1 after minimum delay of 700 us from VREFBAT field being set to 1 */
+      unsigned int reserved11   :  5;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CFG_t__ */
+
+/*@}*/
+
+/** @defgroup PWRUP ADC Power-up Time (PWRUP) Register
+ *  ADC Power-up Time (PWRUP) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_PWRUP_Struct
+ *! \brief  ADC Power-up Time Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_PWRUP_t__
+typedef struct _ADI_ADC_PWRUP_t {
+  union {
+    struct {
+      unsigned int WAIT       : 11;  /**< Program this count to generate 20us wait time with respect to the PCLK frequency */
+      unsigned int reserved11 :  5;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_PWRUP_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_PWRUP_t__ */
+
+/*@}*/
+
+/** @defgroup CAL_WORD Calibration Word (CAL_WORD) Register
+ *  Calibration Word (CAL_WORD) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CAL_WORD_Struct
+ *! \brief  Calibration Word Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CAL_WORD_t__
+typedef struct _ADI_ADC_CAL_WORD_t {
+  union {
+    struct {
+      unsigned int VALUE      :  7;  /**< Offset calibration word */
+      unsigned int reserved7  :  9;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CAL_WORD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CAL_WORD_t__ */
+
+/*@}*/
+
+/** @defgroup CNV_CFG ADC Conversion Configuration (CNV_CFG) Register
+ *  ADC Conversion Configuration (CNV_CFG) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CNV_CFG_Struct
+ *! \brief  ADC Conversion Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CNV_CFG_t__
+typedef struct _ADI_ADC_CNV_CFG_t {
+  union {
+    struct {
+      unsigned int SEL        :  8;  /**< To select channel(s) to convert */
+      unsigned int BAT        :  1;  /**< To enable battery monitoring */
+      unsigned int TMP        :  1;  /**< To select temperature measurement 1 */
+      unsigned int TMP2       :  1;  /**< To select temperature measurement 2 */
+      unsigned int reserved11 :  1;
+      unsigned int AUTOMODE   :  1;  /**< To enable auto mode */
+      unsigned int DMAEN      :  1;  /**< To enable DMA channel */
+      unsigned int SINGLE     :  1;  /**< Set to start single conversion */
+      unsigned int MULTI      :  1;  /**< Set to start multiple conversions */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CNV_CFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CNV_CFG_t__ */
+
+/*@}*/
+
+/** @defgroup CNV_TIME ADC Conversion Time (CNV_TIME) Register
+ *  ADC Conversion Time (CNV_TIME) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CNV_TIME_Struct
+ *! \brief  ADC Conversion Time Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CNV_TIME_t__
+typedef struct _ADI_ADC_CNV_TIME_t {
+  union {
+    struct {
+      unsigned int SAMPTIME   :  8;  /**< Number of clock cycles (ACLK) required for sampling */
+      unsigned int DLY        :  8;  /**< Delay between two consecutive conversions in terms of number of ACLK cycles */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CNV_TIME_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CNV_TIME_t__ */
+
+/*@}*/
+
+/** @defgroup AVG_CFG Averaging Configuration (AVG_CFG) Register
+ *  Averaging Configuration (AVG_CFG) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_AVG_CFG_Struct
+ *! \brief  Averaging Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_AVG_CFG_t__
+typedef struct _ADI_ADC_AVG_CFG_t {
+  union {
+    struct {
+      unsigned int FACTOR     :  8;  /**< Program averaging factor for averaging enabled channels (1-256) */
+      unsigned int reserved8  :  6;
+      unsigned int OS         :  1;  /**< Enable oversampling */
+      unsigned int EN         :  1;  /**< To enable averaging on Channels enabled in enable register */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_AVG_CFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_AVG_CFG_t__ */
+
+/*@}*/
+
+/** @defgroup IRQ_EN Interrupt Enable (IRQ_EN) Register
+ *  Interrupt Enable (IRQ_EN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_IRQ_EN_Struct
+ *! \brief  Interrupt Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_IRQ_EN_t__
+typedef struct _ADI_ADC_IRQ_EN_t {
+  union {
+    struct {
+      unsigned int CNVDONE    :  1;  /**< Set it to enable interrupt after conversion is done */
+      unsigned int reserved1  :  9;
+      unsigned int CALDONE    :  1;  /**< Set it to enable interrupt for calibration done */
+      unsigned int OVF        :  1;  /**< Set to enable interrupt in case of overflow */
+      unsigned int ALERT      :  1;  /**< Set to enable interrupt on crossing lower or higher limit */
+      unsigned int RDY        :  1;  /**< Set to enable interrupt when ADC is ready to convert */
+      unsigned int reserved14 :  2;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_IRQ_EN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_IRQ_EN_t__ */
+
+/*@}*/
+
+/** @defgroup STAT ADC Status (STAT) Register
+ *  ADC Status (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_STAT_Struct
+ *! \brief  ADC Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_STAT_t__
+typedef struct _ADI_ADC_STAT_t {
+  union {
+    struct {
+      unsigned int DONE0      :  1;  /**< Indicates conversion done on Channel 0 */
+      unsigned int DONE1      :  1;  /**< Indicates conversion done on Channel 1 */
+      unsigned int DONE2      :  1;  /**< Indicates conversion done on Channel 2 */
+      unsigned int DONE3      :  1;  /**< Indicates conversion done on Channel 3 */
+      unsigned int DONE4      :  1;  /**< Indicates conversion done on Channel 4 */
+      unsigned int DONE5      :  1;  /**< Indicates conversion done on Channel 5 */
+      unsigned int DONE6      :  1;  /**< Indicates conversion done on Channel 6 */
+      unsigned int DONE7      :  1;  /**< Indicates conversion done on Channel 7 */
+      unsigned int BATDONE    :  1;  /**< Indicates conversion done for battery monitoring */
+      unsigned int TMPDONE    :  1;  /**< Indicates conversion is done for temperature sensing */
+      unsigned int TMP2DONE   :  1;  /**< Indicates conversion is done for temperature sensing 2 */
+      unsigned int reserved11 :  3;
+      unsigned int CALDONE    :  1;  /**< Indicates calibration is done */
+      unsigned int RDY        :  1;  /**< Indicates ADC is ready to start converting, when using external reference buffer */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup OVF Overflow of Output Registers (OVF) Register
+ *  Overflow of Output Registers (OVF) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_OVF_Struct
+ *! \brief  Overflow of Output Registers Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_OVF_t__
+typedef struct _ADI_ADC_OVF_t {
+  union {
+    struct {
+      unsigned int CH0        :  1;  /**< Indicates overflow in channel 0 output register */
+      unsigned int CH1        :  1;  /**< Indicates overflow in channel 1 output register */
+      unsigned int CH2        :  1;  /**< Indicates overflow in channel 2 output register */
+      unsigned int CH3        :  1;  /**< Indicates overflow in channel 3 output register */
+      unsigned int CH4        :  1;  /**< Indicates overflow in channel 4 output register */
+      unsigned int CH5        :  1;  /**< Indicates overflow in channel 5 output register */
+      unsigned int CH6        :  1;  /**< Indicates overflow in channel 6 output register */
+      unsigned int CH7        :  1;  /**< Indicates overflow in channel 7 output register */
+      unsigned int BAT        :  1;  /**< Indicates overflow in battery monitoring output register */
+      unsigned int TMP        :  1;  /**< Indicates overflow in temperature output register */
+      unsigned int TMP2       :  1;  /**< Indicates overflow in temperature 2 output register */
+      unsigned int reserved11 :  5;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_OVF_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_OVF_t__ */
+
+/*@}*/
+
+/** @defgroup ALERT Alert Indication (ALERT) Register
+ *  Alert Indication (ALERT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_ALERT_Struct
+ *! \brief  Alert Indication Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_ALERT_t__
+typedef struct _ADI_ADC_ALERT_t {
+  union {
+    struct {
+      unsigned int HI0        :  1;  /**< Channel 0 High alert status */
+      unsigned int LO0        :  1;  /**< Channel 0 Low alert status */
+      unsigned int HI1        :  1;  /**< Channel 1 High alert status */
+      unsigned int LO1        :  1;  /**< Channel 1 Low alert status */
+      unsigned int HI2        :  1;  /**< Channel 2 High alert status */
+      unsigned int LO2        :  1;  /**< Channel 2 Low alert status */
+      unsigned int HI3        :  1;  /**< Channel 3 High alert status */
+      unsigned int LO3        :  1;  /**< Channel 3 Low alert status */
+      unsigned int reserved8  :  8;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_ALERT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_ALERT_t__ */
+
+/*@}*/
+
+/** @defgroup CH0_OUT Conversion Result Channel 0 (CH0_OUT) Register
+ *  Conversion Result Channel 0 (CH0_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CH0_OUT_Struct
+ *! \brief  Conversion Result Channel 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH0_OUT_t__
+typedef struct _ADI_ADC_CH0_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion result of channel 0 is stored here */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CH0_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH0_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup CH1_OUT Conversion Result Channel 1 (CH1_OUT) Register
+ *  Conversion Result Channel 1 (CH1_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CH1_OUT_Struct
+ *! \brief  Conversion Result Channel 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH1_OUT_t__
+typedef struct _ADI_ADC_CH1_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion result of channel 1 is stored here */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CH1_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH1_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup CH2_OUT Conversion Result Channel 2 (CH2_OUT) Register
+ *  Conversion Result Channel 2 (CH2_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CH2_OUT_Struct
+ *! \brief  Conversion Result Channel 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH2_OUT_t__
+typedef struct _ADI_ADC_CH2_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion result of channel 2 is stored here */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CH2_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH2_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup CH3_OUT Conversion Result Channel 3 (CH3_OUT) Register
+ *  Conversion Result Channel 3 (CH3_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CH3_OUT_Struct
+ *! \brief  Conversion Result Channel 3 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH3_OUT_t__
+typedef struct _ADI_ADC_CH3_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion result of channel 3 is stored here */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CH3_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH3_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup CH4_OUT Conversion Result Channel 4 (CH4_OUT) Register
+ *  Conversion Result Channel 4 (CH4_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CH4_OUT_Struct
+ *! \brief  Conversion Result Channel 4 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH4_OUT_t__
+typedef struct _ADI_ADC_CH4_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion result of channel 4 is stored here */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CH4_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH4_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup CH5_OUT Conversion Result Channel 5 (CH5_OUT) Register
+ *  Conversion Result Channel 5 (CH5_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CH5_OUT_Struct
+ *! \brief  Conversion Result Channel 5 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH5_OUT_t__
+typedef struct _ADI_ADC_CH5_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion result of channel 5 is stored here */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CH5_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH5_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup CH6_OUT Conversion Result Channel 6 (CH6_OUT) Register
+ *  Conversion Result Channel 6 (CH6_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CH6_OUT_Struct
+ *! \brief  Conversion Result Channel 6 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH6_OUT_t__
+typedef struct _ADI_ADC_CH6_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion result of channel 6 is stored here */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CH6_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH6_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup CH7_OUT Conversion Result Channel 7 (CH7_OUT) Register
+ *  Conversion Result Channel 7 (CH7_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CH7_OUT_Struct
+ *! \brief  Conversion Result Channel 7 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH7_OUT_t__
+typedef struct _ADI_ADC_CH7_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion result of channel 7 is stored here */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CH7_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH7_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup BAT_OUT Battery Monitoring Result (BAT_OUT) Register
+ *  Battery Monitoring Result (BAT_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_BAT_OUT_Struct
+ *! \brief  Battery Monitoring Result Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_BAT_OUT_t__
+typedef struct _ADI_ADC_BAT_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion result of battery monitoring is stored here */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_BAT_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_BAT_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup TMP_OUT Temperature Result (TMP_OUT) Register
+ *  Temperature Result (TMP_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_TMP_OUT_Struct
+ *! \brief  Temperature Result Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_TMP_OUT_t__
+typedef struct _ADI_ADC_TMP_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion result of Temperature measurement 1 is stored here */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_TMP_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_TMP_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup TMP2_OUT Temperature Result 2 (TMP2_OUT) Register
+ *  Temperature Result 2 (TMP2_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_TMP2_OUT_Struct
+ *! \brief  Temperature Result 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_TMP2_OUT_t__
+typedef struct _ADI_ADC_TMP2_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Conversion result of Temperature measurement 2 is stored here */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_TMP2_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_TMP2_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup DMA_OUT DMA Output Register (DMA_OUT) Register
+ *  DMA Output Register (DMA_OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_DMA_OUT_Struct
+ *! \brief  DMA Output Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_DMA_OUT_t__
+typedef struct _ADI_ADC_DMA_OUT_t {
+  union {
+    struct {
+      unsigned int RESULT     : 16;  /**< Register to store conversion result for DMA */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_DMA_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_DMA_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup LIM0_LO Channel 0 Low Limit (LIM0_LO) Register
+ *  Channel 0 Low Limit (LIM0_LO) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_LIM0_LO_Struct
+ *! \brief  Channel 0 Low Limit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM0_LO_t__
+typedef struct _ADI_ADC_LIM0_LO_t {
+  union {
+    struct {
+      unsigned int VALUE      : 12;  /**< Low limit value for channel 0 */
+      unsigned int reserved12 :  3;
+      unsigned int EN         :  1;  /**< To enable low limit comparison on Channel 0 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_LIM0_LO_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM0_LO_t__ */
+
+/*@}*/
+
+/** @defgroup LIM0_HI Channel 0 High Limit (LIM0_HI) Register
+ *  Channel 0 High Limit (LIM0_HI) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_LIM0_HI_Struct
+ *! \brief  Channel 0 High Limit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM0_HI_t__
+typedef struct _ADI_ADC_LIM0_HI_t {
+  union {
+    struct {
+      unsigned int VALUE      : 12;  /**< High limit value for channel 0 */
+      unsigned int reserved12 :  3;
+      unsigned int EN         :  1;  /**< To enable high limit comparison on Channel 0 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_LIM0_HI_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM0_HI_t__ */
+
+/*@}*/
+
+/** @defgroup HYS0 Channel 0 Hysteresis (HYS0) Register
+ *  Channel 0 Hysteresis (HYS0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_HYS0_Struct
+ *! \brief  Channel 0 Hysteresis Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_HYS0_t__
+typedef struct _ADI_ADC_HYS0_t {
+  union {
+    struct {
+      unsigned int VALUE      :  9;  /**< Hysteresis value for Channel 0 */
+      unsigned int reserved9  :  3;
+      unsigned int MONCYC     :  3;  /**< Program number of conversion cycles to monitor channel 0 before raising alert */
+      unsigned int EN         :  1;  /**< To enable hysteresis for comparison on Channel 0 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_HYS0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_HYS0_t__ */
+
+/*@}*/
+
+/** @defgroup LIM1_LO Channel 1 Low Limit (LIM1_LO) Register
+ *  Channel 1 Low Limit (LIM1_LO) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_LIM1_LO_Struct
+ *! \brief  Channel 1 Low Limit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM1_LO_t__
+typedef struct _ADI_ADC_LIM1_LO_t {
+  union {
+    struct {
+      unsigned int VALUE      : 12;  /**< Low limit value for channel 1 */
+      unsigned int reserved12 :  3;
+      unsigned int EN         :  1;  /**< To enable low limit comparison on Channel 1 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_LIM1_LO_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM1_LO_t__ */
+
+/*@}*/
+
+/** @defgroup LIM1_HI Channel 1 High Limit (LIM1_HI) Register
+ *  Channel 1 High Limit (LIM1_HI) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_LIM1_HI_Struct
+ *! \brief  Channel 1 High Limit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM1_HI_t__
+typedef struct _ADI_ADC_LIM1_HI_t {
+  union {
+    struct {
+      unsigned int VALUE      : 12;  /**< High limit value for channel 1 */
+      unsigned int reserved12 :  3;
+      unsigned int EN         :  1;  /**< To enable high limit comparison on Channel 1 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_LIM1_HI_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM1_HI_t__ */
+
+/*@}*/
+
+/** @defgroup HYS1 Channel 1 Hysteresis (HYS1) Register
+ *  Channel 1 Hysteresis (HYS1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_HYS1_Struct
+ *! \brief  Channel 1 Hysteresis Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_HYS1_t__
+typedef struct _ADI_ADC_HYS1_t {
+  union {
+    struct {
+      unsigned int VALUE      :  9;  /**< Hysteresis value for Channel 1 */
+      unsigned int reserved9  :  3;
+      unsigned int MONCYC     :  3;  /**< Program number of conversion cycles to monitor channel 1 before raising alert */
+      unsigned int EN         :  1;  /**< To enable hysteresis for comparison on Channel 1 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_HYS1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_HYS1_t__ */
+
+/*@}*/
+
+/** @defgroup LIM2_LO Channel 2 Low Limit (LIM2_LO) Register
+ *  Channel 2 Low Limit (LIM2_LO) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_LIM2_LO_Struct
+ *! \brief  Channel 2 Low Limit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM2_LO_t__
+typedef struct _ADI_ADC_LIM2_LO_t {
+  union {
+    struct {
+      unsigned int VALUE      : 12;  /**< Low limit value for channel 2 */
+      unsigned int reserved12 :  3;
+      unsigned int EN         :  1;  /**< To enable low limit comparison on Channel 2 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_LIM2_LO_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM2_LO_t__ */
+
+/*@}*/
+
+/** @defgroup LIM2_HI Channel 2 High Limit (LIM2_HI) Register
+ *  Channel 2 High Limit (LIM2_HI) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_LIM2_HI_Struct
+ *! \brief  Channel 2 High Limit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM2_HI_t__
+typedef struct _ADI_ADC_LIM2_HI_t {
+  union {
+    struct {
+      unsigned int VALUE      : 12;  /**< High limit value for channel 2 */
+      unsigned int reserved12 :  3;
+      unsigned int EN         :  1;  /**< To enable high limit comparison on Channel 2 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_LIM2_HI_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM2_HI_t__ */
+
+/*@}*/
+
+/** @defgroup HYS2 Channel 2 Hysteresis (HYS2) Register
+ *  Channel 2 Hysteresis (HYS2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_HYS2_Struct
+ *! \brief  Channel 2 Hysteresis Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_HYS2_t__
+typedef struct _ADI_ADC_HYS2_t {
+  union {
+    struct {
+      unsigned int VALUE      :  9;  /**< Hysteresis value for Channel 2 */
+      unsigned int reserved9  :  3;
+      unsigned int MONCYC     :  3;  /**< Program number of conversion cycles to monitor channel 2 before raising alert */
+      unsigned int EN         :  1;  /**< To enable hysteresis for comparison on Channel 2 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_HYS2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_HYS2_t__ */
+
+/*@}*/
+
+/** @defgroup LIM3_LO Channel 3 Low Limit (LIM3_LO) Register
+ *  Channel 3 Low Limit (LIM3_LO) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_LIM3_LO_Struct
+ *! \brief  Channel 3 Low Limit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM3_LO_t__
+typedef struct _ADI_ADC_LIM3_LO_t {
+  union {
+    struct {
+      unsigned int VALUE      : 12;  /**< Low limit value for channel 3 */
+      unsigned int reserved12 :  3;
+      unsigned int EN         :  1;  /**< To enable low limit comparison on Channel 3 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_LIM3_LO_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM3_LO_t__ */
+
+/*@}*/
+
+/** @defgroup LIM3_HI Channel 3 High Limit (LIM3_HI) Register
+ *  Channel 3 High Limit (LIM3_HI) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_LIM3_HI_Struct
+ *! \brief  Channel 3 High Limit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM3_HI_t__
+typedef struct _ADI_ADC_LIM3_HI_t {
+  union {
+    struct {
+      unsigned int VALUE      : 12;  /**< High limit value for channel 3 */
+      unsigned int reserved12 :  3;
+      unsigned int EN         :  1;  /**< To enable high limit comparison on Channel 3 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_LIM3_HI_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM3_HI_t__ */
+
+/*@}*/
+
+/** @defgroup HYS3 Channel 3 Hysteresis (HYS3) Register
+ *  Channel 3 Hysteresis (HYS3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_HYS3_Struct
+ *! \brief  Channel 3 Hysteresis Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_HYS3_t__
+typedef struct _ADI_ADC_HYS3_t {
+  union {
+    struct {
+      unsigned int VALUE      :  9;  /**< Hysteresis value for Channel 3 */
+      unsigned int reserved9  :  3;
+      unsigned int MONCYC     :  3;  /**< Program number of conversion cycles to monitor channel 3 before raising alert */
+      unsigned int EN         :  1;  /**< To enable hysteresis for comparison on Channel 3 */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_HYS3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_HYS3_t__ */
+
+/*@}*/
+
+/** @defgroup CFG1 Reference Buffer Low Power Mode (CFG1) Register
+ *  Reference Buffer Low Power Mode (CFG1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_ADC_CFG1_Struct
+ *! \brief  Reference Buffer Low Power Mode Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CFG1_t__
+typedef struct _ADI_ADC_CFG1_t {
+  union {
+    struct {
+      unsigned int RBUFLP     :  1;  /**< Enable low power mode for reference buffer */
+      unsigned int reserved1  : 15;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_ADC_CFG1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CFG1_t__ */
+
+/*@}*/
+
+/** @defgroup STAT DMA Status (STAT) Register
+ *  DMA Status (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_STAT_Struct
+ *! \brief  DMA Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_STAT_t__
+typedef struct _ADI_DMA_STAT_t {
+  union {
+    struct {
+      unsigned int MEN        :  1;  /**< Enable Status of the Controller */
+      unsigned int reserved1  : 15;
+      unsigned int CHANM1     :  5;  /**< Number of Available DMA Channels Minus 1 */
+      unsigned int reserved21 : 11;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup CFG DMA Configuration (CFG) Register
+ *  DMA Configuration (CFG) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_CFG_Struct
+ *! \brief  DMA Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_CFG_t__
+typedef struct _ADI_DMA_CFG_t {
+  union {
+    struct {
+      unsigned int MEN        :  1;  /**< Controller Enable */
+      unsigned int reserved1  : 31;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_CFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_CFG_t__ */
+
+/*@}*/
+
+/** @defgroup PDBPTR DMA Channel Primary Control Database Pointer (PDBPTR) Register
+ *  DMA Channel Primary Control Database Pointer (PDBPTR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_PDBPTR_Struct
+ *! \brief  DMA Channel Primary Control Database Pointer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_PDBPTR_t__
+typedef struct _ADI_DMA_PDBPTR_t {
+  union {
+    struct {
+      unsigned int ADDR       : 32;  /**< Pointer to the Base Address of the Primary Data Structure */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_PDBPTR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_PDBPTR_t__ */
+
+/*@}*/
+
+/** @defgroup ADBPTR DMA Channel Alternate Control Database Pointer (ADBPTR) Register
+ *  DMA Channel Alternate Control Database Pointer (ADBPTR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_ADBPTR_Struct
+ *! \brief  DMA Channel Alternate Control Database Pointer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ADBPTR_t__
+typedef struct _ADI_DMA_ADBPTR_t {
+  union {
+    struct {
+      unsigned int ADDR       : 32;  /**< Base Address of the Alternate Data Structure */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_ADBPTR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ADBPTR_t__ */
+
+/*@}*/
+
+/** @defgroup SWREQ DMA Channel Software Request (SWREQ) Register
+ *  DMA Channel Software Request (SWREQ) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_SWREQ_Struct
+ *! \brief  DMA Channel Software Request Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_SWREQ_t__
+typedef struct _ADI_DMA_SWREQ_t {
+  union {
+    struct {
+      unsigned int CHAN       : 27;  /**< Generate Software Request */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_SWREQ_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_SWREQ_t__ */
+
+/*@}*/
+
+/** @defgroup RMSK_SET DMA Channel Request Mask Set (RMSK_SET) Register
+ *  DMA Channel Request Mask Set (RMSK_SET) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_RMSK_SET_Struct
+ *! \brief  DMA Channel Request Mask Set Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_RMSK_SET_t__
+typedef struct _ADI_DMA_RMSK_SET_t {
+  union {
+    struct {
+      unsigned int CHAN       : 27;  /**< Mask Requests from DMA Channels */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_RMSK_SET_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_RMSK_SET_t__ */
+
+/*@}*/
+
+/** @defgroup RMSK_CLR DMA Channel Request Mask Clear (RMSK_CLR) Register
+ *  DMA Channel Request Mask Clear (RMSK_CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_RMSK_CLR_Struct
+ *! \brief  DMA Channel Request Mask Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_RMSK_CLR_t__
+typedef struct _ADI_DMA_RMSK_CLR_t {
+  union {
+    struct {
+      unsigned int CHAN       : 27;  /**< Clear Request Mask Set Bits */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_RMSK_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_RMSK_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup EN_SET DMA Channel Enable Set (EN_SET) Register
+ *  DMA Channel Enable Set (EN_SET) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_EN_SET_Struct
+ *! \brief  DMA Channel Enable Set Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_EN_SET_t__
+typedef struct _ADI_DMA_EN_SET_t {
+  union {
+    struct {
+      unsigned int CHAN       : 27;  /**< Enable DMA Channels */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_EN_SET_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_EN_SET_t__ */
+
+/*@}*/
+
+/** @defgroup EN_CLR DMA Channel Enable Clear (EN_CLR) Register
+ *  DMA Channel Enable Clear (EN_CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_EN_CLR_Struct
+ *! \brief  DMA Channel Enable Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_EN_CLR_t__
+typedef struct _ADI_DMA_EN_CLR_t {
+  union {
+    struct {
+      unsigned int CHAN       : 27;  /**< Disable DMA Channels */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_EN_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_EN_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup ALT_SET DMA Channel Primary Alternate Set (ALT_SET) Register
+ *  DMA Channel Primary Alternate Set (ALT_SET) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_ALT_SET_Struct
+ *! \brief  DMA Channel Primary Alternate Set Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ALT_SET_t__
+typedef struct _ADI_DMA_ALT_SET_t {
+  union {
+    struct {
+      unsigned int CHAN       : 27;  /**< Control Structure Status / Select Alternate Structure */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_ALT_SET_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ALT_SET_t__ */
+
+/*@}*/
+
+/** @defgroup ALT_CLR DMA Channel Primary Alternate Clear (ALT_CLR) Register
+ *  DMA Channel Primary Alternate Clear (ALT_CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_ALT_CLR_Struct
+ *! \brief  DMA Channel Primary Alternate Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ALT_CLR_t__
+typedef struct _ADI_DMA_ALT_CLR_t {
+  union {
+    struct {
+      unsigned int CHAN       : 27;  /**< Select Primary Data Structure */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_ALT_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ALT_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup PRI_SET DMA Channel Priority Set (PRI_SET) Register
+ *  DMA Channel Priority Set (PRI_SET) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_PRI_SET_Struct
+ *! \brief  DMA Channel Priority Set Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_PRI_SET_t__
+typedef struct _ADI_DMA_PRI_SET_t {
+  union {
+    struct {
+      unsigned int CHAN       : 27;  /**< Configure Channel for High Priority */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_PRI_SET_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_PRI_SET_t__ */
+
+/*@}*/
+
+/** @defgroup PRI_CLR DMA Channel Priority Clear (PRI_CLR) Register
+ *  DMA Channel Priority Clear (PRI_CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_PRI_CLR_Struct
+ *! \brief  DMA Channel Priority Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_PRI_CLR_t__
+typedef struct _ADI_DMA_PRI_CLR_t {
+  union {
+    struct {
+      unsigned int CHPRICLR   : 27;  /**< Configure Channel for Default Priority Level */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_PRI_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_PRI_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup ERRCHNL_CLR DMA per Channel Error Clear (ERRCHNL_CLR) Register
+ *  DMA per Channel Error Clear (ERRCHNL_CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_ERRCHNL_CLR_Struct
+ *! \brief  DMA per Channel Error Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ERRCHNL_CLR_t__
+typedef struct _ADI_DMA_ERRCHNL_CLR_t {
+  union {
+    struct {
+      unsigned int CHAN       : 27;  /**< Per Channel Bus Error Status/Clear */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_ERRCHNL_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ERRCHNL_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup ERR_CLR DMA Bus Error Clear (ERR_CLR) Register
+ *  DMA Bus Error Clear (ERR_CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_ERR_CLR_Struct
+ *! \brief  DMA Bus Error Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ERR_CLR_t__
+typedef struct _ADI_DMA_ERR_CLR_t {
+  union {
+    struct {
+      unsigned int CHAN       : 27;  /**< Bus Error Status */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_ERR_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ERR_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup INVALIDDESC_CLR DMA per Channel Invalid Descriptor Clear (INVALIDDESC_CLR) Register
+ *  DMA per Channel Invalid Descriptor Clear (INVALIDDESC_CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_INVALIDDESC_CLR_Struct
+ *! \brief  DMA per Channel Invalid Descriptor Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_INVALIDDESC_CLR_t__
+typedef struct _ADI_DMA_INVALIDDESC_CLR_t {
+  union {
+    struct {
+      unsigned int CHAN       : 27;  /**< Per Channel Invalid Descriptor Status/Clear */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_INVALIDDESC_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_INVALIDDESC_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup BS_SET DMA Channel Bytes Swap Enable Set (BS_SET) Register
+ *  DMA Channel Bytes Swap Enable Set (BS_SET) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_BS_SET_Struct
+ *! \brief  DMA Channel Bytes Swap Enable Set Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_BS_SET_t__
+typedef struct _ADI_DMA_BS_SET_t {
+  union {
+    struct {
+      unsigned int CHAN       : 27;  /**< Byte Swap Status */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_BS_SET_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_BS_SET_t__ */
+
+/*@}*/
+
+/** @defgroup BS_CLR DMA Channel Bytes Swap Enable Clear (BS_CLR) Register
+ *  DMA Channel Bytes Swap Enable Clear (BS_CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_BS_CLR_Struct
+ *! \brief  DMA Channel Bytes Swap Enable Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_BS_CLR_t__
+typedef struct _ADI_DMA_BS_CLR_t {
+  union {
+    struct {
+      unsigned int CHAN       : 27;  /**< Disable Byte Swap */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_BS_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_BS_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup SRCADDR_SET DMA Channel Source Address Decrement Enable Set (SRCADDR_SET) Register
+ *  DMA Channel Source Address Decrement Enable Set (SRCADDR_SET) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_SRCADDR_SET_Struct
+ *! \brief  DMA Channel Source Address Decrement Enable Set Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_SRCADDR_SET_t__
+typedef struct _ADI_DMA_SRCADDR_SET_t {
+  union {
+    struct {
+      unsigned int CHAN       : 27;  /**< Source Address Decrement Status */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_SRCADDR_SET_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_SRCADDR_SET_t__ */
+
+/*@}*/
+
+/** @defgroup SRCADDR_CLR DMA Channel Source Address Decrement Enable Clear (SRCADDR_CLR) Register
+ *  DMA Channel Source Address Decrement Enable Clear (SRCADDR_CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_SRCADDR_CLR_Struct
+ *! \brief  DMA Channel Source Address Decrement Enable Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_SRCADDR_CLR_t__
+typedef struct _ADI_DMA_SRCADDR_CLR_t {
+  union {
+    struct {
+      unsigned int CHAN       : 27;  /**< Disable Source Address Decrement */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_SRCADDR_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_SRCADDR_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup DSTADDR_SET DMA Channel Destination Address Decrement Enable Set (DSTADDR_SET) Register
+ *  DMA Channel Destination Address Decrement Enable Set (DSTADDR_SET) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_DSTADDR_SET_Struct
+ *! \brief  DMA Channel Destination Address Decrement Enable Set Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_DSTADDR_SET_t__
+typedef struct _ADI_DMA_DSTADDR_SET_t {
+  union {
+    struct {
+      unsigned int CHAN       : 27;  /**< Destination Address Decrement Status */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_DSTADDR_SET_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_DSTADDR_SET_t__ */
+
+/*@}*/
+
+/** @defgroup DSTADDR_CLR DMA Channel Destination Address Decrement Enable Clear (DSTADDR_CLR) Register
+ *  DMA Channel Destination Address Decrement Enable Clear (DSTADDR_CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_DSTADDR_CLR_Struct
+ *! \brief  DMA Channel Destination Address Decrement Enable Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_DSTADDR_CLR_t__
+typedef struct _ADI_DMA_DSTADDR_CLR_t {
+  union {
+    struct {
+      unsigned int CHAN       : 27;  /**< Disable Destination Address Decrement */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_DSTADDR_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_DSTADDR_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup REVID DMA Controller Revision ID (REVID) Register
+ *  DMA Controller Revision ID (REVID) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_DMA_REVID_Struct
+ *! \brief  DMA Controller Revision ID Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_REVID_t__
+typedef struct _ADI_DMA_REVID_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< DMA Controller Revision ID */
+      unsigned int reserved8  : 24;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_DMA_REVID_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_REVID_t__ */
+
+/*@}*/
+
+/** @defgroup STAT Status (STAT) Register
+ *  Status (STAT) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_FLCC_STAT_ACCESS_MODE
+ *! \brief  Access Mode (ACCESS_MODE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  FLCC_STAT_DIRECT   = 0,  /**< Flash controller is currently in Direct Access mode; user access to all registers is enabled                                                                                                                                                                                                                                         */
+  FLCC_STAT_INDIRECT = 1   /**< Flash Controller is currently in Indirect Access mode; user access to registers is limited to read-only access of the status register. Full register access will be restored when the Cryptographic module releases control of the flash controller (crypto completes the ongoing operation within the protected key storage region) */
+} ADI_FLCC_STAT_ACCESS_MODE;
+
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_STAT_Struct
+ *! \brief  Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_STAT_t__
+typedef struct _ADI_FLCC_STAT_t {
+  union {
+    struct {
+      unsigned int CMDBUSY    :  1;  /**< Command busy */
+      unsigned int WRCLOSE    :  1;  /**< WRITE registers are closed */
+      unsigned int CMDCOMP    :  1;  /**< Command complete */
+      unsigned int WRALCOMP   :  1;  /**< Write almost complete */
+      unsigned int CMDFAIL    :  2;  /**< Provides information on command failures */
+      unsigned int SLEEPING   :  1;  /**< Flash array is in low power (sleep) mode */
+      unsigned int ECCERRCMD  :  2;  /**< ECC errors detected during user issued SIGN command */
+      unsigned int ECCRDERR   :  2;  /**< ECC IRQ cause */
+      unsigned int OVERLAP    :  1;  /**< Overlapping Command */
+      unsigned int reserved12 :  1;
+      unsigned int SIGNERR    :  1;  /**< Signature check failure during initialization */
+      unsigned int INIT       :  1;  /**< Flash controller initialization in progress */
+      unsigned int ECCINFOSIGN :  2;  /**< ECC status of flash initialization */
+      unsigned int ECCERRCNT   :  3;  /**< ECC correction counter */
+      unsigned int reserved20  :  5;
+      unsigned int ECCICODE    :  2;  /**< ICode AHB Bus Error ECC status */
+      unsigned int ECCDCODE    :  2;  /**< DCode AHB Bus Error ECC status */
+      unsigned int CACHESRAMPERR :  1;  /**< SRAM parity errors in Cache Controller */
+      unsigned int reserved30    :  1;
+      unsigned int ACCESS_MODE   :  1;  /**< Access Mode */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup IEN Interrupt Enable (IEN) Register
+ *  Interrupt Enable (IEN) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_FLCC_IEN_ECC_CORRECT
+ *! \brief  Control whether to generate bus errors, interrupts, or neither in response to 1-bit ECC Correction events (ECC_CORRECT) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  FLCC_IEN_NONE_COR    = 0,  /**< Do not generate a response to ECC events      */
+  FLCC_IEN_BUS_ERR_COR = 1,  /**< Generate Bus Errors in response to ECC events */
+  FLCC_IEN_IRQ_COR     = 2   /**< Generate IRQs in response to ECC events       */
+} ADI_FLCC_IEN_ECC_CORRECT;
+
+
+/*  =========================================================================
+ *! \enum   ADI_FLCC_IEN_ECC_ERROR
+ *! \brief  Control whether to generate bus errors, interrupts, or neither in response to 2-bit ECC Error events (ECC_ERROR) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  FLCC_IEN_NONE_ERR    = 0,  /**< Do not generate a response to ECC events      */
+  FLCC_IEN_BUS_ERR_ERR = 1,  /**< Generate Bus Errors in response to ECC events */
+  FLCC_IEN_IRQ_ERR     = 2   /**< Generate IRQs in response to ECC events       */
+} ADI_FLCC_IEN_ECC_ERROR;
+
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_IEN_Struct
+ *! \brief  Interrupt Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_IEN_t__
+typedef struct _ADI_FLCC_IEN_t {
+  union {
+    struct {
+      unsigned int CMDCMPLT   :  1;  /**< Command complete interrupt enable */
+      unsigned int WRALCMPLT  :  1;  /**< Write almost complete interrupt enable */
+      unsigned int CMDFAIL    :  1;  /**< Command fail interrupt enable */
+      unsigned int reserved3   :  1;
+      unsigned int ECC_CORRECT :  2;  /**< Control whether to generate bus errors, interrupts, or neither in response to 1-bit ECC Correction events */
+      unsigned int ECC_ERROR   :  2;  /**< Control whether to generate bus errors, interrupts, or neither in response to 2-bit ECC Error events */
+      unsigned int reserved8   : 24;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_IEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_IEN_t__ */
+
+/*@}*/
+
+/** @defgroup CMD Command (CMD) Register
+ *  Command (CMD) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_FLCC_CMD_VALUE
+ *! \brief  Commands (VALUE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  FLCC_CMD_IDLE        = 0,  /**< IDLE                                                                  */
+  FLCC_CMD_ABORT       = 1,  /**< ABORT                                                                 */
+  FLCC_CMD_SLEEP       = 2,  /**< Requests flash to enter Sleep mode                                    */
+  FLCC_CMD_SIGN        = 3,  /**< SIGN                                                                  */
+  FLCC_CMD_WRITE       = 4,  /**< WRITE                                                                 */
+  FLCC_CMD_BLANK_CHECK = 5,  /**< Checks all of User Space; fails if any bits in user space are cleared */
+  FLCC_CMD_ERASEPAGE   = 6,  /**< ERASEPAGE                                                             */
+  FLCC_CMD_MASSERASE   = 7   /**< MASSERASE                                                             */
+} ADI_FLCC_CMD_VALUE;
+
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_CMD_Struct
+ *! \brief  Command Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CMD_t__
+typedef struct _ADI_FLCC_CMD_t {
+  union {
+    struct {
+      unsigned int VALUE      :  4;  /**< Commands */
+      unsigned int reserved4  : 28;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_CMD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CMD_t__ */
+
+/*@}*/
+
+/** @defgroup KH_ADDR Write Address (KH_ADDR) Register
+ *  Write Address (KH_ADDR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_KH_ADDR_Struct
+ *! \brief  Write Address Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_KH_ADDR_t__
+typedef struct _ADI_FLCC_KH_ADDR_t {
+  union {
+    struct {
+      unsigned int reserved0  :  3;
+      unsigned int VALUE      : 17;  /**< Address to be written on a WRITE command */
+      unsigned int reserved20 : 12;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_KH_ADDR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_KH_ADDR_t__ */
+
+/*@}*/
+
+/** @defgroup KH_DATA0 Write Lower Data (KH_DATA0) Register
+ *  Write Lower Data (KH_DATA0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_KH_DATA0_Struct
+ *! \brief  Write Lower Data Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_KH_DATA0_t__
+typedef struct _ADI_FLCC_KH_DATA0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Lower half of 64-bit dual word data to be written on a Write command */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_KH_DATA0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_KH_DATA0_t__ */
+
+/*@}*/
+
+/** @defgroup KH_DATA1 Write Upper Data (KH_DATA1) Register
+ *  Write Upper Data (KH_DATA1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_KH_DATA1_Struct
+ *! \brief  Write Upper Data Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_KH_DATA1_t__
+typedef struct _ADI_FLCC_KH_DATA1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Upper half of 64-bit dual word data to be written on a Write command */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_KH_DATA1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_KH_DATA1_t__ */
+
+/*@}*/
+
+/** @defgroup PAGE_ADDR0 Lower Page Address (PAGE_ADDR0) Register
+ *  Lower Page Address (PAGE_ADDR0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_PAGE_ADDR0_Struct
+ *! \brief  Lower Page Address Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_PAGE_ADDR0_t__
+typedef struct _ADI_FLCC_PAGE_ADDR0_t {
+  union {
+    struct {
+      unsigned int reserved0  : 10;
+      unsigned int VALUE      : 10;  /**< Lower address bits of the page address */
+      unsigned int reserved20 : 12;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_PAGE_ADDR0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_PAGE_ADDR0_t__ */
+
+/*@}*/
+
+/** @defgroup PAGE_ADDR1 Upper Page Address (PAGE_ADDR1) Register
+ *  Upper Page Address (PAGE_ADDR1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_PAGE_ADDR1_Struct
+ *! \brief  Upper Page Address Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_PAGE_ADDR1_t__
+typedef struct _ADI_FLCC_PAGE_ADDR1_t {
+  union {
+    struct {
+      unsigned int reserved0  : 10;
+      unsigned int VALUE      : 10;  /**< Upper address bits of the page address */
+      unsigned int reserved20 : 12;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_PAGE_ADDR1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_PAGE_ADDR1_t__ */
+
+/*@}*/
+
+/** @defgroup KEY Key (KEY) Register
+ *  Key (KEY) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_FLCC_KEY_VALUE
+ *! \brief  Key register (VALUE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  FLCC_KEY_USERKEY = 1735161189   /**< USERKEY */
+} ADI_FLCC_KEY_VALUE;
+
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_KEY_Struct
+ *! \brief  Key Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_KEY_t__
+typedef struct _ADI_FLCC_KEY_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Key register */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_KEY_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_KEY_t__ */
+
+/*@}*/
+
+/** @defgroup WR_ABORT_ADDR Write Abort Address (WR_ABORT_ADDR) Register
+ *  Write Abort Address (WR_ABORT_ADDR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_WR_ABORT_ADDR_Struct
+ *! \brief  Write Abort Address Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_WR_ABORT_ADDR_t__
+typedef struct _ADI_FLCC_WR_ABORT_ADDR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Address of recently aborted write command */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_WR_ABORT_ADDR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_WR_ABORT_ADDR_t__ */
+
+/*@}*/
+
+/** @defgroup WRPROT Write Protection (WRPROT) Register
+ *  Write Protection (WRPROT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_WRPROT_Struct
+ *! \brief  Write Protection Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_WRPROT_t__
+typedef struct _ADI_FLCC_WRPROT_t {
+  union {
+    struct {
+      unsigned int WORD       : 32;  /**< Clear bits to write protect related groups of user space pages */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_WRPROT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_WRPROT_t__ */
+
+/*@}*/
+
+/** @defgroup SIGNATURE Signature (SIGNATURE) Register
+ *  Signature (SIGNATURE) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_SIGNATURE_Struct
+ *! \brief  Signature Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_SIGNATURE_t__
+typedef struct _ADI_FLCC_SIGNATURE_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Read signature */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_SIGNATURE_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_SIGNATURE_t__ */
+
+/*@}*/
+
+/** @defgroup UCFG User Configuration (UCFG) Register
+ *  User Configuration (UCFG) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_UCFG_Struct
+ *! \brief  User Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_UCFG_t__
+typedef struct _ADI_FLCC_UCFG_t {
+  union {
+    struct {
+      unsigned int KHDMAEN    :  1;  /**< Key hole DMA enable */
+      unsigned int AUTOINCEN  :  1;  /**< Auto Address Increment for Key Hole Access */
+      unsigned int reserved2  : 30;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_UCFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_UCFG_t__ */
+
+/*@}*/
+
+/** @defgroup TIME_PARAM0 Time Parameter 0 (TIME_PARAM0) Register
+ *  Time Parameter 0 (TIME_PARAM0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_TIME_PARAM0_Struct
+ *! \brief  Time Parameter 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_TIME_PARAM0_t__
+typedef struct _ADI_FLCC_TIME_PARAM0_t {
+  union {
+    struct {
+      unsigned int DIVREFCLK  :  1;  /**< Divide Reference Clock (by 2) */
+      unsigned int reserved1  :  3;
+      unsigned int TNVS       :  4;  /**< PROG/ERASE to NVSTR setup time */
+      unsigned int TPGS       :  4;  /**< NVSTR to Program setup time */
+      unsigned int TPROG      :  4;  /**< Program time */
+      unsigned int TNVH       :  4;  /**< NVSTR Hold time */
+      unsigned int TRCV       :  4;  /**< Recovery time */
+      unsigned int TERASE     :  4;  /**< Erase Time */
+      unsigned int TNVH1      :  4;  /**< NVSTR Hold time during Mass Erase */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_TIME_PARAM0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_TIME_PARAM0_t__ */
+
+/*@}*/
+
+/** @defgroup TIME_PARAM1 Time Parameter 1 (TIME_PARAM1) Register
+ *  Time Parameter 1 (TIME_PARAM1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_TIME_PARAM1_Struct
+ *! \brief  Time Parameter 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_TIME_PARAM1_t__
+typedef struct _ADI_FLCC_TIME_PARAM1_t {
+  union {
+    struct {
+      unsigned int TWK        :  4;  /**< Wake up time */
+      unsigned int WAITSTATES :  3;  /**< Number of wait states to access flash */
+      unsigned int reserved7     :  1;
+      unsigned int CURWAITSTATES :  3;  /**< Current wait states [2:0] */
+      unsigned int reserved11    : 21;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_TIME_PARAM1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_TIME_PARAM1_t__ */
+
+/*@}*/
+
+/** @defgroup ABORT_EN_LO IRQ Abort Enable (Lower Bits) (ABORT_EN_LO) Register
+ *  IRQ Abort Enable (Lower Bits) (ABORT_EN_LO) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_ABORT_EN_LO_Struct
+ *! \brief  IRQ Abort Enable (Lower Bits) Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_ABORT_EN_LO_t__
+typedef struct _ADI_FLCC_ABORT_EN_LO_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< VALUE[31:0] Sys IRQ Abort Enable */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_ABORT_EN_LO_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_ABORT_EN_LO_t__ */
+
+/*@}*/
+
+/** @defgroup ABORT_EN_HI IRQ Abort Enable (Upper Bits) (ABORT_EN_HI) Register
+ *  IRQ Abort Enable (Upper Bits) (ABORT_EN_HI) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_ABORT_EN_HI_Struct
+ *! \brief  IRQ Abort Enable (Upper Bits) Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_ABORT_EN_HI_t__
+typedef struct _ADI_FLCC_ABORT_EN_HI_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< VALUE[63:32] Sys IRQ Abort Enable */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_ABORT_EN_HI_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_ABORT_EN_HI_t__ */
+
+/*@}*/
+
+/** @defgroup ECC_CFG ECC Configuration (ECC_CFG) Register
+ *  ECC Configuration (ECC_CFG) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_ECC_CFG_Struct
+ *! \brief  ECC Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_ECC_CFG_t__
+typedef struct _ADI_FLCC_ECC_CFG_t {
+  union {
+    struct {
+      unsigned int EN         :  1;  /**< ECC Enable */
+      unsigned int INFOEN     :  1;  /**< Info space ECC Enable bit */
+      unsigned int reserved2  :  6;
+      unsigned int PTR        : 24;  /**< ECC start page pointer */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_ECC_CFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_ECC_CFG_t__ */
+
+/*@}*/
+
+/** @defgroup ECC_ADDR ECC Status (Address) (ECC_ADDR) Register
+ *  ECC Status (Address) (ECC_ADDR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_ECC_ADDR_Struct
+ *! \brief  ECC Status (Address) Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_ECC_ADDR_t__
+typedef struct _ADI_FLCC_ECC_ADDR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 20;  /**< This register has the address for which ECC error is detected */
+      unsigned int reserved20 : 12;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_ECC_ADDR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_ECC_ADDR_t__ */
+
+/*@}*/
+
+/** @defgroup POR_SEC Flash Security (POR_SEC) Register
+ *  Flash Security (POR_SEC) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_POR_SEC_Struct
+ *! \brief  Flash Security Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_POR_SEC_t__
+typedef struct _ADI_FLCC_POR_SEC_t {
+  union {
+    struct {
+      unsigned int SECURE     :  1;  /**< Set this bit to prevent read or write access to User Space (sticky when set) */
+      unsigned int reserved1  : 31;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_POR_SEC_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_POR_SEC_t__ */
+
+/*@}*/
+
+/** @defgroup VOL_CFG Volatile Flash Configuration (VOL_CFG) Register
+ *  Volatile Flash Configuration (VOL_CFG) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_VOL_CFG_Struct
+ *! \brief  Volatile Flash Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_VOL_CFG_t__
+typedef struct _ADI_FLCC_VOL_CFG_t {
+  union {
+    struct {
+      unsigned int INFO_REMAP :  1;  /**< Alias the info space to the base address of user space */
+      unsigned int reserved1  : 31;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_VOL_CFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_VOL_CFG_t__ */
+
+/*@}*/
+
+/** @defgroup STAT Cache Status Register (STAT) Register
+ *  Cache Status Register (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_CACHE_STAT_Struct
+ *! \brief  Cache Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_STAT_t__
+typedef struct _ADI_FLCC_CACHE_STAT_t {
+  union {
+    struct {
+      unsigned int ICEN       :  1;  /**< If this bit is set,  I-Cache is enabled */
+      unsigned int reserved1  : 31;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_CACHE_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup SETUP Cache Setup Register (SETUP) Register
+ *  Cache Setup Register (SETUP) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_CACHE_SETUP_Struct
+ *! \brief  Cache Setup Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_SETUP_t__
+typedef struct _ADI_FLCC_CACHE_SETUP_t {
+  union {
+    struct {
+      unsigned int ICEN       :  1;  /**< If this bit set, I-Cache is enabled for AHB accesses */
+      unsigned int LCKIC      :  1;  /**< If this bit is set, I-Cache contents are locked */
+      unsigned int reserved2  : 30;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_CACHE_SETUP_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_SETUP_t__ */
+
+/*@}*/
+
+/** @defgroup KEY Cache Key Register (KEY) Register
+ *  Cache Key Register (KEY) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_FLCC_CACHE_KEY_Struct
+ *! \brief  Cache Key Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_KEY_t__
+typedef struct _ADI_FLCC_CACHE_KEY_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Cache Key */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_FLCC_CACHE_KEY_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_KEY_t__ */
+
+/*@}*/
+
+/** @defgroup CFG Port  Configuration (CFG) Register
+ *  Port  Configuration (CFG) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_CFG_Struct
+ *! \brief  Port  Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_CFG_t__
+typedef struct _ADI_GPIO_CFG_t {
+  union {
+    struct {
+      unsigned int PIN00      :  2;  /**< Pin 0 configuration bits */
+      unsigned int PIN01      :  2;  /**< Pin 1 configuration bits */
+      unsigned int PIN02      :  2;  /**< Pin 2 configuration bits */
+      unsigned int PIN03      :  2;  /**< Pin 3 configuration bits */
+      unsigned int PIN04      :  2;  /**< Pin 4 configuration bits */
+      unsigned int PIN05      :  2;  /**< Pin 5 configuration bits */
+      unsigned int PIN06      :  2;  /**< Pin 6 configuration bits */
+      unsigned int PIN07      :  2;  /**< Pin 7 configuration bits */
+      unsigned int PIN08      :  2;  /**< Pin 8 configuration bits */
+      unsigned int PIN09      :  2;  /**< Pin 9 configuration bits */
+      unsigned int PIN10      :  2;  /**< Pin 10  configuration bits */
+      unsigned int PIN11      :  2;  /**< Pin 11  configuration bits */
+      unsigned int PIN12      :  2;  /**< Pin 12  configuration bits */
+      unsigned int PIN13      :  2;  /**< Pin 13  configuration bits */
+      unsigned int PIN14      :  2;  /**< Pin 14  configuration bits */
+      unsigned int PIN15      :  2;  /**< Pin 15  configuration bits */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_GPIO_CFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_CFG_t__ */
+
+/*@}*/
+
+/** @defgroup OEN Port Output Enable (OEN) Register
+ *  Port Output Enable (OEN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_OEN_Struct
+ *! \brief  Port Output Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_OEN_t__
+typedef struct _ADI_GPIO_OEN_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Pin Output Drive enable */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_OEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_OEN_t__ */
+
+/*@}*/
+
+/** @defgroup PE Port Output Pull-up/Pull-down Enable (PE) Register
+ *  Port Output Pull-up/Pull-down Enable (PE) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_PE_Struct
+ *! \brief  Port Output Pull-up/Pull-down Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_PE_t__
+typedef struct _ADI_GPIO_PE_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Pin Pull enable */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_PE_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_PE_t__ */
+
+/*@}*/
+
+/** @defgroup IEN Port  Input Path Enable (IEN) Register
+ *  Port  Input Path Enable (IEN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_IEN_Struct
+ *! \brief  Port  Input Path Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_IEN_t__
+typedef struct _ADI_GPIO_IEN_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Input path enable */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_IEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_IEN_t__ */
+
+/*@}*/
+
+/** @defgroup IN Port  Registered Data Input (IN) Register
+ *  Port  Registered Data Input (IN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_IN_Struct
+ *! \brief  Port  Registered Data Input Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_IN_t__
+typedef struct _ADI_GPIO_IN_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Registered data input */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_IN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_IN_t__ */
+
+/*@}*/
+
+/** @defgroup OUT Port Data Output (OUT) Register
+ *  Port Data Output (OUT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_OUT_Struct
+ *! \brief  Port Data Output Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_OUT_t__
+typedef struct _ADI_GPIO_OUT_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Data out */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_OUT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_OUT_t__ */
+
+/*@}*/
+
+/** @defgroup SET Port Data Out Set (SET) Register
+ *  Port Data Out Set (SET) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_SET_Struct
+ *! \brief  Port Data Out Set Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_SET_t__
+typedef struct _ADI_GPIO_SET_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Set the output HIGH for the pin */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_SET_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_SET_t__ */
+
+/*@}*/
+
+/** @defgroup CLR Port Data Out Clear (CLR) Register
+ *  Port Data Out Clear (CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_CLR_Struct
+ *! \brief  Port Data Out Clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_CLR_t__
+typedef struct _ADI_GPIO_CLR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Set the output low  for the port pin */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup TGL Port Pin Toggle (TGL) Register
+ *  Port Pin Toggle (TGL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_TGL_Struct
+ *! \brief  Port Pin Toggle Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_TGL_t__
+typedef struct _ADI_GPIO_TGL_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Toggle the output of the port pin */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_TGL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_TGL_t__ */
+
+/*@}*/
+
+/** @defgroup POL Port Interrupt Polarity (POL) Register
+ *  Port Interrupt Polarity (POL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_POL_Struct
+ *! \brief  Port Interrupt Polarity Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_POL_t__
+typedef struct _ADI_GPIO_POL_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Interrupt polarity */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_POL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_POL_t__ */
+
+/*@}*/
+
+/** @defgroup IENA Port Interrupt A Enable (IENA) Register
+ *  Port Interrupt A Enable (IENA) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_IENA_Struct
+ *! \brief  Port Interrupt A Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_IENA_t__
+typedef struct _ADI_GPIO_IENA_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Interrupt A enable */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_IENA_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_IENA_t__ */
+
+/*@}*/
+
+/** @defgroup IENB Port Interrupt B Enable (IENB) Register
+ *  Port Interrupt B Enable (IENB) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_IENB_Struct
+ *! \brief  Port Interrupt B Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_IENB_t__
+typedef struct _ADI_GPIO_IENB_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Interrupt B enable */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_IENB_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_IENB_t__ */
+
+/*@}*/
+
+/** @defgroup INT Port Interrupt Status (INT) Register
+ *  Port Interrupt Status (INT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_INT_Struct
+ *! \brief  Port Interrupt Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_INT_t__
+typedef struct _ADI_GPIO_INT_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Interrupt Status */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_INT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_INT_t__ */
+
+/*@}*/
+
+/** @defgroup DS Port Drive Strength Select (DS) Register
+ *  Port Drive Strength Select (DS) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_GPIO_DS_Struct
+ *! \brief  Port Drive Strength Select Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_DS_t__
+typedef struct _ADI_GPIO_DS_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Drive strength select */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_GPIO_DS_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_DS_t__ */
+
+/*@}*/
+
+/** @defgroup CTL_A Half SPORT 'A' Control Register (CTL_A) Register
+ *  Half SPORT 'A' Control Register (CTL_A) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_SPEN
+ *! \brief  Serial Port Enable (SPEN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_DIS = 0,  /**< Disable */
+  SPORT_CTL_A_CTL_EN  = 1   /**< Enable  */
+} ADI_SPORT_CTL_A_SPEN;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_FSMUXSEL
+ *! \brief  Frame Sync Multiplexer Select (FSMUXSEL) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_FS_MUX_DIS = 0,  /**< Disable frame sync multiplexing */
+  SPORT_CTL_A_CTL_FS_MUX_EN  = 1   /**< Enable frame sync multiplexing  */
+} ADI_SPORT_CTL_A_FSMUXSEL;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_CKMUXSEL
+ *! \brief  Clock Multiplexer Select (CKMUXSEL) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_CLK_MUX_DIS = 0,  /**< Disable serial clock multiplexing */
+  SPORT_CTL_A_CTL_CLK_MUX_EN  = 1   /**< Enable serial clock multiplexing  */
+} ADI_SPORT_CTL_A_CKMUXSEL;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_LSBF
+ *! \brief  Least-Significant Bit First (LSBF) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_MSB_FIRST = 0,  /**< MSB first sent/received */
+  SPORT_CTL_A_CTL_LSB_FIRST = 1   /**< LSB first sent/received */
+} ADI_SPORT_CTL_A_LSBF;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_ICLK
+ *! \brief  Internal Clock (ICLK) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_EXTERNAL_CLK = 0,  /**< External clock */
+  SPORT_CTL_A_CTL_INTERNAL_CLK = 1   /**< Internal clock */
+} ADI_SPORT_CTL_A_ICLK;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_OPMODE
+ *! \brief  Operation mode (OPMODE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_SERIAL        = 0,  /**< DSP standard      */
+  SPORT_CTL_A_CTL_TIMER_EN_MODE = 1   /**< Timer_enable mode */
+} ADI_SPORT_CTL_A_OPMODE;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_CKRE
+ *! \brief  Clock Rising Edge (CKRE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_CLK_FALL_EDGE = 0,  /**< Clock falling edge */
+  SPORT_CTL_A_CTL_CLK_RISE_EDGE = 1   /**< Clock rising edge  */
+} ADI_SPORT_CTL_A_CKRE;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_FSR
+ *! \brief  Frame Sync Required (FSR) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_FS_NOT_REQ = 0,  /**< No frame sync required */
+  SPORT_CTL_A_CTL_FS_REQ     = 1   /**< Frame sync required    */
+} ADI_SPORT_CTL_A_FSR;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_IFS
+ *! \brief  Internal Frame Sync (IFS) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_EXTERNAL_FS = 0,  /**< External frame sync */
+  SPORT_CTL_A_CTL_INTERNAL_FS = 1   /**< Internal frame sync */
+} ADI_SPORT_CTL_A_IFS;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_DIFS
+ *! \brief  Data-Independent Frame Sync (DIFS) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_DATA_DEP_FS  = 0,  /**< Data-dependent frame sync   */
+  SPORT_CTL_A_CTL_DATA_INDP_FS = 1   /**< Data-independent frame sync */
+} ADI_SPORT_CTL_A_DIFS;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_LFS
+ *! \brief  Active-Low Frame Sync (LFS) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_FS_LO = 0,  /**< Active high frame sync */
+  SPORT_CTL_A_CTL_FS_HI = 1   /**< Active low frame sync  */
+} ADI_SPORT_CTL_A_LFS;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_LAFS
+ *! \brief  Late Frame Sync (LAFS) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_EARLY_FS = 0,  /**< Early frame sync */
+  SPORT_CTL_A_CTL_LATE_FS  = 1   /**< Late frame sync  */
+} ADI_SPORT_CTL_A_LAFS;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_PACK
+ *! \brief  Packing Enable (PACK) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_PACK_DIS   = 0,  /**< Disable               */
+  SPORT_CTL_A_CTL_PACK_8BIT  = 1,  /**< 8-bit packing enable  */
+  SPORT_CTL_A_CTL_PACK_16BIT = 2   /**< 16-bit packing enable */
+} ADI_SPORT_CTL_A_PACK;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_GCLKEN
+ *! \brief  Gated Clock Enable (GCLKEN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_GCLK_DIS = 0,  /**< Disable */
+  SPORT_CTL_A_CTL_GCLK_EN  = 1   /**< Enable  */
+} ADI_SPORT_CTL_A_GCLKEN;
+
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_A_SPTRAN
+ *! \brief  Serial Port Transfer Direction (SPTRAN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_A_CTL_RX = 0,  /**< Receive  */
+  SPORT_CTL_A_CTL_TX = 1   /**< Transmit */
+} ADI_SPORT_CTL_A_SPTRAN;
+
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_CTL_A_Struct
+ *! \brief  Half SPORT 'A' Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_CTL_A_t__
+typedef struct _ADI_SPORT_CTL_A_t {
+  union {
+    struct {
+      unsigned int SPEN       :  1;  /**< Serial Port Enable */
+      unsigned int FSMUXSEL   :  1;  /**< Frame Sync Multiplexer Select */
+      unsigned int CKMUXSEL   :  1;  /**< Clock Multiplexer Select */
+      unsigned int LSBF       :  1;  /**< Least-Significant Bit First */
+      unsigned int SLEN       :  5;  /**< Serial Word Length */
+      unsigned int reserved9  :  1;
+      unsigned int ICLK       :  1;  /**< Internal Clock */
+      unsigned int OPMODE     :  1;  /**< Operation mode */
+      unsigned int CKRE       :  1;  /**< Clock Rising Edge */
+      unsigned int FSR        :  1;  /**< Frame Sync Required */
+      unsigned int IFS        :  1;  /**< Internal Frame Sync */
+      unsigned int DIFS       :  1;  /**< Data-Independent Frame Sync */
+      unsigned int LFS        :  1;  /**< Active-Low Frame Sync */
+      unsigned int LAFS       :  1;  /**< Late Frame Sync */
+      unsigned int PACK       :  2;  /**< Packing Enable */
+      unsigned int FSERRMODE  :  1;  /**< Frame Sync Error Operation */
+      unsigned int GCLKEN     :  1;  /**< Gated Clock Enable */
+      unsigned int reserved22 :  3;
+      unsigned int SPTRAN     :  1;  /**< Serial Port Transfer Direction */
+      unsigned int DMAEN      :  1;  /**< DMA Enable */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_CTL_A_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_CTL_A_t__ */
+
+/*@}*/
+
+/** @defgroup DIV_A Half SPORT 'A' Divisor Register (DIV_A) Register
+ *  Half SPORT 'A' Divisor Register (DIV_A) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_DIV_A_Struct
+ *! \brief  Half SPORT 'A' Divisor Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_DIV_A_t__
+typedef struct _ADI_SPORT_DIV_A_t {
+  union {
+    struct {
+      unsigned int CLKDIV     : 16;  /**< Clock Divisor */
+      unsigned int FSDIV      :  8;  /**< Frame Sync Divisor */
+      unsigned int reserved24 :  8;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_DIV_A_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_DIV_A_t__ */
+
+/*@}*/
+
+/** @defgroup IEN_A Half SPORT A's Interrupt Enable register (IEN_A) Register
+ *  Half SPORT A's Interrupt Enable register (IEN_A) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_IEN_A_TF
+ *! \brief  Transfer Finish Interrupt Enable (TF) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_IEN_A_CTL_TXFIN_DIS = 0,  /**< Transfer finish Interrupt is disabled */
+  SPORT_IEN_A_CTL_TXFIN_EN  = 1   /**< Transfer Finish Interrupt is Enabled  */
+} ADI_SPORT_IEN_A_TF;
+
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_IEN_A_Struct
+ *! \brief  Half SPORT A's Interrupt Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_IEN_A_t__
+typedef struct _ADI_SPORT_IEN_A_t {
+  union {
+    struct {
+      unsigned int TF         :  1;  /**< Transfer Finish Interrupt Enable */
+      unsigned int DERRMSK    :  1;  /**< Data Error (Interrupt) Mask */
+      unsigned int FSERRMSK   :  1;  /**< Frame Sync Error (Interrupt) Mask */
+      unsigned int DATA       :  1;  /**< Data request interrupt to the core */
+      unsigned int SYSDATERR  :  1;  /**< Data error for system writes or reads */
+      unsigned int reserved5  : 27;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_IEN_A_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_IEN_A_t__ */
+
+/*@}*/
+
+/** @defgroup STAT_A Half SPORT 'A' Status register (STAT_A) Register
+ *  Half SPORT 'A' Status register (STAT_A) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_STAT_A_DXS
+ *! \brief  Data Transfer Buffer Status (DXS) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_STAT_A_CTL_EMPTY     = 0,  /**< Empty          */
+  SPORT_STAT_A_CTL_PART_FULL = 2,  /**< Partially full */
+  SPORT_STAT_A_CTL_FULL      = 3   /**< Full           */
+} ADI_SPORT_STAT_A_DXS;
+
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_STAT_A_Struct
+ *! \brief  Half SPORT 'A' Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_STAT_A_t__
+typedef struct _ADI_SPORT_STAT_A_t {
+  union {
+    struct {
+      unsigned int TFI        :  1;  /**< Transmit Finish Interrupt Status */
+      unsigned int DERR       :  1;  /**< Data Error Status */
+      unsigned int FSERR      :  1;  /**< Frame Sync Error Status */
+      unsigned int DATA       :  1;  /**< Data Buffer status */
+      unsigned int SYSDATERR  :  1;  /**< System Data Error Status */
+      unsigned int reserved5  :  3;
+      unsigned int DXS        :  2;  /**< Data Transfer Buffer Status */
+      unsigned int reserved10 : 22;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_STAT_A_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_STAT_A_t__ */
+
+/*@}*/
+
+/** @defgroup NUMTRAN_A Half SPORT A Number of transfers register (NUMTRAN_A) Register
+ *  Half SPORT A Number of transfers register (NUMTRAN_A) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_NUMTRAN_A_Struct
+ *! \brief  Half SPORT A Number of transfers Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_NUMTRAN_A_t__
+typedef struct _ADI_SPORT_NUMTRAN_A_t {
+  union {
+    struct {
+      unsigned int VALUE      : 12;  /**< Number of transfers (Half SPORT A) */
+      unsigned int reserved12 : 20;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_NUMTRAN_A_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_NUMTRAN_A_t__ */
+
+/*@}*/
+
+/** @defgroup CNVT_A Half SPORT 'A' CNV width (CNVT_A) Register
+ *  Half SPORT 'A' CNV width (CNVT_A) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_CNVT_A_Struct
+ *! \brief  Half SPORT 'A' CNV width Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_CNVT_A_t__
+typedef struct _ADI_SPORT_CNVT_A_t {
+  union {
+    struct {
+      unsigned int WID        :  4;  /**< CNV signal width: Half SPORT A */
+      unsigned int reserved4  :  4;
+      unsigned int POL        :  1;  /**< Polarity of the CNV signal */
+      unsigned int reserved9  :  7;
+      unsigned int CNVT2FS    :  8;  /**< CNV to FS duration: Half SPORT A */
+      unsigned int reserved24 :  8;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_CNVT_A_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_CNVT_A_t__ */
+
+/*@}*/
+
+/** @defgroup TX_A Half SPORT 'A' Tx Buffer Register (TX_A) Register
+ *  Half SPORT 'A' Tx Buffer Register (TX_A) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_TX_A_Struct
+ *! \brief  Half SPORT 'A' Tx Buffer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_TX_A_t__
+typedef struct _ADI_SPORT_TX_A_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Transmit Buffer */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_TX_A_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_TX_A_t__ */
+
+/*@}*/
+
+/** @defgroup RX_A Half SPORT 'A' Rx Buffer Register (RX_A) Register
+ *  Half SPORT 'A' Rx Buffer Register (RX_A) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_RX_A_Struct
+ *! \brief  Half SPORT 'A' Rx Buffer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_RX_A_t__
+typedef struct _ADI_SPORT_RX_A_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Receive Buffer */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_RX_A_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_RX_A_t__ */
+
+/*@}*/
+
+/** @defgroup CTL_B Half SPORT 'B' Control Register (CTL_B) Register
+ *  Half SPORT 'B' Control Register (CTL_B) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_CTL_B_PACK
+ *! \brief  Packing Enable (PACK) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_CTL_B_CTL_PACK_DIS   = 0,  /**< Disable               */
+  SPORT_CTL_B_CTL_PACK_8BIT  = 1,  /**< 8-bit packing enable  */
+  SPORT_CTL_B_CTL_PACK_16BIT = 2   /**< 16-bit packing enable */
+} ADI_SPORT_CTL_B_PACK;
+
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_CTL_B_Struct
+ *! \brief  Half SPORT 'B' Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_CTL_B_t__
+typedef struct _ADI_SPORT_CTL_B_t {
+  union {
+    struct {
+      unsigned int SPEN       :  1;  /**< Serial Port Enable */
+      unsigned int reserved1  :  2;
+      unsigned int LSBF       :  1;  /**< Least-Significant Bit First */
+      unsigned int SLEN       :  5;  /**< Serial Word Length */
+      unsigned int reserved9  :  1;
+      unsigned int ICLK       :  1;  /**< Internal Clock */
+      unsigned int OPMODE     :  1;  /**< Operation mode */
+      unsigned int CKRE       :  1;  /**< Clock Rising Edge */
+      unsigned int FSR        :  1;  /**< Frame Sync Required */
+      unsigned int IFS        :  1;  /**< Internal Frame Sync */
+      unsigned int DIFS       :  1;  /**< Data-Independent Frame Sync */
+      unsigned int LFS        :  1;  /**< Active-Low Frame Sync */
+      unsigned int LAFS       :  1;  /**< Late Frame Sync */
+      unsigned int PACK       :  2;  /**< Packing Enable */
+      unsigned int FSERRMODE  :  1;  /**< Frame Sync Error Operation */
+      unsigned int GCLKEN     :  1;  /**< Gated Clock Enable */
+      unsigned int reserved22 :  3;
+      unsigned int SPTRAN     :  1;  /**< Serial Port Transfer Direction */
+      unsigned int DMAEN      :  1;  /**< DMA Enable */
+      unsigned int reserved27 :  5;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_CTL_B_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_CTL_B_t__ */
+
+/*@}*/
+
+/** @defgroup DIV_B Half SPORT 'B' Divisor Register (DIV_B) Register
+ *  Half SPORT 'B' Divisor Register (DIV_B) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_DIV_B_Struct
+ *! \brief  Half SPORT 'B' Divisor Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_DIV_B_t__
+typedef struct _ADI_SPORT_DIV_B_t {
+  union {
+    struct {
+      unsigned int CLKDIV     : 16;  /**< Clock Divisor */
+      unsigned int FSDIV      :  8;  /**< Frame Sync Divisor */
+      unsigned int reserved24 :  8;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_DIV_B_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_DIV_B_t__ */
+
+/*@}*/
+
+/** @defgroup IEN_B Half SPORT B's Interrupt Enable register (IEN_B) Register
+ *  Half SPORT B's Interrupt Enable register (IEN_B) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_IEN_B_TF
+ *! \brief  Transmit Finish Interrupt Enable (TF) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_IEN_B_CTL_TXFIN_DIS = 0,  /**< Transfer Finish Interrupt is disabled */
+  SPORT_IEN_B_CTL_TXFIN_EN  = 1   /**< Transfer Finish Interrupt is Enabled  */
+} ADI_SPORT_IEN_B_TF;
+
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_IEN_B_Struct
+ *! \brief  Half SPORT B's Interrupt Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_IEN_B_t__
+typedef struct _ADI_SPORT_IEN_B_t {
+  union {
+    struct {
+      unsigned int TF         :  1;  /**< Transmit Finish Interrupt Enable */
+      unsigned int DERRMSK    :  1;  /**< Data Error (Interrupt) Mask */
+      unsigned int FSERRMSK   :  1;  /**< Frame Sync Error (Interrupt) Mask */
+      unsigned int DATA       :  1;  /**< Data request interrupt to the core */
+      unsigned int SYSDATERR  :  1;  /**< Data error for system writes or reads */
+      unsigned int reserved5  : 27;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_IEN_B_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_IEN_B_t__ */
+
+/*@}*/
+
+/** @defgroup STAT_B Half SPORT 'B' Status register (STAT_B) Register
+ *  Half SPORT 'B' Status register (STAT_B) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_SPORT_STAT_B_DXS
+ *! \brief  Data Transfer Buffer Status (DXS) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  SPORT_STAT_B_CTL_EMPTY     = 0,  /**< Empty          */
+  SPORT_STAT_B_CTL_PART_FULL = 2,  /**< Partially full */
+  SPORT_STAT_B_CTL_FULL      = 3   /**< Full           */
+} ADI_SPORT_STAT_B_DXS;
+
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_STAT_B_Struct
+ *! \brief  Half SPORT 'B' Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_STAT_B_t__
+typedef struct _ADI_SPORT_STAT_B_t {
+  union {
+    struct {
+      unsigned int TFI        :  1;  /**< Transmit Finish Interrupt Status */
+      unsigned int DERR       :  1;  /**< Data Error Status */
+      unsigned int FSERR      :  1;  /**< Frame Sync Error Status */
+      unsigned int DATA       :  1;  /**< Data Buffer status */
+      unsigned int SYSDATERR  :  1;  /**< System Data Error Status */
+      unsigned int reserved5  :  3;
+      unsigned int DXS        :  2;  /**< Data Transfer Buffer Status */
+      unsigned int reserved10 : 22;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_STAT_B_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_STAT_B_t__ */
+
+/*@}*/
+
+/** @defgroup NUMTRAN_B Half SPORT B Number of transfers register (NUMTRAN_B) Register
+ *  Half SPORT B Number of transfers register (NUMTRAN_B) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_NUMTRAN_B_Struct
+ *! \brief  Half SPORT B Number of transfers Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_NUMTRAN_B_t__
+typedef struct _ADI_SPORT_NUMTRAN_B_t {
+  union {
+    struct {
+      unsigned int VALUE      : 12;  /**< Number of transfers (Half SPORT A) */
+      unsigned int reserved12 : 20;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_NUMTRAN_B_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_NUMTRAN_B_t__ */
+
+/*@}*/
+
+/** @defgroup CNVT_B Half SPORT 'B' CNV width register (CNVT_B) Register
+ *  Half SPORT 'B' CNV width register (CNVT_B) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_CNVT_B_Struct
+ *! \brief  Half SPORT 'B' CNV width Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_CNVT_B_t__
+typedef struct _ADI_SPORT_CNVT_B_t {
+  union {
+    struct {
+      unsigned int WID        :  4;  /**< CNV signal width: Half SPORT B */
+      unsigned int reserved4  :  4;
+      unsigned int POL        :  1;  /**< Polarity of the CNV signal */
+      unsigned int reserved9  :  7;
+      unsigned int CNVT2FS    :  8;  /**< CNV to FS duration: Half SPORT B */
+      unsigned int reserved24 :  8;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_CNVT_B_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_CNVT_B_t__ */
+
+/*@}*/
+
+/** @defgroup TX_B Half SPORT 'B' Tx Buffer Register (TX_B) Register
+ *  Half SPORT 'B' Tx Buffer Register (TX_B) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_TX_B_Struct
+ *! \brief  Half SPORT 'B' Tx Buffer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_TX_B_t__
+typedef struct _ADI_SPORT_TX_B_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Transmit Buffer */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_TX_B_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_TX_B_t__ */
+
+/*@}*/
+
+/** @defgroup RX_B Half SPORT 'B' Rx Buffer Register (RX_B) Register
+ *  Half SPORT 'B' Rx Buffer Register (RX_B) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPORT_RX_B_Struct
+ *! \brief  Half SPORT 'B' Rx Buffer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_RX_B_t__
+typedef struct _ADI_SPORT_RX_B_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Receive Buffer */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_SPORT_RX_B_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_RX_B_t__ */
+
+/*@}*/
+
+/** @defgroup CTL CRC Control (CTL) Register
+ *  CRC Control (CTL) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_CRC_CTL_EN
+ *! \brief  CRC Peripheral Enable (EN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CRC_CTL_CRC_DIS = 0,  /**< CRC peripheral is disabled */
+  CRC_CTL_CRC_EN  = 1   /**< CRC peripheral is enabled  */
+} ADI_CRC_CTL_EN;
+
+
+/*  =========================================================================
+ *! \enum   ADI_CRC_CTL_LSBFIRST
+ *! \brief  LSB First Calculation Order (LSBFIRST) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CRC_CTL_MSB_FIRST = 0,  /**< MSB First CRC calculation is done */
+  CRC_CTL_LSB_FIRST = 1   /**< LSB First CRC calculation is done */
+} ADI_CRC_CTL_LSBFIRST;
+
+
+/*  =========================================================================
+ *! \enum   ADI_CRC_CTL_BITMIRR
+ *! \brief  Bit Mirroring (BITMIRR) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CRC_CTL_BITMIRR_DIS = 0,  /**< Bit Mirroring is disabled */
+  CRC_CTL_BITMIRR_EN  = 1   /**< Bit Mirroring is enabled  */
+} ADI_CRC_CTL_BITMIRR;
+
+
+/*  =========================================================================
+ *! \enum   ADI_CRC_CTL_BYTMIRR
+ *! \brief  Byte Mirroring (BYTMIRR) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CRC_CTL_BYTEMIR_DIS = 0,  /**< Byte Mirroring is disabled */
+  CRC_CTL_BYTEMIR_EN  = 1   /**< Byte Mirroring is enabled  */
+} ADI_CRC_CTL_BYTMIRR;
+
+
+/*  =========================================================================
+ *! \enum   ADI_CRC_CTL_W16SWP
+ *! \brief  Word16 Swap (W16SWP) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CRC_CTL_W16SP_DIS = 0,  /**< Word16 Swap disabled */
+  CRC_CTL_W16SP_EN  = 1   /**< Word16 Swap enabled  */
+} ADI_CRC_CTL_W16SWP;
+
+
+/* ==========================================================================
+ *! \struct ADI_CRC_CTL_Struct
+ *! \brief  CRC Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_CTL_t__
+typedef struct _ADI_CRC_CTL_t {
+  union {
+    struct {
+      unsigned int EN         :  1;  /**< CRC Peripheral Enable */
+      unsigned int LSBFIRST   :  1;  /**< LSB First Calculation Order */
+      unsigned int BITMIRR    :  1;  /**< Bit Mirroring */
+      unsigned int BYTMIRR    :  1;  /**< Byte Mirroring */
+      unsigned int W16SWP     :  1;  /**< Word16 Swap */
+      unsigned int reserved5  : 23;
+      unsigned int RevID      :  4;  /**< Revision ID */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRC_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup IPDATA Input Data Word (IPDATA) Register
+ *  Input Data Word (IPDATA) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRC_IPDATA_Struct
+ *! \brief  Input Data Word Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_IPDATA_t__
+typedef struct _ADI_CRC_IPDATA_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Data Input */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRC_IPDATA_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_IPDATA_t__ */
+
+/*@}*/
+
+/** @defgroup RESULT CRC Result (RESULT) Register
+ *  CRC Result (RESULT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRC_RESULT_Struct
+ *! \brief  CRC Result Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_RESULT_t__
+typedef struct _ADI_CRC_RESULT_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< CRC Residue */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRC_RESULT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_RESULT_t__ */
+
+/*@}*/
+
+/** @defgroup POLY Programmable CRC Polynomial (POLY) Register
+ *  Programmable CRC Polynomial (POLY) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRC_POLY_Struct
+ *! \brief  Programmable CRC Polynomial Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_POLY_t__
+typedef struct _ADI_CRC_POLY_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< CRC Reduction Polynomial */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRC_POLY_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_POLY_t__ */
+
+/*@}*/
+
+/** @defgroup IPBITS Input Data Bits (IPBITS) Register
+ *  Input Data Bits (IPBITS) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRC_IPBITS_Struct
+ *! \brief  Input Data Bits Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_IPBITS_t__
+typedef struct _ADI_CRC_IPBITS_t {
+  union {
+    struct {
+      unsigned int DATA_BITS  :  8;  /**< Input Data Bits */
+    };
+    uint8_t VALUE8;
+  };
+} ADI_CRC_IPBITS_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_IPBITS_t__ */
+
+/*@}*/
+
+/** @defgroup IPBYTE Input Data Byte (IPBYTE) Register
+ *  Input Data Byte (IPBYTE) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRC_IPBYTE_Struct
+ *! \brief  Input Data Byte Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_IPBYTE_t__
+typedef struct _ADI_CRC_IPBYTE_t {
+  union {
+    struct {
+      unsigned int DATA_BYTE  :  8;  /**< Input Data Byte */
+    };
+    uint8_t VALUE8;
+  };
+} ADI_CRC_IPBYTE_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_IPBYTE_t__ */
+
+/*@}*/
+
+/** @defgroup CTL RNG Control Register (CTL) Register
+ *  RNG Control Register (CTL) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_RNG_CTL_EN
+ *! \brief  RNG Enable (EN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  RNG_CTL_DISABLE = 0,  /**< Disable the RNG */
+  RNG_CTL_ENABLE  = 1   /**< Enable the RNG  */
+} ADI_RNG_CTL_EN;
+
+
+/*  =========================================================================
+ *! \enum   ADI_RNG_CTL_SINGLE
+ *! \brief  Generate a Single Number (SINGLE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  RNG_CTL_WORD   = 0,  /**< Buffer Word */
+  RNG_CTL_SINGLE = 1   /**< Single Byte */
+} ADI_RNG_CTL_SINGLE;
+
+
+/* ==========================================================================
+ *! \struct ADI_RNG_CTL_Struct
+ *! \brief  RNG Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_CTL_t__
+typedef struct _ADI_RNG_CTL_t {
+  union {
+    struct {
+      unsigned int EN         :  1;  /**< RNG Enable */
+      unsigned int reserved1  :  2;
+      unsigned int SINGLE     :  1;  /**< Generate a Single Number */
+      unsigned int reserved4  : 12;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RNG_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup LEN RNG Sample Length Register (LEN) Register
+ *  RNG Sample Length Register (LEN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RNG_LEN_Struct
+ *! \brief  RNG Sample Length Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_LEN_t__
+typedef struct _ADI_RNG_LEN_t {
+  union {
+    struct {
+      unsigned int RELOAD     : 12;  /**< Reload Value for the Sample Counter */
+      unsigned int PRESCALE   :  4;  /**< Prescaler for the Sample Counter */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RNG_LEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_LEN_t__ */
+
+/*@}*/
+
+/** @defgroup STAT RNG Status Register (STAT) Register
+ *  RNG Status Register (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RNG_STAT_Struct
+ *! \brief  RNG Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_STAT_t__
+typedef struct _ADI_RNG_STAT_t {
+  union {
+    struct {
+      unsigned int RNRDY      :  1;  /**< Random Number Ready */
+      unsigned int STUCK      :  1;  /**< Sampled Data Stuck High or Low */
+      unsigned int reserved2  : 14;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_RNG_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup DATA RNG Data Register (DATA) Register
+ *  RNG Data Register (DATA) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RNG_DATA_Struct
+ *! \brief  RNG Data Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_DATA_t__
+typedef struct _ADI_RNG_DATA_t {
+  union {
+    struct {
+      unsigned int VALUE      :  8;  /**< Value of the CRC Accumulator */
+      unsigned int BUFF       : 24;  /**< Buffer for RNG Data */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_RNG_DATA_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_DATA_t__ */
+
+/*@}*/
+
+/** @defgroup OSCCNT Oscillator Count (OSCCNT) Register
+ *  Oscillator Count (OSCCNT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RNG_OSCCNT_Struct
+ *! \brief  Oscillator Count Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_OSCCNT_t__
+typedef struct _ADI_RNG_OSCCNT_t {
+  union {
+    struct {
+      unsigned int VALUE      : 28;  /**< Oscillator Count */
+      unsigned int reserved28 :  4;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_RNG_OSCCNT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_OSCCNT_t__ */
+
+/*@}*/
+
+/** @defgroup OSCDIFF Oscillator Difference (OSCDIFF) Register
+ *  Oscillator Difference (OSCDIFF) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_RNG_OSCDIFF_Struct
+ *! \brief  Oscillator Difference Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_OSCDIFF_t__
+typedef struct _ADI_RNG_OSCDIFF_t {
+  union {
+    struct {
+      signed int DELTA      :  8;  /**< Oscillator Count Difference */
+    };
+    int8_t VALUE8;
+  };
+} ADI_RNG_OSCDIFF_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_OSCDIFF_t__ */
+
+/*@}*/
+
+/** @defgroup CFG Configuration Register (CFG) Register
+ *  Configuration Register (CFG) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_CRYPT_CFG_BLKEN
+ *! \brief  Enable Bit for Crypto Block (BLKEN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CRYPT_CFG_ENABLE  = 0,  /**< Enable Crypto Block  */
+  CRYPT_CFG_DISABLE = 1   /**< Disable Crypto Block */
+} ADI_CRYPT_CFG_BLKEN;
+
+
+/*  =========================================================================
+ *! \enum   ADI_CRYPT_CFG_INDMAEN
+ *! \brief  Enable DMA Channel Request for Input Buffer (INDMAEN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CRYPT_CFG_DMA_DISABLE_INBUF = 0,  /**< Disable DMA Requesting for Input Buffer */
+  CRYPT_CFG_DMA_ENABLE_INBUF  = 1   /**< Enable DMA Requesting for Input Buffer  */
+} ADI_CRYPT_CFG_INDMAEN;
+
+
+/*  =========================================================================
+ *! \enum   ADI_CRYPT_CFG_OUTDMAEN
+ *! \brief  Enable DMA Channel Request for Output Buffer (OUTDMAEN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CRYPT_CFG_DMA_DISABLE_OUTBUF = 0,  /**< Disable DMA Requesting for Output Buffer */
+  CRYPT_CFG_DMA_ENABLE_OUTBUF  = 1   /**< Enable DMA Requesting for Output Buffer  */
+} ADI_CRYPT_CFG_OUTDMAEN;
+
+
+/*  =========================================================================
+ *! \enum   ADI_CRYPT_CFG_AESKEYLEN
+ *! \brief  Select Key Length for AES Cipher (AESKEYLEN) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CRYPT_CFG_AESKEYLEN128 = 0,  /**< Uses 128-bit long key */
+  CRYPT_CFG_AESKEYLEN256 = 2   /**< Uses 256-bit long key */
+} ADI_CRYPT_CFG_AESKEYLEN;
+
+
+/*  =========================================================================
+ *! \enum   ADI_CRYPT_CFG_KUWKeyLen
+ *! \brief  Key Length  Key Wrap Unwrap (KUWKeyLen) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  CRYPT_CFG_LEN128 = 1,  /**< The key size of KUW key is 128 bits */
+  CRYPT_CFG_LEN256 = 2,  /**< The key size of KUW key is 256 bits */
+  CRYPT_CFG_LEN512 = 3   /**< The key size of KUW key is 512 bits */
+} ADI_CRYPT_CFG_KUWKeyLen;
+
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_CFG_Struct
+ *! \brief  Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_CFG_t__
+typedef struct _ADI_CRYPT_CFG_t {
+  union {
+    struct {
+      unsigned int BLKEN      :  1;  /**< Enable Bit for Crypto Block */
+      unsigned int ENCR       :  1;  /**< Encrypt or Decrypt */
+      unsigned int INDMAEN    :  1;  /**< Enable DMA Channel Request for Input Buffer */
+      unsigned int OUTDMAEN   :  1;  /**< Enable DMA Channel Request for Output Buffer */
+      unsigned int INFLUSH    :  1;  /**< Input Buffer Flush */
+      unsigned int OUTFLUSH   :  1;  /**< Output Buffer Flush */
+      unsigned int reserved6  :  2;
+      unsigned int AESKEYLEN  :  2;  /**< Select Key Length for AES Cipher */
+      unsigned int KUWKeyLen  :  2;  /**< Key Length  Key Wrap Unwrap */
+      unsigned int AES_BYTESWAP :  1;  /**< Byteswap for AES Input */
+      unsigned int SHA_BYTESWAP :  1;  /**< Enable Key Wrap */
+      unsigned int KEY_BYTESWAP :  1;  /**< Use Key Unwrap Before HMAC */
+      unsigned int PRKSTOREN    :  1;  /**< Enable PRKSTOR Commands */
+      unsigned int ECBEN        :  1;  /**< Enable ECB Mode Operation */
+      unsigned int CTREN        :  1;  /**< Enable CTR Mode Operation */
+      unsigned int CBCEN        :  1;  /**< Enable CBC Mode Operation */
+      unsigned int CCMEN        :  1;  /**< Enable CCM/CCM* Mode Operation */
+      unsigned int CMACEN       :  1;  /**< Enable CMAC Mode Operation */
+      unsigned int HMACEN       :  1;  /**< HMAC Enable */
+      unsigned int reserved22   :  3;
+      unsigned int SHA256EN     :  1;  /**< Enable SHA-256 Operation */
+      unsigned int SHAINIT      :  1;  /**< Restarts SHA Computation */
+      unsigned int reserved27   :  1;
+      unsigned int RevID        :  4;  /**< Rev ID for Crypto */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_CFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_CFG_t__ */
+
+/*@}*/
+
+/** @defgroup DATALEN Payload Data Length (DATALEN) Register
+ *  Payload Data Length (DATALEN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_DATALEN_Struct
+ *! \brief  Payload Data Length Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_DATALEN_t__
+typedef struct _ADI_CRYPT_DATALEN_t {
+  union {
+    struct {
+      unsigned int VALUE      : 20;  /**< Length of Payload Data */
+      unsigned int reserved20 : 12;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_DATALEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_DATALEN_t__ */
+
+/*@}*/
+
+/** @defgroup PREFIXLEN Authentication Data Length (PREFIXLEN) Register
+ *  Authentication Data Length (PREFIXLEN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_PREFIXLEN_Struct
+ *! \brief  Authentication Data Length Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_PREFIXLEN_t__
+typedef struct _ADI_CRYPT_PREFIXLEN_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Length of Associated Data */
+      unsigned int reserved16 : 16;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_PREFIXLEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_PREFIXLEN_t__ */
+
+/*@}*/
+
+/** @defgroup INTEN Interrupt Enable Register (INTEN) Register
+ *  Interrupt Enable Register (INTEN) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_INTEN_Struct
+ *! \brief  Interrupt Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_INTEN_t__
+typedef struct _ADI_CRYPT_INTEN_t {
+  union {
+    struct {
+      unsigned int INRDYEN    :  1;  /**< Enable Input Ready Interrupt */
+      unsigned int OUTRDYEN   :  1;  /**< Enables the Output Ready Interrupt */
+      unsigned int INOVREN    :  1;  /**< Enable Input Overflow Interrupt */
+      unsigned int reserved3  :  2;
+      unsigned int SHADONEN   :  1;  /**< Enable SHA_Done Interrupt */
+      unsigned int HMACDONEEN :  1;  /**< Interrupt Enable for HMAC Done */
+      unsigned int HMACMSGRDYEN :  1;  /**< Status Bit for HMAC Message Input Ready */
+      unsigned int PRKSTRCMDONEEN :  1;  /**< PRKSTOR CMD DONE INTEN */
+      unsigned int reserved9      : 23;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_INTEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_INTEN_t__ */
+
+/*@}*/
+
+/** @defgroup STAT Status Register (STAT) Register
+ *  Status Register (STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_STAT_Struct
+ *! \brief  Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_STAT_t__
+typedef struct _ADI_CRYPT_STAT_t {
+  union {
+    struct {
+      unsigned int INRDY      :  1;  /**< Input Buffer Status */
+      unsigned int OUTRDY     :  1;  /**< Output Data Ready */
+      unsigned int INOVR      :  1;  /**< Overflow in the Input Buffer */
+      unsigned int reserved3  :  2;
+      unsigned int SHADONE    :  1;  /**< SHA Computation Complete */
+      unsigned int SHABUSY    :  1;  /**< SHA Busy. in Computation */
+      unsigned int INWORDS    :  3;  /**< Number of Words in the Input Buffer */
+      unsigned int OUTWORDS   :  3;  /**< Number of Words in the Output Buffer */
+      unsigned int HMACBUSY   :  1;  /**< Status Bit Indicates HMAC Busy */
+      unsigned int HMACDONE   :  1;  /**< Status Bit Indicates HMAC Done */
+      unsigned int HMACMSGRDY :  1;  /**< Status Bit Indicates HMAC is Message Ready */
+      unsigned int reserved16       :  7;
+      unsigned int PRKSTOR_CMD_DONE :  1;  /**< Indicates Command Done for PrKStor */
+      unsigned int PRKSTOR_CMD_FAIL :  1;  /**< Indicates Last Command Issued Failed */
+      unsigned int PRKSTOR_RET_STATUS :  2;  /**< ECC Errors in the PRKSTOR_RETRIEVE Command */
+      unsigned int CMD_ISSUED         :  4;  /**< Last Command Issued to PrKStor; */
+      unsigned int PRKSTOR_BUSY       :  1;  /**< Indicates PrKSTOR is Busy */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup INBUF Input Buffer (INBUF) Register
+ *  Input Buffer (INBUF) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_INBUF_Struct
+ *! \brief  Input Buffer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_INBUF_t__
+typedef struct _ADI_CRYPT_INBUF_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Input Buffer */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_INBUF_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_INBUF_t__ */
+
+/*@}*/
+
+/** @defgroup OUTBUF Output Buffer (OUTBUF) Register
+ *  Output Buffer (OUTBUF) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_OUTBUF_Struct
+ *! \brief  Output Buffer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_OUTBUF_t__
+typedef struct _ADI_CRYPT_OUTBUF_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Output Buffer */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_OUTBUF_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_OUTBUF_t__ */
+
+/*@}*/
+
+/** @defgroup NONCE0 Nonce Bits [31:0] (NONCE0) Register
+ *  Nonce Bits [31:0] (NONCE0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_NONCE0_Struct
+ *! \brief  Nonce Bits [31:0] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE0_t__
+typedef struct _ADI_CRYPT_NONCE0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Word 0: Nonce Bits [31:0] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_NONCE0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE0_t__ */
+
+/*@}*/
+
+/** @defgroup NONCE1 Nonce Bits [63:32] (NONCE1) Register
+ *  Nonce Bits [63:32] (NONCE1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_NONCE1_Struct
+ *! \brief  Nonce Bits [63:32] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE1_t__
+typedef struct _ADI_CRYPT_NONCE1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Word 1: Nonce Bits [63:32] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_NONCE1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE1_t__ */
+
+/*@}*/
+
+/** @defgroup NONCE2 Nonce Bits [95:64] (NONCE2) Register
+ *  Nonce Bits [95:64] (NONCE2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_NONCE2_Struct
+ *! \brief  Nonce Bits [95:64] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE2_t__
+typedef struct _ADI_CRYPT_NONCE2_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Word 2: Nonce Bits [95:64] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_NONCE2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE2_t__ */
+
+/*@}*/
+
+/** @defgroup NONCE3 Nonce Bits [127:96] (NONCE3) Register
+ *  Nonce Bits [127:96] (NONCE3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_NONCE3_Struct
+ *! \brief  Nonce Bits [127:96] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE3_t__
+typedef struct _ADI_CRYPT_NONCE3_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Word 3: Nonce Bits [127:96] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_NONCE3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE3_t__ */
+
+/*@}*/
+
+/** @defgroup AESKEY0 AES Key Bits [31:0] (AESKEY0) Register
+ *  AES Key Bits [31:0] (AESKEY0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_AESKEY0_Struct
+ *! \brief  AES Key Bits [31:0] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY0_t__
+typedef struct _ADI_CRYPT_AESKEY0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Key: Bytes [3:0] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_AESKEY0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY0_t__ */
+
+/*@}*/
+
+/** @defgroup AESKEY1 AES Key Bits [63:32] (AESKEY1) Register
+ *  AES Key Bits [63:32] (AESKEY1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_AESKEY1_Struct
+ *! \brief  AES Key Bits [63:32] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY1_t__
+typedef struct _ADI_CRYPT_AESKEY1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Key: Bytes [7:4] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_AESKEY1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY1_t__ */
+
+/*@}*/
+
+/** @defgroup AESKEY2 AES Key Bits [95:64] (AESKEY2) Register
+ *  AES Key Bits [95:64] (AESKEY2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_AESKEY2_Struct
+ *! \brief  AES Key Bits [95:64] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY2_t__
+typedef struct _ADI_CRYPT_AESKEY2_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Key: Bytes [11:8] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_AESKEY2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY2_t__ */
+
+/*@}*/
+
+/** @defgroup AESKEY3 AES Key Bits [127:96] (AESKEY3) Register
+ *  AES Key Bits [127:96] (AESKEY3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_AESKEY3_Struct
+ *! \brief  AES Key Bits [127:96] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY3_t__
+typedef struct _ADI_CRYPT_AESKEY3_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Key: Bytes [15:12] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_AESKEY3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY3_t__ */
+
+/*@}*/
+
+/** @defgroup AESKEY4 AES Key Bits [159:128] (AESKEY4) Register
+ *  AES Key Bits [159:128] (AESKEY4) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_AESKEY4_Struct
+ *! \brief  AES Key Bits [159:128] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY4_t__
+typedef struct _ADI_CRYPT_AESKEY4_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Key: Bytes [19:16] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_AESKEY4_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY4_t__ */
+
+/*@}*/
+
+/** @defgroup AESKEY5 AES Key Bits [191:160] (AESKEY5) Register
+ *  AES Key Bits [191:160] (AESKEY5) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_AESKEY5_Struct
+ *! \brief  AES Key Bits [191:160] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY5_t__
+typedef struct _ADI_CRYPT_AESKEY5_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Key: Bytes [23:20] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_AESKEY5_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY5_t__ */
+
+/*@}*/
+
+/** @defgroup AESKEY6 AES Key Bits [223:192] (AESKEY6) Register
+ *  AES Key Bits [223:192] (AESKEY6) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_AESKEY6_Struct
+ *! \brief  AES Key Bits [223:192] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY6_t__
+typedef struct _ADI_CRYPT_AESKEY6_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Key: Bytes [27:24] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_AESKEY6_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY6_t__ */
+
+/*@}*/
+
+/** @defgroup AESKEY7 AES Key Bits [255:224] (AESKEY7) Register
+ *  AES Key Bits [255:224] (AESKEY7) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_AESKEY7_Struct
+ *! \brief  AES Key Bits [255:224] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY7_t__
+typedef struct _ADI_CRYPT_AESKEY7_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Key: Bytes [31:28] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_AESKEY7_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY7_t__ */
+
+/*@}*/
+
+/** @defgroup CNTRINIT Counter Initialization Vector (CNTRINIT) Register
+ *  Counter Initialization Vector (CNTRINIT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_CNTRINIT_Struct
+ *! \brief  Counter Initialization Vector Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_CNTRINIT_t__
+typedef struct _ADI_CRYPT_CNTRINIT_t {
+  union {
+    struct {
+      unsigned int VALUE      : 20;  /**< Counter Initialization Value */
+      unsigned int reserved20 : 12;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_CNTRINIT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_CNTRINIT_t__ */
+
+/*@}*/
+
+/** @defgroup SHAH0 SHA Bits [31:0] (SHAH0) Register
+ *  SHA Bits [31:0] (SHAH0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_SHAH0_Struct
+ *! \brief  SHA Bits [31:0] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH0_t__
+typedef struct _ADI_CRYPT_SHAH0_t {
+  union {
+    struct {
+      unsigned int SHAHASH0   : 32;  /**< Word 0: SHA Hash */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_SHAH0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH0_t__ */
+
+/*@}*/
+
+/** @defgroup SHAH1 SHA Bits [63:32] (SHAH1) Register
+ *  SHA Bits [63:32] (SHAH1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_SHAH1_Struct
+ *! \brief  SHA Bits [63:32] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH1_t__
+typedef struct _ADI_CRYPT_SHAH1_t {
+  union {
+    struct {
+      unsigned int SHAHASH1   : 32;  /**< Word 1: SHA Hash */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_SHAH1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH1_t__ */
+
+/*@}*/
+
+/** @defgroup SHAH2 SHA Bits [95:64] (SHAH2) Register
+ *  SHA Bits [95:64] (SHAH2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_SHAH2_Struct
+ *! \brief  SHA Bits [95:64] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH2_t__
+typedef struct _ADI_CRYPT_SHAH2_t {
+  union {
+    struct {
+      unsigned int SHAHASH2   : 32;  /**< Word 2: SHA Hash */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_SHAH2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH2_t__ */
+
+/*@}*/
+
+/** @defgroup SHAH3 SHA Bits [127:96] (SHAH3) Register
+ *  SHA Bits [127:96] (SHAH3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_SHAH3_Struct
+ *! \brief  SHA Bits [127:96] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH3_t__
+typedef struct _ADI_CRYPT_SHAH3_t {
+  union {
+    struct {
+      unsigned int SHAHASH3   : 32;  /**< Word 3: SHA Hash */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_SHAH3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH3_t__ */
+
+/*@}*/
+
+/** @defgroup SHAH4 SHA Bits [159:128] (SHAH4) Register
+ *  SHA Bits [159:128] (SHAH4) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_SHAH4_Struct
+ *! \brief  SHA Bits [159:128] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH4_t__
+typedef struct _ADI_CRYPT_SHAH4_t {
+  union {
+    struct {
+      unsigned int SHAHASH4   : 32;  /**< Word 4: SHA Hash */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_SHAH4_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH4_t__ */
+
+/*@}*/
+
+/** @defgroup SHAH5 SHA Bits [191:160] (SHAH5) Register
+ *  SHA Bits [191:160] (SHAH5) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_SHAH5_Struct
+ *! \brief  SHA Bits [191:160] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH5_t__
+typedef struct _ADI_CRYPT_SHAH5_t {
+  union {
+    struct {
+      unsigned int SHAHASH5   : 32;  /**< Word 5: SHA Hash */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_SHAH5_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH5_t__ */
+
+/*@}*/
+
+/** @defgroup SHAH6 SHA Bits [223:192] (SHAH6) Register
+ *  SHA Bits [223:192] (SHAH6) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_SHAH6_Struct
+ *! \brief  SHA Bits [223:192] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH6_t__
+typedef struct _ADI_CRYPT_SHAH6_t {
+  union {
+    struct {
+      unsigned int SHAHASH6   : 32;  /**< Word 6: SHA Hash */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_SHAH6_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH6_t__ */
+
+/*@}*/
+
+/** @defgroup SHAH7 SHA Bits [255:224] (SHAH7) Register
+ *  SHA Bits [255:224] (SHAH7) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_SHAH7_Struct
+ *! \brief  SHA Bits [255:224] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH7_t__
+typedef struct _ADI_CRYPT_SHAH7_t {
+  union {
+    struct {
+      unsigned int SHAHASH7   : 32;  /**< Word 7: SHA Hash */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_SHAH7_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH7_t__ */
+
+/*@}*/
+
+/** @defgroup SHA_LAST_WORD SHA Last Word and Valid Bits Information (SHA_LAST_WORD) Register
+ *  SHA Last Word and Valid Bits Information (SHA_LAST_WORD) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_SHA_LAST_WORD_Struct
+ *! \brief  SHA Last Word and Valid Bits Information Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHA_LAST_WORD_t__
+typedef struct _ADI_CRYPT_SHA_LAST_WORD_t {
+  union {
+    struct {
+      unsigned int O_Last_Word :  1;  /**< Last SHA Input Word */
+      unsigned int O_Bits_Valid :  5;  /**< Bits Valid in SHA Last Word Input */
+      unsigned int reserved6    : 26;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_SHA_LAST_WORD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHA_LAST_WORD_t__ */
+
+/*@}*/
+
+/** @defgroup CCM_NUM_VALID_BYTES NUM_VALID_BYTES (CCM_NUM_VALID_BYTES) Register
+ *  NUM_VALID_BYTES (CCM_NUM_VALID_BYTES) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_CCM_NUM_VALID_BYTES_Struct
+ *! \brief  NUM_VALID_BYTES Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_CCM_NUM_VALID_BYTES_t__
+typedef struct _ADI_CRYPT_CCM_NUM_VALID_BYTES_t {
+  union {
+    struct {
+      unsigned int NUM_VALID_BYTES :  4;  /**< Number of Valid Bytes in CCM Last Data */
+      unsigned int reserved4       : 28;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_CCM_NUM_VALID_BYTES_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_CCM_NUM_VALID_BYTES_t__ */
+
+/*@}*/
+
+/** @defgroup PRKSTORCFG PRKSTOR Configuration (PRKSTORCFG) Register
+ *  PRKSTOR Configuration (PRKSTORCFG) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_PRKSTORCFG_Struct
+ *! \brief  PRKSTOR Configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_PRKSTORCFG_t__
+typedef struct _ADI_CRYPT_PRKSTORCFG_t {
+  union {
+    struct {
+      unsigned int KEY_INDEX  :  7;  /**< Index of Key in PRKSTOR */
+      unsigned int CMD        :  4;  /**< Command Input for PRKSTOR */
+      unsigned int reserved11 : 21;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_PRKSTORCFG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_PRKSTORCFG_t__ */
+
+/*@}*/
+
+/** @defgroup KUW0 Key Wrap Unwrap Register 0 (KUW0) Register
+ *  Key Wrap Unwrap Register 0 (KUW0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_KUW0_Struct
+ *! \brief  Key Wrap Unwrap Register 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW0_t__
+typedef struct _ADI_CRYPT_KUW0_t {
+  union {
+    struct {
+      unsigned int KUW0       : 32;  /**< KUW [31:0] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_KUW0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW0_t__ */
+
+/*@}*/
+
+/** @defgroup KUW1 Key Wrap Unwrap Register 1 (KUW1) Register
+ *  Key Wrap Unwrap Register 1 (KUW1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_KUW1_Struct
+ *! \brief  Key Wrap Unwrap Register 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW1_t__
+typedef struct _ADI_CRYPT_KUW1_t {
+  union {
+    struct {
+      unsigned int KUW1       : 32;  /**< KUW [63:32] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_KUW1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW1_t__ */
+
+/*@}*/
+
+/** @defgroup KUW2 Key Wrap Unwrap Register 2 (KUW2) Register
+ *  Key Wrap Unwrap Register 2 (KUW2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_KUW2_Struct
+ *! \brief  Key Wrap Unwrap Register 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW2_t__
+typedef struct _ADI_CRYPT_KUW2_t {
+  union {
+    struct {
+      unsigned int KUW2       : 32;  /**< KUW [95:64] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_KUW2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW2_t__ */
+
+/*@}*/
+
+/** @defgroup KUW3 Key Wrap Unwrap Register 3 (KUW3) Register
+ *  Key Wrap Unwrap Register 3 (KUW3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_KUW3_Struct
+ *! \brief  Key Wrap Unwrap Register 3 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW3_t__
+typedef struct _ADI_CRYPT_KUW3_t {
+  union {
+    struct {
+      unsigned int KUW3       : 32;  /**< KUW [127:96] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_KUW3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW3_t__ */
+
+/*@}*/
+
+/** @defgroup KUW4 Key Wrap Unwrap Register 4 (KUW4) Register
+ *  Key Wrap Unwrap Register 4 (KUW4) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_KUW4_Struct
+ *! \brief  Key Wrap Unwrap Register 4 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW4_t__
+typedef struct _ADI_CRYPT_KUW4_t {
+  union {
+    struct {
+      unsigned int KUW4       : 32;  /**< KUW [159:128] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_KUW4_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW4_t__ */
+
+/*@}*/
+
+/** @defgroup KUW5 Key Wrap Unwrap Register 5 (KUW5) Register
+ *  Key Wrap Unwrap Register 5 (KUW5) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_KUW5_Struct
+ *! \brief  Key Wrap Unwrap Register 5 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW5_t__
+typedef struct _ADI_CRYPT_KUW5_t {
+  union {
+    struct {
+      unsigned int KUW5       : 32;  /**< KUW [191:160] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_KUW5_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW5_t__ */
+
+/*@}*/
+
+/** @defgroup KUW6 Key Wrap Unwrap Register 6 (KUW6) Register
+ *  Key Wrap Unwrap Register 6 (KUW6) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_KUW6_Struct
+ *! \brief  Key Wrap Unwrap Register 6 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW6_t__
+typedef struct _ADI_CRYPT_KUW6_t {
+  union {
+    struct {
+      unsigned int KUW6       : 32;  /**< KUW [223:192] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_KUW6_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW6_t__ */
+
+/*@}*/
+
+/** @defgroup KUW7 Key Wrap Unwrap Register 7 (KUW7) Register
+ *  Key Wrap Unwrap Register 7 (KUW7) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_KUW7_Struct
+ *! \brief  Key Wrap Unwrap Register 7 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW7_t__
+typedef struct _ADI_CRYPT_KUW7_t {
+  union {
+    struct {
+      unsigned int KUW7       : 32;  /**< KUW [255:224] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_KUW7_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW7_t__ */
+
+/*@}*/
+
+/** @defgroup KUW8 Key Wrap Unwrap Register 8 (KUW8) Register
+ *  Key Wrap Unwrap Register 8 (KUW8) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_KUW8_Struct
+ *! \brief  Key Wrap Unwrap Register 8 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW8_t__
+typedef struct _ADI_CRYPT_KUW8_t {
+  union {
+    struct {
+      unsigned int KUW8       : 32;  /**< KUW [287:256] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_KUW8_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW8_t__ */
+
+/*@}*/
+
+/** @defgroup KUW9 Key Wrap Unwrap Register 9 (KUW9) Register
+ *  Key Wrap Unwrap Register 9 (KUW9) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_KUW9_Struct
+ *! \brief  Key Wrap Unwrap Register 9 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW9_t__
+typedef struct _ADI_CRYPT_KUW9_t {
+  union {
+    struct {
+      unsigned int KUW9       : 32;  /**< KUW [319:288] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_KUW9_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW9_t__ */
+
+/*@}*/
+
+/** @defgroup KUW10 Key Wrap Unwrap Register 10 (KUW10) Register
+ *  Key Wrap Unwrap Register 10 (KUW10) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_KUW10_Struct
+ *! \brief  Key Wrap Unwrap Register 10 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW10_t__
+typedef struct _ADI_CRYPT_KUW10_t {
+  union {
+    struct {
+      unsigned int KUW10      : 32;  /**< KUW [351:320] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_KUW10_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW10_t__ */
+
+/*@}*/
+
+/** @defgroup KUW11 Key Wrap Unwrap Register 11 (KUW11) Register
+ *  Key Wrap Unwrap Register 11 (KUW11) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_KUW11_Struct
+ *! \brief  Key Wrap Unwrap Register 11 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW11_t__
+typedef struct _ADI_CRYPT_KUW11_t {
+  union {
+    struct {
+      unsigned int KUW11      : 32;  /**< KUW [383:352] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_KUW11_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW11_t__ */
+
+/*@}*/
+
+/** @defgroup KUW12 Key Wrap Unwrap Register 12 (KUW12) Register
+ *  Key Wrap Unwrap Register 12 (KUW12) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_KUW12_Struct
+ *! \brief  Key Wrap Unwrap Register 12 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW12_t__
+typedef struct _ADI_CRYPT_KUW12_t {
+  union {
+    struct {
+      unsigned int KUW12      : 32;  /**< KUW [415:384] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_KUW12_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW12_t__ */
+
+/*@}*/
+
+/** @defgroup KUW13 Key Wrap Unwrap Register 13 (KUW13) Register
+ *  Key Wrap Unwrap Register 13 (KUW13) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_KUW13_Struct
+ *! \brief  Key Wrap Unwrap Register 13 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW13_t__
+typedef struct _ADI_CRYPT_KUW13_t {
+  union {
+    struct {
+      unsigned int KUW13      : 32;  /**< KUW [447:416] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_KUW13_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW13_t__ */
+
+/*@}*/
+
+/** @defgroup KUW14 Key Wrap Unwrap Register 14 (KUW14) Register
+ *  Key Wrap Unwrap Register 14 (KUW14) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_KUW14_Struct
+ *! \brief  Key Wrap Unwrap Register 14 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW14_t__
+typedef struct _ADI_CRYPT_KUW14_t {
+  union {
+    struct {
+      unsigned int KUW14      : 32;  /**< KUW [479:448] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_KUW14_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW14_t__ */
+
+/*@}*/
+
+/** @defgroup KUW15 Key Wrap Unwrap Register 15 (KUW15) Register
+ *  Key Wrap Unwrap Register 15 (KUW15) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_KUW15_Struct
+ *! \brief  Key Wrap Unwrap Register 15 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW15_t__
+typedef struct _ADI_CRYPT_KUW15_t {
+  union {
+    struct {
+      unsigned int KUW15      : 32;  /**< KUW [511:480] */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_KUW15_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW15_t__ */
+
+/*@}*/
+
+/** @defgroup KUWValStr1 Key Wrap Unwrap Validation String [63:32] (KUWValStr1) Register
+ *  Key Wrap Unwrap Validation String [63:32] (KUWValStr1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_KUWValStr1_Struct
+ *! \brief  Key Wrap Unwrap Validation String [63:32] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUWValStr1_t__
+typedef struct _ADI_CRYPT_KUWValStr1_t {
+  union {
+    struct {
+      unsigned int InitalValue0 : 32;  /**< Initial Value */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_KUWValStr1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUWValStr1_t__ */
+
+/*@}*/
+
+/** @defgroup KUWValStr2 Key Wrap Unwrap Validation String [31:0] (KUWValStr2) Register
+ *  Key Wrap Unwrap Validation String [31:0] (KUWValStr2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CRYPT_KUWValStr2_Struct
+ *! \brief  Key Wrap Unwrap Validation String [31:0] Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUWValStr2_t__
+typedef struct _ADI_CRYPT_KUWValStr2_t {
+  union {
+    struct {
+      unsigned int InitialValue1 : 32;  /**< Initial Value */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CRYPT_KUWValStr2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUWValStr2_t__ */
+
+/*@}*/
+
+/** @defgroup IEN Power Supply Monitor Interrupt Enable (IEN) Register
+ *  Power Supply Monitor Interrupt Enable (IEN) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_PMG_IEN_RANGEBAT
+ *! \brief  Battery Monitor Range (RANGEBAT) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  PMG_IEN_REGION1 = 0,  /**< Configure to generate interrupt if VBAT in Region1 */
+  PMG_IEN_REGION2 = 1,  /**< Configure to generate interrupt if VBAT in Region2 */
+  PMG_IEN_REGION3 = 2,  /**< Configure to generate interrupt if VBAT in Region3 */
+  PMG_IEN_NA      = 3   /**< NA                                                 */
+} ADI_PMG_IEN_RANGEBAT;
+
+
+/* ==========================================================================
+ *! \struct ADI_PMG_IEN_Struct
+ *! \brief  Power Supply Monitor Interrupt Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_IEN_t__
+typedef struct _ADI_PMG_IEN_t {
+  union {
+    struct {
+      unsigned int VBAT       :  1;  /**< Enable Interrupt for VBAT */
+      unsigned int VREGUNDR   :  1;  /**< Enable Interrupt when VREG under-voltage (below 1 V) */
+      unsigned int VREGOVR    :  1;  /**< Enable Interrupt when VREG over-voltage (above 1.32 V) */
+      unsigned int reserved3  :  5;
+      unsigned int RANGEBAT   :  2;  /**< Battery Monitor Range */
+      unsigned int IENBAT     :  1;  /**< Interrupt enable for VBAT range */
+      unsigned int reserved11 : 21;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_IEN_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_IEN_t__ */
+
+/*@}*/
+
+/** @defgroup PSM_STAT Power Supply Monitor Status (PSM_STAT) Register
+ *  Power Supply Monitor Status (PSM_STAT) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_PMG_PSM_STAT_RORANGE1
+ *! \brief  VBAT range1 (RORANGE1) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  PMG_PSM_STAT_BATSTAT1 = 0,  /**< VBAT NOT in the range specified */
+  PMG_PSM_STAT_BATSTAT0 = 1   /**< VBAT in the range specified     */
+} ADI_PMG_PSM_STAT_RORANGE1;
+
+
+/* ==========================================================================
+ *! \struct ADI_PMG_PSM_STAT_Struct
+ *! \brief  Power Supply Monitor Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_PSM_STAT_t__
+typedef struct _ADI_PMG_PSM_STAT_t {
+  union {
+    struct {
+      unsigned int VBATUNDR   :  1;  /**< Status bit indicating an Alarm that battery is below 1.8 V */
+      unsigned int VREGUNDR   :  1;  /**< Status bit for Alarm indicating VREG is below 1 V */
+      unsigned int VREGOVR    :  1;  /**< Status bit for alarm indicating Over Voltage for VREG */
+      unsigned int reserved3  :  4;
+      unsigned int WICENACK   :  1;  /**< WIC Enable Acknowledge from Cortex */
+      unsigned int RANGE1     :  1;  /**< VBAT range1 */
+      unsigned int RANGE2     :  1;  /**< VBAT range2 */
+      unsigned int RANGE3     :  1;  /**< VBAT range3 */
+      unsigned int reserved11 :  2;
+      unsigned int RORANGE1   :  1;  /**< VBAT range1 */
+      unsigned int RORANGE2   :  1;  /**< VBAT range2 */
+      unsigned int RORANGE3   :  1;  /**< VBAT range3 */
+      unsigned int reserved16 : 16;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_PSM_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_PSM_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup PWRMOD Power Mode Register (PWRMOD) Register
+ *  Power Mode Register (PWRMOD) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_PMG_PWRMOD_MODE
+ *! \brief  Power Mode Bits (MODE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  PMG_PWRMOD_FLEXI     = 0,  /**< Flexi Mode     */
+  PMG_PWRMOD_HIBERNATE = 2,  /**< Hibernate Mode */
+  PMG_PWRMOD_SHUTDOWN  = 3   /**< Shutdown Mode  */
+} ADI_PMG_PWRMOD_MODE;
+
+
+/* ==========================================================================
+ *! \struct ADI_PMG_PWRMOD_Struct
+ *! \brief  Power Mode Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_PWRMOD_t__
+typedef struct _ADI_PMG_PWRMOD_t {
+  union {
+    struct {
+      unsigned int MODE       :  2;  /**< Power Mode Bits */
+      unsigned int reserved2  :  1;
+      unsigned int MONVBATN   :  1;  /**< Monitor VBAT during Hibernate Mode. Monitors VBAT by default */
+      unsigned int reserved4  : 28;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_PWRMOD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_PWRMOD_t__ */
+
+/*@}*/
+
+/** @defgroup PWRKEY Key Protection for PWRMOD and  SRAMRET (PWRKEY) Register
+ *  Key Protection for PWRMOD and  SRAMRET (PWRKEY) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PMG_PWRKEY_Struct
+ *! \brief  Key Protection for PWRMOD and  SRAMRET Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_PWRKEY_t__
+typedef struct _ADI_PMG_PWRKEY_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Power Control Key */
+      unsigned int reserved16 : 16;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_PWRKEY_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_PWRKEY_t__ */
+
+/*@}*/
+
+/** @defgroup SHDN_STAT Shutdown Status Register (SHDN_STAT) Register
+ *  Shutdown Status Register (SHDN_STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PMG_SHDN_STAT_Struct
+ *! \brief  Shutdown Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_SHDN_STAT_t__
+typedef struct _ADI_PMG_SHDN_STAT_t {
+  union {
+    struct {
+      unsigned int EXTINT0    :  1;  /**< Interrupt from External Interrupt 0 */
+      unsigned int EXTINT1    :  1;  /**< Interrupt from External Interrupt 1 */
+      unsigned int EXTINT2    :  1;  /**< Interrupt from External Interrupt 2 */
+      unsigned int RTC        :  1;  /**< Interrupt from RTC */
+      unsigned int reserved4  : 28;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_SHDN_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_SHDN_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup SRAMRET Control for Retention SRAM in Hibernate Mode (SRAMRET) Register
+ *  Control for Retention SRAM in Hibernate Mode (SRAMRET) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PMG_SRAMRET_Struct
+ *! \brief  Control for Retention SRAM in Hibernate Mode Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_SRAMRET_t__
+typedef struct _ADI_PMG_SRAMRET_t {
+  union {
+    struct {
+      unsigned int RET1       :  1;  /**< Enable retention bank 1 (12 KB) */
+      unsigned int RET2       :  1;  /**< Enable retention bank 3 and bank 4 (32 KB) */
+      unsigned int reserved2  :  6;
+      unsigned int RET3       :  1;  /**< Enable retention bank 5 (32 KB) */
+      unsigned int RET4       :  1;  /**< Enable retention bank 6 and bank 7 (32 KB) */
+      unsigned int reserved10               : 13;
+      unsigned int HIBERNATE_SRAM_LOAD_MODE :  1;  /**< Hibernate mode SRAM load mode control */
+      unsigned int reserved24               :  8;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_SRAMRET_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_SRAMRET_t__ */
+
+/*@}*/
+
+/** @defgroup TRIM Trimming Bits (TRIM) Register
+ *  Trimming Bits (TRIM) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_PMG_TRIM_hibernate_load_mode
+ *! \brief  Hibernate mode load mode control (hibernate_load_mode) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  PMG_TRIM_HIGH_LOAD = 0,  /**< High hibernate load */
+  PMG_TRIM_LOW_LOAD  = 7   /**< Low hibernate load  */
+} ADI_PMG_TRIM_hibernate_load_mode;
+
+
+/* ==========================================================================
+ *! \struct ADI_PMG_TRIM_Struct
+ *! \brief  Trimming Bits Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TRIM_t__
+typedef struct _ADI_PMG_TRIM_t {
+  union {
+    struct {
+      unsigned int reserved0           : 29;
+      unsigned int hibernate_load_mode :  3;  /**< Hibernate mode load mode control */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_TRIM_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TRIM_t__ */
+
+/*@}*/
+
+/** @defgroup RST_STAT Reset Status (RST_STAT) Register
+ *  Reset Status (RST_STAT) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_PMG_RST_STAT_PORSRC
+ *! \brief  Power on reset Source (PORSRC) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  PMG_RST_STAT_FAILSAFE_HV = 0,  /**< POR triggered because VBAT drops below Fail Safe */
+  PMG_RST_STAT_RST_VBAT    = 1,  /**< POR trigger because VBAT supply (VBAT < 1.7 V)   */
+  PMG_RST_STAT_RST_VREG    = 2,  /**< POR triggered because VDD supply (VDD < 1.08 V)  */
+  PMG_RST_STAT_FAILSAFE_LV = 3   /**< POR triggered because VREG drops below Fail Safe */
+} ADI_PMG_RST_STAT_PORSRC;
+
+
+/* ==========================================================================
+ *! \struct ADI_PMG_RST_STAT_Struct
+ *! \brief  Reset Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_RST_STAT_t__
+typedef struct _ADI_PMG_RST_STAT_t {
+  union {
+    struct {
+      unsigned int POR        :  1;  /**< Power-on reset */
+      unsigned int EXTRST     :  1;  /**< External reset */
+      unsigned int WDRST      :  1;  /**< Watchdog timeout */
+      unsigned int SWRST      :  1;  /**< Software reset */
+      unsigned int PORSRC     :  2;  /**< Power on reset Source */
+      unsigned int reserved6  : 26;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_RST_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_RST_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup CTL1 HPBUCK Control (CTL1) Register
+ *  HPBUCK Control (CTL1) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_PMG_CTL1_HPBUCK_LD_MODE
+ *! \brief  HP Buck load mode (HPBUCK_LD_MODE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  PMG_CTL1_HPBUCKLOWLOAD  = 0,  /**< HPBUCK Low load mode is enabled  */
+  PMG_CTL1_HPBUCKHIGHLOAD = 1   /**< HPBUCK High load mode is enabled */
+} ADI_PMG_CTL1_HPBUCK_LD_MODE;
+
+
+/*  =========================================================================
+ *! \enum   ADI_PMG_CTL1_HPBUCK_LOWPWR_MODE
+ *! \brief  HP Buck low power mode (HPBUCK_LOWPWR_MODE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  PMG_CTL1_LOWPWRDISABLE = 0,  /**< HPBUCK Low power mode is disabled */
+  PMG_CTL1_LOWPWRENABLE  = 1   /**< HPBUCK Low power mode is enabled  */
+} ADI_PMG_CTL1_HPBUCK_LOWPWR_MODE;
+
+
+/* ==========================================================================
+ *! \struct ADI_PMG_CTL1_Struct
+ *! \brief  HPBUCK Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_CTL1_t__
+typedef struct _ADI_PMG_CTL1_t {
+  union {
+    struct {
+      unsigned int HPBUCKEN   :  1;  /**< Enable HP Buck */
+      unsigned int HPBUCK_LD_MODE :  1;  /**< HP Buck load mode */
+      unsigned int HPBUCK_LOWPWR_MODE :  1;  /**< HP Buck low power mode */
+      unsigned int reserved3          : 29;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_CTL1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_CTL1_t__ */
+
+/*@}*/
+
+/** @defgroup CFG0 External Interrupt configuration (CFG0) Register
+ *  External Interrupt configuration (CFG0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_XINT_CFG0_Struct
+ *! \brief  External Interrupt configuration Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_CFG0_t__
+typedef struct _ADI_XINT_CFG0_t {
+  union {
+    struct {
+      unsigned int IRQ0MDE    :  3;  /**< External Interrupt 0 Mode registers */
+      unsigned int IRQ0EN     :  1;  /**< External Interrupt 0 Enable bit */
+      unsigned int IRQ1MDE    :  3;  /**< External Interrupt 1 Mode registers */
+      unsigned int IRQ1EN     :  1;  /**< External Interrupt 1 Enable bit */
+      unsigned int IRQ2MDE    :  3;  /**< External Interrupt 2 Mode registers */
+      unsigned int IRQ2EN     :  1;  /**< External Interrupt 2 Enable bit */
+      unsigned int IRQ3MDE    :  3;  /**< External Interrupt 3 Mode registers */
+      unsigned int IRQ3EN     :  1;  /**< External Interrupt 3 enable bit */
+      unsigned int reserved16 :  4;
+      unsigned int UART_RX_EN :  1;  /**< External Interrupt using SIP_UPDATE enable bit */
+      unsigned int UART_RX_MDE :  3;  /**< External Interrupt using UART_RX wakeup Mode registers */
+      unsigned int reserved24  :  8;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_XINT_CFG0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_CFG0_t__ */
+
+/*@}*/
+
+/** @defgroup EXT_STAT External Wakeup Interrupt Status register (EXT_STAT) Register
+ *  External Wakeup Interrupt Status register (EXT_STAT) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_XINT_EXT_STAT_Struct
+ *! \brief  External Wakeup Interrupt Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_EXT_STAT_t__
+typedef struct _ADI_XINT_EXT_STAT_t {
+  union {
+    struct {
+      unsigned int STAT_EXTINT0 :  1;  /**< Interrupt status bit for External Interrupt 0 */
+      unsigned int STAT_EXTINT1 :  1;  /**< Interrupt status bit for External Interrupt 1 */
+      unsigned int STAT_EXTINT2 :  1;  /**< Interrupt status bit for External Interrupt 2 */
+      unsigned int STAT_EXTINT3 :  1;  /**< Interrupt status bit for External Interrupt 3 */
+      unsigned int reserved4        :  1;
+      unsigned int STAT_UART_RXWKUP :  1;  /**< Interrupt status bit for UART RX WAKEUP interrupt */
+      unsigned int reserved6        : 26;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_XINT_EXT_STAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_EXT_STAT_t__ */
+
+/*@}*/
+
+/** @defgroup CLR External Interrupt clear (CLR) Register
+ *  External Interrupt clear (CLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_XINT_CLR_Struct
+ *! \brief  External Interrupt clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_CLR_t__
+typedef struct _ADI_XINT_CLR_t {
+  union {
+    struct {
+      unsigned int IRQ0       :  1;  /**< External interrupt 0 */
+      unsigned int IRQ1       :  1;  /**< External interrupt 1 */
+      unsigned int IRQ2       :  1;  /**< External interrupt 2 */
+      unsigned int IRQ3       :  1;  /**< External interrupt 3 */
+      unsigned int reserved4   :  1;
+      unsigned int UART_RX_CLR :  1;  /**< External interrupt Clear for UART_RX WAKEUP interrupt */
+      unsigned int reserved6   : 26;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_XINT_CLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_CLR_t__ */
+
+/*@}*/
+
+/** @defgroup NMICLR Non-maskable interrupt clear (NMICLR) Register
+ *  Non-maskable interrupt clear (NMICLR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_XINT_NMICLR_Struct
+ *! \brief  Non-maskable interrupt clear Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_NMICLR_t__
+typedef struct _ADI_XINT_NMICLR_t {
+  union {
+    struct {
+      unsigned int CLR        :  1;  /**< NMI clear */
+      unsigned int reserved1  : 31;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_XINT_NMICLR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_NMICLR_t__ */
+
+/*@}*/
+
+/** @defgroup KEY Key Protection for OSCCTRL (KEY) Register
+ *  Key Protection for OSCCTRL (KEY) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CLKG_OSC_KEY_Struct
+ *! \brief  Key Protection for OSCCTRL Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_KEY_t__
+typedef struct _ADI_CLKG_OSC_KEY_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Oscillator key */
+      unsigned int reserved16 : 16;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CLKG_OSC_KEY_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_KEY_t__ */
+
+/*@}*/
+
+/** @defgroup CTL Oscillator Control (CTL) Register
+ *  Oscillator Control (CTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CLKG_OSC_CTL_Struct
+ *! \brief  Oscillator Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_CTL_t__
+typedef struct _ADI_CLKG_OSC_CTL_t {
+  union {
+    struct {
+      unsigned int LFCLK_MUX  :  1;  /**< 32 kHz clock select mux */
+      unsigned int HFOSC_EN   :  1;  /**< High frequency internal oscillator enable */
+      unsigned int LFX_EN     :  1;  /**< Low frequency crystal oscillator enable */
+      unsigned int HFX_EN     :  1;  /**< High frequency crystal oscillator enable */
+      unsigned int LFX_BYP    :  1;  /**< Low frequency crystal oscillator Bypass */
+      unsigned int LFX_MON_EN :  1;  /**< LFXTAL clock monitor and Clock FAIL interrupt enable */
+      unsigned int reserved6  :  2;
+      unsigned int LFOSC_OK   :  1;  /**< Status of LFOSC oscillator */
+      unsigned int HFOSC_OK   :  1;  /**< Status of HFOSC oscillator */
+      unsigned int LFX_OK     :  1;  /**< Status of LFXTAL oscillator */
+      unsigned int HFX_OK     :  1;  /**< Status of HFXTAL oscillator */
+      unsigned int LFX_AUTSW_EN :  1;  /**< Enables automatic Switching of the LF Mux to LFOSC on LFXTAL Failure */
+      unsigned int LFX_AUTSW_STA :  1;  /**< Status of automatic switching of the LF Mux to LFOSC upon detection of LFXTAL failure */
+      unsigned int LFX_ROBUST_EN :  1;  /**< LFXTAL Mode select */
+      unsigned int LFX_ROBUST_LD :  2;  /**< LFXTAL Robust Mode Load select */
+      unsigned int reserved17    :  3;
+      unsigned int ROOT_MON_EN   :  1;  /**< ROOT clock monitor and Clock FAIL interrupt enable */
+      unsigned int ROOT_AUTSW_EN :  1;  /**< Enables automatic Switching of the Root clock  to HFOSC on Root clock Failure */
+      unsigned int ROOT_AUTSW_STA :  1;  /**< Status of automatic switching of the Root clock to HFOSC upon detection of Root clock failure */
+      unsigned int reserved23     :  7;
+      unsigned int ROOT_FAIL_STA  :  1;  /**< Root clock (crystal clock) Not Stable */
+      unsigned int LFX_FAIL_STA   :  1;  /**< LF XTAL (crystal clock) Not Stable */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CLKG_OSC_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup SRAM_CTL Control for SRAM Parity and Instruction SRAM (SRAM_CTL) Register
+ *  Control for SRAM Parity and Instruction SRAM (SRAM_CTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PMG_TST_SRAM_CTL_Struct
+ *! \brief  Control for SRAM Parity and Instruction SRAM Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_SRAM_CTL_t__
+typedef struct _ADI_PMG_TST_SRAM_CTL_t {
+  union {
+    struct {
+      unsigned int reserved0  :  1;
+      unsigned int BNK1EN     :  1;  /**< Enable initialization */
+      unsigned int BNK2EN     :  1;  /**< Enable initialization */
+      unsigned int reserved3  :  4;
+      unsigned int BNK7EN     :  1;  /**< Enable initialization */
+      unsigned int reserved8  :  5;
+      unsigned int STARTINIT  :  1;  /**< Write one to trigger initialization. Self-cleared */
+      unsigned int AUTOINIT   :  1;  /**< Automatic initialization on wake up from hibernate mode */
+      unsigned int ABTINIT    :  1;  /**< Abort current initialization. Self-cleared */
+      unsigned int PENBNK0    :  1;  /**< Enable parity check */
+      unsigned int PENBNK1    :  1;  /**< Enable parity check */
+      unsigned int PENBNK2    :  1;  /**< Enable parity check */
+      unsigned int PENBNK3    :  1;  /**< Enable parity check */
+      unsigned int PENBNK4    :  1;  /**< Enable parity check */
+      unsigned int PENBNK5    :  1;  /**< Enable parity check */
+      unsigned int PENBNK6    :  1;  /**< Enable parity check */
+      unsigned int PENBNK7    :  1;  /**< Enable parity check */
+      unsigned int reserved24 :  7;
+      unsigned int INSTREN    :  1;  /**< Enables 32 KB instruction SRAM */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_TST_SRAM_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_SRAM_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup SRAM_INITSTAT Initialization Status Register (SRAM_INITSTAT) Register
+ *  Initialization Status Register (SRAM_INITSTAT) Register.
+ *  @{
+ */
+
+/*  =========================================================================
+ *! \enum   ADI_PMG_TST_SRAM_INITSTAT_BNK0DONE
+ *! \brief  Bank 0 initialization status (BNK0DONE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  PMG_TST_SRAM_INITSTAT_NO_BANK0_INIT = 0,  /**< Bank 0 not initialized */
+  PMG_TST_SRAM_INITSTAT_BANK0_INIT    = 1   /**< Bank 0 initialized     */
+} ADI_PMG_TST_SRAM_INITSTAT_BNK0DONE;
+
+
+/*  =========================================================================
+ *! \enum   ADI_PMG_TST_SRAM_INITSTAT_BNK1DONE
+ *! \brief  Bank 1 initialization status (BNK1DONE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  PMG_TST_SRAM_INITSTAT_NO_BANK1_INIT = 0,  /**< Bank 1 not initialized */
+  PMG_TST_SRAM_INITSTAT_BANK1_INIT    = 1   /**< Bank 1 initialized     */
+} ADI_PMG_TST_SRAM_INITSTAT_BNK1DONE;
+
+
+/*  =========================================================================
+ *! \enum   ADI_PMG_TST_SRAM_INITSTAT_BNK2DONE
+ *! \brief  Bank 2 initialization status (BNK2DONE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  PMG_TST_SRAM_INITSTAT_NO_BANK2_INIT = 0,  /**< Bank 2 not initialized */
+  PMG_TST_SRAM_INITSTAT_BANK2_INIT    = 1   /**< Bank 2 initialized     */
+} ADI_PMG_TST_SRAM_INITSTAT_BNK2DONE;
+
+
+/*  =========================================================================
+ *! \enum   ADI_PMG_TST_SRAM_INITSTAT_BNK3DONE
+ *! \brief  Bank 3 initialization status (BNK3DONE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  PMG_TST_SRAM_INITSTAT_NO_BANK3_INIT = 0,  /**< Bank 3 not initialized */
+  PMG_TST_SRAM_INITSTAT_BANK3_INIT    = 1   /**< Bank 3 initialized     */
+} ADI_PMG_TST_SRAM_INITSTAT_BNK3DONE;
+
+
+/*  =========================================================================
+ *! \enum   ADI_PMG_TST_SRAM_INITSTAT_BNK4DONE
+ *! \brief  Bank 4 initialization status (BNK4DONE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  PMG_TST_SRAM_INITSTAT_NO_BANK4_INIT = 0,  /**< Bank 4 not initialized */
+  PMG_TST_SRAM_INITSTAT_BANK4_INIT    = 1   /**< Bank 4 initialized     */
+} ADI_PMG_TST_SRAM_INITSTAT_BNK4DONE;
+
+
+/*  =========================================================================
+ *! \enum   ADI_PMG_TST_SRAM_INITSTAT_BNK5DONE
+ *! \brief  Bank 5 initialization status (BNK5DONE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  PMG_TST_SRAM_INITSTAT_NO_BANK5_INIT = 0,  /**< Bank 5 not initialized */
+  PMG_TST_SRAM_INITSTAT_BANK5_INIT    = 1   /**< Bank 5 initialized     */
+} ADI_PMG_TST_SRAM_INITSTAT_BNK5DONE;
+
+
+/*  =========================================================================
+ *! \enum   ADI_PMG_TST_SRAM_INITSTAT_BNK6DONE
+ *! \brief  Bank 6 initialization status (BNK6DONE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  PMG_TST_SRAM_INITSTAT_NO_BANK6_INIT = 0,  /**< Bank 6 not initialized */
+  PMG_TST_SRAM_INITSTAT_BANK6_INIT    = 1   /**< Bank 6 initialized     */
+} ADI_PMG_TST_SRAM_INITSTAT_BNK6DONE;
+
+
+/*  =========================================================================
+ *! \enum   ADI_PMG_TST_SRAM_INITSTAT_BNK7DONE
+ *! \brief  Bank 7 initialization status (BNK7DONE) Enumerations
+ *  ========================================================================= */
+typedef enum
+{
+  PMG_TST_SRAM_INITSTAT_NO_BANK7_INIT = 0,  /**< Bank 7 not initialized */
+  PMG_TST_SRAM_INITSTAT_BANK7_INIT    = 1   /**< Bank 7 initialized     */
+} ADI_PMG_TST_SRAM_INITSTAT_BNK7DONE;
+
+
+/* ==========================================================================
+ *! \struct ADI_PMG_TST_SRAM_INITSTAT_Struct
+ *! \brief  Initialization Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_SRAM_INITSTAT_t__
+typedef struct _ADI_PMG_TST_SRAM_INITSTAT_t {
+  union {
+    struct {
+      unsigned int BNK0DONE   :  1;  /**< Bank 0 initialization status */
+      unsigned int BNK1DONE   :  1;  /**< Bank 1 initialization status */
+      unsigned int BNK2DONE   :  1;  /**< Bank 2 initialization status */
+      unsigned int BNK3DONE   :  1;  /**< Bank 3 initialization status */
+      unsigned int BNK4DONE   :  1;  /**< Bank 4 initialization status */
+      unsigned int BNK5DONE   :  1;  /**< Bank 5 initialization status */
+      unsigned int BNK6DONE   :  1;  /**< Bank 6 initialization status */
+      unsigned int BNK7DONE   :  1;  /**< Bank 7 initialization status */
+      unsigned int reserved8  : 24;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_TST_SRAM_INITSTAT_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_SRAM_INITSTAT_t__ */
+
+/*@}*/
+
+/** @defgroup CLR_LATCH_GPIOS Clear GPIO After Shutdown Mode (CLR_LATCH_GPIOS) Register
+ *  Clear GPIO After Shutdown Mode (CLR_LATCH_GPIOS) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PMG_TST_CLR_LATCH_GPIOS_Struct
+ *! \brief  Clear GPIO After Shutdown Mode Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_CLR_LATCH_GPIOS_t__
+typedef struct _ADI_PMG_TST_CLR_LATCH_GPIOS_t {
+  union {
+    struct {
+      unsigned int VALUE      : 16;  /**< Writing 0x58FA creates a pulse to clear the latches for the GPIOs */
+    };
+    uint16_t VALUE16;
+  };
+} ADI_PMG_TST_CLR_LATCH_GPIOS_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_CLR_LATCH_GPIOS_t__ */
+
+/*@}*/
+
+/** @defgroup SCRPAD_IMG Scratch Pad Image (SCRPAD_IMG) Register
+ *  Scratch Pad Image (SCRPAD_IMG) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PMG_TST_SCRPAD_IMG_Struct
+ *! \brief  Scratch Pad Image Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_SCRPAD_IMG_t__
+typedef struct _ADI_PMG_TST_SCRPAD_IMG_t {
+  union {
+    struct {
+      unsigned int DATA       : 32;  /**< Value written to this register is saved in 3 V when going to shutdown */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_TST_SCRPAD_IMG_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_SCRPAD_IMG_t__ */
+
+/*@}*/
+
+/** @defgroup SCRPAD_3V_RD Scratch Pad Saved in Battery Domain (SCRPAD_3V_RD) Register
+ *  Scratch Pad Saved in Battery Domain (SCRPAD_3V_RD) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PMG_TST_SCRPAD_3V_RD_Struct
+ *! \brief  Scratch Pad Saved in Battery Domain Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_SCRPAD_3V_RD_t__
+typedef struct _ADI_PMG_TST_SCRPAD_3V_RD_t {
+  union {
+    struct {
+      unsigned int DATA       : 32;  /**< Reading the scratch pad stored in shutdown mode */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_TST_SCRPAD_3V_RD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_SCRPAD_3V_RD_t__ */
+
+/*@}*/
+
+/** @defgroup FAST_SHT_WAKEUP Fast Shutdown Wake-up Enable (FAST_SHT_WAKEUP) Register
+ *  Fast Shutdown Wake-up Enable (FAST_SHT_WAKEUP) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PMG_TST_FAST_SHT_WAKEUP_Struct
+ *! \brief  Fast Shutdown Wake-up Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_FAST_SHT_WAKEUP_t__
+typedef struct _ADI_PMG_TST_FAST_SHT_WAKEUP_t {
+  union {
+    struct {
+      unsigned int FAST_SHT_WAKEUP :  1;  /**< Enables fast shutdown wake-up */
+      unsigned int reserved1       : 31;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PMG_TST_FAST_SHT_WAKEUP_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_FAST_SHT_WAKEUP_t__ */
+
+/*@}*/
+
+/** @defgroup CTL0 Misc Clock Settings (CTL0) Register
+ *  Misc Clock Settings (CTL0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CLKG_CLK_CTL0_Struct
+ *! \brief  Misc Clock Settings Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL0_t__
+typedef struct _ADI_CLKG_CLK_CTL0_t {
+  union {
+    struct {
+      unsigned int CLKMUX     :  2;  /**< Clock mux select */
+      unsigned int reserved2  :  1;
+      unsigned int CLKOUT     :  4;  /**< GPIO clock out select */
+      unsigned int reserved7  :  1;
+      unsigned int RCLKMUX    :  2;  /**< Flash reference clock and HPBUCK clock source mux */
+      unsigned int reserved10 :  1;
+      unsigned int PLL_IPSEL  :  2;  /**< SPLL source select mux */
+      unsigned int reserved13 :  1;
+      unsigned int LFXTALIE   :  1;  /**< Low frequency crystal interrupt enable */
+      unsigned int HFXTALIE   :  1;  /**< High frequency crystal interrupt enable */
+      unsigned int reserved16 : 16;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CLKG_CLK_CTL0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL0_t__ */
+
+/*@}*/
+
+/** @defgroup CTL1 Clock Dividers (CTL1) Register
+ *  Clock Dividers (CTL1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CLKG_CLK_CTL1_Struct
+ *! \brief  Clock Dividers Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL1_t__
+typedef struct _ADI_CLKG_CLK_CTL1_t {
+  union {
+    struct {
+      unsigned int HCLKDIVCNT :  6;  /**< HCLK divide count */
+      unsigned int reserved6  :  2;
+      unsigned int PCLKDIVCNT :  6;  /**< PCLK divide count */
+      unsigned int reserved14 :  2;
+      unsigned int ACLKDIVCNT :  9;  /**< ACLK Divide Count */
+      unsigned int reserved25 :  7;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CLKG_CLK_CTL1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL1_t__ */
+
+/*@}*/
+
+/** @defgroup CTL2 HF Oscillator Divided Clock Select (CTL2) Register
+ *  HF Oscillator Divided Clock Select (CTL2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CLKG_CLK_CTL2_Struct
+ *! \brief  HF Oscillator Divided Clock Select Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL2_t__
+typedef struct _ADI_CLKG_CLK_CTL2_t {
+  union {
+    struct {
+      unsigned int HFOSCAUTODIV_EN :  1;  /**< HF Oscillator auto divide by one clock selection during wakeup from Flexi power mode */
+      unsigned int HFOSCDIVCLKSEL  :  3;  /**< HF Oscillator divided clock select */
+      unsigned int reserved4       : 28;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CLKG_CLK_CTL2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL2_t__ */
+
+/*@}*/
+
+/** @defgroup CTL3 System PLL (CTL3) Register
+ *  System PLL (CTL3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CLKG_CLK_CTL3_Struct
+ *! \brief  System PLL Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL3_t__
+typedef struct _ADI_CLKG_CLK_CTL3_t {
+  union {
+    struct {
+      unsigned int SPLLNSEL   :  5;  /**< System PLL N multiplier */
+      unsigned int reserved5  :  3;
+      unsigned int SPLLDIV2   :  1;  /**< System PLL division by 2 */
+      unsigned int SPLLEN     :  1;  /**< System PLL enable */
+      unsigned int SPLLIE     :  1;  /**< System PLL interrupt enable */
+      unsigned int SPLLMSEL   :  4;  /**< System PLL M Divider */
+      unsigned int reserved15 :  1;
+      unsigned int SPLLMUL2   :  1;  /**< System PLL multiply by 2 */
+      unsigned int reserved17 : 15;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CLKG_CLK_CTL3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL3_t__ */
+
+/*@}*/
+
+/** @defgroup CTL5 User Clock Gating Control (CTL5) Register
+ *  User Clock Gating Control (CTL5) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CLKG_CLK_CTL5_Struct
+ *! \brief  User Clock Gating Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL5_t__
+typedef struct _ADI_CLKG_CLK_CTL5_t {
+  union {
+    struct {
+      unsigned int GPTCLK0OFF :  1;  /**< GP Timer 0 user control */
+      unsigned int GPTCLK1OFF :  1;  /**< GP Timer 1 user control */
+      unsigned int GPTCLK2OFF :  1;  /**< GP Timer 2 user control */
+      unsigned int UCLKI2COFF :  1;  /**< I2C clock user control */
+      unsigned int GPIOCLKOFF :  1;  /**< GPIO clock control */
+      unsigned int PERCLKOFF  :  1;  /**< This bit is used to disable all clocks connected to all peripherals */
+      unsigned int TMRRGBCLKOFF :  1;  /**< Timer RGB user control */
+      unsigned int reserved7    : 25;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CLKG_CLK_CTL5_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL5_t__ */
+
+/*@}*/
+
+/** @defgroup STAT0 Clocking Status (STAT0) Register
+ *  Clocking Status (STAT0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CLKG_CLK_STAT0_Struct
+ *! \brief  Clocking Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_STAT0_t__
+typedef struct _ADI_CLKG_CLK_STAT0_t {
+  union {
+    struct {
+      unsigned int SPLL       :  1;  /**< System PLL status */
+      unsigned int SPLLLK     :  1;  /**< System PLL lock */
+      unsigned int SPLLUNLK   :  1;  /**< System PLL unlock */
+      unsigned int reserved3  :  5;
+      unsigned int LFXTAL     :  1;  /**< LF crystal status */
+      unsigned int LFXTALOK   :  1;  /**< LF crystal stable */
+      unsigned int LFXTALNOK  :  1;  /**< LF crystal not stable */
+      unsigned int reserved11 :  1;
+      unsigned int HFXTAL     :  1;  /**< HF crystal status */
+      unsigned int HFXTALOK   :  1;  /**< HF crystal stable */
+      unsigned int HFXTALNOK  :  1;  /**< HF crystal not stable */
+      unsigned int reserved15 : 17;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_CLKG_CLK_STAT0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_STAT0_t__ */
+
+/*@}*/
+
+/** @defgroup ARBIT0 Arbitration Priority Configuration for FLASH and SRAM0 (ARBIT0) Register
+ *  Arbitration Priority Configuration for FLASH and SRAM0 (ARBIT0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_BUSM_ARBIT0_Struct
+ *! \brief  Arbitration Priority Configuration for FLASH and SRAM0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT0_t__
+typedef struct _ADI_BUSM_ARBIT0_t {
+  union {
+    struct {
+      unsigned int FLSH_DCODE :  2;  /**< Flash priority for DCODE */
+      unsigned int FLSH_SBUS  :  2;  /**< Flash priority for SBUS */
+      unsigned int FLSH_DMA0  :  2;  /**< Flash priority for DMA0 */
+      unsigned int reserved6   : 10;
+      unsigned int SRAM0_DCODE :  2;  /**< SRAM0 priority for Dcode */
+      unsigned int SRAM0_SBUS  :  2;  /**< SRAM0 priority for SBUS */
+      unsigned int SRAM0_DMA0  :  2;  /**< SRAM0 priority for DMA0 */
+      unsigned int reserved22  : 10;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_BUSM_ARBIT0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT0_t__ */
+
+/*@}*/
+
+/** @defgroup ARBIT1 Arbitration Priority Configuration for SRAM1 and SIP (ARBIT1) Register
+ *  Arbitration Priority Configuration for SRAM1 and SIP (ARBIT1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_BUSM_ARBIT1_Struct
+ *! \brief  Arbitration Priority Configuration for SRAM1 and SIP Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT1_t__
+typedef struct _ADI_BUSM_ARBIT1_t {
+  union {
+    struct {
+      unsigned int SRAM1_DCODE :  2;  /**< SRAM1 priority for Dcode */
+      unsigned int SRAM1_SBUS  :  2;  /**< SRAM1 priority for SBUS */
+      unsigned int SRAM1_DMA0  :  2;  /**< SRAM1 priority for DMA0 */
+      unsigned int reserved6   : 10;
+      unsigned int SIP_DCODE   :  2;  /**< SIP priority for DCODE */
+      unsigned int SIP_SBUS    :  2;  /**< SIP priority for SBUS */
+      unsigned int SIP_DMA0    :  2;  /**< SIP priority for DMA0 */
+      unsigned int reserved22  : 10;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_BUSM_ARBIT1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT1_t__ */
+
+/*@}*/
+
+/** @defgroup ARBIT2 Arbitration Priority Configuration for APB32 and APB16 (ARBIT2) Register
+ *  Arbitration Priority Configuration for APB32 and APB16 (ARBIT2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_BUSM_ARBIT2_Struct
+ *! \brief  Arbitration Priority Configuration for APB32 and APB16 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT2_t__
+typedef struct _ADI_BUSM_ARBIT2_t {
+  union {
+    struct {
+      unsigned int APB32_DCODE :  2;  /**< APB32 priority for DCODE */
+      unsigned int APB32_SBUS  :  2;  /**< APB32 priority for SBUS */
+      unsigned int APB32_DMA0  :  2;  /**< APB32 priority for DMA0 */
+      unsigned int reserved6   : 10;
+      unsigned int APB16_DCODE :  2;  /**< APB16 priority for DCODE */
+      unsigned int APB16_SBUS  :  2;  /**< APB16 priority for SBUS */
+      unsigned int APB16_DMA0  :  2;  /**< APB16 priority for DMA0 */
+      unsigned int reserved22  : 10;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_BUSM_ARBIT2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT2_t__ */
+
+/*@}*/
+
+/** @defgroup ARBIT3 Arbitration Priority Configuration for APB16 priority for core and for DMA1 (ARBIT3) Register
+ *  Arbitration Priority Configuration for APB16 priority for core and for DMA1 (ARBIT3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_BUSM_ARBIT3_Struct
+ *! \brief  Arbitration Priority Configuration for APB16 priority for core and for DMA1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT3_t__
+typedef struct _ADI_BUSM_ARBIT3_t {
+  union {
+    struct {
+      unsigned int APB16_CORE :  1;  /**< APB16 priority for CORE */
+      unsigned int APB16_DMA1 :  1;  /**< APB16 priority for DMA1 */
+      unsigned int reserved2       : 14;
+      unsigned int APB16_4DMA_CORE :  1;  /**< APB16 for dma priority for CORE */
+      unsigned int APB16_4DMA_DMA1 :  1;  /**< APB16 for dma priority for DMA1 */
+      unsigned int reserved18      : 14;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_BUSM_ARBIT3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT3_t__ */
+
+/*@}*/
+
+/** @defgroup ARBIT4 Arbitration Priority Configuration for SRAM1 and SIP (ARBIT4) Register
+ *  Arbitration Priority Configuration for SRAM1 and SIP (ARBIT4) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_BUSM_ARBIT4_Struct
+ *! \brief  Arbitration Priority Configuration for SRAM1 and SIP Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT4_t__
+typedef struct _ADI_BUSM_ARBIT4_t {
+  union {
+    struct {
+      unsigned int SRAM2_DCODE :  2;  /**< SRAM2 priority for Dcode */
+      unsigned int SRAM2_SBUS  :  2;  /**< SRAM2 priority for SBUS */
+      unsigned int SRAM2_DMA0  :  2;  /**< SRAM2 priority for DMA0 */
+      unsigned int reserved6   : 26;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_BUSM_ARBIT4_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT4_t__ */
+
+/*@}*/
+
+/** @defgroup RST_ISR_STARTADDR Reset ISR Start Address (RST_ISR_STARTADDR) Register
+ *  Reset ISR Start Address (RST_ISR_STARTADDR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PTI_RST_ISR_STARTADDR_Struct
+ *! \brief  Reset ISR Start Address Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PTI_RST_ISR_STARTADDR_t__
+typedef struct _ADI_PTI_RST_ISR_STARTADDR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PTI_RST_ISR_STARTADDR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PTI_RST_ISR_STARTADDR_t__ */
+
+/*@}*/
+
+/** @defgroup RST_STACK_PTR Reset Stack Pointer (RST_STACK_PTR) Register
+ *  Reset Stack Pointer (RST_STACK_PTR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PTI_RST_STACK_PTR_Struct
+ *! \brief  Reset Stack Pointer Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PTI_RST_STACK_PTR_t__
+typedef struct _ADI_PTI_RST_STACK_PTR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PTI_RST_STACK_PTR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PTI_RST_STACK_PTR_t__ */
+
+/*@}*/
+
+/** @defgroup CTL Parallel Test Interface Control Register (CTL) Register
+ *  Parallel Test Interface Control Register (CTL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_PTI_CTL_Struct
+ *! \brief  Parallel Test Interface Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_PTI_CTL_t__
+typedef struct _ADI_PTI_CTL_t {
+  union {
+    struct {
+      unsigned int EN         :  1;
+      unsigned int reserved1  : 31;
+    };
+    uint32_t VALUE32;
+  };
+} ADI_PTI_CTL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_PTI_CTL_t__ */
+
+/*@}*/
+
+/** @defgroup INTNUM Interrupt Control Type (INTNUM) Register
+ *  Interrupt Control Type (INTNUM) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTNUM_Struct
+ *! \brief  Interrupt Control Type Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTNUM_t__
+typedef struct _ADI_NVIC_INTNUM_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Interrupt Control Type */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTNUM_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTNUM_t__ */
+
+/*@}*/
+
+/** @defgroup STKSTA Systick Control and Status (STKSTA) Register
+ *  Systick Control and Status (STKSTA) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_STKSTA_Struct
+ *! \brief  Systick Control and Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_STKSTA_t__
+typedef struct _ADI_NVIC_STKSTA_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Systick Control and Status */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_STKSTA_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_STKSTA_t__ */
+
+/*@}*/
+
+/** @defgroup STKLD Systick Reload Value (STKLD) Register
+ *  Systick Reload Value (STKLD) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_STKLD_Struct
+ *! \brief  Systick Reload Value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_STKLD_t__
+typedef struct _ADI_NVIC_STKLD_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Systick Reload Value */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_STKLD_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_STKLD_t__ */
+
+/*@}*/
+
+/** @defgroup STKVAL Systick Current Value (STKVAL) Register
+ *  Systick Current Value (STKVAL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_STKVAL_Struct
+ *! \brief  Systick Current Value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_STKVAL_t__
+typedef struct _ADI_NVIC_STKVAL_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Systick Current Value */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_STKVAL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_STKVAL_t__ */
+
+/*@}*/
+
+/** @defgroup STKCAL Systick Calibration Value (STKCAL) Register
+ *  Systick Calibration Value (STKCAL) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_STKCAL_Struct
+ *! \brief  Systick Calibration Value Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_STKCAL_t__
+typedef struct _ADI_NVIC_STKCAL_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Systick Calibration Value */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_STKCAL_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_STKCAL_t__ */
+
+/*@}*/
+
+/** @defgroup INTSETE0 IRQ0..31 Set_Enable (INTSETE0) Register
+ *  IRQ0..31 Set_Enable (INTSETE0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTSETE0_Struct
+ *! \brief  IRQ0..31 Set_Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETE0_t__
+typedef struct _ADI_NVIC_INTSETE0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ0..31 Set_Enable */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTSETE0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETE0_t__ */
+
+/*@}*/
+
+/** @defgroup INTSETE1 IRQ32..63 Set_Enable (INTSETE1) Register
+ *  IRQ32..63 Set_Enable (INTSETE1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTSETE1_Struct
+ *! \brief  IRQ32..63 Set_Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETE1_t__
+typedef struct _ADI_NVIC_INTSETE1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ32..63 Set_Enable */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTSETE1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETE1_t__ */
+
+/*@}*/
+
+/** @defgroup INTCLRE0 IRQ0..31 Clear_Enable (INTCLRE0) Register
+ *  IRQ0..31 Clear_Enable (INTCLRE0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCLRE0_Struct
+ *! \brief  IRQ0..31 Clear_Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRE0_t__
+typedef struct _ADI_NVIC_INTCLRE0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ0..31 Clear_Enable */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCLRE0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRE0_t__ */
+
+/*@}*/
+
+/** @defgroup INTCLRE1 IRQ32..63 Clear_Enable (INTCLRE1) Register
+ *  IRQ32..63 Clear_Enable (INTCLRE1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCLRE1_Struct
+ *! \brief  IRQ32..63 Clear_Enable Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRE1_t__
+typedef struct _ADI_NVIC_INTCLRE1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ32..63 Clear_Enable */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCLRE1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRE1_t__ */
+
+/*@}*/
+
+/** @defgroup INTSETP0 IRQ0..31 Set_Pending (INTSETP0) Register
+ *  IRQ0..31 Set_Pending (INTSETP0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTSETP0_Struct
+ *! \brief  IRQ0..31 Set_Pending Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETP0_t__
+typedef struct _ADI_NVIC_INTSETP0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ0..31 Set_Pending */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTSETP0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETP0_t__ */
+
+/*@}*/
+
+/** @defgroup INTSETP1 IRQ32..63 Set_Pending (INTSETP1) Register
+ *  IRQ32..63 Set_Pending (INTSETP1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTSETP1_Struct
+ *! \brief  IRQ32..63 Set_Pending Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETP1_t__
+typedef struct _ADI_NVIC_INTSETP1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ32..63 Set_Pending */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTSETP1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETP1_t__ */
+
+/*@}*/
+
+/** @defgroup INTCLRP0 IRQ0..31 Clear_Pending (INTCLRP0) Register
+ *  IRQ0..31 Clear_Pending (INTCLRP0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCLRP0_Struct
+ *! \brief  IRQ0..31 Clear_Pending Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRP0_t__
+typedef struct _ADI_NVIC_INTCLRP0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ0..31 Clear_Pending */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCLRP0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRP0_t__ */
+
+/*@}*/
+
+/** @defgroup INTCLRP1 IRQ32..63 Clear_Pending (INTCLRP1) Register
+ *  IRQ32..63 Clear_Pending (INTCLRP1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCLRP1_Struct
+ *! \brief  IRQ32..63 Clear_Pending Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRP1_t__
+typedef struct _ADI_NVIC_INTCLRP1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ32..63 Clear_Pending */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCLRP1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRP1_t__ */
+
+/*@}*/
+
+/** @defgroup INTACT0 IRQ0..31 Active Bit (INTACT0) Register
+ *  IRQ0..31 Active Bit (INTACT0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTACT0_Struct
+ *! \brief  IRQ0..31 Active Bit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTACT0_t__
+typedef struct _ADI_NVIC_INTACT0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ0..31 Active Bit */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTACT0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTACT0_t__ */
+
+/*@}*/
+
+/** @defgroup INTACT1 IRQ32..63 Active Bit (INTACT1) Register
+ *  IRQ32..63 Active Bit (INTACT1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTACT1_Struct
+ *! \brief  IRQ32..63 Active Bit Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTACT1_t__
+typedef struct _ADI_NVIC_INTACT1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ32..63 Active Bit */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTACT1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTACT1_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI0 IRQ0..3 Priority (INTPRI0) Register
+ *  IRQ0..3 Priority (INTPRI0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI0_Struct
+ *! \brief  IRQ0..3 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI0_t__
+typedef struct _ADI_NVIC_INTPRI0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ0..3 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI0_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI1 IRQ4..7 Priority (INTPRI1) Register
+ *  IRQ4..7 Priority (INTPRI1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI1_Struct
+ *! \brief  IRQ4..7 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI1_t__
+typedef struct _ADI_NVIC_INTPRI1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ4..7 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI1_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI2 IRQ8..11 Priority (INTPRI2) Register
+ *  IRQ8..11 Priority (INTPRI2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI2_Struct
+ *! \brief  IRQ8..11 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI2_t__
+typedef struct _ADI_NVIC_INTPRI2_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ8..11 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI2_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI3 IRQ12..15 Priority (INTPRI3) Register
+ *  IRQ12..15 Priority (INTPRI3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI3_Struct
+ *! \brief  IRQ12..15 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI3_t__
+typedef struct _ADI_NVIC_INTPRI3_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ12..15 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI3_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI4 IRQ16..19 Priority (INTPRI4) Register
+ *  IRQ16..19 Priority (INTPRI4) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI4_Struct
+ *! \brief  IRQ16..19 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI4_t__
+typedef struct _ADI_NVIC_INTPRI4_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ16..19 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI4_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI4_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI5 IRQ20..23 Priority (INTPRI5) Register
+ *  IRQ20..23 Priority (INTPRI5) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI5_Struct
+ *! \brief  IRQ20..23 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI5_t__
+typedef struct _ADI_NVIC_INTPRI5_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ20..23 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI5_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI5_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI6 IRQ24..27 Priority (INTPRI6) Register
+ *  IRQ24..27 Priority (INTPRI6) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI6_Struct
+ *! \brief  IRQ24..27 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI6_t__
+typedef struct _ADI_NVIC_INTPRI6_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ24..27 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI6_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI6_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI7 IRQ28..31 Priority (INTPRI7) Register
+ *  IRQ28..31 Priority (INTPRI7) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI7_Struct
+ *! \brief  IRQ28..31 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI7_t__
+typedef struct _ADI_NVIC_INTPRI7_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ28..31 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI7_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI7_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI8 IRQ32..35 Priority (INTPRI8) Register
+ *  IRQ32..35 Priority (INTPRI8) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI8_Struct
+ *! \brief  IRQ32..35 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI8_t__
+typedef struct _ADI_NVIC_INTPRI8_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ32..35 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI8_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI8_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI9 IRQ36..39 Priority (INTPRI9) Register
+ *  IRQ36..39 Priority (INTPRI9) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI9_Struct
+ *! \brief  IRQ36..39 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI9_t__
+typedef struct _ADI_NVIC_INTPRI9_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ36..39 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI9_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI9_t__ */
+
+/*@}*/
+
+/** @defgroup INTPRI10 IRQ40..43 Priority (INTPRI10) Register
+ *  IRQ40..43 Priority (INTPRI10) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPRI10_Struct
+ *! \brief  IRQ40..43 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI10_t__
+typedef struct _ADI_NVIC_INTPRI10_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< IRQ40..43 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPRI10_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI10_t__ */
+
+/*@}*/
+
+/** @defgroup INTCPID CPUID Base (INTCPID) Register
+ *  CPUID Base (INTCPID) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCPID_Struct
+ *! \brief  CPUID Base Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCPID_t__
+typedef struct _ADI_NVIC_INTCPID_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< CPUID Base */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCPID_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCPID_t__ */
+
+/*@}*/
+
+/** @defgroup INTSTA Interrupt Control State (INTSTA) Register
+ *  Interrupt Control State (INTSTA) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTSTA_Struct
+ *! \brief  Interrupt Control State Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSTA_t__
+typedef struct _ADI_NVIC_INTSTA_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Interrupt Control State */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTSTA_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSTA_t__ */
+
+/*@}*/
+
+/** @defgroup INTVEC Vector Table Offset (INTVEC) Register
+ *  Vector Table Offset (INTVEC) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTVEC_Struct
+ *! \brief  Vector Table Offset Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTVEC_t__
+typedef struct _ADI_NVIC_INTVEC_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Vector Table Offset */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTVEC_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTVEC_t__ */
+
+/*@}*/
+
+/** @defgroup INTAIRC Application Interrupt/Reset Control (INTAIRC) Register
+ *  Application Interrupt/Reset Control (INTAIRC) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTAIRC_Struct
+ *! \brief  Application Interrupt/Reset Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTAIRC_t__
+typedef struct _ADI_NVIC_INTAIRC_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Application Interrupt/Reset Control */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTAIRC_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTAIRC_t__ */
+
+/*@}*/
+
+/** @defgroup INTCON0 System Control (INTCON0) Register
+ *  System Control (INTCON0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCON0_Struct
+ *! \brief  System Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCON0_t__
+typedef struct _ADI_NVIC_INTCON0_t {
+  union {
+    struct {
+      unsigned int reserved0   :  1;
+      unsigned int SLEEPONEXIT :  1;  /**< Sleeps the core on exit from an ISR */
+      unsigned int SLEEPDEEP   :  1;  /**< deep sleep flag for HIBERNATE mode */
+      unsigned int reserved3   : 13;
+    };
+    uint16_t VALUE16;
+  };
+} ADI_NVIC_INTCON0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCON0_t__ */
+
+/*@}*/
+
+/** @defgroup INTCON1 Configuration Control (INTCON1) Register
+ *  Configuration Control (INTCON1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCON1_Struct
+ *! \brief  Configuration Control Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCON1_t__
+typedef struct _ADI_NVIC_INTCON1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Configuration Control */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCON1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCON1_t__ */
+
+/*@}*/
+
+/** @defgroup INTSHPRIO0 System Handlers 4-7 Priority (INTSHPRIO0) Register
+ *  System Handlers 4-7 Priority (INTSHPRIO0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTSHPRIO0_Struct
+ *! \brief  System Handlers 4-7 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO0_t__
+typedef struct _ADI_NVIC_INTSHPRIO0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< System Handlers 4-7 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTSHPRIO0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO0_t__ */
+
+/*@}*/
+
+/** @defgroup INTSHPRIO1 System Handlers 8-11 Priority (INTSHPRIO1) Register
+ *  System Handlers 8-11 Priority (INTSHPRIO1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTSHPRIO1_Struct
+ *! \brief  System Handlers 8-11 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO1_t__
+typedef struct _ADI_NVIC_INTSHPRIO1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< System Handlers 8-11 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTSHPRIO1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO1_t__ */
+
+/*@}*/
+
+/** @defgroup INTSHPRIO3 System Handlers 12-15 Priority (INTSHPRIO3) Register
+ *  System Handlers 12-15 Priority (INTSHPRIO3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTSHPRIO3_Struct
+ *! \brief  System Handlers 12-15 Priority Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO3_t__
+typedef struct _ADI_NVIC_INTSHPRIO3_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< System Handlers 12-15 Priority */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTSHPRIO3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO3_t__ */
+
+/*@}*/
+
+/** @defgroup INTSHCSR System Handler Control and State (INTSHCSR) Register
+ *  System Handler Control and State (INTSHCSR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTSHCSR_Struct
+ *! \brief  System Handler Control and State Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHCSR_t__
+typedef struct _ADI_NVIC_INTSHCSR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< System Handler Control and State */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTSHCSR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHCSR_t__ */
+
+/*@}*/
+
+/** @defgroup INTCFSR Configurable Fault Status (INTCFSR) Register
+ *  Configurable Fault Status (INTCFSR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCFSR_Struct
+ *! \brief  Configurable Fault Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCFSR_t__
+typedef struct _ADI_NVIC_INTCFSR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Configurable Fault Status */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCFSR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCFSR_t__ */
+
+/*@}*/
+
+/** @defgroup INTHFSR Hard Fault Status (INTHFSR) Register
+ *  Hard Fault Status (INTHFSR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTHFSR_Struct
+ *! \brief  Hard Fault Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTHFSR_t__
+typedef struct _ADI_NVIC_INTHFSR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Hard Fault Status */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTHFSR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTHFSR_t__ */
+
+/*@}*/
+
+/** @defgroup INTDFSR Debug Fault Status (INTDFSR) Register
+ *  Debug Fault Status (INTDFSR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTDFSR_Struct
+ *! \brief  Debug Fault Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTDFSR_t__
+typedef struct _ADI_NVIC_INTDFSR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Debug Fault Status */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTDFSR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTDFSR_t__ */
+
+/*@}*/
+
+/** @defgroup INTMMAR Mem Manage Address (INTMMAR) Register
+ *  Mem Manage Address (INTMMAR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTMMAR_Struct
+ *! \brief  Mem Manage Address Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMAR_t__
+typedef struct _ADI_NVIC_INTMMAR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Mem Manage Address */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTMMAR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMAR_t__ */
+
+/*@}*/
+
+/** @defgroup INTBFAR Bus Fault Address (INTBFAR) Register
+ *  Bus Fault Address (INTBFAR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTBFAR_Struct
+ *! \brief  Bus Fault Address Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTBFAR_t__
+typedef struct _ADI_NVIC_INTBFAR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Bus Fault Address */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTBFAR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTBFAR_t__ */
+
+/*@}*/
+
+/** @defgroup INTAFSR Auxiliary Fault Status (INTAFSR) Register
+ *  Auxiliary Fault Status (INTAFSR) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTAFSR_Struct
+ *! \brief  Auxiliary Fault Status Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTAFSR_t__
+typedef struct _ADI_NVIC_INTAFSR_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Auxiliary Fault Status */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTAFSR_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTAFSR_t__ */
+
+/*@}*/
+
+/** @defgroup INTPFR0 Processor Feature Register 0 (INTPFR0) Register
+ *  Processor Feature Register 0 (INTPFR0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPFR0_Struct
+ *! \brief  Processor Feature Register 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPFR0_t__
+typedef struct _ADI_NVIC_INTPFR0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Processor Feature Register 0 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPFR0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPFR0_t__ */
+
+/*@}*/
+
+/** @defgroup INTPFR1 Processor Feature Register 1 (INTPFR1) Register
+ *  Processor Feature Register 1 (INTPFR1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPFR1_Struct
+ *! \brief  Processor Feature Register 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPFR1_t__
+typedef struct _ADI_NVIC_INTPFR1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Processor Feature Register 1 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPFR1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPFR1_t__ */
+
+/*@}*/
+
+/** @defgroup INTDFR0 Debug Feature Register 0 (INTDFR0) Register
+ *  Debug Feature Register 0 (INTDFR0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTDFR0_Struct
+ *! \brief  Debug Feature Register 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTDFR0_t__
+typedef struct _ADI_NVIC_INTDFR0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Debug Feature Register 0 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTDFR0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTDFR0_t__ */
+
+/*@}*/
+
+/** @defgroup INTAFR0 Auxiliary Feature Register 0 (INTAFR0) Register
+ *  Auxiliary Feature Register 0 (INTAFR0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTAFR0_Struct
+ *! \brief  Auxiliary Feature Register 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTAFR0_t__
+typedef struct _ADI_NVIC_INTAFR0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Auxiliary Feature Register 0 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTAFR0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTAFR0_t__ */
+
+/*@}*/
+
+/** @defgroup INTMMFR0 Memory Model Feature Register 0 (INTMMFR0) Register
+ *  Memory Model Feature Register 0 (INTMMFR0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTMMFR0_Struct
+ *! \brief  Memory Model Feature Register 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR0_t__
+typedef struct _ADI_NVIC_INTMMFR0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Memory Model Feature Register 0 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTMMFR0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR0_t__ */
+
+/*@}*/
+
+/** @defgroup INTMMFR1 Memory Model Feature Register 1 (INTMMFR1) Register
+ *  Memory Model Feature Register 1 (INTMMFR1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTMMFR1_Struct
+ *! \brief  Memory Model Feature Register 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR1_t__
+typedef struct _ADI_NVIC_INTMMFR1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Memory Model Feature Register 1 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTMMFR1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR1_t__ */
+
+/*@}*/
+
+/** @defgroup INTMMFR2 Memory Model Feature Register 2 (INTMMFR2) Register
+ *  Memory Model Feature Register 2 (INTMMFR2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTMMFR2_Struct
+ *! \brief  Memory Model Feature Register 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR2_t__
+typedef struct _ADI_NVIC_INTMMFR2_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Memory Model Feature Register 2 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTMMFR2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR2_t__ */
+
+/*@}*/
+
+/** @defgroup INTMMFR3 Memory Model Feature Register 3 (INTMMFR3) Register
+ *  Memory Model Feature Register 3 (INTMMFR3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTMMFR3_Struct
+ *! \brief  Memory Model Feature Register 3 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR3_t__
+typedef struct _ADI_NVIC_INTMMFR3_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Memory Model Feature Register 3 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTMMFR3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR3_t__ */
+
+/*@}*/
+
+/** @defgroup INTISAR0 ISA Feature Register 0 (INTISAR0) Register
+ *  ISA Feature Register 0 (INTISAR0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTISAR0_Struct
+ *! \brief  ISA Feature Register 0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR0_t__
+typedef struct _ADI_NVIC_INTISAR0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< ISA Feature Register 0 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTISAR0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR0_t__ */
+
+/*@}*/
+
+/** @defgroup INTISAR1 ISA Feature Register 1 (INTISAR1) Register
+ *  ISA Feature Register 1 (INTISAR1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTISAR1_Struct
+ *! \brief  ISA Feature Register 1 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR1_t__
+typedef struct _ADI_NVIC_INTISAR1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< ISA Feature Register 1 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTISAR1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR1_t__ */
+
+/*@}*/
+
+/** @defgroup INTISAR2 ISA Feature Register 2 (INTISAR2) Register
+ *  ISA Feature Register 2 (INTISAR2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTISAR2_Struct
+ *! \brief  ISA Feature Register 2 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR2_t__
+typedef struct _ADI_NVIC_INTISAR2_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< ISA Feature Register 2 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTISAR2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR2_t__ */
+
+/*@}*/
+
+/** @defgroup INTISAR3 ISA Feature Register 3 (INTISAR3) Register
+ *  ISA Feature Register 3 (INTISAR3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTISAR3_Struct
+ *! \brief  ISA Feature Register 3 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR3_t__
+typedef struct _ADI_NVIC_INTISAR3_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< ISA Feature Register 3 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTISAR3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR3_t__ */
+
+/*@}*/
+
+/** @defgroup INTISAR4 ISA Feature Register 4 (INTISAR4) Register
+ *  ISA Feature Register 4 (INTISAR4) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTISAR4_Struct
+ *! \brief  ISA Feature Register 4 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR4_t__
+typedef struct _ADI_NVIC_INTISAR4_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< ISA Feature Register 4 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTISAR4_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR4_t__ */
+
+/*@}*/
+
+/** @defgroup INTTRGI Software Trigger Interrupt Register (INTTRGI) Register
+ *  Software Trigger Interrupt Register (INTTRGI) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTTRGI_Struct
+ *! \brief  Software Trigger Interrupt Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTTRGI_t__
+typedef struct _ADI_NVIC_INTTRGI_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Software Trigger Interrupt Register */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTTRGI_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTTRGI_t__ */
+
+/*@}*/
+
+/** @defgroup INTPID4 Peripheral Identification Register 4 (INTPID4) Register
+ *  Peripheral Identification Register 4 (INTPID4) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPID4_Struct
+ *! \brief  Peripheral Identification Register 4 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID4_t__
+typedef struct _ADI_NVIC_INTPID4_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Peripheral Identification Register 4 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPID4_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID4_t__ */
+
+/*@}*/
+
+/** @defgroup INTPID5 Peripheral Identification Register 5 (INTPID5) Register
+ *  Peripheral Identification Register 5 (INTPID5) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPID5_Struct
+ *! \brief  Peripheral Identification Register 5 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID5_t__
+typedef struct _ADI_NVIC_INTPID5_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Peripheral Identification Register 5 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPID5_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID5_t__ */
+
+/*@}*/
+
+/** @defgroup INTPID6 Peripheral Identification Register 6 (INTPID6) Register
+ *  Peripheral Identification Register 6 (INTPID6) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPID6_Struct
+ *! \brief  Peripheral Identification Register 6 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID6_t__
+typedef struct _ADI_NVIC_INTPID6_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Peripheral Identification Register 6 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPID6_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID6_t__ */
+
+/*@}*/
+
+/** @defgroup INTPID7 Peripheral Identification Register 7 (INTPID7) Register
+ *  Peripheral Identification Register 7 (INTPID7) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPID7_Struct
+ *! \brief  Peripheral Identification Register 7 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID7_t__
+typedef struct _ADI_NVIC_INTPID7_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Peripheral Identification Register 7 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPID7_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID7_t__ */
+
+/*@}*/
+
+/** @defgroup INTPID0 Peripheral Identification Bits7:0 (INTPID0) Register
+ *  Peripheral Identification Bits7:0 (INTPID0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPID0_Struct
+ *! \brief  Peripheral Identification Bits7:0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID0_t__
+typedef struct _ADI_NVIC_INTPID0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Peripheral Identification Bits7:0 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPID0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID0_t__ */
+
+/*@}*/
+
+/** @defgroup INTPID1 Peripheral Identification Bits15:8 (INTPID1) Register
+ *  Peripheral Identification Bits15:8 (INTPID1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPID1_Struct
+ *! \brief  Peripheral Identification Bits15:8 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID1_t__
+typedef struct _ADI_NVIC_INTPID1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Peripheral Identification Bits15:8 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPID1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID1_t__ */
+
+/*@}*/
+
+/** @defgroup INTPID2 Peripheral Identification Bits16:23 (INTPID2) Register
+ *  Peripheral Identification Bits16:23 (INTPID2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPID2_Struct
+ *! \brief  Peripheral Identification Bits16:23 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID2_t__
+typedef struct _ADI_NVIC_INTPID2_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Peripheral Identification Bits16:23 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPID2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID2_t__ */
+
+/*@}*/
+
+/** @defgroup INTPID3 Peripheral Identification Bits24:31 (INTPID3) Register
+ *  Peripheral Identification Bits24:31 (INTPID3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTPID3_Struct
+ *! \brief  Peripheral Identification Bits24:31 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID3_t__
+typedef struct _ADI_NVIC_INTPID3_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Peripheral Identification Bits24:31 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTPID3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID3_t__ */
+
+/*@}*/
+
+/** @defgroup INTCID0 Component Identification Bits7:0 (INTCID0) Register
+ *  Component Identification Bits7:0 (INTCID0) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCID0_Struct
+ *! \brief  Component Identification Bits7:0 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID0_t__
+typedef struct _ADI_NVIC_INTCID0_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Component Identification Bits7:0 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCID0_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID0_t__ */
+
+/*@}*/
+
+/** @defgroup INTCID1 Component Identification Bits15:8 (INTCID1) Register
+ *  Component Identification Bits15:8 (INTCID1) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCID1_Struct
+ *! \brief  Component Identification Bits15:8 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID1_t__
+typedef struct _ADI_NVIC_INTCID1_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Component Identification Bits15:8 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCID1_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID1_t__ */
+
+/*@}*/
+
+/** @defgroup INTCID2 Component Identification Bits16:23 (INTCID2) Register
+ *  Component Identification Bits16:23 (INTCID2) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCID2_Struct
+ *! \brief  Component Identification Bits16:23 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID2_t__
+typedef struct _ADI_NVIC_INTCID2_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Component Identification Bits16:23 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCID2_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID2_t__ */
+
+/*@}*/
+
+/** @defgroup INTCID3 Component Identification Bits24:31 (INTCID3) Register
+ *  Component Identification Bits24:31 (INTCID3) Register.
+ *  @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_NVIC_INTCID3_Struct
+ *! \brief  Component Identification Bits24:31 Register bit field structure
+ * ========================================================================== */
+#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID3_t__
+typedef struct _ADI_NVIC_INTCID3_t {
+  union {
+    struct {
+      unsigned int VALUE      : 32;  /**< Component Identification Bits24:31 */
+    };
+    uint32_t VALUE32;
+  };
+} ADI_NVIC_INTCID3_t;
+#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID3_t__ */
+
+/*@}*/
+
+
+#if defined (_MISRA_RULES)
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_cio_macros.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_cio_macros.h
new file mode 100755
index 00000000000..45f235b44be
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_cio_macros.h
@@ -0,0 +1,50 @@
+/*
+** adi_cio_macros.h
+**
+** Copyright (C) 2016 Analog Devices, Inc. All Rights Reserved.
+**
+*/
+
+#ifndef _ADI_CIO_MACROS_H
+#define _ADI_CIO_MACROS_H
+
+/*
+ * Macro definitions in adi_ADuCM4*50_cdef.h and the struct definitions
+ * in adi_ADuCM4*50_device.h use macros "__I __C", "__O" and "__IO" to
+ * represent read-only, write-only and read/write register attributes.
+ *
+ * The core_cm4.h include file will define macros __I, __O and __IO as below
+ * but it does not define __C.
+ *
+ * The __C macro is defined to nothing here. The __C macro is intended for
+ * the proprietary compilers in CCES to avoid MISRA Rule 19.4 errors regarding
+ * permitted macro expansions. The iccarm.exe MISRA checking does not fault
+ * the combined "volatile const" __I macro so __C is not required.
+ *
+ * Each of the macro defines is guarded by a #ifndef check to allow them
+ * to be redefined if required.
+ *
+ * Workaround for 01-00-0757 / 01-00-0759
+ */
+
+#ifndef __I
+  #ifdef __cplusplus
+    #define   __I   volatile       /*!< Defines 'read only' permissions    */
+  #else
+    #define   __I   volatile const /*!< Defines 'read only' permissions    */
+  #endif
+#endif
+
+#ifndef __O
+  #define   __O     volatile       /*!< Defines 'write only' permissions   */
+#endif
+
+#ifndef __IO
+  #define   __IO    volatile       /*!< Defines 'read / write' permissions */
+#endif
+
+#ifndef __C
+  #define     __C     /*nothing*/
+#endif
+
+#endif /* _ADI_CIO_MACROS_H */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/platform.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/platform.h
new file mode 100755
index 00000000000..c21be7b2935
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/platform.h
@@ -0,0 +1,56 @@
+/*!
+ *****************************************************************************
+ * @file:    platform.h
+ * @brief:   Include appropriate architecture definitions.
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#ifndef __ADI_SYS_PLATFORM_H__
+#define __ADI_SYS_PLATFORM_H__
+
+/* Include the ADI cdef header for the selected target. */
+
+#if defined(__ADUCM4050__)
+#include <ADuCM4050_cdef.h>
+#else
+#error <sys/platform.h> not configured for this target.
+#endif
+
+#endif /* __ADI_SYS_PLATFORM_H__ */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/system_ADuCM4050.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/system_ADuCM4050.h
new file mode 100755
index 00000000000..5bde78d691e
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/system_ADuCM4050.h
@@ -0,0 +1,159 @@
+/*!
+ *****************************************************************************
+ * @file:    system_ADuCM4050.h
+ * @brief:   CMSIS Cortex-M4 Device Peripheral Access Layer Header File
+ *           for ADuCM4050
+ * @version  V3.10
+ * @date     23. November 2012
+ *
+ * @note  Modified September 21 2016 Analog Devices
+******************************************************************************/
+/* Copyright (c) 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef SYSTEM_ADUCM4050_H
+#define SYSTEM_ADUCM4050_H
+
+#include <stddef.h>     /* for 'NULL' */
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+extern uint32_t SystemCoreClock;     /* System Clock Frequency (Core Clock)  */
+
+#if defined (__ICCARM__)
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm011 (rule 6.3): Types which specify sign and size should be used
+*   We use bool which is accepted by MISRA but the toolchain does not accept it
+*
+*/
+#pragma diag_suppress=Pm011
+
+#endif
+
+/*! \addtogroup SYS_Driver System Interfaces
+ *  @{
+ * System global interfaces and CMSIS required variables
+ */
+
+/*! System API function return codes */
+typedef enum
+{
+    ADI_SYS_SUCCESS = 0,  /*!< No error detected. */
+    ADI_SYS_FAILURE,      /*!< The API call failed. */
+} ADI_SYS_RESULT;
+
+
+/*! \cond PRIVATE */
+/* System clock constant */
+#define __HFOSC     26000000u
+
+/* System clock constant (may also be 16000000) */
+#define __HFXTAL    26000000u
+
+ /*System clock constant (same whether internal osc or external xtal) */
+#define __LFCLK        32768u
+
+ /*Selecting HFOSC as input for generating root clock*/
+#define HFMUX_INTERNAL_OSC_VAL      (0u << BITP_CLKG_CLK_CTL0_CLKMUX)
+
+ /*Selecting HFXTAL as input for generating root clock*/
+#define HFMUX_EXTERNAL_XTAL_VAL     (1u << BITP_CLKG_CLK_CTL0_CLKMUX)
+
+ /*Selecting SPLL as input for generating root clock*/
+#define HFMUX_SYSTEM_SPLL_VAL       (2u << BITP_CLKG_CLK_CTL0_CLKMUX)
+
+ /*Selecting GPIO as input for generating root clock*/
+#define HFMUX_GPIO_VAL              (3u << BITP_CLKG_CLK_CTL0_CLKMUX)
+
+/*! Cache controller key */
+#define CACHE_CONTROLLER_KEY 0xF123F456u
+/*! Power  key */
+#define PWRKEY_VALUE_KEY 0x4859u
+
+/**
+ * Security options
+ */
+typedef struct {
+        const uint32_t ReadProtectKeyHash[4];
+        const uint32_t CrcOfReadProtectKeyHash;
+        const uint32_t LastCRCPage;
+        const uint32_t InCircuitWriteProtectCode;
+        const uint32_t FlashBlockWriteProtect;
+
+} ADI_ADUCM4X50_SECURITY_OPTIONS;
+
+/*! \endcond*/
+
+/**
+ *  SRAM banks
+ */
+typedef uint32_t ADI_SRAM_BANK;
+
+/*! SRAM_BANK_0 */
+#define ADI_SRAM_BANK_0  (1u << 0)
+/*! SRAM_BANK_1 */
+#define ADI_SRAM_BANK_1  (1u << 1)
+/*! SRAM_BANK_2 */
+#define ADI_SRAM_BANK_2  (1u << 2)
+/*! SRAM_BANK_3 */
+#define ADI_SRAM_BANK_3  (1u << 3)
+/*! SRAM_BANK_4 */
+#define ADI_SRAM_BANK_4  (1u << 4)
+/*! SRAM_BANK_5 */
+#define ADI_SRAM_BANK_5  (1u << 5)
+/*! SRAM_BANK_6 */
+#define ADI_SRAM_BANK_6  (1u << 6)
+/*! SRAM_BANK_7 */
+#define ADI_SRAM_BANK_7  (1u << 7)
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+void adi_system_EnableCache(bool bEnable);
+ADI_SYS_RESULT adi_system_EnableRetention(ADI_SRAM_BANK eBank, bool bEnable);
+void adi_system_EnableISRAM(bool bEnable);
+
+#if defined (__ICCARM__)
+#pragma diag_default=Pm011
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_ADUCM4050_H */
+
+/*@}*/
+/*
+** EOF
+*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr.c
new file mode 100755
index 00000000000..b7153b79a8d
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr.c
@@ -0,0 +1,611 @@
+/*! *****************************************************************************
+ * @file    adi_tmr.c
+ * @brief   GP and RGB timer device driver implementation
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm011 (rule 6.3): the basic types of char, int, short, long, float, and double should not be used
+*   Necessary for stdbool.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+*
+* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file
+*   Static configuration data file is included.
+*
+* Pm140 (Rule 11.4): a cast should not be performed between a pointer type and an integral type
+*   This violation appears when deferencing the pointer to the register typedef. No way around this.
+*
+* Pm141 (Rule 11.4): a cast should not be performed between a pointer to object type and a different pointer to object type
+*   The pointer casting is necessary to allow the GP and RGB timers to abstracted into one driver. This has been approved by the PO.
+*/
+#pragma diag_suppress=Pm011,Pm073,Pm123,Pm140,Pm141,Pm143
+#endif /* __ICCARM__ */
+
+
+/** @addtogroup TMR_Driver Timer Driver
+ *  @{
+ * @brief General Purpose and RGB Timer Driver
+ * @details The timer driver controls the timer period, event capture, and
+ * pulse width modulation (PWM) features of the General Purpose (GP) Timers and
+ * the RGB Timer.
+ *  @note The application must include drivers/tmr/adi_tmr.h to use this driver
+ */
+
+#include <adi_processor.h>
+#include <adi_tmr_config.h>
+#include <rtos_map/adi_rtos_map.h>
+#include <drivers/tmr/adi_tmr.h>
+
+/* Static configuration data */
+#if ADI_TIMER_ENABLE_STATIC_CONFIG_SUPPORT == 1u
+#include "adi_tmr_data.c"
+#endif
+
+
+/* In adi_tmr_ConfigPwm, the bit positions for just PWM0 are used for PWM1 and PWM2 to simplify the code. Check here to make sure this is safe. */
+#if BITP_TMR_RGB_PWM0CTL_IDLESTATE != BITP_TMR_RGB_PWM1CTL_IDLESTATE
+#error "Bit positions for PWM0 and PWM1 do not match. Fix adi_tmr_ConfigPwm."
+#endif
+#if BITP_TMR_RGB_PWM0CTL_IDLESTATE != BITP_TMR_RGB_PWM2CTL_IDLESTATE
+#error "Bit positions for PWM0 and PWM2 do not match. Fix adi_tmr_ConfigPwm."
+#endif
+#if BITP_TMR_RGB_PWM0CTL_MATCH != BITP_TMR_RGB_PWM1CTL_MATCH
+#error "Bit positions for PWM0 and PWM1 do not match. Fix adi_tmr_ConfigPwm."
+#endif
+#if BITP_TMR_RGB_PWM0CTL_MATCH != BITP_TMR_RGB_PWM2CTL_MATCH
+#error "Bit positions for PWM0 and PWM2 do not match. Fix adi_tmr_ConfigPwm."
+#endif
+
+/*! Number of events that can be captured */
+#define ADI_TMR_NUM_EVENTS (40u)
+
+/*! \cond PRIVATE */
+
+/* Since the RGB typedef is a superset of the GP typedef, treat the GP timers as RGB timers and restrict top register access */
+static ADI_TMR_RGB_TypeDef * adi_tmr_registers[ADI_TMR_DEVICE_NUM] = {(ADI_TMR_RGB_TypeDef *) pADI_TMR0, (ADI_TMR_RGB_TypeDef *) pADI_TMR1, (ADI_TMR_RGB_TypeDef *) pADI_TMR2, pADI_TMR_RGB};
+
+/* Interrupt enums */
+static const IRQn_Type adi_tmr_interrupt[ADI_TMR_DEVICE_NUM] = {TMR0_EVT_IRQn, TMR1_EVT_IRQn, TMR2_EVT_IRQn, TMR_RGB_EVT_IRQn};
+
+/* Private data that the driver needs to retain between function calls */
+static ADI_CALLBACK adi_tmr_callbacks[ADI_TMR_DEVICE_NUM];
+static void * adi_tmr_parameters[ADI_TMR_DEVICE_NUM];
+
+static ADI_TMR_RESULT WaitForStatusBit   (ADI_TMR_DEVICE const eDevice, uint16_t nBusyBit);
+static void           CommonIntHandler   (ADI_TMR_DEVICE const eDevice);
+       void           GP_Tmr0_Int_Handler(void);
+       void           GP_Tmr1_Int_Handler(void);
+       void           GP_Tmr2_Int_Handler(void);
+       void           RGB_Tmr_Int_Handler(void);
+
+/*! \endcond */
+
+
+/*********************************************************************************
+                                    API IMPLEMENTATIONS 
+*********************************************************************************/
+
+
+/*!
+ * @brief       Initialize GP or RGB Timer
+ *
+ * @details     Setup callback function, device interrupt, and perform static configuration (if applicable).
+ *
+ * @note        This function can only be called when the timer is disabled. This function should be called
+ *              before any other functions are called.
+ *
+ * @param [in]  eDevice : Device number
+ *
+ * @param [in]  pfCallback : Callback function
+ *
+ * @param [in]  pCBParam : Callback function parameter
+ *
+ * @param [in]  bEnableInt : True to enable the device interrupt, false to disable it
+ *
+ * @return      ADI_TMR_RESULT
+ *                - #ADI_TMR_BAD_DEVICE_NUM        [D]  Invalid eDevice parameter supplied
+ *                - #ADI_TMR_OPERATION_NOT_ALLOWED [D]  Timer is currently running
+ *                - #ADI_TMR_SUCCESS                    Function call completed successfully
+ *
+ */
+ADI_TMR_RESULT adi_tmr_Init(ADI_TMR_DEVICE const eDevice, ADI_CALLBACK const pfCallback, void * const pCBParam, bool bEnableInt) {
+#ifdef ADI_DEBUG
+    /* IF(Bad device input parameter) */
+    if (eDevice >= ADI_TMR_DEVICE_NUM) {
+        return ADI_TMR_BAD_DEVICE_NUM;
+    } /* ENDIF */
+    /* IF(The timer is already running) */
+    if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_EN) == BITM_TMR_RGB_CTL_EN) {
+        return ADI_TMR_OPERATION_NOT_ALLOWED;
+    } /* ENDIF */         
+#endif
+    /* Setup the callback function */
+    adi_tmr_callbacks [eDevice] = pfCallback;
+    adi_tmr_parameters[eDevice] = pCBParam;
+
+    /* IF(Enable interrupt) */
+    if (bEnableInt == true) {
+        NVIC_EnableIRQ(adi_tmr_interrupt[eDevice]);
+    /* ELSE(Disable interrupt) */
+    } else {
+        NVIC_DisableIRQ(adi_tmr_interrupt[eDevice]);
+    } /* ENDIF */
+
+    /* Static configuration */
+#if ADI_TIMER_ENABLE_STATIC_CONFIG_SUPPORT == 1u
+    adi_tmr_registers[eDevice]->CTL           = aTimerCtlConfig     [eDevice];
+    adi_tmr_registers[eDevice]->LOAD          = aTimerLoadConfig    [eDevice];
+    adi_tmr_registers[eDevice]->ALOAD         = aTimerALoadConfig   [eDevice];
+    adi_tmr_registers[eDevice]->EVENTSELECT   = aTimerEventConfig   [eDevice];
+    adi_tmr_registers[eDevice]->PWM0CTL       = aTimerPwmCtlConfig  [eDevice];
+    adi_tmr_registers[eDevice]->PWM0MATCH     = aTimerPwmMatchConfig[eDevice];    
+
+    /* IF(Initializing the RGB timer, there are 2 other PWM outputs to configure) */
+    if (eDevice == ADI_TMR_DEVICE_RGB) { 
+        /* The array is bumped by 1 to get to the 5th entry in the static config array, which contains RGB PWM1 */
+        adi_tmr_registers[eDevice]->PWM1CTL   = aTimerPwmCtlConfig  [eDevice+1u];
+        adi_tmr_registers[eDevice]->PWM1MATCH = aTimerPwmMatchConfig[eDevice+1u];
+        /* The array is bumped by 2 to get to the 6th entry in the static config array, which contains RGB PWM2 */
+        adi_tmr_registers[eDevice]->PWM2CTL   = aTimerPwmCtlConfig  [eDevice+2u];        
+        adi_tmr_registers[eDevice]->PWM2MATCH = aTimerPwmMatchConfig[eDevice+2u];
+    } /* ENDIF */
+#endif
+
+    return ADI_TMR_SUCCESS;
+}
+
+
+/*!
+ * @brief       Configure GP or RGB Timer
+ *
+ * @details     Configure the basic hardware timer parameters.
+ *
+ * @note        This function can only be called when the timer is disabled.
+ *
+ * @param [in]  eDevice : Device number
+ *
+ * @param [in]  timerConfig : Timer configuration structure, filled by user prior to function call
+ *
+ * @return      ADI_TMR_RESULT
+ *                - #ADI_TMR_BAD_DEVICE_NUM           [D] Invalid eDevice parameter supplied
+ *                - #ADI_TMR_BAD_RELOAD_CONFIGURATION [D] bPeriodic is false and bReloading is true
+ *                - #ADI_TMR_OPERATION_NOT_ALLOWED    [D] Timer is currently running
+ *                - #ADI_TMR_DEVICE_BUSY                  Timer is busy processing a previous control register write
+ *                - #ADI_TMR_SUCCESS                      Function call completed successfully
+ *
+ */
+ADI_TMR_RESULT adi_tmr_ConfigTimer(ADI_TMR_DEVICE const eDevice, ADI_TMR_CONFIG timerConfig) {
+    uint16_t nTemp;
+#ifdef ADI_DEBUG
+    /* IF(Bad device input parameter) */
+    if (eDevice >= ADI_TMR_DEVICE_NUM) {
+        return ADI_TMR_BAD_DEVICE_NUM;
+    } /* ENDIF */
+    /* IF(Bad configuration, cannot enable reloading while in free running mode) */
+    if ((timerConfig.bPeriodic == false) && (timerConfig.bReloading == true)) {
+        return ADI_TMR_BAD_RELOAD_CONFIGURATION;
+    } /* ENDIF */
+    /* IF(The timer is already running) */
+    if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_EN) == BITM_TMR_RGB_CTL_EN) {
+        return ADI_TMR_OPERATION_NOT_ALLOWED;
+    } /* ENDIF */
+#endif
+    /* Set the load registers */
+    adi_tmr_registers[eDevice]->LOAD  = timerConfig.nLoad;
+    adi_tmr_registers[eDevice]->ALOAD = timerConfig.nAsyncLoad;
+
+    /* IF(Busy bit does not clear after waiting) */
+    if (ADI_TMR_SUCCESS != WaitForStatusBit(eDevice, (uint16_t) BITM_TMR_RGB_STAT_BUSY)) {
+        return ADI_TMR_DEVICE_BUSY; 
+    } /* ENDIF */
+
+    /* Read the control register and clear everything aside to the event capture bits, which are the only fields not set in this function */
+    nTemp  = adi_tmr_registers[eDevice]->CTL;
+    nTemp &= (uint16_t) (BITM_TMR_RGB_CTL_EVTEN | BITM_TMR_RGB_CTL_RSTEN);
+
+    /* Setup the prescaler and the clock source */
+    nTemp |=  (uint16_t)(((uint16_t) timerConfig.ePrescaler  ) << BITP_TMR_RGB_CTL_PRE);
+    nTemp |=  (uint16_t)(((uint16_t) timerConfig.eClockSource) << BITP_TMR_RGB_CTL_CLK);
+
+    /* IF(Periodic mode) */
+    if (timerConfig.bPeriodic == true) {
+        nTemp |= (1u << BITP_TMR_RGB_CTL_MODE);
+    } /* ENDIF */    
+    
+    /* IF(Counting up) */
+    if (timerConfig.bCountingUp == true) {
+        nTemp |= (1u << BITP_TMR_RGB_CTL_UP);
+    } /* ENDIF */
+    
+    /* IF(Reloading is enabled) */
+    if (timerConfig.bReloading == true) {
+        nTemp |= (1u << BITP_TMR_RGB_CTL_RLD);
+    } /* ENDIF */
+    
+    /* IF(Sync bypass is enabled) */
+    if (timerConfig.bSyncBypass == true) {
+        nTemp |= (1u << BITP_TMR_RGB_CTL_SYNCBYP);
+    } /* ENDIF */
+    
+    /* Update the control register with the new configuration */
+    adi_tmr_registers[eDevice]->CTL = nTemp;
+
+    return ADI_TMR_SUCCESS;
+}
+
+
+/*!
+ * @brief       Setup GP or RGB Timer Event Capture
+ *
+ * @details     The timer can be configured to capture the timer value when a specific event occurs. The
+ *              list of events can be found in the hardware reference manual. The callback function specified
+ *              in #adi_tmr_Init will be supplied #ADI_TMR_EVENT_CAPTURE to indicate the event occured. The 
+ *              user can then read the captured value by calling #adi_tmr_GetCaptureCount.
+ *
+ * @note        This function can only be called when the timer is disabled.
+ *
+ * @param [in]  eDevice : Device number
+ *
+ * @param [in]  eventConfig : Event configuration structure, filled by user prior to function call
+ *
+ * @return      ADI_TMR_RESULT
+ *                - #ADI_TMR_BAD_DEVICE_NUM        [D] Invalid eDevice parameter supplied
+ *                - #ADI_TMR_BAD_EVENT_ID          [D] Event ID was not out of the valid range [0,#ADI_TMR_NUM_EVENTS]
+ *                - #ADI_TMR_OPERATION_NOT_ALLOWED [D] Timer is currently running
+ *                - #ADI_TMR_DEVICE_BUSY               Timer is busy processing a previous control register write
+ *                - #ADI_TMR_SUCCESS                   Function call completed successfully
+ *
+ */
+ADI_TMR_RESULT adi_tmr_ConfigEvent(ADI_TMR_DEVICE const eDevice, ADI_TMR_EVENT_CONFIG eventConfig) {
+#ifdef ADI_DEBUG
+    /* IF(Bad device input parameter) */
+    if (eDevice >= ADI_TMR_DEVICE_NUM) {
+        return ADI_TMR_BAD_DEVICE_NUM;
+    } /* ENDIF */
+    /* IF(Bad event input parameter) */
+    if (eventConfig.nEventID >= ADI_TMR_NUM_EVENTS) {
+        return ADI_TMR_BAD_EVENT_ID;
+    } /* ENDIF */
+    /* IF(The timer is already running) */
+    if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_EN) == BITM_TMR_RGB_CTL_EN) {
+        return ADI_TMR_OPERATION_NOT_ALLOWED;
+    } /* ENDIF */        
+#endif
+    /* Set the event number */
+    adi_tmr_registers[eDevice]->EVENTSELECT = (uint16_t) eventConfig.nEventID;
+
+    /* IF(Busy bit does not clear after waiting) */
+    if (ADI_TMR_SUCCESS != WaitForStatusBit(eDevice, (uint16_t) BITM_TMR_RGB_STAT_BUSY)) {
+        return ADI_TMR_DEVICE_BUSY; 
+    } /* ENDIF */
+
+    /* Clear the event enable bit and keep the other bits */
+    adi_tmr_registers[eDevice]->CTL &= (uint16_t) ~(BITM_TMR_RGB_CTL_EVTEN | BITM_TMR_RGB_CTL_RSTEN);
+
+    /* IF(Turning event capture on) */
+    if (eventConfig.bEnable == true) {
+        adi_tmr_registers[eDevice]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_EVTEN;
+    } /* ENDIF */
+
+    /* IF(Enabling reset on event capture) */
+    if (eventConfig.bPrescaleReset == true) {
+        adi_tmr_registers[eDevice]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_RSTEN;
+    } /* ENDIF */
+
+    return ADI_TMR_SUCCESS;
+}
+
+
+/*!
+ * @brief       Setup GP or RGB Timer Pulse Width Modulation
+ *
+ * @details     The timer can be configured to generate a pulse width modulation output signal.
+ *              The period of this signal is simply determined by the period of timer. The duty
+ *              cycle will be 50% in toggle mode, or can be configured by the user for a different
+ *              value using the match value. The pulse will toggle when the timer count matches
+ *              the match value. The user can also specify the polarity of the signal by choosing
+ *              if the signal idles low or high. GPIO muxing will be required to use the PWM output.
+ *
+ * @note        This function can only be called when the timer is disabled.
+ *
+ * @param [in]  eDevice : Device number
+ *
+ * @param [in]  pwmConfig : PWM configuration structure, filled by user prior to function call
+ *
+ * @return      ADI_TMR_RESULT
+ *                - #ADI_TMR_BAD_DEVICE_NUM          [D] Invalid eDevice parameter supplied
+ *                - #ADI_TMR_OPERATION_NOT_ALLOWED   [D] Timer is currently running
+ *                - #ADI_TMR_BAD_PWM_NUM             [D] Invalid eOutput parameter supplied
+ *                - #ADI_TMR_SUCCESS                     Function call completed successfully
+ *
+ */
+ADI_TMR_RESULT adi_tmr_ConfigPwm(ADI_TMR_DEVICE const eDevice, ADI_TMR_PWM_CONFIG pwmConfig) {
+    uint16_t nControl = 0u;
+#ifdef ADI_DEBUG
+    /* IF(Bad device input parameter) */
+    if (eDevice >= ADI_TMR_DEVICE_NUM) {
+        return ADI_TMR_BAD_DEVICE_NUM;
+    } /* ENDIF */
+    /* IF(The timer is already running) */
+    if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_EN) == BITM_TMR_RGB_CTL_EN) {
+        return ADI_TMR_OPERATION_NOT_ALLOWED;
+    } /* ENDIF */
+    /* IF(Bad PWM output and device combo OR bad PWM output) */
+    if (((eDevice != ADI_TMR_DEVICE_RGB) && (pwmConfig.eOutput != ADI_TMR_PWM_OUTPUT_0)) || (pwmConfig.eOutput >= ADI_TMR_PWM_OUTPUT_NUM)) {
+        return ADI_TMR_BAD_PWM_NUM;
+    } /* ENDIF */
+#endif
+    /* IF(Idle high is set) */
+    if (pwmConfig.bIdleHigh == true) {
+        nControl = (1u << ((uint16_t) BITP_TMR_RGB_PWM0CTL_IDLESTATE));
+    } /* ENDIF */
+ 
+    /* IF(Match mode is enabled) */
+    if (pwmConfig.bMatch == true) {
+        nControl |= (1u << ((uint16_t) BITP_TMR_RGB_PWM0CTL_MATCH));
+    } /* ENDIF */    
+    
+    /* IF(PWM output 0) */
+    if (pwmConfig.eOutput == ADI_TMR_PWM_OUTPUT_0) {
+        adi_tmr_registers[eDevice]->PWM0CTL   = nControl;
+        adi_tmr_registers[eDevice]->PWM0MATCH = pwmConfig.nMatchValue; 
+    /* IF(PWM output 1) */
+    } else if (pwmConfig.eOutput == ADI_TMR_PWM_OUTPUT_1) {
+        adi_tmr_registers[eDevice]->PWM1CTL   = nControl;
+        adi_tmr_registers[eDevice]->PWM1MATCH = pwmConfig.nMatchValue;     
+    /* ELSE(PWM output 2) */
+    } else {
+        adi_tmr_registers[eDevice]->PWM2CTL   = nControl;
+        adi_tmr_registers[eDevice]->PWM2MATCH = pwmConfig.nMatchValue;
+    } /* ENDIF */
+
+    return ADI_TMR_SUCCESS;
+}
+
+
+/*!
+ * @brief       Enable or Disable the GP or RGB Timer
+ *
+ * @details     Start or stop the timer.
+ *
+ * @param [in]  eDevice : Device number
+ *
+ * @param [in]  bEnable : True to enable, false to disable
+ *
+ * @return      ADI_TMR_RESULT
+ *                - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied
+ *                - #ADI_TMR_DEVICE_BUSY        Timer is busy processing a previous control register write
+ *                - #ADI_TMR_SUCCESS            Function call completed successfully
+ *
+ */
+ADI_TMR_RESULT adi_tmr_Enable(ADI_TMR_DEVICE const eDevice, bool bEnable) {
+#ifdef ADI_DEBUG
+    /* IF(Bad device input parameter) */
+    if (eDevice >= ADI_TMR_DEVICE_NUM) {
+        return ADI_TMR_BAD_DEVICE_NUM;
+    } /* ENDIF */
+#endif
+    /* IF(Busy bit does not clear after waiting) */
+    if (ADI_TMR_SUCCESS != WaitForStatusBit(eDevice, (uint16_t) BITM_TMR_RGB_STAT_BUSY)) {
+        return ADI_TMR_DEVICE_BUSY; 
+    } /* ENDIF */
+
+    /* Clear the enable bit and keep the other bits */
+    adi_tmr_registers[eDevice]->CTL &= (uint16_t) ~BITM_TMR_RGB_CTL_EN;
+
+    /* IF(Turning the timer on) */
+    if (bEnable == true) {
+        adi_tmr_registers[eDevice]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_EN;
+    } /* ENDIF */
+
+    return ADI_TMR_SUCCESS;
+}
+
+
+/*!
+ * @brief       Get GP or RGB Timer Current Count
+ *
+ * @details     Read the timer.
+ *
+ * @param [in]  eDevice : Device number
+ *
+ * @param [out] pCount : Pointer to the result.
+ *
+ * @return      ADI_TMR_RESULT
+ *                - #ADI_TMR_BAD_DEVICE_NUM [D]      Invalid eDevice parameter supplied
+ *                - #ADI_TMR_NULL_POINTER   [D]      Invalid pCount parameter supplied
+ *                - #ADI_TMR_SUCCESS                 Function call completed successfully
+ *
+ */
+ADI_TMR_RESULT adi_tmr_GetCurrentCount(ADI_TMR_DEVICE const eDevice, uint16_t *pCount) {
+#ifdef ADI_DEBUG
+    /* IF(Bad device input parameter) */
+    if (eDevice >= ADI_TMR_DEVICE_NUM) {
+        return ADI_TMR_BAD_DEVICE_NUM;
+    } /* ENDIF */
+    /* IF(Null pointer) */
+    if (pCount == NULL) {
+        return ADI_TMR_NULL_POINTER; 
+    } /* ENDIF */
+#endif
+    *pCount = adi_tmr_registers[eDevice]->CURCNT;
+    return ADI_TMR_SUCCESS;
+}
+
+
+/*!
+ * @brief       Get GP or RGB Timer Captured Count
+ *
+ * @details     Read the captured timer value. This should be called after the callback function
+ *              is called with #ADI_TMR_EVENT_CAPTURE in the Event field.
+ *
+ * @param [in]  eDevice : Device number
+ *
+ * @param [out] pCount : Pointer to the result.
+ *
+ * @return      ADI_TMR_RESULT
+ *                - #ADI_TMR_BAD_DEVICE_NUM [D]      Invalid eDevice parameter supplied
+ *                - #ADI_TMR_NULL_POINTER   [D]      Invalid pCount parameter supplied
+ *                - #ADI_TMR_SUCCESS                 Function call completed successfully
+ *
+ */
+ADI_TMR_RESULT adi_tmr_GetCaptureCount(ADI_TMR_DEVICE const eDevice, uint16_t *pCount) {
+#ifdef ADI_DEBUG
+    /* IF(Bad device input parameter) */
+    if (eDevice >= ADI_TMR_DEVICE_NUM) {
+        return ADI_TMR_BAD_DEVICE_NUM;
+    } /* ENDIF */
+    /* IF(Null pointer) */
+    if (pCount == NULL) {
+        return ADI_TMR_NULL_POINTER; 
+    } /* ENDIF */
+#endif
+    *pCount = adi_tmr_registers[eDevice]->CAPTURE;
+    return ADI_TMR_SUCCESS;
+}
+
+
+/*!
+ * @brief       Reload GP or RGB Timer
+ *
+ * @details     Only relevent in peridic mode and when bReloading was set to 
+ *              true when configuring the timer. Calling this function will
+ *              reload (i.e. reset) the timer to the LOAD value.
+ *
+ * @param [in]  eDevice : Device number
+ *
+ * @return      ADI_TMR_RESULT
+ *                - #ADI_TMR_BAD_DEVICE_NUM  [D]     Invalid eDevice parameter supplied
+ *                - #ADI_TMR_RELOAD_DISABLED [D]     Reloading not enabled for this timer
+ *                - #ADI_TMR_DEVICE_BUSY             Reload did not take effect in time
+ *                - #ADI_TMR_SUCCESS                 Function call completed successfully
+ *
+ */
+ADI_TMR_RESULT adi_tmr_Reload(ADI_TMR_DEVICE const eDevice) {
+#ifdef ADI_DEBUG
+    /* IF(Bad device input parameter) */
+    if (eDevice >= ADI_TMR_DEVICE_NUM) {
+        return ADI_TMR_BAD_DEVICE_NUM;
+    } /* ENDIF */
+    /* IF(Reloading has not been enabled) */
+    if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_RLD) != BITM_TMR_RGB_CTL_RLD) {
+        return ADI_TMR_RELOAD_DISABLED;
+    } /* ENDIF */
+#endif
+    /* Clear the timeout bit to cause a reload to happen */
+    adi_tmr_registers[eDevice]->CLRINT = BITM_TMR_RGB_CLRINT_TIMEOUT;
+    /* IF(The clear interrupt does not take effect in a reasonable amount of time) */
+    if (ADI_TMR_SUCCESS != WaitForStatusBit(eDevice, (uint16_t) BITM_TMR_RGB_STAT_PDOK)) {
+        return ADI_TMR_DEVICE_BUSY; 
+    } /* ENDIF */    
+    return ADI_TMR_SUCCESS;
+}
+
+
+/*********************************************************************************
+                                   PRIVATE FUNCTIONS
+*********************************************************************************/
+
+ /*! \cond PRIVATE */
+
+static ADI_TMR_RESULT WaitForStatusBit(ADI_TMR_DEVICE const eDevice, uint16_t nBusyBit) {
+    /* FOR(Number of arbitrary iterations) */
+    for (uint16_t i = 0u; i < 1000u; i++) { 
+            /* IF(Busy bit is low) */
+            if ((adi_tmr_registers[(eDevice)]->STAT & nBusyBit) == ((uint16_t) 0u)) {
+                return ADI_TMR_SUCCESS;
+            } /* ENDIF */
+    } /* ENDFOR */
+    return ADI_TMR_DEVICE_BUSY;
+}
+
+static void CommonIntHandler(ADI_TMR_DEVICE const eDevice) {
+    /* Read status register */
+    uint16_t IntStatus = adi_tmr_registers[eDevice]->STAT;
+    /* IF(Callback function has been set) */
+    if(adi_tmr_callbacks[eDevice] != NULL) {
+        /* IF(Timeout interrupt occurred) */
+        if((IntStatus & ((uint16_t) BITM_TMR_RGB_STAT_TIMEOUT)) != ((uint16_t) 0u)) {
+            adi_tmr_callbacks[eDevice](adi_tmr_parameters[eDevice], ADI_TMR_EVENT_TIMEOUT, NULL);
+        } /* ENDIF */
+        /* IF(Event capture interrupt occurred) */
+        if((IntStatus & ((uint16_t) BITM_TMR_RGB_STAT_CAPTURE)) != ((uint16_t) 0u)) {
+            adi_tmr_callbacks[eDevice](adi_tmr_parameters[eDevice], ADI_TMR_EVENT_CAPTURE, NULL);
+        } /* ENDIF */
+    } /* ENDIF */
+    /* Clear pending interrupt */
+    adi_tmr_registers[eDevice]->CLRINT = (BITM_TMR_RGB_CLRINT_EVTCAPT | BITM_TMR_RGB_CLRINT_TIMEOUT);
+}
+
+void GP_Tmr0_Int_Handler(void) {
+    ISR_PROLOG()
+    CommonIntHandler(ADI_TMR_DEVICE_GP0);
+    ISR_EPILOG()
+}
+
+void GP_Tmr1_Int_Handler(void) {
+    ISR_PROLOG()
+    CommonIntHandler(ADI_TMR_DEVICE_GP1);
+    ISR_EPILOG()
+}
+
+void GP_Tmr2_Int_Handler(void) {
+    ISR_PROLOG()
+    CommonIntHandler(ADI_TMR_DEVICE_GP2);
+    ISR_EPILOG()
+}
+
+void RGB_Tmr_Int_Handler(void) {
+    ISR_PROLOG()
+    CommonIntHandler(ADI_TMR_DEVICE_RGB);
+    ISR_EPILOG()
+}
+
+/*! \endcond */
+
+/*! @} */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr_data.c
new file mode 100755
index 00000000000..31b2dbe8fc8
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr_data.c
@@ -0,0 +1,154 @@
+/*! *****************************************************************************
+ * @file    adi_tmr_data.c
+ * @brief   GP and RGB timer static configuration data
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+
+#ifndef ADI_TMR_DATA
+#define ADI_TMR_DATA
+
+#include <adi_processor.h>
+#include <stdlib.h>
+#include <adi_tmr_config.h>
+#include <drivers/tmr/adi_tmr.h>
+
+/* CTL register static configuration */
+static uint16_t aTimerCtlConfig[] =
+{
+    (TMR0_CFG_COUNT_UP              << BITP_TMR_RGB_CTL_UP)      |
+    (TMR0_CFG_MODE                  << BITP_TMR_RGB_CTL_MODE)    |
+    (TMR0_CFG_PRESCALE_FACTOR       << BITP_TMR_RGB_CTL_PRE)     |
+    (TMR0_CFG_CLOCK_SOURCE          << BITP_TMR_RGB_CTL_CLK)     |
+    (TMR0_CFG_ENABLE_RELOADING      << BITP_TMR_RGB_CTL_RLD)     |
+    (TMR0_CFG_ENABLE_SYNC_BYPASS    << BITP_TMR_RGB_CTL_SYNCBYP) |
+    (TMR0_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN)   |
+    (TMR0_CFG_ENABLE_EVENT_CAPTURE  << BITP_TMR_RGB_CTL_EVTEN),
+
+    (TMR1_CFG_COUNT_UP              << BITP_TMR_RGB_CTL_UP)      |
+    (TMR1_CFG_MODE                  << BITP_TMR_RGB_CTL_MODE)    |
+    (TMR1_CFG_PRESCALE_FACTOR       << BITP_TMR_RGB_CTL_PRE)     |
+    (TMR1_CFG_CLOCK_SOURCE          << BITP_TMR_RGB_CTL_CLK)     |
+    (TMR1_CFG_ENABLE_RELOADING      << BITP_TMR_RGB_CTL_RLD)     |
+    (TMR1_CFG_ENABLE_SYNC_BYPASS    << BITP_TMR_RGB_CTL_SYNCBYP) |
+    (TMR1_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN)   |
+    (TMR1_CFG_ENABLE_EVENT_CAPTURE  << BITP_TMR_RGB_CTL_EVTEN),
+
+    (TMR2_CFG_COUNT_UP              << BITP_TMR_RGB_CTL_UP)      |
+    (TMR2_CFG_MODE                  << BITP_TMR_RGB_CTL_MODE)    |
+    (TMR2_CFG_PRESCALE_FACTOR       << BITP_TMR_RGB_CTL_PRE)     |
+    (TMR2_CFG_CLOCK_SOURCE          << BITP_TMR_RGB_CTL_CLK)     |
+    (TMR2_CFG_ENABLE_RELOADING      << BITP_TMR_RGB_CTL_RLD)     |
+    (TMR2_CFG_ENABLE_SYNC_BYPASS    << BITP_TMR_RGB_CTL_SYNCBYP) |
+    (TMR2_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN)   |
+    (TMR2_CFG_ENABLE_EVENT_CAPTURE  << BITP_TMR_RGB_CTL_EVTEN),
+
+    (TMR3_CFG_COUNT_UP              << BITP_TMR_RGB_CTL_UP)      |
+    (TMR3_CFG_MODE                  << BITP_TMR_RGB_CTL_MODE)    |
+    (TMR3_CFG_PRESCALE_FACTOR       << BITP_TMR_RGB_CTL_PRE)     |
+    (TMR3_CFG_CLOCK_SOURCE          << BITP_TMR_RGB_CTL_CLK)     |
+    (TMR3_CFG_ENABLE_RELOADING      << BITP_TMR_RGB_CTL_RLD)     |
+    (TMR3_CFG_ENABLE_SYNC_BYPASS    << BITP_TMR_RGB_CTL_SYNCBYP) |
+    (TMR3_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN)   |
+    (TMR3_CFG_ENABLE_EVENT_CAPTURE  << BITP_TMR_RGB_CTL_EVTEN),
+};
+
+/* LOAD register static configuration */
+static uint16_t aTimerLoadConfig[] =
+{
+    TMR0_CFG_LOAD_VALUE,
+    TMR1_CFG_LOAD_VALUE,
+    TMR2_CFG_LOAD_VALUE,
+    TMR3_CFG_LOAD_VALUE,
+};
+
+/* Asynchronous LOAD static configuraton */
+static uint16_t aTimerALoadConfig[] =
+{
+    TMR0_CFG_ASYNC_LOAD_VALUE,
+    TMR1_CFG_ASYNC_LOAD_VALUE,
+    TMR2_CFG_ASYNC_LOAD_VALUE,
+    TMR3_CFG_ASYNC_LOAD_VALUE,
+};
+
+/* EVENTSELECT static configuration */
+static uint16_t aTimerEventConfig[] =
+{
+    TMR0_CFG_EVENT_CAPTURE,
+    TMR1_CFG_EVENT_CAPTURE,
+    TMR2_CFG_EVENT_CAPTURE,
+    TMR3_CFG_EVENT_CAPTURE,
+};
+
+/* PWM CTL static configuration */
+static uint16_t aTimerPwmCtlConfig[] =
+{
+  (TMR0_CFG_PWM0_IDLE_STATE  << BITP_TMR_RGB_PWM0CTL_IDLESTATE) |
+  (TMR0_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH),
+
+  (TMR1_CFG_PWM0_IDLE_STATE  << BITP_TMR_RGB_PWM0CTL_IDLESTATE) |
+  (TMR1_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH),
+
+  (TMR2_CFG_PWM0_IDLE_STATE  << BITP_TMR_RGB_PWM0CTL_IDLESTATE) |
+  (TMR2_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH),
+
+  (TMR3_CFG_PWM0_IDLE_STATE  << BITP_TMR_RGB_PWM0CTL_IDLESTATE) |
+  (TMR3_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH),
+
+  (TMR3_CFG_PWM1_IDLE_STATE  << BITP_TMR_RGB_PWM1CTL_IDLESTATE) |
+  (TMR3_CFG_PWM1_MATCH_VALUE << BITP_TMR_RGB_PWM1CTL_MATCH),
+
+  (TMR3_CFG_PWM2_IDLE_STATE  << BITP_TMR_RGB_PWM2CTL_IDLESTATE) |
+  (TMR3_CFG_PWM2_MATCH_VALUE << BITP_TMR_RGB_PWM2CTL_MATCH),
+};
+
+/* PWM MATCH static configuration */
+static uint16_t aTimerPwmMatchConfig[] = {
+  TMR0_CFG_PWM0_MATCH_VALUE,
+  TMR1_CFG_PWM0_MATCH_VALUE,
+  TMR2_CFG_PWM0_MATCH_VALUE,
+  TMR3_CFG_PWM0_MATCH_VALUE,
+  TMR3_CFG_PWM1_MATCH_VALUE,
+  TMR3_CFG_PWM2_MATCH_VALUE
+};
+
+
+#endif /* ADI_TMR_DATA */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart.c
new file mode 100755
index 00000000000..d1f72d60482
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart.c
@@ -0,0 +1,2779 @@
+/*! *****************************************************************************
+ * @file:     adi_uart.c
+ * @brief:    uart device driver implementation
+ * @details:  This file contains the UART device driver functions
+ -----------------------------------------------------------------------------
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+/** @addtogroup UART_Driver
+ *  @{
+ *  @brief UART Driver
+ *  @note The application must include drivers/uart/adi_uart.h to use this
+ *  driver
+ *  @note This driver requires the DMA driver.The application must
+ *  include the DMA driver sources to avoid link errors.
+ */
+
+/*!  \cond PRIVATE */
+#include <drivers/uart/adi_uart.h>
+#include <drivers/dma/adi_dma.h>
+#include "adi_uart_def.h"
+#include <adi_cyclecount.h>
+
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm50: (MISRA C 2004 rule 14.3): a null statement shall only occur on a line by itself,
+*                                 and shall not have any other text on the same line
+*                                 Some Macros, such as ISR_PROLOGUE, may not have any expansion
+*                                 resulting in just the terminating ';'.
+*
+* Pm073 (rule 14.7): A function should have a single point of exit.
+* Pm143 (rule 14.7): A function should have a single point of exit at the end of the function.
+*                    Multiple returns are used for error handling.
+*
+* Pm088 (rule 17.4): Pointer arithmetic should not be used.
+*                    Relying on pointer arithmetic for buffer handling.
+*
+* Pm123 (rule 18.5): There shall be no definition of objects in a header file.
+*
+* Pm140 (rule 11.3): A cast should not be performed between a pointer type and an integral type.
+*                    MMR addresses are defined as simple constants. Accessing the MMR requires casting to a pointer type.
+*
+* Pm152 (rule 17.4): Array indexing shall only be applied to objects defined as an array type.
+*                    Relying on pointer arithmetic for buffer handling and
+*                    Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors.
+*
+* Pm008: Code should not be commented out.
+         This code was commented out to show what the autobaud equations would look like if there were floating point precision.
+         Ideally this would be the case but for the sake of footprint size we will leave it at single point precision.
+*/
+#pragma diag_suppress=Pm050,Pm073,Pm088,Pm123,Pm140,Pm143,Pm152,Pm008
+#endif /* __ICCARM__ */
+
+
+
+
+/**********************************************************
+ * UART Data
+ **********************************************************/
+static  ADI_UART_DEVICE_INFO uart_device_info[ ] =
+{
+  {
+    UART0_TX_CHANn,             /*!< DMA channel number for UART0 Tx. */
+    UART0_RX_CHANn,             /*!< DMA channel number for UART0 Rx. */
+    DMA0_CH8_DONE_IRQn,         /*!< DMA channel IRQ for UART0 Tx.    */
+    DMA0_CH9_DONE_IRQn,         /*!< DMA channel IRQ for UART0 Rx.    */
+    (IRQn_Type)INTR_UART0_EVT,  /*!< UART0 interrupt ID.              */
+    pADI_UART0,                 /*!< Start address of UART0.          */
+    NULL                        /*!< Device Handle for UART0.         */
+  },
+  {
+    UART1_TX_CHANn,             /*!< DMA channel number for UART1 Tx. */
+    UART1_RX_CHANn,             /*!< DMA channel number for UART1 Rx. */
+    DMA0_CH25_DONE_IRQn,        /*!< DMA channel IRQ for UART1 Tx.    */
+    DMA0_CH26_DONE_IRQn,        /*!< DMA channel IRQ for UART1 Rx.    */
+    (IRQn_Type)INTR_UART1_EVT,  /*!< UART1 interrupt ID.              */
+    pADI_UART1,                 /*!< Start address of UART1.          */
+    NULL                        /*!< Device Handle for UART1.         */
+  },
+};
+
+static const ADI_UART_CONFIG gUARTCfg[ ] =
+{
+    {
+      /* Line control register.                                         */
+      ((ADI_UART0_CFG_WORD_LENGTH          << BITP_UART_LCR_WLS)  |
+       (ADI_UART0_CFG_STOP_BIT             << BITP_UART_LCR_STOP) |
+       (ADI_UART0_CFG_ENABLE_PARITY        << BITP_UART_LCR_PEN)  |
+       (ADI_UART0_CFG_PARITY_SELECTION     << BITP_UART_LCR_EPS)  |
+       (ADI_UART0_CFG_ENABLE_STICKY_PARITY << BITP_UART_LCR_SP)),
+
+      /* Div-C in baudrate divider register.                            */
+      ADI_UART0_CFG_DIVC,
+
+      /* Div-M and Div-N in fractional baudrate Register.               */
+      (((uint32_t)ADI_UART0_CFG_DIVN       << BITP_UART_FBR_DIVN) |
+       ((uint32_t)ADI_UART0_CFG_DIVM       << BITP_UART_FBR_DIVM) |
+       ((uint32_t)BITM_UART_FBR_FBEN)),
+
+      /* Over sample rate in second line control register.              */
+      ADI_UART0_CFG_OSR,
+
+      /* FIFO control register.                                         */
+      ((ADI_UART0_CFG_ENABLE_FIFO          << BITP_UART_FCR_FIFOEN)|
+       (ADI_UART0_CFG_TRIG_LEVEL           << BITP_UART_FCR_RFTRIG)),
+
+      /* Half duplex control register.                                  */
+      ((ADI_UART0_CFG_SOUT_POLARITY        << BITP_UART_RSC_OENP)  |
+       (ADI_UART0_CFG_DEASSERTION          << BITP_UART_RSC_OENSP) |
+       (ADI_UART0_CFG_DISABLE_RX           << BITP_UART_RSC_DISRX) |
+       (ADI_UART0_CFG_HOLD_TX              << BITP_UART_RSC_DISTX)),
+
+      /* Interrupt enable register.                                     */
+      ((ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT << BITP_UART_IEN_EDSSI) |
+      (ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT     << BITP_UART_IEN_ELSI))
+
+    },
+
+    {
+      /* Line control register.                                         */
+      ((ADI_UART1_CFG_WORD_LENGTH          << BITP_UART_LCR_WLS)  |
+       (ADI_UART1_CFG_STOP_BIT             << BITP_UART_LCR_STOP) |
+       (ADI_UART1_CFG_ENABLE_PARITY        << BITP_UART_LCR_PEN)  |
+       (ADI_UART1_CFG_PARITY_SELECTION     << BITP_UART_LCR_EPS)  |
+       (ADI_UART1_CFG_ENABLE_STICKY_PARITY << BITP_UART_LCR_SP)),
+
+      /* Div-C in Baudrate divider register.                            */
+      ADI_UART1_CFG_DIVC,
+
+      /* Div-M and Div-N in fractional baudrate Register.               */
+      (((uint32_t)ADI_UART1_CFG_DIVN       << BITP_UART_FBR_DIVN) |
+       ((uint32_t)ADI_UART1_CFG_DIVM       << BITP_UART_FBR_DIVM) |
+       ((uint32_t)BITM_UART_FBR_FBEN)),
+
+      /* Over sample rate in second line control register.              */
+      ADI_UART1_CFG_OSR,
+
+      /* FIFO control register.                                         */
+      ((ADI_UART1_CFG_ENABLE_FIFO          << BITP_UART_FCR_FIFOEN)|
+       (ADI_UART1_CFG_TRIG_LEVEL           << BITP_UART_FCR_RFTRIG)),
+
+      /* Half duplex control register.                                  */
+      ((ADI_UART1_CFG_SOUT_POLARITY        << BITP_UART_RSC_OENP)  |
+       (ADI_UART1_CFG_DEASSERTION          << BITP_UART_RSC_OENSP) |
+       (ADI_UART1_CFG_DISABLE_RX           << BITP_UART_RSC_DISRX) |
+       (ADI_UART1_CFG_HOLD_TX              << BITP_UART_RSC_DISTX)),
+
+      /* Interrupt enable register.                                     */
+      ((ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT << BITP_UART_IEN_EDSSI) |
+       (ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT    << BITP_UART_IEN_ELSI))
+    }
+};
+
+/*! \endcond */
+
+/*! Number of UART devices available on the chip. */
+#define ADI_UART_NUM_DEVICES (sizeof(uart_device_info)/sizeof(ADI_UART_DEVICE_INFO))
+
+/* Override "weak" default binding in startup.c */
+/*! \cond PRIVATE */
+extern void UART0_Int_Handler(void);
+extern void UART1_Int_Handler(void);
+extern void DMA_UART0_TX_Int_Handler(void);
+extern void DMA_UART0_RX_Int_Handler(void);
+extern void DMA_UART1_TX_Int_Handler(void);
+extern void DMA_UART1_RX_Int_Handler(void);
+
+/* Internal DMA Callback for receiving DMA faults from common DMA error handler. */
+static void RxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg);
+static void RxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) {
+
+    /* Recover the device handle. */
+    ADI_UART_HANDLE hDevice = (ADI_UART_HANDLE)pCBParam;
+    ADI_UART_BUFF_INFO * pNextBuff = hDevice->pChannelRx->pFillBuffer->pNextBuffer;
+    uint32_t nEvent = 0u;
+
+    /* Save the DMA error. */
+    switch (Event) {
+        case ADI_DMA_EVENT_ERR_BUS:
+            nEvent |= (uint32_t)ADI_UART_HW_ERR_RX_CHAN_DMA_BUS_FAULT;
+            break;
+        case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR:
+            nEvent |= (uint32_t)ADI_UART_HW_ERR_RX_CHAN_DMA_INVALID_DESCR;
+            break;
+        default:
+            nEvent |= (uint32_t)ADI_UART_HW_ERR_RX_CHAN_DMA_UNKNOWN_ERROR;
+            break;
+    }
+
+    if((pNextBuff->pStartAddress != NULL) && (pNextBuff->bDMA == true))
+    {
+        hDevice->nHwError |= nEvent;
+        pNextBuff->bInUse = false;
+        uart_ManageProcessedBuffer(hDevice,hDevice->pChannelRx,ADI_UART_EVENT_RX_BUFFER_PROCESSED);
+
+    }
+    hDevice->nHwError |= nEvent;
+    uart_ManageProcessedBuffer(hDevice,hDevice->pChannelRx,ADI_UART_EVENT_RX_BUFFER_PROCESSED);
+}
+
+static void TxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg);
+static void TxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) {
+
+    /* Recover the device handle. */
+    ADI_UART_HANDLE hDevice = (ADI_UART_HANDLE)pCBParam;
+    ADI_UART_BUFF_INFO * pNextBuff = hDevice->pChannelTx->pFillBuffer->pNextBuffer;
+    uint32_t nEvent = 0u;
+
+    /* Save the DMA error. */
+    switch (Event) {
+        case ADI_DMA_EVENT_ERR_BUS:
+            nEvent |= (uint32_t)ADI_UART_HW_ERR_TX_CHAN_DMA_BUS_FAULT;
+            break;
+        case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR:
+            nEvent |= (uint32_t)ADI_UART_HW_ERR_TX_CHAN_DMA_INVALID_DESCR;
+            break;
+        default:
+            nEvent |= (uint32_t)ADI_UART_HW_ERR_TX_CHAN_DMA_UNKNOWN_ERROR;
+            break;
+    }
+    if((pNextBuff->pStartAddress != NULL) && (pNextBuff->bDMA == true))
+    {
+        hDevice->nHwError |= nEvent;
+        pNextBuff->bInUse = false;
+        uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED);
+
+    }
+
+    hDevice->nHwError |= nEvent;
+    uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED);
+}
+/*! \endcond */
+
+/**********************************************************
+ * General UART APIs
+ **********************************************************/
+
+/*!
+ * @brief       Initialization function for the UART device.
+ * @details     Opens the specified UART device. This function must be called before operating any UART device.
+ *
+ *
+ * @param [in]  nDeviceNum     UART device instance to be opened.
+ * @param [in]  eDirection     Direction of the UART operation. (i.e Rx or Tx)
+ * @param [in]  pMemory        Pointer to a 32 bit aligned buffer the size of #ADI_UART_UNIDIR_MEMORY_SIZE
+ *                             or #ADI_UART_BIDIR_MEMORY_SIZE.
+ * @param [in]  nMemSize       Size of the buffer to which "pMemory" points. This will vary based on
+ *                             direction of operation for this device instance. (i.e Rx and Tx, Rx, Tx)
+ *
+ * @param [out] phDevice       The caller's device handle pointer for storing the initialized device instance data pointer.
+ *
+ * @return      Status
+ *              - #ADI_UART_SUCCESS                     Successfully initialized UART device.
+ *              - #ADI_UART_SEMAPHORE_FAILED            Failed to create semaphore.
+ *              - #ADI_UART_INVALID_DEVICE_NUM      [D] Device instance is invalid.
+ *              - #ADI_UART_INSUFFICIENT_MEMORY     [D] Supplied memory is insufficient for the operation of specified UART device.
+ *              - #ADI_UART_DEVICE_IN_USE           [D] Device is already open.
+ *
+ * @sa  adi_uart_Close()
+ *
+ * @note: Memory supplied by the API will be used by the driver for managing the UART device. This memory can be reused once
+ *        device is closed.
+ *
+ */
+ADI_UART_RESULT adi_uart_Open(
+                              uint32_t            const nDeviceNum,
+                              ADI_UART_DIRECTION  const eDirection,
+                              void                     *pMemory,
+                              uint32_t            const nMemSize,
+                              ADI_UART_HANDLE    *const phDevice
+                             )
+{
+#ifdef ADI_DEBUG
+    /* Check if the given device number is within the range of UART
+     * devices present in the processor. There are two devices present here
+     * so this can be a 0 or 1.
+     */
+    if(nDeviceNum >= ADI_UART_NUM_DEVICES)
+    {
+        return(ADI_UART_INVALID_DEVICE_NUM);
+    }
+
+    /* Verify the device is not already open. */
+    if(uart_device_info[nDeviceNum].hDevice != NULL)
+    {
+        return(ADI_UART_DEVICE_IN_USE);
+    }
+
+    /* Make sure there is enough memory for the device instance to operate in a single direction. */
+    if(eDirection !=  ADI_UART_DIR_BIDIRECTION)
+    {
+        if(nMemSize < (uint32_t)ADI_UART_UNIDIR_MEMORY_SIZE)
+        {
+            return(ADI_UART_INSUFFICIENT_MEMORY);
+        }
+        assert(nMemSize == (sizeof(ADI_UART_DEVICE) + sizeof(ADI_UART_DATA_CHANNEL)));
+    }
+
+    /* Make sure there is enough memory for the device instance to operate in both directions. */
+    else
+    {
+        if(nMemSize < (uint32_t)ADI_UART_BIDIR_MEMORY_SIZE)
+        {
+            return(ADI_UART_INSUFFICIENT_MEMORY);
+        }
+        assert(nMemSize == (sizeof(ADI_UART_DEVICE) + (sizeof(ADI_UART_DATA_CHANNEL)*2u)));
+    }
+#endif /* ADI_DEBUG */
+
+    /* Initialize the device handle to NULL in case of a failure. */
+    *phDevice = NULL;
+
+    /* Link the ADI_UART_HANDLE to the ADI_UART_DEVICE structure. */
+     ADI_UART_HANDLE hDevice = pMemory;
+
+    /* Zero the device handle memory so we do not have to explicitely initialize
+       the structure members to 0.
+    */
+    memset(pMemory, 0, nMemSize);
+
+
+    /* Set the device information. */
+    hDevice->pUartInfo = &uart_device_info[nDeviceNum];
+
+    /* Set the base of the UART register address. We do this to minimize
+       the cycle count when accessing the UART registers.
+    */
+    hDevice->pUARTRegs = uart_device_info[nDeviceNum].pUartRegs;
+
+    /* Store the direction that this device will operate in. */
+    hDevice->eDirection = eDirection;
+
+    /* Increment the device handle with the size of the UART device structure
+       so we can set the channel data next without overwriting
+       the #ADI_UART_DEVICE data.
+    */
+    pMemory = ((uint8_t *)pMemory +(sizeof(ADI_UART_DEVICE)));
+
+    /* Set up the DMA Controller. */
+    adi_dma_Init();
+
+    /* Initialize the TX-channel. */
+    if(ADI_UART_DIR_RECEIVE != eDirection)
+    {
+         hDevice->pChannelTx = (ADI_UART_DATA_CHANNEL *)pMemory;
+
+         /* Initialize the data transfer mode. */
+         hDevice->pChannelTx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE;
+
+         /* Initialize Tx buffer pointers. */
+         hDevice->pChannelTx->pFreeBuffer = &hDevice->pChannelTx->PingPong[0];
+         hDevice->pChannelTx->pActiveBuffer = &hDevice->pChannelTx->PingPong[0];
+         hDevice->pChannelTx->pFillBuffer = &hDevice->pChannelTx->PingPong[0];
+
+
+         /* Create a "semaphore" (varies per OS) used for blocking buffer resource management. */
+         SEM_CREATE(hDevice->pChannelTx, "UART_TX_SEM", ADI_UART_SEMAPHORE_FAILED);
+
+         /* Set submit buffer function pointer. */
+         hDevice->pChannelTx->pfSubmitBuffer = &uart_submittxbuffer;
+
+         hDevice->pChannelTx->PingPong[0].pNextBuffer  = &hDevice->pChannelTx->PingPong[1];
+         hDevice->pChannelTx->PingPong[1].pNextBuffer  = &hDevice->pChannelTx->PingPong[0];
+
+         /*Register DMA Callback. */
+         if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pUartInfo->dmaTxChannelNum, TxDmaErrorCallback, (void*)hDevice))
+         {
+              adi_uart_Close(hDevice);
+              return  ADI_UART_ERR_DMA_REGISTER;
+         }
+
+         /* Increment the device handle the size of #ADI_UART_DATA_CHANNEL
+            structure in case there is another channel to configure.
+         */
+         pMemory =  ((uint8_t *)pMemory + sizeof(ADI_UART_DATA_CHANNEL));
+    }
+    /* Initialize the RX-channel. */
+    if(ADI_UART_DIR_TRANSMIT != eDirection)
+    {
+        hDevice->pChannelRx = (ADI_UART_DATA_CHANNEL *)pMemory;
+
+        /* Initialize the data transfer mode. */
+        hDevice->pChannelRx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE;
+
+        /* Initialize Rx buffer pointers. */
+        hDevice->pChannelRx->pFreeBuffer = &hDevice->pChannelRx->PingPong[0];
+        hDevice->pChannelRx->pActiveBuffer = &hDevice->pChannelRx->PingPong[0];
+        hDevice->pChannelRx->pFillBuffer = &hDevice->pChannelRx->PingPong[0];
+
+        /* Create a "semaphore" (varies per OS) used for blocking buffer resource management. */
+        SEM_CREATE(hDevice->pChannelRx, "UART_RX_SEM", ADI_UART_SEMAPHORE_FAILED);
+
+        /* Set submit buffer function pointer. */
+        hDevice->pChannelRx->pfSubmitBuffer = &uart_submitrxbuffer;
+
+        hDevice->pChannelRx->PingPong[0].pNextBuffer  = &hDevice->pChannelRx->PingPong[1];
+        hDevice->pChannelRx->PingPong[1].pNextBuffer  = &hDevice->pChannelRx->PingPong[0];
+
+         /*Register DMA Callback. */
+         if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pUartInfo->dmaRxChannelNum, RxDmaErrorCallback, (void*)hDevice))
+         {
+              adi_uart_Close(hDevice);
+              return  ADI_UART_ERR_DMA_REGISTER;
+         }
+    }
+
+    /* Initialize the device with the static config values.*/
+    uart_init(hDevice, nDeviceNum);
+
+    /* Write the device data pointer to the application's handle. */
+    *phDevice = hDevice;
+
+    /* Store the device handle. */
+    uart_device_info[nDeviceNum].hDevice = hDevice;
+
+
+    /* Enable UART Interrupt. */
+    NVIC_ClearPendingIRQ(hDevice->pUartInfo->eIRQn);
+    NVIC_EnableIRQ(hDevice->pUartInfo->eIRQn);
+
+    /* Enable the interrupt for the DMA. */
+    NVIC_EnableIRQ(hDevice->pUartInfo->eDMATx);
+    NVIC_EnableIRQ(hDevice->pUartInfo->eDMARx);
+
+    /* Return SUCCESS */
+    return(ADI_UART_SUCCESS);
+}
+
+/*!
+ * @brief       Uninitialize the memory for the specified UART instance.
+ *
+ * @param [in]  hDevice   UART device handle whose operation is to be closed. This handle was obtained when the UART
+ *                        device instance was opened successfully.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS               Successfully closed the UART device instance.
+ *    - #ADI_UART_SEMAPHORE_FAILED      Failed to delete the semaphore.
+ *    - #ADI_UART_INVALID_HANDLE    [D] Invalid UART device handle.
+ *    - #ADI_UART_DEVICE_IN_USE     [D] Specified UART device is in the process of a transaction or autobaud has not completed.
+ *
+ * @details     Closes the operation of specified UART device. Device needs to be opened again for any further use.
+ *
+ * @sa  adi_uart_Open()
+ *
+ * @note: It is the user's responsibility to free/reuse the memory supplied during the opening of the device.
+ */
+ADI_UART_RESULT adi_uart_Close(
+                               ADI_UART_HANDLE const hDevice
+                              )
+{
+#ifdef ADI_DEBUG
+    /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* Make sure there are no active buffers on any active channel, autobaud is not in progress and the
+       Tx shift register is completely empty. This can be an issue if you submitted a nonblocking transmit
+       because you will receive interrupt before the hardware has fully finished the transaction. The start
+       address of the active buffer will remain in use until the buffer has been completely processed.
+       Therefore if the start address is NULL it means it has not been submitted for a transaction.
+    */
+    if(((hDevice->pUARTRegs->LSR & BITM_UART_LSR_TEMT) != BITM_UART_LSR_TEMT)                                        ||
+       ((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pFillBuffer->pStartAddress != NULL)) ||
+       ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pFillBuffer->pStartAddress != NULL)) ||
+       (hDevice->bAutobaudInProgress == true))
+    {
+        return(ADI_UART_DEVICE_IN_USE);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Disable UART status interrupts. */
+    hDevice->pUARTRegs->IEN = 0x00U;
+
+    /* Disable DMA UART interrupts. */
+    NVIC_DisableIRQ(hDevice->pUartInfo->eDMARx);
+    NVIC_DisableIRQ(hDevice->pUartInfo->eDMATx);
+
+    /* Disable UART event interrupt. */
+    NVIC_DisableIRQ(hDevice->pUartInfo->eIRQn);
+
+    /* Delete Tx-Channel semaphore. */
+    if(hDevice->eDirection != ADI_UART_DIR_RECEIVE)
+    {
+        SEM_DELETE(hDevice->pChannelTx, ADI_UART_SEMAPHORE_FAILED);
+    }
+
+    /* Delete Rx-Channel semaphore. */
+    if(hDevice->eDirection != ADI_UART_DIR_TRANSMIT)
+    {
+        SEM_DELETE(hDevice->pChannelRx, ADI_UART_SEMAPHORE_FAILED);
+    }
+
+     /* Free up the device memory. */
+    hDevice->pUartInfo->hDevice = NULL;
+
+    return(ADI_UART_SUCCESS);
+}
+
+/*!
+ * @brief       Submit a "filled" buffer for transmitting data in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING.
+ *              This function sets up the apropriate interrupts associated with the transaction and marks
+ *              the buffer as submitted.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  pBuffer    Pointer to data supplied by the API that is to be transmitted.
+ * @param [in]  nBufSize   Size of the buffer to be transmitted(in bytes). Must be smaller than 1024 bytes for DMA transfers.
+ * @param [in]  bDMA       Submit the buffer using the DMA flag.
+
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                        Successfully submitted the buffer for transmission.
+ *    - #ADI_UART_FAILED                     [D] Generic failure. In this case the size of the data buffer we are trying
+ *                                               to submit is NULL.
+ *    - #ADI_UART_INVALID_DATA_TRANSFER_MODE [D] Device is operating in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. This
+ *                                               operation is only allowed in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING.
+ *    - #ADI_UART_INVALID_HANDLE             [D] Invalid UART device handle.
+ *    - #ADI_UART_OPERATION_NOT_ALLOWED      [D] Device direction is set up as #ADI_UART_DIR_RECEIVE, so we can not complete
+ *                                               a transmit operation. The required directions are #ADI_UART_DIR_TRANSMIT or
+ *                                               #ADI_UART_DIR_BIDIRECTION.
+ *    - #ADI_UART_INVALID_POINTER            [D] Pointer to the buffer being submitted is NULL.
+ *    - #ADI_UART_DEVICE_IN_USE              [D] Autobaud in progress.
+ *    - #ADI_UART_INVALID_DATA_SIZE          [D] DMA transfers must be smaller than 1025 bytes.
+ *
+ * @sa  adi_uart_IsTxBufferAvailable()
+ * @sa  adi_uart_GetTxBuffer()
+ * @sa  adi_uart_SubmitRxBuffer()
+ *
+ * @note: Only one transfer mode (DMA vs. PIO) can be used at once. For example, if you submit a buffer in PIO mode
+ *        and then right away another using the DMA, this transaction will be denied.
+ *
+ */
+ADI_UART_RESULT adi_uart_SubmitTxBuffer(
+                                         ADI_UART_HANDLE const hDevice,
+                                         void           *const pBuffer,
+                                         uint32_t        const nBufSize,
+                                         bool            const bDMA
+                                       )
+{
+
+#ifdef ADI_DEBUG
+    /* Validate the device handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* Validate the pointer to the buffer memory. */
+    if(pBuffer == NULL)
+    {
+        return(ADI_UART_INVALID_POINTER);
+    }
+
+    /* Validate the buffer size. */
+    if(nBufSize == 0U)
+    {
+        return(ADI_UART_FAILED);
+    }
+
+    /* Autobaud in progress. */
+    if(hDevice->bAutobaudInProgress == true)
+    {
+        return(ADI_UART_DEVICE_IN_USE);
+    }
+
+    /* Make sure we are transmitting. */
+    if(ADI_UART_DIR_RECEIVE == hDevice->eDirection)
+    {
+        return(ADI_UART_OPERATION_NOT_ALLOWED);
+    }
+
+    /* Check the data transfer mode (only allowed in nonblocking mode). */
+    if(hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING)
+    {
+        return(ADI_UART_INVALID_DATA_TRANSFER_MODE);
+    }
+
+    /* Check that there is a free buffer to use for this transmit operation. pFreeBuffer
+       is the next buffer available, so if it is in use we can make the assumption that
+       there are no buffers available. The start address is set to NULL once the buffer
+       has finished being processed in "adi_uart_GetBuffer()" or "adi_uart_PendForBuffer()".
+    */
+    if(hDevice->pChannelTx->pFreeBuffer->pStartAddress != NULL)
+    {
+        return(ADI_UART_OPERATION_NOT_ALLOWED);
+    }
+
+    /* Make sure the DMA transfer size is not too large. */
+    if((bDMA == true) && (nBufSize > DMA_TRANSFER_LIMIT))
+    {
+        return(ADI_UART_INVALID_DATA_SIZE);
+    }
+
+#endif /* ADI_DEBUG */
+
+     /* Set the start address of the data buffer we are going to submit. */
+     hDevice->pChannelTx->pFreeBuffer->pStartAddress =   pBuffer;
+
+     /* Set the buffer size to the size of the data buffer passed down from the API. */
+     hDevice->pChannelTx->pFreeBuffer->nCount        =   nBufSize;
+
+     /* Initialize the buffer index to zero because we will start shifting out
+        the Tx data from the first position of the buffer.
+     */
+     hDevice->pChannelTx->pFreeBuffer->nIndex        =   0U;
+
+     /* Mark the buffer as in use so no other transactions can use it until this one is complete. */
+     hDevice->pChannelTx->pFreeBuffer->bInUse        =   true;
+
+     /* Mark the DMA as in use. */
+     hDevice->pChannelTx->pFreeBuffer->bDMA          =   bDMA;
+
+     /* Now that this "pFreeBuffer" is no longer free for use, update the
+        "pFreeBuffer" to the other PingPong buffer. Because there are only two
+        buffers in the PingPong structure, this will be the opposite of the one
+        we just submitted. "pFreeBuffer" will only be updated during the process of
+        submitting a buffer or a read/write operation.
+     */
+      hDevice->pChannelTx->pFreeBuffer = hDevice->pChannelTx->pFreeBuffer->pNextBuffer;
+
+     /* Set the data transfer mode in case it was #ADI_UART_DATA_TRANSFER_MODE_NONE.
+        This will be set back to #ADI_UART_DATA_TRANSFER_MODE_NONE once this
+        transaction is complete. Then, if a buffer is not currently active, set up the
+        interrupts for this transaction. Otherwise if a buffer is currently active,
+        this will be taken care of in the ISR.
+     */
+     if (hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONE)
+     {
+         hDevice->pChannelTx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING;
+         hDevice->pChannelTx->pfSubmitBuffer(hDevice, hDevice->pChannelTx->pFillBuffer);
+     }
+
+     return(ADI_UART_SUCCESS);
+  }
+
+/*!  \cond PRIVATE */
+
+/*
+ * @brief      This is an internal helper function for adi_uart_SubmitTxBuffer(). It sets up the Tx channel DMA
+               or device interrupts for the Tx channel to transmit data.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  pBuffer    Pointer to buffer from where data will be transmitted.
+ * @param [in]  nBufSize   Size of the buffer containing the data to be transmitted(in bytes).
+ * @param [in]  bDMA       Submit the buffer using the DMA.
+*/
+static void uart_submittxbuffer(
+                                 ADI_UART_CONST_HANDLE  const hDevice,
+                                 ADI_UART_BUFF_INFO    *const pBuffer
+                               )
+{
+  /* If this transmission is using DMA... */
+  if (pBuffer->bDMA)
+  {
+      /* Enable clear source address decrement for TX channel DMA. */
+      pADI_DMA0->SRCADDR_CLR = 1u << (uint32_t)hDevice->pUartInfo->dmaTxChannelNum;
+
+      /* Enable Tx channel DMA. */
+      pADI_DMA0->EN_SET = 1u << hDevice->pUartInfo->dmaTxChannelNum;
+
+      /* Enable UART peripheral to generate DMA requests. */
+      pADI_DMA0->RMSK_CLR = 1u << hDevice->pUartInfo->dmaTxChannelNum;
+
+      /* Set the primary control data structure as the current DMA descriptor. */
+      pADI_DMA0->ALT_CLR = 1u << hDevice->pUartInfo->dmaTxChannelNum;
+
+      /* Fill in the DMA RAM descriptors */
+      pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMASRCEND =   ((uint32_t)pBuffer->pStartAddress + (uint32_t)(pBuffer->nCount - 1u));
+
+      pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMADSTEND =   (uint32_t)&hDevice->pUARTRegs->TX;
+
+      pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMACDC    =   ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC)      |
+                                                                     ((uint32_t)ADI_DMA_INCR_1_BYTE << DMA_BITP_CTL_SRC_INC)    |
+                                                                     (ADI_DMA_WIDTH_1_BYTE << DMA_BITP_CTL_SRC_SIZE)            |
+                                                                     (0u << DMA_BITP_CTL_R_POWER)                               |
+                                                                     ((pBuffer->nCount - 1u) << DMA_BITP_CTL_N_MINUS_1)         |
+                                                                     (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
+      /* Enable UART DMA request interrupt for the Tx channel. */
+      hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_EDMAT);
+  }
+  else
+  /* If this transmission is using UART interrupts.. */
+  {
+      /* Enable buffer empty interrupts.  */
+      hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ETBEI);
+  }
+}
+
+/*! \endcond */
+
+/*!
+ * @brief       Submit an empty buffer for receiving the data in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING.
+ *              This will set up the Rx channel for notification on incoming data using either the DMA
+ *              or UART interrupts, as well as mark the buffer as submitted.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  pBuffer    Pointer to buffer from that will be filled by the driver when data has been received.
+ * @param [in]  nBufSize   Size of the buffer(in bytes). Must be smaller than 1024 bytes for DMA transfers.
+ * @param [in]  bDMA       Submit the buffer using DMA flag.
+
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                        Successfully submitted the buffer for receiving data.
+ *    - #ADI_UART_FAILED                     [D] Generic failure. In this case the size of the data buffer we are trying
+ *                                               to submit is NULL.
+ *    - #ADI_UART_INVALID_DATA_TRANSFER_MODE [D] Device is operating in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. This
+ *                                               operation is only allowed in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING.
+ *    - #ADI_UART_INVALID_HANDLE             [D] Invalid UART device handle.
+ *    - #ADI_UART_OPERATION_NOT_ALLOWED      [D] Device direction is set up as #ADI_UART_DIR_TRANSMIT, so we can not complete
+ *                                               a receive operation. The required directions are #ADI_UART_DIR_RECEIVE or
+ *                                               #ADI_UART_DIR_BIDIRECTION.
+ *    - #ADI_UART_INVALID_POINTER            [D] Pointer to the buffer being submitted is NULL.
+ *    - #ADI_UART_DEVICE_IN_USE              [D] Autobaud in progress.
+ *    - #ADI_UART_INVALID_DATA_SIZE          [D] DMA transfers must be smaller than 1025 bytes.
+ *
+ * @sa  adi_uart_IsRxBufferAvailable()
+ * @sa  adi_uart_GetRxBuffer()
+ * @sa  adi_uart_SubmitTxBuffer()
+ *
+ * @note: Only one transfer mode (DMA vs. PIO) can be used at once. For example, if you submit a buffer in PIO mode
+ *        and then right away another using the DMA, this transaction will be denied.
+*/
+ADI_UART_RESULT adi_uart_SubmitRxBuffer(
+                                         ADI_UART_HANDLE const hDevice,
+                                         void           *const pBuffer,
+                                         uint32_t        const nBufSize,
+                                         bool            const bDMA
+                                       )
+{
+
+#ifdef ADI_DEBUG
+    /* Validate the device handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* Validate the pointer to the buffer memory. */
+    if(pBuffer == NULL)
+    {
+        return(ADI_UART_INVALID_POINTER);
+    }
+
+    /* Validate the buffer size. */
+    if(nBufSize == 0U )
+    {
+        return(ADI_UART_FAILED);
+    }
+
+    /* Autobaud in progress. */
+    if(hDevice->bAutobaudInProgress == true)
+    {
+        return(ADI_UART_DEVICE_IN_USE);
+    }
+
+    /* Make sure the UART device is configured to operate in the receive direction. */
+    if(ADI_UART_DIR_TRANSMIT == hDevice->eDirection)
+    {
+        return(ADI_UART_OPERATION_NOT_ALLOWED);
+    }
+
+    /* Check for the data transfer mode(only allowed in nonblocking mode). */
+    if(hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING)
+    {
+        return(ADI_UART_INVALID_DATA_TRANSFER_MODE);
+    }
+
+    /* Check that there is a free buffer to use for this operation. pFreeBuffer
+       is the next buffer available, so if it is in use we can make the assumption that
+       there are no buffers available. If the start address is not set to NULL, then we
+       can conclude the buffer has not finished being processed because this gets set in
+       adi_uart_pend_for_buffer() and adi_uart_get_buffer().
+    */
+    if(hDevice->pChannelRx->pFreeBuffer->pStartAddress != NULL)
+    {
+        return(ADI_UART_OPERATION_NOT_ALLOWED);
+    }
+
+    /* Make sure the DMA transfer size is not too large. */
+    if((bDMA == true) && (nBufSize > DMA_TRANSFER_LIMIT))
+    {
+        return(ADI_UART_INVALID_DATA_SIZE);
+    }
+
+#endif /* ADI_DEBUG */
+
+    /* Set the start address of the buffer you are going to submit. */
+     hDevice->pChannelRx->pFreeBuffer->pStartAddress =   pBuffer;
+
+     /* Set the size of the buffer. */
+     hDevice->pChannelRx->pFreeBuffer->nCount        =   nBufSize;
+
+     /* Initialize the buffer index to 0, because as we receive data it will be put into
+        the buffer starting at the first position.
+     */
+     hDevice->pChannelRx->pFreeBuffer->nIndex        =   0U;
+
+     /* Mark the buffer as in use. */
+     hDevice->pChannelRx->pFreeBuffer->bInUse        =   true;
+
+     /* Mark the DMA as in use. */
+     hDevice->pChannelRx->pFreeBuffer->bDMA          =   bDMA;
+
+     /* Now that this "pFreeBuffer" is no longer free for use, update the
+        "pFreeBuffer" to the other PingPong buffer. Because there are only two
+        buffers in the PingPong structure, this will be the opposite of the one
+        we just submitted. "pFreeBuffer" will only be updated during the process of
+        submitting a buffer or a read/write operation.
+     */
+      hDevice->pChannelRx->pFreeBuffer = hDevice->pChannelRx->pFreeBuffer->pNextBuffer;
+
+
+    /* Set the data transfer mode in case it was #ADI_UART_DATA_TRANSFER_MODE_NONE.
+       This will be set back to #ADI_UART_DATA_TRANSFER_MODE_NONE once this
+       transaction is complete. Then, if a buffer is not currently active, set up the
+       interrupts for this transaction. Otherwise if a buffer is currently active,
+       this will be taken care of in the ISR.
+    */
+     if (hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONE)
+     {
+         hDevice->pChannelRx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING;
+         hDevice->pChannelRx->pfSubmitBuffer(hDevice, hDevice->pChannelRx->pFillBuffer);
+     }
+
+     return(ADI_UART_SUCCESS);
+}
+
+/*! \cond PRIVATE */
+
+/*
+ * @brief                  This is an internal helper function for adi_uart_SubmitRxBuffer(). It sets up the DMA
+ *                         or device receive interrupts for the Rx channel to receive data.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  pBuffer    Pointer to the empty receive buffer.
+ * @param [in]  nBufSize   Size of the receive buffer(in bytes).
+ * @param [in]  bDMA       Submit the buffer using the DMA.
+*/
+static void uart_submitrxbuffer(
+                                 ADI_UART_CONST_HANDLE   const hDevice,
+                                 ADI_UART_BUFF_INFO     *const pBuffer
+                               )
+{
+
+
+    /* If this transaction is using the DMA.. */
+    if (pBuffer->bDMA)
+    {
+        /* Enable source address decrement for RX DMA channel. */
+        pADI_DMA0->DSTADDR_CLR = 1u << (uint32_t)hDevice->pUartInfo->dmaRxChannelNum;
+
+        /* Enable Rx DMA channel. */
+        pADI_DMA0->EN_SET = 1u << hDevice->pUartInfo->dmaRxChannelNum;
+
+        /* Enable UART peripheral to generate DMA requests. */
+        pADI_DMA0->RMSK_CLR = 1u << hDevice->pUartInfo->dmaRxChannelNum;
+
+        /* Set the primary data structure as the current DMA descriptor. */
+        pADI_DMA0->ALT_CLR = 1u << hDevice->pUartInfo->dmaRxChannelNum;
+
+        /* Fill in the DMA RAM descriptors. */
+        pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMASRCEND =   (uint32_t)&hDevice->pUARTRegs->RX;
+
+        pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMADSTEND =   ((uint32_t)pBuffer->pStartAddress + (uint32_t)(pBuffer->nCount - 1u));
+
+        pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMACDC    =   (uint32_t)(ADI_DMA_INCR_1_BYTE << DMA_BITP_CTL_DST_INC)            |
+                                                                       (uint32_t)(ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC)              |
+                                                                       (ADI_DMA_WIDTH_1_BYTE << DMA_BITP_CTL_SRC_SIZE)                    |
+                                                                       (0u << DMA_BITP_CTL_R_POWER)                                       |
+                                                                       ((pBuffer->nCount - 1u) << DMA_BITP_CTL_N_MINUS_1)                 |
+                                                                       (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL);
+        /* Enable UART receive DMA requests. */
+        hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_EDMAR);
+    }
+    /* If this transaction is using UART interrupts.. */
+    else
+    {
+        /* Enable buffer full interrupt. */
+        hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ERBFI);
+    }
+}
+
+/*! \endcond */
+
+/*!
+ * @brief       Transfer buffer ownership from the device back to the API if the data
+ *              transmit has completed. Otherwise it will block until completion.
+ *              This allows a nonblocking call to become blocking.
+ *              This function is only called in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  ppBuffer   Contains the address of the buffer passed down from the API
+ *                         for transmitting data.
+ * @param [out] pHwError   Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status.
+ *                         If there is no hardware event, this will be 0.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                       Successfully returned buffer to the API.
+ *    - #ADI_UART_HW_ERROR_DETECTED             Hardware error(s) detected. "pHwError" can be checked for the specific error code(s).
+ *    - #ADI_UART_OPERATION_NOT_ALLOWED     [D] Call to this function is not allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING.
+ *    - #ADI_UART_INVALID_HANDLE            [D] Invalid UART device handle.
+ *    - #ADI_UART_BUFFER_NOT_SUBMITTED      [D] The buffer has not been submitted to the driver.
+ *
+ * @sa  adi_uart_IsTxBufferAvailable()
+ * @sa  adi_uart_SubmitTxBuffer()
+ *
+ * @note: If the transaction has already completed, this will return immediately rather than block.
+ */
+ADI_UART_RESULT adi_uart_GetTxBuffer(
+                                      ADI_UART_HANDLE const   hDevice,
+                                      void          **const   ppBuffer,
+                                      uint32_t               *pHwError
+                                     )
+
+{
+
+#ifdef ADI_DEBUG
+    /* Validate the device handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* Validate that this buffer has actually been submitted. */
+    if(hDevice->pChannelTx->pActiveBuffer->pStartAddress == NULL)
+    {
+        return(ADI_UART_BUFFER_NOT_SUBMITTED);
+    }
+
+    /* This function is allowed to be called when the channel is operating in NONBLOCKING mode. */
+    if(hDevice->pChannelTx->eDataTranferMode ==  ADI_UART_DATA_TRANSFER_MODE_BLOCKING)
+    {
+        return(ADI_UART_OPERATION_NOT_ALLOWED);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Blocking call to get the submitted buffer */
+    return(uart_getbuffer(hDevice, hDevice->pChannelTx, ppBuffer, pHwError));
+}
+
+
+
+/*!
+ * @brief       Transfer buffer ownership from the device back to the API if the data
+ *              receive has completed. Otherwise it will block until completion.
+ *              This allows a nonblocking call to become blocking.
+ *              This function is only called in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  ppBuffer   Contains the address of the buffer passed down from the API
+ *                         for receiving data.
+ * @param [out] pHwError   Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status.
+ *                         If there is no hardware event, this will be 0.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                       Successfully returned buffer to the API.
+ *    - #ADI_UART_HW_ERROR_DETECTED             Hardware error(s) detected. "pHwError" can be checked for the specific error code(s).
+ *    - #ADI_UART_OPERATION_NOT_ALLOWED     [D] Call to this function is not allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING.
+ *    - #ADI_UART_INVALID_HANDLE            [D] Invalid UART device handle.
+ *    - #ADI_UART_BUFFER_NOT_SUBMITTED      [D] The buffer has not been submitted to the driver.
+ *
+ * @sa  adi_uart_IsRxBufferAvailable()
+ * @sa  adi_uart_SubmitRxBuffer()
+ *
+ * @note: If the transaction has already completed, this will return immediately rather than block.
+*/
+ADI_UART_RESULT adi_uart_GetRxBuffer(
+                                      ADI_UART_HANDLE  const   hDevice,
+                                      void           **const   ppBuffer,
+                                      uint32_t                *pHwError
+                                     )
+
+{
+
+#ifdef ADI_DEBUG
+    /* Validate the device handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* Validate that this buffer has actually been submitted. */
+    if(hDevice->pChannelRx->pActiveBuffer->pStartAddress == NULL)
+    {
+        return(ADI_UART_BUFFER_NOT_SUBMITTED);
+    }
+
+     /* This function is only allowed to be called when the channel is operating in NONBLOCKING mode. */
+    if(hDevice->pChannelRx->eDataTranferMode ==  ADI_UART_DATA_TRANSFER_MODE_BLOCKING)
+    {
+        return(ADI_UART_OPERATION_NOT_ALLOWED);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Blocking call to get the full Rx Buffer */
+    return(uart_getbuffer(hDevice, hDevice->pChannelRx, ppBuffer, pHwError));
+}
+
+/*! \cond PRIVATE */
+
+/*
+ * @brief       This is an internal helper function for adi_uart_GetRxBuffer() and adi_uart_GetTxBuffer().
+ *              It blocks until until the completion of the data transaction.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  pChannel   Pointer to UART channel data structure.
+ * @param [out] ppBuffer   Contains the address of the buffer passed down from the API.
+ * @param [out] pHwError   Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status.
+ *                         If there is no hardware event, this will be 0.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                Successfully got buffer.
+ *    - #ADI_UART_HW_ERROR_DETECTED      Hardware error(s) detected. "pHwError" can be checked for the specific error code(s).
+ *
+*/
+static ADI_UART_RESULT uart_getbuffer(
+                                       ADI_UART_HANDLE        hDevice,
+                                       ADI_UART_DATA_CHANNEL *pChannel,
+                                       void                 **ppBuffer,
+                                       uint32_t              *pHwError
+                                      )
+{
+    /* Set ppBuffer to NULL in case there is an error. */
+    *ppBuffer = NULL;
+
+    /* Wait until the peripheral has finished processing the buffer. */
+    SEM_PEND(pChannel,ADI_UART_FAILED);
+
+    /* Save the address of the buffer that has just been processed, so it can be
+       returned back to the API.
+    */
+    *ppBuffer = pChannel->pActiveBuffer->pStartAddress;
+
+    /* Reinitialize the start address to NULL so this buffer can be used for a new transaction. */
+    pChannel->pActiveBuffer->pStartAddress = NULL;
+
+    /* Now that the desired data has either been transmitted or received, this buffer is no longer
+       in use. We can update "pActiveBuffer" to point to the next buffer that will become or is already
+       active.
+    */
+     pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer;
+
+     /* Set the data transfer mode to none so that the next transfer can be either in blocking or in nonblocking mode.
+        This will only be done if there are no other active buffers in flight to avoid disrupting an active transfer.
+    */
+     if(pChannel->pActiveBuffer->pStartAddress == NULL)
+     {
+        pChannel->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE;
+     }
+
+    /* If there are hardware errors and no callback, then return failure. */
+    if(hDevice->nHwError != 0u)
+    {
+        /* Save the hardware error detected. This will be passed back to the API. */
+        *pHwError = hDevice->nHwError;
+
+        /* Clear any hardware errors detected. */
+        hDevice->nHwError = 0u;
+
+        return(ADI_UART_HW_ERROR_DETECTED);
+    }
+    else
+    {
+        return(ADI_UART_SUCCESS);
+    }
+}
+
+/*! \endcond */
+
+
+/*!
+ * @brief       Submit the buffer for transmitting the data in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING.
+ *              Call to this function will not return until the entire buffer is transmitted.
+ *              Returns error if this function is called when device is operating in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING.
+ *              i.e Function "adi_uart_SubmitTxBuffer()" is called and the transfer is not yet complete.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  pBuffer    Pointer to data supplied by the API that is to be transmitted.
+ * @param [in]  nBufSize   Size of the buffer(in bytes). Must be smaller than 1024 bytes for DMA transfers.
+ * @param [in]  bDMA       Submit the buffer using the DMA flag.
+ * @param [out] pHwError   Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status.
+ *                         If there is no hardware event, this will be 0.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                             Successfully transmitted the data from the submitted buffer.
+ *    - #ADI_UART_HW_ERROR_DETECTED                   Hardware error(s) detected. "pHwError" can be checked for the specific error code(s).
+ *    - #ADI_UART_FAILED                          [D] Generic failure. In this case the size of the data buffer we are trying
+ *                                                    to submit is NULL.
+ *    - #ADI_UART_INVALID_DATA_TRANSFER_MODE      [D] Device is operating in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. This
+ *                                                    operation is only allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING.
+ *    - #ADI_UART_OPERATION_NOT_ALLOWED           [D] Device direction is set up as #ADI_UART_DIR_RECEIVE, so we can not complete
+ *                                                    a transmit operation. The required directions are #ADI_UART_DIR_TRANSMIT or
+ *                                                    #ADI_UART_DIR_BIDIRECTION.
+ *    - #ADI_UART_INVALID_HANDLE                  [D] Invalid UART device handle.
+ *    - #ADI_UART_INVALID_POINTER                 [D] The pointer to the buffer being submitted is a NULL.
+ *    - #ADI_UART_DEVICE_IN_USE                   [D] Autobaud in progress.
+ *    - #ADI_UART_INVALID_DATA_SIZE               [D] DMA transfers must be smaller than 1025 bytes.
+ *
+ * @sa  adi_uart_Read()
+ * @sa  adi_uart_SubmitTxBuffer()
+ *
+ * @note: This function is a blocking function which means that the function returns only after the completion of
+ *        buffer transmission.
+*/
+ADI_UART_RESULT adi_uart_Write(
+                               ADI_UART_HANDLE const hDevice,
+                               void           *const pBuffer,
+                               uint32_t        const nBufSize,
+                               bool            const bDMA,
+                               uint32_t             *pHwError
+                              )
+{
+
+#ifdef ADI_DEBUG
+        /* Validate the given handle. */
+        if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+        {
+            return(ADI_UART_INVALID_HANDLE);
+        }
+
+        /* Validate the pointer to the buffer memory. */
+        if(pBuffer == NULL)
+        {
+            return(ADI_UART_INVALID_POINTER);
+        }
+
+        /* Validate the buffer size. */
+        if(nBufSize == 0U )
+        {
+            return(ADI_UART_FAILED);
+        }
+
+        /* Autobaud in progress. */
+        if(hDevice->bAutobaudInProgress == true)
+        {
+            return(ADI_UART_DEVICE_IN_USE);
+        }
+
+        /* Make sure we are transmitting. */
+        if(ADI_UART_DIR_RECEIVE == hDevice->eDirection)
+        {
+            return(ADI_UART_OPERATION_NOT_ALLOWED);
+        }
+
+        /* Check for the data transfer mode (only allowed in blocking mode). */
+        if(hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING)
+        {
+            return(ADI_UART_INVALID_DATA_TRANSFER_MODE);
+        }
+
+        /* Check that there is a free buffer to use for this transmit operation. "pFreeBuffer"
+          is the next buffer available, so if it is in use we can make the assumption that
+          there are no buffers available. The start address is set to NULL once the buffer
+          has been processed.
+        */
+        if(hDevice->pChannelTx->pFreeBuffer->pStartAddress != NULL)
+        {
+            return(ADI_UART_OPERATION_NOT_ALLOWED);
+        }
+
+        /* Make sure the DMA transfer size is not too large. */
+        if((bDMA == true) && (nBufSize > DMA_TRANSFER_LIMIT))
+        {
+            return(ADI_UART_INVALID_DATA_SIZE);
+        }
+
+#endif /* ADI_DEBUG */
+
+        /* Set the data transfer mode in case it was #ADI_UART_DATA_TRANSFER_MODE_NONE. */
+        hDevice->pChannelTx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_BLOCKING;
+
+        /* Set the start address of the data buffer we are going to submit. */
+        hDevice->pChannelTx->pFreeBuffer->pStartAddress  =   pBuffer;
+
+        /* Set the buffer size to the size of the data buffer passed down from the API. */
+        hDevice->pChannelTx->pFreeBuffer->nCount         =   nBufSize;
+
+        /* Initialize the buffer index to zero because we will start shifting out
+           the Tx data from the first position of the buffer.
+        */
+        hDevice->pChannelTx->pFreeBuffer->nIndex         =   0U;
+
+        /* Mark the buffer as in use so no other transactions can use it until this one is complete. */
+        hDevice->pChannelTx->pFreeBuffer->bInUse         =   true;
+
+        /* Mark the DMA as in use. */
+        hDevice->pChannelTx->pFreeBuffer->bDMA           =   bDMA;
+
+        /* Now that this "pFreeBuffer" is no longer free for use, update the
+           "pFreeBuffer" to the other PingPong buffer. Because there are only two
+           buffers in the PingPong structure, this will be the opposite of the one
+           we just submitted. "pFreeBuffer" will only be updated during the process of
+           submitting a buffer or a read/write operation.
+        */
+        hDevice->pChannelTx->pFreeBuffer = hDevice->pChannelTx->pFreeBuffer->pNextBuffer;
+
+        hDevice->pChannelTx->pfSubmitBuffer(hDevice, hDevice->pChannelTx->pFillBuffer);
+
+        /* Block for the active buffer to complete. */
+        return(uart_PendForBuffer(hDevice, hDevice->pChannelTx, pHwError));
+}
+
+/*!
+ * @brief       Submit the buffer for reading the data in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. Call to this function will not
+ *              return until the entire buffer is filled up. Returns error if this function is called when
+ *              device is operating in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. i.e The function "adi_uart_SubmitRxBuffer()" is called
+ *              when the transfer is not yet complete.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  pBuffer    Pointer to buffer from that will be filled by the driver when data has been received.
+ * @param [in]  nBufSize   Size of the buffer(in bytes). Must be smaller than 1024 bytes for DMA transfers.
+ * @param [in]  bDMA       Submit the buffer using DMA flag.
+ * @param [out] pHwError   Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status.
+ *                         If there is no hardware event, this will be 0.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                        Successfully submitted the buffer for receiving data.
+ *    - #ADI_UART_HW_ERROR_DETECTED              Hardware error(s) detected. "pHwError" can be checked for the specific error code(s).
+ *    - #ADI_UART_FAILED                     [D] Generic failure. In this case the size of the data buffer we are trying
+ *                                               to submit is NULL.
+ *    - #ADI_UART_INVALID_DATA_TRANSFER_MODE [D] Device is operating in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. This
+ *                                               operation is only allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING.
+ *    - #ADI_UART_INVALID_HANDLE             [D] Invalid UART device handle.
+ *    - #ADI_UART_OPERATION_NOT_ALLOWED      [D] Device direction is set up as #ADI_UART_DIR_TRANSMIT, so we can not complete
+ *                                               a receive operation. The required directions are #ADI_UART_DIR_RECEIVE or
+ *                                               #ADI_UART_DIR_BIDIRECTION.
+ *    - #ADI_UART_INVALID_POINTER            [D] Pointer to the buffer being submitted is NULL.
+ *    - #ADI_UART_DEVICE_IN_USE              [D] Autobaud in progress.
+ *    - #ADI_UART_INVALID_DATA_SIZE          [D] DMA transfers must be smaller than 1025 bytes.
+ *
+ * @sa  adi_uart_Write()
+ * @sa  adi_uart_SubmitTxBuffer()
+ *
+ * @note: This function is a blocking function which means that the function returns only after the completion of
+ *        data receive.
+*/
+ADI_UART_RESULT adi_uart_Read(
+                              ADI_UART_HANDLE const hDevice,
+                              void           *const pBuffer,
+                              uint32_t        const nBufSize,
+                              bool            const bDMA,
+                              uint32_t             *pHwError
+                             )
+{
+
+#ifdef ADI_DEBUG
+     /* Validate the given handle. */
+     if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+     {
+         return(ADI_UART_INVALID_HANDLE);
+     }
+
+    /* Validate the pointer to the buffer memory. */
+    if(pBuffer == NULL)
+    {
+        return(ADI_UART_INVALID_POINTER);
+    }
+
+    /* Validate the buffer size. */
+    if(nBufSize == 0U )
+    {
+        return(ADI_UART_FAILED);
+    }
+
+    /* Autobaud in progress. */
+    if(hDevice->bAutobaudInProgress == true)
+    {
+        return(ADI_UART_DEVICE_IN_USE);
+    }
+
+    /* Make sure the UART device is configured to operate in the receive direction. */
+    if(ADI_UART_DIR_TRANSMIT == hDevice->eDirection)
+    {
+        return(ADI_UART_OPERATION_NOT_ALLOWED);
+    }
+
+    /* Check for the data transfer mode(only allowed in blocking mode).*/
+    if(hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING)
+    {
+        return(ADI_UART_INVALID_DATA_TRANSFER_MODE);
+    }
+
+    /* Check that there is a free buffer to use for this receive operation. "pFreeBuffer"
+       is the next buffer available, so if it is in use we can make the assumption that
+       there are no buffers available. The start address gets set to NULL once the buffer
+       processing has completed.
+    */
+    if(hDevice->pChannelRx->pFreeBuffer->pStartAddress != NULL)
+    {
+        return(ADI_UART_OPERATION_NOT_ALLOWED);
+    }
+
+    /* Make sure the DMA transfer size is not too large. */
+    if((bDMA == true) && (nBufSize > DMA_TRANSFER_LIMIT))
+    {
+        return(ADI_UART_INVALID_DATA_SIZE);
+    }
+
+#endif /* ADI_DEBUG */
+
+    /* Set the data transfer mode in case it was #ADI_UART_DATA_TRANSFER_MODE_NONE.
+       This will be set back to #ADI_UART_DATA_TRANSFER_MODE_NONE once this
+       transaction is complete.
+    */
+    hDevice->pChannelRx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_BLOCKING;
+
+    /* Set the start address of the buffer you are going to submit. */
+    hDevice->pChannelRx->pFreeBuffer->pStartAddress  =  pBuffer;
+
+    /* Set the size of the buffer. */
+    hDevice->pChannelRx->pFreeBuffer->nCount         =  nBufSize;
+
+    /* Initialize the buffer index to 0, because as we receive data it will be put into
+       the buffer starting at the first position.
+    */
+    hDevice->pChannelRx->pFreeBuffer->nIndex         =  0U;
+
+    /* Mark the buffer as in use. */
+    hDevice->pChannelRx->pFreeBuffer->bInUse         =  true;
+
+    /* Mark the DMA as in use. */
+    hDevice->pChannelRx->pFreeBuffer->bDMA           =  bDMA;
+
+
+    /* Now that this "pFreeBuffer" is no longer free for use, update the
+       "pFreeBuffer" to the other PingPong buffer. Because there are only two
+       buffers in the PingPong structure, this will be the opposite of the one
+       we just submitted. "pFreeBuffer" will only be updated during the process of
+       submitting a buffer or a read/write operation.
+    */
+    hDevice->pChannelRx->pFreeBuffer = hDevice->pChannelRx->pFreeBuffer->pNextBuffer;
+
+    hDevice->pChannelRx->pfSubmitBuffer(hDevice, hDevice->pChannelRx->pFillBuffer);
+
+    /* Block for the active buffer to complete. */
+    return(uart_PendForBuffer(hDevice, hDevice->pChannelRx, pHwError));
+}
+
+/*! \cond PRIVATE */
+
+/*
+ * @brief       Pends for data transaction to complete. Buffer gets returned to API.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  pChannel   Pointer to UART channel data structure.
+ * @param [out] pBuffer    Address of buffer on which data transfer being carried out.
+ * @param [out] pHwError   Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status.
+ *                         If there is no hardware event, this will be 0.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS            Successfully got buffer.
+ *    - #ADI_UART_HW_ERROR_DETECTED  Hardware error(s) detected. "pHwError" can be checked for the specific error code(s).
+ *
+*/
+static ADI_UART_RESULT uart_PendForBuffer(
+                                           ADI_UART_HANDLE        const hDevice,
+                                           ADI_UART_DATA_CHANNEL       *pChannel,
+                                           uint32_t                    *pHwError
+                                          )
+{
+
+    /* Wait until the peripheral has finished processing the buffer. */
+    SEM_PEND(pChannel,ADI_UART_FAILED);
+
+     /* Reinitialize the start address to NULL so this buffer can be used for a new transaction. */
+     pChannel->pActiveBuffer->pStartAddress = NULL;
+
+      /* Now that the desired data has either been transmitted or received, this buffer is no longer
+         in use. We can update "pActiveBuffer" to point to the next buffer that will become or is already
+         active. This will only be updated in places where transactions are completed,
+         such as uart_PendForBuffer() and uart_GetBuffer().
+      */
+       pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer;
+
+     /* Set the data transfer mode to none so that the next transfer can be either in blocking or in nonblocking mode.
+        Only if there are no active buffers.
+     */
+     if(pChannel->pActiveBuffer->pStartAddress == NULL)
+     {
+        pChannel->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE;
+     }
+
+      /* If there are hardware errors and no callback, then return failure. */
+      if(hDevice->nHwError != 0u)
+      {
+          /* Save the hardware error detected. This will be passed back to the API. */
+          *pHwError = hDevice->nHwError;
+
+          /* Clear any hardware errors detected. */
+          hDevice->nHwError = 0u;
+
+          return(ADI_UART_HW_ERROR_DETECTED);
+      }
+      else
+      {
+          return(ADI_UART_SUCCESS);
+      }
+
+}
+/*! \endcond */
+
+
+/*!
+ * @brief       Peek function to know if an empty buffer is avilable.
+ *
+ * @param [in]  hDevice      Device handle obtained from adi_uart_Open().
+ * @param [out] pbAvailable  Pointer to a boolean variable. Contains "true" if there is an empty buffer
+ *                           and a call to "adi_uart_GetTxBuffer" is ensured to be successful. Contains
+ *                           "false" if there is no empty buffer.
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                   Successfully retrieved the status of availability of the buffer.
+ *    - #ADI_UART_INVALID_HANDLE        [D] Invalid UART device handle.
+ *    - #ADI_UART_OPERATION_NOT_ALLOWED [D] Call to this function is not allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING.
+ *
+ * @sa  adi_uart_GetTxBuffer()
+ * @sa  adi_uart_IsRxBufferAvailable
+ *
+ */
+
+ADI_UART_RESULT adi_uart_IsTxBufferAvailable(
+                                              ADI_UART_HANDLE const hDevice,
+                                              bool           *const pbAvailable
+                                            )
+{
+
+#ifdef ADI_DEBUG
+    /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* This function is only allowed to be called when the channel is operating in NONBLOCKING mode. */
+    if(hDevice->pChannelTx->eDataTranferMode ==  ADI_UART_DATA_TRANSFER_MODE_BLOCKING)
+    {
+        return(ADI_UART_OPERATION_NOT_ALLOWED);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Initialize to "false" in case of an error. */
+    *pbAvailable = false;
+
+    /* Make sure the buffer has not already been processed. This would mean that there are
+       currently no active buffers. This is only updated in adi_uart_GetBuffer(), which is
+       called once a transaction has completed.
+    */
+    if (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)
+    {
+        /* If the buffer has reached the interrupt handler, "bInUse" will be
+           updated so we know that the buffer has become available.
+        */
+        if (hDevice->pChannelTx->pActiveBuffer->bInUse == false)
+        {
+            *pbAvailable = true;
+        }
+    }
+    return(ADI_UART_SUCCESS);
+}
+
+/*!
+ * @brief       Peek function to know if a filled buffer is available.
+ *
+ *
+ * @param [in]  hDevice      Device handle obtained from adi_uart_Open().
+ * @param [out] pbAvailable  Pointer to a boolean variable. Contains "true" if there is an empty buffer
+ *                           and a call to "adi_uart_GetTxBuffer" is ensured to be successful. Contains
+ *                           "false" if there is no empty buffer.
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                   Successfully retrieved the status of availability of the buffer.
+ *    - #ADI_UART_INVALID_HANDLE        [D] Invalid UART device handle.
+ *    - #ADI_UART_OPERATION_NOT_ALLOWED [D] Call to this function is not allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING.
+ *
+ * @sa  adi_uart_GetRxBuffer()
+ *
+ */
+ADI_UART_RESULT    adi_uart_IsRxBufferAvailable(
+                                                 ADI_UART_HANDLE const hDevice,
+                                                 bool           *const pbAvailable
+                                                )
+{
+
+#ifdef ADI_DEBUG
+    /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* This function is only allowed to be called when the channel is operating in NONBLOCKING mode. */
+    if(hDevice->pChannelRx->eDataTranferMode ==  ADI_UART_DATA_TRANSFER_MODE_BLOCKING)
+    {
+        return(ADI_UART_OPERATION_NOT_ALLOWED);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Initialize to "false" in case of an error. */
+    *pbAvailable = false;
+
+    /* Make sure the buffer has not already been processed. This would mean that there are
+       currently no active buffers. This is only updated in adi_uart_GetBuffer(), which is
+       called once a transaction has completed.
+    */
+    if(hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)
+    {
+        /* If the buffer has reached the interrupt handler, "bInUse" will be
+           updated so we know that the buffer has become available.
+        */
+        if (hDevice->pChannelRx->pActiveBuffer->bInUse == false)
+        {
+            *pbAvailable = true;
+        }
+    }
+    return(ADI_UART_SUCCESS);
+}
+
+/*!
+ * @brief       Function to let the API know if all the data had been drained from the Tx shift registers.
+ *
+ * @param [in]  hDevice      Device handle obtained from adi_uart_Open().
+ * @param [out] pbComplete   Pointer to a boolean variable. Contains "true" if there is no data left in the
+ *                           device to transmit and device can be disabled without data loss. Contains "false"
+ *                           if the data transmission is not complete.
+ * @return      Status
+ *    - #ADI_UART_SUCCESS            Successfully retrieved the status of data transmission.
+ *    - #ADI_UART_INVALID_HANDLE [D] Specified handle is invalid.
+ *
+ * @note  adi_uart_getTxBuffer() or the callback may indicate that a transmit transaction is complete when the
+ *        device is using the DMA. This is because the interrupt will trigger once the transmit holding register is empty.
+          However, there may still be a some data in the shift register. If the transmit channel needs
+ *        to be closed then the application must poll the transmit channel to see if all data has indeed been transmitted before
+ *        shutting down the channel. Otherwise data will be lost.
+ *
+ */
+
+ADI_UART_RESULT adi_uart_IsTxComplete(
+                                     ADI_UART_HANDLE const hDevice,
+                                     bool           *const pbComplete
+                                     )
+{
+#ifdef ADI_DEBUG
+    /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Initialize to false. */
+    *pbComplete = false;
+
+    /* If the register is empty, set the return variable to "true".
+       This register is empty, when the value becomes a 1.
+    */
+    if((hDevice->pUARTRegs->LSR & BITM_UART_LSR_TEMT) == BITM_UART_LSR_TEMT)
+    {
+        *pbComplete = true;
+    }
+    return(ADI_UART_SUCCESS);
+}
+
+
+/*!
+ * @brief       Registering a callback function.
+ *
+ * @param [in]  hDevice       Device handle obtained from adi_uart_Open().
+ * @param [in]  pfCallback    Function pointer to callback. Passing a NULL pointer will unregister
+ *                            the callback function.
+ * @param [in]  pCBParam      Callback function parameter.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                Successfully registered callback function.
+ *    - #ADI_UART_DEVICE_IN_USE      [D] This operation is not allowed when a data transfer is in progress.
+ *    - #ADI_UART_INVALID_HANDLE     [D] Invalid UART device handle.
+ *
+ *
+*/
+ADI_UART_RESULT adi_uart_RegisterCallback(
+                                          ADI_UART_HANDLE const hDevice,
+                                          const ADI_CALLBACK    pfCallback,
+                                          void           *const pCBParam
+                                         )
+{
+
+#ifdef ADI_DEBUG
+    /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* Make sure there are no active buffers on any active channel and autobaud is not in progress. */
+    if(((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) ||
+       ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)) ||
+       (hDevice->bAutobaudInProgress == true))
+    {
+        return(ADI_UART_DEVICE_IN_USE);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Set the device callback. */
+    hDevice->pfCallback = pfCallback;
+
+    /* Set the callback parameter. */
+    hDevice->pCBParam = pCBParam;
+
+    return(ADI_UART_SUCCESS);
+}
+
+
+/*!
+ * @brief        Configuration of UART data.
+ *
+ * @details      Sets the configuration parameters for the specified UART device such as wordlength, whether to
+ *               enable/disable the parity, and the number of stop bits. This function returns an error if the
+ *               device has active data or autobaud is in progress.
+ *
+ * @param [in]  hDevice      Device handle obtained from adi_uart_Open().
+ * @param [in]  eParity      Specify the type of parity check for the UART device.
+ * @param [in]  eStopBits    Specify the stop-bits for the UART device.
+ * @param [in]  eWordLength  Specify the word size of the data for the UART device.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                Successfully set the data configuration.
+ *    - #ADI_UART_DEVICE_IN_USE      [D] This operation is not allowed when a data transfer or autobaud is in progress.
+ *    - #ADI_UART_INVALID_HANDLE     [D] Invalid UART device handle.
+ *
+*/
+ADI_UART_RESULT adi_uart_SetConfiguration(
+                                         ADI_UART_HANDLE   const hDevice,
+                                         ADI_UART_PARITY   const eParity,
+                                         ADI_UART_STOPBITS const eStopBits,
+                                         ADI_UART_WORDLEN  const eWordLength
+                                         )
+{
+#ifdef ADI_DEBUG
+    /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* Make sure there are no active buffers on any active channel and autobaud is not in progress. */
+    if(((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) ||
+       ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)) ||
+       (hDevice->bAutobaudInProgress == true))
+    {
+        return(ADI_UART_DEVICE_IN_USE);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Clear all the fields.  */
+    uint16_t nDataCfg = hDevice->pUARTRegs->LCR & (uint16_t)(~(BITM_UART_LCR_WLS |BITM_UART_LCR_STOP |BITM_UART_LCR_PEN));
+
+    /* Construct the configuration word. */
+    nDataCfg |= (uint16_t)(((uint16_t)((uint16_t)eWordLength |(uint16_t)eStopBits) |(uint16_t)eParity));
+
+    /* Write to the register */
+    hDevice->pUARTRegs->LCR = nDataCfg;
+
+    /* Return Success */
+    return(ADI_UART_SUCCESS);
+}
+
+/*!
+ * @brief        Set baudrate by configuring the fractional dividors.
+ *
+ * @details      Baudrate is calculated as per below equation.
+ *
+ *               Baudrate = (UARTCLK / (nDivM + nDivN/2048)*pow(2,nOSR+2)* nDivC)).
+ *
+ * @param [in]  hDevice      Device handle obtained from adi_uart_Open().
+ * @param [in]  nDivC        Specify the "nDivC" in the above equation.
+ * @param [in]  nDivM        Specify the "nDivM" in the above equation.
+ * @param [in]  nDivN        Specify the "nDivN" in the above equation.
+ * @param [in]  nOSR         Specify the "nOSR" " in the above equation.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                 Successfully set the baudrate for the device.
+ *    - #ADI_UART_INVALID_HANDLE     [D]  Invalid UART device handle.
+ *    - #ADI_UART_DEVICE_IN_USE      [D]  Device is in use
+ *    - #ADI_UART_INVALID_PARAMETER  [D]  Input for baud rate values are out of range.
+ *
+ *   @sa  adi_uart_GetBaudRate()
+ *   @sa  adi_uart_EnableAutobaud();
+ *
+ *   @note It is expected that initialization of the power management
+ *         driver is done before calling this function.
+ *
+ */
+ADI_UART_RESULT adi_uart_ConfigBaudRate(
+                                       ADI_UART_HANDLE const hDevice,
+                                       uint16_t        const nDivC,
+                                       uint8_t         const nDivM,
+                                       uint16_t        const nDivN,
+                                       uint8_t         const nOSR
+                                       )
+{
+#ifdef ADI_DEBUG
+    /* Validate the given handle */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* Make sure there are no active buffers on any active channel. */
+    if(((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) ||
+       ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)))
+    {
+        return(ADI_UART_DEVICE_IN_USE);
+    }
+
+    /* Check if the given baudrate is valid */
+    if( (nDivM < 1u) || (nDivM > 3u)|| (nDivN > 2047u ) || (nOSR > 3u))
+    {
+        return ADI_UART_INVALID_PARAMETER;
+    }
+
+#endif /* ADI_DEBUG */
+
+    /* Write back the register contents for baudrate detection in the hardware. */
+    hDevice->pUARTRegs->DIV  =  nDivC;
+    hDevice->pUARTRegs->FBR  =  (uint16_t)((uint16_t)nDivN | (uint16_t)((uint16_t)nDivM <<BITP_UART_FBR_DIVM)) | (uint16_t)BITM_UART_FBR_FBEN;
+    hDevice->pUARTRegs->LCR2 = nOSR;
+
+    return(ADI_UART_SUCCESS);
+}
+
+
+/*!
+ * @brief       Get the baudrate of the UART device instance. This is used in the scenario when a callback has not been initialized.
+ *              This allows the the API to know if autobaud is complete. If this returns a baudrate other than 0,
+ *              it indicates that the autobaud completed, otherwise autobaud is still in progress.
+ *
+ * @param [in]   hDevice         Device handle obtained from adi_uart_Open().
+ * @param [out]  pnBaudRate      Pointer to a location where baudrate is to be written.
+ * @param [out]  pAutobaudError  Pointer to an integer that will hold the value of any baudrate error(s), that correlates with
+ *                               #ADI_UART_AUTOBAUD_ERRORS. This will be 0 if there are no errors.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                   Successfully retrieved the baudrate.
+ *    - #ADI_UART_AUTOBAUD_ERROR_DETECTED   There has been an autobaud error. The API can get the specific error(s)
+ *                                          by checking "pAutobaudError".
+ *    - #ADI_UART_INVALID_HANDLE        [D] Invalid UART device handle.
+ *    - #ADI_UART_INVALID_POINTER       [D] The pointer to baudrate or autobaud error is NULL.
+
+ *
+*/
+ADI_UART_RESULT adi_uart_GetBaudRate(
+                                      ADI_UART_HANDLE const     hDevice,
+                                      uint32_t                 *pnBaudRate,
+                                      uint32_t                 *pAutobaudError
+                                    )
+{
+
+#ifdef ADI_DEBUG
+    /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* Validate pointers. */
+    if(pnBaudRate == NULL)
+    {
+        return(ADI_UART_INVALID_POINTER);
+    }
+
+#endif /* ADI_DEBUG */
+
+    /* If an error occured during autobaud this value will be set to a
+       non-zero value. The specific error can be found by checking against
+       #ADI_UART_EVENT.
+    */
+    if(hDevice->nAutobaudError != 0u)
+    {
+      /* Save the autobaud error to pass back to the API.*/
+      *pAutobaudError = hDevice->nAutobaudError;
+
+      /* Clear the autobaud errors found. */
+      hDevice->nAutobaudError = 0u;
+
+      return(ADI_UART_AUTOBAUD_ERROR_DETECTED);
+    }
+
+    /* Return the baudrate. If this is 0, then autobaud has not completed. */
+    *pnBaudRate = hDevice->nBaudRate;
+
+    return(ADI_UART_SUCCESS);
+}
+
+
+/*!
+ * @brief       Enable/Disable UART autobaud detection as well as configures the device for autobaud detection.
+ *
+ * @details     The baud rate is detected using the hardware support.
+ *              After the baud rate is detected the interrupt handler is notified of the completion.
+ *              When a callback is not registered with UART driver, the API adi_uart_GetBaudRate()
+ *              can be used to know if autobaud is complete. Autobaud needs to be disabled in order to
+ *              clear the internal counter and to close the device.
+ *
+ * @param [in]  hDevice                 Handle to UART device whose autobaud detection to be enabled/disabled.
+ * @param [in]  bEnable                 Boolean flag to indicate whether to enable or disable the autobaud.
+ * @param [in]  bAutobaudCallbackMode   Use a callback to report autobaud errors or type #ADI_UART_AUTOBAUD_ERRORS.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS                       Successfully enabled/disabled Autobaud detection.
+ *    - #ADI_UART_DEVICE_IN_USE             [D] Trying to enable/disable Autobaud when
+ *                                              dataflow is enabled or autobaud is in progress.
+ *    - #ADI_UART_INVALID_HANDLE            [D] Invalid UART device handle.
+ *
+ * @sa  adi_uart_GetBaudRate()
+ *
+ * @note: For autobaud we assume the key character being used is a carrige return (0xD), so the start edge count is
+ *        hardcoded to the second edge (first edge after start edge) and the last edge count is set to the fouth edge.
+ *        This will give us a total bit count of 8 bits that we will time in order to figure out the baud rate (bits/second).
+ */
+ADI_UART_RESULT adi_uart_EnableAutobaud(
+                                        ADI_UART_HANDLE          const hDevice,
+                                        bool                     const bEnable,
+                                        bool                     const bAutobaudCallbackMode
+                                       )
+{
+
+#ifdef ADI_DEBUG
+     /* Validate the given handle */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+
+    /* Make sure there are no active buffers on any active channel and autobaud is not in progress. */
+    if(((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) ||
+       ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)))
+    {
+        return(ADI_UART_DEVICE_IN_USE);
+    }
+
+#endif /* ADI_DEBUG */
+
+    if(bEnable)
+    {
+        /* Enable Autobaud, timeout interrupt and done interrupt in the autobaud control register.
+           Set the starting edge trigger to the second edge. Set the ending edge count to
+           the fourth edge, for the carrige return key character (0xD).
+        */
+        hDevice->pUARTRegs->ACR |=(BITM_UART_ACR_ABE | BITM_UART_ACR_DNIEN | BITM_UART_ACR_TOIEN |(1u << 4u) | (3u << 8u));
+
+        /* Initialize device baudrate to 0. This will be set once autobaud is complete. */
+        hDevice->nBaudRate = 0u;
+
+        /* Change the state to indicate autobaud is in progress. */
+        hDevice->bAutobaudInProgress = true;
+
+        /* Set the callback mode for autobaud based on the user input. */
+        hDevice->bAutobaudCallbackMode = bAutobaudCallbackMode;
+    }
+    else
+    {
+        /* Change the state to indicate autobaud is not in progress. */
+        hDevice->bAutobaudInProgress = false;
+
+        /* Disable Autobaud, timeout interrupt and done interrupt in the autobaud control register. */
+        hDevice->pUARTRegs->ACR |= (uint16_t)(~(uint32_t)BITM_UART_ACR_ABE | ~(uint32_t)BITM_UART_ACR_DNIEN | ~(uint32_t)BITM_UART_ACR_TOIEN);
+
+        /* Initialize device baudrate to 0. */
+        hDevice->nBaudRate = 0u;
+    }
+
+    return ADI_UART_SUCCESS;
+}
+
+/*!
+ * @brief       Forces the UART to send out a break signal.
+ *
+ * @details     Sets the UART Tx pin to a logic-low/high (depending upon the
+ *              Tx polarity) asynchronously. The UART keeps transmitting break
+ *              until it is disabled to send the break.
+ *
+ * @param [in]  hDevice             Handle to the UART whose Tx is forced to
+ *                                  send a break.
+ * @param [in]  bEnable             Flag which indicates whether to enable or
+ *                                  disable transmitting the break.
+ *
+ * @return      Status
+ *
+ * - #ADI_UART_SUCCESS              If successfully enabled or disabled sending break.
+ * - #ADI_UART_INVALID_HANDLE   [D] If the given UART handle is invalid.
+ */
+ADI_UART_RESULT adi_uart_ForceTxBreak(
+                                      ADI_UART_HANDLE         const hDevice,
+                                      bool                    const bEnable
+                                     )
+{
+
+#ifdef ADI_DEBUG
+     /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+#endif /* ADI_DEBUG */
+
+    if(bEnable == true)
+    {
+        /* Set the force break bit. */
+        hDevice->pUARTRegs->LCR    |= BITM_UART_LCR_BRK;
+    }
+    else
+    {
+        /* Clear the force break bit. */
+        hDevice->pUARTRegs->LCR    &= (uint16_t)~(BITM_UART_LCR_BRK);
+    }
+
+    return ADI_UART_SUCCESS;
+}
+
+/*!
+ * @brief       Enable/Disable the loopback for the specified UART device.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  bEnable    Boolean flag to indicate whether to enable or disable the loopback mode.
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS            Successfully enable/disable the loopback.
+ *    - #ADI_UART_INVALID_HANDLE     Invalid  UART device handle.
+ *
+*/
+ADI_UART_RESULT adi_uart_EnableLoopBack(
+                                        ADI_UART_HANDLE const hDevice,
+                                        bool            const bEnable
+                                       )
+{
+
+#ifdef ADI_DEBUG
+     /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+#endif /* ADI_DEBUG */
+
+    if(true == bEnable)
+    {
+        /* Enable loopback. */
+        hDevice->pUARTRegs->MCR |= (BITM_UART_MCR_LOOPBACK);
+    }
+    else
+    {
+        /* Disable loopback. */
+        hDevice->pUARTRegs->MCR &= (uint16_t)~(BITM_UART_MCR_LOOPBACK);
+    }
+    return(ADI_UART_SUCCESS);
+}
+
+/*!
+ * @brief       Sets the RX FIFO trigger level. This will be the amount of data in the FIFO
+ *              that will trigger an interrupt.
+ *
+ *
+ * @param [in]  hDevice         Device handle obtained from adi_uart_Open().
+ * @param [in]  eTriglevel      Trigger level to be set in terms of number of bytes.
+ *
+ * @return      Status
+ *  - #ADI_UART_SUCCESS             Successfully set the trigger level.
+ *  - #ADI_UART_INVALID_HANDLE  [D] The given UART handle is invalid.
+ */
+ADI_UART_RESULT adi_uart_SetRxFifoTriggerLevel(
+                                               ADI_UART_CONST_HANDLE         const hDevice,
+                                               ADI_UART_TRIG_LEVEL           const eTriglevel
+                                              )
+{
+#ifdef ADI_DEBUG
+     /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Clear existing FIFO trigger level. */
+    hDevice->pUARTRegs->FCR &= (uint16_t)~BITM_UART_FCR_RFTRIG;
+
+    /* Set the FIFO trigger level. */
+    hDevice->pUARTRegs->FCR |= (uint16_t)eTriglevel;
+
+    return(ADI_UART_SUCCESS);
+}
+/*!
+ * @brief       Enables internal FIFO as to work in 16550 mode. This helps to minimize system overhead
+ *              and maximize system efficiency.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  bEnable    Boolean flag to indicate whether to enable or disable FIFO.
+ *
+ * @return      Status
+ *  - #ADI_UART_SUCCESS              If successfully enabled FIFO for UART device.
+ *  - #ADI_UART_INVALID_HANDLE   [D] The given UART handle is invalid.
+ */
+ADI_UART_RESULT adi_uart_EnableFifo(
+                                     ADI_UART_HANDLE         const hDevice,
+                                     bool                    const bEnable
+                                    )
+{
+
+#ifdef ADI_DEBUG
+     /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+#endif /* ADI_DEBUG */
+
+    if(bEnable == true)
+    {
+       /* Enable TX/RX FIFO. */
+       hDevice->pUARTRegs->FCR    |=  BITM_UART_FCR_FIFOEN;
+       hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ERBFI);
+
+       hDevice->bRxFifoEn = true;
+
+    }
+    else
+    {
+       /* Disable TX/RX FIFO. */
+       hDevice->pUARTRegs->FCR    &= (uint16_t)~(BITM_UART_FCR_FIFOEN);
+
+       hDevice->bRxFifoEn = false;
+    }
+
+    return ADI_UART_SUCCESS;
+}
+
+/*!
+ * @brief      To flush the TX FIFO.
+ *
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ *
+ *
+ * @return      Status
+ *  - #ADI_UART_SUCCESS             Successfully flushed TX Fifo.
+ *  - #ADI_UART_INVALID_HANDLE  [D] The given UART handle is invalid.
+ */
+ADI_UART_RESULT adi_uart_FlushTxFifo(
+                                     ADI_UART_CONST_HANDLE         const hDevice
+                                    )
+{
+
+#ifdef ADI_DEBUG
+     /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Flush the Tx FIFO. */
+    hDevice->pUARTRegs->FCR    |=  BITM_UART_FCR_TFCLR;
+
+    return(ADI_UART_SUCCESS);
+}
+
+/*!
+ * @brief       Flush the RX FIFO.
+ *
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ *
+ *
+ * @return      Status
+ *  - #ADI_UART_SUCCESS              Successfully flushed RX Fifo.
+ *  - #ADI_UART_INVALID_HANDLE   [D] The given UART handle is invalid.
+ */
+ADI_UART_RESULT adi_uart_FlushRxFifo(
+                                      ADI_UART_CONST_HANDLE         const hDevice
+                                     )
+{
+
+#ifdef ADI_DEBUG
+     /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Flush RX FIFO. */
+    hDevice->pUARTRegs->FCR    |=  BITM_UART_FCR_RFCLR;
+
+    return ADI_UART_SUCCESS;
+}
+
+/*!
+ * @brief      Flush the Rx channel and disable interrupts. This will stop any buffers in flight and
+ *             clear out any data that was in the RX holding register as well as the Rx fifo. Once this is done,
+ *             in order to turn back on Rx interrupts, a new transaction will need to be started (adi_uart_Read()
+ *             or adi_uart_SubmitRxBuffer()).
+ *
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ *
+ * @return      Status
+ *  - #ADI_UART_SUCCESS                       Successfully flushed the Rx channel.
+ *  - #ADI_UART_INVALID_HANDLE            [D] The given UART handle is invalid.
+ */
+ADI_UART_RESULT adi_uart_FlushRxChannel(
+                                         ADI_UART_CONST_HANDLE  const hDevice
+                                        )
+{
+
+#ifdef ADI_DEBUG
+     /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Disable receive interrupts in PIO mode as well as DMA mode. */
+    hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ERBFI | BITM_UART_IEN_EDMAR);
+
+    /* Clear any data in the Rx Fifo. */
+    hDevice->pUARTRegs->FCR |=  BITM_UART_FCR_RFCLR;
+
+    /* Reset the buffers to 0. */
+    memset(hDevice->pChannelRx->PingPong,0, sizeof (hDevice->pChannelRx->PingPong));
+
+    hDevice->pChannelRx->PingPong[0].pNextBuffer  = &hDevice->pChannelRx->PingPong[1];
+    hDevice->pChannelRx->PingPong[1].pNextBuffer  = &hDevice->pChannelRx->PingPong[0];
+
+    /* Reset the buffer pointers. */
+    hDevice->pChannelRx->pActiveBuffer = &hDevice->pChannelRx->PingPong[0];
+    hDevice->pChannelRx->pFreeBuffer = &hDevice->pChannelRx->PingPong[0];
+    hDevice->pChannelRx->pFillBuffer = &hDevice->pChannelRx->PingPong[0];
+
+    /* Dummy read to flush the RX register. */
+    hDevice->pUARTRegs->RX;
+
+    return(ADI_UART_SUCCESS);
+}
+
+/*!
+ * @brief      Flush the Tx channel and disable interrupts.This will stop any buffers in flight and
+ *             clear out any data that was in the TX holding register. Any data in the TX shift register
+ *             will still finish transmitting.
+ *
+ *
+ * @param [in]  hDevice       Device handle to UART device obtained when an UART device is opened successfully.
+ *
+ * @return      Status
+ *  - #ADI_UART_SUCCESS                   Successfully flushed the Tx channel.
+ *  - #ADI_UART_INVALID_HANDLE        [D] The given UART handle is invalid.
+ */
+ADI_UART_RESULT adi_uart_FlushTxChannel(ADI_UART_CONST_HANDLE  const hDevice)
+{
+
+#ifdef ADI_DEBUG
+     /* Validate the given handle. */
+    if(ValidateHandle(hDevice) != ADI_UART_SUCCESS)
+    {
+        return(ADI_UART_INVALID_HANDLE);
+    }
+#endif /* ADI_DEBUG */
+
+    /* Disable transmit interrupts in PIO mode as well as DMA mode. */
+    hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ETBEI | BITM_UART_IEN_EDMAT);
+
+    /* Clear any data in the Rx Fifo. */
+    hDevice->pUARTRegs->FCR |=  BITM_UART_FCR_TFCLR;
+
+    /* Reset the buffers to 0. */
+    memset(hDevice->pChannelTx->PingPong,0, sizeof (hDevice->pChannelTx->PingPong));
+
+    hDevice->pChannelTx->PingPong[0].pNextBuffer  = &hDevice->pChannelTx->PingPong[1];
+    hDevice->pChannelTx->PingPong[1].pNextBuffer  = &hDevice->pChannelTx->PingPong[0];
+
+    /* Reset the buffer pointers. */
+    hDevice->pChannelTx->pActiveBuffer = &hDevice->pChannelTx->PingPong[0];
+    hDevice->pChannelTx->pFreeBuffer = &hDevice->pChannelTx->PingPong[0];
+    hDevice->pChannelTx->pFillBuffer = &hDevice->pChannelTx->PingPong[0];
+
+    return(ADI_UART_SUCCESS);
+}
+
+
+/*! \cond PRIVATE */
+
+void UART0_Int_Handler(void)
+{
+    ISR_PROLOG();
+    ADI_UART_HANDLE hDevice = (ADI_UART_HANDLE)uart_device_info[0].hDevice;
+    Common_Uart_Interrupt_Handler(hDevice);
+#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u)
+    ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_UART);    
+#endif
+    ISR_EPILOG();
+    return;
+}
+
+void UART1_Int_Handler(void)
+{
+    ISR_PROLOG();
+    ADI_UART_HANDLE hDevice = (ADI_UART_HANDLE)uart_device_info[1].hDevice;
+    Common_Uart_Interrupt_Handler(hDevice);
+#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u)
+    ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_UART);    
+#endif
+    ISR_EPILOG();
+    return;
+}
+
+static void Common_Uart_Interrupt_Handler(ADI_UART_HANDLE hDevice)
+{
+      switch(hDevice->pUARTRegs->IIR & BITM_UART_IIR_STAT )
+    {
+        /* Tx buffer empty interrupt. This means that the data has successfully left the holding register and is
+           now in transmit shift register or has completed its transfer.
+        */
+        case ENUM_UART_IIR_STAT_ETBEI:
+          uart_TxDataHandler(hDevice);
+          break;
+
+        /* Rx buffer FIFO timeout interrupt. This means that we have data in the RX FIFO
+           but there is not enough data to trigger an interrupt so we will process this data here.
+        */
+        case ENUM_UART_IIR_STAT_RFTOI:
+          uart_RxDataHandler(hDevice);
+          break;
+
+        /* Rx buffer full interrupt. This means that the RX buffer has finished receiving data. */
+        case ENUM_UART_IIR_STAT_ERBFI:
+          uart_RxDataHandler(hDevice);
+          break;
+
+        /* Line status interrupt. */
+        case ENUM_UART_IIR_STAT_RLSI:
+        {
+            /* Initialze the line status event to 0. */
+            uint32_t nEvent = 0u;
+
+            /* Get the interrupts status. */
+            uint16_t  nStatus = hDevice->pUARTRegs->LSR;
+
+            /* If a break signal is detected.. */
+            if((BITM_UART_LSR_BI & nStatus) == BITM_UART_LSR_BI)
+            {
+                /* Dummy read to flush the RX register. We do this because
+                   we do not actaully want to do anything with this data as it
+                   is only a break indicator. */
+                hDevice->pUARTRegs->RX;
+
+                /* Set the event to a break interrupt. */
+                nEvent  = (uint32_t)ADI_UART_BREAK_INTERRUPT;
+            }
+
+            /* Ignore the framing error if the break is asserted.
+               We do this because a break can trigger a false framing error.
+            */
+            else if((BITM_UART_LSR_FE & nStatus) == BITM_UART_LSR_FE)
+            {
+                /* Set the event to show a framing error has been detected. */
+                nEvent |= (uint32_t)ADI_UART_HW_ERR_FRAMING;
+            }
+            else
+            {
+              /* Do nothing. This is required for MISRA. */
+            }
+
+            if((BITM_UART_LSR_PE & nStatus) == BITM_UART_LSR_PE)
+            {
+                /* Set the event to show a parity error has been detected. */
+                nEvent  |=  (uint32_t)ADI_UART_HW_ERR_PARITY;
+            }
+            if((BITM_UART_LSR_OE & nStatus) == BITM_UART_LSR_OE)
+            {
+                /* Set the event to show a hardware overrun error has been detected, meaning receive data has
+                   been overwritten.
+                */
+                nEvent |= (uint32_t)ADI_UART_HW_ERR_OVERRUN;
+            }
+
+            /* If there was an event and autobaud is not in progress, notify the API. */
+            if((nEvent != 0u) && (hDevice->bAutobaudInProgress == false))
+            {
+                /* Set the UART device hw error bit field. This will allow us to return the
+                   specific failure to the application once we return from this ISR.
+                */
+                hDevice->nHwError |= nEvent;
+                uart_ManageProcessedBuffer(hDevice, hDevice->pChannelRx, ADI_UART_EVENT_HW_ERROR_DETECTED);
+            }
+            break;
+         }
+
+         /* If there was a modem status interrupt. For our purposes, we will only check if this is related to autobaud. */
+         case ENUM_UART_IIR_STAT_EDSSI:
+         {
+#if (ADI_UART_CFG_ENABLE_AUTOBAUD == 1)
+            /* Initialize the autobaud event to 0. */
+            uint32_t nEvent = 0u;
+
+            /* Get the autobaud interrupt status but not the counter value. */
+            uint16_t nStatus =  hDevice->pUARTRegs->ASRL & 0xFu;
+
+            /* Read the autobaud control register to see if autobaud was enabled. */
+            uint16_t  acr = (hDevice->pUARTRegs->ACR & BITM_UART_ACR_ABE);
+
+            /* If there is an autobaud event and autobaud is enabled */
+            if((nStatus != 0u) && (acr != 0u))
+            {
+                uint32_t nClock;
+                uint32_t nCount;
+
+                /*Get the clock frequency. */
+                if(adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK,&nClock) != ADI_PWR_SUCCESS)
+                {
+                  nClock = 0u;
+                }
+
+                /* Get the autobaud counter bits 12-19. */
+                nCount = (uint32_t)hDevice->pUARTRegs->ASRH << 12u;
+
+                /* Get the autobaud counter bits 0-11. */
+                nCount |= (uint32_t)hDevice->pUARTRegs->ASRL >> 4u;
+
+                /* if the autobaud event was that the autobaud is done.. */
+                if((nStatus & BITM_UART_ASRL_DONE) == BITM_UART_ASRL_DONE)
+                {
+                    /* If the fractional baud generator is enabled, calculate the fractional portional of the baudrate.
+                       It seems that in order to get a correct baudrate reading, we need the fractional divider enabled.
+                    */
+                    if ((hDevice->pUARTRegs->FBR & 0x8000u) == 0x8000u)
+                    {
+                        uint8_t nOSR = 0u;
+                        uint32_t nDivN;
+                        uint32_t nDivNSubtractor = 2048u;
+
+                        /* DIVC is always 1, unless the oversample rate is 32. */
+                        uint16_t nDivC = 1u;
+
+                        /* If the oversample rate is 4.. */
+                        if(nCount < (8u << 3u))
+                        {
+                             nDivN = ((nCount << 9u) / 8u) - nDivNSubtractor;
+                        }
+
+                        /* If the oversample rate is 8.. */
+                        else if(nCount < (8u << 4u))
+                        {
+                             nDivN = ((nCount << 8u) / 8u) - nDivNSubtractor;
+                             nOSR = 1u;
+                        }
+
+                        /* If the oversample rate is 16.. */
+                        else if(nCount < (8u << 5u))
+                        {
+                             nDivN = ((nCount << 7u) / 8u) - nDivNSubtractor;
+                             nOSR = 2u;
+                        }
+
+                        /* If the oversample rate is 32.. */
+                        else
+                        {
+                            nDivC = (uint16_t) (nCount / 32u / 8u);
+                            nDivN = ((nCount << 6u) / (8u * nDivC)) - nDivNSubtractor;
+                            nOSR = 3u;
+                        }
+
+                        /* Write back the register contents for baudrate detection in the hardware. */
+                        adi_uart_ConfigBaudRate(hDevice, nDivC, 1u, (uint16_t)nDivN, nOSR);
+
+                        /* For more precise calculations we would use floating point math here. Integer precision will do for now.
+                           This avoids bringing in extra libraries for floating point math. */
+
+                        /* Baudrate = (UARTCLK / (nDivM + nDivN / 2048) * pow(2, nOSR + 2) * nDivC)
+                        nOSR = (1u << (nOSR + 2u)); Seperate this out of the equation for misra compliance
+                        hDevice->nBaudRate = ((float)nClock / (((float)1 + (float)nDivN / (float)2048) * (float)nOSR * (float)nDivC));
+                        */
+
+                        /* In order to avoid bringing in the extra floating point libraries, we will use the non fractional baudrate for the API. */
+                        hDevice->nBaudRate = ((nClock * 8u) / nCount);
+                    }
+                    else
+                    {
+                      /* No Fractional divider: Baudrate (bits/second) = (UARTCLK (cycles/second) * counted bits (bits)) / nCount (cycles)*/
+                      hDevice->nBaudRate = ((nClock * 8u) / nCount);
+                    }
+
+                    /* If there is a callback, notify the API that autobaud is complete.
+                       If there is not a callback, the baudrate will be set to a non zero value so the user can call "Get_BaudRate"
+                       to know that autobaud has completed.
+                    */
+                    if((hDevice->pfCallback != NULL) && (hDevice->bAutobaudCallbackMode == true))
+                    {
+                        hDevice->pfCallback(hDevice->pCBParam, ADI_UART_EVENT_AUTOBAUD_COMPLETE, (void*)hDevice->nBaudRate);
+                    }
+                }
+                else
+                {
+                    if((nStatus & BITM_UART_ASRL_BRKTO) == BITM_UART_ASRL_BRKTO)
+                    {
+                        /* Autobaud timed out due to break error. */
+                       nEvent |= (uint32_t)ADI_UART_AUTOBAUD_TIMEOUT_LONGBREAK;
+                    }
+                    if((nStatus & BITM_UART_ASRL_NSETO) == BITM_UART_ASRL_NSETO)
+                    {
+                        /* Autobaud timed out due to no valid start edge found. */
+                        nEvent |= (uint32_t)ADI_UART_AUTOBAUD_TIMEOUT_NO_START_EDGE;
+                    }
+                    if((nStatus & BITM_UART_ASRL_NEETO) == BITM_UART_ASRL_NEETO)
+                    {
+                        /* Autobaud timed out due to no valid end edge found. */
+                        nEvent |= (uint32_t)ADI_UART_AUTOBAUD_TIMEOUT_NO_END_EDGE;
+                    }
+                    /* If there is an event callback.. */
+                    if((hDevice->pfCallback != NULL) && (hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING))
+                    {
+                      /* Notify application of errors through callback. */
+                      hDevice->pfCallback(hDevice->pCBParam, ADI_UART_EVENT_AUTOBAUD_ERROR_DETECTED, (void*)nEvent);
+                    }
+                    else
+                    {
+                      /* Notify application of errors through autobaud return value. */
+                      hDevice->nAutobaudError = nEvent;
+                    }
+
+                }
+
+                /* Dummy read to flush the RX register to clear the key character that was sent while configuring autobaud. */
+                hDevice->pUARTRegs->RX;
+            }
+#endif
+            /* Clear auto baud enable and interrupt registers. We disable autobaud here because it is required in order to clear the counter.  */
+             hDevice->pUARTRegs->ACR &=(uint16_t)~( BITM_UART_ACR_ABE   |
+                                                       BITM_UART_ACR_DNIEN |
+                                                       BITM_UART_ACR_TOIEN );
+
+             hDevice->bAutobaudInProgress = false;
+             break;
+         }
+        default:
+          break;
+    }
+    return;
+}
+
+
+/* DMA interrupt handlers */
+void DMA_UART0_TX_Int_Handler(void)
+{
+   ISR_PROLOG();
+   ADI_UART_HANDLE const hDevice = (ADI_UART_HANDLE)uart_device_info[0].hDevice;
+   uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED);
+#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u)
+    ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_DMA_UART_TX);    
+#endif
+   ISR_EPILOG();
+}
+
+void DMA_UART0_RX_Int_Handler(void)
+{
+   ISR_PROLOG();
+   ADI_UART_HANDLE const hDevice = (ADI_UART_HANDLE)uart_device_info[0].hDevice;
+   uart_ManageProcessedBuffer(hDevice,hDevice->pChannelRx,ADI_UART_EVENT_RX_BUFFER_PROCESSED);
+#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u)
+    ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_DMA_UART_RX);    
+#endif
+   ISR_EPILOG();
+}
+
+void DMA_UART1_TX_Int_Handler(void)
+{
+   ISR_PROLOG();
+   ADI_UART_HANDLE const hDevice = (ADI_UART_HANDLE)uart_device_info[1].hDevice;
+   uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED);
+#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u)
+    ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_DMA_UART_TX);    
+#endif
+   ISR_EPILOG();
+}
+
+void DMA_UART1_RX_Int_Handler(void)
+{
+   ISR_PROLOG();
+   ADI_UART_HANDLE const hDevice = (ADI_UART_HANDLE)uart_device_info[1].hDevice;
+   uart_ManageProcessedBuffer(hDevice,hDevice->pChannelRx,ADI_UART_EVENT_RX_BUFFER_PROCESSED);
+#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u)
+    ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_DMA_UART_RX);    
+#endif
+   ISR_EPILOG();
+}
+
+
+/*
+ * @brief                  UART interrupt handler for receiving the data in interrupt mode.
+ *
+ * @param [in]  hDevice   Device handle obtained from adi_uart_Open().
+ *
+*/
+static void uart_RxDataHandler(ADI_UART_HANDLE hDevice)
+{
+    volatile uint8_t *pNextData;
+
+    /* If there is an active buffer.. */
+    if((hDevice->pChannelRx->pFillBuffer->pStartAddress != NULL) && (hDevice->pChannelRx->pFillBuffer->bInUse == true))
+    {
+           /* Get the address of the buffer we are filling. */
+           pNextData = (uint8_t *)hDevice->pChannelRx->pFillBuffer->pStartAddress;
+
+           /* Read data from the RX holding register into the buffer at the indexed location. */
+           pNextData[hDevice->pChannelRx->pFillBuffer->nIndex] = (uint8_t) hDevice->pUARTRegs->RX;
+
+           /* Increment the buffer index so we don't overwrite this data in the buffer. */
+           hDevice->pChannelRx->pFillBuffer->nIndex++;
+
+           /* If all of the data has been processed, manage the processed data buffer. Otherwise we will
+              leave everything as is and continue to receive interrupts for the incoming data, until this
+              buffer has been filled.
+           */
+           if(hDevice->pChannelRx->pFillBuffer->nIndex == hDevice->pChannelRx->pFillBuffer->nCount)
+           {
+                  uart_ManageProcessedBuffer(hDevice, hDevice->pChannelRx, ADI_UART_EVENT_RX_BUFFER_PROCESSED);
+           }
+    }
+    /* If we do not have a buffer submitted.. */
+    else
+    {
+          /* Ask the API for a buffer so we can process this data before having an overflow.
+             if there is no callback, the API will not be able to submit a buffer in time.
+          */
+          if (hDevice->pfCallback != NULL)
+          {
+              hDevice->pfCallback(hDevice->pCBParam, (uint32_t)ADI_UART_EVENT_NO_RX_BUFFER_EVENT, NULL);
+          }
+
+          /* This check here is in case in the callback the application submitted a buffer. If they did
+             not then we need to clear the RX register in order to clear this interrupt.
+          */
+          if((hDevice->pChannelRx->pFillBuffer->pStartAddress == NULL) && (hDevice->pChannelRx->pFillBuffer->bInUse == false))
+          {
+              hDevice->pUARTRegs->RX;
+          }
+    }
+
+    return;
+}
+
+/*
+ * @brief      UART interrupt handler transmitting the data in interrupt mode.
+ *
+ * @param [in]  hDevice   Device handle obtained from adi_uart_Open().
+ *
+*/
+static void uart_TxDataHandler(ADI_UART_HANDLE hDevice)
+{
+      volatile uint8_t *pNextData;
+
+    /* If there is an active buffer.. */
+   if((hDevice->pChannelTx->pFillBuffer->pStartAddress != NULL) && (hDevice->pChannelTx->pFillBuffer->bInUse == true))
+    {
+           /* Get the start address of the buffer we are transmitting data from. */
+           pNextData = (uint8_t *)hDevice->pChannelTx->pFillBuffer->pStartAddress;
+
+           /* Write data to the TX holding register. This will be shifted out at the baud rate by the shift register. */
+           hDevice->pUARTRegs->TX = (uint16_t)pNextData[hDevice->pChannelTx->pFillBuffer->nIndex];
+
+           /* Increment the buffer index. */
+          hDevice->pChannelTx->pFillBuffer->nIndex++;
+
+
+           /* If all of the characters have been transmitted, manage the data buffer. Otherwise we will leave everything
+              as is and continue to transmit this data until everything is out of the buffer. */
+           if(hDevice->pChannelTx->pFillBuffer->nIndex >= hDevice->pChannelTx->pFillBuffer->nCount)
+           {
+                  uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED);
+           }
+    }
+    return;
+}
+
+
+/*
+ * @brief       Function for managing the processed buffer. This gets called after the receive buffer has been filled
+ *              and when the transmit buffer has been emptied.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  pChannel   Channel handler for the Tx or Rx.
+ * @param [in]  eEvent     Indicate the event ID to be passed to registered callback function, if one has been registered.
+ *
+*/
+
+static void uart_ManageProcessedBuffer(ADI_UART_HANDLE hDevice,ADI_UART_DATA_CHANNEL *pChannel, ADI_UART_EVENT eEvent)
+{
+
+
+    /* Now that this transaction has completed, this buffer is no longer in use. */
+    pChannel->pFillBuffer->bInUse = false;
+
+    pChannel->pFillBuffer = pChannel->pFillBuffer->pNextBuffer;
+
+    if(eEvent == ADI_UART_EVENT_TX_BUFFER_PROCESSED)
+    {
+        /* Disable Tx buffer interrupts. */
+        hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ETBEI | BITM_UART_IEN_EDMAT);
+    }
+    else
+    {
+        /* Disable Rx buffer interrupts for the DMA. We do not disable receive buffer full interrupts to allow
+           the use of the RX FIFO.
+        */
+        hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_EDMAR);
+
+        if (hDevice->bRxFifoEn != true)
+        {
+            /* Disable Rx buffer interrupts for PIO mode if the FIFO is not enabled.
+            */
+            hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ERBFI);
+        }
+
+    }
+
+    /* If there is a callback registered, notify the API that a buffer has been processed. Clean up the buffer. */
+    if((hDevice->pfCallback != NULL) && (pChannel->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING))
+    {
+        uint32_t nEvent = hDevice->nHwError;
+        hDevice->nHwError = 0u;
+
+        uint32_t *pBuffer = pChannel->pActiveBuffer->pStartAddress;
+
+        /* Reinitialize the start address to NULL so this buffer can be used for a new transaction. */
+        pChannel->pActiveBuffer->pStartAddress = NULL;
+
+        /* Now that the desired data has either been transmitted or received, this buffer is no longer
+           in use. We can update "pActiveBuffer" to point to the next buffer that will become or is already
+           active.
+        */
+         pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer;
+
+        /* Set the data transfer mode to none so that the next transfer can be either in blocking or in nonblocking mode.
+           This will only be done if there are no other active buffers in flight to avoid disrupting an active transfer.
+        */
+        if(pChannel->pActiveBuffer->pStartAddress == NULL)
+        {
+            pChannel->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE;
+        }
+        if(nEvent != 0u)
+        {
+           hDevice->pfCallback(hDevice->pCBParam, ADI_UART_EVENT_HW_ERROR_DETECTED,(void*)nEvent);
+
+        }
+        else
+        {
+            hDevice->pfCallback(hDevice->pCBParam, (uint32_t)eEvent, (void*)pBuffer);
+        }
+
+    }
+    else
+    {
+        /* Post to the blocking function. If we are in blocking mode, this will allow the buffer to be returned to the API.
+           If we are in nonblocking mode, this will allow adi_uart_GetBuffer() to return immediately so the API can have
+           control over the buffer again.
+        */
+        SEM_POST(pChannel);
+    }
+
+    /* If there is another buffer active. The buffer we want to check is "pFillBuffer" because that is the next one that would
+       be processed. So if it has been submitted, now would be the time to set up the interrupts based on its requirements.
+    */
+    if(pChannel->pFillBuffer->bInUse == true)
+    {
+        pChannel->pfSubmitBuffer(hDevice, pChannel->pFillBuffer);
+    }
+}
+
+
+/*
+ * @brief       Initialize the UART instance to the default values specified in "adi_uart_config.h".
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ * @param [in]  nDeviceNum  UART device number
+*/
+
+static void uart_init(ADI_UART_CONST_HANDLE const hDevice, uint32_t const nDeviceNum)
+{
+
+    ADI_UART_CONFIG const* pUARTCfg = &gUARTCfg[nDeviceNum];
+
+    /* Line Control Register. */
+    hDevice->pUARTRegs->LCR = pUARTCfg->LCR;
+
+    /* Div-C in Baudrate divider register. */
+    hDevice->pUARTRegs->DIV = pUARTCfg->DIV;
+
+    /* Div-M and Div-N in Fractional Baudrate register. */
+    hDevice->pUARTRegs->FBR = pUARTCfg->FBR;
+
+    /* Second line control register. */
+    hDevice->pUARTRegs->LCR2 = pUARTCfg->LCR2;
+
+    /* FIFO control register. */
+    hDevice->pUARTRegs->FCR  = pUARTCfg->FCR;
+
+    /* Half Duplex Control Register. */
+    hDevice->pUARTRegs->RSC  = pUARTCfg->RSC;
+
+    /* Interrupt enable register. */
+    hDevice->pUARTRegs->IEN  = pUARTCfg->IEN;
+}
+
+#ifdef ADI_DEBUG
+/*
+ * @brief       Validate the device handle.
+ *
+ * @param [in]  hDevice    Device handle obtained from adi_uart_Open().
+ *
+ * @return      Status
+ *    - #ADI_UART_SUCCESS          Specified handle is valid.
+ *    - #ADI_UART_INVALID_HANDLE   Specified handle is invalid.
+ *
+*/
+
+static ADI_UART_RESULT ValidateHandle(ADI_UART_CONST_HANDLE hDevice)
+{
+    uint32_t i;
+
+
+    for(i = 0U; i <  ADI_UART_NUM_DEVICES; i++)
+    {
+
+      if((hDevice == uart_device_info[i].hDevice) && (hDevice != NULL))
+       {
+           return(ADI_UART_SUCCESS);
+       }
+    }
+    return(ADI_UART_INVALID_HANDLE);
+}
+#endif /* ADI_DEBUG */
+/*! \endcond */
+/*@}*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart_def.h
new file mode 100755
index 00000000000..0762d9d13ba
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart_def.h
@@ -0,0 +1,214 @@
+/*! *****************************************************************************
+ * @file:    adi_uart_def.h
+ * @brief:   UART Device Driver definition for processor
+ -----------------------------------------------------------------------------
+Copyright (c) 2010-2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+/*! \cond PRIVATE */
+#ifndef DEF_UART_DEF_H
+#define DEF_UART_DEF_H
+
+
+/*!
+ *****************************************************************************
+ * \struct ADI_UART_BUFF_INFO
+ *  Structure for managing the submitted buffers.
+ *****************************************************************************/
+
+typedef struct UART_BUFF_INFO
+{
+    void                      *pStartAddress;             /*!< Address of buffer passed down to the UART driver.    */
+    uint32_t                   nCount;                    /*!< Size of buffer in bytes.                             */
+    uint32_t                   nIndex;                    /*!< Buffer index.                                        */   
+    bool                       bInUse;                    /*!< Buffer in use flag.                                  */
+    bool                       bDMA;                      /*!< Transaction is using the DMA flag.                   */
+    struct UART_BUFF_INFO     *pNextBuffer;               /*!< Pointer to the next buffer in the list.              */
+
+
+}ADI_UART_BUFF_INFO;
+
+
+/*! Function pointer typedef for the function which  submit the buffer */
+typedef void (*UART_BUFFER_SUBMIT) (ADI_UART_CONST_HANDLE  const hDevice,
+                                    ADI_UART_BUFF_INFO    *const pBuffer
+                                    );
+
+
+/*!
+ *****************************************************************************
+ * \struct ADI_UART_DATA_CHANNEL
+ *  Structure to manage the data transfer for a given channel.
+ *  One instance of this  structure will be created for managing the
+ *  data transfer in each direction.
+ *****************************************************************************/
+ 
+typedef struct _ADI_UART_DATA_CHANNEL
+{ 
+    ADI_UART_BUFF_INFO        PingPong[2];       /*!< Ping Pong Buffers.                                            */
+    ADI_UART_BUFF_INFO       *pFreeBuffer;       /*!< Pointer to free buffer (next buffer to submit).               */  
+    ADI_UART_BUFF_INFO       *pFillBuffer;       /*!< Pointer to the next buffer to be filled. This is needed for 
+                                                      the case where two buffers are "submitted" before a "get" is 
+                                                      called.                                                       */
+    ADI_UART_BUFF_INFO       *pActiveBuffer;     /*!< Pointer to active buffer (next buffer waiting for completion).*/
+    ADI_UART_TRANSFER_MODE    eDataTranferMode;  /*!< Data transfer mode.                                           */ 
+    UART_BUFFER_SUBMIT        pfSubmitBuffer;    /*!< Pointer to a function used for submitting a buffer.           */
+    SEM_VAR_DECLR                               
+
+}ADI_UART_DATA_CHANNEL;
+
+
+/*!
+ *****************************************************************************
+ * \struct  ADI_UART_DEVICE_INFO
+ *  Structure for storing basic device information.
+ *****************************************************************************/
+
+typedef struct _ADI_UART_DEVICE_INFO
+{
+    DMA_CHANn_TypeDef      dmaTxChannelNum;    /*!<  DMA channel ID-Tx.                  */       
+    DMA_CHANn_TypeDef      dmaRxChannelNum;    /*!<  DMA channel ID-Rx.                  */   
+    IRQn_Type              eDMATx;             /*!<  DMA channel IRQ-Tx.                 */       
+    IRQn_Type              eDMARx;             /*!<  DMA channel IRQ-Rx.                 */  
+    IRQn_Type              eIRQn;              /*!<  UART interrupt ID.                  */   
+    ADI_UART_TypeDef      *pUartRegs;          /*!<  Base address of the UART registers. */       
+    ADI_UART_HANDLE        hDevice;            /*!<  Handle for the device instance.     */
+
+}ADI_UART_DEVICE_INFO;
+
+
+/*!
+ *****************************************************************************
+ * \struct  ADI_UART_DEVICE
+ *  Structure for managing the UART device. 
+ *****************************************************************************/
+
+typedef struct _ADI_UART_DEVICE
+{
+    ADI_UART_DIRECTION          eDirection;           /*!< UART operation direction.                                       */
+    ADI_UART_DEVICE_INFO       *pUartInfo;            /*!< Access to device information about the uart instance.           */
+    volatile ADI_UART_TypeDef  *pUARTRegs;            /*!< Access to UART Memory Mapped Registers.                         */     
+    ADI_CALLBACK                pfCallback;           /*!< Callback function.                                              */
+    void                       *pCBParam;             /*!< Parameter for callback function.                                */
+    bool                        bAutobaudInProgress;  /*!< Autobaud in progress flag.                                      */   
+    volatile uint32_t           nHwError;             /*!< Line status error(s).                                           */
+    volatile uint32_t           nAutobaudError;       /*!< Autobaud error(s).                                              */         
+    ADI_UART_DATA_CHANNEL      *pChannelTx;           /*!< Tx channel.                                                     */    
+    ADI_UART_DATA_CHANNEL      *pChannelRx;           /*!< Rx channel.                                                     */
+    volatile uint32_t           nBaudRate;            /*!< Baudrate.                                                       */
+    bool                        bAutobaudCallbackMode;/*!< Autobaud detection is using callback mode flag.                 */
+    bool                        bRxFifoEn;            /*!< Rx FIFO enabled. Rx buffer full interrupts will remain enabled. */
+     
+} ADI_UART_DEVICE;
+
+
+/*!
+ *****************************************************************************
+ * \struct  ADI_UART_CONFIG
+ *  Structure for initializing the static config.
+ *****************************************************************************/
+
+typedef struct _ADI_UART_CONFIG
+{
+    uint16_t                    LCR;                 /*!< UART_COMLCR Register. */    
+
+    uint16_t                    DIV;                 /*!< UART_COMDIV Register. */ 
+
+    uint16_t                    FBR;                 /*!< UART_COMFBR Register. */ 
+
+    uint16_t                    LCR2;                /*!< UART_COMLCR2 Register.*/ 
+
+    uint16_t                    FCR;                 /*!< UART_COMFCR Register. */ 
+
+    uint16_t                    RSC;                 /*!< UART_COMRSC Register. */              
+
+    uint16_t                    IEN;                 /*!< UART_COMIEN Register .*/ 
+
+} ADI_UART_CONFIG;
+
+
+/******************************************************************************
+ * UART Device internal API function prototypes
+ *****************************************************************************/
+
+/*
+ * UART device initialization helper function.
+*/
+static void uart_init(ADI_UART_CONST_HANDLE const hDevice, uint32_t const nDeviceNum);
+
+
+/*
+ * Data transfer helper functions.
+*/
+static void uart_submittxbuffer(ADI_UART_CONST_HANDLE const hDevice, ADI_UART_BUFF_INFO *const pBuffer);
+
+static void uart_submitrxbuffer(ADI_UART_CONST_HANDLE const hDevice, ADI_UART_BUFF_INFO *const pBuffer);
+
+
+/*
+ * Data management helper functions.
+*/
+static ADI_UART_RESULT uart_getbuffer(ADI_UART_HANDLE hDevice, ADI_UART_DATA_CHANNEL *pChannel, void **ppBuffer, uint32_t *pHwError);
+
+static ADI_UART_RESULT uart_PendForBuffer(ADI_UART_HANDLE const hDevice , ADI_UART_DATA_CHANNEL *pChannel, uint32_t *pHwError);
+
+static void uart_ManageProcessedBuffer(ADI_UART_HANDLE hDevice, ADI_UART_DATA_CHANNEL *pChannel, ADI_UART_EVENT eEvent);
+
+static void uart_TxDataHandler(ADI_UART_HANDLE hDevice);
+
+static void uart_RxDataHandler(ADI_UART_HANDLE hDevice);
+
+
+/* 
+ * Interrupt Handler.
+*/
+static void Common_Uart_Interrupt_Handler(ADI_UART_HANDLE hDevice);
+
+
+/* 
+ * Handle Validation function
+*/
+#ifdef ADI_DEBUG
+static ADI_UART_RESULT  ValidateHandle(ADI_UART_CONST_HANDLE hDevice);
+#endif /* ADI_DEBUG */
+
+#endif  /* end of ifndef DEF_UART_DEF_H */
+/*! \endcond */
+
+
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/wdt/adi_wdt.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/wdt/adi_wdt.c
new file mode 100755
index 00000000000..b2f34894a25
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/wdt/adi_wdt.c
@@ -0,0 +1,225 @@
+/*! *****************************************************************************
+ * @file    adi_wdt.c
+ * @brief   WDT device driver implementation
+ -----------------------------------------------------------------------------
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+*
+* Pm011 (rule 6.3): the basic types of char, int, short, long, float, and double should not be used
+*   Necessary for stdbool.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+*
+* Pm140 (Rule 11.4): a cast should not be performed between a pointer type and an integral type
+*   This violation appears when deferencing the pointer to the register typedef. No way around this.
+*/
+#pragma diag_suppress=Pm011,Pm073,Pm140,Pm143
+#endif /* __ICCARM__ */
+
+
+/** @addtogroup WDT_Driver WDT Driver
+ *  @{
+ * @brief Watchdog Timer (WDT) Driver
+ * @details The watchdog timer driver allows the user to enable the timer with
+ * the static configuration parameters, reset the timer, and read the timer
+ * count.  No interface is provided for setting the timer parameters are
+ * runtime since the WDT may only be configured once for the program lifetime.
+ * The timer is disabled by default by the ADuCM4x50 boot kernel.
+ * @note The application must include drivers/wdt/adi_wdt.h to use this driver
+ */
+
+#include <stdlib.h>
+#include <adi_processor.h>
+#include <rtos_map/adi_rtos_map.h>
+#include <adi_wdt_config.h>
+#include <drivers/wdt/adi_wdt.h>
+
+/*! \cond PRIVATE */
+
+/*! Bus synchronization bits that must go low before writing to the CTL or RESET registers */
+#define ADI_WDT_SYNC_BITS ((0x1u << BITP_WDT_STAT_COUNTING) | (0x1u << BITP_WDT_STAT_LOADING) | (0x1u << BITP_WDT_STAT_CLRIRQ))
+
+/*! Value that is written to the reset register to kick the dog */
+#define ADI_WDT_CLR_VALUE (0xCCCCu)
+
+/*! Store the callback locally if we are using interrupt mode */
+#if (ADI_WDT_CONTROL_TIMEOUT_MODE == 1u)
+static ADI_CALLBACK gAppCallback;
+#endif
+
+/*! \endcond */
+
+/*********************************************************************************
+                                    API IMPLEMENTATIONS 
+*********************************************************************************/
+
+
+/*!
+ * @brief      WDT Enable
+ *
+ * @details    Enables/disables the WDT with the paramters supplied in adi_wdt_config.h
+ *
+ * @param [in] bEnable    : True to turn WDT on, false to turn it off
+ *
+ * @param [in] pfCallback : If interrupt mode is enabled, specify application callback function,
+ *                          otherwise simply pass NULL for the argument.
+ *
+ * @return     ADI_WDT_RESULT
+ *                - #ADI_WDT_FAILURE_LOCKED           WDT has already been initialized
+ *                - #ADI_WDT_SUCCESS                  Function call completed successfully
+ */
+ADI_WDT_RESULT adi_wdt_Enable(bool const bEnable, ADI_CALLBACK const pfCallback) {
+    /* IF(Device is enabled, application can't modify it) */
+    if ((pADI_WDT0->STAT & ((uint16_t) BITM_WDT_STAT_LOCKED)) != ((uint16_t) 0x0u)) {
+        return ADI_WDT_FAILURE_LOCKED;
+    } /* ENDIF */
+
+    /* Setup interrupts if we are in interrupt mode */
+#if (ADI_WDT_CONTROL_TIMEOUT_MODE == 1u)
+    gAppCallback = pfCallback;
+    /* IF(We are enabling the WDT) */
+    if (bEnable == true) {
+        NVIC_EnableIRQ (WDT_EXP_IRQn);
+    /* ELSE (We are disabling the WDT, this might not be necessary, depends on startup config) */
+    } else {
+        NVIC_DisableIRQ(WDT_EXP_IRQn);
+    } /* ENDIF */
+#endif
+
+    /* WHILE(Bus sync is underway) */
+    while((pADI_WDT0->STAT & ADI_WDT_SYNC_BITS) != 0u) {
+        ;
+    } /* ENDWHILE */
+
+
+    ADI_INT_STATUS_ALLOC();
+    ADI_ENTER_CRITICAL_REGION();
+
+    pADI_WDT0->LOAD = ADI_WDT_LOAD_VALUE;
+
+    /* IF(Turning the WDT on) */
+    if (bEnable == true) {
+        pADI_WDT0->CTL  = (ADI_WDT_CONTROL_TIMER_MODE      << BITP_WDT_CTL_MODE) |
+                          (0x1u                            << BITP_WDT_CTL_EN  ) |
+                          (ADI_WDT_CONTROL_CLOCK_PRESCALER << BITP_WDT_CTL_PRE ) |
+                          (ADI_WDT_CONTROL_TIMEOUT_MODE    << BITP_WDT_CTL_IRQ ) |
+                          (ADI_WDT_CONTROL_POWER_MODE      <<               0u );
+    /* ELSE(Turning the WDT off) */
+    } else {
+        pADI_WDT0->CTL  = (ADI_WDT_CONTROL_TIMER_MODE      << BITP_WDT_CTL_MODE) |
+                          (0x0u                            << BITP_WDT_CTL_EN  ) |
+                          (ADI_WDT_CONTROL_CLOCK_PRESCALER << BITP_WDT_CTL_PRE ) |
+                          (ADI_WDT_CONTROL_TIMEOUT_MODE    << BITP_WDT_CTL_IRQ ) |
+                          (ADI_WDT_CONTROL_POWER_MODE      <<               0u );
+    } /* ENDIF */
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    return ADI_WDT_SUCCESS;
+}
+
+/*!
+ * @brief      WDT Reset
+ *
+ * @details    Resets the WDT
+ *
+ * @return     None
+ */
+void adi_wdt_Kick(void) {
+    /* WHILE(Bus sync is underway) */
+    while((pADI_WDT0->STAT & ADI_WDT_SYNC_BITS) != 0u) {
+        ;
+    } /* ENDWHILE */
+
+   /* Kick the dog! */
+    pADI_WDT0->RESTART = ADI_WDT_CLR_VALUE;
+}
+
+/*!
+ * @brief       WDT Read Count
+ *
+ * @details     Read the current WDT count
+ *
+ * @param [out] pCurCount : Pointer to memory to read the count into
+ *
+ * @return      None
+ */
+void adi_wdt_GetCount(uint16_t * const pCurCount) {
+    /* Read the count */
+    *pCurCount = pADI_WDT0->CCNT;
+}
+
+/*! \cond PRIVATE */
+
+/*!
+ * @brief     WDT0 Interrupt Handler
+ *
+ * @details   Kicks the dog and calls the user supplied callback function
+ *
+ * @return    None
+ *
+ * @note      Do not need to explicitly clear the interrupt status,
+ *            kicking the dog performs this action.
+ */
+#if (ADI_WDT_CONTROL_TIMEOUT_MODE == 1u)
+extern void WDog_Tmr_Int_Handler(void); 
+void WDog_Tmr_Int_Handler(void) {
+    ISR_PROLOG()
+    /* Kick the dog  */
+    adi_wdt_Kick();
+    /* IF(Application supplied a callback) */
+    if(gAppCallback != NULL) {
+        /* Call the callback */
+        gAppCallback(NULL, 0x0u, NULL);
+    } /* ENDIF */
+    ISR_EPILOG()
+}
+#endif /* (ADI_WDT_CONTROL_TIMEOUT_MODE == 1u) */
+
+/*! \endcond */
+
+/*! @} */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/xint/adi_xint.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/xint/adi_xint.c
new file mode 100755
index 00000000000..53e763cb70b
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/xint/adi_xint.c
@@ -0,0 +1,413 @@
+/******************************************************************************
+   @file:    adi_xint.c
+   @brief:   External Interrupt device driver implementation.
+  -----------------------------------------------------------------------------
+
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+/*****************************************************************************/
+
+#include <stddef.h>
+#include <string.h>
+#include <assert.h>
+#include <drivers/xint/adi_xint.h>
+#include <rtos_map/adi_rtos_map.h>
+#include "adi_xint_def.h"
+
+#ifdef __ICCARM__
+/*
+* IAR MISRA C 2004 error suppressions.
+*
+* Pm073 (rule 14.7): a function should have a single point of exit
+* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function
+*   Multiple returns are used for error handling.
+* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type
+*   The rule makes an exception for memory-mapped register accesses.
+* Pm140 (rule 10.3): illegal explicit conversion from underlying MISRA type unsigned int to enum
+*   The typecast is used for efficiency of the code.
+* Pm140 (rule 17.4): array indexing shall only be applied to objects defined as an array
+*   Array indexing is required on the pointer. The memory for gpCallbackTable is passed from application
+*/
+#pragma diag_suppress=Pm073,Pm143,Pm140,Pm136,Pm152
+#endif /* __ICCARM__ */
+
+static inline void XIntCommonInterruptHandler  (const ADI_XINT_EVENT eEvent);
+void Ext_Int0_Handler(void);
+void Ext_Int1_Handler(void);
+void Ext_Int2_Handler(void);
+void Ext_Int3_Handler(void);
+
+
+
+/*==========  D A T A  ==========*/
+
+static ADI_XINT_CALLBACK_INFO *gpCallbackTable;
+
+/*! \endcond */
+
+/*! \addtogroup XINT_Driver External Interrupt Driver
+ *  @{
+ *  @brief External Interrupt (XINT) Driver
+ *  @note The application must include drivers/xint/adi_xint.h to use this driver
+ */
+
+/*!
+    @brief      Initializes the External Interrupt Driver.
+
+    @details    This function does the external interrupt driver initialization. This function should be called
+                before calling any of the XINT driver APIs.
+
+    @param[in] pMemory      Pointer to the memory to be used by the driver.
+                            Size of the memory should be at equal to #ADI_XINT_MEMORY_SIZE bytes.
+    @param[in] MemorySize   Size of the memory passed in pMemory parameter.
+
+    @return     Status
+                    - ADI_XINT_SUCCESS                  If successfully initialized XINT driver.
+                    - ADI_XINT_NULL_PARAMETER       [D] If the given pointer to the driver memory is pointing to NULL.
+                    - ADI_XINT_INVALID_MEMORY_SIZE  [D] If the given memory size is not sufficient to operate the driver.
+
+    @sa         adi_xint_UnInit
+*/
+ADI_XINT_RESULT adi_xint_Init(void*                const pMemory,
+                              uint32_t             const MemorySize
+)
+{
+
+#ifdef ADI_DEBUG
+        /* Verify the given memory pointer */
+        if(NULL == pMemory)
+        {
+            return ADI_XINT_NULL_PARAMETER;
+        }
+        /* Check if the memory size is sufficient to operate the driver */
+        if(MemorySize < ADI_XINT_MEMORY_SIZE)
+        {
+            return ADI_XINT_INVALID_MEMORY_SIZE;
+        }
+        assert(MemorySize == (sizeof(ADI_XINT_CALLBACK_INFO) * ADI_XINT_EVENT_MAX));
+#endif
+
+    /* Only initialize on 1st init call, i.e., preserve callbacks on multiple inits */
+    if (gpCallbackTable == NULL)
+    {
+        /* Clear the memory passed by the application */
+        memset(pMemory, 0, MemorySize);
+
+        gpCallbackTable = (ADI_XINT_CALLBACK_INFO *)pMemory;
+    }
+    return (ADI_XINT_SUCCESS);
+}
+
+
+/*!
+    @brief      Un-initialize the external interrupt driver.
+
+    @details    Terminates the XINT functions, leaving everything unchanged.
+
+    @return     Status
+                    - #ADI_XINT_SUCCESS             If successfully uninitialized XINT driver.
+                    - #ADI_XINT_NOT_INITIALIZED [D] If XINT driver not yet initialized.
+
+    @sa         adi_xint_Init
+*/
+ADI_XINT_RESULT adi_xint_UnInit(void)
+{
+
+#ifdef ADI_DEBUG
+    /* IF (not initialized) */
+    if (NULL == gpCallbackTable)
+    {
+        /* return error if not initialized */
+        return (ADI_XINT_NOT_INITIALIZED);
+    }
+#endif
+
+    /* Clear the callback pointer */
+    gpCallbackTable = NULL;
+
+    return (ADI_XINT_SUCCESS);
+}
+
+
+
+/*!
+    @brief      Enable an External Interrupt
+
+    @details    Enables and sets the triggering mode for the given external interrupt.
+                Applications may register a callback using the #adi_xint_RegisterCallback
+                API to get a notification when the interrupt occurs.
+
+                To get the external interrupt working application has to enable the input
+                (using the GPIO driver API \a adi_gpio_InputEnable) for the corresponding GPIO
+                pin. Please refer the GPIO chapter pin-muxing section of the Hardware Reference
+                Manual to see the GPIO pin that is mapped to the required external interrupt.
+
+    @param[in]  eEvent      Event which needs to be enabled.
+    @param[in]  eMode       Interrupt trigger mode for the external interrupt.
+
+    @return     Status
+                    - #ADI_XINT_SUCCESS             If successfully enabled the external interrupt.
+                    - #ADI_XINT_NOT_INITIALIZED [D] If external interrupt driver not yet initialized.
+
+    @sa         adi_xint_DisableIRQ
+    @sa         adi_xint_RegisterCallback
+*/
+ADI_XINT_RESULT adi_xint_EnableIRQ(const ADI_XINT_EVENT eEvent, const ADI_XINT_IRQ_MODE eMode)
+{
+    uint32_t            Mask;       /* mask to manipulate the register */
+    uint32_t            Pattern;    /* bit pattern that will be written into the register */
+    uint32_t            CfgReg;     /* interrupt config register value */
+    IRQn_Type           XintIrq;
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == gpCallbackTable)
+    {
+        return (ADI_XINT_NOT_INITIALIZED);
+    }
+#endif
+
+    /* create the mask we'll use to clear the relevant bits in the config register */
+    Mask = (BITM_XINT_CFG0_IRQ0MDE | BITM_XINT_CFG0_IRQ0EN) << (ADI_XINT_CFG_BITS * (uint32_t)eEvent);
+
+    /* The Pattern has to be created differently for UART RX wakeup and other events as the
+       mode and enable bits are flipped in case of UART RX */
+    
+    /* Based on the event figure out the interrupt it is mapped to */
+    if(eEvent == ADI_XINT_EVENT_UART_RX)
+    {
+        /* create the bit pattern we're going to write into the configuration register */
+        Pattern = (BITM_XINT_CFG0_UART_RX_EN | ((uint32_t)eMode << BITP_XINT_CFG0_UART_RX_MDE));
+        
+        XintIrq = XINT_EVT3_IRQn;
+    }
+    else
+    {
+        /* create the bit pattern we're going to write into the configuration register */
+        Pattern = (BITM_XINT_CFG0_IRQ0EN | eMode) << (ADI_XINT_CFG_BITS * (uint32_t)eEvent);
+        
+        XintIrq = (IRQn_Type)((uint32_t)XINT_EVT0_IRQn + (uint32_t)eEvent);
+    }
+
+    
+    ADI_ENTER_CRITICAL_REGION();
+
+    /* read/modify/write the appropriate bits in the register */
+    CfgReg = pADI_XINT0->CFG0;
+    CfgReg &= ~Mask;
+    CfgReg |= Pattern;
+    pADI_XINT0->CFG0 = CfgReg;
+
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* enable the interrupt */
+    NVIC_EnableIRQ(XintIrq);
+
+    return (ADI_XINT_SUCCESS);
+}
+
+
+/*!
+    @brief      Disable an External Interrupt
+
+    @details    Disables an external interrupt
+
+    @param[in]  eEvent  External Interrupt event that should be disabled.
+
+    @return     Status
+                    - #ADI_XINT_SUCCESS             If successfully disabled the external interrupt.
+                    - #ADI_XINT_NOT_INITIALIZED [D] If external interrupt driver is not yet initialized.
+
+    @sa         adi_xint_EnableIRQ
+    @sa         adi_xint_RegisterCallback
+*/
+ADI_XINT_RESULT adi_xint_DisableIRQ(const ADI_XINT_EVENT eEvent)
+{
+    uint32_t            Mask;       /* mask to manipulate the register */
+    uint32_t            CfgReg;     /* interrupt config register value */
+    IRQn_Type           XintIrq;    /* External interrupt IRQ the event is mapped to */
+
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == gpCallbackTable)
+    {
+        return (ADI_XINT_NOT_INITIALIZED);
+    }
+#endif
+
+    /* Based on the event figure out the interrupt it is mapped to */
+    if(eEvent == ADI_XINT_EVENT_UART_RX)
+    {
+        XintIrq = XINT_EVT3_IRQn;
+    }
+    else
+    {
+        XintIrq = (IRQn_Type)((uint32_t)XINT_EVT0_IRQn + (uint32_t)eEvent);
+    }
+
+    /* disable the interrupt */
+    NVIC_DisableIRQ(XintIrq);
+
+    /* create the mask we'll use to clear the relevant bits in the config register */
+    Mask = (BITM_XINT_CFG0_IRQ0MDE | BITM_XINT_CFG0_IRQ0EN) << (ADI_XINT_CFG_BITS * (uint32_t)eEvent);
+
+    ADI_ENTER_CRITICAL_REGION();
+    /* read/modify/write the appropriate bits in the register */
+    CfgReg = pADI_XINT0->CFG0;
+    CfgReg &= ~Mask;
+    pADI_XINT0->CFG0 = CfgReg;
+    ADI_EXIT_CRITICAL_REGION();
+
+    return (ADI_XINT_SUCCESS);
+}
+
+
+/*!
+    @brief      Register or unregister an application callback function for external pin interrupts.
+
+    @details    Applications may register a callback function that will be called when an
+                external interrupt occurs. In addition to registering the interrupt,
+                the application should call the #adi_xint_EnableIRQ API to enable the
+                external pin interrupt.
+
+                The driver dispatches calls to registered callback functions when the
+                properly configured pin(s) latches an external interrupt input on the XINT
+                pin(s).  The callback is dispatched with the following parameters, respectively:
+
+                - application-provided callback parameter (\a pCBParam),
+                - the interrupt ID (#ADI_XINT_EVENT) that initiated the interrupt,
+                - NULL.
+
+    @param[in]  eEvent          The interrupt for which the callback is being registered.
+    @param[in]  pfCallback      Pointer to the callback function. This can be passed as NULL to
+                                unregister the callback.
+    @param[in]  pCBParam        Callback parameter which will be passed back to the application
+                                when the callback is called..
+
+    @return     Status
+                    - #ADI_XINT_SUCCESS                 If successfully registered the callback.
+                    - #ADI_XINT_NOT_INITIALIZED     [D] If external interrupt driver is not yet initialized.
+
+    @sa         adi_xint_EnableIRQ
+    @sa         adi_xint_DisableIRQ
+*/
+ADI_XINT_RESULT  adi_xint_RegisterCallback (const ADI_XINT_EVENT eEvent, ADI_CALLBACK const pfCallback, void *const pCBParam )
+{
+    ADI_INT_STATUS_ALLOC();
+
+#ifdef ADI_DEBUG
+    /* make sure we're initialized */
+    if (NULL == gpCallbackTable)
+    {
+        return (ADI_XINT_NOT_INITIALIZED);
+    }
+#endif
+
+    ADI_ENTER_CRITICAL_REGION();
+    gpCallbackTable[eEvent].pfCallback  = pfCallback;
+    gpCallbackTable[eEvent].pCBParam    = pCBParam;
+    ADI_EXIT_CRITICAL_REGION();
+
+    /* return the status */
+    return (ADI_XINT_SUCCESS);
+}
+
+/*@}*/
+
+/*! \cond PRIVATE */
+/* All of the following is excluded from the doxygen output... */
+
+/* Common external interrupt handler */
+static inline void XIntCommonInterruptHandler(const ADI_XINT_EVENT eEvent)
+{
+    /* Clear the IRQ */
+    pADI_XINT0->CLR = (1u << (uint32_t)eEvent);
+
+    /* params list is: application-registered cbParam, Event ID, and NULL */
+    if(gpCallbackTable[eEvent].pfCallback != NULL)
+    {
+        gpCallbackTable[eEvent].pfCallback (gpCallbackTable[eEvent].pCBParam, (uint32_t) eEvent, NULL);
+    }
+}
+
+/* strongly-bound interrupt handlers to override the default weak bindings */
+void Ext_Int0_Handler(void)
+{
+    ISR_PROLOG()
+    XIntCommonInterruptHandler(ADI_XINT_EVENT_INT0);
+    ISR_EPILOG()
+}
+
+void Ext_Int1_Handler(void)
+{
+    ISR_PROLOG()
+    XIntCommonInterruptHandler(ADI_XINT_EVENT_INT1);
+    ISR_EPILOG()
+}
+
+void Ext_Int2_Handler(void)
+{
+    ISR_PROLOG()
+    XIntCommonInterruptHandler(ADI_XINT_EVENT_INT2);
+    ISR_EPILOG()
+
+}
+
+void Ext_Int3_Handler(void)
+{
+    ISR_PROLOG()
+    if((pADI_XINT0->EXT_STAT & BITM_XINT_EXT_STAT_STAT_UART_RXWKUP)==BITM_XINT_EXT_STAT_STAT_UART_RXWKUP)
+    {
+       XIntCommonInterruptHandler(ADI_XINT_EVENT_UART_RX);
+    }
+    else
+    {
+       XIntCommonInterruptHandler(ADI_XINT_EVENT_INT3);
+    }
+    ISR_EPILOG()
+}
+
+/*! \endcond */
+
+/*
+** EOF
+*/
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/xint/adi_xint_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/xint/adi_xint_def.h
new file mode 100755
index 00000000000..205602215cd
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/xint/adi_xint_def.h
@@ -0,0 +1,61 @@
+/*!
+ *****************************************************************************
+ * @file:    adi_xint_def.h
+ * @brief:   External Interrupt Driver definition
+ *****************************************************************************
+Copyright (c) 2016 Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+  - Redistributions of source code must retain the above copyright notice,
+    this list of conditions and the following disclaimer.
+  - Redistributions in binary form must reproduce the above copyright notice,
+    this list of conditions and the following disclaimer in the documentation
+    and/or other materials provided with the distribution.
+  - Modified versions of the software must be conspicuously marked as such.
+  - This software is licensed solely and exclusively for use with processors
+    manufactured by or for Analog Devices, Inc.
+  - This software may not be combined or merged with other code in any manner
+    that would cause the software to become subject to terms and conditions
+    which differ from those listed here.
+  - Neither the name of Analog Devices, Inc. nor the names of its
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+  - The use of this software may or may not infringe the patent rights of one
+    or more patent holders.  This license does not release you from the
+    requirement that you obtain separate licenses from these patent holders
+    to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-
+INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF
+CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*****************************************************************************/
+#ifndef ADI_XINT_DEF_H
+#define ADI_XINT_DEF_H
+/*! \cond PRIVATE */
+
+/* General macros */
+#define ADI_XINT_CFG_BITS       (4u)       /*!< number of bits for each external interrupt configuration */
+
+/*! Structure to hold callback function and parameter */
+typedef struct _ADI_XINT_CALLBACK_INFO
+{
+    ADI_CALLBACK         pfCallback;        /*!< Callback function pointer */
+    void                 *pCBParam;         /*!< Callback parameter */
+} ADI_XINT_CALLBACK_INFO;
+
+
+/*! \endcond */
+#endif /* ADI_XINT_DEF_H */
diff --git a/targets/TARGET_Analog_Devices/mbed_rtx.h b/targets/TARGET_Analog_Devices/mbed_rtx.h
new file mode 100755
index 00000000000..04f126e9a09
--- /dev/null
+++ b/targets/TARGET_Analog_Devices/mbed_rtx.h
@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_MBED_RTX_H
+#define MBED_MBED_RTX_H
+
+#if defined(TARGET_EV_COG_AD3029LZ)
+
+#ifndef INITIAL_SP
+#define INITIAL_SP              (0x20004000UL)
+#endif
+#ifndef OS_CLOCK
+#define OS_CLOCK                26000000
+#endif
+
+#elif defined(TARGET_EV_COG_AD4050LZ)
+
+#ifndef INITIAL_SP
+#define INITIAL_SP              (0x20048000UL)
+#endif
+#ifndef OS_CLOCK
+#define OS_CLOCK                26000000
+#endif
+
+#endif
+
+#endif  // MBED_MBED_RTX_H
diff --git a/targets/TARGET_Freescale/TARGET_K20XX/rtc_api.c b/targets/TARGET_Freescale/TARGET_K20XX/rtc_api.c
index d7dd1c8050c..8e891a2f25c 100644
--- a/targets/TARGET_Freescale/TARGET_K20XX/rtc_api.c
+++ b/targets/TARGET_Freescale/TARGET_K20XX/rtc_api.c
@@ -29,14 +29,14 @@ static void init(void) {
 
 void rtc_init(void) {
     init();
-    
+
     // Enable the oscillator
 #if defined (TARGET_K20D50M)
     RTC->CR |= RTC_CR_OSCE_MASK;
 #else
     // Teensy3.1 requires 20pF MCU loading capacitors for 32KHz RTC oscillator
     /* RTC->CR: SC2P=0,SC4P=1,SC8P=0,SC16P=1,CLKO=0,OSCE=1,UM=0,SUP=0,SPE=0,SWR=0 */
-    RTC->CR |= RTC_CR_OSCE_MASK |RTC_CR_SC16P_MASK | RTC_CR_SC4P_MASK; 
+    RTC->CR |= RTC_CR_OSCE_MASK |RTC_CR_SC16P_MASK | RTC_CR_SC4P_MASK;
 #endif
 
     //Configure the TSR. default value: 1
@@ -78,11 +78,6 @@ void rtc_write(time_t t) {
     // disable counter
     RTC->SR &= ~RTC_SR_TCE_MASK;
 
-    // we do not write 0 into TSR
-    // to avoid invalid time
-    if (t == 0)
-        t = 1;
-
     // write seconds
     RTC->TSR = t;
 
diff --git a/targets/TARGET_Freescale/TARGET_KLXX/rtc_api.c b/targets/TARGET_Freescale/TARGET_KLXX/rtc_api.c
index 987f76f1687..4832258f89d 100644
--- a/targets/TARGET_Freescale/TARGET_KLXX/rtc_api.c
+++ b/targets/TARGET_Freescale/TARGET_KLXX/rtc_api.c
@@ -26,7 +26,7 @@ static void init(void) {
 
     // select RTC clock source
     SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
-    
+
     // Enable external crystal source if clock source is 32KHz
     if (extosc_frequency()==32768) {
         SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(OSC32KCLK);
@@ -104,11 +104,6 @@ void rtc_write(time_t t) {
     // disable counter
     RTC->SR &= ~RTC_SR_TCE_MASK;
 
-    // we do not write 0 into TSR
-    // to avoid invalid time
-    if (t == 0)
-        t = 1;
-
     // write seconds
     RTC->TSR = t;
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_clock_config.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_clock_config.c
old mode 100644
new mode 100755
index 93d47c7f502..d053db788a1
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_clock_config.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_clock_config.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -28,154 +28,6 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "fsl_common.h"
-#include "fsl_smc.h"
-#include "fsl_clock_config.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-/*! @brief Clock configuration structure. */
-typedef struct _clock_config
-{
-    mcg_config_t mcgConfig;       /*!< MCG configuration.      */
-    sim_clock_config_t simConfig; /*!< SIM configuration.      */
-    osc_config_t oscConfig;       /*!< OSC configuration.      */
-    uint32_t coreClock;           /*!< core clock frequency.   */
-} clock_config_t;
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/* System clock frequency. */
-extern uint32_t SystemCoreClock;
-
-/* Configuration for enter VLPR mode. Core clock = 4MHz. */
-const clock_config_t g_defaultClockConfigVlpr = {
-    .mcgConfig =
-        {
-            .mcgMode = kMCG_ModeBLPI,            /* Work in BLPI mode. */
-            .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable.   */
-            .ircs = kMCG_IrcFast,                /* Select IRC4M.      */
-            .fcrdiv = 0U,                        /* FCRDIV is 0.*/
-
-            .frdiv = 0U,
-            .drs = kMCG_DrsLow,         /* Low frequency range */
-            .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
-            .oscsel = kMCG_OscselOsc,   /* Select OSC */
-
-            .pll0Config =
-                {
-                    .enableMode = 0U, /* Don't enable PLL. */
-                    .prdiv = 0U,
-                    .vdiv = 0U,
-                },
-            .pllcs = kMCG_PllClkSelPll0,
-        },
-    .simConfig =
-        {
-            .pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */
-            .pllFllDiv = 0U,
-            .pllFllFrac = 0U,
-            .er32kSrc = 2U,         /* ERCLK32K selection, use RTC. */
-            .clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */
-        },
-    .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
-                  .capLoad = 0U,
-                  .workMode = kOSC_ModeOscLowPower,
-                  .oscerConfig =
-                      {
-                          .enableMode = kOSC_ErClkEnable,
-#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
-                          .erclkDiv = 0U,
-#endif
-                      }},
-    .coreClock = 4000000U, /* Core clock frequency */
-};
-
-/* Configuration for enter RUN mode. Core clock = 120MHz. */
-const clock_config_t g_defaultClockConfigRun = {
-    .mcgConfig =
-        {
-            .mcgMode = kMCG_ModePEE,             /* Work in PEE mode. */
-            .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
-            .ircs = kMCG_IrcSlow,                /* Select IRC32k. */
-            .fcrdiv = 0U,                        /* FCRDIV is 0. */
-
-            .frdiv = 4U,
-            .drs = kMCG_DrsLow,         /* Low frequency range */
-            .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
-            .oscsel = kMCG_OscselOsc,   /* Select OSC */
-
-            .pll0Config =
-                {
-                    .enableMode = 0U, .prdiv = 0x00U, .vdiv = 0x04U,
-                },
-            .pllcs = kMCG_PllClkSelPll0,
-        },
-    .simConfig =
-        {
-            .pllFllSel = 1U, /* PLLFLLSEL select PLL. */
-            .pllFllDiv = 0U,
-            .pllFllFrac = 0U,
-            .er32kSrc = 2U,         /* ERCLK32K selection, use RTC. */
-            .clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */
-        },
-    .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
-                  .capLoad = 0,
-                  .workMode = kOSC_ModeOscLowPower,
-                  .oscerConfig =
-                      {
-                          .enableMode = kOSC_ErClkEnable,
-#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
-                          .erclkDiv = 0U,
-#endif
-                      }},
-    .coreClock = 120000000U, /* Core clock frequency */
-};
-
-/* Configuration for HSRUN mode. Core clock = 180MHz. */
-const clock_config_t g_defaultClockConfigHsrun = {
-    .mcgConfig =
-        {
-            .mcgMode = kMCG_ModePEE,                   /* Work in PEE mode. */
-            .irclkEnableMode = kMCG_IrclkEnableInStop, /* MCGIRCLK enable. */
-            .ircs = kMCG_IrcSlow,                      /* Select IRC32k.*/
-            .fcrdiv = 0U,                              /* FCRDIV is 0. */
-
-            .frdiv = 4U,
-            .drs = kMCG_DrsLow,         /* Low frequency range. */
-            .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
-            .oscsel = kMCG_OscselOsc,   /* Select OSC. */
-
-            .pll0Config =
-                {
-                    .enableMode = 0U, .prdiv = 0x00U, .vdiv = 0x0EU,
-                },
-            .pllcs = kMCG_PllClkSelPll0,
-        },
-    .simConfig =
-        {
-            .pllFllSel = 1U,        /* PLLFLLSEL select PLL. */
-            .er32kSrc = 2U,         /* ERCLK32K selection, use RTC. */
-            .clkdiv1 = 0x02260000U, /* SIM_CLKDIV1. */
-        },
-    .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
-                  .capLoad = 0,
-                  .workMode = kOSC_ModeOscLowPower,
-                  .oscerConfig =
-                      {
-                          .enableMode = kOSC_ErClkEnable,
-#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
-                          .erclkDiv = 0U,
-#endif
-                      }},
-    .coreClock = 180000000U, /* Core clock frequency */
-};
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
 /*
  * How to setup clock using clock driver functions:
  *
@@ -204,62 +56,389 @@ const clock_config_t g_defaultClockConfigHsrun = {
  * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
  */
 
-void BOARD_BootClockVLPR(void)
-{
-    CLOCK_SetSimSafeDivs();
-
-    CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs,
-                         g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode);
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!ClocksProfile
+product: Clocks v1.0
+processor: MK66FN2M0xxx18
+package_id: MK66FN2M0VMD18
+mcu_data: ksdk2_0
+processor_version: 1.0.1
+board: FRDM-K66F
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
 
-    CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig);
+#include "fsl_smc.h"
+#include "fsl_clock_config.h"
 
-    SystemCoreClock = g_defaultClockConfigVlpr.coreClock;
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define MCG_PLL_DISABLE                                   0U  /*!< MCGPLLCLK disabled */
+#define OSC_CAP0P                                         0U  /*!< Oscillator 0pF capacitor load */
+#define OSC_ER_CLK_DISABLE                                0U  /*!< Disable external reference clock */
+#define SIM_OSC32KSEL_RTC32KCLK_CLK                       2U  /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
+#define SIM_PLLFLLSEL_IRC48MCLK_CLK                       3U  /*!< PLLFLL select: IRC48MCLK clock */
+#define SIM_PLLFLLSEL_MCGPLLCLK_CLK                       1U  /*!< PLLFLL select: MCGPLLCLK clock */
 
-    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
-    SMC_SetPowerModeVlpr(SMC);
-    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
-    {
-    }
-}
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
 
-void BOARD_BootClockRUN(void)
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_CONFIG_SetFllExtRefDiv
+ * Description   : Configure FLL external reference divider (FRDIV).
+ * Param frdiv   : The value to set FRDIV.
+ *
+ *END**************************************************************************/
+static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
 {
-    CLOCK_SetSimSafeDivs();
-
-    CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
-    CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
-
-    CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
-                        &g_defaultClockConfigRun.mcgConfig.pll0Config);
-
-    CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
-                                  g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
+    MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
+}
 
-    CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockHSRUN **********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockHSRUN
+outputs:
+- {id: Bus_clock.outFreq, value: 60 MHz}
+- {id: Core_clock.outFreq, value: 180 MHz, locked: true, accuracy: '0.001'}
+- {id: Flash_clock.outFreq, value: 180/7 MHz}
+- {id: FlexBus_clock.outFreq, value: 60 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGFFCLK.outFreq, value: 375 kHz}
+- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
+- {id: OSCERCLK.outFreq, value: 12 MHz}
+- {id: OSCERCLK_UNDIV.outFreq, value: 12 MHz}
+- {id: PLLFLLCLK.outFreq, value: 180 MHz}
+- {id: System_clock.outFreq, value: 180 MHz}
+settings:
+- {id: MCGMode, value: PEE}
+- {id: powerMode, value: HSRUN}
+- {id: MCG.FCRDIV.scale, value: '1', locked: true}
+- {id: MCG.FRDIV.scale, value: '32'}
+- {id: MCG.IREFS.sel, value: MCG.FRDIV}
+- {id: MCG.PLLS.sel, value: MCG.PLLCS}
+- {id: MCG.VDIV.scale, value: '30'}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: MCG_C1_IREFSTEN_CFG, value: Enabled}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: Very_high}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
+- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
+- {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
+- {id: RTC_CR_CLKO_CFG, value: Disabled}
+- {id: SIM.LPUARTSRCSEL.sel, value: OSC.OSCERCLK}
+- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
+- {id: SIM.OUTDIV2.scale, value: '3', locked: true}
+- {id: SIM.OUTDIV3.scale, value: '3', locked: true}
+- {id: SIM.OUTDIV4.scale, value: '7', locked: true}
+- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
+- {id: SIM.RMIICLKSEL.sel, value: SIM.ENET_1588_CLK_EXT}
+- {id: SIM.SDHCSRCSEL.sel, value: OSC.OSCERCLK}
+- {id: SIM.TPMSRCSEL.sel, value: SIM.PLLFLLDIV}
+- {id: SIM.TRACECLKSEL.sel, value: SIM.TRACEDIV}
+- {id: SIM.TRACEDIV.scale, value: '2'}
+- {id: SIM.USBSRCSEL.sel, value: SIM.USBDIV}
+- {id: USBPHY.DIV.scale, value: '40'}
+- {id: USBPHY.PFD_CLK_SEL.sel, value: USBPHY.PFD_CLK_DIV2}
+- {id: USBPHY.PFD_FRAC_DIV.scale, value: '24', locked: true}
+sources:
+- {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
 
-    SystemCoreClock = g_defaultClockConfigRun.coreClock;
-}
+/*******************************************************************************
+ * Variables for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockHSRUN =
+    {
+        .mcgMode = kMCG_ModePEE,                  /* PEE - PLL Engaged External */
+        .irclkEnableMode = kMCG_IrclkEnable | kMCG_IrclkEnableInStop,/* MCGIRCLK enabled as well as in STOP mode */
+        .ircs = kMCG_IrcSlow,                     /* Slow internal reference clock selected */
+        .fcrdiv = 0x0U,                           /* Fast IRC divider: divided by 1 */
+        .frdiv = 0x0U,                            /* FLL reference clock divider: divided by 32 */
+        .drs = kMCG_DrsLow,                       /* Low frequency range */
+        .dmx32 = kMCG_Dmx32Default,               /* DCO has a default range of 25% */
+        .oscsel = kMCG_OscselOsc,                 /* Selects System Oscillator (OSCCLK) */
+        .pll0Config =
+            {
+                .enableMode = MCG_PLL_DISABLE,    /* MCGPLLCLK disabled */
+                .prdiv = 0x0U,                    /* PLL Reference divider: divided by 1 */
+                .vdiv = 0xeU,                     /* VCO divider: multiplied by 30 */
+            },
+        .pllcs = kMCG_PllClkSelPll0,              /* PLL0 output clock is selected */
+    };
+const sim_clock_config_t simConfig_BOARD_BootClockHSRUN =
+    {
+        .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
+        .pllFllDiv = 0,                           /* PLLFLLSEL clock divider divisor: divided by 1 */
+        .pllFllFrac = 0,                          /* PLLFLLSEL clock divider fraction: multiplied by 1 */
+        .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK,  /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
+        .clkdiv1 = 0x2260000U,                    /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /3, OUTDIV3: /3, OUTDIV4: /7 */
+    };
+const osc_config_t oscConfig_BOARD_BootClockHSRUN =
+    {
+        .freq = 12000000U,                        /* Oscillator frequency: 12000000Hz */
+        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
+        .workMode = kOSC_ModeOscLowPower,         /* Oscillator low power */
+        .oscerConfig =
+            {
+                .enableMode = kOSC_ErClkEnable,   /* Enable external reference clock, disable external reference clock in STOP mode */
+                .erclkDiv = 0,                    /* Divider for OSCERCLK: divided by 1 */
+            }
+    };
 
+/*******************************************************************************
+ * Code for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
 void BOARD_BootClockHSRUN(void)
 {
+    /* Set HSRUN power mode */
     SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
     SMC_SetPowerModeHsrun(SMC);
     while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
     {
     }
-
+    /* Set the system clock dividers in SIM to safe value. */
     CLOCK_SetSimSafeDivs();
+    /* Initializes OSC0 according to board configuration. */
+    CLOCK_InitOsc0(&oscConfig_BOARD_BootClockHSRUN);
+    CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockHSRUN.freq);
+    /* Configure the Internal Reference clock (MCGIRCLK). */
+    CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode,
+                                  mcgConfig_BOARD_BootClockHSRUN.ircs,
+                                  mcgConfig_BOARD_BootClockHSRUN.fcrdiv);
+    /* Configure FLL external reference divider (FRDIV). */
+    CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockHSRUN.frdiv);
+    /* Set MCG to PEE mode. */
+    CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockHSRUN.oscsel,
+                        mcgConfig_BOARD_BootClockHSRUN.pllcs,
+                        &mcgConfig_BOARD_BootClockHSRUN.pll0Config);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
+}
 
-    CLOCK_InitOsc0(&g_defaultClockConfigHsrun.oscConfig);
-    CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockVLPR
+outputs:
+- {id: Bus_clock.outFreq, value: 4 MHz}
+- {id: Core_clock.outFreq, value: 4 MHz}
+- {id: Flash_clock.outFreq, value: 800 kHz}
+- {id: FlexBus_clock.outFreq, value: 4 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGIRCLK.outFreq, value: 4 MHz}
+- {id: System_clock.outFreq, value: 4 MHz}
+settings:
+- {id: MCGMode, value: BLPI}
+- {id: powerMode, value: VLPR}
+- {id: MCG.CLKS.sel, value: MCG.IRCS}
+- {id: MCG.FCRDIV.scale, value: '1', locked: true}
+- {id: MCG.FRDIV.scale, value: '32'}
+- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: Very_high}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
+- {id: RTC_CR_CLKO_CFG, value: Disabled}
+- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
+- {id: SIM.OUTDIV3.scale, value: '1'}
+- {id: SIM.OUTDIV4.scale, value: '5'}
+- {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK}
+sources:
+- {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
+    {
+        .mcgMode = kMCG_ModeBLPI,                 /* BLPI - Bypassed Low Power Internal */
+        .irclkEnableMode = kMCG_IrclkEnable,      /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+        .ircs = kMCG_IrcFast,                     /* Fast internal reference clock selected */
+        .fcrdiv = 0x0U,                           /* Fast IRC divider: divided by 1 */
+        .frdiv = 0x0U,                            /* FLL reference clock divider: divided by 32 */
+        .drs = kMCG_DrsLow,                       /* Low frequency range */
+        .dmx32 = kMCG_Dmx32Default,               /* DCO has a default range of 25% */
+        .oscsel = kMCG_OscselOsc,                 /* Selects System Oscillator (OSCCLK) */
+        .pll0Config =
+            {
+                .enableMode = MCG_PLL_DISABLE,    /* MCGPLLCLK disabled */
+                .prdiv = 0x0U,                    /* PLL Reference divider: divided by 1 */
+                .vdiv = 0x0U,                     /* VCO divider: multiplied by 16 */
+            },
+        .pllcs = kMCG_PllClkSelPll0,              /* PLL0 output clock is selected */
+    };
+const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
+    {
+        .pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */
+        .pllFllDiv = 0,                           /* PLLFLLSEL clock divider divisor: divided by 1 */
+        .pllFllFrac = 0,                          /* PLLFLLSEL clock divider fraction: multiplied by 1 */
+        .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK,  /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
+        .clkdiv1 = 0x40000U,                      /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */
+    };
+const osc_config_t oscConfig_BOARD_BootClockVLPR =
+    {
+        .freq = 12000000U,                        /* Oscillator frequency: 12000000Hz */
+        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
+        .workMode = kOSC_ModeOscLowPower,         /* Oscillator low power */
+        .oscerConfig =
+            {
+                .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+                .erclkDiv = 0,                    /* Divider for OSCERCLK: divided by 1 */
+            }
+    };
 
-    CLOCK_BootToPeeMode(g_defaultClockConfigHsrun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
-                        &g_defaultClockConfigHsrun.mcgConfig.pll0Config);
+/*******************************************************************************
+ * Code for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+void BOARD_BootClockVLPR(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Initializes OSC0 according to board configuration. */
+    CLOCK_InitOsc0(&oscConfig_BOARD_BootClockVLPR);
+    CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockVLPR.freq);
+    /* Set MCG to BLPI mode. */
+    CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
+                         mcgConfig_BOARD_BootClockVLPR.ircs,
+                         mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
+    /* Select the MCG external reference clock. */
+    CLOCK_SetExternalRefClkConfig(mcgConfig_BOARD_BootClockVLPR.oscsel);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
+    /* Set VLPR power mode. */
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+    SMC_SetPowerModeVlpr(SMC, false);
+#else
+    SMC_SetPowerModeVlpr(SMC);
+#endif
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
+    {
+    }
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
+}
 
-    CLOCK_SetInternalRefClkConfig(g_defaultClockConfigHsrun.mcgConfig.irclkEnableMode,
-                                  g_defaultClockConfigHsrun.mcgConfig.ircs, g_defaultClockConfigHsrun.mcgConfig.fcrdiv);
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockRUN
+outputs:
+- {id: Bus_clock.outFreq, value: 60 MHz}
+- {id: Core_clock.outFreq, value: 120 MHz}
+- {id: Flash_clock.outFreq, value: 24 MHz}
+- {id: FlexBus_clock.outFreq, value: 60 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGFFCLK.outFreq, value: 375 kHz}
+- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
+- {id: OSCERCLK.outFreq, value: 12 MHz}
+- {id: OSCERCLK_UNDIV.outFreq, value: 12 MHz}
+- {id: PLLFLLCLK.outFreq, value: 120 MHz}
+- {id: System_clock.outFreq, value: 120 MHz}
+settings:
+- {id: MCGMode, value: PEE}
+- {id: MCG.FCRDIV.scale, value: '1', locked: true}
+- {id: MCG.FRDIV.scale, value: '32'}
+- {id: MCG.IREFS.sel, value: MCG.FRDIV}
+- {id: MCG.PLLS.sel, value: MCG.PLLCS}
+- {id: MCG.PRDIV.scale, value: '1', locked: true}
+- {id: MCG.VDIV.scale, value: '20', locked: true}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: Very_high}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
+- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
+- {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
+- {id: RTC_CR_CLKO_CFG, value: Disabled}
+- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
+- {id: SIM.OUTDIV1.scale, value: '1', locked: true}
+- {id: SIM.OUTDIV2.scale, value: '2'}
+- {id: SIM.OUTDIV4.scale, value: '5'}
+- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
+sources:
+- {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
 
-    CLOCK_SetSimConfig(&g_defaultClockConfigHsrun.simConfig);
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockRUN =
+    {
+        .mcgMode = kMCG_ModePEE,                  /* PEE - PLL Engaged External */
+        .irclkEnableMode = kMCG_IrclkEnable,      /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+        .ircs = kMCG_IrcSlow,                     /* Slow internal reference clock selected */
+        .fcrdiv = 0x0U,                           /* Fast IRC divider: divided by 1 */
+        .frdiv = 0x0U,                            /* FLL reference clock divider: divided by 32 */
+        .drs = kMCG_DrsLow,                       /* Low frequency range */
+        .dmx32 = kMCG_Dmx32Default,               /* DCO has a default range of 25% */
+        .oscsel = kMCG_OscselOsc,                 /* Selects System Oscillator (OSCCLK) */
+        .pll0Config =
+            {
+                .enableMode = MCG_PLL_DISABLE,    /* MCGPLLCLK disabled */
+                .prdiv = 0x0U,                    /* PLL Reference divider: divided by 1 */
+                .vdiv = 0x4U,                     /* VCO divider: multiplied by 20 */
+            },
+        .pllcs = kMCG_PllClkSelPll0,              /* PLL0 output clock is selected */
+    };
+const sim_clock_config_t simConfig_BOARD_BootClockRUN =
+    {
+        .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
+        .pllFllDiv = 0,                           /* PLLFLLSEL clock divider divisor: divided by 1 */
+        .pllFllFrac = 0,                          /* PLLFLLSEL clock divider fraction: multiplied by 1 */
+        .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK,  /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
+        .clkdiv1 = 0x1140000U,                    /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /5 */
+    };
+const osc_config_t oscConfig_BOARD_BootClockRUN =
+    {
+        .freq = 12000000U,                        /* Oscillator frequency: 12000000Hz */
+        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
+        .workMode = kOSC_ModeOscLowPower,         /* Oscillator low power */
+        .oscerConfig =
+            {
+                .enableMode = kOSC_ErClkEnable,   /* Enable external reference clock, disable external reference clock in STOP mode */
+                .erclkDiv = 0,                    /* Divider for OSCERCLK: divided by 1 */
+            }
+    };
 
-    SystemCoreClock = g_defaultClockConfigHsrun.coreClock;
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Initializes OSC0 according to board configuration. */
+    CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
+    CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
+    /* Configure the Internal Reference clock (MCGIRCLK). */
+    CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
+                                  mcgConfig_BOARD_BootClockRUN.ircs,
+                                  mcgConfig_BOARD_BootClockRUN.fcrdiv);
+    /* Configure FLL external reference divider (FRDIV). */
+    CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
+    /* Set MCG to PEE mode. */
+    CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel,
+                        mcgConfig_BOARD_BootClockRUN.pllcs,
+                        &mcgConfig_BOARD_BootClockRUN.pll0Config);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
 }
+
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_clock_config.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_clock_config.h
old mode 100644
new mode 100755
index 0a23dd9917f..1086faaa83b
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_clock_config.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_clock_config.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -27,28 +27,121 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
+
 #ifndef _CLOCK_CONFIG_H_
 #define _CLOCK_CONFIG_H_
 
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         12000000U  /*!< Board xtal0 frequency in Hz */
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockHSRUN **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK           180000000U  /*!< Core clock frequency: 180000000Hz */
+
+/*! @brief MCG set for BOARD_BootClockHSRUN configuration.
+ */
+extern const mcg_config_t mcgConfig_BOARD_BootClockHSRUN;
+/*! @brief SIM module set for BOARD_BootClockHSRUN configuration.
+ */
+extern const sim_clock_config_t simConfig_BOARD_BootClockHSRUN;
+/*! @brief OSC set for BOARD_BootClockHSRUN configuration.
+ */
+extern const osc_config_t oscConfig_BOARD_BootClockHSRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockHSRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
 /*******************************************************************************
- * DEFINITION
+ * Definitions for BOARD_BootClockVLPR configuration
  ******************************************************************************/
-#define BOARD_XTAL0_CLK_HZ 12000000U
-#define BOARD_XTAL32K_CLK_HZ 32768U
+#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK              4000000U  /*!< Core clock frequency: 4000000Hz */
+
+/*! @brief MCG set for BOARD_BootClockVLPR configuration.
+ */
+extern const mcg_config_t mcgConfig_BOARD_BootClockVLPR;
+/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
+ */
+extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
+/*! @brief OSC set for BOARD_BootClockVLPR configuration.
+ */
+extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
 
 /*******************************************************************************
- * API
+ * API for BOARD_BootClockVLPR configuration
  ******************************************************************************/
 #if defined(__cplusplus)
 extern "C" {
 #endif /* __cplusplus*/
 
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
 void BOARD_BootClockVLPR(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             120000000U  /*!< Core clock frequency: 120000000Hz */
+
+/*! @brief MCG set for BOARD_BootClockRUN configuration.
+ */
+extern const mcg_config_t mcgConfig_BOARD_BootClockRUN;
+/*! @brief SIM module set for BOARD_BootClockRUN configuration.
+ */
+extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
+/*! @brief OSC set for BOARD_BootClockRUN configuration.
+ */
+extern const osc_config_t oscConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
 void BOARD_BootClockRUN(void);
-void BOARD_BootClockHSRUN(void);
 
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus*/
 
 #endif /* _CLOCK_CONFIG_H_ */
+
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_phy.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_phy.c
index 961a97f339f..a5bef533d5f 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_phy.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_phy.c
@@ -1,32 +1,32 @@
 /*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-*   of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-*   list of conditions and the following disclaimer in the documentation and/or
-*   other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-*   contributors may be used to endorse or promote products derived from this
-*   software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #include "fsl_phy.h"
 
@@ -53,8 +53,10 @@ extern uint32_t ENET_GetInstance(ENET_Type *base);
  * Variables
  ******************************************************************************/
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to enet clocks for each instance. */
 extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
@@ -64,14 +66,30 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
 {
     uint32_t bssReg;
     uint32_t counter = PHY_TIMEOUT_COUNT;
+    uint32_t idReg = 0;
     status_t result = kStatus_Success;
     uint32_t instance = ENET_GetInstance(base);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Set SMI first. */
     CLOCK_EnableClock(s_enetClock[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
     ENET_SetSMI(base, srcClock_Hz, false);
 
+    /* Initialization after PHY stars to work. */
+    while ((idReg != PHY_CONTROL_ID1) && (counter != 0))
+    {
+        PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
+        counter --;       
+    }
+
+    if (!counter)
+    {
+        return kStatus_Fail;
+    }
+
     /* Reset PHY. */
+    counter = PHY_TIMEOUT_COUNT;
     result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
     if (result == kStatus_Success)
     {
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_phy.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_phy.h
index bf3167fa69a..9353bea7989 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_phy.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/TARGET_FRDM/fsl_phy.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/MK66F18.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/MK66F18.h
index 516ce8501e3..a2d8eec3b9c 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/MK66F18.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/MK66F18.h
@@ -9,17 +9,17 @@
 **                          Freescale C/C++ for Embedded ARM
 **                          GNU C Compiler
 **                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
 **
 **     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015
 **     Version:             rev. 3.0, 2015-03-25
-**     Build:               b151218
+**     Build:               b170112
 **
 **     Abstract:
 **         CMSIS Peripheral Access Layer for MK66F18
 **
-**     Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
-**     All rights reserved.
-**
+**     Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016 - 2017 NXP
 **     Redistribution and use in source and binary forms, with or without modification,
 **     are permitted provided that the following conditions are met:
 **
@@ -30,7 +30,7 @@
 **       list of conditions and the following disclaimer in the documentation and/or
 **       other materials provided with the distribution.
 **
-**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**     o Neither the name of the copyright holder nor the names of its
 **       contributors may be used to endorse or promote products derived from this
 **       software without specific prior written permission.
 **
@@ -45,8 +45,8 @@
 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
 **
 **     Revisions:
 **     - rev. 1.0 (2013-09-02)
@@ -5218,7 +5218,7 @@ typedef struct {
 /** Array initializer of DMA peripheral base pointers */
 #define DMA_BASE_PTRS                            { DMA0 }
 /** Interrupt vectors for the DMA peripheral type */
-#define DMA_CHN_IRQS                             { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn }
+#define DMA_CHN_IRQS                             { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
 #define DMA_ERROR_IRQS                           { DMA_Error_IRQn }
 
 /*!
@@ -6182,6 +6182,9 @@ typedef struct {
 #define ENET_Receive_IRQS                        { ENET_Receive_IRQn }
 #define ENET_Error_IRQS                          { ENET_Error_IRQn }
 #define ENET_1588_Timer_IRQS                     { ENET_1588_Timer_IRQn }
+/* ENET Buffer Descriptor and Buffer Address Alignment. */
+#define ENET_BUFF_ALIGNMENT                      (16U)
+
 
 /*!
  * @}
@@ -7731,30 +7734,30 @@ typedef struct {
 
 
 /* GPIO - Peripheral instance base addresses */
-/** Peripheral PTA base address */
-#define PTA_BASE                                 (0x400FF000u)
-/** Peripheral PTA base pointer */
-#define PTA                                      ((GPIO_Type *)PTA_BASE)
-/** Peripheral PTB base address */
-#define PTB_BASE                                 (0x400FF040u)
-/** Peripheral PTB base pointer */
-#define PTB                                      ((GPIO_Type *)PTB_BASE)
-/** Peripheral PTC base address */
-#define PTC_BASE                                 (0x400FF080u)
-/** Peripheral PTC base pointer */
-#define PTC                                      ((GPIO_Type *)PTC_BASE)
-/** Peripheral PTD base address */
-#define PTD_BASE                                 (0x400FF0C0u)
-/** Peripheral PTD base pointer */
-#define PTD                                      ((GPIO_Type *)PTD_BASE)
-/** Peripheral PTE base address */
-#define PTE_BASE                                 (0x400FF100u)
-/** Peripheral PTE base pointer */
-#define PTE                                      ((GPIO_Type *)PTE_BASE)
+/** Peripheral GPIOA base address */
+#define GPIOA_BASE                               (0x400FF000u)
+/** Peripheral GPIOA base pointer */
+#define GPIOA                                    ((GPIO_Type *)GPIOA_BASE)
+/** Peripheral GPIOB base address */
+#define GPIOB_BASE                               (0x400FF040u)
+/** Peripheral GPIOB base pointer */
+#define GPIOB                                    ((GPIO_Type *)GPIOB_BASE)
+/** Peripheral GPIOC base address */
+#define GPIOC_BASE                               (0x400FF080u)
+/** Peripheral GPIOC base pointer */
+#define GPIOC                                    ((GPIO_Type *)GPIOC_BASE)
+/** Peripheral GPIOD base address */
+#define GPIOD_BASE                               (0x400FF0C0u)
+/** Peripheral GPIOD base pointer */
+#define GPIOD                                    ((GPIO_Type *)GPIOD_BASE)
+/** Peripheral GPIOE base address */
+#define GPIOE_BASE                               (0x400FF100u)
+/** Peripheral GPIOE base pointer */
+#define GPIOE                                    ((GPIO_Type *)GPIOE_BASE)
 /** Array initializer of GPIO peripheral base addresses */
-#define GPIO_BASE_ADDRS                          { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
+#define GPIO_BASE_ADDRS                          { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
 /** Array initializer of GPIO peripheral base pointers */
-#define GPIO_BASE_PTRS                           { PTA, PTB, PTC, PTD, PTE }
+#define GPIO_BASE_PTRS                           { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
 
 /*!
  * @}
@@ -9827,252 +9830,6 @@ typedef struct {
  */ /* end of group MCM_Peripheral_Access_Layer */
 
 
-/* ----------------------------------------------------------------------------
-   -- MPU Peripheral Access Layer
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
- * @{
- */
-
-/** MPU - Register Layout Typedef */
-typedef struct {
-  __IO uint32_t CESR;                              /**< Control/Error Status Register, offset: 0x0 */
-       uint8_t RESERVED_0[12];
-  struct {                                         /* offset: 0x10, array step: 0x8 */
-    __I  uint32_t EAR;                               /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
-    __I  uint32_t EDR;                               /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
-  } SP[5];
-       uint8_t RESERVED_1[968];
-  __IO uint32_t WORD[12][4];                       /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
-       uint8_t RESERVED_2[832];
-  __IO uint32_t RGDAAC[12];                        /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
-} MPU_Type;
-
-/* ----------------------------------------------------------------------------
-   -- MPU Register Masks
-   ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MPU_Register_Masks MPU Register Masks
- * @{
- */
-
-/*! @name CESR - Control/Error Status Register */
-#define MPU_CESR_VLD_MASK                        (0x1U)
-#define MPU_CESR_VLD_SHIFT                       (0U)
-#define MPU_CESR_VLD(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_CESR_VLD_SHIFT)) & MPU_CESR_VLD_MASK)
-#define MPU_CESR_NRGD_MASK                       (0xF00U)
-#define MPU_CESR_NRGD_SHIFT                      (8U)
-#define MPU_CESR_NRGD(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NRGD_SHIFT)) & MPU_CESR_NRGD_MASK)
-#define MPU_CESR_NSP_MASK                        (0xF000U)
-#define MPU_CESR_NSP_SHIFT                       (12U)
-#define MPU_CESR_NSP(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NSP_SHIFT)) & MPU_CESR_NSP_MASK)
-#define MPU_CESR_HRL_MASK                        (0xF0000U)
-#define MPU_CESR_HRL_SHIFT                       (16U)
-#define MPU_CESR_HRL(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_CESR_HRL_SHIFT)) & MPU_CESR_HRL_MASK)
-#define MPU_CESR_SPERR_MASK                      (0xF8000000U)
-#define MPU_CESR_SPERR_SHIFT                     (27U)
-#define MPU_CESR_SPERR(x)                        (((uint32_t)(((uint32_t)(x)) << MPU_CESR_SPERR_SHIFT)) & MPU_CESR_SPERR_MASK)
-
-/*! @name EAR - Error Address Register, slave port n */
-#define MPU_EAR_EADDR_MASK                       (0xFFFFFFFFU)
-#define MPU_EAR_EADDR_SHIFT                      (0U)
-#define MPU_EAR_EADDR(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_EAR_EADDR_SHIFT)) & MPU_EAR_EADDR_MASK)
-
-/* The count of MPU_EAR */
-#define MPU_EAR_COUNT                            (5U)
-
-/*! @name EDR - Error Detail Register, slave port n */
-#define MPU_EDR_ERW_MASK                         (0x1U)
-#define MPU_EDR_ERW_SHIFT                        (0U)
-#define MPU_EDR_ERW(x)                           (((uint32_t)(((uint32_t)(x)) << MPU_EDR_ERW_SHIFT)) & MPU_EDR_ERW_MASK)
-#define MPU_EDR_EATTR_MASK                       (0xEU)
-#define MPU_EDR_EATTR_SHIFT                      (1U)
-#define MPU_EDR_EATTR(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EATTR_SHIFT)) & MPU_EDR_EATTR_MASK)
-#define MPU_EDR_EMN_MASK                         (0xF0U)
-#define MPU_EDR_EMN_SHIFT                        (4U)
-#define MPU_EDR_EMN(x)                           (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EMN_SHIFT)) & MPU_EDR_EMN_MASK)
-#define MPU_EDR_EPID_MASK                        (0xFF00U)
-#define MPU_EDR_EPID_SHIFT                       (8U)
-#define MPU_EDR_EPID(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EPID_SHIFT)) & MPU_EDR_EPID_MASK)
-#define MPU_EDR_EACD_MASK                        (0xFFFF0000U)
-#define MPU_EDR_EACD_SHIFT                       (16U)
-#define MPU_EDR_EACD(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EACD_SHIFT)) & MPU_EDR_EACD_MASK)
-
-/* The count of MPU_EDR */
-#define MPU_EDR_COUNT                            (5U)
-
-/*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
-#define MPU_WORD_VLD_MASK                        (0x1U)
-#define MPU_WORD_VLD_SHIFT                       (0U)
-#define MPU_WORD_VLD(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_WORD_VLD_SHIFT)) & MPU_WORD_VLD_MASK)
-#define MPU_WORD_M0UM_MASK                       (0x7U)
-#define MPU_WORD_M0UM_SHIFT                      (0U)
-#define MPU_WORD_M0UM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0UM_SHIFT)) & MPU_WORD_M0UM_MASK)
-#define MPU_WORD_M0SM_MASK                       (0x18U)
-#define MPU_WORD_M0SM_SHIFT                      (3U)
-#define MPU_WORD_M0SM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0SM_SHIFT)) & MPU_WORD_M0SM_MASK)
-#define MPU_WORD_M0PE_MASK                       (0x20U)
-#define MPU_WORD_M0PE_SHIFT                      (5U)
-#define MPU_WORD_M0PE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0PE_SHIFT)) & MPU_WORD_M0PE_MASK)
-#define MPU_WORD_ENDADDR_MASK                    (0xFFFFFFE0U)
-#define MPU_WORD_ENDADDR_SHIFT                   (5U)
-#define MPU_WORD_ENDADDR(x)                      (((uint32_t)(((uint32_t)(x)) << MPU_WORD_ENDADDR_SHIFT)) & MPU_WORD_ENDADDR_MASK)
-#define MPU_WORD_SRTADDR_MASK                    (0xFFFFFFE0U)
-#define MPU_WORD_SRTADDR_SHIFT                   (5U)
-#define MPU_WORD_SRTADDR(x)                      (((uint32_t)(((uint32_t)(x)) << MPU_WORD_SRTADDR_SHIFT)) & MPU_WORD_SRTADDR_MASK)
-#define MPU_WORD_M1UM_MASK                       (0x1C0U)
-#define MPU_WORD_M1UM_SHIFT                      (6U)
-#define MPU_WORD_M1UM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1UM_SHIFT)) & MPU_WORD_M1UM_MASK)
-#define MPU_WORD_M1SM_MASK                       (0x600U)
-#define MPU_WORD_M1SM_SHIFT                      (9U)
-#define MPU_WORD_M1SM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1SM_SHIFT)) & MPU_WORD_M1SM_MASK)
-#define MPU_WORD_M1PE_MASK                       (0x800U)
-#define MPU_WORD_M1PE_SHIFT                      (11U)
-#define MPU_WORD_M1PE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1PE_SHIFT)) & MPU_WORD_M1PE_MASK)
-#define MPU_WORD_M2UM_MASK                       (0x7000U)
-#define MPU_WORD_M2UM_SHIFT                      (12U)
-#define MPU_WORD_M2UM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2UM_SHIFT)) & MPU_WORD_M2UM_MASK)
-#define MPU_WORD_M2SM_MASK                       (0x18000U)
-#define MPU_WORD_M2SM_SHIFT                      (15U)
-#define MPU_WORD_M2SM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2SM_SHIFT)) & MPU_WORD_M2SM_MASK)
-#define MPU_WORD_PIDMASK_MASK                    (0xFF0000U)
-#define MPU_WORD_PIDMASK_SHIFT                   (16U)
-#define MPU_WORD_PIDMASK(x)                      (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PIDMASK_SHIFT)) & MPU_WORD_PIDMASK_MASK)
-#define MPU_WORD_M2PE_MASK                       (0x20000U)
-#define MPU_WORD_M2PE_SHIFT                      (17U)
-#define MPU_WORD_M2PE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2PE_SHIFT)) & MPU_WORD_M2PE_MASK)
-#define MPU_WORD_M3UM_MASK                       (0x1C0000U)
-#define MPU_WORD_M3UM_SHIFT                      (18U)
-#define MPU_WORD_M3UM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3UM_SHIFT)) & MPU_WORD_M3UM_MASK)
-#define MPU_WORD_M3SM_MASK                       (0x600000U)
-#define MPU_WORD_M3SM_SHIFT                      (21U)
-#define MPU_WORD_M3SM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3SM_SHIFT)) & MPU_WORD_M3SM_MASK)
-#define MPU_WORD_M3PE_MASK                       (0x800000U)
-#define MPU_WORD_M3PE_SHIFT                      (23U)
-#define MPU_WORD_M3PE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3PE_SHIFT)) & MPU_WORD_M3PE_MASK)
-#define MPU_WORD_PID_MASK                        (0xFF000000U)
-#define MPU_WORD_PID_SHIFT                       (24U)
-#define MPU_WORD_PID(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PID_SHIFT)) & MPU_WORD_PID_MASK)
-#define MPU_WORD_M4WE_MASK                       (0x1000000U)
-#define MPU_WORD_M4WE_SHIFT                      (24U)
-#define MPU_WORD_M4WE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4WE_SHIFT)) & MPU_WORD_M4WE_MASK)
-#define MPU_WORD_M4RE_MASK                       (0x2000000U)
-#define MPU_WORD_M4RE_SHIFT                      (25U)
-#define MPU_WORD_M4RE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4RE_SHIFT)) & MPU_WORD_M4RE_MASK)
-#define MPU_WORD_M5WE_MASK                       (0x4000000U)
-#define MPU_WORD_M5WE_SHIFT                      (26U)
-#define MPU_WORD_M5WE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5WE_SHIFT)) & MPU_WORD_M5WE_MASK)
-#define MPU_WORD_M5RE_MASK                       (0x8000000U)
-#define MPU_WORD_M5RE_SHIFT                      (27U)
-#define MPU_WORD_M5RE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5RE_SHIFT)) & MPU_WORD_M5RE_MASK)
-#define MPU_WORD_M6WE_MASK                       (0x10000000U)
-#define MPU_WORD_M6WE_SHIFT                      (28U)
-#define MPU_WORD_M6WE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6WE_SHIFT)) & MPU_WORD_M6WE_MASK)
-#define MPU_WORD_M6RE_MASK                       (0x20000000U)
-#define MPU_WORD_M6RE_SHIFT                      (29U)
-#define MPU_WORD_M6RE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6RE_SHIFT)) & MPU_WORD_M6RE_MASK)
-#define MPU_WORD_M7WE_MASK                       (0x40000000U)
-#define MPU_WORD_M7WE_SHIFT                      (30U)
-#define MPU_WORD_M7WE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7WE_SHIFT)) & MPU_WORD_M7WE_MASK)
-#define MPU_WORD_M7RE_MASK                       (0x80000000U)
-#define MPU_WORD_M7RE_SHIFT                      (31U)
-#define MPU_WORD_M7RE(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7RE_SHIFT)) & MPU_WORD_M7RE_MASK)
-
-/* The count of MPU_WORD */
-#define MPU_WORD_COUNT                           (12U)
-
-/* The count of MPU_WORD */
-#define MPU_WORD_COUNT2                          (4U)
-
-/*! @name RGDAAC - Region Descriptor Alternate Access Control n */
-#define MPU_RGDAAC_M0UM_MASK                     (0x7U)
-#define MPU_RGDAAC_M0UM_SHIFT                    (0U)
-#define MPU_RGDAAC_M0UM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0UM_SHIFT)) & MPU_RGDAAC_M0UM_MASK)
-#define MPU_RGDAAC_M0SM_MASK                     (0x18U)
-#define MPU_RGDAAC_M0SM_SHIFT                    (3U)
-#define MPU_RGDAAC_M0SM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0SM_SHIFT)) & MPU_RGDAAC_M0SM_MASK)
-#define MPU_RGDAAC_M0PE_MASK                     (0x20U)
-#define MPU_RGDAAC_M0PE_SHIFT                    (5U)
-#define MPU_RGDAAC_M0PE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0PE_SHIFT)) & MPU_RGDAAC_M0PE_MASK)
-#define MPU_RGDAAC_M1UM_MASK                     (0x1C0U)
-#define MPU_RGDAAC_M1UM_SHIFT                    (6U)
-#define MPU_RGDAAC_M1UM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1UM_SHIFT)) & MPU_RGDAAC_M1UM_MASK)
-#define MPU_RGDAAC_M1SM_MASK                     (0x600U)
-#define MPU_RGDAAC_M1SM_SHIFT                    (9U)
-#define MPU_RGDAAC_M1SM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1SM_SHIFT)) & MPU_RGDAAC_M1SM_MASK)
-#define MPU_RGDAAC_M1PE_MASK                     (0x800U)
-#define MPU_RGDAAC_M1PE_SHIFT                    (11U)
-#define MPU_RGDAAC_M1PE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1PE_SHIFT)) & MPU_RGDAAC_M1PE_MASK)
-#define MPU_RGDAAC_M2UM_MASK                     (0x7000U)
-#define MPU_RGDAAC_M2UM_SHIFT                    (12U)
-#define MPU_RGDAAC_M2UM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2UM_SHIFT)) & MPU_RGDAAC_M2UM_MASK)
-#define MPU_RGDAAC_M2SM_MASK                     (0x18000U)
-#define MPU_RGDAAC_M2SM_SHIFT                    (15U)
-#define MPU_RGDAAC_M2SM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2SM_SHIFT)) & MPU_RGDAAC_M2SM_MASK)
-#define MPU_RGDAAC_M2PE_MASK                     (0x20000U)
-#define MPU_RGDAAC_M2PE_SHIFT                    (17U)
-#define MPU_RGDAAC_M2PE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2PE_SHIFT)) & MPU_RGDAAC_M2PE_MASK)
-#define MPU_RGDAAC_M3UM_MASK                     (0x1C0000U)
-#define MPU_RGDAAC_M3UM_SHIFT                    (18U)
-#define MPU_RGDAAC_M3UM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3UM_SHIFT)) & MPU_RGDAAC_M3UM_MASK)
-#define MPU_RGDAAC_M3SM_MASK                     (0x600000U)
-#define MPU_RGDAAC_M3SM_SHIFT                    (21U)
-#define MPU_RGDAAC_M3SM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3SM_SHIFT)) & MPU_RGDAAC_M3SM_MASK)
-#define MPU_RGDAAC_M3PE_MASK                     (0x800000U)
-#define MPU_RGDAAC_M3PE_SHIFT                    (23U)
-#define MPU_RGDAAC_M3PE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3PE_SHIFT)) & MPU_RGDAAC_M3PE_MASK)
-#define MPU_RGDAAC_M4WE_MASK                     (0x1000000U)
-#define MPU_RGDAAC_M4WE_SHIFT                    (24U)
-#define MPU_RGDAAC_M4WE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4WE_SHIFT)) & MPU_RGDAAC_M4WE_MASK)
-#define MPU_RGDAAC_M4RE_MASK                     (0x2000000U)
-#define MPU_RGDAAC_M4RE_SHIFT                    (25U)
-#define MPU_RGDAAC_M4RE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4RE_SHIFT)) & MPU_RGDAAC_M4RE_MASK)
-#define MPU_RGDAAC_M5WE_MASK                     (0x4000000U)
-#define MPU_RGDAAC_M5WE_SHIFT                    (26U)
-#define MPU_RGDAAC_M5WE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5WE_SHIFT)) & MPU_RGDAAC_M5WE_MASK)
-#define MPU_RGDAAC_M5RE_MASK                     (0x8000000U)
-#define MPU_RGDAAC_M5RE_SHIFT                    (27U)
-#define MPU_RGDAAC_M5RE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5RE_SHIFT)) & MPU_RGDAAC_M5RE_MASK)
-#define MPU_RGDAAC_M6WE_MASK                     (0x10000000U)
-#define MPU_RGDAAC_M6WE_SHIFT                    (28U)
-#define MPU_RGDAAC_M6WE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6WE_SHIFT)) & MPU_RGDAAC_M6WE_MASK)
-#define MPU_RGDAAC_M6RE_MASK                     (0x20000000U)
-#define MPU_RGDAAC_M6RE_SHIFT                    (29U)
-#define MPU_RGDAAC_M6RE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6RE_SHIFT)) & MPU_RGDAAC_M6RE_MASK)
-#define MPU_RGDAAC_M7WE_MASK                     (0x40000000U)
-#define MPU_RGDAAC_M7WE_SHIFT                    (30U)
-#define MPU_RGDAAC_M7WE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7WE_SHIFT)) & MPU_RGDAAC_M7WE_MASK)
-#define MPU_RGDAAC_M7RE_MASK                     (0x80000000U)
-#define MPU_RGDAAC_M7RE_SHIFT                    (31U)
-#define MPU_RGDAAC_M7RE(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7RE_SHIFT)) & MPU_RGDAAC_M7RE_MASK)
-
-/* The count of MPU_RGDAAC */
-#define MPU_RGDAAC_COUNT                         (12U)
-
-
-/*!
- * @}
- */ /* end of group MPU_Register_Masks */
-
-
-/* MPU - Peripheral instance base addresses */
-/** Peripheral MPU base address */
-#define MPU_BASE                                 (0x4000D000u)
-/** Peripheral MPU base pointer */
-#define MPU                                      ((MPU_Type *)MPU_BASE)
-/** Array initializer of MPU peripheral base addresses */
-#define MPU_BASE_ADDRS                           { MPU_BASE }
-/** Array initializer of MPU peripheral base pointers */
-#define MPU_BASE_PTRS                            { MPU }
-
-/*!
- * @}
- */ /* end of group MPU_Peripheral_Access_Layer */
-
-
 /* ----------------------------------------------------------------------------
    -- NV Peripheral Access Layer
    ---------------------------------------------------------------------------- */
@@ -10590,7 +10347,7 @@ typedef struct {
 /** Array initializer of PIT peripheral base pointers */
 #define PIT_BASE_PTRS                            { PIT }
 /** Interrupt vectors for the PIT peripheral type */
-#define PIT_IRQS                                 { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
+#define PIT_IRQS                                 { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }
 
 /*!
  * @}
@@ -13236,6 +12993,252 @@ typedef struct {
  */ /* end of group SPI_Peripheral_Access_Layer */
 
 
+/* ----------------------------------------------------------------------------
+   -- SYSMPU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSMPU_Peripheral_Access_Layer SYSMPU Peripheral Access Layer
+ * @{
+ */
+
+/** SYSMPU - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CESR;                              /**< Control/Error Status Register, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  struct {                                         /* offset: 0x10, array step: 0x8 */
+    __I  uint32_t EAR;                               /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
+    __I  uint32_t EDR;                               /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
+  } SP[5];
+       uint8_t RESERVED_1[968];
+  __IO uint32_t WORD[12][4];                       /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
+       uint8_t RESERVED_2[832];
+  __IO uint32_t RGDAAC[12];                        /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
+} SYSMPU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SYSMPU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSMPU_Register_Masks SYSMPU Register Masks
+ * @{
+ */
+
+/*! @name CESR - Control/Error Status Register */
+#define SYSMPU_CESR_VLD_MASK                     (0x1U)
+#define SYSMPU_CESR_VLD_SHIFT                    (0U)
+#define SYSMPU_CESR_VLD(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
+#define SYSMPU_CESR_NRGD_MASK                    (0xF00U)
+#define SYSMPU_CESR_NRGD_SHIFT                   (8U)
+#define SYSMPU_CESR_NRGD(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
+#define SYSMPU_CESR_NSP_MASK                     (0xF000U)
+#define SYSMPU_CESR_NSP_SHIFT                    (12U)
+#define SYSMPU_CESR_NSP(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
+#define SYSMPU_CESR_HRL_MASK                     (0xF0000U)
+#define SYSMPU_CESR_HRL_SHIFT                    (16U)
+#define SYSMPU_CESR_HRL(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
+#define SYSMPU_CESR_SPERR_MASK                   (0xF8000000U)
+#define SYSMPU_CESR_SPERR_SHIFT                  (27U)
+#define SYSMPU_CESR_SPERR(x)                     (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
+
+/*! @name EAR - Error Address Register, slave port n */
+#define SYSMPU_EAR_EADDR_MASK                    (0xFFFFFFFFU)
+#define SYSMPU_EAR_EADDR_SHIFT                   (0U)
+#define SYSMPU_EAR_EADDR(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
+
+/* The count of SYSMPU_EAR */
+#define SYSMPU_EAR_COUNT                         (5U)
+
+/*! @name EDR - Error Detail Register, slave port n */
+#define SYSMPU_EDR_ERW_MASK                      (0x1U)
+#define SYSMPU_EDR_ERW_SHIFT                     (0U)
+#define SYSMPU_EDR_ERW(x)                        (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
+#define SYSMPU_EDR_EATTR_MASK                    (0xEU)
+#define SYSMPU_EDR_EATTR_SHIFT                   (1U)
+#define SYSMPU_EDR_EATTR(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
+#define SYSMPU_EDR_EMN_MASK                      (0xF0U)
+#define SYSMPU_EDR_EMN_SHIFT                     (4U)
+#define SYSMPU_EDR_EMN(x)                        (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
+#define SYSMPU_EDR_EPID_MASK                     (0xFF00U)
+#define SYSMPU_EDR_EPID_SHIFT                    (8U)
+#define SYSMPU_EDR_EPID(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK)
+#define SYSMPU_EDR_EACD_MASK                     (0xFFFF0000U)
+#define SYSMPU_EDR_EACD_SHIFT                    (16U)
+#define SYSMPU_EDR_EACD(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
+
+/* The count of SYSMPU_EDR */
+#define SYSMPU_EDR_COUNT                         (5U)
+
+/*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
+#define SYSMPU_WORD_VLD_MASK                     (0x1U)
+#define SYSMPU_WORD_VLD_SHIFT                    (0U)
+#define SYSMPU_WORD_VLD(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
+#define SYSMPU_WORD_M0UM_MASK                    (0x7U)
+#define SYSMPU_WORD_M0UM_SHIFT                   (0U)
+#define SYSMPU_WORD_M0UM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
+#define SYSMPU_WORD_M0SM_MASK                    (0x18U)
+#define SYSMPU_WORD_M0SM_SHIFT                   (3U)
+#define SYSMPU_WORD_M0SM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
+#define SYSMPU_WORD_M0PE_MASK                    (0x20U)
+#define SYSMPU_WORD_M0PE_SHIFT                   (5U)
+#define SYSMPU_WORD_M0PE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK)
+#define SYSMPU_WORD_ENDADDR_MASK                 (0xFFFFFFE0U)
+#define SYSMPU_WORD_ENDADDR_SHIFT                (5U)
+#define SYSMPU_WORD_ENDADDR(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
+#define SYSMPU_WORD_SRTADDR_MASK                 (0xFFFFFFE0U)
+#define SYSMPU_WORD_SRTADDR_SHIFT                (5U)
+#define SYSMPU_WORD_SRTADDR(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
+#define SYSMPU_WORD_M1UM_MASK                    (0x1C0U)
+#define SYSMPU_WORD_M1UM_SHIFT                   (6U)
+#define SYSMPU_WORD_M1UM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
+#define SYSMPU_WORD_M1SM_MASK                    (0x600U)
+#define SYSMPU_WORD_M1SM_SHIFT                   (9U)
+#define SYSMPU_WORD_M1SM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
+#define SYSMPU_WORD_M1PE_MASK                    (0x800U)
+#define SYSMPU_WORD_M1PE_SHIFT                   (11U)
+#define SYSMPU_WORD_M1PE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK)
+#define SYSMPU_WORD_M2UM_MASK                    (0x7000U)
+#define SYSMPU_WORD_M2UM_SHIFT                   (12U)
+#define SYSMPU_WORD_M2UM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
+#define SYSMPU_WORD_M2SM_MASK                    (0x18000U)
+#define SYSMPU_WORD_M2SM_SHIFT                   (15U)
+#define SYSMPU_WORD_M2SM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
+#define SYSMPU_WORD_PIDMASK_MASK                 (0xFF0000U)
+#define SYSMPU_WORD_PIDMASK_SHIFT                (16U)
+#define SYSMPU_WORD_PIDMASK(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK)
+#define SYSMPU_WORD_M2PE_MASK                    (0x20000U)
+#define SYSMPU_WORD_M2PE_SHIFT                   (17U)
+#define SYSMPU_WORD_M2PE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK)
+#define SYSMPU_WORD_M3UM_MASK                    (0x1C0000U)
+#define SYSMPU_WORD_M3UM_SHIFT                   (18U)
+#define SYSMPU_WORD_M3UM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
+#define SYSMPU_WORD_M3SM_MASK                    (0x600000U)
+#define SYSMPU_WORD_M3SM_SHIFT                   (21U)
+#define SYSMPU_WORD_M3SM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
+#define SYSMPU_WORD_M3PE_MASK                    (0x800000U)
+#define SYSMPU_WORD_M3PE_SHIFT                   (23U)
+#define SYSMPU_WORD_M3PE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)
+#define SYSMPU_WORD_PID_MASK                     (0xFF000000U)
+#define SYSMPU_WORD_PID_SHIFT                    (24U)
+#define SYSMPU_WORD_PID(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK)
+#define SYSMPU_WORD_M4WE_MASK                    (0x1000000U)
+#define SYSMPU_WORD_M4WE_SHIFT                   (24U)
+#define SYSMPU_WORD_M4WE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
+#define SYSMPU_WORD_M4RE_MASK                    (0x2000000U)
+#define SYSMPU_WORD_M4RE_SHIFT                   (25U)
+#define SYSMPU_WORD_M4RE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
+#define SYSMPU_WORD_M5WE_MASK                    (0x4000000U)
+#define SYSMPU_WORD_M5WE_SHIFT                   (26U)
+#define SYSMPU_WORD_M5WE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
+#define SYSMPU_WORD_M5RE_MASK                    (0x8000000U)
+#define SYSMPU_WORD_M5RE_SHIFT                   (27U)
+#define SYSMPU_WORD_M5RE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
+#define SYSMPU_WORD_M6WE_MASK                    (0x10000000U)
+#define SYSMPU_WORD_M6WE_SHIFT                   (28U)
+#define SYSMPU_WORD_M6WE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
+#define SYSMPU_WORD_M6RE_MASK                    (0x20000000U)
+#define SYSMPU_WORD_M6RE_SHIFT                   (29U)
+#define SYSMPU_WORD_M6RE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
+#define SYSMPU_WORD_M7WE_MASK                    (0x40000000U)
+#define SYSMPU_WORD_M7WE_SHIFT                   (30U)
+#define SYSMPU_WORD_M7WE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
+#define SYSMPU_WORD_M7RE_MASK                    (0x80000000U)
+#define SYSMPU_WORD_M7RE_SHIFT                   (31U)
+#define SYSMPU_WORD_M7RE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
+
+/* The count of SYSMPU_WORD */
+#define SYSMPU_WORD_COUNT                        (12U)
+
+/* The count of SYSMPU_WORD */
+#define SYSMPU_WORD_COUNT2                       (4U)
+
+/*! @name RGDAAC - Region Descriptor Alternate Access Control n */
+#define SYSMPU_RGDAAC_M0UM_MASK                  (0x7U)
+#define SYSMPU_RGDAAC_M0UM_SHIFT                 (0U)
+#define SYSMPU_RGDAAC_M0UM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
+#define SYSMPU_RGDAAC_M0SM_MASK                  (0x18U)
+#define SYSMPU_RGDAAC_M0SM_SHIFT                 (3U)
+#define SYSMPU_RGDAAC_M0SM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
+#define SYSMPU_RGDAAC_M0PE_MASK                  (0x20U)
+#define SYSMPU_RGDAAC_M0PE_SHIFT                 (5U)
+#define SYSMPU_RGDAAC_M0PE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK)
+#define SYSMPU_RGDAAC_M1UM_MASK                  (0x1C0U)
+#define SYSMPU_RGDAAC_M1UM_SHIFT                 (6U)
+#define SYSMPU_RGDAAC_M1UM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
+#define SYSMPU_RGDAAC_M1SM_MASK                  (0x600U)
+#define SYSMPU_RGDAAC_M1SM_SHIFT                 (9U)
+#define SYSMPU_RGDAAC_M1SM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
+#define SYSMPU_RGDAAC_M1PE_MASK                  (0x800U)
+#define SYSMPU_RGDAAC_M1PE_SHIFT                 (11U)
+#define SYSMPU_RGDAAC_M1PE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK)
+#define SYSMPU_RGDAAC_M2UM_MASK                  (0x7000U)
+#define SYSMPU_RGDAAC_M2UM_SHIFT                 (12U)
+#define SYSMPU_RGDAAC_M2UM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
+#define SYSMPU_RGDAAC_M2SM_MASK                  (0x18000U)
+#define SYSMPU_RGDAAC_M2SM_SHIFT                 (15U)
+#define SYSMPU_RGDAAC_M2SM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
+#define SYSMPU_RGDAAC_M2PE_MASK                  (0x20000U)
+#define SYSMPU_RGDAAC_M2PE_SHIFT                 (17U)
+#define SYSMPU_RGDAAC_M2PE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK)
+#define SYSMPU_RGDAAC_M3UM_MASK                  (0x1C0000U)
+#define SYSMPU_RGDAAC_M3UM_SHIFT                 (18U)
+#define SYSMPU_RGDAAC_M3UM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
+#define SYSMPU_RGDAAC_M3SM_MASK                  (0x600000U)
+#define SYSMPU_RGDAAC_M3SM_SHIFT                 (21U)
+#define SYSMPU_RGDAAC_M3SM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
+#define SYSMPU_RGDAAC_M3PE_MASK                  (0x800000U)
+#define SYSMPU_RGDAAC_M3PE_SHIFT                 (23U)
+#define SYSMPU_RGDAAC_M3PE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)
+#define SYSMPU_RGDAAC_M4WE_MASK                  (0x1000000U)
+#define SYSMPU_RGDAAC_M4WE_SHIFT                 (24U)
+#define SYSMPU_RGDAAC_M4WE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
+#define SYSMPU_RGDAAC_M4RE_MASK                  (0x2000000U)
+#define SYSMPU_RGDAAC_M4RE_SHIFT                 (25U)
+#define SYSMPU_RGDAAC_M4RE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
+#define SYSMPU_RGDAAC_M5WE_MASK                  (0x4000000U)
+#define SYSMPU_RGDAAC_M5WE_SHIFT                 (26U)
+#define SYSMPU_RGDAAC_M5WE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
+#define SYSMPU_RGDAAC_M5RE_MASK                  (0x8000000U)
+#define SYSMPU_RGDAAC_M5RE_SHIFT                 (27U)
+#define SYSMPU_RGDAAC_M5RE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
+#define SYSMPU_RGDAAC_M6WE_MASK                  (0x10000000U)
+#define SYSMPU_RGDAAC_M6WE_SHIFT                 (28U)
+#define SYSMPU_RGDAAC_M6WE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
+#define SYSMPU_RGDAAC_M6RE_MASK                  (0x20000000U)
+#define SYSMPU_RGDAAC_M6RE_SHIFT                 (29U)
+#define SYSMPU_RGDAAC_M6RE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
+#define SYSMPU_RGDAAC_M7WE_MASK                  (0x40000000U)
+#define SYSMPU_RGDAAC_M7WE_SHIFT                 (30U)
+#define SYSMPU_RGDAAC_M7WE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
+#define SYSMPU_RGDAAC_M7RE_MASK                  (0x80000000U)
+#define SYSMPU_RGDAAC_M7RE_SHIFT                 (31U)
+#define SYSMPU_RGDAAC_M7RE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
+
+/* The count of SYSMPU_RGDAAC */
+#define SYSMPU_RGDAAC_COUNT                      (12U)
+
+
+/*!
+ * @}
+ */ /* end of group SYSMPU_Register_Masks */
+
+
+/* SYSMPU - Peripheral instance base addresses */
+/** Peripheral SYSMPU base address */
+#define SYSMPU_BASE                              (0x4000D000u)
+/** Peripheral SYSMPU base pointer */
+#define SYSMPU                                   ((SYSMPU_Type *)SYSMPU_BASE)
+/** Array initializer of SYSMPU peripheral base addresses */
+#define SYSMPU_BASE_ADDRS                        { SYSMPU_BASE }
+/** Array initializer of SYSMPU peripheral base pointers */
+#define SYSMPU_BASE_PTRS                         { SYSMPU }
+
+/*!
+ * @}
+ */ /* end of group SYSMPU_Peripheral_Access_Layer */
+
+
 /* ----------------------------------------------------------------------------
    -- TPM Peripheral Access Layer
    ---------------------------------------------------------------------------- */
@@ -17249,6 +17252,43 @@ typedef struct {
  */ /* end of group Peripheral_access_layer */
 
 
+/* ----------------------------------------------------------------------------
+   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header
+  #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
 /* ----------------------------------------------------------------------------
    -- SDK Compatibility
    ---------------------------------------------------------------------------- */
@@ -17498,16 +17538,16 @@ typedef struct {
 #define DSPI2                                    SPI2
 #define FLEXCAN0                                 CAN0
 #define FLEXCAN1                                 CAN1
-#define GPIOA_BASE                               PTA_BASE
-#define GPIOA                                    PTA
-#define GPIOB_BASE                               PTB_BASE
-#define GPIOB                                    PTB
-#define GPIOC_BASE                               PTC_BASE
-#define GPIOC                                    PTC
-#define GPIOD_BASE                               PTD_BASE
-#define GPIOD                                    PTD
-#define GPIOE_BASE                               PTE_BASE
-#define GPIOE                                    PTE
+#define PTA_BASE                                 GPIOA_BASE
+#define PTA                                      GPIOA
+#define PTB_BASE                                 GPIOB_BASE
+#define PTB                                      GPIOB
+#define PTC_BASE                                 GPIOC_BASE
+#define PTC                                      GPIOC
+#define PTD_BASE                                 GPIOD_BASE
+#define PTD                                      GPIOD
+#define PTE_BASE                                 GPIOE_BASE
+#define PTE                                      GPIOE
 #define Watchdog_IRQn                            WDOG_EWM_IRQn
 #define Watchdog_IRQHandler                      WDOG_EWM_IRQHandler
 #define LPTimer_IRQn                             LPTMR0_IRQn
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/MK66F18_features.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/MK66F18_features.h
index 07207f3a71c..19bfac70136 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/MK66F18_features.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/MK66F18_features.h
@@ -1,14 +1,13 @@
 /*
 ** ###################################################################
 **     Version:             rev. 2.9, 2015-06-08
-**     Build:               b151217
+**     Build:               b170228
 **
 **     Abstract:
 **         Chip specific module features.
 **
-**     Copyright (c) 2015 Freescale Semiconductor, Inc.
-**     All rights reserved.
-**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
 **     Redistribution and use in source and binary forms, with or without modification,
 **     are permitted provided that the following conditions are met:
 **
@@ -19,7 +18,7 @@
 **       list of conditions and the following disclaimer in the documentation and/or
 **       other materials provided with the distribution.
 **
-**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**     o Neither the name of the copyright holder nor the names of its
 **       contributors may be used to endorse or promote products derived from this
 **       software without specific prior written permission.
 **
@@ -34,8 +33,8 @@
 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
 **
 **     Revisions:
 **     - rev. 1.0 (2013-09-02)
@@ -212,8 +211,8 @@
 #define FSL_FEATURE_SOC_MMAU_COUNT (0)
 /* @brief MMDVSQ availability on the SoC. */
 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
-/* @brief MPU availability on the SoC. */
-#define FSL_FEATURE_SOC_MPU_COUNT (1)
+/* @brief SYSMPU availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSMPU_COUNT (1)
 /* @brief MSCAN availability on the SoC. */
 #define FSL_FEATURE_SOC_MSCAN_COUNT (0)
 /* @brief MSCM availability on the SoC. */
@@ -304,6 +303,8 @@
 #define FSL_FEATURE_SOC_USB_COUNT (1)
 /* @brief USBDCD availability on the SoC. */
 #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
+/* @brief USBHS availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHS_COUNT (1)
 /* @brief USBHSDCD availability on the SoC. */
 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (1)
 /* @brief USBPHY availability on the SoC. */
@@ -376,6 +377,8 @@
 #define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (0)
 /* @brief Number of interrupt vectors. */
 #define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6)
+/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
+#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
 
 /* CMP module features */
 
@@ -437,7 +440,7 @@
 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32)
 /* @brief Total number of DMA channels on all modules. */
 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 32)
-/* @brief Has the periodic trigger capability for the triggered DMA channel 0 (register bit CHCFG0[TRIG]). */
+/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
 
 /* ENET module features */
@@ -485,6 +488,10 @@
     #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
     /* @brief Has flash cache control in MCM module. */
     #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has flash cache control in MSCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has prefetch speculation control in flash, such as kv5x. */
+    #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
     /* @brief P-Flash start address. */
     #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
     /* @brief P-Flash block count. */
@@ -499,6 +506,8 @@
     #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
     /* @brief P-Flash block swap feature. */
     #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1)
+    /* @brief P-Flash protection region count. */
+    #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
     /* @brief Has FlexNVM memory. */
     #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
     /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
@@ -551,6 +560,10 @@
     #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1)
     /* @brief Has 0x49 Erase All Blocks Unsecure command. */
     #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
+    /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
+    /* @brief Has 0x4B Erase All Execute-only Segments command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
     /* @brief Has 0x80 Program Partition command. */
     #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
     /* @brief Has 0x81 Set FlexRAM Function command. */
@@ -662,6 +675,10 @@
     #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
     /* @brief Has flash cache control in MCM module. */
     #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has flash cache control in MSCM module. */
+    #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
+    /* @brief Has prefetch speculation control in flash, such as kv5x. */
+    #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
     /* @brief P-Flash start address. */
     #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
     /* @brief P-Flash block count. */
@@ -676,6 +693,8 @@
     #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
     /* @brief P-Flash block swap feature. */
     #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1)
+    /* @brief P-Flash protection region count. */
+    #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (16)
     /* @brief Has FlexNVM memory. */
     #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1)
     /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
@@ -728,6 +747,10 @@
     #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1)
     /* @brief Has 0x49 Erase All Blocks Unsecure command. */
     #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
+    /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
+    #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
+    /* @brief Has 0x4B Erase All Execute-only Segments command. */
+    #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
     /* @brief Has 0x80 Program Partition command. */
     #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1)
     /* @brief Has 0x81 Set FlexRAM Function command. */
@@ -830,6 +853,8 @@
     ((x) == FTM3 ? (8) : (-1)))))
 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
+/* @brief Has extended deadtime value. */
+#define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0)
 /* @brief Enable pwm output for the module. */
 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0)
 /* @brief Has half-cycle reload for the module. */
@@ -839,6 +864,15 @@
 /* @brief Has reload initialization trigger. */
 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0)
 
+/* GPIO module features */
+
+/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
+#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
+/* @brief Has port input disable register (PIDR). */
+#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
+/* @brief Has dedicated interrupt vector. */
+#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
+
 /* I2C module features */
 
 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
@@ -861,6 +895,8 @@
 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
 /* @brief Has double buffering support (register S2). */
 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
+/* @brief Has double buffer enable. */
+#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0)
 
 /* SAI module features */
 
@@ -899,12 +935,14 @@
 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
 /* @brief Number of digital filters. */
 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4)
-/* @brief Has MF5 register. */
+/* @brief Has MF register. */
 #define FSL_FEATURE_LLWU_HAS_MF (1)
 /* @brief Has PF register. */
 #define FSL_FEATURE_LLWU_HAS_PF (1)
 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
+/* @brief Has no internal module wakeup flag register. */
+#define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
 /* @brief Has external pin 0 connected to LLWU device. */
 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
 /* @brief Index of port of external pin. */
@@ -1126,14 +1164,24 @@
 
 /* @brief Has process identifier support. */
 #define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (0)
+/* @brief L1 ICACHE line size in byte. */
+#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (16)
+/* @brief L1 DCACHE line size in byte. */
+#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (16)
 
 /* LPTMR module features */
 
 /* @brief Has shared interrupt handler with another LPTMR module. */
 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
+/* @brief Whether LPTMR counter is 32 bits width. */
+#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0)
+/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
+#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0)
 
 /* LPUART module features */
 
+/* @brief LPUART0 and LPUART1 has shared interrupt vector. */
+#define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0)
 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
@@ -1150,8 +1198,10 @@
 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
 /* @brief 2 bits long stop bit is available. */
 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
-/* @brief Maximal data width without parity bit. */
+/* @brief If 10-bit mode is supported. */
 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
+/* @brief If 7-bit mode is supported. */
+#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0)
 /* @brief Baud rate fine adjustment is available. */
 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
@@ -1184,12 +1234,14 @@
 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
-/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
-#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (0)
+/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
+#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
 /* @brief Has separate DMA RX and TX requests. */
 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
+/* @brief Has separate RX and TX interrupts. */
+#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
 /* @brief Has LPAURT_PARAM. */
 #define FSL_FEATURE_LPUART_HAS_PARAM (0)
 /* @brief Has LPUART_VERID. */
@@ -1239,7 +1291,7 @@
 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
 /* @brief TBD */
 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
-/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */
+/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */
 #define FSL_FEATURE_MCG_HAS_PLL (1)
 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
@@ -1270,29 +1322,6 @@
 /* @brief Reset clock mode is BLPI. */
 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
 
-/* MPU module features */
-
-/* @brief Specifies number of descriptors available. */
-#define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (12)
-/* @brief Has process identifier support. */
-#define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1)
-/* @brief Has master 0. */
-#define FSL_FEATURE_MPU_HAS_MASTER0 (1)
-/* @brief Has master 1. */
-#define FSL_FEATURE_MPU_HAS_MASTER1 (1)
-/* @brief Has master 2. */
-#define FSL_FEATURE_MPU_HAS_MASTER2 (1)
-/* @brief Has master 3. */
-#define FSL_FEATURE_MPU_HAS_MASTER3 (1)
-/* @brief Has master 4. */
-#define FSL_FEATURE_MPU_HAS_MASTER4 (1)
-/* @brief Has master 5. */
-#define FSL_FEATURE_MPU_HAS_MASTER5 (1)
-/* @brief Has master 6. */
-#define FSL_FEATURE_MPU_HAS_MASTER6 (1)
-/* @brief Has master 7. */
-#define FSL_FEATURE_MPU_HAS_MASTER7 (0)
-
 /* interrupt module features */
 
 /* @brief Lowest interrupt request number. */
@@ -1390,20 +1419,13 @@
 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
 /* @brief Has dedicated interrupt vector. */
 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
+/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
+#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0)
 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */
 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
 
-/* GPIO module features */
-
-/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
-#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
-/* @brief Has port input disable register (PIDR). */
-#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
-/* @brief Has dedicated interrupt vector. */
-#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
-
 /* RCM module features */
 
 /* @brief Has Loss-of-Lock Reset support. */
@@ -1746,6 +1768,12 @@
 #define FSL_FEATURE_SMC_HAS_PARAM (0)
 /* @brief Has SMC_VERID. */
 #define FSL_FEATURE_SMC_HAS_VERID (0)
+/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
+#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1)
+/* @brief Has tamper reset (register bit SRS[TAMPER]). */
+#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
+/* @brief Has security violation reset (register bit SRS[SECVIO]). */
+#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
 
 /* DSPI module features */
 
@@ -1769,6 +1797,17 @@
 /* @brief Has separate DMA RX and TX requests. */
 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
 
+/* SYSMPU module features */
+
+/* @brief Specifies number of descriptors available. */
+#define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (12)
+/* @brief Has process identifier support. */
+#define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1)
+/* @brief Total number of MPU slave. */
+#define FSL_FEATURE_SYSMPU_SLAVE_COUNT (5)
+/* @brief Total number of MPU master. */
+#define FSL_FEATURE_SYSMPU_MASTER_COUNT (7)
+
 /* SysTick module features */
 
 /* @brief Systick has external reference clock. */
@@ -1796,12 +1835,20 @@
 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
 /* @brief Has external trigger selection. */
 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
-/* @brief Has TPM_COMBINE. */
+/* @brief Has TPM_COMBINE register. */
 #define FSL_FEATURE_TPM_HAS_COMBINE (1)
-/* @brief Has TPM_FILTER. */
+/* @brief Whether COMBINE register has effect. */
+#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1)
+/* @brief Has TPM_POL. */
+#define FSL_FEATURE_TPM_HAS_POL (1)
+/* @brief Has TPM_FILTER register. */
 #define FSL_FEATURE_TPM_HAS_FILTER (1)
-/* @brief Has TPM_QDCTRL. */
+/* @brief Whether FILTER register has effect. */
+#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1)
+/* @brief Has TPM_QDCTRL register. */
 #define FSL_FEATURE_TPM_HAS_QDCTRL (1)
+/* @brief Whether QDCTRL register has effect. */
+#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1)
 
 /* TSI module features */
 
@@ -1828,8 +1875,8 @@
 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
 /* @brief 2 bits long stop bit is available. */
 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
-/* @brief Maximal data width without parity bit. */
-#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
+/* @brief If 10-bit mode is supported. */
+#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1)
 /* @brief Baud rate fine adjustment is available. */
 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
@@ -1881,6 +1928,8 @@
 
 /* USB module features */
 
+/* @brief KHCI module instance count */
+#define FSL_FEATURE_USB_KHCI_COUNT (1)
 /* @brief HOST mode enabled */
 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
 /* @brief OTG mode enabled */
@@ -1900,6 +1949,8 @@
 
 /* USBHS module features */
 
+/* @brief EHCI module instance count */
+#define FSL_FEATURE_USBHS_EHCI_COUNT (1)
 /* @brief Number of endpoints supported */
 #define FSL_FEATURE_USBHS_ENDPT_COUNT (8)
 
@@ -1909,7 +1960,7 @@
 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
-/* @brief Describes the set of SC[MODE_LV] bitfield values */
+/* @brief If high/low buffer mode supported */
 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
 /* @brief Module has also low reference (registers VREFL/VREFH) */
 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/MK66FN2M0xxx18.sct b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/MK66FN2M0xxx18.sct
index c19ce975ff1..a3b5b01f763 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/MK66FN2M0xxx18.sct
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/MK66FN2M0xxx18.sct
@@ -7,14 +7,13 @@
 **     Compiler:            Keil ARM C/C++ Compiler
 **     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015
 **     Version:             rev. 3.0, 2015-03-25
-**     Build:               b160406
+**     Build:               b170214
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
-**     Copyright (c) 2016 Freescale Semiconductor, Inc.
-**     All rights reserved.
-**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
 **     Redistribution and use in source and binary forms, with or without modification,
 **     are permitted provided that the following conditions are met:
 **
@@ -25,7 +24,7 @@
 **       list of conditions and the following disclaimer in the documentation and/or
 **       other materials provided with the distribution.
 **
-**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**     o Neither the name of the copyright holder nor the names of its
 **       contributors may be used to endorse or promote products derived from this
 **       software without specific prior written permission.
 **
@@ -40,8 +39,8 @@
 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
 **
 ** ###################################################################
 */
@@ -53,14 +52,22 @@
   #define __ram_vector_table_size__    0x00000000
 #endif
 
-#define m_interrupts_start             0x00000000
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x200000
+#endif
+
+#define m_interrupts_start             MBED_APP_START
 #define m_interrupts_size              0x00000400
 
-#define m_flash_config_start           0x00000400
+#define m_flash_config_start           MBED_APP_START + 0x400
 #define m_flash_config_size            0x00000010
 
-#define m_text_start                   0x00000410
-#define m_text_size                    0x001FFBF0
+#define m_text_start                   MBED_APP_START + 0x410
+#define m_text_size                    MBED_APP_SIZE - 0x410
 
 #define m_interrupts_ram_start         0x1FFF0000
 #define m_interrupts_ram_size          __ram_vector_table_size__
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/startup_MK66F18.S b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/startup_MK66F18.S
index c7b44f7b247..3782b2f0a71 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/startup_MK66F18.S
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/startup_MK66F18.S
@@ -4,12 +4,11 @@
 ; *            MK66F18
 ; *  @version: 3.0
 ; *  @date:    2015-3-25
-; *  @build:   b151210
+; *  @build:   b170112
 ; * ---------------------------------------------------------------------------------------
 ; *
-; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
-; * All rights reserved.
-; *
+; * Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc.
+; * Copyright 2016 - 2017 NXP
 ; * Redistribution and use in source and binary forms, with or without modification,
 ; * are permitted provided that the following conditions are met:
 ; *
@@ -20,7 +19,7 @@
 ; *   list of conditions and the following disclaimer in the documentation and/or
 ; *   other materials provided with the distribution.
 ; *
-; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+; * o Neither the name of the copyright holder nor the names of its
 ; *   contributors may be used to endorse or promote products derived from this
 ; *   software without specific prior written permission.
 ; *
@@ -483,6 +482,8 @@ Reset_Handler   PROC
                 LDR     R0, =0xE000ED08
                 LDR     R1, =__Vectors
                 STR     R1, [R0]
+                LDR     R2, [R1]
+                MSR     MSP, R2
                 LDR     R0, =SystemInit
                 BLX     R0
                 CPSIE   i               ; Unmask interrupts
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/MK66FN2M0xxx18.ld b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/MK66FN2M0xxx18.ld
index 4145ee2c690..6cf07e2c19c 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/MK66FN2M0xxx18.ld
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/MK66FN2M0xxx18.ld
@@ -6,14 +6,13 @@
 **     Compiler:            GNU C Compiler
 **     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015
 **     Version:             rev. 3.0, 2015-03-25
-**     Build:               b151217
+**     Build:               b170214
 **
 **     Abstract:
 **         Linker file for the GNU C Compiler
 **
-**     Copyright (c) 2015 Freescale Semiconductor, Inc.
-**     All rights reserved.
-**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
 **     Redistribution and use in source and binary forms, with or without modification,
 **     are permitted provided that the following conditions are met:
 **
@@ -24,7 +23,7 @@
 **       list of conditions and the following disclaimer in the documentation and/or
 **       other materials provided with the distribution.
 **
-**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**     o Neither the name of the copyright holder nor the names of its
 **       contributors may be used to endorse or promote products derived from this
 **       software without specific prior written permission.
 **
@@ -39,8 +38,8 @@
 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
 **
 ** ###################################################################
 */
@@ -60,6 +59,14 @@ __stack_size__ = 0x400;
  * heap and the page heap in uVisor applications. */
 __heap_size__ = 0x6000;
 
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x200000
+#endif
+
 HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
 STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
 M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;
@@ -67,9 +74,9 @@ M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;
 /* Specify the memory areas */
 MEMORY
 {
-  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400
-  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010
-  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x001FFBF0
+  m_interrupts          (RX)  : ORIGIN = MBED_APP_START, LENGTH = 0x400
+  m_flash_config        (RX)  : ORIGIN = MBED_APP_START + 0x400, LENGTH = 0x10
+  m_text                (RX)  : ORIGIN = MBED_APP_START + 0x410, LENGTH = MBED_APP_SIZE - 0x410
   m_data                (RW)  : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
   m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00030000
 }
@@ -212,7 +219,6 @@ SECTIONS
   text_end = ORIGIN(m_text) + LENGTH(m_text);
   ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
 
-  USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800;
   /* Uninitialized data section */
   .bss :
   {
@@ -222,9 +228,6 @@ SECTIONS
     __bss_start__ = .;
     *(.bss)
     *(.bss*)
-    . = ALIGN(512);
-    USB_RAM_START = .;
-    . += USB_RAM_GAP;
     *(COMMON)
     . = ALIGN(4);
     __bss_end__ = .;
@@ -248,17 +251,6 @@ SECTIONS
     . += STACK_SIZE;
   } > m_data_2
 
-  m_usb_bdt USB_RAM_START (NOLOAD) :
-  {
-    *(m_usb_bdt)
-    USB_RAM_BDT_END = .;
-  }
-
-  m_usb_global USB_RAM_BDT_END (NOLOAD) :
-  {
-    *(m_usb_global)
-  }
-
   /* Initializes stack on the end of block */
   __StackTop   = ORIGIN(m_data_2) + LENGTH(m_data_2);
   __StackLimit = __StackTop - STACK_SIZE;
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/startup_MK66F18.S b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/startup_MK66F18.S
index 5a03e0326d8..ceb9bbf6c30 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/startup_MK66F18.S
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/startup_MK66F18.S
@@ -4,12 +4,11 @@
 /*            MK66F18                                                                     */
 /*  @version: 3.0                                                                         */
 /*  @date:    2015-3-25                                                                   */
-/*  @build:   b151210                                                                     */
+/*  @build:   b170112                                                                     */
 /* ---------------------------------------------------------------------------------------*/
 /*                                                                                        */
-/* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.                              */
-/* All rights reserved.                                                                   */
-/*                                                                                        */
+/* Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc.                               */
+/* Copyright 2016 - 2017 NXP                                                              */
 /* Redistribution and use in source and binary forms, with or without modification,       */
 /* are permitted provided that the following conditions are met:                          */
 /*                                                                                        */
@@ -20,7 +19,7 @@
 /*   list of conditions and the following disclaimer in the documentation and/or          */
 /*   other materials provided with the distribution.                                      */
 /*                                                                                        */
-/* o Neither the name of Freescale Semiconductor, Inc. nor the names of its               */
+/* o Neither the name of the copyright holder nor the names of its                        */
 /*   contributors may be used to endorse or promote products derived from this            */
 /*   software without specific prior written permission.                                  */
 /*                                                                                        */
@@ -328,6 +327,8 @@ Reset_Handler:
     ldr     r0, =VTOR
     ldr     r1, =__isr_vector
     str     r1, [r0]
+    ldr     r2, [r1]
+    msr     msp, r2
 #ifndef __NO_SYSTEM_INIT
     ldr   r0,=SystemInit
     blx   r0
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_IAR/MK66FN2M0xxx18.icf b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_IAR/MK66FN2M0xxx18.icf
index fe0daadc6ae..54de75b7bd4 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_IAR/MK66FN2M0xxx18.icf
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_IAR/MK66FN2M0xxx18.icf
@@ -6,14 +6,13 @@
 **     Compiler:            IAR ANSI C/C++ Compiler for ARM
 **     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015
 **     Version:             rev. 3.0, 2015-03-25
-**     Build:               b151009
+**     Build:               b170214
 **
 **     Abstract:
 **         Linker file for the IAR ANSI C/C++ Compiler for ARM
 **
-**     Copyright (c) 2015 Freescale Semiconductor, Inc.
-**     All rights reserved.
-**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
 **     Redistribution and use in source and binary forms, with or without modification,
 **     are permitted provided that the following conditions are met:
 **
@@ -24,7 +23,7 @@
 **       list of conditions and the following disclaimer in the documentation and/or
 **       other materials provided with the distribution.
 **
-**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**     o Neither the name of the copyright holder nor the names of its
 **       contributors may be used to endorse or promote products derived from this
 **       software without specific prior written permission.
 **
@@ -39,8 +38,8 @@
 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
 **
 ** ###################################################################
 */
@@ -50,17 +49,25 @@ define symbol __ram_vector_table__ = 1;
 define symbol __stack_size__=0x8000;
 define symbol __heap_size__=0x10000;
 
+if (!isdefinedsymbol(MBED_APP_START)) {
+    define symbol MBED_APP_START = 0;
+}
+
+if (!isdefinedsymbol(MBED_APP_SIZE)) {
+    define symbol MBED_APP_SIZE = 0x200000;
+}
+
 define symbol __ram_vector_table_size__ =  isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
 define symbol __ram_vector_table_offset__ =  isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;
 
-define symbol m_interrupts_start       = 0x00000000;
-define symbol m_interrupts_end         = 0x000003FF;
+define symbol m_interrupts_start       = MBED_APP_START;
+define symbol m_interrupts_end         = MBED_APP_START + 0x3FF;
 
-define symbol m_flash_config_start     = 0x00000400;
-define symbol m_flash_config_end       = 0x0000040F;
+define symbol m_flash_config_start     = MBED_APP_START + 0x400;
+define symbol m_flash_config_end       = MBED_APP_START + 0x40F;
 
-define symbol m_text_start             = 0x00000410;
-define symbol m_text_end               = 0x001FFFFF;
+define symbol m_text_start             = MBED_APP_START + 0x410;
+define symbol m_text_end               = MBED_APP_START + MBED_APP_SIZE - 1;
 
 define symbol m_interrupts_ram_start   = 0x1FFF0000;
 define symbol m_interrupts_ram_end     = 0x1FFF0000 + __ram_vector_table_offset__;
@@ -113,4 +120,3 @@ place in DATA_region                        { block ZI };
 place in DATA_region                        { last block HEAP };
 place in CSTACK_region                      { block CSTACK };
 place in m_interrupts_ram_region            { section m_interrupts_ram };
-
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_IAR/startup_MK66F18.S b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_IAR/startup_MK66F18.S
index 4a5928de9f2..47036fbd89f 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_IAR/startup_MK66F18.S
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_IAR/startup_MK66F18.S
@@ -4,12 +4,11 @@
 ;            MK66F18
 ;  @version: 3.0
 ;  @date:    2015-3-25
-;  @build:   b151210
+;  @build:   b170112
 ; ---------------------------------------------------------------------------------------
 ;
-; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
-; All rights reserved.
-;
+; Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc.
+; Copyright 2016 - 2017 NXP
 ; Redistribution and use in source and binary forms, with or without modification,
 ; are permitted provided that the following conditions are met:
 ;
@@ -20,7 +19,7 @@
 ;   list of conditions and the following disclaimer in the documentation and/or
 ;   other materials provided with the distribution.
 ;
-; o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+; o Neither the name of the copyright holder nor the names of its
 ;   contributors may be used to endorse or promote products derived from this
 ;   software without specific prior written permission.
 ;
@@ -355,6 +354,8 @@ Reset_Handler
         LDR     R0, =0xE000ED08
         LDR     R1, =__vector_table
         STR     R1, [R0]
+        LDR     R2, [R1]
+        MSR     MSP, R2
         LDR     R0, =SystemInit
         BLX     R0
         CPSIE   I               ; Unmask interrupts
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/fsl_device_registers.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/fsl_device_registers.h
index f7a122fcdb6..9438c67fa13 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/fsl_device_registers.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/fsl_device_registers.h
@@ -1,7 +1,6 @@
 /*
- * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
+ * Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 - 2017 NXP
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *
@@ -12,7 +11,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -26,6 +25,7 @@
  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
  */
 
 #ifndef __FSL_DEVICE_REGISTERS_H__
@@ -36,7 +36,7 @@
  *
  * The CPU macro should be declared in the project or makefile.
  */
-#if (defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
+#if (defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VLQ18) || \
     defined(CPU_MK66FX1M0VMD18))
 
 #define K66F18_SERIES
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/system_MK66F18.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/system_MK66F18.c
index 04996c713f3..a0a09bbc4d4 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/system_MK66F18.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/system_MK66F18.c
@@ -9,19 +9,19 @@
 **                          Freescale C/C++ for Embedded ARM
 **                          GNU C Compiler
 **                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
 **
 **     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015
 **     Version:             rev. 3.0, 2015-03-25
-**     Build:               b151216
+**     Build:               b170112
 **
 **     Abstract:
 **         Provides a system configuration function and a global variable that
 **         contains the system frequency. It configures the device and initializes
 **         the oscillator (PLL) that is part of the microcontroller device.
 **
-**     Copyright (c) 2015 Freescale Semiconductor, Inc.
-**     All rights reserved.
-**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016 - 2017 NXP
 **     Redistribution and use in source and binary forms, with or without modification,
 **     are permitted provided that the following conditions are met:
 **
@@ -32,7 +32,7 @@
 **       list of conditions and the following disclaimer in the documentation and/or
 **       other materials provided with the distribution.
 **
-**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**     o Neither the name of the copyright holder nor the names of its
 **       contributors may be used to endorse or promote products derived from this
 **       software without specific prior written permission.
 **
@@ -47,8 +47,8 @@
 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
 **
 **     Revisions:
 **     - rev. 1.0 (2013-09-02)
@@ -213,7 +213,6 @@ void SystemCoreClockUpdate (void) {
             Divider *= 0x04U;
           } else if ((USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) == USBPHY_ANACTRL_PFD_CLK_SEL(2)) {
             Divider *= 0x02U;
-          } else {
           }
           MCGOUTClock = (uint32_t)(480000000 / Divider);
           MCGOUTClock *= 18;
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/system_MK66F18.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/system_MK66F18.h
index 3e8652e09a7..3bbd4bf70d6 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/system_MK66F18.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/system_MK66F18.h
@@ -9,19 +9,19 @@
 **                          Freescale C/C++ for Embedded ARM
 **                          GNU C Compiler
 **                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
 **
 **     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015
 **     Version:             rev. 3.0, 2015-03-25
-**     Build:               b151216
+**     Build:               b170112
 **
 **     Abstract:
 **         Provides a system configuration function and a global variable that
 **         contains the system frequency. It configures the device and initializes
 **         the oscillator (PLL) that is part of the microcontroller device.
 **
-**     Copyright (c) 2015 Freescale Semiconductor, Inc.
-**     All rights reserved.
-**
+**     Copyright (c) 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016 - 2017 NXP
 **     Redistribution and use in source and binary forms, with or without modification,
 **     are permitted provided that the following conditions are met:
 **
@@ -32,7 +32,7 @@
 **       list of conditions and the following disclaimer in the documentation and/or
 **       other materials provided with the distribution.
 **
-**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**     o Neither the name of the copyright holder nor the names of its
 **       contributors may be used to endorse or promote products derived from this
 **       software without specific prior written permission.
 **
@@ -47,8 +47,8 @@
 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
 **
 **     Revisions:
 **     - rev. 1.0 (2013-09-02)
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_adc16.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_adc16.c
index 8f1aa77b2ea..0af6a4443e9 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_adc16.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_adc16.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -46,8 +46,10 @@ static uint32_t ADC16_GetInstance(ADC_Type *base);
 /*! @brief Pointers to ADC16 bases for each instance. */
 static ADC_Type *const s_adc16Bases[] = ADC_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to ADC16 clocks for each instance. */
-const clock_ip_name_t s_adc16Clocks[] = ADC16_CLOCKS;
+static const clock_ip_name_t s_adc16Clocks[] = ADC16_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
@@ -57,7 +59,7 @@ static uint32_t ADC16_GetInstance(ADC_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_ADC16_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_adc16Bases); instance++)
     {
         if (s_adc16Bases[instance] == base)
         {
@@ -65,7 +67,7 @@ static uint32_t ADC16_GetInstance(ADC_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_ADC16_COUNT);
+    assert(instance < ARRAY_SIZE(s_adc16Bases));
 
     return instance;
 }
@@ -76,8 +78,10 @@ void ADC16_Init(ADC_Type *base, const adc16_config_t *config)
 
     uint32_t tmp32;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the clock. */
     CLOCK_EnableClock(s_adc16Clocks[ADC16_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* ADCx_CFG1. */
     tmp32 = ADC_CFG1_ADICLK(config->clockSource) | ADC_CFG1_MODE(config->resolution);
@@ -126,8 +130,10 @@ void ADC16_Init(ADC_Type *base, const adc16_config_t *config)
 
 void ADC16_Deinit(ADC_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable the clock. */
     CLOCK_DisableClock(s_adc16Clocks[ADC16_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void ADC16_GetDefaultConfig(adc16_config_t *config)
@@ -149,7 +155,7 @@ void ADC16_GetDefaultConfig(adc16_config_t *config)
 status_t ADC16_DoAutoCalibration(ADC_Type *base)
 {
     bool bHWTrigger = false;
-    uint32_t tmp32;
+    volatile uint32_t tmp32; /* 'volatile' here is for the dummy read of ADCx_R[0] register. */
     status_t status = kStatus_Success;
 
     /* The calibration would be failed when in hardwar mode.
@@ -171,6 +177,7 @@ status_t ADC16_DoAutoCalibration(ADC_Type *base)
             break;
         }
     }
+    tmp32 = base->R[0]; /* Dummy read to clear COCO caused by calibration. */
 
     /* Restore the hardware trigger setting if it was enabled before. */
     if (bHWTrigger)
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_adc16.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_adc16.h
index c6b5bc0d1ae..ea62c55fee6 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_adc16.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_adc16.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -38,7 +38,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -74,7 +73,7 @@ enum _adc16_status_flags
  * @brief Channel multiplexer mode for each channel.
  *
  * For some ADC16 channels, there are two pin selections in channel multiplexer. For example, ADC0_SE4a and ADC0_SE4b
- * are the different channels but share the same channel number.
+ * are the different channels that share the same channel number.
  */
 typedef enum _adc_channel_mux_mode
 {
@@ -104,7 +103,7 @@ typedef enum _adc16_resolution
     kADC16_Resolution12or13Bit = 1U, /*!< Single End 12-bit or Differential Sample 13-bit. */
     kADC16_Resolution10or11Bit = 2U, /*!< Single End 10-bit or Differential Sample 11-bit. */
 
-    /* This group of enumeration is for public user. */
+    /* This group of enumeration is for a public user. */
     kADC16_ResolutionSE8Bit = kADC16_Resolution8or9Bit,    /*!< Single End 8-bit. */
     kADC16_ResolutionSE12Bit = kADC16_Resolution12or13Bit, /*!< Single End 12-bit. */
     kADC16_ResolutionSE10Bit = kADC16_Resolution10or11Bit, /*!< Single End 10-bit. */
@@ -203,7 +202,7 @@ typedef enum _adc16_pga_gain
 #endif /* FSL_FEATURE_ADC16_HAS_PGA */
 
 /*!
- * @brief ADC16 converter configuration .
+ * @brief ADC16 converter configuration.
  */
 typedef struct _adc16_config
 {
@@ -219,7 +218,7 @@ typedef struct _adc16_config
 } adc16_config_t;
 
 /*!
- * @brief ADC16 Hardware compare configuration.
+ * @brief ADC16 Hardware comparison configuration.
  */
 typedef struct _adc16_hardware_compare_config
 {
@@ -237,7 +236,7 @@ typedef struct _adc16_channel_config
     uint32_t channelNumber;                    /*!< Setting the conversion channel number. The available range is 0-31.
                                                     See channel connection information for each chip in Reference
                                                     Manual document. */
-    bool enableInterruptOnConversionCompleted; /*!< Generate a interrupt request once the conversion is completed. */
+    bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */
 #if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
     bool enableDifferentialConversion; /*!< Using Differential sample mode. */
 #endif                                 /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
@@ -296,9 +295,9 @@ void ADC16_Init(ADC_Type *base, const adc16_config_t *config);
 void ADC16_Deinit(ADC_Type *base);
 
 /*!
- * @brief Gets an available pre-defined settings for converter's configuration.
+ * @brief Gets an available pre-defined settings for the converter's configuration.
  *
- * This function initializes the converter configuration structure with an available settings. The default values are:
+ * This function initializes the converter configuration structure with available settings. The default values are as follows.
  * @code
  *   config->referenceVoltageSource     = kADC16_ReferenceVoltageSourceVref;
  *   config->clockSource                = kADC16_ClockSourceAsynchronousClock;
@@ -310,7 +309,7 @@ void ADC16_Deinit(ADC_Type *base);
  *   config->enableLowPower             = false;
  *   config->enableContinuousConversion = false;
  * @endcode
- * @param config Pointer to configuration structure.
+ * @param config Pointer to the configuration structure.
  */
 void ADC16_GetDefaultConfig(adc16_config_t *config);
 
@@ -318,15 +317,15 @@ void ADC16_GetDefaultConfig(adc16_config_t *config);
 /*!
  * @brief  Automates the hardware calibration.
  *
- * This auto calibration helps to adjust the plus/minus side gain automatically on the converter's working situation.
+ * This auto calibration helps to adjust the plus/minus side gain automatically.
  * Execute the calibration before using the converter. Note that the hardware trigger should be used
- * during calibration.
+ * during the calibration.
  *
  * @param  base ADC16 peripheral base address.
  *
  * @return                 Execution status.
  * @retval kStatus_Success Calibration is done successfully.
- * @retval kStatus_Fail    Calibration is failed.
+ * @retval kStatus_Fail    Calibration has failed.
  */
 status_t ADC16_DoAutoCalibration(ADC_Type *base);
 #endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
@@ -350,16 +349,16 @@ static inline void ADC16_SetOffsetValue(ADC_Type *base, int16_t value)
 /* @} */
 
 /*!
- * @name Advanced Feature
+ * @name Advanced Features
  * @{
  */
 
 #if defined(FSL_FEATURE_ADC16_HAS_DMA) && FSL_FEATURE_ADC16_HAS_DMA
 /*!
- * @brief Enables generating the DMA trigger when conversion is completed.
+ * @brief Enables generating the DMA trigger when the conversion is complete.
  *
  * @param base   ADC16 peripheral base address.
- * @param enable Switcher of DMA feature. "true" means to enable, "false" means not.
+ * @param enable Switcher of the DMA feature. "true" means enabled, "false" means not enabled.
  */
 static inline void ADC16_EnableDMA(ADC_Type *base, bool enable)
 {
@@ -378,7 +377,7 @@ static inline void ADC16_EnableDMA(ADC_Type *base, bool enable)
  * @brief Enables the hardware trigger mode.
  *
  * @param base   ADC16 peripheral base address.
- * @param enable Switcher of hardware trigger feature. "true" means to enable, "false" means not.
+ * @param enable Switcher of the hardware trigger feature. "true" means enabled, "false" means not enabled.
  */
 static inline void ADC16_EnableHardwareTrigger(ADC_Type *base, bool enable)
 {
@@ -408,13 +407,12 @@ void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode);
 /*!
  * @brief Configures the hardware compare mode.
  *
- * The hardware compare mode provides a way to process the conversion result automatically by hardware. Only the result
- * in
- * compare range is available. To compare the range, see "adc16_hardware_compare_mode_t", or the reference
- * manual document for more detailed information.
+ * The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the result
+ * in the compare range is available. To compare the range, see "adc16_hardware_compare_mode_t" or the appopriate reference
+ * manual for more information.
  *
  * @param base     ADC16 peripheral base address.
- * @param config   Pointer to "adc16_hardware_compare_config_t" structure. Passing "NULL" is to disable the feature.
+ * @param config   Pointer to the "adc16_hardware_compare_config_t" structure. Passing "NULL" disables the feature.
  */
 void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config);
 
@@ -422,21 +420,21 @@ void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare
 /*!
  * @brief Sets the hardware average mode.
  *
- * Hardware average mode provides a way to process the conversion result automatically by hardware. The multiple
- * conversion results are accumulated and averaged internally. This aids  reading results.
+ * The hardware average mode provides a way to process the conversion result automatically by using hardware. The multiple
+ * conversion results are accumulated and averaged internally making them easier to read.
  *
  * @param base  ADC16 peripheral base address.
- * @param mode  Setting hardware average mode. See "adc16_hardware_average_mode_t".
+ * @param mode  Setting the hardware average mode. See "adc16_hardware_average_mode_t".
  */
 void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode);
 #endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
 
 #if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
 /*!
- * @brief Configures the PGA for converter's front end.
+ * @brief Configures the PGA for the converter's front end.
  *
  * @param base    ADC16 peripheral base address.
- * @param config  Pointer to "adc16_pga_config_t" structure. Passing "NULL" is to disable the feature.
+ * @param config  Pointer to the "adc16_pga_config_t" structure. Passing "NULL" disables the feature.
  */
 void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config);
 #endif /* FSL_FEATURE_ADC16_HAS_PGA */
@@ -468,26 +466,26 @@ void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask);
 /*!
  * @brief Configures the conversion channel.
  *
- * This operation triggers the conversion if in software trigger mode. When in hardware trigger mode, this API
+ * This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API
  * configures the channel while the external trigger source helps to trigger the conversion.
  *
  * Note that the "Channel Group" has a detailed description.
- * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC can have more than one
- * group of status and control register, one for each conversion. The channel group parameter indicates which group of
- * registers are used channel group 0 is for Group A registers and channel group 1 is for Group B registers.  The
+ * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one
+ * group of status and control registers, one for each conversion. The channel group parameter indicates which group of
+ * registers are used, for example, channel group 0 is for Group A registers and channel group 1 is for Group B registers. The
  * channel groups are used in a "ping-pong" approach to control the ADC operation.  At any point, only one of
- * the channel groups is actively controlling ADC conversions. Channel group 0 is used for both software and hardware
- * trigger modes of operation. Channel groups 1 and greater indicate potentially multiple channel group registers for
- * use only in hardware trigger mode. See the chip configuration information in the MCU reference manual about the
- * number of SC1n registers (channel groups) specific to this device.  None of the channel groups 1 or greater are used
- * for software trigger operation and therefore writes to these channel groups do not initiate a new conversion.
- * Updating channel group 0 while a different channel group is actively controlling a conversion is allowed and
+ * the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and hardware
+ * trigger modes. Channel group 1 and greater indicates multiple channel group registers for
+ * use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual for the
+ * number of SC1n registers (channel groups) specific to this device.  Channel group 1 or greater are not used
+ * for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion.
+ * Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and
  * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a
  * conversion aborts the current conversion.
  *
  * @param base          ADC16 peripheral base address.
  * @param channelGroup  Channel group index.
- * @param config        Pointer to "adc16_channel_config_t" structure for conversion channel.
+ * @param config        Pointer to the "adc16_channel_config_t" structure for the conversion channel.
  */
 void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config);
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_clock.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_clock.c
index bffbb4a3125..d75d97ff4f1 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_clock.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_clock.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016 - 2017 , NXP
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
@@ -12,7 +13,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -28,7 +29,6 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "fsl_common.h"
 #include "fsl_clock.h"
 
 /*******************************************************************************
@@ -124,7 +124,6 @@ static uint32_t s_extPllFreq = 0U;
 
 /* External XTAL0 (OSC0) clock frequency. */
 uint32_t g_xtal0Freq;
-
 /* External XTAL32K clock frequency. */
 uint32_t g_xtal32Freq;
 
@@ -195,17 +194,36 @@ static uint32_t CLOCK_GetPll0RefFreq(void);
  */
 static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq);
 
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN
 /*!
  * @brief Delay function to wait FLL stable.
  *
  * Delay function to wait FLL stable in FEI mode or FEE mode, should wait at least
  * 1ms. Every time changes FLL setting, should wait this time for FLL stable.
  */
-static void CLOCK_FllStableDelay(void);
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
+void CLOCK_FllStableDelay(void)
+{
+    /*
+       Should wait at least 1ms. Because in these modes, the core clock is 100MHz
+       at most, so this function could obtain the 1ms delay.
+     */
+    volatile uint32_t i = 30000U;
+    while (i--)
+    {
+        __NOP();
+    }
+}
+#else  /* With MCG_USER_CONFIG_FLL_STABLE_DELAY_EN defined. */
+/* Once user defines the MCG_USER_CONFIG_FLL_STABLE_DELAY_EN to use their own delay function, he has to
+ * create his own CLOCK_FllStableDelay() function in application code. Since the clock functions in this
+ * file would call the CLOCK_FllStableDelay() regardness how it is defined.
+ */
+extern void CLOCK_FllStableDelay(void);
+#endif /* MCG_USER_CONFIG_FLL_STABLE_DELAY_EN */
 
 static uint32_t CLOCK_GetMcgExtClkFreq(void)
 {
@@ -342,19 +360,6 @@ static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq)
     return range;
 }
 
-static void CLOCK_FllStableDelay(void)
-{
-    /*
-       Should wait at least 1ms. Because in these modes, the core clock is 100MHz
-       at most, so this function could obtain the 1ms delay.
-     */
-    volatile uint32_t i = 30000U;
-    while (i--)
-    {
-        __NOP();
-    }
-}
-
 uint32_t CLOCK_GetOsc0ErClkUndivFreq(void)
 {
     if (OSC0->CR & OSC_CR_ERCLKEN_MASK)
@@ -419,6 +424,9 @@ uint32_t CLOCK_GetPllFllSelClkFreq(void)
         case 1U: /* PLL. */
             freq = CLOCK_GetPll0Freq();
             break;
+        case 2U: /* USB1 PFD */
+            freq = CLOCK_GetExtPllFreq();
+            break;
         case 3U: /* MCG IRC48M. */
             freq = MCG_INTERNAL_IRC_48M;
             break;
@@ -572,8 +580,31 @@ bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
 }
 
 bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
+{
+    /* Source and freq are not used for USB HS. */
+    src = src;
+    freq = freq;
+
+    SIM->SCGC3 |= SIM_SCGC3_USBHS_MASK;
+
+    SIM->USBPHYCTL = ((SIM->USBPHYCTL & ~(SIM_USBPHYCTL_USB3VOUTTRG_MASK)) | SIM_USBPHYCTL_USB3VOUTTRG(6U) /* 3.310V */
+                      | SIM_USBPHYCTL_USBVREGSEL_MASK); /* VREG_IN1 */
+
+    USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* Enable USB clock output from USB PHY PLL */
+
+    return true;
+}
+
+void CLOCK_DisableUsbhs0Clock(void)
+{
+    USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* Disable USB clock output from USB PHY PLL */
+    SIM->SCGC3 &= ~SIM_SCGC3_USBHS_MASK;
+}
+
+bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
 {
     volatile uint32_t i;
+    uint32_t phyPllDiv = 0U;
 
     /*
      * In order to bring up the internal 480MHz USB PLL clock, should make sure:
@@ -584,12 +615,28 @@ bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
     assert(!(MCG->C2 & MCG_C2_IRCS_MASK));
     assert(OSC0->CR & OSC_CR_ERCLKEN_MASK);
 
+    if (24000000U == freq)
+    {
+        phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(0U);
+    }
+    else if (16000000U == freq)
+    {
+        phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(1U);
+    }
+    else if (12000000U == freq)
+    {
+        phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(2U);
+    }
+    else
+    {
+        return false;
+    }
+
     /* Source and freq are not used for USB HS. */
     src = src;
-    freq = freq;
 
+    SIM->SCGC3 |= SIM_SCGC3_USBHSPHY_MASK;
     SIM->SOPT2 |= SIM_SOPT2_USBREGEN_MASK;
-    SIM->SCGC3 |= (SIM_SCGC3_USBHS_MASK | SIM_SCGC3_USBHSPHY_MASK);
 
     i = 500000U;
     while (i--)
@@ -597,12 +644,66 @@ bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
         __NOP();
     }
 
-    SIM->USBPHYCTL = ((SIM->USBPHYCTL & ~(SIM_USBPHYCTL_USB3VOUTTRG_MASK)) | SIM_USBPHYCTL_USB3VOUTTRG(6U) /* 3.310V */
-                      | SIM_USBPHYCTL_USBVREGSEL_MASK); /* VREG_IN1 */
+    USBPHY->TRIM_OVERRIDE_EN = 0x01U;                 /* Override the trim. */
+    USBPHY->CTRL &= ~USBPHY_CTRL_SFTRST_MASK;         /* release PHY from reset */
+    USBPHY->PLL_SIC |= USBPHY_PLL_SIC_PLL_POWER_MASK; /* power up PLL */
+    USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) | phyPllDiv;
+    USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_BYPASS_MASK; /* Clear bypass bit */
+    USBPHY->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK;          /* Clear to 0U to run clocks */
+
+    /* Wait for lock. */
+    while (!(USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK))
+    {
+    }
 
     return true;
 }
 
+void CLOCK_DisableUsbhs0PhyPllClock(void)
+{
+    USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK;          /* Set to 1U to gate clocks */
+    USBPHY->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; /* Power down PLL */
+    SIM->SOPT2 &= ~SIM_SOPT2_USBREGEN_MASK;
+    SIM->SCGC3 &= ~SIM_SCGC3_USBHSPHY_MASK;
+}
+
+void CLOCK_EnableUsbhs0PfdClock(uint8_t frac, clock_usb_pfd_src_t src)
+{
+    assert((frac <= 35U) && (frac >= 18U));
+    uint32_t fracFreq = (480000U * 18U / frac) * 1000U;
+
+    USBPHY->ANACTRL = (USBPHY->ANACTRL & ~(USBPHY_ANACTRL_PFD_FRAC_MASK | USBPHY_ANACTRL_PFD_CLK_SEL_MASK)) |
+                      (USBPHY_ANACTRL_PFD_FRAC(frac) | USBPHY_ANACTRL_PFD_CLK_SEL(src));
+
+    USBPHY->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK;
+    while (!(USBPHY->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK))
+    {
+    }
+
+    if (kCLOCK_UsbPfdSrcExt == src)
+    {
+        s_extPllFreq = g_xtal0Freq;
+    }
+    else if (kCLOCK_UsbPfdSrcFracDivBy4 == src)
+    {
+        s_extPllFreq = fracFreq / 4U;
+    }
+    else if (kCLOCK_UsbPfdSrcFracDivBy2 == src)
+    {
+        s_extPllFreq = fracFreq / 2U;
+    }
+    else
+    {
+        s_extPllFreq = fracFreq;
+    }
+}
+
+void CLOCK_DisableUsbhs0PfdClock(void)
+{
+    USBPHY->ANACTRL |= USBPHY_ANACTRL_PFD_CLKGATE_MASK;
+    s_extPllFreq = 0U;
+}
+
 uint32_t CLOCK_GetOutClkFreq(void)
 {
     uint32_t mcgoutclk;
@@ -705,6 +806,12 @@ uint32_t CLOCK_GetPll0Freq(void)
 
     mcgpll0clk = CLOCK_GetPll0RefFreq();
 
+    /*
+     * Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock.
+     * Please call CLOCK_SetXtal1Freq base on board setting before using OSC1 clock.
+     */
+    assert(mcgpll0clk);
+
     mcgpll0clk /= (FSL_FEATURE_MCG_PLL_PRDIV_BASE + MCG_C5_PRDIV0_VAL);
     mcgpll0clk *= (FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL);
 
@@ -746,16 +853,6 @@ status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
     }
 
     MCG->C7 = (MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel);
-    if (kMCG_OscselOsc == oscsel)
-    {
-        if (MCG->C2 & MCG_C2_EREFS_MASK)
-        {
-            while (!(MCG->S & MCG_S_OSCINIT0_MASK))
-            {
-            }
-        }
-    }
-
     if (needDelay)
     {
         /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */
@@ -936,6 +1033,14 @@ void CLOCK_EnablePll0(mcg_pll_config_t const *config)
     }
 }
 
+void CLOCK_SetPllClkSel(mcg_pll_clk_select_t pllcs)
+{
+    MCG->C11 = ((MCG->C11 & ~MCG_C11_PLLCS_MASK)) | MCG_C11_PLLCS(pllcs);
+    while (pllcs != MCG_S2_PLLCST_VAL)
+    {
+    }
+}
+
 void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
 {
     /* Clear the previous flag, MCG_SC[LOCS0]. */
@@ -1279,7 +1384,7 @@ mcg_mode_t CLOCK_GetMode(void)
     return mode;
 }
 
-status_t CLOCK_SetFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void))
+status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
 {
     uint8_t mcg_c4;
     bool change_drs = false;
@@ -1323,7 +1428,7 @@ status_t CLOCK_SetFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void))
     }
 
     /* In FEI mode, the MCG_C4[DMX32] is set to 0U. */
-    MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DRST_DRS(drs));
+    MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs));
 
     /* Check MCG_S[CLKST] */
     while (kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
@@ -1372,6 +1477,17 @@ status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void
                 | MCG_C1_FRDIV(frdiv)                  /* FRDIV */
                 | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
 
+    /* If use external crystal as clock source, wait for it stable. */
+    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
+    {
+        if (MCG->C2 & MCG_C2_EREFS_MASK)
+        {
+            while (!(MCG->S & MCG_S_OSCINIT0_MASK))
+            {
+            }
+        }
+    }
+
     /* Wait and check status. */
     while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
     {
@@ -1406,7 +1522,7 @@ status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void
     return kStatus_Success;
 }
 
-status_t CLOCK_SetFbiMode(mcg_drs_t drs, void (*fllStableDelay)(void))
+status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
 {
     uint8_t mcg_c4;
     bool change_drs = false;
@@ -1459,7 +1575,7 @@ status_t CLOCK_SetFbiMode(mcg_drs_t drs, void (*fllStableDelay)(void))
     {
     }
 
-    MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DRST_DRS(drs));
+    MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs));
 
     /* Wait for FLL stable time. */
     if (fllStableDelay)
@@ -1514,6 +1630,17 @@ status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void
                 | MCG_C1_FRDIV(frdiv)                  /* FRDIV = frdiv */
                 | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
 
+    /* If use external crystal as clock source, wait for it stable. */
+    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
+    {
+        if (MCG->C2 & MCG_C2_EREFS_MASK)
+        {
+            while (!(MCG->S & MCG_S_OSCINIT0_MASK))
+            {
+            }
+        }
+    }
+
     /* Wait for Reference clock Status bit to clear */
     while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
     {
@@ -1574,6 +1701,12 @@ status_t CLOCK_SetBlpeMode(void)
 
 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
 {
+    /* If external PLL is used, then the config could be NULL. */
+    if (kMCG_PllClkSelExtPll != pllcs)
+    {
+        assert(config);
+    }
+
     /*
        This function is designed to change MCG to PBE mode from PEE/BLPE/FBE,
        but with this workflow, the source mode could be all modes except PEI/PBI.
@@ -1601,13 +1734,15 @@ status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *co
         CLOCK_EnablePll0(config);
     }
 
+    /* Change to PLL mode. */
+    MCG->C6 |= MCG_C6_PLLS_MASK;
+
     MCG->C11 = ((MCG->C11 & ~MCG_C11_PLLCS_MASK)) | MCG_C11_PLLCS(pllcs);
     while (pllcs != MCG_S2_PLLCST_VAL)
     {
     }
 
-    /* Change to PLL mode. */
-    MCG->C6 |= MCG_C6_PLLS_MASK;
+    /* Wait for PLL mode changed. */
     while (!(MCG->S & MCG_S_PLLST_MASK))
     {
     }
@@ -1682,9 +1817,9 @@ status_t CLOCK_InternalModeToFbiModeQuick(void)
     return kStatus_Success;
 }
 
-status_t CLOCK_BootToFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void))
+status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
 {
-    return CLOCK_SetFeiMode(drs, fllStableDelay);
+    return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay);
 }
 
 status_t CLOCK_BootToFeeMode(
@@ -1721,6 +1856,17 @@ status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
         ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcExternal)    /* CLKS = 2 */
                                                                 | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
 
+    /* If use external crystal as clock source, wait for it stable. */
+    if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK))
+    {
+        if (MCG->C2 & MCG_C2_EREFS_MASK)
+        {
+            while (!(MCG->S & MCG_S_OSCINIT0_MASK))
+            {
+            }
+        }
+    }
+
     /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */
     while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
            (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt)))
@@ -1735,7 +1881,11 @@ status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
 
 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config)
 {
-    assert(config);
+    /* If external PLL is used, then the config could be NULL. */
+    if (kMCG_PllClkSelExtPll != pllcs)
+    {
+        assert(config);
+    }
 
     CLOCK_SetExternalRefClkConfig(oscsel);
 
@@ -1793,7 +1943,7 @@ status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
         if (!(MCG->S & MCG_S_IRCST_MASK))
         {
             CLOCK_ExternalModeToFbeModeQuick();
-            CLOCK_SetFeiMode(config->drs, (void (*)(void))0);
+            CLOCK_SetFeiMode(config->dmx32, config->drs, (void (*)(void))0);
         }
 
         CLOCK_SetExternalRefClkConfig(config->oscsel);
@@ -1805,7 +1955,7 @@ status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
         MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
 
         {
-            CLOCK_SetFeiMode(config->drs, CLOCK_FllStableDelay);
+            CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
         }
     }
 
@@ -1821,13 +1971,13 @@ status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
         switch (next_mode)
         {
             case kMCG_ModeFEI:
-                status = CLOCK_SetFeiMode(config->drs, CLOCK_FllStableDelay);
+                status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
                 break;
             case kMCG_ModeFEE:
                 status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
                 break;
             case kMCG_ModeFBI:
-                status = CLOCK_SetFbiMode(config->drs, (void (*)(void))0);
+                status = CLOCK_SetFbiMode(config->dmx32, config->drs, (void (*)(void))0);
                 break;
             case kMCG_ModeFBE:
                 status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, (void (*)(void))0);
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_clock.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_clock.h
index d145692508d..3f343f5cc9f 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_clock.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_clock.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016 - 2017 , NXP
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
@@ -12,7 +13,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -31,45 +32,83 @@
 #ifndef _FSL_CLOCK_H_
 #define _FSL_CLOCK_H_
 
-#include "fsl_device_registers.h"
-#include <stdint.h>
-#include <stdbool.h>
-#include <assert.h>
+#include "fsl_common.h"
 
 /*! @addtogroup clock */
 /*! @{ */
 
+/*! @file */
+
+/*******************************************************************************
+ * Configurations
+ ******************************************************************************/
+
+/*! @brief Configures whether to check a parameter in a function.
+ *
+ * Some MCG settings must be changed with conditions, for example:
+ *  1. MCGIRCLK settings, such as the source, divider, and the trim value should not change when
+ *     MCGIRCLK is used as a system clock source.
+ *  2. MCG_C7[OSCSEL] should not be changed  when the external reference clock is used
+ *     as a system clock source. For example, in FBE/BLPE/PBE modes.
+ *  3. The users should only switch between the supported clock modes.
+ *
+ * MCG functions check the parameter and MCG status before setting, if not allowed
+ * to change, the functions return error. The parameter checking increases code size,
+ * if code size is a critical requirement, change #MCG_CONFIG_CHECK_PARAM to 0 to
+ * disable parameter checking.
+ */
+#ifndef MCG_CONFIG_CHECK_PARAM
+#define MCG_CONFIG_CHECK_PARAM 0U
+#endif
+
+/*! @brief Configure whether driver controls clock
+ *
+ * When set to 0, peripheral drivers will enable clock in initialize function
+ * and disable clock in de-initialize function. When set to 1, peripheral
+ * driver will not control the clock, application could contol the clock out of
+ * the driver.
+ *
+ * @note All drivers share this feature switcher. If it is set to 1, application
+ * should handle clock enable and disable for all drivers.
+ */
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
+#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
+#endif
+
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
-/*! @brief Clock driver version. */
-#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */
+/*! @name Driver version */
+/*@{*/
+/*! @brief CLOCK driver version 2.2.2. */
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))
+/*@}*/
 
 /*! @brief External XTAL0 (OSC0) clock frequency.
  *
- * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz, when the clock is setup, use the
- * function CLOCK_SetXtal0Freq to set the value in to clock driver. For example,
- * if XTAL0 is 8MHz,
+ * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
+ * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
+ * if XTAL0 is 8 MHz:
  * @code
- * CLOCK_InitOsc0(...); // Setup the OSC0
- * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to clock driver.
+ * CLOCK_InitOsc0(...); // Set up the OSC0
+ * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to the clock driver.
  * @endcode
  *
- * This is important for the multicore platforms, only one core needs to setup
- * OSC0 using CLOCK_InitOsc0, all other cores need to call CLOCK_SetXtal0Freq
- * to get valid clock frequency.
+ * This is important for the multicore platforms where only one core needs to set up the
+ * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
+ * to get a valid clock frequency.
  */
 extern uint32_t g_xtal0Freq;
 
 /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
  *
- * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz, when the clock is setup, use the
- * function CLOCK_SetXtal32Freq to set the value in to clock driver.
+ * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
+ * function CLOCK_SetXtal32Freq to set the value in the clock driver.
  *
- * This is important for the multicore platforms, only one core needs to setup
- * the clock, all other cores need to call CLOCK_SetXtal32Freq
- * to get valid clock frequency.
+ * This is important for the multicore platforms where only one core needs to set up
+ * the clock. All other cores need to call the CLOCK_SetXtal32Freq
+ * to get a valid clock frequency.
  */
 extern uint32_t g_xtal32Freq;
 
@@ -194,16 +233,10 @@ extern uint32_t g_xtal32Freq;
         kCLOCK_Sdramc0 \
     }
 
-/*! @brief Clock ip name array for MMCAU. */
-#define MMCAU_CLOCKS  \
-    {                 \
-        kCLOCK_Mmcau0 \
-    }
-
 /*! @brief Clock ip name array for MPU. */
-#define MPU_CLOCKS  \
-    {               \
-        kCLOCK_Mpu0 \
+#define SYSMPU_CLOCKS  \
+    {                  \
+        kCLOCK_Sysmpu0 \
     }
 
 /*! @brief Clock ip name array for VREF. */
@@ -242,12 +275,6 @@ extern uint32_t g_xtal32Freq;
         kCLOCK_Crc0 \
     }
 
-/*! @brief Clock ip name array for LMEM. */
-#define LMEM_CLOCKS  \
-    {                \
-        kCLOCK_Lmem0 \
-    }
-
 /*! @brief Clock ip name array for I2C. */
 #define I2C_CLOCKS                                         \
     {                                                      \
@@ -267,9 +294,9 @@ extern uint32_t g_xtal32Freq;
     }
 
 /*! @brief Clock ip name array for CMP. */
-#define CMP_CLOCKS                            \
-    {                                         \
-        kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2 \
+#define CMP_CLOCKS                                         \
+    {                                                      \
+        kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2, kCLOCK_Cmp3 \
     }
 
 /*!
@@ -334,9 +361,26 @@ typedef enum _clock_usb_src
     kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U),   /*!< Use PLL0.      */
     kCLOCK_UsbSrcUsbPfd = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(2U), /*!< Use USBPFDCLK. */
     kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U), /*!< Use IRC48M.    */
-    kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U)                               /*!< Use USB_CLKIN. */
+    kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U),                              /*!< Use USB_CLKIN. */
+    kCLOCK_UsbSrcUnused = 0xFFFFFFFFU,                                    /*!< Used when the function does not
+                                                                               care the clock source. */
 } clock_usb_src_t;
 
+/*! @brief Source of the USB HS PHY. */
+typedef enum _clock_usb_phy_src
+{
+    kCLOCK_UsbPhySrcExt = 0U, /*!< Use external crystal. */
+} clock_usb_phy_src_t;
+
+/*! @brief Source of the USB HS PFD clock (USB1PFDCLK) */
+typedef enum _clock_usb_pfd_src
+{
+    kCLOCK_UsbPfdSrcExt = 0U,        /*!< Use external crystal. */
+    kCLOCK_UsbPfdSrcFracDivBy4 = 1U, /*!< Use PFD_FRAC output divided by 4. */
+    kCLOCK_UsbPfdSrcFracDivBy2 = 2U, /*!< Use PFD_FRAC output divided by 2. */
+    kCLOCK_UsbPfdSrcFrac = 3U,       /*!< Use PFD_FRAC output. */
+} clock_usb_pfd_src_t;
+
 /*------------------------------------------------------------------------------
 
  clock_gate_t definition:
@@ -402,6 +446,7 @@ typedef enum _clock_ip_name
     kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
     kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
     kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 19U),
+    kCLOCK_Cmp3 = CLK_GATE_DEFINE(0x1034U, 19U),
     kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
 
     kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
@@ -430,7 +475,7 @@ typedef enum _clock_ip_name
 
     kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U),
     kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
-    kCLOCK_Mpu0 = CLK_GATE_DEFINE(0x1040U, 2U),
+    kCLOCK_Sysmpu0 = CLK_GATE_DEFINE(0x1040U, 2U),
     kCLOCK_Sdramc0 = CLK_GATE_DEFINE(0x1040U, 3U),
 } clock_ip_name_t;
 
@@ -447,7 +492,7 @@ typedef struct _sim_clock_config
 /*! @brief OSC work mode. */
 typedef enum _osc_mode
 {
-    kOSC_ModeExt = 0U, /*!< Use external clock.   */
+    kOSC_ModeExt = 0U, /*!< Use an external clock.   */
 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
     kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
 #else
@@ -498,8 +543,8 @@ typedef struct _oscer_config
  * @brief OSC Initialization Configuration Structure
  *
  * Defines the configuration data structure to initialize the OSC.
- * When porting to a new board, please set the following members
- * according to board setting:
+ * When porting to a new board, set the following members
+ * according to the board setting:
  * 1. freq: The external frequency.
  * 2. workMode: The OSC module mode.
  */
@@ -575,7 +620,7 @@ typedef enum _mcg_oscsel
 typedef enum _mcg_pll_clk_select
 {
     kMCG_PllClkSelPll0,  /*!< PLL0 output clock is selected  */
-    kMCG_PllClkSelExtPll /* External PLL clock is selected   */
+    kMCG_PllClkSelExtPll /* The external PLL clock is selected   */
 } mcg_pll_clk_select_t;
 
 /*! @brief MCG clock monitor mode. */
@@ -596,8 +641,8 @@ enum _mcg_status
     kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3), /*!< Invalid desired frequency for ATM. */
     kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4),            /*!< IRC is used when using ATM. */
     kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5),       /*!< Hardware fail occurs during ATM. */
-    kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6)             /*!< Could not change clock source because
-                                                                               it is used currently. */
+    kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6)             /*!< Can't change the clock source because
+                                                                               it is in use. */
 };
 
 /*! @brief MCG status flags. */
@@ -621,11 +666,11 @@ enum _mcg_irclk_enable_mode
 /*! @brief MCG PLL clock enable mode definition. */
 enum _mcg_pll_enable_mode
 {
-    kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable indepencent of
-                                                           MCG clock mode. Generally, PLL
+    kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
+                                                           MCG clock mode. Generally, the PLL
                                                            is disabled in FLL modes
-                                                           (FEI/FBI/FEE/FBE), set PLL clock
-                                                           enable independent will enable
+                                                           (FEI/FBI/FEE/FBE). Setting the PLL clock
+                                                           enable independent, enables the
                                                            PLL in the FLL modes.          */
     kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK        /*!< MCGPLLCLK enable in STOP mode. */
 };
@@ -652,16 +697,16 @@ typedef struct _mcg_pll_config
     uint8_t vdiv;       /*!< VCO divider VDIV.           */
 } mcg_pll_config_t;
 
-/*! @brief MCG configure structure for mode change.
+/*! @brief MCG mode change configuration structure
  *
- * When porting to a new board, please set the following members
- * according to board setting:
- * 1. frdiv: If FLL uses the external reference clock, please set this
- *    value to make sure external reference clock divided by frdiv is
- *    in the range 31.25kHz to 39.0625kHz.
+ * When porting to a new board, set the following members
+ * according to the board setting:
+ * 1. frdiv: If the FLL uses the external reference clock, set this
+ *    value to ensure that the external reference clock divided by frdiv is
+ *    in the 31.25 kHz to 39.0625 kHz range.
  * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
- *    PRDIV should be in the range of FSL_FEATURE_MCG_PLL_REF_MIN to
- *    FSL_FEATURE_MCG_PLL_REF_MAX.
+ *    PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
+ *    FSL_FEATURE_MCG_PLL_REF_MAX range.
  */
 typedef struct _mcg_config
 {
@@ -693,26 +738,6 @@ typedef struct _mcg_config
 extern "C" {
 #endif /* __cplusplus */
 
-/*!
- * @brief Set the XTAL0 frequency based on board setting.
- *
- * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
- */
-static inline void CLOCK_SetXtal0Freq(uint32_t freq)
-{
-    g_xtal0Freq = freq;
-}
-
-/*!
- * @brief Set the XTAL32/RTC_CLKIN frequency based on board setting.
- *
- * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
- */
-static inline void CLOCK_SetXtal32Freq(uint32_t freq)
-{
-    g_xtal32Freq = freq;
-}
-
 /*!
  * @brief Enable the clock for specific IP.
  *
@@ -839,8 +864,12 @@ static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
 
 /*! @brief Enable USB HS clock.
  *
- * @param src  USB HS clock source.
- * @param freq The frequency specified by src.
+ * This function only enables the access to USB HS prepheral, upper layer
+ * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
+ * clock to use USB HS.
+ *
+ * @param src  USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
+ * @param freq USB HS does not care about the clock source, so this parameter is ignored.
  * @retval true The clock is set successfully.
  * @retval false The clock source is invalid to get proper USB HS clock.
  */
@@ -848,13 +877,49 @@ bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
 
 /*! @brief Disable USB HS clock.
  *
- * Disable USB HS clock.
+ * Disable USB HS clock, this function should not be called after
+ * @ref CLOCK_DisableUsbhs0PhyPllClock.
  */
-static inline void CLOCK_DisableUsbhs0Clock(void)
-{
-    SIM->SOPT2 &= ~SIM_SOPT2_USBREGEN_MASK;
-    SIM->SCGC3 &= ~(SIM_SCGC3_USBHS_MASK | SIM_SCGC3_USBHSPHY_MASK);
-}
+void CLOCK_DisableUsbhs0Clock(void);
+
+/*! @brief Enable USB HS PHY PLL clock.
+ *
+ * This function enables the internal 480MHz USB PHY PLL clock.
+ *
+ * @param src  USB HS PHY PLL clock source.
+ * @param freq The frequency specified by src.
+ * @retval true The clock is set successfully.
+ * @retval false The clock source is invalid to get proper USB HS clock.
+ */
+bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
+
+/*! @brief Disable USB HS PHY PLL clock.
+ *
+ * This function disables USB HS PHY PLL clock.
+ */
+void CLOCK_DisableUsbhs0PhyPllClock(void);
+
+/*! @brief Enable USB HS PFD clock.
+ *
+ * This function enables USB HS PFD clock. It should be called after function
+ * @ref CLOCK_EnableUsbhs0PhyPllClock.
+ * The PFD output clock is selected by the parameter @p src. When the @p src is
+ * @ref kCLOCK_UsbPfdSrcExt, then the PFD outout is from external crystal
+ * directly, in this case, the @p frac is not used. In other cases, the PFD_FRAC
+ * output clock frequency is 480MHz*18/frac, the PFD output frequency is based
+ * on the PFD_FRAC output.
+ *
+ * @param frac The value set to PFD_FRAC, it must be in the range of 18 to 35.
+ * @param src Source of the USB HS PFD clock (USB1PFDCLK).
+ */
+void CLOCK_EnableUsbhs0PfdClock(uint8_t frac, clock_usb_pfd_src_t src);
+
+/*! @brief Disable USB HS PFD clock.
+ *
+ * This function disables USB HS PFD clock. It should be called before function
+ * @ref CLOCK_DisableUsbhs0PhyPllClock.
+ */
+void CLOCK_DisableUsbhs0PfdClock(void);
 
 /*! @brief Enable USB FS clock.
  *
@@ -997,9 +1062,9 @@ static inline void CLOCK_SetSimSafeDivs(void)
 /*@{*/
 
 /*!
- * @brief Get the MCG output clock(MCGOUTCLK) frequency.
+ * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
  *
- * This function gets the MCG output clock frequency (Hz) based on current MCG
+ * This function gets the MCG output clock frequency in Hz based on the current MCG
  * register value.
  *
  * @return The frequency of MCGOUTCLK.
@@ -1007,40 +1072,40 @@ static inline void CLOCK_SetSimSafeDivs(void)
 uint32_t CLOCK_GetOutClkFreq(void);
 
 /*!
- * @brief Get the MCG FLL clock(MCGFLLCLK) frequency.
+ * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
  *
- * This function gets the MCG FLL clock frequency (Hz) based on current MCG
- * register value. The FLL is only enabled in FEI/FBI/FEE/FBE mode, in other
- * modes, FLL is disabled in low power state.
+ * This function gets the MCG FLL clock frequency in Hz based on the current MCG
+ * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
+ * disabled in low power state in other modes.
  *
  * @return The frequency of MCGFLLCLK.
  */
 uint32_t CLOCK_GetFllFreq(void);
 
 /*!
- * @brief Get the MCG internal reference clock(MCGIRCLK) frequency.
+ * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
  *
- * This function gets the MCG internal reference clock frequency (Hz) based
- * on current MCG register value.
+ * This function gets the MCG internal reference clock frequency in Hz based
+ * on the current MCG register value.
  *
  * @return The frequency of MCGIRCLK.
  */
 uint32_t CLOCK_GetInternalRefClkFreq(void);
 
 /*!
- * @brief Get the MCG fixed frequency clock(MCGFFCLK) frequency.
+ * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
  *
- * This function gets the MCG fixed frequency clock frequency (Hz) based
- * on current MCG register value.
+ * This function gets the MCG fixed frequency clock frequency in Hz based
+ * on the current MCG register value.
  *
  * @return The frequency of MCGFFCLK.
  */
 uint32_t CLOCK_GetFixedFreqClkFreq(void);
 
 /*!
- * @brief Get the MCG PLL0 clock(MCGPLL0CLK) frequency.
+ * @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency.
  *
- * This function gets the MCG PLL0 clock frequency (Hz) based on current MCG
+ * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG
  * register value.
  *
  * @return The frequency of MCGPLL0CLK.
@@ -1048,21 +1113,21 @@ uint32_t CLOCK_GetFixedFreqClkFreq(void);
 uint32_t CLOCK_GetPll0Freq(void);
 
 /*!
- * @brief Get the MCG external PLL frequency.
+ * @brief Gets the MCG external PLL frequency.
  *
- * This function gets the MCG external PLL frequency (Hz).
+ * This function gets the MCG external PLL frequency in Hz.
  *
- * @return The frequency of MCG external PLL.
+ * @return The frequency of the MCG external PLL.
  */
 uint32_t CLOCK_GetExtPllFreq(void);
 
 /*!
- * @brief Set the MCG external PLL frequency.
+ * @brief Sets the MCG external PLL frequency.
  *
- * This function sets the MCG external PLL frequency (Hz), the MCG external PLL
- * frequency is passed in to MCG driver through this function. Please call this
- * function after the external PLL frequency is changed, otherwise the APIs for
- * get frequency may returns wrong value.
+ * This function sets the MCG external PLL frequency in Hz. The MCG external PLL
+ * frequency is passed to the MCG driver using this function. Call this
+ * function after the external PLL frequency is changed. Otherwise, the APIs, which are used to get
+ * the frequency, may return an incorrect value.
  *
  * @param The frequency of MCG external PLL.
  */
@@ -1074,12 +1139,12 @@ void CLOCK_SetExtPllFreq(uint32_t freq);
 /*@{*/
 
 /*!
- * @brief Enable or disable MCG low power.
+ * @brief Enables or disables the MCG low power.
  *
- * Enable MCG low power will disable the PLL and FLL in bypass modes. That is,
- * in FBE and PBE modes, enable low power will set MCG to BLPE mode, in FBI and
- * PBI mode, enable low power will set MCG to BLPI mode.
- * When disable MCG low power, the PLL or FLL will be enabled based on MCG setting.
+ * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
+ * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
+ * PBI modes, enabling low power sets the MCG to BLPI mode.
+ * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
  *
  * @param enable True to enable MCG low power, false to disable MCG low power.
  */
@@ -1096,42 +1161,56 @@ static inline void CLOCK_SetLowPowerEnable(bool enable)
 }
 
 /*!
- * @brief Configure the Internal Reference clock (MCGIRCLK)
+ * @brief Configures the Internal Reference clock (MCGIRCLK).
  *
- * This function setups the \c MCGIRCLK base on parameters. It selects the IRC
- * source, if fast IRC is used, this function also sets the fast IRC divider.
- * This function also sets whether enable \c MCGIRCLK in stop mode.
- * Calling this function in FBI/PBI/BLPI modes may change the system clock, so
- * it is not allowed to use this in these modes.
+ * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
+ * source. If the fast IRC is used, this function sets the fast IRC divider.
+ * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
+ * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
+ * using the function in these modes it is not allowed.
  *
  * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
  * @param ircs       MCGIRCLK clock source, choose fast or slow.
  * @param fcrdiv     Fast IRC divider setting (\c FCRDIV).
- * @retval kStatus_MCG_SourceUsed MCGIRCLK is used as system clock, should not configure MCGIRCLK.
+ * @retval kStatus_MCG_SourceUsed Because the internall reference clock is used as a clock source,
+ * the confuration should not be changed. Otherwise, a glitch occurs.
  * @retval kStatus_Success MCGIRCLK configuration finished successfully.
  */
 status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
 
 /*!
- * @brief Select the MCG external reference clock.
+ * @brief Selects the MCG external reference clock.
  *
- * Select the MCG external reference clock source, it changes the MCG_C7[OSCSEL]
- * and wait for the clock source stable. Should not change external reference
- * clock in FEE/FBE/BLPE/PBE/PEE mdes, so don't call this function in these modes.
+ * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
+ * and waits for the clock source to be stable. Because the external reference
+ * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
  *
  * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
- * @retval kStatus_MCG_SourceUsed External reference clock is used, should not change.
+ * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
+ * the confuration should not be changed. Otherwise, a glitch occurs.
  * @retval kStatus_Success External reference clock set successfully.
  */
 status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
 
+/*!
+ * @brief Set the FLL external reference clock divider value.
+ *
+ * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
+ *
+ * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
+ */
+static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
+{
+    MCG->C1 = (MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv);
+}
+
 /*!
  * @brief Enables the PLL0 in FLL mode.
  *
- * This function setups the PLL0 in FLL mode, make sure the PLL reference
- * clock is enabled before calling this function. This function reconfigures
- * the PLL0, make sure the PLL0 is not used as a clock source while calling
- * this function. The function CLOCK_CalcPllDiv can help to get the proper PLL
+ * This function sets us the PLL0 in FLL mode and reconfigures
+ * the PLL0. Ensure that the PLL reference
+ * clock is enabled before calling this function and that the PLL0 is not used as a clock source.
+ * The function CLOCK_CalcPllDiv gets the correct PLL
  * divider values.
  *
  * @param config Pointer to the configuration structure.
@@ -1141,7 +1220,7 @@ void CLOCK_EnablePll0(mcg_pll_config_t const *config);
 /*!
  * @brief Disables the PLL0 in FLL mode.
  *
- * This function disables the PLL0 in FLL mode, it should be used together with
+ * This function disables the PLL0 in FLL mode. It should be used together with the
  * @ref CLOCK_EnablePll0.
  */
 static inline void CLOCK_DisablePll0(void)
@@ -1150,70 +1229,80 @@ static inline void CLOCK_DisablePll0(void)
 }
 
 /*!
- * @brief Calculates the PLL divider setting for desired output frequency.
+ * @brief Calculates the PLL divider setting for a desired output frequency.
  *
- * This function calculates the proper reference clock divider (\c PRDIV) and
- * VCO divider (\c VDIV) to generate desired PLL output frequency. It returns the
- * closest frequency PLL could generate, the corresponding \c PRDIV/VDIV are
- * returned from parameters. If desired frequency is not valid, this function
+ * This function calculates the correct reference clock divider (\c PRDIV) and
+ * VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the
+ * closest frequency match with the corresponding \c PRDIV/VDIV
+ * returned from parameters. If a desired frequency is not valid, this function
  * returns 0.
  *
  * @param refFreq    PLL reference clock frequency.
  * @param desireFreq Desired PLL output frequency.
  * @param prdiv      PRDIV value to generate desired PLL frequency.
  * @param vdiv       VDIV value to generate desired PLL frequency.
- * @return Closest frequency PLL could generate.
+ * @return Closest frequency match that the PLL was able generate.
  */
 uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv);
 
+/*!
+ * @brief Set the PLL selection.
+ *
+ * This function sets the PLL selection between PLL0/PLL1/EXTPLL, and waits for
+ * change finished.
+ *
+ * @param pllcs The PLL to select.
+ */
+void CLOCK_SetPllClkSel(mcg_pll_clk_select_t pllcs);
+
 /*@}*/
 
 /*! @name MCG clock lock monitor functions. */
 /*@{*/
 
 /*!
- * @brief Set the OSC0 clock monitor mode.
+ * @brief Sets the OSC0 clock monitor mode.
  *
- * Set the OSC0 clock monitor mode, see @ref mcg_monitor_mode_t for details.
+ * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
  *
- * @param mode The monitor mode to set.
+ * @param mode Monitor mode to set.
  */
 void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
 
 /*!
- * @brief Set the RTC OSC clock monitor mode.
+ * @brief Sets the RTC OSC clock monitor mode.
  *
- * Set the RTC OSC clock monitor mode, see @ref mcg_monitor_mode_t for details.
+ * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
  *
- * @param mode The monitor mode to set.
+ * @param mode Monitor mode to set.
  */
 void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
 
 /*!
- * @brief Set the PLL0 clock monitor mode.
+ * @brief Sets the PLL0 clock monitor mode.
  *
- * Set the PLL0 clock monitor mode, see @ref mcg_monitor_mode_t for details.
+ * This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
  *
- * @param mode The monitor mode to set.
+ * @param mode Monitor mode to set.
  */
 void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
 
 /*!
- * @brief Set the external PLL clock monitor mode.
+ * @brief Sets the external PLL clock monitor mode.
  *
- * Set the external PLL clock monitor mode, see @ref mcg_monitor_mode_t
+ * This function ets the external PLL clock monitor mode. See @ref mcg_monitor_mode_t
  * for details.
  *
- * @param mode The monitor mode to set.
+ * @param mode Monitor mode to set.
  */
 void CLOCK_SetExtPllMonitorMode(mcg_monitor_mode_t mode);
 
 /*!
- * @brief Get the MCG status flags.
+ * @brief Gets the MCG status flags.
  *
- * This function gets the MCG clock status flags, all the status flags are
+ * This function gets the MCG clock status flags. All status flags are
  * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To
- * check specific flags, compare the return value with the flags.
+ * check a specific flag, compare the return value with the flag.
  *
  * Example:
  * @code
@@ -1239,8 +1328,8 @@ uint32_t CLOCK_GetStatusFlags(void);
 /*!
  * @brief Clears the MCG status flags.
  *
- * This function clears the MCG clock lock lost status. The parameter is logical
- * OR value of the flags to clear, see @ref _mcg_status_flags_t.
+ * This function clears the MCG clock lock lost status. The parameter is a logical
+ * OR value of the flags to clear. See @ref _mcg_status_flags_t.
  *
  * Example:
  * @code
@@ -1265,8 +1354,8 @@ void CLOCK_ClearStatusFlags(uint32_t mask);
  * @brief Configures the OSC external reference clock (OSCERCLK).
  *
  * This function configures the OSC external reference clock (OSCERCLK).
- * For example, to enable the OSCERCLK in normal mode and stop mode, and also set
- * the output divider to 1, as follows:
+ * This is an example to enable the OSCERCLK in normal and stop modes and also set
+ * the output divider to 1:
  *
    @code
    oscer_config_t config =
@@ -1320,45 +1409,71 @@ static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
 }
 
 /*!
- * @brief Initialize OSC0.
+ * @brief Initializes the OSC0.
  *
- * This function initializes OSC0 according to board configuration.
+ * This function initializes the OSC0 according to the board configuration.
  *
  * @param  config Pointer to the OSC0 configuration structure.
  */
 void CLOCK_InitOsc0(osc_config_t const *config);
 
 /*!
- * @brief Deinitialize OSC0.
+ * @brief Deinitializes the OSC0.
  *
- * This function deinitializes OSC0.
+ * This function deinitializes the OSC0.
  */
 void CLOCK_DeinitOsc0(void);
 
 /* @} */
 
+/*!
+ * @name External clock frequency
+ * @{
+ */
+
+/*!
+ * @brief Sets the XTAL0 frequency based on board settings.
+ *
+ * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
+ */
+static inline void CLOCK_SetXtal0Freq(uint32_t freq)
+{
+    g_xtal0Freq = freq;
+}
+
+/*!
+ * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
+ *
+ * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
+ */
+static inline void CLOCK_SetXtal32Freq(uint32_t freq)
+{
+    g_xtal32Freq = freq;
+}
+/* @} */
+
 /*!
  * @name MCG auto-trim machine.
  * @{
  */
 
 /*!
- * @brief Auto trim the internal reference clock.
+ * @brief Auto trims the internal reference clock.
  *
- * This function trims the internal reference clock using external clock. If
+ * This function trims the internal reference clock by using the external clock. If
  * successful, it returns the kStatus_Success and the frequency after
  * trimming is received in the parameter @p actualFreq. If an error occurs,
  * the error code is returned.
  *
- * @param extFreq      External clock frequency, should be bus clock.
- * @param desireFreq   Frequency want to trim to.
- * @param actualFreq   Actual frequency after trim.
+ * @param extFreq      External clock frequency, which should be a bus clock.
+ * @param desireFreq   Frequency to trim to.
+ * @param actualFreq   Actual frequency after trimming.
  * @param atms         Trim fast or slow internal reference clock.
  * @retval kStatus_Success ATM success.
- * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for ATM.
+ * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
  * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
- * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as bus clock source.
- * @retval kStatus_MCG_AtmHardwareFail Hardware fails during trim.
+ * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
+ * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
  */
 status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
 /* @} */
@@ -1369,260 +1484,265 @@ status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_
 /*!
  * @brief Gets the current MCG mode.
  *
- * This function checks the MCG registers and determine current MCG mode.
+ * This function checks the MCG registers and determines the current MCG mode.
  *
- * @return Current MCG mode or error code, see @ref mcg_mode_t.
+ * @return Current MCG mode or error code; See @ref mcg_mode_t.
  */
 mcg_mode_t CLOCK_GetMode(void);
 
 /*!
- * @brief Set MCG to FEI mode.
+ * @brief Sets the MCG to FEI mode.
  *
- * This function sets MCG to FEI mode. If could not set to FEI mode directly
- * from current mode, this function returns error. @ref kMCG_Dmx32Default is used in this
- * mode because using kMCG_Dmx32Fine with internal reference clock source
- * might damage hardware.
+ * This function sets the MCG to FEI mode. If setting to FEI mode fails
+ * from the current mode, this function returns an error.
  *
+ * @param       dmx32  DMX32 in FEI mode.
  * @param       drs The DCO range selection.
- * @param       fllStableDelay Delay function to make sure FLL is stable, if pass
- *              in NULL, then does not delay.
+ * @param       fllStableDelay Delay function to  ensure that the FLL is stable. Passing
+ *              NULL does not cause a delay.
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
+ * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
+ * to a frequency above 32768 Hz.
  */
-status_t CLOCK_SetFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void));
+status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
 
 /*!
- * @brief Set MCG to FEE mode.
+ * @brief Sets the MCG to FEE mode.
  *
- * This function sets MCG to FEE mode. If could not set to FEE mode directly
- * from current mode, this function returns error.
+ * This function sets the MCG to FEE mode. If setting to FEE mode fails
+ * from the current mode, this function returns an error.
  *
  * @param   frdiv  FLL reference clock divider setting, FRDIV.
  * @param   dmx32  DMX32 in FEE mode.
  * @param   drs    The DCO range selection.
- * @param   fllStableDelay Delay function to make sure FLL is stable, if pass
- *          in NULL, then does not delay.
+ * @param   fllStableDelay Delay function to make sure FLL is stable. Passing
+ *          NULL does not cause a delay.
  *
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
  */
 status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
 
 /*!
- * @brief Set MCG to FBI mode.
+ * @brief Sets the MCG to FBI mode.
  *
- * This function sets MCG to FBI mode. If could not set to FBI mode directly
- * from current mode, this function returns error.
+ * This function sets the MCG to FBI mode. If setting to FBI mode fails
+ * from the current mode, this function returns an error.
  *
+ * @param  dmx32  DMX32 in FBI mode.
  * @param  drs  The DCO range selection.
- * @param  fllStableDelay Delay function to make sure FLL is stable. If FLL
- *         is not used in FBI mode, this parameter could be NULL. Pass in
- *         NULL does not delay.
+ * @param  fllStableDelay Delay function to make sure FLL is stable. If the FLL
+ *         is not used in FBI mode, this parameter can be NULL. Passing
+ *         NULL does not cause a delay.
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
+ * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
+ * to frequency above 32768 Hz.
  */
-status_t CLOCK_SetFbiMode(mcg_drs_t drs, void (*fllStableDelay)(void));
+status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
 
 /*!
- * @brief Set MCG to FBE mode.
+ * @brief Sets the MCG to FBE mode.
  *
- * This function sets MCG to FBE mode. If could not set to FBE mode directly
- * from current mode, this function returns error.
+ * This function sets the MCG to FBE mode. If setting to FBE mode fails
+ * from the current mode, this function returns an error.
  *
  * @param   frdiv  FLL reference clock divider setting, FRDIV.
  * @param   dmx32  DMX32 in FBE mode.
  * @param   drs    The DCO range selection.
- * @param   fllStableDelay Delay function to make sure FLL is stable. If FLL
- *          is not used in FBE mode, this parameter could be NULL. Pass in NULL
- *          does not delay.
+ * @param   fllStableDelay Delay function to make sure FLL is stable. If the FLL
+ *          is not used in FBE mode, this parameter can be NULL. Passing NULL
+ *          does not cause a delay.
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
  */
 status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
 
 /*!
- * @brief Set MCG to BLPI mode.
+ * @brief Sets the MCG to BLPI mode.
  *
- * This function sets MCG to BLPI mode. If could not set to BLPI mode directly
- * from current mode, this function returns error.
+ * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
+ * from the current mode, this function returns an error.
  *
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
  */
 status_t CLOCK_SetBlpiMode(void);
 
 /*!
- * @brief Set MCG to BLPE mode.
+ * @brief Sets the MCG to BLPE mode.
  *
- * This function sets MCG to BLPE mode. If could not set to BLPE mode directly
- * from current mode, this function returns error.
+ * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
+ * from the current mode, this function returns an error.
  *
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
  */
 status_t CLOCK_SetBlpeMode(void);
 
 /*!
- * @brief Set MCG to PBE mode.
+ * @brief Sets the MCG to PBE mode.
  *
- * This function sets MCG to PBE mode. If could not set to PBE mode directly
- * from current mode, this function returns error.
+ * This function sets the MCG to PBE mode. If setting to PBE mode fails
+ * from the current mode, this function returns an error.
  *
  * @param   pllcs  The PLL selection, PLLCS.
  * @param   config Pointer to the PLL configuration.
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
  *
  * @note
- * 1. The parameter \c pllcs selects the PLL, for some platforms, there is
- * only one PLL, the parameter pllcs is kept for interface compatible.
- * 2. The parameter \c config is the PLL configuration structure, on some
- * platforms, could choose the external PLL directly. This means that the
- * configuration structure is not necessary, pass in NULL for this case.
+ * 1. The parameter \c pllcs selects the PLL. For platforms with
+ * only one PLL, the parameter pllcs is kept for interface compatibility.
+ * 2. The parameter \c config is the PLL configuration structure. On some
+ * platforms,  it is possible to choose the external PLL directly, which renders the
+ * configuration structure not necessary. In this case, pass in NULL.
  * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
  */
 status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
 
 /*!
- * @brief Set MCG to PEE mode.
+ * @brief Sets the MCG to PEE mode.
  *
- * This function sets MCG to PEE mode.
+ * This function sets the MCG to PEE mode.
  *
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
  *
- * @note This function only change CLKS to use PLL/FLL output. If the
- *       PRDIV/VDIV are different from PBE mode, please setup these
- *       settings in PBE mode and wait for stable then switch to PEE mode.
+ * @note This function only changes the CLKS to use the PLL/FLL output. If the
+ *       PRDIV/VDIV are different than in the PBE mode, set them up
+ *       in PBE mode and wait. When the clock is stable, switch to PEE mode.
  */
 status_t CLOCK_SetPeeMode(void);
 
 /*!
- * @brief Switch MCG to FBE mode quickly from external mode.
+ * @brief Switches the MCG to FBE mode from the external mode.
  *
- * This function changes MCG from external modes (PEE/PBE/BLPE/FEE) to FBE mode quickly.
- * It only changes to use external clock as the system clock souce and disable PLL, but does not
- * configure FLL settings. This is a lite function with small code size, it is useful
- * during mode switch. For example, to switch from PEE mode to FEI mode:
+ * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
+ * The external clock is used as the system clock souce and PLL is disabled. However,
+ * the FLL settings are not configured. This is a lite function with a small code size, which is useful
+ * during the mode switch. For example, to switch from PEE mode to FEI mode:
  *
  * @code
  * CLOCK_ExternalModeToFbeModeQuick();
  * CLOCK_SetFeiMode(...);
  * @endcode
  *
- * @retval kStatus_Success Change successfully.
- * @retval kStatus_MCG_ModeInvalid Current mode is not external modes, should not call this function.
+ * @retval kStatus_Success Switched successfully.
+ * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
  */
 status_t CLOCK_ExternalModeToFbeModeQuick(void);
 
 /*!
- * @brief Switch MCG to FBI mode quickly from internal modes.
+ * @brief Switches the MCG to FBI mode from internal modes.
  *
- * This function changes MCG from internal modes (PEI/PBI/BLPI/FEI) to FBI mode quickly.
- * It only changes to use MCGIRCLK as the system clock souce and disable PLL, but does not
- * configure FLL settings. This is a lite function with small code size, it is useful
- * during mode switch. For example, to switch from PEI mode to FEE mode:
+ * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
+ * The MCGIRCLK is used as the system clock souce and PLL is disabled. However,
+ * FLL settings are not configured. This is a lite function with a small code size, which is useful
+ * during the mode switch. For example, to switch from PEI mode to FEE mode:
  *
  * @code
  * CLOCK_InternalModeToFbiModeQuick();
  * CLOCK_SetFeeMode(...);
  * @endcode
  *
- * @retval kStatus_Success Change successfully.
- * @retval kStatus_MCG_ModeInvalid Current mode is not internal mode, should not call this function.
+ * @retval kStatus_Success Switched successfully.
+ * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
  */
 status_t CLOCK_InternalModeToFbiModeQuick(void);
 
 /*!
- * @brief Set MCG to FEI mode during system boot up.
+ * @brief Sets the MCG to FEI mode during system boot up.
  *
- * This function sets MCG to FEI mode from reset mode, it could be used to
- * set up MCG during system boot up. @ref kMCG_Dmx32Default is used in this
- * mode because using kMCG_Dmx32Fine with internal reference clock source
- * might damage hardware.
+ * This function sets the MCG to FEI mode from the reset mode. It can also be used to
+ * set up MCG during system boot up.
  *
+ * @param  dmx32  DMX32 in FEI mode.
  * @param  drs The DCO range selection.
- * @param  fllStableDelay Delay function to make sure FLL is stable.
+ * @param  fllStableDelay Delay function to ensure that the FLL is stable.
  *
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
+ * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
+ * to frequency above 32768 Hz.
  */
-status_t CLOCK_BootToFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void));
+status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
 
 /*!
- * @brief Set MCG to FEE mode during system bootup.
+ * @brief Sets the MCG to FEE mode during system bootup.
  *
- * This function sets MCG to FEE mode from reset mode, it could be used to
- * set up MCG during system boot up.
+ * This function sets MCG to FEE mode from the reset mode. It can also be used to
+ * set up the MCG during system boot up.
  *
  * @param   oscsel OSC clock select, OSCSEL.
  * @param   frdiv  FLL reference clock divider setting, FRDIV.
  * @param   dmx32  DMX32 in FEE mode.
  * @param   drs    The DCO range selection.
- * @param   fllStableDelay Delay function to make sure FLL is stable.
+ * @param   fllStableDelay Delay function to ensure that the FLL is stable.
  *
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
  */
 status_t CLOCK_BootToFeeMode(
     mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
 
 /*!
- * @brief Set MCG to BLPI mode during system boot up.
+ * @brief Sets the MCG to BLPI mode during system boot up.
  *
- * This function sets MCG to BLPI mode from reset mode, it could be used to
- * setup MCG during sytem boot up.
+ * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
+ * set up the MCG during sytem boot up.
  *
  * @param  fcrdiv Fast IRC divider, FCRDIV.
  * @param  ircs   The internal reference clock to select, IRCS.
  * @param  ircEnableMode  The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
  *
  * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
  */
 status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
 
 /*!
- * @brief Set MCG to BLPE mode during sytem boot up.
+ * @brief Sets the MCG to BLPE mode during sytem boot up.
  *
- * This function sets MCG to BLPE mode from reset mode, it could be used to
- * setup MCG during sytem boot up.
+ * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
+ * set up the MCG during sytem boot up.
  *
  * @param  oscsel OSC clock select, MCG_C7[OSCSEL].
  *
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
  */
 status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
 
 /*!
- * @brief Set MCG to PEE mode during system boot up.
+ * @brief Sets the MCG to PEE mode during system boot up.
  *
- * This function sets MCG to PEE mode from reset mode, it could be used to
- * setup MCG during system boot up.
+ * This function sets the MCG to PEE mode from reset mode. It can also be used to
+ * set up the MCG during system boot up.
  *
  * @param   oscsel OSC clock select, MCG_C7[OSCSEL].
  * @param   pllcs  The PLL selection, PLLCS.
  * @param   config Pointer to the PLL configuration.
  *
  * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
- * @retval kStatus_Success Switch to target mode successfully.
+ * @retval kStatus_Success Switched to the target mode successfully.
  */
 status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
 
 /*!
- * @brief Set MCG to some target mode.
+ * @brief Sets the MCG to a target mode.
  *
- * This function sets MCG to some target mode defined by the configure
- * structure, if cannot switch to target mode directly, this function will
- * choose the proper path.
+ * This function sets MCG to a target mode defined by the configuration
+ * structure. If switching to the target mode fails, this function
+ * chooses the correct path.
  *
  * @param  config Pointer to the target MCG mode configuration structure.
- * @return Return kStatus_Success if switch successfully, otherwise return error code #_mcg_status.
+ * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status.
  *
- * @note If external clock is used in the target mode, please make sure it is
- * enabled, for example, if the OSC0 is used, please setup OSC0 correctly before
- * this funciton.
+ * @note If the external clock is used in the target mode, ensure that it is
+ * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
+ * function.
  */
 status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmp.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmp.c
index 09885e74211..6a5f15a75b1 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmp.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmp.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -45,8 +45,10 @@ static uint32_t CMP_GetInstance(CMP_Type *base);
  ******************************************************************************/
 /*! @brief Pointers to CMP bases for each instance. */
 static CMP_Type *const s_cmpBases[] = CMP_BASE_PTRS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to CMP clocks for each instance. */
-const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS;
+static const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Codes
@@ -56,7 +58,7 @@ static uint32_t CMP_GetInstance(CMP_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_CMP_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_cmpBases); instance++)
     {
         if (s_cmpBases[instance] == base)
         {
@@ -64,7 +66,7 @@ static uint32_t CMP_GetInstance(CMP_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_CMP_COUNT);
+    assert(instance < ARRAY_SIZE(s_cmpBases));
 
     return instance;
 }
@@ -75,8 +77,10 @@ void CMP_Init(CMP_Type *base, const cmp_config_t *config)
 
     uint8_t tmp8;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the clock. */
     CLOCK_EnableClock(s_cmpClocks[CMP_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Configure. */
     CMP_Enable(base, false); /* Disable the CMP module during configuring. */
@@ -123,8 +127,10 @@ void CMP_Deinit(CMP_Type *base)
     /* Disable the CMP module. */
     CMP_Enable(base, false);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable the clock. */
     CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void CMP_GetDefaultConfig(cmp_config_t *config)
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmp.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmp.h
index 53d84a0f2d2..5d16bf08de4 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmp.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmp.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -38,7 +38,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -64,8 +63,8 @@ enum _cmp_interrupt_enable
  */
 enum _cmp_status_flags
 {
-    kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK,  /*!< Rising-edge on compare output has occurred. */
-    kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK, /*!< Falling-edge on compare output has occurred. */
+    kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK,  /*!< Rising-edge on the comparison output has occurred. */
+    kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */
     kCMP_OutputAssertEventFlag = CMP_SCR_COUT_MASK, /*!< Return the current value of the analog comparator output. */
 };
 
@@ -85,20 +84,20 @@ typedef enum _cmp_hysteresis_mode
  */
 typedef enum _cmp_reference_voltage_source
 {
-    kCMP_VrefSourceVin1 = 0U, /*!< Vin1 is selected as resistor ladder network supply reference Vin. */
-    kCMP_VrefSourceVin2 = 1U, /*!< Vin2 is selected as resistor ladder network supply reference Vin. */
+    kCMP_VrefSourceVin1 = 0U, /*!< Vin1 is selected as a resistor ladder network supply reference Vin. */
+    kCMP_VrefSourceVin2 = 1U, /*!< Vin2 is selected as a resistor ladder network supply reference Vin. */
 } cmp_reference_voltage_source_t;
 
 /*!
- * @brief Configure the comparator.
+ * @brief Configures the comparator.
  */
 typedef struct _cmp_config
 {
     bool enableCmp;                       /*!< Enable the CMP module. */
     cmp_hysteresis_mode_t hysteresisMode; /*!< CMP Hysteresis mode. */
-    bool enableHighSpeed;                 /*!< Enable High Speed (HS) comparison mode. */
-    bool enableInvertOutput;              /*!< Enable inverted comparator output. */
-    bool useUnfilteredOutput;             /*!< Set compare output(COUT) to equal COUTA(true) or COUT(false). */
+    bool enableHighSpeed;                 /*!< Enable High-speed (HS) comparison mode. */
+    bool enableInvertOutput;              /*!< Enable the inverted comparator output. */
+    bool useUnfilteredOutput;             /*!< Set the compare output(COUT) to equal COUTA(true) or COUT(false). */
     bool enablePinOut;                    /*!< The comparator output is available on the associated pin. */
 #if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE
     bool enableTriggerMode; /*!< Enable the trigger mode. */
@@ -106,24 +105,24 @@ typedef struct _cmp_config
 } cmp_config_t;
 
 /*!
- * @brief Configure the filter.
+ * @brief Configures the filter.
  */
 typedef struct _cmp_filter_config
 {
 #if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT
-    bool enableSample;    /*!< Using external SAMPLE as sampling clock input, or using divided bus clock. */
+    bool enableSample;    /*!< Using the external SAMPLE as a sampling clock input or using a divided bus clock. */
 #endif                    /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */
-    uint8_t filterCount;  /*!< Filter Sample Count. Available range is 1-7, 0 would cause the filter disabled.*/
-    uint8_t filterPeriod; /*!< Filter Sample Period. The divider to bus clock. Available range is 0-255. */
+    uint8_t filterCount;  /*!< Filter Sample Count. Available range is 1-7; 0 disables the filter.*/
+    uint8_t filterPeriod; /*!< Filter Sample Period. The divider to the bus clock. Available range is 0-255. */
 } cmp_filter_config_t;
 
 /*!
- * @brief Configure the internal DAC.
+ * @brief Configures the internal DAC.
  */
 typedef struct _cmp_dac_config
 {
     cmp_reference_voltage_source_t referenceVoltageSource; /*!< Supply voltage reference source. */
-    uint8_t DACValue;                                      /*!< Value for DAC Output Voltage. Available range is 0-63.*/
+    uint8_t DACValue;                                      /*!< Value for the DAC Output Voltage. Available range is 0-63.*/
 } cmp_dac_config_t;
 
 #if defined(__cplusplus)
@@ -142,28 +141,28 @@ extern "C" {
 /*!
  * @brief Initializes the CMP.
  *
- * This function initializes the CMP module. The operations included are:
+ * This function initializes the CMP module. The operations included are as follows.
  * - Enabling the clock for CMP module.
  * - Configuring the comparator.
  * - Enabling the CMP module.
- * Note: For some devices, multiple CMP instance share the same clock gate. In this case, to enable the clock for
- * any instance enables all the CMPs. Check the chip reference manual for the clock assignment of the CMP.
+ * Note that for some devices, multiple CMP instances share the same clock gate. In this case, to enable the clock for
+ * any instance enables all CMPs. See the appropriate MCU reference manual for the clock assignment of the CMP.
  *
  * @param base   CMP peripheral base address.
- * @param config Pointer to configuration structure.
+ * @param config Pointer to the configuration structure.
  */
 void CMP_Init(CMP_Type *base, const cmp_config_t *config);
 
 /*!
  * @brief De-initializes the CMP module.
  *
- * This function de-initializes the CMP module. The operations included are:
+ * This function de-initializes the CMP module. The operations included are as follows.
  * - Disabling the CMP module.
  * - Disabling the clock for CMP module.
  *
  * This function disables the clock for the CMP.
- * Note: For some devices, multiple CMP instance shares the same clock gate. In this case, before disabling the
- * clock for the CMP,  ensure that all the CMP instances are not used.
+ * Note that for some devices, multiple CMP instances share the same clock gate. In this case, before disabling the
+ * clock for the CMP, ensure that all the CMP instances are not used.
  *
  * @param base CMP peripheral base address.
  */
@@ -173,7 +172,7 @@ void CMP_Deinit(CMP_Type *base);
  * @brief Enables/disables the CMP module.
  *
  * @param base CMP peripheral base address.
- * @param enable Enable the module or not.
+ * @param enable Enables or disables the module.
  */
 static inline void CMP_Enable(CMP_Type *base, bool enable)
 {
@@ -190,7 +189,7 @@ static inline void CMP_Enable(CMP_Type *base, bool enable)
 /*!
 * @brief Initializes the CMP user configuration structure.
 *
-* This function initializes the user configure structure to these default values:
+* This function initializes the user configuration structure to these default values.
 * @code
 *   config->enableCmp           = true;
 *   config->hysteresisMode      = kCMP_HysteresisLevel0;
@@ -208,7 +207,7 @@ void CMP_GetDefaultConfig(cmp_config_t *config);
  * @brief  Sets the input channels for the comparator.
  *
  * This function sets the input channels for the comparator.
- * Note that two input channels cannot be set as same in the application. When the user selects the same input
+ * Note that two input channels cannot be set the same way in the application. When the user selects the same input
  * from the analog mux to the positive and negative port, the comparator is disabled automatically.
  *
  * @param  base            CMP peripheral base address.
@@ -229,13 +228,11 @@ void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negat
  * @brief Enables/disables the DMA request for rising/falling events.
  *
  * This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of
- * the DMA
- * request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from the CMP
- * if the
- * DMA is disabled.
+ * the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from the CMP
+ * if the DMA is disabled.
  *
  * @param base CMP peripheral base address.
- * @param enable Enable the feature or not.
+ * @param enable Enables or disables the feature.
  */
 void CMP_EnableDMA(CMP_Type *base, bool enable);
 #endif /* FSL_FEATURE_CMP_HAS_DMA */
@@ -245,7 +242,7 @@ void CMP_EnableDMA(CMP_Type *base, bool enable);
  * @brief Enables/disables the window mode.
  *
  * @param base CMP peripheral base address.
- * @param enable Enable the feature or not.
+ * @param enable Enables or disables the feature.
  */
 static inline void CMP_EnableWindowMode(CMP_Type *base, bool enable)
 {
@@ -265,7 +262,7 @@ static inline void CMP_EnableWindowMode(CMP_Type *base, bool enable)
  * @brief Enables/disables the pass through mode.
  *
  * @param base CMP peripheral base address.
- * @param enable Enable the feature or not.
+ * @param enable Enables or disables the feature.
  */
 static inline void CMP_EnablePassThroughMode(CMP_Type *base, bool enable)
 {
@@ -284,7 +281,7 @@ static inline void CMP_EnablePassThroughMode(CMP_Type *base, bool enable)
  * @brief  Configures the filter.
  *
  * @param  base   CMP peripheral base address.
- * @param  config Pointer to configuration structure.
+ * @param  config Pointer to the configuration structure.
  */
 void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config);
 
@@ -292,7 +289,7 @@ void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config);
  * @brief Configures the internal DAC.
  *
  * @param base   CMP peripheral base address.
- * @param config Pointer to configuration structure. "NULL" is for disabling the feature.
+ * @param config Pointer to the configuration structure. "NULL" disables the feature.
  */
 void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config);
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmt.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmt.c
index 9e8831f9983..8cf72bc7e7d 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmt.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmt.c
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -46,8 +46,6 @@
 #define CMT_CMTDIV_FOUR (4)
 /* CMT diver 8. */
 #define CMT_CMTDIV_EIGHT (8)
-/* CMT mode bit mask. */
-#define CMT_MODE_BIT_MASK (CMT_MSC_MCGEN_MASK | CMT_MSC_FSK_MASK | CMT_MSC_BASE_MASK)
 
 /*******************************************************************************
  * Prototypes
@@ -64,14 +62,16 @@ static uint32_t CMT_GetInstance(CMT_Type *base);
  * Variables
  ******************************************************************************/
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to cmt clocks for each instance. */
-const clock_ip_name_t s_cmtClock[FSL_FEATURE_SOC_CMT_COUNT] = CMT_CLOCKS;
+static const clock_ip_name_t s_cmtClock[FSL_FEATURE_SOC_CMT_COUNT] = CMT_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*! @brief Pointers to cmt bases for each instance. */
 static CMT_Type *const s_cmtBases[] = CMT_BASE_PTRS;
 
 /*! @brief Pointers to cmt IRQ number for each instance. */
-const IRQn_Type s_cmtIrqs[] = CMT_IRQS;
+static const IRQn_Type s_cmtIrqs[] = CMT_IRQS;
 
 /*******************************************************************************
  * Codes
@@ -82,7 +82,7 @@ static uint32_t CMT_GetInstance(CMT_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_CMT_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_cmtBases); instance++)
     {
         if (s_cmtBases[instance] == base)
         {
@@ -90,7 +90,7 @@ static uint32_t CMT_GetInstance(CMT_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_CMT_COUNT);
+    assert(instance < ARRAY_SIZE(s_cmtBases));
 
     return instance;
 }
@@ -113,8 +113,10 @@ void CMT_Init(CMT_Type *base, const cmt_config_t *config, uint32_t busClock_Hz)
 
     uint8_t divider;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Ungate clock. */
     CLOCK_EnableClock(s_cmtClock[CMT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Sets clock divider. The divider set in pps should be set
        to make sycClock_Hz/divder = 8MHz */
@@ -144,15 +146,17 @@ void CMT_Deinit(CMT_Type *base)
     CMT_DisableInterrupts(base, kCMT_EndOfCycleInterruptEnable);
     DisableIRQ(s_cmtIrqs[CMT_GetInstance(base)]);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Gate the clock. */
     CLOCK_DisableClock(s_cmtClock[CMT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulateConfig)
 {
-    uint8_t mscReg;
+    uint8_t mscReg = base->MSC;
 
-    /* Set the mode. */
+    /* Judge the mode. */
     if (mode != kCMT_DirectIROCtl)
     {
         assert(modulateConfig);
@@ -166,13 +170,14 @@ void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulat
 
         /* Set carrier modulator. */
         CMT_SetModulateMarkSpace(base, modulateConfig->markCount, modulateConfig->spaceCount);
+        mscReg &= ~ (CMT_MSC_FSK_MASK | CMT_MSC_BASE_MASK);
+        mscReg |= mode;
+    }
+    else
+    {
+        mscReg &= ~CMT_MSC_MCGEN_MASK;
     }
-
     /* Set the CMT mode. */
-    mscReg = base->MSC;
-    mscReg &= ~CMT_MODE_BIT_MASK;
-    mscReg |= mode;
-
     base->MSC = mscReg;
 }
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmt.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmt.h
index df0b2c91066..3d81f8a9a4a 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmt.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_cmt.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,7 +37,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -45,8 +44,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief CMT driver version 2.0.0. */
-#define FSL_CMT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief CMT driver version 2.0.1. */
+#define FSL_CMT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
 /*@}*/
 
 /*!
@@ -128,15 +127,15 @@ enum _cmt_interrupt_enable
 };
 
 /*!
- * @brief CMT carrier generator and modulator configure structure
+ * @brief CMT carrier generator and modulator configuration structure
  *
  */
 typedef struct _cmt_modulate_config
 {
-    uint8_t highCount1;  /*!< The high time for carrier generator first register. */
-    uint8_t lowCount1;   /*!< The low time for carrier generator first register. */
-    uint8_t highCount2;  /*!< The high time for carrier generator second register for FSK mode. */
-    uint8_t lowCount2;   /*!< The low time for carrier generator second register for FSK mode. */
+    uint8_t highCount1;  /*!< The high-time for carrier generator first register. */
+    uint8_t lowCount1;   /*!< The low-time for carrier generator first register. */
+    uint8_t highCount2;  /*!< The high-time for carrier generator second register for FSK mode. */
+    uint8_t lowCount2;   /*!< The low-time for carrier generator second register for FSK mode. */
     uint16_t markCount;  /*!< The mark time for the modulator gate. */
     uint16_t spaceCount; /*!< The space time for the modulator gate. */
 } cmt_modulate_config_t;
@@ -164,10 +163,10 @@ extern "C" {
  */
 
 /*!
- * @brief Gets the CMT default configuration structure. The purpose
- * of this API is to get the default configuration structure for the CMT_Init().
- * Use the initialized structure unchanged in CMT_Init(), or modify
- * some fields of the structure before calling the CMT_Init().
+ * @brief Gets the CMT default configuration structure. This API
+ * gets the default configuration structure for the CMT_Init().
+ * Use the initialized structure unchanged in CMT_Init() or modify
+ * fields of the structure before calling the CMT_Init().
  *
  * @param config The CMT configuration structure pointer.
  */
@@ -216,7 +215,7 @@ void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulat
  *
  * @param base   CMT peripheral base address.
  * @return The CMT mode.
- *     kCMT_DirectIROCtl     Carrier modulator is disabled, the IRO signal is directly in software control.
+ *     kCMT_DirectIROCtl     Carrier modulator is disabled; the IRO signal is directly in software control.
  *     kCMT_TimeMode         Carrier modulator is enabled in time mode.
  *     kCMT_FSKMode          Carrier modulator is enabled in FSK mode.
  *     kCMT_BasebandMode     Carrier modulator is enabled in baseband mode.
@@ -235,11 +234,11 @@ uint32_t CMT_GetCMTFrequency(CMT_Type *base, uint32_t busClock_Hz);
 /*!
  * @brief Sets the primary data set for the CMT carrier generator counter.
  *
- * This function sets the high time and low time of the primary data set for the
+ * This function sets the high-time and low-time of the primary data set for the
  * CMT carrier generator counter to control the period and the duty cycle of the
  * output carrier signal.
- * If the CMT clock period is Tcmt, The period of the carrier generator signal equals
- * (highCount + lowCount) * Tcmt. The duty cycle equals  highCount / (highCount + lowCount).
+ * If the CMT clock period is Tcmt, the period of the carrier generator signal equals
+ * (highCount + lowCount) * Tcmt. The duty cycle equals to highCount / (highCount + lowCount).
  *
  * @param base      CMT peripheral base address.
  * @param highCount The number of CMT clocks for carrier generator signal high time,
@@ -261,10 +260,10 @@ static inline void CMT_SetCarrirGenerateCountOne(CMT_Type *base, uint32_t highCo
 /*!
  * @brief Sets the secondary data set for the CMT carrier generator counter.
  *
- * This function is used for FSK mode setting the high time and low time of the secondary
+ * This function is used for FSK mode setting the high-time and low-time of the secondary
  * data set CMT carrier generator counter to control the period and the duty cycle
  * of the output carrier signal.
- * If the CMT clock period is Tcmt, The period of the carrier generator signal equals
+ * If the CMT clock period is Tcmt, the period of the carrier generator signal equals
  * (highCount + lowCount) * Tcmt. The duty cycle equals  highCount / (highCount + lowCount).
  *
  * @param base      CMT peripheral base address.
@@ -325,7 +324,7 @@ static inline void CMT_EnableExtendedSpace(CMT_Type *base, bool enable)
 }
 
 /*!
- * @brief Sets IRO - infrared output signal state.
+ * @brief Sets the IRO (infrared output) signal state.
  *
  * Changes the states of the IRO signal when the kCMT_DirectIROMode mode is set
  * and the IRO signal is enabled.
@@ -338,12 +337,12 @@ void CMT_SetIroState(CMT_Type *base, cmt_infrared_output_state_t state);
 /*!
  * @brief Enables the CMT interrupt.
  *
- * This function enables the CMT interrupts according to the provided maskIf enabled.
+ * This function enables the CMT interrupts according to the provided mask if enabled.
  * The CMT only has the end of the cycle interrupt - an interrupt occurs at the end
  * of the modulator cycle. This interrupt provides a means for the user
  * to reload the new mark/space values into the CMT modulator data registers
  * and verify the modulator mark and space.
- * For example, to enable the end of cycle, do the following:
+ * For example, to enable the end of cycle, do the following.
  * @code
  *     CMT_EnableInterrupts(CMT, kCMT_EndOfCycleInterruptEnable);
  * @endcode
@@ -360,7 +359,7 @@ static inline void CMT_EnableInterrupts(CMT_Type *base, uint32_t mask)
  *
  * This function disables the CMT interrupts according to the provided maskIf enabled.
  * The CMT only has the end of the cycle interrupt.
- * For example, to disable the end of cycle, do the following:
+ * For example, to disable the end of cycle, do the following.
  * @code
  *     CMT_DisableInterrupts(CMT, kCMT_EndOfCycleInterruptEnable);
  * @endcode
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_common.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_common.h
index 7061b621391..b20ec09973b 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_common.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_common.h
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -34,8 +34,12 @@
 #include <assert.h>
 #include <stdbool.h>
 #include <stdint.h>
-#include <stddef.h>
 #include <string.h>
+
+#if defined(__ICCARM__)
+#include <stddef.h>
+#endif
+
 #include "fsl_device_registers.h"
 
 /*!
@@ -43,8 +47,6 @@
  * @{
  */
 
-/*! @file */
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
@@ -56,11 +58,13 @@
 #define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
 
 /* Debug console type definition. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U   /*!< No debug console.             */
-#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U   /*!< Debug console base on UART.   */
-#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U  /*!< Debug console base on LPSCI.  */
-#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U     /*!< No debug console.             */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U     /*!< Debug console base on UART.   */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U   /*!< Debug console base on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U    /*!< Debug console base on LPSCI.  */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U   /*!< Debug console base on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U    /*!< Debug console base on i.MX UART. */
 
 /*! @brief Status group numbers. */
 enum _status_groups
@@ -87,6 +91,11 @@ enum _status_groups
     kStatusGroup_SCG = 21,                    /*!< Group number for SCG status codes. */
     kStatusGroup_SDSPI = 22,                  /*!< Group number for SDSPI status codes. */
     kStatusGroup_FLEXIO_I2S = 23,             /*!< Group number for FLEXIO I2S status codes */
+    kStatusGroup_FLEXIO_MCULCD = 24,          /*!< Group number for FLEXIO LCD status codes */
+    kStatusGroup_FLASHIAP = 25,               /*!< Group number for FLASHIAP status codes */
+    kStatusGroup_FLEXCOMM_I2C = 26,           /*!< Group number for FLEXCOMM I2C status codes */
+    kStatusGroup_I2S = 27,                    /*!< Group number for I2S status codes */
+    kStatusGroup_IUART = 28,                  /*!< Group number for IUART status codes */
     kStatusGroup_SDRAMC = 35,                 /*!< Group number for SDRAMC status codes. */
     kStatusGroup_POWER = 39,                  /*!< Group number for POWER status codes. */
     kStatusGroup_ENET = 40,                   /*!< Group number for ENET status codes. */
@@ -101,6 +110,18 @@ enum _status_groups
     kStatusGroup_FLEXCAN = 53,                /*!< Group number for FlexCAN status codes. */
     kStatusGroup_LTC = 54,                    /*!< Group number for LTC status codes. */
     kStatusGroup_FLEXIO_CAMERA = 55,          /*!< Group number for FLEXIO CAMERA status codes. */
+    kStatusGroup_LPC_SPI = 56,                /*!< Group number for LPC_SPI status codes. */
+    kStatusGroup_LPC_USART = 57,              /*!< Group number for LPC_USART status codes. */
+    kStatusGroup_DMIC = 58,                   /*!< Group number for DMIC status codes. */
+    kStatusGroup_SDIF = 59,                   /*!< Group number for SDIF status codes.*/
+    kStatusGroup_SPIFI = 60,                  /*!< Group number for SPIFI status codes. */
+    kStatusGroup_OTP = 61,                    /*!< Group number for OTP status codes. */
+    kStatusGroup_MCAN = 62,                   /*!< Group number for MCAN status codes. */
+    kStatusGroup_CAAM = 63,                   /*!< Group number for CAAM status codes. */
+    kStatusGroup_ECSPI = 64,                  /*!< Group number for ECSPI status codes. */
+    kStatusGroup_USDHC = 65,                  /*!< Group number for USDHC status codes.*/
+    kStatusGroup_ESAI = 69,                   /*!< Group number for ESAI status codes. */
+    kStatusGroup_FLEXSPI = 70,                /*!< Group number for FLEXSPI status codes. */
     kStatusGroup_NOTIFIER = 98,               /*!< Group number for NOTIFIER status codes. */
     kStatusGroup_DebugConsole = 99,           /*!< Group number for debug console status codes. */
     kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */
@@ -127,6 +148,14 @@ typedef int32_t status_t;
  */
 #include "fsl_clock.h"
 
+/*
+ * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
+ */
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+#include "fsl_reset.h"
+#endif
+
 /*! @name Min/max macros */
 /* @{ */
 #if !defined(MIN)
@@ -182,11 +211,20 @@ extern "C" {
  */
 static inline void EnableIRQ(IRQn_Type interrupt)
 {
+    if (NotAvail_IRQn == interrupt)
+    {
+        return;
+    }
+
 #if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
     if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
 #endif
     {
+#if defined(__GIC_PRIO_BITS)
+        GIC_EnableIRQ(interrupt);
+#else
         NVIC_EnableIRQ(interrupt);
+#endif
     }
 }
 
@@ -199,11 +237,20 @@ static inline void EnableIRQ(IRQn_Type interrupt)
  */
 static inline void DisableIRQ(IRQn_Type interrupt)
 {
+    if (NotAvail_IRQn == interrupt)
+    {
+        return;
+    }
+
 #if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
     if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
 #endif
     {
+#if defined(__GIC_PRIO_BITS)
+        GIC_DisableIRQ(interrupt);
+#else
         NVIC_DisableIRQ(interrupt);
+#endif
     }
 }
 
@@ -217,11 +264,19 @@ static inline void DisableIRQ(IRQn_Type interrupt)
  */
 static inline uint32_t DisableGlobalIRQ(void)
 {
+#if defined(CPSR_I_Msk)
+    uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
+
+    __disable_irq();
+
+    return cpsr;
+#else
     uint32_t regPrimask = __get_PRIMASK();
 
     __disable_irq();
 
     return regPrimask;
+#endif
 }
 
 /*!
@@ -236,7 +291,11 @@ static inline uint32_t DisableGlobalIRQ(void)
  */
 static inline void EnableGlobalIRQ(uint32_t primask)
 {
+#if defined(CPSR_I_Msk)
+    __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
+#else
     __set_PRIMASK(primask);
+#endif
 }
 
 /*!
@@ -244,9 +303,42 @@ static inline void EnableGlobalIRQ(uint32_t primask)
  *
  * @param irq IRQ number
  * @param irqHandler IRQ handler address
+ * @return The old IRQ handler address
  */
 void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
 
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+/*!
+ * @brief Enable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Enable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
+ *
+ * @param interrupt The IRQ number.
+ */
+void EnableDeepSleepIRQ(IRQn_Type interrupt);
+
+/*!
+ * @brief Disable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Disable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
+ *
+ * @param interrupt The IRQ number.
+ */
+void DisableDeepSleepIRQ(IRQn_Type interrupt);
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_crc.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_crc.c
index f73647e1c78..dba1db8c463 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_crc.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_crc.c
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -32,6 +32,11 @@
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
+/*! @internal @brief Has data register with name CRC. */
+#if defined(FSL_FEATURE_CRC_HAS_CRC_REG) && FSL_FEATURE_CRC_HAS_CRC_REG
+#define DATA CRC
+#define DATALL CRCLL
+#endif
 
 #if defined(CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT
 /* @brief Default user configuration structure for CRC-16-CCITT */
@@ -87,7 +92,7 @@ typedef struct _crc_module_config
  *
  * @param enable True or false for the selected CRC protocol Reflect In (refin) parameter.
  */
-static inline crc_transpose_type_t crc_GetTransposeTypeFromReflectIn(bool enable)
+static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectIn(bool enable)
 {
     return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeBytes);
 }
@@ -99,7 +104,7 @@ static inline crc_transpose_type_t crc_GetTransposeTypeFromReflectIn(bool enable
  *
  * @param enable True or false for the selected CRC protocol Reflect Out (refout) parameter.
  */
-static inline crc_transpose_type_t crc_GetTransposeTypeFromReflectOut(bool enable)
+static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectOut(bool enable)
 {
     return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeNone);
 }
@@ -113,7 +118,7 @@ static inline crc_transpose_type_t crc_GetTransposeTypeFromReflectOut(bool enabl
  * @param base CRC peripheral address.
  * @param config Pointer to protocol configuration structure.
  */
-static void crc_ConfigureAndStart(CRC_Type *base, const crc_module_config_t *config)
+static void CRC_ConfigureAndStart(CRC_Type *base, const crc_module_config_t *config)
 {
     uint32_t crcControl;
 
@@ -148,18 +153,18 @@ static void crc_ConfigureAndStart(CRC_Type *base, const crc_module_config_t *con
  * @param base CRC peripheral address.
  * @param protocolConfig Pointer to protocol configuration structure.
  */
-static void crc_SetProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig)
+static void CRC_SetProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig)
 {
     crc_module_config_t moduleConfig;
     /* convert protocol to CRC peripheral module configuration, prepare for final checksum */
     moduleConfig.polynomial = protocolConfig->polynomial;
     moduleConfig.seed = protocolConfig->seed;
-    moduleConfig.readTranspose = crc_GetTransposeTypeFromReflectOut(protocolConfig->reflectOut);
-    moduleConfig.writeTranspose = crc_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn);
+    moduleConfig.readTranspose = CRC_GetTransposeTypeFromReflectOut(protocolConfig->reflectOut);
+    moduleConfig.writeTranspose = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn);
     moduleConfig.complementChecksum = protocolConfig->complementChecksum;
     moduleConfig.crcBits = protocolConfig->crcBits;
 
-    crc_ConfigureAndStart(base, &moduleConfig);
+    CRC_ConfigureAndStart(base, &moduleConfig);
 }
 
 /*!
@@ -172,7 +177,7 @@ static void crc_SetProtocolConfig(CRC_Type *base, const crc_config_t *protocolCo
  * @param base CRC peripheral address.
  * @param protocolConfig Pointer to protocol configuration structure.
  */
-static void crc_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig)
+static void CRC_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig)
 {
     crc_module_config_t moduleConfig;
     /* convert protocol to CRC peripheral module configuration, prepare for intermediate checksum */
@@ -180,25 +185,27 @@ static void crc_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protoco
     moduleConfig.seed = protocolConfig->seed;
     moduleConfig.readTranspose =
         kCrcTransposeNone; /* intermediate checksum does no transpose of data register read value */
-    moduleConfig.writeTranspose = crc_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn);
+    moduleConfig.writeTranspose = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn);
     moduleConfig.complementChecksum = false; /* intermediate checksum does no xor of data register read value */
     moduleConfig.crcBits = protocolConfig->crcBits;
 
-    crc_ConfigureAndStart(base, &moduleConfig);
+    CRC_ConfigureAndStart(base, &moduleConfig);
 }
 
 void CRC_Init(CRC_Type *base, const crc_config_t *config)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* ungate clock */
     CLOCK_EnableClock(kCLOCK_Crc0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
     /* configure CRC module and write the seed */
     if (config->crcResult == kCrcFinalChecksum)
     {
-        crc_SetProtocolConfig(base, config);
+        CRC_SetProtocolConfig(base, config);
     }
     else
     {
-        crc_SetRawProtocolConfig(base, config);
+        CRC_SetRawProtocolConfig(base, config);
     }
 }
 
@@ -246,6 +253,11 @@ void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
     }
 }
 
+uint32_t CRC_Get32bitResult(CRC_Type *base)
+{
+    return base->DATA;
+}
+
 uint16_t CRC_Get16bitResult(CRC_Type *base)
 {
     uint32_t retval;
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_crc.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_crc.h
index ce0b60fbaf9..247a9bac781 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_crc.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_crc.h
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -34,28 +34,27 @@
 #include "fsl_common.h"
 
 /*!
- * @addtogroup crc_driver
+ * @addtogroup crc
  * @{
  */
 
-/*! @file */
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief CRC driver version. Version 2.0.0. */
-#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief CRC driver version. Version 2.0.1.
+ *
+ * Current version: 2.0.1
+ *
+ * Change log:
+ * - Version 2.0.1
+ *   - move DATA and DATALL macro definition from header file to source file
+ */
+#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
 /*@}*/
 
-/*! @internal @brief Has data register with name CRC. */
-#if defined(FSL_FEATURE_CRC_HAS_CRC_REG) && FSL_FEATURE_CRC_HAS_CRC_REG
-#define DATA CRC
-#define DATALL CRCLL
-#endif
-
 #ifndef CRC_DRIVER_CUSTOM_DEFAULTS
 /*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */
 #define CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT 1
@@ -108,31 +107,33 @@ extern "C" {
 /*!
  * @brief Enables and configures the CRC peripheral module.
  *
- * This functions enables the clock gate in the Kinetis SIM module for the CRC peripheral.
- * It also configures the CRC module and starts checksum computation by writing the seed.
+ * This function enables the clock gate in the SIM module for the CRC peripheral.
+ * It also configures the CRC module and starts a checksum computation by writing the seed.
  *
  * @param base CRC peripheral address.
- * @param config CRC module configuration structure
+ * @param config CRC module configuration structure.
  */
 void CRC_Init(CRC_Type *base, const crc_config_t *config);
 
 /*!
  * @brief Disables the CRC peripheral module.
  *
- * This functions disables the clock gate in the Kinetis SIM module for the CRC peripheral.
+ * This function disables the clock gate in the SIM module for the CRC peripheral.
  *
  * @param base CRC peripheral address.
  */
 static inline void CRC_Deinit(CRC_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* gate clock */
     CLOCK_DisableClock(kCLOCK_Crc0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 /*!
- * @brief Loads default values to CRC protocol configuration structure.
+ * @brief Loads default values to the CRC protocol configuration structure.
  *
- * Loads default values to CRC protocol configuration structure. The default values are:
+ * Loads default values to the CRC protocol configuration structure. The default values are as follows.
  * @code
  *   config->polynomial = 0x1021;
  *   config->seed = 0xFFFF;
@@ -143,14 +144,14 @@ static inline void CRC_Deinit(CRC_Type *base)
  *   config->crcResult = kCrcFinalChecksum;
  * @endcode
  *
- * @param config CRC protocol configuration structure
+ * @param config CRC protocol configuration structure.
  */
 void CRC_GetDefaultConfig(crc_config_t *config);
 
 /*!
  * @brief Writes data to the CRC module.
  *
- * Writes input data buffer bytes to CRC data register.
+ * Writes input data buffer bytes to the CRC data register.
  * The configured type of transpose is applied.
  *
  * @param base CRC peripheral address.
@@ -160,27 +161,24 @@ void CRC_GetDefaultConfig(crc_config_t *config);
 void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize);
 
 /*!
- * @brief Reads 32-bit checksum from the CRC module.
+ * @brief Reads the 32-bit checksum from the CRC module.
  *
- * Reads CRC data register (intermediate or final checksum).
- * The configured type of transpose and complement are applied.
+ * Reads the CRC data register (either an intermediate or the final checksum).
+ * The configured type of transpose and complement is applied.
  *
  * @param base CRC peripheral address.
- * @return intermediate or final 32-bit checksum, after configured transpose and complement operations.
+ * @return An intermediate or the final 32-bit checksum, after configured transpose and complement operations.
  */
-static inline uint32_t CRC_Get32bitResult(CRC_Type *base)
-{
-    return base->DATA;
-}
+uint32_t CRC_Get32bitResult(CRC_Type *base);
 
 /*!
- * @brief Reads 16-bit checksum from the CRC module.
+ * @brief Reads a 16-bit checksum from the CRC module.
  *
- * Reads CRC data register (intermediate or final checksum).
- * The configured type of transpose and complement are applied.
+ * Reads the CRC data register (either an intermediate or the final checksum).
+ * The configured type of transpose and complement is applied.
  *
  * @param base CRC peripheral address.
- * @return intermediate or final 16-bit checksum, after configured transpose and complement operations.
+ * @return An intermediate or the final 16-bit checksum, after configured transpose and complement operations.
  */
 uint16_t CRC_Get16bitResult(CRC_Type *base);
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dac.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dac.c
index 2f83f5ee9e6..8d13d622835 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dac.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dac.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -45,8 +45,10 @@ static uint32_t DAC_GetInstance(DAC_Type *base);
  ******************************************************************************/
 /*! @brief Pointers to DAC bases for each instance. */
 static DAC_Type *const s_dacBases[] = DAC_BASE_PTRS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to DAC clocks for each instance. */
-const clock_ip_name_t s_dacClocks[] = DAC_CLOCKS;
+static const clock_ip_name_t s_dacClocks[] = DAC_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Codes
@@ -56,7 +58,7 @@ static uint32_t DAC_GetInstance(DAC_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_DAC_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_dacBases); instance++)
     {
         if (s_dacBases[instance] == base)
         {
@@ -64,7 +66,7 @@ static uint32_t DAC_GetInstance(DAC_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_DAC_COUNT);
+    assert(instance < ARRAY_SIZE(s_dacBases));
 
     return instance;
 }
@@ -75,8 +77,10 @@ void DAC_Init(DAC_Type *base, const dac_config_t *config)
 
     uint8_t tmp8;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the clock. */
     CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Configure. */
     /* DACx_C0. */
@@ -91,15 +95,18 @@ void DAC_Init(DAC_Type *base, const dac_config_t *config)
     }
     base->C0 = tmp8;
 
-    DAC_Enable(base, true);
+    /* DAC_Enable(base, true); */
+    /* Tip: The DAC output can be enabled till then after user sets their own available data in application. */
 }
 
 void DAC_Deinit(DAC_Type *base)
 {
     DAC_Enable(base, false);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable the clock. */
     CLOCK_DisableClock(s_dacClocks[DAC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void DAC_GetDefaultConfig(dac_config_t *config)
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dac.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dac.h
index 44e2d048bd9..b71febf3bc3 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dac.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dac.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -38,7 +38,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -46,8 +45,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief DAC driver version 2.0.0. */
-#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief DAC driver version 2.0.1. */
+#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
 /*@}*/
 
 /*!
@@ -104,15 +103,15 @@ typedef enum _dac_buffer_watermark
 #if defined(FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD
     kDAC_BufferWatermark1Word = 0U, /*!< 1 word  away from the upper limit. */
 #endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD */
-#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_2_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_2_WORD
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS
     kDAC_BufferWatermark2Word = 1U, /*!< 2 words away from the upper limit. */
-#endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_2_WORD */
-#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_3_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_3_WORD
+#endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS */
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS
     kDAC_BufferWatermark3Word = 2U, /*!< 3 words away from the upper limit. */
-#endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_3_WORD */
-#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_4_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_4_WORD
+#endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS */
+#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS
     kDAC_BufferWatermark4Word = 3U, /*!< 4 words away from the upper limit. */
-#endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_4_WORD */
+#endif                              /* FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS */
 } dac_buffer_watermark_t;
 #endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
 
@@ -137,7 +136,7 @@ typedef enum _dac_buffer_work_mode
 typedef struct _dac_config
 {
     dac_reference_voltage_source_t referenceVoltageSource; /*!< Select the DAC reference voltage source. */
-    bool enableLowPowerMode;                               /*!< Enable the low power mode. */
+    bool enableLowPowerMode;                               /*!< Enable the low-power mode. */
 } dac_config_t;
 
 /*!
@@ -150,8 +149,8 @@ typedef struct _dac_buffer_config
     dac_buffer_watermark_t watermark; /*!< Select the buffer's watermark. */
 #endif                                /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */
     dac_buffer_work_mode_t workMode;  /*!< Select the buffer's work mode. */
-    uint8_t upperLimit;               /*!< Set the upper limit for buffer index.
-                                           Normally, 0-15 is available for buffer with 16 item. */
+    uint8_t upperLimit;               /*!< Set the upper limit for the buffer index.
+                                           Normally, 0-15 is available for a buffer with 16 items. */
 } dac_buffer_config_t;
 
 /*******************************************************************************
@@ -169,7 +168,7 @@ extern "C" {
 /*!
  * @brief Initializes the DAC module.
  *
- * This function initializes the DAC module, including:
+ * This function initializes the DAC module including the following operations.
  *  - Enabling the clock for DAC module.
  *  - Configuring the DAC converter with a user configuration.
  *  - Enabling the DAC module.
@@ -182,7 +181,7 @@ void DAC_Init(DAC_Type *base, const dac_config_t *config);
 /*!
  * @brief De-initializes the DAC module.
  *
- * This function de-initializes the DAC module, including:
+ * This function de-initializes the DAC module including the following operations.
  *  - Disabling the DAC module.
  *  - Disabling the clock for the DAC module.
  *
@@ -193,7 +192,7 @@ void DAC_Deinit(DAC_Type *base);
 /*!
  * @brief Initializes the DAC user configuration structure.
  *
- * This function initializes the user configuration structure to a default value. The default values are:
+ * This function initializes the user configuration structure to a default value. The default values are as follows.
  * @code
  *   config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2;
  *   config->enableLowPowerMode = false;
@@ -206,7 +205,7 @@ void DAC_GetDefaultConfig(dac_config_t *config);
  * @brief Enables the DAC module.
  *
  * @param base DAC peripheral base address.
- * @param enable Enables the feature or not.
+ * @param enable Enables or disables the feature.
  */
 static inline void DAC_Enable(DAC_Type *base, bool enable)
 {
@@ -231,7 +230,7 @@ static inline void DAC_Enable(DAC_Type *base, bool enable)
  * @brief Enables the DAC buffer.
  *
  * @param base DAC peripheral base address.
- * @param enable Enables the feature or not.
+ * @param enable Enables or disables the feature.
  */
 static inline void DAC_EnableBuffer(DAC_Type *base, bool enable)
 {
@@ -256,7 +255,7 @@ void DAC_SetBufferConfig(DAC_Type *base, const dac_buffer_config_t *config);
 /*!
  * @brief Initializes the DAC buffer configuration structure.
  *
- * This function initializes the DAC buffer configuration structure to a default value. The default values are:
+ * This function initializes the DAC buffer configuration structure to default values. The default values are as follows.
  * @code
  *   config->triggerMode = kDAC_BufferTriggerBySoftwareMode;
  *   config->watermark   = kDAC_BufferWatermark1Word;
@@ -271,7 +270,7 @@ void DAC_GetDefaultBufferConfig(dac_buffer_config_t *config);
  * @brief Enables the DMA for DAC buffer.
  *
  * @param base DAC peripheral base address.
- * @param enable Enables the feature or not.
+ * @param enable Enables or disables the feature.
  */
 static inline void DAC_EnableBufferDMA(DAC_Type *base, bool enable)
 {
@@ -289,15 +288,15 @@ static inline void DAC_EnableBufferDMA(DAC_Type *base, bool enable)
  * @brief Sets the value for  items in the buffer.
  *
  * @param base  DAC peripheral base address.
- * @param index Setting index for items in the buffer. The available index should not exceed the size of the DAC buffer.
- * @param value Setting value for items in the buffer. 12-bits are available.
+ * @param index Setting the index for items in the buffer. The available index should not exceed the size of the DAC buffer.
+ * @param value Setting the value for items in the buffer. 12-bits are available.
  */
 void DAC_SetBufferValue(DAC_Type *base, uint8_t index, uint16_t value);
 
 /*!
- * @brief Triggers the buffer by software and updates the read pointer of the DAC buffer.
+ * @brief Triggers the buffer using software and updates the read pointer of the DAC buffer.
  *
- * This function triggers the function by software. The read pointer of the DAC buffer is updated with one step
+ * This function triggers the function using software. The read pointer of the DAC buffer is updated with one step
  * after this function is called. Changing the read pointer depends on the buffer's work mode.
  *
  * @param base DAC peripheral base address.
@@ -311,12 +310,12 @@ static inline void DAC_DoSoftwareTriggerBuffer(DAC_Type *base)
  * @brief Gets the current read pointer of the DAC buffer.
  *
  * This function gets the current read pointer of the DAC buffer.
- * The current output value depends on the item indexed by the read pointer. It is updated
- * by software trigger or hardware trigger.
+ * The current output value depends on the item indexed by the read pointer. It is updated either
+ * by a software trigger or a hardware trigger.
  *
  * @param  base DAC peripheral base address.
  *
- * @return      Current read pointer of DAC buffer.
+ * @return      The current read pointer of the DAC buffer.
  */
 static inline uint8_t DAC_GetBufferReadPointer(DAC_Type *base)
 {
@@ -327,11 +326,11 @@ static inline uint8_t DAC_GetBufferReadPointer(DAC_Type *base)
  * @brief Sets the current read pointer of the DAC buffer.
  *
  * This function sets the current read pointer of the DAC buffer.
- * The current output value depends on the item indexed by the read pointer. It is updated by
- * software trigger or hardware trigger. After the read pointer changes, the DAC output value also changes.
+ * The current output value depends on the item indexed by the read pointer. It is updated either by a
+ * software trigger or a hardware trigger. After the read pointer changes, the DAC output value also changes.
  *
  * @param base  DAC peripheral base address.
- * @param index Setting index value for the pointer.
+ * @param index Setting an index value for the pointer.
  */
 void DAC_SetBufferReadPointer(DAC_Type *base, uint8_t index);
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dmamux.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dmamux.c
index a288b9f22fc..39ce9cfbead 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dmamux.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dmamux.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -52,8 +52,10 @@ static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base);
 /*! @brief Array to map DMAMUX instance number to base pointer. */
 static DMAMUX_Type *const s_dmamuxBases[] = DMAMUX_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Array to map DMAMUX instance number to clock name. */
 static const clock_ip_name_t s_dmamuxClockName[] = DMAMUX_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
@@ -63,7 +65,7 @@ static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_DMAMUX_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_dmamuxBases); instance++)
     {
         if (s_dmamuxBases[instance] == base)
         {
@@ -71,17 +73,21 @@ static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_DMAMUX_COUNT);
+    assert(instance < ARRAY_SIZE(s_dmamuxBases));
 
     return instance;
 }
 
 void DMAMUX_Init(DMAMUX_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_EnableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void DMAMUX_Deinit(DMAMUX_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_DisableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dmamux.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dmamux.h
index f4294d4dfa8..071348b2c25 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dmamux.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dmamux.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -38,7 +38,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -46,8 +45,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief DMAMUX driver version 2.0.0. */
-#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief DMAMUX driver version 2.0.2. */
+#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
 /*@}*/
 
 /*******************************************************************************
@@ -59,14 +58,14 @@ extern "C" {
 #endif /* __cplusplus */
 
 /*!
- * @name DMAMUX Initialize and De-initialize
+ * @name DMAMUX Initialization and de-initialization
  * @{
  */
 
 /*!
- * @brief Initializes DMAMUX peripheral.
+ * @brief Initializes the DMAMUX peripheral.
  *
- * This function ungate the DMAMUX clock.
+ * This function ungates the DMAMUX clock.
  *
  * @param base DMAMUX peripheral base address.
  *
@@ -74,9 +73,9 @@ extern "C" {
 void DMAMUX_Init(DMAMUX_Type *base);
 
 /*!
- * @brief Deinitializes DMAMUX peripheral.
+ * @brief Deinitializes the DMAMUX peripheral.
  *
- * This function gate the DMAMUX clock.
+ * This function gates the DMAMUX clock.
  *
  * @param base DMAMUX peripheral base address.
  */
@@ -89,9 +88,9 @@ void DMAMUX_Deinit(DMAMUX_Type *base);
  */
 
 /*!
- * @brief Enable DMAMUX channel.
+ * @brief Enables the DMAMUX channel.
  *
- * This function enable DMAMUX channel to work.
+ * This function enables the DMAMUX channel.
  *
  * @param base DMAMUX peripheral base address.
  * @param channel DMAMUX channel number.
@@ -104,11 +103,11 @@ static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel)
 }
 
 /*!
- * @brief Disable DMAMUX channel.
+ * @brief Disables the DMAMUX channel.
  *
- * This function disable DMAMUX channel.
+ * This function disables the DMAMUX channel.
  *
- * @note User must disable DMAMUX channel before configure it.
+ * @note The user must disable the DMAMUX channel before configuring it.
  * @param base DMAMUX peripheral base address.
  * @param channel DMAMUX channel number.
  */
@@ -120,13 +119,13 @@ static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel)
 }
 
 /*!
- * @brief Configure DMAMUX channel source.
+ * @brief Configures the DMAMUX channel source.
  *
  * @param base DMAMUX peripheral base address.
  * @param channel DMAMUX channel number.
- * @param source Channel source which is used to trigger DMA transfer.
+ * @param source Channel source, which is used to trigger the DMA transfer.
  */
-static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint8_t source)
+static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_t source)
 {
     assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
 
@@ -135,9 +134,9 @@ static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint8_t
 
 #if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U
 /*!
- * @brief Enable DMAMUX period trigger.
+ * @brief Enables the DMAMUX period trigger.
  *
- * This function enable DMAMUX period trigger feature.
+ * This function enables the DMAMUX period trigger feature.
  *
  * @param base DMAMUX peripheral base address.
  * @param channel DMAMUX channel number.
@@ -150,9 +149,9 @@ static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channe
 }
 
 /*!
- * @brief Disable DMAMUX period trigger.
+ * @brief Disables the DMAMUX period trigger.
  *
- * This function disable DMAMUX period trigger.
+ * This function disables the DMAMUX period trigger.
  *
  * @param base DMAMUX peripheral base address.
  * @param channel DMAMUX channel number.
@@ -165,6 +164,31 @@ static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t chann
 }
 #endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */
 
+#if (defined(FSL_FEATURE_DMAMUX_HAS_A_ON) && FSL_FEATURE_DMAMUX_HAS_A_ON)
+/*!
+ * @brief Enables the DMA channel to be always ON.
+ *
+ * This function enables the DMAMUX channel always ON feature.
+ *
+ * @param base DMAMUX peripheral base address.
+ * @param channel DMAMUX channel number.
+ * @param enable Switcher of the always ON feature. "true" means enabled, "false" means disabled.
+ */
+static inline void DMAMUX_EnableAlwaysOn(DMAMUX_Type *base, uint32_t channel, bool enable)
+{
+    assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL);
+
+    if (enable)
+    {
+        base->CHCFG[channel] |= DMAMUX_CHCFG_A_ON_MASK;
+    }
+    else
+    {
+        base->CHCFG[channel] &= ~DMAMUX_CHCFG_A_ON_MASK;
+    }
+}
+#endif /* FSL_FEATURE_DMAMUX_HAS_A_ON */
+
 /* @} */
 
 #if defined(__cplusplus)
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi.c
index 5654ce7aac6..d3b3f0aa5f7 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi.c
@@ -1,32 +1,32 @@
 /*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-*   of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-*   list of conditions and the following disclaimer in the documentation and/or
-*   other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-*   contributors may be used to endorse or promote products derived from this
-*   software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #include "fsl_dspi.h"
 
@@ -65,27 +65,27 @@ static void DSPI_SetOnePcsPolarity(SPI_Type *base, dspi_which_pcs_t pcs, dspi_pc
 
 /*!
  * @brief Master fill up the TX FIFO with data.
- * This is not a public API as it is called from other driver functions.
+ * This is not a public API.
  */
 static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t *handle);
 
 /*!
  * @brief Master finish up a transfer.
  * It would call back if there is callback function and set the state to idle.
- * This is not a public API as it is called from other driver functions.
+ * This is not a public API.
  */
 static void DSPI_MasterTransferComplete(SPI_Type *base, dspi_master_handle_t *handle);
 
 /*!
  * @brief Slave fill up the TX FIFO with data.
- * This is not a public API as it is called from other driver functions.
+ * This is not a public API.
  */
 static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t *handle);
 
 /*!
  * @brief Slave finish up a transfer.
  * It would call back if there is callback function and set the state to idle.
- * This is not a public API as it is called from other driver functions.
+ * This is not a public API.
  */
 static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *handle);
 
@@ -100,7 +100,7 @@ static void DSPI_CommonIRQHandler(SPI_Type *base, void *param);
 /*!
  * @brief Master prepare the transfer.
  * Basically it set up dspi_master_handle .
- * This is not a public API as it is called from other driver functions. fsl_dspi_edma.c also call this function.
+ * This is not a public API.
  */
 static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer);
 
@@ -123,11 +123,13 @@ static SPI_Type *const s_dspiBases[] = SPI_BASE_PTRS;
 /*! @brief Pointers to dspi IRQ number for each instance. */
 static IRQn_Type const s_dspiIRQ[] = SPI_IRQS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to dspi clocks for each instance. */
 static clock_ip_name_t const s_dspiClock[] = DSPI_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*! @brief Pointers to dspi handles for each instance. */
-static void *g_dspiHandle[FSL_FEATURE_SOC_DSPI_COUNT];
+static void *g_dspiHandle[ARRAY_SIZE(s_dspiBases)];
 
 /*! @brief Pointer to master IRQ handler for each instance. */
 static dspi_master_isr_t s_dspiMasterIsr;
@@ -135,6 +137,8 @@ static dspi_master_isr_t s_dspiMasterIsr;
 /*! @brief Pointer to slave IRQ handler for each instance. */
 static dspi_slave_isr_t s_dspiSlaveIsr;
 
+/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/
+volatile uint8_t s_dummyData[ARRAY_SIZE(s_dspiBases)] = {0};
 /**********************************************************************************************************************
 * Code
 *********************************************************************************************************************/
@@ -143,7 +147,7 @@ uint32_t DSPI_GetInstance(SPI_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_DSPI_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_dspiBases); instance++)
     {
         if (s_dspiBases[instance] == base)
         {
@@ -151,16 +155,26 @@ uint32_t DSPI_GetInstance(SPI_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_DSPI_COUNT);
+    assert(instance < ARRAY_SIZE(s_dspiBases));
 
     return instance;
 }
 
+void DSPI_SetDummyData(SPI_Type *base, uint8_t dummyData)
+{
+    uint32_t instance = DSPI_GetInstance(base);
+    s_dummyData[instance] = dummyData;
+}
+
 void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz)
 {
+    assert(masterConfig);
+
     uint32_t temp;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* enable DSPI clock */
     CLOCK_EnableClock(s_dspiClock[DSPI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     DSPI_Enable(base, true);
     DSPI_StopTransfer(base);
@@ -196,11 +210,14 @@ void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, u
     DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_BetweenTransfer, srcClock_Hz,
                              masterConfig->ctarConfig.betweenTransferDelayInNanoSec);
 
+    DSPI_SetDummyData(base, DSPI_DUMMY_DATA);
     DSPI_StartTransfer(base);
 }
 
 void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig)
 {
+    assert(masterConfig);
+
     masterConfig->whichCtar = kDSPI_Ctar0;
     masterConfig->ctarConfig.baudRate = 500000;
     masterConfig->ctarConfig.bitsPerFrame = 8;
@@ -223,10 +240,14 @@ void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig)
 
 void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig)
 {
+    assert(slaveConfig);
+
     uint32_t temp = 0;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* enable DSPI clock */
     CLOCK_EnableClock(s_dspiClock[DSPI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     DSPI_Enable(base, true);
     DSPI_StopTransfer(base);
@@ -250,11 +271,15 @@ void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig)
                                          SPI_CTAR_SLAVE_CPOL(slaveConfig->ctarConfig.cpol) |
                                          SPI_CTAR_SLAVE_CPHA(slaveConfig->ctarConfig.cpha);
 
+    DSPI_SetDummyData(base, DSPI_DUMMY_DATA);
+
     DSPI_StartTransfer(base);
 }
 
 void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig)
 {
+    assert(slaveConfig);
+
     slaveConfig->whichCtar = kDSPI_Ctar0;
     slaveConfig->ctarConfig.bitsPerFrame = 8;
     slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
@@ -271,8 +296,10 @@ void DSPI_Deinit(SPI_Type *base)
     DSPI_StopTransfer(base);
     DSPI_Enable(base, false);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* disable DSPI clock */
     CLOCK_DisableClock(s_dspiClock[DSPI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 static void DSPI_SetOnePcsPolarity(SPI_Type *base, dspi_which_pcs_t pcs, dspi_pcs_polarity_config_t activeLowOrHigh)
@@ -457,6 +484,8 @@ uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base,
 
 void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command)
 {
+    assert(command);
+
     command->isPcsContinuous = false;
     command->whichCtar = kDSPI_Ctar0;
     command->whichPcs = kDSPI_Pcs0;
@@ -466,6 +495,8 @@ void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command)
 
 void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data)
 {
+    assert(command);
+
     /* First, clear Transmit Complete Flag (TCF) */
     DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag);
 
@@ -562,7 +593,7 @@ status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer)
 
     uint16_t wordToSend = 0;
     uint16_t wordReceived = 0;
-    uint8_t dummyData = DSPI_MASTER_DUMMY_DATA;
+    uint8_t dummyData = s_dummyData[DSPI_GetInstance(base)];
     uint8_t bitsPerFrame;
 
     uint32_t command;
@@ -598,6 +629,7 @@ status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer)
 
     command = DSPI_MasterGetFormattedCommand(&(commandStruct));
 
+    commandStruct.isEndOfQueue = true;
     commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer);
     lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct));
 
@@ -626,25 +658,6 @@ status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer)
         {
             if (remainingSendByteCount == 1)
             {
-                while ((remainingReceiveByteCount - remainingSendByteCount) >= fifoSize)
-                {
-                    if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
-                    {
-                        if (rxData != NULL)
-                        {
-                            *(rxData) = DSPI_ReadData(base);
-                            rxData++;
-                        }
-                        else
-                        {
-                            DSPI_ReadData(base);
-                        }
-                        remainingReceiveByteCount--;
-
-                        DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
-                    }
-                }
-
                 while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag))
                 {
                     DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
@@ -702,20 +715,23 @@ status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer)
 
                 DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
 
-                if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
+                while ((remainingReceiveByteCount - remainingSendByteCount) >= fifoSize)
                 {
-                    if (rxData != NULL)
-                    {
-                        *(rxData) = DSPI_ReadData(base);
-                        rxData++;
-                    }
-                    else
+                    if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
                     {
-                        DSPI_ReadData(base);
-                    }
-                    remainingReceiveByteCount--;
+                        if (rxData != NULL)
+                        {
+                            *(rxData) = DSPI_ReadData(base);
+                            rxData++;
+                        }
+                        else
+                        {
+                            DSPI_ReadData(base);
+                        }
+                        remainingReceiveByteCount--;
 
-                    DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
+                        DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
+                    }
                 }
             }
         }
@@ -726,25 +742,6 @@ status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer)
         {
             if (remainingSendByteCount <= 2)
             {
-                while (((remainingReceiveByteCount - remainingSendByteCount) / 2) >= fifoSize)
-                {
-                    if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
-                    {
-                        wordReceived = DSPI_ReadData(base);
-
-                        if (rxData != NULL)
-                        {
-                            *rxData = wordReceived;
-                            ++rxData;
-                            *rxData = wordReceived >> 8;
-                            ++rxData;
-                        }
-                        remainingReceiveByteCount -= 2;
-
-                        DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
-                    }
-                }
-
                 while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag))
                 {
                     DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
@@ -825,20 +822,23 @@ status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer)
 
                 DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
 
-                if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
+                while (((remainingReceiveByteCount - remainingSendByteCount) / 2) >= fifoSize)
                 {
-                    wordReceived = DSPI_ReadData(base);
-
-                    if (rxData != NULL)
+                    if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag)
                     {
-                        *rxData = wordReceived;
-                        ++rxData;
-                        *rxData = wordReceived >> 8;
-                        ++rxData;
-                    }
-                    remainingReceiveByteCount -= 2;
+                        wordReceived = DSPI_ReadData(base);
+
+                        if (rxData != NULL)
+                        {
+                            *rxData = wordReceived;
+                            ++rxData;
+                            *rxData = wordReceived >> 8;
+                            ++rxData;
+                        }
+                        remainingReceiveByteCount -= 2;
 
-                    DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
+                        DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag);
+                    }
                 }
             }
         }
@@ -849,6 +849,9 @@ status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer)
 
 static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer)
 {
+    assert(handle);
+    assert(transfer);
+
     dspi_command_data_config_t commandStruct;
 
     DSPI_StopTransfer(base);
@@ -864,6 +867,7 @@ static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *han
     commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterPcsContinuous);
     handle->command = DSPI_MasterGetFormattedCommand(&(commandStruct));
 
+    commandStruct.isEndOfQueue = true;
     commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer);
     handle->lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct));
 
@@ -886,7 +890,8 @@ static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *han
 
 status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer)
 {
-    assert(handle && transfer);
+    assert(handle);
+    assert(transfer);
 
     /* If the transfer count is zero, then return immediately.*/
     if (transfer->dataSize == 0)
@@ -903,13 +908,10 @@ status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *ha
     handle->state = kDSPI_Busy;
 
     DSPI_MasterTransferPrepare(base, handle, transfer);
-    DSPI_StartTransfer(base);
 
     /* Enable the NVIC for DSPI peripheral. */
     EnableIRQ(s_dspiIRQ[DSPI_GetInstance(base)]);
 
-    DSPI_MasterTransferFillUpTxFifo(base, handle);
-
     /* RX FIFO Drain request: RFDF_RE to enable RFDF interrupt
     * Since SPI is a synchronous interface, we only need to enable the RX interrupt.
     * The IRQ handler will get the status of RX and TX interrupt flags.
@@ -917,7 +919,10 @@ status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *ha
     s_dspiMasterIsr = DSPI_MasterTransferHandleIRQ;
 
     DSPI_EnableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable);
+    DSPI_StartTransfer(base);
 
+    /* Fill up the Tx FIFO to trigger the transfer. */
+    DSPI_MasterTransferFillUpTxFifo(base, handle);
     return kStatus_Success;
 }
 
@@ -943,6 +948,8 @@ status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handl
 
 static void DSPI_MasterTransferComplete(SPI_Type *base, dspi_master_handle_t *handle)
 {
+    assert(handle);
+
     /* Disable interrupt requests*/
     DSPI_DisableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable);
 
@@ -956,19 +963,20 @@ static void DSPI_MasterTransferComplete(SPI_Type *base, dspi_master_handle_t *ha
         status = kStatus_Success;
     }
 
+    handle->state = kDSPI_Idle;
+
     if (handle->callback)
     {
         handle->callback(base, handle, status, handle->userData);
     }
-
-    /* The transfer is complete.*/
-    handle->state = kDSPI_Idle;
 }
 
 static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t *handle)
 {
+    assert(handle);
+
     uint16_t wordToSend = 0;
-    uint8_t dummyData = DSPI_MASTER_DUMMY_DATA;
+    uint8_t dummyData = s_dummyData[DSPI_GetInstance(base)];
 
     /* If bits/frame is greater than one byte */
     if (handle->bitsPerFrame > 8)
@@ -1081,6 +1089,8 @@ static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t
 
 void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle)
 {
+    assert(handle);
+
     DSPI_StopTransfer(base);
 
     /* Disable interrupt requests*/
@@ -1091,6 +1101,8 @@ void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle)
 
 void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle)
 {
+    assert(handle);
+
     /* RECEIVE IRQ handler: Check read buffer only if there are remaining bytes to read. */
     if (handle->remainingReceiveByteCount)
     {
@@ -1212,7 +1224,8 @@ void DSPI_SlaveTransferCreateHandle(SPI_Type *base,
 
 status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer)
 {
-    assert(handle && transfer);
+    assert(handle);
+    assert(transfer);
 
     /* If receive length is zero */
     if (transfer->dataSize == 0)
@@ -1254,11 +1267,6 @@ status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *hand
     DSPI_FlushFifo(base, true, true);
     DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag);
 
-    DSPI_StartTransfer(base);
-
-    /* Prepare data to transmit */
-    DSPI_SlaveTransferFillUpTxFifo(base, handle);
-
     s_dspiSlaveIsr = DSPI_SlaveTransferHandleIRQ;
 
     /* Enable RX FIFO drain request, the slave only use this interrupt */
@@ -1275,6 +1283,11 @@ status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *hand
         DSPI_EnableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable);
     }
 
+    DSPI_StartTransfer(base);
+
+    /* Prepare data to transmit */
+    DSPI_SlaveTransferFillUpTxFifo(base, handle);
+
     return kStatus_Success;
 }
 
@@ -1300,8 +1313,10 @@ status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle,
 
 static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t *handle)
 {
+    assert(handle);
+
     uint16_t transmitData = 0;
-    uint8_t dummyPattern = DSPI_SLAVE_DUMMY_DATA;
+    uint8_t dummyPattern = s_dummyData[DSPI_GetInstance(base)];
 
     /* Service the transmitter, if transmit buffer provided, transmit the data,
     * else transmit dummy pattern
@@ -1386,6 +1401,8 @@ static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t *
 
 static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *handle)
 {
+    assert(handle);
+
     /* Disable interrupt requests */
     DSPI_DisableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable |
                                      kDSPI_RxFifoOverflowInterruptEnable | kDSPI_RxFifoDrainRequestInterruptEnable);
@@ -1406,16 +1423,18 @@ static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *hand
         status = kStatus_Success;
     }
 
+    handle->state = kDSPI_Idle;
+
     if (handle->callback)
     {
         handle->callback(base, handle, status, handle->userData);
     }
-
-    handle->state = kDSPI_Idle;
 }
 
 void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle)
 {
+    assert(handle);
+
     DSPI_StopTransfer(base);
 
     /* Disable interrupt requests */
@@ -1429,7 +1448,9 @@ void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle)
 
 void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle)
 {
-    uint8_t dummyPattern = DSPI_SLAVE_DUMMY_DATA;
+    assert(handle);
+
+    uint8_t dummyPattern = s_dummyData[DSPI_GetInstance(base)];
     uint32_t dataReceived;
     uint32_t dataSend = 0;
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi.h
index 93da32fa2f7..abfc7707d75 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -33,27 +33,24 @@
 #include "fsl_common.h"
 
 /*!
- * @addtogroup dspi
+ * @addtogroup dspi_driver
  * @{
  */
 
-/*! @file */
-
 /**********************************************************************************************************************
  * Definitions
  *********************************************************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief DSPI driver version 2.1.0. */
-#define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*! @brief DSPI driver version 2.2.0. */
+#define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
 /*@}*/
 
-/*! @name Dummy data */
-/*@{*/
-#define DSPI_MASTER_DUMMY_DATA (0x00U) /*!< Master dummy data used for tx if there is not txData. */
-#define DSPI_SLAVE_DUMMY_DATA (0x00U)  /*!< Slave dummy data used for tx if there is not txData. */
-/*@}*/
+#ifndef DSPI_DUMMY_DATA
+/*! @brief DSPI dummy data if there is no Tx data.*/
+#define DSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for Tx if there is no txData. */
+#endif
 
 /*! @brief Status for the DSPI driver.*/
 enum _dspi_status
@@ -61,7 +58,7 @@ enum _dspi_status
     kStatus_DSPI_Busy = MAKE_STATUS(kStatusGroup_DSPI, 0),      /*!< DSPI transfer is busy.*/
     kStatus_DSPI_Error = MAKE_STATUS(kStatusGroup_DSPI, 1),     /*!< DSPI driver error. */
     kStatus_DSPI_Idle = MAKE_STATUS(kStatusGroup_DSPI, 2),      /*!< DSPI is idle.*/
-    kStatus_DSPI_OutOfRange = MAKE_STATUS(kStatusGroup_DSPI, 3) /*!< DSPI transfer out Of range. */
+    kStatus_DSPI_OutOfRange = MAKE_STATUS(kStatusGroup_DSPI, 3) /*!< DSPI transfer out of range. */
 };
 
 /*! @brief DSPI status flags in SPIx_SR register.*/
@@ -75,7 +72,7 @@ enum _dspi_flags
     kDSPI_RxFifoDrainRequestFlag = SPI_SR_RFDF_MASK, /*!< Receive FIFO Drain Flag.*/
     kDSPI_TxAndRxStatusFlag = SPI_SR_TXRXS_MASK,     /*!< The module is in Stopped/Running state.*/
     kDSPI_AllStatusFlag = SPI_SR_TCF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TFFF_MASK | SPI_SR_RFOF_MASK |
-                          SPI_SR_RFDF_MASK | SPI_SR_TXRXS_MASK /*!< All status above.*/
+                          SPI_SR_RFDF_MASK | SPI_SR_TXRXS_MASK /*!< All statuses above.*/
 };
 
 /*! @brief DSPI interrupt source.*/
@@ -109,8 +106,9 @@ typedef enum _dspi_master_slave_mode
 } dspi_master_slave_mode_t;
 
 /*!
- * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in Modified Transfer Format. This field is valid
- * only when CPHA bit in CTAR register is 0.
+ * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in the Modified Transfer Format. This field is
+ * valid
+ * only when the CPHA bit in the CTAR register is 0.
  */
 typedef enum _dspi_master_sample_point
 {
@@ -169,36 +167,37 @@ typedef enum _dspi_clock_phase
 typedef enum _dspi_shift_direction
 {
     kDSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/
-    kDSPI_LsbFirst = 1U  /*!< Data transfers start with least significant bit.*/
+    kDSPI_LsbFirst = 1U  /*!< Data transfers start with least significant bit.
+                              Shifting out of LSB is not supported for slave */
 } dspi_shift_direction_t;
 
 /*! @brief DSPI delay type selection.*/
 typedef enum _dspi_delay_type
 {
     kDSPI_PcsToSck = 1U,  /*!< Pcs-to-SCK delay. */
-    kDSPI_LastSckToPcs,   /*!< Last SCK edge to Pcs delay. */
+    kDSPI_LastSckToPcs,   /*!< The last SCK edge to Pcs delay. */
     kDSPI_BetweenTransfer /*!< Delay between transfers. */
 } dspi_delay_type_t;
 
 /*! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection.*/
 typedef enum _dspi_ctar_selection
 {
-    kDSPI_Ctar0 = 0U, /*!< CTAR0 selection option for master or slave mode, note that CTAR0 and CTAR0_SLAVE are the
+    kDSPI_Ctar0 = 0U, /*!< CTAR0 selection option for master or slave mode; note that CTAR0 and CTAR0_SLAVE are the
                          same register address. */
     kDSPI_Ctar1 = 1U, /*!< CTAR1 selection option for master mode only. */
-    kDSPI_Ctar2 = 2U, /*!< CTAR2 selection option for master mode only , note that some device do not support CTAR2. */
-    kDSPI_Ctar3 = 3U, /*!< CTAR3 selection option for master mode only , note that some device do not support CTAR3. */
-    kDSPI_Ctar4 = 4U, /*!< CTAR4 selection option for master mode only , note that some device do not support CTAR4. */
-    kDSPI_Ctar5 = 5U, /*!< CTAR5 selection option for master mode only , note that some device do not support CTAR5. */
-    kDSPI_Ctar6 = 6U, /*!< CTAR6 selection option for master mode only , note that some device do not support CTAR6. */
-    kDSPI_Ctar7 = 7U  /*!< CTAR7 selection option for master mode only , note that some device do not support CTAR7. */
+    kDSPI_Ctar2 = 2U, /*!< CTAR2 selection option for master mode only; note that some devices do not support CTAR2. */
+    kDSPI_Ctar3 = 3U, /*!< CTAR3 selection option for master mode only; note that some devices do not support CTAR3. */
+    kDSPI_Ctar4 = 4U, /*!< CTAR4 selection option for master mode only; note that some devices do not support CTAR4. */
+    kDSPI_Ctar5 = 5U, /*!< CTAR5 selection option for master mode only; note that some devices do not support CTAR5. */
+    kDSPI_Ctar6 = 6U, /*!< CTAR6 selection option for master mode only; note that some devices do not support CTAR6. */
+    kDSPI_Ctar7 = 7U  /*!< CTAR7 selection option for master mode only; note that some devices do not support CTAR7. */
 } dspi_ctar_selection_t;
 
-#define DSPI_MASTER_CTAR_SHIFT (0U)   /*!< DSPI master CTAR shift macro , internal used. */
-#define DSPI_MASTER_CTAR_MASK (0x0FU) /*!< DSPI master CTAR mask macro , internal used. */
-#define DSPI_MASTER_PCS_SHIFT (4U)    /*!< DSPI master PCS shift macro , internal used. */
-#define DSPI_MASTER_PCS_MASK (0xF0U)  /*!< DSPI master PCS mask macro , internal used. */
-/*! @brief Can use this enumeration for DSPI master transfer configFlags. */
+#define DSPI_MASTER_CTAR_SHIFT (0U)   /*!< DSPI master CTAR shift macro; used internally. */
+#define DSPI_MASTER_CTAR_MASK (0x0FU) /*!< DSPI master CTAR mask macro; used internally. */
+#define DSPI_MASTER_PCS_SHIFT (4U)    /*!< DSPI master PCS shift macro; used internally. */
+#define DSPI_MASTER_PCS_MASK (0xF0U)  /*!< DSPI master PCS mask macro; used internally. */
+/*! @brief Use this enumeration for the DSPI master transfer configFlags. */
 enum _dspi_transfer_config_flag_for_master
 {
     kDSPI_MasterCtar0 = 0U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR0 setting. */
@@ -217,20 +216,21 @@ enum _dspi_transfer_config_flag_for_master
     kDSPI_MasterPcs4 = 4U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS4 signal. */
     kDSPI_MasterPcs5 = 5U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS5 signal. */
 
-    kDSPI_MasterPcsContinuous = 1U << 20,       /*!< Is PCS signal continuous. */
-    kDSPI_MasterActiveAfterTransfer = 1U << 21, /*!< Is PCS signal active after last frame transfer.*/
+    kDSPI_MasterPcsContinuous = 1U << 20,       /*!< Indicates whether the PCS signal is continuous. */
+    kDSPI_MasterActiveAfterTransfer =
+        1U << 21, /*!< Indicates whether the PCS signal is active after the last frame transfer.*/
 };
 
-#define DSPI_SLAVE_CTAR_SHIFT (0U)   /*!< DSPI slave CTAR shift macro , internal used. */
-#define DSPI_SLAVE_CTAR_MASK (0x07U) /*!< DSPI slave CTAR mask macro , internal used. */
-/*! @brief Can use this enum for DSPI slave transfer configFlags. */
+#define DSPI_SLAVE_CTAR_SHIFT (0U)   /*!< DSPI slave CTAR shift macro; used internally. */
+#define DSPI_SLAVE_CTAR_MASK (0x07U) /*!< DSPI slave CTAR mask macro; used internally. */
+/*! @brief Use this enumeration for the DSPI slave transfer configFlags. */
 enum _dspi_transfer_config_flag_for_slave
 {
     kDSPI_SlaveCtar0 = 0U << DSPI_SLAVE_CTAR_SHIFT, /*!< DSPI slave transfer use CTAR0 setting. */
                                                     /*!< DSPI slave can only use PCS0. */
 };
 
-/*! @brief DSPI transfer state, which is used for DSPI transactional APIs' state machine. */
+/*! @brief DSPI transfer state, which is used for DSPI transactional API state machine. */
 enum _dspi_transfer_state
 {
     kDSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */
@@ -238,15 +238,15 @@ enum _dspi_transfer_state
     kDSPI_Error        /*!< Transfer error. */
 };
 
-/*! @brief DSPI master command date configuration used for SPIx_PUSHR.*/
+/*! @brief DSPI master command date configuration used for the SPIx_PUSHR.*/
 typedef struct _dspi_command_data_config
 {
-    bool isPcsContinuous;            /*!< Option to enable the continuous assertion of chip select between transfers.*/
+    bool isPcsContinuous;            /*!< Option to enable the continuous assertion of the chip select between transfers.*/
     dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes
                                           Register (CTAR) to use for CTAS.*/
     dspi_which_pcs_t whichPcs;       /*!< The desired PCS signal to use for the data transfer.*/
     bool isEndOfQueue;               /*!< Signals that the current transfer is the last in the queue.*/
-    bool clearTransferCount;         /*!< Clears SPI Transfer Counter (SPI_TCNT) before transmission starts.*/
+    bool clearTransferCount;         /*!< Clears the SPI Transfer Counter (SPI_TCNT) before transmission starts.*/
 } dspi_command_data_config_t;
 
 /*! @brief DSPI master ctar configuration structure.*/
@@ -258,33 +258,33 @@ typedef struct _dspi_master_ctar_config
     dspi_clock_phase_t cpha;          /*!< Clock phase. */
     dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */
 
-    uint32_t pcsToSckDelayInNanoSec;        /*!< PCS to SCK delay time with nanosecond , set to 0 sets the minimum
-                                               delay. It sets the boundary value if out of range that can be set.*/
-    uint32_t lastSckToPcsDelayInNanoSec;    /*!< Last SCK to PCS delay time with nanosecond , set to 0 sets the
-                                               minimum delay.It sets the boundary value if out of range that can be
-                                               set.*/
-    uint32_t betweenTransferDelayInNanoSec; /*!< After SCK delay time with nanosecond , set to 0 sets the minimum
-                                             delay.It sets the boundary value if out of range that can be set.*/
+    uint32_t pcsToSckDelayInNanoSec;        /*!< PCS to SCK delay time in nanoseconds; setting to 0 sets the minimum
+                                               delay. It also sets the boundary value if out of range.*/
+    uint32_t lastSckToPcsDelayInNanoSec;    /*!< The last SCK to PCS delay time in nanoseconds; setting to 0 sets the
+                                               minimum delay. It also sets the boundary value if out of range.*/
+
+    uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time in nanoseconds; setting to 0 sets the minimum
+                                             delay. It also sets the boundary value if out of range.*/
 } dspi_master_ctar_config_t;
 
 /*! @brief DSPI master configuration structure.*/
 typedef struct _dspi_master_config
 {
-    dspi_ctar_selection_t whichCtar;      /*!< Desired CTAR to use. */
+    dspi_ctar_selection_t whichCtar;      /*!< The desired CTAR to use. */
     dspi_master_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */
 
-    dspi_which_pcs_t whichPcs;                     /*!< Desired Peripheral Chip Select (pcs). */
-    dspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low. */
+    dspi_which_pcs_t whichPcs;                     /*!< The desired Peripheral Chip Select (pcs). */
+    dspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< The desired PCS active high or low. */
 
-    bool enableContinuousSCK;   /*!< CONT_SCKE, continuous SCK enable . Note that continuous SCK is only
+    bool enableContinuousSCK;   /*!< CONT_SCKE, continuous SCK enable. Note that the continuous SCK is only
                                      supported for CPHA = 1.*/
-    bool enableRxFifoOverWrite; /*!< ROOE, Receive FIFO overflow overwrite enable. ROOE = 0, the incoming
-                                     data is ignored, the data from the transfer that generated the overflow
-                                     is either ignored. ROOE = 1, the incoming data is shifted in to the
-                                     shift to the shift register. */
+    bool enableRxFifoOverWrite; /*!< ROOE, receive FIFO overflow overwrite enable. If ROOE = 0, the incoming
+                                     data is ignored and the data from the transfer that generated the overflow
+                                     is also ignored. If ROOE = 1, the incoming data is shifted to the
+                                     shift register. */
 
-    bool enableModifiedTimingFormat;        /*!< Enables a modified transfer format to be used if it's true.*/
-    dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in Modified Transfer
+    bool enableModifiedTimingFormat;        /*!< Enables a modified transfer format to be used if true.*/
+    dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in the Modified Transfer
                                                  Format. It's valid only when CPHA=0. */
 } dspi_master_config_t;
 
@@ -294,23 +294,23 @@ typedef struct _dspi_slave_ctar_config
     uint32_t bitsPerFrame;      /*!< Bits per frame, minimum 4, maximum 16.*/
     dspi_clock_polarity_t cpol; /*!< Clock polarity. */
     dspi_clock_phase_t cpha;    /*!< Clock phase. */
-                                /*!< Slave only supports MSB , does not support LSB.*/
+                                /*!< Slave only supports MSB and does not support LSB.*/
 } dspi_slave_ctar_config_t;
 
 /*! @brief DSPI slave configuration structure.*/
 typedef struct _dspi_slave_config
 {
-    dspi_ctar_selection_t whichCtar;     /*!< Desired CTAR to use. */
+    dspi_ctar_selection_t whichCtar;     /*!< The desired CTAR to use. */
     dspi_slave_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */
 
-    bool enableContinuousSCK;               /*!< CONT_SCKE, continuous SCK enable. Note that continuous SCK is only
+    bool enableContinuousSCK;               /*!< CONT_SCKE, continuous SCK enable. Note that the continuous SCK is only
                                                  supported for CPHA = 1.*/
-    bool enableRxFifoOverWrite;             /*!< ROOE, Receive FIFO overflow overwrite enable. ROOE = 0, the incoming
-                                                 data is ignored, the data from the transfer that generated the overflow
-                                                 is either ignored. ROOE = 1, the incoming data is shifted in to the
-                                                 shift to the shift register. */
-    bool enableModifiedTimingFormat;        /*!< Enables a modified transfer format to be used if it's true.*/
-    dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in Modified Transfer
+    bool enableRxFifoOverWrite;             /*!< ROOE, receive FIFO overflow overwrite enable. If ROOE = 0, the incoming
+                                                 data is ignored and the data from the transfer that generated the overflow
+                                                 is also ignored. If ROOE = 1, the incoming data is shifted to the
+                                                 shift register. */
+    bool enableModifiedTimingFormat;        /*!< Enables a modified transfer format to be used if true.*/
+    dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in the Modified Transfer
                                                Format. It's valid only when CPHA=0. */
 } dspi_slave_config_t;
 
@@ -357,7 +357,7 @@ typedef struct _dspi_transfer
     volatile size_t dataSize; /*!< Transfer bytes. */
 
     uint32_t
-        configFlags; /*!< Transfer transfer configuration flags , set from _dspi_transfer_config_flag_for_master if the
+        configFlags; /*!< Transfer transfer configuration flags; set from _dspi_transfer_config_flag_for_master if the
                         transfer is used for master or _dspi_transfer_config_flag_for_slave enumeration if the transfer
                         is used for slave.*/
 } dspi_transfer_t;
@@ -365,38 +365,39 @@ typedef struct _dspi_transfer
 /*! @brief DSPI master transfer handle structure used for transactional API. */
 struct _dspi_master_handle
 {
-    uint32_t bitsPerFrame;         /*!< Desired number of bits per frame. */
-    volatile uint32_t command;     /*!< Desired data command. */
-    volatile uint32_t lastCommand; /*!< Desired last data command. */
+    uint32_t bitsPerFrame;         /*!< The desired number of bits per frame. */
+    volatile uint32_t command;     /*!< The desired data command. */
+    volatile uint32_t lastCommand; /*!< The desired last data command. */
 
     uint8_t fifoSize; /*!< FIFO dataSize. */
 
-    volatile bool isPcsActiveAfterTransfer; /*!< Is PCS signal keep active after the last frame transfer.*/
-    volatile bool isThereExtraByte;         /*!< Is there extra byte.*/
+    volatile bool
+        isPcsActiveAfterTransfer;   /*!< Indicates whether the PCS signal is active after the last frame transfer.*/
+    volatile bool isThereExtraByte;         /*!< Indicates whether there are extra bytes.*/
 
     uint8_t *volatile txData;                  /*!< Send buffer. */
     uint8_t *volatile rxData;                  /*!< Receive buffer. */
-    volatile size_t remainingSendByteCount;    /*!< Number of bytes remaining to send.*/
-    volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/
-    size_t totalByteCount;                     /*!< Number of transfer bytes*/
+    volatile size_t remainingSendByteCount;    /*!< A number of bytes remaining to send.*/
+    volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/
+    size_t totalByteCount;                     /*!< A number of transfer bytes*/
 
-    volatile uint8_t state; /*!< DSPI transfer state , _dspi_transfer_state.*/
+    volatile uint8_t state; /*!< DSPI transfer state, see _dspi_transfer_state.*/
 
     dspi_master_transfer_callback_t callback; /*!< Completion callback. */
     void *userData;                           /*!< Callback user data. */
 };
 
-/*! @brief DSPI slave transfer handle structure used for transactional API. */
+/*! @brief DSPI slave transfer handle structure used for the transactional API. */
 struct _dspi_slave_handle
 {
-    uint32_t bitsPerFrame;          /*!< Desired number of bits per frame. */
-    volatile bool isThereExtraByte; /*!< Is there extra byte.*/
+    uint32_t bitsPerFrame;          /*!< The desired number of bits per frame. */
+    volatile bool isThereExtraByte; /*!< Indicates whether there are extra bytes.*/
 
     uint8_t *volatile txData;                  /*!< Send buffer. */
     uint8_t *volatile rxData;                  /*!< Receive buffer. */
-    volatile size_t remainingSendByteCount;    /*!< Number of bytes remaining to send.*/
-    volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/
-    size_t totalByteCount;                     /*!< Number of transfer bytes*/
+    volatile size_t remainingSendByteCount;    /*!< A number of bytes remaining to send.*/
+    volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/
+    size_t totalByteCount;                     /*!< A number of transfer bytes*/
 
     volatile uint8_t state; /*!< DSPI transfer state.*/
 
@@ -421,18 +422,18 @@ extern "C" {
 /*!
  * @brief Initializes the DSPI master.
  *
- * This function initializes the DSPI master configuration. An example use case is as follows:
+ * This function initializes the DSPI master configuration. This is an example use case.
  *  @code
  *   dspi_master_config_t  masterConfig;
  *   masterConfig.whichCtar                                = kDSPI_Ctar0;
- *   masterConfig.ctarConfig.baudRate                      = 500000000;
+ *   masterConfig.ctarConfig.baudRate                      = 500000000U;
  *   masterConfig.ctarConfig.bitsPerFrame                  = 8;
  *   masterConfig.ctarConfig.cpol                          = kDSPI_ClockPolarityActiveHigh;
  *   masterConfig.ctarConfig.cpha                          = kDSPI_ClockPhaseFirstEdge;
  *   masterConfig.ctarConfig.direction                     = kDSPI_MsbFirst;
- *   masterConfig.ctarConfig.pcsToSckDelayInNanoSec        = 1000000000 / masterConfig.ctarConfig.baudRate ;
- *   masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec    = 1000000000 / masterConfig.ctarConfig.baudRate ;
- *   masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.ctarConfig.baudRate ;
+ *   masterConfig.ctarConfig.pcsToSckDelayInNanoSec        = 1000000000U / masterConfig.ctarConfig.baudRate ;
+ *   masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec    = 1000000000U / masterConfig.ctarConfig.baudRate ;
+ *   masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ;
  *   masterConfig.whichPcs                                 = kDSPI_Pcs0;
  *   masterConfig.pcsActiveHighOrLow                       = kDSPI_PcsActiveLow;
  *   masterConfig.enableContinuousSCK                      = false;
@@ -443,8 +444,8 @@ extern "C" {
  *  @endcode
  *
  * @param base DSPI peripheral address.
- * @param masterConfig Pointer to structure dspi_master_config_t.
- * @param srcClock_Hz Module source input clock in Hertz
+ * @param masterConfig Pointer to the structure dspi_master_config_t.
+ * @param srcClock_Hz Module source input clock in Hertz.
  */
 void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz);
 
@@ -452,8 +453,8 @@ void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, u
  * @brief Sets the dspi_master_config_t structure to default values.
  *
  * The purpose of this API is to get the configuration structure initialized for the DSPI_MasterInit().
- * User may use the initialized structure unchanged in DSPI_MasterInit() or modify the structure
- * before calling DSPI_MasterInit().
+ * Users may use the initialized structure unchanged in the DSPI_MasterInit() or modify the structure
+ * before calling the DSPI_MasterInit().
  * Example:
  * @code
  *  dspi_master_config_t  masterConfig;
@@ -466,7 +467,7 @@ void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig);
 /*!
  * @brief DSPI slave configuration.
  *
- * This function initializes the DSPI slave configuration. An example use case is as follows:
+ * This function initializes the DSPI slave configuration. This is an example use case.
  *  @code
  *   dspi_slave_config_t  slaveConfig;
  *  slaveConfig->whichCtar                  = kDSPI_Ctar0;
@@ -481,22 +482,22 @@ void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig);
  *  @endcode
  *
  * @param base DSPI peripheral address.
- * @param slaveConfig Pointer to structure dspi_master_config_t.
+ * @param slaveConfig Pointer to the structure dspi_master_config_t.
  */
 void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig);
 
 /*!
- * @brief Sets the dspi_slave_config_t structure to default values.
+ * @brief Sets the dspi_slave_config_t structure to a default value.
  *
  * The purpose of this API is to get the configuration structure initialized for the DSPI_SlaveInit().
- * User may use the initialized structure unchanged in DSPI_SlaveInit(), or modify the structure
- * before calling DSPI_SlaveInit().
- * Example:
+ * Users may use the initialized structure unchanged in the DSPI_SlaveInit() or modify the structure
+ * before calling the DSPI_SlaveInit().
+ * This is an example.
  * @code
  *  dspi_slave_config_t  slaveConfig;
  *  DSPI_SlaveGetDefaultConfig(&slaveConfig);
  * @endcode
- * @param slaveConfig pointer to dspi_slave_config_t structure.
+ * @param slaveConfig Pointer to the dspi_slave_config_t structure.
  */
 void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig);
 
@@ -510,7 +511,7 @@ void DSPI_Deinit(SPI_Type *base);
  * @brief Enables the DSPI peripheral and sets the MCR MDIS to 0.
  *
  * @param base DSPI peripheral address.
- * @param enable pass true to enable module, false to disable module.
+ * @param enable Pass true to enable module, false to disable module.
  */
 static inline void DSPI_Enable(SPI_Type *base, bool enable)
 {
@@ -536,7 +537,7 @@ static inline void DSPI_Enable(SPI_Type *base, bool enable)
 /*!
  * @brief Gets the DSPI status flag state.
  * @param base DSPI peripheral address.
- * @return The DSPI status(in SR register).
+ * @return DSPI status (in SR register).
  */
 static inline uint32_t DSPI_GetStatusFlags(SPI_Type *base)
 {
@@ -549,13 +550,13 @@ static inline uint32_t DSPI_GetStatusFlags(SPI_Type *base)
  * This function  clears the desired status bit by using a write-1-to-clear. The user passes in the base and the
  * desired status bit to clear.  The list of status bits is defined in the dspi_status_and_interrupt_request_t. The
  * function uses these bit positions in its algorithm to clear the desired flag state.
- * Example usage:
+ * This is an example.
  * @code
  *  DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag|kDSPI_EndOfQueueFlag);
  * @endcode
  *
  * @param base DSPI peripheral address.
- * @param statusFlags The status flag , used from type dspi_flags.
+ * @param statusFlags The status flag used from the type dspi_flags.
  */
 static inline void DSPI_ClearStatusFlags(SPI_Type *base, uint32_t statusFlags)
 {
@@ -574,15 +575,16 @@ static inline void DSPI_ClearStatusFlags(SPI_Type *base, uint32_t statusFlags)
 /*!
  * @brief Enables the DSPI interrupts.
  *
- * This function configures the various interrupt masks of the DSPI.  The parameters are base and an interrupt mask.
+ * This function configures the various interrupt masks of the DSPI.  The parameters are a base and an interrupt mask.
  * Note, for Tx Fill and Rx FIFO drain requests, enable the interrupt request and disable the DMA request.
+ *       Do not use this API(write to RSER register) while DSPI is in running state.
  *
  * @code
  *  DSPI_EnableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable );
  * @endcode
  *
  * @param base DSPI peripheral address.
- * @param mask The interrupt mask, can use the enum _dspi_interrupt_enable.
+ * @param mask The interrupt mask; use the enum _dspi_interrupt_enable.
  */
 void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask);
 
@@ -594,7 +596,7 @@ void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask);
  * @endcode
  *
  * @param base DSPI peripheral address.
- * @param mask The interrupt mask, can use the enum _dspi_interrupt_enable.
+ * @param mask The interrupt mask; use the enum _dspi_interrupt_enable.
  */
 static inline void DSPI_DisableInterrupts(SPI_Type *base, uint32_t mask)
 {
@@ -613,13 +615,13 @@ static inline void DSPI_DisableInterrupts(SPI_Type *base, uint32_t mask)
 /*!
  * @brief Enables the DSPI DMA request.
  *
- * This function configures the Rx and Tx DMA mask of the DSPI.  The parameters are base and a DMA mask.
+ * This function configures the Rx and Tx DMA mask of the DSPI.  The parameters are a base and a DMA mask.
  * @code
  *  DSPI_EnableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable);
  * @endcode
  *
  * @param base DSPI peripheral address.
- * @param mask The interrupt mask can use the enum dspi_dma_enable.
+ * @param mask The interrupt mask; use the enum dspi_dma_enable.
  */
 static inline void DSPI_EnableDMA(SPI_Type *base, uint32_t mask)
 {
@@ -629,13 +631,13 @@ static inline void DSPI_EnableDMA(SPI_Type *base, uint32_t mask)
 /*!
  * @brief Disables the DSPI DMA request.
  *
- * This function configures the Rx and Tx DMA mask of the DSPI.  The parameters are base and a DMA mask.
+ * This function configures the Rx and Tx DMA mask of the DSPI.  The parameters are a base and a DMA mask.
  * @code
  *  SPI_DisableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable);
  * @endcode
  *
  * @param base DSPI peripheral address.
- * @param mask The interrupt mask can use the enum dspi_dma_enable.
+ * @param mask The interrupt mask; use the enum dspi_dma_enable.
  */
 static inline void DSPI_DisableDMA(SPI_Type *base, uint32_t mask)
 {
@@ -714,7 +716,7 @@ static inline bool DSPI_IsMaster(SPI_Type *base)
 /*!
  * @brief Starts the DSPI transfers and clears HALT bit in MCR.
  *
- * This function sets the module to begin data transfer in either master or slave mode.
+ * This function sets the module to start data transfer in either master or slave mode.
  *
  * @param base DSPI peripheral address.
  */
@@ -723,9 +725,9 @@ static inline void DSPI_StartTransfer(SPI_Type *base)
     base->MCR &= ~SPI_MCR_HALT_MASK;
 }
 /*!
- * @brief Stops (halts) DSPI transfers and sets HALT bit in MCR.
+ * @brief Stops DSPI transfers and sets the HALT bit in MCR.
  *
- * This function stops data transfers in either master or slave mode.
+ * This function stops data transfers in either master or slave modes.
  *
  * @param base DSPI peripheral address.
  */
@@ -735,15 +737,15 @@ static inline void DSPI_StopTransfer(SPI_Type *base)
 }
 
 /*!
- * @brief Enables (or disables) the DSPI FIFOs.
+ * @brief Enables or disables the DSPI FIFOs.
  *
- * This function  allows the caller to disable/enable the Tx and Rx FIFOs (independently).
- * Note that to disable, the caller must pass in a logic 0 (false) for the particular FIFO configuration.  To enable,
- * the caller must pass in a logic 1 (true).
+ * This function  allows the caller to disable/enable the Tx and Rx FIFOs independently.
+ * Note that to disable, pass in a logic 0 (false) for the particular FIFO configuration.  To enable,
+ * pass in a logic 1 (true).
  *
  * @param base DSPI peripheral address.
- * @param enableTxFifo Disables (false) the TX FIFO, else enables (true) the TX FIFO
- * @param enableRxFifo Disables (false) the RX FIFO, else enables (true) the RX FIFO
+ * @param enableTxFifo Disables (false) the TX FIFO; Otherwise, enables (true) the TX FIFO
+ * @param enableRxFifo Disables (false) the RX FIFO; Otherwise, enables (true) the RX FIFO
  */
 static inline void DSPI_SetFifoEnable(SPI_Type *base, bool enableTxFifo, bool enableRxFifo)
 {
@@ -755,8 +757,8 @@ static inline void DSPI_SetFifoEnable(SPI_Type *base, bool enableTxFifo, bool en
  * @brief Flushes the DSPI FIFOs.
  *
  * @param base DSPI peripheral address.
- * @param flushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO
- * @param flushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO
+ * @param flushTxFifo Flushes (true) the Tx FIFO; Otherwise, does not flush (false) the Tx FIFO
+ * @param flushRxFifo Flushes (true) the Rx FIFO; Otherwise, does not flush (false) the Rx FIFO
  */
 static inline void DSPI_FlushFifo(SPI_Type *base, bool flushTxFifo, bool flushRxFifo)
 {
@@ -766,13 +768,13 @@ static inline void DSPI_FlushFifo(SPI_Type *base, bool flushTxFifo, bool flushRx
 
 /*!
  * @brief Configures the DSPI peripheral chip select polarity simultaneously.
- * For example, PCS0 and PCS1 set to active low and other PCS set to active high. Note that the number of
+ * For example, PCS0 and PCS1 are set to active low and other PCS is set to active high. Note that the number of
  * PCSs is specific to the device.
  * @code
  *  DSPI_SetAllPcsPolarity(base, kDSPI_Pcs0ActiveLow | kDSPI_Pcs1ActiveLow);
    @endcode
  * @param base DSPI peripheral address.
- * @param mask The PCS polarity mask ,  can use the enum _dspi_pcs_polarity.
+ * @param mask The PCS polarity mask; use the enum _dspi_pcs_polarity.
  */
 static inline void DSPI_SetAllPcsPolarity(SPI_Type *base, uint32_t mask)
 {
@@ -801,19 +803,19 @@ uint32_t DSPI_MasterSetBaudRate(SPI_Type *base,
  * @brief Manually configures the delay prescaler and scaler for a particular CTAR.
  *
  * This function configures the PCS to SCK delay pre-scalar (PcsSCK) and scalar (CSSCK), after SCK delay pre-scalar
- * (PASC) and scalar (ASC), and the delay after transfer pre-scalar (PDT)and scalar (DT).
+ * (PASC) and scalar (ASC), and the delay after transfer pre-scalar (PDT) and scalar (DT).
  *
- * These delay names are available in type dspi_delay_type_t.
+ * These delay names are available in the type dspi_delay_type_t.
  *
- * The user passes the delay to configure along with the prescaler and scaler value.
- * This allows the user to directly set the prescaler/scaler values if they have pre-calculated them or if they simply
- * wish to manually increment either value.
+ * The user passes the delay to the configuration along with the prescaler and scaler value.
+ * This allows the user to directly set the prescaler/scaler values if pre-calculated or
+ * to manually increment either value.
  *
  * @param base DSPI peripheral address.
  * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t.
  * @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3).
  * @param scaler The scaler delay value (can be any integer between 0 to 15).
- * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t
+ * @param whichDelay The desired delay to configure; must be of type dspi_delay_type_t
  */
 void DSPI_MasterSetDelayScaler(
     SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay);
@@ -821,19 +823,19 @@ void DSPI_MasterSetDelayScaler(
 /*!
  * @brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds.
  *
- * This function calculates the values for:
+ * This function calculates the values for the following.
  * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or
  * After SCK delay pre-scalar (PASC) and scalar (ASC), or
- * Delay after transfer pre-scalar (PDT)and scalar (DT).
+ * Delay after transfer pre-scalar (PDT) and scalar (DT).
  *
- * These delay names are available in type dspi_delay_type_t.
+ * These delay names are available in the type dspi_delay_type_t.
  *
- * The user passes which delay they want to configure along with the desired delay value in nanoseconds.  The function
- * calculates the values needed for the prescaler and scaler and returning the actual calculated delay as an exact
+ * The user passes which delay to configure along with the desired delay value in nanoseconds.  The function
+ * calculates the values needed for the prescaler and scaler. Note that returning the calculated delay as an exact
  * delay match may not be possible. In this case, the closest match is calculated without going below the desired
  * delay value input.
  * It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum
- * supported delay is returned. The higher level peripheral driver alerts the user of an out of range delay
+ * supported delay is returned. The higher-level peripheral driver alerts the user of an out of range delay
  * input.
  *
  * @param base DSPI peripheral address.
@@ -853,11 +855,11 @@ uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base,
  * @brief Writes data into the data buffer for master mode.
  *
  * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
- * provides characteristics of the data such as the optional continuous chip select
+ * provides characteristics of the data, such as the optional continuous chip select
  * operation between transfers, the desired Clock and Transfer Attributes register to use for the
  * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
  * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
- * sending the first frame of a data packet). This is an example:
+ * sending the first frame of a data packet). This is an example.
  * @code
  *  dspi_command_data_config_t commandConfig;
  *  commandConfig.isPcsContinuous = true;
@@ -869,7 +871,7 @@ uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base,
    @endcode
  *
  * @param base DSPI peripheral address.
- * @param command Pointer to command structure.
+ * @param command Pointer to the command structure.
  * @param data The data word to be sent.
  */
 static inline void DSPI_MasterWriteData(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data)
@@ -883,14 +885,14 @@ static inline void DSPI_MasterWriteData(SPI_Type *base, dspi_command_data_config
  * @brief Sets the dspi_command_data_config_t structure to default values.
  *
  * The purpose of this API is to get the configuration structure initialized for use in the DSPI_MasterWrite_xx().
- * User may use the initialized structure unchanged in DSPI_MasterWrite_xx() or modify the structure
- * before calling DSPI_MasterWrite_xx().
- * Example:
+ * Users may use the initialized structure unchanged in the DSPI_MasterWrite_xx() or modify the structure
+ * before calling the DSPI_MasterWrite_xx().
+ * This is an example.
  * @code
  *  dspi_command_data_config_t  command;
  *  DSPI_GetDefaultDataCommandConfig(&command);
  * @endcode
- * @param command pointer to dspi_command_data_config_t structure.
+ * @param command Pointer to the dspi_command_data_config_t structure.
  */
 void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command);
 
@@ -898,11 +900,11 @@ void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command);
  * @brief Writes data into the data buffer master mode and waits till complete to return.
  *
  * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
- * provides characteristics of the data such as the optional continuous chip select
+ * provides characteristics of the data, such as the optional continuous chip select
  * operation between transfers, the desired Clock and Transfer Attributes register to use for the
  * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
  * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
- * sending the first frame of a data packet). This is an example:
+ * sending the first frame of a data packet). This is an example.
  * @code
  *  dspi_command_config_t commandConfig;
  *  commandConfig.isPcsContinuous = true;
@@ -915,10 +917,10 @@ void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command);
  *
  * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be
  * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). Because the SPI is a synchronous protocol,
- * receive data is available when transmit completes.
+ * the received data is available when the transmit completes.
  *
  * @param base DSPI peripheral address.
- * @param command Pointer to command structure.
+ * @param command Pointer to the command structure.
  * @param data The data word to be sent.
  */
 void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data);
@@ -933,10 +935,10 @@ void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *co
  * improve performance in cases where the command structure is constant. For example, the user calls this function
  * before starting a transfer to generate the command word. When they are ready to transmit the data, they OR
  * this formatted command word with the desired data to transmit. This process increases transmit performance when
- * compared to calling send functions such as DSPI_HAL_WriteDataMastermode which format the command word each time a
+ * compared to calling send functions, such as DSPI_HAL_WriteDataMastermode,  which format the command word each time a
  * data word is to be sent.
  *
- * @param command Pointer to command structure.
+ * @param command Pointer to the command structure.
  * @return The command word formatted to the PUSHR data register bit field.
  */
 static inline uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t *command)
@@ -949,24 +951,25 @@ static inline uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t
 
 /*!
  * @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data
- *        buffer, master mode and waits till complete to return.
+ *        buffer master mode and waits till complete to return.
  *
- * In this function, the user must append the 16-bit data to the 16-bit command info then provide the total 32-bit word
+ * In this function, the user must append the 16-bit data to the 16-bit command information and then provide the total
+* 32-bit word
  * as the data to send.
- * The command portion provides characteristics of the data such as the optional continuous chip select operation
-* between
- * transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the desired PCS
+ * The command portion provides characteristics of the data, such as the optional continuous chip select operation
+ * between transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the
+* desired PCS
  * signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the
  * transfer count (normally needed when sending the first frame of a data packet). The user is responsible for
  * appending this command with the data to send. This is an example:
  * @code
  *  dataWord = <16-bit command> | <16-bit data>;
- *  DSPI_HAL_WriteCommandDataMastermodeBlocking(base, dataWord);
+ *  DSPI_MasterWriteCommandDataBlocking(base, dataWord);
  * @endcode
  *
  * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be
  * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0).
- * Because the SPI is a synchronous protocol, the receive data is available when transmit completes.
+ * Because the SPI is a synchronous protocol, the received data is available when the transmit completes.
  *
  *  For a blocking polling transfer, see methods below.
  *  Option 1:
@@ -985,7 +988,7 @@ static inline uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t
 *   DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_2);
 *
  * @param base DSPI peripheral address.
- * @param data The data word (command and data combined) to be sent
+ * @param data The data word (command and data combined) to be sent.
  */
 void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data);
 
@@ -1024,6 +1027,14 @@ static inline uint32_t DSPI_ReadData(SPI_Type *base)
     return (base->POPR);
 }
 
+/*!
+ * @brief Set up the dummy data.
+ *
+ * @param base DSPI peripheral address.
+ * @param dummyData Data to be transferred when tx buffer is NULL.
+ */
+void DSPI_SetDummyData(SPI_Type *base, uint8_t dummyData);
+
 /*!
  *@}
 */
@@ -1037,13 +1048,13 @@ static inline uint32_t DSPI_ReadData(SPI_Type *base)
 /*!
  * @brief Initializes the DSPI master handle.
  *
- * This function initializes the DSPI handle which can be used for other DSPI transactional APIs.  Usually, for a
+ * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs.  Usually, for a
  * specified DSPI instance,  call this API once to get the initialized handle.
  *
  * @param base DSPI peripheral base address.
  * @param handle DSPI handle pointer to dspi_master_handle_t.
- * @param callback dspi callback.
- * @param userData callback function parameter.
+ * @param callback DSPI callback.
+ * @param userData Callback function parameter.
  */
 void DSPI_MasterTransferCreateHandle(SPI_Type *base,
                                      dspi_master_handle_t *handle,
@@ -1053,12 +1064,11 @@ void DSPI_MasterTransferCreateHandle(SPI_Type *base,
 /*!
  * @brief DSPI master transfer data using polling.
  *
- * This function transfers data with polling. This is a blocking function, which does not return until all transfers
- * have been
- * completed.
+ * This function transfers data using polling. This is a blocking function, which does not return until all transfers
+ * have been completed.
  *
  * @param base DSPI peripheral base address.
- * @param transfer pointer to dspi_transfer_t structure.
+ * @param transfer Pointer to the dspi_transfer_t structure.
  * @return status of status_t.
  */
 status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer);
@@ -1067,12 +1077,11 @@ status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer);
  * @brief DSPI master transfer data using interrupts.
  *
  * This function transfers data using interrupts. This is a non-blocking function, which returns right away. When all
- data
- * have been transferred, the callback function is called.
+ * data is transferred, the callback function is called.
 
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
- * @param transfer pointer to dspi_transfer_t structure.
+ * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state.
+ * @param transfer Pointer to the dspi_transfer_t structure.
  * @return status of status_t.
  */
 status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer);
@@ -1083,19 +1092,19 @@ status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *ha
  * This function gets the master transfer count.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
- * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state.
+ * @param count The number of bytes transferred by using the non-blocking transaction.
  * @return status of status_t.
  */
 status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count);
 
 /*!
- * @brief DSPI master aborts transfer using an interrupt.
+ * @brief DSPI master aborts a transfer using an interrupt.
  *
  * This function aborts a transfer using an interrupt.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
+ * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state.
  */
 void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle);
 
@@ -1105,7 +1114,7 @@ void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle);
  * This function processes the DSPI transmit and receive IRQ.
 
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
+ * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state.
  */
 void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle);
 
@@ -1115,10 +1124,10 @@ void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle);
  * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs.  Usually, for a
  * specified DSPI instance, call this API once to get the initialized handle.
  *
- * @param handle DSPI handle pointer to dspi_slave_handle_t.
+ * @param handle DSPI handle pointer to the dspi_slave_handle_t.
  * @param base DSPI peripheral base address.
  * @param callback DSPI callback.
- * @param userData callback function parameter.
+ * @param userData Callback function parameter.
  */
 void DSPI_SlaveTransferCreateHandle(SPI_Type *base,
                                     dspi_slave_handle_t *handle,
@@ -1129,12 +1138,11 @@ void DSPI_SlaveTransferCreateHandle(SPI_Type *base,
  * @brief DSPI slave transfers data using an interrupt.
  *
  * This function transfers data using an interrupt. This is a non-blocking function, which returns right away. When all
- * data
- * have been transferred, the callback function is called.
+ * data is transferred, the callback function is called.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_slave_handle_t structure which stores the transfer state.
- * @param transfer pointer to dspi_transfer_t structure.
+ * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state.
+ * @param transfer Pointer to the dspi_transfer_t structure.
  * @return status of status_t.
  */
 status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer);
@@ -1145,8 +1153,8 @@ status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *hand
  * This function gets the slave transfer count.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
- * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state.
+ * @param count The number of bytes transferred by using the non-blocking transaction.
  * @return status of status_t.
  */
 status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count);
@@ -1154,10 +1162,10 @@ status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle,
 /*!
  * @brief DSPI slave aborts a transfer using an interrupt.
  *
- * This function aborts transfer using an interrupt.
+ * This function aborts a transfer using an interrupt.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_slave_handle_t structure which stores the transfer state.
+ * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state.
  */
 void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle);
 
@@ -1167,7 +1175,7 @@ void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle);
  * This function processes the DSPI transmit and receive IRQ.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_slave_handle_t structure which stores the transfer state.
+ * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state.
  */
 void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle);
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi_edma.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi_edma.c
index 4d9e129ff24..ef0d15174f5 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi_edma.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi_edma.c
@@ -1,32 +1,32 @@
 /*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-*   of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-*   list of conditions and the following disclaimer in the documentation and/or
-*   other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-*   contributors may be used to endorse or promote products derived from this
-*   software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #include "fsl_dspi_edma.h"
 
@@ -57,7 +57,7 @@ typedef struct _dspi_slave_edma_private_handle
 ***********************************************************************************************************************/
 /*!
 * @brief EDMA_DspiMasterCallback after the DSPI master transfer completed by using EDMA.
-* This is not a public API as it is called from other driver functions.
+* This is not a public API.
 */
 static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle,
                                     void *g_dspiEdmaPrivateHandle,
@@ -66,7 +66,7 @@ static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle,
 
 /*!
 * @brief EDMA_DspiSlaveCallback after the DSPI slave transfer completed by using EDMA.
-* This is not a public API as it is called from other driver functions.
+* This is not a public API.
 */
 static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle,
                                    void *g_dspiEdmaPrivateHandle,
@@ -102,6 +102,9 @@ void DSPI_MasterTransferCreateHandleEDMA(SPI_Type *base,
                                          edma_handle_t *edmaIntermediaryToTxRegHandle)
 {
     assert(handle);
+    assert(edmaRxRegToRxDataHandle);
+    assert(edmaTxDataToIntermediaryHandle);
+    assert(edmaIntermediaryToTxRegHandle);
 
     /* Zero the handle. */
     memset(handle, 0, sizeof(*handle));
@@ -121,7 +124,8 @@ void DSPI_MasterTransferCreateHandleEDMA(SPI_Type *base,
 
 status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, dspi_transfer_t *transfer)
 {
-    assert(handle && transfer);
+    assert(handle);
+    assert(transfer);
 
     /* If the transfer count is zero, then return immediately.*/
     if (transfer->dataSize == 0)
@@ -141,9 +145,11 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
         return kStatus_DSPI_Busy;
     }
 
+    handle->state = kDSPI_Busy;
+
     uint32_t instance = DSPI_GetInstance(base);
     uint16_t wordToSend = 0;
-    uint8_t dummyData = DSPI_MASTER_DUMMY_DATA;
+    uint8_t dummyData = DSPI_DUMMY_DATA;
     uint8_t dataAlreadyFed = 0;
     uint8_t dataFedMax = 2;
 
@@ -156,9 +162,7 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
     edma_transfer_config_t transferConfigB;
     edma_transfer_config_t transferConfigC;
 
-    handle->txBuffIfNull = ((uint32_t)DSPI_MASTER_DUMMY_DATA << 8) | DSPI_MASTER_DUMMY_DATA;
-
-    handle->state = kDSPI_Busy;
+    handle->txBuffIfNull = ((uint32_t)DSPI_DUMMY_DATA << 8) | DSPI_DUMMY_DATA;
 
     dspi_command_data_config_t commandStruct;
     DSPI_StopTransfer(base);
@@ -174,6 +178,7 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
     commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterPcsContinuous);
     handle->command = DSPI_MasterGetFormattedCommand(&(commandStruct));
 
+    commandStruct.isEndOfQueue = true;
     commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer);
     handle->lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct));
 
@@ -193,39 +198,70 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
     handle->remainingReceiveByteCount = transfer->dataSize;
     handle->totalByteCount = transfer->dataSize;
 
-    /* this limits the amount of data we can transfer due to the linked channel.
-    * The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
+    /* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer
+    * due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
     */
+    uint32_t limited_size = 0;
+    if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+    {
+        limited_size = 32767u;
+    }
+    else
+    {
+        limited_size = 511u;
+    }
+
     if (handle->bitsPerFrame > 8)
     {
-        if (transfer->dataSize > 1022)
+        if (transfer->dataSize > (limited_size << 1u))
         {
+            handle->state = kDSPI_Idle;
             return kStatus_DSPI_OutOfRange;
         }
     }
     else
     {
-        if (transfer->dataSize > 511)
+        if (transfer->dataSize > limited_size)
         {
+            handle->state = kDSPI_Idle;
             return kStatus_DSPI_OutOfRange;
         }
     }
 
+    /*The data size should be even if the bitsPerFrame is greater than 8 (that is 2 bytes per frame in dspi) */
+    if ((handle->bitsPerFrame > 8) && (transfer->dataSize & 0x1))
+    {
+        handle->state = kDSPI_Idle;
+        return kStatus_InvalidArgument;
+    }
+
     DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
 
     EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiMasterCallback,
                      &s_dspiMasterEdmaPrivateHandle[instance]);
 
-    handle->isThereExtraByte = false;
-    if (handle->bitsPerFrame > 8)
-    {
-        if (handle->remainingSendByteCount % 2 == 1)
-        {
-            handle->remainingSendByteCount++;
-            handle->remainingReceiveByteCount--;
-            handle->isThereExtraByte = true;
-        }
-    }
+    /*
+    (1)For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_B-> channel_C.
+    channel_A minor link to channel_B , channel_B minor link to channel_C.
+
+    Already pushed 1 or 2 data in SPI_PUSHR , then start the DMA tansfer.
+    channel_A:SPI_POPR to rxData,
+    channel_B:next txData to handle->command (low 16 bits),
+    channel_C:handle->command (32 bits) to SPI_PUSHR, and use the scatter/gather to transfer the last data
+    (handle->lastCommand to SPI_PUSHR).
+
+    (2)For DSPI instances with separate RX and TX DMA requests:
+    Rx DMA request -> channel_A
+    Tx DMA request -> channel_C -> channel_B .
+    channel_C major link to channel_B.
+    So need prepare the first data in "intermediary"  before the DMA
+    transfer and then channel_B is used to prepare the next data to "intermediary"
+
+    channel_A:SPI_POPR to rxData,
+    channel_C: handle->command (32 bits) to SPI_PUSHR,
+    channel_B: next txData to handle->command (low 16 bits), and use the scatter/gather to prepare the last data
+    (handle->lastCommand to handle->Command).
+    */
 
     /*If dspi has separate dma request , prepare the first data in "intermediary" .
     else (dspi has shared dma request) , send first 2 data if there is fifo or send first 1 data if there is no fifo*/
@@ -243,22 +279,16 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
             {
                 if (handle->txData)
                 {
-                    if (handle->isThereExtraByte)
-                    {
-                        wordToSend = *(handle->txData) | ((uint32_t)dummyData << 8);
-                    }
-                    else
-                    {
-                        wordToSend = *(handle->txData);
-                        ++handle->txData; /* increment to next data byte */
-                        wordToSend |= (unsigned)(*(handle->txData)) << 8U;
-                    }
+                    wordToSend = *(handle->txData);
+                    ++handle->txData; /* increment to next data byte */
+                    wordToSend |= (unsigned)(*(handle->txData)) << 8U;
                 }
                 else
                 {
                     wordToSend = ((uint32_t)dummyData << 8) | dummyData;
                 }
                 handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend;
+                handle->command = handle->lastCommand;
             }
             else /* For all words except the last word , frame > 8bits */
             {
@@ -291,6 +321,7 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
             if (handle->remainingSendByteCount == 1)
             {
                 handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend;
+                handle->command = handle->lastCommand;
             }
             else
             {
@@ -315,21 +346,13 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
                 {
                     if (handle->txData)
                     {
-                        if (handle->isThereExtraByte)
-                        {
-                            wordToSend = *(handle->txData) | ((uint32_t)dummyData << 8);
-                        }
-                        else
-                        {
-                            wordToSend = *(handle->txData);
-                            ++handle->txData;
-                            wordToSend |= (unsigned)(*(handle->txData)) << 8U;
-                        }
+                        wordToSend = *(handle->txData);
+                        ++handle->txData;
+                        wordToSend |= (unsigned)(*(handle->txData)) << 8U;
                     }
                     else
                     {
                         wordToSend = ((uint32_t)dummyData << 8) | dummyData;
-                        ;
                     }
                     handle->remainingSendByteCount = 0;
                     base->PUSHR = (handle->lastCommand & 0xffff0000U) | wordToSend;
@@ -347,7 +370,6 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
                     else
                     {
                         wordToSend = ((uint32_t)dummyData << 8) | dummyData;
-                        ;
                     }
                     handle->remainingSendByteCount -= 2;
                     base->PUSHR = (handle->command & 0xffff0000U) | wordToSend;
@@ -404,7 +426,7 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
         }
     }
 
-    /***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer*/
+    /***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer(rxData)*/
     EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel);
 
     transferConfigA.srcAddr = (uint32_t)rxAddr;
@@ -435,6 +457,10 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
         transferConfigA.minorLoopBytes = 2;
         transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2;
     }
+
+    /* Store the initially configured eDMA minor byte transfer count into the DSPI handle */
+    handle->nbytes = transferConfigA.minorLoopBytes;
+
     EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
                            &transferConfigA, NULL);
     EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
@@ -443,9 +469,82 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
     /***channel_B *** used for carry the data from User_Send_Buffer to "intermediary" because the SPIx_PUSHR should
     write the 32bits at once time . Then use channel_C to carry the "intermediary" to SPIx_PUSHR. Note that the
     SPIx_PUSHR upper 16 bits are the "command" and the low 16bits are data */
+
     EDMA_ResetChannel(handle->edmaTxDataToIntermediaryHandle->base, handle->edmaTxDataToIntermediaryHandle->channel);
 
-    if (handle->remainingSendByteCount > 0)
+    /*Calculate the last data : handle->lastCommand*/
+    if (((handle->remainingSendByteCount > 0) && (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) ||
+        ((((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) ||
+          ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8))) &&
+         (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))))
+    {
+        if (handle->txData)
+        {
+            uint32_t bufferIndex = 0;
+
+            if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+            {
+                if (handle->bitsPerFrame <= 8)
+                {
+                    bufferIndex = handle->remainingSendByteCount - 1;
+                }
+                else
+                {
+                    bufferIndex = handle->remainingSendByteCount - 2;
+                }
+            }
+            else
+            {
+                bufferIndex = handle->remainingSendByteCount;
+            }
+
+            if (handle->bitsPerFrame <= 8)
+            {
+                handle->lastCommand = (handle->lastCommand & 0xffff0000U) | handle->txData[bufferIndex - 1];
+            }
+            else
+            {
+                handle->lastCommand = (handle->lastCommand & 0xffff0000U) |
+                                      ((uint32_t)handle->txData[bufferIndex - 1] << 8) |
+                                      handle->txData[bufferIndex - 2];
+            }
+        }
+        else
+        {
+            if (handle->bitsPerFrame <= 8)
+            {
+                wordToSend = dummyData;
+            }
+            else
+            {
+                wordToSend = ((uint32_t)dummyData << 8) | dummyData;
+            }
+            handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend;
+        }
+    }
+
+    /*For DSPI instances with separate RX and TX DMA requests: use the scatter/gather to prepare the last data
+     * (handle->lastCommand) to handle->Command*/
+    if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+    {
+        transferConfigB.srcAddr = (uint32_t) & (handle->lastCommand);
+        transferConfigB.destAddr = (uint32_t) & (handle->command);
+        transferConfigB.srcTransferSize = kEDMA_TransferSize4Bytes;
+        transferConfigB.destTransferSize = kEDMA_TransferSize4Bytes;
+        transferConfigB.srcOffset = 0;
+        transferConfigB.destOffset = 0;
+        transferConfigB.minorLoopBytes = 4;
+        transferConfigB.majorLoopCounts = 1;
+
+        EDMA_TcdReset(softwareTCD);
+        EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigB, NULL);
+    }
+
+    /*User_Send_Buffer(txData) to intermediary(handle->command)*/
+    if (((((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame <= 8)) ||
+          ((handle->remainingSendByteCount > 4) && (handle->bitsPerFrame > 8))) &&
+         (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) ||
+        (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)))
     {
         if (handle->txData)
         {
@@ -470,8 +569,7 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
 
             if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
             {
-                /*already prepared the first data in "intermediary" , so minus 1 */
-                transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 1;
+                transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 2;
             }
             else
             {
@@ -486,8 +584,7 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
             transferConfigB.minorLoopBytes = 2;
             if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
             {
-                /*already prepared the first data in "intermediary" , so minus 1 */
-                transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 - 1;
+                transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 - 2;
             }
             else
             {
@@ -497,74 +594,33 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
             }
         }
 
+        if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+        {
+            EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
+                                   handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, softwareTCD);
+            EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base,
+                                       handle->edmaIntermediaryToTxRegHandle->channel, false);
+        }
+        else
+        {
+            EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
+                                   handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, NULL);
+        }
+    }
+    else
+    {
         EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
                                handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, NULL);
     }
 
     /***channel_C ***carry the "intermediary" to SPIx_PUSHR. used the edma Scatter Gather function on channel_C to
     handle the last data */
-    EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel);
-
-    if (((handle->remainingSendByteCount > 0) && (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) ||
-        ((((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) ||
-          ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8))) &&
-         (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))))
-    {
-        if (handle->txData)
-        {
-            uint32_t bufferIndex = 0;
 
-            if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
-            {
-                if (handle->bitsPerFrame <= 8)
-                {
-                    bufferIndex = handle->remainingSendByteCount - 1;
-                }
-                else
-                {
-                    bufferIndex = handle->remainingSendByteCount - 2;
-                }
-            }
-            else
-            {
-                bufferIndex = handle->remainingSendByteCount;
-            }
-
-            if (handle->bitsPerFrame <= 8)
-            {
-                handle->lastCommand = (handle->lastCommand & 0xffff0000U) | handle->txData[bufferIndex - 1];
-            }
-            else
-            {
-                if (handle->isThereExtraByte)
-                {
-                    handle->lastCommand = (handle->lastCommand & 0xffff0000U) | handle->txData[bufferIndex - 2] |
-                                          ((uint32_t)dummyData << 8);
-                }
-                else
-                {
-                    handle->lastCommand = (handle->lastCommand & 0xffff0000U) |
-                                          ((uint32_t)handle->txData[bufferIndex - 1] << 8) |
-                                          handle->txData[bufferIndex - 2];
-                }
-            }
-        }
-        else
-        {
-            if (handle->bitsPerFrame <= 8)
-            {
-                wordToSend = dummyData;
-            }
-            else
-            {
-                wordToSend = ((uint32_t)dummyData << 8) | dummyData;
-            }
-            handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend;
-        }
-    }
+    EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel);
 
-    if ((1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) ||
-        ((1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) && (handle->remainingSendByteCount > 0)))
+    /*For DSPI instances with shared RX/TX DMA requests: use the scatter/gather to prepare the last data
+     * (handle->lastCommand) to SPI_PUSHR*/
+    if (((1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) && (handle->remainingSendByteCount > 0)))
     {
         transferConfigC.srcAddr = (uint32_t) & (handle->lastCommand);
         transferConfigC.destAddr = (uint32_t)txAddr;
@@ -580,7 +636,8 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
     }
 
     if (((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) ||
-        ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8)))
+        ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8)) ||
+        (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)))
     {
         transferConfigC.srcAddr = (uint32_t)(&(handle->command));
         transferConfigC.destAddr = (uint32_t)txAddr;
@@ -590,18 +647,28 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
         transferConfigC.srcOffset = 0;
         transferConfigC.destOffset = 0;
         transferConfigC.minorLoopBytes = 4;
-
-        if (handle->bitsPerFrame <= 8)
+        if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
         {
-            transferConfigC.majorLoopCounts = handle->remainingSendByteCount - 1;
+            if (handle->bitsPerFrame <= 8)
+            {
+                transferConfigC.majorLoopCounts = handle->remainingSendByteCount - 1;
+            }
+            else
+            {
+                transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2 - 1;
+            }
+
+            EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
+                                   handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, softwareTCD);
         }
         else
         {
-            transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2 - 1;
+            transferConfigC.majorLoopCounts = 1;
+
+            EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
+                                   handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, NULL);
         }
 
-        EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
-                               handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, softwareTCD);
         EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base,
                                    handle->edmaIntermediaryToTxRegHandle->channel, false);
     }
@@ -673,20 +740,15 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
                                         &preemption_config_t);
     }
 
-    /*Set the channel link.
-    For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_B-> channel_C.
-    For DSPI instances with separate RX and TX DMA requests:
-    Rx DMA request -> channel_A
-    Tx DMA request -> channel_C -> channel_B . (so need prepare the first data in "intermediary"  before the DMA
-    transfer and then channel_B is used to prepare the next data to "intermediary" ) */
+    /*Set the channel link.*/
     if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
     {
         /*if there is Tx DMA request , carry the 32bits data (handle->command) to PUSHR first , then link to channelB
-        to prepare the next 32bits data (User_send_buffer to handle->command) */
+        to prepare the next 32bits data (txData to handle->command) */
         if (handle->remainingSendByteCount > 1)
         {
             EDMA_SetChannelLink(handle->edmaIntermediaryToTxRegHandle->base,
-                                handle->edmaIntermediaryToTxRegHandle->channel, kEDMA_MinorLink,
+                                handle->edmaIntermediaryToTxRegHandle->channel, kEDMA_MajorLink,
                                 handle->edmaTxDataToIntermediaryHandle->channel);
         }
 
@@ -699,12 +761,6 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
             EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
                                 kEDMA_MinorLink, handle->edmaTxDataToIntermediaryHandle->channel);
 
-            if (handle->isThereExtraByte)
-            {
-                EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
-                                    kEDMA_MajorLink, handle->edmaTxDataToIntermediaryHandle->channel);
-            }
-
             EDMA_SetChannelLink(handle->edmaTxDataToIntermediaryHandle->base,
                                 handle->edmaTxDataToIntermediaryHandle->channel, kEDMA_MinorLink,
                                 handle->edmaIntermediaryToTxRegHandle->channel);
@@ -723,37 +779,28 @@ static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle,
                                     bool transferDone,
                                     uint32_t tcds)
 {
+    assert(edmaHandle);
+    assert(g_dspiEdmaPrivateHandle);
+
     dspi_master_edma_private_handle_t *dspiEdmaPrivateHandle;
 
     dspiEdmaPrivateHandle = (dspi_master_edma_private_handle_t *)g_dspiEdmaPrivateHandle;
 
-    uint32_t dataReceived;
-
     DSPI_DisableDMA((dspiEdmaPrivateHandle->base), kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
 
-    if (dspiEdmaPrivateHandle->handle->isThereExtraByte)
-    {
-        while (!((dspiEdmaPrivateHandle->base)->SR & SPI_SR_RFDF_MASK))
-        {
-        }
-        dataReceived = (dspiEdmaPrivateHandle->base)->POPR;
-        if (dspiEdmaPrivateHandle->handle->rxData)
-        {
-            (dspiEdmaPrivateHandle->handle->rxData[dspiEdmaPrivateHandle->handle->totalByteCount - 1]) = dataReceived;
-        }
-    }
+    dspiEdmaPrivateHandle->handle->state = kDSPI_Idle;
 
     if (dspiEdmaPrivateHandle->handle->callback)
     {
         dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle,
                                                 kStatus_Success, dspiEdmaPrivateHandle->handle->userData);
     }
-
-    dspiEdmaPrivateHandle->handle->state = kDSPI_Idle;
 }
 
 void DSPI_MasterTransferAbortEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle)
 {
+    assert(handle);
+
     DSPI_StopTransfer(base);
 
     DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
@@ -783,7 +830,8 @@ status_t DSPI_MasterTransferGetCountEDMA(SPI_Type *base, dspi_master_edma_handle
 
     size_t bytes;
 
-    bytes = EDMA_GetRemainingBytes(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel);
+    bytes = (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base,
+                                                                       handle->edmaRxRegToRxDataHandle->channel);
 
     *count = handle->totalByteCount - bytes;
 
@@ -798,6 +846,8 @@ void DSPI_SlaveTransferCreateHandleEDMA(SPI_Type *base,
                                         edma_handle_t *edmaTxDataToTxRegHandle)
 {
     assert(handle);
+    assert(edmaRxRegToRxDataHandle);
+    assert(edmaTxDataToTxRegHandle);
 
     /* Zero the handle. */
     memset(handle, 0, sizeof(*handle));
@@ -816,7 +866,8 @@ void DSPI_SlaveTransferCreateHandleEDMA(SPI_Type *base,
 
 status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, dspi_transfer_t *transfer)
 {
-    assert(handle && transfer);
+    assert(handle);
+    assert(transfer);
 
     /* If send/receive length is zero */
     if (transfer->dataSize == 0)
@@ -836,7 +887,7 @@ status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle
         return kStatus_DSPI_Busy;
     }
 
-    edma_tcd_t *softwareTCD = (edma_tcd_t *)((uint32_t)(&handle->dspiSoftwareTCD[1]) & (~0x1FU));
+    handle->state = kDSPI_Busy;
 
     uint32_t instance = DSPI_GetInstance(base);
     uint8_t whichCtar = (transfer->configFlags & DSPI_SLAVE_CTAR_MASK) >> DSPI_SLAVE_CTAR_SHIFT;
@@ -846,54 +897,51 @@ status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle
     /* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer
     * due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
     */
-    if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+    uint32_t limited_size = 0;
+    if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
     {
-        if (handle->bitsPerFrame > 8)
+        limited_size = 32767u;
+    }
+    else
+    {
+        limited_size = 511u;
+    }
+
+    if (handle->bitsPerFrame > 8)
+    {
+        if (transfer->dataSize > (limited_size << 1u))
         {
-            if (transfer->dataSize > 1022)
-            {
-                return kStatus_DSPI_OutOfRange;
-            }
+            handle->state = kDSPI_Idle;
+            return kStatus_DSPI_OutOfRange;
         }
-        else
+    }
+    else
+    {
+        if (transfer->dataSize > limited_size)
         {
-            if (transfer->dataSize > 511)
-            {
-                return kStatus_DSPI_OutOfRange;
-            }
+            handle->state = kDSPI_Idle;
+            return kStatus_DSPI_OutOfRange;
         }
     }
 
-    if ((handle->bitsPerFrame > 8) && (transfer->dataSize < 2))
+    /*The data size should be even if the bitsPerFrame is greater than 8 (that is 2 bytes per frame in dspi) */
+    if ((handle->bitsPerFrame > 8) && (transfer->dataSize & 0x1))
     {
+        handle->state = kDSPI_Idle;
         return kStatus_InvalidArgument;
     }
 
     EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiSlaveCallback, &s_dspiSlaveEdmaPrivateHandle[instance]);
 
-    handle->state = kDSPI_Busy;
-
     /* Store transfer information */
     handle->txData = transfer->txData;
     handle->rxData = transfer->rxData;
     handle->remainingSendByteCount = transfer->dataSize;
     handle->remainingReceiveByteCount = transfer->dataSize;
     handle->totalByteCount = transfer->dataSize;
-    handle->errorCount = 0;
-
-    handle->isThereExtraByte = false;
-    if (handle->bitsPerFrame > 8)
-    {
-        if (handle->remainingSendByteCount % 2 == 1)
-        {
-            handle->remainingSendByteCount++;
-            handle->remainingReceiveByteCount--;
-            handle->isThereExtraByte = true;
-        }
-    }
 
     uint16_t wordToSend = 0;
-    uint8_t dummyData = DSPI_SLAVE_DUMMY_DATA;
+    uint8_t dummyData = DSPI_DUMMY_DATA;
     uint8_t dataAlreadyFed = 0;
     uint8_t dataFedMax = 2;
 
@@ -929,16 +977,9 @@ status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle
                 {
                     wordToSend = *(handle->txData);
                     ++handle->txData; /* Increment to next data byte */
-                    if ((handle->remainingSendByteCount == 2) && (handle->isThereExtraByte))
-                    {
-                        wordToSend |= (unsigned)(dummyData) << 8U;
-                        ++handle->txData; /* Increment to next data byte */
-                    }
-                    else
-                    {
-                        wordToSend |= (unsigned)(*(handle->txData)) << 8U;
-                        ++handle->txData; /* Increment to next data byte */
-                    }
+
+                    wordToSend |= (unsigned)(*(handle->txData)) << 8U;
+                    ++handle->txData; /* Increment to next data byte */
                 }
                 else
                 {
@@ -1025,6 +1066,10 @@ status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle
             transferConfigA.minorLoopBytes = 2;
             transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2;
         }
+
+        /* Store the initially configured eDMA minor byte transfer count into the DSPI handle */
+        handle->nbytes = transferConfigA.minorLoopBytes;
+
         EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
                                &transferConfigA, NULL);
         EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
@@ -1036,98 +1081,47 @@ status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle
         /***channel_C *** used for carry the data from User_Send_Buffer to Tx_Data_Register(PUSHR_SLAVE)*/
         EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel);
 
-        /*If there is extra byte , it would use the */
-        if (handle->isThereExtraByte)
-        {
-            if (handle->txData)
-            {
-                handle->txLastData =
-                    handle->txData[handle->remainingSendByteCount - 2] | ((uint32_t)DSPI_SLAVE_DUMMY_DATA << 8);
-            }
-            else
-            {
-                handle->txLastData = DSPI_SLAVE_DUMMY_DATA | ((uint32_t)DSPI_SLAVE_DUMMY_DATA << 8);
-            }
-            transferConfigC.srcAddr = (uint32_t)(&(handle->txLastData));
-            transferConfigC.destAddr = (uint32_t)txAddr;
-            transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes;
-            transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes;
-            transferConfigC.srcOffset = 0;
-            transferConfigC.destOffset = 0;
-            transferConfigC.minorLoopBytes = 4;
-            transferConfigC.majorLoopCounts = 1;
-
-            EDMA_TcdReset(softwareTCD);
-            EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigC, NULL);
-        }
+        transferConfigC.destAddr = (uint32_t)txAddr;
+        transferConfigC.destOffset = 0;
 
-        /*Set another  transferConfigC*/
-        if ((handle->isThereExtraByte) && (handle->remainingSendByteCount == 2))
+        if (handle->txData)
         {
-            EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
-                                   &transferConfigC, NULL);
+            transferConfigC.srcAddr = (uint32_t)(&(handle->txData[0]));
+            transferConfigC.srcOffset = 1;
         }
         else
         {
-            transferConfigC.destAddr = (uint32_t)txAddr;
-            transferConfigC.destOffset = 0;
-
-            if (handle->txData)
-            {
-                transferConfigC.srcAddr = (uint32_t)(&(handle->txData[0]));
-                transferConfigC.srcOffset = 1;
-            }
-            else
-            {
-                transferConfigC.srcAddr = (uint32_t)(&handle->txBuffIfNull);
-                transferConfigC.srcOffset = 0;
-                if (handle->bitsPerFrame <= 8)
-                {
-                    handle->txBuffIfNull = DSPI_SLAVE_DUMMY_DATA;
-                }
-                else
-                {
-                    handle->txBuffIfNull = (DSPI_SLAVE_DUMMY_DATA << 8) | DSPI_SLAVE_DUMMY_DATA;
-                }
-            }
-
-            transferConfigC.srcTransferSize = kEDMA_TransferSize1Bytes;
-
+            transferConfigC.srcAddr = (uint32_t)(&handle->txBuffIfNull);
+            transferConfigC.srcOffset = 0;
             if (handle->bitsPerFrame <= 8)
             {
-                transferConfigC.destTransferSize = kEDMA_TransferSize1Bytes;
-                transferConfigC.minorLoopBytes = 1;
-                transferConfigC.majorLoopCounts = handle->remainingSendByteCount;
+                handle->txBuffIfNull = DSPI_DUMMY_DATA;
             }
             else
             {
-                transferConfigC.destTransferSize = kEDMA_TransferSize2Bytes;
-                transferConfigC.minorLoopBytes = 2;
-                if (handle->isThereExtraByte)
-                {
-                    transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2 - 1;
-                }
-                else
-                {
-                    transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2;
-                }
+                handle->txBuffIfNull = (DSPI_DUMMY_DATA << 8) | DSPI_DUMMY_DATA;
             }
+        }
 
-            if (handle->isThereExtraByte)
-            {
-                EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
-                                       &transferConfigC, softwareTCD);
-                EDMA_EnableAutoStopRequest(handle->edmaTxDataToTxRegHandle->base,
-                                           handle->edmaTxDataToTxRegHandle->channel, false);
-            }
-            else
-            {
-                EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
-                                       &transferConfigC, NULL);
-            }
+        transferConfigC.srcTransferSize = kEDMA_TransferSize1Bytes;
 
-            EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle);
+        if (handle->bitsPerFrame <= 8)
+        {
+            transferConfigC.destTransferSize = kEDMA_TransferSize1Bytes;
+            transferConfigC.minorLoopBytes = 1;
+            transferConfigC.majorLoopCounts = handle->remainingSendByteCount;
         }
+        else
+        {
+            transferConfigC.destTransferSize = kEDMA_TransferSize2Bytes;
+            transferConfigC.minorLoopBytes = 2;
+            transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2;
+        }
+
+        EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
+                               &transferConfigC, NULL);
+
+        EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle);
     }
 
     EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle);
@@ -1195,37 +1189,28 @@ static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle,
                                    bool transferDone,
                                    uint32_t tcds)
 {
+    assert(edmaHandle);
+    assert(g_dspiEdmaPrivateHandle);
+
     dspi_slave_edma_private_handle_t *dspiEdmaPrivateHandle;
 
     dspiEdmaPrivateHandle = (dspi_slave_edma_private_handle_t *)g_dspiEdmaPrivateHandle;
 
-    uint32_t dataReceived;
-
     DSPI_DisableDMA((dspiEdmaPrivateHandle->base), kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
 
-    if (dspiEdmaPrivateHandle->handle->isThereExtraByte)
-    {
-        while (!((dspiEdmaPrivateHandle->base)->SR & SPI_SR_RFDF_MASK))
-        {
-        }
-        dataReceived = (dspiEdmaPrivateHandle->base)->POPR;
-        if (dspiEdmaPrivateHandle->handle->rxData)
-        {
-            (dspiEdmaPrivateHandle->handle->rxData[dspiEdmaPrivateHandle->handle->totalByteCount - 1]) = dataReceived;
-        }
-    }
+    dspiEdmaPrivateHandle->handle->state = kDSPI_Idle;
 
     if (dspiEdmaPrivateHandle->handle->callback)
     {
         dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle,
                                                 kStatus_Success, dspiEdmaPrivateHandle->handle->userData);
     }
-
-    dspiEdmaPrivateHandle->handle->state = kDSPI_Idle;
 }
 
 void DSPI_SlaveTransferAbortEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle)
 {
+    assert(handle);
+
     DSPI_StopTransfer(base);
 
     DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
@@ -1254,7 +1239,8 @@ status_t DSPI_SlaveTransferGetCountEDMA(SPI_Type *base, dspi_slave_edma_handle_t
 
     size_t bytes;
 
-    bytes = EDMA_GetRemainingBytes(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel);
+    bytes = (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base,
+                                                                       handle->edmaRxRegToRxDataHandle->channel);
 
     *count = handle->totalByteCount - bytes;
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi_edma.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi_edma.h
index 326b7ee442a..23e29ce2983 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi_edma.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_dspi_edma.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,8 +37,6 @@
  * @{
  */
 
-/*! @file */
-
 /***********************************************************************************************************************
  * Definitions
  **********************************************************************************************************************/
@@ -57,9 +55,9 @@ typedef struct _dspi_slave_edma_handle dspi_slave_edma_handle_t;
  * @brief Completion callback function pointer type.
  *
  * @param base DSPI peripheral base address.
- * @param handle Pointer to the handle for the DSPI master.
+ * @param handle A pointer to the handle for the DSPI master.
  * @param status Success or error code describing whether the transfer completed.
- * @param userData Arbitrary pointer-dataSized value passed from the application.
+ * @param userData An arbitrary pointer-dataSized value passed from the application.
  */
 typedef void (*dspi_master_edma_transfer_callback_t)(SPI_Type *base,
                                                      dspi_master_edma_handle_t *handle,
@@ -69,38 +67,39 @@ typedef void (*dspi_master_edma_transfer_callback_t)(SPI_Type *base,
  * @brief Completion callback function pointer type.
  *
  * @param base DSPI peripheral base address.
- * @param handle Pointer to the handle for the DSPI slave.
+ * @param handle A pointer to the handle for the DSPI slave.
  * @param status Success or error code describing whether the transfer completed.
- * @param userData Arbitrary pointer-dataSized value passed from the application.
+ * @param userData An arbitrary pointer-dataSized value passed from the application.
  */
 typedef void (*dspi_slave_edma_transfer_callback_t)(SPI_Type *base,
                                                     dspi_slave_edma_handle_t *handle,
                                                     status_t status,
                                                     void *userData);
 
-/*! @brief DSPI master eDMA transfer handle structure used for transactional API. */
+/*! @brief DSPI master eDMA transfer handle structure used for the transactional API. */
 struct _dspi_master_edma_handle
 {
-    uint32_t bitsPerFrame;         /*!< Desired number of bits per frame. */
-    volatile uint32_t command;     /*!< Desired data command. */
-    volatile uint32_t lastCommand; /*!< Desired last data command. */
+    uint32_t bitsPerFrame;         /*!< The desired number of bits per frame. */
+    volatile uint32_t command;     /*!< The desired data command. */
+    volatile uint32_t lastCommand; /*!< The desired last data command. */
 
     uint8_t fifoSize; /*!< FIFO dataSize. */
 
-    volatile bool isPcsActiveAfterTransfer; /*!< Is PCS signal keep active after the last frame transfer.*/
-    volatile bool isThereExtraByte;         /*!< Is there extra byte.*/
+    volatile bool
+        isPcsActiveAfterTransfer; /*!< Indicates whether the PCS signal keeps active after the last frame transfer.*/
+
+    uint8_t nbytes;         /*!< eDMA minor byte transfer count initially configured. */
+    volatile uint8_t state; /*!< DSPI transfer state , _dspi_transfer_state.*/
 
     uint8_t *volatile txData;                  /*!< Send buffer. */
     uint8_t *volatile rxData;                  /*!< Receive buffer. */
-    volatile size_t remainingSendByteCount;    /*!< Number of bytes remaining to send.*/
-    volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/
-    size_t totalByteCount;                     /*!< Number of transfer bytes*/
+    volatile size_t remainingSendByteCount;    /*!< A number of bytes remaining to send.*/
+    volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/
+    size_t totalByteCount;                     /*!< A number of transfer bytes*/
 
     uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/
     uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/
 
-    volatile uint8_t state; /*!< DSPI transfer state , _dspi_transfer_state.*/
-
     dspi_master_edma_transfer_callback_t callback; /*!< Completion callback. */
     void *userData;                                /*!< Callback user data. */
 
@@ -111,33 +110,30 @@ struct _dspi_master_edma_handle
     edma_tcd_t dspiSoftwareTCD[2]; /*!<SoftwareTCD , internal used*/
 };
 
-/*! @brief DSPI slave eDMA transfer handle structure used for transactional API.*/
+/*! @brief DSPI slave eDMA transfer handle structure used for the transactional API.*/
 struct _dspi_slave_edma_handle
 {
-    uint32_t bitsPerFrame;          /*!< Desired number of bits per frame. */
-    volatile bool isThereExtraByte; /*!< Is there extra byte.*/
+    uint32_t bitsPerFrame; /*!< The desired number of bits per frame. */
 
     uint8_t *volatile txData;                  /*!< Send buffer. */
     uint8_t *volatile rxData;                  /*!< Receive buffer. */
-    volatile size_t remainingSendByteCount;    /*!< Number of bytes remaining to send.*/
-    volatile size_t remainingReceiveByteCount; /*!< Number of bytes remaining to receive.*/
-    size_t totalByteCount;                     /*!< Number of transfer bytes*/
+    volatile size_t remainingSendByteCount;    /*!< A number of bytes remaining to send.*/
+    volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/
+    size_t totalByteCount;                     /*!< A number of transfer bytes*/
 
     uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/
     uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/
     uint32_t txLastData;   /*!< Used if there is an extra byte when 16bits per frame for DMA purpose.*/
 
-    volatile uint8_t state; /*!< DSPI transfer state.*/
+    uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */
 
-    uint32_t errorCount; /*!< Error count for slave transfer.*/
+    volatile uint8_t state; /*!< DSPI transfer state.*/
 
     dspi_slave_edma_transfer_callback_t callback; /*!< Completion callback. */
     void *userData;                               /*!< Callback user data. */
 
     edma_handle_t *edmaRxRegToRxDataHandle; /*!<edma_handle_t handle point used for RxReg to RxData buff*/
     edma_handle_t *edmaTxDataToTxRegHandle; /*!<edma_handle_t handle point used for TxData to TxReg*/
-
-    edma_tcd_t dspiSoftwareTCD[2]; /*!<SoftwareTCD , internal used*/
 };
 
 /***********************************************************************************************************************
@@ -153,17 +149,18 @@ extern "C" {
  * @brief Initializes the DSPI master eDMA handle.
  *
  * This function initializes the DSPI eDMA handle which can be used for other DSPI transactional APIs.  Usually, for a
- * specified DSPI instance, user need only call this API once to get the initialized handle.
+ * specified DSPI instance, call this API once to get the initialized handle.
  *
- * Note that DSPI eDMA has separated (RX and TX as two sources) or shared (RX  and TX are the same source) DMA request source.
- * (1)For the separated DMA request source, enable and set the RX DMAMUX source for edmaRxRegToRxDataHandle and
+ * Note that DSPI eDMA has separated (RX and TX as two sources) or shared (RX  and TX are the same source) DMA request
+ * source.
+ * (1) For the separated DMA request source, enable and set the RX DMAMUX source for edmaRxRegToRxDataHandle and
  * TX DMAMUX source for edmaIntermediaryToTxRegHandle.
- * (2)For the shared DMA request source, enable and set the RX/RX DMAMUX source for the edmaRxRegToRxDataHandle.
+ * (2) For the shared DMA request source, enable and set the RX/RX DMAMUX source for the edmaRxRegToRxDataHandle.
  *
  * @param base DSPI peripheral base address.
  * @param handle DSPI handle pointer to dspi_master_edma_handle_t.
  * @param callback DSPI callback.
- * @param userData callback function parameter.
+ * @param userData A callback function parameter.
  * @param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t.
  * @param edmaTxDataToIntermediaryHandle edmaTxDataToIntermediaryHandle pointer to edma_handle_t.
  * @param edmaIntermediaryToTxRegHandle edmaIntermediaryToTxRegHandle pointer to edma_handle_t.
@@ -179,34 +176,34 @@ void DSPI_MasterTransferCreateHandleEDMA(SPI_Type *base,
 /*!
  * @brief DSPI master transfer data using eDMA.
  *
- * This function transfer data using eDMA. This is non-blocking function, which returns right away. When all data
- * have been transfer, the callback function is called.
+ * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data
+ * is transferred, the callback function is called.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_master_edma_handle_t structure which stores the transfer state.
- * @param transfer pointer to dspi_transfer_t structure.
+ * @param handle A pointer to the dspi_master_edma_handle_t structure which stores the transfer state.
+ * @param transfer A pointer to the dspi_transfer_t structure.
  * @return status of status_t.
  */
 status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, dspi_transfer_t *transfer);
 
 /*!
- * @brief DSPI master aborts a transfer which using eDMA.
+ * @brief DSPI master aborts a transfer which is using eDMA.
  *
- * This function aborts a transfer which using eDMA.
+ * This function aborts a transfer which is using eDMA.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_master_edma_handle_t structure which stores the transfer state.
+ * @param handle A pointer to the dspi_master_edma_handle_t structure which stores the transfer state.
  */
 void DSPI_MasterTransferAbortEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle);
 
 /*!
  * @brief Gets the master eDMA transfer count.
  *
- * This function get the master eDMA transfer count.
+ * This function gets the master eDMA transfer count.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_master_edma_handle_t structure which stores the transfer state.
- * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @param handle A pointer to the dspi_master_edma_handle_t structure which stores the transfer state.
+ * @param count A number of bytes transferred by the non-blocking transaction.
  * @return status of status_t.
  */
 status_t DSPI_MasterTransferGetCountEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, size_t *count);
@@ -217,7 +214,8 @@ status_t DSPI_MasterTransferGetCountEDMA(SPI_Type *base, dspi_master_edma_handle
  * This function initializes the DSPI eDMA handle which can be used for other DSPI transactional APIs.  Usually, for a
  * specified DSPI instance, call this API once to get the initialized handle.
  *
- * Note that DSPI eDMA has separated (RN and TX in 2 sources) or shared (RX  and TX are the same source) DMA request source.
+ * Note that DSPI eDMA has separated (RN and TX in 2 sources) or shared (RX  and TX are the same source) DMA request
+ * source.
  * (1)For the separated DMA request source, enable and set the RX DMAMUX source for edmaRxRegToRxDataHandle and
  * TX DMAMUX source for edmaTxDataToTxRegHandle.
  * (2)For the shared DMA request source,  enable and set the RX/RX DMAMUX source for the edmaRxRegToRxDataHandle.
@@ -225,7 +223,7 @@ status_t DSPI_MasterTransferGetCountEDMA(SPI_Type *base, dspi_master_edma_handle
  * @param base DSPI peripheral base address.
  * @param handle DSPI handle pointer to dspi_slave_edma_handle_t.
  * @param callback DSPI callback.
- * @param userData callback function parameter.
+ * @param userData A callback function parameter.
  * @param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t.
  * @param edmaTxDataToTxRegHandle edmaTxDataToTxRegHandle pointer to edma_handle_t.
  */
@@ -239,25 +237,25 @@ void DSPI_SlaveTransferCreateHandleEDMA(SPI_Type *base,
 /*!
  * @brief DSPI slave transfer data using eDMA.
  *
- * This function transfer data using eDMA. This is non-blocking function, which returns right away. When all data
- * have been transfer, the callback function is called.
- * Note that slave EDMA transfer cannot support the situation that transfer_size is 1 when the bitsPerFrame is greater
- * than 8 .
+ * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data
+ * is transferred, the callback function is called.
+ * Note that the slave eDMA transfer doesn't support transfer_size is 1 when the bitsPerFrame is greater
+ * than eight.
 
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_slave_edma_handle_t structure which stores the transfer state.
- * @param transfer pointer to dspi_transfer_t structure.
+ * @param handle A pointer to the dspi_slave_edma_handle_t structure which stores the transfer state.
+ * @param transfer A pointer to the dspi_transfer_t structure.
  * @return status of status_t.
  */
 status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, dspi_transfer_t *transfer);
 
 /*!
- * @brief DSPI slave aborts a transfer which using eDMA.
+ * @brief DSPI slave aborts a transfer which is using eDMA.
  *
- * This function aborts a transfer which using eDMA.
+ * This function aborts a transfer which is using eDMA.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_slave_edma_handle_t structure which stores the transfer state.
+ * @param handle A pointer to the dspi_slave_edma_handle_t structure which stores the transfer state.
  */
 void DSPI_SlaveTransferAbortEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle);
 
@@ -267,8 +265,8 @@ void DSPI_SlaveTransferAbortEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handl
  * This function gets the slave eDMA transfer count.
  *
  * @param base DSPI peripheral base address.
- * @param handle pointer to dspi_slave_edma_handle_t structure which stores the transfer state.
- * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @param handle A pointer to the dspi_slave_edma_handle_t structure which stores the transfer state.
+ * @param count A number of bytes transferred so far by the non-blocking transaction.
  * @return status of status_t.
  */
 status_t DSPI_SlaveTransferGetCountEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, size_t *count);
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_edma.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_edma.c
index 1f09025fe72..be51f4c1a4d 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_edma.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_edma.c
@@ -1,32 +1,32 @@
 /*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-*   of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-*   list of conditions and the following disclaimer in the documentation and/or
-*   other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-*   contributors may be used to endorse or promote products derived from this
-*   software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #include "fsl_edma.h"
 
@@ -63,11 +63,13 @@ static void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd);
 /*! @brief Array to map EDMA instance number to base pointer. */
 static DMA_Type *const s_edmaBases[] = DMA_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Array to map EDMA instance number to clock name. */
 static const clock_ip_name_t s_edmaClockName[] = EDMA_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*! @brief Array to map EDMA instance number to IRQ number. */
-static const IRQn_Type s_edmaIRQNumber[] = DMA_CHN_IRQS;
+static const IRQn_Type s_edmaIRQNumber[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS;
 
 /*! @brief Pointers to transfer handle for each EDMA channel. */
 static edma_handle_t *s_EDMAHandle[FSL_FEATURE_EDMA_MODULE_CHANNEL * FSL_FEATURE_SOC_EDMA_COUNT];
@@ -81,7 +83,7 @@ static uint32_t EDMA_GetInstance(DMA_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_EDMA_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_edmaBases); instance++)
     {
         if (s_edmaBases[instance] == base)
         {
@@ -89,7 +91,7 @@ static uint32_t EDMA_GetInstance(DMA_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_EDMA_COUNT);
+    assert(instance < ARRAY_SIZE(s_edmaBases));
 
     return instance;
 }
@@ -122,8 +124,10 @@ void EDMA_Init(DMA_Type *base, const edma_config_t *config)
 
     uint32_t tmpreg;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Ungate EDMA periphral clock */
     CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
     /* Configure EDMA peripheral according to the configuration structure. */
     tmpreg = base->CR;
     tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK);
@@ -134,8 +138,10 @@ void EDMA_Init(DMA_Type *base, const edma_config_t *config)
 
 void EDMA_Deinit(DMA_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Gate EDMA periphral clock */
     CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void EDMA_GetDefaultConfig(edma_config_t *config)
@@ -409,46 +415,32 @@ void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask)
     }
 }
 
-uint32_t EDMA_GetRemainingBytes(DMA_Type *base, uint32_t channel)
+uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel)
 {
     assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
 
-    uint32_t nbytes = 0;
-    uint32_t remainingBytes = 0;
+    uint32_t remainingCount = 0;
 
     if (DMA_CSR_DONE_MASK & base->TCD[channel].CSR)
     {
-        remainingBytes = 0;
+        remainingCount = 0;
     }
     else
     {
-        /* Calculate the nbytes */
-        if (base->TCD[channel].NBYTES_MLOFFYES & (DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK))
-        {
-            nbytes = (base->TCD[channel].NBYTES_MLOFFYES & DMA_NBYTES_MLOFFYES_NBYTES_MASK) >>
-                     DMA_NBYTES_MLOFFYES_NBYTES_SHIFT;
-        }
-        else
-        {
-            nbytes =
-                (base->TCD[channel].NBYTES_MLOFFNO & DMA_NBYTES_MLOFFNO_NBYTES_MASK) >> DMA_NBYTES_MLOFFNO_NBYTES_SHIFT;
-        }
         /* Calculate the unfinished bytes */
         if (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK)
         {
-            remainingBytes = ((base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >>
-                              DMA_CITER_ELINKYES_CITER_SHIFT) *
-                             nbytes;
+            remainingCount =
+                (base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT;
         }
         else
         {
-            remainingBytes =
-                ((base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT) *
-                nbytes;
+            remainingCount =
+                (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT;
         }
     }
 
-    return remainingBytes;
+    return remainingCount;
 }
 
 uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel)
@@ -497,14 +489,19 @@ void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel)
     uint32_t channelIndex;
     edma_tcd_t *tcdRegs;
 
+    /* Zero the handle */
+    memset(handle, 0, sizeof(*handle));
+
     handle->base = base;
     handle->channel = channel;
     /* Get the DMA instance number */
     edmaInstance = EDMA_GetInstance(base);
     channelIndex = (edmaInstance * FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel;
     s_EDMAHandle[channelIndex] = handle;
+
     /* Enable NVIC interrupt */
-    EnableIRQ(s_edmaIRQNumber[channelIndex]);
+    EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]);
+
     /*
        Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set),
        CSR will be 0. Because in order to suit EDMA busy check mechanism in
@@ -558,8 +555,8 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config,
     assert(config != NULL);
     assert(srcAddr != NULL);
     assert(destAddr != NULL);
-    assert(srcWidth == 1U || srcWidth == 2U || srcWidth == 4U || srcWidth == 16U || srcWidth == 32U);
-    assert(destWidth == 1U || destWidth == 2U || destWidth == 4U || destWidth == 16U || destWidth == 32U);
+    assert((srcWidth == 1U) || (srcWidth == 2U) || (srcWidth == 4U) || (srcWidth == 16U) || (srcWidth == 32U));
+    assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 16U) || (destWidth == 32U));
     assert(transferBytes % bytesEachRequest == 0);
 
     config->destAddr = (uint32_t)destAddr;
@@ -825,11 +822,11 @@ void EDMA_HandleIRQ(edma_handle_t *handle)
 
     /* Clear EDMA interrupt flag */
     handle->base->CINT = handle->channel;
-    if (handle->tcdPool == NULL)
+    if ((handle->tcdPool == NULL) && (handle->callback != NULL))
     {
         (handle->callback)(handle, handle->userData, true, 0);
     }
-    else /* Use the TCD queue. */
+    else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */
     {
         uint32_t sga = handle->base->TCD[handle->channel].DLAST_SGA;
         uint32_t sga_index;
@@ -839,19 +836,19 @@ void EDMA_HandleIRQ(edma_handle_t *handle)
 
         /* Check if transfer is already finished. */
         transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0);
-        /* Get the offset of the current transfer TCD blcoks. */
+        /* Get the offset of the next transfer TCD blcoks to be loaded into the eDMA engine. */
         sga -= (uint32_t)handle->tcdPool;
-        /* Get the index of the current transfer TCD blcoks. */
+        /* Get the index of the next transfer TCD blcoks to be loaded into the eDMA engine. */
         sga_index = sga / sizeof(edma_tcd_t);
         /* Adjust header positions. */
         if (transfer_done)
         {
-            /* New header shall point to the next TCD (current one is already finished) */
+            /* New header shall point to the next TCD to be loaded (current one is already finished) */
             new_header = sga_index;
         }
         else
         {
-            /* New header shall point to this descriptor (not finished yet) */
+            /* New header shall point to this descriptor currently loaded (not finished yet) */
             new_header = sga_index ? sga_index - 1U : handle->tcdSize - 1U;
         }
         /* Calculate the number of finished TCDs */
@@ -863,7 +860,7 @@ void EDMA_HandleIRQ(edma_handle_t *handle)
             }
             else
             {
-                /* Internal error occurs. */
+                /* No TCD in the memory are going to be loaded or internal error occurs. */
                 tcds_done = 0;
             }
         }
@@ -875,9 +872,9 @@ void EDMA_HandleIRQ(edma_handle_t *handle)
                 tcds_done += handle->tcdSize;
             }
         }
-        /* Advance header to the point beyond the last finished TCD block. */
+        /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */
         handle->header = new_header;
-        /* Release TCD blocks. */
+        /* Release TCD blocks. tcdUsed is the TCD number which can be used/loaded in the memory pool. */
         handle->tcdUsed -= tcds_done;
         /* Invoke callback function. */
         if (handle->callback)
@@ -937,12 +934,260 @@ void DMA0_37_DriverIRQHandler(void)
         EDMA_HandleIRQ(s_EDMAHandle[7]);
     }
 }
+
+#if defined(DMA1)
+void DMA1_04_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[8]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[12]);
+    }
+}
+
+void DMA1_15_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[9]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[13]);
+    }
+}
+
+void DMA1_26_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[10]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[14]);
+    }
+}
+
+void DMA1_37_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[11]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[15]);
+    }
+}
+#endif
 #endif /* 8 channels (Shared) */
 
+/* 16 channels (Shared): K32H844P */
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 16U
+
+void DMA0_08_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[0]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[8]);
+    }
+}
+
+void DMA0_19_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[1]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[9]);
+    }
+}
+
+void DMA0_210_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[2]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[10]);
+    }
+}
+
+void DMA0_311_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[3]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[11]);
+    }
+}
+
+void DMA0_412_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[4]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[12]);
+    }
+}
+
+void DMA0_513_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[5]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[13]);
+    }
+}
+
+void DMA0_614_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[6]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[14]);
+    }
+}
+
+void DMA0_715_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[7]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[15]);
+    }
+}
+
+#if defined(DMA1)
+void DMA1_08_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[16]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 8U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[24]);
+    }
+}
+
+void DMA1_19_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[17]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 9U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[25]);
+    }
+}
+
+void DMA1_210_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[18]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 10U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[26]);
+    }
+}
+
+void DMA1_311_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[19]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 11U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[27]);
+    }
+}
+
+void DMA1_412_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[20]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 12U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[28]);
+    }
+}
+
+void DMA1_513_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[21]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 13U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[29]);
+    }
+}
+
+void DMA1_614_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[22]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 14U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[30]);
+    }
+}
+
+void DMA1_715_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[23]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA1, 15U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[31]);
+    }
+}
+#endif
+#endif /* 16 channels (Shared) */
+
 /* 32 channels (Shared): k80 */
 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U
 
-void DMA0_DMA16_IRQHandler(void)
+void DMA0_DMA16_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -954,7 +1199,7 @@ void DMA0_DMA16_IRQHandler(void)
     }
 }
 
-void DMA1_DMA17_IRQHandler(void)
+void DMA1_DMA17_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -966,7 +1211,7 @@ void DMA1_DMA17_IRQHandler(void)
     }
 }
 
-void DMA2_DMA18_IRQHandler(void)
+void DMA2_DMA18_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -978,7 +1223,7 @@ void DMA2_DMA18_IRQHandler(void)
     }
 }
 
-void DMA3_DMA19_IRQHandler(void)
+void DMA3_DMA19_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -990,7 +1235,7 @@ void DMA3_DMA19_IRQHandler(void)
     }
 }
 
-void DMA4_DMA20_IRQHandler(void)
+void DMA4_DMA20_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1002,7 +1247,7 @@ void DMA4_DMA20_IRQHandler(void)
     }
 }
 
-void DMA5_DMA21_IRQHandler(void)
+void DMA5_DMA21_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1014,7 +1259,7 @@ void DMA5_DMA21_IRQHandler(void)
     }
 }
 
-void DMA6_DMA22_IRQHandler(void)
+void DMA6_DMA22_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1026,7 +1271,7 @@ void DMA6_DMA22_IRQHandler(void)
     }
 }
 
-void DMA7_DMA23_IRQHandler(void)
+void DMA7_DMA23_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1038,7 +1283,7 @@ void DMA7_DMA23_IRQHandler(void)
     }
 }
 
-void DMA8_DMA24_IRQHandler(void)
+void DMA8_DMA24_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1050,7 +1295,7 @@ void DMA8_DMA24_IRQHandler(void)
     }
 }
 
-void DMA9_DMA25_IRQHandler(void)
+void DMA9_DMA25_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1062,7 +1307,7 @@ void DMA9_DMA25_IRQHandler(void)
     }
 }
 
-void DMA10_DMA26_IRQHandler(void)
+void DMA10_DMA26_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1074,7 +1319,7 @@ void DMA10_DMA26_IRQHandler(void)
     }
 }
 
-void DMA11_DMA27_IRQHandler(void)
+void DMA11_DMA27_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1086,7 +1331,7 @@ void DMA11_DMA27_IRQHandler(void)
     }
 }
 
-void DMA12_DMA28_IRQHandler(void)
+void DMA12_DMA28_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1098,7 +1343,7 @@ void DMA12_DMA28_IRQHandler(void)
     }
 }
 
-void DMA13_DMA29_IRQHandler(void)
+void DMA13_DMA29_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1110,7 +1355,7 @@ void DMA13_DMA29_IRQHandler(void)
     }
 }
 
-void DMA14_DMA30_IRQHandler(void)
+void DMA14_DMA30_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1122,7 +1367,7 @@ void DMA14_DMA30_IRQHandler(void)
     }
 }
 
-void DMA15_DMA31_IRQHandler(void)
+void DMA15_DMA31_DriverIRQHandler(void)
 {
     if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
     {
@@ -1135,6 +1380,202 @@ void DMA15_DMA31_IRQHandler(void)
 }
 #endif /* 32 channels (Shared) */
 
+/* 32 channels (Shared): MCIMX7U5_M4 */
+#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U
+
+void DMA0_0_4_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[0]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[4]);
+    }
+}
+
+void DMA0_1_5_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[1]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[5]);
+    }
+}
+
+void DMA0_2_6_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[2]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[6]);
+    }
+}
+
+void DMA0_3_7_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[3]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[7]);
+    }
+}
+
+void DMA0_8_12_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[8]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[12]);
+    }
+}
+
+void DMA0_9_13_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[9]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[13]);
+    }
+}
+
+void DMA0_10_14_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[10]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[14]);
+    }
+}
+
+void DMA0_11_15_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[11]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[15]);
+    }
+}
+
+void DMA0_16_20_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[16]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[20]);
+    }
+}
+
+void DMA0_17_21_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[17]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[21]);
+    }
+}
+
+void DMA0_18_22_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[18]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[22]);
+    }
+}
+
+void DMA0_19_23_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[19]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[23]);
+    }
+}
+
+void DMA0_24_28_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[24]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[28]);
+    }
+}
+
+void DMA0_25_29_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[25]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[29]);
+    }
+}
+
+void DMA0_26_30_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[26]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[30]);
+    }
+}
+
+void DMA0_27_31_DriverIRQHandler(void)
+{
+    if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[27]);
+    }
+    if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U)
+    {
+        EDMA_HandleIRQ(s_EDMAHandle[31]);
+    }
+}
+#endif /* 32 channels (Shared): MCIMX7U5 */
+
 /* 4 channels (No Shared): kv10  */
 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 0
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_edma.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_edma.h
index ca9632e247a..a97622d7e1e 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_edma.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_edma.h
@@ -1,32 +1,32 @@
 /*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-*   of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-*   list of conditions and the following disclaimer in the documentation and/or
-*   other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-*   contributors may be used to endorse or promote products derived from this
-*   software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _FSL_EDMA_H_
 #define _FSL_EDMA_H_
@@ -34,11 +34,10 @@
 #include "fsl_common.h"
 
 /*!
- * @addtogroup edma_driver
+ * @addtogroup edma
  * @{
  */
 
-/*! @file */
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
@@ -46,7 +45,7 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief eDMA driver version */
-#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1. */
 /*@}*/
 
 /*! @brief Compute the offset unit from DCHPRI3 */
@@ -78,28 +77,28 @@ typedef enum _edma_modulo
     kEDMA_Modulo128bytes,       /*!< Circular buffer size is 128 bytes. */
     kEDMA_Modulo256bytes,       /*!< Circular buffer size is 256 bytes. */
     kEDMA_Modulo512bytes,       /*!< Circular buffer size is 512 bytes. */
-    kEDMA_Modulo1Kbytes,        /*!< Circular buffer size is 1K bytes. */
-    kEDMA_Modulo2Kbytes,        /*!< Circular buffer size is 2K bytes. */
-    kEDMA_Modulo4Kbytes,        /*!< Circular buffer size is 4K bytes. */
-    kEDMA_Modulo8Kbytes,        /*!< Circular buffer size is 8K bytes. */
-    kEDMA_Modulo16Kbytes,       /*!< Circular buffer size is 16K bytes. */
-    kEDMA_Modulo32Kbytes,       /*!< Circular buffer size is 32K bytes. */
-    kEDMA_Modulo64Kbytes,       /*!< Circular buffer size is 64K bytes. */
-    kEDMA_Modulo128Kbytes,      /*!< Circular buffer size is 128K bytes. */
-    kEDMA_Modulo256Kbytes,      /*!< Circular buffer size is 256K bytes. */
-    kEDMA_Modulo512Kbytes,      /*!< Circular buffer size is 512K bytes. */
-    kEDMA_Modulo1Mbytes,        /*!< Circular buffer size is 1M bytes. */
-    kEDMA_Modulo2Mbytes,        /*!< Circular buffer size is 2M bytes. */
-    kEDMA_Modulo4Mbytes,        /*!< Circular buffer size is 4M bytes. */
-    kEDMA_Modulo8Mbytes,        /*!< Circular buffer size is 8M bytes. */
-    kEDMA_Modulo16Mbytes,       /*!< Circular buffer size is 16M bytes. */
-    kEDMA_Modulo32Mbytes,       /*!< Circular buffer size is 32M bytes. */
-    kEDMA_Modulo64Mbytes,       /*!< Circular buffer size is 64M bytes. */
-    kEDMA_Modulo128Mbytes,      /*!< Circular buffer size is 128M bytes. */
-    kEDMA_Modulo256Mbytes,      /*!< Circular buffer size is 256M bytes. */
-    kEDMA_Modulo512Mbytes,      /*!< Circular buffer size is 512M bytes. */
-    kEDMA_Modulo1Gbytes,        /*!< Circular buffer size is 1G bytes. */
-    kEDMA_Modulo2Gbytes,        /*!< Circular buffer size is 2G bytes. */
+    kEDMA_Modulo1Kbytes,        /*!< Circular buffer size is 1 K bytes. */
+    kEDMA_Modulo2Kbytes,        /*!< Circular buffer size is 2 K bytes. */
+    kEDMA_Modulo4Kbytes,        /*!< Circular buffer size is 4 K bytes. */
+    kEDMA_Modulo8Kbytes,        /*!< Circular buffer size is 8 K bytes. */
+    kEDMA_Modulo16Kbytes,       /*!< Circular buffer size is 16 K bytes. */
+    kEDMA_Modulo32Kbytes,       /*!< Circular buffer size is 32 K bytes. */
+    kEDMA_Modulo64Kbytes,       /*!< Circular buffer size is 64 K bytes. */
+    kEDMA_Modulo128Kbytes,      /*!< Circular buffer size is 128 K bytes. */
+    kEDMA_Modulo256Kbytes,      /*!< Circular buffer size is 256 K bytes. */
+    kEDMA_Modulo512Kbytes,      /*!< Circular buffer size is 512 K bytes. */
+    kEDMA_Modulo1Mbytes,        /*!< Circular buffer size is 1 M bytes. */
+    kEDMA_Modulo2Mbytes,        /*!< Circular buffer size is 2 M bytes. */
+    kEDMA_Modulo4Mbytes,        /*!< Circular buffer size is 4 M bytes. */
+    kEDMA_Modulo8Mbytes,        /*!< Circular buffer size is 8 M bytes. */
+    kEDMA_Modulo16Mbytes,       /*!< Circular buffer size is 16 M bytes. */
+    kEDMA_Modulo32Mbytes,       /*!< Circular buffer size is 32 M bytes. */
+    kEDMA_Modulo64Mbytes,       /*!< Circular buffer size is 64 M bytes. */
+    kEDMA_Modulo128Mbytes,      /*!< Circular buffer size is 128 M bytes. */
+    kEDMA_Modulo256Mbytes,      /*!< Circular buffer size is 256 M bytes. */
+    kEDMA_Modulo512Mbytes,      /*!< Circular buffer size is 512 M bytes. */
+    kEDMA_Modulo1Gbytes,        /*!< Circular buffer size is 1 G bytes. */
+    kEDMA_Modulo2Gbytes,        /*!< Circular buffer size is 2 G bytes. */
 } edma_modulo_t;
 
 /*! @brief Bandwidth control */
@@ -143,7 +142,7 @@ enum _edma_error_status_flags
 #if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1
     kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */
 #endif
-    kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit will be 0, otherwise be 1 */
+    kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */
 };
 
 /*! @brief eDMA interrupt source */
@@ -178,7 +177,7 @@ typedef struct _edma_config
                                            the link channel is itself. */
     bool enableHaltOnError;           /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set.
                                            Subsequently, all service requests are ignored until the HALT bit is cleared.*/
-    bool enableRoundRobinArbitration; /*!< Enable (true) round robin channel arbitration method, or fixed priority
+    bool enableRoundRobinArbitration; /*!< Enable (true) round robin channel arbitration method or fixed priority
                                            arbitration is used for channel selection */
     bool enableDebugMode; /*!< Enable(true) eDMA debug mode. When in debug mode, the eDMA stalls the start of
                                a new channel. Executing channels are allowed to complete. */
@@ -212,15 +211,15 @@ typedef struct _edma_transfer_config
                                                 form the next-state value as each source read is completed. */
     int16_t destOffset;                    /*!< Sign-extended offset applied to the current destination address to
                                                 form the next-state value as each destination write is completed. */
-    uint16_t minorLoopBytes;               /*!< Bytes to transfer in a minor loop*/
+    uint32_t minorLoopBytes;               /*!< Bytes to transfer in a minor loop*/
     uint32_t majorLoopCounts;              /*!< Major loop iteration count. */
 } edma_transfer_config_t;
 
 /*! @brief eDMA channel priority configuration */
 typedef struct _edma_channel_Preemption_config
 {
-    bool enableChannelPreemption; /*!< If true: channel can be suspended by other channel with higher priority */
-    bool enablePreemptAbility;    /*!< If true: channel can suspend other channel with low priority */
+    bool enableChannelPreemption; /*!< If true: a channel can be suspended by other channel with higher priority */
+    bool enablePreemptAbility;    /*!< If true: a channel can suspend other channel with low priority */
     uint8_t channelPriority;      /*!< Channel priority */
 } edma_channel_Preemption_config_t;
 
@@ -229,14 +228,14 @@ typedef struct _edma_minor_offset_config
 {
     bool enableSrcMinorOffset;  /*!< Enable(true) or Disable(false) source minor loop offset. */
     bool enableDestMinorOffset; /*!< Enable(true) or Disable(false) destination minor loop offset. */
-    uint32_t minorOffset;       /*!< Offset for minor loop mapping. */
+    uint32_t minorOffset;       /*!< Offset for a minor loop mapping. */
 } edma_minor_offset_config_t;
 
 /*!
  * @brief eDMA TCD.
  *
  * This structure is same as TCD register which is described in reference manual,
- * and is used to configure scatter/gather feature as a next hardware TCD.
+ * and is used to configure the scatter/gather feature as a next hardware TCD.
  */
 typedef struct _edma_tcd
 {
@@ -256,20 +255,21 @@ typedef struct _edma_tcd
 /*! @brief Callback for eDMA */
 struct _edma_handle;
 
-/*! @brief Define Callback function for eDMA. */
+/*! @brief Define callback function for eDMA. */
 typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds);
 
 /*! @brief eDMA transfer handle structure */
 typedef struct _edma_handle
 {
-    edma_callback callback;  /*!< Callback function for major count exhausted. */
-    void *userData;          /*!< Callback function parameter. */
-    DMA_Type *base;          /*!< eDMA peripheral base address. */
-    edma_tcd_t *tcdPool;     /*!< Pointer to memory stored TCDs. */
-    uint8_t channel;         /*!< eDMA channel number. */
-    volatile int8_t header;  /*!< The first TCD index. */
-    volatile int8_t tail;    /*!< The last TCD index. */
-    volatile int8_t tcdUsed; /*!< The number of used TCD slots. */
+    edma_callback callback; /*!< Callback function for major count exhausted. */
+    void *userData;         /*!< Callback function parameter. */
+    DMA_Type *base;         /*!< eDMA peripheral base address. */
+    edma_tcd_t *tcdPool;    /*!< Pointer to memory stored TCDs. */
+    uint8_t channel;        /*!< eDMA channel number. */
+    volatile int8_t header; /*!< The first TCD index. Should point to the next TCD to be loaded into the eDMA engine. */
+    volatile int8_t tail;   /*!< The last TCD index. Should point to the next TCD to be stored into the memory pool. */
+    volatile int8_t tcdUsed; /*!< The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in
+                                the memory. */
     volatile int8_t tcdSize; /*!< The total number of TCD slots in the queue. */
     uint8_t flags;           /*!< The status of the current channel. */
 } edma_handle_t;
@@ -282,24 +282,24 @@ extern "C" {
 #endif /* __cplusplus */
 
 /*!
- * @name eDMA initialization and De-initialization
+ * @name eDMA initialization and de-initialization
  * @{
  */
 
 /*!
- * @brief Initializes eDMA peripheral.
+ * @brief Initializes the eDMA peripheral.
  *
- * This function ungates the eDMA clock and configure eDMA peripheral according
+ * This function ungates the eDMA clock and configures the eDMA peripheral according
  * to the configuration structure.
  *
  * @param base eDMA peripheral base address.
- * @param config Pointer to configuration structure, see "edma_config_t".
- * @note This function enable the minor loop map feature.
+ * @param config A pointer to the configuration structure, see "edma_config_t".
+ * @note This function enables the minor loop map feature.
  */
 void EDMA_Init(DMA_Type *base, const edma_config_t *config);
 
 /*!
- * @brief Deinitializes eDMA peripheral.
+ * @brief Deinitializes the eDMA peripheral.
  *
  * This function gates the eDMA clock.
  *
@@ -310,8 +310,8 @@ void EDMA_Deinit(DMA_Type *base);
 /*!
  * @brief Gets the eDMA default configuration structure.
  *
- * This function sets the configuration structure to a default value.
- * The default configuration is set to the following value:
+ * This function sets the configuration structure to default values.
+ * The default configuration is set to the following values.
  * @code
  *   config.enableContinuousLinkMode = false;
  *   config.enableHaltOnError = true;
@@ -319,7 +319,7 @@ void EDMA_Deinit(DMA_Type *base);
  *   config.enableDebugMode = false;
  * @endcode
  *
- * @param config Pointer to eDMA configuration structure.
+ * @param config A pointer to the eDMA configuration structure.
  */
 void EDMA_GetDefaultConfig(edma_config_t *config);
 
@@ -330,22 +330,22 @@ void EDMA_GetDefaultConfig(edma_config_t *config);
  */
 
 /*!
- * @brief Sets all TCD registers to a default value.
+ * @brief Sets all TCD registers to default values.
  *
- * This function sets TCD registers for this channel to default value.
+ * This function sets TCD registers for this channel to default values.
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @note This function must not be called while the channel transfer is on-going,
- *       or it will case unpredicated results.
- * @note This function will enable auto stop request feature.
+ * @note This function must not be called while the channel transfer is ongoing
+ *       or it causes unpredictable results.
+ * @note This function enables the auto stop request feature.
  */
 void EDMA_ResetChannel(DMA_Type *base, uint32_t channel);
 
 /*!
  * @brief Configures the eDMA transfer attribute.
  *
- * This function configure the transfer attribute, including source address, destination address,
+ * This function configures the transfer attribute, including source address, destination address,
  * transfer size, address offset, and so on. It also configures the scatter gather feature if the
  * user supplies the TCD address.
  * Example:
@@ -361,11 +361,11 @@ void EDMA_ResetChannel(DMA_Type *base, uint32_t channel);
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
  * @param config Pointer to eDMA transfer configuration structure.
- * @param nextTcd Point to TCD structure. It can be NULL if user
+ * @param nextTcd Point to TCD structure. It can be NULL if users
  *                do not want to enable scatter/gather feature.
- * @note If nextTcd is not NULL, it means scatter gather feature will be enabled.
- *       And DREQ bit will be cleared in the previous transfer configuration which
- *       will be set in eDMA_ResetChannel.
+ * @note If nextTcd is not NULL, it means scatter gather feature is enabled
+ *       and DREQ bit is cleared in the previous transfer configuration, which
+ *       is set in the eDMA_ResetChannel.
  */
 void EDMA_SetTransferConfig(DMA_Type *base,
                             uint32_t channel,
@@ -375,12 +375,12 @@ void EDMA_SetTransferConfig(DMA_Type *base,
 /*!
  * @brief Configures the eDMA minor offset feature.
  *
- * Minor offset means signed-extended value added to source address or destination
+ * The minor offset means that the signed-extended value is added to the source address or destination
  * address after each minor loop.
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @param config Pointer to Minor offset configuration structure.
+ * @param config A pointer to the minor offset configuration structure.
  */
 void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config);
 
@@ -391,7 +391,7 @@ void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_mino
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number
- * @param config Pointer to channel preemption configuration structure.
+ * @param config A pointer to the channel preemption configuration structure.
  */
 static inline void EDMA_SetChannelPreemptionConfig(DMA_Type *base,
                                                    uint32_t channel,
@@ -408,30 +408,31 @@ static inline void EDMA_SetChannelPreemptionConfig(DMA_Type *base,
 /*!
  * @brief Sets the channel link for the eDMA transfer.
  *
- * This function configures  minor link or major link mode. The minor link means that the channel link is
- * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is exhausted.
+ * This function configures either the minor link or the major link mode. The minor link means that the channel link is
+ * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is
+ * exhausted.
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @param type Channel link type, it can be one of:
+ * @param type A channel link type, which can be one of the following:
  *   @arg kEDMA_LinkNone
  *   @arg kEDMA_MinorLink
  *   @arg kEDMA_MajorLink
  * @param linkedChannel The linked channel number.
- * @note User should ensure that DONE flag is cleared before call this interface, or the configuration will be invalid.
+ * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
  */
 void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel);
 
 /*!
  * @brief Sets the bandwidth for the eDMA transfer.
  *
- * In general, because the eDMA processes the minor loop, it continuously generates read/write sequences
+ * Because the eDMA processes the minor loop, it continuously generates read/write sequences
  * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of
  * each read/write access to control the bus request bandwidth seen by the crossbar switch.
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @param bandWidth Bandwidth setting, it can be one of:
+ * @param bandWidth A bandwidth setting, which can be one of the following:
  *     @arg kEDMABandwidthStallNone
  *     @arg kEDMABandwidthStall4Cycle
  *     @arg kEDMABandwidthStall8Cycle
@@ -439,7 +440,7 @@ void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_typ
 void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth);
 
 /*!
- * @brief Sets the source modulo and destination modulo for eDMA transfer.
+ * @brief Sets the source modulo and the destination modulo for the eDMA transfer.
  *
  * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
  * calculation is performed or the original register value. It provides the ability to implement a circular data
@@ -447,8 +448,8 @@ void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWi
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @param srcModulo Source modulo value.
- * @param destModulo Destination modulo value.
+ * @param srcModulo A source modulo value.
+ * @param destModulo A destination modulo value.
  */
 void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo);
 
@@ -458,7 +459,7 @@ void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, e
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @param enable The command for enable(ture) or disable(false).
+ * @param enable The command to enable (true) or disable (false).
  */
 static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable)
 {
@@ -475,7 +476,7 @@ static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, boo
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @param enable The command for enable (true) or disable (false).
+ * @param enable The command to enable (true) or disable (false).
  */
 static inline void EDMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable)
 {
@@ -489,7 +490,7 @@ static inline void EDMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel,
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @param mask The mask of interrupt source to be set. User need to use
+ * @param mask The mask of interrupt source to be set. Users need to use
  *             the defined edma_interrupt_enable_t type.
  */
 void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask);
@@ -499,7 +500,7 @@ void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mas
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @param mask The mask of interrupt source to be set. Use
+ * @param mask The mask of the interrupt source to be set. Use
  *             the defined edma_interrupt_enable_t type.
  */
 void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask);
@@ -516,15 +517,15 @@ void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t ma
  * This function sets all fields for this TCD structure to default value.
  *
  * @param tcd Pointer to the TCD structure.
- * @note This function will enable auto stop request feature.
+ * @note This function enables the auto stop request feature.
  */
 void EDMA_TcdReset(edma_tcd_t *tcd);
 
 /*!
  * @brief Configures the eDMA TCD transfer attribute.
  *
- * TCD is a transfer control descriptor. The content of the TCD is the same as hardware TCD registers.
- * STCD is used in scatter-gather mode.
+ * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers.
+ * The STCD is used in the scatter-gather mode.
  * This function configures the TCD transfer attribute, including source address, destination address,
  * transfer size, address offset, and so on. It also configures the scatter gather feature if the
  * user supplies the next TCD address.
@@ -540,33 +541,34 @@ void EDMA_TcdReset(edma_tcd_t *tcd);
  *
  * @param tcd Pointer to the TCD structure.
  * @param config Pointer to eDMA transfer configuration structure.
- * @param nextTcd Pointer to the next TCD structure. It can be NULL if user
+ * @param nextTcd Pointer to the next TCD structure. It can be NULL if users
  *                do not want to enable scatter/gather feature.
- * @note TCD address should be 32 bytes aligned, or it will cause eDMA error.
- * @note If nextTcd is not NULL, it means scatter gather feature will be enabled.
- *       And DREQ bit will be cleared in the previous transfer configuration which
- *       will be set in EDMA_TcdReset.
+ * @note TCD address should be 32 bytes aligned or it causes an eDMA error.
+ * @note If the nextTcd is not NULL, the scatter gather feature is enabled
+ *       and DREQ bit is cleared in the previous transfer configuration, which
+ *       is set in the EDMA_TcdReset.
  */
 void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd);
 
 /*!
  * @brief Configures the eDMA TCD minor offset feature.
  *
- * Minor offset is a signed-extended value added to the source address or destination
+ * A minor offset is a signed-extended value added to the source address or a destination
  * address after each minor loop.
  *
- * @param tcd Point to the TCD structure.
- * @param config Pointer to Minor offset configuration structure.
+ * @param tcd A point to the TCD structure.
+ * @param config A pointer to the minor offset configuration structure.
  */
 void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config);
 
 /*!
- * @brief Sets the channel link for eDMA TCD.
+ * @brief Sets the channel link for the eDMA TCD.
  *
  * This function configures either a minor link or a major link. The minor link means the channel link is
- * triggered every time CITER decreases by 1. The major link means that the channel link  is triggered when the CITER is exhausted.
+ * triggered every time CITER decreases by 1. The major link means that the channel link  is triggered when the CITER is
+ * exhausted.
  *
- * @note User should ensure that DONE flag is cleared before call this interface, or the configuration will be invalid.
+ * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
  * @param tcd Point to the TCD structure.
  * @param type Channel link type, it can be one of:
  *   @arg kEDMA_LinkNone
@@ -579,11 +581,11 @@ void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint
 /*!
  * @brief Sets the bandwidth for the eDMA TCD.
  *
- * In general, because the eDMA processes the minor loop, it continuously generates read/write sequences
- * until the minor count is exhausted. Bandwidth forces the eDMA to stall after the completion of
+ * Because the eDMA processes the minor loop, it continuously generates read/write sequences
+ * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of
  * each read/write access to control the bus request bandwidth seen by the crossbar switch.
- * @param tcd Point to the TCD structure.
- * @param bandWidth Bandwidth setting, it can be one of:
+ * @param tcd A pointer to the TCD structure.
+ * @param bandWidth A bandwidth setting, which can be one of the following:
  *     @arg kEDMABandwidthStallNone
  *     @arg kEDMABandwidthStall4Cycle
  *     @arg kEDMABandwidthStall8Cycle
@@ -597,15 +599,15 @@ static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWi
 }
 
 /*!
- * @brief Sets the source modulo and destination modulo for eDMA TCD.
+ * @brief Sets the source modulo and the destination modulo for the eDMA TCD.
  *
  * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
  * calculation is performed or the original register value. It provides the ability to implement a circular data
  * queue easily.
  *
- * @param tcd Point to the TCD structure.
- * @param srcModulo Source modulo value.
- * @param destModulo Destination modulo value.
+ * @param tcd A pointer to the TCD structure.
+ * @param srcModulo A source modulo value.
+ * @param destModulo A destination modulo value.
  */
 void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo);
 
@@ -614,8 +616,8 @@ void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t d
  *
  * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.
  *
- * @param tcd Point to the TCD structure.
- * @param enable The command for enable(ture) or disable(false).
+ * @param tcd A pointer to the TCD structure.
+ * @param enable The command to enable (true) or disable (false).
  */
 static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable)
 {
@@ -629,7 +631,7 @@ static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable)
  * @brief Enables the interrupt source for the eDMA TCD.
  *
  * @param tcd Point to the TCD structure.
- * @param mask The mask of interrupt source to be set. User need to use
+ * @param mask The mask of interrupt source to be set. Users need to use
  *             the defined edma_interrupt_enable_t type.
  */
 void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask);
@@ -638,7 +640,7 @@ void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask);
  * @brief Disables the interrupt source for the eDMA TCD.
  *
  * @param tcd Point to the TCD structure.
- * @param mask The mask of interrupt source to be set. User need to use
+ * @param mask The mask of interrupt source to be set. Users need to use
  *             the defined edma_interrupt_enable_t type.
  */
 void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask);
@@ -680,7 +682,7 @@ static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel)
 }
 
 /*!
- * @brief Starts the eDMA transfer by software trigger.
+ * @brief Starts the eDMA transfer by using the software trigger.
  *
  * This function starts a minor loop transfer.
  *
@@ -701,25 +703,34 @@ static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel)
  */
 
 /*!
- * @brief Gets the Remaining bytes from the eDMA current channel TCD.
+ * @brief Gets the remaining major loop count from the eDMA current channel TCD.
  *
  * This function checks the TCD (Task Control Descriptor) status for a specified
- * eDMA channel and returns the the number of bytes that have not finished.
+ * eDMA channel and returns the the number of major loop count that has not finished.
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @return Bytes have not been transferred yet for the current TCD.
- * @note This function can only be used to get unfinished bytes of transfer without
- *       the next TCD, or it might be inaccuracy.
- */
-uint32_t EDMA_GetRemainingBytes(DMA_Type *base, uint32_t channel);
+ * @return Major loop count which has not been transferred yet for the current TCD.
+ * @note 1. This function can only be used to get unfinished major loop count of transfer without
+ *          the next TCD, or it might be inaccuracy.
+ *       2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while
+ *          the channel is running.
+ *          Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO
+ *          register is needed while the eDMA IP does not support getting it while a channel is active.
+ *          In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine
+ *          is working with while a channel is running.
+ *          Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example
+ *          copied before enabling the channel) is needed. The formula to calculate it is shown below:
+ *          RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)
+ */
+uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel);
 
 /*!
  * @brief Gets the eDMA channel error status flags.
  *
  * @param base eDMA peripheral base address.
- * @return The mask of error status flags. User need to use the
- *         _edma_error_status_flags type to decode the return variables.
+ * @return The mask of error status flags. Users need to use the
+*         _edma_error_status_flags type to decode the return variables.
  */
 static inline uint32_t EDMA_GetErrorStatusFlags(DMA_Type *base)
 {
@@ -731,7 +742,7 @@ static inline uint32_t EDMA_GetErrorStatusFlags(DMA_Type *base)
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @return The mask of channel status flags. User need to use the
+ * @return The mask of channel status flags. Users need to use the
  *         _edma_channel_status_flags type to decode the return variables.
  */
 uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel);
@@ -741,7 +752,7 @@ uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel);
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
- * @param mask The mask of channel status to be cleared. User need to use
+ * @param mask The mask of channel status to be cleared. Users need to use
  *             the defined _edma_channel_status_flags type.
  */
 void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask);
@@ -754,8 +765,8 @@ void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mas
 /*!
  * @brief Creates the eDMA handle.
  *
- * This function is called if using transaction API for eDMA. This function
- * initializes the internal state of eDMA handle.
+ * This function is called if using the transactional API for eDMA. This function
+ * initializes the internal state of the eDMA handle.
  *
  * @param handle eDMA handle pointer. The eDMA handle stores callback function and
  *               parameters.
@@ -765,12 +776,12 @@ void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mas
 void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel);
 
 /*!
- * @brief Installs the TCDs memory pool into eDMA handle.
+ * @brief Installs the TCDs memory pool into the eDMA handle.
  *
  * This function is called after the EDMA_CreateHandle to use scatter/gather feature.
  *
  * @param handle eDMA handle pointer.
- * @param tcdPool Memory pool to store TCDs. It must be 32 bytes aligned.
+ * @param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned.
  * @param tcdSize The number of TCD slots.
  */
 void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize);
@@ -778,12 +789,12 @@ void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t
 /*!
  * @brief Installs a callback function for the eDMA transfer.
  *
- * This callback is called in eDMA IRQ handler. Use the callback to do something after
+ * This callback is called in the eDMA IRQ handler. Use the callback to do something after
  * the current major loop transfer completes.
  *
  * @param handle eDMA handle pointer.
  * @param callback eDMA callback function pointer.
- * @param userData Parameter for callback function.
+ * @param userData A parameter for the callback function.
  */
 void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData);
 
@@ -801,8 +812,8 @@ void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userD
  * @param transferBytes eDMA transfer bytes to be transferred.
  * @param type eDMA transfer type.
  * @note The data address and the data width must be consistent. For example, if the SRC
- *       is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in
- *       source address error(SAE).
+ *       is 4 bytes, the source address must be 4 bytes aligned, or it results in
+ *       source address error (SAE).
  */
 void EDMA_PrepareTransfer(edma_transfer_config_t *config,
                           void *srcAddr,
@@ -817,7 +828,7 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config,
  * @brief Submits the eDMA transfer request.
  *
  * This function submits the eDMA transfer request according to the transfer configuration structure.
- * If the user submits the transfer request repeatedly, this function packs an unprocessed request as
+ * If submitting the transfer request repeatedly, this function packs an unprocessed request as
  * a TCD and enables scatter/gather feature to process it in the next time.
  *
  * @param handle eDMA handle pointer.
@@ -829,9 +840,9 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config,
 status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config);
 
 /*!
- * @brief eDMA start transfer.
+ * @brief eDMA starts transfer.
  *
- * This function enables the channel request. User can call this function after submitting the transfer request
+ * This function enables the channel request. Users can call this function after submitting the transfer request
  * or before submitting the transfer request.
  *
  * @param handle eDMA handle pointer.
@@ -839,9 +850,9 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t
 void EDMA_StartTransfer(edma_handle_t *handle);
 
 /*!
- * @brief eDMA stop transfer.
+ * @brief eDMA stops transfer.
  *
- * This function disables the channel request to pause the transfer. User can call EDMA_StartTransfer()
+ * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer()
  * again to resume the transfer.
  *
  * @param handle eDMA handle pointer.
@@ -849,21 +860,41 @@ void EDMA_StartTransfer(edma_handle_t *handle);
 void EDMA_StopTransfer(edma_handle_t *handle);
 
 /*!
- * @brief eDMA abort transfer.
+ * @brief eDMA aborts transfer.
  *
  * This function disables the channel request and clear transfer status bits.
- * User can submit another transfer after calling this API.
+ * Users can submit another transfer after calling this API.
  *
  * @param handle DMA handle pointer.
  */
 void EDMA_AbortTransfer(edma_handle_t *handle);
 
 /*!
- * @brief eDMA IRQ handler for current major loop transfer complete.
+ * @brief eDMA IRQ handler for the current major loop transfer completion.
  *
- * This function clears the channel major interrupt flag and call
+ * This function clears the channel major interrupt flag and calls
  * the callback function if it is not NULL.
  *
+ * Note:
+ * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed.
+ * These include the final address adjustments and reloading of the BITER field into the CITER.
+ * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from
+ * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled).
+ *
+ * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine.
+ * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index
+ * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be
+ * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have
+ * been loaded into the eDMA engine at this point already.).
+ *
+ * For the last two continuous ISRs in a scatter/gather process, they  both load the last TCD (The last ISR does not
+ * load a new TCD) from the memory pool to the eDMA engine when major loop completes.
+ * Therefore, ensure that the header and tcdUsed updated are identical for them.
+ * tcdUsed are both 0 in this case as no TCD to be loaded.
+ *
+ * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for
+ * further details.
+ *
  * @param handle eDMA handle pointer.
  */
 void EDMA_HandleIRQ(edma_handle_t *handle);
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_enet.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_enet.c
index fe6077fba8f..674f525025d 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_enet.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_enet.c
@@ -1,32 +1,32 @@
 /*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-*   of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-*   list of conditions and the following disclaimer in the documentation and/or
-*   other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-*   contributors may be used to endorse or promote products derived from this
-*   software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #include "fsl_enet.h"
 
@@ -90,10 +90,8 @@
 #define ENET_IPV6VERSION 0x0006U
 /*! @brief Ethernet mac address length. */
 #define ENET_FRAME_MACLEN 6U
-/*! @brief Ethernet Frame header length. */
-#define ENET_FRAME_HEADERLEN 14U
 /*! @brief Ethernet VLAN header length. */
-#define ENET_FRAME_VLAN_HEADERLEN 18U
+#define ENET_FRAME_VLAN_TAGLEN 4U
 /*! @brief MDC frequency. */
 #define ENET_MDC_FREQUENCY 2500000U
 /*! @brief NanoSecond in one second. */
@@ -238,8 +236,10 @@ static status_t ENET_StoreRxFrameTime(ENET_Type *base, enet_handle_t *handle, en
 /*! @brief Pointers to enet handles for each instance. */
 static enet_handle_t *s_ENETHandle[FSL_FEATURE_SOC_ENET_COUNT] = {NULL};
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to enet clocks for each instance. */
 const clock_ip_name_t s_enetClock[] = ENET_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*! @brief Pointers to enet transmit IRQ number for each instance. */
 static const IRQn_Type s_enetTxIrqId[] = ENET_Transmit_IRQS;
@@ -259,6 +259,7 @@ static ENET_Type *const s_enetBases[] = ENET_BASE_PTRS;
 static enet_isr_t s_enetTxIsr;
 static enet_isr_t s_enetRxIsr;
 static enet_isr_t s_enetErrIsr;
+static enet_isr_t s_enetTsIsr;
 /*******************************************************************************
  * Code
  ******************************************************************************/
@@ -268,7 +269,7 @@ uint32_t ENET_GetInstance(ENET_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_ENET_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_enetBases); instance++)
     {
         if (s_enetBases[instance] == base)
         {
@@ -276,7 +277,7 @@ uint32_t ENET_GetInstance(ENET_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_ENET_COUNT);
+    assert(instance < ARRAY_SIZE(s_enetBases));
 
     return instance;
 }
@@ -314,10 +315,11 @@ void ENET_Init(ENET_Type *base,
     assert(bufferConfig->rxBufferAlign);
     assert(macAddr);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     uint32_t instance = ENET_GetInstance(base);
-
     /* Ungate ENET clock. */
     CLOCK_EnableClock(s_enetClock[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Reset ENET module. */
     ENET_Reset(base);
@@ -346,8 +348,10 @@ void ENET_Deinit(ENET_Type *base)
     /* Disable ENET. */
     base->ECR &= ~ENET_ECR_ETHEREN_MASK;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disables the clock source. */
     CLOCK_DisableClock(s_enetClock[ENET_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData)
@@ -407,7 +411,13 @@ static void ENET_SetMacController(ENET_Type *base,
     uint32_t tcr = 0;
     uint32_t ecr = 0;
     uint32_t macSpecialConfig = config->macSpecialConfig;
-    uint32_t instance = ENET_GetInstance(base);
+    uint32_t maxFrameLen = config->rxMaxFrameLen;
+
+    /* Maximum frame length check. */
+    if ((macSpecialConfig & kENET_ControlVLANTagEnable) && (maxFrameLen <= ENET_FRAME_MAX_FRAMELEN))
+    {
+        maxFrameLen = (ENET_FRAME_MAX_FRAMELEN + ENET_FRAME_VLAN_TAGLEN);
+    }
 
     /* Configures MAC receive controller with user configure structure. */
     rcr = ENET_RCR_NLC(!!(macSpecialConfig & kENET_ControlRxPayloadCheckEnable)) |
@@ -417,16 +427,16 @@ static void ENET_SetMacController(ENET_Type *base,
           ENET_RCR_BC_REJ(!!(macSpecialConfig & kENET_ControlRxBroadCastRejectEnable)) |
           ENET_RCR_PROM(!!(macSpecialConfig & kENET_ControlPromiscuousEnable)) | ENET_RCR_MII_MODE(1) |
           ENET_RCR_RMII_MODE(config->miiMode) | ENET_RCR_RMII_10T(!config->miiSpeed) |
-          ENET_RCR_MAX_FL(config->rxMaxFrameLen) | ENET_RCR_CRCFWD(1);
+          ENET_RCR_MAX_FL(maxFrameLen) | ENET_RCR_CRCFWD(1);
     /* Receive setting for half duplex. */
     if (config->miiDuplex == kENET_MiiHalfDuplex)
     {
-        rcr |= ENET_RCR_DRT(1);
+        rcr |= ENET_RCR_DRT_MASK;
     }
     /* Sets internal loop only for MII mode. */
     if ((config->macSpecialConfig & kENET_ControlMIILoopEnable) && (config->miiMode == kENET_MiiMode))
     {
-        rcr |= ENET_RCR_LOOP(1);
+        rcr |= ENET_RCR_LOOP_MASK;
         rcr &= ~ENET_RCR_DRT_MASK;
     }
     base->RCR = rcr;
@@ -446,7 +456,7 @@ static void ENET_SetMacController(ENET_Type *base,
         uint32_t reemReg;
         base->OPD = config->pauseDuration;
         reemReg = ENET_RSEM_RX_SECTION_EMPTY(config->rxFifoEmptyThreshold);
-#if FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD
+#if defined (FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD) && FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD
         reemReg |= ENET_RSEM_STAT_SECTION_EMPTY(config->rxFifoStatEmptyThreshold);
 #endif /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */
         base->RSEM = reemReg;
@@ -492,7 +502,22 @@ static void ENET_SetMacController(ENET_Type *base,
         ENET_SetSMI(base, srcClock_Hz, !!(config->macSpecialConfig & kENET_ControlSMIPreambleDisable));
     }
 
-    /* Enables Ethernet interrupt and NVIC. */
+/* Enables Ethernet interrupt and NVIC. */
+#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE
+    if (config->intCoalesceCfg)
+    {
+        uint32_t intMask = (ENET_EIMR_TXB_MASK | ENET_EIMR_RXB_MASK);
+
+        /* Clear all buffer interrupts. */
+        base->EIMR &= ~intMask;
+
+        /* Set the interrupt coalescence. */
+        base->TXIC = ENET_TXIC_ICFT(config->intCoalesceCfg->txCoalesceFrameCount[0]) |
+                     config->intCoalesceCfg->txCoalesceTimeCount[0] | ENET_TXIC_ICCS_MASK | ENET_TXIC_ICEN_MASK;
+        base->RXIC = ENET_RXIC_ICFT(config->intCoalesceCfg->rxCoalesceFrameCount[0]) |
+                     config->intCoalesceCfg->rxCoalesceTimeCount[0] | ENET_RXIC_ICCS_MASK | ENET_RXIC_ICEN_MASK;
+    }
+#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */
     ENET_EnableInterrupts(base, config->interrupt);
 
     /* ENET control register setting. */
@@ -545,7 +570,6 @@ static void ENET_SetTxBufferDescriptors(volatile enet_tx_bd_struct_t *txBdStartA
         /* Increase the index. */
         curBuffDescrip++;
     }
-
 }
 
 static void ENET_SetRxBufferDescriptors(volatile enet_rx_bd_struct_t *rxBdStartAlign,
@@ -688,6 +712,46 @@ void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_
     base->MMFR = mmfr;
 }
 
+#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO
+void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
+{
+    uint32_t mmfr = 0;
+
+    /* Parse the address from the input register. */
+    uint16_t devAddr = (phyReg >> ENET_MMFR_TA_SHIFT) & 0x1FU;
+    uint16_t regAddr = (uint16_t)(phyReg & 0xFFFFU);
+
+    /* Address write firstly. */
+    mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) |
+           ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr);
+    base->MMFR = mmfr;
+
+    /* Build MII write command. */
+    mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiWriteFrame_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) |
+           ENET_MMFR_TA(2) | ENET_MMFR_DATA(data);
+    base->MMFR = mmfr;
+}
+
+void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg)
+{
+    uint32_t mmfr = 0;
+
+    /* Parse the address from the input register. */
+    uint16_t devAddr = (phyReg >> ENET_MMFR_TA_SHIFT) & 0x1FU;
+    uint16_t regAddr = (uint16_t)(phyReg & 0xFFFFU);
+
+    /* Address write firstly. */
+    mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) |
+           ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr);
+    base->MMFR = mmfr;
+
+    /* Build MII read command. */
+    mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiReadFrame_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) |
+           ENET_MMFR_TA(2);
+    base->MMFR = mmfr;
+}
+#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */
+
 void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic)
 {
     assert(handle);
@@ -769,13 +833,15 @@ status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length)
     assert(handle->rxBdCurrent);
     assert(length);
 
+    /* Reset the length to zero. */
+    *length = 0;
+
     uint16_t validLastMask = ENET_BUFFDESCRIPTOR_RX_LAST_MASK | ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK;
     volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent;
 
     /* Check the current buffer descriptor's empty flag.  if empty means there is no frame received. */
     if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK)
     {
-        *length = 0;
         return kStatus_ENET_RxFrameEmpty;
     }
 
@@ -791,7 +857,6 @@ status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length)
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
                     )
             {
-                *length = 0;
                 return kStatus_ENET_RxFrameError;
             }
             /* FCS is removed by MAC. */
@@ -821,8 +886,9 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
 
     uint32_t len = 0;
     uint32_t offset = 0;
+    uint16_t control;
     bool isLastBuff = false;
-    volatile enet_rx_bd_struct_t *curBuffDescrip;
+    volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent;
     status_t result = kStatus_Success;
 
     /* For data-NULL input, only update the buffer descriptor. */
@@ -830,37 +896,24 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
     {
         do
         {
-            /* Get the current buffer descriptor. */
-            curBuffDescrip = handle->rxBdCurrent;
-            /* Increase current buffer descriptor to the next one. */
-            if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK)
-            {
-                handle->rxBdCurrent = handle->rxBdBase;
-            }
-            else
-            {
-                handle->rxBdCurrent++;
-            }
+            /* Update the control flag. */
+            control = handle->rxBdCurrent->control;
+            /* Updates the receive buffer descriptors. */
+            ENET_UpdateReadBuffers(base, handle);
 
-            /* The last buffer descriptor of a frame. */
-            if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK)
+            /* Find the last buffer descriptor for the frame. */
+            if (control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK)
             {
-                /* Find the last buffer descriptor for the frame*/
                 break;
             }
-        } while (handle->rxBdCurrent != handle->rxBdDirty);
 
-        /* Update all receive buffer descriptors for the whole frame. */
-        ENET_UpdateReadBuffers(base, handle);
+        } while (handle->rxBdCurrent != curBuffDescrip);
 
         return result;
     }
     else
     {
-        /* Frame read from the MAC to user buffer and update the buffer descriptors.
-        Process the frame, a frame on several receive buffers are considered . */
-        /* Get the current buffer descriptor. */
-        curBuffDescrip = handle->rxBdCurrent;
+/* A frame on one buffer or several receive buffers are both considered. */
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
         enet_ptp_time_data_t ptpTimestamp;
         bool isPtpEventMessage = false;
@@ -871,16 +924,6 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
 
         while (!isLastBuff)
         {
-            /* Increase current buffer descriptor to the next one. */
-            if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK)
-            {
-                handle->rxBdCurrent = handle->rxBdBase;
-            }
-            else
-            {
-                handle->rxBdCurrent++;
-            }
-
             /* The last buffer descriptor of a frame. */
             if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK)
             {
@@ -900,28 +943,39 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
                         result = ENET_StoreRxFrameTime(base, handle, &ptpTimestamp);
                     }
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
+
+                    /* Updates the receive buffer descriptors. */
                     ENET_UpdateReadBuffers(base, handle);
                     return result;
                 }
+                else
+                {
+                    /* Updates the receive buffer descriptors. */
+                    ENET_UpdateReadBuffers(base, handle);
+                }
             }
             else
             {
-                /* Store the fragments of a frame on several buffer descriptors. */
+                /* Store a frame on several buffer descriptors. */
                 isLastBuff = false;
-                memcpy(data + offset, curBuffDescrip->buffer, handle->rxBuffSizeAlign);
-                offset += handle->rxBuffSizeAlign;
+                /* Length check. */
                 if (offset >= length)
                 {
                     break;
                 }
+
+                memcpy(data + offset, curBuffDescrip->buffer, handle->rxBuffSizeAlign);
+                offset += handle->rxBuffSizeAlign;
+
+                /* Updates the receive buffer descriptors. */
+                ENET_UpdateReadBuffers(base, handle);
             }
 
             /* Get the current buffer descriptor. */
             curBuffDescrip = handle->rxBdCurrent;
         }
-        /* All error happens will break the while loop and arrive here to update receive buffers. */
-        ENET_UpdateReadBuffers(base, handle);
     }
+
     return kStatus_ENET_RxFrameFail;
 }
 
@@ -929,26 +983,23 @@ static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle)
 {
     assert(handle);
 
-    do
-    {
-        /* Clears status. */
-        handle->rxBdDirty->control &= ENET_BUFFDESCRIPTOR_RX_WRAP_MASK;
-        /* Sets the receive buffer descriptor with the empty flag. */
-        handle->rxBdDirty->control |= ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK;
-        /* Increases the buffer descriptor to the next one. */
-        if (handle->rxBdDirty->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK)
-        {
-            handle->rxBdDirty = handle->rxBdBase;
-        }
-        else
-        {
-            handle->rxBdDirty++;
-        }
+    /* Clears status. */
+    handle->rxBdCurrent->control &= ENET_BUFFDESCRIPTOR_RX_WRAP_MASK;
+    /* Sets the receive buffer descriptor with the empty flag. */
+    handle->rxBdCurrent->control |= ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK;
 
-        /* Actives the receive buffer descriptor. */
-        base->RDAR = ENET_RDAR_RDAR_MASK;
+    /* Increase current buffer descriptor to the next one. */
+    if (handle->rxBdCurrent->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK)
+    {
+        handle->rxBdCurrent = handle->rxBdBase;
+    }
+    else
+    {
+        handle->rxBdCurrent++;
+    }
 
-    } while (handle->rxBdDirty != handle->rxBdCurrent);
+    /* Actives the receive buffer descriptor. */
+    base->RDAR = ENET_RDAR_RDAR_MASK;
 }
 
 status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length)
@@ -956,7 +1007,7 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
     assert(handle);
     assert(handle->txBdCurrent);
     assert(data);
-    assert(length <= (ENET_FRAME_MAX_VALNFRAMELEN - 4));
+    assert(length <= ENET_FRAME_MAX_FRAMELEN);
 
     volatile enet_tx_bd_struct_t *curBuffDescrip = handle->txBdCurrent;
     uint32_t len = 0;
@@ -985,6 +1036,11 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
         {
             curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK;
         }
+        else
+        {
+            curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK;
+        }
+
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
         curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK);
 
@@ -1013,6 +1069,10 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
             {
                 curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK;
             }
+            else
+            {
+                curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK;
+            }
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 
             /* Increase the buffer descriptor address. */
@@ -1034,6 +1094,7 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
                 curBuffDescrip->length = handle->txBuffSizeAlign;
                 len += handle->txBuffSizeAlign;
                 /* Sets the control flag. */
+                curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK;
                 curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK;
                 /* Active the transmit buffer descriptor*/
                 base->TDAR = ENET_TDAR_TDAR_MASK;
@@ -1054,7 +1115,7 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
 
         } while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK));
 
-        return kStatus_ENET_TxFrameFail;
+        return kStatus_ENET_TxFrameBusy;
     }
 }
 
@@ -1216,7 +1277,7 @@ static bool ENET_Ptp1588ParseFrame(uint8_t *data, enet_ptp_time_data_t *ptpTsDat
     /* Check for VLAN frame. */
     if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == ENET_HTONS(ENET_8021QVLAN))
     {
-        buffer += (ENET_FRAME_VLAN_HEADERLEN - ENET_FRAME_HEADERLEN);
+        buffer += ENET_FRAME_VLAN_TAGLEN;
     }
 
     ptpType = *(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET);
@@ -1299,7 +1360,8 @@ void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_conf
 
     /* Enables the time stamp interrupt for the master clock on a device. */
     ENET_EnableInterrupts(base, kENET_TsTimerInterrupt);
-    /* Enables the transmit interrupt to store the transmit frame time-stamp. */
+    /* Enables only frame interrupt for transmit side to store the transmit
+    frame time-stamp when the whole frame is transmitted out. */
     ENET_EnableInterrupts(base, kENET_TxFrameInterrupt);
     ENET_DisableInterrupts(base, kENET_TxBufferInterrupt);
 
@@ -1318,6 +1380,7 @@ void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_conf
 
     /* Set the IRQ handler when the interrupt is enabled. */
     s_enetTxIsr = ENET_TransmitIRQHandler;
+    s_enetTsIsr = ENET_Ptp1588TimerIRQHandler;
     EnableIRQ(s_enetTsIrqId[instance]);
     EnableIRQ(s_enetTxIrqId[instance]);
 }
@@ -1624,8 +1687,8 @@ void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle)
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
         if (base->EIR & kENET_TxFrameInterrupt)
         {
-        /* Store the transmit timestamp from the buffer descriptor should be done here. */
-        ENET_StoreTxFrameTime(base, handle);
+            /* Store the transmit timestamp from the buffer descriptor should be done here. */
+            ENET_StoreTxFrameTime(base, handle);
         }
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 
@@ -1665,7 +1728,7 @@ void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle)
     uint32_t errMask = kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | kENET_PayloadRxInterrupt |
                        kENET_LateCollisionInterrupt | kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt;
 
-    /* Check if the PTP time stamp interrupt happen. */
+    /* Check if the error interrupt happen. */
     if (kENET_WakeupInterrupt & base->EIR)
     {
         /* Clear the wakeup interrupt. */
@@ -1680,7 +1743,7 @@ void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle)
     }
     else
     {
-        /* Clear the time stamp interrupt. */
+        /* Clear the error interrupt event status. */
         errMask &= base->EIR;
         base->EIR = errMask;
         /* Callback function. */
@@ -1721,13 +1784,34 @@ void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle)
         }
     }
 }
+#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 
-void ENET_1588_Timer_IRQHandler(void)
+void ENET_CommonFrame0IRQHandler(ENET_Type *base)
 {
-    ENET_Ptp1588TimerIRQHandler(ENET, s_ENETHandle[0]);
+    uint32_t event = base->EIR;
+    uint32_t instance = ENET_GetInstance(base);
+
+    if (event & ENET_TX_INTERRUPT)
+    {
+        s_enetTxIsr(base, s_ENETHandle[instance]);
+    }
+
+    if (event & ENET_RX_INTERRUPT)
+    {
+        s_enetRxIsr(base, s_ENETHandle[instance]);
+    }
+
+    if (event & ENET_TS_INTERRUPT)
+    {
+        s_enetTsIsr(base, s_ENETHandle[instance]);
+    }
+    if (event & ENET_ERR_INTERRUPT)
+    {
+        s_enetErrIsr(base, s_ENETHandle[instance]);
+    }
 }
-#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 
+#if defined(ENET)
 void ENET_Transmit_IRQHandler(void)
 {
     s_enetTxIsr(ENET, s_ENETHandle[0]);
@@ -1742,3 +1826,10 @@ void ENET_Error_IRQHandler(void)
 {
     s_enetErrIsr(ENET, s_ENETHandle[0]);
 }
+
+void ENET_1588_Timer_IRQHandler(void)
+{
+    s_enetTsIsr(ENET, s_ENETHandle[0]);
+}
+#endif
+
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_enet.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_enet.h
index f35da473cd8..211a01138b4 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_enet.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_enet.h
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,7 +37,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -46,7 +45,7 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief Defines the driver version. */
-#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1. */
 /*@}*/
 
 /*! @name Control and status region bit masks of the receive buffer descriptor. */
@@ -124,18 +123,18 @@
 #endif
 #define ENET_TX_INTERRUPT (kENET_TxFrameInterrupt | kENET_TxBufferInterrupt)
 #define ENET_RX_INTERRUPT (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt)
+#define ENET_TS_INTERRUPT (kENET_TsTimerInterrupt | kENET_TsAvailInterrupt)
 #define ENET_ERR_INTERRUPT (kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | \
     kENET_LateCollisionInterrupt | kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt | kENET_PayloadRxInterrupt)
 
+
 /*! @name Defines the maximum Ethernet frame size. */
 /*@{*/
-#define ENET_FRAME_MAX_FRAMELEN 1518U     /*!< Maximum Ethernet frame size. */
-#define ENET_FRAME_MAX_VALNFRAMELEN 1522U /*!< Maximum VLAN frame size. */
+#define ENET_FRAME_MAX_FRAMELEN 1518U     /*!< Default maximum Ethernet frame size. */
 /*@}*/
 
 #define ENET_FIFO_MIN_RX_FULL 5U /*!< ENET minimum receive FIFO full. */
 #define ENET_RX_MIN_BUFFERSIZE 256U /*!< ENET minimum buffer size. */
-#define ENET_BUFF_ALIGNMENT 16U /*!< Ethernet buffer alignment. */
 
 /*! @brief Defines the PHY address scope for the ENET. */
 #define ENET_PHY_MAXADDRESS (ENET_MMFR_PA_MASK >> ENET_MMFR_PA_SHIFT)
@@ -191,6 +190,15 @@ typedef enum _enet_mii_read
     kENET_MiiReadNoCompliant = 3U /*!< Read frame operation, but not MII-compliant. */
 } enet_mii_read_t;
 
+#if defined (FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO
+/*! @brief Define the MII opcode for extended MDIO_CLAUSES_45 Frame. */
+typedef enum _enet_mii_extend_opcode {
+    kENET_MiiAddrWrite_C45 = 0U,  /*!< Address Write operation. */
+    kENET_MiiWriteFrame_C45 = 1U, /*!< Write frame operation for a valid MII management frame. */
+    kENET_MiiReadFrame_C45 = 3U   /*!< Read frame operation for a valid MII management frame. */
+} enet_mii_extend_opcode;
+#endif  /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */
+
 /*! @brief Defines a special configuration for ENET MAC controller.
  *
  * These control flags are provided for special user requirements.
@@ -237,12 +245,9 @@ typedef enum _enet_interrupt_enable
     kENET_RetryLimitInterrupt = ENET_EIR_RL_MASK,    /*!< Collision Retry Limit interrupt source */
     kENET_UnderrunInterrupt = ENET_EIR_UN_MASK,      /*!< Transmit FIFO underrun interrupt source */
     kENET_PayloadRxInterrupt = ENET_EIR_PLR_MASK,    /*!< Payload Receive interrupt source */
-    kENET_WakeupInterrupt = ENET_EIR_WAKEUP_MASK     /*!< WAKEUP interrupt source */
-#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
-    ,
+    kENET_WakeupInterrupt = ENET_EIR_WAKEUP_MASK,     /*!< WAKEUP interrupt source */
     kENET_TsAvailInterrupt = ENET_EIR_TS_AVAIL_MASK, /*!< TS AVAIL interrupt source for PTP */
     kENET_TsTimerInterrupt = ENET_EIR_TS_TIMER_MASK  /*!< TS WRAP interrupt source for PTP */
-#endif                                               /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 } enet_interrupt_enable_t;
 
 /*! @brief Defines the common interrupt event for callback use. */
@@ -252,10 +257,8 @@ typedef enum _enet_event
     kENET_TxEvent,     /*!< Transmit event. */
     kENET_ErrEvent,    /*!< Error event: BABR/BABT/EBERR/LC/RL/UN/PLR . */
     kENET_WakeUpEvent, /*!< Wake up from sleep mode event. */
-#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
     kENET_TimeStampEvent,     /*!< Time stamp event. */
     kENET_TimeStampAvailEvent /*!< Time stamp available event.*/
-#endif                        /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 } enet_event_t;
 
 /*! @brief Defines the transmit accelerator configuration. */
@@ -380,15 +383,20 @@ typedef struct _enet_data_error_stats
 #endif                                   /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 } enet_data_error_stats_t;
 
-/*! @brief Defines the receive buffer descriptor configure structure.
+/*! @brief Defines the receive buffer descriptor configuration structure.
  *
- * Note: For the internal DMA requirements, the buffers have a corresponding alignment requirement:
- * 1. The aligned receive and transmit buffer size must be evenly divisible by 16.
+ * Note that for the internal DMA requirements, the buffers have a corresponding alignment requirements.
+ * 1. The aligned receive and transmit buffer size must be evenly divisible by ENET_BUFF_ALIGNMENT.
+ *    when the data buffers are in cacheable region when cache is enabled, all those size should be
+ *    aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size.
  * 2. The aligned transmit and receive buffer descriptor start address must be at
- *    least 64 bit aligned. However, it's recommended to be evenly divisible by 16.
- * 3. The aligned transmit and receive buffer start address must be evenly divisible by 16.
+ *    least 64 bit aligned. However, it's recommended to be evenly divisible by ENET_BUFF_ALIGNMENT.
+ *    buffer descriptors should be put in non-cacheable region when cache is enabled.
+ * 3. The aligned transmit and receive data buffer start address must be evenly divisible by ENET_BUFF_ALIGNMENT.
  *    Receive buffers should be continuous with the total size equal to "rxBdNumber * rxBuffSizeAlign".
  *    Transmit buffers should be continuous with the total size equal to "txBdNumber * txBuffSizeAlign".
+ *    when the data buffers are in cacheable region when cache is enabled, all those size should be
+ *    aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size. 
  */
 typedef struct _enet_buffer_config
 {
@@ -429,7 +437,7 @@ typedef struct _enet_ptp_time_data_ring
     enet_ptp_time_data_t *ptpTsData; /*!< PTP message data structure. */
 } enet_ptp_time_data_ring_t;
 
-/*! @brief Defines the ENET PTP configure structure. */
+/*! @brief Defines the ENET PTP configuration structure. */
 typedef struct _enet_ptp_config
 {
     uint8_t ptpTsRxBuffNum;            /*!< Receive 1588 timestamp buffer number*/
@@ -441,19 +449,28 @@ typedef struct _enet_ptp_config
 } enet_ptp_config_t;
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 
-
+#if defined (FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE
+/*! @brief Defines the interrupt coalescing configure structure. */
+typedef struct _enet_intcoalesce_config
+{
+    uint8_t txCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit interrupt coalescing frame count threshold. */
+    uint16_t txCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit interrupt coalescing timer count threshold. */
+    uint8_t rxCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; /*!< Receive interrupt coalescing frame count threshold. */
+    uint16_t rxCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; /*!< Receive interrupt coalescing timer count threshold. */
+} enet_intcoalesce_config_t;
+#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */
 
 /*! @brief Defines the basic configuration structure for the ENET device.
  *
  * Note:
- *  1. macSpecialConfig is used for a special control configuration, A logical OR of
+ *  1. macSpecialConfig is used for a special control configuration, a logical OR of
  *  "enet_special_control_flag_t". For a special configuration for MAC,
  *  set this parameter to 0.
- *  2. txWatermark is used for a cut-through operation. It is in steps of 64 bytes:
+ *  2. txWatermark is used for a cut-through operation. It is in steps of 64 bytes.
  *  0/1  - 64 bytes written to TX FIFO before transmission of a frame begins.
  *  2    - 128 bytes written to TX FIFO ....
  *  3    - 192 bytes written to TX FIFO ....
- *  The maximum of txWatermark is 0x2F   - 4032 bytes written to TX FIFO ....
+ *  The maximum of txWatermark is 0x2F   - 4032 bytes written to TX FIFO.
  *  txWatermark allows minimizing the transmit latency to set the txWatermark to 0 or 1
  *  or for larger bus access latency 3 or larger due to contention for the system bus.
  *  3. rxFifoFullThreshold is similar to the txWatermark for cut-through operation in RX.
@@ -485,7 +502,7 @@ typedef struct _enet_config
     uint16_t pauseDuration;       /*!< For flow control enabled case: Pause duration. */
     uint8_t rxFifoEmptyThreshold; /*!< For flow control enabled case:  when RX FIFO level reaches this value,
                                      it makes MAC generate XOFF pause frame. */
-#if FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD
+#if defined (FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD) && FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD
     uint8_t rxFifoStatEmptyThreshold; /*!< For flow control enabled case: number of frames in the receive FIFO,
                                     independent of size, that can be accept. If the limit is reached, reception
                                     continues and a pause frame is triggered. */
@@ -494,6 +511,10 @@ typedef struct _enet_config
                                       the MAC receive ready status. */
     uint8_t txFifoWatermark;          /*!< For store and forward disable case, the data required in TX FIFO
                                       before a frame transmit start. */
+#if defined (FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE
+    enet_intcoalesce_config_t *intCoalesceCfg; /* If the interrupt coalsecence is not required in the ring n(0,1,2), please set
+                                         to NULL. */
+#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */
 } enet_config_t;
 
 /* Forward declaration of the handle typedef. */
@@ -507,7 +528,6 @@ struct _enet_handle
 {
     volatile enet_rx_bd_struct_t *rxBdBase;    /*!< Receive buffer descriptor base address pointer. */
     volatile enet_rx_bd_struct_t *rxBdCurrent; /*!< The current available receive buffer descriptor pointer. */
-    volatile enet_rx_bd_struct_t *rxBdDirty;   /*!< The dirty receive buffer descriptor needed to be updated from. */
     volatile enet_tx_bd_struct_t *txBdBase;    /*!< Transmit buffer descriptor base address pointer. */
     volatile enet_tx_bd_struct_t *txBdCurrent; /*!< The current available transmit buffer descriptor pointer. */
     volatile enet_tx_bd_struct_t *txBdDirty;   /*!< The dirty transmit buffer descriptor needed to be updated from. */
@@ -533,7 +553,7 @@ extern "C" {
 #endif
 
 /*!
-  * @name Initialization and De-initialization
+  * @name Initialization and de-initialization
   * @{
   */
 
@@ -541,10 +561,10 @@ extern "C" {
  * @brief Gets the ENET default configuration structure.
  *
  * The purpose of this API is to get the default ENET MAC controller
- * configure structure for ENET_Init(). User may use the initialized
- * structure unchanged in ENET_Init(), or modify some fields of the
+ * configuration structure for ENET_Init(). Users may use the initialized
+ * structure unchanged in ENET_Init() or modify fields of the
  * structure before calling ENET_Init().
- * Example:
+ * This is an example.
    @code
    enet_config_t config;
    ENET_GetDefaultConfig(&config);
@@ -560,18 +580,18 @@ void ENET_GetDefaultConfig(enet_config_t *config);
  *
  * @param base    ENET peripheral base address.
  * @param handle  ENET handler pointer.
- * @param config  ENET mac configuration structure pointer.
+ * @param config  ENET Mac configuration structure pointer.
  *        The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig
  *        can be used directly. It is also possible to verify the Mac configuration using other methods.
  * @param bufferConfig  ENET buffer configuration structure pointer.
  *        The buffer configuration should be prepared for ENET Initialization.
- * @param macAddr  ENET mac address of Ethernet device. This MAC address should be
+ * @param macAddr  ENET mac address of the Ethernet device. This Mac address should be
  *        provided.
  * @param srcClock_Hz The internal module clock source for MII clock.
  *
- * @note ENET has two buffer descriptors: legacy buffer descriptors and
- * enhanced 1588 buffer descriptors. The legacy descriptor is used by default. To
- * use 1588 feature, use the enhanced 1588 buffer descriptor
+ * @note ENET has two buffer descriptors legacy buffer descriptors and
+ * enhanced IEEE 1588 buffer descriptors. The legacy descriptor is used by default. To
+ * use the IEEE 1588 feature, use the enhanced IEEE 1588 buffer descriptor
  * by defining "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" and calling ENET_Ptp1588Configure()
  * to configure the 1588 feature and related buffers after calling ENET_Init().
  */
@@ -593,8 +613,8 @@ void ENET_Deinit(ENET_Type *base);
 /*!
  * @brief Resets the ENET module.
  *
- * This function restores the ENET module to reset state.
- * Note that this function sets all registers to
+ * This function restores the ENET module to the reset state.
+ * Note that this function sets all registers to the
  * reset state. As a result, the ENET module can't work after calling this function.
  *
  * @param base  ENET peripheral base address.
@@ -621,7 +641,7 @@ static inline void ENET_Reset(ENET_Type *base)
 void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex);
 
 /*!
- * @brief Sets the ENET SMI(serial management interface)- MII management interface.
+ * @brief Sets the ENET SMI (serial management interface) - MII management interface.
  *
  * @param base  ENET peripheral base address.
  * @param srcClock_Hz This is the ENET module clock frequency. Normally it's the system clock. See clock distribution.
@@ -634,7 +654,7 @@ void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled)
 /*!
  * @brief Gets the ENET SMI- MII management interface configuration.
  *
- * This API is used to get the SMI configuration to check if the MII management
+ * This API is used to get the SMI configuration to check whether the MII management
  * interface has been set.
  *
  * @param base  ENET peripheral base address.
@@ -646,7 +666,7 @@ static inline bool ENET_GetSMI(ENET_Type *base)
 }
 
 /*!
- * @brief Reads data from the PHY register through SMI interface.
+ * @brief Reads data from the PHY register through an SMI interface.
  *
  * @param base  ENET peripheral base address.
  * @return The data read from PHY
@@ -667,7 +687,7 @@ static inline uint32_t ENET_ReadSMIData(ENET_Type *base)
 void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation);
 
 /*!
- * @brief Starts a SMI write command.
+ * @brief Starts an SMI write command.
  *
  * @param base  ENET peripheral base address.
  * @param phyAddr The PHY address.
@@ -677,6 +697,31 @@ void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_
  */
 void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data);
 
+#if defined (FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO
+/*!
+ * @brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI read command.
+ *
+ * @param base  ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param phyReg The PHY register. For MDIO IEEE802.3 Clause 45,
+ *        the phyReg is a 21-bits combination of the devaddr (5 bits device address)
+ *        and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr.
+ */
+void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg);
+
+/*!
+ * @brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI write command.
+ *
+ * @param base  ENET peripheral base address.
+ * @param phyAddr The PHY address.
+ * @param phyReg The PHY register. For MDIO IEEE802.3 Clause 45,
+ *        the phyReg is a 21-bits combination of the devaddr (5 bits device address)
+ *        and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr.
+ * @param data The data written to PHY.
+ */
+void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
+#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */
+
 /* @} */
 
 /*!
@@ -721,7 +766,7 @@ void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address);
 /* @} */
 
 /*!
- * @name Other basic operation
+ * @name Other basic operations
  * @{
  */
 
@@ -762,13 +807,13 @@ static inline void ENET_EnableSleepMode(ENET_Type *base, bool enable)
 }
 
 /*!
- * @brief Gets ENET transmit and receive accelerator functions from MAC controller.
+ * @brief Gets ENET transmit and receive accelerator functions from the MAC controller.
  *
  * @param base  ENET peripheral base address.
  * @param txAccelOption The transmit accelerator option. The "enet_tx_accelerator_t" is
- *         recommended to be used to as the mask to get the exact the accelerator option.
+ *         recommended  as the mask to get the exact the accelerator option.
  * @param rxAccelOption The receive accelerator option. The "enet_rx_accelerator_t" is
- *         recommended to be used to as the mask to get the exact the accelerator option.
+ *         recommended as the mask to get the exact the accelerator option.
  */
 static inline void ENET_GetAccelFunction(ENET_Type *base, uint32_t *txAccelOption, uint32_t *rxAccelOption)
 {
@@ -782,7 +827,7 @@ static inline void ENET_GetAccelFunction(ENET_Type *base, uint32_t *txAccelOptio
 /* @} */
 
 /*!
- * @name Interrupts.
+ * @name Interrupts
  * @{
  */
 
@@ -791,7 +836,7 @@ static inline void ENET_GetAccelFunction(ENET_Type *base, uint32_t *txAccelOptio
  *
  * This function enables the ENET interrupt according to the provided mask. The mask
  * is a logical OR of enumeration members. See @ref enet_interrupt_enable_t.
- * For example, to enable the TX frame interrupt and RX frame interrupt, do this:
+ * For example, to enable the TX frame interrupt and RX frame interrupt, do the following.
  * @code
  *     ENET_EnableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt);
  * @endcode
@@ -810,7 +855,7 @@ static inline void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask)
  *
  * This function disables the ENET interrupts according to the provided mask. The mask
  * is a logical OR of enumeration members. See @ref enet_interrupt_enable_t.
- * For example, to disable the TX frame interrupt and RX frame interrupt, do this:
+ * For example, to disable the TX frame interrupt and RX frame interrupt, do the following.
  * @code
  *     ENET_DisableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt);
  * @endcode
@@ -841,7 +886,7 @@ static inline uint32_t ENET_GetInterruptStatus(ENET_Type *base)
  *
  * This function clears enabled ENET interrupts according to the provided mask. The mask
  * is a logical OR of enumeration members. See the @ref enet_interrupt_enable_t.
- * For example, to clear the TX frame interrupt and RX frame interrupt, do this:
+ * For example, to clear the TX frame interrupt and RX frame interrupt, do the following.
  * @code
  *     ENET_ClearInterruptStatus(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt);
  * @endcode
@@ -863,8 +908,8 @@ static inline void ENET_ClearInterruptStatus(ENET_Type *base, uint32_t mask)
  */
 
 /*!
- * @brief Set the callback function.
- * This API is provided for application callback required case when ENET
+ * @brief Sets the callback function.
+ * This API is provided for the application callback required case when ENET
  * interrupt is enabled. This API should be called after calling ENET_Init.
  *
  * @param handle ENET handler pointer. Should be provided by application.
@@ -879,7 +924,7 @@ void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *use
  * This API must be called after the ENET_GetRxFrameSize and before the ENET_ReadFrame().
  * If the ENET_GetRxFrameSize returns kStatus_ENET_RxFrameError,
  * the ENET_GetRxErrBeforeReadFrame can be used to get the exact error statistics.
- * For example:
+ * This is an example.
  * @code
  *       status = ENET_GetRxFrameSize(&g_handle, &length);
  *       if (status == kStatus_ENET_RxFrameError)
@@ -911,29 +956,54 @@ void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t
  */
 status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic);
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
-       /*!
-       * @brief Gets the size of the read frame.
-       * This function reads a received frame size from the ENET buffer descriptors.
-       * @note The FCS of the frame is removed by MAC controller and the size is the length without the FCS.
-       * After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the
-       * receive buffers If the result is not "kStatus_ENET_RxFrameEmpty".
-       *
-       * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
-       * @param length The length of the valid frame received.
-       * @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame.
-       * @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data
-       *         and NULL length to update the receive buffers.
-       * @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame
-       *         should be called with the right data buffer and the captured data length input.
-       */
+/*!
+* @brief Gets the size of the read frame.
+* This function gets a received frame size from the ENET buffer descriptors.
+* @note The FCS of the frame is automatically removed by Mac and the size is the length without the FCS.
+* After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the
+* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty".
+*
+* @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
+* @param length The length of the valid frame received.
+* @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame.
+* @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data
+*         and NULL length to update the receive buffers.
+* @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame
+*         should be called with the right data buffer and the captured data length input.
+*/
 status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length);
 
 /*!
  * @brief Reads a frame from the ENET device.
  * This function reads a frame (both the data and the length) from the ENET buffer descriptors.
  * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer.
- * @note The FCS of the frame is removed by MAC controller and is not delivered to the application.
- *
+ * This is an example.
+ * @code
+ *       uint32_t length;
+ *       enet_handle_t g_handle;
+ *       //Get the received frame size firstly.
+ *       status = ENET_GetRxFrameSize(&g_handle, &length);
+ *       if (length != 0)
+ *       {
+ *           //Allocate memory here with the size of "length"
+ *           uint8_t *data = memory allocate interface;
+ *           if (!data)
+ *           {
+ *               ENET_ReadFrame(ENET, &g_handle, NULL, 0);
+ *               //Add the console warning log.
+ *           }
+ *           else
+ *           {
+ *              status = ENET_ReadFrame(ENET, &g_handle, data, length);
+ *              //Call stack input API to deliver the data to stack
+ *           }
+ *       }
+ *       else if (status == kStatus_ENET_RxFrameError)
+ *       {
+ *          //Update the received buffer when a error frame is received.
+ *           ENET_ReadFrame(ENET, &g_handle, NULL, 0);
+ *       }
+ * @endcode
  * @param base  ENET peripheral base address.
  * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init.
  * @param data The data buffer provided by user to store the frame which memory size should be at least "length".
@@ -952,8 +1022,10 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
  * @param data The data buffer provided by user to be send.
  * @param length The length of the data to be send.
  * @retval kStatus_Success  Send frame succeed.
- * @retval kStatus_ENET_TxFrameBusy  Transmit buffer descriptor is busy under transmit.
- * @retval kStatus_ENET_TxFrameFail  Transmit frame fail.
+ * @retval kStatus_ENET_TxFrameBusy  Transmit buffer descriptor is busy under transmission.
+ *         The transmit busy happens when the data send rate is over the MAC capacity.
+ *         The waiting mechanism is recommended to be added after each call return with
+ *         kStatus_ENET_TxFrameBusy.
  */
 status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length);
 
@@ -981,6 +1053,14 @@ void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle);
  */
 void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle);
 
+/*!
+ * @brief the common IRQ handler for the tx/rx/error etc irq handler.
+ *
+ * This is used for the combined tx/rx/error interrupt for single ring (ring 0).
+ *
+ * @param base  ENET peripheral base address.
+ */
+void ENET_CommonFrame0IRQHandler(ENET_Type *base);
 /* @} */
 
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
@@ -990,7 +1070,7 @@ void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle);
  */
 
 /*!
- * @brief Configures the ENET PTP 1588 feature with the basic configuration.
+ * @brief Configures the ENET PTP IEEE 1588 feature with the basic configuration.
  * The function sets the clock for PTP 1588 timer and enables
  * time stamp interrupts and transmit interrupts for PTP 1588 features.
  * This API should be called when the 1588 feature is enabled
@@ -1044,7 +1124,7 @@ static inline void ENET_Ptp1588StopTimer(ENET_Type *base)
 void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod);
 
 /*!
- * @brief Sets ENET PTP 1588 timer channel mode.
+ * @brief Sets the ENET PTP 1588 timer channel mode.
  *
  * @param base  ENET peripheral base address.
  * @param channel The ENET PTP timer channel number.
@@ -1064,8 +1144,55 @@ static inline void ENET_Ptp1588SetChannelMode(ENET_Type *base,
     base->CHANNEL[channel].TCSR = tcrReg;
 }
 
+#if defined(FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL) && FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL
+/*!
+ * @brief Sets ENET PTP 1588 timer channel mode pulse width.
+ *
+ * For the input "mode" in ENET_Ptp1588SetChannelMode, the kENET_PtpChannelPulseLowonCompare
+ * kENET_PtpChannelPulseHighonCompare only support the pulse width for one 1588 clock.
+ * this function is extended for control the pulse width from 1 to 32 1588 clock cycles. 
+ * so call this function if you need to set the timer channel mode for 
+ * kENET_PtpChannelPulseLowonCompare or kENET_PtpChannelPulseHighonCompare
+ * with pulse width more than one 1588 clock,
+ *
+ * @param base  ENET peripheral base address.
+ * @param channel The ENET PTP timer channel number.
+ * @param isOutputLow  True --- timer channel is configured for output compare 
+ *                              pulse output low.
+ *                     false --- timer channel is configured for output compare
+ *                              pulse output high.
+ * @param pulseWidth  The pulse width control value, range from 0 ~ 31.
+ *                     0  --- pulse width is one 1588 clock cycle.
+ *                     31 --- pulse width is thirty two 1588 clock cycles.      
+ * @param intEnable Enables or disables the interrupt.
+ */
+static inline void ENET_Ptp1588SetChannelOutputPulseWidth(ENET_Type *base,
+                                              enet_ptp_timer_channel_t channel,
+                                              bool isOutputLow,
+                                              uint8_t pulseWidth,
+                                              bool intEnable)
+{
+    uint32_t tcrReg;
+
+    tcrReg = ENET_TCSR_TIE(intEnable) | ENET_TCSR_TPWC(pulseWidth);
+    
+    if (isOutputLow)
+    {
+        tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseLowonCompare);
+    }
+    else
+    {
+        tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseHighonCompare);
+    }
+
+    /* Disable channel mode first. */
+    base->CHANNEL[channel].TCSR = 0;
+    base->CHANNEL[channel].TCSR = tcrReg;
+}
+#endif   /* FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL */
+
 /*!
- * @brief Sets ENET PTP 1588 timer channel comparison value.
+ * @brief Sets the ENET PTP 1588 timer channel comparison value.
  *
  * @param base  ENET peripheral base address.
  * @param channel The PTP timer channel, see "enet_ptp_timer_channel_t".
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ewm.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ewm.c
index 1a71a07e582..f22eff941e9 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ewm.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ewm.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -40,7 +40,12 @@ void EWM_Init(EWM_Type *base, const ewm_config_t *config)
 
     uint32_t value = 0U;
 
+#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \
+    (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE))
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_EnableClock(kCLOCK_Ewm0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+#endif
     value = EWM_CTRL_EWMEN(config->enableEwm) | EWM_CTRL_ASSIN(config->setInputAssertLogic) |
             EWM_CTRL_INEN(config->enableEwmInput) | EWM_CTRL_INTEN(config->enableInterrupt);
 #if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER
@@ -59,7 +64,12 @@ void EWM_Init(EWM_Type *base, const ewm_config_t *config)
 void EWM_Deinit(EWM_Type *base)
 {
     EWM_DisableInterrupts(base, kEWM_InterruptEnable);
+#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \
+    (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE))
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_DisableClock(kCLOCK_Ewm0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+#endif /* FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE */
 }
 
 void EWM_GetDefaultConfig(ewm_config_t *config)
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ewm.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ewm.h
index a5c45b3fe76..aa32ed3c713 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ewm.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ewm.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -33,11 +33,10 @@
 #include "fsl_common.h"
 
 /*!
- * @addtogroup ewm_driver
+ * @addtogroup ewm
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -49,14 +48,14 @@
 #define FSL_EWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
 /*@}*/
 
-/*! @brief Describes ewm clock source. */
+/*! @brief Describes EWM clock source. */
 #if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT
 typedef enum _ewm_lpo_clock_source
 {
-    kEWM_LpoClockSource0 = 0U, /*!< ewm clock sourced from lpo_clk[0]*/
-    kEWM_LpoClockSource1 = 1U, /*!< ewm clock sourced from lpo_clk[1]*/
-    kEWM_LpoClockSource2 = 2U, /*!< ewm clock sourced from lpo_clk[2]*/
-    kEWM_LpoClockSource3 = 3U, /*!< ewm clock sourced from lpo_clk[3]*/
+    kEWM_LpoClockSource0 = 0U, /*!< EWM clock sourced from lpo_clk[0]*/
+    kEWM_LpoClockSource1 = 1U, /*!< EWM clock sourced from lpo_clk[1]*/
+    kEWM_LpoClockSource2 = 2U, /*!< EWM clock sourced from lpo_clk[2]*/
+    kEWM_LpoClockSource3 = 3U, /*!< EWM clock sourced from lpo_clk[3]*/
 } ewm_lpo_clock_source_t;
 #endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */
 
@@ -77,18 +76,18 @@ typedef struct _ewm_config
 #if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER
     uint8_t prescaler;        /*!< Clock prescaler value */
 #endif                        /* FSL_FEATURE_EWM_HAS_PRESCALER */
-    uint8_t compareLowValue;  /*!< Compare low register value */
-    uint8_t compareHighValue; /*!< Compare high register value */
+    uint8_t compareLowValue;  /*!< Compare low-register value */
+    uint8_t compareHighValue; /*!< Compare high-register value */
 } ewm_config_t;
 
 /*!
- * @brief EWM interrupt configuration structure, default settings all disabled.
+ * @brief EWM interrupt configuration structure with default settings all disabled.
  *
- * This structure contains the settings for all of the EWM interrupt configurations.
+ * This structure contains the settings for all of EWM interrupt configurations.
  */
 enum _ewm_interrupt_enable_t
 {
-    kEWM_InterruptEnable = EWM_CTRL_INTEN_MASK, /*!< Enable EWM to generate an interrupt*/
+    kEWM_InterruptEnable = EWM_CTRL_INTEN_MASK, /*!< Enable the EWM to generate an interrupt*/
 };
 
 /*!
@@ -98,7 +97,7 @@ enum _ewm_interrupt_enable_t
  */
 enum _ewm_status_flags_t
 {
-    kEWM_RunningFlag = EWM_CTRL_EWMEN_MASK, /*!< Running flag, set when ewm is enabled*/
+    kEWM_RunningFlag = EWM_CTRL_EWMEN_MASK, /*!< Running flag, set when EWM is enabled*/
 };
 
 /*******************************************************************************
@@ -110,7 +109,7 @@ extern "C" {
 #endif /* __cplusplus */
 
 /*!
- * @name EWM Initialization and De-initialization
+ * @name EWM initialization and de-initialization
  * @{
  */
 
@@ -119,10 +118,10 @@ extern "C" {
  *
  * This function is used to initialize the EWM. After calling, the EWM
  * runs immediately according to the configuration.
- * Note that except for interrupt enable control bit, other control bits and registers are write once after a
+ * Note that, except for the interrupt enable control bit, other control bits and registers are write once after a
  * CPU reset. Modifying them more than once generates a bus transfer error.
  *
- * Example:
+ * This is an example.
  * @code
  *   ewm_config_t config;
  *   EWM_GetDefaultConfig(&config);
@@ -131,7 +130,7 @@ extern "C" {
  * @endcode
  *
  * @param base EWM peripheral base address
- * @param config The configuration of EWM
+ * @param config The configuration of the EWM
 */
 void EWM_Init(EWM_Type *base, const ewm_config_t *config);
 
@@ -147,8 +146,8 @@ void EWM_Deinit(EWM_Type *base);
 /*!
  * @brief Initializes the EWM configuration structure.
  *
- * This function initializes the EWM configure structure to default values. The default
- * values are:
+ * This function initializes the EWM configuration structure to default values. The default
+ * values are as follows.
  * @code
  *   ewmConfig->enableEwm = true;
  *   ewmConfig->enableEwmInput = false;
@@ -160,7 +159,7 @@ void EWM_Deinit(EWM_Type *base);
  *   ewmConfig->compareHighValue = 0xFEU;
  * @endcode
  *
- * @param config Pointer to EWM configuration structure.
+ * @param config Pointer to the EWM configuration structure.
  * @see ewm_config_t
  */
 void EWM_GetDefaultConfig(ewm_config_t *config);
@@ -179,7 +178,7 @@ void EWM_GetDefaultConfig(ewm_config_t *config);
  *
  * @param base EWM peripheral base address
  * @param mask The interrupts to enable
- *        The parameter can be combination of the following source if defined:
+ *        The parameter can be combination of the following source if defined
  *        @arg kEWM_InterruptEnable
  */
 static inline void EWM_EnableInterrupts(EWM_Type *base, uint32_t mask)
@@ -194,7 +193,7 @@ static inline void EWM_EnableInterrupts(EWM_Type *base, uint32_t mask)
  *
  * @param base EWM peripheral base address
  * @param mask The interrupts to disable
- *        The parameter can be combination of the following source if defined:
+ *        The parameter can be combination of the following source if defined
  *        @arg kEWM_InterruptEnable
  */
 static inline void EWM_DisableInterrupts(EWM_Type *base, uint32_t mask)
@@ -203,19 +202,19 @@ static inline void EWM_DisableInterrupts(EWM_Type *base, uint32_t mask)
 }
 
 /*!
- * @brief Gets EWM all status flags.
+ * @brief Gets all status flags.
  *
  * This function gets all status flags.
  *
- * Example for getting Running Flag:
+ * This is an example for getting the running flag.
  * @code
  *   uint32_t status;
  *   status = EWM_GetStatusFlags(ewm_base) & kEWM_RunningFlag;
  * @endcode
  * @param base        EWM peripheral base address
  * @return            State of the status flag: asserted (true) or not-asserted (false).@see _ewm_status_flags_t
- *                    - true: related status flag has been set.
- *                    - false: related status flag is not set.
+ *                    - True: a related status flag has been set.
+ *                    - False: a related status flag is not set.
  */
 static inline uint32_t EWM_GetStatusFlags(EWM_Type *base)
 {
@@ -223,9 +222,9 @@ static inline uint32_t EWM_GetStatusFlags(EWM_Type *base)
 }
 
 /*!
- * @brief Service EWM.
+ * @brief Services the EWM.
  *
- * This function reset EWM counter to zero.
+ * This function resets the EWM counter to zero.
  *
  * @param base EWM peripheral base address
 */
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flash.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flash.c
index 2add4e96352..f63e6c98145 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flash.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flash.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -38,6 +38,7 @@
  * @name Misc utility defines
  * @{
  */
+/*! @brief Alignment utility. */
 #ifndef ALIGN_DOWN
 #define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a))))
 #endif
@@ -45,18 +46,74 @@
 #define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a))))))
 #endif
 
-#define BYTES_JOIN_TO_WORD_1_3(x, y) ((((uint32_t)(x)&0xFFU) << 24) | ((uint32_t)(y)&0xFFFFFFU))
-#define BYTES_JOIN_TO_WORD_2_2(x, y) ((((uint32_t)(x)&0xFFFFU) << 16) | ((uint32_t)(y)&0xFFFFU))
-#define BYTES_JOIN_TO_WORD_3_1(x, y) ((((uint32_t)(x)&0xFFFFFFU) << 8) | ((uint32_t)(y)&0xFFU))
-#define BYTES_JOIN_TO_WORD_1_1_2(x, y, z) \
-    ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFU) << 16) | ((uint32_t)(z)&0xFFFFU))
-#define BYTES_JOIN_TO_WORD_1_2_1(x, y, z) \
-    ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFFFU) << 8) | ((uint32_t)(z)&0xFFU))
-#define BYTES_JOIN_TO_WORD_2_1_1(x, y, z) \
-    ((((uint32_t)(x)&0xFFFFU) << 16) | (((uint32_t)(y)&0xFFU) << 8) | ((uint32_t)(z)&0xFFU))
-#define BYTES_JOIN_TO_WORD_1_1_1_1(x, y, z, w)                                                      \
-    ((((uint32_t)(x)&0xFFU) << 24) | (((uint32_t)(y)&0xFFU) << 16) | (((uint32_t)(z)&0xFFU) << 8) | \
-     ((uint32_t)(w)&0xFFU))
+/*! @brief Join bytes to word utility. */
+#define B1P4(b) (((uint32_t)(b)&0xFFU) << 24)
+#define B1P3(b) (((uint32_t)(b)&0xFFU) << 16)
+#define B1P2(b) (((uint32_t)(b)&0xFFU) << 8)
+#define B1P1(b) ((uint32_t)(b)&0xFFU)
+#define B2P3(b) (((uint32_t)(b)&0xFFFFU) << 16)
+#define B2P2(b) (((uint32_t)(b)&0xFFFFU) << 8)
+#define B2P1(b) ((uint32_t)(b)&0xFFFFU)
+#define B3P2(b) (((uint32_t)(b)&0xFFFFFFU) << 8)
+#define B3P1(b) ((uint32_t)(b)&0xFFFFFFU)
+#define BYTES_JOIN_TO_WORD_1_3(x, y) (B1P4(x) | B3P1(y))
+#define BYTES_JOIN_TO_WORD_2_2(x, y) (B2P3(x) | B2P1(y))
+#define BYTES_JOIN_TO_WORD_3_1(x, y) (B3P2(x) | B1P1(y))
+#define BYTES_JOIN_TO_WORD_1_1_2(x, y, z) (B1P4(x) | B1P3(y) | B2P1(z))
+#define BYTES_JOIN_TO_WORD_1_2_1(x, y, z) (B1P4(x) | B2P2(y) | B1P1(z))
+#define BYTES_JOIN_TO_WORD_2_1_1(x, y, z) (B2P3(x) | B1P2(y) | B1P1(z))
+#define BYTES_JOIN_TO_WORD_1_1_1_1(x, y, z, w) (B1P4(x) | B1P3(y) | B1P2(z) | B1P1(w))
+/*@}*/
+
+/*!
+ * @name Secondary flash configuration
+ * @{
+ */
+/*! @brief Indicates whether the secondary flash has its own protection register in flash module. */
+#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) && defined(FTFE_FPROTS_PROTS_MASK)
+#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER (1)
+#else
+#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER (0)
+#endif
+
+/*! @brief Indicates whether the secondary flash has its own Execute-Only access register in flash module. */
+#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) && defined(FTFE_FACSSS_SGSIZE_S_MASK)
+#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER (1)
+#else
+#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER (0)
+#endif
+/*@}*/
+
+/*!
+ * @name Flash cache ands speculation control defines
+ * @{
+ */
+#if defined(MCM_PLACR_CFCC_MASK) || defined(MCM_CPCR2_CCBC_MASK)
+#define FLASH_CACHE_IS_CONTROLLED_BY_MCM (1)
+#else
+#define FLASH_CACHE_IS_CONTROLLED_BY_MCM (0)
+#endif
+#if defined(FMC_PFB0CR_CINV_WAY_MASK) || defined(FMC_PFB01CR_CINV_WAY_MASK)
+#define FLASH_CACHE_IS_CONTROLLED_BY_FMC (1)
+#else
+#define FLASH_CACHE_IS_CONTROLLED_BY_FMC (0)
+#endif
+#if defined(MCM_PLACR_DFCS_MASK)
+#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM (1)
+#else
+#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM (0)
+#endif
+#if defined(MSCM_OCMDR_OCM1_MASK) || defined(MSCM_OCMDR_OCMC1_MASK)
+#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM (1)
+#else
+#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM (0)
+#endif
+#if defined(FMC_PFB0CR_S_INV_MASK) || defined(FMC_PFB0CR_S_B_INV_MASK) || defined(FMC_PFB01CR_S_INV_MASK) || \
+    defined(FMC_PFB01CR_S_B_INV_MASK)
+#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC (1)
+#else
+#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC (0)
+#endif
 /*@}*/
 
 /*! @brief Data flash IFR map Field*/
@@ -121,6 +178,7 @@
 #define FTFx_ERASE_BLOCK 0x08U                     /*!< ERSBLK*/
 #define FTFx_ERASE_SECTOR 0x09U                    /*!< ERSSCR*/
 #define FTFx_PROGRAM_SECTION 0x0BU                 /*!< PGMSEC*/
+#define FTFx_GENERATE_CRC 0x0CU                    /*!< CRCGEN*/
 #define FTFx_VERIFY_ALL_BLOCK 0x40U                /*!< RD1ALL*/
 #define FTFx_READ_ONCE 0x41U                       /*!< RDONCE or RDINDEX*/
 #define FTFx_PROGRAM_ONCE 0x43U                    /*!< PGMONCE or PGMINDEX*/
@@ -192,19 +250,56 @@
 /*@}*/
 
 /*!
- * @brief Enumeration for access segment property.
+ * @name Common flash register access info defines
+ * @{
  */
-enum _flash_access_segment_property
-{
-    kFLASH_accessSegmentBase = 256UL,
-};
+#define FTFx_FCCOB3_REG (FTFx->FCCOB3)
+#define FTFx_FCCOB5_REG (FTFx->FCCOB5)
+#define FTFx_FCCOB6_REG (FTFx->FCCOB6)
+#define FTFx_FCCOB7_REG (FTFx->FCCOB7)
+
+#if defined(FTFA_FPROTH0_PROT_MASK) || defined(FTFE_FPROTH0_PROT_MASK) || defined(FTFL_FPROTH0_PROT_MASK)
+#define FTFx_FPROT_HIGH_REG (FTFx->FPROTH3)
+#define FTFx_FPROTH3_REG (FTFx->FPROTH3)
+#define FTFx_FPROTH2_REG (FTFx->FPROTH2)
+#define FTFx_FPROTH1_REG (FTFx->FPROTH1)
+#define FTFx_FPROTH0_REG (FTFx->FPROTH0)
+#endif
+
+#if defined(FTFA_FPROTL0_PROT_MASK) || defined(FTFE_FPROTL0_PROT_MASK) || defined(FTFL_FPROTL0_PROT_MASK)
+#define FTFx_FPROT_LOW_REG (FTFx->FPROTL3)
+#define FTFx_FPROTL3_REG (FTFx->FPROTL3)
+#define FTFx_FPROTL2_REG (FTFx->FPROTL2)
+#define FTFx_FPROTL1_REG (FTFx->FPROTL1)
+#define FTFx_FPROTL0_REG (FTFx->FPROTL0)
+#elif defined(FTFA_FPROT0_PROT_MASK) || defined(FTFE_FPROT0_PROT_MASK) || defined(FTFL_FPROT0_PROT_MASK)
+#define FTFx_FPROT_LOW_REG (FTFx->FPROT3)
+#define FTFx_FPROTL3_REG (FTFx->FPROT3)
+#define FTFx_FPROTL2_REG (FTFx->FPROT2)
+#define FTFx_FPROTL1_REG (FTFx->FPROT1)
+#define FTFx_FPROTL0_REG (FTFx->FPROT0)
+#endif
+
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER
+#define FTFx_FPROTSH_REG (FTFx->FPROTSH)
+#define FTFx_FPROTSL_REG (FTFx->FPROTSL)
+#endif
+
+#define FTFx_XACCH3_REG (FTFx->XACCH3)
+#define FTFx_XACCL3_REG (FTFx->XACCL3)
+
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER
+#define FTFx_XACCSH_REG (FTFx->XACCSH)
+#define FTFx_XACCSL_REG (FTFx->XACCSL)
+#endif
+/*@}*/
 
 /*!
- * @brief Enumeration for acceleration ram property.
+ * @brief Enumeration for access segment property.
  */
-enum _flash_acceleration_ram_property
+enum _flash_access_segment_property
 {
-    kFLASH_accelerationRamSize = 0x400U
+    kFLASH_AccessSegmentBase = 256UL,
 };
 
 /*!
@@ -212,25 +307,78 @@ enum _flash_acceleration_ram_property
  */
 enum _flash_config_area_range
 {
-    kFLASH_configAreaStart = 0x400U,
-    kFLASH_configAreaEnd = 0x40FU
+    kFLASH_ConfigAreaStart = 0x400U,
+    kFLASH_ConfigAreaEnd = 0x40FU
 };
 
-/*! @brief program Flash block base address*/
-#define PFLASH_BLOCK_BASE 0x00U
-
-/*! @brief Total flash region count*/
-#define FSL_FEATURE_FTFx_REGION_COUNT (32U)
-
 /*!
  * @name Flash register access type defines
  * @{
  */
-#if FLASH_DRIVER_IS_FLASH_RESIDENT
-#define FTFx_REG_ACCESS_TYPE volatile uint8_t *
+#define FTFx_REG8_ACCESS_TYPE volatile uint8_t *
 #define FTFx_REG32_ACCESS_TYPE volatile uint32_t *
-#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
-       /*@}*/
+/*@}*/
+
+/*!
+ * @brief MCM cache register access info defines.
+ */
+#if defined(MCM_PLACR_CFCC_MASK)
+#define MCM_CACHE_CLEAR_MASK MCM_PLACR_CFCC_MASK
+#define MCM_CACHE_CLEAR_SHIFT MCM_PLACR_CFCC_SHIFT
+#if defined(MCM)
+#define MCM0_CACHE_REG MCM->PLACR
+#elif defined(MCM0)
+#define MCM0_CACHE_REG MCM0->PLACR
+#endif
+#if defined(MCM1)
+#define MCM1_CACHE_REG MCM1->PLACR
+#endif
+#elif defined(MCM_CPCR2_CCBC_MASK)
+#define MCM_CACHE_CLEAR_MASK MCM_CPCR2_CCBC_MASK
+#define MCM_CACHE_CLEAR_SHIFT MCM_CPCR2_CCBC_SHIFT
+#if defined(MCM)
+#define MCM0_CACHE_REG MCM->CPCR2
+#elif defined(MCM0)
+#define MCM0_CACHE_REG MCM0->CPCR2
+#endif
+#if defined(MCM1)
+#define MCM1_CACHE_REG MCM1->CPCR2
+#endif
+#endif
+
+/*!
+ * @brief MSCM cache register access info defines.
+ */
+#if defined(MSCM_OCMDR_OCM1_MASK)
+#define MSCM_SPECULATION_DISABLE_MASK MSCM_OCMDR_OCM1_MASK
+#define MSCM_SPECULATION_DISABLE_SHIFT MSCM_OCMDR_OCM1_SHIFT
+#define MSCM_SPECULATION_DISABLE(x) MSCM_OCMDR_OCM1(x)
+#elif defined(MSCM_OCMDR_OCMC1_MASK)
+#define MSCM_SPECULATION_DISABLE_MASK MSCM_OCMDR_OCMC1_MASK
+#define MSCM_SPECULATION_DISABLE_SHIFT MSCM_OCMDR_OCMC1_SHIFT
+#define MSCM_SPECULATION_DISABLE(x) MSCM_OCMDR_OCMC1(x)
+#endif
+
+/*!
+ * @brief MSCM prefetch speculation defines.
+ */
+#define MSCM_OCMDR_OCMC1_DFDS_MASK (0x10U)
+#define MSCM_OCMDR_OCMC1_DFCS_MASK (0x20U)
+
+#define MSCM_OCMDR_OCMC1_DFDS_SHIFT (4U)
+#define MSCM_OCMDR_OCMC1_DFCS_SHIFT (5U)
+
+/*!
+ * @brief Flash size encoding rule.
+ */
+#define FLASH_MEMORY_SIZE_ENCODING_RULE_K1_2 (0x00U)
+#define FLASH_MEMORY_SIZE_ENCODING_RULE_K3 (0x01U)
+
+#if defined(K32W042S1M2_M0P_SERIES) || defined(K32W042S1M2_M4_SERIES)
+#define FLASH_MEMORY_SIZE_ENCODING_RULE (FLASH_MEMORY_SIZE_ENCODING_RULE_K3)
+#else
+#define FLASH_MEMORY_SIZE_ENCODING_RULE (FLASH_MEMORY_SIZE_ENCODING_RULE_K1_2)
+#endif
 
 /*******************************************************************************
  * Prototypes
@@ -238,9 +386,9 @@ enum _flash_config_area_range
 
 #if FLASH_DRIVER_IS_FLASH_RESIDENT
 /*! @brief Copy flash_run_command() to RAM*/
-static void copy_flash_run_command(uint8_t *flashRunCommand);
+static void copy_flash_run_command(uint32_t *flashRunCommand);
 /*! @brief Copy flash_cache_clear_command() to RAM*/
-static void copy_flash_cache_clear_command(uint8_t *flashCacheClearCommand);
+static void copy_flash_common_bit_operation(uint32_t *flashCommonBitOperation);
 /*! @brief Check whether flash execute-in-ram functions are ready*/
 static status_t flash_check_execute_in_ram_function_info(flash_config_t *config);
 #endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
@@ -251,6 +399,9 @@ static status_t flash_command_sequence(flash_config_t *config);
 /*! @brief Perform the cache clear to the flash*/
 void flash_cache_clear(flash_config_t *config);
 
+/*! @brief Process the cache to the flash*/
+static void flash_cache_clear_process(flash_config_t *config, flash_cache_clear_process_t process);
+
 /*! @brief Validates the range and alignment of the given address range.*/
 static status_t flash_check_range(flash_config_t *config,
                                   uint32_t startAddress,
@@ -291,44 +442,131 @@ static status_t flash_validate_swap_indicator_address(flash_config_t *config, ui
 static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option);
 #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
 
+/*! @brief Gets the flash protection information (region size, region count).*/
+static status_t flash_get_protection_info(flash_config_t *config, flash_protection_config_t *info);
+
+#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL
+/*! @brief Gets the flash Execute-Only access information (Segment size, Segment count).*/
+static status_t flash_get_access_info(flash_config_t *config, flash_access_config_t *info);
+#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
+
+#if FLASH_CACHE_IS_CONTROLLED_BY_MCM
+/*! @brief Performs the cache clear to the flash by MCM.*/
+void mcm_flash_cache_clear(flash_config_t *config);
+#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MCM */
+
+#if FLASH_CACHE_IS_CONTROLLED_BY_FMC
+/*! @brief Performs the cache clear to the flash by FMC.*/
+void fmc_flash_cache_clear(void);
+#endif /* FLASH_CACHE_IS_CONTROLLED_BY_FMC */
+
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
+/*! @brief Sets the prefetch speculation buffer to the flash by MSCM.*/
+void mscm_flash_prefetch_speculation_enable(bool enable);
+#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM */
+
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC
+/*! @brief Performs the prefetch speculation buffer clear to the flash by FMC.*/
+void fmc_flash_prefetch_speculation_clear(void);
+#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC */
+
 /*******************************************************************************
  * Variables
  ******************************************************************************/
 
 /*! @brief Access to FTFx->FCCOB */
-#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA
-volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFA->FCCOB3;
-#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE
-volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFE->FCCOB3;
-#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL
-volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFL->FCCOB3;
-#else
-#error "Unknown flash controller"
+volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFx_FCCOB3_REG;
+/*! @brief Access to FTFx->FPROT */
+volatile uint32_t *const kFPROTL = (volatile uint32_t *)&FTFx_FPROT_LOW_REG;
+#if defined(FTFx_FPROT_HIGH_REG)
+volatile uint32_t *const kFPROTH = (volatile uint32_t *)&FTFx_FPROT_HIGH_REG;
 #endif
 
-/*! @brief Access to FTFx->FPROT */
-#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA
-volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFA->FPROT3;
-#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE
-volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFE->FPROT3;
-#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL
-volatile uint32_t *const kFPROT = (volatile uint32_t *)&FTFL->FPROT3;
-#else
-#error "Unknown flash controller"
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER
+volatile uint8_t *const kFPROTSL = (volatile uint8_t *)&FTFx_FPROTSL_REG;
+volatile uint8_t *const kFPROTSH = (volatile uint8_t *)&FTFx_FPROTSH_REG;
 #endif
 
 #if FLASH_DRIVER_IS_FLASH_RESIDENT
 /*! @brief A function pointer used to point to relocated flash_run_command() */
-static void (*callFlashRunCommand)(FTFx_REG_ACCESS_TYPE ftfx_fstat);
-/*! @brief A function pointer used to point to relocated flash_cache_clear_command() */
-static void (*callFlashCacheClearCommand)(FTFx_REG32_ACCESS_TYPE ftfx_reg);
+static void (*callFlashRunCommand)(FTFx_REG8_ACCESS_TYPE ftfx_fstat);
+/*! @brief A function pointer used to point to relocated flash_common_bit_operation() */
+static void (*callFlashCommonBitOperation)(FTFx_REG32_ACCESS_TYPE base,
+                                           uint32_t bitMask,
+                                           uint32_t bitShift,
+                                           uint32_t bitValue);
+
+/*!
+ * @brief Position independent code of flash_run_command()
+ *
+ * Note1: The prototype of C function is shown as below:
+ * @code
+ *   void flash_run_command(FTFx_REG8_ACCESS_TYPE ftfx_fstat)
+ *   {
+ *       // clear CCIF bit
+ *       *ftfx_fstat = FTFx_FSTAT_CCIF_MASK;
+ *
+ *       // Check CCIF bit of the flash status register, wait till it is set.
+ *       // IP team indicates that this loop will always complete.
+ *       while (!((*ftfx_fstat) & FTFx_FSTAT_CCIF_MASK))
+ *       {
+ *       }
+ *   }
+ * @endcode
+ * Note2: The binary code is generated by IAR 7.70.1
+ */
+const static uint16_t s_flashRunCommandFunctionCode[] = {
+    0x2180, /* MOVS  R1, #128 ; 0x80 */
+    0x7001, /* STRB  R1, [R0] */
+    /* @4: */
+    0x7802, /* LDRB  R2, [R0] */
+    0x420a, /* TST   R2, R1 */
+    0xd0fc, /* BEQ.N @4 */
+    0x4770  /* BX    LR */
+};
+
+/*!
+ * @brief Position independent code of flash_common_bit_operation()
+ *
+ * Note1: The prototype of C function is shown as below:
+ * @code
+ *   void flash_common_bit_operation(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, uint32_t
+ * bitValue)
+ *   {
+ *       if (bitMask)
+ *       {
+ *           uint32_t value = (((uint32_t)(((uint32_t)(bitValue)) << bitShift)) & bitMask);
+ *           *base = (*base & (~bitMask)) | value;
+ *       }
+ *
+ *       __ISB();
+ *       __DSB();
+ *   }
+ * @endcode
+ * Note2: The binary code is generated by IAR 7.70.1
+ */
+const static uint16_t s_flashCommonBitOperationFunctionCode[] = {
+    0xb510, /* PUSH  {R4, LR} */
+    0x2900, /* CMP   R1, #0 */
+    0xd005, /* BEQ.N @12 */
+    0x6804, /* LDR   R4, [R0] */
+    0x438c, /* BICS  R4, R4, R1 */
+    0x4093, /* LSLS  R3, R3, R2 */
+    0x4019, /* ANDS  R1, R1, R3 */
+    0x4321, /* ORRS  R1, R1, R4 */
+    0x6001, /* STR   R1, [R0] */
+    /*  @12: */
+    0xf3bf, 0x8f6f, /* ISB */
+    0xf3bf, 0x8f4f, /* DSB */
+    0xbd10          /* POP   {R4, PC} */
+};
 #endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
 
 #if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED)
 /*! @brief A static buffer used to hold flash_run_command() */
-static uint8_t s_flashRunCommand[kFLASH_executeInRamFunctionMaxSize];
-/*! @brief A static buffer used to hold flash_cache_clear_command() */
-static uint8_t s_flashCacheClearCommand[kFLASH_executeInRamFunctionMaxSize];
+static uint32_t s_flashRunCommand[kFLASH_ExecuteInRamFunctionMaxSizeInWords];
+/*! @brief A static buffer used to hold flash_common_bit_operation() */
+static uint32_t s_flashCommonBitOperation[kFLASH_ExecuteInRamFunctionMaxSizeInWords];
 /*! @brief Flash execute-in-ram function information */
 static flash_execute_in_ram_function_config_t s_flashExecuteInRamFunctionInfo;
 #endif
@@ -351,6 +589,7 @@ static flash_execute_in_ram_function_config_t s_flashExecuteInRamFunctionInfo;
  *      flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10;
  *  @endcode
  */
+#if (FLASH_MEMORY_SIZE_ENCODING_RULE == FLASH_MEMORY_SIZE_ENCODING_RULE_K1_2)
 const uint16_t kPFlashDensities[] = {
     8,    /* 0x0 - 8192, 8KB */
     16,   /* 0x1 - 16384, 16KB */
@@ -369,6 +608,26 @@ const uint16_t kPFlashDensities[] = {
     1536, /* 0xe - 1572864, 1.5MB */
     /* 2048,  0xf - 2097152, 2MB */
 };
+#elif(FLASH_MEMORY_SIZE_ENCODING_RULE == FLASH_MEMORY_SIZE_ENCODING_RULE_K3)
+const uint16_t kPFlashDensities[] = {
+    0,    /* 0x0 - undefined */
+    0,    /* 0x1 - undefined */
+    0,    /* 0x2 - undefined */
+    0,    /* 0x3 - undefined */
+    0,    /* 0x4 - undefined */
+    0,    /* 0x5 - undefined */
+    0,    /* 0x6 - undefined */
+    0,    /* 0x7 - undefined */
+    0,    /* 0x8 - undefined */
+    0,    /* 0x9 - undefined */
+    256,  /* 0xa - 262144, 256KB */
+    0,    /* 0xb - undefined */
+    1024, /* 0xc - 1048576, 1MB */
+    0,    /* 0xd - undefined */
+    0,    /* 0xe - undefined */
+    0,    /* 0xf - undefined */
+};
+#endif
 
 /*******************************************************************************
  * Code
@@ -376,39 +635,86 @@ const uint16_t kPFlashDensities[] = {
 
 status_t FLASH_Init(flash_config_t *config)
 {
-    uint32_t flashDensity;
-
     if (config == NULL)
     {
         return kStatus_FLASH_InvalidArgument;
     }
 
-    /* calculate the flash density from SIM_FCFG1.PFSIZE */
-    uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT;
-    /* PFSIZE=0xf means that on customer parts the IFR was not correctly programmed.
-     * We just use the pre-defined flash size in feature file here to support pre-production parts */
-    if (pfsize == 0xf)
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED
+    if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash)
     {
-        flashDensity = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE;
+/* calculate the flash density from SIM_FCFG1.PFSIZE */
+#if defined(SIM_FCFG1_CORE1_PFSIZE_MASK)
+        uint32_t flashDensity;
+        uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_CORE1_PFSIZE_MASK) >> SIM_FCFG1_CORE1_PFSIZE_SHIFT;
+        if (pfsize == 0xf)
+        {
+            flashDensity = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE;
+        }
+        else
+        {
+            flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10;
+        }
+        config->PFlashTotalSize = flashDensity;
+#else
+        /* Unused code to solve MISRA-C issue*/
+        config->PFlashBlockBase = kPFlashDensities[0];
+        config->PFlashTotalSize = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE;
+#endif
+        config->PFlashBlockBase = FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS;
+        config->PFlashBlockCount = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT;
+        config->PFlashSectorSize = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE;
     }
     else
+#endif /* FLASH_SSD_IS_SECONDARY_FLASH_ENABLED */
     {
-        flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10;
-    }
+        uint32_t flashDensity;
+
+/* calculate the flash density from SIM_FCFG1.PFSIZE */
+#if defined(SIM_FCFG1_CORE0_PFSIZE_MASK)
+        uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_CORE0_PFSIZE_MASK) >> SIM_FCFG1_CORE0_PFSIZE_SHIFT;
+#elif defined(SIM_FCFG1_PFSIZE_MASK)
+        uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT;
+#else
+#error "Unknown flash size"
+#endif
+        /* PFSIZE=0xf means that on customer parts the IFR was not correctly programmed.
+         * We just use the pre-defined flash size in feature file here to support pre-production parts */
+        if (pfsize == 0xf)
+        {
+            flashDensity = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE;
+        }
+        else
+        {
+            flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10;
+        }
 
-    /* fill out a few of the structure members */
-    config->PFlashBlockBase = PFLASH_BLOCK_BASE;
-    config->PFlashTotalSize = flashDensity;
-    config->PFlashBlockCount = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT;
-    config->PFlashSectorSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE;
+        /* fill out a few of the structure members */
+        config->PFlashBlockBase = FSL_FEATURE_FLASH_PFLASH_START_ADDRESS;
+        config->PFlashTotalSize = flashDensity;
+        config->PFlashBlockCount = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT;
+        config->PFlashSectorSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE;
+    }
 
+    {
 #if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL
-    config->PFlashAccessSegmentSize = kFLASH_accessSegmentBase << FTFx->FACSS;
-    config->PFlashAccessSegmentCount = FTFx->FACSN;
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER
+        if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash)
+        {
+            config->PFlashAccessSegmentSize = kFLASH_AccessSegmentBase << FTFx->FACSSS;
+            config->PFlashAccessSegmentCount = FTFx->FACSNS;
+        }
+        else
+#endif
+        {
+            config->PFlashAccessSegmentSize = kFLASH_AccessSegmentBase << FTFx->FACSS;
+            config->PFlashAccessSegmentCount = FTFx->FACSN;
+        }
 #else
-    config->PFlashAccessSegmentSize = 0;
-    config->PFlashAccessSegmentCount = 0;
+        config->PFlashAccessSegmentSize = 0;
+        config->PFlashAccessSegmentCount = 0;
 #endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
+    }
 
     config->PFlashCallback = NULL;
 
@@ -418,7 +724,7 @@ status_t FLASH_Init(flash_config_t *config)
     {
         s_flashExecuteInRamFunctionInfo.activeFunctionCount = 0;
         s_flashExecuteInRamFunctionInfo.flashRunCommand = s_flashRunCommand;
-        s_flashExecuteInRamFunctionInfo.flashCacheClearCommand = s_flashCacheClearCommand;
+        s_flashExecuteInRamFunctionInfo.flashCommonBitOperation = s_flashCommonBitOperation;
         config->flashExecuteInRamFunctionInfo = &s_flashExecuteInRamFunctionInfo.activeFunctionCount;
         FLASH_PrepareExecuteInRamFunctions(config);
     }
@@ -467,8 +773,8 @@ status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config)
     flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo;
 
     copy_flash_run_command(flashExecuteInRamFunctionInfo->flashRunCommand);
-    copy_flash_cache_clear_command(flashExecuteInRamFunctionInfo->flashCacheClearCommand);
-    flashExecuteInRamFunctionInfo->activeFunctionCount = kFLASH_executeInRamFunctionTotalNum;
+    copy_flash_common_bit_operation(flashExecuteInRamFunctionInfo->flashCommonBitOperation);
+    flashExecuteInRamFunctionInfo->activeFunctionCount = kFLASH_ExecuteInRamFunctionTotalNum;
 
     return kStatus_FLASH_Success;
 }
@@ -493,6 +799,8 @@ status_t FLASH_EraseAll(flash_config_t *config, uint32_t key)
         return returnCode;
     }
 
+    flash_cache_clear_process(config, kFLASH_CacheClearProcessPre);
+
     /* calling flash command sequence function to execute the command */
     returnCode = flash_command_sequence(config);
 
@@ -513,22 +821,29 @@ status_t FLASH_EraseAll(flash_config_t *config, uint32_t key)
 status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key)
 {
     uint32_t sectorSize;
-    flash_operation_config_t flashInfo;
+    flash_operation_config_t flashOperationInfo;
     uint32_t endAddress;      /* storing end address */
     uint32_t numberOfSectors; /* number of sectors calculated by endAddress */
     status_t returnCode;
 
-    flash_get_matched_operation_info(config, start, &flashInfo);
+    flash_get_matched_operation_info(config, start, &flashOperationInfo);
 
     /* Check the supplied address range. */
-    returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectorCmdAddressAligment);
+    returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectorCmdAddressAligment);
+    if (returnCode)
+    {
+        return returnCode;
+    }
+
+    /* Validate the user key */
+    returnCode = flash_check_user_key(key);
     if (returnCode)
     {
         return returnCode;
     }
 
-    start = flashInfo.convertedAddress;
-    sectorSize = flashInfo.activeSectorSize;
+    start = flashOperationInfo.convertedAddress;
+    sectorSize = flashOperationInfo.activeSectorSize;
 
     /* calculating Flash end address */
     endAddress = start + lengthInBytes - 1;
@@ -541,6 +856,8 @@ status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBy
         endAddress = numberOfSectors * sectorSize - 1;
     }
 
+    flash_cache_clear_process(config, kFLASH_CacheClearProcessPre);
+
     /* the start address will increment to the next sector address
      * until it reaches the endAdddress */
     while (start <= endAddress)
@@ -548,13 +865,6 @@ status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBy
         /* preparing passing parameter to erase a flash block */
         kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_SECTOR, start);
 
-        /* Validate the user key */
-        returnCode = flash_check_user_key(key);
-        if (returnCode)
-        {
-            return returnCode;
-        }
-
         /* calling flash command sequence function to execute the command */
         returnCode = flash_command_sequence(config);
 
@@ -601,6 +911,8 @@ status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key)
         return returnCode;
     }
 
+    flash_cache_clear_process(config, kFLASH_CacheClearProcessPre);
+
     /* calling flash command sequence function to execute the command */
     returnCode = flash_command_sequence(config);
 
@@ -639,6 +951,8 @@ status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key)
         return returnCode;
     }
 
+    flash_cache_clear_process(config, kFLASH_CacheClearProcessPre);
+
     /* calling flash command sequence function to execute the command */
     returnCode = flash_command_sequence(config);
 
@@ -650,33 +964,35 @@ status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key)
 status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes)
 {
     status_t returnCode;
-    flash_operation_config_t flashInfo;
+    flash_operation_config_t flashOperationInfo;
 
     if (src == NULL)
     {
         return kStatus_FLASH_InvalidArgument;
     }
 
-    flash_get_matched_operation_info(config, start, &flashInfo);
+    flash_get_matched_operation_info(config, start, &flashOperationInfo);
 
     /* Check the supplied address range. */
-    returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.blockWriteUnitSize);
+    returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.blockWriteUnitSize);
     if (returnCode)
     {
         return returnCode;
     }
 
-    start = flashInfo.convertedAddress;
+    start = flashOperationInfo.convertedAddress;
+
+    flash_cache_clear_process(config, kFLASH_CacheClearProcessPre);
 
     while (lengthInBytes > 0)
     {
         /* preparing passing parameter to program the flash block */
         kFCCOBx[1] = *src++;
-        if (4 == flashInfo.blockWriteUnitSize)
+        if (4 == flashOperationInfo.blockWriteUnitSize)
         {
             kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_LONGWORD, start);
         }
-        else if (8 == flashInfo.blockWriteUnitSize)
+        else if (8 == flashOperationInfo.blockWriteUnitSize)
         {
             kFCCOBx[2] = *src++;
             kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_PHRASE, start);
@@ -702,10 +1018,10 @@ status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, ui
         else
         {
             /* update start address for next iteration */
-            start += flashInfo.blockWriteUnitSize;
+            start += flashOperationInfo.blockWriteUnitSize;
 
             /* update lengthInBytes for next iteration */
-            lengthInBytes -= flashInfo.blockWriteUnitSize;
+            lengthInBytes -= flashOperationInfo.blockWriteUnitSize;
         }
     }
 
@@ -742,6 +1058,8 @@ status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint32_t *src
     }
 #endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */
 
+    flash_cache_clear_process(config, kFLASH_CacheClearProcessPre);
+
     /* calling flash command sequence function to execute the command */
     returnCode = flash_command_sequence(config);
 
@@ -755,7 +1073,7 @@ status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *
 {
     status_t returnCode;
     uint32_t sectorSize;
-    flash_operation_config_t flashInfo;
+    flash_operation_config_t flashOperationInfo;
 #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
     bool needSwitchFlexRamMode = false;
 #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
@@ -765,17 +1083,17 @@ status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *
         return kStatus_FLASH_InvalidArgument;
     }
 
-    flash_get_matched_operation_info(config, start, &flashInfo);
+    flash_get_matched_operation_info(config, start, &flashOperationInfo);
 
     /* Check the supplied address range. */
-    returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectionCmdAddressAligment);
+    returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectionCmdAddressAligment);
     if (returnCode)
     {
         return returnCode;
     }
 
-    start = flashInfo.convertedAddress;
-    sectorSize = flashInfo.activeSectorSize;
+    start = flashOperationInfo.convertedAddress;
+    sectorSize = flashOperationInfo.activeSectorSize;
 
 #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
     /* Switch function of FlexRAM if needed */
@@ -783,7 +1101,7 @@ status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *
     {
         needSwitchFlexRamMode = true;
 
-        returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableAsRam);
+        returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableAsRam);
         if (returnCode != kStatus_FLASH_Success)
         {
             return kStatus_FLASH_SetFlexramAsRamError;
@@ -791,6 +1109,8 @@ status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *
     }
 #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
 
+    flash_cache_clear_process(config, kFLASH_CacheClearProcessPre);
+
     while (lengthInBytes > 0)
     {
         /* Make sure the write operation doesn't span two sectors */
@@ -819,9 +1139,9 @@ status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *
             uint32_t programSizeOfCurrentPass;
             uint32_t numberOfPhases;
 
-            if (lengthTobeProgrammedOfCurrentSector > kFLASH_accelerationRamSize)
+            if (lengthTobeProgrammedOfCurrentSector > kFLASH_AccelerationRamSize)
             {
-                programSizeOfCurrentPass = kFLASH_accelerationRamSize;
+                programSizeOfCurrentPass = kFLASH_AccelerationRamSize;
             }
             else
             {
@@ -833,7 +1153,7 @@ status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *
             /* Set start address of the data to be programmed */
             kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_SECTION, start + currentOffset);
             /* Set program size in terms of FEATURE_FLASH_SECTION_CMD_ADDRESS_ALIGMENT */
-            numberOfPhases = programSizeOfCurrentPass / flashInfo.sectionCmdAddressAligment;
+            numberOfPhases = programSizeOfCurrentPass / flashOperationInfo.sectionCmdAddressAligment;
 
             kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_2(numberOfPhases, 0xFFFFU);
 
@@ -867,7 +1187,7 @@ status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *
     /* Restore function of FlexRAM if needed. */
     if (needSwitchFlexRamMode)
     {
-        returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableForEeprom);
+        returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableForEeprom);
         if (returnCode != kStatus_FLASH_Success)
         {
             return kStatus_FLASH_RecoverFlexramAsEepromError;
@@ -904,7 +1224,7 @@ status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src,
     {
         needSwitchFlexRamMode = true;
 
-        returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableForEeprom);
+        returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableForEeprom);
         if (returnCode != kStatus_FLASH_Success)
         {
             return kStatus_FLASH_SetFlexramAsEepromError;
@@ -950,7 +1270,7 @@ status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src,
     /* Switch function of FlexRAM if needed */
     if (needSwitchFlexRamMode)
     {
-        returnCode = FLASH_SetFlexramFunction(config, kFLASH_flexramFunctionOptionAvailableAsRam);
+        returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableAsRam);
         if (returnCode != kStatus_FLASH_Success)
         {
             return kStatus_FLASH_RecoverFlexramAsRamError;
@@ -966,17 +1286,18 @@ status_t FLASH_ReadResource(
     flash_config_t *config, uint32_t start, uint32_t *dst, uint32_t lengthInBytes, flash_read_resource_option_t option)
 {
     status_t returnCode;
-    flash_operation_config_t flashInfo;
+    flash_operation_config_t flashOperationInfo;
 
     if ((config == NULL) || (dst == NULL))
     {
         return kStatus_FLASH_InvalidArgument;
     }
 
-    flash_get_matched_operation_info(config, start, &flashInfo);
+    flash_get_matched_operation_info(config, start, &flashOperationInfo);
 
     /* Check the supplied address range. */
-    returnCode = flash_check_resource_range(start, lengthInBytes, flashInfo.resourceCmdAddressAligment, option);
+    returnCode =
+        flash_check_resource_range(start, lengthInBytes, flashOperationInfo.resourceCmdAddressAligment, option);
     if (returnCode != kStatus_FLASH_Success)
     {
         return returnCode;
@@ -986,11 +1307,11 @@ status_t FLASH_ReadResource(
     {
         /* preparing passing parameter */
         kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_READ_RESOURCE, start);
-        if (flashInfo.resourceCmdAddressAligment == 4)
+        if (flashOperationInfo.resourceCmdAddressAligment == 4)
         {
             kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU);
         }
-        else if (flashInfo.resourceCmdAddressAligment == 8)
+        else if (flashOperationInfo.resourceCmdAddressAligment == 8)
         {
             kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU);
         }
@@ -1008,14 +1329,14 @@ status_t FLASH_ReadResource(
 
         /* fetch data */
         *dst++ = kFCCOBx[1];
-        if (flashInfo.resourceCmdAddressAligment == 8)
+        if (flashOperationInfo.resourceCmdAddressAligment == 8)
         {
             *dst++ = kFCCOBx[2];
         }
         /* update start address for next iteration */
-        start += flashInfo.resourceCmdAddressAligment;
+        start += flashOperationInfo.resourceCmdAddressAligment;
         /* update lengthInBytes for next iteration */
-        lengthInBytes -= flashInfo.resourceCmdAddressAligment;
+        lengthInBytes -= flashOperationInfo.resourceCmdAddressAligment;
     }
 
     return (returnCode);
@@ -1075,7 +1396,7 @@ status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *
     if (FLASH_SECURITY_STATE_UNSECURED == (registerValue & FTFx_FSEC_SEC_MASK))
     {
         /* Flash in unsecured state */
-        *state = kFLASH_securityStateNotSecure;
+        *state = kFLASH_SecurityStateNotSecure;
     }
     else
     {
@@ -1084,12 +1405,12 @@ status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *
         if (FLASH_SECURITY_STATE_KEYEN == (registerValue & FTFx_FSEC_KEYEN_MASK))
         {
             /* Backdoor key security enabled */
-            *state = kFLASH_securityStateBackdoorEnabled;
+            *state = kFLASH_SecurityStateBackdoorEnabled;
         }
         else
         {
             /* Backdoor key security disabled */
-            *state = kFLASH_securityStateBackdoorDisabled;
+            *state = kFLASH_SecurityStateBackdoorDisabled;
         }
     }
 
@@ -1146,22 +1467,22 @@ status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t leng
 {
     /* Check arguments. */
     uint32_t blockSize;
-    flash_operation_config_t flashInfo;
+    flash_operation_config_t flashOperationInfo;
     uint32_t nextBlockStartAddress;
     uint32_t remainingBytes;
     status_t returnCode;
 
-    flash_get_matched_operation_info(config, start, &flashInfo);
+    flash_get_matched_operation_info(config, start, &flashOperationInfo);
 
-    returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.sectionCmdAddressAligment);
+    returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectionCmdAddressAligment);
     if (returnCode)
     {
         return returnCode;
     }
 
-    flash_get_matched_operation_info(config, start, &flashInfo);
-    start = flashInfo.convertedAddress;
-    blockSize = flashInfo.activeBlockSize;
+    flash_get_matched_operation_info(config, start, &flashOperationInfo);
+    start = flashOperationInfo.convertedAddress;
+    blockSize = flashOperationInfo.activeBlockSize;
 
     nextBlockStartAddress = ALIGN_UP(start, blockSize);
     if (nextBlockStartAddress == start)
@@ -1180,7 +1501,7 @@ status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t leng
             verifyLength = remainingBytes;
         }
 
-        numberOfPhrases = verifyLength / flashInfo.sectionCmdAddressAligment;
+        numberOfPhrases = verifyLength / flashOperationInfo.sectionCmdAddressAligment;
 
         /* Fill in verify section command parameters. */
         kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_VERIFY_SECTION, start);
@@ -1210,22 +1531,22 @@ status_t FLASH_VerifyProgram(flash_config_t *config,
                              uint32_t *failedData)
 {
     status_t returnCode;
-    flash_operation_config_t flashInfo;
+    flash_operation_config_t flashOperationInfo;
 
     if (expectedData == NULL)
     {
         return kStatus_FLASH_InvalidArgument;
     }
 
-    flash_get_matched_operation_info(config, start, &flashInfo);
+    flash_get_matched_operation_info(config, start, &flashOperationInfo);
 
-    returnCode = flash_check_range(config, start, lengthInBytes, flashInfo.checkCmdAddressAligment);
+    returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.checkCmdAddressAligment);
     if (returnCode)
     {
         return returnCode;
     }
 
-    start = flashInfo.convertedAddress;
+    start = flashOperationInfo.convertedAddress;
 
     while (lengthInBytes)
     {
@@ -1251,9 +1572,9 @@ status_t FLASH_VerifyProgram(flash_config_t *config,
             break;
         }
 
-        lengthInBytes -= flashInfo.checkCmdAddressAligment;
-        expectedData += flashInfo.checkCmdAddressAligment / sizeof(*expectedData);
-        start += flashInfo.checkCmdAddressAligment;
+        lengthInBytes -= flashOperationInfo.checkCmdAddressAligment;
+        expectedData += flashOperationInfo.checkCmdAddressAligment / sizeof(*expectedData);
+        start += flashOperationInfo.checkCmdAddressAligment;
     }
 
     return (returnCode);
@@ -1279,19 +1600,21 @@ status_t FLASH_IsProtected(flash_config_t *config,
                            flash_protection_state_t *protection_state)
 {
     uint32_t endAddress;           /* end address for protection check */
-    uint32_t protectionRegionSize; /* size of flash protection region */
     uint32_t regionCheckedCounter; /* increments each time the flash address was checked for
                                     * protection status */
     uint32_t regionCounter;        /* incrementing variable used to increment through the flash
                                     * protection regions */
     uint32_t protectStatusCounter; /* increments each time a flash region was detected as protected */
 
-    uint8_t flashRegionProtectStatus[FSL_FEATURE_FTFx_REGION_COUNT]; /* array of the protection status for each
+    uint8_t flashRegionProtectStatus[FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT]; /* array of the protection
+                                                                      * status for each
                                                                       * protection region */
-    uint32_t flashRegionAddress[FSL_FEATURE_FTFx_REGION_COUNT + 1];  /* array of the start addresses for each flash
-                                                                      * protection region. Note this is REGION_COUNT+1
-                                                                      * due to requiring the next start address after
-                                                                      * the end of flash for loop-check purposes below */
+    uint32_t flashRegionAddress[FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT +
+                                1];                /* array of the start addresses for each flash
+                                 * protection region. Note this is REGION_COUNT+1
+                                 * due to requiring the next start address after
+                                 * the end of flash for loop-check purposes below */
+    flash_protection_config_t flashProtectionInfo; /* flash protection information */
     status_t returnCode;
 
     if (protection_state == NULL)
@@ -1306,28 +1629,24 @@ status_t FLASH_IsProtected(flash_config_t *config,
         return returnCode;
     }
 
-    /* calculating Flash end address */
-    endAddress = start + lengthInBytes;
-
-    /* Calculate the size of the flash protection region
-     * If the flash density is > 32KB, then protection region is 1/32 of total flash density
-     * Else if flash density is < 32KB, then flash protection region is set to 1KB */
-    if (config->PFlashTotalSize > 32 * 1024)
-    {
-        protectionRegionSize = (config->PFlashTotalSize) / FSL_FEATURE_FTFx_REGION_COUNT;
-    }
-    else
+    /* Get necessary flash protection information. */
+    returnCode = flash_get_protection_info(config, &flashProtectionInfo);
+    if (returnCode)
     {
-        protectionRegionSize = 1024;
+        return returnCode;
     }
 
+    /* calculating Flash end address */
+    endAddress = start + lengthInBytes;
+
     /* populate the flashRegionAddress array with the start address of each flash region */
     regionCounter = 0; /* make sure regionCounter is initialized to 0 first */
 
     /* populate up to 33rd element of array, this is the next address after end of flash array */
-    while (regionCounter <= FSL_FEATURE_FTFx_REGION_COUNT)
+    while (regionCounter <= flashProtectionInfo.regionCount)
     {
-        flashRegionAddress[regionCounter] = config->PFlashBlockBase + protectionRegionSize * regionCounter;
+        flashRegionAddress[regionCounter] =
+            flashProtectionInfo.regionBase + flashProtectionInfo.regionSize * regionCounter;
         regionCounter++;
     }
 
@@ -1341,24 +1660,80 @@ status_t FLASH_IsProtected(flash_config_t *config,
      * regionCounter is used to determine which FPROT[3:0] register to check for protection status
      * Note: FPROT=1 means NOT protected, FPROT=0 means protected */
     regionCounter = 0; /* make sure regionCounter is initialized to 0 first */
-    while (regionCounter < FSL_FEATURE_FTFx_REGION_COUNT)
+    while (regionCounter < flashProtectionInfo.regionCount)
     {
-        if (regionCounter < 8)
-        {
-            flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT3) >> regionCounter) & (0x01u);
-        }
-        else if ((regionCounter >= 8) && (regionCounter < 16))
-        {
-            flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT2) >> (regionCounter - 8)) & (0x01u);
-        }
-        else if ((regionCounter >= 16) && (regionCounter < 24))
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER
+        if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash)
         {
-            flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT1) >> (regionCounter - 16)) & (0x01u);
+            if (regionCounter < 8)
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTSL_REG >> regionCounter) & (0x01u);
+            }
+            else if ((regionCounter >= 8) && (regionCounter < 16))
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTSH_REG >> (regionCounter - 8)) & (0x01u);
+            }
+            else
+            {
+                break;
+            }
         }
         else
+#endif
         {
-            flashRegionProtectStatus[regionCounter] = ((FTFx->FPROT0) >> (regionCounter - 24)) & (0x01u);
+            /* Note: So far protection region count may be 16/20/24/32/64 */
+            if (regionCounter < 8)
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL3_REG >> regionCounter) & (0x01u);
+            }
+            else if ((regionCounter >= 8) && (regionCounter < 16))
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL2_REG >> (regionCounter - 8)) & (0x01u);
+            }
+#if defined(FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT) && (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT > 16)
+#if (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT == 20)
+            else if ((regionCounter >= 16) && (regionCounter < 20))
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL1_REG >> (regionCounter - 16)) & (0x01u);
+            }
+#else
+            else if ((regionCounter >= 16) && (regionCounter < 24))
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL1_REG >> (regionCounter - 16)) & (0x01u);
+            }
+#endif /* (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT == 20) */
+#endif
+#if defined(FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT) && (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT > 24)
+            else if ((regionCounter >= 24) && (regionCounter < 32))
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL0_REG >> (regionCounter - 24)) & (0x01u);
+            }
+#endif
+#if defined(FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT) && \
+    (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT == 64)
+            else if (regionCounter < 40)
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH3_REG >> (regionCounter - 32)) & (0x01u);
+            }
+            else if (regionCounter < 48)
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH2_REG >> (regionCounter - 40)) & (0x01u);
+            }
+            else if (regionCounter < 56)
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH1_REG >> (regionCounter - 48)) & (0x01u);
+            }
+            else if (regionCounter < 64)
+            {
+                flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH0_REG >> (regionCounter - 56)) & (0x01u);
+            }
+#endif
+            else
+            {
+                break;
+            }
         }
+
         regionCounter++;
     }
 
@@ -1386,7 +1761,7 @@ status_t FLASH_IsProtected(flash_config_t *config,
                 /* increment protectStatusCounter to indicate this region is protected */
                 protectStatusCounter++;
             }
-            start += protectionRegionSize; /* increment to an address within the next region */
+            start += flashProtectionInfo.regionSize; /* increment to an address within the next region */
         }
         regionCounter++; /* increment regionCounter to check for the next flash protection region */
     }
@@ -1394,18 +1769,18 @@ status_t FLASH_IsProtected(flash_config_t *config,
     /* if protectStatusCounter == 0, then no region of the desired flash region is protected */
     if (protectStatusCounter == 0)
     {
-        *protection_state = kFLASH_protectionStateUnprotected;
+        *protection_state = kFLASH_ProtectionStateUnprotected;
     }
     /* if protectStatusCounter == regionCheckedCounter, then each region checked was protected */
     else if (protectStatusCounter == regionCheckedCounter)
     {
-        *protection_state = kFLASH_protectionStateProtected;
+        *protection_state = kFLASH_ProtectionStateProtected;
     }
     /* if protectStatusCounter != regionCheckedCounter, then protection status is mixed
      * In other words, some regions are protected while others are unprotected */
     else
     {
-        *protection_state = kFLASH_protectionStateMixed;
+        *protection_state = kFLASH_ProtectionStateMixed;
     }
 
     return (returnCode);
@@ -1416,6 +1791,9 @@ status_t FLASH_IsExecuteOnly(flash_config_t *config,
                              uint32_t lengthInBytes,
                              flash_execute_only_access_state_t *access_state)
 {
+#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL
+    flash_access_config_t flashAccessInfo; /* flash Execute-Only information */
+#endif                                     /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
     status_t returnCode;
 
     if (access_state == NULL)
@@ -1431,6 +1809,13 @@ status_t FLASH_IsExecuteOnly(flash_config_t *config,
     }
 
 #if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL
+    /* Get necessary flash Execute-Only information. */
+    returnCode = flash_get_access_info(config, &flashAccessInfo);
+    if (returnCode)
+    {
+        return returnCode;
+    }
+
     {
         uint32_t executeOnlySegmentCounter = 0;
 
@@ -1438,31 +1823,56 @@ status_t FLASH_IsExecuteOnly(flash_config_t *config,
         uint32_t endAddress = start + lengthInBytes;
 
         /* Aligning start address and end address */
-        uint32_t alignedStartAddress = ALIGN_DOWN(start, config->PFlashAccessSegmentSize);
-        uint32_t alignedEndAddress = ALIGN_UP(endAddress, config->PFlashAccessSegmentSize);
+        uint32_t alignedStartAddress = ALIGN_DOWN(start, flashAccessInfo.SegmentSize);
+        uint32_t alignedEndAddress = ALIGN_UP(endAddress, flashAccessInfo.SegmentSize);
 
         uint32_t segmentIndex = 0;
         uint32_t maxSupportedExecuteOnlySegmentCount =
-            (alignedEndAddress - alignedStartAddress) / config->PFlashAccessSegmentSize;
+            (alignedEndAddress - alignedStartAddress) / flashAccessInfo.SegmentSize;
 
         while (start < endAddress)
         {
             uint32_t xacc;
 
-            segmentIndex = start / config->PFlashAccessSegmentSize;
+            segmentIndex = (start - flashAccessInfo.SegmentBase) / flashAccessInfo.SegmentSize;
 
-            if (segmentIndex < 32)
-            {
-                xacc = *(const volatile uint32_t *)&FTFx->XACCL3;
-            }
-            else if (segmentIndex < config->PFlashAccessSegmentCount)
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER
+            if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash)
             {
-                xacc = *(const volatile uint32_t *)&FTFx->XACCH3;
-                segmentIndex -= 32;
+                /* For secondary flash, The two XACCS registers allow up to 16 restricted segments of equal memory size.
+                 */
+                if (segmentIndex < 8)
+                {
+                    xacc = *(const volatile uint8_t *)&FTFx_XACCSL_REG;
+                }
+                else if (segmentIndex < flashAccessInfo.SegmentCount)
+                {
+                    xacc = *(const volatile uint8_t *)&FTFx_XACCSH_REG;
+                    segmentIndex -= 8;
+                }
+                else
+                {
+                    break;
+                }
             }
             else
+#endif
             {
-                break;
+                /* For primary flash, The eight XACC registers allow up to 64 restricted segments of equal memory size.
+                 */
+                if (segmentIndex < 32)
+                {
+                    xacc = *(const volatile uint32_t *)&FTFx_XACCL3_REG;
+                }
+                else if (segmentIndex < flashAccessInfo.SegmentCount)
+                {
+                    xacc = *(const volatile uint32_t *)&FTFx_XACCH3_REG;
+                    segmentIndex -= 32;
+                }
+                else
+                {
+                    break;
+                }
             }
 
             /* Determine if this address range is in a execute-only protection flash segment. */
@@ -1471,24 +1881,24 @@ status_t FLASH_IsExecuteOnly(flash_config_t *config,
                 executeOnlySegmentCounter++;
             }
 
-            start += config->PFlashAccessSegmentSize;
+            start += flashAccessInfo.SegmentSize;
         }
 
         if (executeOnlySegmentCounter < 1u)
         {
-            *access_state = kFLASH_accessStateUnLimited;
+            *access_state = kFLASH_AccessStateUnLimited;
         }
         else if (executeOnlySegmentCounter < maxSupportedExecuteOnlySegmentCount)
         {
-            *access_state = kFLASH_accessStateMixed;
+            *access_state = kFLASH_AccessStateMixed;
         }
         else
         {
-            *access_state = kFLASH_accessStateExecuteOnly;
+            *access_state = kFLASH_AccessStateExecuteOnly;
         }
     }
 #else
-    *access_state = kFLASH_accessStateUnLimited;
+    *access_state = kFLASH_AccessStateUnLimited;
 #endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
 
     return (returnCode);
@@ -1503,27 +1913,27 @@ status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichPro
 
     switch (whichProperty)
     {
-        case kFLASH_propertyPflashSectorSize:
+        case kFLASH_PropertyPflashSectorSize:
             *value = config->PFlashSectorSize;
             break;
 
-        case kFLASH_propertyPflashTotalSize:
+        case kFLASH_PropertyPflashTotalSize:
             *value = config->PFlashTotalSize;
             break;
 
-        case kFLASH_propertyPflashBlockSize:
+        case kFLASH_PropertyPflashBlockSize:
             *value = config->PFlashTotalSize / FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT;
             break;
 
-        case kFLASH_propertyPflashBlockCount:
-            *value = config->PFlashBlockCount;
+        case kFLASH_PropertyPflashBlockCount:
+            *value = (uint32_t)config->PFlashBlockCount;
             break;
 
-        case kFLASH_propertyPflashBlockBaseAddr:
+        case kFLASH_PropertyPflashBlockBaseAddr:
             *value = config->PFlashBlockBase;
             break;
 
-        case kFLASH_propertyPflashFacSupport:
+        case kFLASH_PropertyPflashFacSupport:
 #if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL)
             *value = FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL;
 #else
@@ -1531,31 +1941,39 @@ status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichPro
 #endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
             break;
 
-        case kFLASH_propertyPflashAccessSegmentSize:
+        case kFLASH_PropertyPflashAccessSegmentSize:
             *value = config->PFlashAccessSegmentSize;
             break;
 
-        case kFLASH_propertyPflashAccessSegmentCount:
+        case kFLASH_PropertyPflashAccessSegmentCount:
             *value = config->PFlashAccessSegmentCount;
             break;
 
+        case kFLASH_PropertyFlexRamBlockBaseAddr:
+            *value = config->FlexRAMBlockBase;
+            break;
+
+        case kFLASH_PropertyFlexRamTotalSize:
+            *value = config->FlexRAMTotalSize;
+            break;
+
 #if FLASH_SSD_IS_FLEXNVM_ENABLED
-        case kFLASH_propertyDflashSectorSize:
+        case kFLASH_PropertyDflashSectorSize:
             *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE;
             break;
-        case kFLASH_propertyDflashTotalSize:
+        case kFLASH_PropertyDflashTotalSize:
             *value = config->DFlashTotalSize;
             break;
-        case kFLASH_propertyDflashBlockSize:
+        case kFLASH_PropertyDflashBlockSize:
             *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE;
             break;
-        case kFLASH_propertyDflashBlockCount:
+        case kFLASH_PropertyDflashBlockCount:
             *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT;
             break;
-        case kFLASH_propertyDflashBlockBaseAddr:
+        case kFLASH_PropertyDflashBlockBaseAddr:
             *value = config->DFlashBlockBase;
             break;
-        case kFLASH_propertyEepromTotalSize:
+        case kFLASH_PropertyEepromTotalSize:
             *value = config->EEpromTotalSize;
             break;
 #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
@@ -1567,6 +1985,65 @@ status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichPro
     return kStatus_FLASH_Success;
 }
 
+status_t FLASH_SetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t value)
+{
+    status_t status = kStatus_FLASH_Success;
+
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    switch (whichProperty)
+    {
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED
+        case kFLASH_PropertyFlashMemoryIndex:
+            if ((value != (uint32_t)kFLASH_MemoryIndexPrimaryFlash) &&
+                (value != (uint32_t)kFLASH_MemoryIndexSecondaryFlash))
+            {
+                return kStatus_FLASH_InvalidPropertyValue;
+            }
+            config->FlashMemoryIndex = (uint8_t)value;
+            break;
+#endif /* FLASH_SSD_IS_SECONDARY_FLASH_ENABLED */
+
+        case kFLASH_PropertyFlashCacheControllerIndex:
+            if ((value != (uint32_t)kFLASH_CacheControllerIndexForCore0) &&
+                (value != (uint32_t)kFLASH_CacheControllerIndexForCore1))
+            {
+                return kStatus_FLASH_InvalidPropertyValue;
+            }
+            config->FlashCacheControllerIndex = (uint8_t)value;
+            break;
+
+        case kFLASH_PropertyPflashSectorSize:
+        case kFLASH_PropertyPflashTotalSize:
+        case kFLASH_PropertyPflashBlockSize:
+        case kFLASH_PropertyPflashBlockCount:
+        case kFLASH_PropertyPflashBlockBaseAddr:
+        case kFLASH_PropertyPflashFacSupport:
+        case kFLASH_PropertyPflashAccessSegmentSize:
+        case kFLASH_PropertyPflashAccessSegmentCount:
+        case kFLASH_PropertyFlexRamBlockBaseAddr:
+        case kFLASH_PropertyFlexRamTotalSize:
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+        case kFLASH_PropertyDflashSectorSize:
+        case kFLASH_PropertyDflashTotalSize:
+        case kFLASH_PropertyDflashBlockSize:
+        case kFLASH_PropertyDflashBlockCount:
+        case kFLASH_PropertyDflashBlockBaseAddr:
+        case kFLASH_PropertyEepromTotalSize:
+#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
+            status = kStatus_FLASH_ReadOnlyProperty;
+            break;
+        default: /* catch inputs that are not recognized */
+            status = kStatus_FLASH_UnknownProperty;
+            break;
+    }
+
+    return status;
+}
+
 #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
 status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function_option_t option)
 {
@@ -1611,7 +2088,7 @@ status_t FLASH_SwapControl(flash_config_t *config,
 
     /* Make sure address provided is in the lower half of Program flash but not in the Flash Configuration Field */
     if ((address >= (config->PFlashTotalSize / 2)) ||
-        ((address >= kFLASH_configAreaStart) && (address <= kFLASH_configAreaEnd)))
+        ((address >= kFLASH_ConfigAreaStart) && (address <= kFLASH_ConfigAreaEnd)))
     {
         return kStatus_FLASH_SwapIndicatorAddressError;
     }
@@ -1628,9 +2105,9 @@ status_t FLASH_SwapControl(flash_config_t *config,
 
     returnCode = flash_command_sequence(config);
 
-    returnInfo->flashSwapState = (flash_swap_state_t)FTFx->FCCOB5;
-    returnInfo->currentSwapBlockStatus = (flash_swap_block_status_t)FTFx->FCCOB6;
-    returnInfo->nextSwapBlockStatus = (flash_swap_block_status_t)FTFx->FCCOB7;
+    returnInfo->flashSwapState = (flash_swap_state_t)FTFx_FCCOB5_REG;
+    returnInfo->currentSwapBlockStatus = (flash_swap_block_status_t)FTFx_FCCOB6_REG;
+    returnInfo->nextSwapBlockStatus = (flash_swap_block_status_t)FTFx_FCCOB7_REG;
 
     return returnCode;
 }
@@ -1646,23 +2123,23 @@ status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_functio
 
     do
     {
-        returnCode = FLASH_SwapControl(config, address, kFLASH_swapControlOptionReportStatus, &returnInfo);
+        returnCode = FLASH_SwapControl(config, address, kFLASH_SwapControlOptionReportStatus, &returnInfo);
         if (returnCode != kStatus_FLASH_Success)
         {
             return returnCode;
         }
 
-        if (kFLASH_swapFunctionOptionDisable == option)
+        if (kFLASH_SwapFunctionOptionDisable == option)
         {
-            if (returnInfo.flashSwapState == kFLASH_swapStateDisabled)
+            if (returnInfo.flashSwapState == kFLASH_SwapStateDisabled)
             {
                 return kStatus_FLASH_Success;
             }
-            else if (returnInfo.flashSwapState == kFLASH_swapStateUninitialized)
+            else if (returnInfo.flashSwapState == kFLASH_SwapStateUninitialized)
             {
                 /* The swap system changed to the DISABLED state with Program flash block 0
                  * located at relative flash address 0x0_0000 */
-                returnCode = FLASH_SwapControl(config, address, kFLASH_swapControlOptionDisableSystem, &returnInfo);
+                returnCode = FLASH_SwapControl(config, address, kFLASH_SwapControlOptionDisableSystem, &returnInfo);
             }
             else
             {
@@ -1679,12 +2156,12 @@ status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_functio
              *    Complete. */
             switch (returnInfo.flashSwapState)
             {
-                case kFLASH_swapStateUninitialized:
+                case kFLASH_SwapStateUninitialized:
                     /* If current swap mode is Uninitialized, Initialize Swap to Initialized/READY state. */
                     returnCode =
-                        FLASH_SwapControl(config, address, kFLASH_swapControlOptionIntializeSystem, &returnInfo);
+                        FLASH_SwapControl(config, address, kFLASH_SwapControlOptionIntializeSystem, &returnInfo);
                     break;
-                case kFLASH_swapStateReady:
+                case kFLASH_SwapStateReady:
                     /* Validate whether the address provided to the swap system is matched to
                      * swap indicator address in the IFR */
                     returnCode = flash_validate_swap_indicator_address(config, address);
@@ -1692,23 +2169,23 @@ status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_functio
                     {
                         /* If current swap mode is Initialized/Ready, Initialize Swap to UPDATE state. */
                         returnCode =
-                            FLASH_SwapControl(config, address, kFLASH_swapControlOptionSetInUpdateState, &returnInfo);
+                            FLASH_SwapControl(config, address, kFLASH_SwapControlOptionSetInUpdateState, &returnInfo);
                     }
                     break;
-                case kFLASH_swapStateUpdate:
+                case kFLASH_SwapStateUpdate:
                     /* If current swap mode is Update, Erase indicator sector in non active block
                      * to proceed swap system to update-erased state */
                     returnCode = FLASH_Erase(config, address + (config->PFlashTotalSize >> 1),
-                                             FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT, kFLASH_apiEraseKey);
+                                             FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT, kFLASH_ApiEraseKey);
                     break;
-                case kFLASH_swapStateUpdateErased:
+                case kFLASH_SwapStateUpdateErased:
                     /* If current swap mode is Update or Update-Erased, progress Swap to COMPLETE State */
                     returnCode =
-                        FLASH_SwapControl(config, address, kFLASH_swapControlOptionSetInCompleteState, &returnInfo);
+                        FLASH_SwapControl(config, address, kFLASH_SwapControlOptionSetInCompleteState, &returnInfo);
                     break;
-                case kFLASH_swapStateComplete:
+                case kFLASH_SwapStateComplete:
                     break;
-                case kFLASH_swapStateDisabled:
+                case kFLASH_SwapStateDisabled:
                     /* When swap system is in disabled state, We need to clear swap system back to uninitialized
                      * by issuing EraseAllBlocks command */
                     returnCode = kStatus_FLASH_SwapSystemNotInUninitialized;
@@ -1722,7 +2199,7 @@ status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_functio
         {
             break;
         }
-    } while (!((kFLASH_swapStateComplete == returnInfo.flashSwapState) && (kFLASH_swapFunctionOptionEnable == option)));
+    } while (!((kFLASH_SwapStateComplete == returnInfo.flashSwapState) && (kFLASH_SwapFunctionOptionEnable == option)));
 
     return returnCode;
 }
@@ -1750,6 +2227,8 @@ status_t FLASH_ProgramPartition(flash_config_t *config,
     kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_2_1(FTFx_PROGRAM_PARTITION, 0xFFFFU, option);
     kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_2(eepromDataSizeCode, flexnvmPartitionCode, 0xFFFFU);
 
+    flash_cache_clear_process(config, kFLASH_CacheClearProcessPre);
+
     /* calling flash command sequence function to execute the command */
     returnCode = flash_command_sequence(config);
 
@@ -1766,31 +2245,70 @@ status_t FLASH_ProgramPartition(flash_config_t *config,
 }
 #endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD */
 
-status_t FLASH_PflashSetProtection(flash_config_t *config, uint32_t protectStatus)
+status_t FLASH_PflashSetProtection(flash_config_t *config, pflash_protection_status_t *protectStatus)
 {
     if (config == NULL)
     {
         return kStatus_FLASH_InvalidArgument;
     }
 
-    *kFPROT = protectStatus;
-
-    if (protectStatus != *kFPROT)
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER
+    if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash)
     {
-        return kStatus_FLASH_CommandFailure;
-    }
+        *kFPROTSL = protectStatus->valueLow32b.prots16b.protsl;
+        if (protectStatus->valueLow32b.prots16b.protsl != *kFPROTSL)
+        {
+            return kStatus_FLASH_CommandFailure;
+        }
+
+        *kFPROTSH = protectStatus->valueLow32b.prots16b.protsh;
+        if (protectStatus->valueLow32b.prots16b.protsh != *kFPROTSH)
+        {
+            return kStatus_FLASH_CommandFailure;
+        }
+    }
+    else
+#endif
+    {
+        *kFPROTL = protectStatus->valueLow32b.protl32b;
+        if (protectStatus->valueLow32b.protl32b != *kFPROTL)
+        {
+            return kStatus_FLASH_CommandFailure;
+        }
+
+#if defined(FTFx_FPROT_HIGH_REG)
+        *kFPROTH = protectStatus->valueHigh32b.proth32b;
+        if (protectStatus->valueHigh32b.proth32b != *kFPROTH)
+        {
+            return kStatus_FLASH_CommandFailure;
+        }
+#endif
+    }
 
     return kStatus_FLASH_Success;
 }
 
-status_t FLASH_PflashGetProtection(flash_config_t *config, uint32_t *protectStatus)
+status_t FLASH_PflashGetProtection(flash_config_t *config, pflash_protection_status_t *protectStatus)
 {
     if ((config == NULL) || (protectStatus == NULL))
     {
         return kStatus_FLASH_InvalidArgument;
     }
 
-    *protectStatus = *kFPROT;
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER
+    if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash)
+    {
+        protectStatus->valueLow32b.prots16b.protsl = *kFPROTSL;
+        protectStatus->valueLow32b.prots16b.protsh = *kFPROTSH;
+    }
+    else
+#endif
+    {
+        protectStatus->valueLow32b.protl32b = *kFPROTL;
+#if defined(FTFx_FPROT_HIGH_REG)
+        protectStatus->valueHigh32b.proth32b = *kFPROTH;
+#endif
+    }
 
     return kStatus_FLASH_Success;
 }
@@ -1881,70 +2399,215 @@ status_t FLASH_EepromGetProtection(flash_config_t *config, uint8_t *protectStatu
 }
 #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
 
-#if FLASH_DRIVER_IS_FLASH_RESIDENT
-/*!
- * @brief Run flash command
- *
- * This function should be copied to RAM for execution to make sure that code works
- * properly even flash cache is disabled.
- * It is for flash-resident bootloader only, not technically required for ROM or
- *  flashloader (RAM-resident bootloader).
- */
-void flash_run_command(FTFx_REG_ACCESS_TYPE ftfx_fstat)
+status_t FLASH_PflashSetPrefetchSpeculation(flash_prefetch_speculation_status_t *speculationStatus)
 {
-    /* clear CCIF bit */
-    *ftfx_fstat = FTFx_FSTAT_CCIF_MASK;
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM
+    {
+        FTFx_REG32_ACCESS_TYPE regBase;
+#if defined(MCM)
+        regBase = (FTFx_REG32_ACCESS_TYPE)&MCM->PLACR;
+#elif defined(MCM0)
+        regBase = (FTFx_REG32_ACCESS_TYPE)&MCM0->PLACR;
+#endif
+        if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionDisable)
+        {
+            if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable)
+            {
+                return kStatus_FLASH_InvalidSpeculationOption;
+            }
+            else
+            {
+                *regBase |= MCM_PLACR_DFCS_MASK;
+            }
+        }
+        else
+        {
+            *regBase &= ~MCM_PLACR_DFCS_MASK;
+            if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable)
+            {
+                *regBase |= MCM_PLACR_EFDS_MASK;
+            }
+            else
+            {
+                *regBase &= ~MCM_PLACR_EFDS_MASK;
+            }
+        }
+    }
+#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC
+    {
+        FTFx_REG32_ACCESS_TYPE regBase;
+        uint32_t b0dpeMask, b0ipeMask;
+#if defined(FMC_PFB01CR_B0DPE_MASK)
+        regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR;
+        b0dpeMask = FMC_PFB01CR_B0DPE_MASK;
+        b0ipeMask = FMC_PFB01CR_B0IPE_MASK;
+#elif defined(FMC_PFB0CR_B0DPE_MASK)
+        regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR;
+        b0dpeMask = FMC_PFB0CR_B0DPE_MASK;
+        b0ipeMask = FMC_PFB0CR_B0IPE_MASK;
+#endif
+        if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionEnable)
+        {
+            *regBase |= b0ipeMask;
+        }
+        else
+        {
+            *regBase &= ~b0ipeMask;
+        }
+        if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable)
+        {
+            *regBase |= b0dpeMask;
+        }
+        else
+        {
+            *regBase &= ~b0dpeMask;
+        }
 
-    /* Check CCIF bit of the flash status register, wait till it is set.
-     * IP team indicates that this loop will always complete. */
-    while (!((*ftfx_fstat) & FTFx_FSTAT_CCIF_MASK))
+/* Invalidate Prefetch Speculation Buffer */
+#if defined(FMC_PFB01CR_S_INV_MASK)
+        FMC->PFB01CR |= FMC_PFB01CR_S_INV_MASK;
+#elif defined(FMC_PFB01CR_S_B_INV_MASK)
+        FMC->PFB01CR |= FMC_PFB01CR_S_B_INV_MASK;
+#elif defined(FMC_PFB0CR_S_INV_MASK)
+        FMC->PFB0CR |= FMC_PFB0CR_S_INV_MASK;
+#elif defined(FMC_PFB0CR_S_B_INV_MASK)
+        FMC->PFB0CR |= FMC_PFB0CR_S_B_INV_MASK;
+#endif
+    }
+#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
     {
+        FTFx_REG32_ACCESS_TYPE regBase;
+        uint32_t flashSpeculationMask, dataPrefetchMask;
+        regBase = (FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0];
+        flashSpeculationMask = MSCM_OCMDR_OCMC1_DFCS_MASK;
+        dataPrefetchMask = MSCM_OCMDR_OCMC1_DFDS_MASK;
+
+        if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionDisable)
+        {
+            if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable)
+            {
+                return kStatus_FLASH_InvalidSpeculationOption;
+            }
+            else
+            {
+                *regBase |= flashSpeculationMask;
+            }
+        }
+        else
+        {
+            *regBase &= ~flashSpeculationMask;
+            if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable)
+            {
+                *regBase &= ~dataPrefetchMask;
+            }
+            else
+            {
+                *regBase |= dataPrefetchMask;
+            }
+        }
     }
-}
+#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */
 
-/*!
- * @brief Be used for determining the size of flash_run_command()
- *
- * This function must be defined that lexically follows flash_run_command(),
- * so we can determine the size of flash_run_command() at runtime and not worry
- * about toolchain or code generation differences.
- */
-void flash_run_command_end(void)
-{
+    return kStatus_FLASH_Success;
 }
 
-/*!
- * @brief Copy flash_run_command() to RAM
- *
- * This function copys the memory between flash_run_command() and flash_run_command_end()
- * into the buffer which is also means that copying flash_run_command() to RAM.
- */
-static void copy_flash_run_command(uint8_t *flashRunCommand)
+status_t FLASH_PflashGetPrefetchSpeculation(flash_prefetch_speculation_status_t *speculationStatus)
 {
-    /* Calculate the valid length of flash_run_command() memory.
-     * Set max size(64 bytes) as default function size, in case some compiler allocates
-     * flash_run_command_end ahead of flash_run_command. */
-    uint32_t funcLength = kFLASH_executeInRamFunctionMaxSize;
-    uint32_t flash_run_command_start_addr = (uint32_t)flash_run_command & (~1U);
-    uint32_t flash_run_command_end_addr = (uint32_t)flash_run_command_end & (~1U);
-    if (flash_run_command_end_addr > flash_run_command_start_addr)
-    {
-        funcLength = flash_run_command_end_addr - flash_run_command_start_addr;
+    memset(speculationStatus, 0, sizeof(flash_prefetch_speculation_status_t));
 
-        assert(funcLength <= kFLASH_executeInRamFunctionMaxSize);
+    /* Assuming that all speculation options are enabled. */
+    speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionEnable;
+    speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionEnable;
 
-        /* In case some compiler allocates other function in the middle of flash_run_command
-         * and flash_run_command_end. */
-        if (funcLength > kFLASH_executeInRamFunctionMaxSize)
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM
+    {
+        uint32_t value;
+#if defined(MCM)
+        value = MCM->PLACR;
+#elif defined(MCM0)
+        value = MCM0->PLACR;
+#endif
+        if (value & MCM_PLACR_DFCS_MASK)
         {
-            funcLength = kFLASH_executeInRamFunctionMaxSize;
+            /* Speculation buffer is off. */
+            speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable;
+            speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable;
+        }
+        else
+        {
+            /* Speculation buffer is on for instruction. */
+            if (!(value & MCM_PLACR_EFDS_MASK))
+            {
+                /* Speculation buffer is off for data. */
+                speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable;
+            }
+        }
+    }
+#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC
+    {
+        uint32_t value;
+        uint32_t b0dpeMask, b0ipeMask;
+#if defined(FMC_PFB01CR_B0DPE_MASK)
+        value = FMC->PFB01CR;
+        b0dpeMask = FMC_PFB01CR_B0DPE_MASK;
+        b0ipeMask = FMC_PFB01CR_B0IPE_MASK;
+#elif defined(FMC_PFB0CR_B0DPE_MASK)
+        value = FMC->PFB0CR;
+        b0dpeMask = FMC_PFB0CR_B0DPE_MASK;
+        b0ipeMask = FMC_PFB0CR_B0IPE_MASK;
+#endif
+        if (!(value & b0dpeMask))
+        {
+            /* Do not prefetch in response to data references. */
+            speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable;
+        }
+        if (!(value & b0ipeMask))
+        {
+            /* Do not prefetch in response to instruction fetches. */
+            speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable;
+        }
+    }
+#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
+    {
+        uint32_t value;
+        uint32_t flashSpeculationMask, dataPrefetchMask;
+        value = MSCM->OCMDR[0];
+        flashSpeculationMask = MSCM_OCMDR_OCMC1_DFCS_MASK;
+        dataPrefetchMask = MSCM_OCMDR_OCMC1_DFDS_MASK;
+
+        if (value & flashSpeculationMask)
+        {
+            /* Speculation buffer is off. */
+            speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable;
+            speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable;
+        }
+        else
+        {
+            /* Speculation buffer is on for instruction. */
+            if (value & dataPrefetchMask)
+            {
+                /* Speculation buffer is off for data. */
+                speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable;
+            }
         }
     }
+#endif
+
+    return kStatus_FLASH_Success;
+}
+
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+/*!
+ * @brief Copy PIC of flash_run_command() to RAM
+ */
+static void copy_flash_run_command(uint32_t *flashRunCommand)
+{
+    assert(sizeof(s_flashRunCommandFunctionCode) <= (kFLASH_ExecuteInRamFunctionMaxSizeInWords * 4));
 
     /* Since the value of ARM function pointer is always odd, but the real start address
-     * of function memory should be even, that's why -1 and +1 operation exist. */
-    memcpy((void *)flashRunCommand, (void *)flash_run_command_start_addr, funcLength);
-    callFlashRunCommand = (void (*)(FTFx_REG_ACCESS_TYPE ftfx_fstat))((uint32_t)flashRunCommand + 1);
+     * of function memory should be even, that's why +1 operation exist. */
+    memcpy((void *)flashRunCommand, (void *)s_flashRunCommandFunctionCode, sizeof(s_flashRunCommandFunctionCode));
+    callFlashRunCommand = (void (*)(FTFx_REG8_ACCESS_TYPE ftfx_fstat))((uint32_t)flashRunCommand + 1);
 }
 #endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
 
@@ -1973,7 +2636,7 @@ static status_t flash_command_sequence(flash_config_t *config)
     /* We pass the ftfx_fstat address as a parameter to flash_run_comamnd() instead of using
      * pre-processed MICRO sentences or operating global variable in flash_run_comamnd()
      * to make sure that flash_run_command() will be compiled into position-independent code (PIC). */
-    callFlashRunCommand((FTFx_REG_ACCESS_TYPE)(&FTFx->FSTAT));
+    callFlashRunCommand((FTFx_REG8_ACCESS_TYPE)(&FTFx->FSTAT));
 #else
     /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */
     FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK;
@@ -2015,100 +2678,173 @@ static status_t flash_command_sequence(flash_config_t *config)
 
 #if FLASH_DRIVER_IS_FLASH_RESIDENT
 /*!
- * @brief Run flash cache clear command
+ * @brief Copy PIC of flash_common_bit_operation() to RAM
  *
- * This function should be copied to RAM for execution to make sure that code works
- * properly even flash cache is disabled.
- * It is for flash-resident bootloader only, not technically required for ROM or
- * flashloader (RAM-resident bootloader).
  */
-void flash_cache_clear_command(FTFx_REG32_ACCESS_TYPE ftfx_reg)
+static void copy_flash_common_bit_operation(uint32_t *flashCommonBitOperation)
 {
-#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS
-    *ftfx_reg |= MCM_PLACR_CFCC_MASK;
-#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS
-#if defined(FMC_PFB01CR_CINV_WAY_MASK)
-    *ftfx_reg = (*ftfx_reg & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0);
-#else
-    *ftfx_reg = (*ftfx_reg & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0);
+    assert(sizeof(s_flashCommonBitOperationFunctionCode) <= (kFLASH_ExecuteInRamFunctionMaxSizeInWords * 4));
+
+    /* Since the value of ARM function pointer is always odd, but the real start address
+     * of function memory should be even, that's why +1 operation exist. */
+    memcpy((void *)flashCommonBitOperation, (void *)s_flashCommonBitOperationFunctionCode,
+           sizeof(s_flashCommonBitOperationFunctionCode));
+    callFlashCommonBitOperation = (void (*)(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift,
+                                            uint32_t bitValue))((uint32_t)flashCommonBitOperation + 1);
+    /* Workround for some devices which doesn't need this function */
+    callFlashCommonBitOperation((FTFx_REG32_ACCESS_TYPE)0, 0, 0, 0);
+}
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+
+#if FLASH_CACHE_IS_CONTROLLED_BY_MCM
+/*! @brief Performs the cache clear to the flash by MCM.*/
+void mcm_flash_cache_clear(flash_config_t *config)
+{
+    FTFx_REG32_ACCESS_TYPE regBase = (FTFx_REG32_ACCESS_TYPE)&MCM0_CACHE_REG;
+
+#if defined(MCM0) && defined(MCM1)
+    if (config->FlashCacheControllerIndex == (uint8_t)kFLASH_CacheControllerIndexForCore1)
+    {
+        regBase = (FTFx_REG32_ACCESS_TYPE)&MCM1_CACHE_REG;
+    }
 #endif
-#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS
-    *ftfx_reg |= MSCM_OCMDR_OCMC1(2);
-    *ftfx_reg |= MSCM_OCMDR_OCMC1(1);
-#else
-/*    #error "Unknown flash cache controller"  */
-#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */
-       /* Memory barriers for good measure.
-        * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
+
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+    callFlashCommonBitOperation(regBase, MCM_CACHE_CLEAR_MASK, MCM_CACHE_CLEAR_SHIFT, 1U);
+#else  /* !FLASH_DRIVER_IS_FLASH_RESIDENT */
+    *regBase |= MCM_CACHE_CLEAR_MASK;
+
+    /* Memory barriers for good measure.
+     * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
     __ISB();
     __DSB();
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
 }
+#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MCM */
 
-/*!
- * @brief Be used for determining the size of flash_cache_clear_command()
- *
- * This function must be defined that lexically follows flash_cache_clear_command(),
- * so we can determine the size of flash_cache_clear_command() at runtime and not worry
- * about toolchain or code generation differences.
- */
-void flash_cache_clear_command_end(void)
+#if FLASH_CACHE_IS_CONTROLLED_BY_FMC
+/*! @brief Performs the cache clear to the flash by FMC.*/
+void fmc_flash_cache_clear(void)
 {
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+    FTFx_REG32_ACCESS_TYPE regBase = (FTFx_REG32_ACCESS_TYPE)0;
+#if defined(FMC_PFB01CR_CINV_WAY_MASK)
+    regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR;
+    callFlashCommonBitOperation(regBase, FMC_PFB01CR_CINV_WAY_MASK, FMC_PFB01CR_CINV_WAY_SHIFT, 0xFU);
+#else
+    regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR;
+    callFlashCommonBitOperation(regBase, FMC_PFB0CR_CINV_WAY_MASK, FMC_PFB0CR_CINV_WAY_SHIFT, 0xFU);
+#endif
+#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */
+#if defined(FMC_PFB01CR_CINV_WAY_MASK)
+    FMC->PFB01CR = (FMC->PFB01CR & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0);
+#else
+    FMC->PFB0CR = (FMC->PFB0CR & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0);
+#endif
+    /* Memory barriers for good measure.
+     * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
+    __ISB();
+    __DSB();
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
 }
+#endif /* FLASH_CACHE_IS_CONTROLLED_BY_FMC */
 
-/*!
- * @brief Copy flash_cache_clear_command() to RAM
- *
- * This function copys the memory between flash_cache_clear_command() and flash_cache_clear_command_end()
- * into the buffer which is also means that copying flash_cache_clear_command() to RAM.
- */
-static void copy_flash_cache_clear_command(uint8_t *flashCacheClearCommand)
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
+/*! @brief Performs the prefetch speculation buffer clear to the flash by MSCM.*/
+void mscm_flash_prefetch_speculation_enable(bool enable)
 {
-    /* Calculate the valid length of flash_cache_clear_command() memory.
-     * Set max size(64 bytes) as default function size, in case some compiler allocates
-     * flash_cache_clear_command_end ahead of flash_cache_clear_command. */
-    uint32_t funcLength = kFLASH_executeInRamFunctionMaxSize;
-    uint32_t flash_cache_clear_command_start_addr = (uint32_t)flash_cache_clear_command & (~1U);
-    uint32_t flash_cache_clear_command_end_addr = (uint32_t)flash_cache_clear_command_end & (~1U);
-    if (flash_cache_clear_command_end_addr > flash_cache_clear_command_start_addr)
+    uint8_t setValue;
+    if (enable)
     {
-        funcLength = flash_cache_clear_command_end_addr - flash_cache_clear_command_start_addr;
+        setValue = 0x0U;
+    }
+    else
+    {
+        setValue = 0x3U;
+    }
 
-        assert(funcLength <= kFLASH_executeInRamFunctionMaxSize);
+/* The OCMDR[0] is always used to prefetch main Pflash*/
+/* For device with FlexNVM support, the OCMDR[1] is used to prefetch Dflash.
+ * For device with secondary flash support, the OCMDR[1] is used to prefetch secondary Pflash. */
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+    callFlashCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0], MSCM_SPECULATION_DISABLE_MASK,
+                                MSCM_SPECULATION_DISABLE_SHIFT, setValue);
+#if FLASH_SSD_IS_FLEXNVM_ENABLED || BL_HAS_SECONDARY_INTERNAL_FLASH
+    callFlashCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[1], MSCM_SPECULATION_DISABLE_MASK,
+                                MSCM_SPECULATION_DISABLE_SHIFT, setValue);
+#endif
+#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */
+    MSCM->OCMDR[0] |= MSCM_SPECULATION_DISABLE(setValue);
 
-        /* In case some compiler allocates other function in the middle of flash_cache_clear_command
-         * and flash_cache_clear_command_end. */
-        if (funcLength > kFLASH_executeInRamFunctionMaxSize)
-        {
-            funcLength = kFLASH_executeInRamFunctionMaxSize;
-        }
-    }
+    /* Memory barriers for good measure.
+     * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
+    __ISB();
+    __DSB();
+#if FLASH_SSD_IS_FLEXNVM_ENABLED || BL_HAS_SECONDARY_INTERNAL_FLASH
+    MSCM->OCMDR[1] |= MSCM_SPECULATION_DISABLE(setValue);
 
-    /* Since the value of ARM function pointer is always odd, but the real start address
-     * of function memory should be even, that's why -1 and +1 operation exist. */
-    memcpy((void *)flashCacheClearCommand, (void *)flash_cache_clear_command_start_addr, funcLength);
-    callFlashCacheClearCommand = (void (*)(FTFx_REG32_ACCESS_TYPE ftfx_reg))((uint32_t)flashCacheClearCommand + 1);
+    /* Each cahce clear instaruction should be followed by below code*/
+    __ISB();
+    __DSB();
+#endif
+
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
 }
+#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM */
+
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC
+/*! @brief Performs the prefetch speculation buffer clear to the flash by FMC.*/
+void fmc_flash_prefetch_speculation_clear(void)
+{
+#if FLASH_DRIVER_IS_FLASH_RESIDENT
+    FTFx_REG32_ACCESS_TYPE regBase = (FTFx_REG32_ACCESS_TYPE)0;
+#if defined(FMC_PFB01CR_S_INV_MASK)
+    regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR;
+    callFlashCommonBitOperation(regBase, FMC_PFB01CR_S_INV_MASK, FMC_PFB01CR_S_INV_SHIFT, 1U);
+#elif defined(FMC_PFB01CR_S_B_INV_MASK)
+    regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR;
+    callFlashCommonBitOperation(regBase, FMC_PFB01CR_S_B_INV_MASK, FMC_PFB01CR_S_B_INV_SHIFT, 1U);
+#elif defined(FMC_PFB0CR_S_INV_MASK)
+    regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR;
+    callFlashCommonBitOperation(regBase, FMC_PFB0CR_S_INV_MASK, FMC_PFB0CR_S_INV_SHIFT, 1U);
+#elif defined(FMC_PFB0CR_S_B_INV_MASK)
+    regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR;
+    callFlashCommonBitOperation(regBase, FMC_PFB0CR_S_B_INV_MASK, FMC_PFB0CR_S_B_INV_SHIFT, 1U);
+#endif
+#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */
+#if defined(FMC_PFB01CR_S_INV_MASK)
+    FMC->PFB01CR |= FMC_PFB01CR_S_INV_MASK;
+#elif defined(FMC_PFB01CR_S_B_INV_MASK)
+    FMC->PFB01CR |= FMC_PFB01CR_S_B_INV_MASK;
+#elif defined(FMC_PFB0CR_S_INV_MASK)
+    FMC->PFB0CR |= FMC_PFB0CR_S_INV_MASK;
+#elif defined(FMC_PFB0CR_S_B_INV_MASK)
+    FMC->PFB0CR |= FMC_PFB0CR_S_B_INV_MASK;
+#endif
+    /* Memory barriers for good measure.
+     * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
+    __ISB();
+    __DSB();
 #endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+}
+#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC */
 
 /*!
  * @brief Flash Cache Clear
  *
- * This function is used to perform the cache clear to the flash.
+ * This function is used to perform the cache and prefetch speculation clear to the flash.
  */
-#if (defined(__GNUC__))
-/* #pragma GCC push_options */
-/* #pragma GCC optimize("O0") */
-void __attribute__((optimize("O0"))) flash_cache_clear(flash_config_t *config)
-#else
-#if (defined(__ICCARM__))
-#pragma optimize = none
-#endif
-#if (defined(__CC_ARM))
-#pragma push
-#pragma O0
-#endif
 void flash_cache_clear(flash_config_t *config)
-#endif
+{
+    flash_cache_clear_process(config, kFLASH_CacheClearProcessPost);
+}
+
+/*!
+ * @brief Flash Cache Clear Process
+ *
+ * This function is used to perform the cache and prefetch speculation clear process to the flash.
+ */
+static void flash_cache_clear_process(flash_config_t *config, flash_cache_clear_process_t process)
 {
 #if FLASH_DRIVER_IS_FLASH_RESIDENT
     status_t returnCode = flash_check_execute_in_ram_function_info(config);
@@ -2116,66 +2852,33 @@ void flash_cache_clear(flash_config_t *config)
     {
         return;
     }
+#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
 
-/* We pass the ftfx register address as a parameter to flash_cache_clear_comamnd() instead of using
- * pre-processed MACROs or a global variable in flash_cache_clear_comamnd()
- * to make sure that flash_cache_clear_command() will be compiled into position-independent code (PIC). */
-#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS
-#if defined(MCM)
-    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM->PLACR);
+    /* We pass the ftfx register address as a parameter to flash_common_bit_operation() instead of using
+     * pre-processed MACROs or a global variable in flash_common_bit_operation()
+     * to make sure that flash_common_bit_operation() will be compiled into position-independent code (PIC). */
+    if (process == kFLASH_CacheClearProcessPost)
+    {
+#if FLASH_CACHE_IS_CONTROLLED_BY_MCM
+        mcm_flash_cache_clear(config);
 #endif
-#if defined(MCM0)
-    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM0->PLACR);
+#if FLASH_CACHE_IS_CONTROLLED_BY_FMC
+        fmc_flash_cache_clear();
 #endif
-#if defined(MCM1)
-    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MCM1->PLACR);
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
+        mscm_flash_prefetch_speculation_enable(true);
 #endif
-#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS
-#if defined(FMC_PFB01CR_CINV_WAY_MASK)
-    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR);
-#else
-    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR);
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC
+        fmc_flash_prefetch_speculation_clear();
 #endif
-#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS
-    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0]);
-#else
-    /* #error "Unknown flash cache controller" */
-    /* meaningless code, just a workaround to solve warning*/
-    callFlashCacheClearCommand((FTFx_REG32_ACCESS_TYPE)0);
-#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */
-
-#else
-
-#if defined(FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS
-#if defined(MCM)
-    MCM->PLACR |= MCM_PLACR_CFCC_MASK;
-#endif
-#if defined(MCM0)
-    MCM0->PLACR |= MCM_PLACR_CFCC_MASK;
-#endif
-#if defined(MCM1)
-    MCM1->PLACR |= MCM_PLACR_CFCC_MASK;
-#endif
-#elif defined(FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS
-#if defined(FMC_PFB01CR_CINV_WAY_MASK)
-    FMC->PFB01CR = (FMC->PFB01CR & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0);
-#else
-    FMC->PFB0CR = (FMC->PFB0CR & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0);
+    }
+    if (process == kFLASH_CacheClearProcessPre)
+    {
+#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
+        mscm_flash_prefetch_speculation_enable(false);
 #endif
-#elif defined(FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS) && FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS
-    MSCM->OCMDR[0] |= MSCM_OCMDR_OCMC1(2);
-    MSCM->OCMDR[0] |= MSCM_OCMDR_OCMC1(1);
-#else
-/*    #error "Unknown flash cache controller" */
-#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */
-#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */
+    }
 }
-#if (defined(__CC_ARM))
-#pragma pop
-#endif
-#if (defined(__GNUC__))
-/* #pragma GCC pop_options */
-#endif
 
 #if FLASH_DRIVER_IS_FLASH_RESIDENT
 /*! @brief Check whether flash execute-in-ram functions are ready  */
@@ -2191,7 +2894,7 @@ static status_t flash_check_execute_in_ram_function_info(flash_config_t *config)
     flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo;
 
     if ((config->flashExecuteInRamFunctionInfo) &&
-        (kFLASH_executeInRamFunctionTotalNum == flashExecuteInRamFunctionInfo->activeFunctionCount))
+        (kFLASH_ExecuteInRamFunctionTotalNum == flashExecuteInRamFunctionInfo->activeFunctionCount))
     {
         return kStatus_FLASH_Success;
     }
@@ -2217,21 +2920,19 @@ static status_t flash_check_range(flash_config_t *config,
         return kStatus_FLASH_AlignmentError;
     }
 
-/* check for valid range of the target addresses */
-#if !FLASH_SSD_IS_FLEXNVM_ENABLED
-    if ((startAddress < config->PFlashBlockBase) ||
-        ((startAddress + lengthInBytes) > (config->PFlashBlockBase + config->PFlashTotalSize)))
-#else
-    if (!(((startAddress >= config->PFlashBlockBase) &&
-           ((startAddress + lengthInBytes) <= (config->PFlashBlockBase + config->PFlashTotalSize))) ||
-          ((startAddress >= config->DFlashBlockBase) &&
-           ((startAddress + lengthInBytes) <= (config->DFlashBlockBase + config->DFlashTotalSize)))))
+    /* check for valid range of the target addresses */
+    if (
+#if FLASH_SSD_IS_FLEXNVM_ENABLED
+        ((startAddress >= config->DFlashBlockBase) &&
+         ((startAddress + lengthInBytes) <= (config->DFlashBlockBase + config->DFlashTotalSize))) ||
 #endif
+        ((startAddress >= config->PFlashBlockBase) &&
+         ((startAddress + lengthInBytes) <= (config->PFlashBlockBase + config->PFlashTotalSize))))
     {
-        return kStatus_FLASH_AddressError;
+        return kStatus_FLASH_Success;
     }
 
-    return kStatus_FLASH_Success;
+    return kStatus_FLASH_AddressError;
 }
 
 /*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/
@@ -2250,6 +2951,8 @@ static status_t flash_get_matched_operation_info(flash_config_t *config,
 #if FLASH_SSD_IS_FLEXNVM_ENABLED
     if ((address >= config->DFlashBlockBase) && (address <= (config->DFlashBlockBase + config->DFlashTotalSize)))
     {
+        /* When required by the command, address bit 23 selects between program flash memory
+         * (=0) and data flash memory (=1).*/
         info->convertedAddress = address - config->DFlashBlockBase + 0x800000U;
         info->activeSectorSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE;
         info->activeBlockSize = config->DFlashTotalSize / FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT;
@@ -2263,11 +2966,25 @@ static status_t flash_get_matched_operation_info(flash_config_t *config,
     else
 #endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */
     {
-        info->convertedAddress = address;
+        info->convertedAddress = address - config->PFlashBlockBase;
         info->activeSectorSize = config->PFlashSectorSize;
         info->activeBlockSize = config->PFlashTotalSize / config->PFlashBlockCount;
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED
+        if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash)
+        {
+#if FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER || FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER
+            /* When required by the command, address bit 23 selects between main flash memory
+             * (=0) and secondary flash memory (=1).*/
+            info->convertedAddress += 0x800000U;
+#endif
+            info->blockWriteUnitSize = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE;
+        }
+        else
+#endif /* FLASH_SSD_IS_SECONDARY_FLASH_ENABLED */
+        {
+            info->blockWriteUnitSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE;
+        }
 
-        info->blockWriteUnitSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE;
         info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT;
         info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT;
         info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT;
@@ -2281,7 +2998,7 @@ static status_t flash_get_matched_operation_info(flash_config_t *config,
 static status_t flash_check_user_key(uint32_t key)
 {
     /* Validate the user key */
-    if (key != kFLASH_apiEraseKey)
+    if (key != kFLASH_ApiEraseKey)
     {
         return kStatus_FLASH_EraseKeyError;
     }
@@ -2307,13 +3024,17 @@ static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *con
         return kStatus_FLASH_InvalidArgument;
     }
 
+#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
     /* Get FlexNVM memory partition info from data flash IFR */
     returnCode = FLASH_ReadResource(config, DFLASH_IFR_READRESOURCE_START_ADDRESS, (uint32_t *)&dataIFRReadOut,
-                                    sizeof(dataIFRReadOut), kFLASH_resourceOptionFlashIfr);
+                                    sizeof(dataIFRReadOut), kFLASH_ResourceOptionFlashIfr);
     if (returnCode != kStatus_FLASH_Success)
     {
         return kStatus_FLASH_PartitionStatusUpdateFailure;
     }
+#else
+#error "Cannot get FlexNVM memory partition info"
+#endif
 
     /* Fill out partitioned EEPROM size */
     dataIFRReadOut.EEPROMDataSetSize &= 0x0FU;
@@ -2515,27 +3236,27 @@ static status_t flash_check_resource_range(uint32_t start,
     status = kStatus_FLASH_Success;
 
     maxReadbleAddress = start + lengthInBytes - 1;
-    if (option == kFLASH_resourceOptionVersionId)
+    if (option == kFLASH_ResourceOptionVersionId)
     {
-        if ((start != kFLASH_resourceRangeVersionIdStart) ||
-            ((start + lengthInBytes - 1) != kFLASH_resourceRangeVersionIdEnd))
+        if ((start != kFLASH_ResourceRangeVersionIdStart) ||
+            ((start + lengthInBytes - 1) != kFLASH_ResourceRangeVersionIdEnd))
         {
             status = kStatus_FLASH_InvalidArgument;
         }
     }
-    else if (option == kFLASH_resourceOptionFlashIfr)
+    else if (option == kFLASH_ResourceOptionFlashIfr)
     {
-        if (maxReadbleAddress < kFLASH_resourceRangePflashIfrSizeInBytes)
+        if (maxReadbleAddress < kFLASH_ResourceRangePflashIfrSizeInBytes)
         {
         }
 #if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP
-        else if ((start >= kFLASH_resourceRangePflashSwapIfrStart) &&
-                 (maxReadbleAddress <= kFLASH_resourceRangePflashSwapIfrEnd))
+        else if ((start >= kFLASH_ResourceRangePflashSwapIfrStart) &&
+                 (maxReadbleAddress <= kFLASH_ResourceRangePflashSwapIfrEnd))
         {
         }
 #endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */
-        else if ((start >= kFLASH_resourceRangeDflashIfrStart) &&
-                 (maxReadbleAddress <= kFLASH_resourceRangeDflashIfrEnd))
+        else if ((start >= kFLASH_ResourceRangeDflashIfrStart) &&
+                 (maxReadbleAddress <= kFLASH_ResourceRangeDflashIfrEnd))
         {
         }
         else
@@ -2556,9 +3277,9 @@ static status_t flash_check_resource_range(uint32_t start,
 /*! @brief Validates the gived swap control option.*/
 static status_t flash_check_swap_control_option(flash_swap_control_option_t option)
 {
-    if ((option == kFLASH_swapControlOptionIntializeSystem) || (option == kFLASH_swapControlOptionSetInUpdateState) ||
-        (option == kFLASH_swapControlOptionSetInCompleteState) || (option == kFLASH_swapControlOptionReportStatus) ||
-        (option == kFLASH_swapControlOptionDisableSystem))
+    if ((option == kFLASH_SwapControlOptionIntializeSystem) || (option == kFLASH_SwapControlOptionSetInUpdateState) ||
+        (option == kFLASH_SwapControlOptionSetInCompleteState) || (option == kFLASH_SwapControlOptionReportStatus) ||
+        (option == kFLASH_SwapControlOptionDisableSystem))
     {
         return kStatus_FLASH_Success;
     }
@@ -2571,21 +3292,48 @@ static status_t flash_check_swap_control_option(flash_swap_control_option_t opti
 /*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/
 static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address)
 {
-    flash_swap_ifr_field_config_t flashSwapIfrField;
+    flash_swap_ifr_field_data_t flashSwapIfrFieldData;
     uint32_t swapIndicatorAddress;
 
     status_t returnCode;
-    returnCode = FLASH_ReadResource(config, kFLASH_resourceRangePflashSwapIfrStart, (uint32_t *)&flashSwapIfrField,
-                                    sizeof(flash_swap_ifr_field_config_t), kFLASH_resourceOptionFlashIfr);
+#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
+    returnCode =
+        FLASH_ReadResource(config, kFLASH_ResourceRangePflashSwapIfrStart, flashSwapIfrFieldData.flashSwapIfrData,
+                           sizeof(flashSwapIfrFieldData.flashSwapIfrData), kFLASH_ResourceOptionFlashIfr);
+
     if (returnCode != kStatus_FLASH_Success)
     {
         return returnCode;
     }
+#else
+    {
+        /* From RM, the actual info are stored in FCCOB6,7 */
+        uint32_t returnValue[2];
+        returnCode = FLASH_ReadOnce(config, kFLASH_RecordIndexSwapAddr, returnValue, 4);
+        if (returnCode != kStatus_FLASH_Success)
+        {
+            return returnCode;
+        }
+        flashSwapIfrFieldData.flashSwapIfrField.swapIndicatorAddress = (uint16_t)returnValue[0];
+        returnCode = FLASH_ReadOnce(config, kFLASH_RecordIndexSwapEnable, returnValue, 4);
+        if (returnCode != kStatus_FLASH_Success)
+        {
+            return returnCode;
+        }
+        flashSwapIfrFieldData.flashSwapIfrField.swapEnableWord = (uint16_t)returnValue[0];
+        returnCode = FLASH_ReadOnce(config, kFLASH_RecordIndexSwapDisable, returnValue, 4);
+        if (returnCode != kStatus_FLASH_Success)
+        {
+            return returnCode;
+        }
+        flashSwapIfrFieldData.flashSwapIfrField.swapDisableWord = (uint16_t)returnValue[0];
+    }
+#endif
 
-    /* The high 2 byte value of Swap Indicator Address is stored in Program Flash Swap IFR Field,
-     * the low 4 bit value of Swap Indicator Address is always 4'b0000 */
-    swapIndicatorAddress =
-        (uint32_t)flashSwapIfrField.swapIndicatorAddress * FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT;
+    /* The high bits value of Swap Indicator Address is stored in Program Flash Swap IFR Field,
+     * the low severval bit value of Swap Indicator Address is always 1'b0 */
+    swapIndicatorAddress = (uint32_t)flashSwapIfrFieldData.flashSwapIfrField.swapIndicatorAddress *
+                           FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT;
     if (address != swapIndicatorAddress)
     {
         return kStatus_FLASH_SwapIndicatorAddressError;
@@ -2599,8 +3347,8 @@ static status_t flash_validate_swap_indicator_address(flash_config_t *config, ui
 /*! @brief Validates the gived flexram function option.*/
 static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option)
 {
-    if ((option != kFLASH_flexramFunctionOptionAvailableAsRam) &&
-        (option != kFLASH_flexramFunctionOptionAvailableForEeprom))
+    if ((option != kFLASH_FlexramFunctionOptionAvailableAsRam) &&
+        (option != kFLASH_FlexramFunctionOptionAvailableForEeprom))
     {
         return kStatus_FLASH_InvalidArgument;
     }
@@ -2608,3 +3356,77 @@ static inline status_t flasn_check_flexram_function_option_range(flash_flexram_f
     return kStatus_FLASH_Success;
 }
 #endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */
+
+/*! @brief Gets the flash protection information (region size, region count).*/
+static status_t flash_get_protection_info(flash_config_t *config, flash_protection_config_t *info)
+{
+    uint32_t pflashTotalSize;
+
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* Clean up info Structure*/
+    memset(info, 0, sizeof(flash_protection_config_t));
+
+/* Note: KW40 has a secondary flash, but it doesn't have independent protection register*/
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && (!FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER)
+    pflashTotalSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE +
+                      FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE;
+    info->regionBase = FSL_FEATURE_FLASH_PFLASH_START_ADDRESS;
+#else
+    pflashTotalSize = config->PFlashTotalSize;
+    info->regionBase = config->PFlashBlockBase;
+#endif
+
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER
+    if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash)
+    {
+        info->regionCount = FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT;
+    }
+    else
+#endif
+    {
+        info->regionCount = FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT;
+    }
+
+    /* Calculate the size of the flash protection region
+     * If the flash density is > 32KB, then protection region is 1/32 of total flash density
+     * Else if flash density is < 32KB, then flash protection region is set to 1KB */
+    if (pflashTotalSize > info->regionCount * 1024)
+    {
+        info->regionSize = (pflashTotalSize) / info->regionCount;
+    }
+    else
+    {
+        info->regionSize = 1024;
+    }
+
+    return kStatus_FLASH_Success;
+}
+
+#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL
+/*! @brief Gets the flash Execute-Only access information (Segment size, Segment count).*/
+static status_t flash_get_access_info(flash_config_t *config, flash_access_config_t *info)
+{
+    if (config == NULL)
+    {
+        return kStatus_FLASH_InvalidArgument;
+    }
+
+    /* Clean up info Structure*/
+    memset(info, 0, sizeof(flash_access_config_t));
+
+/* Note: KW40 has a secondary flash, but it doesn't have independent access register*/
+#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && (!FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER)
+    info->SegmentBase = FSL_FEATURE_FLASH_PFLASH_START_ADDRESS;
+#else
+    info->SegmentBase = config->PFlashBlockBase;
+#endif
+    info->SegmentSize = config->PFlashAccessSegmentSize;
+    info->SegmentCount = config->PFlashAccessSegmentCount;
+
+    return kStatus_FLASH_Success;
+}
+#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flash.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flash.h
index 63463e03cb4..e143cb3e1f6 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flash.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flash.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2013-2016, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -53,21 +53,21 @@
  * @name Flash version
  * @{
  */
-/*! @brief Construct the version number for drivers. */
+/*! @brief Constructs the version number for drivers. */
 #if !defined(MAKE_VERSION)
 #define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
 #endif
 
-/*! @brief FLASH driver version for SDK*/
-#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */
+/*! @brief Flash driver version for SDK*/
+#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*!< Version 2.3.1. */
 
-/*! @brief FLASH driver version for ROM*/
+/*! @brief Flash driver version for ROM*/
 enum _flash_driver_version_constants
 {
-    kFLASH_driverVersionName = 'F', /*!< Flash driver version name.*/
-    kFLASH_driverVersionMajor = 2,  /*!< Major flash driver version.*/
-    kFLASH_driverVersionMinor = 1,  /*!< Minor flash driver version.*/
-    kFLASH_driverVersionBugfix = 0  /*!< Bugfix for flash driver version.*/
+    kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/
+    kFLASH_DriverVersionMajor = 2,  /*!< Major flash driver version.*/
+    kFLASH_DriverVersionMinor = 3,  /*!< Minor flash driver version.*/
+    kFLASH_DriverVersionBugfix = 1  /*!< Bugfix for flash driver version.*/
 };
 /*@}*/
 
@@ -75,29 +75,41 @@ enum _flash_driver_version_constants
  * @name Flash configuration
  * @{
  */
-/*! @brief Whether to support FlexNVM in flash driver */
+/*! @brief Indicates whether to support FlexNVM in the Flash driver */
 #if !defined(FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT)
-#define FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT 1 /*!< Enable FlexNVM support by default. */
+#define FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT 1 /*!< Enables the FlexNVM support by default. */
 #endif
 
-/*! @brief Whether the FlexNVM is enabled in flash driver */
+/*! @brief Indicates whether the FlexNVM is enabled in the Flash driver */
 #define FLASH_SSD_IS_FLEXNVM_ENABLED (FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT && FSL_FEATURE_FLASH_HAS_FLEX_NVM)
 
+/*! @brief Indicates whether to support Secondary flash in the Flash driver */
+#if !defined(FLASH_SSD_CONFIG_ENABLE_SECONDARY_FLASH_SUPPORT)
+#define FLASH_SSD_CONFIG_ENABLE_SECONDARY_FLASH_SUPPORT 1 /*!< Enables the secondary flash support by default. */
+#endif
+
+/*! @brief Indicates whether the secondary flash is supported in the Flash driver */
+#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS)
+#define FLASH_SSD_IS_SECONDARY_FLASH_ENABLED (FLASH_SSD_CONFIG_ENABLE_SECONDARY_FLASH_SUPPORT)
+#else
+#define FLASH_SSD_IS_SECONDARY_FLASH_ENABLED (0)
+#endif
+
 /*! @brief Flash driver location. */
 #if !defined(FLASH_DRIVER_IS_FLASH_RESIDENT)
 #if (!defined(BL_TARGET_ROM) && !defined(BL_TARGET_RAM))
-#define FLASH_DRIVER_IS_FLASH_RESIDENT 1 /*!< Used for flash resident application. */
+#define FLASH_DRIVER_IS_FLASH_RESIDENT 1 /*!< Used for the flash resident application. */
 #else
-#define FLASH_DRIVER_IS_FLASH_RESIDENT 0 /*!< Used for non-flash resident application. */
+#define FLASH_DRIVER_IS_FLASH_RESIDENT 0 /*!< Used for the non-flash resident application. */
 #endif
 #endif
 
 /*! @brief Flash Driver Export option */
 #if !defined(FLASH_DRIVER_IS_EXPORTED)
 #if (defined(BL_TARGET_ROM) || defined(BL_TARGET_FLASH))
-#define FLASH_DRIVER_IS_EXPORTED 1 /*!< Used for ROM bootloader. */
+#define FLASH_DRIVER_IS_EXPORTED 1 /*!< Used for the ROM bootloader. */
 #else
-#define FLASH_DRIVER_IS_EXPORTED 0 /*!< Used for SDK application. */
+#define FLASH_DRIVER_IS_EXPORTED 0 /*!< Used for the MCUXpresso SDK application. */
 #endif
 #endif
 /*@}*/
@@ -118,7 +130,7 @@ enum _flash_driver_version_constants
 #define kStatusGroupFlashDriver 1
 #endif
 
-/*! @brief Construct a status code value from a group and code number. */
+/*! @brief Constructs a status code value from a group and a code number. */
 #if !defined(MAKE_STATUS)
 #define MAKE_STATUS(group, code) ((((group)*100) + (code)))
 #endif
@@ -128,37 +140,43 @@ enum _flash_driver_version_constants
  */
 enum _flash_status
 {
-    kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0),         /*!< Api is executed successfully*/
+    kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0),         /*!< API is executed successfully*/
     kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/
     kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0),   /*!< Error size*/
     kStatus_FLASH_AlignmentError =
-        MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with specified baseline*/
+        MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/
     kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */
     kStatus_FLASH_AccessError =
-        MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bounds addresses */
+        MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */
     kStatus_FLASH_ProtectionViolation = MAKE_STATUS(
         kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */
     kStatus_FLASH_CommandFailure =
         MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */
-    kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6),   /*!< Unknown property.*/
-    kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7),     /*!< Api erase key is invalid.*/
-    kStatus_FLASH_RegionExecuteOnly = MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< Current region is execute only.*/
+    kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/
+    kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7),   /*!< API erase key is invalid.*/
+    kStatus_FLASH_RegionExecuteOnly =
+        MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/
     kStatus_FLASH_ExecuteInRamFunctionNotReady =
-        MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-ram function is not available.*/
+        MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/
     kStatus_FLASH_PartitionStatusUpdateFailure =
         MAKE_STATUS(kStatusGroupFlashDriver, 10), /*!< Failed to update partition status.*/
     kStatus_FLASH_SetFlexramAsEepromError =
-        MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Failed to set flexram as eeprom.*/
+        MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Failed to set FlexRAM as EEPROM.*/
     kStatus_FLASH_RecoverFlexramAsRamError =
-        MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< Failed to recover flexram as ram.*/
-    kStatus_FLASH_SetFlexramAsRamError = MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< Failed to set flexram as ram.*/
+        MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< Failed to recover FlexRAM as RAM.*/
+    kStatus_FLASH_SetFlexramAsRamError = MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< Failed to set FlexRAM as RAM.*/
     kStatus_FLASH_RecoverFlexramAsEepromError =
-        MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< Failed to recover flexram as eeprom.*/
-    kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 15), /*!< Flash api is not supported.*/
+        MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< Failed to recover FlexRAM as EEPROM.*/
+    kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 15), /*!< Flash API is not supported.*/
     kStatus_FLASH_SwapSystemNotInUninitialized =
-        MAKE_STATUS(kStatusGroupFlashDriver, 16), /*!< Swap system is not in uninitialzed state.*/
+        MAKE_STATUS(kStatusGroupFlashDriver, 16), /*!< Swap system is not in an uninitialzed state.*/
     kStatus_FLASH_SwapIndicatorAddressError =
-        MAKE_STATUS(kStatusGroupFlashDriver, 17), /*!< Swap indicator address is invalid.*/
+        MAKE_STATUS(kStatusGroupFlashDriver, 17), /*!< The swap indicator address is invalid.*/
+    kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 18), /*!< The flash property is read-only.*/
+    kStatus_FLASH_InvalidPropertyValue =
+        MAKE_STATUS(kStatusGroupFlashDriver, 19), /*!< The flash property value is out of range.*/
+    kStatus_FLASH_InvalidSpeculationOption =
+        MAKE_STATUS(kStatusGroupFlashDriver, 20), /*!< The option of flash prefetch speculation is invalid.*/
 };
 /*@}*/
 
@@ -166,13 +184,13 @@ enum _flash_status
  * @name Flash API key
  * @{
  */
-/*! @brief Construct the four char code for flash driver API key. */
+/*! @brief Constructs the four character code for the Flash driver API key. */
 #if !defined(FOUR_CHAR_CODE)
 #define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a)))
 #endif
 
 /*!
- * @brief Enumeration for flash driver API keys.
+ * @brief Enumeration for Flash driver API keys.
  *
  * @note The resulting value is built with a byte order such that the string
  * being readable in expected order when viewed in a hex editor, if the value
@@ -180,7 +198,7 @@ enum _flash_status
  */
 enum _flash_driver_api_keys
 {
-    kFLASH_apiEraseKey = FOUR_CHAR_CODE('k', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/
+    kFLASH_ApiEraseKey = FOUR_CHAR_CODE('k', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/
 };
 /*@}*/
 
@@ -189,10 +207,10 @@ enum _flash_driver_api_keys
  */
 typedef enum _flash_margin_value
 {
-    kFLASH_marginValueNormal,  /*!< Use the 'normal' read level for 1s.*/
-    kFLASH_marginValueUser,    /*!< Apply the 'User' margin to the normal read-1 level.*/
-    kFLASH_marginValueFactory, /*!< Apply the 'Factory' margin to the normal read-1 level.*/
-    kFLASH_marginValueInvalid  /*!< Not real margin level, Used to determine the range of valid margin level. */
+    kFLASH_MarginValueNormal,  /*!< Use the 'normal' read level for 1s.*/
+    kFLASH_MarginValueUser,    /*!< Apply the 'User' margin to the normal read-1 level.*/
+    kFLASH_MarginValueFactory, /*!< Apply the 'Factory' margin to the normal read-1 level.*/
+    kFLASH_MarginValueInvalid  /*!< Not real margin level, Used to determine the range of valid margin level. */
 } flash_margin_value_t;
 
 /*!
@@ -200,9 +218,9 @@ typedef enum _flash_margin_value
  */
 typedef enum _flash_security_state
 {
-    kFLASH_securityStateNotSecure,       /*!< Flash is not secure.*/
-    kFLASH_securityStateBackdoorEnabled, /*!< Flash backdoor is enabled.*/
-    kFLASH_securityStateBackdoorDisabled /*!< Flash backdoor is disabled.*/
+    kFLASH_SecurityStateNotSecure,       /*!< Flash is not secure.*/
+    kFLASH_SecurityStateBackdoorEnabled, /*!< Flash backdoor is enabled.*/
+    kFLASH_SecurityStateBackdoorDisabled /*!< Flash backdoor is disabled.*/
 } flash_security_state_t;
 
 /*!
@@ -210,9 +228,9 @@ typedef enum _flash_security_state
  */
 typedef enum _flash_protection_state
 {
-    kFLASH_protectionStateUnprotected, /*!< Flash region is not protected.*/
-    kFLASH_protectionStateProtected,   /*!< Flash region is protected.*/
-    kFLASH_protectionStateMixed        /*!< Flash is mixed with protected and unprotected region.*/
+    kFLASH_ProtectionStateUnprotected, /*!< Flash region is not protected.*/
+    kFLASH_ProtectionStateProtected,   /*!< Flash region is protected.*/
+    kFLASH_ProtectionStateMixed        /*!< Flash is mixed with protected and unprotected region.*/
 } flash_protection_state_t;
 
 /*!
@@ -220,9 +238,9 @@ typedef enum _flash_protection_state
  */
 typedef enum _flash_execute_only_access_state
 {
-    kFLASH_accessStateUnLimited,   /*!< Flash region is unLimited.*/
-    kFLASH_accessStateExecuteOnly, /*!< Flash region is execute only.*/
-    kFLASH_accessStateMixed        /*!< Flash is mixed with unLimited and execute only region.*/
+    kFLASH_AccessStateUnLimited,   /*!< Flash region is unlimited.*/
+    kFLASH_AccessStateExecuteOnly, /*!< Flash region is execute only.*/
+    kFLASH_AccessStateMixed        /*!< Flash is mixed with unlimited and execute only region.*/
 } flash_execute_only_access_state_t;
 
 /*!
@@ -230,41 +248,43 @@ typedef enum _flash_execute_only_access_state
  */
 typedef enum _flash_property_tag
 {
-    kFLASH_propertyPflashSectorSize = 0x00U,         /*!< Pflash sector size property.*/
-    kFLASH_propertyPflashTotalSize = 0x01U,          /*!< Pflash total size property.*/
-    kFLASH_propertyPflashBlockSize = 0x02U,          /*!< Pflash block size property.*/
-    kFLASH_propertyPflashBlockCount = 0x03U,         /*!< Pflash block count property.*/
-    kFLASH_propertyPflashBlockBaseAddr = 0x04U,      /*!< Pflash block base address property.*/
-    kFLASH_propertyPflashFacSupport = 0x05U,         /*!< Pflash fac support property.*/
-    kFLASH_propertyPflashAccessSegmentSize = 0x06U,  /*!< Pflash access segment size property.*/
-    kFLASH_propertyPflashAccessSegmentCount = 0x07U, /*!< Pflash access segment count property.*/
-    kFLASH_propertyFlexRamBlockBaseAddr = 0x08U,     /*!< FlexRam block base address property.*/
-    kFLASH_propertyFlexRamTotalSize = 0x09U,         /*!< FlexRam total size property.*/
-    kFLASH_propertyDflashSectorSize = 0x10U,         /*!< Dflash sector size property.*/
-    kFLASH_propertyDflashTotalSize = 0x11U,          /*!< Dflash total size property.*/
-    kFLASH_propertyDflashBlockSize = 0x12U,          /*!< Dflash block count property.*/
-    kFLASH_propertyDflashBlockCount = 0x13U,         /*!< Dflash block base address property.*/
-    kFLASH_propertyDflashBlockBaseAddr = 0x14U,      /*!< Eeprom total size property.*/
-    kFLASH_propertyEepromTotalSize = 0x15U
+    kFLASH_PropertyPflashSectorSize = 0x00U,         /*!< Pflash sector size property.*/
+    kFLASH_PropertyPflashTotalSize = 0x01U,          /*!< Pflash total size property.*/
+    kFLASH_PropertyPflashBlockSize = 0x02U,          /*!< Pflash block size property.*/
+    kFLASH_PropertyPflashBlockCount = 0x03U,         /*!< Pflash block count property.*/
+    kFLASH_PropertyPflashBlockBaseAddr = 0x04U,      /*!< Pflash block base address property.*/
+    kFLASH_PropertyPflashFacSupport = 0x05U,         /*!< Pflash fac support property.*/
+    kFLASH_PropertyPflashAccessSegmentSize = 0x06U,  /*!< Pflash access segment size property.*/
+    kFLASH_PropertyPflashAccessSegmentCount = 0x07U, /*!< Pflash access segment count property.*/
+    kFLASH_PropertyFlexRamBlockBaseAddr = 0x08U,     /*!< FlexRam block base address property.*/
+    kFLASH_PropertyFlexRamTotalSize = 0x09U,         /*!< FlexRam total size property.*/
+    kFLASH_PropertyDflashSectorSize = 0x10U,         /*!< Dflash sector size property.*/
+    kFLASH_PropertyDflashTotalSize = 0x11U,          /*!< Dflash total size property.*/
+    kFLASH_PropertyDflashBlockSize = 0x12U,          /*!< Dflash block size property.*/
+    kFLASH_PropertyDflashBlockCount = 0x13U,         /*!< Dflash block count property.*/
+    kFLASH_PropertyDflashBlockBaseAddr = 0x14U,      /*!< Dflash block base address property.*/
+    kFLASH_PropertyEepromTotalSize = 0x15U,          /*!< EEPROM total size property.*/
+    kFLASH_PropertyFlashMemoryIndex = 0x20U,         /*!< Flash memory index property.*/
+    kFLASH_PropertyFlashCacheControllerIndex = 0x21U /*!< Flash cache controller index property.*/
 } flash_property_tag_t;
 
 /*!
- * @brief Constants for execute-in-ram flash function.
+ * @brief Constants for execute-in-RAM flash function.
  */
 enum _flash_execute_in_ram_function_constants
 {
-    kFLASH_executeInRamFunctionMaxSize = 64U, /*!< Max size of execute-in-ram function.*/
-    kFLASH_executeInRamFunctionTotalNum = 2U  /*!< Total number of execute-in-ram functions.*/
+    kFLASH_ExecuteInRamFunctionMaxSizeInWords = 16U, /*!< The maximum size of execute-in-RAM function.*/
+    kFLASH_ExecuteInRamFunctionTotalNum = 2U         /*!< Total number of execute-in-RAM functions.*/
 };
 
 /*!
- * @brief Flash execute-in-ram function information.
+ * @brief Flash execute-in-RAM function information.
  */
 typedef struct _flash_execute_in_ram_function_config
 {
-    uint32_t activeFunctionCount;    /*!< Number of available execute-in-ram functions.*/
-    uint8_t *flashRunCommand;        /*!< execute-in-ram function: flash_run_command.*/
-    uint8_t *flashCacheClearCommand; /*!< execute-in-ram function: flash_cache_clear_command.*/
+    uint32_t activeFunctionCount;      /*!< Number of available execute-in-RAM functions.*/
+    uint32_t *flashRunCommand;         /*!< Execute-in-RAM function: flash_run_command.*/
+    uint32_t *flashCommonBitOperation; /*!< Execute-in-RAM function: flash_common_bit_operation.*/
 } flash_execute_in_ram_function_config_t;
 
 /*!
@@ -272,9 +292,9 @@ typedef struct _flash_execute_in_ram_function_config
  */
 typedef enum _flash_read_resource_option
 {
-    kFLASH_resourceOptionFlashIfr =
+    kFLASH_ResourceOptionFlashIfr =
         0x00U, /*!< Select code for Program flash 0 IFR, Program flash swap 0 IFR, Data flash 0 IFR */
-    kFLASH_resourceOptionVersionId = 0x01U /*!< Select code for Version ID*/
+    kFLASH_ResourceOptionVersionId = 0x01U /*!< Select code for the version ID*/
 } flash_read_resource_option_t;
 
 /*!
@@ -283,124 +303,262 @@ typedef enum _flash_read_resource_option
 enum _flash_read_resource_range
 {
 #if (FSL_FEATURE_FLASH_IS_FTFE == 1)
-    kFLASH_resourceRangePflashIfrSizeInBytes = 1024U, /*!< Pflash IFR size in byte.*/
-    kFLASH_resourceRangeVersionIdSizeInBytes = 8U,    /*!< Version ID IFR size in byte.*/
-    kFLASH_resourceRangeVersionIdStart = 0x08U,       /*!< Version ID IFR start address.*/
-    kFLASH_resourceRangeVersionIdEnd = 0x0FU,         /*!< Version ID IFR end address.*/
-#else                                                 /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */
-    kFLASH_resourceRangePflashIfrSizeInBytes = 256U, /*!< Pflash IFR size in byte.*/
-    kFLASH_resourceRangeVersionIdSizeInBytes = 8U,   /*!< Version ID IFR size in byte.*/
-    kFLASH_resourceRangeVersionIdStart = 0x00U,      /*!< Version ID IFR start address.*/
-    kFLASH_resourceRangeVersionIdEnd = 0x07U,        /*!< Version ID IFR end address.*/
+    kFLASH_ResourceRangePflashIfrSizeInBytes = 1024U,  /*!< Pflash IFR size in byte.*/
+    kFLASH_ResourceRangeVersionIdSizeInBytes = 8U,     /*!< Version ID IFR size in byte.*/
+    kFLASH_ResourceRangeVersionIdStart = 0x08U,        /*!< Version ID IFR start address.*/
+    kFLASH_ResourceRangeVersionIdEnd = 0x0FU,          /*!< Version ID IFR end address.*/
+    kFLASH_ResourceRangePflashSwapIfrStart = 0x40000U, /*!< Pflash swap IFR start address.*/
+    kFLASH_ResourceRangePflashSwapIfrEnd =
+        (kFLASH_ResourceRangePflashSwapIfrStart + 0x3FFU), /*!< Pflash swap IFR end address.*/
+#else                                                      /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */
+    kFLASH_ResourceRangePflashIfrSizeInBytes = 256U,  /*!< Pflash IFR size in byte.*/
+    kFLASH_ResourceRangeVersionIdSizeInBytes = 8U,    /*!< Version ID IFR size in byte.*/
+    kFLASH_ResourceRangeVersionIdStart = 0x00U,       /*!< Version ID IFR start address.*/
+    kFLASH_ResourceRangeVersionIdEnd = 0x07U,         /*!< Version ID IFR end address.*/
+#if 0x20000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE)
+    kFLASH_ResourceRangePflashSwapIfrStart = 0x8000U, /*!< Pflash swap IFR start address.*/
+#elif 0x40000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE)
+    kFLASH_ResourceRangePflashSwapIfrStart = 0x10000U, /*!< Pflash swap IFR start address.*/
+#elif 0x80000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE)
+    kFLASH_ResourceRangePflashSwapIfrStart = 0x20000U, /*!< Pflash swap IFR start address.*/
+#else
+    kFLASH_ResourceRangePflashSwapIfrStart = 0,
 #endif
-    kFLASH_resourceRangePflashSwapIfrStart = 0x40000U, /*!< Pflash swap IFR start address.*/
-    kFLASH_resourceRangePflashSwapIfrEnd = 0x403FFU,   /*!< Pflash swap IFR end address.*/
-    kFLASH_resourceRangeDflashIfrStart = 0x800000U,    /*!< Dflash IFR start address.*/
-    kFLASH_resourceRangeDflashIfrEnd = 0x8003FFU,      /*!< Dflash IFR end address.*/
+    kFLASH_ResourceRangePflashSwapIfrEnd =
+        (kFLASH_ResourceRangePflashSwapIfrStart + 0xFFU), /*!< Pflash swap IFR end address.*/
+#endif
+    kFLASH_ResourceRangeDflashIfrStart = 0x800000U, /*!< Dflash IFR start address.*/
+    kFLASH_ResourceRangeDflashIfrEnd = 0x8003FFU,   /*!< Dflash IFR end address.*/
+};
+
+/*!
+ * @brief Enumeration for the index of read/program once record
+ */
+enum _k3_flash_read_once_index
+{
+    kFLASH_RecordIndexSwapAddr = 0xA1U,    /*!< Index of Swap indicator address.*/
+    kFLASH_RecordIndexSwapEnable = 0xA2U,  /*!< Index of Swap system enable.*/
+    kFLASH_RecordIndexSwapDisable = 0xA3U, /*!< Index of Swap system disable.*/
 };
 
 /*!
- * @brief Enumeration for the two possilbe options of set flexram function command.
+ * @brief Enumeration for the two possilbe options of set FlexRAM function command.
  */
 typedef enum _flash_flexram_function_option
 {
-    kFLASH_flexramFunctionOptionAvailableAsRam = 0xFFU,    /*!< Option used to make FlexRAM available as RAM */
-    kFLASH_flexramFunctionOptionAvailableForEeprom = 0x00U /*!< Option used to make FlexRAM available for EEPROM */
+    kFLASH_FlexramFunctionOptionAvailableAsRam = 0xFFU,    /*!< An option used to make FlexRAM available as RAM */
+    kFLASH_FlexramFunctionOptionAvailableForEeprom = 0x00U /*!< An option used to make FlexRAM available for EEPROM */
 } flash_flexram_function_option_t;
 
+/*!
+ * @brief Enumeration for acceleration RAM property.
+ */
+enum _flash_acceleration_ram_property
+{
+    kFLASH_AccelerationRamSize = 0x400U
+};
+
 /*!
  * @brief Enumeration for the possible options of Swap function
  */
 typedef enum _flash_swap_function_option
 {
-    kFLASH_swapFunctionOptionEnable = 0x00U, /*!< Option used to enable Swap function */
-    kFLASH_swapFunctionOptionDisable = 0x01U /*!< Option used to Disable Swap function */
+    kFLASH_SwapFunctionOptionEnable = 0x00U, /*!< An option used to enable the Swap function */
+    kFLASH_SwapFunctionOptionDisable = 0x01U /*!< An option used to disable the Swap function */
 } flash_swap_function_option_t;
 
 /*!
- * @brief Enumeration for the possible options of Swap Control commands
+ * @brief Enumeration for the possible options of Swap control commands
  */
 typedef enum _flash_swap_control_option
 {
-    kFLASH_swapControlOptionIntializeSystem = 0x01U,    /*!< Option used to Intialize Swap System */
-    kFLASH_swapControlOptionSetInUpdateState = 0x02U,   /*!< Option used to Set Swap in Update State */
-    kFLASH_swapControlOptionSetInCompleteState = 0x04U, /*!< Option used to Set Swap in Complete State */
-    kFLASH_swapControlOptionReportStatus = 0x08U,       /*!< Option used to Report Swap Status */
-    kFLASH_swapControlOptionDisableSystem = 0x10U       /*!< Option used to Disable Swap Status */
+    kFLASH_SwapControlOptionIntializeSystem = 0x01U,    /*!< An option used to initialize the Swap system */
+    kFLASH_SwapControlOptionSetInUpdateState = 0x02U,   /*!< An option used to set the Swap in an update state */
+    kFLASH_SwapControlOptionSetInCompleteState = 0x04U, /*!< An option used to set the Swap in a complete state */
+    kFLASH_SwapControlOptionReportStatus = 0x08U,       /*!< An option used to report the Swap status */
+    kFLASH_SwapControlOptionDisableSystem = 0x10U       /*!< An option used to disable the Swap status */
 } flash_swap_control_option_t;
 
 /*!
- * @brief Enumeration for the possible flash swap status.
+ * @brief Enumeration for the possible flash Swap status.
  */
 typedef enum _flash_swap_state
 {
-    kFLASH_swapStateUninitialized = 0x00U, /*!< Flash swap system is in uninitialized state.*/
-    kFLASH_swapStateReady = 0x01U,         /*!< Flash swap system is in ready state.*/
-    kFLASH_swapStateUpdate = 0x02U,        /*!< Flash swap system is in update state.*/
-    kFLASH_swapStateUpdateErased = 0x03U,  /*!< Flash swap system is in updateErased state.*/
-    kFLASH_swapStateComplete = 0x04U,      /*!< Flash swap system is in complete state.*/
-    kFLASH_swapStateDisabled = 0x05U       /*!< Flash swap system is in disabled state.*/
+    kFLASH_SwapStateUninitialized = 0x00U, /*!< Flash Swap system is in an uninitialized state.*/
+    kFLASH_SwapStateReady = 0x01U,         /*!< Flash Swap system is in a ready state.*/
+    kFLASH_SwapStateUpdate = 0x02U,        /*!< Flash Swap system is in an update state.*/
+    kFLASH_SwapStateUpdateErased = 0x03U,  /*!< Flash Swap system is in an updateErased state.*/
+    kFLASH_SwapStateComplete = 0x04U,      /*!< Flash Swap system is in a complete state.*/
+    kFLASH_SwapStateDisabled = 0x05U       /*!< Flash Swap system is in a disabled state.*/
 } flash_swap_state_t;
 
 /*!
- * @breif Enumeration for the possible flash swap block status
+ * @breif Enumeration for the possible flash Swap block status
  */
 typedef enum _flash_swap_block_status
 {
-    kFLASH_swapBlockStatusLowerHalfProgramBlocksAtZero =
+    kFLASH_SwapBlockStatusLowerHalfProgramBlocksAtZero =
         0x00U, /*!< Swap block status is that lower half program block at zero.*/
-    kFLASH_swapBlockStatusUpperHalfProgramBlocksAtZero =
+    kFLASH_SwapBlockStatusUpperHalfProgramBlocksAtZero =
         0x01U, /*!< Swap block status is that upper half program block at zero.*/
 } flash_swap_block_status_t;
 
 /*!
- * @brief Flash Swap information.
+ * @brief Flash Swap information
  */
 typedef struct _flash_swap_state_config
 {
-    flash_swap_state_t flashSwapState;                /*!< Current swap system status.*/
-    flash_swap_block_status_t currentSwapBlockStatus; /*!< Current swap block status.*/
-    flash_swap_block_status_t nextSwapBlockStatus;    /*!< Next swap block status.*/
+    flash_swap_state_t flashSwapState;                /*!<The current Swap system status.*/
+    flash_swap_block_status_t currentSwapBlockStatus; /*!< The current Swap block status.*/
+    flash_swap_block_status_t nextSwapBlockStatus;    /*!< The next Swap block status.*/
 } flash_swap_state_config_t;
 
 /*!
- * @brief Flash Swap IFR fileds.
+ * @brief Flash Swap IFR fields
  */
 typedef struct _flash_swap_ifr_field_config
 {
-    uint16_t swapIndicatorAddress; /*!< Swap indicator address field.*/
-    uint16_t swapEnableWord;       /*!< Swap enable word field.*/
-    uint8_t reserved0[6];          /*!< Reserved field.*/
-    uint16_t swapDisableWord;      /*!< Swap disable word field.*/
-    uint8_t reserved1[4];          /*!< Reserved field.*/
+    uint16_t swapIndicatorAddress; /*!< A Swap indicator address field.*/
+    uint16_t swapEnableWord;       /*!< A Swap enable word field.*/
+    uint8_t reserved0[4];          /*!< A reserved field.*/
+#if (FSL_FEATURE_FLASH_IS_FTFE == 1)
+    uint8_t reserved1[2];     /*!< A reserved field.*/
+    uint16_t swapDisableWord; /*!< A Swap disable word field.*/
+    uint8_t reserved2[4];     /*!< A reserved field.*/
+#endif
 } flash_swap_ifr_field_config_t;
 
 /*!
- * @brief Enumeration for FlexRAM load during reset option.
+ * @brief Flash Swap IFR field data
+ */
+typedef union _flash_swap_ifr_field_data
+{
+    uint32_t flashSwapIfrData[2];                    /*!< A flash Swap IFR field data .*/
+    flash_swap_ifr_field_config_t flashSwapIfrField; /*!< A flash Swap IFR field structure.*/
+} flash_swap_ifr_field_data_t;
+
+/*!
+ * @brief PFlash protection status - low 32bit
+ */
+typedef union _pflash_protection_status_low
+{
+    uint32_t protl32b; /*!< PROT[31:0] .*/
+    struct
+    {
+        uint8_t protsl; /*!< PROTS[7:0] .*/
+        uint8_t protsh; /*!< PROTS[15:8] .*/
+        uint8_t reserved[2];
+    } prots16b;
+} pflash_protection_status_low_t;
+
+/*!
+ * @brief PFlash protection status - full
+ */
+typedef struct _pflash_protection_status
+{
+    pflash_protection_status_low_t valueLow32b; /*!< PROT[31:0] or PROTS[15:0].*/
+#if ((FSL_FEATURE_FLASH_IS_FTFA == 1) && (defined(FTFA_FPROTH0_PROT_MASK))) || \
+    ((FSL_FEATURE_FLASH_IS_FTFE == 1) && (defined(FTFE_FPROTH0_PROT_MASK))) || \
+    ((FSL_FEATURE_FLASH_IS_FTFL == 1) && (defined(FTFL_FPROTH0_PROT_MASK)))
+    // uint32_t protHigh; /*!< PROT[63:32].*/
+    struct
+    {
+        uint32_t proth32b;
+    } valueHigh32b;
+#endif
+} pflash_protection_status_t;
+
+/*!
+ * @brief Enumeration for the FlexRAM load during reset option.
  */
 typedef enum _flash_partition_flexram_load_option
 {
-    kFLASH_partitionFlexramLoadOptionLoadedWithValidEepromData =
+    kFLASH_PartitionFlexramLoadOptionLoadedWithValidEepromData =
         0x00U, /*!< FlexRAM is loaded with valid EEPROM data during reset sequence.*/
-    kFLASH_partitionFlexramLoadOptionNotLoaded = 0x01U /*!< FlexRAM is not loaded during reset sequence.*/
+    kFLASH_PartitionFlexramLoadOptionNotLoaded = 0x01U /*!< FlexRAM is not loaded during reset sequence.*/
 } flash_partition_flexram_load_option_t;
 
-/*! @brief callback type used for pflash block*/
+/*!
+ * @brief Enumeration for the flash memory index.
+ */
+typedef enum _flash_memory_index
+{
+    kFLASH_MemoryIndexPrimaryFlash = 0x00U,   /*!< Current flash memory is primary flash.*/
+    kFLASH_MemoryIndexSecondaryFlash = 0x01U, /*!< Current flash memory is secondary flash.*/
+} flash_memory_index_t;
+
+/*!
+ * @brief Enumeration for the flash cache controller index.
+ */
+typedef enum _flash_cache_controller_index
+{
+    kFLASH_CacheControllerIndexForCore0 = 0x00U, /*!< Current flash cache controller is for core 0.*/
+    kFLASH_CacheControllerIndexForCore1 = 0x01U, /*!< Current flash cache controller is for core 1.*/
+} flash_cache_controller_index_t;
+
+/*! @brief A callback type used for the Pflash block*/
 typedef void (*flash_callback_t)(void);
 
 /*!
- * @brief Active flash information for current operation.
+ * @brief Enumeration for the two possible options of flash prefetch speculation.
+ */
+typedef enum _flash_prefetch_speculation_option
+{
+    kFLASH_prefetchSpeculationOptionEnable = 0x00U,
+    kFLASH_prefetchSpeculationOptionDisable = 0x01U
+} flash_prefetch_speculation_option_t;
+
+/*!
+ * @brief Flash prefetch speculation status.
+ */
+typedef struct _flash_prefetch_speculation_status
+{
+    flash_prefetch_speculation_option_t instructionOption; /*!< Instruction speculation.*/
+    flash_prefetch_speculation_option_t dataOption;        /*!< Data speculation.*/
+} flash_prefetch_speculation_status_t;
+
+/*!
+ * @brief Flash cache clear process code.
+ */
+typedef enum _flash_cache_clear_process
+{
+    kFLASH_CacheClearProcessPre = 0x00U,  /*!< Pre flash cache clear process.*/
+    kFLASH_CacheClearProcessPost = 0x01U, /*!< Post flash cache clear process.*/
+} flash_cache_clear_process_t;
+
+/*!
+ * @brief Active flash protection information for the current operation.
+ */
+typedef struct _flash_protection_config
+{
+    uint32_t regionBase;  /*!< Base address of flash protection region.*/
+    uint32_t regionSize;  /*!< size of flash protection region.*/
+    uint32_t regionCount; /*!< flash protection region count.*/
+} flash_protection_config_t;
+
+/*!
+ * @brief Active flash Execute-Only access information for the current operation.
+ */
+typedef struct _flash_access_config
+{
+    uint32_t SegmentBase;  /*!< Base address of flash Execute-Only segment.*/
+    uint32_t SegmentSize;  /*!< size of flash Execute-Only segment.*/
+    uint32_t SegmentCount; /*!< flash Execute-Only segment count.*/
+} flash_access_config_t;
+
+/*!
+ * @brief Active flash information for the current operation.
  */
 typedef struct _flash_operation_config
 {
-    uint32_t convertedAddress;           /*!< Converted address for current flash type.*/
-    uint32_t activeSectorSize;           /*!< Sector size of current flash type.*/
-    uint32_t activeBlockSize;            /*!< Block size of current flash type.*/
-    uint32_t blockWriteUnitSize;         /*!< write unit size.*/
-    uint32_t sectorCmdAddressAligment;   /*!< Erase sector command address alignment.*/
-    uint32_t sectionCmdAddressAligment;  /*!< Program/Verify section command address alignment.*/
-    uint32_t resourceCmdAddressAligment; /*!< Read resource command address alignment.*/
-    uint32_t checkCmdAddressAligment;    /*!< Program check command address alignment.*/
+    uint32_t convertedAddress;           /*!< A converted address for the current flash type.*/
+    uint32_t activeSectorSize;           /*!< A sector size of the current flash type.*/
+    uint32_t activeBlockSize;            /*!< A block size of the current flash type.*/
+    uint32_t blockWriteUnitSize;         /*!< The write unit size.*/
+    uint32_t sectorCmdAddressAligment;   /*!< An erase sector command address alignment.*/
+    uint32_t sectionCmdAddressAligment;  /*!< A program/verify section command address alignment.*/
+    uint32_t resourceCmdAddressAligment; /*!< A read resource command address alignment.*/
+    uint32_t checkCmdAddressAligment;    /*!< A program check command address alignment.*/
 } flash_operation_config_t;
 
 /*! @brief Flash driver state information.
@@ -410,25 +568,29 @@ typedef struct _flash_operation_config
  */
 typedef struct _flash_config
 {
-    uint32_t PFlashBlockBase;                /*!< Base address of the first PFlash block */
-    uint32_t PFlashTotalSize;                /*!< Size of all combined PFlash block. */
-    uint32_t PFlashBlockCount;               /*!< Number of PFlash blocks. */
-    uint32_t PFlashSectorSize;               /*!< Size in bytes of a sector of PFlash. */
-    flash_callback_t PFlashCallback;         /*!< Callback function for flash API. */
-    uint32_t PFlashAccessSegmentSize;        /*!< Size in bytes of a access segment of PFlash. */
-    uint32_t PFlashAccessSegmentCount;       /*!< Number of PFlash access segments. */
-    uint32_t *flashExecuteInRamFunctionInfo; /*!< Info struct of flash execute-in-ram function. */
-    uint32_t FlexRAMBlockBase;               /*!< For FlexNVM device, this is the base address of FlexRAM
-                                                  For non-FlexNVM device, this is the base address of acceleration RAM memory */
-    uint32_t FlexRAMTotalSize;               /*!< For FlexNVM device, this is the size of FlexRAM
-                                                  For non-FlexNVM device, this is the size of acceleration RAM memory */
-    uint32_t DFlashBlockBase; /*!< For FlexNVM device, this is the base address of D-Flash memory (FlexNVM memory);
-                                   For non-FlexNVM device, this field is unused */
-    uint32_t DFlashTotalSize; /*!< For FlexNVM device, this is total size of the FlexNVM memory;
-                                   For non-FlexNVM device, this field is unused */
-    uint32_t EEpromTotalSize; /*!< For FlexNVM device, this is the size in byte of EEPROM area which was partitioned
-                                 from FlexRAM;
-                                   For non-FlexNVM device, this field is unused */
+    uint32_t PFlashBlockBase;                /*!< A base address of the first PFlash block */
+    uint32_t PFlashTotalSize;                /*!< The size of the combined PFlash block. */
+    uint8_t PFlashBlockCount;                /*!< A number of PFlash blocks. */
+    uint8_t FlashMemoryIndex;                /*!< 0 - primary flash; 1 - secondary flash*/
+    uint8_t FlashCacheControllerIndex;       /*!< 0 - Controller for core 0; 1 - Controller for core 1 */
+    uint8_t Reserved0;                       /*!< Reserved field 0 */
+    uint32_t PFlashSectorSize;               /*!< The size in bytes of a sector of PFlash. */
+    flash_callback_t PFlashCallback;         /*!< The callback function for the flash API. */
+    uint32_t PFlashAccessSegmentSize;        /*!< A size in bytes of an access segment of PFlash. */
+    uint32_t PFlashAccessSegmentCount;       /*!< A number of PFlash access segments. */
+    uint32_t *flashExecuteInRamFunctionInfo; /*!< An information structure of the flash execute-in-RAM function. */
+    uint32_t FlexRAMBlockBase;               /*!< For the FlexNVM device, this is the base address of the FlexRAM */
+    /*!< For the non-FlexNVM device, this is the base address of the acceleration RAM memory */
+    uint32_t FlexRAMTotalSize; /*!< For the FlexNVM device, this is the size of the FlexRAM */
+                               /*!< For the non-FlexNVM device, this is the size of the acceleration RAM memory */
+    uint32_t
+        DFlashBlockBase; /*!< For the FlexNVM device, this is the base address of the D-Flash memory (FlexNVM memory) */
+                         /*!< For the non-FlexNVM device, this field is unused */
+    uint32_t DFlashTotalSize; /*!< For the FlexNVM device, this is the total size of the FlexNVM memory; */
+                              /*!< For the non-FlexNVM device, this field is unused */
+    uint32_t EEpromTotalSize; /*!< For the FlexNVM device, this is the size in bytes of the EEPROM area which was
+                                 partitioned from FlexRAM */
+    /*!< For the non-FlexNVM device, this field is unused */
 } flash_config_t;
 
 /*******************************************************************************
@@ -445,37 +607,37 @@ extern "C" {
  */
 
 /*!
- * @brief Initializes global flash properties structure members
+ * @brief Initializes the global flash properties structure members.
  *
- * This function checks and initializes Flash module for the other Flash APIs.
+ * This function checks and initializes the Flash module for the other Flash APIs.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config Pointer to the storage for the driver runtime state.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
- * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
+ * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update the partition status.
  */
 status_t FLASH_Init(flash_config_t *config);
 
 /*!
- * @brief Set the desired flash callback function
+ * @brief Sets the desired flash callback function.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param callback callback function to be stored in driver
+ * @param config Pointer to the storage for the driver runtime state.
+ * @param callback A callback function to be stored in the driver.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  */
 status_t FLASH_SetCallback(flash_config_t *config, flash_callback_t callback);
 
 /*!
- * @brief Prepare flash execute-in-ram functions
+ * @brief Prepares flash execute-in-RAM functions.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config Pointer to the storage for the driver runtime state.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  */
 #if FLASH_DRIVER_IS_FLASH_RESIDENT
 status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config);
@@ -491,59 +653,59 @@ status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config);
 /*!
  * @brief Erases entire flash
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param key value used to validate all flash erase APIs.
+ * @param config Pointer to the storage for the driver runtime state.
+ * @param key A value used to validate all flash erase APIs.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_EraseKeyError API erase key is invalid.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
  * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
- * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status
+ * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update the partition status.
  */
 status_t FLASH_EraseAll(flash_config_t *config, uint32_t key);
 
 /*!
- * @brief Erases flash sectors encompassed by parameters passed into function
+ * @brief Erases the flash sectors encompassed by parameters passed into function.
  *
  * This function erases the appropriate number of flash sectors based on the
  * desired start address and length.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config The pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be erased.
- *              The start address does not need to be sector aligned but must be word-aligned.
+ *              The start address does not need to be sector-aligned but must be word-aligned.
  * @param lengthInBytes The length, given in bytes (not words or long-words)
- *                      to be erased. Must be word aligned.
- * @param key value used to validate all flash erase APIs.
- *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
- * @retval #kStatus_FLASH_AddressError Address is out of range.
- * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ *                      to be erased. Must be word-aligned.
+ * @param key The value used to validate all flash erase APIs.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline.
+ * @retval #kStatus_FLASH_AddressError The address is out of range.
+ * @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key);
 
 /*!
- * @brief Erases entire flash, including protected sectors.
+ * @brief Erases the entire flash, including protected sectors.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param key value used to validate all flash erase APIs.
+ * @param config Pointer to the storage for the driver runtime state.
+ * @param key A value used to validate all flash erase APIs.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_EraseKeyError API erase key is invalid.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
  * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
- * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update partition status
+ * @retval #kStatus_FLASH_PartitionStatusUpdateFailure Failed to update the partition status.
  */
 #if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD
 status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key);
@@ -552,16 +714,16 @@ status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key);
 /*!
  * @brief Erases all program flash execute-only segments defined by the FXACC registers.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param key value used to validate all flash erase APIs.
+ * @param config Pointer to the storage for the driver runtime state.
+ * @param key A value used to validate all flash erase APIs.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_EraseKeyError Api erase key is invalid.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_EraseKeyError API erase key is invalid.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key);
 
@@ -573,101 +735,101 @@ status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key)
  */
 
 /*!
- * @brief Programs flash with data at locations passed in through parameters
+ * @brief Programs flash with data at locations passed in through parameters.
  *
- * This function programs the flash memory with desired data for a given
- * flash area as determined by the start address and length.
+ * This function programs the flash memory with the desired data for a given
+ * flash area as determined by the start address and the length.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be programmed. Must be
  *              word-aligned.
- * @param src Pointer to the source buffer of data that is to be programmed
+ * @param src A pointer to the source buffer of data that is to be programmed
  *            into the flash.
- * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
  *                      to be programmed. Must be word-aligned.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline.
  * @retval #kStatus_FLASH_AddressError Address is out of range.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes);
 
 /*!
- * @brief Programs Program Once Field through parameters
+ * @brief Programs Program Once Field through parameters.
  *
- * This function programs the Program Once Field with desired data for a given
+ * This function programs the Program Once Field with the desired data for a given
  * flash area as determined by the index and length.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param index The index indicating which area of Program Once Field to be programmed.
- * @param src Pointer to the source buffer of data that is to be programmed
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param index The index indicating which area of the Program Once Field to be programmed.
+ * @param src A pointer to the source buffer of data that is to be programmed
  *            into the Program Once Field.
- * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
  *                      to be programmed. Must be word-aligned.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint32_t *src, uint32_t lengthInBytes);
 
 /*!
- * @brief Programs flash with data at locations passed in through parameters via Program Section command
+ * @brief Programs flash with data at locations passed in through parameters via the Program Section command.
  *
- * This function programs the flash memory with desired data for a given
+ * This function programs the flash memory with the desired data for a given
  * flash area as determined by the start address and length.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be programmed. Must be
  *              word-aligned.
- * @param src Pointer to the source buffer of data that is to be programmed
+ * @param src A pointer to the source buffer of data that is to be programmed
  *            into the flash.
- * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
  *                      to be programmed. Must be word-aligned.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
  * @retval #kStatus_FLASH_AddressError Address is out of range.
- * @retval #kStatus_FLASH_SetFlexramAsRamError Failed to set flexram as ram
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_SetFlexramAsRamError Failed to set flexram as RAM.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
  * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
- * @retval #kStatus_FLASH_RecoverFlexramAsEepromError Failed to recover flexram as eeprom
+ * @retval #kStatus_FLASH_RecoverFlexramAsEepromError Failed to recover FlexRAM as EEPROM.
  */
 #if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD
 status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes);
 #endif
 
 /*!
- * @brief Programs EEPROM with data at locations passed in through parameters
+ * @brief Programs the EEPROM with data at locations passed in through parameters.
  *
- * This function programs the Emulated EEPROM with desired data for a given
+ * This function programs the emulated EEPROM with the desired data for a given
  * flash area as determined by the start address and length.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be programmed. Must be
  *              word-aligned.
- * @param src Pointer to the source buffer of data that is to be programmed
+ * @param src A pointer to the source buffer of data that is to be programmed
  *            into the flash.
- * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
  *                      to be programmed. Must be word-aligned.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_AddressError Address is out of range.
  * @retval #kStatus_FLASH_SetFlexramAsEepromError Failed to set flexram as eeprom.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_RecoverFlexramAsRamError Failed to recover flexram as ram
+ * @retval #kStatus_FLASH_RecoverFlexramAsRamError Failed to recover the FlexRAM as RAM.
  */
 #if FLASH_SSD_IS_FLEXNVM_ENABLED
 status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes);
@@ -681,27 +843,27 @@ status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src,
  */
 
 /*!
- * @brief Read resource with data at locations passed in through parameters
+ * @brief Reads the resource with data at locations passed in through parameters.
  *
- * This function reads the flash memory with desired location for a given
+ * This function reads the flash memory with the desired location for a given
  * flash area as determined by the start address and length.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be programmed. Must be
  *              word-aligned.
- * @param dst Pointer to the destination buffer of data that is used to store
+ * @param dst A pointer to the destination buffer of data that is used to store
  *        data to be read.
- * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
  *        to be read. Must be word-aligned.
  * @param option The resource option which indicates which area should be read back.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 #if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD
 status_t FLASH_ReadResource(
@@ -709,23 +871,23 @@ status_t FLASH_ReadResource(
 #endif
 
 /*!
- * @brief Read Program Once Field through parameters
+ * @brief Reads the Program Once Field through parameters.
  *
- * This function reads the read once feild with given index and length
+ * This function reads the read once feild with given index and length.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param index The index indicating the area of program once field to be read.
- * @param dst Pointer to the destination buffer of data that is used to store
+ * @param dst A pointer to the destination buffer of data that is used to store
  *        data to be read.
- * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
  *        to be programmed. Must be word-aligned.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint32_t *dst, uint32_t lengthInBytes);
 
@@ -737,35 +899,35 @@ status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint32_t *dst, u
  */
 
 /*!
- * @brief Returns the security state via the pointer passed into the function
+ * @brief Returns the security state via the pointer passed into the function.
  *
- * This function retrieves the current Flash security status, including the
+ * This function retrieves the current flash security status, including the
  * security enabling state and the backdoor key enabling state.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param state Pointer to the value returned for the current security status code:
+ * @param config A pointer to storage for the driver runtime state.
+ * @param state A pointer to the value returned for the current security status code:
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  */
 status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *state);
 
 /*!
- * @brief Allows user to bypass security with a backdoor key
+ * @brief Allows users to bypass security with a backdoor key.
  *
- * If the MCU is in secured state, this function will unsecure the MCU by
- * comparing the provided backdoor key with ones in the Flash Configuration
- * Field.
+ * If the MCU is in secured state, this function unsecures the MCU by
+ * comparing the provided backdoor key with ones in the flash configuration
+ * field.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param backdoorKey Pointer to the user buffer containing the backdoor key.
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param backdoorKey A pointer to the user buffer containing the backdoor key.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey);
 
@@ -777,75 +939,75 @@ status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey
  */
 
 /*!
- * @brief Verifies erasure of entire flash at specified margin level
+ * @brief Verifies erasure of the entire flash at a specified margin level.
  *
- * This function will check to see if the flash have been erased to the
+ * This function checks whether the flash is erased to the
  * specified read margin level.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param margin Read margin choice
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param margin Read margin choice.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 status_t FLASH_VerifyEraseAll(flash_config_t *config, flash_margin_value_t margin);
 
 /*!
- * @brief Verifies erasure of desired flash area at specified margin level
+ * @brief Verifies an erasure of the desired flash area at a specified margin level.
  *
- * This function will check the appropriate number of flash sectors based on
- * the desired start address and length to see if the flash have been erased
+ * This function checks the appropriate number of flash sectors based on
+ * the desired start address and length to check whether the flash is erased
  * to the specified read margin level.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be verified.
- *        The start address does not need to be sector aligned but must be word-aligned.
- * @param lengthInBytes The length, given in bytes (not words or long-words)
+ *        The start address does not need to be sector-aligned but must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
  *        to be verified. Must be word-aligned.
- * @param margin Read margin choice
+ * @param margin Read margin choice.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
  * @retval #kStatus_FLASH_AddressError Address is out of range.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, flash_margin_value_t margin);
 
 /*!
- * @brief Verifies programming of desired flash area at specified margin level
+ * @brief Verifies programming of the desired flash area at a specified margin level.
  *
  * This function verifies the data programed in the flash memory using the
- * Flash Program Check Command and compares it with expected data for a given
+ * Flash Program Check Command and compares it to the expected data for a given
  * flash area as determined by the start address and length.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be verified. Must be word-aligned.
- * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
  *        to be verified. Must be word-aligned.
- * @param expectedData Pointer to the expected data that is to be
+ * @param expectedData A pointer to the expected data that is to be
  *        verified against.
- * @param margin Read margin choice
- * @param failedAddress Pointer to returned failing address.
- * @param failedData Pointer to returned failing data.  Some derivitives do
- *        not included failed data as part of the FCCOBx registers.  In this
+ * @param margin Read margin choice.
+ * @param failedAddress A pointer to the returned failing address.
+ * @param failedData A pointer to the returned failing data.  Some derivatives do
+ *        not include failed data as part of the FCCOBx registers.  In this
  *        case, zeros are returned upon failure.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
  * @retval #kStatus_FLASH_AddressError Address is out of range.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 status_t FLASH_VerifyProgram(flash_config_t *config,
                              uint32_t start,
@@ -856,18 +1018,18 @@ status_t FLASH_VerifyProgram(flash_config_t *config,
                              uint32_t *failedData);
 
 /*!
- * @brief Verifies if the program flash executeonly segments have been erased to
- *  the specified read margin level
+ * @brief Verifies whether the program flash execute-only segments have been erased to
+ *  the specified read margin level.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param margin Read margin choice
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param margin Read margin choice.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 status_t FLASH_VerifyEraseAllExecuteOnlySegments(flash_config_t *config, flash_margin_value_t margin);
 
@@ -879,22 +1041,22 @@ status_t FLASH_VerifyEraseAllExecuteOnlySegments(flash_config_t *config, flash_m
  */
 
 /*!
- * @brief Returns the protection state of desired flash area via the pointer passed into the function
+ * @brief Returns the protection state of the desired flash area via the pointer passed into the function.
  *
- * This function retrieves the current Flash protect status for a given
+ * This function retrieves the current flash protect status for a given
  * flash area as determined by the start address and length.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be checked. Must be word-aligned.
  * @param lengthInBytes The length, given in bytes (not words or long-words)
  *        to be checked.  Must be word-aligned.
- * @param protection_state Pointer to the value returned for the current
+ * @param protection_state A pointer to the value returned for the current
  *        protection status code for the desired flash area.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
- * @retval #kStatus_FLASH_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_AddressError The address is out of range.
  */
 status_t FLASH_IsProtected(flash_config_t *config,
                            uint32_t start,
@@ -902,22 +1064,22 @@ status_t FLASH_IsProtected(flash_config_t *config,
                            flash_protection_state_t *protection_state);
 
 /*!
- * @brief Returns the access state of desired flash area via the pointer passed into the function
+ * @brief Returns the access state of the desired flash area via the pointer passed into the function.
  *
- * This function retrieves the current Flash access status for a given
+ * This function retrieves the current flash access status for a given
  * flash area as determined by the start address and length.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param start The start address of the desired flash memory to be checked. Must be word-aligned.
- * @param lengthInBytes The length, given in bytes (not words or long-words)
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
  *        to be checked.  Must be word-aligned.
- * @param access_state Pointer to the value returned for the current
+ * @param access_state A pointer to the value returned for the current
  *        access status code for the desired flash area.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
- * @retval #kStatus_FLASH_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned to the specified baseline.
+ * @retval #kStatus_FLASH_AddressError The address is out of range.
  */
 status_t FLASH_IsExecuteOnly(flash_config_t *config,
                              uint32_t start,
@@ -934,17 +1096,33 @@ status_t FLASH_IsExecuteOnly(flash_config_t *config,
 /*!
  * @brief Returns the desired flash property.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param whichProperty The desired property from the list of properties in
  *        enum flash_property_tag_t
- * @param value Pointer to the value returned for the desired flash property
+ * @param value A pointer to the value returned for the desired flash property.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_UnknownProperty unknown property tag
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_UnknownProperty An unknown property tag.
  */
 status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value);
 
+/*!
+ * @brief Sets the desired flash property.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param whichProperty The desired property from the list of properties in
+ *        enum flash_property_tag_t
+ * @param value A to set for the desired flash property.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_UnknownProperty An unknown property tag.
+ * @retval #kStatus_FLASH_InvalidPropertyValue An invalid property value.
+ * @retval #kStatus_FLASH_ReadOnlyProperty An read-only property tag.
+ */
+status_t FLASH_SetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t value);
+
 /*@}*/
 
 /*!
@@ -953,17 +1131,17 @@ status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichPro
  */
 
 /*!
- * @brief Set FlexRAM Function command
+ * @brief Sets the FlexRAM function command.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param option The option used to set work mode of FlexRAM
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param option The option used to set the work mode of FlexRAM.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 #if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD
 status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function_option_t option);
@@ -977,21 +1155,21 @@ status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function
  */
 
 /*!
- * @brief Configure Swap function or Check the swap state of Flash Module
+ * @brief Configures the Swap function or checks the the swap state of the Flash module.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param address Address used to configure the flash swap function
- * @param option The possible option used to configure Flash Swap function or check the flash swap status
- * @param returnInfo Pointer to the data which is used to return the information of flash swap.
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param address Address used to configure the flash Swap function.
+ * @param option The possible option used to configure Flash Swap function or check the flash Swap status
+ * @param returnInfo A pointer to the data which is used to return the information of flash Swap.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
- * @retval #kStatus_FLASH_SwapIndicatorAddressError Swap indicator address is invalid
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_SwapIndicatorAddressError Swap indicator address is invalid.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
- * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
  */
 #if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD
 status_t FLASH_SwapControl(flash_config_t *config,
@@ -1001,21 +1179,21 @@ status_t FLASH_SwapControl(flash_config_t *config,
 #endif
 
 /*!
- * @brief Swap the lower half flash with the higher half flaock
+ * @brief Swaps the lower half flash with the higher half flash.
  *
- * @param config Pointer to storage for the driver runtime state.
+ * @param config A pointer to the storage for the driver runtime state.
  * @param address Address used to configure the flash swap function
- * @param option The possible option used to configure Flash Swap function or check the flash swap status
+ * @param option The possible option used to configure the Flash Swap function or check the flash Swap status.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
- * @retval #kStatus_FLASH_SwapIndicatorAddressError Swap indicator address is invalid
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_SwapIndicatorAddressError Swap indicator address is invalid.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
  * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
- * @retval #kStatus_FLASH_SwapSystemNotInUninitialized Swap system is not in uninitialzed state
+ * @retval #kStatus_FLASH_SwapSystemNotInUninitialized Swap system is not in an uninitialzed state.
  */
 #if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP
 status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_function_option_t option);
@@ -1036,9 +1214,9 @@ status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_functio
  * @param flexnvmPartitionCode Specifies how to split the FlexNVM block between data flash memory and EEPROM backup
  *        memory supporting EEPROM functions.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
  * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-ram function is not available.
+ * @retval #kStatus_FLASH_ExecuteInRamFunctionNotReady Execute-in-RAM function is not available.
  * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
  * @retval #kStatus_FLASH_ProtectionViolation The program/erase operation is requested to execute on protected areas.
  * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
@@ -1058,51 +1236,54 @@ status_t FLASH_ProgramPartition(flash_config_t *config,
 */
 
 /*!
- * @brief Set PFLASH Protection to the intended protection status.
+ * @brief Sets the PFlash Protection to the intended protection status.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param protectStatus The expected protect status user wants to set to PFlash protection register. Each bit is
- * corresponding to protection of 1/32 of the total PFlash. The least significant bit is corresponding to the lowest
- * address area of P-Flash. The most significant bit is corresponding to the highest address area of PFlash. There are
+ * @param config A pointer to storage for the driver runtime state.
+ * @param protectStatus The expected protect status to set to the PFlash protection register. Each bit is
+ * corresponding to protection of 1/32(64) of the total PFlash. The least significant bit is corresponding to the lowest
+ * address area of PFlash. The most significant bit is corresponding to the highest address area of PFlash. There are
  * two possible cases as shown below:
  *       0: this area is protected.
  *       1: this area is unprotected.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
  */
-status_t FLASH_PflashSetProtection(flash_config_t *config, uint32_t protectStatus);
+status_t FLASH_PflashSetProtection(flash_config_t *config, pflash_protection_status_t *protectStatus);
 
 /*!
- * @brief Get PFLASH Protection Status.
+ * @brief Gets the PFlash protection status.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param protectStatus  Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/32 of the
- * total PFlash. The least significant bit is corresponding to the lowest address area of PFlash. The most significant
- * bit is corresponding to the highest address area of PFlash. Thee are two possible cases as below:
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param protectStatus  Protect status returned by the PFlash IP. Each bit is corresponding to the protection of
+ * 1/32(64)
+ * of the
+ * total PFlash. The least significant bit corresponds to the lowest address area of the PFlash. The most significant
+ * bit corresponds to the highest address area of PFlash. There are two possible cases as shown below:
  *       0: this area is protected.
  *       1: this area is unprotected.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
  */
-status_t FLASH_PflashGetProtection(flash_config_t *config, uint32_t *protectStatus);
+status_t FLASH_PflashGetProtection(flash_config_t *config, pflash_protection_status_t *protectStatus);
 
 /*!
- * @brief Set DFLASH Protection to the intended protection status.
+ * @brief Sets the DFlash protection to the intended protection status.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param protectStatus The expected protect status user wants to set to DFlash protection register. Each bit is
- * corresponding to protection of 1/8 of the total DFlash. The least significant bit is corresponding to the lowest
- * address area of DFlash. The most significant bit is corresponding to the highest address area of  DFlash. There are
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param protectStatus The expected protect status to set to the DFlash protection register. Each bit
+ * corresponds to the protection of the 1/8 of the total DFlash. The least significant bit corresponds to the lowest
+ * address area of the DFlash. The most significant bit corresponds to the highest address area of  the DFlash. There
+ * are
  * two possible cases as shown below:
  *       0: this area is protected.
  *       1: this area is unprotected.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
  * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
  */
 #if FLASH_SSD_IS_FLEXNVM_ENABLED
@@ -1110,38 +1291,39 @@ status_t FLASH_DflashSetProtection(flash_config_t *config, uint8_t protectStatus
 #endif
 
 /*!
- * @brief Get DFLASH Protection Status.
+ * @brief Gets the DFlash protection status.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param protectStatus  DFlash Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/8 of
- * the total DFlash. The least significant bit is corresponding to the lowest address area of DFlash. The most
- * significant bit is corresponding to the highest address area of DFlash and so on. There are two possible cases as
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param protectStatus  DFlash Protect status returned by the PFlash IP. Each bit corresponds to the protection of the
+ * 1/8 of
+ * the total DFlash. The least significant bit corresponds to the lowest address area of the DFlash. The most
+ * significant bit corresponds to the highest address area of the DFlash, and so on. There are two possible cases as
  * below:
  *       0: this area is protected.
  *       1: this area is unprotected.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
  */
 #if FLASH_SSD_IS_FLEXNVM_ENABLED
 status_t FLASH_DflashGetProtection(flash_config_t *config, uint8_t *protectStatus);
 #endif
 
 /*!
- * @brief Set EEPROM Protection to the intended protection status.
+ * @brief Sets the EEPROM protection to the intended protection status.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param protectStatus The expected protect status user wants to set to EEPROM protection register. Each bit is
- * corresponding to protection of 1/8 of the total EEPROM. The least significant bit is corresponding to the lowest
- * address area of EEPROM. The most significant bit is corresponding to the highest address area of EEPROM, and so on.
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param protectStatus The expected protect status to set to the EEPROM protection register. Each bit
+ * corresponds to the protection of the 1/8 of the total EEPROM. The least significant bit corresponds to the lowest
+ * address area of the EEPROM. The most significant bit corresponds to the highest address area of EEPROM, and so on.
  * There are two possible cases as shown below:
  *       0: this area is protected.
  *       1: this area is unprotected.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
  * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution.
  */
 #if FLASH_SSD_IS_FLEXNVM_ENABLED
@@ -1149,18 +1331,19 @@ status_t FLASH_EepromSetProtection(flash_config_t *config, uint8_t protectStatus
 #endif
 
 /*!
- * @brief Get DFLASH Protection Status.
+ * @brief Gets the DFlash protection status.
  *
- * @param config Pointer to storage for the driver runtime state.
- * @param protectStatus  DFlash Protect status returned by PFlash IP. Each bit is corresponding to protection of 1/8 of
- * the total EEPROM. The least significant bit is corresponding to the lowest address area of EEPROM. The most
- * significant bit is corresponding to the highest address area of EEPROM. There are two possible cases as below:
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param protectStatus  DFlash Protect status returned by the PFlash IP. Each bit corresponds to the protection of the
+ * 1/8 of
+ * the total EEPROM. The least significant bit corresponds to the lowest address area of the EEPROM. The most
+ * significant bit corresponds to the highest address area of the EEPROM. There are two possible cases as below:
  *       0: this area is protected.
  *       1: this area is unprotected.
  *
- * @retval #kStatus_FLASH_Success Api was executed successfully.
- * @retval #kStatus_FLASH_InvalidArgument Invalid argument is provided.
- * @retval #kStatus_FLASH_CommandNotSupported Flash api is not supported.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
  */
 #if FLASH_SSD_IS_FLEXNVM_ENABLED
 status_t FLASH_EepromGetProtection(flash_config_t *config, uint8_t *protectStatus);
@@ -1168,6 +1351,32 @@ status_t FLASH_EepromGetProtection(flash_config_t *config, uint8_t *protectStatu
 
 /*@}*/
 
+/*@}*/
+
+/*!
+* @name Flash Speculation Utilities
+* @{
+*/
+
+/*!
+ * @brief Sets the PFlash prefetch speculation to the intended speculation status.
+ *
+ * @param speculationStatus The expected protect status to set to the PFlash protection register. Each bit is
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidSpeculationOption An invalid speculation option argument is provided.
+ */
+status_t FLASH_PflashSetPrefetchSpeculation(flash_prefetch_speculation_status_t *speculationStatus);
+
+/*!
+ * @brief Gets the PFlash prefetch speculation status.
+ *
+ * @param speculationStatus  Speculation status returned by the PFlash IP.
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ */
+status_t FLASH_PflashGetPrefetchSpeculation(flash_prefetch_speculation_status_t *speculationStatus);
+
+/*@}*/
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexbus.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexbus.c
index 009a730fdf6..4a179b159d9 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexbus.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexbus.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -50,8 +50,10 @@ static uint32_t FLEXBUS_GetInstance(FB_Type *base);
 /*! @brief Pointers to FLEXBUS bases for each instance. */
 static FB_Type *const s_flexbusBases[] = FB_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to FLEXBUS clocks for each instance. */
 static const clock_ip_name_t s_flexbusClocks[] = FLEXBUS_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
@@ -62,7 +64,7 @@ static uint32_t FLEXBUS_GetInstance(FB_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_FB_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_flexbusBases); instance++)
     {
         if (s_flexbusBases[instance] == base)
         {
@@ -70,7 +72,7 @@ static uint32_t FLEXBUS_GetInstance(FB_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_FB_COUNT);
+    assert(instance < ARRAY_SIZE(s_flexbusBases));
 
     return instance;
 }
@@ -84,8 +86,10 @@ void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config)
     uint32_t chip = 0;
     uint32_t reg_value = 0;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Ungate clock for FLEXBUS */
     CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Reset all the register to default state */
     for (chip = 0; chip < FB_CSAR_COUNT; chip++)
@@ -168,8 +172,10 @@ void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config)
 
 void FLEXBUS_Deinit(FB_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Gate clock for FLEXBUS */
-    CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]);
+    CLOCK_DisableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void FLEXBUS_GetDefaultConfig(flexbus_config_t *config)
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexbus.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexbus.h
index 23cde14a569..f20ed44f055 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexbus.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexbus.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -38,7 +38,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -46,7 +45,7 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_FLEXBUS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+#define FSL_FLEXBUS_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */
 /*@}*/
 
 /*!
@@ -197,11 +196,11 @@ extern "C" {
  *
  * This function enables the clock gate for FlexBus module.
  * Only chip 0 is validated and set to known values. Other chips are disabled.
- * NOTE: In this function, certain parameters, depending on external memories,  must
- * be set before using FLEXBUS_Init() function.
+ * Note that in this function, certain parameters, depending on external memories,  must
+ * be set before using the FLEXBUS_Init() function.
  * This example shows how to set up the uart_state_t and the
  * flexbus_config_t parameters and how to call the FLEXBUS_Init function by passing
- * in these parameters:
+ * in these parameters.
    @code
     flexbus_config_t flexbusConfig;
     FLEXBUS_GetDefaultConfig(&flexbusConfig);
@@ -212,7 +211,7 @@ extern "C" {
    @endcode
  *
  * @param base FlexBus peripheral address.
- * @param config Pointer to the configure structure
+ * @param config Pointer to the configuration structure
 */
 void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config);
 
@@ -229,7 +228,7 @@ void FLEXBUS_Deinit(FB_Type *base);
  * @brief Initializes the FlexBus configuration structure.
  *
  * This function initializes the FlexBus configuration structure to default value. The default
- * values are:
+ * values are.
    @code
    fbConfig->chip                   = 0;
    fbConfig->writeProtect           = 0;
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.c
index 15e1f55f437..f58f3f55f05 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -165,8 +165,6 @@ static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_
 /*******************************************************************************
  * Variables
  ******************************************************************************/
-/* Array of FlexCAN handle. */
-static flexcan_handle_t *s_flexcanHandle[FSL_FEATURE_SOC_FLEXCAN_COUNT];
 
 /* Array of FlexCAN peripheral base address. */
 static CAN_Type *const s_flexcanBases[] = CAN_BASE_PTRS;
@@ -179,8 +177,17 @@ static const IRQn_Type s_flexcanErrorIRQ[] = CAN_Error_IRQS;
 static const IRQn_Type s_flexcanBusOffIRQ[] = CAN_Bus_Off_IRQS;
 static const IRQn_Type s_flexcanMbIRQ[] = CAN_ORed_Message_buffer_IRQS;
 
+/* Array of FlexCAN handle. */
+static flexcan_handle_t *s_flexcanHandle[ARRAY_SIZE(s_flexcanBases)];
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /* Array of FlexCAN clock name. */
 static const clock_ip_name_t s_flexcanClock[] = FLEXCAN_CLOCKS;
+#if defined(FLEXCAN_PERIPH_CLOCKS)
+/* Array of FlexCAN serial clock name. */
+static const clock_ip_name_t s_flexcanPeriphClock[] = FLEXCAN_PERIPH_CLOCKS;
+#endif /* FLEXCAN_PERIPH_CLOCKS */
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /* FlexCAN ISR for transactional APIs. */
 static flexcan_isr_t s_flexcanIsr;
@@ -194,7 +201,7 @@ uint32_t FLEXCAN_GetInstance(CAN_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_FLEXCAN_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_flexcanBases); instance++)
     {
         if (s_flexcanBases[instance] == base)
         {
@@ -202,7 +209,7 @@ uint32_t FLEXCAN_GetInstance(CAN_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_FLEXCAN_COUNT);
+    assert(instance < ARRAY_SIZE(s_flexcanBases));
 
     return instance;
 }
@@ -314,9 +321,13 @@ static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx)
     else
     {
         if (base->IMASK2 & ((uint32_t)(1 << (mbIdx - 32))))
+        {
             return true;
+        }
         else
+        {
             return false;
+        }
     }
 #endif
 }
@@ -420,14 +431,25 @@ static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_
 void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz)
 {
     uint32_t mcrTemp;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    uint32_t instance;
+#endif
 
     /* Assertion. */
     assert(config);
     assert((config->maxMbNum > 0) && (config->maxMbNum <= FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)));
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    instance = FLEXCAN_GetInstance(base);
     /* Enable FlexCAN clock. */
-    CLOCK_EnableClock(s_flexcanClock[FLEXCAN_GetInstance(base)]);
-
+    CLOCK_EnableClock(s_flexcanClock[instance]);
+#if defined(FLEXCAN_PERIPH_CLOCKS)
+    /* Enable FlexCAN serial clock. */
+    CLOCK_EnableClock(s_flexcanPeriphClock[instance]);
+#endif /* FLEXCAN_PERIPH_CLOCKS */
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE
     /* Disable FlexCAN Module. */
     FLEXCAN_Enable(base, false);
 
@@ -436,6 +458,7 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc
      */
     base->CTRL1 = (kFLEXCAN_ClkSrcOsc == config->clkSrc) ? base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK :
                                                            base->CTRL1 | CAN_CTRL1_CLKSRC_MASK;
+#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */
 
     /* Enable FlexCAN Module for configuartion. */
     FLEXCAN_Enable(base, true);
@@ -472,14 +495,24 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc
 
 void FLEXCAN_Deinit(CAN_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    uint32_t instance;
+#endif
     /* Reset all Register Contents. */
     FLEXCAN_Reset(base);
 
     /* Disable FlexCAN module. */
     FLEXCAN_Enable(base, false);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    instance = FLEXCAN_GetInstance(base);
+#if defined(FLEXCAN_PERIPH_CLOCKS)
+    /* Disable FlexCAN serial clock. */
+    CLOCK_DisableClock(s_flexcanPeriphClock[instance]);
+#endif /* FLEXCAN_PERIPH_CLOCKS */
     /* Disable FlexCAN clock. */
-    CLOCK_DisableClock(s_flexcanClock[FLEXCAN_GetInstance(base)]);
+    CLOCK_DisableClock(s_flexcanClock[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void FLEXCAN_GetDefaultConfig(flexcan_config_t *config)
@@ -488,7 +521,9 @@ void FLEXCAN_GetDefaultConfig(flexcan_config_t *config)
     assert(config);
 
     /* Initialize FlexCAN Module config struct with default value. */
+#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE
     config->clkSrc = kFLEXCAN_ClkSrcOsc;
+#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */
     config->baudRate = 125000U;
     config->maxMbNum = 16;
     config->enableLoopBack = false;
@@ -1293,13 +1328,13 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)
            (0 != (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag |
                             kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag))));
 #else
-        while ((0 != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFU)) ||
-               (0 != (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag |
-                                kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag))));
+    while ((0 != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFU)) ||
+            (0 != (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag |
+                            kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag))));
 #endif
 }
 
-#if (FSL_FEATURE_SOC_FLEXCAN_COUNT > 0)
+#if defined(CAN0)
 void CAN0_DriverIRQHandler(void)
 {
     assert(s_flexcanHandle[0]);
@@ -1308,7 +1343,7 @@ void CAN0_DriverIRQHandler(void)
 }
 #endif
 
-#if (FSL_FEATURE_SOC_FLEXCAN_COUNT > 1)
+#if defined(CAN1)
 void CAN1_DriverIRQHandler(void)
 {
     assert(s_flexcanHandle[1]);
@@ -1317,7 +1352,7 @@ void CAN1_DriverIRQHandler(void)
 }
 #endif
 
-#if (FSL_FEATURE_SOC_FLEXCAN_COUNT > 2)
+#if defined(CAN2)
 void CAN2_DriverIRQHandler(void)
 {
     assert(s_flexcanHandle[2]);
@@ -1326,7 +1361,7 @@ void CAN2_DriverIRQHandler(void)
 }
 #endif
 
-#if (FSL_FEATURE_SOC_FLEXCAN_COUNT > 3)
+#if defined(CAN3)
 void CAN3_DriverIRQHandler(void)
 {
     assert(s_flexcanHandle[3]);
@@ -1335,7 +1370,7 @@ void CAN3_DriverIRQHandler(void)
 }
 #endif
 
-#if (FSL_FEATURE_SOC_FLEXCAN_COUNT > 4)
+#if defined(CAN4)
 void CAN4_DriverIRQHandler(void)
 {
     assert(s_flexcanHandle[4]);
@@ -1343,3 +1378,30 @@ void CAN4_DriverIRQHandler(void)
     s_flexcanIsr(CAN4, s_flexcanHandle[4]);
 }
 #endif
+
+#if defined(DMA_CAN0)
+void DMA_FLEXCAN0_DriverIRQHandler(void)
+{
+    assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN0)]);
+
+    s_flexcanIsr(DMA_CAN0, s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN0)]);
+}
+#endif
+
+#if defined(DMA_CAN1)
+void DMA_FLEXCAN1_DriverIRQHandler(void)
+{
+    assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN1)]);
+
+    s_flexcanIsr(DMA_CAN0, s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN1)]);
+}
+#endif
+
+#if defined(DMA_CAN2)
+void DMA_FLEXCAN2_DriverIRQHandler(void)
+{
+    assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN2)]);
+
+    s_flexcanIsr(DMA_CAN2, s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN2)]);
+}
+#endif
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.h
index 13c28f357d4..118badf58fb 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,15 +37,14 @@
  * @{
  */
 
-
 /******************************************************************************
  * Definitions
  *****************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief FlexCAN driver version 2.1.0. */
-#define FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*! @brief FlexCAN driver version 2.2.0. */
+#define FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
 /*@}*/
 
 /*! @brief FlexCAN Frame ID helper macro. */
@@ -69,19 +68,18 @@
      (FLEXCAN_ID_STD(id) << 1)) /*!< Standard Rx FIFO Mask helper macro Type A helper macro. */
 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide)                     \
     (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
-     (FLEXCAN_ID_STD(id) << 16)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */
+     (((uint32_t)(id) & 0x7FF) << 19)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */
 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide)                      \
     (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \
-     FLEXCAN_ID_STD(id)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */
+     (((uint32_t)(id) & 0x7FF) << 3)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */
 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id) \
-    ((FLEXCAN_ID_STD(id) & 0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */
-#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id)                                                                 \
-    ((FLEXCAN_ID_STD(id) & 0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. \
-                                                */
+    (((uint32_t)(id) & 0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */
+#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id) \
+    (((uint32_t)(id) & 0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. */
 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id) \
-    ((FLEXCAN_ID_STD(id) & 0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */
+    (((uint32_t)(id) & 0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */
 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) \
-    ((FLEXCAN_ID_STD(id) & 0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */
+    (((uint32_t)(id) & 0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */
 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide)                          \
     (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
      (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */
@@ -157,7 +155,7 @@ enum _flexcan_status
     kStatus_FLEXCAN_RxFifoBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 6),     /*!< Rx Message FIFO is Busy. */
     kStatus_FLEXCAN_RxFifoIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 7),     /*!< Rx Message FIFO is Idle. */
     kStatus_FLEXCAN_RxFifoOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 8), /*!< Rx Message FIFO is overflowed. */
-    kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 0),  /*!< Rx Message FIFO is almost overflowed. */
+    kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 9),  /*!< Rx Message FIFO is almost overflowed. */
     kStatus_FLEXCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_FLEXCAN, 10),   /*!< FlexCAN Module Error and Status. */
     kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 11),     /*!< UnHadled Interrupt asserted. */
 };
@@ -176,12 +174,14 @@ typedef enum _flexcan_frame_type
     kFLEXCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */
 } flexcan_frame_type_t;
 
+#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE
 /*! @brief FlexCAN clock source. */
 typedef enum _flexcan_clock_source
 {
     kFLEXCAN_ClkSrcOsc = 0x0U,  /*!< FlexCAN Protocol Engine clock from Oscillator. */
     kFLEXCAN_ClkSrcPeri = 0x1U, /*!< FlexCAN Protocol Engine clock from Peripheral Clock. */
 } flexcan_clock_source_t;
+#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */
 
 /*! @brief FlexCAN Rx Fifo Filter type. */
 typedef enum _flexcan_rx_fifo_filter_type
@@ -195,7 +195,7 @@ typedef enum _flexcan_rx_fifo_filter_type
 } flexcan_rx_fifo_filter_type_t;
 
 /*!
- * @brief FlexCAN Rx FIFO priority
+ * @brief FlexCAN Rx FIFO priority.
  *
  * The matching process starts from the Rx MB(or Rx FIFO) with higher priority.
  * If no MB(or Rx FIFO filter) is satisfied, the matching process goes on with
@@ -326,7 +326,9 @@ typedef struct _flexcan_frame
 typedef struct _flexcan_config
 {
     uint32_t baudRate;             /*!< FlexCAN baud rate in bps. */
+#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE
     flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */
+#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */
     uint8_t maxMbNum;              /*!< The maximum number of Message Buffers used by user. */
     bool enableLoopBack;           /*!< Enable or Disable Loop Back Self Test Mode. */
     bool enableSelfWakeup;         /*!< Enable or Disable Self Wakeup Mode. */
@@ -366,7 +368,7 @@ typedef struct _flexcan_rx_mb_config
 /*! @brief FlexCAN Rx FIFO configuration structure. */
 typedef struct _flexcan_rx_fifo_config
 {
-    uint32_t *idFilterTable;                    /*!< Pointer to FlexCAN Rx FIFO identifier filter table. */
+    uint32_t *idFilterTable;                    /*!< Pointer to the FlexCAN Rx FIFO identifier filter table. */
     uint8_t idFilterNum;                        /*!< The quantity of filter elements. */
     flexcan_rx_fifo_filter_type_t idFilterType; /*!< The FlexCAN Rx FIFO Filter type. */
     flexcan_rx_fifo_priority_t priority;        /*!< The FlexCAN Rx FIFO receive priority. */
@@ -431,7 +433,7 @@ extern "C" {
  *
  * This function initializes the FlexCAN module with user-defined settings.
  * This example shows how to set up the flexcan_config_t parameters and how
- * to call the FLEXCAN_Init function by passing in these parameters:
+ * to call the FLEXCAN_Init function by passing in these parameters.
  *  @code
  *   flexcan_config_t flexcanConfig;
  *   flexcanConfig.clkSrc            = kFLEXCAN_ClkSrcOsc;
@@ -445,7 +447,7 @@ extern "C" {
  *   @endcode
  *
  * @param base FlexCAN peripheral base address.
- * @param config Pointer to user-defined configuration structure.
+ * @param config Pointer to the user-defined configuration structure.
  * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz.
  */
 void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz);
@@ -453,18 +455,18 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc
 /*!
  * @brief De-initializes a FlexCAN instance.
  *
- * This function disable the FlexCAN module clock and set all register value
- * to reset value.
+ * This function disables the FlexCAN module clock and sets all register values
+ * to the reset value.
  *
  * @param base FlexCAN peripheral base address.
  */
 void FLEXCAN_Deinit(CAN_Type *base);
 
 /*!
- * @brief Get the default configuration structure.
+ * @brief Gets the default configuration structure.
  *
- * This function initializes the FlexCAN configuration structure to default value. The default
- * value are:
+ * This function initializes the FlexCAN configuration structure to default values. The default
+ * values are as follows.
  *   flexcanConfig->clkSrc            = KFLEXCAN_ClkSrcOsc;
  *   flexcanConfig->baudRate          = 125000U;
  *   flexcanConfig->maxMbNum          = 16;
@@ -473,7 +475,7 @@ void FLEXCAN_Deinit(CAN_Type *base);
  *   flexcanConfig->enableIndividMask = false;
  *   flexcanConfig->enableDoze        = false;
  *
- * @param config Pointer to FlexCAN configuration structure.
+ * @param config Pointer to the FlexCAN configuration structure.
  */
 void FLEXCAN_GetDefaultConfig(flexcan_config_t *config);
 
@@ -503,7 +505,7 @@ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *conf
 /*!
  * @brief Sets the FlexCAN receive message buffer global mask.
  *
- * This function sets the global mask for FlexCAN message buffer in a matching process.
+ * This function sets the global mask for the FlexCAN message buffer in a matching process.
  * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init().
  *
  * @param base FlexCAN peripheral base address.
@@ -524,12 +526,12 @@ void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask);
 /*!
  * @brief Sets the FlexCAN receive individual mask.
  *
- * This function sets the individual mask for FlexCAN matching process.
- * The configuration is only effective when the Rx individual mask is enabled in FLEXCAN_Init().
- * If Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer.
- * If Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to
- * the Rx Filter with same index. What calls for special attention is that only the first 32
- * individual masks can be used as Rx FIFO filter mask.
+ * This function sets the individual mask for the FlexCAN matching process.
+ * The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init().
+ * If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer.
+ * If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to
+ * the Rx Filter with the same index. Note that only the first 32
+ * individual masks can be used as the Rx FIFO filter mask.
  *
  * @param base FlexCAN peripheral base address.
  * @param maskIdx The Index of individual Mask.
@@ -545,7 +547,7 @@ void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask)
  *
  * @param base FlexCAN peripheral base address.
  * @param mbIdx The Message Buffer index.
- * @param enable Enable/Disable Tx Message Buffer.
+ * @param enable Enable/disable Tx Message Buffer.
  *               - true: Enable Tx Message Buffer.
  *               - false: Disable Tx Message Buffer.
  */
@@ -559,8 +561,8 @@ void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable);
  *
  * @param base FlexCAN peripheral base address.
  * @param mbIdx The Message Buffer index.
- * @param config Pointer to FlexCAN Message Buffer configuration structure.
- * @param enable Enable/Disable Rx Message Buffer.
+ * @param config Pointer to the FlexCAN Message Buffer configuration structure.
+ * @param enable Enable/disable Rx Message Buffer.
  *               - true: Enable Rx Message Buffer.
  *               - false: Disable Rx Message Buffer.
  */
@@ -572,8 +574,8 @@ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_co
  * This function configures the Rx FIFO with given Rx FIFO configuration.
  *
  * @param base FlexCAN peripheral base address.
- * @param config Pointer to FlexCAN Rx FIFO configuration structure.
- * @param enable Enable/Disable Rx FIFO.
+ * @param config Pointer to the FlexCAN Rx FIFO configuration structure.
+ * @param enable Enable/disable Rx FIFO.
  *               - true: Enable Rx FIFO.
  *               - false: Disable Rx FIFO.
  */
@@ -676,7 +678,7 @@ static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint32_t mask)
 #endif
 {
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-    base->IFLAG1 = (uint32_t)(mask & 0xFFFFFFFF);
+    base->IFLAG1 = (uint32_t)(mask & 0xFFFFFFFFU);
     base->IFLAG2 = (uint32_t)(mask >> 32);
 #else
     base->IFLAG1 = mask;
@@ -691,9 +693,9 @@ static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint32_t mask)
  */
 
 /*!
- * @brief Enables FlexCAN interrupts according to provided mask.
+ * @brief Enables FlexCAN interrupts according to the provided mask.
  *
- * This function enables the FlexCAN interrupts according to provided mask. The mask
+ * This function enables the FlexCAN interrupts according to the provided mask. The mask
  * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable.
  *
  * @param base FlexCAN peripheral base address.
@@ -712,9 +714,9 @@ static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask)
 }
 
 /*!
- * @brief Disables FlexCAN interrupts according to provided mask.
+ * @brief Disables FlexCAN interrupts according to the provided mask.
  *
- * This function disables the FlexCAN interrupts according to provided mask. The mask
+ * This function disables the FlexCAN interrupts according to the provided mask. The mask
  * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable.
  *
  * @param base FlexCAN peripheral base address.
@@ -735,7 +737,7 @@ static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask)
 /*!
  * @brief Enables FlexCAN Message Buffer interrupts.
  *
- * This function enables the interrupts of given Message Buffers
+ * This function enables the interrupts of given Message Buffers.
  *
  * @param base FlexCAN peripheral base address.
  * @param mask The ORed FlexCAN Message Buffer mask.
@@ -747,7 +749,7 @@ static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint32_t mask)
 #endif
 {
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-    base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFF);
+    base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFFU);
     base->IMASK2 |= (uint32_t)(mask >> 32);
 #else
     base->IMASK1 |= mask;
@@ -757,7 +759,7 @@ static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint32_t mask)
 /*!
  * @brief Disables FlexCAN Message Buffer interrupts.
  *
- * This function disables the interrupts of given Message Buffers
+ * This function disables the interrupts of given Message Buffers.
  *
  * @param base FlexCAN peripheral base address.
  * @param mask The ORed FlexCAN Message Buffer mask.
@@ -769,7 +771,7 @@ static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint32_t mask)
 #endif
 {
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
-    base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFF));
+    base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFFU));
     base->IMASK2 &= ~((uint32_t)(mask >> 32));
 #else
     base->IMASK1 &= ~mask;
@@ -846,7 +848,7 @@ static inline void FLEXCAN_Enable(CAN_Type *base, bool enable)
 }
 
 /*!
- * @brief Writes a FlexCAN Message to Transmit Message Buffer.
+ * @brief Writes a FlexCAN Message to the Transmit Message Buffer.
  *
  * This function writes a CAN Message to the specified Transmit Message Buffer
  * and changes the Message Buffer state to start CAN Message transmit. After
@@ -938,7 +940,7 @@ status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rx
 /*!
  * @brief Initializes the FlexCAN handle.
  *
- * This function initializes the FlexCAN handle which can be used for other FlexCAN
+ * This function initializes the FlexCAN handle, which can be used for other FlexCAN
  * transactional APIs. Usually, for a specified FlexCAN instance,
  * call this API once to get the initialized handle.
  *
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ftm.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ftm.c
index 85dc2194254..9cca44b0e41 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ftm.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ftm.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -72,8 +72,10 @@ static void FTM_SetReloadPoints(FTM_Type *base, uint32_t reloadPoints);
 /*! @brief Pointers to FTM bases for each instance. */
 static FTM_Type *const s_ftmBases[] = FTM_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to FTM clocks for each instance. */
 static const clock_ip_name_t s_ftmClocks[] = FTM_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
@@ -228,8 +230,10 @@ status_t FTM_Init(FTM_Type *base, const ftm_config_t *config)
         return kStatus_Fail;
     }
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Ungate the FTM clock*/
     CLOCK_EnableClock(s_ftmClocks[FTM_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Configure the fault mode, enable FTM mode and disable write protection */
     base->MODE = FTM_MODE_FAULTM(config->faultMode) | FTM_MODE_FTMEN_MASK | FTM_MODE_WPDIS_MASK;
@@ -266,7 +270,13 @@ status_t FTM_Init(FTM_Type *base, const ftm_config_t *config)
 #endif /* FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER */
 
     /* FTM deadtime insertion control */
-    base->DEADTIME = (FTM_DEADTIME_DTPS(config->deadTimePrescale) | FTM_DEADTIME_DTVAL(config->deadTimeValue));
+    base->DEADTIME = (0u | 
+#if defined(FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE) && (FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE)
+                        /* Has extended deadtime value register) */
+                        FTM_DEADTIME_DTVALEX(config->deadTimeValue >> 6) | 
+#endif /* FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE */
+                        FTM_DEADTIME_DTPS(config->deadTimePrescale) | 
+                        FTM_DEADTIME_DTVAL(config->deadTimeValue));
 
     /* FTM fault filter value */
     reg = base->FLTCTRL;
@@ -282,8 +292,10 @@ void FTM_Deinit(FTM_Type *base)
     /* Set clock source to none to disable counter */
     base->SC &= ~(FTM_SC_CLKS_MASK);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Gate the FTM clock */
     CLOCK_DisableClock(s_ftmClocks[FTM_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void FTM_GetDefaultConfig(ftm_config_t *config)
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ftm.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ftm.h
index 2fb1c08e49c..8db81a633ac 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ftm.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_ftm.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,7 +37,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -45,8 +44,8 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_FTM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
-/*@}*/
+#define FSL_FTM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */
+                                                       /*@}*/
 
 /*!
  * @brief List of FTM channels
@@ -162,7 +161,7 @@ typedef struct _ftm_phase_param
 typedef struct _ftm_fault_param
 {
     bool enableFaultInput; /*!< True: Fault input is enabled; false: Fault input is disabled */
-    bool faultLevel;       /*!< True: Fault polarity is active low i.e., '0' indicates a fault;
+    bool faultLevel;       /*!< True: Fault polarity is active low; in other words, '0' indicates a fault;
                                 False: Fault polarity is active high */
     bool useFaultFilter;   /*!< True: Use the filtered fault signal;
                                 False: Use the direct path from fault input */
@@ -310,6 +309,17 @@ typedef enum _ftm_status_flags
     kFTM_ReloadFlag = (1U << 11)       /*!< Reload Flag; Available only on certain SoC's */
 } ftm_status_flags_t;
 
+/*!
+ * @brief List of FTM Quad Decoder flags.
+ */
+enum _ftm_quad_decoder_flags
+{
+    kFTM_QuadDecoderCountingIncreaseFlag = FTM_QDCTRL_QUADIR_MASK, /*!< Counting direction is increasing (FTM counter
+                                                                        increment), or the direction is decreasing. */
+    kFTM_QuadDecoderCountingOverflowOnTopFlag = FTM_QDCTRL_TOFDIR_MASK, /*!< Indicates if the TOF bit was set on the top
+                                                                             or the bottom of counting. */
+};
+
 /*!
  * @brief FTM configuration structure
  *
@@ -333,7 +343,9 @@ typedef struct _ftm_config
     ftm_fault_mode_t faultMode;               /*!< FTM fault control mode */
     uint8_t faultFilterValue;                 /*!< Fault input filter value */
     ftm_deadtime_prescale_t deadTimePrescale; /*!< The dead time prescalar value */
-    uint8_t deadTimeValue;                    /*!< The dead time value */
+    uint32_t deadTimeValue;                   /*!< The dead time value
+                                                   deadTimeValue's available range is 0-1023 when register has DTVALEX,
+                                                   otherwise its available range is 0-63. */
     uint32_t extTriggers;                     /*!< External triggers to enable. Multiple trigger sources can be
                                                    enabled by providing an OR'ed list of options available in
                                                    enumeration ::ftm_external_trigger_t. */
@@ -359,7 +371,7 @@ extern "C" {
 /*!
  * @brief Ungates the FTM clock and configures the peripheral for basic operation.
  *
- * @note This API should be called at the beginning of the application using the FTM driver.
+ * @note This API should be called at the beginning of the application which is using the FTM driver.
  *
  * @param base   FTM peripheral base address
  * @param config Pointer to the user configuration structure.
@@ -508,19 +520,6 @@ void FTM_SetupDualEdgeCapture(FTM_Type *base,
 
 /*! @}*/
 
-/*!
- * @brief Configures the parameters and activates the quadrature decoder mode.
- *
- * @param base         FTM peripheral base address
- * @param phaseAParams Phase A configuration parameters
- * @param phaseBParams Phase B configuration parameters
- * @param quadMode     Selects encoding mode used in quadrature decoder mode
- */
-void FTM_SetupQuadDecode(FTM_Type *base,
-                         const ftm_phase_params_t *phaseAParams,
-                         const ftm_phase_params_t *phaseBParams,
-                         ftm_quad_decode_mode_t quadMode);
-
 /*!
  * @brief Sets up the working of the FTM fault protection.
  *
@@ -593,6 +592,48 @@ void FTM_ClearStatusFlags(FTM_Type *base, uint32_t mask);
 
 /*! @}*/
 
+/*!
+ * @name Read and write the timer period
+ * @{
+ */
+
+/*!
+ * @brief Sets the timer period in units of ticks.
+ *
+ * Timers counts from 0 until it equals the count value set here. The count value is written to
+ * the MOD register.
+ *
+ * @note
+ * 1. This API allows the user to use the FTM module as a timer. Do not mix usage
+ *    of this API with FTM's PWM setup API's.
+ * 2. Call the utility macros provided in the fsl_common.h to convert usec or msec to ticks.
+ *
+ * @param base FTM peripheral base address
+ * @param ticks A timer period in units of ticks, which should be equal or greater than 1.
+ */
+static inline void FTM_SetTimerPeriod(FTM_Type *base, uint32_t ticks)
+{
+    base->MOD = ticks;
+}
+
+/*!
+ * @brief Reads the current timer counting value.
+ *
+ * This function returns the real-time timer counting value in a range from 0 to a
+ * timer period.
+ *
+ * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.
+ *
+ * @param base FTM peripheral base address
+ *
+ * @return The current counter value in ticks
+ */
+static inline uint32_t FTM_GetCurrentTimerCount(FTM_Type *base)
+{
+    return (uint32_t)((base->CNT & FTM_CNT_COUNT_MASK) >> FTM_CNT_COUNT_SHIFT);
+}
+
+/*! @}*/
 /*!
  * @name Timer Start and Stop
  * @{
@@ -711,7 +752,7 @@ static inline void FTM_SetOutputMask(FTM_Type *base, ftm_chnl_t chnlNumber, bool
 
 #if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT)
 /*!
- * @brief Allows user to enable an output on an FTM channel.
+ * @brief Allows users to enable an output on an FTM channel.
  *
  * To enable the PWM channel output call this function with val=true. For input mode,
  * call this function with val=false.
@@ -816,6 +857,76 @@ static inline void FTM_SetInvertEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber
 
 /*! @}*/
 
+/*!
+ * @name Quad Decoder
+ * @{
+ */
+
+/*!
+ * @brief Configures the parameters and activates the quadrature decoder mode.
+ *
+ * @param base         FTM peripheral base address
+ * @param phaseAParams Phase A configuration parameters
+ * @param phaseBParams Phase B configuration parameters
+ * @param quadMode     Selects encoding mode used in quadrature decoder mode
+ */
+void FTM_SetupQuadDecode(FTM_Type *base,
+                         const ftm_phase_params_t *phaseAParams,
+                         const ftm_phase_params_t *phaseBParams,
+                         ftm_quad_decode_mode_t quadMode);
+
+/*!
+ * @brief Gets the FTM Quad Decoder flags.
+ *
+ * @param base FTM peripheral base address.
+ * @return Flag mask of FTM Quad Decoder, see #_ftm_quad_decoder_flags.
+ */
+static inline uint32_t FTM_GetQuadDecoderFlags(FTM_Type *base)
+{
+    return base->QDCTRL & (FTM_QDCTRL_QUADIR_MASK | FTM_QDCTRL_TOFDIR_MASK);
+}
+
+/*!
+ * @brief Sets the modulo values for Quad Decoder.
+ *
+ * The modulo values configure the minimum and maximum values that the Quad decoder counter can reach. After the counter goes
+ * over, the counter value goes to the other side and decrease/increase again.
+ *
+ * @param base FTM peripheral base address.
+ * @param startValue The low limit value for Quad Decoder counter.
+ * @param overValue The high limit value for Quad Decoder counter.
+ */
+static inline void FTM_SetQuadDecoderModuloValue(FTM_Type *base, uint32_t startValue, uint32_t overValue)
+{
+    base->CNTIN = startValue;
+    base->MOD = overValue;
+}
+
+/*!
+ * @brief Gets the current Quad Decoder counter value.
+ *
+ * @param base FTM peripheral base address.
+ * @return Current quad Decoder counter value.
+ */
+static inline uint32_t FTM_GetQuadDecoderCounterValue(FTM_Type *base)
+{
+    return base->CNT;
+}
+
+/*!
+ * @brief Clears the current Quad Decoder counter value.
+ *
+ * The counter is set as the initial value.
+ *
+ * @param base FTM peripheral base address.
+ */
+static inline void FTM_ClearQuadDecoderCounterValue(FTM_Type *base)
+{
+    base->CNT = base->CNTIN;
+}
+
+/*! @}*/
+
 /*!
  * @brief Enables or disables the FTM software trigger for PWM synchronization.
  *
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_gpio.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_gpio.c
index 8fc068f2d6a..b40ee3ac11c 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_gpio.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_gpio.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -57,7 +57,7 @@ static uint32_t GPIO_GetInstance(GPIO_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_GPIO_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++)
     {
         if (s_gpioBases[instance] == base)
         {
@@ -65,7 +65,7 @@ static uint32_t GPIO_GetInstance(GPIO_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_GPIO_COUNT);
+    assert(instance < ARRAY_SIZE(s_gpioBases));
 
     return instance;
 }
@@ -103,6 +103,14 @@ void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask)
     portBase->ISFR = mask;
 }
 
+#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
+void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute)
+{
+    base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) |
+                 ((uint32_t)attribute << GPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB3_SHIFT);
+}
+#endif
+
 #if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
 
 /*******************************************************************************
@@ -130,7 +138,7 @@ static uint32_t FGPIO_GetInstance(FGPIO_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_FGPIO_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_fgpioBases); instance++)
     {
         if (s_fgpioBases[instance] == base)
         {
@@ -138,7 +146,7 @@ static uint32_t FGPIO_GetInstance(FGPIO_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_FGPIO_COUNT);
+    assert(instance < ARRAY_SIZE(s_fgpioBases));
 
     return instance;
 }
@@ -176,4 +184,12 @@ void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask)
     portBase->ISFR = mask;
 }
 
+#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER
+void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute)
+{
+    base->GACR = (attribute << FGPIO_GACR_ACB0_SHIFT) | (attribute << FGPIO_GACR_ACB1_SHIFT) |
+                 (attribute << FGPIO_GACR_ACB2_SHIFT) | (attribute << FGPIO_GACR_ACB3_SHIFT);
+}
+#endif
+
 #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_gpio.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_gpio.h
index 6eaaaa08744..410e2b8ee46 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_gpio.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_gpio.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,14 +12,14 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
@@ -38,38 +38,60 @@
  * @{
  */
 
-/*! @file */
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief GPIO driver version 2.1.0. */
-#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*! @brief GPIO driver version 2.1.1. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
 /*@}*/
 
-/*! @brief GPIO direction definition*/
+/*! @brief GPIO direction definition */
 typedef enum _gpio_pin_direction
 {
     kGPIO_DigitalInput = 0U,  /*!< Set current pin as digital input*/
     kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
 } gpio_pin_direction_t;
 
+#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
+/*! @brief GPIO checker attribute */
+typedef enum _gpio_checker_attribute
+{
+    kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW =
+        0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW =
+        0x01U, /*!< User nonsecure:Read;       User Secure:Read+Write; Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW =
+        0x02U, /*!< User nonsecure:None;       User Secure:Read+Write; Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW =
+        0x03U, /*!< User nonsecure:Read;       User Secure:Read;       Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW =
+        0x04U, /*!< User nonsecure:None;       User Secure:Read;       Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW =
+        0x05U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR =
+        0x06U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:Read */
+    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN =
+        0x07U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:None */
+    kGPIO_IgnoreAttributeCheck = 0x10U, /*!< Ignores the attribute check */
+} gpio_checker_attribute_t;
+#endif
+
 /*!
  * @brief The GPIO pin configuration structure.
  *
- * Every pin can only be configured as either output pin or input pin at a time.
- * If configured as a input pin, then leave the outputConfig unused
- * Note : In some cases, the corresponding port property should be configured in advance
- *        with the PORT_SetPinConfig()
+ * Each pin can only be configured as either an output pin or an input pin at a time.
+ * If configured as an input pin, leave the outputConfig unused.
+ * Note that in some use cases, the corresponding port property should be configured in advance
+ *        with the PORT_SetPinConfig().
  */
 typedef struct _gpio_pin_config
 {
-    gpio_pin_direction_t pinDirection; /*!< gpio direction, input or output */
-    /* Output configurations, please ignore if configured as a input one */
-    uint8_t outputLogic; /*!< Set default output logic, no use in input */
+    gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
+    /* Output configurations; ignore if configured as an input pin */
+    uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */
 } gpio_pin_config_t;
 
 /*! @} */
@@ -93,10 +115,10 @@ extern "C" {
 /*!
  * @brief Initializes a GPIO pin used by the board.
  *
- * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
+ * To initialize the GPIO, define a pin configuration, as either input or output, in the user file.
  * Then, call the GPIO_PinInit() function.
  *
- * This is an example to define an input pin or output pin configuration:
+ * This is an example to define an input pin or an output pin configuration.
  * @code
  * // Define a digital input pin configuration,
  * gpio_pin_config_t config =
@@ -112,7 +134,7 @@ extern "C" {
  * }
  * @endcode
  *
- * @param base   GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
+ * @param base   GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
  * @param pin    GPIO port pin number
  * @param config GPIO pin configuration pointer
  */
@@ -126,29 +148,29 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config
 /*!
  * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0.
  *
- * @param base    GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param pin     GPIO pin's number
+ * @param base    GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param pin     GPIO pin number
  * @param output  GPIO pin output logic level.
- *        - 0: corresponding pin output low logic level.
- *        - 1: corresponding pin output high logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
  */
 static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output)
 {
     if (output == 0U)
     {
-        base->PCOR = 1 << pin;
+        base->PCOR = 1U << pin;
     }
     else
     {
-        base->PSOR = 1 << pin;
+        base->PSOR = 1U << pin;
     }
 }
 
 /*!
  * @brief Sets the output level of the multiple GPIO pins to the logic 1.
  *
- * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pins' numbers macro
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
  */
 static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask)
 {
@@ -158,8 +180,8 @@ static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask)
 /*!
  * @brief Sets the output level of the multiple GPIO pins to the logic 0.
  *
- * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pins' numbers macro
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
  */
 static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask)
 {
@@ -167,10 +189,10 @@ static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask)
 }
 
 /*!
- * @brief Reverses current output logic of the multiple GPIO pins.
+ * @brief Reverses the current output logic of the multiple GPIO pins.
  *
- * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pins' numbers macro
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
  */
 static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask)
 {
@@ -182,13 +204,13 @@ static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask)
 /*@{*/
 
 /*!
- * @brief Reads the current input value of the whole GPIO port.
+ * @brief Reads the current input value of the GPIO port.
  *
- * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param pin     GPIO pin's number
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param pin     GPIO pin number
  * @retval GPIO port input value
- *        - 0: corresponding pin input low logic level.
- *        - 1: corresponding pin input high logic level.
+ *        - 0: corresponding pin input low-logic level.
+ *        - 1: corresponding pin input high-logic level.
  */
 static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin)
 {
@@ -200,7 +222,7 @@ static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin)
 /*@{*/
 
 /*!
- * @brief Reads whole GPIO port interrupt status flag.
+ * @brief Reads the GPIO port interrupt status flag.
  *
  * If a pin is configured to generate the DMA request, the corresponding flag
  * is cleared automatically at the completion of the requested DMA transfer.
@@ -208,20 +230,34 @@ static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin)
  * If configured for a level sensitive interrupt that remains asserted, the flag
  * is set again immediately.
  *
- * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @retval Current GPIO port interrupt status flag, for example, 0x00010001 means the
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the
  *         pin 0 and 17 have the interrupt.
  */
 uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base);
 
 /*!
- * @brief Clears multiple GPIO pins' interrupt status flag.
+ * @brief Clears multiple GPIO pin interrupt status flags.
  *
- * @param base GPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask GPIO pins' numbers macro
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
  */
 void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask);
 
+#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
+/*!
+ * @brief The GPIO module supports a device-specific number of data ports, organized as 32-bit
+ * words. Each 32-bit data port includes a GACR register, which defines the byte-level
+ * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
+ * bytes in the GACR follow a standard little endian
+ * data convention.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute);
+#endif
+
 /*@}*/
 /*! @} */
 
@@ -231,10 +267,10 @@ void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask);
  */
 
 /*
- * Introduce the FGPIO feature.
+ * Introduces the FGPIO feature.
  *
- * The FGPIO features are only support on some of Kinetis chips. The FGPIO registers are aliased to the IOPORT
- * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and will therefore
+ * The FGPIO features are only support on some Kinetis MCUs. The FGPIO registers are aliased to the IOPORT
+ * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and
  * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO.
  */
 
@@ -246,10 +282,10 @@ void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask);
 /*!
  * @brief Initializes a FGPIO pin used by the board.
  *
- * To initialize the FGPIO driver, define a pin configuration, either input or output, in the user file.
+ * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file.
  * Then, call the FGPIO_PinInit() function.
  *
- * This is an example to define an input pin or output pin configuration:
+ * This is an example to define an input pin or an output pin configuration:
  * @code
  * // Define a digital input pin configuration,
  * gpio_pin_config_t config =
@@ -265,7 +301,7 @@ void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask);
  * }
  * @endcode
  *
- * @param base   FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
+ * @param base   FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
  * @param pin    FGPIO port pin number
  * @param config FGPIO pin configuration pointer
  */
@@ -279,11 +315,11 @@ void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *conf
 /*!
  * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0.
  *
- * @param base    FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param pin     FGPIO pin's number
+ * @param base    FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param pin     FGPIO pin number
  * @param output  FGPIOpin output logic level.
- *        - 0: corresponding pin output low logic level.
- *        - 1: corresponding pin output high logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
  */
 static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output)
 {
@@ -300,8 +336,8 @@ static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t
 /*!
  * @brief Sets the output level of the multiple FGPIO pins to the logic 1.
  *
- * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask FGPIO pins' numbers macro
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
  */
 static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask)
 {
@@ -311,8 +347,8 @@ static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask)
 /*!
  * @brief Sets the output level of the multiple FGPIO pins to the logic 0.
  *
- * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask FGPIO pins' numbers macro
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
  */
 static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask)
 {
@@ -320,10 +356,10 @@ static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask)
 }
 
 /*!
- * @brief Reverses current output logic of the multiple FGPIO pins.
+ * @brief Reverses the current output logic of the multiple FGPIO pins.
  *
- * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask FGPIO pins' numbers macro
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
  */
 static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask)
 {
@@ -335,13 +371,13 @@ static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask)
 /*@{*/
 
 /*!
- * @brief Reads the current input value of the whole FGPIO port.
+ * @brief Reads the current input value of the FGPIO port.
  *
- * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param pin  FGPIO pin's number
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param pin  FGPIO pin number
  * @retval FGPIO port input value
- *        - 0: corresponding pin input low logic level.
- *        - 1: corresponding pin input high logic level.
+ *        - 0: corresponding pin input low-logic level.
+ *        - 1: corresponding pin input high-logic level.
  */
 static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin)
 {
@@ -353,28 +389,42 @@ static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin)
 /*@{*/
 
 /*!
- * @brief Reads the whole FGPIO port interrupt status flag.
+ * @brief Reads the FGPIO port interrupt status flag.
  *
- * If a pin is configured to generate the DMA request,  the corresponding flag
+ * If a pin is configured to generate the DMA request, the corresponding flag
  * is cleared automatically at the completion of the requested DMA transfer.
  * Otherwise, the flag remains set until a logic one is written to that flag.
- * If configured for a level sensitive interrupt that remains asserted, the flag
+ * If configured for a level-sensitive interrupt that remains asserted, the flag
  * is set again immediately.
  *
- * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @retval Current FGPIO port interrupt status flags, for example, 0x00010001 means the
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the
  *         pin 0 and 17 have the interrupt.
  */
 uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base);
 
 /*!
- * @brief Clears the multiple FGPIO pins' interrupt status flag.
+ * @brief Clears the multiple FGPIO pin interrupt status flag.
  *
- * @param base FGPIO peripheral base pointer(GPIOA, GPIOB, GPIOC, and so on.)
- * @param mask FGPIO pins' numbers macro
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
  */
 void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask);
 
+#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
+/*!
+ * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit
+ * words. Each 32-bit data port includes a GACR register, which defines the byte-level
+ * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
+ * bytes in the GACR follow a standard little endian
+ * data convention.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
+ */
+void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute);
+#endif
+
 /*@}*/
 
 #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c.c
index e77a3832399..6c9770af256 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -75,6 +75,19 @@ typedef void (*i2c_isr_t)(I2C_Type *base, void *i2cHandle);
  */
 uint32_t I2C_GetInstance(I2C_Type *base);
 
+/*!
+* @brief Set SCL/SDA hold time, this API receives SCL stop hold time, calculate the
+* closest SCL divider and MULT value for the SDA hold time, SCL start and SCL stop
+* hold time. To reduce the ROM size, SDA/SCL hold value mapping table is not provided,
+* assume SCL divider = SCL stop hold value *2 to get the closest SCL divider value and MULT
+* value, then the related SDA hold time, SCL start and SCL stop hold time is used.
+*
+* @param base I2C peripheral base address.
+* @param sourceClock_Hz I2C functional clock frequency in Hertz.
+* @param sclStopHoldTime_ns SCL stop hold time in ns.
+*/
+static void I2C_SetHoldTime(I2C_Type *base, uint32_t sclStopHoldTime_ns, uint32_t sourceClock_Hz);
+
 /*!
  * @brief Set up master transfer, send slave address and decide the initial
  * transfer state.
@@ -125,20 +138,22 @@ static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle);
 static void *s_i2cHandle[FSL_FEATURE_SOC_I2C_COUNT] = {NULL};
 
 /*! @brief SCL clock divider used to calculate baudrate. */
-const uint16_t s_i2cDividerTable[] = {20,   22,   24,   26,   28,   30,   34,   40,   28,   32,   36,   40,  44,
-                                      48,   56,   68,   48,   56,   64,   72,   80,   88,   104,  128,  80,  96,
-                                      112,  128,  144,  160,  192,  240,  160,  192,  224,  256,  288,  320, 384,
-                                      480,  320,  384,  448,  512,  576,  640,  768,  960,  640,  768,  896, 1024,
-                                      1152, 1280, 1536, 1920, 1280, 1536, 1792, 2048, 2304, 2560, 3072, 3840};
+static const uint16_t s_i2cDividerTable[] = {
+    20,  22,  24,  26,   28,   30,   34,   40,   28,   32,   36,   40,   44,   48,   56,   68,
+    48,  56,  64,  72,   80,   88,   104,  128,  80,   96,   112,  128,  144,  160,  192,  240,
+    160, 192, 224, 256,  288,  320,  384,  480,  320,  384,  448,  512,  576,  640,  768,  960,
+    640, 768, 896, 1024, 1152, 1280, 1536, 1920, 1280, 1536, 1792, 2048, 2304, 2560, 3072, 3840};
 
 /*! @brief Pointers to i2c bases for each instance. */
 static I2C_Type *const s_i2cBases[] = I2C_BASE_PTRS;
 
 /*! @brief Pointers to i2c IRQ number for each instance. */
-const IRQn_Type s_i2cIrqs[] = I2C_IRQS;
+static const IRQn_Type s_i2cIrqs[] = I2C_IRQS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to i2c clocks for each instance. */
-const clock_ip_name_t s_i2cClocks[] = I2C_CLOCKS;
+static const clock_ip_name_t s_i2cClocks[] = I2C_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*! @brief Pointer to master IRQ handler for each instance. */
 static i2c_isr_t s_i2cMasterIsr;
@@ -155,7 +170,7 @@ uint32_t I2C_GetInstance(I2C_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_I2C_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_i2cBases); instance++)
     {
         if (s_i2cBases[instance] == base)
         {
@@ -163,16 +178,63 @@ uint32_t I2C_GetInstance(I2C_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_I2C_COUNT);
+    assert(instance < ARRAY_SIZE(s_i2cBases));
 
     return instance;
 }
 
+static void I2C_SetHoldTime(I2C_Type *base, uint32_t sclStopHoldTime_ns, uint32_t sourceClock_Hz)
+{
+    uint32_t multiplier;
+    uint32_t computedSclHoldTime;
+    uint32_t absError;
+    uint32_t bestError = UINT32_MAX;
+    uint32_t bestMult = 0u;
+    uint32_t bestIcr = 0u;
+    uint8_t mult;
+    uint8_t i;
+
+    /* Search for the settings with the lowest error. Mult is the MULT field of the I2C_F register,
+     * and ranges from 0-2. It selects the multiplier factor for the divider. */
+    /* SDA hold time = bus period (s) * mul * SDA hold value. */
+    /* SCL start hold time = bus period (s) * mul * SCL start hold value. */
+    /* SCL stop hold time = bus period (s) * mul * SCL stop hold value. */
+
+    for (mult = 0u; (mult <= 2u) && (bestError != 0); ++mult)
+    {
+        multiplier = 1u << mult;
+
+        /* Scan table to find best match. */
+        for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(s_i2cDividerTable[0]); ++i)
+        {
+            /* Assume SCL hold(stop) value = s_i2cDividerTable[i]/2. */
+            computedSclHoldTime = ((multiplier * s_i2cDividerTable[i]) * 500000000U) / sourceClock_Hz;
+            absError = sclStopHoldTime_ns > computedSclHoldTime ? (sclStopHoldTime_ns - computedSclHoldTime) :
+                                                                  (computedSclHoldTime - sclStopHoldTime_ns);
+
+            if (absError < bestError)
+            {
+                bestMult = mult;
+                bestIcr = i;
+                bestError = absError;
+
+                /* If the error is 0, then we can stop searching because we won't find a better match. */
+                if (absError == 0)
+                {
+                    break;
+                }
+            }
+        }
+    }
+
+    /* Set frequency register based on best settings. */
+    base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr);
+}
+
 static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer)
 {
     status_t result = kStatus_Success;
     i2c_direction_t direction = xfer->direction;
-    uint16_t timeout = UINT16_MAX;
 
     /* Initialize the handle transfer information. */
     handle->transfer = *xfer;
@@ -183,27 +245,13 @@ static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t
     /* Initial transfer state. */
     if (handle->transfer.subaddressSize > 0)
     {
-        handle->state = kSendCommandState;
         if (xfer->direction == kI2C_Read)
         {
             direction = kI2C_Write;
         }
     }
-    else
-    {
-        handle->state = kCheckAddressState;
-    }
 
-    /* Wait until the data register is ready for transmit. */
-    while ((!(base->S & kI2C_TransferCompleteFlag)) && (--timeout))
-    {
-    }
-
-    /* Failed to start the transfer. */
-    if (timeout == 0)
-    {
-        return kStatus_I2C_Timeout;
-    }
+    handle->state = kCheckAddressState;
 
     /* Clear all status before transfer. */
     I2C_MasterClearStatusFlags(base, kClearFlags);
@@ -265,34 +313,41 @@ static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_han
         result = kStatus_Success;
     }
 
-    if (result)
-    {
-        return result;
-    }
-
     /* Handle Check address state to check the slave address is Acked in slave
        probe application. */
     if (handle->state == kCheckAddressState)
     {
         if (statusFlags & kI2C_ReceiveNakFlag)
         {
-            return kStatus_I2C_Nak;
+            result = kStatus_I2C_Addr_Nak;
         }
         else
         {
-            if (handle->transfer.direction == kI2C_Write)
+            if (handle->transfer.subaddressSize > 0)
             {
-                /* Next state, send data. */
-                handle->state = kSendDataState;
+                handle->state = kSendCommandState;
             }
             else
             {
-                /* Next state, receive data begin. */
-                handle->state = kReceiveDataBeginState;
+                if (handle->transfer.direction == kI2C_Write)
+                {
+                    /* Next state, send data. */
+                    handle->state = kSendDataState;
+                }
+                else
+                {
+                    /* Next state, receive data begin. */
+                    handle->state = kReceiveDataBeginState;
+                }
             }
         }
     }
 
+    if (result)
+    {
+        return result;
+    }
+
     /* Run state machine. */
     switch (handle->state)
     {
@@ -375,6 +430,10 @@ static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_han
                     {
                         result = I2C_MasterStop(base);
                     }
+                    else
+                    {
+                        base->C1 |= I2C_C1_TX_MASK;
+                    }
                 }
 
                 /* Send NAK at the last receive byte. */
@@ -407,6 +466,7 @@ static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle)
     {
         s_i2cSlaveIsr(base, handle);
     }
+    __DSB();
 }
 
 void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
@@ -415,12 +475,26 @@ void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uin
 
     /* Temporary register for filter read. */
     uint8_t fltReg;
-#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
-    uint8_t c2Reg;
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    uint8_t s2Reg;
 #endif
-
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable I2C clock. */
     CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset the module. */
+    base->A1 = 0;
+    base->F = 0;
+    base->C1 = 0;
+    base->S = 0xFFU;
+    base->C2 = 0;
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    base->FLT = 0x50U;
+#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
+    base->FLT = 0x40U;
+#endif
+    base->RA = 0;
 
     /* Disable I2C prior to configuring it. */
     base->C1 &= ~(I2C_C1_IICEN_MASK);
@@ -431,14 +505,6 @@ void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uin
     /* Configure baud rate. */
     I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz);
 
-#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
-    /* Configure high drive feature. */
-    c2Reg = base->C2;
-    c2Reg &= ~(I2C_C2_HDRS_MASK);
-    c2Reg |= I2C_C2_HDRS(masterConfig->enableHighDrive);
-    base->C2 = c2Reg;
-#endif
-
     /* Read out the FLT register. */
     fltReg = base->FLT;
 
@@ -455,6 +521,12 @@ void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uin
     /* Write the register value back to the filter register. */
     base->FLT = fltReg;
 
+/* Enable/Disable double buffering. */
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    s2Reg = base->S2 & (~I2C_S2_DFEN_MASK);
+    base->S2 = s2Reg | I2C_S2_DFEN(masterConfig->enableDoubleBuffering);
+#endif
+
     /* Enable the I2C peripheral based on the configuration. */
     base->C1 = I2C_C1_IICEN(masterConfig->enableMaster);
 }
@@ -464,8 +536,10 @@ void I2C_MasterDeinit(I2C_Type *base)
     /* Disable I2C module. */
     I2C_Enable(base, false);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable I2C clock. */
     CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig)
@@ -475,11 +549,6 @@ void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig)
     /* Default baud rate at 100kbps. */
     masterConfig->baudRate_Bps = 100000U;
 
-/* Default pin high drive is disabled. */
-#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
-    masterConfig->enableHighDrive = false;
-#endif
-
 /* Default stop hold enable is disabled. */
 #if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF
     masterConfig->enableStopHold = false;
@@ -488,12 +557,21 @@ void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig)
     /* Default glitch filter value is no filter. */
     masterConfig->glitchFilterWidth = 0U;
 
+/* Default enable double buffering. */
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    masterConfig->enableDoubleBuffering = true;
+#endif
+
     /* Enable the I2C peripheral. */
     masterConfig->enableMaster = true;
 }
 
 void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask)
 {
+#ifdef I2C_HAS_STOP_DETECT
+    uint8_t fltReg;
+#endif
+
     if (mask & kI2C_GlobalInterruptEnable)
     {
         base->C1 |= I2C_C1_IICIE_MASK;
@@ -502,14 +580,28 @@ void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask)
 #if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
     if (mask & kI2C_StopDetectInterruptEnable)
     {
-        base->FLT |= I2C_FLT_STOPIE_MASK;
+        fltReg = base->FLT;
+
+        /* Keep STOPF flag. */
+        fltReg &= ~I2C_FLT_STOPF_MASK;
+
+        /* Stop detect enable. */
+        fltReg |= I2C_FLT_STOPIE_MASK;
+        base->FLT = fltReg;
     }
 #endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */
 
 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
     if (mask & kI2C_StartStopDetectInterruptEnable)
     {
-        base->FLT |= I2C_FLT_SSIE_MASK;
+        fltReg = base->FLT;
+
+        /* Keep STARTF and STOPF flags. */
+        fltReg &= ~(I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK);
+
+        /* Start and stop detect enable. */
+        fltReg |= I2C_FLT_SSIE_MASK;
+        base->FLT = fltReg;
     }
 #endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
 }
@@ -524,14 +616,14 @@ void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask)
 #if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
     if (mask & kI2C_StopDetectInterruptEnable)
     {
-        base->FLT &= ~I2C_FLT_STOPIE_MASK;
+        base->FLT &= ~(I2C_FLT_STOPIE_MASK | I2C_FLT_STOPF_MASK);
     }
 #endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */
 
 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
     if (mask & kI2C_StartStopDetectInterruptEnable)
     {
-        base->FLT &= ~I2C_FLT_SSIE_MASK;
+        base->FLT &= ~(I2C_FLT_SSIE_MASK | I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK);
     }
 #endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
 }
@@ -623,7 +715,7 @@ status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_
         base->F = savedMult & (~I2C_F_MULT_MASK);
 
         /* We are already in a transfer, so send a repeated start. */
-        base->C1 |= I2C_C1_RSTA_MASK;
+        base->C1 |= I2C_C1_RSTA_MASK | I2C_C1_TX_MASK;
 
         /* Restore the multiplier factor. */
         base->F = savedMult;
@@ -690,7 +782,7 @@ uint32_t I2C_MasterGetStatusFlags(I2C_Type *base)
     return statusFlags;
 }
 
-status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize)
+status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags)
 {
     status_t result = kStatus_Success;
     uint8_t statusFlags = 0;
@@ -728,7 +820,7 @@ status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t t
             result = kStatus_I2C_ArbitrationLost;
         }
 
-        if (statusFlags & kI2C_ReceiveNakFlag)
+        if ((statusFlags & kI2C_ReceiveNakFlag) && txSize)
         {
             base->S = kI2C_ReceiveNakFlag;
             result = kStatus_I2C_Nak;
@@ -741,10 +833,19 @@ status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t t
         }
     }
 
+    if (((result == kStatus_Success) && (!(flags & kI2C_TransferNoStopFlag))) || (result == kStatus_I2C_Nak))
+    {
+        /* Clear the IICIF flag. */
+        base->S = kI2C_IntPendingFlag;
+
+        /* Send stop. */
+        result = I2C_MasterStop(base);
+    }
+
     return result;
 }
 
-status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize)
+status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags)
 {
     status_t result = kStatus_Success;
     volatile uint8_t dummy = 0;
@@ -786,8 +887,16 @@ status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize)
         /* Single byte use case. */
         if (rxSize == 0)
         {
-            /* Read the final byte. */
-            result = I2C_MasterStop(base);
+            if (!(flags & kI2C_TransferNoStopFlag))
+            {
+                /* Issue STOP command before reading last byte. */
+                result = I2C_MasterStop(base);
+            }
+            else
+            {
+                /* Change direction to Tx to avoid extra clocks. */
+                base->C1 |= I2C_C1_TX_MASK;
+            }
         }
 
         if (rxSize == 1)
@@ -840,19 +949,42 @@ status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer)
         return result;
     }
 
+    while (!(base->S & kI2C_IntPendingFlag))
+    {
+    }
+
+    /* Check if there's transfer error. */
+    result = I2C_CheckAndClearError(base, base->S);
+
+    /* Return if error. */
+    if (result)
+    {
+        if (result == kStatus_I2C_Nak)
+        {
+            result = kStatus_I2C_Addr_Nak;
+
+            I2C_MasterStop(base);
+        }
+
+        return result;
+    }
+
     /* Send subaddress. */
     if (xfer->subaddressSize)
     {
         do
         {
+            /* Clear interrupt pending flag. */
+            base->S = kI2C_IntPendingFlag;
+
+            xfer->subaddressSize--;
+            base->D = ((xfer->subaddress) >> (8 * xfer->subaddressSize));
+
             /* Wait until data transfer complete. */
             while (!(base->S & kI2C_IntPendingFlag))
             {
             }
 
-            /* Clear interrupt pending flag. */
-            base->S = kI2C_IntPendingFlag;
-
             /* Check if there's transfer error. */
             result = I2C_CheckAndClearError(base, base->S);
 
@@ -866,21 +998,27 @@ status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer)
                 return result;
             }
 
-            xfer->subaddressSize--;
-            base->D = ((xfer->subaddress) >> (8 * xfer->subaddressSize));
-
         } while ((xfer->subaddressSize > 0) && (result == kStatus_Success));
 
         if (xfer->direction == kI2C_Read)
         {
+            /* Clear pending flag. */
+            base->S = kI2C_IntPendingFlag;
+
+            /* Send repeated start and slave address. */
+            result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, kI2C_Read);
+
+            /* Return if error. */
+            if (result)
+            {
+                return result;
+            }
+
             /* Wait until data transfer complete. */
             while (!(base->S & kI2C_IntPendingFlag))
             {
             }
 
-            /* Clear pending flag. */
-            base->S = kI2C_IntPendingFlag;
-
             /* Check if there's transfer error. */
             result = I2C_CheckAndClearError(base, base->S);
 
@@ -888,62 +1026,27 @@ status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer)
             {
                 if (result == kStatus_I2C_Nak)
                 {
+                    result = kStatus_I2C_Addr_Nak;
+
                     I2C_MasterStop(base);
                 }
 
                 return result;
             }
-
-            /* Send repeated start and slave address. */
-            result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, kI2C_Read);
-
-            /* Return if error. */
-            if (result)
-            {
-                return result;
-            }
-        }
-    }
-
-    /* Wait until address + command transfer complete. */
-    while (!(base->S & kI2C_IntPendingFlag))
-    {
-    }
-
-    /* Check if there's transfer error. */
-    result = I2C_CheckAndClearError(base, base->S);
-
-    /* Return if error. */
-    if (result)
-    {
-        if (result == kStatus_I2C_Nak)
-        {
-            I2C_MasterStop(base);
         }
-
-        return result;
     }
 
     /* Transmit data. */
     if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0))
     {
         /* Send Data. */
-        result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize);
-
-        if (((result == kStatus_Success) && (!(xfer->flags & kI2C_TransferNoStopFlag))) || (result == kStatus_I2C_Nak))
-        {
-            /* Clear the IICIF flag. */
-            base->S = kI2C_IntPendingFlag;
-
-            /* Send stop. */
-            result = I2C_MasterStop(base);
-        }
+        result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags);
     }
 
     /* Receive Data. */
     if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0))
     {
-        result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize);
+        result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags);
     }
 
     return result;
@@ -1006,11 +1109,37 @@ void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle)
 {
     assert(handle);
 
+    volatile uint8_t dummy = 0;
+
+    /* Add this to avoid build warning. */
+    dummy++;
+
     /* Disable interrupt. */
     I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable);
 
     /* Reset the state to idle. */
     handle->state = kIdleState;
+
+    /* Send STOP signal. */
+    if (handle->transfer.direction == kI2C_Read)
+    {
+        base->C1 |= I2C_C1_TXAK_MASK;
+        while (!(base->S & kI2C_IntPendingFlag))
+        {
+        }
+        base->S = kI2C_IntPendingFlag;
+
+        base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+        dummy = base->D;
+    }
+    else
+    {
+        while (!(base->S & kI2C_IntPendingFlag))
+        {
+        }
+        base->S = kI2C_IntPendingFlag;
+        base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+    }
 }
 
 status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count)
@@ -1044,7 +1173,8 @@ void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle)
     if (isDone || result)
     {
         /* Send stop command if transfer done or received Nak. */
-        if ((!(handle->transfer.flags & kI2C_TransferNoStopFlag)) || (result == kStatus_I2C_Nak))
+        if ((!(handle->transfer.flags & kI2C_TransferNoStopFlag)) || (result == kStatus_I2C_Nak) ||
+            (result == kStatus_I2C_Addr_Nak))
         {
             /* Ensure stop command is a need. */
             if ((base->C1 & I2C_C1_MST_MASK))
@@ -1070,13 +1200,28 @@ void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle)
     }
 }
 
-void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig)
+void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz)
 {
     assert(slaveConfig);
 
     uint8_t tmpReg;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Reset the module. */
+    base->A1 = 0;
+    base->F = 0;
+    base->C1 = 0;
+    base->S = 0xFFU;
+    base->C2 = 0;
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    base->FLT = 0x50U;
+#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
+    base->FLT = 0x40U;
+#endif
+    base->RA = 0;
 
     /* Configure addressing mode. */
     switch (slaveConfig->addressingMode)
@@ -1101,15 +1246,20 @@ void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig)
     tmpReg &= ~I2C_C1_WUEN_MASK;
     base->C1 = tmpReg | I2C_C1_WUEN(slaveConfig->enableWakeUp) | I2C_C1_IICEN(slaveConfig->enableSlave);
 
-    /* Configure general call & baud rate control & high drive feature. */
+    /* Configure general call & baud rate control. */
     tmpReg = base->C2;
     tmpReg &= ~(I2C_C2_SBRC_MASK | I2C_C2_GCAEN_MASK);
     tmpReg |= I2C_C2_SBRC(slaveConfig->enableBaudRateCtl) | I2C_C2_GCAEN(slaveConfig->enableGeneralCall);
-#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
-    tmpReg &= ~I2C_C2_HDRS_MASK;
-    tmpReg |= I2C_C2_HDRS(slaveConfig->enableHighDrive);
-#endif
     base->C2 = tmpReg;
+
+/* Enable/Disable double buffering. */
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    tmpReg = base->S2 & (~I2C_S2_DFEN_MASK);
+    base->S2 = tmpReg | I2C_S2_DFEN(slaveConfig->enableDoubleBuffering);
+#endif
+
+    /* Set hold time. */
+    I2C_SetHoldTime(base, slaveConfig->sclStopHoldTime_ns, srcClock_Hz);
 }
 
 void I2C_SlaveDeinit(I2C_Type *base)
@@ -1117,8 +1267,10 @@ void I2C_SlaveDeinit(I2C_Type *base)
     /* Disable I2C module. */
     I2C_Enable(base, false);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable I2C clock. */
     CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig)
@@ -1134,48 +1286,106 @@ void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig)
     /* Slave address match waking up MCU from low power mode is disabled. */
     slaveConfig->enableWakeUp = false;
 
-#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
-    /* Default pin high drive is disabled. */
-    slaveConfig->enableHighDrive = false;
-#endif
-
     /* Independent slave mode baud rate at maximum frequency is disabled. */
     slaveConfig->enableBaudRateCtl = false;
 
+/* Default enable double buffering. */
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    slaveConfig->enableDoubleBuffering = true;
+#endif
+
+    /* Set default SCL stop hold time to 4us which is minimum requirement in I2C spec. */
+    slaveConfig->sclStopHoldTime_ns = 4000;
+
     /* Enable the I2C peripheral. */
     slaveConfig->enableSlave = true;
 }
 
 status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize)
 {
-    return I2C_MasterWriteBlocking(base, txBuff, txSize);
+    status_t result = kStatus_Success;
+    volatile uint8_t dummy = 0;
+
+    /* Add this to avoid build warning. */
+    dummy++;
+
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    /* Check start flag. */
+    while (!(base->FLT & I2C_FLT_STARTF_MASK))
+    {
+    }
+    /* Clear STARTF flag. */
+    base->FLT |= I2C_FLT_STARTF_MASK;
+    /* Clear the IICIF flag. */
+    base->S = kI2C_IntPendingFlag;
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
+
+    /* Wait for address match flag. */
+    while (!(base->S & kI2C_AddressMatchFlag))
+    {
+    }
+
+    /* Read dummy to release bus. */
+    dummy = base->D;
+
+    result = I2C_MasterWriteBlocking(base, txBuff, txSize, kI2C_TransferDefaultFlag);
+
+    /* Switch to receive mode. */
+    base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+
+    /* Read dummy to release bus. */
+    dummy = base->D;
+
+    return result;
 }
 
 void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize)
 {
+    volatile uint8_t dummy = 0;
+
+    /* Add this to avoid build warning. */
+    dummy++;
+
+/* Wait until address match. */
+#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
+    /* Check start flag. */
+    while (!(base->FLT & I2C_FLT_STARTF_MASK))
+    {
+    }
+    /* Clear STARTF flag. */
+    base->FLT |= I2C_FLT_STARTF_MASK;
     /* Clear the IICIF flag. */
     base->S = kI2C_IntPendingFlag;
+#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
 
-    /* Wait until the data register is ready for receive. */
-    while (!(base->S & kI2C_TransferCompleteFlag))
+    /* Wait for address match and int pending flag. */
+    while (!(base->S & kI2C_AddressMatchFlag))
+    {
+    }
+    while (!(base->S & kI2C_IntPendingFlag))
     {
     }
 
+    /* Read dummy to release bus. */
+    dummy = base->D;
+
+    /* Clear the IICIF flag. */
+    base->S = kI2C_IntPendingFlag;
+
     /* Setup the I2C peripheral to receive data. */
     base->C1 &= ~(I2C_C1_TX_MASK);
 
     while (rxSize--)
     {
+        /* Wait until data transfer complete. */
+        while (!(base->S & kI2C_IntPendingFlag))
+        {
+        }
         /* Clear the IICIF flag. */
         base->S = kI2C_IntPendingFlag;
 
         /* Read from the data register. */
         *rxBuff++ = base->D;
-
-        /* Wait until data transfer complete. */
-        while (!(base->S & kI2C_IntPendingFlag))
-        {
-        }
     }
 }
 
@@ -1226,7 +1436,7 @@ status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle
         handle->isBusy = true;
 
         /* Set up event mask. tx and rx are always enabled. */
-        handle->eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent;
+        handle->eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | kI2C_SlaveGenaralcallEvent;
 
         /* Clear all flags. */
         I2C_SlaveClearStatusFlags(base, kClearFlags);
@@ -1315,7 +1525,10 @@ void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle)
             }
         }
 
-        return;
+        if (!(status & kI2C_AddressMatchFlag))
+        {
+            return;
+        }
     }
 #endif /* I2C_HAS_STOP_DETECT */
 
@@ -1328,7 +1541,7 @@ void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle)
         /* Clear the interrupt flag. */
         base->S = kI2C_IntPendingFlag;
 
-        xfer->event = kI2C_SlaveRepeatedStartEvent;
+        xfer->event = kI2C_SlaveStartEvent;
 
         if ((handle->eventMask & xfer->event) && (handle->callback))
         {
@@ -1385,31 +1598,12 @@ void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle)
         handle->isBusy = true;
         xfer->event = kI2C_SlaveAddressMatchEvent;
 
-        if ((handle->eventMask & xfer->event) && (handle->callback))
-        {
-            handle->callback(base, xfer, handle->userData);
-        }
-
         /* Slave transmit, master reading from slave. */
         if (status & kI2C_TransferDirectionFlag)
         {
             /* Change direction to send data. */
             base->C1 |= I2C_C1_TX_MASK;
 
-            /* If we're out of data, invoke callback to get more. */
-            if ((!xfer->data) || (!xfer->dataSize))
-            {
-                xfer->event = kI2C_SlaveTransmitEvent;
-
-                if (handle->callback)
-                {
-                    handle->callback(base, xfer, handle->userData);
-                }
-
-                /* Clear the transferred count now that we have a new buffer. */
-                xfer->transferredCount = 0;
-            }
-
             doTransmit = true;
         }
         else
@@ -1417,22 +1611,18 @@ void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle)
             /* Slave receive, master writing to slave. */
             base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
 
-            /* If we're out of data, invoke callback to get more. */
-            if ((!xfer->data) || (!xfer->dataSize))
-            {
-                xfer->event = kI2C_SlaveReceiveEvent;
-
-                if (handle->callback)
-                {
-                    handle->callback(base, xfer, handle->userData);
-                }
+            /* Read dummy to release the bus. */
+            dummy = base->D;
 
-                /* Clear the transferred count now that we have a new buffer. */
-                xfer->transferredCount = 0;
+            if (dummy == 0)
+            {
+                xfer->event = kI2C_SlaveGenaralcallEvent;
             }
+        }
 
-            /* Read dummy to release the bus. */
-            dummy = base->D;
+        if ((handle->eventMask & xfer->event) && (handle->callback))
+        {
+            handle->callback(base, xfer, handle->userData);
         }
     }
     /* Check transfer complete flag. */
@@ -1445,6 +1635,20 @@ void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle)
         }
         else
         {
+            /* If we're out of data, invoke callback to get more. */
+            if ((!xfer->data) || (!xfer->dataSize))
+            {
+                xfer->event = kI2C_SlaveReceiveEvent;
+
+                if (handle->callback)
+                {
+                    handle->callback(base, xfer, handle->userData);
+                }
+
+                /* Clear the transferred count now that we have a new buffer. */
+                xfer->transferredCount = 0;
+            }
+
             /* Slave receive, master writing to slave. */
             uint8_t data = base->D;
 
@@ -1480,6 +1684,20 @@ void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle)
     /* Send data if there is the need. */
     if (doTransmit)
     {
+        /* If we're out of data, invoke callback to get more. */
+        if ((!xfer->data) || (!xfer->dataSize))
+        {
+            xfer->event = kI2C_SlaveTransmitEvent;
+
+            if (handle->callback)
+            {
+                handle->callback(base, xfer, handle->userData);
+            }
+
+            /* Clear the transferred count now that we have a new buffer. */
+            xfer->transferredCount = 0;
+        }
+
         if (handle->transfer.dataSize)
         {
             /* Send data. */
@@ -1510,27 +1728,30 @@ void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle)
     }
 }
 
+#if defined(I2C0)
 void I2C0_DriverIRQHandler(void)
 {
     I2C_TransferCommonIRQHandler(I2C0, s_i2cHandle[0]);
 }
+#endif
 
-#if (FSL_FEATURE_SOC_I2C_COUNT > 1)
+#if defined(I2C1)
 void I2C1_DriverIRQHandler(void)
 {
     I2C_TransferCommonIRQHandler(I2C1, s_i2cHandle[1]);
 }
-#endif /* I2C COUNT > 1 */
+#endif
 
-#if (FSL_FEATURE_SOC_I2C_COUNT > 2)
+#if defined(I2C2)
 void I2C2_DriverIRQHandler(void)
 {
     I2C_TransferCommonIRQHandler(I2C2, s_i2cHandle[2]);
 }
-#endif /* I2C COUNT > 2 */
-#if (FSL_FEATURE_SOC_I2C_COUNT > 3)
+#endif
+
+#if defined(I2C3)
 void I2C3_DriverIRQHandler(void)
 {
     I2C_TransferCommonIRQHandler(I2C3, s_i2cHandle[3]);
 }
-#endif /* I2C COUNT > 3 */
+#endif
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c.h
index 41a9afbdd54..d55fd1d8ea3 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,16 +37,14 @@
  * @{
  */
 
-/*! @file */
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief I2C driver version 2.0.0. */
-#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief I2C driver version 2.0.3. */
+#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
 /*@}*/
 
 #if (defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT || \
@@ -62,6 +60,7 @@ enum _i2c_status
     kStatus_I2C_Nak = MAKE_STATUS(kStatusGroup_I2C, 2),             /*!< NAK received during transfer. */
     kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_I2C, 3), /*!< Arbitration lost during transfer. */
     kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_I2C, 4),         /*!< Wait event timeout. */
+    kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_I2C, 5),        /*!< NAK received during the address probe. */
 };
 
 /*!
@@ -109,11 +108,11 @@ enum _i2c_interrupt_enable
 #endif                                                       /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
 };
 
-/*! @brief Direction of master and slave transfers. */
+/*! @brief The direction of master and slave transfers. */
 typedef enum _i2c_direction
 {
-    kI2C_Write = 0x0U, /*!< Master transmit to slave. */
-    kI2C_Read = 0x1U,  /*!< Master receive from slave. */
+    kI2C_Write = 0x0U, /*!< Master transmits to the slave. */
+    kI2C_Read = 0x1U,  /*!< Master receives from the slave. */
 } i2c_direction_t;
 
 /*! @brief Addressing mode. */
@@ -126,17 +125,17 @@ typedef enum _i2c_slave_address_mode
 /*! @brief I2C transfer control flag. */
 enum _i2c_master_transfer_flags
 {
-    kI2C_TransferDefaultFlag = 0x0U,       /*!< Transfer starts with a start signal, stops with a stop signal. */
-    kI2C_TransferNoStartFlag = 0x1U,       /*!< Transfer starts without a start signal. */
-    kI2C_TransferRepeatedStartFlag = 0x2U, /*!< Transfer starts with a repeated start signal. */
-    kI2C_TransferNoStopFlag = 0x4U,        /*!< Transfer ends without a stop signal. */
+    kI2C_TransferDefaultFlag = 0x0U,       /*!< A transfer starts with a start signal, stops with a stop signal. */
+    kI2C_TransferNoStartFlag = 0x1U,       /*!< A transfer starts without a start signal. */
+    kI2C_TransferRepeatedStartFlag = 0x2U, /*!< A transfer starts with a repeated start signal. */
+    kI2C_TransferNoStopFlag = 0x4U,        /*!< A transfer ends without a stop signal. */
 };
 
 /*!
  * @brief Set of events sent to the callback for nonblocking slave transfers.
  *
  * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together
- * events is passed to I2C_SlaveTransferNonBlocking() in order to specify which events to enable.
+ * events is passed to I2C_SlaveTransferNonBlocking() to specify which events to enable.
  * Then, when the slave callback is invoked, it is passed the current event through its @a transfer
  * parameter.
  *
@@ -145,33 +144,35 @@ enum _i2c_master_transfer_flags
 typedef enum _i2c_slave_transfer_event
 {
     kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */
-    kI2C_SlaveTransmitEvent = 0x02U,     /*!< Callback is requested to provide data to transmit
+    kI2C_SlaveTransmitEvent = 0x02U,     /*!< A callback is requested to provide data to transmit
                                                 (slave-transmitter role). */
-    kI2C_SlaveReceiveEvent = 0x04U,      /*!< Callback is requested to provide a buffer in which to place received
+    kI2C_SlaveReceiveEvent = 0x04U,      /*!< A callback is requested to provide a buffer in which to place received
                                                  data (slave-receiver role). */
-    kI2C_SlaveTransmitAckEvent = 0x08U,  /*!< Callback needs to either transmit an ACK or NACK. */
+    kI2C_SlaveTransmitAckEvent = 0x08U,  /*!< A callback needs to either transmit an ACK or NACK. */
 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
-    kI2C_SlaveRepeatedStartEvent = 0x10U, /*!< A repeated start was detected. */
+    kI2C_SlaveStartEvent = 0x10U, /*!< A start/repeated start was detected. */
 #endif
-    kI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected or finished transfer, completing the transfer. */
+    kI2C_SlaveCompletionEvent = 0x20U,  /*!< A stop was detected or finished transfer, completing the transfer. */
+    kI2C_SlaveGenaralcallEvent = 0x40U, /*!< Received the general call address after a start or repeated start. */
 
-    /*! Bit mask of all available events. */
+    /*! A bit mask of all available events. */
     kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent |
 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
-                          kI2C_SlaveRepeatedStartEvent |
+                          kI2C_SlaveStartEvent |
 #endif
-                          kI2C_SlaveCompletionEvent,
+                          kI2C_SlaveCompletionEvent | kI2C_SlaveGenaralcallEvent,
 } i2c_slave_transfer_event_t;
 
 /*! @brief I2C master user configuration. */
 typedef struct _i2c_master_config
 {
     bool enableMaster; /*!< Enables the I2C peripheral at initialization time. */
-#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
-    bool enableHighDrive; /*!< Controls the drive capability of the I2C pads. */
-#endif
 #if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF
     bool enableStopHold; /*!< Controls the stop hold enable. */
+#endif
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    bool enableDoubleBuffering; /*!< Controls double buffer enable; notice that
+                                     enabling the double buffer disables the clock stretch. */
 #endif
     uint32_t baudRate_Bps;     /*!< Baud rate configuration of I2C peripheral. */
     uint8_t glitchFilterWidth; /*!< Controls the width of the glitch. */
@@ -181,15 +182,20 @@ typedef struct _i2c_master_config
 typedef struct _i2c_slave_config
 {
     bool enableSlave;       /*!< Enables the I2C peripheral at initialization time. */
-    bool enableGeneralCall; /*!< Enable general call addressing mode. */
-    bool enableWakeUp;      /*!< Enables/disables waking up MCU from low power mode. */
-#if defined(FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION) && FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION
-    bool enableHighDrive; /*!< Controls the drive capability of the I2C pads. */
+    bool enableGeneralCall; /*!< Enables the general call addressing mode. */
+    bool enableWakeUp;      /*!< Enables/disables waking up MCU from low-power mode. */
+#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
+    bool enableDoubleBuffering; /*!< Controls a double buffer enable; notice that
+                                     enabling the double buffer disables the clock stretch. */
 #endif
     bool enableBaudRateCtl; /*!< Enables/disables independent slave baud rate on SCL in very fast I2C modes. */
-    uint16_t slaveAddress;  /*!< Slave address configuration. */
-    uint16_t upperAddress;  /*!< Maximum boundary slave address used in range matching mode. */
-    i2c_slave_address_mode_t addressingMode; /*!< Addressing mode configuration of i2c_slave_address_mode_config_t. */
+    uint16_t slaveAddress;  /*!< A slave address configuration. */
+    uint16_t upperAddress;  /*!< A maximum boundary slave address used in a range matching mode. */
+    i2c_slave_address_mode_t
+        addressingMode;          /*!< An addressing mode configuration of i2c_slave_address_mode_config_t. */
+    uint32_t sclStopHoldTime_ns; /*!< the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
+                                    data) while SCL is high (stop condition), SDA hold time and SCL start hold time
+                                    are also configured according to the SCL stop hold time. */
 } i2c_slave_config_t;
 
 /*! @brief I2C master handle typedef. */
@@ -207,13 +213,13 @@ typedef struct _i2c_slave_handle i2c_slave_handle_t;
 /*! @brief I2C master transfer structure. */
 typedef struct _i2c_master_transfer
 {
-    uint32_t flags;            /*!< Transfer flag which controls the transfer. */
+    uint32_t flags;            /*!< A transfer flag which controls the transfer. */
     uint8_t slaveAddress;      /*!< 7-bit slave address. */
-    i2c_direction_t direction; /*!< Transfer direction, read or write. */
-    uint32_t subaddress;       /*!< Sub address. Transferred MSB first. */
-    uint8_t subaddressSize;    /*!< Size of command buffer. */
-    uint8_t *volatile data;    /*!< Transfer buffer. */
-    volatile size_t dataSize;  /*!< Transfer size. */
+    i2c_direction_t direction; /*!< A transfer direction, read or write. */
+    uint32_t subaddress;       /*!< A sub address. Transferred MSB first. */
+    uint8_t subaddressSize;    /*!< A size of the command buffer. */
+    uint8_t *volatile data;    /*!< A transfer buffer. */
+    volatile size_t dataSize;  /*!< A transfer size. */
 } i2c_master_transfer_t;
 
 /*! @brief I2C master handle structure. */
@@ -221,20 +227,21 @@ struct _i2c_master_handle
 {
     i2c_master_transfer_t transfer;                    /*!< I2C master transfer copy. */
     size_t transferSize;                               /*!< Total bytes to be transferred. */
-    uint8_t state;                                     /*!< Transfer state maintained during transfer. */
-    i2c_master_transfer_callback_t completionCallback; /*!< Callback function called when transfer finished. */
-    void *userData;                                    /*!< Callback parameter passed to callback function. */
+    uint8_t state;                                     /*!< A transfer state maintained during transfer. */
+    i2c_master_transfer_callback_t completionCallback; /*!< A callback function called when the transfer is finished. */
+    void *userData;                                    /*!< A callback parameter passed to the callback function. */
 };
 
 /*! @brief I2C slave transfer structure. */
 typedef struct _i2c_slave_transfer
 {
-    i2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */
-    uint8_t *volatile data;           /*!< Transfer buffer. */
-    volatile size_t dataSize;         /*!< Transfer size. */
+    i2c_slave_transfer_event_t event; /*!< A reason that the callback is invoked. */
+    uint8_t *volatile data;           /*!< A transfer buffer. */
+    volatile size_t dataSize;         /*!< A transfer size. */
     status_t completionStatus;        /*!< Success or error code describing how the transfer completed. Only applies for
                                          #kI2C_SlaveCompletionEvent. */
-    size_t transferredCount;          /*!< Number of bytes actually transferred since start or last repeated start. */
+    size_t transferredCount; /*!< A number of bytes actually transferred since the start or since the last repeated
+                                start. */
 } i2c_slave_transfer_t;
 
 /*! @brief I2C slave transfer callback typedef. */
@@ -243,11 +250,11 @@ typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, i2c_slave_transfer
 /*! @brief I2C slave handle structure. */
 struct _i2c_slave_handle
 {
-    bool isBusy;                            /*!< Whether transfer is busy. */
+    volatile bool isBusy;                   /*!< Indicates whether a transfer is busy. */
     i2c_slave_transfer_t transfer;          /*!< I2C slave transfer copy. */
-    uint32_t eventMask;                     /*!< Mask of enabled events. */
-    i2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */
-    void *userData;                         /*!< Callback parameter passed to callback. */
+    uint32_t eventMask;                     /*!< A mask of enabled events. */
+    i2c_slave_transfer_callback_t callback; /*!< A callback function called at the transfer event. */
+    void *userData;                         /*!< A callback parameter passed to the callback. */
 };
 
 /*******************************************************************************
@@ -267,12 +274,12 @@ extern "C" {
  * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock
  * and configure the I2C with master configuration.
  *
- * @note This API should be called at the beginning of the application to use
- * the I2C driver, or any operation to the I2C module could cause hard fault
- * because clock is not enabled. The configuration structure can be filled by user
- * from scratch, or be set with default values by I2C_MasterGetDefaultConfig().
+ * @note This API should be called at the beginning of the application.
+ * Otherwise, any operation to the I2C module can cause a hard fault
+ * because the clock is not enabled. The configuration structure can be custom filled
+ * or it can be set with default values by using the I2C_MasterGetDefaultConfig().
  * After calling this API, the master is ready to transfer.
- * Example:
+ * This is an example.
  * @code
  * i2c_master_config_t config = {
  * .enableMaster = true,
@@ -285,20 +292,20 @@ extern "C" {
  * @endcode
  *
  * @param base I2C base pointer
- * @param masterConfig pointer to master configuration structure
+ * @param masterConfig A pointer to the master configuration structure
  * @param srcClock_Hz I2C peripheral clock frequency in Hz
  */
 void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz);
 
 /*!
  * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock
- * and initializes the I2C with slave configuration.
+ * and initialize the I2C with the slave configuration.
  *
- * @note This API should be called at the beginning of the application to use
- * the I2C driver, or any operation to the I2C module can cause a hard fault
+ * @note This API should be called at the beginning of the application.
+ * Otherwise, any operation to the I2C module can cause a hard fault
  * because the clock is not enabled. The configuration structure can partly be set
- * with default values by I2C_SlaveGetDefaultConfig(), or can be filled by the user.
- * Example
+ * with default values by I2C_SlaveGetDefaultConfig() or it can be custom filled by the user.
+ * This is an example.
  * @code
  * i2c_slave_config_t config = {
  * .enableSlave = true,
@@ -307,15 +314,17 @@ void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uin
  * .slaveAddress = 0x1DU,
  * .enableWakeUp = false,
  * .enablehighDrive = false,
- * .enableBaudRateCtl = false
+ * .enableBaudRateCtl = false,
+ * .sclStopHoldTime_ns = 4000
  * };
- * I2C_SlaveInit(I2C0, &config);
+ * I2C_SlaveInit(I2C0, &config, 12000000U);
  * @endcode
  *
  * @param base I2C base pointer
- * @param slaveConfig pointer to slave configuration structure
+ * @param slaveConfig A pointer to the slave configuration structure
+ * @param srcClock_Hz I2C peripheral clock frequency in Hz
  */
-void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig);
+void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz);
 
 /*!
  * @brief De-initializes the I2C master peripheral. Call this API to gate the I2C clock.
@@ -335,28 +344,28 @@ void I2C_SlaveDeinit(I2C_Type *base);
  * @brief  Sets the I2C master configuration structure to default values.
  *
  * The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterConfigure().
- * Use the initialized structure unchanged in I2C_MasterConfigure(), or modify some fields of
- * the structure before calling I2C_MasterConfigure().
- * Example:
+ * Use the initialized structure unchanged in the I2C_MasterConfigure() or modify
+ * the structure before calling the I2C_MasterConfigure().
+ * This is an example.
  * @code
  * i2c_master_config_t config;
  * I2C_MasterGetDefaultConfig(&config);
  * @endcode
- * @param masterConfig Pointer to the master configuration structure.
+ * @param masterConfig A pointer to the master configuration structure.
 */
 void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig);
 
 /*!
  * @brief  Sets the I2C slave configuration structure to default values.
  *
- * The purpose of this API is to get the configuration structure initialized for use in I2C_SlaveConfigure().
+ * The purpose of this API is to get the configuration structure initialized for use in the I2C_SlaveConfigure().
  * Modify fields of the structure before calling the I2C_SlaveConfigure().
- * Example:
+ * This is an example.
  * @code
  * i2c_slave_config_t config;
  * I2C_SlaveGetDefaultConfig(&config);
  * @endcode
- * @param slaveConfig Pointer to the slave configuration structure.
+ * @param slaveConfig A pointer to the slave configuration structure.
  */
 void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig);
 
@@ -364,7 +373,7 @@ void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig);
  * @brief Enables or disabless the I2C peripheral operation.
  *
  * @param base I2C base pointer
- * @param enable pass true to enable module, false to disable module
+ * @param enable Pass true to enable and false to disable the module.
  */
 static inline void I2C_Enable(I2C_Type *base, bool enable)
 {
@@ -389,7 +398,7 @@ static inline void I2C_Enable(I2C_Type *base, bool enable)
  * @brief Gets the I2C status flags.
  *
  * @param base I2C base pointer
- * @return status flag, use status flag to AND #_i2c_flags could get the related status.
+ * @return status flag, use status flag to AND #_i2c_flags to get the related status.
  */
 uint32_t I2C_MasterGetStatusFlags(I2C_Type *base);
 
@@ -397,7 +406,7 @@ uint32_t I2C_MasterGetStatusFlags(I2C_Type *base);
  * @brief Gets the I2C status flags.
  *
  * @param base I2C base pointer
- * @return status flag, use status flag to AND #_i2c_flags could get the related status.
+ * @return status flag, use status flag to AND #_i2c_flags to get the related status.
  */
 static inline uint32_t I2C_SlaveGetStatusFlags(I2C_Type *base)
 {
@@ -407,11 +416,11 @@ static inline uint32_t I2C_SlaveGetStatusFlags(I2C_Type *base)
 /*!
  * @brief Clears the I2C status flag state.
  *
- * The following status register flags can be cleared: kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag
+ * The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag.
  *
  * @param base I2C base pointer
  * @param statusMask The status flag mask, defined in type i2c_status_flag_t.
- *      The parameter could be any combination of the following values:
+ *      The parameter can be any combination of the following values:
  *          @arg kI2C_StartDetectFlag (if available)
  *          @arg kI2C_StopDetectFlag (if available)
  *          @arg kI2C_ArbitrationLostFlag
@@ -442,11 +451,11 @@ static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMas
 /*!
  * @brief Clears the I2C status flag state.
  *
- * The following status register flags can be cleared: kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag
+ * The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag
  *
   * @param base I2C base pointer
   * @param statusMask The status flag mask, defined in type i2c_status_flag_t.
- *      The parameter could be any combination of the following values:
+ *      The parameter can be any combination of the following values:
  *          @arg kI2C_StartDetectFlag (if available)
  *          @arg kI2C_StopDetectFlag (if available)
  *          @arg kI2C_ArbitrationLostFlag
@@ -574,19 +583,21 @@ status_t I2C_MasterStop(I2C_Type *base);
 status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction);
 
 /*!
- * @brief Performs a polling send transaction on the I2C bus without a STOP signal.
+ * @brief Performs a polling send transaction on the I2C bus.
  *
  * @param base  The I2C peripheral base pointer.
  * @param txBuff The pointer to the data to be transferred.
  * @param txSize The length in bytes of the data to be transferred.
+ * @param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag
+*  to issue a stop and kI2C_TransferNoStop to not send a stop.
  * @retval kStatus_Success Successfully complete the data transmission.
  * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
  * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
  */
-status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize);
+status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags);
 
 /*!
- * @brief Performs a polling receive transaction on the I2C bus with a STOP signal.
+ * @brief Performs a polling receive transaction on the I2C bus.
  *
  * @note The I2C_MasterReadBlocking function stops the bus before reading the final byte.
  * Without stopping the bus prior for the final read, the bus issues another read, resulting
@@ -595,10 +606,12 @@ status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t t
  * @param base I2C peripheral base pointer.
  * @param rxBuff The pointer to the data to store the received data.
  * @param rxSize The length in bytes of the data to be received.
+ * @param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag
+*  to issue a stop and kI2C_TransferNoStop to not send a stop.
  * @retval kStatus_Success Successfully complete the data transmission.
  * @retval kStatus_I2C_Timeout Send stop signal failed, timeout.
  */
-status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize);
+status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags);
 
 /*!
  * @brief Performs a polling send transaction on the I2C bus.
@@ -650,7 +663,7 @@ status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer)
  * @param base I2C base pointer.
  * @param handle pointer to i2c_master_handle_t structure to store the transfer state.
  * @param callback pointer to user callback function.
- * @param userData user paramater passed to the callback function.
+ * @param userData user parameter passed to the callback function.
  */
 void I2C_MasterTransferCreateHandle(I2C_Type *base,
                                     i2c_master_handle_t *handle,
@@ -660,15 +673,15 @@ void I2C_MasterTransferCreateHandle(I2C_Type *base,
 /*!
  * @brief Performs a master interrupt non-blocking transfer on the I2C bus.
  *
- * @note Calling the API will return immediately after transfer initiates, user needs
+ * @note Calling the API returns immediately after transfer initiates. The user needs
  * to call I2C_MasterGetTransferCount to poll the transfer status to check whether
- * the transfer is finished, if the return status is not kStatus_I2C_Busy, the transfer
+ * the transfer is finished. If the return status is not kStatus_I2C_Busy, the transfer
  * is finished.
  *
  * @param base I2C base pointer.
  * @param handle pointer to i2c_master_handle_t structure which stores the transfer state.
  * @param xfer pointer to i2c_master_transfer_t structure.
- * @retval kStatus_Success Sucessully start the data transmission.
+ * @retval kStatus_Success Successfully start the data transmission.
  * @retval kStatus_I2C_Busy Previous transmission still not finished.
  * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
  */
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c_edma.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c_edma.c
index c8f7c20629f..28a415e075a 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c_edma.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c_edma.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -162,6 +162,26 @@ static void I2C_MasterTransferCallbackEDMA(edma_handle_t *handle, void *userData
             result = I2C_MasterStop(i2cPrivateHandle->base);
         }
     }
+    else
+    {
+        if (i2cPrivateHandle->handle->transfer.direction == kI2C_Read)
+        {
+            /* Change to send NAK at the last byte. */
+            i2cPrivateHandle->base->C1 |= I2C_C1_TXAK_MASK;
+
+            /* Wait the last data to be received. */
+            while (!(i2cPrivateHandle->base->S & kI2C_TransferCompleteFlag))
+            {
+            }
+
+            /* Change direction to send. */
+            i2cPrivateHandle->base->C1 |= I2C_C1_TX_MASK;
+
+            /* Read the last data byte. */
+            *(i2cPrivateHandle->handle->transfer.data + i2cPrivateHandle->handle->transfer.dataSize - 1) =
+                i2cPrivateHandle->base->D;
+        }
+    }
 
     i2cPrivateHandle->handle->state = kIdleState;
 
@@ -203,7 +223,6 @@ static status_t I2C_InitTransferStateMachineEDMA(I2C_Type *base,
     assert(xfer);
 
     status_t result = kStatus_Success;
-    uint16_t timeout = UINT16_MAX;
 
     if (handle->state != kIdleState)
     {
@@ -221,16 +240,6 @@ static status_t I2C_InitTransferStateMachineEDMA(I2C_Type *base,
 
         handle->state = kTransferDataState;
 
-        /* Wait until ready to complete. */
-        while ((!(base->S & kI2C_TransferCompleteFlag)) && (--timeout))
-        {
-        }
-
-        /* Failed to start the transfer. */
-        if (timeout == 0)
-        {
-            return kStatus_I2C_Timeout;
-        }
         /* Clear all status before transfer. */
         I2C_MasterClearStatusFlags(base, kClearFlags);
 
@@ -250,22 +259,55 @@ static status_t I2C_InitTransferStateMachineEDMA(I2C_Type *base,
             result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction);
         }
 
-        /* Send subaddress. */
-        if (handle->transfer.subaddressSize)
+        if (result)
         {
-            do
+            return result;
+        }
+
+        while (!(base->S & kI2C_IntPendingFlag))
+        {
+        }
+
+        /* Check if there's transfer error. */
+        result = I2C_CheckAndClearError(base, base->S);
+
+        /* Return if error. */
+        if (result)
+        {
+            if (result == kStatus_I2C_Nak)
             {
-                /* Wait until data transfer complete. */
-                while (!(base->S & kI2C_IntPendingFlag))
+                result = kStatus_I2C_Addr_Nak;
+
+                if (I2C_MasterStop(base) != kStatus_Success)
                 {
+                    result = kStatus_I2C_Timeout;
                 }
 
+                if (handle->completionCallback)
+                {
+                    (handle->completionCallback)(base, handle, result, handle->userData);
+                }
+            }
+
+            return result;
+        }
+
+        /* Send subaddress. */
+        if (handle->transfer.subaddressSize)
+        {
+            do
+            {
                 /* Clear interrupt pending flag. */
                 base->S = kI2C_IntPendingFlag;
 
                 handle->transfer.subaddressSize--;
                 base->D = ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize));
 
+                /* Wait until data transfer complete. */
+                while (!(base->S & kI2C_IntPendingFlag))
+                {
+                }
+
                 /* Check if there's transfer error. */
                 result = I2C_CheckAndClearError(base, base->S);
 
@@ -278,34 +320,34 @@ static status_t I2C_InitTransferStateMachineEDMA(I2C_Type *base,
 
             if (handle->transfer.direction == kI2C_Read)
             {
-                /* Wait until data transfer complete. */
-                while (!(base->S & kI2C_IntPendingFlag))
-                {
-                }
-
                 /* Clear pending flag. */
                 base->S = kI2C_IntPendingFlag;
 
                 /* Send repeated start and slave address. */
                 result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read);
-            }
-        }
 
-        if (result)
-        {
-            return result;
-        }
+                if (result)
+                {
+                    return result;
+                }
 
-        /* Wait until data transfer complete. */
-        while (!(base->S & kI2C_IntPendingFlag))
-        {
+                /* Wait until data transfer complete. */
+                while (!(base->S & kI2C_IntPendingFlag))
+                {
+                }
+
+                /* Check if there's transfer error. */
+                result = I2C_CheckAndClearError(base, base->S);
+
+                if (result)
+                {
+                    return result;
+                }
+            }
         }
 
         /* Clear pending flag. */
         base->S = kI2C_IntPendingFlag;
-
-        /* Check if there's transfer error. */
-        result = I2C_CheckAndClearError(base, base->S);
     }
 
     return result;
@@ -319,17 +361,7 @@ static void I2C_MasterTransferEDMAConfig(I2C_Type *base, i2c_master_edma_handle_
     {
         transfer_config.srcAddr = (uint32_t)I2C_GetDataRegAddr(base);
         transfer_config.destAddr = (uint32_t)(handle->transfer.data);
-
-        /* Send stop if kI2C_TransferNoStop flag is not asserted. */
-        if (!(handle->transfer.flags & kI2C_TransferNoStopFlag))
-        {
-            transfer_config.majorLoopCounts = (handle->transfer.dataSize - 1);
-        }
-        else
-        {
-            transfer_config.majorLoopCounts = handle->transfer.dataSize;
-        }
-
+        transfer_config.majorLoopCounts = (handle->transfer.dataSize - 1);
         transfer_config.srcTransferSize = kEDMA_TransferSize1Bytes;
         transfer_config.srcOffset = 0;
         transfer_config.destTransferSize = kEDMA_TransferSize1Bytes;
@@ -348,6 +380,9 @@ static void I2C_MasterTransferEDMAConfig(I2C_Type *base, i2c_master_edma_handle_
         transfer_config.minorLoopBytes = 1;
     }
 
+    /* Store the initially configured eDMA minor byte transfer count into the I2C handle */
+    handle->nbytes = transfer_config.minorLoopBytes;
+
     EDMA_SubmitTransfer(handle->dmaHandle, &transfer_config);
     EDMA_StartTransfer(handle->dmaHandle);
 }
@@ -427,7 +462,7 @@ status_t I2C_MasterTransferEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle
         if (handle->transfer.direction == kI2C_Read)
         {
             /* Change direction for receive. */
-            base->C1 &= ~I2C_C1_TX_MASK;
+            base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
 
             /* Read dummy to release the bus. */
             dummy = base->D;
@@ -479,6 +514,11 @@ status_t I2C_MasterTransferEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle
         {
             result = I2C_MasterStop(base);
         }
+        else
+        {
+            /* Change direction to send. */
+            base->C1 |= I2C_C1_TX_MASK;
+        }
 
         /* Read the last byte of data. */
         if (handle->transfer.direction == kI2C_Read)
@@ -504,7 +544,9 @@ status_t I2C_MasterTransferGetCountEDMA(I2C_Type *base, i2c_master_edma_handle_t
 
     if (kIdleState != handle->state)
     {
-        *count = (handle->transferSize - EDMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel));
+        *count = (handle->transferSize -
+                  (uint32_t)handle->nbytes *
+                      EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel));
     }
     else
     {
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c_edma.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c_edma.h
index 234876d451c..40cb648ea99 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c_edma.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_i2c_edma.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -39,31 +39,30 @@
  * @{
  */
 
-/*! @file */
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
-/*! @brief I2C master edma handle typedef. */
+/*! @brief I2C master eDMA handle typedef. */
 typedef struct _i2c_master_edma_handle i2c_master_edma_handle_t;
 
-/*! @brief I2C master edma transfer callback typedef. */
+/*! @brief I2C master eDMA transfer callback typedef. */
 typedef void (*i2c_master_edma_transfer_callback_t)(I2C_Type *base,
                                                     i2c_master_edma_handle_t *handle,
                                                     status_t status,
                                                     void *userData);
 
-/*! @brief I2C master edma transfer structure. */
+/*! @brief I2C master eDMA transfer structure. */
 struct _i2c_master_edma_handle
 {
-    i2c_master_transfer_t transfer; /*!< I2C master transfer struct. */
+    i2c_master_transfer_t transfer; /*!< I2C master transfer structure. */
     size_t transferSize;            /*!< Total bytes to be transferred. */
+    uint8_t nbytes;                 /*!< eDMA minor byte transfer count initially configured. */
     uint8_t state;                  /*!< I2C master transfer status. */
     edma_handle_t *dmaHandle;       /*!< The eDMA handler used. */
     i2c_master_edma_transfer_callback_t
-        completionCallback; /*!< Callback function called after edma transfer finished. */
-    void *userData;         /*!< Callback parameter passed to callback function. */
+        completionCallback; /*!< A callback function called after the eDMA transfer is finished. */
+    void *userData;         /*!< A callback parameter passed to the callback function. */
 };
 
 /*******************************************************************************
@@ -75,18 +74,18 @@ extern "C" {
 #endif /*_cplusplus. */
 
 /*!
- * @name I2C Block EDMA Transfer Operation
+ * @name I2C Block eDMA Transfer Operation
  * @{
  */
 
 /*!
- * @brief Init the I2C handle which is used in transcational functions.
+ * @brief Initializes the I2C handle which is used in transcational functions.
  *
  * @param base I2C peripheral base address.
- * @param handle pointer to i2c_master_edma_handle_t structure.
- * @param callback pointer to user callback function.
- * @param userData user param passed to the callback function.
- * @param edmaHandle EDMA handle pointer.
+ * @param handle A pointer to the i2c_master_edma_handle_t structure.
+ * @param callback A pointer to the user callback function.
+ * @param userData A user parameter passed to the callback function.
+ * @param edmaHandle eDMA handle pointer.
  */
 void I2C_MasterCreateEDMAHandle(I2C_Type *base,
                                 i2c_master_edma_handle_t *handle,
@@ -95,33 +94,33 @@ void I2C_MasterCreateEDMAHandle(I2C_Type *base,
                                 edma_handle_t *edmaHandle);
 
 /*!
- * @brief Performs a master edma non-blocking transfer on the I2C bus.
+ * @brief Performs a master eDMA non-blocking transfer on the I2C bus.
  *
  * @param base I2C peripheral base address.
- * @param handle pointer to i2c_master_edma_handle_t structure.
- * @param xfer pointer to transfer structure of i2c_master_transfer_t.
- * @retval kStatus_Success Sucessully complete the data transmission.
- * @retval kStatus_I2C_Busy Previous transmission still not finished.
- * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
+ * @param handle A pointer to the i2c_master_edma_handle_t structure.
+ * @param xfer A pointer to the transfer structure of i2c_master_transfer_t.
+ * @retval kStatus_Success Sucessfully completed the data transmission.
+ * @retval kStatus_I2C_Busy A previous transmission is still not finished.
+ * @retval kStatus_I2C_Timeout Transfer error, waits for a signal timeout.
  * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
- * @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer.
+ * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
  */
 status_t I2C_MasterTransferEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, i2c_master_transfer_t *xfer);
 
 /*!
- * @brief Get master transfer status during a edma non-blocking transfer.
+ * @brief Gets a master transfer status during the eDMA non-blocking transfer.
  *
  * @param base I2C peripheral base address.
- * @param handle pointer to i2c_master_edma_handle_t structure.
- * @param count Number of bytes transferred so far by the non-blocking transaction.
+ * @param handle A pointer to the i2c_master_edma_handle_t structure.
+ * @param count A number of bytes transferred by the non-blocking transaction.
  */
 status_t I2C_MasterTransferGetCountEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, size_t *count);
 
 /*!
- * @brief Abort a master edma non-blocking transfer in a early time.
+ * @brief Aborts a master eDMA non-blocking transfer early.
  *
  * @param base I2C peripheral base address.
- * @param handle pointer to i2c_master_edma_handle_t structure.
+ * @param handle A pointer to the i2c_master_edma_handle_t structure.
  */
 void I2C_MasterTransferAbortEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle);
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_llwu.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_llwu.c
index c27b91e9f04..74b1001a88a 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_llwu.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_llwu.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_llwu.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_llwu.h
index 7c11572e806..d5a0037bb58 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_llwu.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_llwu.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -35,7 +35,6 @@
 /*! @addtogroup llwu */
 /*! @{ */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -52,9 +51,9 @@
  */
 typedef enum _llwu_external_pin_mode
 {
-    kLLWU_ExternalPinDisable = 0U,     /*!< Pin disabled as wakeup input.           */
-    kLLWU_ExternalPinRisingEdge = 1U,  /*!< Pin enabled with rising edge detection. */
-    kLLWU_ExternalPinFallingEdge = 2U, /*!< Pin enabled with falling edge detection.*/
+    kLLWU_ExternalPinDisable = 0U,     /*!< Pin disabled as a wakeup input.           */
+    kLLWU_ExternalPinRisingEdge = 1U,  /*!< Pin enabled with the rising edge detection. */
+    kLLWU_ExternalPinFallingEdge = 2U, /*!< Pin enabled with the falling edge detection.*/
     kLLWU_ExternalPinAnyEdge = 3U      /*!< Pin enabled with any change detection.  */
 } llwu_external_pin_mode_t;
 
@@ -75,9 +74,9 @@ typedef enum _llwu_pin_filter_mode
  */
 typedef struct _llwu_version_id
 {
-    uint16_t feature; /*!< Feature Specification Number. */
-    uint8_t minor;    /*!< Minor version number.         */
-    uint8_t major;    /*!< Major version number.         */
+    uint16_t feature; /*!< A feature specification number. */
+    uint8_t minor;    /*!< The minor version number.         */
+    uint8_t major;    /*!< The major version number.         */
 } llwu_version_id_t;
 #endif /* FSL_FEATURE_LLWU_HAS_VERID */
 
@@ -87,20 +86,20 @@ typedef struct _llwu_version_id
  */
 typedef struct _llwu_param
 {
-    uint8_t filters; /*!< Number of pin filter.      */
-    uint8_t dmas;    /*!< Number of wakeup DMA.      */
-    uint8_t modules; /*!< Number of wakeup module.   */
-    uint8_t pins;    /*!< Number of wake up pin.     */
+    uint8_t filters; /*!< A number of the pin filter.      */
+    uint8_t dmas;    /*!< A number of the wakeup DMA.      */
+    uint8_t modules; /*!< A number of the wakeup module.   */
+    uint8_t pins;    /*!< A number of the wake up pin.     */
 } llwu_param_t;
 #endif /* FSL_FEATURE_LLWU_HAS_PARAM */
 
 #if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER)
 /*!
- * @brief External input pin filter control structure
+ * @brief An external input pin filter control structure
  */
 typedef struct _llwu_external_pin_filter_mode
 {
-    uint32_t pinIndex;                 /*!< Pin number  */
+    uint32_t pinIndex;                 /*!< A pin number  */
     llwu_pin_filter_mode_t filterMode; /*!< Filter mode */
 } llwu_external_pin_filter_mode_t;
 #endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */
@@ -122,11 +121,11 @@ extern "C" {
 /*!
  * @brief Gets the LLWU version ID.
  *
- * This function gets the LLWU version ID, including major version number,
- * minor version number, and feature specification number.
+ * This function gets the LLWU version ID, including the major version number,
+ * the minor version number, and the feature specification number.
  *
  * @param base LLWU peripheral base address.
- * @param versionId     Pointer to version ID structure.
+ * @param versionId     A pointer to the version ID structure.
  */
 static inline void LLWU_GetVersionId(LLWU_Type *base, llwu_version_id_t *versionId)
 {
@@ -138,11 +137,11 @@ static inline void LLWU_GetVersionId(LLWU_Type *base, llwu_version_id_t *version
 /*!
  * @brief Gets the LLWU parameter.
  *
- * This function gets the LLWU parameter, including wakeup pin number, module
- * number, DMA number, and pin filter number.
+ * This function gets the LLWU parameter, including a wakeup pin number, a module
+ * number, a DMA number, and a pin filter number.
  *
  * @param base LLWU peripheral base address.
- * @param param         Pointer to LLWU param structure.
+ * @param param         A pointer to the LLWU parameter structure.
  */
 static inline void LLWU_GetParam(LLWU_Type *base, llwu_param_t *param)
 {
@@ -158,8 +157,8 @@ static inline void LLWU_GetParam(LLWU_Type *base, llwu_param_t *param)
  * as a wake up source.
  *
  * @param base LLWU peripheral base address.
- * @param pinIndex pin index which to be enabled as external wakeup source, start from 1.
- * @param pinMode pin configuration mode defined in llwu_external_pin_modes_t
+ * @param pinIndex A pin index to be enabled as an external wakeup source starting from 1.
+ * @param pinMode A pin configuration mode defined in the llwu_external_pin_modes_t.
  */
 void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode);
 
@@ -167,11 +166,11 @@ void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_exte
  * @brief Gets the external wakeup source flag.
  *
  * This function checks the external pin flag to detect whether the MCU is
- * woke up by the specific pin.
+ * woken up by the specific pin.
  *
  * @param base LLWU peripheral base address.
- * @param pinIndex     pin index, start from 1.
- * @return true if the specific pin is wake up source.
+ * @param pinIndex     A pin index, which starts from 1.
+ * @return True if the specific pin is a wakeup source.
  */
 bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex);
 
@@ -181,7 +180,7 @@ bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex);
  * This function clears the external wakeup source flag for a specific pin.
  *
  * @param base LLWU peripheral base address.
- * @param pinIndex pin index, start from 1.
+ * @param pinIndex A pin index, which starts from 1.
  */
 void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex);
 #endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
@@ -194,8 +193,8 @@ void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex);
  * as a wake up source.
  *
  * @param base LLWU peripheral base address.
- * @param moduleIndex   module index which to be enabled as internal wakeup source, start from 1.
- * @param enable        enable or disable setting
+ * @param moduleIndex   A module index to be enabled as an internal wakeup source starting from 1.
+ * @param enable        An enable or a disable setting
  */
 static inline void LLWU_EnableInternalModuleInterruptWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable)
 {
@@ -213,31 +212,31 @@ static inline void LLWU_EnableInternalModuleInterruptWakup(LLWU_Type *base, uint
  * @brief Gets the external wakeup source flag.
  *
  * This function checks the external pin flag to detect whether the system is
- * woke up by the specific pin.
+ * woken up by the specific pin.
  *
  * @param base LLWU peripheral base address.
- * @param moduleIndex  module index, start from 1.
- * @return true if the specific pin is wake up source.
+ * @param moduleIndex  A module index, which starts from 1.
+ * @return True if the specific pin is a wake up source.
  */
 static inline bool LLWU_GetInternalWakeupModuleFlag(LLWU_Type *base, uint32_t moduleIndex)
 {
+#if (defined(FSL_FEATURE_LLWU_HAS_MF) && FSL_FEATURE_LLWU_HAS_MF)
 #if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32))
     return (bool)(base->MF & (1U << moduleIndex));
 #else
-#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
-#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF)
     return (bool)(base->MF5 & (1U << moduleIndex));
+#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
 #else
+#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16))
     return (bool)(base->F5 & (1U << moduleIndex));
-#endif /* FSL_FEATURE_LLWU_HAS_PF */
 #else
 #if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF)
     return (bool)(base->PF3 & (1U << moduleIndex));
 #else
     return (bool)(base->F3 & (1U << moduleIndex));
-#endif
+#endif /* FSL_FEATURE_LLWU_HAS_PF */
 #endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */
-#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */
+#endif /* FSL_FEATURE_LLWU_HAS_MF */
 }
 #endif /* FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE */
 
@@ -248,8 +247,8 @@ static inline bool LLWU_GetInternalWakeupModuleFlag(LLWU_Type *base, uint32_t mo
  * This function enables/disables the internal DMA that is used as a wake up source.
  *
  * @param base LLWU peripheral base address.
- * @param moduleIndex   Internal module index which used as DMA request source, start from 1.
- * @param enable        Enable or disable DMA request source
+ * @param moduleIndex   An internal module index which is used as a DMA request source, starting from 1.
+ * @param enable        Enable or disable the DMA request source
  */
 static inline void LLWU_EnableInternalModuleDmaRequestWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable)
 {
@@ -271,8 +270,8 @@ static inline void LLWU_EnableInternalModuleDmaRequestWakup(LLWU_Type *base, uin
  * This function sets the pin filter configuration.
  *
  * @param base LLWU peripheral base address.
- * @param filterIndex pin filter index which used to enable/disable the digital filter, start from 1.
- * @param filterMode filter mode configuration
+ * @param filterIndex A pin filter index used to enable/disable the digital filter, starting from 1.
+ * @param filterMode A filter mode configuration
  */
 void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode);
 
@@ -282,18 +281,18 @@ void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_
  * This function gets the pin filter flag.
  *
  * @param base LLWU peripheral base address.
- * @param filterIndex pin filter index, start from 1.
- * @return true if the flag is a source of existing a low-leakage power mode.
+ * @param filterIndex A pin filter index, which starts from 1.
+ * @return True if the flag is a source of the existing low-leakage power mode.
  */
 bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex);
 
 /*!
- * @brief Clear the pin filter configuration.
+ * @brief Clears the pin filter configuration.
  *
- * This function clear the pin filter flag.
+ * This function clears the pin filter flag.
  *
  * @param base LLWU peripheral base address.
- * @param filterIndex pin filter index which to be clear the flag, start from 1.
+ * @param filterIndex A pin filter index to clear the flag, starting from 1.
  */
 void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex);
 
@@ -303,10 +302,10 @@ void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex);
 /*!
  * @brief Sets the reset pin mode.
  *
- * This function sets how the reset pin is used as a low leakage mode exit source.
+ * This function determines how the reset pin is used as a low leakage mode exit source.
  *
- * @param pinEnable       Enable reset pin filter
- * @param pinFilterEnable Specify whether pin filter is enabled in Low-Leakage power mode.
+ * @param pinEnable       Enable reset the pin filter
+ * @param pinFilterEnable Specify whether the pin filter is enabled in Low-Leakage power mode.
  */
 void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode);
 #endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lmem_cache.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lmem_cache.c
index fb6f06c3ac2..bff12af5655 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lmem_cache.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lmem_cache.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -48,7 +48,7 @@ void LMEM_EnableCodeCache(LMEM_Type *base, bool enable)
         LMEM_CodeCacheInvalidateAll(base);
 
         /* Now enable the cache. */
-        base->PCCCR |= LMEM_PCCCR_ENCACHE_MASK | LMEM_PCCCR_ENWRBUF_MASK;
+        base->PCCCR |= LMEM_PCCCR_ENCACHE_MASK;
     }
     else
     {
@@ -56,7 +56,7 @@ void LMEM_EnableCodeCache(LMEM_Type *base, bool enable)
         LMEM_CodeCachePushAll(base);
 
         /* Now disable the cache. */
-        base->PCCCR &= ~(LMEM_PCCCR_ENCACHE_MASK | LMEM_PCCCR_ENWRBUF_MASK);
+        base->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK;
     }
 }
 
@@ -236,7 +236,7 @@ void LMEM_CodeCacheClearMultiLines(LMEM_Type *base, uint32_t address, uint32_t l
         }
     }
 }
-
+#if (!defined(FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE)) || !FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE
 status_t LMEM_CodeCacheDemoteRegion(LMEM_Type *base, lmem_cache_region_t region, lmem_cache_mode_t cacheMode)
 {
     uint32_t mode = base->PCCRMR;
@@ -255,6 +255,7 @@ status_t LMEM_CodeCacheDemoteRegion(LMEM_Type *base, lmem_cache_region_t region,
         return kStatus_Success;
     }
 }
+#endif /* FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE */
 
 #if FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
 void LMEM_EnableSystemCache(LMEM_Type *base, bool enable)
@@ -265,7 +266,7 @@ void LMEM_EnableSystemCache(LMEM_Type *base, bool enable)
         LMEM_SystemCacheInvalidateAll(base);
 
         /* Now enable the cache. */
-        base->PSCCR |= LMEM_PSCCR_ENCACHE_MASK | LMEM_PSCCR_ENWRBUF_MASK;
+        base->PSCCR |= LMEM_PSCCR_ENCACHE_MASK ;
     }
     else
     {
@@ -273,7 +274,7 @@ void LMEM_EnableSystemCache(LMEM_Type *base, bool enable)
         LMEM_SystemCachePushAll(base);
 
         /* Now disable the cache. */
-        base->PSCCR &= ~(LMEM_PSCCR_ENCACHE_MASK | LMEM_PSCCR_ENWRBUF_MASK);
+        base->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK;
     }
 }
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lmem_cache.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lmem_cache.h
index 9e69feb4130..8df4cea3d3d 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lmem_cache.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lmem_cache.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,7 +37,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -45,8 +44,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief LMEM controller driver version 2.0.0. */
-#define FSL_LMEM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief LMEM controller driver version 2.1.0. */
+#define FSL_LMEM_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
 /*@}*/
 
 #define LMEM_CACHE_LINE_SIZE (0x10U)   /*!< Cache line is 16-bytes. */
@@ -55,9 +54,9 @@
 /*! @brief LMEM cache mode options. */
 typedef enum _lmem_cache_mode
 {
-    kLMEM_NonCacheable = 0x0U,      /*!< CACHE mode: non-cacheable. */
-    kLMEM_CacheWriteThrough = 0x2U, /*!< CACHE mode: write-through. */
-    kLMEM_CacheWriteBack = 0x3U     /*!< CACHE mode: write-back. */
+    kLMEM_NonCacheable = 0x0U,      /*!< Cache mode: non-cacheable. */
+    kLMEM_CacheWriteThrough = 0x2U, /*!< Cache mode: write-through. */
+    kLMEM_CacheWriteBack = 0x3U     /*!< Cache mode: write-back. */
 } lmem_cache_mode_t;
 
 /*! @brief LMEM cache regions. */
@@ -106,7 +105,7 @@ extern "C" {
 /*!
  * @brief Enables/disables the processor code bus cache.
  * This function enables/disables the cache.  The function first invalidates the entire cache
- * and then enables/disable both the cache and write buffers.
+ * and then enables/disables both the cache and write buffers.
  *
  * @param base LMEM peripheral base address.
  * @param enable The enable or disable flag.
@@ -115,6 +114,26 @@ extern "C" {
  */
 void LMEM_EnableCodeCache(LMEM_Type *base, bool enable);
 
+/*!
+ * @brief Enables/disables the processor code bus write buffer.
+ *
+ * @param base LMEM peripheral base address.
+ * @param enable The enable or disable flag.
+ *       true  - enable the code bus write buffer.
+ *       false - disable the code bus write buffer.
+ */
+static inline void LMEM_EnableCodeWriteBuffer(LMEM_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->PCCCR |= LMEM_PCCCR_ENWRBUF_MASK;
+    }
+    else
+    {
+        base->PCCCR &= ~LMEM_PCCCR_ENWRBUF_MASK;
+    }
+}
+
 /*!
  * @brief Invalidates the processor code bus cache.
  * This function invalidates the cache both ways, which means that
@@ -163,10 +182,10 @@ void LMEM_CodeCacheInvalidateLine(LMEM_Type *base, uint32_t address);
  * This function invalidates multiple lines in the cache
  * based on the physical address and length in bytes passed in by the
  * user.  If the function detects that the length meets or exceeds half the
- * cache. Then the function performs an entire cache invalidate function, which is
+ * cache, the function performs an entire cache invalidate function, which is
  * more efficient than invalidating the cache line-by-line.
- * The need to check half the total amount of cache is due to the fact that the cache consists of
- * two ways and that line commands based on the physical address searches both ways.
+ * Because the cache consists of two ways and line commands based on the physical address searches both ways,
+ * check half the total amount of cache.
  * Invalidate - Unconditionally clear valid and modified bits of a cache entry.
  *
  * @param base LMEM peripheral base address.
@@ -197,8 +216,8 @@ void LMEM_CodeCachePushLine(LMEM_Type *base, uint32_t address);
  * user.  If the function detects that the length meets or exceeds half of the
  * cache, the function performs an cache push function, which is
  * more efficient than pushing the modified lines in the cache line-by-line.
- * The need to check half the total amount of cache is due to the fact that the cache consists of
- * two ways and that line commands based on the physical address searches both ways.
+ * Because the cache consists of two ways and line commands based on the physical address searches both ways,
+ * check half the total amount of cache.
  * Push - Push a cache entry if it is valid and modified, then clear the modified bit. If
  * the entry is not valid or not modified, leave as is. This action does not clear the valid
  * bit. A cache push is synonymous with a cache flush.
@@ -230,8 +249,8 @@ void LMEM_CodeCacheClearLine(LMEM_Type *base, uint32_t address);
  * user.  If the function detects that the length meets or exceeds half the total amount of
  * cache, the function performs a cache clear function which is
  * more efficient than clearing the lines in the cache line-by-line.
- * The need to check half the total amount of cache is due to the fact that the cache consists of
- * two ways and that line commands based on the physical address searches both ways.
+ * Because the cache consists of two ways and line commands based on the physical address searches both ways,
+ * check half the total amount of cache.
  * Clear - Push a cache entry if it is valid and modified, then clear the valid and
  * modify bits. If entry not valid or not modified, clear the valid bit.
  *
@@ -242,6 +261,7 @@ void LMEM_CodeCacheClearLine(LMEM_Type *base, uint32_t address);
  */
 void LMEM_CodeCacheClearMultiLines(LMEM_Type *base, uint32_t address, uint32_t length);
 
+#if (!defined(FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE)) || !FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE
 /*!
  * @brief Demotes the cache mode of a region in processor code bus cache.
  * This function allows the user to demote the cache mode of a region within the device's
@@ -264,6 +284,7 @@ void LMEM_CodeCacheClearMultiLines(LMEM_Type *base, uint32_t address, uint32_t l
  * kStatus_Fail The cache demote operation is failure.
  */
 status_t LMEM_CodeCacheDemoteRegion(LMEM_Type *base, lmem_cache_region_t region, lmem_cache_mode_t cacheMode);
+#endif  /* FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE */
 
 /*@}*/
 
@@ -285,6 +306,26 @@ status_t LMEM_CodeCacheDemoteRegion(LMEM_Type *base, lmem_cache_region_t region,
  */
 void LMEM_EnableSystemCache(LMEM_Type *base, bool enable);
 
+/*!
+ * @brief Enables/disables the processor system bus write buffer.
+ *
+ * @param base LMEM peripheral base address.
+ * @param enable The enable or disable flag.
+ *       true  - enable the system bus write buffer.
+ *       false - disable the system bus write buffer.
+ */
+static inline void LMEM_EnableSystemWriteBuffer(LMEM_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->PSCCR |= LMEM_PSCCR_ENWRBUF_MASK;       
+    }
+    else
+    {
+        base->PSCCR &= ~LMEM_PSCCR_ENWRBUF_MASK;               
+    }
+}
+
 /*!
  * @brief Invalidates the processor system bus cache.
  * This function invalidates the entire cache both ways.
@@ -320,7 +361,7 @@ void LMEM_SystemCacheClearAll(LMEM_Type *base);
  * @brief Invalidates a specific line in the processor system bus cache.
  * This function invalidates a specific line in the cache
  * based on the physical address passed in by the user.
- * Invalidate - Unconditionally clear valid and modify bits of a cache entry
+ * Invalidate - Unconditionally clears valid and modify bits of a cache entry.
  *
  * @param base LMEM peripheral base address. Should be 16-byte aligned address.
  * If not, it is changed to the 16-byte aligned memory address.
@@ -335,8 +376,8 @@ void LMEM_SystemCacheInvalidateLine(LMEM_Type *base, uint32_t address);
  * user.  If the function detects that the length meets or exceeds half of the
  * cache, the function performs an entire cache invalidate function (which is
  * more efficient than invalidating the cache line-by-line).
- * The need to check half the total amount of cache is due to the fact that the cache consists of
- * two ways and that line commands based on the physical address  searches both ways.
+ * Because the cache consists of two ways and line commands based on the physical address searches both ways,
+ * check half the total amount of cache.
  * Invalidate - Unconditionally clear valid and modify bits of a cache entry
  *
  * @param base LMEM peripheral base address.
@@ -367,8 +408,8 @@ void LMEM_SystemCachePushLine(LMEM_Type *base, uint32_t address);
  * user.  If the function detects that the length meets or exceeds half of the
  * cache, the function performs an entire cache push function (which is
  * more efficient than pushing the modified lines in the cache line-by-line).
- * The need to check half the total amount of cache is due to the fact that the cache consists of
- * two ways and that line commands based on the physical address searches both ways.
+ * Because the cache consists of two ways and line commands based on the physical address searches both ways,
+ * check half the total amount of cache.
  * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
  * the entry is not valid or not modified, leave as is. This action does not clear the valid
  * bit. A cache push is synonymous with a cache flush.
@@ -400,8 +441,8 @@ void LMEM_SystemCacheClearLine(LMEM_Type *base, uint32_t address);
  * user.  If the function detects that the length meets or exceeds half of the
  * cache, the function performs an entire cache clear function (which is
  * more efficient than clearing the lines in the cache line-by-line).
- * The need to check half the total amount of cache is due to the fact that the cache consists of
- * two ways and that line commands based on the physical address searches both ways.
+ * Because the cache consists of two ways and line commands based on the physical address searches both ways,
+ * check half the total amount of cache.
  * Clear - Push a cache entry if it is valid and modified, then clear the valid and
  * modify bits. If the entry is not valid or not modified, clear the valid bit.
  *
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lptmr.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lptmr.c
index b3dcc89d55d..67b3b9785cf 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lptmr.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lptmr.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -48,9 +48,17 @@ static uint32_t LPTMR_GetInstance(LPTMR_Type *base);
 /*! @brief Pointers to LPTMR bases for each instance. */
 static LPTMR_Type *const s_lptmrBases[] = LPTMR_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to LPTMR clocks for each instance. */
 static const clock_ip_name_t s_lptmrClocks[] = LPTMR_CLOCKS;
 
+#if defined(LPTMR_PERIPH_CLOCKS)
+/* Array of LPTMR functional clock name. */
+static const clock_ip_name_t s_lptmrPeriphClocks[] = LPTMR_PERIPH_CLOCKS;
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
 /*******************************************************************************
  * Code
  ******************************************************************************/
@@ -59,7 +67,7 @@ static uint32_t LPTMR_GetInstance(LPTMR_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_LPTMR_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_lptmrBases); instance++)
     {
         if (s_lptmrBases[instance] == base)
         {
@@ -67,7 +75,7 @@ static uint32_t LPTMR_GetInstance(LPTMR_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_LPTMR_COUNT);
+    assert(instance < ARRAY_SIZE(s_lptmrBases));
 
     return instance;
 }
@@ -76,8 +84,17 @@ void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config)
 {
     assert(config);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    
+    uint32_t instance = LPTMR_GetInstance(base);
+
     /* Ungate the LPTMR clock*/
-    CLOCK_EnableClock(s_lptmrClocks[LPTMR_GetInstance(base)]);
+    CLOCK_EnableClock(s_lptmrClocks[instance]);
+#if defined(LPTMR_PERIPH_CLOCKS)
+    CLOCK_EnableClock(s_lptmrPeriphClocks[instance]);
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Configure the timers operation mode and input pin setup */
     base->CSR = (LPTMR_CSR_TMS(config->timerMode) | LPTMR_CSR_TFC(config->enableFreeRunning) |
@@ -92,8 +109,17 @@ void LPTMR_Deinit(LPTMR_Type *base)
 {
     /* Disable the LPTMR and reset the internal logic */
     base->CSR &= ~LPTMR_CSR_TEN_MASK;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+
+    uint32_t instance = LPTMR_GetInstance(base);
+
     /* Gate the LPTMR clock*/
-    CLOCK_DisableClock(s_lptmrClocks[LPTMR_GetInstance(base)]);
+    CLOCK_DisableClock(s_lptmrClocks[instance]);
+#if defined(LPTMR_PERIPH_CLOCKS)
+    CLOCK_DisableClock(s_lptmrPeriphClocks[instance]);
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void LPTMR_GetDefaultConfig(lptmr_config_t *config)
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lptmr.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lptmr.h
index fd3cb1ed242..6cc909b3148 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lptmr.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lptmr.h
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -33,22 +33,20 @@
 #include "fsl_common.h"
 
 /*!
- * @addtogroup lptmr_driver
+ * @addtogroup lptmr
  * @{
  */
 
-/*! @file */
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */
 /*@}*/
 
-/*! @brief LPTMR pin selection, used in pulse counter mode.*/
+/*! @brief LPTMR pin selection used in pulse counter mode.*/
 typedef enum _lptmr_pin_select
 {
     kLPTMR_PinSelectInput_0 = 0x0U, /*!< Pulse counter input 0 is selected */
@@ -57,7 +55,7 @@ typedef enum _lptmr_pin_select
     kLPTMR_PinSelectInput_3 = 0x3U  /*!< Pulse counter input 3 is selected */
 } lptmr_pin_select_t;
 
-/*! @brief LPTMR pin polarity, used in pulse counter mode.*/
+/*! @brief LPTMR pin polarity used in pulse counter mode.*/
 typedef enum _lptmr_pin_polarity
 {
     kLPTMR_PinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high */
@@ -104,13 +102,13 @@ typedef enum _lptmr_prescaler_clock_select
     kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */
 } lptmr_prescaler_clock_select_t;
 
-/*! @brief List of LPTMR interrupts */
+/*! @brief List of the LPTMR interrupts */
 typedef enum _lptmr_interrupt_enable
 {
     kLPTMR_TimerInterruptEnable = LPTMR_CSR_TIE_MASK, /*!< Timer interrupt enable */
 } lptmr_interrupt_enable_t;
 
-/*! @brief List of LPTMR status flags */
+/*! @brief List of the LPTMR status flags */
 typedef enum _lptmr_status_flags
 {
     kLPTMR_TimerCompareFlag = LPTMR_CSR_TCF_MASK, /*!< Timer compare flag */
@@ -121,18 +119,18 @@ typedef enum _lptmr_status_flags
  *
  * This structure holds the configuration settings for the LPTMR peripheral. To initialize this
  * structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a
- * pointer to your config structure instance.
+ * pointer to your configuration structure instance.
  *
- * The config struct can be made const so it resides in flash
+ * The configuration struct can be made constant so it resides in flash.
  */
 typedef struct _lptmr_config
 {
     lptmr_timer_mode_t timerMode;     /*!< Time counter mode or pulse counter mode */
     lptmr_pin_select_t pinSelect;     /*!< LPTMR pulse input pin select; used only in pulse counter mode */
     lptmr_pin_polarity_t pinPolarity; /*!< LPTMR pulse input pin polarity; used only in pulse counter mode */
-    bool enableFreeRunning;           /*!< true: enable free running, counter is reset on overflow
-                                           false: counter is reset when the compare flag is set */
-    bool bypassPrescaler;             /*!< true: bypass prescaler; false: use clock from prescaler */
+    bool enableFreeRunning;           /*!< True: enable free running, counter is reset on overflow
+                                           False: counter is reset when the compare flag is set */
+    bool bypassPrescaler;             /*!< True: bypass prescaler; false: use clock from prescaler */
     lptmr_prescaler_clock_select_t prescalerClockSource; /*!< LPTMR clock source */
     lptmr_prescaler_glitch_value_t value;                /*!< Prescaler or glitch filter value */
 } lptmr_config_t;
@@ -151,26 +149,26 @@ extern "C" {
  */
 
 /*!
- * @brief Ungate the LPTMR clock and configures the peripheral for basic operation.
+ * @brief Ungates the LPTMR clock and configures the peripheral for a basic operation.
  *
  * @note This API should be called at the beginning of the application using the LPTMR driver.
  *
  * @param base   LPTMR peripheral base address
- * @param config Pointer to user's LPTMR config structure.
+ * @param config A pointer to the LPTMR configuration structure.
  */
 void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config);
 
 /*!
- * @brief Gate the LPTMR clock
+ * @brief Gates the LPTMR clock.
  *
  * @param base LPTMR peripheral base address
  */
 void LPTMR_Deinit(LPTMR_Type *base);
 
 /*!
- * @brief Fill in the LPTMR config struct with the default settings
+ * @brief Fills in the LPTMR configuration structure with default settings.
  *
- * The default values are:
+ * The default values are as follows.
  * @code
  *    config->timerMode = kLPTMR_TimerModeTimeCounter;
  *    config->pinSelect = kLPTMR_PinSelectInput_0;
@@ -180,7 +178,7 @@ void LPTMR_Deinit(LPTMR_Type *base);
  *    config->prescalerClockSource = kLPTMR_PrescalerClock_1;
  *    config->value = kLPTMR_Prescale_Glitch_0;
  * @endcode
- * @param config Pointer to user's LPTMR config structure.
+ * @param config A pointer to the LPTMR configuration structure.
  */
 void LPTMR_GetDefaultConfig(lptmr_config_t *config);
 
@@ -200,7 +198,12 @@ void LPTMR_GetDefaultConfig(lptmr_config_t *config);
  */
 static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask)
 {
-    base->CSR |= mask;
+    uint32_t reg = base->CSR;
+
+    /* Clear the TCF bit so that we don't clear this w1c bit when writing back */
+    reg &= ~(LPTMR_CSR_TCF_MASK);
+    reg |= mask;
+    base->CSR = reg;
 }
 
 /*!
@@ -208,11 +211,16 @@ static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask)
  *
  * @param base LPTMR peripheral base address
  * @param mask The interrupts to disable. This is a logical OR of members of the
- *             enumeration ::lptmr_interrupt_enable_t
+ *             enumeration ::lptmr_interrupt_enable_t.
  */
 static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask)
 {
-    base->CSR &= ~mask;
+    uint32_t reg = base->CSR;
+
+    /* Clear the TCF bit so that we don't clear this w1c bit when writing back */
+    reg &= ~(LPTMR_CSR_TCF_MASK);
+    reg &= ~mask;
+    base->CSR = reg;
 }
 
 /*!
@@ -236,7 +244,7 @@ static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base)
  */
 
 /*!
- * @brief Gets the LPTMR status flags
+ * @brief Gets the LPTMR status flags.
  *
  * @param base LPTMR peripheral base address
  *
@@ -249,11 +257,11 @@ static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base)
 }
 
 /*!
- * @brief  Clears the LPTMR status flags
+ * @brief  Clears the LPTMR status flags.
  *
  * @param base LPTMR peripheral base address
  * @param mask The status flags to clear. This is a logical OR of members of the
- *             enumeration ::lptmr_status_flags_t
+ *             enumeration ::lptmr_status_flags_t.
  */
 static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask)
 {
@@ -263,47 +271,48 @@ static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask)
 /*! @}*/
 
 /*!
- * @name Read and Write the timer period
+ * @name Read and write the timer period
  * @{
  */
 
 /*!
  * @brief Sets the timer period in units of count.
  *
- * Timers counts from 0 till it equals the count value set here. The count value is written to
+ * Timers counts from 0 until it equals the count value set here. The count value is written to
  * the CMR register.
  *
  * @note
  * 1. The TCF flag is set with the CNR equals the count provided here and then increments.
- * 2. User can call the utility macros provided in fsl_common.h to convert to ticks
+ * 2. Call the utility macros provided in the fsl_common.h to convert to ticks.
  *
  * @param base  LPTMR peripheral base address
- * @param ticks Timer period in units of ticks
+ * @param ticks A timer period in units of ticks, which should be equal or greater than 1.
  */
-static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint16_t ticks)
+static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint32_t ticks)
 {
-    base->CMR = ticks;
+    assert(ticks > 0);
+    base->CMR = ticks - 1;
 }
 
 /*!
  * @brief Reads the current timer counting value.
  *
- * This function returns the real-time timer counting value, in a range from 0 to a
+ * This function returns the real-time timer counting value in a range from 0 to a
  * timer period.
  *
- * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
+ * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.
  *
  * @param base LPTMR peripheral base address
  *
- * @return Current counter value in ticks
+ * @return The current counter value in ticks
  */
-static inline uint16_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base)
+static inline uint32_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base)
 {
-    /* Must first write any value to the CNR. This will synchronize and register the current value
+    /* Must first write any value to the CNR. This synchronizes and registers the current value
      * of the CNR into a temporary register which can then be read
      */
     base->CNR = 0U;
-    return (uint16_t)base->CNR;
+    return (uint32_t)((base->CNR & LPTMR_CNR_COUNTER_MASK) >> LPTMR_CNR_COUNTER_SHIFT);
 }
 
 /*! @}*/
@@ -314,30 +323,40 @@ static inline uint16_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base)
  */
 
 /*!
- * @brief Starts the timer counting.
+ * @brief Starts the timer.
  *
  * After calling this function, the timer counts up to the CMR register value.
- * Each time the timer reaches CMR value and then increments, it generates a
- * trigger pulse and sets the timeout interrupt flag. An interrupt will also be
+ * Each time the timer reaches the CMR value and then increments, it generates a
+ * trigger pulse and sets the timeout interrupt flag. An interrupt is also
  * triggered if the timer interrupt is enabled.
  *
  * @param base LPTMR peripheral base address
  */
 static inline void LPTMR_StartTimer(LPTMR_Type *base)
 {
-    base->CSR |= LPTMR_CSR_TEN_MASK;
+    uint32_t reg = base->CSR;
+
+    /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */
+    reg &= ~(LPTMR_CSR_TCF_MASK);
+    reg |= LPTMR_CSR_TEN_MASK;
+    base->CSR = reg;
 }
 
 /*!
- * @brief Stops the timer counting.
+ * @brief Stops the timer.
  *
- * This function stops the timer counting and resets the timer's counter register
+ * This function stops the timer and resets the timer's counter register.
  *
  * @param base LPTMR peripheral base address
  */
 static inline void LPTMR_StopTimer(LPTMR_Type *base)
 {
-    base->CSR &= ~LPTMR_CSR_TEN_MASK;
+    uint32_t reg = base->CSR;
+
+    /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */
+    reg &= ~(LPTMR_CSR_TCF_MASK);
+    reg &= ~LPTMR_CSR_TEN_MASK;
+    base->CSR = reg;
 }
 
 /*! @}*/
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart.c
index b1b015f6f49..9a83b5698d2 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart.c
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -109,9 +109,23 @@ static lpuart_handle_t *s_lpuartHandle[FSL_FEATURE_SOC_LPUART_COUNT];
 /* Array of LPUART peripheral base address. */
 static LPUART_Type *const s_lpuartBases[] = LPUART_BASE_PTRS;
 /* Array of LPUART IRQ number. */
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+static const IRQn_Type s_lpuartRxIRQ[] = LPUART_RX_IRQS;
+static const IRQn_Type s_lpuartTxIRQ[] = LPUART_TX_IRQS;
+#else
 static const IRQn_Type s_lpuartIRQ[] = LPUART_RX_TX_IRQS;
+#endif
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /* Array of LPUART clock name. */
 static const clock_ip_name_t s_lpuartClock[] = LPUART_CLOCKS;
+
+#if defined(LPUART_PERIPH_CLOCKS)
+/* Array of LPUART functional clock name. */
+static const clock_ip_name_t s_lpuartPeriphClocks[] = LPUART_PERIPH_CLOCKS;
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
 /* LPUART ISR for transactional APIs. */
 static lpuart_isr_t s_lpuartIsr;
 
@@ -123,7 +137,7 @@ uint32_t LPUART_GetInstance(LPUART_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_LPUART_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_lpuartBases); instance++)
     {
         if (s_lpuartBases[instance] == base)
         {
@@ -131,13 +145,15 @@ uint32_t LPUART_GetInstance(LPUART_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_LPUART_COUNT);
+    assert(instance < ARRAY_SIZE(s_lpuartBases));
 
     return instance;
 }
 
 static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle)
 {
+    assert(handle);
+
     size_t size;
 
     if (handle->rxRingBufferTail > handle->rxRingBufferHead)
@@ -154,6 +170,8 @@ static size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_han
 
 static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle)
 {
+    assert(handle);
+
     bool full;
 
     if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U))
@@ -169,6 +187,8 @@ static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t
 
 static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
 {
+    assert(data);
+
     size_t i;
 
     /* The Non Blocking write data API assume user have ensured there is enough space in
@@ -181,33 +201,48 @@ static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size
 
 static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length)
 {
+    assert(data);
+
     size_t i;
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl = base->CTRL;
+    bool isSevenDataBits =
+        ((ctrl & LPUART_CTRL_M7_MASK) ||
+         ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
+#endif
 
     /* The Non Blocking read data API assume user have ensured there is enough space in
     peripheral to write. */
     for (i = 0; i < length; i++)
     {
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+        if (isSevenDataBits)
+        {
+            data[i] = (base->DATA & 0x7F);
+        }
+        else
+        {
+            data[i] = base->DATA;
+        }
+#else
         data[i] = base->DATA;
+#endif
     }
 }
 
-void LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)
+status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)
 {
     assert(config);
+    assert(config->baudRate_Bps);
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
     assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark);
     assert(FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark);
 #endif
+
     uint32_t temp;
     uint16_t sbr, sbrTemp;
     uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff;
 
-    /* Enable lpuart clock */
-    CLOCK_EnableClock(s_lpuartClock[LPUART_GetInstance(base)]);
-
-    /* Disable LPUART TX RX before setting. */
-    base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
-
     /* This LPUART instantiation uses a slightly different baud rate calculation
      * The idea is to use the best OSR (over-sampling rate) possible
      * Note, OSR is typically hard-set to 16 in other LPUART instantiations
@@ -248,34 +283,75 @@ void LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcC
 
     /* Check to see if actual baud rate is within 3% of desired baud rate
      * based on the best calculate OSR value */
-    if (baudDiff < ((config->baudRate_Bps / 100) * 3))
+    if (baudDiff > ((config->baudRate_Bps / 100) * 3))
     {
-        temp = base->BAUD;
+        /* Unacceptable baud rate difference of more than 3%*/
+        return kStatus_LPUART_BaudrateNotSupport;
+    }
 
-        /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
-         * If so, then "BOTHEDGE" sampling must be turned on */
-        if ((osr > 3) && (osr < 8))
-        {
-            temp |= LPUART_BAUD_BOTHEDGE_MASK;
-        }
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    
+    uint32_t instance = LPUART_GetInstance(base);
 
-        /* program the osr value (bit value is one less than actual value) */
-        temp &= ~LPUART_BAUD_OSR_MASK;
-        temp |= LPUART_BAUD_OSR(osr - 1);
+    /* Enable lpuart clock */
+    CLOCK_EnableClock(s_lpuartClock[instance]);
+#if defined(LPUART_PERIPH_CLOCKS)
+    CLOCK_EnableClock(s_lpuartPeriphClocks[instance]);
+#endif
 
-        /* write the sbr value to the BAUD registers */
-        temp &= ~LPUART_BAUD_SBR_MASK;
-        base->BAUD = temp | LPUART_BAUD_SBR(sbr);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL
+    /*Reset all internal logic and registers, except the Global Register */
+    LPUART_SoftwareReset(base);
+#else
+    /* Disable LPUART TX RX before setting. */
+    base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
+#endif
+
+    temp = base->BAUD;
+
+    /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
+     * If so, then "BOTHEDGE" sampling must be turned on */
+    if ((osr > 3) && (osr < 8))
+    {
+        temp |= LPUART_BAUD_BOTHEDGE_MASK;
     }
 
+    /* program the osr value (bit value is one less than actual value) */
+    temp &= ~LPUART_BAUD_OSR_MASK;
+    temp |= LPUART_BAUD_OSR(osr - 1);
+
+    /* write the sbr value to the BAUD registers */
+    temp &= ~LPUART_BAUD_SBR_MASK;
+    base->BAUD = temp | LPUART_BAUD_SBR(sbr);
+
     /* Set bit count and parity mode. */
     base->BAUD &= ~LPUART_BAUD_M10_MASK;
 
     temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK);
 
-    if (kLPUART_ParityDisabled != config->parityMode)
+    temp |= (uint8_t)config->parityMode;
+
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    if (kLPUART_SevenDataBits == config->dataBitsCount)
+    {
+        if (kLPUART_ParityDisabled != config->parityMode)
+        {
+            temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */
+        }
+        else
+        {
+            temp |= LPUART_CTRL_M7_MASK;
+        }
+    }
+    else
+#endif
     {
-        temp |= (LPUART_CTRL_M_MASK | (uint8_t)config->parityMode);
+        if (kLPUART_ParityDisabled != config->parityMode)
+        {
+            temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */
+        }
     }
 
     base->CTRL = temp;
@@ -298,17 +374,27 @@ void LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcC
 #endif
 
     /* Clear all status flags */
-    temp = (LPUART_STAT_LBKDIF_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
+    temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
             LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
 
 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
-    temp |= LPUART_STAT_IDLE_MASK;
+    temp |= LPUART_STAT_LBKDIF_MASK;
 #endif
 
 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
     temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK);
 #endif
 
+    /* Set data bits order. */
+    if (config->isMsb)
+    {
+        temp |= LPUART_STAT_MSBF_MASK;
+    }
+    else
+    {
+        temp &= ~LPUART_STAT_MSBF_MASK;
+    }
+
     base->STAT |= temp;
 
     /* Enable TX/RX base on configure structure. */
@@ -324,6 +410,8 @@ void LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcC
     }
 
     base->CTRL = temp;
+
+    return kStatus_Success;
 }
 void LPUART_Deinit(LPUART_Type *base)
 {
@@ -341,11 +429,11 @@ void LPUART_Deinit(LPUART_Type *base)
     }
 
     /* Clear all status flags */
-    temp = (LPUART_STAT_LBKDIF_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
+    temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
             LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
 
 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
-    temp |= LPUART_STAT_IDLE_MASK;
+    temp |= LPUART_STAT_LBKDIF_MASK;
 #endif
 
 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
@@ -357,15 +445,27 @@ void LPUART_Deinit(LPUART_Type *base)
     /* Disable the module. */
     base->CTRL = 0;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    uint32_t instance = LPUART_GetInstance(base);
+
     /* Disable lpuart clock */
-    CLOCK_DisableClock(s_lpuartClock[LPUART_GetInstance(base)]);
+    CLOCK_DisableClock(s_lpuartClock[instance]);
+
+#if defined(LPUART_PERIPH_CLOCKS)
+    CLOCK_DisableClock(s_lpuartPeriphClocks[instance]);
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void LPUART_GetDefaultConfig(lpuart_config_t *config)
 {
     assert(config);
+
     config->baudRate_Bps = 115200U;
     config->parityMode = kLPUART_ParityDisabled;
+    config->dataBitsCount = kLPUART_EightDataBits;
+    config->isMsb = false;
 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
     config->stopBitCount = kLPUART_OneStopBit;
 #endif
@@ -377,18 +477,14 @@ void LPUART_GetDefaultConfig(lpuart_config_t *config)
     config->enableRx = false;
 }
 
-void LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
+status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
 {
+    assert(baudRate_Bps);
+
     uint32_t temp, oldCtrl;
     uint16_t sbr, sbrTemp;
     uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff;
 
-    /* Store CTRL before disable Tx and Rx */
-    oldCtrl = base->CTRL;
-
-    /* Disable LPUART TX RX before setting. */
-    base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
-
     /* This LPUART instantiation uses a slightly different baud rate calculation
      * The idea is to use the best OSR (over-sampling rate) possible
      * Note, OSR is typically hard-set to 16 in other LPUART instantiations
@@ -431,6 +527,12 @@ void LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcCl
      * based on the best calculate OSR value */
     if (baudDiff < ((baudRate_Bps / 100) * 3))
     {
+        /* Store CTRL before disable Tx and Rx */
+        oldCtrl = base->CTRL;
+
+        /* Disable LPUART TX RX before setting. */
+        base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
+
         temp = base->BAUD;
 
         /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
@@ -447,17 +549,25 @@ void LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcCl
         /* write the sbr value to the BAUD registers */
         temp &= ~LPUART_BAUD_SBR_MASK;
         base->BAUD = temp | LPUART_BAUD_SBR(sbr);
-    }
 
-    /* Restore CTRL. */
-    base->CTRL = oldCtrl;
+        /* Restore CTRL. */
+        base->CTRL = oldCtrl;
+
+        return kStatus_Success;
+    }
+    else
+    {
+        /* Unacceptable baud rate difference of more than 3%*/
+        return kStatus_LPUART_BaudrateNotSupport;
+    }
 }
 
 void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
 {
     base->BAUD |= ((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
-    base->FIFO |= ((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
+    base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) |
+                 ((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
 #endif
     mask &= 0xFFFFFF00U;
     base->CTRL |= mask;
@@ -467,7 +577,8 @@ void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)
 {
     base->BAUD &= ~((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK));
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
-    base->FIFO &= ~((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
+    base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) &
+                 ~((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
 #endif
     mask &= 0xFFFFFF00U;
     base->CTRL &= ~mask;
@@ -503,24 +614,24 @@ status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)
     status_t status;
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
     temp = (uint32_t)base->FIFO;
-    temp &= (uint32_t)(~(kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag));
-    temp |= mask & (kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag);
+    temp &= (uint32_t)(~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK));
+    temp |= (mask << 16) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK);
     base->FIFO = temp;
 #endif
     temp = (uint32_t)base->STAT;
 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
-    temp &= (uint32_t)(~(kLPUART_LinBreakFlag));
-    temp |= mask & kLPUART_LinBreakFlag;
+    temp &= (uint32_t)(~(LPUART_STAT_LBKDIF_MASK));
+    temp |= mask & LPUART_STAT_LBKDIF_MASK;
 #endif
-    temp &= (uint32_t)(~(kLPUART_RxActiveEdgeFlag | kLPUART_IdleLineFlag | kLPUART_RxOverrunFlag |
-                         kLPUART_NoiseErrorFlag | kLPUART_FramingErrorFlag | kLPUART_ParityErrorFlag));
-    temp |= mask & (kLPUART_RxActiveEdgeFlag | kLPUART_IdleLineFlag | kLPUART_RxOverrunFlag | kLPUART_NoiseErrorFlag |
-                    kLPUART_FramingErrorFlag | kLPUART_ParityErrorFlag);
+    temp &= (uint32_t)(~(LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
+                         LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK));
+    temp |= mask & (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
+                    LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
-    temp &= (uint32_t)(~(kLPUART_DataMatch2Flag | kLPUART_DataMatch2Flag));
-    temp |= mask & (kLPUART_DataMatch2Flag | kLPUART_DataMatch2Flag);
+    temp &= (uint32_t)(~(LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK));
+    temp |= mask & (LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK);
 #endif
-    base->STAT |= temp;
+    base->STAT = temp;
     /* If some flags still pending. */
     if (mask & LPUART_GetStatusFlags(base))
     {
@@ -540,6 +651,8 @@ status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)
 
 void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
 {
+    assert(data);
+
     /* This API can only ensure that the data is written into the data buffer but can't
     ensure all data in the data buffer are sent into the transmit shift buffer. */
     while (length--)
@@ -553,7 +666,15 @@ void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
 
 status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)
 {
+    assert(data);
+
     uint32_t statusFlag;
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl = base->CTRL;
+    bool isSevenDataBits =
+        ((ctrl & LPUART_CTRL_M7_MASK) ||
+         ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
+#endif
 
     while (length--)
     {
@@ -589,7 +710,18 @@ status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)
                 return kStatus_LPUART_ParityError;
             }
         }
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+        if (isSevenDataBits)
+        {
+            *(data++) = (base->DATA & 0x7F);
+        }
+        else
+        {
+            *(data++) = base->DATA;
+        }
+#else
         *(data++) = base->DATA;
+#endif
     }
 
     return kStatus_Success;
@@ -603,6 +735,12 @@ void LPUART_TransferCreateHandle(LPUART_Type *base,
     assert(handle);
 
     uint32_t instance;
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl = base->CTRL;
+    bool isSevenDataBits =
+        ((ctrl & LPUART_CTRL_M7_MASK) ||
+         ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
+#endif
 
     /* Zero the handle. */
     memset(handle, 0, sizeof(lpuart_handle_t));
@@ -615,6 +753,11 @@ void LPUART_TransferCreateHandle(LPUART_Type *base,
     handle->callback = callback;
     handle->userData = userData;
 
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    /* Initial seven data bits flag */
+    handle->isSevenDataBits = isSevenDataBits;
+#endif
+
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
     /* Note:
        Take care of the RX FIFO, RX interrupt request only assert when received bytes
@@ -624,7 +767,7 @@ void LPUART_TransferCreateHandle(LPUART_Type *base,
        5 bytes are received. the last byte will be saved in FIFO but not trigger
        RX interrupt because the water mark is 2.
      */
-    base->WATER &= (~LPUART_WATER_RXWATER_SHIFT);
+    base->WATER &= (~LPUART_WATER_RXWATER_MASK);
 #endif
 
     /* Get instance from peripheral base address. */
@@ -635,8 +778,13 @@ void LPUART_TransferCreateHandle(LPUART_Type *base,
 
     s_lpuartIsr = LPUART_TransferHandleIRQ;
 
-    /* Enable interrupt in NVIC. */
+/* Enable interrupt in NVIC. */
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+    EnableIRQ(s_lpuartRxIRQ[instance]);
+    EnableIRQ(s_lpuartTxIRQ[instance]);
+#else
     EnableIRQ(s_lpuartIRQ[instance]);
+#endif
 }
 
 void LPUART_TransferStartRingBuffer(LPUART_Type *base,
@@ -645,18 +793,16 @@ void LPUART_TransferStartRingBuffer(LPUART_Type *base,
                                     size_t ringBufferSize)
 {
     assert(handle);
+    assert(ringBuffer);
 
     /* Setup the ring buffer address */
-    if (ringBuffer)
-    {
-        handle->rxRingBuffer = ringBuffer;
-        handle->rxRingBufferSize = ringBufferSize;
-        handle->rxRingBufferHead = 0U;
-        handle->rxRingBufferTail = 0U;
+    handle->rxRingBuffer = ringBuffer;
+    handle->rxRingBufferSize = ringBufferSize;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
 
-        /* Enable the interrupt to accept the data when user need the ring buffer. */
-        LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
-    }
+    /* Enable the interrupt to accept the data when user need the ring buffer. */
+    LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable);
 }
 
 void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle)
@@ -676,13 +822,12 @@ void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle)
 
 status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer)
 {
-    status_t status;
+    assert(handle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
 
-    /* Return error if xfer invalid. */
-    if ((0U == xfer->dataSize) || (NULL == xfer->data))
-    {
-        return kStatus_InvalidArgument;
-    }
+    status_t status;
 
     /* Return error if current TX busy. */
     if (kLPUART_TxBusy == handle->txState)
@@ -707,6 +852,8 @@ status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *hand
 
 void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle)
 {
+    assert(handle);
+
     LPUART_DisableInterrupts(base, kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_TransmissionCompleteInterruptEnable);
 
     handle->txDataSize = 0;
@@ -715,16 +862,14 @@ void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle)
 
 status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
 {
+    assert(handle);
+    assert(count);
+
     if (kLPUART_TxIdle == handle->txState)
     {
         return kStatus_NoTransferInProgress;
     }
 
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
     *count = handle->txDataSizeAll - handle->txDataSize;
 
     return kStatus_Success;
@@ -735,6 +880,11 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
                                            lpuart_transfer_t *xfer,
                                            size_t *receivedBytes)
 {
+    assert(handle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
+
     uint32_t i;
     status_t status;
     /* How many bytes to copy from ring buffer to user memory. */
@@ -743,13 +893,6 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
     size_t bytesToReceive;
     /* How many bytes currently have received. */
     size_t bytesCurrentReceived;
-    uint32_t regPrimask = 0U;
-
-    /* Return error if xfer invalid. */
-    if ((0U == xfer->dataSize) || (NULL == xfer->data))
-    {
-        return kStatus_InvalidArgument;
-    }
 
     /* How to get data:
        1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
@@ -773,8 +916,8 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
         /* If RX ring buffer is used. */
         if (handle->rxRingBuffer)
         {
-            /* Disable IRQ, protect ring buffer. */
-            regPrimask = DisableGlobalIRQ();
+            /* Disable LPUART RX IRQ, protect ring buffer. */
+            LPUART_DisableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable);
 
             /* How many bytes in RX ring buffer currently. */
             bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle);
@@ -811,8 +954,8 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
                 handle->rxDataSizeAll = bytesToReceive;
                 handle->rxState = kLPUART_RxBusy;
             }
-            /* Enable IRQ if previously enabled. */
-            EnableGlobalIRQ(regPrimask);
+            /* Enable LPUART RX IRQ if previously enabled. */
+            LPUART_EnableInterrupts(base, kLPUART_RxDataRegFullInterruptEnable);
 
             /* Call user callback since all data are received. */
             if (0 == bytesToReceive)
@@ -849,6 +992,8 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
 
 void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)
 {
+    assert(handle);
+
     /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
     if (!handle->rxRingBuffer)
     {
@@ -862,16 +1007,14 @@ void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)
 
 status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
 {
+    assert(handle);
+    assert(count);
+
     if (kLPUART_RxIdle == handle->rxState)
     {
         return kStatus_NoTransferInProgress;
     }
 
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
     *count = handle->rxDataSizeAll - handle->rxDataSize;
 
     return kStatus_Success;
@@ -879,19 +1022,17 @@ status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *hand
 
 void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
 {
+    assert(handle);
+
     uint8_t count;
     uint8_t tempCount;
-    volatile uint8_t dummy;
-
-    assert(handle);
 
     /* If RX overrun. */
     if (LPUART_STAT_OR_MASK & base->STAT)
     {
-        /* Read base->DATA, otherwise the RX does not work. */
-        dummy = base->DATA;
-        /* Avoid optimization */
-        dummy++;
+        /* Clear overrun flag, otherwise the RX does not work. */
+        base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK);
+
         /* Trigger callback. */
         if (handle->callback)
         {
@@ -964,8 +1105,19 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
                     }
                 }
 
-                /* Read data. */
+/* Read data. */
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+                if (handle->isSevenDataBits)
+                {
+                    handle->rxRingBuffer[handle->rxRingBufferHead] = (base->DATA & 0x7F);
+                }
+                else
+                {
+                    handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA;
+                }
+#else
                 handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA;
+#endif
 
                 /* Increase handle->rxRingBufferHead. */
                 if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
@@ -1033,71 +1185,113 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle)
 
 void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle)
 {
-    /* TODO: To be implemented. */
+    /* To be implemented by User. */
 }
 
 #if defined(LPUART0)
-void LPUART0_DriverIRQHandler(void)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART0_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
+}
+void LPUART0_RX_DriverIRQHandler(void)
 {
     s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
 }
-void LPUART0_RX_TX_DriverIRQHandler(void)
+#else
+void LPUART0_DriverIRQHandler(void)
 {
-    LPUART0_DriverIRQHandler();
+    s_lpuartIsr(LPUART0, s_lpuartHandle[0]);
 }
 #endif
+#endif
 
 #if defined(LPUART1)
-void LPUART1_DriverIRQHandler(void)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART1_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
+}
+void LPUART1_RX_DriverIRQHandler(void)
 {
     s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
 }
-void LPUART1_RX_TX_DriverIRQHandler(void)
+#else
+void LPUART1_DriverIRQHandler(void)
 {
-    LPUART1_DriverIRQHandler();
+    s_lpuartIsr(LPUART1, s_lpuartHandle[1]);
 }
 #endif
+#endif
 
 #if defined(LPUART2)
-void LPUART2_DriverIRQHandler(void)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART2_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
+}
+void LPUART2_RX_DriverIRQHandler(void)
 {
     s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
 }
-void LPUART2_RX_TX_DriverIRQHandler(void)
+#else
+void LPUART2_DriverIRQHandler(void)
 {
-    LPUART2_DriverIRQHandler();
+    s_lpuartIsr(LPUART2, s_lpuartHandle[2]);
 }
 #endif
+#endif
 
 #if defined(LPUART3)
-void LPUART3_DriverIRQHandler(void)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART3_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
+}
+void LPUART3_RX_DriverIRQHandler(void)
 {
     s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
 }
-void LPUART3_RX_TX_DriverIRQHandler(void)
+#else
+void LPUART3_DriverIRQHandler(void)
 {
-    LPUART3_DriverIRQHandler();
+    s_lpuartIsr(LPUART3, s_lpuartHandle[3]);
 }
 #endif
+#endif
 
 #if defined(LPUART4)
-void LPUART4_DriverIRQHandler(void)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART4_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
+}
+void LPUART4_RX_DriverIRQHandler(void)
 {
     s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
 }
-void LPUART4_RX_TX_DriverIRQHandler(void)
+#else
+void LPUART4_DriverIRQHandler(void)
 {
-    LPUART4_DriverIRQHandler();
+    s_lpuartIsr(LPUART4, s_lpuartHandle[4]);
 }
 #endif
+#endif
 
 #if defined(LPUART5)
-void LPUART5_DriverIRQHandler(void)
+#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
+void LPUART5_TX_DriverIRQHandler(void)
+{
+    s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
+}
+void LPUART5_RX_DriverIRQHandler(void)
 {
     s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
 }
-void LPUART5_RX_TX_DriverIRQHandler(void)
+#else
+void LPUART5_DriverIRQHandler(void)
 {
-    LPUART5_DriverIRQHandler();
+    s_lpuartIsr(LPUART5, s_lpuartHandle[5]);
 }
 #endif
+#endif
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart.h
index a357400b56a..0c60f82d88f 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart.h
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,36 +37,35 @@
  * @{
  */
 
-/*! @file*/
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief LPUART driver version 2.1.0. */
-#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*! @brief LPUART driver version 2.2.3. */
+#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 3))
 /*@}*/
 
 /*! @brief Error codes for the LPUART driver. */
 enum _lpuart_status
 {
-    kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0),              /*!< TX busy */
-    kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1),              /*!< RX busy */
-    kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2),              /*!< LPUART transmitter is idle. */
-    kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3),              /*!< LPUART receiver is idle. */
-    kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large  */
-    kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large  */
-    kStatus_LPUART_FlagCannotClearManually =
-        MAKE_STATUS(kStatusGroup_LPUART, 6),                    /*!< Some flag can't manually clear */
-    kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */
+    kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0),                  /*!< TX busy */
+    kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1),                  /*!< RX busy */
+    kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2),                  /*!< LPUART transmitter is idle. */
+    kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3),                  /*!< LPUART receiver is idle. */
+    kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4),     /*!< TX FIFO watermark too large  */
+    kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5),     /*!< RX FIFO watermark too large  */
+    kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */
+    kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7),                   /*!< Error happens on LPUART. */
     kStatus_LPUART_RxRingBufferOverrun =
         MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */
     kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */
     kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10),       /*!< LPUART noise error. */
     kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11),     /*!< LPUART framing error. */
     kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12),      /*!< LPUART parity error. */
+    kStatus_LPUART_BaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */
 };
 
 /*! @brief LPUART parity mode. */
@@ -77,6 +76,15 @@ typedef enum _lpuart_parity_mode
     kLPUART_ParityOdd = 0x3U,      /*!< Parity enabled, type odd,  bit setting: PE|PT = 11 */
 } lpuart_parity_mode_t;
 
+/*! @brief LPUART data bits count. */
+typedef enum _lpuart_data_bits
+{
+    kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */
+#endif
+} lpuart_data_bits_t;
+
 /*! @brief LPUART stop bit count. */
 typedef enum _lpuart_stop_bit_count
 {
@@ -158,11 +166,13 @@ enum _lpuart_flags
 #endif
 };
 
-/*! @brief LPUART configure structure. */
+/*! @brief LPUART configuration structure. */
 typedef struct _lpuart_config
 {
-    uint32_t baudRate_Bps;           /*!< LPUART baud rate  */
-    lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
+    uint32_t baudRate_Bps;            /*!< LPUART baud rate  */
+    lpuart_parity_mode_t parityMode;  /*!< Parity mode, disabled (default), even, odd */
+    lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */
+    bool isMsb;                       /*!< Data bits order, LSB (default), MSB */
 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
     lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
 #endif
@@ -206,7 +216,11 @@ struct _lpuart_handle
     void *userData;                      /*!< LPUART callback function parameter.*/
 
     volatile uint8_t txState; /*!< TX transfer state. */
-    volatile uint8_t rxState; /*!< RX transfer state */
+    volatile uint8_t rxState; /*!< RX transfer state. */
+
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    bool isSevenDataBits; /*!< Seven data bits flag. */
+#endif
 };
 
 /*******************************************************************************
@@ -217,32 +231,59 @@ struct _lpuart_handle
 extern "C" {
 #endif /* _cplusplus */
 
+#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL
+
+/*!
+ * @name Software Reset
+ * @{
+ */
+
+/*!
+ * @brief Resets the LPUART using software.
+ *
+ * This function resets all internal logic and registers except the Global Register.
+ * Remains set until cleared by software.
+ *
+ * @param base LPUART peripheral base address.
+ */
+static inline void LPUART_SoftwareReset(LPUART_Type *base)
+{
+    base->GLOBAL |= LPUART_GLOBAL_RST_MASK;
+    base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
+}
+/* @} */
+#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/
+
 /*!
  * @name Initialization and deinitialization
  * @{
  */
 
 /*!
-* @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock.
-*
-* This function configures the LPUART module with  user-defined settings. Call the LPUART_GetDefaultConfig() function
-* to configure the configuration structure and get the default configuration.
-* The example below shows how to use this API to configure the LPUART.
-* @code
-*  lpuart_config_t lpuartConfig;
-*  lpuartConfig.baudRate_Bps = 115200U;
-*  lpuartConfig.parityMode = kLPUART_ParityDisabled;
-*  lpuartConfig.stopBitCount = kLPUART_OneStopBit;
-*  lpuartConfig.txFifoWatermark = 0;
-*  lpuartConfig.rxFifoWatermark = 1;
-*  LPUART_Init(LPUART1, &lpuartConfig, 20000000U);
-* @endcode
-*
-* @param base LPUART peripheral base address.
-* @param config Pointer to a user-defined configuration structure.
-* @param srcClock_Hz LPUART clock source frequency in HZ.
-*/
-void LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz);
+ * @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock.
+ *
+ * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function
+ * to configure the configuration structure and get the default configuration.
+ * The example below shows how to use this API to configure the LPUART.
+ * @code
+ *  lpuart_config_t lpuartConfig;
+ *  lpuartConfig.baudRate_Bps = 115200U;
+ *  lpuartConfig.parityMode = kLPUART_ParityDisabled;
+ *  lpuartConfig.dataBitsCount = kLPUART_EightDataBits;
+ *  lpuartConfig.isMsb = false;
+ *  lpuartConfig.stopBitCount = kLPUART_OneStopBit;
+ *  lpuartConfig.txFifoWatermark = 0;
+ *  lpuartConfig.rxFifoWatermark = 1;
+ *  LPUART_Init(LPUART1, &lpuartConfig, 20000000U);
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @param config Pointer to a user-defined configuration structure.
+ * @param srcClock_Hz LPUART clock source frequency in HZ.
+ * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success LPUART initialize succeed
+ */
+status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz);
 
 /*!
  * @brief Deinitializes a LPUART instance.
@@ -260,6 +301,8 @@ void LPUART_Deinit(LPUART_Type *base);
  * values are:
  *   lpuartConfig->baudRate_Bps = 115200U;
  *   lpuartConfig->parityMode = kLPUART_ParityDisabled;
+ *   lpuartConfig->dataBitsCount = kLPUART_EightDataBits;
+ *   lpuartConfig->isMsb = false;
  *   lpuartConfig->stopBitCount = kLPUART_OneStopBit;
  *   lpuartConfig->txFifoWatermark = 0;
  *   lpuartConfig->rxFifoWatermark = 1;
@@ -282,8 +325,10 @@ void LPUART_GetDefaultConfig(lpuart_config_t *config);
  * @param base LPUART peripheral base address.
  * @param baudRate_Bps LPUART baudrate to be set.
  * @param srcClock_Hz LPUART clock source frequency in HZ.
+ * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source.
+ * @retval kStatus_Success Set baudrate succeeded.
  */
-void LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
+status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
 
 /* @} */
 
@@ -512,24 +557,40 @@ static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data)
 }
 
 /*!
- * @brief Reads the RX register.
+ * @brief Reads the receiver register.
  *
- * This function reads data from the TX register directly. The upper layer must
- * ensure that the RX register is full or that the TX FIFO has data before calling this function.
+ * This function reads data from the receiver register directly. The upper layer must
+ * ensure that the receiver register is full or that the RX FIFO has data before calling this function.
  *
  * @param base LPUART peripheral base address.
  * @return Data read from data register.
  */
 static inline uint8_t LPUART_ReadByte(LPUART_Type *base)
 {
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl = base->CTRL;
+    bool isSevenDataBits =
+        ((ctrl & LPUART_CTRL_M7_MASK) ||
+         ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
+
+    if (isSevenDataBits)
+    {
+        return (base->DATA & 0x7F);
+    }
+    else
+    {
+        return base->DATA;
+    }
+#else
     return base->DATA;
+#endif
 }
 
 /*!
- * @brief Writes to transmitter register using a blocking method.
+ * @brief Writes to the transmitter register using a blocking method.
  *
  * This function polls the transmitter register, waits for the register to be empty or  for TX FIFO to have
- * room and then writes data to the transmitter buffer.
+ * room, and writes data to the transmitter buffer.
  *
  * @note This function does not check whether all data has been sent out to the bus.
  * Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is
@@ -542,10 +603,10 @@ static inline uint8_t LPUART_ReadByte(LPUART_Type *base)
 void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
 
 /*!
-* @brief Reads the RX data register using a blocking method.
+* @brief Reads the receiver data register using a blocking method.
  *
- * This function polls the RX register, waits for the RX register full or RX FIFO
- * has data then reads data from the TX register.
+ * This function polls the receiver register, waits for the receiver register full or receiver FIFO
+ * has data, and reads data from the TX register.
  *
  * @param base LPUART peripheral base address.
  * @param data Start address of the buffer to store the received data.
@@ -601,7 +662,7 @@ void LPUART_TransferCreateHandle(LPUART_Type *base,
  *
  * @param base LPUART peripheral base address.
  * @param handle LPUART handle pointer.
- * @param xfer LPUART transfer structure, refer to #lpuart_transfer_t.
+ * @param xfer LPUART transfer structure, see #lpuart_transfer_t.
  * @retval kStatus_Success Successfully start the data transmission.
  * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register.
  * @retval kStatus_InvalidArgument Invalid argument.
@@ -631,7 +692,7 @@ void LPUART_TransferStartRingBuffer(LPUART_Type *base,
                                     size_t ringBufferSize);
 
 /*!
- * @brief Abort the background transfer and uninstall the ring buffer.
+ * @brief Aborts the background transfer and uninstalls the ring buffer.
  *
  * This function aborts the background transfer and uninstalls the ring buffer.
  *
@@ -644,7 +705,7 @@ void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle);
  * @brief Aborts the interrupt-driven data transmit.
  *
  * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
- * how many bytes are still not sent out.
+ * how many bytes are not sent out.
  *
  * @param base LPUART peripheral base address.
  * @param handle LPUART handle pointer.
@@ -652,10 +713,10 @@ void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle);
 void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle);
 
 /*!
- * @brief Get the number of bytes that have been written to LPUART TX register.
+ * @brief Gets the number of bytes that have been written to the LPUART transmitter register.
  *
  * This function gets the number of bytes that have been written to LPUART TX
- * register by interrupt method.
+ * register by an interrupt method.
  *
  * @param base LPUART peripheral base address.
  * @param handle LPUART handle pointer.
@@ -686,7 +747,7 @@ status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle,
  *
  * @param base LPUART peripheral base address.
  * @param handle LPUART handle pointer.
- * @param xfer LPUART transfer structure, refer to #uart_transfer_t.
+ * @param xfer LPUART transfer structure, see #uart_transfer_t.
  * @param receivedBytes Bytes received from the ring buffer directly.
  * @retval kStatus_Success Successfully queue the transfer into the transmit queue.
  * @retval kStatus_LPUART_RxBusy Previous receive request is not finished.
@@ -709,7 +770,7 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
 void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle);
 
 /*!
- * @brief Get the number of bytes that have been received.
+ * @brief Gets the number of bytes that have been received.
  *
  * This function gets the number of bytes that have been received.
  *
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart_edma.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart_edma.c
index b4242f62625..24da4831477 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart_edma.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart_edma.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -98,6 +98,8 @@ extern uint32_t LPUART_GetInstance(LPUART_Type *base);
 
 static void LPUART_SendEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
 {
+    assert(param);
+
     lpuart_edma_private_handle_t *lpuartPrivateHandle = (lpuart_edma_private_handle_t *)param;
 
     /* Avoid the warning for unused variables. */
@@ -118,6 +120,8 @@ static void LPUART_SendEDMACallback(edma_handle_t *handle, void *param, bool tra
 
 static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
 {
+    assert(param);
+
     lpuart_edma_private_handle_t *lpuartPrivateHandle = (lpuart_edma_private_handle_t *)param;
 
     /* Avoid warning for unused parameters. */
@@ -138,11 +142,11 @@ static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool
 }
 
 void LPUART_TransferCreateHandleEDMA(LPUART_Type *base,
-                             lpuart_edma_handle_t *handle,
-                             lpuart_edma_transfer_callback_t callback,
-                             void *userData,
-                             edma_handle_t *txEdmaHandle,
-                             edma_handle_t *rxEdmaHandle)
+                                     lpuart_edma_handle_t *handle,
+                                     lpuart_edma_transfer_callback_t callback,
+                                     void *userData,
+                                     edma_handle_t *txEdmaHandle,
+                                     edma_handle_t *rxEdmaHandle)
 {
     assert(handle);
 
@@ -189,19 +193,18 @@ void LPUART_TransferCreateHandleEDMA(LPUART_Type *base,
         EDMA_SetCallback(handle->rxEdmaHandle, LPUART_ReceiveEDMACallback, &s_edmaPrivateHandle[instance]);
     }
 }
+
 status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)
 {
+    assert(handle);
     assert(handle->txEdmaHandle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
 
     edma_transfer_config_t xferConfig;
     status_t status;
 
-    /* Return error if xfer invalid. */
-    if ((0U == xfer->dataSize) || (NULL == xfer->data))
-    {
-        return kStatus_InvalidArgument;
-    }
-
     /* If previous TX not finished. */
     if (kLPUART_TxBusy == handle->txState)
     {
@@ -216,6 +219,9 @@ status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart
         EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)LPUART_GetDataRegisterAddress(base),
                              sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_MemoryToPeripheral);
 
+        /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */
+        handle->nbytes = sizeof(uint8_t);
+
         /* Submit transfer. */
         EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig);
         EDMA_StartTransfer(handle->txEdmaHandle);
@@ -231,17 +237,15 @@ status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart
 
 status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)
 {
+    assert(handle);
     assert(handle->rxEdmaHandle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
 
     edma_transfer_config_t xferConfig;
     status_t status;
 
-    /* Return error if xfer invalid. */
-    if ((0U == xfer->dataSize) || (NULL == xfer->data))
-    {
-        return kStatus_InvalidArgument;
-    }
-
     /* If previous RX not finished. */
     if (kLPUART_RxBusy == handle->rxState)
     {
@@ -256,6 +260,9 @@ status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpu
         EDMA_PrepareTransfer(&xferConfig, (void *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data,
                              sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory);
 
+        /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */
+        handle->nbytes = sizeof(uint8_t);
+
         /* Submit transfer. */
         EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig);
         EDMA_StartTransfer(handle->rxEdmaHandle);
@@ -271,6 +278,7 @@ status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpu
 
 void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)
 {
+    assert(handle);
     assert(handle->txEdmaHandle);
 
     /* Disable LPUART TX EDMA. */
@@ -284,6 +292,7 @@ void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handl
 
 void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle)
 {
+    assert(handle);
     assert(handle->rxEdmaHandle);
 
     /* Disable LPUART RX EDMA. */
@@ -297,38 +306,36 @@ void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *ha
 
 status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)
 {
+    assert(handle);
     assert(handle->rxEdmaHandle);
+    assert(count);
 
     if (kLPUART_RxIdle == handle->rxState)
     {
         return kStatus_NoTransferInProgress;
     }
 
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    *count = handle->rxDataSizeAll - EDMA_GetRemainingBytes(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel);
+    *count = handle->rxDataSizeAll -
+             (uint32_t)handle->nbytes *
+                 EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel);
 
     return kStatus_Success;
 }
 
 status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count)
 {
+    assert(handle);
     assert(handle->txEdmaHandle);
+    assert(count);
 
     if (kLPUART_TxIdle == handle->txState)
     {
         return kStatus_NoTransferInProgress;
     }
 
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    *count = handle->txDataSizeAll - EDMA_GetRemainingBytes(handle->txEdmaHandle->base, handle->txEdmaHandle->channel);
+    *count = handle->txDataSizeAll -
+             (uint32_t)handle->nbytes *
+                 EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel);
 
     return kStatus_Success;
 }
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart_edma.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart_edma.h
index 35e922e1251..79565c688d6 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart_edma.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_lpuart_edma.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -39,8 +39,6 @@
  * @{
  */
 
-/*! @file*/
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
@@ -67,6 +65,8 @@ struct _lpuart_edma_handle
     edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */
     edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */
 
+    uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */
+
     volatile uint8_t txState; /*!< TX transfer state. */
     volatile uint8_t rxState; /*!< RX transfer state */
 };
@@ -94,11 +94,11 @@ extern "C" {
  * @param rxEdmaHandle User requested DMA handle for RX DMA transfer.
  */
 void LPUART_TransferCreateHandleEDMA(LPUART_Type *base,
-                             lpuart_edma_handle_t *handle,
-                             lpuart_edma_transfer_callback_t callback,
-                             void *userData,
-                             edma_handle_t *txEdmaHandle,
-                             edma_handle_t *rxEdmaHandle);
+                                     lpuart_edma_handle_t *handle,
+                                     lpuart_edma_transfer_callback_t callback,
+                                     void *userData,
+                                     edma_handle_t *txEdmaHandle,
+                                     edma_handle_t *rxEdmaHandle);
 
 /*!
  * @brief Sends data using eDMA.
@@ -123,7 +123,7 @@ status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart
  *
  * @param base LPUART peripheral base address.
  * @param handle Pointer to lpuart_edma_handle_t structure.
- * @param xfer LPUART eDMA transfer structure, refer to #lpuart_transfer_t.
+ * @param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t.
  * @retval kStatus_Success if succeed, others fail.
  * @retval kStatus_LPUART_RxBusy Previous transfer ongoing.
  * @retval kStatus_InvalidArgument Invalid argument.
@@ -151,9 +151,9 @@ void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handl
 void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle);
 
 /*!
- * @brief Get the number of bytes that have been written to LPUART TX register.
+ * @brief Gets the number of bytes written to the LPUART TX register.
  *
- * This function gets the number of bytes that have been written to LPUART TX
+ * This function gets the number of bytes written to the LPUART TX
  * register by DMA.
  *
  * @param base LPUART peripheral base address.
@@ -166,9 +166,9 @@ void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *ha
 status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count);
 
 /*!
- * @brief Get the number of bytes that have been received.
+ * @brief Gets the number of received bytes.
  *
- * This function gets the number of bytes that have been received.
+ * This function gets the number of received bytes.
  *
  * @param base LPUART peripheral base address.
  * @param handle LPUART handle pointer.
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_mpu.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_mpu.c
deleted file mode 100644
index 926eff9641f..00000000000
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_mpu.c
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "fsl_mpu.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/* Defines the register numbers of the region descriptor configure. */
-#define MPU_REGIONDESCRIPTOR_WROD_REGNUM (4U)
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-
-const clock_ip_name_t g_mpuClock[FSL_FEATURE_SOC_MPU_COUNT] = MPU_CLOCKS;
-
-/*******************************************************************************
- * Codes
- ******************************************************************************/
-
-void MPU_Init(MPU_Type *base, const mpu_config_t *config)
-{
-    assert(config);
-    uint8_t count;
-
-    /* Un-gate MPU clock */
-    CLOCK_EnableClock(g_mpuClock[0]);
-
-    /* Initializes the regions. */
-    for (count = 1; count < FSL_FEATURE_MPU_DESCRIPTOR_COUNT; count++)
-    {
-        base->WORD[count][3] = 0; /* VLD/VID+PID. */
-        base->WORD[count][0] = 0; /* Start address. */
-        base->WORD[count][1] = 0; /* End address. */
-        base->WORD[count][2] = 0; /* Access rights. */
-        base->RGDAAC[count] = 0;  /* Alternate access rights. */
-    }
-
-    /* MPU configure. */
-    while (config)
-    {
-        MPU_SetRegionConfig(base, &(config->regionConfig));
-        config = config->next;
-    }
-    /* Enable MPU. */
-    MPU_Enable(base, true);
-}
-
-void MPU_Deinit(MPU_Type *base)
-{
-    /* Disable MPU. */
-    MPU_Enable(base, false);
-
-    /* Gate the clock. */
-    CLOCK_DisableClock(g_mpuClock[0]);
-}
-
-void MPU_GetHardwareInfo(MPU_Type *base, mpu_hardware_info_t *hardwareInform)
-{
-    assert(hardwareInform);
-
-    uint32_t cesReg = base->CESR;
-
-    hardwareInform->hardwareRevisionLevel = (cesReg & MPU_CESR_HRL_MASK) >> MPU_CESR_HRL_SHIFT;
-    hardwareInform->slavePortsNumbers = (cesReg & MPU_CESR_NSP_MASK) >> MPU_CESR_NSP_SHIFT;
-    hardwareInform->regionsNumbers = (mpu_region_total_num_t)((cesReg & MPU_CESR_NRGD_MASK) >> MPU_CESR_NRGD_SHIFT);
-}
-
-void MPU_SetRegionConfig(MPU_Type *base, const mpu_region_config_t *regionConfig)
-{
-    assert(regionConfig);
-
-    uint32_t wordReg = 0;
-    uint8_t count;
-    uint8_t number = regionConfig->regionNum;
-
-    /* The start and end address of the region descriptor. */
-    base->WORD[number][0] = regionConfig->startAddress;
-    base->WORD[number][1] = regionConfig->endAddress;
-
-    /* The region descriptor access rights control. */
-    for (count = 0; count < MPU_REGIONDESCRIPTOR_WROD_REGNUM; count++)
-    {
-        wordReg |= MPU_WORD_LOW_MASTER(count, (((uint32_t)regionConfig->accessRights1[count].superAccessRights << 3U) |
-                                               (uint8_t)regionConfig->accessRights1[count].userAccessRights)) |
-                   MPU_WORD_HIGH_MASTER(count, ((uint32_t)regionConfig->accessRights2[count].readEnable << 1U |
-                                                (uint8_t)regionConfig->accessRights2[count].writeEnable));
-
-#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
-        wordReg |= MPU_WORD_MASTER_PE(count, regionConfig->accessRights1[count].processIdentifierEnable);
-#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
-    }
-
-    /* Set region descriptor access rights. */
-    base->WORD[number][2] = wordReg;
-
-    wordReg = MPU_WORD_VLD(1);
-#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
-    wordReg |= MPU_WORD_PID(regionConfig->processIdentifier) | MPU_WORD_PIDMASK(regionConfig->processIdMask);
-#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
-
-    base->WORD[number][3] = wordReg;
-}
-
-void MPU_SetRegionAddr(MPU_Type *base, mpu_region_num_t regionNum, uint32_t startAddr, uint32_t endAddr)
-{
-    base->WORD[regionNum][0] = startAddr;
-    base->WORD[regionNum][1] = endAddr;
-}
-
-void MPU_SetRegionLowMasterAccessRights(MPU_Type *base,
-                                        mpu_region_num_t regionNum,
-                                        mpu_master_t masterNum,
-                                        const mpu_low_masters_access_rights_t *accessRights)
-{
-    assert(accessRights);
-#if FSL_FEATURE_MPU_HAS_MASTER4
-    assert(masterNum < kMPU_Master4);
-#endif
-    uint32_t mask = MPU_WORD_LOW_MASTER_MASK(masterNum);
-    uint32_t right = base->RGDAAC[regionNum];
-
-#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
-    mask |= MPU_LOW_MASTER_PE_MASK(masterNum);
-#endif
-
-    /* Build rights control value. */
-    right &= ~mask;
-    right |= MPU_WORD_LOW_MASTER(masterNum,
-                                 ((uint32_t)(accessRights->superAccessRights << 3U) | accessRights->userAccessRights));
-#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
-    right |= MPU_WORD_MASTER_PE(masterNum, accessRights->processIdentifierEnable);
-#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
-
-    /* Set low master region access rights. */
-    base->RGDAAC[regionNum] = right;
-}
-
-void MPU_SetRegionHighMasterAccessRights(MPU_Type *base,
-                                         mpu_region_num_t regionNum,
-                                         mpu_master_t masterNum,
-                                         const mpu_high_masters_access_rights_t *accessRights)
-{
-    assert(accessRights);
-#if FSL_FEATURE_MPU_HAS_MASTER3
-    assert(masterNum > kMPU_Master3);
-#endif
-    uint32_t mask = MPU_WORD_HIGH_MASTER_MASK(masterNum);
-    uint32_t right = base->RGDAAC[regionNum];
-
-    /* Build rights control value. */
-    right &= ~mask;
-    right |= MPU_WORD_HIGH_MASTER((masterNum - (uint8_t)kMPU_RegionNum04),
-                                  (((uint32_t)accessRights->readEnable << 1U) | accessRights->writeEnable));
-    /* Set low master region access rights. */
-    base->RGDAAC[regionNum] = right;
-}
-
-bool MPU_GetSlavePortErrorStatus(MPU_Type *base, mpu_slave_t slaveNum)
-{
-    uint8_t sperr;
-
-    sperr = ((base->CESR & MPU_CESR_SPERR_MASK) >> MPU_CESR_SPERR_SHIFT) & (0x1U << slaveNum);
-
-    return (sperr != 0) ? true : false;
-}
-
-void MPU_GetDetailErrorAccessInfo(MPU_Type *base, mpu_slave_t slaveNum, mpu_access_err_info_t *errInform)
-{
-    assert(errInform);
-
-    uint16_t value;
-
-    /* Error address. */
-    errInform->address = base->SP[slaveNum].EAR;
-
-    /* Error detail information. */
-    value = (base->SP[slaveNum].EDR & MPU_EDR_EACD_MASK) >> MPU_EDR_EACD_SHIFT;
-    if (!value)
-    {
-        errInform->accessControl = kMPU_NoRegionHit;
-    }
-    else if (!(value & (uint16_t)(value - 1)))
-    {
-        errInform->accessControl = kMPU_NoneOverlappRegion;
-    }
-    else
-    {
-        errInform->accessControl = kMPU_OverlappRegion;
-    }
-
-    value = base->SP[slaveNum].EDR;
-    errInform->master = (mpu_master_t)((value & MPU_EDR_EMN_MASK) >> MPU_EDR_EMN_SHIFT);
-    errInform->attributes = (mpu_err_attributes_t)((value & MPU_EDR_EATTR_MASK) >> MPU_EDR_EATTR_SHIFT);
-    errInform->accessType = (mpu_err_access_type_t)((value & MPU_EDR_ERW_MASK) >> MPU_EDR_ERW_SHIFT);
-#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
-    errInform->processorIdentification = (uint8_t)((value & MPU_EDR_EPID_MASK) >> MPU_EDR_EPID_SHIFT);
-#endif
-
-    /*!< Clears error slave port bit. */
-    value = (base->CESR & ~MPU_CESR_SPERR_MASK) | (0x1U << slaveNum);
-    base->CESR = value;
-}
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_mpu.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_mpu.h
deleted file mode 100644
index acdcfd1be38..00000000000
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_mpu.h
+++ /dev/null
@@ -1,495 +0,0 @@
-/*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_MPU_H_
-#define _FSL_MPU_H_
-
-#include "fsl_common.h"
-
-/*!
- * @addtogroup mpu
- * @{
- */
-
-/*! @file */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief MPU driver version 2.0.0. */
-#define FSL_MPU_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
-/*! @brief MPU low master bit shift. */
-#define MPU_WORD_LOW_MASTER_SHIFT(n) (n * 6)
-
-/*! @brief MPU low master bit mask. */
-#define MPU_WORD_LOW_MASTER_MASK(n) (0x1Fu << MPU_WORD_LOW_MASTER_SHIFT(n))
-
-/*! @brief MPU low master bit width. */
-#define MPU_WORD_LOW_MASTER_WIDTH 5
-
-/*! @brief MPU low master priority setting. */
-#define MPU_WORD_LOW_MASTER(n, x) \
-    (((uint32_t)(((uint32_t)(x)) << MPU_WORD_LOW_MASTER_SHIFT(n))) & MPU_WORD_LOW_MASTER_MASK(n))
-
-/*! @brief MPU low master process enable bit shift. */
-#define MPU_LOW_MASTER_PE_SHIFT(n) (n * 6 + 5)
-
-/*! @brief MPU low master process enable bit mask. */
-#define MPU_LOW_MASTER_PE_MASK(n) (0x1u << MPU_LOW_MASTER_PE_SHIFT(n))
-
-/*! @brief MPU low master process enable width. */
-#define MPU_WORD_MASTER_PE_WIDTH 1
-
-/*! @brief MPU low master process enable setting. */
-#define MPU_WORD_MASTER_PE(n, x) \
-    (((uint32_t)(((uint32_t)(x)) << MPU_LOW_MASTER_PE_SHIFT(n))) & MPU_LOW_MASTER_PE_MASK(n))
-
-/*! @brief MPU high master bit shift. */
-#define MPU_WORD_HIGH_MASTER_SHIFT(n) (n * 2 + 24)
-
-/*! @brief MPU high master bit mask. */
-#define MPU_WORD_HIGH_MASTER_MASK(n) (0x03u << MPU_WORD_HIGH_MASTER_SHIFT(n))
-
-/*! @brief MPU high master bit width. */
-#define MPU_WORD_HIGH_MASTER_WIDTH 2
-
-/*! @brief MPU high master priority setting. */
-#define MPU_WORD_HIGH_MASTER(n, x) \
-    (((uint32_t)(((uint32_t)(x)) << MPU_WORD_HIGH_MASTER_SHIFT(n))) & MPU_WORD_HIGH_MASTER_MASK(n))
-
-/*! @brief MPU region number. */
-typedef enum _mpu_region_num
-{
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 0U
-    kMPU_RegionNum00 = 0U, /*!< MPU region number 0. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 1U
-    kMPU_RegionNum01 = 1U, /*!< MPU region number 1. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 2U
-    kMPU_RegionNum02 = 2U, /*!< MPU region number 2. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 3U
-    kMPU_RegionNum03 = 3U, /*!< MPU region number 3. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 4U
-    kMPU_RegionNum04 = 4U, /*!< MPU region number 4. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 5U
-    kMPU_RegionNum05 = 5U, /*!< MPU region number 5. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 6U
-    kMPU_RegionNum06 = 6U, /*!< MPU region number 6. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 7U
-    kMPU_RegionNum07 = 7U, /*!< MPU region number 7. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 8U
-    kMPU_RegionNum08 = 8U, /*!< MPU region number 8. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 9U
-    kMPU_RegionNum09 = 9U, /*!< MPU region number 9. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 10U
-    kMPU_RegionNum10 = 10U, /*!< MPU region number 10. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 11U
-    kMPU_RegionNum11 = 11U, /*!< MPU region number 11. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 12U
-    kMPU_RegionNum12 = 12U, /*!< MPU region number 12. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 13U
-    kMPU_RegionNum13 = 13U, /*!< MPU region number 13. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 14U
-    kMPU_RegionNum14 = 14U, /*!< MPU region number 14. */
-#endif
-#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 15U
-    kMPU_RegionNum15 = 15U, /*!< MPU region number 15. */
-#endif
-} mpu_region_num_t;
-
-/*! @brief MPU master number. */
-typedef enum _mpu_master
-{
-#if FSL_FEATURE_MPU_HAS_MASTER0
-    kMPU_Master0 = 0U, /*!< MPU master core. */
-#endif
-#if FSL_FEATURE_MPU_HAS_MASTER1
-    kMPU_Master1 = 1U, /*!< MPU master defined in SoC. */
-#endif
-#if FSL_FEATURE_MPU_HAS_MASTER2
-    kMPU_Master2 = 2U, /*!< MPU master defined in SoC. */
-#endif
-#if FSL_FEATURE_MPU_HAS_MASTER3
-    kMPU_Master3 = 3U, /*!< MPU master defined in SoC. */
-#endif
-#if FSL_FEATURE_MPU_HAS_MASTER4
-    kMPU_Master4 = 4U, /*!< MPU master defined in SoC. */
-#endif
-#if FSL_FEATURE_MPU_HAS_MASTER5
-    kMPU_Master5 = 5U, /*!< MPU master defined in SoC. */
-#endif
-#if FSL_FEATURE_MPU_HAS_MASTER6
-    kMPU_Master6 = 6U, /*!< MPU master defined in SoC. */
-#endif
-#if FSL_FEATURE_MPU_HAS_MASTER7
-    kMPU_Master7 = 7U /*!< MPU master defined in SoC. */
-#endif
-} mpu_master_t;
-
-/*! @brief Describes the number of MPU regions. */
-typedef enum _mpu_region_total_num
-{
-    kMPU_8Regions = 0x0U,  /*!< MPU supports 8 regions.  */
-    kMPU_12Regions = 0x1U, /*!< MPU supports 12 regions. */
-    kMPU_16Regions = 0x2U  /*!< MPU supports 16 regions. */
-} mpu_region_total_num_t;
-
-/*! @brief MPU slave port number. */
-typedef enum _mpu_slave
-{
-    kMPU_Slave0 = 4U, /*!< MPU slave port 0. */
-    kMPU_Slave1 = 3U, /*!< MPU slave port 1. */
-    kMPU_Slave2 = 2U, /*!< MPU slave port 2. */
-    kMPU_Slave3 = 1U, /*!< MPU slave port 3. */
-    kMPU_Slave4 = 0U  /*!< MPU slave port 4. */
-} mpu_slave_t;
-
-/*! @brief MPU error access control detail. */
-typedef enum _mpu_err_access_control
-{
-    kMPU_NoRegionHit = 0U,        /*!< No region hit error. */
-    kMPU_NoneOverlappRegion = 1U, /*!< Access single region error. */
-    kMPU_OverlappRegion = 2U      /*!< Access overlapping region error. */
-} mpu_err_access_control_t;
-
-/*! @brief MPU error access type. */
-typedef enum _mpu_err_access_type
-{
-    kMPU_ErrTypeRead = 0U, /*!< MPU error access type --- read.  */
-    kMPU_ErrTypeWrite = 1U /*!< MPU error access type --- write. */
-} mpu_err_access_type_t;
-
-/*! @brief MPU access error attributes.*/
-typedef enum _mpu_err_attributes
-{
-    kMPU_InstructionAccessInUserMode = 0U,       /*!< Access instruction error in user mode. */
-    kMPU_DataAccessInUserMode = 1U,              /*!< Access data error in user mode. */
-    kMPU_InstructionAccessInSupervisorMode = 2U, /*!< Access instruction error in supervisor mode. */
-    kMPU_DataAccessInSupervisorMode = 3U         /*!< Access data error in supervisor mode. */
-} mpu_err_attributes_t;
-
-/*! @brief MPU access rights in supervisor mode for master port 0 ~ port 3. */
-typedef enum _mpu_supervisor_access_rights
-{
-    kMPU_SupervisorReadWriteExecute = 0U, /*!< Read write and execute operations are allowed in supervisor mode. */
-    kMPU_SupervisorReadExecute = 1U,      /*!< Read and execute operations are allowed in supervisor mode. */
-    kMPU_SupervisorReadWrite = 2U,        /*!< Read write operations are allowed in supervisor mode. */
-    kMPU_SupervisorEqualToUsermode = 3U   /*!< Access permission equal to user mode. */
-} mpu_supervisor_access_rights_t;
-
-/*! @brief MPU access rights in user mode for master port 0 ~ port 3. */
-typedef enum _mpu_user_access_rights
-{
-    kMPU_UserNoAccessRights = 0U,  /*!< No access allowed in user mode.  */
-    kMPU_UserExecute = 1U,         /*!< Execute operation is allowed in user mode. */
-    kMPU_UserWrite = 2U,           /*!< Write operation is allowed in user mode. */
-    kMPU_UserWriteExecute = 3U,    /*!< Write and execute operations are allowed in user mode. */
-    kMPU_UserRead = 4U,            /*!< Read is allowed in user mode. */
-    kMPU_UserReadExecute = 5U,     /*!< Read and execute operations are allowed in user mode. */
-    kMPU_UserReadWrite = 6U,       /*!< Read and write operations are allowed in user mode. */
-    kMPU_UserReadWriteExecute = 7U /*!< Read write and execute operations are allowed in user mode. */
-} mpu_user_access_rights_t;
-
-/*! @brief MPU hardware basic information. */
-typedef struct _mpu_hardware_info
-{
-    uint8_t hardwareRevisionLevel;         /*!< Specifies the MPU's hardware and definition reversion level. */
-    uint8_t slavePortsNumbers;             /*!< Specifies the number of slave ports connected to MPU. */
-    mpu_region_total_num_t regionsNumbers; /*!< Indicates the number of region descriptors implemented. */
-} mpu_hardware_info_t;
-
-/*! @brief MPU detail error access information. */
-typedef struct _mpu_access_err_info
-{
-    mpu_master_t master;                    /*!< Access error master. */
-    mpu_err_attributes_t attributes;        /*!< Access error attributes. */
-    mpu_err_access_type_t accessType;       /*!< Access error type. */
-    mpu_err_access_control_t accessControl; /*!< Access error control. */
-    uint32_t address;                       /*!< Access error address. */
-#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
-    uint8_t processorIdentification; /*!< Access error processor identification. */
-#endif                               /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
-} mpu_access_err_info_t;
-
-/*! @brief MPU access rights for low master master port 0 ~ port 3. */
-typedef struct _mpu_low_masters_access_rights
-{
-    mpu_supervisor_access_rights_t superAccessRights; /*!< Master access rights in supervisor mode. */
-    mpu_user_access_rights_t userAccessRights;        /*!< Master access rights in user mode. */
-#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
-    bool processIdentifierEnable; /*!< Enables or disables process identifier. */
-#endif                            /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
-} mpu_low_masters_access_rights_t;
-
-/*! @brief MPU access rights mode for high master port 4 ~ port 7. */
-typedef struct _mpu_high_masters_access_rights
-{
-    bool writeEnable; /*!< Enables or disables write permission. */
-    bool readEnable;  /*!< Enables or disables read permission.  */
-} mpu_high_masters_access_rights_t;
-
-/*!
- * @brief MPU region configuration structure.
- *
- * This structure is used to configure the regionNum region.
- * The accessRights1[0] ~ accessRights1[3] are used to configure the four low master
- * numbers: master 0 ~ master 3.   The accessRights2[0] ~ accessRights2[3] are
- * used to configure the four high master numbers: master 4 ~ master 7.
- * The master port assignment is the chip configuration. Normally, the core is the
- * master 0, debugger is the master 1.
- * Note: MPU assigns a priority scheme where the debugger is treated as the highest
- * priority master followed by the core and then all the remaining masters.
- * MPU protection does not allow writes from the core to affect the "regionNum 0" start
- * and end address nor the permissions associated with the debugger. It can only write
- * the permission fields associated with the other masters. This protection guarantee
- * the debugger always has access to the entire address space and those rights can't
- * be changed by the core or any other bus master. Prepare
- * the region configuration when regionNum is kMPU_RegionNum00.
- */
-typedef struct _mpu_region_config
-{
-    mpu_region_num_t regionNum; /*!< MPU region number. */
-    uint32_t startAddress; /*!< Memory region start address. Note: bit0 ~ bit4 always be marked as 0 by MPU. The actual
-                              start address is 0-modulo-32 byte address.  */
-    uint32_t endAddress; /*!< Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU. The actual end
-                            address is 31-modulo-32 byte address. */
-    mpu_low_masters_access_rights_t accessRights1[4];  /*!< Low masters access permission.  */
-    mpu_high_masters_access_rights_t accessRights2[4]; /*!< High masters access permission. */
-#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
-    uint8_t processIdentifier; /*!< Process identifier used when "processIdentifierEnable" set with true. */
-    uint8_t
-        processIdMask; /*!< Process identifier mask. The setting bit will ignore the same bit in process identifier. */
-#endif                 /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
-} mpu_region_config_t;
-
-/*!
- * @brief The configuration structure for the MPU initialization.
- *
- * This structure is used when calling the MPU_Init function.
- */
-typedef struct _mpu_config
-{
-    mpu_region_config_t regionConfig; /*!< region access permission. */
-    struct _mpu_config *next;         /*!< pointer to the next structure. */
-} mpu_config_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif /* _cplusplus */
-
-/*!
- * @name Initialization and deinitialization
- * @{
- */
-
-/*!
- * @brief Initializes the MPU with the user configuration structure.
- *
- * This function configures the MPU module with the user-defined configuration.
- *
- * @param base     MPU peripheral base address.
- * @param config   The pointer to the configuration structure.
- */
-void MPU_Init(MPU_Type *base, const mpu_config_t *config);
-
-/*!
- * @brief Deinitializes the MPU regions.
- *
- * @param base     MPU peripheral base address.
- */
-void MPU_Deinit(MPU_Type *base);
-
-/* @}*/
-
-/*!
- * @name Basic Control Operations
- * @{
- */
-
-/*!
- * @brief Enables/disables the MPU globally.
- *
- * Call this API to enable or disable the MPU module.
- *
- * @param base     MPU peripheral base address.
- * @param enable   True enable MPU, false disable MPU.
- */
-static inline void MPU_Enable(MPU_Type *base, bool enable)
-{
-    if (enable)
-    {
-        /* Enable the MPU globally. */
-        base->CESR |= MPU_CESR_VLD_MASK;
-    }
-    else
-    { /* Disable the MPU globally. */
-        base->CESR &= ~MPU_CESR_VLD_MASK;
-    }
-}
-
-/*!
- * @brief Enables/disables the MPU for a special region.
- *
- * When MPU is enabled, call this API to disable an unused region
- * of an enabled MPU. Call this API to minimize the power dissipation.
- *
- * @param base     MPU peripheral base address.
- * @param number   MPU region number.
- * @param enable   True enable the special region MPU, false disable the special region MPU.
- */
-static inline void MPU_RegionEnable(MPU_Type *base, mpu_region_num_t number, bool enable)
-{
-    if (enable)
-    {
-        /* Enable the #number region MPU. */
-        base->WORD[number][3] |= MPU_WORD_VLD_MASK;
-    }
-    else
-    { /* Disable the #number region MPU. */
-        base->WORD[number][3] &= ~MPU_WORD_VLD_MASK;
-    }
-}
-
-/*!
- * @brief Gets the MPU basic hardware information.
- *
- * @param base           MPU peripheral base address.
- * @param hardwareInform The pointer to the MPU hardware information structure. See "mpu_hardware_info_t".
- */
-void MPU_GetHardwareInfo(MPU_Type *base, mpu_hardware_info_t *hardwareInform);
-
-/*!
- * @brief Sets the MPU region.
- *
- * Note: Due to the MPU protection, the kMPU_RegionNum00 does not allow writes from the
- * core to affect the start and end address nor the permissions associated with
- * the debugger. It can only write the permission fields associated
- * with the other masters.
- *
- * @param base          MPU peripheral base address.
- * @param regionConfig  The pointer to the MPU user configuration structure. See "mpu_region_config_t".
- */
-void MPU_SetRegionConfig(MPU_Type *base, const mpu_region_config_t *regionConfig);
-
-/*!
- * @brief Sets the region start and end address.
- *
- * Memory region start address. Note: bit0 ~ bit4 is always marked as 0 by MPU.
- * The actual start address by MPU is 0-modulo-32 byte address.
- * Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU.
- * The actual end address used by MPU is 31-modulo-32 byte address.
- * Note: Due to the MPU protection, the startAddr and endAddr can't be
- * changed by the core when regionNum is "kMPU_RegionNum00".
- *
- * @param base          MPU peripheral base address.
- * @param regionNum     MPU region number.
- * @param startAddr     Region start address.
- * @param endAddr       Region end address.
- */
-void MPU_SetRegionAddr(MPU_Type *base, mpu_region_num_t regionNum, uint32_t startAddr, uint32_t endAddr);
-
-/*!
- * @brief Sets the MPU region access rights for low master port 0 ~ port 3.
- * This can be used to change the region access rights for any master port for any region.
- *
- * @param base          MPU peripheral base address.
- * @param regionNum     MPU region number.
- * @param masterNum     MPU master number. Should range from kMPU_Master0 ~ kMPU_Master3.
- * @param accessRights  The pointer to the MPU access rights configuration. See "mpu_low_masters_access_rights_t".
- */
-void MPU_SetRegionLowMasterAccessRights(MPU_Type *base,
-                                        mpu_region_num_t regionNum,
-                                        mpu_master_t masterNum,
-                                        const mpu_low_masters_access_rights_t *accessRights);
-
-/*!
- * @brief Sets the MPU region access rights for high master port 4 ~ port 7.
- * This can be used to change the region access rights for any master port for any region.
- *
- * @param base          MPU peripheral base address.
- * @param regionNum     MPU region number.
- * @param masterNum     MPU master number. Should range from kMPU_Master4 ~ kMPU_Master7.
- * @param accessRights  The pointer to the MPU access rights configuration. See "mpu_high_masters_access_rights_t".
- */
-void MPU_SetRegionHighMasterAccessRights(MPU_Type *base,
-                                         mpu_region_num_t regionNum,
-                                         mpu_master_t masterNum,
-                                         const mpu_high_masters_access_rights_t *accessRights);
-
-/*!
- * @brief Gets the numbers of slave ports where errors occur.
- *
- * @param base       MPU peripheral base address.
- * @param slaveNum   MPU slave port number.
- * @return The slave ports error status.
- *         true  - error happens in this slave port.
- *         false - error didn't happen in this slave port.
- */
-bool MPU_GetSlavePortErrorStatus(MPU_Type *base, mpu_slave_t slaveNum);
-
-/*!
- * @brief Gets the MPU detailed error access information.
- *
- * @param base       MPU peripheral base address.
- * @param slaveNum   MPU slave port number.
- * @param errInform  The pointer to the MPU access error information. See "mpu_access_err_info_t".
- */
-void MPU_GetDetailErrorAccessInfo(MPU_Type *base, mpu_slave_t slaveNum, mpu_access_err_info_t *errInform);
-
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* _FSL_MPU_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pdb.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pdb.c
index b5c9b88ec6c..1fc4a9a486a 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pdb.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pdb.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -45,8 +45,10 @@ static uint32_t PDB_GetInstance(PDB_Type *base);
  ******************************************************************************/
 /*! @brief Pointers to PDB bases for each instance. */
 static PDB_Type *const s_pdbBases[] = PDB_BASE_PTRS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to PDB clocks for each instance. */
-const clock_ip_name_t s_pdbClocks[] = PDB_CLOCKS;
+static const clock_ip_name_t s_pdbClocks[] = PDB_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Codes
@@ -56,7 +58,7 @@ static uint32_t PDB_GetInstance(PDB_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_PDB_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_pdbBases); instance++)
     {
         if (s_pdbBases[instance] == base)
         {
@@ -64,7 +66,7 @@ static uint32_t PDB_GetInstance(PDB_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_PDB_COUNT);
+    assert(instance < ARRAY_SIZE(s_pdbBases));
 
     return instance;
 }
@@ -75,8 +77,10 @@ void PDB_Init(PDB_Type *base, const pdb_config_t *config)
 
     uint32_t tmp32;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the clock. */
     CLOCK_EnableClock(s_pdbClocks[PDB_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Configure. */
     /* PDBx_SC. */
@@ -98,8 +102,10 @@ void PDB_Deinit(PDB_Type *base)
 {
     PDB_Enable(base, false); /* Disable the PDB module. */
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable the clock. */
     CLOCK_DisableClock(s_pdbClocks[PDB_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void PDB_GetDefaultConfig(pdb_config_t *config)
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pdb.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pdb.h
index 1f05b61b26b..3dec9463462 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pdb.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pdb.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -38,7 +38,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -67,32 +66,32 @@ enum _pdb_status_flags
 enum _pdb_adc_pretrigger_flags
 {
     /* PDB PreTrigger channel match flags. */
-    kPDB_ADCPreTriggerChannel0Flag = PDB_S_CF(1U << 0), /*!< Pre-Trigger 0 flag. */
-    kPDB_ADCPreTriggerChannel1Flag = PDB_S_CF(1U << 1), /*!< Pre-Trigger 1 flag. */
-#if (PDB_DLY_COUNT > 2)
-    kPDB_ADCPreTriggerChannel2Flag = PDB_S_CF(1U << 2), /*!< Pre-Trigger 2 flag. */
-    kPDB_ADCPreTriggerChannel3Flag = PDB_S_CF(1U << 3), /*!< Pre-Trigger 3 flag. */
-#endif                                                  /* PDB_DLY_COUNT > 2 */
-#if (PDB_DLY_COUNT > 4)
-    kPDB_ADCPreTriggerChannel4Flag = PDB_S_CF(1U << 4), /*!< Pre-Trigger 4 flag. */
-    kPDB_ADCPreTriggerChannel5Flag = PDB_S_CF(1U << 5), /*!< Pre-Trigger 5 flag. */
-    kPDB_ADCPreTriggerChannel6Flag = PDB_S_CF(1U << 6), /*!< Pre-Trigger 6 flag. */
-    kPDB_ADCPreTriggerChannel7Flag = PDB_S_CF(1U << 7), /*!< Pre-Trigger 7 flag. */
-#endif                                                  /* PDB_DLY_COUNT > 4 */
+    kPDB_ADCPreTriggerChannel0Flag = PDB_S_CF(1U << 0), /*!< Pre-trigger 0 flag. */
+    kPDB_ADCPreTriggerChannel1Flag = PDB_S_CF(1U << 1), /*!< Pre-trigger 1 flag. */
+#if (PDB_DLY_COUNT2 > 2)
+    kPDB_ADCPreTriggerChannel2Flag = PDB_S_CF(1U << 2), /*!< Pre-trigger 2 flag. */
+    kPDB_ADCPreTriggerChannel3Flag = PDB_S_CF(1U << 3), /*!< Pre-trigger 3 flag. */
+#endif                                                  /* PDB_DLY_COUNT2 > 2 */
+#if (PDB_DLY_COUNT2 > 4)
+    kPDB_ADCPreTriggerChannel4Flag = PDB_S_CF(1U << 4), /*!< Pre-trigger 4 flag. */
+    kPDB_ADCPreTriggerChannel5Flag = PDB_S_CF(1U << 5), /*!< Pre-trigger 5 flag. */
+    kPDB_ADCPreTriggerChannel6Flag = PDB_S_CF(1U << 6), /*!< Pre-trigger 6 flag. */
+    kPDB_ADCPreTriggerChannel7Flag = PDB_S_CF(1U << 7), /*!< Pre-trigger 7 flag. */
+#endif                                                  /* PDB_DLY_COUNT2 > 4 */
 
     /* PDB PreTrigger channel error flags. */
-    kPDB_ADCPreTriggerChannel0ErrorFlag = PDB_S_ERR(1U << 0), /*!< Pre-Trigger 0 Error. */
-    kPDB_ADCPreTriggerChannel1ErrorFlag = PDB_S_ERR(1U << 1), /*!< Pre-Trigger 1 Error. */
-#if (PDB_DLY_COUNT > 2)
-    kPDB_ADCPreTriggerChannel2ErrorFlag = PDB_S_ERR(1U << 2), /*!< Pre-Trigger 2 Error. */
-    kPDB_ADCPreTriggerChannel3ErrorFlag = PDB_S_ERR(1U << 3), /*!< Pre-Trigger 3 Error. */
-#endif                                                        /* PDB_DLY_COUNT > 2 */
-#if (PDB_DLY_COUNT > 4)
-    kPDB_ADCPreTriggerChannel4ErrorFlag = PDB_S_ERR(1U << 4), /*!< Pre-Trigger 4 Error. */
-    kPDB_ADCPreTriggerChannel5ErrorFlag = PDB_S_ERR(1U << 5), /*!< Pre-Trigger 5 Error. */
-    kPDB_ADCPreTriggerChannel6ErrorFlag = PDB_S_ERR(1U << 6), /*!< Pre-Trigger 6 Error. */
-    kPDB_ADCPreTriggerChannel7ErrorFlag = PDB_S_ERR(1U << 7), /*!< Pre-Trigger 7 Error. */
-#endif                                                        /* PDB_DLY_COUNT > 4 */
+    kPDB_ADCPreTriggerChannel0ErrorFlag = PDB_S_ERR(1U << 0), /*!< Pre-trigger 0 Error. */
+    kPDB_ADCPreTriggerChannel1ErrorFlag = PDB_S_ERR(1U << 1), /*!< Pre-trigger 1 Error. */
+#if (PDB_DLY_COUNT2 > 2)
+    kPDB_ADCPreTriggerChannel2ErrorFlag = PDB_S_ERR(1U << 2), /*!< Pre-trigger 2 Error. */
+    kPDB_ADCPreTriggerChannel3ErrorFlag = PDB_S_ERR(1U << 3), /*!< Pre-trigger 3 Error. */
+#endif                                                        /* PDB_DLY_COUNT2 > 2 */
+#if (PDB_DLY_COUNT2 > 4)
+    kPDB_ADCPreTriggerChannel4ErrorFlag = PDB_S_ERR(1U << 4), /*!< Pre-trigger 4 Error. */
+    kPDB_ADCPreTriggerChannel5ErrorFlag = PDB_S_ERR(1U << 5), /*!< Pre-trigger 5 Error. */
+    kPDB_ADCPreTriggerChannel6ErrorFlag = PDB_S_ERR(1U << 6), /*!< Pre-trigger 6 Error. */
+    kPDB_ADCPreTriggerChannel7ErrorFlag = PDB_S_ERR(1U << 7), /*!< Pre-trigger 7 Error. */
+#endif                                                        /* PDB_DLY_COUNT2 > 4 */
 };
 
 /*!
@@ -108,7 +107,7 @@ enum _pdb_interrupt_enable
  * @brief PDB load value mode.
  *
  * Selects the mode to load the internal values after doing the load operation (write 1 to PDBx_SC[LDOK]).
- * These values are for:
+ * These values are for the following operations.
  *  - PDB counter (PDBx_MOD, PDBx_IDLY)
  *  - ADC trigger (PDBx_CHnDLYm)
  *  - DAC trigger (PDBx_DACINTx)
@@ -158,7 +157,7 @@ typedef enum _pdb_divider_multiplication_factor
  * @brief Trigger input source
  *
  * Selects the trigger input source for the PDB. The trigger input source can be internal or external (EXTRG pin), or
- * the software trigger. Refer to chip configuration details for the actual PDB input trigger connections.
+ * the software trigger. See chip configuration details for the actual PDB input trigger connections.
  */
 typedef enum _pdb_trigger_input_source
 {
@@ -177,7 +176,7 @@ typedef enum _pdb_trigger_input_source
     kPDB_TriggerInput12 = 12U,  /*!< Trigger-In 12. */
     kPDB_TriggerInput13 = 13U,  /*!< Trigger-In 13. */
     kPDB_TriggerInput14 = 14U,  /*!< Trigger-In 14. */
-    kPDB_TriggerSoftware = 15U, /*!< Trigger-In 15. */
+    kPDB_TriggerSoftware = 15U, /*!< Trigger-In 15, software trigger. */
 } pdb_trigger_input_source_t;
 
 /*!
@@ -193,15 +192,15 @@ typedef struct _pdb_config
 } pdb_config_t;
 
 /*!
- * @brief PDB ADC Pre-Trigger configuration.
+ * @brief PDB ADC Pre-trigger configuration.
  */
 typedef struct _pdb_adc_pretrigger_config
 {
-    uint32_t enablePreTriggerMask;          /*!< PDB Channel Pre-Trigger Enable. */
-    uint32_t enableOutputMask;              /*!< PDB Channel Pre-Trigger Output Select.
+    uint32_t enablePreTriggerMask;          /*!< PDB Channel Pre-trigger Enable. */
+    uint32_t enableOutputMask;              /*!< PDB Channel Pre-trigger Output Select.
                                                  PDB channel's corresponding pre-trigger asserts when the counter
                                                  reaches the channel delay register. */
-    uint32_t enableBackToBackOperationMask; /*!< PDB Channel Pre-Trigger Back-to-Back Operation Enable.
+    uint32_t enableBackToBackOperationMask; /*!< PDB Channel pre-trigger Back-to-Back Operation Enable.
                                                  Back-to-back operation enables the ADC conversions complete to trigger
                                                  the next PDB channel pre-trigger and trigger output, so that the ADC
                                                  conversions can be triggered on next set of configuration and results
@@ -230,29 +229,29 @@ extern "C" {
  */
 
 /*!
- * @brief Initializes  the PDB module.
+ * @brief Initializes the PDB module.
  *
- * This function is to make the initialization for PDB module. The operations includes are:
+ * This function initializes the PDB module. The operations included are as follows.
  *  - Enable the clock for PDB instance.
  *  - Configure the PDB module.
  *  - Enable the PDB module.
  *
  * @param base PDB peripheral base address.
- * @param config Pointer to configuration structure. See "pdb_config_t".
+ * @param config Pointer to the configuration structure. See "pdb_config_t".
  */
 void PDB_Init(PDB_Type *base, const pdb_config_t *config);
 
 /*!
- * @brief De-initializes  the PDB module.
+ * @brief De-initializes the PDB module.
  *
  * @param base PDB peripheral base address.
  */
 void PDB_Deinit(PDB_Type *base);
 
 /*!
- * @brief Initializes the PDB user configure structure.
+ * @brief Initializes the PDB user configuration structure.
  *
- * This function initializes the user configure structure to default value. the default value are:
+ * This function initializes the user configuration structure to a default value. The default values are as follows.
  * @code
  *   config->loadValueMode = kPDB_LoadValueImmediately;
  *   config->prescalerDivider = kPDB_PrescalerDivider1;
@@ -302,7 +301,7 @@ static inline void PDB_DoSoftwareTrigger(PDB_Type *base)
 /*!
  * @brief Loads the counter values.
  *
- * This function is to load the counter values from their internal buffer.
+ * This function loads the counter values from the internal buffer.
  * See "pdb_load_value_mode_t" about PDB's load mode.
  *
  * @param base PDB peripheral base address.
@@ -382,7 +381,7 @@ static inline void PDB_ClearStatusFlags(PDB_Type *base, uint32_t mask)
 }
 
 /*!
- * @brief  Specifies the period of the counter.
+ * @brief  Specifies the counter period.
  *
  * @param  base  PDB peripheral base address.
  * @param  value Setting value for the modulus. 16-bit is available.
@@ -405,7 +404,7 @@ static inline uint32_t PDB_GetCounterValue(PDB_Type *base)
 }
 
 /*!
- * @brief Sets the value for PDB counter delay event.
+ * @brief Sets the value for the PDB counter delay event.
  *
  * @param base  PDB peripheral base address.
  * @param value Setting value for PDB counter delay event. 16-bit is available.
@@ -417,16 +416,16 @@ static inline void PDB_SetCounterDelayValue(PDB_Type *base, uint32_t value)
 /* @} */
 
 /*!
- * @name ADC Pre-Trigger
+ * @name ADC Pre-trigger
  * @{
  */
 
 /*!
- * @brief Configures the ADC PreTrigger in PDB module.
+ * @brief Configures the ADC pre-trigger in the PDB module.
  *
  * @param base    PDB peripheral base address.
  * @param channel Channel index for ADC instance.
- * @param config  Pointer to configuration structure. See "pdb_adc_pretrigger_config_t".
+ * @param config  Pointer to the configuration structure. See "pdb_adc_pretrigger_config_t".
  */
 static inline void PDB_SetADCPreTriggerConfig(PDB_Type *base, uint32_t channel, pdb_adc_pretrigger_config_t *config)
 {
@@ -434,30 +433,31 @@ static inline void PDB_SetADCPreTriggerConfig(PDB_Type *base, uint32_t channel,
     assert(NULL != config);
 
     base->CH[channel].C1 = PDB_C1_BB(config->enableBackToBackOperationMask) | PDB_C1_TOS(config->enableOutputMask) |
-                           PDB_C1_EN(config->enableOutputMask);
+                           PDB_C1_EN(config->enablePreTriggerMask);
 }
 
 /*!
- * @brief Sets the value for ADC Pre-Trigger delay event.
+ * @brief Sets the value for the ADC pre-trigger delay event.
  *
- * This function is to set the value for ADC Pre-Trigger delay event. IT Specifies the delay value for the channel's
- * corresponding pre-trigger. The pre-trigger asserts when the PDB counter is equal to the setting value here.
+ * This function sets the value for ADC pre-trigger delay event. It specifies the delay value for the channel's
+ * corresponding pre-trigger. The pre-trigger asserts when the PDB counter is equal to the set value.
  *
  * @param base       PDB peripheral base address.
  * @param channel    Channel index for ADC instance.
  * @param preChannel Channel group index for ADC instance.
- * @param value      Setting value for ADC Pre-Trigger delay event. 16-bit is available.
+ * @param value      Setting value for ADC pre-trigger delay event. 16-bit is available.
  */
 static inline void PDB_SetADCPreTriggerDelayValue(PDB_Type *base, uint32_t channel, uint32_t preChannel, uint32_t value)
 {
     assert(channel < PDB_C1_COUNT);
-    assert(preChannel < PDB_DLY_COUNT);
+    assert(preChannel < PDB_DLY_COUNT2);
+    /* xx_COUNT2 is actually the count for pre-triggers in header file. xx_COUNT is used for the count of channels. */
 
     base->CH[channel].DLY[preChannel] = PDB_DLY_DLY(value);
 }
 
 /*!
- * @brief  Gets the ADC Pre-Trigger's status flags.
+ * @brief  Gets the ADC pre-trigger's status flags.
  *
  * @param  base    PDB peripheral base address.
  * @param  channel Channel index for ADC instance.
@@ -472,7 +472,7 @@ static inline uint32_t PDB_GetADCPreTriggerStatusFlags(PDB_Type *base, uint32_t
 }
 
 /*!
- * @brief Clears the ADC Pre-Trigger's status flags.
+ * @brief Clears the ADC pre-trigger status flags.
  *
  * @param base    PDB peripheral base address.
  * @param channel Channel index for ADC instance.
@@ -494,19 +494,19 @@ static inline void PDB_ClearADCPreTriggerStatusFlags(PDB_Type *base, uint32_t ch
  */
 
 /*!
- * @brief Configures the DAC trigger in PDB module.
+ * @brief Configures the DAC trigger in the PDB module.
  *
  * @param base    PDB peripheral base address.
  * @param channel Channel index for DAC instance.
- * @param config  Pointer to configuration structure. See "pdb_dac_trigger_config_t".
+ * @param config  Pointer to the configuration structure. See "pdb_dac_trigger_config_t".
  */
 void PDB_SetDACTriggerConfig(PDB_Type *base, uint32_t channel, pdb_dac_trigger_config_t *config);
 
 /*!
  * @brief Sets the value for the DAC interval event.
  *
- * This fucntion is to set the value for DAC interval event. DAC interval trigger would trigger the DAC module to update
- * buffer when the DAC interval counter is equal to the setting value here.
+ * This fucntion sets the value for DAC interval event. DAC interval trigger triggers the DAC module to update
+ * the buffer when the DAC interval counter is equal to the set value.
  *
  * @param base    PDB peripheral base address.
  * @param channel Channel index for DAC instance.
@@ -532,7 +532,7 @@ static inline void PDB_SetDACTriggerIntervalValue(PDB_Type *base, uint32_t chann
  *
  * @param base        PDB peripheral base address.
  * @param channelMask Channel mask value for multiple pulse out trigger channel.
- * @param enable Enable the feature or not.
+ * @param enable Whether the feature is enabled or not.
  */
 static inline void PDB_EnablePulseOutTrigger(PDB_Type *base, uint32_t channelMask, bool enable)
 {
@@ -547,11 +547,11 @@ static inline void PDB_EnablePulseOutTrigger(PDB_Type *base, uint32_t channelMas
 }
 
 /*!
- * @brief Sets event values for pulse out trigger.
+ * @brief Sets event values for the pulse out trigger.
  *
- * This function is used to set event values for pulse output trigger.
- * These pulse output trigger delay values specify the delay for the PDB Pulse-Out. Pulse-Out goes high when the PDB
- * counter is equal to the pulse output high value (value1). Pulse-Out goes low when the PDB counter is equal to the
+ * This function is used to set event values for the pulse output trigger.
+ * These pulse output trigger delay values specify the delay for the PDB Pulse-out. Pulse-out goes high when the PDB
+ * counter is equal to the pulse output high value (value1). Pulse-out goes low when the PDB counter is equal to the
  * pulse output low value (value2).
  *
  * @param base    PDB peripheral base address.
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pit.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pit.c
index 1f2fdfe8b45..e5c3c4e013d 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pit.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pit.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -48,8 +48,10 @@ static uint32_t PIT_GetInstance(PIT_Type *base);
 /*! @brief Pointers to PIT bases for each instance. */
 static PIT_Type *const s_pitBases[] = PIT_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to PIT clocks for each instance. */
 static const clock_ip_name_t s_pitClocks[] = PIT_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
@@ -59,7 +61,7 @@ static uint32_t PIT_GetInstance(PIT_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_PIT_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_pitBases); instance++)
     {
         if (s_pitBases[instance] == base)
         {
@@ -67,7 +69,7 @@ static uint32_t PIT_GetInstance(PIT_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_PIT_COUNT);
+    assert(instance < ARRAY_SIZE(s_pitBases));
 
     return instance;
 }
@@ -76,8 +78,10 @@ void PIT_Init(PIT_Type *base, const pit_config_t *config)
 {
     assert(config);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Ungate the PIT clock*/
     CLOCK_EnableClock(s_pitClocks[PIT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Enable PIT timers */
     base->MCR &= ~PIT_MCR_MDIS_MASK;
@@ -98,8 +102,10 @@ void PIT_Deinit(PIT_Type *base)
     /* Disable PIT timers */
     base->MCR |= PIT_MCR_MDIS_MASK;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Gate the PIT clock*/
     CLOCK_DisableClock(s_pitClocks[PIT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 #if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pit.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pit.h
index 61606e7e8bd..99c30e1e4bc 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pit.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pit.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -33,11 +33,10 @@
 #include "fsl_common.h"
 
 /*!
- * @addtogroup pit_driver
+ * @addtogroup pit
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -73,13 +72,13 @@ typedef enum _pit_status_flags
 } pit_status_flags_t;
 
 /*!
- * @brief PIT config structure
+ * @brief PIT configuration structure
  *
  * This structure holds the configuration settings for the PIT peripheral. To initialize this
  * structure to reasonable defaults, call the PIT_GetDefaultConfig() function and pass a
  * pointer to your config structure instance.
  *
- * The config struct can be made const so it resides in flash
+ * The configuration structure can be made constant so it resides in flash.
  */
 typedef struct _pit_config
 {
@@ -100,30 +99,30 @@ extern "C" {
  */
 
 /*!
- * @brief Ungates the PIT clock, enables the PIT module and configures the peripheral for basic operation.
+ * @brief Ungates the PIT clock, enables the PIT module, and configures the peripheral for basic operations.
  *
  * @note This API should be called at the beginning of the application using the PIT driver.
  *
  * @param base   PIT peripheral base address
- * @param config Pointer to user's PIT config structure
+ * @param config Pointer to the user's PIT config structure
  */
 void PIT_Init(PIT_Type *base, const pit_config_t *config);
 
 /*!
- * @brief Gate the PIT clock and disable the PIT module
+ * @brief Gates the PIT clock and disables the PIT module.
  *
  * @param base PIT peripheral base address
  */
 void PIT_Deinit(PIT_Type *base);
 
 /*!
- * @brief Fill in the PIT config struct with the default settings
+ * @brief Fills in the PIT configuration structure with the default settings.
  *
- * The default values are:
+ * The default values are as follows.
  * @code
  *     config->enableRunInDebug = false;
  * @endcode
- * @param config Pointer to user's PIT config structure.
+ * @param config Pointer to the onfiguration structure.
  */
 static inline void PIT_GetDefaultConfig(pit_config_t *config)
 {
@@ -140,9 +139,9 @@ static inline void PIT_GetDefaultConfig(pit_config_t *config)
  *
  * When a timer has a chain mode enabled, it only counts after the previous
  * timer has expired. If the timer n-1 has counted down to 0, counter n
- * decrements the value by one. Each timer is 32-bits, this allows the developers
+ * decrements the value by one. Each timer is 32-bits, which allows the developers
  * to chain timers together and form a longer timer (64-bits and larger). The first timer
- * (timer 0) cannot be chained to any other timer.
+ * (timer 0) can't be chained to any other timer.
  *
  * @param base    PIT peripheral base address
  * @param channel Timer channel number which is chained with the previous timer
@@ -219,7 +218,7 @@ static inline uint32_t PIT_GetEnabledInterrupts(PIT_Type *base, pit_chnl_t chann
  */
 
 /*!
- * @brief Gets the PIT status flags
+ * @brief Gets the PIT status flags.
  *
  * @param base    PIT peripheral base address
  * @param channel Timer channel number
@@ -256,11 +255,11 @@ static inline void PIT_ClearStatusFlags(PIT_Type *base, pit_chnl_t channel, uint
  * @brief Sets the timer period in units of count.
  *
  * Timers begin counting from the value set by this function until it reaches 0,
- * then it will generate an interrupt and load this regiter value again.
- * Writing a new value to this register will not restart the timer; instead the value
- * will be loaded after the timer expires.
+ * then it generates an interrupt and load this register value again.
+ * Writing a new value to this register does not restart the timer. Instead, the value
+ * is loaded after the timer expires.
  *
- * @note User can call the utility macros provided in fsl_common.h to convert to ticks
+ * @note Users can call the utility macros provided in fsl_common.h to convert to ticks.
  *
  * @param base    PIT peripheral base address
  * @param channel Timer channel number
@@ -277,7 +276,7 @@ static inline void PIT_SetTimerPeriod(PIT_Type *base, pit_chnl_t channel, uint32
  * This function returns the real-time timer counting value, in a range from 0 to a
  * timer period.
  *
- * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
+ * @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec.
  *
  * @param base    PIT peripheral base address
  * @param channel Timer channel number
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pmc.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pmc.c
index 82d7b7ace13..bcdd5cb8231 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pmc.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pmc.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pmc.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pmc.h
index c60c19c01e9..99fc149fc22 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pmc.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_pmc.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -35,7 +35,6 @@
 /*! @addtogroup pmc */
 /*! @{ */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -49,36 +48,36 @@
 
 #if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV)
 /*!
- * @brief Low-Voltage Detect Voltage Select
+ * @brief Low-voltage Detect Voltage Select
  */
 typedef enum _pmc_low_volt_detect_volt_select
 {
-    kPMC_LowVoltDetectLowTrip = 0U, /*!< Low trip point selected (VLVD = VLVDL )*/
-    kPMC_LowVoltDetectHighTrip = 1U /*!< High trip point selected (VLVD = VLVDH )*/
+    kPMC_LowVoltDetectLowTrip = 0U, /*!< Low-trip point selected (VLVD = VLVDL )*/
+    kPMC_LowVoltDetectHighTrip = 1U /*!< High-trip point selected (VLVD = VLVDH )*/
 } pmc_low_volt_detect_volt_select_t;
 #endif
 
 #if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV)
 /*!
- * @brief Low-Voltage Warning Voltage Select
+ * @brief Low-voltage Warning Voltage Select
  */
 typedef enum _pmc_low_volt_warning_volt_select
 {
-    kPMC_LowVoltWarningLowTrip = 0U,  /*!< Low trip point selected (VLVW = VLVW1)*/
+    kPMC_LowVoltWarningLowTrip = 0U,  /*!< Low-trip point selected (VLVW = VLVW1)*/
     kPMC_LowVoltWarningMid1Trip = 1U, /*!< Mid 1 trip point selected (VLVW = VLVW2)*/
     kPMC_LowVoltWarningMid2Trip = 2U, /*!< Mid 2 trip point selected (VLVW = VLVW3)*/
-    kPMC_LowVoltWarningHighTrip = 3U  /*!< High trip point selected (VLVW = VLVW4)*/
+    kPMC_LowVoltWarningHighTrip = 3U  /*!< High-trip point selected (VLVW = VLVW4)*/
 } pmc_low_volt_warning_volt_select_t;
 #endif
 
 #if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1)
 /*!
- * @brief High-Voltage Detect Voltage Select
+ * @brief High-voltage Detect Voltage Select
  */
 typedef enum _pmc_high_volt_detect_volt_select
 {
-    kPMC_HighVoltDetectLowTrip = 0U, /*!< Low trip point selected (VHVD = VHVDL )*/
-    kPMC_HighVoltDetectHighTrip = 1U /*!< High trip point selected (VHVD = VHVDH )*/
+    kPMC_HighVoltDetectLowTrip = 0U, /*!< Low-trip point selected (VHVD = VHVDL )*/
+    kPMC_HighVoltDetectHighTrip = 1U /*!< High-trip point selected (VHVD = VHVDH )*/
 } pmc_high_volt_detect_volt_select_t;
 #endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */
 
@@ -88,8 +87,8 @@ typedef enum _pmc_high_volt_detect_volt_select
  */
 typedef enum _pmc_bandgap_buffer_drive_select
 {
-    kPMC_BandgapBufferDriveLow = 0U, /*!< Low drive.  */
-    kPMC_BandgapBufferDriveHigh = 1U /*!< High drive. */
+    kPMC_BandgapBufferDriveLow = 0U, /*!< Low-drive.  */
+    kPMC_BandgapBufferDriveHigh = 1U /*!< High-drive. */
 } pmc_bandgap_buffer_drive_select_t;
 #endif /* FSL_FEATURE_PMC_HAS_BGBDS */
 
@@ -126,37 +125,37 @@ typedef struct _pmc_param
 #endif /* FSL_FEATURE_PMC_HAS_PARAM */
 
 /*!
- * @brief Low-Voltage Detect Configuration Structure
+ * @brief Low-voltage Detect Configuration Structure
  */
 typedef struct _pmc_low_volt_detect_config
 {
-    bool enableInt;   /*!< Enable interrupt when low voltage detect*/
-    bool enableReset; /*!< Enable system reset when low voltage detect*/
+    bool enableInt;   /*!< Enable interrupt when Low-voltage detect*/
+    bool enableReset; /*!< Enable system reset when Low-voltage detect*/
 #if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV)
-    pmc_low_volt_detect_volt_select_t voltSelect; /*!< Low voltage detect trip point voltage selection*/
+    pmc_low_volt_detect_volt_select_t voltSelect; /*!< Low-voltage detect trip point voltage selection*/
 #endif
 } pmc_low_volt_detect_config_t;
 
 /*!
- * @brief Low-Voltage Warning Configuration Structure
+ * @brief Low-voltage Warning Configuration Structure
  */
 typedef struct _pmc_low_volt_warning_config
 {
-    bool enableInt; /*!< Enable interrupt when low voltage warning*/
+    bool enableInt; /*!< Enable interrupt when low-voltage warning*/
 #if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV)
-    pmc_low_volt_warning_volt_select_t voltSelect; /*!< Low voltage warning trip point voltage selection*/
+    pmc_low_volt_warning_volt_select_t voltSelect; /*!< Low-voltage warning trip point voltage selection*/
 #endif
 } pmc_low_volt_warning_config_t;
 
 #if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1)
 /*!
- * @brief High-Voltage Detect Configuration Structure
+ * @brief High-voltage Detect Configuration Structure
  */
 typedef struct _pmc_high_volt_detect_config
 {
-    bool enableInt;                                /*!< Enable interrupt when high voltage detect*/
-    bool enableReset;                              /*!< Enable system reset when high voltage detect*/
-    pmc_high_volt_detect_volt_select_t voltSelect; /*!< High voltage detect trip point voltage selection*/
+    bool enableInt;                                /*!< Enable interrupt when high-voltage detect*/
+    bool enableReset;                              /*!< Enable system reset when high-voltage detect*/
+    pmc_high_volt_detect_volt_select_t voltSelect; /*!< High-voltage detect trip point voltage selection*/
 } pmc_high_volt_detect_config_t;
 #endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */
 
@@ -172,7 +171,7 @@ typedef struct _pmc_bandgap_buffer_config
     bool enable; /*!< Enable bandgap buffer.                   */
 #endif
 #if (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN)
-    bool enableInLowPowerMode; /*!< Enable bandgap buffer in low power mode. */
+    bool enableInLowPowerMode; /*!< Enable bandgap buffer in low-power mode. */
 #endif                         /* FSL_FEATURE_PMC_HAS_BGEN */
 #if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)
     pmc_bandgap_buffer_drive_select_t drive; /*!< Bandgap buffer drive select.             */
@@ -196,7 +195,7 @@ extern "C" {
  * @brief Gets the PMC version ID.
  *
  * This function gets the PMC version ID, including major version number,
- * minor version number and feature specification number.
+ * minor version number, and a feature specification number.
  *
  * @param base PMC peripheral base address.
  * @param versionId     Pointer to version ID structure.
@@ -211,7 +210,7 @@ static inline void PMC_GetVersionId(PMC_Type *base, pmc_version_id_t *versionId)
 /*!
  * @brief Gets the PMC parameter.
  *
- * This function gets the PMC parameter, including VLPO enable and HVD enable.
+ * This function gets the PMC parameter including the VLPO enable and the HVD enable.
  *
  * @param base PMC peripheral base address.
  * @param param         Pointer to PMC param structure.
@@ -220,26 +219,25 @@ void PMC_GetParam(PMC_Type *base, pmc_param_t *param);
 #endif
 
 /*!
- * @brief Configure the low voltage detect setting.
+ * @brief Configures the low-voltage detect setting.
  *
- * This function configures the low voltage detect setting, including the trip
- * point voltage setting, enable interrupt or not, enable system reset or not.
+ * This function configures the low-voltage detect setting, including the trip
+ * point voltage setting, enables or disables the interrupt, enables or disables the system reset.
  *
  * @param base PMC peripheral base address.
- * @param config  Low-Voltage detect configuration structure.
+ * @param config  Low-voltage detect configuration structure.
  */
 void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config);
 
 /*!
- * @brief Get Low-Voltage Detect Flag status
+ * @brief Gets the Low-voltage Detect Flag status.
  *
- * This function  reads the current LVDF status. If it returns 1, a low
- * voltage event is detected.
+ * This function  reads the current LVDF status. If it returns 1, a low-voltage event is detected.
  *
  * @param base PMC peripheral base address.
- * @return Current low voltage detect flag
- *                - true: Low-Voltage detected
- *                - false: Low-Voltage not detected
+ * @return Current low-voltage detect flag
+ *                - true: Low-voltage detected
+ *                - false: Low-voltage not detected
  */
 static inline bool PMC_GetLowVoltDetectFlag(PMC_Type *base)
 {
@@ -247,9 +245,9 @@ static inline bool PMC_GetLowVoltDetectFlag(PMC_Type *base)
 }
 
 /*!
- * @brief Acknowledge to clear the Low-Voltage Detect flag
+ * @brief Acknowledges clearing the Low-voltage Detect flag.
  *
- * This function acknowledges the low voltage detection errors (write 1 to
+ * This function acknowledges the low-voltage detection errors (write 1 to
  * clear LVDF).
  *
  * @param base PMC peripheral base address.
@@ -260,18 +258,18 @@ static inline void PMC_ClearLowVoltDetectFlag(PMC_Type *base)
 }
 
 /*!
- * @brief Configure the low voltage warning setting.
+ * @brief Configures the low-voltage warning setting.
  *
- * This function configures the low voltage warning setting, including the trip
- * point voltage setting and enable interrupt or not.
+ * This function configures the low-voltage warning setting, including the trip
+ * point voltage setting and enabling or disabling the interrupt.
  *
  * @param base PMC peripheral base address.
- * @param config  Low-Voltage warning configuration structure.
+ * @param config  Low-voltage warning configuration structure.
  */
 void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config);
 
 /*!
- * @brief Get Low-Voltage Warning Flag status
+ * @brief Gets the Low-voltage Warning Flag status.
  *
  * This function polls the current LVWF status. When 1 is returned, it
  * indicates a low-voltage warning event. LVWF is set when V Supply transitions
@@ -279,8 +277,8 @@ void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_conf
  *
  * @param base PMC peripheral base address.
  * @return Current LVWF status
- *                  - true: Low-Voltage Warning Flag is set.
- *                  - false: the  Low-Voltage Warning does not happen.
+ *                  - true: Low-voltage Warning Flag is set.
+ *                  - false: the  Low-voltage Warning does not happen.
  */
 static inline bool PMC_GetLowVoltWarningFlag(PMC_Type *base)
 {
@@ -288,7 +286,7 @@ static inline bool PMC_GetLowVoltWarningFlag(PMC_Type *base)
 }
 
 /*!
- * @brief Acknowledge to Low-Voltage Warning flag
+ * @brief Acknowledges the Low-voltage Warning flag.
  *
  * This function acknowledges the low voltage warning errors (write 1 to
  * clear LVWF).
@@ -302,26 +300,26 @@ static inline void PMC_ClearLowVoltWarningFlag(PMC_Type *base)
 
 #if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1)
 /*!
- * @brief Configure the high voltage detect setting.
+ * @brief Configures the high-voltage detect setting.
  *
- * This function configures the high voltage detect setting, including the trip
- * point voltage setting, enable interrupt or not, enable system reset or not.
+ * This function configures the high-voltage detect setting, including the trip
+ * point voltage setting, enabling or disabling the interrupt, enabling or disabling the system reset.
  *
  * @param base PMC peripheral base address.
- * @param config  High-Voltage detect configuration structure.
+ * @param config  High-voltage detect configuration structure.
  */
 void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config);
 
 /*!
- * @brief Get High-Voltage Detect Flag status
+ * @brief Gets the High-voltage Detect Flag status.
  *
  * This function  reads the current HVDF status. If it returns 1, a low
  * voltage event is detected.
  *
  * @param base PMC peripheral base address.
- * @return Current high voltage detect flag
- *                - true: High-Voltage detected
- *                - false: High-Voltage not detected
+ * @return Current high-voltage detect flag
+ *                - true: High-voltage detected
+ *                - false: High-voltage not detected
  */
 static inline bool PMC_GetHighVoltDetectFlag(PMC_Type *base)
 {
@@ -329,9 +327,9 @@ static inline bool PMC_GetHighVoltDetectFlag(PMC_Type *base)
 }
 
 /*!
- * @brief Acknowledge to clear the High-Voltage Detect flag
+ * @brief Acknowledges clearing the High-voltage Detect flag.
  *
- * This function acknowledges the high voltage detection errors (write 1 to
+ * This function acknowledges the high-voltage detection errors (write 1 to
  * clear HVDF).
  *
  * @param base PMC peripheral base address.
@@ -346,10 +344,10 @@ static inline void PMC_ClearHighVoltDetectFlag(PMC_Type *base)
      (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \
      (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS))
 /*!
- * @brief Configure the PMC bandgap
+ * @brief Configures the PMC bandgap.
  *
  * This function configures the PMC bandgap, including the drive select and
- * behavior in low power mode.
+ * behavior in low-power mode.
  *
  * @param base PMC peripheral base address.
  * @param config Pointer to the configuration structure
@@ -378,7 +376,7 @@ static inline bool PMC_GetPeriphIOIsolationFlag(PMC_Type *base)
 }
 
 /*!
- * @brief Acknowledge to Peripherals and I/O pads isolation flag.
+ * @brief Acknowledges the isolation flag to Peripherals and I/O pads.
  *
  * This function  clears the ACK Isolation flag. Writing one to this setting
  * when it is set releases the I/O pads and certain peripherals to their normal
@@ -394,9 +392,9 @@ static inline void PMC_ClearPeriphIOIsolationFlag(PMC_Type *base)
 
 #if (defined(FSL_FEATURE_PMC_HAS_REGONS) && FSL_FEATURE_PMC_HAS_REGONS)
 /*!
- * @brief Gets the Regulator regulation status.
+ * @brief Gets the regulator regulation status.
  *
- * This function  returns the regulator to a run regulation status. It provides
+ * This function  returns the regulator to run a regulation status. It provides
  * the current status of the internal voltage regulator.
  *
  * @param base PMC peripheral base address.
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_port.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_port.h
index 790518ccd3c..eb8e77e6ddd 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_port.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_port.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,14 +12,14 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
@@ -33,59 +33,65 @@
 #include "fsl_common.h"
 
 /*!
- * @addtogroup port_driver
+ * @addtogroup port
  * @{
  */
 
-/*! @file */
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! Version 2.0.1. */
-#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*! Version 2.0.2. */
+#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
 /*@}*/
 
+#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
 /*! @brief Internal resistor pull feature selection */
 enum _port_pull
 {
-    kPORT_PullDisable = 0U, /*!< internal pull-up/down resistor is disabled. */
-    kPORT_PullDown = 2U,    /*!< internal pull-down resistor is enabled. */
-    kPORT_PullUp = 3U,      /*!< internal pull-up resistor is enabled. */
+    kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */
+    kPORT_PullDown = 2U,    /*!< Internal pull-down resistor is enabled. */
+    kPORT_PullUp = 3U,      /*!< Internal pull-up resistor is enabled. */
 };
+#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
 
+#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
 /*! @brief Slew rate selection */
 enum _port_slew_rate
 {
-    kPORT_FastSlewRate = 0U, /*!< fast slew rate is configured. */
-    kPORT_SlowSlewRate = 1U, /*!< slow slew rate is configured. */
+    kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */
+    kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */
 };
+#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
 
 #if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
-/*! @brief Internal resistor pull feature enable/disable */
+/*! @brief Open Drain feature enable/disable */
 enum _port_open_drain_enable
 {
-    kPORT_OpenDrainDisable = 0U, /*!< internal pull-down resistor is disabled. */
-    kPORT_OpenDrainEnable = 1U,  /*!< internal pull-up resistor is enabled. */
+    kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */
+    kPORT_OpenDrainEnable = 1U,  /*!< Open drain output is enabled. */
 };
 #endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
 
+#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
 /*! @brief Passive filter feature enable/disable */
 enum _port_passive_filter_enable
 {
-    kPORT_PassiveFilterDisable = 0U, /*!< fast slew rate is configured. */
-    kPORT_PassiveFilterEnable = 1U,  /*!< slow slew rate is configured. */
+    kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */
+    kPORT_PassiveFilterEnable = 1U,  /*!< Passive input filter is enabled. */
 };
+#endif
 
+#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
 /*! @brief Configures the drive strength. */
 enum _port_drive_strength
 {
-    kPORT_LowDriveStrength = 0U,  /*!< low drive strength is configured. */
-    kPORT_HighDriveStrength = 1U, /*!< high drive strength is configured. */
+    kPORT_LowDriveStrength = 0U,  /*!< Low-drive strength is configured. */
+    kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */
 };
+#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */
 
 #if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
 /*! @brief Unlock/lock the pin control register field[15:0] */
@@ -96,18 +102,28 @@ enum _port_lock_register
 };
 #endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
 
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
 /*! @brief Pin mux selection */
 typedef enum _port_mux
 {
-    kPORT_PinDisabledOrAnalog = 0U, /*!< corresponding pin is disabled, but is used as an analog pin. */
-    kPORT_MuxAsGpio = 1U,           /*!< corresponding pin is configured as GPIO. */
-    kPORT_MuxAlt2 = 2U,             /*!< chip-specific */
-    kPORT_MuxAlt3 = 3U,             /*!< chip-specific */
-    kPORT_MuxAlt4 = 4U,             /*!< chip-specific */
-    kPORT_MuxAlt5 = 5U,             /*!< chip-specific */
-    kPORT_MuxAlt6 = 6U,             /*!< chip-specific */
-    kPORT_MuxAlt7 = 7U,             /*!< chip-specific */
+    kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */
+    kPORT_MuxAsGpio = 1U,           /*!< Corresponding pin is configured as GPIO. */
+    kPORT_MuxAlt2 = 2U,             /*!< Chip-specific */
+    kPORT_MuxAlt3 = 3U,             /*!< Chip-specific */
+    kPORT_MuxAlt4 = 4U,             /*!< Chip-specific */
+    kPORT_MuxAlt5 = 5U,             /*!< Chip-specific */
+    kPORT_MuxAlt6 = 6U,             /*!< Chip-specific */
+    kPORT_MuxAlt7 = 7U,             /*!< Chip-specific */
+    kPORT_MuxAlt8 = 8U,             /*!< Chip-specific */
+    kPORT_MuxAlt9 = 9U,             /*!< Chip-specific */
+    kPORT_MuxAlt10 = 10U,           /*!< Chip-specific */
+    kPORT_MuxAlt11 = 11U,           /*!< Chip-specific */
+    kPORT_MuxAlt12 = 12U,           /*!< Chip-specific */
+    kPORT_MuxAlt13 = 13U,           /*!< Chip-specific */
+    kPORT_MuxAlt14 = 14U,           /*!< Chip-specific */
+    kPORT_MuxAlt15 = 15U,           /*!< Chip-specific */
 } port_mux_t;
+#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
 
 /*! @brief Configures the interrupt generation condition. */
 typedef enum _port_interrupt
@@ -129,8 +145,8 @@ typedef enum _port_interrupt
     kPORT_InterruptEitherEdge = 0xBU,  /*!< Interrupt on either edge. */
     kPORT_InterruptLogicOne = 0xCU,    /*!< Interrupt when logic one. */
 #if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER
-    kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high trigger output. */
-    kPORT_ActiveLowTriggerOutputEnable = 0xEU,  /*!< Enable active low trigger output. */
+    kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */
+    kPORT_ActiveLowTriggerOutputEnable = 0xEU,  /*!< Enable active low-trigger output. */
 #endif
 } port_interrupt_t;
 
@@ -150,44 +166,76 @@ typedef struct _port_digital_filter_config
 } port_digital_filter_config_t;
 #endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
 
-/*! @brief PORT pin config structure */
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
+/*! @brief PORT pin configuration structure */
 typedef struct _port_pin_config
 {
-    uint16_t pullSelect : 2; /*!< no-pull/pull-down/pull-up select */
-    uint16_t slewRate : 1;   /*!< fast/slow slew rate Configure */
+#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
+    uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */
+#else
+    uint16_t : 2;
+#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
+
+#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
+    uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */
+#else
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
+
+    uint16_t : 1;
+
+#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
+    uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */
+#else
     uint16_t : 1;
-    uint16_t passiveFilterEnable : 1; /*!< passive filter enable/disable */
+#endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */
+
 #if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
-    uint16_t openDrainEnable : 1; /*!< open drain enable/disable */
+    uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */
+#else
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
+
+#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
+    uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */
 #else
     uint16_t : 1;
-#endif                          /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
-    uint16_t driveStrength : 1; /*!< fast/slow drive strength configure */
+#endif
+
     uint16_t : 1;
-    uint16_t mux : 3; /*!< pin mux Configure */
+
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
+    uint16_t mux : 3; /*!< Pin mux Configure */
+#else
+    uint16_t : 3;
+#endif
+
     uint16_t : 4;
+
 #if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
-    uint16_t lockRegister : 1; /*!< lock/unlock the pcr field[15:0] */
+    uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */
 #else
     uint16_t : 1;
 #endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
 } port_pin_config_t;
+#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
 
 /*******************************************************************************
- * API
- ******************************************************************************/
+* API
+******************************************************************************/
 
 #if defined(__cplusplus)
 extern "C" {
 #endif
 
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
 /*! @name Configuration */
 /*@{*/
 
 /*!
  * @brief Sets the port PCR register.
  *
- * This is an example to define an input pin or output pin PCR configuration:
+ * This is an example to define an input pin or output pin PCR configuration.
  * @code
  * // Define a digital input pin PCR configuration
  * port_pin_config_t config = {
@@ -203,7 +251,7 @@ extern "C" {
  *
  * @param base   PORT peripheral base pointer.
  * @param pin    PORT pin number.
- * @param config PORT PCR register configure structure.
+ * @param config PORT PCR register configuration structure.
  */
 static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
 {
@@ -215,7 +263,7 @@ static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_p
 /*!
  * @brief Sets the port PCR register for multiple pins.
  *
- * This is an example to define input pins or output pins PCR configuration:
+ * This is an example to define input pins or output pins PCR configuration.
  * @code
  * // Define a digital input pin PCR configuration
  * port_pin_config_t config = {
@@ -231,8 +279,8 @@ static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_p
  * @endcode
  *
  * @param base   PORT peripheral base pointer.
- * @param mask   PORT pins' numbers macro.
- * @param config PORT PCR register configure structure.
+ * @param mask   PORT pin number macro.
+ * @param config PORT PCR register configuration structure.
  */
 static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
 {
@@ -265,15 +313,16 @@ static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, co
  *        - #kPORT_MuxAlt6            : chip-specific.
  *        - #kPORT_MuxAlt7            : chip-specific.
  * @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because
- *         the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux will
- *         be reset to zero : kPORT_PinDisabledOrAnalog).
- *         This function is recommended to use in the case you just need to reset the pin mux
+ *         the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is
+ *         reset to zero : kPORT_PinDisabledOrAnalog).
+ *        This function is recommended to use to reset the pin mux
  *
  */
 static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
 {
     base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
 }
+#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
 
 #if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
 
@@ -281,7 +330,7 @@ static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
  * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin.
  *
  * @param base  PORT peripheral base pointer.
- * @param mask  PORT pins' numbers macro.
+ * @param mask  PORT pin number macro.
  */
 static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
 {
@@ -334,8 +383,8 @@ static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digit
  *        - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
  *        - #kPORT_InterruptEitherEdge : Interrupt on either edge.
  *        - #kPORT_InterruptLogicOne   : Interrupt when logic one.
- *        - #kPORT_ActiveHighTriggerOutputEnable : Enable active high trigger output(if the trigger states exit).
- *        - #kPORT_ActiveLowTriggerOutputEnable  : Enable active low trigger output(if the trigger states exit).
+ *        - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
+ *        - #kPORT_ActiveLowTriggerOutputEnable  : Enable active low-trigger output (if the trigger states exit).
  */
 static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config)
 {
@@ -351,9 +400,9 @@ static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, por
  * If configured for a level sensitive interrupt that remains asserted, the flag
  * is set again immediately.
  *
- * @param  base PORT peripheral base pointer.
+ * @param base PORT peripheral base pointer.
  * @return Current port interrupt status flags, for example, 0x00010001 means the
- *         pin 0 and 17 have the interrupt.
+ *         pin 0 and 16 have the interrupt.
  */
 static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
 {
@@ -361,10 +410,10 @@ static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
 }
 
 /*!
- * @brief Clears the multiple pins' interrupt status flag.
+ * @brief Clears the multiple pin interrupt status flag.
  *
  * @param base PORT peripheral base pointer.
- * @param mask PORT pins' numbers macro.
+ * @param mask PORT pin number macro.
  */
 static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
 {
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rcm.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rcm.c
index 538f6872a3a..0d738643b53 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rcm.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rcm.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -32,6 +32,8 @@
 
 void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config)
 {
+    assert(config);
+
 #if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
     uint32_t reg;
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rcm.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rcm.h
index 81e25559eaf..99b843aaf3a 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rcm.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rcm.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -35,7 +35,6 @@
 /*! @addtogroup rcm */
 /*! @{*/
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -43,8 +42,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief RCM driver version 2.0.0. */
-#define FSL_RCM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief RCM driver version 2.0.1. */
+#define FSL_RCM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
 /*@}*/
 
 /*!
@@ -57,7 +56,7 @@ typedef enum _rcm_reset_source
 #if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP)
     kRCM_SourceWakeup = RCM_SRS_WAKEUP_MASK, /*!< Low-leakage wakeup reset */
 #endif
-    kRCM_SourceLvd = RCM_SRS_LVD_MASK, /*!< low voltage detect reset */
+    kRCM_SourceLvd = RCM_SRS_LVD_MASK, /*!< Low-voltage detect reset */
 #if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC)
     kRCM_SourceLoc = RCM_SRS_LOC_MASK, /*!< Loss of clock reset */
 #endif                                 /* FSL_FEATURE_RCM_HAS_LOC */
@@ -85,7 +84,7 @@ typedef enum _rcm_reset_source
 #if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP)
     kRCM_SourceWakeup = RCM_SRS0_WAKEUP_MASK, /*!< Low-leakage wakeup reset */
 #endif
-    kRCM_SourceLvd = RCM_SRS0_LVD_MASK, /*!< low voltage detect reset */
+    kRCM_SourceLvd = RCM_SRS0_LVD_MASK, /*!< Low-voltage detect reset */
 #if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC)
     kRCM_SourceLoc = RCM_SRS0_LOC_MASK,   /*!< Loss of clock reset */
 #endif /* FSL_FEATURE_RCM_HAS_LOC */
@@ -99,7 +98,7 @@ typedef enum _rcm_reset_source
     kRCM_SourceJtag = RCM_SRS1_JTAG_MASK << 8U,     /*!< JTAG generated reset */
 #endif /* FSL_FEATURE_RCM_HAS_JTAG */
     kRCM_SourceLockup = RCM_SRS1_LOCKUP_MASK << 8U, /*!< Core lock up reset */
-    kRCM_SourceSw = RCM_SRS1_SW_MASK, /*!< Software reset */
+    kRCM_SourceSw = RCM_SRS1_SW_MASK << 8U, /*!< Software reset */
 #if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP)
     kRCM_SourceMdmap = RCM_SRS1_MDM_AP_MASK << 8U,    /*!< MDM-AP system reset */
 #endif /* FSL_FEATURE_RCM_HAS_MDM_AP */
@@ -112,7 +111,7 @@ typedef enum _rcm_reset_source
 } rcm_reset_source_t;
 
 /*!
- * @brief Reset pin filter select in Run and Wait modes
+ * @brief Reset pin filter select in Run and Wait modes.
  */
 typedef enum _rcm_run_wait_filter_mode
 {
@@ -136,7 +135,7 @@ typedef enum _rcm_boot_rom_config
 
 #if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE)
 /*!
- * @brief Max delay time from interrupt asserts to system reset.
+ * @brief Maximum delay time from interrupt asserts to system reset.
  */
 typedef enum _rcm_reset_delay
 {
@@ -187,7 +186,7 @@ typedef struct _rcm_version_id
 #endif
 
 /*!
- * @brief Reset pin filter configuration
+ * @brief Reset pin filter configuration.
  */
 typedef struct _rcm_reset_pin_filter_config
 {
@@ -214,7 +213,7 @@ extern "C" {
  * the minor version number, and the feature specification number.
  *
  * @param base RCM peripheral base address.
- * @param versionId     Pointer to version ID structure.
+ * @param versionId     Pointer to the version ID structure.
  */
 static inline void RCM_GetVersionId(RCM_Type *base, rcm_version_id_t *versionId)
 {
@@ -229,7 +228,7 @@ static inline void RCM_GetVersionId(RCM_Type *base, rcm_version_id_t *versionId)
  * This function gets the RCM parameter that indicates whether the corresponding reset source is implemented.
  * Use source masks defined in the rcm_reset_source_t to get the desired source status.
  *
- * Example:
+ * This is an example.
    @code
    uint32_t status;
 
@@ -252,7 +251,7 @@ static inline uint32_t RCM_GetResetSourceImplementedStatus(RCM_Type *base)
  * This function gets the current reset source status. Use source masks
  * defined in the rcm_reset_source_t to get the desired source status.
  *
- * Example:
+ * This is an example.
    @code
    uint32_t resetStatus;
 
@@ -283,9 +282,9 @@ static inline uint32_t RCM_GetPreviousResetSources(RCM_Type *base)
  * @brief Gets the sticky reset source status.
  *
  * This function gets the current reset source status that has not been cleared
- * by software for some specific source.
+ * by software for a specific source.
  *
- * Example:
+ * This is an example.
    @code
    uint32_t resetStatus;
 
@@ -316,7 +315,7 @@ static inline uint32_t RCM_GetStickyResetSources(RCM_Type *base)
  *
  * This function clears the sticky system reset flags indicated by source masks.
  *
- * Example:
+ * This is an example.
    @code
    // Clears multiple reset sources.
    RCM_ClearStickyResetSources(kRCM_SourceWdog | kRCM_SourcePin);
@@ -403,7 +402,7 @@ void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config);
 /*!
  * @brief Sets the system reset interrupt configuration.
  *
- * For graceful shutdown, the RCM supports delaying the assertion of the system
+ * For a graceful shut down, the RCM supports delaying the assertion of the system
  * reset for a period of time when the reset interrupt is generated. This function
  * can be used to enable the interrupt and the delay period. The interrupts
  * are passed in as bit mask. See rcm_int_t for details. For example, to
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rnga.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rnga.c
index 9be27499efd..6f0adc66f59 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rnga.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rnga.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -181,10 +181,14 @@ static uint32_t rnga_ReadEntropy(RNG_Type *base);
 
 void RNGA_Init(RNG_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the clock gate. */
     CLOCK_EnableClock(kCLOCK_Rnga0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
     CLOCK_DisableClock(kCLOCK_Rnga0); /* To solve the release version on twrkm43z75m */
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_EnableClock(kCLOCK_Rnga0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Reset the registers for RNGA module to reset state. */
     RNG_WR_CR(base, 0);
@@ -194,8 +198,10 @@ void RNGA_Init(RNG_Type *base)
 
 void RNGA_Deinit(RNG_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable the clock for RNGA module.*/
     CLOCK_DisableClock(kCLOCK_Rnga0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 /*!
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rnga.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rnga.h
index 04950a4540c..92f5bff8bec 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rnga.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rnga.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -34,11 +34,10 @@
 
 #if defined(FSL_FEATURE_SOC_RNG_COUNT) && FSL_FEATURE_SOC_RNG_COUNT
 /*!
- * @addtogroup rnga_driver
+ * @addtogroup rnga
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rtc.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rtc.c
index 898a544a467..d68055a2690 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rtc.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rtc.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -74,6 +74,8 @@ static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datet
  ******************************************************************************/
 static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime)
 {
+    assert(datetime);
+
     /* Table of days in a month for a non leap year. First entry in the table is not used,
      * valid months start from 1
      */
@@ -88,13 +90,13 @@ static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime)
     }
 
     /* Adjust the days in February for a leap year */
-    if (!(datetime->year & 3U))
+    if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0))
     {
         daysPerMonth[2] = 29U;
     }
 
     /* Check the validity of the day */
-    if (datetime->day > daysPerMonth[datetime->month])
+    if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U))
     {
         return false;
     }
@@ -104,6 +106,9 @@ static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime)
 
 static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime)
 {
+    assert(datetime);
+
+    /* Number of days from begin of the non Leap-year*/
     /* Number of days from begin of the non Leap-year*/
     uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U};
     uint32_t seconds;
@@ -131,6 +136,8 @@ static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime)
 
 static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime)
 {
+    assert(datetime);
+
     uint32_t x;
     uint32_t secondsRemaining, days;
     uint16_t daysInYear;
@@ -204,7 +211,9 @@ void RTC_Init(RTC_Type *base, const rtc_config_t *config)
 
     uint32_t reg;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_EnableClock(kCLOCK_Rtc0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Issue a software reset if timer is invalid */
     if (RTC_GetStatusFlags(RTC) & kRTC_TimeInvalidFlag)
@@ -216,7 +225,7 @@ void RTC_Init(RTC_Type *base, const rtc_config_t *config)
     /* Setup the update mode and supervisor access mode */
     reg &= ~(RTC_CR_UM_MASK | RTC_CR_SUP_MASK);
     reg |= RTC_CR_UM(config->updateMode) | RTC_CR_SUP(config->supervisorAccess);
-#if defined(FSL_FEATURE_RTC_HAS_WAKEUP_PIN) && FSL_FEATURE_RTC_HAS_WAKEUP_PIN
+#if defined(FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION) && FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION
     /* Setup the wakeup pin select */
     reg &= ~(RTC_CR_WPS_MASK);
     reg |= RTC_CR_WPS(config->wakeupSelect);
@@ -340,6 +349,8 @@ void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask)
 
 void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter)
 {
+    assert(counter);
+
     *counter = (((uint64_t)base->MCHR << 32) | ((uint64_t)base->MCLR));
 }
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rtc.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rtc.h
index 063d1d40c34..99effc6dcb9 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rtc.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_rtc.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -33,11 +33,10 @@
 #include "fsl_common.h"
 
 /*!
- * @addtogroup rtc_driver
+ * @addtogroup rtc
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -65,15 +64,19 @@ typedef enum _rtc_status_flags
     kRTC_AlarmFlag = RTC_SR_TAF_MASK         /*!< Alarm flag*/
 } rtc_status_flags_t;
 
+#if (defined(FSL_FEATURE_RTC_HAS_OSC_SCXP) && FSL_FEATURE_RTC_HAS_OSC_SCXP)
+
 /*! @brief List of RTC Oscillator capacitor load settings */
 typedef enum _rtc_osc_cap_load
 {
-    kRTC_Capacitor_2p = RTC_CR_SC2P_MASK,  /*!< 2pF capacitor load */
-    kRTC_Capacitor_4p = RTC_CR_SC4P_MASK,  /*!< 4pF capacitor load */
-    kRTC_Capacitor_8p = RTC_CR_SC8P_MASK,  /*!< 8pF capacitor load */
-    kRTC_Capacitor_16p = RTC_CR_SC16P_MASK /*!< 16pF capacitor load */
+    kRTC_Capacitor_2p = RTC_CR_SC2P_MASK,  /*!< 2 pF capacitor load */
+    kRTC_Capacitor_4p = RTC_CR_SC4P_MASK,  /*!< 4 pF capacitor load */
+    kRTC_Capacitor_8p = RTC_CR_SC8P_MASK,  /*!< 8 pF capacitor load */
+    kRTC_Capacitor_16p = RTC_CR_SC16P_MASK /*!< 16 pF capacitor load */
 } rtc_osc_cap_load_t;
 
+#endif /* FSL_FEATURE_SCG_HAS_OSC_SCXP */
+
 /*! @brief Structure is used to hold the date and time */
 typedef struct _rtc_datetime
 {
@@ -96,7 +99,7 @@ typedef struct _rtc_datetime
  */
 typedef struct _rtc_config
 {
-    bool wakeupSelect;             /*!< true: Wakeup pin outputs the 32KHz clock;
+    bool wakeupSelect;             /*!< true: Wakeup pin outputs the 32 KHz clock;
                                         false:Wakeup pin used to wakeup the chip  */
     bool updateMode;               /*!< true: Registers can be written even when locked under certain
                                         conditions, false: No writes allowed when registers are locked */
@@ -122,17 +125,17 @@ extern "C" {
 /*!
  * @brief Ungates the RTC clock and configures the peripheral for basic operation.
  *
- * This function will issue a software reset if the timer invalid flag is set.
+ * This function issues a software reset if the timer invalid flag is set.
  *
  * @note This API should be called at the beginning of the application using the RTC driver.
  *
  * @param base   RTC peripheral base address
- * @param config Pointer to user's RTC config structure.
+ * @param config Pointer to the user's RTC configuration structure.
  */
 void RTC_Init(RTC_Type *base, const rtc_config_t *config);
 
 /*!
- * @brief Stop the timer and gate the RTC clock
+ * @brief Stops the timer and gate the RTC clock.
  *
  * @param base RTC peripheral base address
  */
@@ -141,14 +144,16 @@ static inline void RTC_Deinit(RTC_Type *base)
     /* Stop the RTC timer */
     base->SR &= ~RTC_SR_TCE_MASK;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Gate the module clock */
     CLOCK_DisableClock(kCLOCK_Rtc0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 /*!
- * @brief Fill in the RTC config struct with the default settings
+ * @brief Fills in the RTC config struct with the default settings.
  *
- * The default values are:
+ * The default values are as follows.
  * @code
  *    config->wakeupSelect = false;
  *    config->updateMode = false;
@@ -156,7 +161,7 @@ static inline void RTC_Deinit(RTC_Type *base)
  *    config->compensationInterval = 0;
  *    config->compensationTime = 0;
  * @endcode
- * @param config Pointer to user's RTC config structure.
+ * @param config Pointer to the user's RTC configuration structure.
  */
 void RTC_GetDefaultConfig(rtc_config_t *config);
 
@@ -170,11 +175,11 @@ void RTC_GetDefaultConfig(rtc_config_t *config);
 /*!
  * @brief Sets the RTC date and time according to the given time structure.
  *
- * The RTC counter must be stopped prior to calling this function as writes to the RTC
- * seconds register will fail if the RTC counter is running.
+ * The RTC counter must be stopped prior to calling this function because writes to the RTC
+ * seconds register fail if the RTC counter is running.
  *
  * @param base     RTC peripheral base address
- * @param datetime Pointer to structure where the date and time details to set are stored
+ * @param datetime Pointer to the structure where the date and time details are stored.
  *
  * @return kStatus_Success: Success in setting the time and starting the RTC
  *         kStatus_InvalidArgument: Error because the datetime format is incorrect
@@ -185,18 +190,18 @@ status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime);
  * @brief Gets the RTC time and stores it in the given time structure.
  *
  * @param base     RTC peripheral base address
- * @param datetime Pointer to structure where the date and time details are stored.
+ * @param datetime Pointer to the structure where the date and time details are stored.
  */
 void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime);
 
 /*!
- * @brief Sets the RTC alarm time
+ * @brief Sets the RTC alarm time.
  *
  * The function checks whether the specified alarm time is greater than the present
  * time. If not, the function does not set the alarm and returns an error.
  *
  * @param base      RTC peripheral base address
- * @param alarmTime Pointer to structure where the alarm time is stored.
+ * @param alarmTime Pointer to the structure where the alarm time is stored.
  *
  * @return kStatus_Success: success in setting the RTC alarm
  *         kStatus_InvalidArgument: Error because the alarm datetime format is incorrect
@@ -208,7 +213,7 @@ status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime);
  * @brief Returns the RTC alarm time.
  *
  * @param base     RTC peripheral base address
- * @param datetime Pointer to structure where the alarm date and time details are stored.
+ * @param datetime Pointer to the structure where the alarm date and time details are stored.
  */
 void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime);
 
@@ -264,7 +269,7 @@ static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base)
  */
 
 /*!
- * @brief Gets the RTC status flags
+ * @brief Gets the RTC status flags.
  *
  * @param base RTC peripheral base address
  *
@@ -319,6 +324,8 @@ static inline void RTC_StopTimer(RTC_Type *base)
 
 /*! @}*/
 
+#if (defined(FSL_FEATURE_RTC_HAS_OSC_SCXP) && FSL_FEATURE_RTC_HAS_OSC_SCXP)
+
 /*!
  * @brief This function sets the specified capacitor configuration for the RTC oscillator.
  *
@@ -336,6 +343,8 @@ static inline void RTC_SetOscCapLoad(RTC_Type *base, uint32_t capLoad)
     base->CR = reg;
 }
 
+#endif /* FSL_FEATURE_SCG_HAS_OSC_SCXP */
+
 /*!
  * @brief Performs a software reset on the RTC module.
  *
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.c
index c38165ec045..73ea64fa4ee 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.c
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -95,15 +95,17 @@ static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWi
 /*******************************************************************************
  * Variables
  ******************************************************************************/
-/*!@brief SAI handle pointer */
-sai_handle_t *s_saiHandle[FSL_FEATURE_SOC_I2S_COUNT][2];
 /* Base pointer array */
 static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS;
+/*!@brief SAI handle pointer */
+sai_handle_t *s_saiHandle[ARRAY_SIZE(s_saiBases)][2];
 /* IRQ number array */
 static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS;
 static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /* Clock name array */
 static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 /*! @brief Pointer to tx IRQ handler for each instance. */
 static sai_tx_isr_t s_saiTxIsr;
 /*! @brief Pointer to tx IRQ handler for each instance. */
@@ -181,7 +183,7 @@ uint32_t SAI_GetInstance(I2S_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_I2S_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_saiBases); instance++)
     {
         if (s_saiBases[instance] == base)
         {
@@ -189,7 +191,7 @@ uint32_t SAI_GetInstance(I2S_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_I2S_COUNT);
+    assert(instance < ARRAY_SIZE(s_saiBases));
 
     return instance;
 }
@@ -237,8 +239,10 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config)
 {
     uint32_t val = 0;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the SAI clock */
     CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
     /* Master clock source setting */
@@ -339,8 +343,10 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config)
 {
     uint32_t val = 0;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable SAI clock first. */
     CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
     /* Master clock source setting */
@@ -441,7 +447,9 @@ void SAI_Deinit(I2S_Type *base)
 {
     SAI_TxEnable(base, false);
     SAI_RxEnable(base, false);
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_DisableClock(s_saiClock[SAI_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void SAI_TxGetDefaultConfig(sai_config_t *config)
@@ -632,7 +640,7 @@ void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint
     uint32_t i = 0;
     uint8_t bytesPerWord = bitWidth / 8U;
 
-    for (i = 0; i < size; i++)
+    while (i < size)
     {
         /* Wait until it can write data */
         while (!(base->TCSR & I2S_TCSR_FWF_MASK))
@@ -641,6 +649,7 @@ void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint
 
         SAI_WriteNonBlocking(base, channel, bitWidth, buffer, bytesPerWord);
         buffer += bytesPerWord;
+        i += bytesPerWord;
     }
 
     /* Wait until the last data is sent */
@@ -654,7 +663,7 @@ void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8
     uint32_t i = 0;
     uint8_t bytesPerWord = bitWidth / 8U;
 
-    for (i = 0; i < size; i++)
+    while (i < size)
     {
         /* Wait until data is received */
         while (!(base->RCSR & I2S_RCSR_FWF_MASK))
@@ -663,6 +672,7 @@ void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8
 
         SAI_ReadNonBlocking(base, channel, bitWidth, buffer, bytesPerWord);
         buffer += bytesPerWord;
+        i += bytesPerWord;
     }
 }
 
@@ -670,6 +680,9 @@ void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf
 {
     assert(handle);
 
+    /* Zero the handle */
+    memset(handle, 0, sizeof(*handle));
+
     s_saiHandle[SAI_GetInstance(base)][0] = handle;
 
     handle->callback = callback;
@@ -686,6 +699,9 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf
 {
     assert(handle);
 
+    /* Zero the handle */
+    memset(handle, 0, sizeof(*handle));
+
     s_saiHandle[SAI_GetInstance(base)][1] = handle;
 
     handle->callback = callback;
@@ -1024,19 +1040,30 @@ void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
 }
 
 #if defined(I2S0)
-#if defined(FSL_FEATURE_SAI_INT_SOURCE_NUM) && (FSL_FEATURE_SAI_INT_SOURCE_NUM == 1)
 void I2S0_DriverIRQHandler(void)
 {
-    if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag)))
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFORequestFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S0->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S0->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S0->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S0->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
     {
         s_saiRxIsr(I2S0, s_saiHandle[0][1]);
     }
-    if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag)))
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFORequestFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S0->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S0->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S0->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S0->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
     {
         s_saiTxIsr(I2S0, s_saiHandle[0][0]);
     }
 }
-#else
+
 void I2S0_Tx_DriverIRQHandler(void)
 {
     assert(s_saiHandle[0][0]);
@@ -1048,10 +1075,33 @@ void I2S0_Rx_DriverIRQHandler(void)
     assert(s_saiHandle[0][1]);
     s_saiRxIsr(I2S0, s_saiHandle[0][1]);
 }
-#endif /* FSL_FEATURE_SAI_INT_SOURCE_NUM */
 #endif /* I2S0*/
 
 #if defined(I2S1)
+void I2S1_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[1][1]) && ((I2S1->RCSR & kSAI_FIFORequestFlag) || (I2S1->RCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S1->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S1->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[1][1]) && ((I2S1->RCSR & kSAI_FIFOWarningFlag) || (I2S1->RCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S1->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S1->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiRxIsr(I2S1, s_saiHandle[1][1]);
+    }
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[1][0]) && ((I2S1->TCSR & kSAI_FIFORequestFlag) || (I2S1->TCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S1->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S1->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[1][0]) && ((I2S1->TCSR & kSAI_FIFOWarningFlag) || (I2S1->TCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S1->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S1->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiTxIsr(I2S1, s_saiHandle[1][0]);
+    }
+}
+
 void I2S1_Tx_DriverIRQHandler(void)
 {
     assert(s_saiHandle[1][0]);
@@ -1063,4 +1113,80 @@ void I2S1_Rx_DriverIRQHandler(void)
     assert(s_saiHandle[1][1]);
     s_saiRxIsr(I2S1, s_saiHandle[1][1]);
 }
+#endif /* I2S1*/
+
+#if defined(I2S2)
+void I2S2_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[2][1]) && ((I2S2->RCSR & kSAI_FIFORequestFlag) || (I2S2->RCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S2->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S2->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[2][1]) && ((I2S2->RCSR & kSAI_FIFOWarningFlag) || (I2S2->RCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S2->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S2->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiRxIsr(I2S2, s_saiHandle[2][1]);
+    }
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[2][0]) && ((I2S2->TCSR & kSAI_FIFORequestFlag) || (I2S2->TCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S2->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S2->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[2][0]) && ((I2S2->TCSR & kSAI_FIFOWarningFlag) || (I2S2->TCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S2->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S2->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiTxIsr(I2S2, s_saiHandle[2][0]);
+    }
+}
+
+void I2S2_Tx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[2][0]);
+    s_saiTxIsr(I2S2, s_saiHandle[2][0]);
+}
+
+void I2S2_Rx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[2][1]);
+    s_saiRxIsr(I2S2, s_saiHandle[2][1]);
+}
+#endif /* I2S2*/
+
+#if defined(I2S3)
+void I2S3_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[3][1]) && ((I2S3->RCSR & kSAI_FIFORequestFlag) || (I2S3->RCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S3->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S3->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[3][1]) && ((I2S3->RCSR & kSAI_FIFOWarningFlag) || (I2S3->RCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S3->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S3->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiRxIsr(I2S3, s_saiHandle[3][1]);
+    }
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[3][0]) && ((I2S3->TCSR & kSAI_FIFORequestFlag) || (I2S3->TCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S3->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S3->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[3][0]) && ((I2S3->TCSR & kSAI_FIFOWarningFlag) || (I2S3->TCSR & kSAI_FIFOErrorFlag)) &&
+                               ((I2S3->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S3->TCSR & kSAI_FIFOErrorInterruptEnable)))
 #endif
+    {
+        s_saiTxIsr(I2S3, s_saiHandle[3][0]);
+    }
+}
+
+void I2S3_Tx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[3][0]);
+    s_saiTxIsr(I2S3, s_saiHandle[3][0]);
+}
+
+void I2S3_Rx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[3][1]);
+    s_saiRxIsr(I2S3, s_saiHandle[3][1]);
+}
+#endif /* I2S3*/
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.h
index cb38688cd92..64a2f667fce 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -38,14 +38,13 @@
  * @{
  */
 
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */
+#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*!< Version 2.1.2 */
 /*@}*/
 
 /*! @brief SAI return status*/
@@ -186,16 +185,16 @@ typedef struct _sai_config
 /*! @brief Audio sample rate */
 typedef enum _sai_sample_rate
 {
-    kSAI_SampleRate8KHz = 8000U,     /*!< Sample rate 8000Hz */
-    kSAI_SampleRate11025Hz = 11025U, /*!< Sample rate 11025Hz */
-    kSAI_SampleRate12KHz = 12000U,   /*!< Sample rate 12000Hz */
-    kSAI_SampleRate16KHz = 16000U,   /*!< Sample rate 16000Hz */
-    kSAI_SampleRate22050Hz = 22050U, /*!< Sample rate 22050Hz */
-    kSAI_SampleRate24KHz = 24000U,   /*!< Sample rate 24000Hz */
-    kSAI_SampleRate32KHz = 32000U,   /*!< Sample rate 32000Hz */
-    kSAI_SampleRate44100Hz = 44100U, /*!< Sample rate 44100Hz */
-    kSAI_SampleRate48KHz = 48000U,   /*!< Sample rate 48000Hz */
-    kSAI_SampleRate96KHz = 96000U    /*!< Sample rate 96000Hz */
+    kSAI_SampleRate8KHz = 8000U,     /*!< Sample rate 8000 Hz */
+    kSAI_SampleRate11025Hz = 11025U, /*!< Sample rate 11025 Hz */
+    kSAI_SampleRate12KHz = 12000U,   /*!< Sample rate 12000 Hz */
+    kSAI_SampleRate16KHz = 16000U,   /*!< Sample rate 16000 Hz */
+    kSAI_SampleRate22050Hz = 22050U, /*!< Sample rate 22050 Hz */
+    kSAI_SampleRate24KHz = 24000U,   /*!< Sample rate 24000 Hz */
+    kSAI_SampleRate32KHz = 32000U,   /*!< Sample rate 32000 Hz */
+    kSAI_SampleRate44100Hz = 44100U, /*!< Sample rate 44100 Hz */
+    kSAI_SampleRate48KHz = 48000U,   /*!< Sample rate 48000 Hz */
+    kSAI_SampleRate96KHz = 96000U    /*!< Sample rate 96000 Hz */
 } sai_sample_rate_t;
 
 /*! @brief Audio word width */
@@ -211,7 +210,7 @@ typedef enum _sai_word_width
 typedef struct _sai_transfer_format
 {
     uint32_t sampleRate_Hz;   /*!< Sample rate of audio data */
-    uint32_t bitWidth;        /*!< Data length of audio data, usually 8/16/24/32bits */
+    uint32_t bitWidth;        /*!< Data length of audio data, usually 8/16/24/32 bits */
     sai_mono_stereo_t stereo; /*!< Mono or stereo */
     uint32_t masterClockHz;   /*!< Master clock frequency in Hz */
 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
@@ -239,7 +238,7 @@ struct _sai_handle
     uint32_t state;                               /*!< Transfer status */
     sai_transfer_callback_t callback;             /*!< Callback function called at transfer event*/
     void *userData;                               /*!< Callback parameter passed to callback function*/
-    uint8_t bitWidth;                             /*!< Bit width for transfer, 8/16/24/32bits */
+    uint8_t bitWidth;                             /*!< Bit width for transfer, 8/16/24/32 bits */
     uint8_t channel;                              /*!< Transfer channel */
     sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */
     size_t transferSize[SAI_XFER_QUEUE_SIZE];     /*!< Data bytes need to transfer */
@@ -301,7 +300,7 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config);
  * This API initializes the configuration structure for use in SAI_TxConfig().
  * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified
  *  before calling SAI_TxConfig().
- * Example:
+ * This is an example.
    @code
    sai_config_t config;
    SAI_TxGetDefaultConfig(&config);
@@ -317,7 +316,7 @@ void SAI_TxGetDefaultConfig(sai_config_t *config);
  * This API initializes the configuration structure for use in SAI_RxConfig().
  * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified
  *  before calling SAI_RxConfig().
- * Example:
+ * This is an example.
    @code
    sai_config_t config;
    SAI_RxGetDefaultConfig(&config);
@@ -356,7 +355,7 @@ void SAI_TxReset(I2S_Type *base);
 void SAI_RxReset(I2S_Type *base);
 
 /*!
- * @brief Enables/disables SAI Tx.
+ * @brief Enables/disables the SAI Tx.
  *
  * @param base SAI base pointer
  * @param enable True means enable SAI Tx, false means disable.
@@ -364,7 +363,7 @@ void SAI_RxReset(I2S_Type *base);
 void SAI_TxEnable(I2S_Type *base, bool enable);
 
 /*!
- * @brief Enables/disables SAI Rx.
+ * @brief Enables/disables the SAI Rx.
  *
  * @param base SAI base pointer
  * @param enable True means enable SAI Rx, false means disable.
@@ -418,7 +417,7 @@ static inline uint32_t SAI_RxGetStatusFlag(I2S_Type *base)
  * @brief Clears the SAI Rx status flag state.
  *
  * @param base SAI base pointer
- * @param mask State mask. It can be a combination of the following source if defined:
+ * @param mask State mask. It can be a combination of the following sources if defined.
  *        @arg kSAI_WordStartFlag
  *        @arg kSAI_SyncErrorFlag
  *        @arg kSAI_FIFOErrorFlag
@@ -436,11 +435,11 @@ static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask)
  */
 
 /*!
- * @brief Enables SAI Tx interrupt requests.
+ * @brief Enables the SAI Tx interrupt requests.
  *
  * @param base SAI base pointer
  * @param mask interrupt source
- *     The parameter can be a combination of the following source if defined:
+ *     The parameter can be a combination of the following sources if defined.
  *     @arg kSAI_WordStartInterruptEnable
  *     @arg kSAI_SyncErrorInterruptEnable
  *     @arg kSAI_FIFOWarningInterruptEnable
@@ -453,11 +452,11 @@ static inline void SAI_TxEnableInterrupts(I2S_Type *base, uint32_t mask)
 }
 
 /*!
- * @brief Enables SAI Rx interrupt requests.
+ * @brief Enables the SAI Rx interrupt requests.
  *
  * @param base SAI base pointer
  * @param mask interrupt source
- *     The parameter can be a combination of the following source if defined:
+ *     The parameter can be a combination of the following sources if defined.
  *     @arg kSAI_WordStartInterruptEnable
  *     @arg kSAI_SyncErrorInterruptEnable
  *     @arg kSAI_FIFOWarningInterruptEnable
@@ -470,11 +469,11 @@ static inline void SAI_RxEnableInterrupts(I2S_Type *base, uint32_t mask)
 }
 
 /*!
- * @brief Disables SAI Tx interrupt requests.
+ * @brief Disables the SAI Tx interrupt requests.
  *
  * @param base SAI base pointer
  * @param mask interrupt source
- *     The parameter can be a combination of the following source if defined:
+ *     The parameter can be a combination of the following sources if defined.
  *     @arg kSAI_WordStartInterruptEnable
  *     @arg kSAI_SyncErrorInterruptEnable
  *     @arg kSAI_FIFOWarningInterruptEnable
@@ -487,11 +486,11 @@ static inline void SAI_TxDisableInterrupts(I2S_Type *base, uint32_t mask)
 }
 
 /*!
- * @brief Disables SAI Rx interrupt requests.
+ * @brief Disables the SAI Rx interrupt requests.
  *
  * @param base SAI base pointer
  * @param mask interrupt source
- *     The parameter can be a combination of the following source if defined:
+ *     The parameter can be a combination of the following sources if defined.
  *     @arg kSAI_WordStartInterruptEnable
  *     @arg kSAI_SyncErrorInterruptEnable
  *     @arg kSAI_FIFOWarningInterruptEnable
@@ -511,10 +510,10 @@ static inline void SAI_RxDisableInterrupts(I2S_Type *base, uint32_t mask)
  */
 
 /*!
- * @brief Enables/disables SAI Tx DMA requests.
+ * @brief Enables/disables the SAI Tx DMA requests.
  * @param base SAI base pointer
  * @param mask DMA source
- *     The parameter can be combination of the following source if defined:
+ *     The parameter can be combination of the following sources if defined.
  *     @arg kSAI_FIFOWarningDMAEnable
  *     @arg kSAI_FIFORequestDMAEnable
  * @param enable True means enable DMA, false means disable DMA.
@@ -532,10 +531,10 @@ static inline void SAI_TxEnableDMA(I2S_Type *base, uint32_t mask, bool enable)
 }
 
 /*!
- * @brief Enables/disables SAI Rx DMA requests.
+ * @brief Enables/disables the SAI Rx DMA requests.
  * @param base SAI base pointer
  * @param mask DMA source
- *     The parameter can be a combination of the following source if defined:
+ *     The parameter can be a combination of the following sources if defined.
  *     @arg kSAI_FIFOWarningDMAEnable
  *     @arg kSAI_FIFORequestDMAEnable
  * @param enable True means enable DMA, false means disable DMA.
@@ -555,7 +554,7 @@ static inline void SAI_RxEnableDMA(I2S_Type *base, uint32_t mask, bool enable)
 /*!
  * @brief  Gets the SAI Tx data register address.
  *
- * This API is used to provide a transfer address for SAI DMA transfer configuration.
+ * This API is used to provide a transfer address for the SAI DMA transfer configuration.
  *
  * @param base SAI base pointer.
  * @param channel Which data channel used.
@@ -569,7 +568,7 @@ static inline uint32_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t cha
 /*!
  * @brief  Gets the SAI Rx data register address.
  *
- * This API is used to provide a transfer address for SAI DMA transfer configuration.
+ * This API is used to provide a transfer address for the SAI DMA transfer configuration.
  *
  * @param base SAI base pointer.
  * @param channel Which data channel used.
@@ -594,10 +593,10 @@ static inline uint32_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t cha
  * format to be transferred.
  *
  * @param base SAI base pointer.
- * @param format Pointer to SAI audio data format structure.
+ * @param format Pointer to the SAI audio data format structure.
  * @param mclkSourceClockHz SAI master clock source frequency in Hz.
- * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master
- * clock, this value should equals to masterClockHz in format.
+ * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master
+ * clock, this value should equal the masterClockHz.
 */
 void SAI_TxSetFormat(I2S_Type *base,
                      sai_transfer_format_t *format,
@@ -611,10 +610,10 @@ void SAI_TxSetFormat(I2S_Type *base,
  * format to be transferred.
  *
  * @param base SAI base pointer.
- * @param format Pointer to SAI audio data format structure.
+ * @param format Pointer to the SAI audio data format structure.
  * @param mclkSourceClockHz SAI master clock source frequency in Hz.
- * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master
- * clock, this value should equals to masterClockHz in format.
+ * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master
+ * clock, this value should equal the masterClockHz.
 */
 void SAI_RxSetFormat(I2S_Type *base,
                      sai_transfer_format_t *format,
@@ -628,7 +627,7 @@ void SAI_RxSetFormat(I2S_Type *base,
  *
  * @param base SAI base pointer.
  * @param channel Data channel used.
- * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
+ * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
  * @param buffer Pointer to the data to be written.
  * @param size Bytes to be written.
  */
@@ -653,14 +652,14 @@ static inline void SAI_WriteData(I2S_Type *base, uint32_t channel, uint32_t data
  *
  * @param base SAI base pointer.
  * @param channel Data channel used.
- * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
+ * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
  * @param buffer Pointer to the data to be read.
  * @param size Bytes to be read.
  */
 void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size);
 
 /*!
- * @brief Reads data from SAI FIFO.
+ * @brief Reads data from the SAI FIFO.
  *
  * @param base SAI base pointer.
  * @param channel Data channel used.
@@ -681,26 +680,26 @@ static inline uint32_t SAI_ReadData(I2S_Type *base, uint32_t channel)
 /*!
  * @brief Initializes the SAI Tx handle.
  *
- * This function initializes the Tx handle for SAI Tx transactional APIs. Call
- * this function one time to get the handle initialized.
+ * This function initializes the Tx handle for the SAI Tx transactional APIs. Call
+ * this function once to get the handle initialized.
  *
  * @param base SAI base pointer
  * @param handle SAI handle pointer.
- * @param callback pointer to user callback function
- * @param userData user parameter passed to the callback function
+ * @param callback Pointer to the user callback function.
+ * @param userData User parameter passed to the callback function
  */
 void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData);
 
 /*!
  * @brief Initializes the SAI Rx handle.
  *
- * This function initializes the Rx handle for SAI Rx transactional APIs. Call
- * this function one time to get the handle initialized.
+ * This function initializes the Rx handle for the SAI Rx transactional APIs. Call
+ * this function once to get the handle initialized.
  *
  * @param base SAI base pointer.
  * @param handle SAI handle pointer.
- * @param callback pointer to user callback function
- * @param userData user parameter passed to the callback function
+ * @param callback Pointer to the user callback function.
+ * @param userData User parameter passed to the callback function.
  */
 void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData);
 
@@ -712,11 +711,11 @@ void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transf
  *
  * @param base SAI base pointer.
  * @param handle SAI handle pointer.
- * @param format Pointer to SAI audio data format structure.
+ * @param format Pointer to the SAI audio data format structure.
  * @param mclkSourceClockHz SAI master clock source frequency in Hz.
  * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master
- * clock, this value should equal to masterClockHz in format.
- * @return Status of this function. Return value is one of status_t.
+ * clock, this value should equal the masterClockHz in format.
+ * @return Status of this function. Return value is the status_t.
 */
 status_t SAI_TransferTxSetFormat(I2S_Type *base,
                                  sai_handle_t *handle,
@@ -732,10 +731,10 @@ status_t SAI_TransferTxSetFormat(I2S_Type *base,
  *
  * @param base SAI base pointer.
  * @param handle SAI handle pointer.
- * @param format Pointer to SAI audio data format structure.
+ * @param format Pointer to the SAI audio data format structure.
  * @param mclkSourceClockHz SAI master clock source frequency in Hz.
- * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master
- * clock, this value should equals to masterClockHz in format.
+ * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master
+ * clock, this value should equal the masterClockHz in format.
  * @return Status of this function. Return value is one of status_t.
 */
 status_t SAI_TransferRxSetFormat(I2S_Type *base,
@@ -752,9 +751,9 @@ status_t SAI_TransferRxSetFormat(I2S_Type *base,
  * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer
  * is finished.
  *
- * @param base SAI base pointer
- * @param handle pointer to sai_handle_t structure which stores the transfer state
- * @param xfer pointer to sai_transfer_t structure
+ * @param base SAI base pointer.
+ * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ * @param xfer Pointer to the sai_transfer_t structure.
  * @retval kStatus_Success Successfully started the data receive.
  * @retval kStatus_SAI_TxBusy Previous receive still not finished.
  * @retval kStatus_InvalidArgument The input parameter is invalid.
@@ -770,8 +769,8 @@ status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_t
  * is finished.
  *
  * @param base SAI base pointer
- * @param handle pointer to sai_handle_t structure which stores the transfer state
- * @param xfer pointer to sai_transfer_t structure
+ * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
+ * @param xfer Pointer to the sai_transfer_t structure.
  * @retval kStatus_Success Successfully started the data receive.
  * @retval kStatus_SAI_RxBusy Previous receive still not finished.
  * @retval kStatus_InvalidArgument The input parameter is invalid.
@@ -782,7 +781,7 @@ status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sa
  * @brief Gets a set byte count.
  *
  * @param base SAI base pointer.
- * @param handle pointer to sai_handle_t structure which stores the transfer state.
+ * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
  * @param count Bytes count sent.
  * @retval kStatus_Success Succeed get the transfer count.
  * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
@@ -793,7 +792,7 @@ status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *
  * @brief Gets a received byte count.
  *
  * @param base SAI base pointer.
- * @param handle pointer to sai_handle_t structure which stores the transfer state.
+ * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
  * @param count Bytes count received.
  * @retval kStatus_Success Succeed get the transfer count.
  * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
@@ -807,18 +806,18 @@ status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_
  * to abort the transfer early.
  *
  * @param base SAI base pointer.
- * @param handle pointer to sai_handle_t structure which stores the transfer state.
+ * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
  */
 void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle);
 
 /*!
  * @brief Aborts the the current IRQ receive.
  *
- * @note This API can be called any time when an interrupt non-blocking transfer initiates
+ * @note This API can be called when an interrupt non-blocking transfer initiates
  * to abort the transfer early.
  *
  * @param base SAI base pointer
- * @param handle pointer to sai_handle_t structure which stores the transfer state.
+ * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
  */
 void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle);
 
@@ -826,7 +825,7 @@ void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle);
  * @brief Tx interrupt handler.
  *
  * @param base SAI base pointer.
- * @param handle pointer to sai_handle_t structure.
+ * @param handle Pointer to the sai_handle_t structure.
  */
 void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle);
 
@@ -834,7 +833,7 @@ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle);
  * @brief Tx interrupt handler.
  *
  * @param base SAI base pointer.
- * @param handle pointer to sai_handle_t structure.
+ * @param handle Pointer to the sai_handle_t structure.
  */
 void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle);
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai_edma.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai_edma.c
index 9b1b2f6c490..dce5a87bfa1 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai_edma.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai_edma.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -132,6 +132,9 @@ void SAI_TransferTxCreateHandleEDMA(
 
     uint32_t instance = SAI_GetInstance(base);
 
+    /* Zero the handle */
+    memset(handle, 0, sizeof(*handle));
+
     /* Set sai base to handle */
     handle->dmaHandle = dmaHandle;
     handle->callback = callback;
@@ -157,6 +160,9 @@ void SAI_TransferRxCreateHandleEDMA(
 
     uint32_t instance = SAI_GetInstance(base);
 
+    /* Zero the handle */
+    memset(handle, 0, sizeof(*handle));
+
     /* Set sai base to handle */
     handle->dmaHandle = dmaHandle;
     handle->callback = callback;
@@ -187,7 +193,14 @@ void SAI_TransferTxSetFormatEDMA(I2S_Type *base,
     SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz);
 
     /* Get the tranfer size from format, this should be used in EDMA configuration */
-    handle->bytesPerFrame = format->bitWidth / 8U;
+    if (format->bitWidth == 24U)
+    {
+        handle->bytesPerFrame = 4U;
+    }
+    else
+    {
+        handle->bytesPerFrame = format->bitWidth / 8U;
+    }
 
     /* Update the data channel SAI used */
     handle->channel = format->channel;
@@ -210,7 +223,14 @@ void SAI_TransferRxSetFormatEDMA(I2S_Type *base,
     SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz);
 
     /* Get the tranfer size from format, this should be used in EDMA configuration */
-    handle->bytesPerFrame = format->bitWidth / 8U;
+    if (format->bitWidth == 24U)
+    {
+        handle->bytesPerFrame = 4U;
+    }
+    else
+    {
+        handle->bytesPerFrame = format->bitWidth / 8U;
+    }
 
     /* Update the data channel SAI used */
     handle->channel = format->channel;
@@ -253,6 +273,9 @@ status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_tra
     EDMA_PrepareTransfer(&config, xfer->data, handle->bytesPerFrame, (void *)destAddr, handle->bytesPerFrame,
                          handle->count * handle->bytesPerFrame, xfer->dataSize, kEDMA_MemoryToPeripheral);
 
+    /* Store the initially configured eDMA minor byte transfer count into the SAI handle */
+    handle->nbytes = handle->count * handle->bytesPerFrame;
+
     EDMA_SubmitTransfer(handle->dmaHandle, &config);
 
     /* Start DMA transfer */
@@ -298,6 +321,9 @@ status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_
     EDMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame,
                          handle->count * handle->bytesPerFrame, xfer->dataSize, kEDMA_PeripheralToMemory);
 
+    /* Store the initially configured eDMA minor byte transfer count into the SAI handle */
+    handle->nbytes = handle->count * handle->bytesPerFrame;
+
     EDMA_SubmitTransfer(handle->dmaHandle, &config);
 
     /* Start DMA transfer */
@@ -322,6 +348,9 @@ void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle)
     /* Disable DMA enable bit */
     SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, false);
 
+    /* Disable Tx */
+    SAI_TxEnable(base, false);
+
     /* Set the handle state */
     handle->state = kSAI_Idle;
 }
@@ -336,6 +365,9 @@ void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle)
     /* Disable DMA enable bit */
     SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, false);
 
+    /* Disable Rx */
+    SAI_RxEnable(base, false);
+
     /* Set the handle state */
     handle->state = kSAI_Idle;
 }
@@ -353,7 +385,8 @@ status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle,
     else
     {
         *count = (handle->transferSize[handle->queueDriver] -
-                  EDMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel));
+                  (uint32_t)handle->nbytes *
+                      EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel));
     }
 
     return status;
@@ -372,7 +405,8 @@ status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *hand
     else
     {
         *count = (handle->transferSize[handle->queueDriver] -
-                  EDMA_GetRemainingBytes(handle->dmaHandle->base, handle->dmaHandle->channel));
+                  (uint32_t)handle->nbytes *
+                      EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel));
     }
 
     return status;
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai_edma.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai_edma.h
index 44506fa039d..9ae05db0e95 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai_edma.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai_edma.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -38,8 +38,6 @@
  * @{
  */
 
-/*! @file */
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
@@ -53,6 +51,7 @@ typedef void (*sai_edma_callback_t)(I2S_Type *base, sai_edma_handle_t *handle, s
 struct _sai_edma_handle
 {
     edma_handle_t *dmaHandle;                     /*!< DMA handler for SAI send */
+    uint8_t nbytes;                               /*!< eDMA minor byte transfer count initially configured. */
     uint8_t bytesPerFrame;                        /*!< Bytes in a frame */
     uint8_t channel;                              /*!< Which data channel */
     uint8_t count;                                /*!< The transfer data count in a DMA request */
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdhc.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdhc.c
index d2774eeabc9..3151cd22ed9 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdhc.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdhc.c
@@ -1,34 +1,28 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
- * Redistribution and use in source and binary forms, with or without
- * modification,
+ * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *
- * o Redistributions of source code must retain the above copyright notice, this
- * list
+ * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
  *
- * o Redistributions in binary form must reproduce the above copyright notice,
- * this
+ * o Redistributions in binary form must reproduce the above copyright notice, this
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
@@ -42,12 +36,8 @@
 /*! @brief Clock setting */
 /* Max SD clock divisor from base clock */
 #define SDHC_MAX_DVS ((SDHC_SYSCTL_DVS_MASK >> SDHC_SYSCTL_DVS_SHIFT) + 1U)
-#define SDHC_INITIAL_DVS (1U)   /* Initial value of SD clock divisor */
-#define SDHC_INITIAL_CLKFS (2U) /* Initial value of SD clock frequency selector */
-#define SDHC_NEXT_DVS(x) ((x) += 1U)
 #define SDHC_PREV_DVS(x) ((x) -= 1U)
 #define SDHC_MAX_CLKFS ((SDHC_SYSCTL_SDCLKFS_MASK >> SDHC_SYSCTL_SDCLKFS_SHIFT) + 1U)
-#define SDHC_NEXT_CLKFS(x) ((x) <<= 1U)
 #define SDHC_PREV_CLKFS(x) ((x) >>= 1U)
 
 /* Typedef for interrupt handler. */
@@ -85,8 +75,9 @@ static void SDHC_SetTransferInterrupt(SDHC_Type *base, bool usingInterruptSignal
  * @param base SDHC peripheral base address.
  * @param command Command to be sent.
  * @param data Data to be transferred.
+ * @param DMA mode selection
  */
-static void SDHC_StartTransfer(SDHC_Type *base, sdhc_command_t *command, sdhc_data_t *data);
+static void SDHC_StartTransfer(SDHC_Type *base, sdhc_command_t *command, sdhc_data_t *data, sdhc_dma_mode_t dmaMode);
 
 /*!
  * @brief Receive command response
@@ -94,7 +85,7 @@ static void SDHC_StartTransfer(SDHC_Type *base, sdhc_command_t *command, sdhc_da
  * @param base SDHC peripheral base address.
  * @param command Command to be sent.
  */
-static void SDHC_ReceiveCommandResponse(SDHC_Type *base, sdhc_command_t *command);
+static status_t SDHC_ReceiveCommandResponse(SDHC_Type *base, sdhc_command_t *command);
 
 /*!
  * @brief Read DATAPORT when buffer enable bit is set.
@@ -230,8 +221,10 @@ static SDHC_Type *const s_sdhcBase[] = SDHC_BASE_PTRS;
 /*! @brief SDHC IRQ name array */
 static const IRQn_Type s_sdhcIRQ[] = SDHC_IRQS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief SDHC clock array name */
 static const clock_ip_name_t s_sdhcClock[] = SDHC_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /* SDHC ISR for transactional APIs. */
 static sdhc_isr_t s_sdhcIsr;
@@ -243,12 +236,12 @@ static uint32_t SDHC_GetInstance(SDHC_Type *base)
 {
     uint8_t instance = 0;
 
-    while ((instance < FSL_FEATURE_SOC_SDHC_COUNT) && (s_sdhcBase[instance] != base))
+    while ((instance < ARRAY_SIZE(s_sdhcBase)) && (s_sdhcBase[instance] != base))
     {
         instance++;
     }
 
-    assert(instance < FSL_FEATURE_SOC_SDHC_COUNT);
+    assert(instance < ARRAY_SIZE(s_sdhcBase));
 
     return instance;
 }
@@ -256,7 +249,6 @@ static uint32_t SDHC_GetInstance(SDHC_Type *base)
 static void SDHC_SetTransferInterrupt(SDHC_Type *base, bool usingInterruptSignal)
 {
     uint32_t interruptEnabled; /* The Interrupt status flags to be enabled */
-    sdhc_dma_mode_t dmaMode = (sdhc_dma_mode_t)((base->PROCTL & SDHC_PROCTL_DMAS_MASK) >> SDHC_PROCTL_DMAS_SHIFT);
     bool cardDetectDat3 = (bool)(base->PROCTL & SDHC_PROCTL_D3CD_MASK);
 
     /* Disable all interrupts */
@@ -267,23 +259,12 @@ static void SDHC_SetTransferInterrupt(SDHC_Type *base, bool usingInterruptSignal
     interruptEnabled =
         (kSDHC_CommandIndexErrorFlag | kSDHC_CommandCrcErrorFlag | kSDHC_CommandEndBitErrorFlag |
          kSDHC_CommandTimeoutFlag | kSDHC_CommandCompleteFlag | kSDHC_DataTimeoutFlag | kSDHC_DataCrcErrorFlag |
-         kSDHC_DataEndBitErrorFlag | kSDHC_DataCompleteFlag | kSDHC_AutoCommand12ErrorFlag);
+         kSDHC_DataEndBitErrorFlag | kSDHC_DataCompleteFlag | kSDHC_AutoCommand12ErrorFlag | kSDHC_BufferReadReadyFlag |
+         kSDHC_BufferWriteReadyFlag | kSDHC_DmaErrorFlag | kSDHC_DmaCompleteFlag);
     if (cardDetectDat3)
     {
         interruptEnabled |= (kSDHC_CardInsertionFlag | kSDHC_CardRemovalFlag);
     }
-    switch (dmaMode)
-    {
-        case kSDHC_DmaModeAdma1:
-        case kSDHC_DmaModeAdma2:
-            interruptEnabled |= (kSDHC_DmaErrorFlag | kSDHC_DmaCompleteFlag);
-            break;
-        case kSDHC_DmaModeNo:
-            interruptEnabled |= (kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag);
-            break;
-        default:
-            break;
-    }
 
     SDHC_EnableInterruptStatus(base, interruptEnabled);
     if (usingInterruptSignal)
@@ -292,48 +273,47 @@ static void SDHC_SetTransferInterrupt(SDHC_Type *base, bool usingInterruptSignal
     }
 }
 
-static void SDHC_StartTransfer(SDHC_Type *base, sdhc_command_t *command, sdhc_data_t *data)
+static void SDHC_StartTransfer(SDHC_Type *base, sdhc_command_t *command, sdhc_data_t *data, sdhc_dma_mode_t dmaMode)
 {
     uint32_t flags = 0U;
     sdhc_transfer_config_t sdhcTransferConfig = {0};
-    sdhc_dma_mode_t dmaMode;
 
     /* Define the flag corresponding to each response type. */
     switch (command->responseType)
     {
-        case kSDHC_ResponseTypeNone:
+        case kCARD_ResponseTypeNone:
             break;
-        case kSDHC_ResponseTypeR1: /* Response 1 */
+        case kCARD_ResponseTypeR1: /* Response 1 */
             flags |= (kSDHC_ResponseLength48Flag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag);
             break;
-        case kSDHC_ResponseTypeR1b: /* Response 1 with busy */
+        case kCARD_ResponseTypeR1b: /* Response 1 with busy */
             flags |= (kSDHC_ResponseLength48BusyFlag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag);
             break;
-        case kSDHC_ResponseTypeR2: /* Response 2 */
+        case kCARD_ResponseTypeR2: /* Response 2 */
             flags |= (kSDHC_ResponseLength136Flag | kSDHC_EnableCrcCheckFlag);
             break;
-        case kSDHC_ResponseTypeR3: /* Response 3 */
+        case kCARD_ResponseTypeR3: /* Response 3 */
             flags |= (kSDHC_ResponseLength48Flag);
             break;
-        case kSDHC_ResponseTypeR4: /* Response 4 */
+        case kCARD_ResponseTypeR4: /* Response 4 */
             flags |= (kSDHC_ResponseLength48Flag);
             break;
-        case kSDHC_ResponseTypeR5: /* Response 5 */
+        case kCARD_ResponseTypeR5: /* Response 5 */
             flags |= (kSDHC_ResponseLength48Flag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag);
             break;
-        case kSDHC_ResponseTypeR5b: /* Response 5 with busy */
+        case kCARD_ResponseTypeR5b: /* Response 5 with busy */
             flags |= (kSDHC_ResponseLength48BusyFlag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag);
             break;
-        case kSDHC_ResponseTypeR6: /* Response 6 */
+        case kCARD_ResponseTypeR6: /* Response 6 */
             flags |= (kSDHC_ResponseLength48Flag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag);
             break;
-        case kSDHC_ResponseTypeR7: /* Response 7 */
+        case kCARD_ResponseTypeR7: /* Response 7 */
             flags |= (kSDHC_ResponseLength48Flag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag);
             break;
         default:
             break;
     }
-    if (command->type == kSDHC_CommandTypeAbort)
+    if (command->type == kCARD_CommandTypeAbort)
     {
         flags |= kSDHC_CommandTypeAbortFlag;
     }
@@ -341,7 +321,7 @@ static void SDHC_StartTransfer(SDHC_Type *base, sdhc_command_t *command, sdhc_da
     if (data)
     {
         flags |= kSDHC_DataPresentFlag;
-        dmaMode = (sdhc_dma_mode_t)((base->PROCTL & SDHC_PROCTL_DMAS_MASK) >> SDHC_PROCTL_DMAS_SHIFT);
+
         if (dmaMode != kSDHC_DmaModeNo)
         {
             flags |= kSDHC_EnableDmaFlag;
@@ -375,14 +355,14 @@ static void SDHC_StartTransfer(SDHC_Type *base, sdhc_command_t *command, sdhc_da
     SDHC_SetTransferConfig(base, &sdhcTransferConfig);
 }
 
-static void SDHC_ReceiveCommandResponse(SDHC_Type *base, sdhc_command_t *command)
+static status_t SDHC_ReceiveCommandResponse(SDHC_Type *base, sdhc_command_t *command)
 {
     uint32_t i;
 
-    if (command->responseType != kSDHC_ResponseTypeNone)
+    if (command->responseType != kCARD_ResponseTypeNone)
     {
         command->response[0U] = SDHC_GetCommandResponse(base, 0U);
-        if (command->responseType == kSDHC_ResponseTypeR2)
+        if (command->responseType == kCARD_ResponseTypeR2)
         {
             command->response[1U] = SDHC_GetCommandResponse(base, 1U);
             command->response[2U] = SDHC_GetCommandResponse(base, 2U);
@@ -401,6 +381,18 @@ static void SDHC_ReceiveCommandResponse(SDHC_Type *base, sdhc_command_t *command
             } while (i--);
         }
     }
+    /* check response error flag */
+    if ((command->responseErrorFlags != 0U) &&
+        ((command->responseType == kCARD_ResponseTypeR1) || (command->responseType == kCARD_ResponseTypeR1b) ||
+         (command->responseType == kCARD_ResponseTypeR6) || (command->responseType == kCARD_ResponseTypeR5)))
+    {
+        if (((command->responseErrorFlags) & (command->response[0U])) != 0U)
+        {
+            return kStatus_SDHC_SendCommandFailed;
+        }
+    }
+
+    return kStatus_Success;
 }
 
 static uint32_t SDHC_ReadDataPort(SDHC_Type *base, sdhc_data_t *data, uint32_t transferredWords)
@@ -411,10 +403,10 @@ static uint32_t SDHC_ReadDataPort(SDHC_Type *base, sdhc_data_t *data, uint32_t t
     uint32_t readWatermark = ((base->WML & SDHC_WML_RDWML_MASK) >> SDHC_WML_RDWML_SHIFT);
 
     /*
-     * Add non aligned access support ,user need make sure your buffer size is big
-     * enough to hold the data,in other words,user need make sure the buffer size
-     * is 4 byte aligned
-     */
+       * Add non aligned access support ,user need make sure your buffer size is big
+       * enough to hold the data,in other words,user need make sure the buffer size
+       * is 4 byte aligned
+       */
     if (data->blockSize % sizeof(uint32_t) != 0U)
     {
         data->blockSize +=
@@ -458,10 +450,10 @@ static status_t SDHC_ReadByDataPortBlocking(SDHC_Type *base, sdhc_data_t *data)
     status_t error = kStatus_Success;
 
     /*
-     * Add non aligned access support ,user need make sure your buffer size is big
-     * enough to hold the data,in other words,user need make sure the buffer size
-     * is 4 byte aligned
-     */
+       * Add non aligned access support ,user need make sure your buffer size is big
+       * enough to hold the data,in other words,user need make sure the buffer size
+       * is 4 byte aligned
+       */
     if (data->blockSize % sizeof(uint32_t) != 0U)
     {
         data->blockSize +=
@@ -487,13 +479,12 @@ static status_t SDHC_ReadByDataPortBlocking(SDHC_Type *base, sdhc_data_t *data)
         {
             transferredWords = SDHC_ReadDataPort(base, data, transferredWords);
         }
-
-        /* Clear buffer enable flag to trigger transfer. Clear data error flag when SDHC encounter error */
-        SDHC_ClearInterruptStatusFlags(base, (kSDHC_BufferReadReadyFlag | kSDHC_DataErrorFlag));
+        /* clear buffer ready and error */
+        SDHC_ClearInterruptStatusFlags(base, kSDHC_BufferReadReadyFlag | kSDHC_DataErrorFlag);
     }
 
     /* Clear data complete flag after the last read operation. */
-    SDHC_ClearInterruptStatusFlags(base, kSDHC_DataCompleteFlag);
+    SDHC_ClearInterruptStatusFlags(base, kSDHC_DataCompleteFlag | kSDHC_DataErrorFlag);
 
     return error;
 }
@@ -506,10 +497,10 @@ static uint32_t SDHC_WriteDataPort(SDHC_Type *base, sdhc_data_t *data, uint32_t
     uint32_t writeWatermark = ((base->WML & SDHC_WML_WRWML_MASK) >> SDHC_WML_WRWML_SHIFT);
 
     /*
-     * Add non aligned access support ,user need make sure your buffer size is big
-     * enough to hold the data,in other words,user need make sure the buffer size
-     * is 4 byte aligned
-     */
+       * Add non aligned access support ,user need make sure your buffer size is big
+       * enough to hold the data,in other words,user need make sure the buffer size
+       * is 4 byte aligned
+       */
     if (data->blockSize % sizeof(uint32_t) != 0U)
     {
         data->blockSize +=
@@ -553,10 +544,10 @@ static status_t SDHC_WriteByDataPortBlocking(SDHC_Type *base, sdhc_data_t *data)
     status_t error = kStatus_Success;
 
     /*
-     * Add non aligned access support ,user need make sure your buffer size is big
-     * enough to hold the data,in other words,user need make sure the buffer size
-     * is 4 byte aligned
-     */
+       * Add non aligned access support ,user need make sure your buffer size is big
+       * enough to hold the data,in other words,user need make sure the buffer size
+       * is 4 byte aligned
+       */
     if (data->blockSize % sizeof(uint32_t) != 0U)
     {
         data->blockSize +=
@@ -598,6 +589,7 @@ static status_t SDHC_WriteByDataPortBlocking(SDHC_Type *base, sdhc_data_t *data)
             error = kStatus_Fail;
         }
     }
+
     SDHC_ClearInterruptStatusFlags(base, (kSDHC_DataCompleteFlag | kSDHC_DataErrorFlag));
 
     return error;
@@ -619,7 +611,7 @@ static status_t SDHC_SendCommandBlocking(SDHC_Type *base, sdhc_command_t *comman
     /* Receive response when command completes successfully. */
     if (error == kStatus_Success)
     {
-        SDHC_ReceiveCommandResponse(base, command);
+        error = SDHC_ReceiveCommandResponse(base, command);
     }
 
     SDHC_ClearInterruptStatusFlags(base, (kSDHC_CommandCompleteFlag | kSDHC_CommandErrorFlag));
@@ -748,7 +740,11 @@ static void SDHC_TransferHandleData(SDHC_Type *base, sdhc_handle_t *handle, uint
         {
             handle->transferredWords = SDHC_WriteDataPort(base, handle->data, handle->transferredWords);
         }
-        else if ((interruptFlags & kSDHC_DataCompleteFlag) && (handle->callback.TransferComplete))
+        else
+        {
+        }
+
+        if ((interruptFlags & kSDHC_DataCompleteFlag) && (handle->callback.TransferComplete))
         {
             handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData);
         }
@@ -787,8 +783,10 @@ void SDHC_Init(SDHC_Type *base, const sdhc_config_t *config)
     uint32_t proctl;
     uint32_t wml;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable SDHC clock. */
     CLOCK_EnableClock(s_sdhcClock[SDHC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Reset SDHC. */
     SDHC_Reset(base, kSDHC_ResetAll, 100);
@@ -822,8 +820,10 @@ void SDHC_Init(SDHC_Type *base, const sdhc_config_t *config)
 
 void SDHC_Deinit(SDHC_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable clock. */
     CLOCK_DisableClock(s_sdhcClock[SDHC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 bool SDHC_Reset(SDHC_Type *base, uint32_t mask, uint32_t timeout)
@@ -877,44 +877,83 @@ uint32_t SDHC_SetSdClock(SDHC_Type *base, uint32_t srcClock_Hz, uint32_t busCloc
     assert(srcClock_Hz != 0U);
     assert((busClock_Hz != 0U) && (busClock_Hz <= srcClock_Hz));
 
-    uint32_t divisor;
-    uint32_t prescaler;
-    uint32_t sysctl;
-    uint32_t nearestFrequency = 0;
+    uint32_t totalDiv = 0U;
+    uint32_t divisor = 0U;
+    uint32_t prescaler = 0U;
+    uint32_t sysctl = 0U;
+    uint32_t nearestFrequency = 0U;
 
-    divisor = SDHC_INITIAL_DVS;
-    prescaler = SDHC_INITIAL_CLKFS;
-
-    /* Disable SD clock. It should be disabled before changing the SD clock frequency.*/
-    base->SYSCTL &= ~SDHC_SYSCTL_SDCLKEN_MASK;
+    /* calucate total divisor first */
+    totalDiv = srcClock_Hz / busClock_Hz;
 
-    if (busClock_Hz > 0U)
+    if (totalDiv != 0U)
     {
-        while ((srcClock_Hz / prescaler / SDHC_MAX_DVS > busClock_Hz) && (prescaler < SDHC_MAX_CLKFS))
+        /* calucate the divisor (srcClock_Hz / divisor) <= busClock_Hz */
+        if ((srcClock_Hz / totalDiv) > busClock_Hz)
         {
-            SDHC_NEXT_CLKFS(prescaler);
+            totalDiv++;
         }
-        while ((srcClock_Hz / prescaler / divisor > busClock_Hz) && (divisor < SDHC_MAX_DVS))
+
+        /* divide the total divisor to div and prescaler */
+        if (totalDiv > SDHC_MAX_DVS)
         {
-            SDHC_NEXT_DVS(divisor);
+            prescaler = totalDiv / SDHC_MAX_DVS;
+            /* prescaler must be a value which equal 2^n and smaller than SDHC_MAX_CLKFS */
+            while (((SDHC_MAX_CLKFS % prescaler) != 0U) || (prescaler == 1U))
+            {
+                prescaler++;
+            }
+            /* calucate the divisor */
+            divisor = totalDiv / prescaler;
+            /* fine tuning the divisor until divisor * prescaler >= totalDiv */
+            while ((divisor * prescaler) < totalDiv)
+            {
+                divisor++;
+            }
+            nearestFrequency = srcClock_Hz / divisor / prescaler;
         }
-        nearestFrequency = srcClock_Hz / prescaler / divisor;
-        SDHC_PREV_CLKFS(prescaler);
+        else
+        {
+            divisor = totalDiv;
+            prescaler = 0U;
+            nearestFrequency = srcClock_Hz / divisor;
+        }
+    }
+    /* in this condition , srcClock_Hz = busClock_Hz, */
+    else
+    {
+        /* total divider = 1U */
+        divisor = 0U;
+        prescaler = 0U;
+        nearestFrequency = srcClock_Hz;
+    }
+
+    /* calucate the value write to register */
+    if (divisor != 0U)
+    {
         SDHC_PREV_DVS(divisor);
+    }
+    /* calucate the value write to register */
+    if (prescaler != 0U)
+    {
+        SDHC_PREV_CLKFS(prescaler);
+    }
 
-        /* Set the SD clock frequency divisor, SD clock frequency select, data timeout counter value. */
-        sysctl = base->SYSCTL;
-        sysctl &= ~(SDHC_SYSCTL_DVS_MASK | SDHC_SYSCTL_SDCLKFS_MASK | SDHC_SYSCTL_DTOCV_MASK);
-        sysctl |= (SDHC_SYSCTL_DVS(divisor) | SDHC_SYSCTL_SDCLKFS(prescaler) | SDHC_SYSCTL_DTOCV(0xEU));
-        base->SYSCTL = sysctl;
+    /* Disable SD clock. It should be disabled before changing the SD clock frequency.*/
+    base->SYSCTL &= ~SDHC_SYSCTL_SDCLKEN_MASK;
 
-        /* Wait until the SD clock is stable. */
-        while (!(base->PRSSTAT & SDHC_PRSSTAT_SDSTB_MASK))
-        {
-        }
-        /* Enable the SD clock. */
-        base->SYSCTL |= SDHC_SYSCTL_SDCLKEN_MASK;
+    /* Set the SD clock frequency divisor, SD clock frequency select, data timeout counter value. */
+    sysctl = base->SYSCTL;
+    sysctl &= ~(SDHC_SYSCTL_DVS_MASK | SDHC_SYSCTL_SDCLKFS_MASK | SDHC_SYSCTL_DTOCV_MASK);
+    sysctl |= (SDHC_SYSCTL_DVS(divisor) | SDHC_SYSCTL_SDCLKFS(prescaler) | SDHC_SYSCTL_DTOCV(0xEU));
+    base->SYSCTL = sysctl;
+
+    /* Wait until the SD clock is stable. */
+    while (!(base->PRSSTAT & SDHC_PRSSTAT_SDSTB_MASK))
+    {
     }
+    /* Enable the SD clock. */
+    base->SYSCTL |= SDHC_SYSCTL_SDCLKEN_MASK;
 
     return nearestFrequency;
 }
@@ -1008,7 +1047,7 @@ void SDHC_SetMmcBootConfig(SDHC_Type *base, const sdhc_boot_config_t *config)
     uint32_t mmcboot = 0U;
 
     mmcboot = (SDHC_MMCBOOT_DTOCVACK(config->ackTimeoutCount) | SDHC_MMCBOOT_BOOTMODE(config->bootMode) |
-              SDHC_MMCBOOT_BOOTBLKCNT(config->blockCount));
+               SDHC_MMCBOOT_BOOTBLKCNT(config->blockCount));
     if (config->enableBootAck)
     {
         mmcboot |= SDHC_MMCBOOT_BOOTACK_MASK;
@@ -1032,7 +1071,7 @@ status_t SDHC_SetAdmaTableConfig(SDHC_Type *base,
                                  uint32_t dataBytes)
 {
     status_t error = kStatus_Success;
-    const uint32_t *startAddress;
+    const uint32_t *startAddress = data;
     uint32_t entries;
     uint32_t i;
 #if defined FSL_SDHC_ENABLE_ADMA1
@@ -1044,14 +1083,19 @@ status_t SDHC_SetAdmaTableConfig(SDHC_Type *base,
         (!data) || (!dataBytes)
 #if !defined FSL_SDHC_ENABLE_ADMA1
         || (dmaMode == kSDHC_DmaModeAdma1)
-#else
-        /* Buffer address configured in ADMA1 descriptor must be 4KB aligned. */
-        || ((dmaMode == kSDHC_DmaModeAdma1) && (((uint32_t)data % SDHC_ADMA1_LENGTH_ALIGN) != 0U))
-#endif /* FSL_SDHC_ENABLE_ADMA1 */
+#endif
             )
     {
         error = kStatus_InvalidArgument;
     }
+    else if (((dmaMode == kSDHC_DmaModeAdma2) && (((uint32_t)startAddress % SDHC_ADMA2_LENGTH_ALIGN) != 0U))
+#if defined FSL_SDHC_ENABLE_ADMA1
+             || ((dmaMode == kSDHC_DmaModeAdma1) && (((uint32_t)startAddress % SDHC_ADMA1_LENGTH_ALIGN) != 0U))
+#endif
+                 )
+    {
+        error = kStatus_SDHC_DMADataBufferAddrNotAlign;
+    }
     else
     {
         switch (dmaMode)
@@ -1071,7 +1115,6 @@ status_t SDHC_SetAdmaTableConfig(SDHC_Type *base,
                         sizeof(uint32_t) - (dataBytes % sizeof(uint32_t)); /* make the data length as word-aligned */
                 }
 
-                startAddress = data;
                 /* Check if ADMA descriptor's number is enough. */
                 entries = ((dataBytes / SDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U);
                 /* ADMA1 needs two descriptors to finish a transfer */
@@ -1113,22 +1156,24 @@ status_t SDHC_SetAdmaTableConfig(SDHC_Type *base,
                     /* When use ADMA, disable simple DMA */
                     base->DSADDR = 0U;
                     base->ADSADDR = (uint32_t)table;
+                    /* disable the buffer ready flag in DMA mode */
+                    SDHC_DisableInterruptSignal(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag);
+                    SDHC_DisableInterruptStatus(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag);
                 }
                 break;
 #endif /* FSL_SDHC_ENABLE_ADMA1 */
             case kSDHC_DmaModeAdma2:
                 /*
-                 * Add non aligned access support ,user need make sure your buffer size is big
-                 * enough to hold the data,in other words,user need make sure the buffer size
-                 * is 4 byte aligned
-                 */
+                * Add non aligned access support ,user need make sure your buffer size is big
+                * enough to hold the data,in other words,user need make sure the buffer size
+                * is 4 byte aligned
+                */
                 if (dataBytes % sizeof(uint32_t) != 0U)
                 {
                     dataBytes +=
                         sizeof(uint32_t) - (dataBytes % sizeof(uint32_t)); /* make the data length as word-aligned */
                 }
 
-                startAddress = data;
                 /* Check if ADMA descriptor's number is enough. */
                 entries = ((dataBytes / SDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U);
                 if (entries > ((tableWords * sizeof(uint32_t)) / sizeof(sdhc_adma2_descriptor_t)))
@@ -1165,6 +1210,9 @@ status_t SDHC_SetAdmaTableConfig(SDHC_Type *base,
                     /* When use ADMA, disable simple DMA */
                     base->DSADDR = 0U;
                     base->ADSADDR = (uint32_t)table;
+                    /* disable the buffer read flag in DMA mode */
+                    SDHC_DisableInterruptSignal(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag);
+                    SDHC_DisableInterruptStatus(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag);
                 }
                 break;
             default:
@@ -1187,44 +1235,53 @@ status_t SDHC_TransferBlocking(SDHC_Type *base, uint32_t *admaTable, uint32_t ad
     /* make sure the cmd/block count is valid */
     if ((!command) || (data && (data->blockCount > SDHC_MAX_BLOCK_COUNT)))
     {
-        error = kStatus_InvalidArgument;
+        return kStatus_InvalidArgument;
     }
-    else
+
+    /* Wait until command/data bus out of busy status. */
+    while (SDHC_GetPresentStatusFlags(base) & kSDHC_CommandInhibitFlag)
     {
-        /* Wait until command/data bus out of busy status. */
-        while (SDHC_GetPresentStatusFlags(base) & kSDHC_CommandInhibitFlag)
+    }
+    while (data && (SDHC_GetPresentStatusFlags(base) & kSDHC_DataInhibitFlag))
+    {
+    }
+
+    /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/
+    if (data && (NULL != admaTable))
+    {
+        error =
+            SDHC_SetAdmaTableConfig(base, dmaMode, admaTable, admaTableWords,
+                                    (data->rxData ? data->rxData : data->txData), (data->blockCount * data->blockSize));
+        /* in this situation , we disable the DMA instead of polling transfer mode */
+        if (error == kStatus_SDHC_DMADataBufferAddrNotAlign)
         {
+            dmaMode = kSDHC_DmaModeNo;
+            SDHC_EnableInterruptStatus(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag);
         }
-        while (data && (SDHC_GetPresentStatusFlags(base) & kSDHC_DataInhibitFlag))
+        else if (error != kStatus_Success)
         {
-        }
-
-        /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/
-        if (data && (kStatus_Success != SDHC_SetAdmaTableConfig(base, dmaMode, admaTable, admaTableWords,
-                                                                (data->rxData ? data->rxData : data->txData),
-                                                                (data->blockCount * data->blockSize))))
-        {
-            error = kStatus_SDHC_PrepareAdmaDescriptorFailed;
+            return error;
         }
         else
         {
-            /* Send command and receive data. */
-            SDHC_StartTransfer(base, command, data);
-            if (kStatus_Success != SDHC_SendCommandBlocking(base, command))
-            {
-                error = kStatus_SDHC_SendCommandFailed;
-            }
-            else if (data && (kStatus_Success != SDHC_TransferDataBlocking(dmaMode, base, data)))
-            {
-                error = kStatus_SDHC_TransferDataFailed;
-            }
-            else
-            {
-            }
         }
     }
 
-    return error;
+    /* Send command and receive data. */
+    SDHC_StartTransfer(base, command, data, dmaMode);
+    if (kStatus_Success != SDHC_SendCommandBlocking(base, command))
+    {
+        return kStatus_SDHC_SendCommandFailed;
+    }
+    else if (data && (kStatus_Success != SDHC_TransferDataBlocking(dmaMode, base, data)))
+    {
+        return kStatus_SDHC_TransferDataFailed;
+    }
+    else
+    {
+    }
+
+    return kStatus_Success;
 }
 
 void SDHC_TransferCreateHandle(SDHC_Type *base,
@@ -1271,40 +1328,49 @@ status_t SDHC_TransferNonBlocking(
     /* make sure cmd/block count is valid */
     if ((!command) || (data && (data->blockCount > SDHC_MAX_BLOCK_COUNT)))
     {
-        error = kStatus_InvalidArgument;
+        return kStatus_InvalidArgument;
     }
-    else
+
+    /* Wait until command/data bus out of busy status. */
+    if ((SDHC_GetPresentStatusFlags(base) & kSDHC_CommandInhibitFlag) ||
+        (data && (SDHC_GetPresentStatusFlags(base) & kSDHC_DataInhibitFlag)))
     {
-        /* Wait until command/data bus out of busy status. */
-        if ((SDHC_GetPresentStatusFlags(base) & kSDHC_CommandInhibitFlag) ||
-            (data && (SDHC_GetPresentStatusFlags(base) & kSDHC_DataInhibitFlag)))
+        return kStatus_SDHC_BusyTransferring;
+    }
+
+    /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/
+    if (data && (NULL != admaTable))
+    {
+        error =
+            SDHC_SetAdmaTableConfig(base, dmaMode, admaTable, admaTableWords,
+                                    (data->rxData ? data->rxData : data->txData), (data->blockCount * data->blockSize));
+        /* in this situation , we disable the DMA instead of polling transfer mode */
+        if (error == kStatus_SDHC_DMADataBufferAddrNotAlign)
         {
-            error = kStatus_SDHC_BusyTransferring;
+            /* change to polling mode */
+            dmaMode = kSDHC_DmaModeNo;
+            SDHC_EnableInterruptSignal(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag);
+            SDHC_EnableInterruptStatus(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag);
+        }
+        else if (error != kStatus_Success)
+        {
+            return error;
         }
         else
         {
-            /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/
-            if (data && (kStatus_Success != SDHC_SetAdmaTableConfig(base, dmaMode, admaTable, admaTableWords,
-                                                                    (data->rxData ? data->rxData : data->txData),
-                                                                    (data->blockCount * data->blockSize))))
-            {
-                error = kStatus_SDHC_PrepareAdmaDescriptorFailed;
-            }
-            else
-            {
-                /* Save command and data into handle before transferring. */
-                handle->command = command;
-                handle->data = data;
-                handle->interruptFlags = 0U;
-                /* transferredWords will only be updated in ISR when transfer way is DATAPORT. */
-                handle->transferredWords = 0U;
-
-                SDHC_StartTransfer(base, command, data);
-            }
         }
     }
 
-    return error;
+    /* Save command and data into handle before transferring. */
+    handle->command = command;
+    handle->data = data;
+    handle->interruptFlags = 0U;
+    /* transferredWords will only be updated in ISR when transfer way is DATAPORT. */
+    handle->transferredWords = 0U;
+
+    SDHC_StartTransfer(base, command, data, dmaMode);
+
+    return kStatus_Success;
 }
 
 void SDHC_TransferHandleIRQ(SDHC_Type *base, sdhc_handle_t *handle)
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdhc.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdhc.h
index 4976649d91a..336b9618e5b 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdhc.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdhc.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,14 +12,14 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
@@ -43,8 +43,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief Driver version 2.1.2. */
-#define FSL_SDHC_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 2U))
+/*! @brief Driver version 2.1.5. */
+#define FSL_SDHC_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 5U))
 /*@}*/
 
 /*! @brief Maximum block count can be set one time */
@@ -57,6 +57,8 @@ enum _sdhc_status
     kStatus_SDHC_PrepareAdmaDescriptorFailed = MAKE_STATUS(kStatusGroup_SDHC, 1U), /*!< Set DMA descriptor failed */
     kStatus_SDHC_SendCommandFailed = MAKE_STATUS(kStatusGroup_SDHC, 2U),           /*!< Send command failed */
     kStatus_SDHC_TransferDataFailed = MAKE_STATUS(kStatusGroup_SDHC, 3U),          /*!< Transfer data failed */
+    kStatus_SDHC_DMADataBufferAddrNotAlign =
+        MAKE_STATUS(kStatusGroup_SDHC, 4U), /*!< data buffer addr not align in DMA mode */
 };
 
 /*! @brief Host controller capabilities flag mask */
@@ -282,32 +284,32 @@ typedef enum _sdhc_boot_mode
 } sdhc_boot_mode_t;
 
 /*! @brief The command type */
-typedef enum _sdhc_command_type
+typedef enum _sdhc_card_command_type
 {
-    kSDHC_CommandTypeNormal = 0U,  /*!< Normal command */
-    kSDHC_CommandTypeSuspend = 1U, /*!< Suspend command */
-    kSDHC_CommandTypeResume = 2U,  /*!< Resume command */
-    kSDHC_CommandTypeAbort = 3U,   /*!< Abort command */
-} sdhc_command_type_t;
+    kCARD_CommandTypeNormal = 0U,  /*!< Normal command */
+    kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */
+    kCARD_CommandTypeResume = 2U,  /*!< Resume command */
+    kCARD_CommandTypeAbort = 3U,   /*!< Abort command */
+} sdhc_card_command_type_t;
 
 /*!
  * @brief The command response type.
  *
  * Define the command response type from card to host controller.
  */
-typedef enum _sdhc_response_type
+typedef enum _sdhc_card_response_type
 {
-    kSDHC_ResponseTypeNone = 0U, /*!< Response type: none */
-    kSDHC_ResponseTypeR1 = 1U,   /*!< Response type: R1 */
-    kSDHC_ResponseTypeR1b = 2U,  /*!< Response type: R1b */
-    kSDHC_ResponseTypeR2 = 3U,   /*!< Response type: R2 */
-    kSDHC_ResponseTypeR3 = 4U,   /*!< Response type: R3 */
-    kSDHC_ResponseTypeR4 = 5U,   /*!< Response type: R4 */
-    kSDHC_ResponseTypeR5 = 6U,   /*!< Response type: R5 */
-    kSDHC_ResponseTypeR5b = 7U,  /*!< Response type: R5b */
-    kSDHC_ResponseTypeR6 = 8U,   /*!< Response type: R6 */
-    kSDHC_ResponseTypeR7 = 9U,   /*!< Response type: R7 */
-} sdhc_response_type_t;
+    kCARD_ResponseTypeNone = 0U, /*!< Response type: none */
+    kCARD_ResponseTypeR1 = 1U,   /*!< Response type: R1 */
+    kCARD_ResponseTypeR1b = 2U,  /*!< Response type: R1b */
+    kCARD_ResponseTypeR2 = 3U,   /*!< Response type: R2 */
+    kCARD_ResponseTypeR3 = 4U,   /*!< Response type: R3 */
+    kCARD_ResponseTypeR4 = 5U,   /*!< Response type: R4 */
+    kCARD_ResponseTypeR5 = 6U,   /*!< Response type: R5 */
+    kCARD_ResponseTypeR5b = 7U,  /*!< Response type: R5b */
+    kCARD_ResponseTypeR6 = 8U,   /*!< Response type: R6 */
+    kCARD_ResponseTypeR7 = 9U,   /*!< Response type: R7 */
+} sdhc_card_response_type_t;
 
 /*! @brief The alignment size for ADDRESS filed in ADMA1's descriptor */
 #define SDHC_ADMA1_ADDRESS_ALIGN (4096U)
@@ -477,7 +479,8 @@ typedef struct _sdhc_config
  * @brief Card data descriptor
  *
  * Defines a structure to contain data-related attribute. 'enableIgnoreError' is used for the case that upper card
- * driver want to ignore the error event to read/write all the data not to stop read/write immediately when error event
+ * driver
+ * want to ignore the error event to read/write all the data not to stop read/write immediately when error event
  * happen for example bus testing procedure for MMC card.
  */
 typedef struct _sdhc_data
@@ -497,11 +500,13 @@ typedef struct _sdhc_data
  */
 typedef struct _sdhc_command
 {
-    uint32_t index;                    /*!< Command index */
-    uint32_t argument;                 /*!< Command argument */
-    sdhc_command_type_t type;          /*!< Command type */
-    sdhc_response_type_t responseType; /*!< Command response type */
-    uint32_t response[4U];             /*!< Response for this command */
+    uint32_t index;                         /*!< Command index */
+    uint32_t argument;                      /*!< Command argument */
+    sdhc_card_command_type_t type;          /*!< Command type */
+    sdhc_card_response_type_t responseType; /*!< Command response type */
+    uint32_t response[4U];                  /*!< Response for this command */
+    uint32_t responseErrorFlags;            /*!< response error flag, the flag which need to check
+                                                the command reponse*/
 } sdhc_command_t;
 
 /*! @brief Transfer state */
@@ -829,7 +834,8 @@ static inline void SDHC_SetDataBusWidth(SDHC_Type *base, sdhc_data_bus_width_t w
  * @brief Sets the card transfer-related configuration.
  *
  * This function fills the card transfer-related command argument/transfer flag/data size. The command and data are sent
- * by SDHC after calling this function.
+ by
+ * SDHC after calling this function.
  *
  * Example:
    @code
@@ -929,7 +935,8 @@ static inline void SDHC_EnableCardDetectTest(SDHC_Type *base, bool enable)
  *
  * This function sets the card detection test level to indicate whether the card is inserted into the SDHC when DAT[3]/
  * CD pin is selected as a card detection pin. This function can also assert the pin logic when DAT[3]/CD pin is
- * selected as the card detection pin.
+ * selected
+ * as the card detection pin.
  *
  * @param base SDHC peripheral base address.
  * @param high True to set the card detect level to high.
@@ -1007,7 +1014,10 @@ static inline void SDHC_SetForceEvent(SDHC_Type *base, uint32_t mask)
  * @brief Transfers the command/data using a blocking method.
  *
  * This function waits until the command response/data is received or the SDHC encounters an error by polling the status
- * flag. The application must not call this API in multiple threads at the same time. Because of that this API doesn't support
+ * flag.
+ * This function support non word align data addr transfer support, if data buffer addr is not align in DMA mode,
+ * the API will continue finish the transfer by polling IO directly
+ * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support
  * the re-entry mechanism.
  *
  * @note There is no need to call the API 'SDHC_TransferCreateHandle' when calling this API.
@@ -1044,7 +1054,10 @@ void SDHC_TransferCreateHandle(SDHC_Type *base,
  * @brief Transfers the command/data using an interrupt and an asynchronous method.
  *
  * This function sends a command and data and returns immediately. It doesn't wait the transfer complete or encounter an
- * error. The application must not call this API in multiple threads at the same time. Because of that this API doesn't support
+ * error.
+ * This function support non word align data addr transfer support, if data buffer addr is not align in DMA mode,
+ * the API will continue finish the transfer by polling IO directly
+ * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support
  * the re-entry mechanism.
  *
  * @note Call the API 'SDHC_TransferCreateHandle' when calling this API.
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdramc.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdramc.c
index ad672cfd604..baf432ed8b5 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdramc.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdramc.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,7 +37,6 @@
 /*! @brief Define macros for SDRAM driver. */
 #define SDRAMC_ONEMILLSEC_NANOSECONDS (1000000U)
 #define SDRAMC_ONESECOND_MILLISECONDS (1000U)
-#define SDRAMC_TIMEOUT_COUNT (0xFFFFU)
 
 /*******************************************************************************
  * Prototypes
@@ -53,8 +52,10 @@ static uint32_t SDRAMC_GetInstance(SDRAM_Type *base);
  * Variables
  ******************************************************************************/
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to SDRAMC clocks for each instance. */
-const clock_ip_name_t s_sdramClock[FSL_FEATURE_SOC_SDRAM_COUNT] = SDRAM_CLOCKS;
+static const clock_ip_name_t s_sdramClock[FSL_FEATURE_SOC_SDRAM_COUNT] = SDRAM_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*! @brief Pointers to SDRAMC bases for each instance. */
 static SDRAM_Type *const s_sdramcBases[] = SDRAM_BASE_PTRS;
@@ -67,7 +68,7 @@ static uint32_t SDRAMC_GetInstance(SDRAM_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_SDRAM_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_sdramcBases); instance++)
     {
         if (s_sdramcBases[instance] == base)
         {
@@ -75,7 +76,7 @@ static uint32_t SDRAMC_GetInstance(SDRAM_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_SDRAM_COUNT);
+    assert(instance < ARRAY_SIZE(s_sdramcBases));
 
     return instance;
 }
@@ -92,8 +93,10 @@ void SDRAMC_Init(SDRAM_Type *base, sdramc_config_t *configure)
     uint32_t count;
     uint32_t index;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Un-gate sdram controller clock. */
     CLOCK_EnableClock(s_sdramClock[SDRAMC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Initialize sdram Auto refresh timing. */
     count = refreshConfig->sdramRefreshRow * (refreshConfig->busClock_Hz / SDRAMC_ONESECOND_MILLISECONDS);
@@ -119,50 +122,23 @@ void SDRAMC_Deinit(SDRAM_Type *base)
     SDRAMC_EnableOperateValid(base, kSDRAMC_Block0, false);
     SDRAMC_EnableOperateValid(base, kSDRAMC_Block1, false);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable SDRAM clock. */
     CLOCK_DisableClock(s_sdramClock[SDRAMC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
-status_t SDRAMC_SendCommand(SDRAM_Type *base, sdramc_block_selection_t block, sdramc_command_t command)
+void SDRAMC_SendCommand(SDRAM_Type *base, sdramc_block_selection_t block, sdramc_command_t command)
 {
-    status_t result = kStatus_Success;
-    uint32_t count = SDRAMC_TIMEOUT_COUNT;
-
     switch (command)
     {
         /* Initiate mrs command. */
         case kSDRAMC_ImrsCommand:
             base->BLOCK[block].AC |= SDRAM_AC_IMRS_MASK;
-            while (count--)
-            {
-                if (!(base->BLOCK[block].AC & SDRAM_AC_IMRS_MASK))
-                {
-                    break;
-                }
-            }
-
-            if (!count)
-            {
-                /* Timeout the mrs command is unfinished. */
-                result = kStatus_Fail;
-            }
-            break;
+            break;            
         /* Initiate precharge command. */
         case kSDRAMC_PrechargeCommand:
             base->BLOCK[block].AC |= SDRAM_AC_IP_MASK;
-            while (count--)
-            {
-                if (!(base->BLOCK[block].AC & SDRAM_AC_IP_MASK))
-                {
-                    break;
-                }
-            }
-
-            /* Timeout the precharge command is unfinished. */
-            if (!count)
-            {
-                result = kStatus_Fail;
-            }
             break;
         /* Enable Auto refresh command. */
         case kSDRAMC_AutoRefreshEnableCommand:
@@ -183,5 +159,4 @@ status_t SDRAMC_SendCommand(SDRAM_Type *base, sdramc_block_selection_t block, sd
         default:
             break;
     }
-    return result;
 }
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdramc.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdramc.h
index 4da5ad756f8..c409fe456ee 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdramc.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sdramc.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,7 +37,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -45,8 +44,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief SDRAMC driver version 2.0.0. */
-#define FSL_SDRAMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief SDRAMC driver version 2.1.0. */
+#define FSL_SDRAMC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
 /*@}*/
 
 /*! @brief SDRAM controller auto-refresh timing. */
@@ -60,14 +59,14 @@ typedef enum _sdramc_refresh_time
 /*!
  * @brief Setting latency for SDRAM controller timing specifications.
  *
- * The latency setting will affects the following SDRAM timing specifications:
+ * The latency setting affects the following SDRAM timing specifications:
  *       - trcd: SRAS assertion to SCAS assertion \n
  *       - tcasl: SCAS assertion to data out \n
  *       - tras: ACTV command to Precharge command \n
  *       - trp: Precharge command to ACTV command \n
  *       - trwl, trdl: Last data input to Precharge command \n
  *       - tep: Last data out to Precharge command \n
- * the details of the latency setting and timing specifications are shown on the following table list: \n
+ * The details of the latency setting and timing specifications are shown in the following table list. \n
  *   latency      trcd:          tcasl         tras           trp        trwl,trdl        tep   \n
  *    0       1 bus clock    1 bus clock   2 bus clocks   1 bus clock   1 bus clock   1 bus clock  \n
  *    1       2 bus clock    2 bus clock   4 bus clocks   2 bus clock   1 bus clock   1 bus clock  \n
@@ -219,10 +218,10 @@ void SDRAMC_Deinit(SDRAM_Type *base);
 
 /*!
  * @brief Sends the SDRAM command.
- * This function sends the command to SDRAM. There are precharge command, initialize MRS command,
+ * This function sends commands to SDRAM. The commands are precharge command, initialization MRS command,
  * auto-refresh enable/disable command, and self-refresh enter/exit commands.
- * Note the self-refresh enter/exit commands are all blocks setting and "block"
- * are ignored. Ensure to set the right "block" when send other commands.
+ * Note that the self-refresh enter/exit commands are all blocks setting and "block"
+ * is ignored. Ensure to set the correct "block" when send other commands.
  *
  * @param base SDRAM controller peripheral base address.
  * @param block The block selection.
@@ -233,13 +232,8 @@ void SDRAMC_Deinit(SDRAM_Type *base);
  *        kSDRAMC_SelfrefreshExitCommand  -  Exit self-refresh command \n
  *        kSDRAMC_AutoRefreshEnableCommand  - Enable auto refresh command \n
  *        kSDRAMC_AutoRefreshDisableCommand  - Disable auto refresh command
- * @return Command execution status.
- * All commands except the "initialize MRS command" and "precharge command"
- * return kStatus_Success directly.
- * For "initialize MRS command" and "precharge command"
- * return kStatus_Success when the command success else return kStatus_Fail.
  */
-status_t SDRAMC_SendCommand(SDRAM_Type *base, sdramc_block_selection_t block, sdramc_command_t command);
+void SDRAMC_SendCommand(SDRAM_Type *base, sdramc_block_selection_t block, sdramc_command_t command);
 
 /*!
  * @brief Enables/disables the write protection.
@@ -261,11 +255,11 @@ static inline void SDRAMC_EnableWriteProtect(SDRAM_Type *base, sdramc_block_sele
 }
 
 /*!
- * @brief Enables/disables the operation valid.
+ * @brief Enables/disables the valid operation.
  *
  * @param base SDRAM peripheral base address.
  * @param block The block which is selected.
- * @param enable True enable the operation valid, false disable the operation valid.
+ * @param enable True enable the valid operation; false disable the valid operation.
  */
 static inline void SDRAMC_EnableOperateValid(SDRAM_Type *base, sdramc_block_selection_t block, bool enable)
 {
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sim.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sim.c
index 3a4b801b7b3..ade512f0306 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sim.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sim.c
@@ -1,32 +1,32 @@
 /*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-*   of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-*   list of conditions and the following disclaimer in the documentation and/or
-*   other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-*   contributors may be used to endorse or promote products derived from this
-*   software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #include "fsl_sim.h"
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sim.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sim.h
index a3b69188841..0a0e4fb3092 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sim.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sim.h
@@ -1,32 +1,32 @@
 /*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-*   of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-*   list of conditions and the following disclaimer in the documentation and/or
-*   other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-*   contributors may be used to endorse or promote products derived from this
-*   software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _FSL_SIM_H_
 #define _FSL_SIM_H_
@@ -36,7 +36,6 @@
 /*! @addtogroup sim */
 /*! @{*/
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -90,10 +89,10 @@ extern "C" {
  * @brief Sets the USB voltage regulator setting.
  *
  * This function configures whether the USB voltage regulator is enabled in
- * normal RUN mode, STOP/VLPS/LLS/VLLS modes and VLPR/VLPW modes. The configurations
- * are passed in as mask value of \ref _sim_usb_volt_reg_enable_mode. For example, enable
+ * normal RUN mode, STOP/VLPS/LLS/VLLS modes, and VLPR/VLPW modes. The configurations
+ * are passed in as mask value of \ref _sim_usb_volt_reg_enable_mode. For example, to enable
  * USB voltage regulator in RUN/VLPR/VLPW modes and disable in STOP/VLPS/LLS/VLLS mode,
- * please use:
+ * use:
  *
  * SIM_SetUsbVoltRegulatorEnableMode(kSIM_UsbVoltRegEnable | kSIM_UsbVoltRegEnableInLowPower);
  *
@@ -103,16 +102,16 @@ void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask);
 #endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */
 
 /*!
- * @brief Get the unique identification register value.
+ * @brief Gets the unique identification register value.
  *
  * @param uid Pointer to the structure to save the UID value.
  */
 void SIM_GetUniqueId(sim_uid_t *uid);
 
 /*!
- * @brief Set the flash enable mode.
+ * @brief Sets the flash enable mode.
  *
- * @param mode The mode to set, see \ref _sim_flash_mode for mode details.
+ * @param mode The mode to set; see \ref _sim_flash_mode for mode details.
  */
 static inline void SIM_SetFlashMode(uint8_t mode)
 {
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_smc.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_smc.c
index 0018cf7dce2..dacf193476c 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_smc.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_smc.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -29,6 +29,7 @@
  */
 
 #include "fsl_smc.h"
+#include "fsl_flash.h"
 
 #if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM)
 void SMC_GetParam(SMC_Type *base, smc_param_t *param)
@@ -41,6 +42,39 @@ void SMC_GetParam(SMC_Type *base, smc_param_t *param)
 }
 #endif /* FSL_FEATURE_SMC_HAS_PARAM */
 
+void SMC_PreEnterStopModes(void)
+{
+    flash_prefetch_speculation_status_t speculationStatus =
+    {
+        kFLASH_prefetchSpeculationOptionDisable, /* Disable instruction speculation.*/
+        kFLASH_prefetchSpeculationOptionDisable, /* Disable data speculation.*/
+    };
+
+    __disable_irq();
+    __ISB();
+
+    /*
+     * Before enter stop modes, the flash cache prefetch should be disabled.
+     * Otherwise the prefetch might be interrupted by stop, then the data and
+     * and instruction from flash are wrong.
+     */
+    FLASH_PflashSetPrefetchSpeculation(&speculationStatus);
+}
+
+void SMC_PostExitStopModes(void)
+{
+    flash_prefetch_speculation_status_t speculationStatus =
+    {
+        kFLASH_prefetchSpeculationOptionEnable, /* Enable instruction speculation.*/
+        kFLASH_prefetchSpeculationOptionEnable, /* Enable data speculation.*/
+    };
+
+    FLASH_PflashSetPrefetchSpeculation(&speculationStatus);
+
+    __enable_irq();
+    __ISB();
+}
+
 status_t SMC_SetPowerModeRun(SMC_Type *base)
 {
     uint8_t reg;
@@ -73,7 +107,9 @@ status_t SMC_SetPowerModeWait(SMC_Type *base)
 {
     /* configure Normal Wait mode */
     SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+    __DSB();
     __WFI();
+    __ISB();
 
     return kStatus_Success;
 }
@@ -101,7 +137,9 @@ status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option)
 
     /* read back to make sure the configuration valid before enter stop mode */
     (void)base->PMCTRL;
+    __DSB();
     __WFI();
+    __ISB();
 
     /* check whether the power mode enter Stop mode succeed */
     if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
@@ -148,16 +186,12 @@ status_t SMC_SetPowerModeVlpr(SMC_Type *base
 
 status_t SMC_SetPowerModeVlpw(SMC_Type *base)
 {
-    /* Power mode transaction to VLPW can only happen in VLPR mode */
-    if (kSMC_PowerStateVlpr != SMC_GetPowerModeState(base))
-    {
-        return kStatus_Fail;
-    }
-
     /* configure VLPW mode */
     /* Set the SLEEPDEEP bit to enable deep sleep mode */
     SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+    __DSB();
     __WFI();
+    __ISB();
 
     return kStatus_Success;
 }
@@ -177,7 +211,9 @@ status_t SMC_SetPowerModeVlps(SMC_Type *base)
 
     /* read back to make sure the configuration valid before enter stop mode */
     (void)base->PMCTRL;
+    __DSB();
     __WFI();
+    __ISB();
 
     /* check whether the power mode enter VLPS mode succeed */
     if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
@@ -231,7 +267,9 @@ status_t SMC_SetPowerModeLls(SMC_Type *base
 
     /* read back to make sure the configuration valid before enter stop mode */
     (void)base->PMCTRL;
+    __DSB();
     __WFI();
+    __ISB();
 
     /* check whether the power mode enter LLS mode succeed */
     if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
@@ -345,7 +383,9 @@ status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t
 
     /* read back to make sure the configuration valid before enter stop mode */
     (void)base->PMCTRL;
+    __DSB();
     __WFI();
+    __ISB();
 
     /* check whether the power mode enter LLS mode succeed */
     if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_smc.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_smc.h
index 5149f87e346..168ce835013 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_smc.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_smc.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -36,7 +36,6 @@
 /*! @addtogroup smc */
 /*! @{ */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -44,8 +43,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief SMC driver version 2.0.1. */
-#define FSL_SMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*! @brief SMC driver version 2.0.3. */
+#define FSL_SMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
 /*@}*/
 
 /*!
@@ -54,14 +53,14 @@
 typedef enum _smc_power_mode_protection
 {
 #if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
-    kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK, /*!< Allow Very-Low-Leakage Stop Mode. */
+    kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK, /*!< Allow Very-low-leakage Stop Mode. */
 #endif
 #if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
-    kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK, /*!< Allow Low-Leakage Stop Mode.      */
+    kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK, /*!< Allow Low-leakage Stop Mode.      */
 #endif                                             /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
-    kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK, /*!< Allow Very-Low-Power Mode.        */
+    kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK, /*!< Allow Very-Low-power Mode.        */
 #if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
-    kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High Speed Run mode.        */
+    kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High-speed Run mode.        */
 #endif                                                 /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
     kSMC_AllowPowerModeAll = (0U
 #if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
@@ -107,10 +106,10 @@ typedef enum _smc_power_state
  */
 typedef enum _smc_run_mode
 {
-    kSMC_RunNormal = 0U, /*!< normal RUN mode.             */
-    kSMC_RunVlpr = 2U,   /*!< Very-Low-Power RUN mode.     */
+    kSMC_RunNormal = 0U, /*!< Normal RUN mode.             */
+    kSMC_RunVlpr = 2U,   /*!< Very-low-power RUN mode.     */
 #if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
-    kSMC_Hsrun = 3U /*!< High Speed Run mode (HSRUN). */
+    kSMC_Hsrun = 3U /*!< High-speed Run mode (HSRUN). */
 #endif              /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
 } smc_run_mode_t;
 
@@ -120,12 +119,12 @@ typedef enum _smc_run_mode
 typedef enum _smc_stop_mode
 {
     kSMC_StopNormal = 0U, /*!< Normal STOP mode.           */
-    kSMC_StopVlps = 2U,   /*!< Very-Low-Power STOP mode.   */
+    kSMC_StopVlps = 2U,   /*!< Very-low-power STOP mode.   */
 #if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE)
-    kSMC_StopLls = 3U, /*!< Low-Leakage Stop mode.      */
+    kSMC_StopLls = 3U, /*!< Low-leakage Stop mode.      */
 #endif                 /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */
 #if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
-    kSMC_StopVlls = 4U /*!< Very-Low-Leakage Stop mode. */
+    kSMC_StopVlls = 4U /*!< Very-low-leakage Stop mode. */
 #endif
 } smc_stop_mode_t;
 
@@ -155,7 +154,7 @@ typedef enum _smc_partial_stop_mode
 } smc_partial_stop_option_t;
 
 /*!
- * @brief SMC configuration status
+ * @brief SMC configuration status.
  */
 enum _smc_status
 {
@@ -190,7 +189,7 @@ typedef struct _smc_param
 #if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \
     (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)
 /*!
- * @brief SMC Low-Leakage Stop power mode config
+ * @brief SMC Low-Leakage Stop power mode configuration.
  */
 typedef struct _smc_power_mode_lls_config
 {
@@ -205,7 +204,7 @@ typedef struct _smc_power_mode_lls_config
 
 #if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
 /*!
- * @brief SMC Very Low-Leakage Stop power mode config
+ * @brief SMC Very Low-Leakage Stop power mode configuration.
  */
 typedef struct _smc_power_mode_vlls_config
 {
@@ -242,10 +241,10 @@ extern "C" {
  * @brief Gets the SMC version ID.
  *
  * This function gets the SMC version ID, including major version number,
- * minor version number and feature specification number.
+ * minor version number, and feature specification number.
  *
  * @param base SMC peripheral base address.
- * @param versionId     Pointer to version ID structure.
+ * @param versionId     Pointer to the version ID structure.
  */
 static inline void SMC_GetVersionId(SMC_Type *base, smc_version_id_t *versionId)
 {
@@ -257,10 +256,10 @@ static inline void SMC_GetVersionId(SMC_Type *base, smc_version_id_t *versionId)
 /*!
  * @brief Gets the SMC parameter.
  *
- * This function gets the SMC parameter, including the enabled power mdoes.
+ * This function gets the SMC parameter including the enabled power mdoes.
  *
  * @param base SMC peripheral base address.
- * @param param         Pointer to SMC param structure.
+ * @param param         Pointer to the SMC param structure.
  */
 void SMC_GetParam(SMC_Type *base, smc_param_t *param);
 #endif
@@ -274,7 +273,7 @@ void SMC_GetParam(SMC_Type *base, smc_param_t *param);
  * system level initialization stage. See the reference manual for details.
  * This register can only write once after the power reset.
  *
- * The allowed modes are passed as bit map, for example, to allow LLS and VLLS,
+ * The allowed modes are passed as bit map. For example, to allow LLS and VLLS,
  * use SMC_SetPowerModeProtection(kSMC_AllowPowerModeVlls | kSMC_AllowPowerModeVlps).
  * To allow all modes, use SMC_SetPowerModeProtection(kSMC_AllowPowerModeAll).
  *
@@ -289,13 +288,13 @@ static inline void SMC_SetPowerModeProtection(SMC_Type *base, uint8_t allowedMod
 /*!
  * @brief Gets the current power mode status.
  *
- * This function  returns the current power mode stat. Once application
- * switches the power mode, it should always check the stat to check whether it
- * runs into the specified mode or not. An application  should  check
+ * This function  returns the current power mode status. After the application
+ * switches the power mode, it should always check the status to check whether it
+ * runs into the specified mode or not. The application  should  check
  * this mode before switching to a different mode. The system  requires that
  * only certain modes can switch to other specific modes. See the
  * reference manual for details and the smc_power_state_t for information about
- * the power stat.
+ * the power status.
  *
  * @param base SMC peripheral base address.
  * @return Current power mode status.
@@ -306,7 +305,45 @@ static inline smc_power_state_t SMC_GetPowerModeState(SMC_Type *base)
 }
 
 /*!
- * @brief Configure the system to RUN power mode.
+ * @brief Prepares to enter stop modes.
+ *
+ * This function should be called before entering STOP/VLPS/LLS/VLLS modes.
+ */
+void SMC_PreEnterStopModes(void);
+
+/*!
+ * @brief Recovers after wake up from stop modes.
+ *
+ * This function should be called after wake up from STOP/VLPS/LLS/VLLS modes.
+ * It is used with @ref SMC_PreEnterStopModes.
+ */
+void SMC_PostExitStopModes(void);
+
+/*!
+ * @brief Prepares to enter wait modes.
+ *
+ * This function should be called before entering WAIT/VLPW modes.
+ */
+static inline void SMC_PreEnterWaitModes(void)
+{
+    __disable_irq();
+    __ISB();
+}
+
+/*!
+ * @brief Recovers after wake up from stop modes.
+ *
+ * This function should be called after wake up from WAIT/VLPW modes.
+ * It is used with @ref SMC_PreEnterWaitModes.
+ */
+static inline void SMC_PostExitWaitModes(void)
+{
+    __enable_irq();
+    __ISB();
+}
+
+/*!
+ * @brief Configures the system to RUN power mode.
  *
  * @param base SMC peripheral base address.
  * @return SMC configuration error code.
@@ -315,7 +352,7 @@ status_t SMC_SetPowerModeRun(SMC_Type *base);
 
 #if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE)
 /*!
- * @brief Configure the system to HSRUN power mode.
+ * @brief Configures the system to HSRUN power mode.
  *
  * @param base SMC peripheral base address.
  * @return SMC configuration error code.
@@ -324,7 +361,7 @@ status_t SMC_SetPowerModeHsrun(SMC_Type *base);
 #endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */
 
 /*!
- * @brief Configure the system to WAIT power mode.
+ * @brief Configures the system to WAIT power mode.
  *
  * @param base SMC peripheral base address.
  * @return SMC configuration error code.
@@ -332,7 +369,7 @@ status_t SMC_SetPowerModeHsrun(SMC_Type *base);
 status_t SMC_SetPowerModeWait(SMC_Type *base);
 
 /*!
- * @brief Configure the system to Stop power mode.
+ * @brief Configures the system to Stop power mode.
  *
  * @param base SMC peripheral base address.
  * @param  option Partial Stop mode option.
@@ -342,7 +379,7 @@ status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option);
 
 #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
 /*!
- * @brief Configure the system to VLPR power mode.
+ * @brief Configures the system to VLPR power mode.
  *
  * @param base SMC peripheral base address.
  * @param  wakeupMode Enter Normal Run mode if true, else stay in VLPR mode.
@@ -351,7 +388,7 @@ status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option);
 status_t SMC_SetPowerModeVlpr(SMC_Type *base, bool wakeupMode);
 #else
 /*!
- * @brief Configure the system to VLPR power mode.
+ * @brief Configures the system to VLPR power mode.
  *
  * @param base SMC peripheral base address.
  * @return SMC configuration error code.
@@ -360,7 +397,7 @@ status_t SMC_SetPowerModeVlpr(SMC_Type *base);
 #endif /* FSL_FEATURE_SMC_HAS_LPWUI */
 
 /*!
- * @brief Configure the system to VLPW power mode.
+ * @brief Configures the system to VLPW power mode.
  *
  * @param base SMC peripheral base address.
  * @return SMC configuration error code.
@@ -368,7 +405,7 @@ status_t SMC_SetPowerModeVlpr(SMC_Type *base);
 status_t SMC_SetPowerModeVlpw(SMC_Type *base);
 
 /*!
- * @brief Configure the system to VLPS power mode.
+ * @brief Configures the system to VLPS power mode.
  *
  * @param base SMC peripheral base address.
  * @return SMC configuration error code.
@@ -379,7 +416,7 @@ status_t SMC_SetPowerModeVlps(SMC_Type *base);
 #if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \
      (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO))
 /*!
- * @brief Configure the system to LLS power mode.
+ * @brief Configures the system to LLS power mode.
  *
  * @param base SMC peripheral base address.
  * @param  config The LLS power mode configuration structure
@@ -388,7 +425,7 @@ status_t SMC_SetPowerModeVlps(SMC_Type *base);
 status_t SMC_SetPowerModeLls(SMC_Type *base, const smc_power_mode_lls_config_t *config);
 #else
 /*!
- * @brief Configure the system to LLS power mode.
+ * @brief Configures the system to LLS power mode.
  *
  * @param base SMC peripheral base address.
  * @return SMC configuration error code.
@@ -399,7 +436,7 @@ status_t SMC_SetPowerModeLls(SMC_Type *base);
 
 #if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE)
 /*!
- * @brief Configure the system to VLLS power mode.
+ * @brief Configures the system to VLLS power mode.
  *
  * @param base SMC peripheral base address.
  * @param  config The VLLS power mode configuration structure.
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sysmpu.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sysmpu.c
new file mode 100755
index 00000000000..b89a7b20e4e
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sysmpu.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_sysmpu.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+const clock_ip_name_t g_sysmpuClock[FSL_FEATURE_SOC_SYSMPU_COUNT] = SYSMPU_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+
+void SYSMPU_Init(SYSMPU_Type *base, const sysmpu_config_t *config)
+{
+    assert(config);
+    uint8_t count;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Un-gate SYSMPU clock */
+    CLOCK_EnableClock(g_sysmpuClock[0]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Initializes the regions. */
+    for (count = 1; count < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT; count++)
+    {
+        base->WORD[count][3] = 0; /* VLD/VID+PID. */
+        base->WORD[count][0] = 0; /* Start address. */
+        base->WORD[count][1] = 0; /* End address. */
+        base->WORD[count][2] = 0; /* Access rights. */
+        base->RGDAAC[count] = 0;  /* Alternate access rights. */
+    }
+
+    /* SYSMPU configure. */
+    while (config)
+    {
+        SYSMPU_SetRegionConfig(base, &(config->regionConfig));
+        config = config->next;
+    }
+    /* Enable SYSMPU. */
+    SYSMPU_Enable(base, true);
+}
+
+void SYSMPU_Deinit(SYSMPU_Type *base)
+{
+    /* Disable SYSMPU. */
+    SYSMPU_Enable(base, false);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Gate the clock. */
+    CLOCK_DisableClock(g_sysmpuClock[0]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+void SYSMPU_GetHardwareInfo(SYSMPU_Type *base, sysmpu_hardware_info_t *hardwareInform)
+{
+    assert(hardwareInform);
+
+    uint32_t cesReg = base->CESR;
+
+    hardwareInform->hardwareRevisionLevel = (cesReg & SYSMPU_CESR_HRL_MASK) >> SYSMPU_CESR_HRL_SHIFT;
+    hardwareInform->slavePortsNumbers = (cesReg & SYSMPU_CESR_NSP_MASK) >> SYSMPU_CESR_NSP_SHIFT;
+    hardwareInform->regionsNumbers = (sysmpu_region_total_num_t)((cesReg & SYSMPU_CESR_NRGD_MASK) >> SYSMPU_CESR_NRGD_SHIFT);
+}
+
+void SYSMPU_SetRegionConfig(SYSMPU_Type *base, const sysmpu_region_config_t *regionConfig)
+{
+    assert(regionConfig);
+    assert(regionConfig->regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT);
+
+    uint32_t wordReg = 0;
+    uint8_t msPortNum;
+    uint8_t regNumber = regionConfig->regionNum;
+
+    /* The start and end address of the region descriptor. */
+    base->WORD[regNumber][0] = regionConfig->startAddress;
+    base->WORD[regNumber][1] = regionConfig->endAddress;
+
+    /* Set the privilege rights for master 0 ~ master 3. */
+    for (msPortNum = 0; msPortNum < SYSMPU_MASTER_RWATTRIBUTE_START_PORT; msPortNum++)
+    {
+        wordReg |= SYSMPU_REGION_RWXRIGHTS_MASTER(
+            msPortNum, (((uint32_t)regionConfig->accessRights1[msPortNum].superAccessRights << 3U) |
+                        (uint32_t)regionConfig->accessRights1[msPortNum].userAccessRights));
+
+#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
+        wordReg |=
+            SYSMPU_REGION_RWXRIGHTS_MASTER_PE(msPortNum, regionConfig->accessRights1[msPortNum].processIdentifierEnable);
+#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
+    }
+
+#if FSL_FEATURE_SYSMPU_MASTER_COUNT > SYSMPU_MASTER_RWATTRIBUTE_START_PORT
+    /* Set the normal read write rights for master 4 ~ master 7. */
+    for (msPortNum = SYSMPU_MASTER_RWATTRIBUTE_START_PORT; msPortNum < FSL_FEATURE_SYSMPU_MASTER_COUNT;
+         msPortNum++)
+    {
+        wordReg |= SYSMPU_REGION_RWRIGHTS_MASTER(msPortNum,
+            ((uint32_t)regionConfig->accessRights2[msPortNum - SYSMPU_MASTER_RWATTRIBUTE_START_PORT].readEnable << 1U |
+            (uint32_t)regionConfig->accessRights2[msPortNum - SYSMPU_MASTER_RWATTRIBUTE_START_PORT].writeEnable));
+    }
+#endif /* FSL_FEATURE_SYSMPU_MASTER_COUNT > SYSMPU_MASTER_RWATTRIBUTE_START_PORT */
+
+    /* Set region descriptor access rights. */
+    base->WORD[regNumber][2] = wordReg;
+
+    wordReg = SYSMPU_WORD_VLD(1);
+#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
+    wordReg |= SYSMPU_WORD_PID(regionConfig->processIdentifier) | SYSMPU_WORD_PIDMASK(regionConfig->processIdMask);
+#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
+
+    base->WORD[regNumber][3] = wordReg;
+}
+
+void SYSMPU_SetRegionAddr(SYSMPU_Type *base, uint32_t regionNum, uint32_t startAddr, uint32_t endAddr)
+{
+    assert(regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT);
+
+    base->WORD[regionNum][0] = startAddr;
+    base->WORD[regionNum][1] = endAddr;
+}
+
+void SYSMPU_SetRegionRwxMasterAccessRights(SYSMPU_Type *base,
+                                        uint32_t regionNum,
+                                        uint32_t masterNum,
+                                        const sysmpu_rwxrights_master_access_control_t *accessRights)
+{
+    assert(accessRights);
+    assert(regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT);
+    assert(masterNum < SYSMPU_MASTER_RWATTRIBUTE_START_PORT);
+
+    uint32_t mask = SYSMPU_REGION_RWXRIGHTS_MASTER_MASK(masterNum);
+    uint32_t right = base->RGDAAC[regionNum];
+
+#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
+    mask |= SYSMPU_REGION_RWXRIGHTS_MASTER_PE_MASK(masterNum);
+#endif
+
+    /* Build rights control value. */
+    right &= ~mask;
+    right |= SYSMPU_REGION_RWXRIGHTS_MASTER(
+        masterNum, ((uint32_t)(accessRights->superAccessRights << 3U) | accessRights->userAccessRights));
+#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
+    right |= SYSMPU_REGION_RWXRIGHTS_MASTER_PE(masterNum, accessRights->processIdentifierEnable);
+#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
+
+    /* Set low master region access rights. */
+    base->RGDAAC[regionNum] = right;
+}
+
+#if FSL_FEATURE_SYSMPU_MASTER_COUNT > 4
+void SYSMPU_SetRegionRwMasterAccessRights(SYSMPU_Type *base,
+                                       uint32_t regionNum,
+                                       uint32_t masterNum,
+                                       const sysmpu_rwrights_master_access_control_t *accessRights)
+{
+    assert(accessRights);
+    assert(regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT);
+    assert(masterNum >= SYSMPU_MASTER_RWATTRIBUTE_START_PORT);
+    assert(masterNum <= (FSL_FEATURE_SYSMPU_MASTER_COUNT - 1));
+
+    uint32_t mask = SYSMPU_REGION_RWRIGHTS_MASTER_MASK(masterNum);
+    uint32_t right = base->RGDAAC[regionNum];
+
+    /* Build rights control value. */
+    right &= ~mask;
+    right |=
+        SYSMPU_REGION_RWRIGHTS_MASTER(masterNum, (((uint32_t)accessRights->readEnable << 1U) | accessRights->writeEnable));
+    /* Set low master region access rights. */
+    base->RGDAAC[regionNum] = right;
+}
+#endif /* FSL_FEATURE_SYSMPU_MASTER_COUNT > 4 */
+
+bool SYSMPU_GetSlavePortErrorStatus(SYSMPU_Type *base, sysmpu_slave_t slaveNum)
+{
+    uint8_t sperr;
+
+    sperr = ((base->CESR & SYSMPU_CESR_SPERR_MASK) >> SYSMPU_CESR_SPERR_SHIFT) & (0x1U << (FSL_FEATURE_SYSMPU_SLAVE_COUNT - slaveNum - 1));
+
+    return (sperr != 0) ? true : false;
+}
+
+void SYSMPU_GetDetailErrorAccessInfo(SYSMPU_Type *base, sysmpu_slave_t slaveNum, sysmpu_access_err_info_t *errInform)
+{
+    assert(errInform);
+
+    uint16_t value;
+    uint32_t cesReg;
+
+    /* Error address. */
+    errInform->address = base->SP[slaveNum].EAR;
+
+    /* Error detail information. */
+    value = (base->SP[slaveNum].EDR & SYSMPU_EDR_EACD_MASK) >> SYSMPU_EDR_EACD_SHIFT;
+    if (!value)
+    {
+        errInform->accessControl = kSYSMPU_NoRegionHit;
+    }
+    else if (!(value & (uint16_t)(value - 1)))
+    {
+        errInform->accessControl = kSYSMPU_NoneOverlappRegion;
+    }
+    else
+    {
+        errInform->accessControl = kSYSMPU_OverlappRegion;
+    }
+
+    value = base->SP[slaveNum].EDR;
+    errInform->master = (uint32_t)((value & SYSMPU_EDR_EMN_MASK) >> SYSMPU_EDR_EMN_SHIFT);
+    errInform->attributes = (sysmpu_err_attributes_t)((value & SYSMPU_EDR_EATTR_MASK) >> SYSMPU_EDR_EATTR_SHIFT);
+    errInform->accessType = (sysmpu_err_access_type_t)((value & SYSMPU_EDR_ERW_MASK) >> SYSMPU_EDR_ERW_SHIFT);
+#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
+    errInform->processorIdentification = (uint8_t)((value & SYSMPU_EDR_EPID_MASK) >> SYSMPU_EDR_EPID_SHIFT);
+#endif
+
+    /* Clears error slave port bit. */
+    cesReg = (base->CESR & ~SYSMPU_CESR_SPERR_MASK) | ((0x1U << (FSL_FEATURE_SYSMPU_SLAVE_COUNT - slaveNum - 1)) << SYSMPU_CESR_SPERR_SHIFT);
+    base->CESR = cesReg;
+}
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sysmpu.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sysmpu.h
new file mode 100755
index 00000000000..6341a31e9d1
--- /dev/null
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sysmpu.h
@@ -0,0 +1,435 @@
+/*
+ * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_SYSMPU_H_
+#define _FSL_SYSMPU_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup sysmpu
+ * @{
+ */
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief SYSMPU driver version 2.2.0. */
+#define FSL_SYSMPU_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
+/*@}*/
+
+/*! @brief define the start master port with read and write attributes. */
+#define SYSMPU_MASTER_RWATTRIBUTE_START_PORT (4)
+
+/*! @brief SYSMPU the bit shift for masters with privilege rights: read write and execute. */
+#define SYSMPU_REGION_RWXRIGHTS_MASTER_SHIFT(n) (n * 6)
+
+/*! @brief SYSMPU masters with read, write and execute rights bit mask. */
+#define SYSMPU_REGION_RWXRIGHTS_MASTER_MASK(n) (0x1Fu << SYSMPU_REGION_RWXRIGHTS_MASTER_SHIFT(n))
+
+/*! @brief SYSMPU masters with read, write and execute rights bit width. */
+#define SYSMPU_REGION_RWXRIGHTS_MASTER_WIDTH 5
+
+/*! @brief SYSMPU masters with read, write and execute rights priority setting. */
+#define SYSMPU_REGION_RWXRIGHTS_MASTER(n, x) \
+    (((uint32_t)(((uint32_t)(x)) << SYSMPU_REGION_RWXRIGHTS_MASTER_SHIFT(n))) & SYSMPU_REGION_RWXRIGHTS_MASTER_MASK(n))
+
+/*! @brief SYSMPU masters with read, write and execute rights process enable bit shift. */
+#define SYSMPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n) (n * 6 + SYSMPU_REGION_RWXRIGHTS_MASTER_WIDTH)
+
+/*! @brief SYSMPU masters with read, write and execute rights process enable bit mask. */
+#define SYSMPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n) (0x1u << SYSMPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n))
+
+/*! @brief SYSMPU masters with read, write and execute rights process enable setting. */
+#define SYSMPU_REGION_RWXRIGHTS_MASTER_PE(n, x) \
+    (((uint32_t)(((uint32_t)(x)) << SYSMPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n))) & SYSMPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n))
+
+/*! @brief SYSMPU masters with normal read write permission bit shift. */
+#define SYSMPU_REGION_RWRIGHTS_MASTER_SHIFT(n) ((n - SYSMPU_MASTER_RWATTRIBUTE_START_PORT) * 2 + 24)
+
+/*! @brief SYSMPU masters with normal read write rights bit mask. */
+#define SYSMPU_REGION_RWRIGHTS_MASTER_MASK(n) (0x3u << SYSMPU_REGION_RWRIGHTS_MASTER_SHIFT(n))
+
+/*! @brief SYSMPU masters with normal read write rights priority setting. */
+#define SYSMPU_REGION_RWRIGHTS_MASTER(n, x) \
+    (((uint32_t)(((uint32_t)(x)) << SYSMPU_REGION_RWRIGHTS_MASTER_SHIFT(n))) & SYSMPU_REGION_RWRIGHTS_MASTER_MASK(n))
+
+
+/*! @brief Describes the number of SYSMPU regions. */
+typedef enum _sysmpu_region_total_num
+{
+    kSYSMPU_8Regions = 0x0U,  /*!< SYSMPU supports 8 regions.  */
+    kSYSMPU_12Regions = 0x1U, /*!< SYSMPU supports 12 regions. */
+    kSYSMPU_16Regions = 0x2U  /*!< SYSMPU supports 16 regions. */
+} sysmpu_region_total_num_t;
+
+/*! @brief SYSMPU slave port number. */
+typedef enum _sysmpu_slave
+{
+    kSYSMPU_Slave0 = 0U, /*!< SYSMPU slave port 0. */
+    kSYSMPU_Slave1 = 1U, /*!< SYSMPU slave port 1. */
+    kSYSMPU_Slave2 = 2U, /*!< SYSMPU slave port 2. */
+    kSYSMPU_Slave3 = 3U, /*!< SYSMPU slave port 3. */
+    kSYSMPU_Slave4 = 4U, /*!< SYSMPU slave port 4. */
+#if FSL_FEATURE_SYSMPU_SLAVE_COUNT > 5
+    kSYSMPU_Slave5 = 5U, /*!< SYSMPU slave port 5. */
+#endif
+#if FSL_FEATURE_SYSMPU_SLAVE_COUNT > 6
+    kSYSMPU_Slave6 = 6U, /*!< SYSMPU slave port 6. */
+#endif
+#if FSL_FEATURE_SYSMPU_SLAVE_COUNT > 7
+    kSYSMPU_Slave7 = 7U, /*!< SYSMPU slave port 7. */
+#endif
+} sysmpu_slave_t;
+
+/*! @brief SYSMPU error access control detail. */
+typedef enum _sysmpu_err_access_control
+{
+    kSYSMPU_NoRegionHit = 0U,        /*!< No region hit error. */
+    kSYSMPU_NoneOverlappRegion = 1U, /*!< Access single region error. */
+    kSYSMPU_OverlappRegion = 2U      /*!< Access overlapping region error. */
+} sysmpu_err_access_control_t;
+
+/*! @brief SYSMPU error access type. */
+typedef enum _sysmpu_err_access_type
+{
+    kSYSMPU_ErrTypeRead = 0U, /*!< SYSMPU error access type --- read.  */
+    kSYSMPU_ErrTypeWrite = 1U /*!< SYSMPU error access type --- write. */
+} sysmpu_err_access_type_t;
+
+/*! @brief SYSMPU access error attributes.*/
+typedef enum _sysmpu_err_attributes
+{
+    kSYSMPU_InstructionAccessInUserMode = 0U,       /*!< Access instruction error in user mode. */
+    kSYSMPU_DataAccessInUserMode = 1U,              /*!< Access data error in user mode. */
+    kSYSMPU_InstructionAccessInSupervisorMode = 2U, /*!< Access instruction error in supervisor mode. */
+    kSYSMPU_DataAccessInSupervisorMode = 3U         /*!< Access data error in supervisor mode. */
+} sysmpu_err_attributes_t;
+
+/*! @brief SYSMPU access rights in supervisor mode for bus master 0 ~ 3. */
+typedef enum _sysmpu_supervisor_access_rights
+{
+    kSYSMPU_SupervisorReadWriteExecute = 0U, /*!< Read write and execute operations are allowed in supervisor mode. */
+    kSYSMPU_SupervisorReadExecute = 1U,      /*!< Read and execute operations are allowed in supervisor mode. */
+    kSYSMPU_SupervisorReadWrite = 2U,        /*!< Read write operations are allowed in supervisor mode. */
+    kSYSMPU_SupervisorEqualToUsermode = 3U   /*!< Access permission equal to user mode. */
+} sysmpu_supervisor_access_rights_t;
+
+/*! @brief SYSMPU access rights in user mode for bus master 0 ~ 3. */
+typedef enum _sysmpu_user_access_rights
+{
+    kSYSMPU_UserNoAccessRights = 0U,  /*!< No access allowed in user mode.  */
+    kSYSMPU_UserExecute = 1U,         /*!< Execute operation is allowed in user mode. */
+    kSYSMPU_UserWrite = 2U,           /*!< Write operation is allowed in user mode. */
+    kSYSMPU_UserWriteExecute = 3U,    /*!< Write and execute operations are allowed in user mode. */
+    kSYSMPU_UserRead = 4U,            /*!< Read is allowed in user mode. */
+    kSYSMPU_UserReadExecute = 5U,     /*!< Read and execute operations are allowed in user mode. */
+    kSYSMPU_UserReadWrite = 6U,       /*!< Read and write operations are allowed in user mode. */
+    kSYSMPU_UserReadWriteExecute = 7U /*!< Read write and execute operations are allowed in user mode. */
+} sysmpu_user_access_rights_t;
+
+/*! @brief SYSMPU hardware basic information. */
+typedef struct _sysmpu_hardware_info
+{
+    uint8_t hardwareRevisionLevel;         /*!< Specifies the SYSMPU's hardware and definition reversion level. */
+    uint8_t slavePortsNumbers;             /*!< Specifies the number of slave ports connected to SYSMPU. */
+    sysmpu_region_total_num_t regionsNumbers; /*!< Indicates the number of region descriptors implemented. */
+} sysmpu_hardware_info_t;
+
+/*! @brief SYSMPU detail error access information. */
+typedef struct _sysmpu_access_err_info
+{
+    uint32_t master;                        /*!< Access error master. */
+    sysmpu_err_attributes_t attributes;        /*!< Access error attributes. */
+    sysmpu_err_access_type_t accessType;       /*!< Access error type. */
+    sysmpu_err_access_control_t accessControl; /*!< Access error control. */
+    uint32_t address;                       /*!< Access error address. */
+#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
+    uint8_t processorIdentification; /*!< Access error processor identification. */
+#endif                               /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
+} sysmpu_access_err_info_t;
+
+/*! @brief SYSMPU read/write/execute rights control for bus master 0 ~ 3. */
+typedef struct _sysmpu_rwxrights_master_access_control
+{
+    sysmpu_supervisor_access_rights_t superAccessRights; /*!< Master access rights in supervisor mode. */
+    sysmpu_user_access_rights_t userAccessRights;        /*!< Master access rights in user mode. */
+#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
+    bool processIdentifierEnable; /*!< Enables or disables process identifier. */
+#endif                            /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
+} sysmpu_rwxrights_master_access_control_t;
+
+/*! @brief SYSMPU read/write access control for bus master 4 ~ 7. */
+typedef struct _sysmpu_rwrights_master_access_control
+{
+    bool writeEnable; /*!< Enables or disables write permission. */
+    bool readEnable;  /*!< Enables or disables read permission.  */
+} sysmpu_rwrights_master_access_control_t;
+
+/*!
+ * @brief SYSMPU region configuration structure.
+ *
+ * This structure is used to configure the regionNum region.
+ * The accessRights1[0] ~ accessRights1[3] are used to configure the bus master
+ * 0 ~ 3 with the privilege rights setting. The accessRights2[0] ~ accessRights2[3]
+ * are used to configure the high master 4 ~ 7 with the normal read write permission.
+ * The master port assignment is the chip configuration. Normally, the core is the
+ * master 0, debugger is the master 1.
+ * Note that the SYSMPU assigns a priority scheme where the debugger is treated as the highest
+ * priority master followed by the core and then all the remaining masters.
+ * SYSMPU protection does not allow writes from the core to affect the "regionNum 0" start
+ * and end address nor the permissions associated with the debugger. It can only write
+ * the permission fields associated with the other masters. This protection guarantees that
+ * the debugger always has access to the entire address space and those rights can't
+ * be changed by the core or any other bus master. Prepare
+ * the region configuration when regionNum is 0.
+ */
+typedef struct _sysmpu_region_config
+{
+    uint32_t regionNum;    /*!< SYSMPU region number, range form 0 ~ FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT - 1. */
+    uint32_t startAddress; /*!< Memory region start address. Note: bit0 ~ bit4 always be marked as 0 by SYSMPU. The actual
+                              start address is 0-modulo-32 byte address.  */
+    uint32_t endAddress; /*!< Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by SYSMPU. The actual end
+                          address is 31-modulo-32 byte address. */
+    sysmpu_rwxrights_master_access_control_t accessRights1[4]; /*!< Masters with read, write and execute rights setting. */
+    sysmpu_rwrights_master_access_control_t accessRights2[4];  /*!< Masters with normal read write rights setting. */
+#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
+    uint8_t processIdentifier; /*!< Process identifier used when "processIdentifierEnable" set with true. */
+    uint8_t
+        processIdMask; /*!< Process identifier mask. The setting bit will ignore the same bit in process identifier. */
+#endif                 /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
+} sysmpu_region_config_t;
+
+/*!
+ * @brief The configuration structure for the SYSMPU initialization.
+ *
+ * This structure is used when calling the SYSMPU_Init function.
+ */
+typedef struct _sysmpu_config
+{
+    sysmpu_region_config_t regionConfig; /*!< Region access permission. */
+    struct _sysmpu_config *next;         /*!< Pointer to the next structure. */
+} sysmpu_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the SYSMPU with the user configuration structure.
+ *
+ * This function configures the SYSMPU module with the user-defined configuration.
+ *
+ * @param base     SYSMPU peripheral base address.
+ * @param config   The pointer to the configuration structure.
+ */
+void SYSMPU_Init(SYSMPU_Type *base, const sysmpu_config_t *config);
+
+/*!
+ * @brief Deinitializes the SYSMPU regions.
+ *
+ * @param base     SYSMPU peripheral base address.
+ */
+void SYSMPU_Deinit(SYSMPU_Type *base);
+
+/* @}*/
+
+/*!
+ * @name Basic Control Operations
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the SYSMPU globally.
+ *
+ * Call this API to enable or disable the SYSMPU module.
+ *
+ * @param base     SYSMPU peripheral base address.
+ * @param enable   True enable SYSMPU, false disable SYSMPU.
+ */
+static inline void SYSMPU_Enable(SYSMPU_Type *base, bool enable)
+{
+    if (enable)
+    {
+        /* Enable the SYSMPU globally. */
+        base->CESR |= SYSMPU_CESR_VLD_MASK;
+    }
+    else
+    { /* Disable the SYSMPU globally. */
+        base->CESR &= ~SYSMPU_CESR_VLD_MASK;
+    }
+}
+
+/*!
+ * @brief Enables/disables the SYSMPU for a special region.
+ *
+ * When SYSMPU is enabled, call this API to disable an unused region
+ * of an enabled SYSMPU. Call this API to minimize the power dissipation.
+ *
+ * @param base     SYSMPU peripheral base address.
+ * @param number   SYSMPU region number.
+ * @param enable   True enable the special region SYSMPU, false disable the special region SYSMPU.
+ */
+static inline void SYSMPU_RegionEnable(SYSMPU_Type *base, uint32_t number, bool enable)
+{
+    if (enable)
+    {
+        /* Enable the #number region SYSMPU. */
+        base->WORD[number][3] |= SYSMPU_WORD_VLD_MASK;
+    }
+    else
+    { /* Disable the #number region SYSMPU. */
+        base->WORD[number][3] &= ~SYSMPU_WORD_VLD_MASK;
+    }
+}
+
+/*!
+ * @brief Gets the SYSMPU basic hardware information.
+ *
+ * @param base           SYSMPU peripheral base address.
+ * @param hardwareInform The pointer to the SYSMPU hardware information structure. See "sysmpu_hardware_info_t".
+ */
+void SYSMPU_GetHardwareInfo(SYSMPU_Type *base, sysmpu_hardware_info_t *hardwareInform);
+
+/*!
+ * @brief Sets the SYSMPU region.
+ *
+ * Note: Due to the SYSMPU protection, the region number 0 does not allow writes from
+ * core to affect the start and end address nor the permissions associated with
+ * the debugger. It can only write the permission fields associated
+ * with the other masters.
+ *
+ * @param base          SYSMPU peripheral base address.
+ * @param regionConfig  The pointer to the SYSMPU user configuration structure. See "sysmpu_region_config_t".
+ */
+void SYSMPU_SetRegionConfig(SYSMPU_Type *base, const sysmpu_region_config_t *regionConfig);
+
+/*!
+ * @brief Sets the region start and end address.
+ *
+ * Memory region start address. Note: bit0 ~ bit4 is always marked as 0 by SYSMPU.
+ * The actual start address by SYSMPU is 0-modulo-32 byte address.
+ * Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by SYSMPU.
+ * The end address used by the SYSMPU is 31-modulo-32 byte address.
+ * Note: Due to the SYSMPU protection, the startAddr and endAddr can't be
+ * changed by the core when regionNum is 0.
+ *
+ * @param base          SYSMPU peripheral base address.
+ * @param regionNum     SYSMPU region number. The range is from 0 to
+ * FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT - 1.
+ * @param startAddr     Region start address.
+ * @param endAddr       Region end address.
+ */
+void SYSMPU_SetRegionAddr(SYSMPU_Type *base, uint32_t regionNum, uint32_t startAddr, uint32_t endAddr);
+
+/*!
+ * @brief Sets the SYSMPU region access rights for masters with read, write, and execute rights.
+ * The SYSMPU access rights depend on two board classifications of bus masters.
+ * The privilege rights masters and the normal rights masters.
+ * The privilege rights masters have the read, write, and execute access rights.
+ * Except the normal read and write rights, the execute rights are also
+ * allowed for these masters. The privilege rights masters normally range from
+ * bus masters 0 - 3. However, the maximum master number is device-specific.
+ * See the "SYSMPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX".
+ * The normal rights masters access rights control see
+ * "SYSMPU_SetRegionRwMasterAccessRights()".
+ *
+ * @param base          SYSMPU peripheral base address.
+ * @param regionNum     SYSMPU region number. Should range from 0 to
+ * FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT - 1.
+ * @param masterNum     SYSMPU bus master number. Should range from 0 to
+ * SYSMPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX.
+ * @param accessRights  The pointer to the SYSMPU access rights configuration. See "sysmpu_rwxrights_master_access_control_t".
+ */
+void SYSMPU_SetRegionRwxMasterAccessRights(SYSMPU_Type *base,
+                                        uint32_t regionNum,
+                                        uint32_t masterNum,
+                                        const sysmpu_rwxrights_master_access_control_t *accessRights);
+#if FSL_FEATURE_SYSMPU_MASTER_COUNT > 4
+/*!
+ * @brief Sets the SYSMPU region access rights for masters with read and write rights.
+ * The SYSMPU access rights depend on two board classifications of bus masters.
+ * The privilege rights masters and the normal rights masters.
+ * The normal rights masters only have the read and write access permissions.
+ * The privilege rights access control see "SYSMPU_SetRegionRwxMasterAccessRights".
+ *
+ * @param base          SYSMPU peripheral base address.
+ * @param regionNum     SYSMPU region number. The range is from 0 to
+ * FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT - 1.
+ * @param masterNum     SYSMPU bus master number. Should range from SYSMPU_MASTER_RWATTRIBUTE_START_PORT
+ * to ~ FSL_FEATURE_SYSMPU_MASTER_COUNT - 1.
+ * @param accessRights  The pointer to the SYSMPU access rights configuration. See "sysmpu_rwrights_master_access_control_t".
+ */
+void SYSMPU_SetRegionRwMasterAccessRights(SYSMPU_Type *base,
+                                       uint32_t regionNum,
+                                       uint32_t masterNum,
+                                       const sysmpu_rwrights_master_access_control_t *accessRights);
+#endif  /* FSL_FEATURE_SYSMPU_MASTER_COUNT > 4 */
+/*!
+ * @brief Gets the numbers of slave ports where errors occur.
+ *
+ * @param base       SYSMPU peripheral base address.
+ * @param slaveNum   SYSMPU slave port number.
+ * @return The slave ports error status.
+ *         true  - error happens in this slave port.
+ *         false - error didn't happen in this slave port.
+ */
+bool SYSMPU_GetSlavePortErrorStatus(SYSMPU_Type *base, sysmpu_slave_t slaveNum);
+
+/*!
+ * @brief Gets the SYSMPU detailed error access information.
+ *
+ * @param base       SYSMPU peripheral base address.
+ * @param slaveNum   SYSMPU slave port number.
+ * @param errInform  The pointer to the SYSMPU access error information. See "sysmpu_access_err_info_t".
+ */
+void SYSMPU_GetDetailErrorAccessInfo(SYSMPU_Type *base, sysmpu_slave_t slaveNum, sysmpu_access_err_info_t *errInform);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_SYSMPU_H_ */
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tpm.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tpm.c
index 079c06df586..9a390a2be47 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tpm.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tpm.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -53,8 +53,10 @@ static uint32_t TPM_GetInstance(TPM_Type *base);
 /*! @brief Pointers to TPM bases for each instance. */
 static TPM_Type *const s_tpmBases[] = TPM_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to TPM clocks for each instance. */
 static const clock_ip_name_t s_tpmClocks[] = TPM_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
@@ -82,8 +84,10 @@ void TPM_Init(TPM_Type *base, const tpm_config_t *config)
 {
     assert(config);
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the module clock */
     CLOCK_EnableClock(s_tpmClocks[TPM_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 #if defined(FSL_FEATURE_TPM_HAS_GLOBAL) && FSL_FEATURE_TPM_HAS_GLOBAL
     /* TPM reset is available on certain SoC's */
@@ -118,8 +122,10 @@ void TPM_Deinit(TPM_Type *base)
 {
     /* Stop the counter */
     base->SC &= ~TPM_SC_CMOD_MASK;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Gate the TPM clock */
     CLOCK_DisableClock(s_tpmClocks[TPM_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void TPM_GetDefaultConfig(tpm_config_t *config)
@@ -162,6 +168,12 @@ status_t TPM_SetupPwm(TPM_Type *base,
     assert(pwmFreq_Hz);
     assert(numOfChnls);
     assert(srcClock_Hz);
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+    if(mode == kTPM_CombinedPwm)
+    {
+        assert(FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base));
+    }
+#endif
 
     uint32_t mod;
     uint32_t tpmClock = (srcClock_Hz / (1U << (base->SC & TPM_SC_PS_MASK)));
@@ -169,8 +181,12 @@ status_t TPM_SetupPwm(TPM_Type *base,
     uint8_t i;
 
 #if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
-    /* Clear quadrature Decoder mode because in quadrature Decoder mode PWM doesn't operate*/
-    base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+    /* The TPM's QDCTRL register required to be effective */
+    if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) )
+    {
+        /* Clear quadrature Decoder mode because in quadrature Decoder mode PWM doesn't operate*/
+        base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+    }
 #endif
 
     switch (mode)
@@ -351,6 +367,12 @@ void TPM_UpdatePwmDutycycle(TPM_Type *base,
                             uint8_t dutyCyclePercent)
 {
     assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base));
+#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
+    if(currentPwmMode == kTPM_CombinedPwm)
+    {
+        assert(FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base));
+    }
+#endif
 
     uint16_t cnv, mod;
 
@@ -401,7 +423,7 @@ void TPM_UpdateChnlEdgeLevelSelect(TPM_Type *base, tpm_chnl_t chnlNumber, uint8_
 
     /* Wait till mode change to disable channel is acknowledged */
     while ((base->CONTROLS[chnlNumber].CnSC &
-                  (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+            (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
     {
     }
 
@@ -424,16 +446,24 @@ void TPM_SetupInputCapture(TPM_Type *base, tpm_chnl_t chnlNumber, tpm_input_capt
     assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base));
 
 #if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
-    /* Clear quadrature Decoder mode for channel 0 or 1*/
-    if ((chnlNumber == 0) || (chnlNumber == 1))
+    /* The TPM's QDCTRL register required to be effective */
+    if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) )
     {
-        base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+        /* Clear quadrature Decoder mode for channel 0 or 1*/
+        if ((chnlNumber == 0) || (chnlNumber == 1))
+        {
+            base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+        }
     }
 #endif
 
 #if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
-    /* Clear the combine bit for chnlNumber */
-    base->COMBINE &= ~(1U << TPM_COMBINE_SHIFT * (chnlNumber / 2));
+        /* The TPM's COMBINE register required to be effective */
+    if( FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base) )
+    {
+        /* Clear the combine bit for chnlNumber */
+        base->COMBINE &= ~(1U << TPM_COMBINE_SHIFT * (chnlNumber / 2));
+    }
 #endif
 
     /* When switching mode, disable channel first  */
@@ -464,10 +494,14 @@ void TPM_SetupOutputCompare(TPM_Type *base,
     assert(chnlNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base));
 
 #if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
-    /* Clear quadrature Decoder mode for channel 0 or 1 */
-    if ((chnlNumber == 0) || (chnlNumber == 1))
+    /* The TPM's QDCTRL register required to be effective */
+    if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) )
     {
-        base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+        /* Clear quadrature Decoder mode for channel 0 or 1 */
+        if ((chnlNumber == 0) || (chnlNumber == 1))
+        {
+            base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+        }
     }
 #endif
 
@@ -502,13 +536,19 @@ void TPM_SetupDualEdgeCapture(TPM_Type *base,
 {
     assert(edgeParam);
     assert(chnlPairNumber < FSL_FEATURE_TPM_CHANNEL_COUNTn(base) / 2);
+    assert(FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base));
 
     uint32_t reg;
-/* Clear quadrature Decoder mode for channel 0 or 1*/
+
 #if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
-    if (chnlPairNumber == 0)
+    /* The TPM's QDCTRL register required to be effective */
+    if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) )
     {
-        base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+        /* Clear quadrature Decoder mode for channel 0 or 1*/
+        if (chnlPairNumber == 0)
+        {
+            base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
+        }
     }
 #endif
 
@@ -518,7 +558,7 @@ void TPM_SetupDualEdgeCapture(TPM_Type *base,
 
     /* Wait till mode change to disable channel is acknowledged */
     while ((base->CONTROLS[chnlPairNumber * 2].CnSC &
-                  (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+            (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
     {
     }
 
@@ -527,7 +567,7 @@ void TPM_SetupDualEdgeCapture(TPM_Type *base,
 
     /* Wait till mode change to disable channel is acknowledged */
     while ((base->CONTROLS[chnlPairNumber * 2 + 1].CnSC &
-                  (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
+            (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)))
     {
     }
 
@@ -589,6 +629,7 @@ void TPM_SetupQuadDecode(TPM_Type *base,
 {
     assert(phaseAParams);
     assert(phaseBParams);
+    assert(FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base));
 
     base->CONTROLS[0].CnSC &= ~(TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK);
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tpm.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tpm.h
index a15e44c1fbf..a1694b37d32 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tpm.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tpm.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,8 +37,6 @@
  * @{
  */
 
-/*! @file */
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
@@ -525,6 +523,47 @@ static inline void TPM_ClearStatusFlags(TPM_Type *base, uint32_t mask)
 
 /*! @}*/
 
+/*!
+ * @name Read and write the timer period
+ * @{
+ */
+
+/*!
+ * @brief Sets the timer period in units of ticks.
+ *
+ * Timers counts from 0 until it equals the count value set here. The count value is written to
+ * the MOD register.
+ *
+ * @note
+ * 1. This API allows the user to use the TPM module as a timer. Do not mix usage
+ *    of this API with TPM's PWM setup API's.
+ * 2. Call the utility macros provided in the fsl_common.h to convert usec or msec to ticks.
+ *
+ * @param base TPM peripheral base address
+ * @param ticks A timer period in units of ticks, which should be equal or greater than 1.
+ */
+static inline void TPM_SetTimerPeriod(TPM_Type *base, uint32_t ticks)
+{
+    base->MOD = ticks;
+}
+
+/*!
+ * @brief Reads the current timer counting value.
+ *
+ * This function returns the real-time timer counting value in a range from 0 to a
+ * timer period.
+ *
+ * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.
+ *
+ * @param base TPM peripheral base address
+ *
+ * @return The current counter value in ticks
+ */
+static inline uint32_t TPM_GetCurrentTimerCount(TPM_Type *base)
+{
+    return (uint32_t)((base->CNT & TPM_CNT_COUNT_MASK) >> TPM_CNT_COUNT_SHIFT);
+}
+
 /*!
  * @name Timer Start and Stop
  * @{
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tsi_v4.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tsi_v4.c
index 6acb64e7e0b..c299c90f633 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tsi_v4.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tsi_v4.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -36,7 +36,9 @@ void TSI_Init(TSI_Type *base, const tsi_config_t *config)
     bool is_module_enabled = false;
     bool is_int_enabled = false;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_EnableClock(kCLOCK_Tsi0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
     if (base->GENCS & TSI_GENCS_TSIEN_MASK)
     {
         is_module_enabled = true;
@@ -47,18 +49,31 @@ void TSI_Init(TSI_Type *base, const tsi_config_t *config)
         is_int_enabled = true;
         TSI_DisableInterrupts(base, kTSI_GlobalInterruptEnable);
     }
-
-    TSI_SetHighThreshold(base, config->thresh);
-    TSI_SetLowThreshold(base, config->thresl);
-    TSI_SetElectrodeOSCPrescaler(base, config->prescaler);
-    TSI_SetReferenceChargeCurrent(base, config->refchrg);
-    TSI_SetElectrodeChargeCurrent(base, config->extchrg);
-    TSI_SetNumberOfScans(base, config->nscn);
-    TSI_SetAnalogMode(base, config->mode);
-    TSI_SetOscVoltageRails(base, config->dvolt);
-    TSI_SetElectrodeSeriesResistor(base, config->resistor);
-    TSI_SetFilterBits(base, config->filter);
-
+    
+    if(config->mode == kTSI_AnalogModeSel_Capacitive)
+    {
+      TSI_SetHighThreshold(base, config->thresh);
+      TSI_SetLowThreshold(base, config->thresl);
+      TSI_SetElectrodeOSCPrescaler(base, config->prescaler);
+      TSI_SetReferenceChargeCurrent(base, config->refchrg);
+      TSI_SetElectrodeChargeCurrent(base, config->extchrg);
+      TSI_SetNumberOfScans(base, config->nscn);
+      TSI_SetAnalogMode(base, config->mode);
+      TSI_SetOscVoltageRails(base, config->dvolt);   
+    }
+    else /* For noise modes */
+    {  
+      TSI_SetHighThreshold(base, config->thresh);
+      TSI_SetLowThreshold(base, config->thresl);
+      TSI_SetElectrodeOSCPrescaler(base, config->prescaler);
+      TSI_SetReferenceChargeCurrent(base, config->refchrg);
+      TSI_SetNumberOfScans(base, config->nscn);
+      TSI_SetAnalogMode(base, config->mode);
+      TSI_SetOscVoltageRails(base, config->dvolt);
+      TSI_SetElectrodeSeriesResistor(base, config->resistor);
+      TSI_SetFilterBits(base, config->filter);  
+    }
+     
     if (is_module_enabled)
     {
         TSI_EnableModule(base, true);
@@ -74,7 +89,9 @@ void TSI_Deinit(TSI_Type *base)
     base->GENCS = 0U;
     base->DATA = 0U;
     base->TSHD = 0U;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     CLOCK_DisableClock(kCLOCK_Tsi0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void TSI_GetNormalModeDefaultConfig(tsi_config_t *userConfig)
@@ -82,13 +99,11 @@ void TSI_GetNormalModeDefaultConfig(tsi_config_t *userConfig)
     userConfig->thresh = 0U;
     userConfig->thresl = 0U;
     userConfig->prescaler = kTSI_ElecOscPrescaler_2div;
-    userConfig->extchrg = kTSI_ExtOscChargeCurrent_4uA;
+    userConfig->extchrg = kTSI_ExtOscChargeCurrent_500nA;
     userConfig->refchrg = kTSI_RefOscChargeCurrent_4uA;
     userConfig->nscn = kTSI_ConsecutiveScansNumber_5time;
     userConfig->mode = kTSI_AnalogModeSel_Capacitive;
     userConfig->dvolt = kTSI_OscVolRailsOption_0;
-    userConfig->resistor = kTSI_SeriesResistance_32k;
-    userConfig->filter = kTSI_FilterBits_3;
 }
 
 void TSI_GetLowPowerModeDefaultConfig(tsi_config_t *userConfig)
@@ -96,13 +111,11 @@ void TSI_GetLowPowerModeDefaultConfig(tsi_config_t *userConfig)
     userConfig->thresh = 400U;
     userConfig->thresl = 0U;
     userConfig->prescaler = kTSI_ElecOscPrescaler_2div;
-    userConfig->extchrg = kTSI_ExtOscChargeCurrent_4uA;
+    userConfig->extchrg = kTSI_ExtOscChargeCurrent_500nA;
     userConfig->refchrg = kTSI_RefOscChargeCurrent_4uA;
     userConfig->nscn = kTSI_ConsecutiveScansNumber_5time;
     userConfig->mode = kTSI_AnalogModeSel_Capacitive;
     userConfig->dvolt = kTSI_OscVolRailsOption_0;
-    userConfig->resistor = kTSI_SeriesResistance_32k;
-    userConfig->filter = kTSI_FilterBits_3;
 }
 
 void TSI_Calibrate(TSI_Type *base, tsi_calibration_data_t *calBuff)
@@ -135,44 +148,56 @@ void TSI_Calibrate(TSI_Type *base, tsi_calibration_data_t *calBuff)
 
 void TSI_EnableInterrupts(TSI_Type *base, uint32_t mask)
 {
+    uint32_t regValue = base->GENCS & (~ALL_FLAGS_MASK);
+
     if (mask & kTSI_GlobalInterruptEnable)
     {
-        base->GENCS |= TSI_GENCS_TSIIEN_MASK;
+        regValue |= TSI_GENCS_TSIIEN_MASK;
     }
     if (mask & kTSI_OutOfRangeInterruptEnable)
     {
-        base->GENCS &= ~TSI_GENCS_ESOR_MASK;
+        regValue &= (~TSI_GENCS_ESOR_MASK);
     }
     if (mask & kTSI_EndOfScanInterruptEnable)
     {
-        base->GENCS |= TSI_GENCS_ESOR_MASK;
+        regValue |= TSI_GENCS_ESOR_MASK;
     }
+
+    base->GENCS = regValue;     /* write value to register */
 }
 
 void TSI_DisableInterrupts(TSI_Type *base, uint32_t mask)
 {
+    uint32_t regValue = base->GENCS & (~ALL_FLAGS_MASK);
+
     if (mask & kTSI_GlobalInterruptEnable)
     {
-        base->GENCS &= ~TSI_GENCS_TSIIEN_MASK;
+        regValue &= (~TSI_GENCS_TSIIEN_MASK);
     }
     if (mask & kTSI_OutOfRangeInterruptEnable)
     {
-        base->GENCS |= TSI_GENCS_ESOR_MASK;
+        regValue |= TSI_GENCS_ESOR_MASK;
     }
     if (mask & kTSI_EndOfScanInterruptEnable)
     {
-        base->GENCS &= ~TSI_GENCS_ESOR_MASK;
+        regValue &= (~TSI_GENCS_ESOR_MASK);
     }
+
+    base->GENCS = regValue;     /* write value to register */
 }
 
 void TSI_ClearStatusFlags(TSI_Type *base, uint32_t mask)
 {
+    uint32_t regValue = base->GENCS & (~ALL_FLAGS_MASK);
+
     if (mask & kTSI_EndOfScanFlag)
     {
-        base->GENCS = (base->GENCS & ~(TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK)) | TSI_GENCS_EOSF_MASK;
+        regValue |= TSI_GENCS_EOSF_MASK;
     }
     if (mask & kTSI_OutOfRangeFlag)
     {
-        base->GENCS = (base->GENCS & ~(TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK)) | TSI_GENCS_OUTRGF_MASK;
+        regValue |= TSI_GENCS_OUTRGF_MASK;
     }
+
+    base->GENCS = regValue;     /* write value to register */
 }
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tsi_v4.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tsi_v4.h
index d389a4d505f..3c204807db6 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tsi_v4.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_tsi_v4.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,7 +37,6 @@
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -45,10 +44,13 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief TSI driver version 2.0.0. */
-#define FSL_TSI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief TSI driver version */
+#define FSL_TSI_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
 /*@}*/
 
+/*! @brief TSI status flags macro collection */
+#define ALL_FLAGS_MASK  (TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK)
+
 /*! @brief resistor bit shift in EXTCHRG bit-field */
 #define TSI_V4_EXTCHRG_RESISTOR_BIT_SHIFT TSI_GENCS_EXTCHRG_SHIFT
 
@@ -57,11 +59,11 @@
 
 /*! @brief macro of clearing the resistor bit in EXTCHRG bit-field */
 #define TSI_V4_EXTCHRG_RESISTOR_BIT_CLEAR \
-    ((uint32_t)((~TSI_GENCS_EXTCHRG_MASK) | (3U << TSI_V4_EXTCHRG_FILTER_BITS_SHIFT)))
+    ((uint32_t)((~(ALL_FLAGS_MASK | TSI_GENCS_EXTCHRG_MASK)) | (3U << TSI_V4_EXTCHRG_FILTER_BITS_SHIFT)))
 
 /*! @brief macro of clearing the filter bits in EXTCHRG bit-field */
 #define TSI_V4_EXTCHRG_FILTER_BITS_CLEAR \
-    ((uint32_t)((~TSI_GENCS_EXTCHRG_MASK) | (1U << TSI_V4_EXTCHRG_RESISTOR_BIT_SHIFT)))
+    ((uint32_t)((~(ALL_FLAGS_MASK | TSI_GENCS_EXTCHRG_MASK)) | (1U << TSI_V4_EXTCHRG_RESISTOR_BIT_SHIFT)))
 
 /*!
  * @brief TSI number of scan intervals for each electrode.
@@ -286,13 +288,11 @@ void TSI_Deinit(TSI_Type *base);
  * The user configure is set to these values:
  * @code
     userConfig->prescaler = kTSI_ElecOscPrescaler_2div;
-    userConfig->extchrg = kTSI_ExtOscChargeCurrent_4uA;
+    userConfig->extchrg = kTSI_ExtOscChargeCurrent_500nA;
     userConfig->refchrg = kTSI_RefOscChargeCurrent_4uA;
     userConfig->nscn = kTSI_ConsecutiveScansNumber_10time;
     userConfig->mode = kTSI_AnalogModeSel_Capacitive;
     userConfig->dvolt = kTSI_OscVolRailsOption_0;
-    userConfig->resistor = kTSI_SeriesResistance_32k;
-    userConfig->filter = kTSI_FilterBits_1;
     userConfig->thresh = 0U;
     userConfig->thresl = 0U;
    @endcode
@@ -308,13 +308,11 @@ void TSI_GetNormalModeDefaultConfig(tsi_config_t *userConfig);
  * The user configure is set to these values:
  * @code
     userConfig->prescaler = kTSI_ElecOscPrescaler_2div;
-    userConfig->extchrg = kTSI_ExtOscChargeCurrent_4uA;
+    userConfig->extchrg = kTSI_ExtOscChargeCurrent_500nA;
     userConfig->refchrg = kTSI_RefOscChargeCurrent_4uA;
     userConfig->nscn = kTSI_ConsecutiveScansNumber_10time;
     userConfig->mode = kTSI_AnalogModeSel_Capacitive;
     userConfig->dvolt = kTSI_OscVolRailsOption_0;
-    userConfig->resistor = kTSI_SeriesResistance_32k;
-    userConfig->filter = kTSI_FilterBits_1;
     userConfig->thresh = 400U;
     userConfig->thresl = 0U;
    @endcode
@@ -417,7 +415,7 @@ static inline bool TSI_IsScanInProgress(TSI_Type *base)
 */
 static inline void TSI_SetElectrodeOSCPrescaler(TSI_Type *base, tsi_electrode_osc_prescaler_t prescaler)
 {
-    base->GENCS = ((base->GENCS) & ~TSI_GENCS_PS_MASK) | (TSI_GENCS_PS(prescaler));
+    base->GENCS = (base->GENCS & ~(TSI_GENCS_PS_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_PS(prescaler));
 }
 
 /*!
@@ -429,7 +427,7 @@ static inline void TSI_SetElectrodeOSCPrescaler(TSI_Type *base, tsi_electrode_os
 */
 static inline void TSI_SetNumberOfScans(TSI_Type *base, tsi_n_consecutive_scans_t number)
 {
-    base->GENCS = ((base->GENCS) & ~TSI_GENCS_NSCN_MASK) | (TSI_GENCS_NSCN(number));
+    base->GENCS = (base->GENCS & ~(TSI_GENCS_NSCN_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_NSCN(number));
 }
 
 /*!
@@ -445,11 +443,11 @@ static inline void TSI_EnableModule(TSI_Type *base, bool enable)
 {
     if (enable)
     {
-        base->GENCS |= TSI_GENCS_TSIEN_MASK; /* Enable module */
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) | TSI_GENCS_TSIEN_MASK;    /* Enable module */
     }
     else
     {
-        base->GENCS &= ~TSI_GENCS_TSIEN_MASK; /* Disable module */
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) & (~TSI_GENCS_TSIEN_MASK); /* Disable module */
     }
 }
 
@@ -467,11 +465,11 @@ static inline void TSI_EnableLowPower(TSI_Type *base, bool enable)
 {
     if (enable)
     {
-        base->GENCS |= TSI_GENCS_STPE_MASK; /* Module enabled in low power stop modes */
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) | TSI_GENCS_STPE_MASK;    /* Module enabled in low power stop modes */
     }
     else
     {
-        base->GENCS &= ~TSI_GENCS_STPE_MASK; /* Module disabled in low power stop modes */
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) & (~TSI_GENCS_STPE_MASK); /* Module disabled in low power stop modes */
     }
 }
 
@@ -488,11 +486,11 @@ static inline void TSI_EnableHardwareTriggerScan(TSI_Type *base, bool enable)
 {
     if (enable)
     {
-        base->GENCS |= TSI_GENCS_STM_MASK; /* Enable hardware trigger scan */
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) | TSI_GENCS_STM_MASK;    /* Enable hardware trigger scan */
     }
     else
     {
-        base->GENCS &= ~TSI_GENCS_STM_MASK; /* Enable software trigger scan */
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) & (~TSI_GENCS_STM_MASK); /* Enable software trigger scan */
     }
 }
 
@@ -567,12 +565,12 @@ static inline void TSI_EnableEndOfScanDmaTransferOnly(TSI_Type *base, bool enabl
 {
     if (enable)
     {
-        base->GENCS |= TSI_GENCS_EOSDMEO_MASK; /* Enable End of Scan DMA transfer request only; */
+        base->GENCS = (base->GENCS & ~ALL_FLAGS_MASK) | TSI_GENCS_EOSDMEO_MASK; /* Enable End of Scan DMA transfer request only; */
     }
     else
     {
-        base->GENCS &=
-            ~TSI_GENCS_EOSDMEO_MASK; /* Both End-of-Scan and Out-of-Range can generate DMA transfer request. */
+        base->GENCS =
+            (base->GENCS & ~ALL_FLAGS_MASK) & (~TSI_GENCS_EOSDMEO_MASK); /* Both End-of-Scan and Out-of-Range can generate DMA transfer request. */
     }
 }
 #endif /* End of (FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE == 1)*/
@@ -625,7 +623,7 @@ static inline void TSI_SetHighThreshold(TSI_Type *base, uint16_t high_threshold)
 */
 static inline void TSI_SetAnalogMode(TSI_Type *base, tsi_analog_mode_t mode)
 {
-    base->GENCS = ((base->GENCS) & ~TSI_GENCS_MODE_MASK) | (TSI_GENCS_MODE(mode));
+    base->GENCS = (base->GENCS & ~(TSI_GENCS_MODE_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_MODE(mode));
 }
 
 /*!
@@ -648,7 +646,7 @@ static inline uint8_t TSI_GetNoiseModeResult(TSI_Type *base)
 */
 static inline void TSI_SetReferenceChargeCurrent(TSI_Type *base, tsi_reference_osc_charge_current_t current)
 {
-    base->GENCS = ((base->GENCS) & ~TSI_GENCS_REFCHRG_MASK) | (TSI_GENCS_REFCHRG(current));
+    base->GENCS = (base->GENCS & ~(TSI_GENCS_REFCHRG_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_REFCHRG(current));
 }
 
 /*!
@@ -660,7 +658,7 @@ static inline void TSI_SetReferenceChargeCurrent(TSI_Type *base, tsi_reference_o
 */
 static inline void TSI_SetElectrodeChargeCurrent(TSI_Type *base, tsi_external_osc_charge_current_t current)
 {
-    base->GENCS = ((base->GENCS) & ~TSI_GENCS_EXTCHRG_MASK) | (TSI_GENCS_EXTCHRG(current));
+    base->GENCS = (base->GENCS & ~(TSI_GENCS_EXTCHRG_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_EXTCHRG(current));
 }
 
 /*!
@@ -672,7 +670,7 @@ static inline void TSI_SetElectrodeChargeCurrent(TSI_Type *base, tsi_external_os
 */
 static inline void TSI_SetOscVoltageRails(TSI_Type *base, tsi_osc_voltage_rails_t dvolt)
 {
-    base->GENCS = ((base->GENCS) & ~TSI_GENCS_DVOLT_MASK) | (TSI_GENCS_DVOLT(dvolt));
+    base->GENCS = (base->GENCS & ~(TSI_GENCS_DVOLT_MASK | ALL_FLAGS_MASK)) | (TSI_GENCS_DVOLT(dvolt));
 }
 
 /*!
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart.c
index b0b92399db4..17d9260027b 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart.c
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,10 +37,12 @@
 /* UART transfer state. */
 enum _uart_tansfer_states
 {
-    kUART_TxIdle, /* TX idle. */
-    kUART_TxBusy, /* TX busy. */
-    kUART_RxIdle, /* RX idle. */
-    kUART_RxBusy  /* RX busy. */
+    kUART_TxIdle,         /* TX idle. */
+    kUART_TxBusy,         /* TX busy. */
+    kUART_RxIdle,         /* RX idle. */
+    kUART_RxBusy,         /* RX busy. */
+    kUART_RxFramingError, /* Rx framing error */
+    kUART_RxParityError   /* Rx parity error */
 };
 
 /* Typedef for interrupt handler. */
@@ -138,8 +140,10 @@ static UART_Type *const s_uartBases[] = UART_BASE_PTRS;
 
 /* Array of UART IRQ number. */
 static const IRQn_Type s_uartIRQ[] = UART_RX_TX_IRQS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /* Array of UART clock name. */
 static const clock_ip_name_t s_uartClock[] = UART_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /* UART ISR for transactional APIs. */
 static uart_isr_t s_uartIsr;
@@ -169,6 +173,8 @@ uint32_t UART_GetInstance(UART_Type *base)
 
 static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle)
 {
+    assert(handle);
+
     size_t size;
 
     if (handle->rxRingBufferTail > handle->rxRingBufferHead)
@@ -185,6 +191,8 @@ static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle)
 
 static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle)
 {
+    assert(handle);
+
     bool full;
 
     if (UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))
@@ -199,36 +207,72 @@ static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle)
     return full;
 }
 
-void UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz)
+status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz)
 {
     assert(config);
+    assert(config->baudRate_Bps);
 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
     assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->txFifoWatermark);
     assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->rxFifoWatermark);
 #endif
 
-    uint16_t sbr;
-    uint8_t temp;
+    uint16_t sbr = 0;
+    uint8_t temp = 0;
+    uint32_t baudDiff = 0;
+
+    /* Calculate the baud rate modulo divisor, sbr*/
+    sbr = srcClock_Hz / (config->baudRate_Bps * 16);
+    /* set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate */
+    if (sbr == 0)
+    {
+        sbr = 1;
+    }
+#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
+    /* Determine if a fractional divider is needed to fine tune closer to the
+     * desired baud, each value of brfa is in 1/32 increments,
+     * hence the multiply-by-32. */
+    uint32_t tempBaud = 0;
+
+    uint16_t brfa = (2 * srcClock_Hz / (config->baudRate_Bps)) - 32 * sbr;
+
+    /* Calculate the baud rate based on the temporary SBR values and BRFA */
+    tempBaud = (srcClock_Hz * 2 / ((sbr * 32 + brfa)));
+    baudDiff =
+        (tempBaud > config->baudRate_Bps) ? (tempBaud - config->baudRate_Bps) : (config->baudRate_Bps - tempBaud);
 
+#else
+    /* Calculate the baud rate based on the temporary SBR values */
+    baudDiff = (srcClock_Hz / (sbr * 16)) - config->baudRate_Bps;
+
+    /* Select the better value between sbr and (sbr + 1) */
+    if (baudDiff > (config->baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1)))))
+    {
+        baudDiff = config->baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1)));
+        sbr++;
+    }
+#endif
+
+    /* next, check to see if actual baud rate is within 3% of desired baud rate
+     * based on the calculate SBR value */
+    if (baudDiff > ((config->baudRate_Bps / 100) * 3))
+    {
+        /* Unacceptable baud rate difference of more than 3%*/
+        return kStatus_UART_BaudrateNotSupport;
+    }
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable uart clock */
     CLOCK_EnableClock(s_uartClock[UART_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Disable UART TX RX before setting. */
     base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK);
 
-    /* Calculate the baud rate modulo divisor, sbr*/
-    sbr = srcClock_Hz / (config->baudRate_Bps * 16);
-
     /* Write the sbr value to the BDH and BDL registers*/
     base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8);
     base->BDL = (uint8_t)sbr;
 
 #if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
-    /* Determine if a fractional divider is needed to fine tune closer to the
-     * desired baud, each value of brfa is in 1/32 increments,
-     * hence the multiply-by-32. */
-    uint16_t brfa = (32 * srcClock_Hz / (config->baudRate_Bps * 16)) - 32 * sbr;
-
     /* Write the brfa value to the register*/
     base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK);
 #endif
@@ -274,6 +318,8 @@ void UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_H
     }
 
     base->C2 = temp;
+
+    return kStatus_Success;
 }
 
 void UART_Deinit(UART_Type *base)
@@ -292,8 +338,10 @@ void UART_Deinit(UART_Type *base)
     /* Disable the module. */
     base->C2 = 0;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable uart clock */
     CLOCK_DisableClock(s_uartClock[UART_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void UART_GetDefaultConfig(uart_config_t *config)
@@ -313,61 +361,101 @@ void UART_GetDefaultConfig(uart_config_t *config)
     config->enableRx = false;
 }
 
-void UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
+status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
 {
-    uint16_t sbr;
-    uint8_t oldCtrl;
-
-    /* Store C2 before disable Tx and Rx */
-    oldCtrl = base->C2;
+    assert(baudRate_Bps);
 
-    /* Disable UART TX RX before setting. */
-    base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK);
+    uint16_t sbr = 0;
+    uint32_t baudDiff = 0;
+    uint8_t oldCtrl;
 
     /* Calculate the baud rate modulo divisor, sbr*/
     sbr = srcClock_Hz / (baudRate_Bps * 16);
-
-    /* Write the sbr value to the BDH and BDL registers*/
-    base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8);
-    base->BDL = (uint8_t)sbr;
-
+    /* set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate */
+    if (sbr == 0)
+    {
+        sbr = 1;
+    }
 #if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
     /* Determine if a fractional divider is needed to fine tune closer to the
      * desired baud, each value of brfa is in 1/32 increments,
      * hence the multiply-by-32. */
-    uint16_t brfa = (32 * srcClock_Hz / (baudRate_Bps * 16)) - 32 * sbr;
+    uint32_t tempBaud = 0;
 
-    /* Write the brfa value to the register*/
-    base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK);
+    uint16_t brfa = (2 * srcClock_Hz / (baudRate_Bps)) - 32 * sbr;
+
+    /* Calculate the baud rate based on the temporary SBR values and BRFA */
+    tempBaud = (srcClock_Hz * 2 / ((sbr * 32 + brfa)));
+    baudDiff = (tempBaud > baudRate_Bps) ? (tempBaud - baudRate_Bps) : (baudRate_Bps - tempBaud);
+#else
+    /* Calculate the baud rate based on the temporary SBR values */
+    baudDiff = (srcClock_Hz / (sbr * 16)) - baudRate_Bps;
+
+    /* Select the better value between sbr and (sbr + 1) */
+    if (baudDiff > (baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1)))))
+    {
+        baudDiff = baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1)));
+        sbr++;
+    }
+#endif
+
+    /* next, check to see if actual baud rate is within 3% of desired baud rate
+     * based on the calculate SBR value */
+    if (baudDiff < ((baudRate_Bps / 100) * 3))
+    {
+        /* Store C2 before disable Tx and Rx */
+        oldCtrl = base->C2;
+
+        /* Disable UART TX RX before setting. */
+        base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK);
+
+        /* Write the sbr value to the BDH and BDL registers*/
+        base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8);
+        base->BDL = (uint8_t)sbr;
+
+#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
+        /* Write the brfa value to the register*/
+        base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK);
 #endif
+        /* Restore C2. */
+        base->C2 = oldCtrl;
 
-    /* Restore C2. */
-    base->C2 = oldCtrl;
+        return kStatus_Success;
+    }
+    else
+    {
+        /* Unacceptable baud rate difference of more than 3%*/
+        return kStatus_UART_BaudrateNotSupport;
+    }
 }
 
 void UART_EnableInterrupts(UART_Type *base, uint32_t mask)
 {
+    mask &= kUART_AllInterruptsEnable;
+
     /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH))
      */
-    base->BDH |= (mask & 0xFF);
-    base->C2 |= ((mask >> 8) & 0xFF);
-    base->C3 |= ((mask >> 16) & 0xFF);
+    base->BDH |= mask;
+    base->C2 |= (mask >> 8);
+    base->C3 |= (mask >> 16);
 
 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
-    base->CFIFO |= ((mask >> 24) & 0xFF);
+    base->CFIFO |= (mask >> 24);
 #endif
 }
 
 void UART_DisableInterrupts(UART_Type *base, uint32_t mask)
 {
+    mask &= kUART_AllInterruptsEnable;
+
     /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH))
      */
-    base->BDH &= ~(mask & 0xFF);
-    base->C2 &= ~((mask >> 8) & 0xFF);
-    base->C3 &= ~((mask >> 16) & 0xFF);
+    base->BDH &= ~mask;
+    base->C2 &= ~(mask >> 8);
+    base->C3 &= ~(mask >> 16);
 
 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
-    base->CFIFO &= ~((mask >> 24) & 0xFF);
+    base->CFIFO &= ~(mask >> 24);
 #endif
 }
 
@@ -381,7 +469,7 @@ uint32_t UART_GetEnabledInterrupts(UART_Type *base)
     temp |= ((uint32_t)(base->CFIFO) << 24);
 #endif
 
-    return temp;
+    return temp & kUART_AllInterruptsEnable;
 }
 
 uint32_t UART_GetStatusFlags(UART_Type *base)
@@ -418,14 +506,24 @@ status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask)
     base->SFIFO = (uint8_t)(mask >> 24);
 #endif
 
-    if (mask & (kUART_IdleLineFlag | kUART_RxOverrunFlag | kUART_NoiseErrorFlag | kUART_FramingErrorFlag |
-                kUART_ParityErrorFlag))
+    if (mask & (kUART_IdleLineFlag | kUART_NoiseErrorFlag | kUART_FramingErrorFlag | kUART_ParityErrorFlag))
     {
         /* Read base->D to clear the flags. */
         (void)base->S1;
         (void)base->D;
     }
 
+    if (mask & kUART_RxOverrunFlag)
+    {
+        /* Read base->D to clear the flags and Flush all data in FIFO. */
+        (void)base->S1;
+        (void)base->D;
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+        /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
+        base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
+#endif
+    }
+
     /* If some flags still pending. */
     if (mask & UART_GetStatusFlags(base))
     {
@@ -457,6 +555,8 @@ void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length)
 
 static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length)
 {
+    assert(data);
+
     size_t i;
 
     /* The Non Blocking write data API assume user have ensured there is enough space in
@@ -469,6 +569,8 @@ static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t l
 
 status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length)
 {
+    assert(data);
+
     uint32_t statusFlag;
 
     while (length--)
@@ -509,6 +611,8 @@ status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length)
 
 static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length)
 {
+    assert(data);
+
     size_t i;
 
     /* The Non Blocking read data API assume user have ensured there is enough space in
@@ -558,7 +662,6 @@ void UART_TransferCreateHandle(UART_Type *base,
     s_uartHandle[instance] = handle;
 
     s_uartIsr = UART_TransferHandleIRQ;
-
     /* Enable interrupt in NVIC. */
     EnableIRQ(s_uartIRQ[instance]);
 }
@@ -566,17 +669,21 @@ void UART_TransferCreateHandle(UART_Type *base,
 void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)
 {
     assert(handle);
+    assert(ringBuffer);
 
     /* Setup the ringbuffer address */
-    if (ringBuffer)
-    {
-        handle->rxRingBuffer = ringBuffer;
-        handle->rxRingBufferSize = ringBufferSize;
-        handle->rxRingBufferHead = 0U;
-        handle->rxRingBufferTail = 0U;
+    handle->rxRingBuffer = ringBuffer;
+    handle->rxRingBufferSize = ringBufferSize;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
 
-        /* Enable the interrupt to accept the data when user need the ring buffer. */
-        UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable);
+    /* Enable the interrupt to accept the data when user need the ring buffer. */
+    UART_EnableInterrupts(
+        base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable | kUART_FramingErrorInterruptEnable);
+    /* Enable parity error interrupt when parity mode is enable*/
+    if (UART_C1_PE_MASK & base->C1)
+    {
+        UART_EnableInterrupts(base, kUART_ParityErrorInterruptEnable);
     }
 }
 
@@ -586,7 +693,13 @@ void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle)
 
     if (handle->rxState == kUART_RxIdle)
     {
-        UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable);
+        UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
+                                         kUART_FramingErrorInterruptEnable);
+        /* Disable parity error interrupt when parity mode is enable*/
+        if (UART_C1_PE_MASK & base->C1)
+        {
+            UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
+        }
     }
 
     handle->rxRingBuffer = NULL;
@@ -597,13 +710,12 @@ void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle)
 
 status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer)
 {
-    status_t status;
+    assert(handle);
+    assert(xfer);
+    assert(xfer->dataSize);
+    assert(xfer->data);
 
-    /* Return error if xfer invalid. */
-    if ((0U == xfer->dataSize) || (NULL == xfer->data))
-    {
-        return kStatus_InvalidArgument;
-    }
+    status_t status;
 
     /* Return error if current TX busy. */
     if (kUART_TxBusy == handle->txState)
@@ -628,6 +740,8 @@ status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, ua
 
 void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle)
 {
+    assert(handle);
+
     UART_DisableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable | kUART_TransmissionCompleteInterruptEnable);
 
     handle->txDataSize = 0;
@@ -636,16 +750,14 @@ void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle)
 
 status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count)
 {
+    assert(handle);
+    assert(count);
+
     if (kUART_TxIdle == handle->txState)
     {
         return kStatus_NoTransferInProgress;
     }
 
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
     *count = handle->txDataSizeAll - handle->txDataSize;
 
     return kStatus_Success;
@@ -656,6 +768,11 @@ status_t UART_TransferReceiveNonBlocking(UART_Type *base,
                                          uart_transfer_t *xfer,
                                          size_t *receivedBytes)
 {
+    assert(handle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
+
     uint32_t i;
     status_t status;
     /* How many bytes to copy from ring buffer to user memory. */
@@ -664,13 +781,6 @@ status_t UART_TransferReceiveNonBlocking(UART_Type *base,
     size_t bytesToReceive;
     /* How many bytes currently have received. */
     size_t bytesCurrentReceived;
-    uint32_t regPrimask = 0U;
-
-    /* Return error if xfer invalid. */
-    if ((0U == xfer->dataSize) || (NULL == xfer->data))
-    {
-        return kStatus_InvalidArgument;
-    }
 
     /* How to get data:
        1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
@@ -694,8 +804,8 @@ status_t UART_TransferReceiveNonBlocking(UART_Type *base,
         /* If RX ring buffer is used. */
         if (handle->rxRingBuffer)
         {
-            /* Disable IRQ, protect ring buffer. */
-            regPrimask = DisableGlobalIRQ();
+            /* Disable UART RX IRQ, protect ring buffer. */
+            UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable);
 
             /* How many bytes in RX ring buffer currently. */
             bytesToCopy = UART_TransferGetRxRingBufferLength(handle);
@@ -733,8 +843,8 @@ status_t UART_TransferReceiveNonBlocking(UART_Type *base,
                 handle->rxState = kUART_RxBusy;
             }
 
-            /* Enable IRQ if previously enabled. */
-            EnableGlobalIRQ(regPrimask);
+            /* Enable UART RX IRQ if previously enabled. */
+            UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable);
 
             /* Call user callback since all data are received. */
             if (0 == bytesToReceive)
@@ -753,8 +863,14 @@ status_t UART_TransferReceiveNonBlocking(UART_Type *base,
             handle->rxDataSizeAll = bytesToReceive;
             handle->rxState = kUART_RxBusy;
 
-            /* Enable RX interrupt. */
-            UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable);
+            /* Enable RX/Rx overrun/framing error interrupt. */
+            UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
+                                            kUART_FramingErrorInterruptEnable);
+            /* Enable parity error interrupt when parity mode is enable*/
+            if (UART_C1_PE_MASK & base->C1)
+            {
+                UART_EnableInterrupts(base, kUART_ParityErrorInterruptEnable);
+            }
         }
 
         /* Return the how many bytes have read. */
@@ -771,11 +887,19 @@ status_t UART_TransferReceiveNonBlocking(UART_Type *base,
 
 void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle)
 {
+    assert(handle);
+
     /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
     if (!handle->rxRingBuffer)
     {
         /* Disable RX interrupt. */
-        UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable);
+        UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
+                                         kUART_FramingErrorInterruptEnable);
+        /* Disable parity error interrupt when parity mode is enable*/
+        if (UART_C1_PE_MASK & base->C1)
+        {
+            UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
+        }
     }
 
     handle->rxDataSize = 0U;
@@ -784,6 +908,9 @@ void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle)
 
 status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count)
 {
+    assert(handle);
+    assert(count);
+
     if (kUART_RxIdle == handle->rxState)
     {
         return kStatus_NoTransferInProgress;
@@ -801,17 +928,67 @@ status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, ui
 
 void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle)
 {
+    assert(handle);
+
     uint8_t count;
     uint8_t tempCount;
 
-    assert(handle);
+    /* If RX framing error */
+    if (UART_S1_FE_MASK & base->S1)
+    {
+        /* Read base->D to clear framing error flag, otherwise the RX does not work. */
+        while (base->S1 & UART_S1_RDRF_MASK)
+        {
+            (void)base->D;
+        }
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+        /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
+        base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
+#endif
+
+        handle->rxState = kUART_RxFramingError;
+        handle->rxDataSize = 0U;
+        /* Trigger callback. */
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kStatus_UART_FramingError, handle->userData);
+        }
+    }
+
+    /* If RX parity error */
+    if (UART_S1_PF_MASK & base->S1)
+    {
+        /* Read base->D to clear parity error flag, otherwise the RX does not work. */
+        while (base->S1 & UART_S1_RDRF_MASK)
+        {
+            (void)base->D;
+        }
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+        /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
+        base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
+#endif
+
+        handle->rxState = kUART_RxParityError;
+        handle->rxDataSize = 0U;
+        /* Trigger callback. */
+        if (handle->callback)
+        {
+            handle->callback(base, handle, kStatus_UART_ParityError, handle->userData);
+        }
+    }
 
     /* If RX overrun. */
     if (UART_S1_OR_MASK & base->S1)
     {
-        /* Read base->D, otherwise the RX does not work. */
-        (void)base->D;
-
+        /* Read base->D to clear overrun flag, otherwise the RX does not work. */
+        while (base->S1 & UART_S1_RDRF_MASK)
+        {
+            (void)base->D;
+        }
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+        /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
+        base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
+#endif
         /* Trigger callback. */
         if (handle->callback)
         {
@@ -898,16 +1075,38 @@ void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle)
                 }
             }
         }
-        /* If no receive requst pending, stop RX interrupt. */
+
         else if (!handle->rxDataSize)
         {
-            UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable);
+            /* Disable RX interrupt/overrun interrupt/fram error interrupt */
+            UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
+                                             kUART_FramingErrorInterruptEnable);
+
+            /* Disable parity error interrupt when parity mode is enable*/
+            if (UART_C1_PE_MASK & base->C1)
+            {
+                UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
+            }
         }
         else
         {
         }
     }
 
+    /* If framing error or parity error happened, stop the RX interrupt when ues no ring buffer */
+    if (((handle->rxState == kUART_RxFramingError) || (handle->rxState == kUART_RxParityError)) &&
+        (!handle->rxRingBuffer))
+    {
+        UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
+                                         kUART_FramingErrorInterruptEnable);
+
+        /* Disable parity error interrupt when parity mode is enable*/
+        if (UART_C1_PE_MASK & base->C1)
+        {
+            UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
+        }
+    }
+
     /* Send data register empty and the interrupt is enabled. */
     if ((base->S1 & UART_S1_TDRE_MASK) && (base->C2 & UART_C2_TIE_MASK))
     {
@@ -952,7 +1151,7 @@ void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle)
 
 void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle)
 {
-    /* TODO: To be implemented. */
+    /* To be implemented by User. */
 }
 
 #if defined(UART0)
@@ -992,7 +1191,6 @@ void UART2_RX_TX_DriverIRQHandler(void)
 {
     UART2_DriverIRQHandler();
 }
-
 #endif
 
 #if defined(UART3)
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart.h
index 3eec4e66b58..451baa9ffd3 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart.h
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,16 +37,14 @@
  * @{
  */
 
-/*! @file */
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief UART driver version 2.1.0. */
-#define FSL_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*! @brief UART driver version 2.1.4. */
+#define FSL_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
 /*@}*/
 
 /*! @brief Error codes for the UART driver. */
@@ -66,6 +64,8 @@ enum _uart_status
     kStatus_UART_NoiseError = MAKE_STATUS(kStatusGroup_UART, 10),         /*!< UART noise error. */
     kStatus_UART_FramingError = MAKE_STATUS(kStatusGroup_UART, 11),       /*!< UART framing error. */
     kStatus_UART_ParityError = MAKE_STATUS(kStatusGroup_UART, 12),        /*!< UART parity error. */
+    kStatus_UART_BaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_UART, 13), /*!< Baudrate is not support in current clock source */
 };
 
 /*! @brief UART parity mode. */
@@ -103,10 +103,23 @@ enum _uart_interrupt_enable
     kUART_FramingErrorInterruptEnable = (UART_C3_FEIE_MASK << 16),        /*!< Framing error flag interrupt. */
     kUART_ParityErrorInterruptEnable = (UART_C3_PEIE_MASK << 16),         /*!< Parity error flag interrupt. */
 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
-    kUART_RxFifoOverflowInterruptEnable = (UART_CFIFO_TXOFE_MASK << 24),  /*!< TX FIFO overflow interrupt. */
-    kUART_TxFifoOverflowInterruptEnable = (UART_CFIFO_RXUFE_MASK << 24),  /*!< RX FIFO underflow interrupt. */
+    kUART_RxFifoOverflowInterruptEnable = (UART_CFIFO_RXOFE_MASK << 24),  /*!< RX FIFO overflow interrupt. */
+    kUART_TxFifoOverflowInterruptEnable = (UART_CFIFO_TXOFE_MASK << 24),  /*!< TX FIFO overflow interrupt. */
     kUART_RxFifoUnderflowInterruptEnable = (UART_CFIFO_RXUFE_MASK << 24), /*!< RX FIFO underflow interrupt. */
 #endif
+    kUART_AllInterruptsEnable =
+#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT
+        kUART_LinBreakInterruptEnable |
+#endif
+        kUART_RxActiveEdgeInterruptEnable | kUART_TxDataRegEmptyInterruptEnable |
+        kUART_TransmissionCompleteInterruptEnable | kUART_RxDataRegFullInterruptEnable | kUART_IdleLineInterruptEnable |
+        kUART_RxOverrunInterruptEnable | kUART_NoiseErrorInterruptEnable | kUART_FramingErrorInterruptEnable |
+        kUART_ParityErrorInterruptEnable
+#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
+        |
+        kUART_RxFifoOverflowInterruptEnable | kUART_TxFifoOverflowInterruptEnable | kUART_RxFifoUnderflowInterruptEnable
+#endif
+    ,
 };
 
 /*!
@@ -128,13 +141,16 @@ enum _uart_flags
     kUART_ParityErrorFlag = (UART_S1_PF_MASK),          /*!< If parity enabled, sets upon parity error detection */
 #if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT
     kUART_LinBreakFlag =
-        (UART_S2_LBKDIF_MASK << 8), /*!< LIN break detect interrupt flag, sets when
-                                                           LIN break char detected and LIN circuit enabled */
+        (UART_S2_LBKDIF_MASK
+         << 8), /*!< LIN break detect interrupt flag, sets when
+                                                       LIN break char detected and LIN circuit enabled */
 #endif
-    kUART_RxActiveEdgeFlag = (UART_S2_RXEDGIF_MASK << 8), /*!< RX pin active edge interrupt flag,
-                                                                                 sets when active edge detected */
-    kUART_RxActiveFlag = (UART_S2_RAF_MASK << 8),         /*!< Receiver Active Flag (RAF),
-                                                                                 sets at beginning of valid start bit */
+    kUART_RxActiveEdgeFlag =
+        (UART_S2_RXEDGIF_MASK << 8), /*!< RX pin active edge interrupt flag,
+                                                                            sets when active edge detected */
+    kUART_RxActiveFlag =
+        (UART_S2_RAF_MASK << 8), /*!< Receiver Active Flag (RAF),
+                                                                        sets at beginning of valid start bit */
 #if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS
     kUART_NoiseErrorInRxDataRegFlag = (UART_ED_NOISY_MASK << 16),    /*!< Noisy bit, sets if noise detected. */
     kUART_ParityErrorInRxDataRegFlag = (UART_ED_PARITYE_MASK << 16), /*!< Paritye bit, sets if parity error detected. */
@@ -213,11 +229,11 @@ extern "C" {
  */
 
 /*!
- * @brief Initializes a UART instance with user configuration structure and peripheral clock.
+ * @brief Initializes a UART instance with a user configuration structure and peripheral clock.
  *
  * This function configures the UART module with the user-defined settings. The user can configure the configuration
  * structure and also get the default configuration by using the UART_GetDefaultConfig() function.
- * Example below shows how to use this API to configure UART.
+ * The example below shows how to use this API to configure UART.
  * @code
  *  uart_config_t uartConfig;
  *  uartConfig.baudRate_Bps = 115200U;
@@ -229,10 +245,12 @@ extern "C" {
  * @endcode
  *
  * @param base UART peripheral base address.
- * @param config Pointer to user-defined configuration structure.
+ * @param config Pointer to the user-defined configuration structure.
  * @param srcClock_Hz UART clock source frequency in HZ.
+ * @retval kStatus_UART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success Status UART initialize succeed
  */
-void UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz);
+status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz);
 
 /*!
  * @brief Deinitializes a UART instance.
@@ -247,7 +265,7 @@ void UART_Deinit(UART_Type *base);
  * @brief Gets the default configuration structure.
  *
  * This function initializes the UART configuration structure to a default value. The default
- * values are:
+ * values are as follows.
  *   uartConfig->baudRate_Bps = 115200U;
  *   uartConfig->bitCountPerChar = kUART_8BitsPerChar;
  *   uartConfig->parityMode = kUART_ParityDisabled;
@@ -272,9 +290,11 @@ void UART_GetDefaultConfig(uart_config_t *config);
  *
  * @param base UART peripheral base address.
  * @param baudRate_Bps UART baudrate to be set.
- * @param srcClock_Hz UART clock source freqency in HZ.
+ * @param srcClock_Hz UART clock source freqency in Hz.
+ * @retval kStatus_UART_BaudrateNotSupport Baudrate is not support in the current clock source.
+ * @retval kStatus_Success Set baudrate succeeded.
  */
-void UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
+status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
 
 /* @} */
 
@@ -284,12 +304,12 @@ void UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_
  */
 
 /*!
- * @brief Get UART status flags.
+ * @brief Gets UART status flags.
  *
- * This function get all UART status flags, the flags are returned as the logical
- * OR value of the enumerators @ref _uart_flags. To check specific status,
+ * This function gets all UART status flags. The flags are returned as the logical
+ * OR value of the enumerators @ref _uart_flags. To check a specific status,
  * compare the return value with enumerators in @ref _uart_flags.
- * For example, to check whether the TX is empty:
+ * For example, to check whether the TX is empty, do the following.
  * @code
  *     if (kUART_TxDataRegEmptyFlag & UART_GetStatusFlags(UART1))
  *     {
@@ -305,19 +325,19 @@ uint32_t UART_GetStatusFlags(UART_Type *base);
 /*!
  * @brief Clears status flags with the provided mask.
  *
- * This function clears UART status flags with a provided mask. Automatically cleared flag
+ * This function clears UART status flags with a provided mask. An automatically cleared flag
  * can't be cleared by this function.
- * Some flags can only be cleared or set by hardware itself. These flags are:
+ * These flags can only be cleared or set by hardware.
  *    kUART_TxDataRegEmptyFlag, kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag,
  *    kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag, kUART_ParityErrorInRxDataRegFlag,
  *    kUART_TxFifoEmptyFlag,kUART_RxFifoEmptyFlag
- * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.
+ * Note that this API should be called when the Tx/Rx is idle. Otherwise it has no effect.
  *
  * @param base UART peripheral base address.
- * @param mask The status flags to be cleared, it is logical OR value of @ref _uart_flags.
+ * @param mask The status flags to be cleared; it is logical OR value of @ref _uart_flags.
  * @retval kStatus_UART_FlagCannotClearManually The flag can't be cleared by this function but
  *         it is cleared automatically by hardware.
- * @retval kStatus_Success Status in the mask are cleared.
+ * @retval kStatus_Success Status in the mask is cleared.
  */
 status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask);
 
@@ -333,7 +353,7 @@ status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask);
  *
  * This function enables the UART interrupts according to the provided mask. The mask
  * is a logical OR of enumeration members. See @ref _uart_interrupt_enable.
- * For example, to enable TX empty interrupt and RX full interrupt:
+ * For example, to enable TX empty interrupt and RX full interrupt, do the following.
  * @code
  *     UART_EnableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable);
  * @endcode
@@ -348,7 +368,7 @@ void UART_EnableInterrupts(UART_Type *base, uint32_t mask);
  *
  * This function disables the UART interrupts according to the provided mask. The mask
  * is a logical OR of enumeration members. See @ref _uart_interrupt_enable.
- * For example, to disable TX empty interrupt and RX full interrupt:
+ * For example, to disable TX empty interrupt and RX full interrupt do the following.
  * @code
  *     UART_DisableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable);
  * @endcode
@@ -363,9 +383,9 @@ void UART_DisableInterrupts(UART_Type *base, uint32_t mask);
  *
  * This function gets the enabled UART interrupts. The enabled interrupts are returned
  * as the logical OR value of the enumerators @ref _uart_interrupt_enable. To check
- * specific interrupts enable status, compare the return value with enumerators
+ * a specific interrupts enable status, compare the return value with enumerators
  * in @ref _uart_interrupt_enable.
- * For example, to check whether TX empty interrupt is enabled:
+ * For example, to check whether TX empty interrupt is enabled, do the following.
  * @code
  *     uint32_t enabledInterrupts = UART_GetEnabledInterrupts(UART1);
  *
@@ -394,7 +414,7 @@ uint32_t UART_GetEnabledInterrupts(UART_Type *base);
  * This function returns the UART data register address, which is mainly used by DMA/eDMA.
  *
  * @param base UART peripheral base address.
- * @return UART data register address which are used both by transmitter and receiver.
+ * @return UART data register addresses which are used both by the transmitter and the receiver.
  */
 static inline uint32_t UART_GetDataRegisterAddress(UART_Type *base)
 {
@@ -526,7 +546,7 @@ static inline void UART_WriteByte(UART_Type *base, uint8_t data)
 /*!
  * @brief Reads the RX register directly.
  *
- * This function reads data from the TX register directly. The upper layer must
+ * This function reads data from the RX register directly. The upper layer must
  * ensure that the RX register is full or that the TX FIFO has data before calling this function.
  *
  * @param base UART peripheral base address.
@@ -543,7 +563,7 @@ static inline uint8_t UART_ReadByte(UART_Type *base)
  * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
  * to have room and writes data to the TX buffer.
  *
- * @note This function does not check whether all the data has been sent out to the bus.
+ * @note This function does not check whether all data is sent out to the bus.
  * Before disabling the TX, check kUART_TransmissionCompleteFlag to ensure that the TX is
  * finished.
  *
@@ -557,15 +577,15 @@ void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length);
  * @brief Read RX data register using a blocking method.
  *
  * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
- * have data and read data from the TX register.
+ * have data, and reads data from the TX register.
  *
  * @param base UART peripheral base address.
  * @param data Start address of the buffer to store the received data.
  * @param length Size of the buffer.
- * @retval kStatus_UART_RxHardwareOverrun Receiver overrun happened while receiving data.
- * @retval kStatus_UART_NoiseError Noise error happened while receiving data.
- * @retval kStatus_UART_FramingError Framing error happened while receiving data.
- * @retval kStatus_UART_ParityError Parity error happened while receiving data.
+ * @retval kStatus_UART_RxHardwareOverrun Receiver overrun occurred while receiving data.
+ * @retval kStatus_UART_NoiseError A noise error occurred while receiving data.
+ * @retval kStatus_UART_FramingError A framing error occurred while receiving data.
+ * @retval kStatus_UART_ParityError A parity error occurred while receiving data.
  * @retval kStatus_Success Successfully received all data.
  */
 status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length);
@@ -600,16 +620,16 @@ void UART_TransferCreateHandle(UART_Type *base,
  * This function sets up the RX ring buffer to a specific UART handle.
  *
  * When the RX ring buffer is used, data received are stored into the ring buffer even when the
- * user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received
+ * user doesn't call the UART_TransferReceiveNonBlocking() API. If data is already received
  * in the ring buffer, the user can get the received data from the ring buffer directly.
  *
  * @note When using the RX ring buffer, one byte is reserved for internal use. In other
- * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ * words, if @p ringBufferSize is 32, only 31 bytes are used for saving data.
  *
  * @param base UART peripheral base address.
  * @param handle UART handle pointer.
  * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
- * @param ringBufferSize size of the ring buffer.
+ * @param ringBufferSize Size of the ring buffer.
  */
 void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize);
 
@@ -632,23 +652,23 @@ void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle);
  * function and passes the @ref kStatus_UART_TxIdle as status parameter.
  *
  * @note The kStatus_UART_TxIdle is passed to the upper layer when all data is written
- * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,
+ * to the TX register. However, it does not ensure that all data is sent out. Before disabling the TX,
  * check the kUART_TransmissionCompleteFlag to ensure that the TX is finished.
  *
  * @param base UART peripheral base address.
  * @param handle UART handle pointer.
  * @param xfer UART transfer structure. See  #uart_transfer_t.
  * @retval kStatus_Success Successfully start the data transmission.
- * @retval kStatus_UART_TxBusy Previous transmission still not finished, data not all written to TX register yet.
+ * @retval kStatus_UART_TxBusy Previous transmission still not finished; data not all written to TX register yet.
  * @retval kStatus_InvalidArgument Invalid argument.
  */
 status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer);
 
 /*!
- * @brief Aborts the interrupt driven data transmit.
+ * @brief Aborts the interrupt-driven data transmit.
  *
- * This function aborts the interrupt driven data sending. The user can get the remainBytes to find out
- * how many bytes are still not sent out.
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
+ * how many bytes are not sent out.
  *
  * @param base UART peripheral base address.
  * @param handle UART handle pointer.
@@ -656,16 +676,16 @@ status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, ua
 void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle);
 
 /*!
- * @brief Get the number of bytes that have been written to UART TX register.
+ * @brief Gets the number of bytes written to the UART TX register.
  *
- * This function gets the number of bytes that have been written to UART TX
- * register by interrupt method.
+ * This function gets the number of bytes written to the UART TX
+ * register by using the interrupt method.
  *
  * @param base UART peripheral base address.
  * @param handle UART handle pointer.
  * @param count Send bytes count.
  * @retval kStatus_NoTransferInProgress No send in progress.
- * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_InvalidArgument The parameter is invalid.
  * @retval kStatus_Success Get successfully through the parameter \p count;
  */
 status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count);
@@ -690,7 +710,7 @@ status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint3
  *
  * @param base UART peripheral base address.
  * @param handle UART handle pointer.
- * @param xfer UART transfer structure, refer to #uart_transfer_t.
+ * @param xfer UART transfer structure, see #uart_transfer_t.
  * @param receivedBytes Bytes received from the ring buffer directly.
  * @retval kStatus_Success Successfully queue the transfer into transmit queue.
  * @retval kStatus_UART_RxBusy Previous receive request is not finished.
@@ -705,7 +725,7 @@ status_t UART_TransferReceiveNonBlocking(UART_Type *base,
  * @brief Aborts the interrupt-driven data receiving.
  *
  * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
- * how many bytes not received yet.
+ * how many bytes are not received yet.
  *
  * @param base UART peripheral base address.
  * @param handle UART handle pointer.
@@ -713,7 +733,7 @@ status_t UART_TransferReceiveNonBlocking(UART_Type *base,
 void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle);
 
 /*!
- * @brief Get the number of bytes that have been received.
+ * @brief Gets the number of bytes that have been received.
  *
  * This function gets the number of bytes that have been received.
  *
@@ -739,7 +759,7 @@ void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle);
 /*!
  * @brief UART Error IRQ handle function.
  *
- * This function handle the UART error IRQ request.
+ * This function handles the UART error IRQ request.
  *
  * @param base UART peripheral base address.
  * @param handle UART handle pointer.
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart_edma.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart_edma.c
index 36734044860..c51e4934639 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart_edma.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart_edma.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -125,6 +125,8 @@ extern uint32_t UART_GetInstance(UART_Type *base);
 
 static void UART_SendEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
 {
+    assert(param);
+
     uart_edma_private_handle_t *uartPrivateHandle = (uart_edma_private_handle_t *)param;
 
     /* Avoid the warning for unused variables. */
@@ -145,6 +147,8 @@ static void UART_SendEDMACallback(edma_handle_t *handle, void *param, bool trans
 
 static void UART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
 {
+    assert(param);
+
     uart_edma_private_handle_t *uartPrivateHandle = (uart_edma_private_handle_t *)param;
 
     /* Avoid warning for unused parameters. */
@@ -165,11 +169,11 @@ static void UART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool tr
 }
 
 void UART_TransferCreateHandleEDMA(UART_Type *base,
-                           uart_edma_handle_t *handle,
-                           uart_edma_transfer_callback_t callback,
-                           void *userData,
-                           edma_handle_t *txEdmaHandle,
-                           edma_handle_t *rxEdmaHandle)
+                                   uart_edma_handle_t *handle,
+                                   uart_edma_transfer_callback_t callback,
+                                   void *userData,
+                                   edma_handle_t *txEdmaHandle,
+                                   edma_handle_t *rxEdmaHandle)
 {
     assert(handle);
 
@@ -219,17 +223,15 @@ void UART_TransferCreateHandleEDMA(UART_Type *base,
 
 status_t UART_SendEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer)
 {
+    assert(handle);
     assert(handle->txEdmaHandle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
 
     edma_transfer_config_t xferConfig;
     status_t status;
 
-    /* Return error if xfer invalid. */
-    if ((0U == xfer->dataSize) || (NULL == xfer->data))
-    {
-        return kStatus_InvalidArgument;
-    }
-
     /* If previous TX not finished. */
     if (kUART_TxBusy == handle->txState)
     {
@@ -244,6 +246,9 @@ status_t UART_SendEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfe
         EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)UART_GetDataRegisterAddress(base),
                              sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_MemoryToPeripheral);
 
+        /* Store the initially configured eDMA minor byte transfer count into the UART handle */
+        handle->nbytes = sizeof(uint8_t);
+
         /* Submit transfer. */
         EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig);
         EDMA_StartTransfer(handle->txEdmaHandle);
@@ -259,17 +264,15 @@ status_t UART_SendEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfe
 
 status_t UART_ReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer)
 {
+    assert(handle);
     assert(handle->rxEdmaHandle);
+    assert(xfer);
+    assert(xfer->data);
+    assert(xfer->dataSize);
 
     edma_transfer_config_t xferConfig;
     status_t status;
 
-    /* Return error if xfer invalid. */
-    if ((0U == xfer->dataSize) || (NULL == xfer->data))
-    {
-        return kStatus_InvalidArgument;
-    }
-
     /* If previous RX not finished. */
     if (kUART_RxBusy == handle->rxState)
     {
@@ -284,6 +287,9 @@ status_t UART_ReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_tran
         EDMA_PrepareTransfer(&xferConfig, (void *)UART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data,
                              sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory);
 
+        /* Store the initially configured eDMA minor byte transfer count into the UART handle */
+        handle->nbytes = sizeof(uint8_t);
+
         /* Submit transfer. */
         EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig);
         EDMA_StartTransfer(handle->rxEdmaHandle);
@@ -299,6 +305,7 @@ status_t UART_ReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_tran
 
 void UART_TransferAbortSendEDMA(UART_Type *base, uart_edma_handle_t *handle)
 {
+    assert(handle);
     assert(handle->txEdmaHandle);
 
     /* Disable UART TX EDMA. */
@@ -312,6 +319,7 @@ void UART_TransferAbortSendEDMA(UART_Type *base, uart_edma_handle_t *handle)
 
 void UART_TransferAbortReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle)
 {
+    assert(handle);
     assert(handle->rxEdmaHandle);
 
     /* Disable UART RX EDMA. */
@@ -325,38 +333,36 @@ void UART_TransferAbortReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle)
 
 status_t UART_TransferGetReceiveCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count)
 {
+    assert(handle);
     assert(handle->rxEdmaHandle);
+    assert(count);
 
     if (kUART_RxIdle == handle->rxState)
     {
         return kStatus_NoTransferInProgress;
     }
 
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    *count = handle->rxDataSizeAll - EDMA_GetRemainingBytes(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel);
+    *count = handle->rxDataSizeAll -
+             (uint32_t)handle->nbytes *
+                 EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel);
 
     return kStatus_Success;
 }
 
 status_t UART_TransferGetSendCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count)
 {
+    assert(handle);
     assert(handle->txEdmaHandle);
+    assert(count);
 
     if (kUART_TxIdle == handle->txState)
     {
         return kStatus_NoTransferInProgress;
     }
 
-    if (!count)
-    {
-        return kStatus_InvalidArgument;
-    }
-
-    *count = handle->txDataSizeAll - EDMA_GetRemainingBytes(handle->txEdmaHandle->base, handle->txEdmaHandle->channel);
+    *count = handle->txDataSizeAll -
+             (uint32_t)handle->nbytes *
+                 EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel);
 
     return kStatus_Success;
 }
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart_edma.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart_edma.h
index 52cc7373a9f..e411ffd7a44 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart_edma.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_uart_edma.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -39,8 +39,6 @@
  * @{
  */
 
-/*! @file*/
-
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
@@ -67,6 +65,8 @@ struct _uart_edma_handle
     edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */
     edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */
 
+    uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */
+
     volatile uint8_t txState; /*!< TX transfer state. */
     volatile uint8_t rxState; /*!< RX transfer state */
 };
@@ -87,18 +87,18 @@ extern "C" {
 /*!
  * @brief Initializes the UART handle which is used in transactional functions.
  * @param base UART peripheral base address.
- * @param handle Pointer to uart_edma_handle_t structure.
+ * @param handle Pointer to the uart_edma_handle_t structure.
  * @param callback UART callback, NULL means no callback.
  * @param userData User callback function data.
- * @param rxEdmaHandle User requested DMA handle for RX DMA transfer.
- * @param txEdmaHandle User requested DMA handle for TX DMA transfer.
+ * @param rxEdmaHandle User-requested DMA handle for RX DMA transfer.
+ * @param txEdmaHandle User-requested DMA handle for TX DMA transfer.
  */
 void UART_TransferCreateHandleEDMA(UART_Type *base,
-                           uart_edma_handle_t *handle,
-                           uart_edma_transfer_callback_t callback,
-                           void *userData,
-                           edma_handle_t *txEdmaHandle,
-                           edma_handle_t *rxEdmaHandle);
+                                   uart_edma_handle_t *handle,
+                                   uart_edma_transfer_callback_t callback,
+                                   void *userData,
+                                   edma_handle_t *txEdmaHandle,
+                                   edma_handle_t *rxEdmaHandle);
 
 /*!
  * @brief Sends data using eDMA.
@@ -109,23 +109,23 @@ void UART_TransferCreateHandleEDMA(UART_Type *base,
  * @param base UART peripheral base address.
  * @param handle UART handle pointer.
  * @param xfer UART eDMA transfer structure. See #uart_transfer_t.
- * @retval kStatus_Success if succeed, others failed.
- * @retval kStatus_UART_TxBusy Previous transfer on going.
+ * @retval kStatus_Success if succeeded; otherwise failed.
+ * @retval kStatus_UART_TxBusy Previous transfer ongoing.
  * @retval kStatus_InvalidArgument Invalid argument.
  */
 status_t UART_SendEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer);
 
 /*!
- * @brief Receive data using eDMA.
+ * @brief Receives data using eDMA.
  *
  * This function receives data using eDMA. This is a non-blocking function, which returns
  * right away. When all data is received, the receive callback function is called.
  *
  * @param base UART peripheral base address.
- * @param handle Pointer to uart_edma_handle_t structure.
+ * @param handle Pointer to the uart_edma_handle_t structure.
  * @param xfer UART eDMA transfer structure. See #uart_transfer_t.
- * @retval kStatus_Success if succeed, others failed.
- * @retval kStatus_UART_RxBusy Previous transfer on going.
+ * @retval kStatus_Success if succeeded; otherwise failed.
+ * @retval kStatus_UART_RxBusy Previous transfer ongoing.
  * @retval kStatus_InvalidArgument Invalid argument.
  */
 status_t UART_ReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer);
@@ -136,7 +136,7 @@ status_t UART_ReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_tran
  * This function aborts sent data using eDMA.
  *
  * @param base UART peripheral base address.
- * @param handle Pointer to uart_edma_handle_t structure.
+ * @param handle Pointer to the uart_edma_handle_t structure.
  */
 void UART_TransferAbortSendEDMA(UART_Type *base, uart_edma_handle_t *handle);
 
@@ -146,12 +146,12 @@ void UART_TransferAbortSendEDMA(UART_Type *base, uart_edma_handle_t *handle);
  * This function aborts receive data using eDMA.
  *
  * @param base UART peripheral base address.
- * @param handle Pointer to uart_edma_handle_t structure.
+ * @param handle Pointer to the uart_edma_handle_t structure.
  */
 void UART_TransferAbortReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle);
 
 /*!
- * @brief Get the number of bytes that have been written to UART TX register.
+ * @brief Gets the number of bytes that have been written to UART TX register.
  *
  * This function gets the number of bytes that have been written to UART TX
  * register by DMA.
@@ -166,9 +166,9 @@ void UART_TransferAbortReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle);
 status_t UART_TransferGetSendCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count);
 
 /*!
- * @brief Get the number of bytes that have been received.
+ * @brief Gets the number of received bytes.
  *
- * This function gets the number of bytes that have been received.
+ * This function gets the number of received bytes.
  *
  * @param base UART peripheral base address.
  * @param handle UART handle pointer.
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_vref.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_vref.c
index 0854ca07577..24f2d1dc280 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_vref.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_vref.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -50,8 +50,10 @@ static uint32_t VREF_GetInstance(VREF_Type *base);
 /*! @brief Pointers to VREF bases for each instance. */
 static VREF_Type *const s_vrefBases[] = VREF_BASE_PTRS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to VREF clocks for each instance. */
 static const clock_ip_name_t s_vrefClocks[] = VREF_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*******************************************************************************
  * Code
@@ -62,7 +64,7 @@ static uint32_t VREF_GetInstance(VREF_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_VREF_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_vrefBases); instance++)
     {
         if (s_vrefBases[instance] == base)
         {
@@ -70,7 +72,7 @@ static uint32_t VREF_GetInstance(VREF_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_VREF_COUNT);
+    assert(instance < ARRAY_SIZE(s_vrefBases));
 
     return instance;
 }
@@ -81,15 +83,24 @@ void VREF_Init(VREF_Type *base, const vref_config_t *config)
 
     uint8_t reg = 0U;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Ungate clock for VREF */
     CLOCK_EnableClock(s_vrefClocks[VREF_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /* Configure VREF to a known state */
 #if defined(FSL_FEATURE_VREF_HAS_CHOP_OSC) && FSL_FEATURE_VREF_HAS_CHOP_OSC
     /* Set chop oscillator bit */
     base->TRM |= VREF_TRM_CHOPEN_MASK;
 #endif /* FSL_FEATURE_VREF_HAS_CHOP_OSC */
+    /* Get current SC register */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+    reg = base->VREFH_SC;
+#else
     reg = base->SC;
+#endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+    /* Clear old buffer mode selection bits */
+    reg &= ~VREF_SC_MODE_LV_MASK;
     /* Set buffer Mode selection and Regulator enable bit */
     reg |= VREF_SC_MODE_LV(config->bufferMode) | VREF_SC_REGEN(1U);
 #if defined(FSL_FEATURE_VREF_HAS_COMPENSATION) && FSL_FEATURE_VREF_HAS_COMPENSATION
@@ -99,30 +110,51 @@ void VREF_Init(VREF_Type *base, const vref_config_t *config)
     /* Enable VREF module */
     reg |= VREF_SC_VREFEN(1U);
     /* Update bit-field from value to Status and Control register */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+    base->VREFH_SC = reg;
+#else
     base->SC = reg;
+#endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
 #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
     reg = base->VREFL_TRM;
-    /* Clear old select external voltage reference and VREFL (0.4 V) reference buffer enable bits*/
+    /* Clear old select external voltage reference and VREFL (0.4 V) reference buffer enable bits */
     reg &= ~(VREF_VREFL_TRM_VREFL_EN_MASK | VREF_VREFL_TRM_VREFL_SEL_MASK);
     /* Select external voltage reference and set VREFL (0.4 V) reference buffer enable */
     reg |= VREF_VREFL_TRM_VREFL_SEL(config->enableExternalVoltRef) | VREF_VREFL_TRM_VREFL_EN(config->enableLowRef);
     base->VREFL_TRM = reg;
 #endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
 
+#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
+    reg = base->TRM4;
+    /* Clear old select internal voltage reference bit (2.1V) */
+    reg &= ~VREF_TRM4_VREF2V1_EN_MASK;
+    /* Select internal voltage reference (2.1V) */
+    reg |= VREF_TRM4_VREF2V1_EN(config->enable2V1VoltRef);
+    base->TRM4 = reg;
+#endif /* FSL_FEATURE_VREF_HAS_TRM4 */
+
     /* Wait until internal voltage stable */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+     while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0)
+#else
     while ((base->SC & VREF_SC_VREFST_MASK) == 0)
+#endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
     {
     }
 }
 
 void VREF_Deinit(VREF_Type *base)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Gate clock for VREF */
     CLOCK_DisableClock(s_vrefClocks[VREF_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
 void VREF_GetDefaultConfig(vref_config_t *config)
 {
+    assert(config);
+
 /* Set High power buffer mode in */
 #if defined(FSL_FEATURE_VREF_MODE_LV_TYPE) && FSL_FEATURE_VREF_MODE_LV_TYPE
     config->bufferMode = kVREF_ModeHighPowerBuffer;
@@ -136,6 +168,11 @@ void VREF_GetDefaultConfig(vref_config_t *config)
     /* Set VREFL (0.4 V) reference buffer disable */
     config->enableLowRef = false;
 #endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+
+#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
+    /* Disable internal voltage reference (2.1V) */
+    config->enable2V1VoltRef = false;
+#endif /* FSL_FEATURE_VREF_HAS_TRM4 */
 }
 
 void VREF_SetTrimVal(VREF_Type *base, uint8_t trimValue)
@@ -147,10 +184,30 @@ void VREF_SetTrimVal(VREF_Type *base, uint8_t trimValue)
     reg = ((reg & ~VREF_TRM_TRIM_MASK) | VREF_TRM_TRIM(trimValue));
     base->TRM = reg;
     /* Wait until internal voltage stable */
+#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
+     while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0)
+#else
+    while ((base->SC & VREF_SC_VREFST_MASK) == 0)
+#endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+    {
+    }
+}
+
+#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
+void VREF_SetTrim2V1Val(VREF_Type *base, uint8_t trimValue)
+{
+    uint8_t reg = 0U;
+
+    /* Set TRIM bits value in voltage reference (2V1) */
+    reg = base->TRM4;
+    reg = ((reg & ~VREF_TRM4_TRIM2V1_MASK) | VREF_TRM4_TRIM2V1(trimValue));
+    base->TRM4 = reg;
+    /* Wait until internal voltage stable */
     while ((base->SC & VREF_SC_VREFST_MASK) == 0)
     {
     }
 }
+#endif /* FSL_FEATURE_VREF_HAS_TRM4 */
 
 #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
 void VREF_SetLowReferenceTrimVal(VREF_Type *base, uint8_t trimValue)
@@ -165,7 +222,8 @@ void VREF_SetLowReferenceTrimVal(VREF_Type *base, uint8_t trimValue)
     reg = ((reg & ~VREF_VREFL_TRM_VREFL_TRIM_MASK) | VREF_VREFL_TRM_VREFL_TRIM(trimValue));
     base->VREFL_TRM = reg;
     /* Wait until internal voltage stable */
-    while ((base->SC & VREF_SC_VREFST_MASK) == 0)
+
+     while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0)
     {
     }
 }
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_vref.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_vref.h
index 79378863bb6..6c6c014b913 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_vref.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_vref.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -38,7 +38,6 @@
  * @{
  */
 
-/*! @file */
 
 /******************************************************************************
  * Definitions
@@ -46,12 +45,11 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_VREF_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+#define FSL_VREF_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */
 /*@}*/
 
 /* Those macros below defined to support SoC family which have VREFL (0.4V) reference */
 #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
-#define SC VREFH_SC
 #define VREF_SC_MODE_LV VREF_VREFH_SC_MODE_LV
 #define VREF_SC_REGEN VREF_VREFH_SC_REGEN
 #define VREF_SC_VREFEN VREF_VREFH_SC_VREFEN
@@ -80,8 +78,8 @@ typedef enum _vref_buffer_mode
 {
     kVREF_ModeBandgapOnly = 0U, /*!< Bandgap on only, for stabilization and startup */
 #if defined(FSL_FEATURE_VREF_MODE_LV_TYPE) && FSL_FEATURE_VREF_MODE_LV_TYPE
-    kVREF_ModeHighPowerBuffer = 1U, /*!< High power buffer mode enabled */
-    kVREF_ModeLowPowerBuffer = 2U   /*!< Low power buffer mode enabled */
+    kVREF_ModeHighPowerBuffer = 1U, /*!< High-power buffer mode enabled */
+    kVREF_ModeLowPowerBuffer = 2U   /*!< Low-power buffer mode enabled */
 #else
     kVREF_ModeTightRegulationBuffer = 2U /*!< Tight regulation buffer enabled */
 #endif /* FSL_FEATURE_VREF_MODE_LV_TYPE */
@@ -97,6 +95,9 @@ typedef struct _vref_config
     bool enableLowRef;          /*!< Set VREFL (0.4 V) reference buffer enable or disable */
     bool enableExternalVoltRef; /*!< Select external voltage reference or not (internal) */
 #endif                          /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */
+#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
+    bool enable2V1VoltRef; /*!< Enable Internal Voltage Reference (2.1V) */
+#endif                     /* FSL_FEATURE_VREF_HAS_TRM4 */
 } vref_config_t;
 
 /******************************************************************************
@@ -115,11 +116,11 @@ extern "C" {
 /*!
  * @brief Enables the clock gate and configures the VREF module according to the configuration structure.
  *
- * This function must be called before calling all the other VREF driver functions,
+ * This function must be called before calling all other VREF driver functions,
  * read/write registers, and configurations with user-defined settings.
  * The example below shows how to set up  vref_config_t parameters and
- * how to call the VREF_Init function by passing in these parameters:
- * Example:
+ * how to call the VREF_Init function by passing in these parameters.
+ * This is an example.
  * @code
  *   vref_config_t vrefConfig;
  *   vrefConfig.bufferMode = kVREF_ModeHighPowerBuffer;
@@ -137,7 +138,7 @@ void VREF_Init(VREF_Type *base, const vref_config_t *config);
  * @brief Stops and disables the clock for the VREF module.
  *
  * This function should be called to shut down the module.
- * Example:
+ * This is an example.
  * @code
  *   vref_config_t vrefUserConfig;
  *   VREF_Init(VREF);
@@ -153,8 +154,8 @@ void VREF_Deinit(VREF_Type *base);
 /*!
  * @brief Initializes the VREF configuration structure.
  *
- * This function initializes the VREF configuration structure to a default value.
- * Example:
+ * This function initializes the VREF configuration structure to default values.
+ * This is an example.
  * @code
  *   vrefConfig->bufferMode = kVREF_ModeHighPowerBuffer;
  *   vrefConfig->enableExternalVoltRef = false;
@@ -166,9 +167,9 @@ void VREF_Deinit(VREF_Type *base);
 void VREF_GetDefaultConfig(vref_config_t *config);
 
 /*!
- * @brief Sets a TRIM value for reference voltage.
+ * @brief Sets a TRIM value for the reference voltage.
  *
- * This function sets a TRIM value for reference voltage.
+ * This function sets a TRIM value for the reference voltage.
  * Note that the TRIM value maximum is 0x3F.
  *
  * @param base VREF peripheral address.
@@ -188,13 +189,40 @@ static inline uint8_t VREF_GetTrimVal(VREF_Type *base)
 {
     return (base->TRM & VREF_TRM_TRIM_MASK);
 }
+
+#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4
+/*!
+ * @brief Sets a TRIM value for the reference voltage (2V1).
+ *
+ * This function sets a TRIM value for the reference voltage (2V1).
+ * Note that the TRIM value maximum is 0x3F.
+ *
+ * @param base VREF peripheral address.
+ * @param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)).
+ */
+void VREF_SetTrim2V1Val(VREF_Type *base, uint8_t trimValue);
+
+/*!
+ * @brief Reads the value of the TRIM meaning output voltage (2V1).
+ *
+ * This function gets the TRIM value from the VREF_TRM4 register.
+ *
+ * @param base VREF peripheral address.
+ * @return Six-bit value of trim setting.
+ */
+static inline uint8_t VREF_GetTrim2V1Val(VREF_Type *base)
+{
+    return (base->TRM4 & VREF_TRM4_TRIM2V1_MASK);
+}
+#endif /* FSL_FEATURE_VREF_HAS_TRM4 */
+
 #if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE
 
 /*!
- * @brief Sets the TRIM value for low voltage reference.
+ * @brief Sets the TRIM value for the low voltage reference.
  *
  * This function sets the TRIM value for low reference voltage.
- * NOTE:
+ * Note the following.
  *      - The TRIM value maximum is 0x05U
  *      - The values 111b and 110b are not valid/allowed.
  *
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_wdog.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_wdog.c
index 489798ca889..781ac133c1a 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_wdog.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_wdog.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_wdog.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_wdog.h
index 949a9a8e046..580adb95a0f 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_wdog.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_wdog.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -33,11 +33,10 @@
 #include "fsl_common.h"
 
 /*!
- * @addtogroup wdog_driver
+ * @addtogroup wdog
  * @{
  */
 
-/*! @file */
 
 /*******************************************************************************
  * Definitions
@@ -136,7 +135,7 @@ typedef struct _wdog_test_config
  */
 enum _wdog_interrupt_enable_t
 {
-    kWDOG_InterruptEnable = WDOG_STCTRLH_IRQRSTEN_MASK, /*!< WDOG timeout will generate interrupt before reset*/
+    kWDOG_InterruptEnable = WDOG_STCTRLH_IRQRSTEN_MASK, /*!< WDOG timeout generates an interrupt before reset*/
 };
 
 /*!
@@ -164,10 +163,10 @@ extern "C" {
  */
 
 /*!
- * @brief Initializes WDOG configure sturcture.
+ * @brief Initializes the WDOG configuration sturcture.
  *
- * This function initializes the WDOG configure structure to default value. The default
- * value are:
+ * This function initializes the WDOG configuration structure to default values. The default
+ * values are as follows.
  * @code
  *   wdogConfig->enableWdog = true;
  *   wdogConfig->clockSource = kWDOG_LpoClockSource;
@@ -182,7 +181,7 @@ extern "C" {
  *   wdogConfig->timeoutValue = 0xFFFFU;
  * @endcode
  *
- * @param config Pointer to WDOG config structure.
+ * @param config Pointer to the WDOG configuration structure.
  * @see wdog_config_t
  */
 void WDOG_GetDefaultConfig(wdog_config_t *config);
@@ -191,10 +190,10 @@ void WDOG_GetDefaultConfig(wdog_config_t *config);
  * @brief Initializes the WDOG.
  *
  * This function initializes the WDOG. When called, the WDOG runs according to the configuration.
- * If user wants to reconfigure WDOG without forcing a reset first, enableUpdate must be set to true
- * in configuration.
+ * To reconfigure WDOG without forcing a reset first, enableUpdate must be set to true
+ * in the configuration.
  *
- * Example:
+ * This is an example.
  * @code
  *   wdog_config_t config;
  *   WDOG_GetDefaultConfig(&config);
@@ -212,18 +211,18 @@ void WDOG_Init(WDOG_Type *base, const wdog_config_t *config);
  * @brief Shuts down the WDOG.
  *
  * This function shuts down the WDOG.
- * Make sure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled.
+ * Ensure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which indicates that the register update is enabled.
  */
 void WDOG_Deinit(WDOG_Type *base);
 
 /*!
- * @brief Configures WDOG functional test.
+ * @brief Configures the WDOG functional test.
  *
  * This function is used to configure the WDOG functional test. When called, the WDOG goes into test mode
  * and runs according to the configuration.
- * Make sure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled.
+ * Ensure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled.
  *
- * Example:
+ * This is an example.
  * @code
  *   wdog_test_config_t test_config;
  *   test_config.testMode = kWDOG_QuickTest;
@@ -259,9 +258,9 @@ static inline void WDOG_Enable(WDOG_Type *base)
 /*!
  * @brief Disables the WDOG module.
  *
- * This function write value into WDOG_STCTRLH register to disable the WDOG, it is a write-once register,
- * make sure that the WCT window is still open and this register has not been written in this WCT
- * while this function is called.
+ * This function writes a value into the WDOG_STCTRLH register to disable the WDOG. It is a write-once register.
+ * Ensure that the WCT window is still open and that register has not been written to in this WCT
+ * while the function is called.
  *
  * @param base WDOG peripheral base address
  */
@@ -271,15 +270,15 @@ static inline void WDOG_Disable(WDOG_Type *base)
 }
 
 /*!
- * @brief Enable WDOG interrupt.
+ * @brief Enables the WDOG interrupt.
  *
- * This function write value into WDOG_STCTRLH register to enable WDOG interrupt, it is a write-once register,
- * make sure that the WCT window is still open and this register has not been written in this WCT
- * while this function is called.
+ * This function writes a value into the WDOG_STCTRLH register to enable the WDOG interrupt. It is a write-once register.
+ * Ensure that the WCT window is still open and the register has not been written to in this WCT
+ * while the function is called.
  *
  * @param base WDOG peripheral base address
  * @param mask The interrupts to enable
- *        The parameter can be combination of the following source if defined:
+ *        The parameter can be combination of the following source if defined.
  *        @arg kWDOG_InterruptEnable
  */
 static inline void WDOG_EnableInterrupts(WDOG_Type *base, uint32_t mask)
@@ -288,15 +287,15 @@ static inline void WDOG_EnableInterrupts(WDOG_Type *base, uint32_t mask)
 }
 
 /*!
- * @brief Disable WDOG interrupt.
+ * @brief Disables the WDOG interrupt.
  *
- * This function write value into WDOG_STCTRLH register to disable WDOG interrupt, it is a write-once register,
- * make sure that the WCT window is still open and this register has not been written in this WCT
- * while this function is called.
+ * This function writes a value into the WDOG_STCTRLH register to disable the WDOG interrupt. It is a write-once register.
+ * Ensure that the WCT window is still open and the register has not been written to in this WCT
+ * while the function is called.
  *
  * @param base WDOG peripheral base address
  * @param mask The interrupts to disable
- *        The parameter can be combination of the following source if defined:
+ *        The parameter can be combination of the following source if defined.
  *        @arg kWDOG_InterruptEnable
  */
 static inline void WDOG_DisableInterrupts(WDOG_Type *base, uint32_t mask)
@@ -305,50 +304,50 @@ static inline void WDOG_DisableInterrupts(WDOG_Type *base, uint32_t mask)
 }
 
 /*!
- * @brief Gets WDOG all status flags.
+ * @brief Gets the WDOG all status flags.
  *
  * This function gets all status flags.
  *
- * Example for getting Running Flag:
+ * This is an example for getting the Running Flag.
  * @code
  *   uint32_t status;
- *   status = WDOG_GetStatusFlags(wdog_base) & kWDOG_RunningFlag;
+ *   status = WDOG_GetStatusFlags (wdog_base) & kWDOG_RunningFlag;
  * @endcode
  * @param base        WDOG peripheral base address
  * @return            State of the status flag: asserted (true) or not-asserted (false).@see _wdog_status_flags_t
- *                    - true: related status flag has been set.
- *                    - false: related status flag is not set.
+ *                    - true: a related status flag has been set.
+ *                    - false: a related status flag is not set.
  */
 uint32_t WDOG_GetStatusFlags(WDOG_Type *base);
 
 /*!
- * @brief Clear WDOG flag.
+ * @brief Clears the WDOG flag.
  *
- * This function clears WDOG status flag.
+ * This function clears the WDOG status flag.
  *
- * Example for clearing timeout(interrupt) flag:
+ * This is an example for clearing the timeout (interrupt) flag.
  * @code
  *   WDOG_ClearStatusFlags(wdog_base,kWDOG_TimeoutFlag);
  * @endcode
  * @param base        WDOG peripheral base address
  * @param mask        The status flags to clear.
- *                    The parameter could be any combination of the following values:
+ *                    The parameter could be any combination of the following values.
  *                    kWDOG_TimeoutFlag
  */
 void WDOG_ClearStatusFlags(WDOG_Type *base, uint32_t mask);
 
 /*!
- * @brief Set the WDOG timeout value.
+ * @brief Sets the WDOG timeout value.
  *
  * This function sets the timeout value.
  * It should be ensured that the time-out value for the WDOG is always greater than
  * 2xWCT time + 20 bus clock cycles.
- * This function write value into WDOG_TOVALH and WDOG_TOVALL registers which are wirte-once.
- * Make sure the WCT window is still open and these two registers have not been written in this WCT
- * while this function is called.
+ * This function writes a value into WDOG_TOVALH and WDOG_TOVALL registers which are wirte-once.
+ * Ensure the WCT window is still open and the two registers have not been written to in this WCT
+ * while the function is called.
  *
  * @param base WDOG peripheral base address
- * @param timeoutCount WDOG timeout value, count of WDOG clock tick.
+ * @param timeoutCount WDOG timeout value; count of WDOG clock tick.
  */
 static inline void WDOG_SetTimeoutValue(WDOG_Type *base, uint32_t timeoutCount)
 {
@@ -360,9 +359,9 @@ static inline void WDOG_SetTimeoutValue(WDOG_Type *base, uint32_t timeoutCount)
  * @brief Sets the WDOG window value.
  *
  * This function sets the WDOG window value.
- * This function write value into WDOG_WINH and WDOG_WINL registers which are wirte-once.
- * Make sure the WCT window is still open and these two registers have not been written in this WCT
- * while this function is called.
+ * This function writes a value into WDOG_WINH and WDOG_WINL registers which are wirte-once.
+ * Ensure the WCT window is still open and the two registers have not been written to in this WCT
+ * while the function is called.
  *
  * @param base WDOG peripheral base address
  * @param windowValue WDOG window value.
@@ -378,7 +377,7 @@ static inline void WDOG_SetWindowValue(WDOG_Type *base, uint32_t windowValue)
  *
  * This function unlocks the WDOG register written.
  * Before starting the unlock sequence and following congfiguration, disable the global interrupts.
- * Otherwise, an interrupt could effectively invalidate the unlock sequence and the WCT may expire,
+ * Otherwise, an interrupt may invalidate the unlocking sequence and the WCT may expire.
  * After the configuration finishes, re-enable the global interrupts.
  *
  * @param base WDOG peripheral base address
@@ -393,7 +392,7 @@ static inline void WDOG_Unlock(WDOG_Type *base)
  * @brief Refreshes the WDOG timer.
  *
  * This function feeds the WDOG.
- * This function should be called before WDOG timer is in timeout. Otherwise, a reset is asserted.
+ * This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted.
  *
  * @param base WDOG peripheral base address
  */
@@ -405,7 +404,7 @@ void WDOG_Refresh(WDOG_Type *base);
  * This function gets the WDOG reset count value.
  *
  * @param base WDOG peripheral base address
- * @return     WDOG reset count value
+ * @return     WDOG reset count value.
  */
 static inline uint16_t WDOG_GetResetCount(WDOG_Type *base)
 {
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/spi_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/spi_api.c
index 8a65bd4f22a..2ca04b99c89 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/spi_api.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/spi_api.c
@@ -122,13 +122,17 @@ int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
                            char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
-    for (int i = 0; i < total; i++) {
-        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
-        char in = spi_master_write(obj, out);
-        if (i < rx_length) {
-            rx_buffer[i] = in;
-        }
-    }
+    // Default write is done in each and every call, in future can create HAL API instead
+    DSPI_SetDummyData(spi_address[obj->instance], write_fill);
+
+    DSPI_MasterTransferBlocking(spi_address[obj->instance], &(dspi_transfer_t){
+          .txData = (uint8_t *)tx_buffer,
+          .rxData = (uint8_t *)rx_buffer,
+          .dataSize = total,
+          .configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous,
+    });
+
+    DSPI_ClearStatusFlags(spi_address[obj->instance], kDSPI_RxFifoDrainRequestFlag | kDSPI_EndOfQueueFlag);
 
     return total;
 }
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/us_ticker.c
index 1be03651e44..dc6ab710f40 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/us_ticker.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/us_ticker.c
@@ -21,6 +21,16 @@
 
 static int us_ticker_inited = 0;
 
+static void pit_isr(void)
+{
+    PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK);
+    PIT_ClearStatusFlags(PIT, kPIT_Chnl_2, PIT_TFLG_TIF_MASK);
+    PIT_StopTimer(PIT, kPIT_Chnl_2);
+    PIT_StopTimer(PIT, kPIT_Chnl_3);
+
+    us_ticker_irq_handler();
+}
+
 void us_ticker_init(void)
 {
     if (us_ticker_inited) {
@@ -47,7 +57,7 @@ void us_ticker_init(void)
     //Ticker
     PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1);
     PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true);
-    NVIC_SetVector(PIT3_IRQn, (uint32_t)us_ticker_irq_handler);
+    NVIC_SetVector(PIT3_IRQn, (uint32_t)pit_isr);
     NVIC_EnableIRQ(PIT3_IRQn);
 }
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/us_ticker.c
index 1be03651e44..dc6ab710f40 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/us_ticker.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/us_ticker.c
@@ -21,6 +21,16 @@
 
 static int us_ticker_inited = 0;
 
+static void pit_isr(void)
+{
+    PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK);
+    PIT_ClearStatusFlags(PIT, kPIT_Chnl_2, PIT_TFLG_TIF_MASK);
+    PIT_StopTimer(PIT, kPIT_Chnl_2);
+    PIT_StopTimer(PIT, kPIT_Chnl_3);
+
+    us_ticker_irq_handler();
+}
+
 void us_ticker_init(void)
 {
     if (us_ticker_inited) {
@@ -47,7 +57,7 @@ void us_ticker_init(void)
     //Ticker
     PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1);
     PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true);
-    NVIC_SetVector(PIT3_IRQn, (uint32_t)us_ticker_irq_handler);
+    NVIC_SetVector(PIT3_IRQn, (uint32_t)pit_isr);
     NVIC_EnableIRQ(PIT3_IRQn);
 }
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/us_ticker.c
index 6af039a5a37..43f7dc0bb4d 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/us_ticker.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/us_ticker.c
@@ -22,6 +22,14 @@
 
 static int us_ticker_inited = 0;
 
+static void lptmr_isr(void)
+{
+    LPTMR_ClearStatusFlags(LPTMR0, kLPTMR_TimerCompareFlag);
+    LPTMR_StopTimer(LPTMR0);
+
+    us_ticker_irq_handler();
+}
+
 void us_ticker_init(void)
 {
     if (us_ticker_inited) {
@@ -56,7 +64,7 @@ void us_ticker_init(void)
     busClock = CLOCK_GetFreq(kCLOCK_McgInternalRefClk);
     LPTMR_SetTimerPeriod(LPTMR0, busClock / 1000000 - 1);
     /* Set interrupt handler */
-    NVIC_SetVector(LPTMR0_IRQn, (uint32_t)us_ticker_irq_handler);
+    NVIC_SetVector(LPTMR0_IRQn, (uint32_t)lptmr_isr);
     NVIC_EnableIRQ(LPTMR0_IRQn);
 }
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/us_ticker.c
index 6af039a5a37..43f7dc0bb4d 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/us_ticker.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/us_ticker.c
@@ -22,6 +22,14 @@
 
 static int us_ticker_inited = 0;
 
+static void lptmr_isr(void)
+{
+    LPTMR_ClearStatusFlags(LPTMR0, kLPTMR_TimerCompareFlag);
+    LPTMR_StopTimer(LPTMR0);
+
+    us_ticker_irq_handler();
+}
+
 void us_ticker_init(void)
 {
     if (us_ticker_inited) {
@@ -56,7 +64,7 @@ void us_ticker_init(void)
     busClock = CLOCK_GetFreq(kCLOCK_McgInternalRefClk);
     LPTMR_SetTimerPeriod(LPTMR0, busClock / 1000000 - 1);
     /* Set interrupt handler */
-    NVIC_SetVector(LPTMR0_IRQn, (uint32_t)us_ticker_irq_handler);
+    NVIC_SetVector(LPTMR0_IRQn, (uint32_t)lptmr_isr);
     NVIC_EnableIRQ(LPTMR0_IRQn);
 }
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/us_ticker.c
index 613483583eb..39142267596 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/us_ticker.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/us_ticker.c
@@ -21,6 +21,16 @@
 
 static int us_ticker_inited = 0;
 
+static void pit_isr(void)
+{
+    PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK);
+    PIT_ClearStatusFlags(PIT, kPIT_Chnl_2, PIT_TFLG_TIF_MASK);
+    PIT_StopTimer(PIT, kPIT_Chnl_2);
+    PIT_StopTimer(PIT, kPIT_Chnl_3);
+
+    us_ticker_irq_handler();
+}
+
 void us_ticker_init(void)
 {
     if (us_ticker_inited) {
@@ -47,7 +57,7 @@ void us_ticker_init(void)
     //Ticker
     PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1);
     PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true);
-    NVIC_SetVector(PIT0_IRQn, (uint32_t)us_ticker_irq_handler);
+    NVIC_SetVector(PIT0_IRQn, (uint32_t)pit_isr);
     NVIC_EnableIRQ(PIT0_IRQn);
 }
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_ARM_STD/MKW24D512xxx5.sct b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_ARM_STD/MKW24D512xxx5.sct
index 0cee6416439..7bf8db50b21 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_ARM_STD/MKW24D512xxx5.sct
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_ARM_STD/MKW24D512xxx5.sct
@@ -51,14 +51,22 @@
   #define __ram_vector_table_size__    0x00000000
 #endif
 
-#define m_interrupts_start             0x00000000
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x80000
+#endif
+
+#define m_interrupts_start             MBED_APP_START
 #define m_interrupts_size              0x00000400
 
-#define m_flash_config_start           0x00000400
+#define m_flash_config_start           MBED_APP_START + 0x400
 #define m_flash_config_size            0x00000010
 
-#define m_text_start                   0x00000410
-#define m_text_size                    0x0007FBF0
+#define m_text_start                   MBED_APP_START + 0x410
+#define m_text_size                    MBED_APP_SIZE - 0x410
 
 #define m_interrupts_ram_start         0x1FFF8000
 #define m_interrupts_ram_size          __ram_vector_table_size__
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_GCC_ARM/MKW24D512xxx5.ld b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_GCC_ARM/MKW24D512xxx5.ld
index 3ee0095bd31..bc648a957b0 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_GCC_ARM/MKW24D512xxx5.ld
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_GCC_ARM/MKW24D512xxx5.ld
@@ -58,6 +58,14 @@ __stack_size__ = 0x400;
  * heap and the page heap in uVisor applications. */
 __heap_size__ = 0x4000;
 
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x80000
+#endif
+
 HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
 STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
 M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;
@@ -65,9 +73,9 @@ M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0;
 /* Specify the memory areas */
 MEMORY
 {
-  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000400
-  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010
-  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x0007FBF0
+  m_interrupts          (RX)  : ORIGIN = MBED_APP_START, LENGTH = 0x400
+  m_flash_config        (RX)  : ORIGIN = MBED_APP_START + 0x400, LENGTH = 0x10
+  m_text                (RX)  : ORIGIN = MBED_APP_START + 0x410, LENGTH = MBED_APP_SIZE - 0x410
   m_data                (RW)  : ORIGIN = 0x1FFF8000, LENGTH = 0x00008000
   m_data_2              (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00008000
 }
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_IAR/MKW24D512xxx5.icf b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_IAR/MKW24D512xxx5.icf
index ed39474da92..28794497a94 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_IAR/MKW24D512xxx5.icf
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_IAR/MKW24D512xxx5.icf
@@ -48,17 +48,25 @@ define symbol __ram_vector_table__ = 1;
 define symbol __stack_size__=0x2000;
 define symbol __heap_size__=0x4000;
 
+if (!isdefinedsymbol(MBED_APP_START)) {
+    define symbol MBED_APP_START = 0;
+}
+
+if (!isdefinedsymbol(MBED_APP_SIZE)) {
+    define symbol MBED_APP_SIZE = 0x80000;
+}
+
 define symbol __ram_vector_table_size__ =  isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
 define symbol __ram_vector_table_offset__ =  isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;
 
-define symbol m_interrupts_start       = 0x00000000;
-define symbol m_interrupts_end         = 0x000003FF;
+define symbol m_interrupts_start       = MBED_APP_START;
+define symbol m_interrupts_end         = MBED_APP_START + 0x3FF;
 
-define symbol m_flash_config_start     = 0x00000400;
-define symbol m_flash_config_end       = 0x0000040F;
+define symbol m_flash_config_start     = MBED_APP_START + 0x400;
+define symbol m_flash_config_end       = MBED_APP_START + 0x40F;
 
-define symbol m_text_start             = 0x00000410;
-define symbol m_text_end               = 0x0007FFFF;
+define symbol m_text_start             = MBED_APP_START + 0x410;
+define symbol m_text_end               = MBED_APP_START + MBED_APP_SIZE - 1;
 
 define symbol m_interrupts_ram_start   = 0x1FFF8000;
 define symbol m_interrupts_ram_end     = 0x1FFF8000 + __ram_vector_table_offset__;
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c
index 1be03651e44..dc6ab710f40 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c
@@ -21,6 +21,16 @@
 
 static int us_ticker_inited = 0;
 
+static void pit_isr(void)
+{
+    PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK);
+    PIT_ClearStatusFlags(PIT, kPIT_Chnl_2, PIT_TFLG_TIF_MASK);
+    PIT_StopTimer(PIT, kPIT_Chnl_2);
+    PIT_StopTimer(PIT, kPIT_Chnl_3);
+
+    us_ticker_irq_handler();
+}
+
 void us_ticker_init(void)
 {
     if (us_ticker_inited) {
@@ -47,7 +57,7 @@ void us_ticker_init(void)
     //Ticker
     PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1);
     PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true);
-    NVIC_SetVector(PIT3_IRQn, (uint32_t)us_ticker_irq_handler);
+    NVIC_SetVector(PIT3_IRQn, (uint32_t)pit_isr);
     NVIC_EnableIRQ(PIT3_IRQn);
 }
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/us_ticker.c
index b376ce0d260..5246cf8d62f 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/us_ticker.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/us_ticker.c
@@ -22,7 +22,16 @@
 
 static int us_ticker_inited = 0;
 
-void us_ticker_init(void) {
+static void lptmr_isr(void)
+{
+    LPTMR_ClearStatusFlags(LPTMR0, kLPTMR_TimerCompareFlag);
+    LPTMR_StopTimer(LPTMR0);
+
+    us_ticker_irq_handler();
+}
+
+void us_ticker_init(void) 
+{
     if (us_ticker_inited) {
         return;
     }
@@ -55,12 +64,13 @@ void us_ticker_init(void) {
     busClock = CLOCK_GetFreq(kCLOCK_McgInternalRefClk);
     LPTMR_SetTimerPeriod(LPTMR0, busClock / 1000000 - 1);
     /* Set interrupt handler */
-    NVIC_SetVector(LPTMR0_IRQn, (uint32_t)us_ticker_irq_handler);
+    NVIC_SetVector(LPTMR0_IRQn, (uint32_t)lptmr_isr);
     NVIC_EnableIRQ(LPTMR0_IRQn);
 }
 
 
-uint32_t us_ticker_read() {
+uint32_t us_ticker_read() 
+{
     if (!us_ticker_inited) {
         us_ticker_init();
     }
@@ -68,15 +78,18 @@ uint32_t us_ticker_read() {
     return ~(PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_1));
 }
 
-void us_ticker_disable_interrupt(void) {
+void us_ticker_disable_interrupt(void) 
+{
     LPTMR_DisableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable);
 }
 
-void us_ticker_clear_interrupt(void) {
+void us_ticker_clear_interrupt(void) 
+{
     LPTMR_ClearStatusFlags(LPTMR0, kLPTMR_TimerCompareFlag);
 }
 
-void us_ticker_set_interrupt(timestamp_t timestamp) {
+void us_ticker_set_interrupt(timestamp_t timestamp) 
+{
     uint32_t delta = timestamp - us_ticker_read();
     LPTMR_StopTimer(LPTMR0);
     LPTMR_SetTimerPeriod(LPTMR0, (uint32_t)delta);
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/us_ticker.c
index 1be03651e44..dc6ab710f40 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/us_ticker.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/us_ticker.c
@@ -21,6 +21,16 @@
 
 static int us_ticker_inited = 0;
 
+static void pit_isr(void)
+{
+    PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK);
+    PIT_ClearStatusFlags(PIT, kPIT_Chnl_2, PIT_TFLG_TIF_MASK);
+    PIT_StopTimer(PIT, kPIT_Chnl_2);
+    PIT_StopTimer(PIT, kPIT_Chnl_3);
+
+    us_ticker_irq_handler();
+}
+
 void us_ticker_init(void)
 {
     if (us_ticker_inited) {
@@ -47,7 +57,7 @@ void us_ticker_init(void)
     //Ticker
     PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1);
     PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true);
-    NVIC_SetVector(PIT3_IRQn, (uint32_t)us_ticker_irq_handler);
+    NVIC_SetVector(PIT3_IRQn, (uint32_t)pit_isr);
     NVIC_EnableIRQ(PIT3_IRQn);
 }
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c
index 9594b3dd486..a4b32f8c3f2 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c
@@ -21,6 +21,16 @@
 
 static int us_ticker_inited = 0;
 
+static void pit_isr(void)
+{
+    PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK);
+    PIT_ClearStatusFlags(PIT, kPIT_Chnl_2, PIT_TFLG_TIF_MASK);
+    PIT_StopTimer(PIT, kPIT_Chnl_2);
+    PIT_StopTimer(PIT, kPIT_Chnl_3);
+
+    us_ticker_irq_handler();
+}
+
 void us_ticker_init(void)
 {
     if (us_ticker_inited) {
@@ -47,7 +57,7 @@ void us_ticker_init(void)
     //Ticker
     PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1);
     PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true);
-    NVIC_SetVector(PIT3_IRQn, (uint32_t)us_ticker_irq_handler);
+    NVIC_SetVector(PIT3_IRQn, (uint32_t)pit_isr);
     NVIC_EnableIRQ(PIT3_IRQn);
 }
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/us_ticker.c
index 1be03651e44..dc6ab710f40 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/us_ticker.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/us_ticker.c
@@ -21,6 +21,16 @@
 
 static int us_ticker_inited = 0;
 
+static void pit_isr(void)
+{
+    PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK);
+    PIT_ClearStatusFlags(PIT, kPIT_Chnl_2, PIT_TFLG_TIF_MASK);
+    PIT_StopTimer(PIT, kPIT_Chnl_2);
+    PIT_StopTimer(PIT, kPIT_Chnl_3);
+
+    us_ticker_irq_handler();
+}
+
 void us_ticker_init(void)
 {
     if (us_ticker_inited) {
@@ -47,7 +57,7 @@ void us_ticker_init(void)
     //Ticker
     PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1);
     PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true);
-    NVIC_SetVector(PIT3_IRQn, (uint32_t)us_ticker_irq_handler);
+    NVIC_SetVector(PIT3_IRQn, (uint32_t)pit_isr);
     NVIC_EnableIRQ(PIT3_IRQn);
 }
 
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/lp_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/lp_ticker.c
index 18fc6e1dfe3..7b57feaf476 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/lp_ticker.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/lp_ticker.c
@@ -139,6 +139,11 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
 
     /* Checking if LPTRM can handle this sleep */
     delta_ticks = USEC_TO_COUNT(delta_us, CLOCK_GetFreq(kCLOCK_Er32kClk));
+    if (delta_ticks == 0) {
+        /* The requested delay is less than the minimum resolution of this counter */
+        delta_ticks = 1;
+    }
+
     if (delta_ticks > MAX_LPTMR_SLEEP) {
         /* Using RTC if wait time is over 16b (2s @32kHz) */
         uint32_t delta_sec;
@@ -154,6 +159,11 @@ void lp_ticker_set_interrupt(timestamp_t timestamp)
         /* Set aditional, subsecond, sleep time */
         if (delta_us) {
             lptmr_schedule = USEC_TO_COUNT(delta_us, CLOCK_GetFreq(kCLOCK_Er32kClk));
+            if (lptmr_schedule == 0) {
+                /* The requested delay is less than the minimum resolution of this counter */
+                lptmr_schedule = 1;
+            }
+
         }
     } else {
         /* Below RTC resolution using LPTMR */
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/rtc_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/rtc_api.c
index 5d7ae20d676..5de7164ac1a 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/rtc_api.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/rtc_api.c
@@ -57,9 +57,6 @@ time_t rtc_read(void)
 
 void rtc_write(time_t t)
 {
-    if (t == 0) {
-        t = 1;
-    }
     RTC_StopTimer(RTC);
     RTC->TSR = t;
     RTC_StartTimer(RTC);
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct
index 3a268542b04..0d10720cf1c 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct
@@ -19,7 +19,7 @@ LR_IROM1 0x1B000 0x0025000  {
    .ANY (+RO)
   }
   RW_IRAM0 0x20002ef8 UNINIT 0x000000c0  { ;no init section
-        *(noinit)
+        *(*noinit)
   }
   RW_IRAM1 0x20002FB8 0x00005048  {
    .ANY (+RW +ZI)
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct
index ef516aa805a..7baf111cbe5 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct
@@ -19,7 +19,7 @@ LR_IROM1 0x18000 0x0028000  {
    .ANY (+RO)
   }
   RW_IRAM0 0x20002000 UNINIT 0x000000c0  { ;no init section
-        *(noinit)
+        *(*noinit)
   }
   RW_IRAM1 0x200020C0 0x00001F40  {
    .ANY (+RW +ZI)
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct
index 585ae2080d8..96fbdd496b0 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct
@@ -19,7 +19,7 @@ LR_IROM1 0x0001B000 0x0025000  {
    .ANY (+RO)
   }
   RW_IRAM0 0x20002ef8 UNINIT 0x000000c0  { ;no init section
-        *(noinit)
+        *(*noinit)
   }
   RW_IRAM1 0x20002FB8 0x00001048  {
    .ANY (+RW +ZI)
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/PinNames.h
new file mode 100644
index 00000000000..0798e678c1e
--- /dev/null
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/PinNames.h
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ *   1. Redistributions of source code must retain the above copyright notice, this list
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
+ *      integrated circuit in a product or a software update for such product, must reproduce
+ *      the above copyright notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
+ *      used to endorse or promote products derived from this software without specific prior
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse
+ *      engineered, decompiled, modified and/or disassembled.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  3
+
+typedef enum {
+    p0  = 0,
+    p1  = 1,
+    p2  = 2,
+    p3  = 3,
+    p4  = 4,
+    p5  = 5,
+    p6  = 6,
+    p7  = 7,
+    p8  = 8,
+    p9  = 9,
+    p10 = 10,
+    p11 = 11,
+    p12 = 12,
+    p13 = 13,
+    p14 = 14,
+    p15 = 15,
+    p16 = 16,
+    p17 = 17,
+    p18 = 18,
+    p19 = 19,
+    p20 = 20,
+    p21 = 21,
+    p22 = 22,
+    p23 = 23,
+    p24 = 24,
+    p25 = 25,
+    p26 = 26,
+    p27 = 27,
+    p28 = 28,
+    p29 = 29,
+    p30 = 30,
+    p31 = 31,
+
+    P0_0  = p0,
+    P0_1  = p1,
+    P0_2  = p2,
+    P0_3  = p3,
+    P0_4  = p4,
+    P0_5  = p5,
+    P0_6  = p6,
+    P0_7  = p7,
+
+    P0_8  = p8,
+    P0_9  = p9,
+    P0_10 = p10,
+    P0_11 = p11,
+    P0_12 = p12,
+    P0_13 = p13,
+    P0_14 = p14,
+    P0_15 = p15,
+
+    P0_16 = p16,
+    P0_17 = p17,
+    P0_18 = p18,
+    P0_19 = p19,
+    P0_20 = p20,
+    P0_21 = p21,
+    P0_22 = p22,
+    P0_23 = p23,
+
+    P0_24 = p24,
+    P0_25 = p25,
+    P0_26 = p26,
+    P0_27 = p27,
+    P0_28 = p28,
+    P0_29 = p29,
+    P0_30 = p30,
+
+    LED1 = p11,
+    LED2 = p11,
+    LED3 = p11,
+    LED4 = p11,
+
+    RX_PIN_NUMBER  = p30,
+    TX_PIN_NUMBER  = p29,
+    CTS_PIN_NUMBER = p28,
+    RTS_PIN_NUMBER = p2,
+
+    // mBed interface Pins
+    USBTX = TX_PIN_NUMBER,
+    USBRX = RX_PIN_NUMBER,
+
+    SPI_PSELMOSI0 = p6,
+    SPI_PSELMISO0 = p7,
+    SPI_PSELSS0   = p3,
+    SPI_PSELSCK0  = p8,
+
+    SPI_PSELMOSI1 = p29,
+    SPI_PSELMISO1 = p30,
+    SPI_PSELSS1   = p28,
+    SPI_PSELSCK1  = p2,
+
+    SPIS_PSELMOSI = p29,
+    SPIS_PSELMISO = p30,
+    SPIS_PSELSS   = p28,
+    SPIS_PSELSCK  = p2,
+
+    I2C_SDA0 = p28,
+    I2C_SCL0 = p2,
+
+    D0 = p30,
+    D1 = p29,
+    D2 = p28,
+    D3 = p2,
+
+    D4 = p3,
+    D5 = p6,
+    D6 = p7,
+    D7 = p8,
+    D8 = p21,
+
+    D9 = p4,
+    D10 = p5,
+
+    D13 = p11,
+
+    A0 = p28,
+    A1 = p29,
+    A2 = p30,
+    A3 = p2,
+    A4 = p4,
+    A5 = p5,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+    PullNone = 0,
+    PullDown = 1,
+    PullUp = 3,
+    PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/device.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/device.h
new file mode 100644
index 00000000000..493844b8012
--- /dev/null
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/device.h
@@ -0,0 +1,23 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#include "objects.h"
+
+#endif
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/nRF52832.sct b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/nRF52832.sct
index 3bb13ec74ac..33da60733cd 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/nRF52832.sct
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/nRF52832.sct
@@ -19,7 +19,7 @@ LR_IROM1 0x1C000 0x0064000  {
    .ANY (+RO)
   }
   RW_IRAM0 0x20002EF8 UNINIT 0x000000D8  { ;no init section
-        *(noinit)
+        *(*noinit)
   }
   RW_IRAM1 0x20002FD0 0x0000D030  {
    .ANY (+RW +ZI)
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52832.sct b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52832.sct
index 37b77b1dd25..496f79dfea4 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52832.sct
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52832.sct
@@ -5,7 +5,7 @@ LR_IROM1 0x21000 0x00DF000  {
    .ANY (+RO)
   }
   RW_IRAM0 0x20003288 UNINIT 0x000000F8  { ;no init section
-        *(noinit)
+        *(*noinit)
   }
   RW_IRAM1 0x20003380 0x0003cc80  {
    .ANY (+RW +ZI)
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c
index ec73afa6a3f..9e12311e8e3 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c
@@ -33,7 +33,6 @@
 typedef struct {
     bool         used_as_gpio : 1;
     PinDirection direction    : 1;
-    bool         init_high    : 1;
     PinMode      pull         : 2;
     bool         used_as_irq  : 1;
     bool         irq_fall     : 1;
@@ -151,12 +150,12 @@ static void gpio_apply_config(uint8_t pin)
                         cfg.pull = NRF_GPIO_PIN_NOPULL;
                     break;
                 }
-                nrf_drv_gpiote_in_init(pin, &cfg, NULL);
+                nrf_gpio_cfg_input(pin,cfg.pull);
             }
         }
         else {
             // Configure as output.
-            nrf_drv_gpiote_out_config_t cfg = GPIOTE_CONFIG_OUT_SIMPLE(m_gpio_cfg[pin].init_high);
+            nrf_drv_gpiote_out_config_t cfg = GPIOTE_CONFIG_OUT_SIMPLE(nrf_gpio_pin_out_read(pin));
             nrf_drv_gpiote_out_init(pin, &cfg);
         }
         m_gpio_initialized |= ((gpio_mask_t)1UL << pin);
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/i2c_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/i2c_api.c
index e8d07601fcd..c6629680174 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/i2c_api.c
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/i2c_api.c
@@ -50,10 +50,14 @@
 #include "nrf_gpio.h"
 #include "nrf_delay.h"
 
-// An arbitrary value used as the counter in loops waiting for given event
-// (e.g. STOPPED), needed to avoid infinite loops (and not involve any timers
-// or tickers).
-#define TIMEOUT_VALUE  1000
+#include "us_ticker_api.h"
+
+// An arbitrary value used as the timeout in loops waiting for given event
+// (e.g. STOPPED), needed to avoid infinite loops.
+// This value might be defined externally.
+#ifndef I2C_TIMEOUT_VALUE_US
+    #define I2C_TIMEOUT_VALUE_US 1000000
+#endif
 
 #if DEVICE_I2C_ASYNCH
     #define TWI_IDX(obj)    ((obj)->i2c.twi_idx)
@@ -371,17 +375,20 @@ int i2c_start(i2c_t *obj)
 int i2c_stop(i2c_t *obj)
 {
     NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)];
+    uint32_t t0;
 
     // The current transfer may be suspended (if it is RX), so it must be
     // resumed before the STOP task is triggered.
     nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME);
     nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP);
-    uint32_t remaining_time = TIMEOUT_VALUE;
+
+    t0 = ticker_read(get_us_ticker_data());
+
     do {
         if (nrf_twi_event_check(twi, NRF_TWI_EVENT_STOPPED)) {
             return 0;
         }
-    } while (--remaining_time);
+    } while (((uint32_t)ticker_read(get_us_ticker_data()) - t0) < I2C_TIMEOUT_VALUE_US);
 
     return 1;
 }
@@ -464,11 +471,15 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
 
 static uint8_t twi_byte_write(NRF_TWI_Type *twi, uint8_t data)
 {
+    uint32_t t0;
+
     nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT);
     nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR);
 
     nrf_twi_txd_set(twi, data);
-    uint32_t remaining_time = TIMEOUT_VALUE;
+
+    t0 = ticker_read(get_us_ticker_data());
+
     do {
         if (nrf_twi_event_check(twi, NRF_TWI_EVENT_TXDSENT)) {
             nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT);
@@ -478,7 +489,7 @@ static uint8_t twi_byte_write(NRF_TWI_Type *twi, uint8_t data)
             nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR);
             return 0; // some error occurred
         }
-    } while (--remaining_time);
+    } while (((uint32_t)ticker_read(get_us_ticker_data()) - t0) < I2C_TIMEOUT_VALUE_US);
 
     return 2; // timeout;
 }
@@ -500,6 +511,9 @@ static void start_twi_write(NRF_TWI_Type *twi, int address)
 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
 {
     twi_info_t *twi_info = TWI_INFO(obj);
+    bool timeout = false;
+    uint32_t t0, t1;
+
 #if DEVICE_I2C_ASYNCH
     if (twi_info->active) {
         return I2C_ERROR_BUS_BUSY;
@@ -522,12 +536,16 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
             nrf_twi_event_clear(twi, event);
             nrf_twi_task_trigger(twi, NRF_TWI_TASK_SUSPEND);
         }
-        uint32_t remaining_time = TIMEOUT_VALUE;
+
+        t0 = ticker_read(get_us_ticker_data());
+
         do {
             if (nrf_twi_event_check(twi, event)) {
                 break;
             }
-        } while (--remaining_time);
+            t1 = ticker_read(get_us_ticker_data());
+            timeout = (t1 - t0) >= I2C_TIMEOUT_VALUE_US;
+        } while (!timeout);
 
         uint32_t errorsrc = nrf_twi_errorsrc_get_and_clear(twi);
         if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK) {
@@ -537,7 +555,7 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
             return I2C_ERROR_NO_SLAVE;
         }
 
-        return (remaining_time ? 0 : I2C_ERROR_BUS_BUSY);
+        return (timeout ? I2C_ERROR_BUS_BUSY : 0);
     }
 
     int result = length;
@@ -574,13 +592,15 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
 int i2c_byte_read(i2c_t *obj, int last)
 {
     NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)];
+    uint32_t t0;
 
     if (last) {
         nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_STOP_MASK);
     }
     nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME);
 
-    uint32_t remaining_time = TIMEOUT_VALUE;
+    t0 = ticker_read(get_us_ticker_data());
+
     do {
         if (nrf_twi_event_check(twi, NRF_TWI_EVENT_RXDREADY)) {
             nrf_twi_event_clear(twi, NRF_TWI_EVENT_RXDREADY);
@@ -590,7 +610,7 @@ int i2c_byte_read(i2c_t *obj, int last)
             nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR);
             return I2C_ERROR_NO_SLAVE;
         }
-    } while (--remaining_time);
+    } while (((uint32_t)ticker_read(get_us_ticker_data()) - t0) < I2C_TIMEOUT_VALUE_US);
 
     return I2C_ERROR_BUS_BUSY;
 }
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/reloc_vector_table.c b/targets/TARGET_NORDIC/TARGET_NRF5/reloc_vector_table.c
index 2862e6c4177..8bf23254de8 100644
--- a/targets/TARGET_NORDIC/TARGET_NRF5/reloc_vector_table.c
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/reloc_vector_table.c
@@ -42,8 +42,8 @@
 #include "nrf_sdm.h"
 #include "section_vars.h"
 
-#if defined(__CC_ARM)
-    __attribute__ ((section("noinit"),zero_init))
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+    __attribute__ ((section(".bss.noinit"),zero_init))
     uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS];
 #elif defined(__GNUC__)
     __attribute__ ((section(".noinit")))
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h
index 6744a32ce9a..9c633835d98 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h
+++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h
@@ -117,10 +117,6 @@ struct pwmout_s {
     uint32_t pulsewidth_us;
 };
 
-struct sleep_s {
-    int powerdown;
-};
-
 struct can_s {
     CANName can;
     char index; 
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c
index 8b05fe86275..7f918418cd8 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c
@@ -339,25 +339,6 @@ static int i2c_set_int(i2c_t *obj, int inten)
     return inten_back;
 }
 
-int i2c_allow_powerdown(void)
-{
-    uint32_t modinit_mask = i2c_modinit_mask;
-    while (modinit_mask) {
-        int i2c_idx = nu_ctz(modinit_mask);
-        const struct nu_modinit_s *modinit = i2c_modinit_tab + i2c_idx;
-        struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
-        if (var->obj) {
-            // Disallow entering power-down mode if I2C transfer is enabled.
-            if (i2c_active(var->obj)) {
-                return 0;
-            }
-        }
-        modinit_mask &= ~(1 << i2c_idx);
-    }
-    
-    return 1;
-}
-
 static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata)
 {
     if (! buf || ! length) {
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c b/targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c
index f89dc4f6a00..d95197c3e4e 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c
@@ -172,26 +172,6 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us)
     pwmout_config(obj);
 }
 
-int pwmout_allow_powerdown(void)
-{
-    uint32_t modinit_mask = pwm_modinit_mask;
-    while (modinit_mask) {
-        int pwm_idx = nu_ctz(modinit_mask);
-        const struct nu_modinit_s *modinit = pwm_modinit_tab + pwm_idx;
-        if (modinit->modname != NC) {
-            PWM_T *pwm_base = (PWM_T *) NU_MODBASE(modinit->modname);
-            uint32_t chn = NU_MODSUBINDEX(modinit->modname);
-            // Disallow entering power-down mode if PWM counter is enabled.
-            if ((pwm_base->CNTEN & (1 << chn)) && pwm_base->CMPDAT[chn]) {
-                return 0;
-            }
-        }
-        modinit_mask &= ~(1 << pwm_idx);
-    }
-    
-    return 1;
-}
-
 static void pwmout_config(pwmout_t* obj)
 {
     PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c
index 292adcf8938..fd3fa1b1a04 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c
@@ -87,6 +87,9 @@ time_t rtc_read(void)
     timeinfo.tm_mday = rtc_datetime.u32Day;
     timeinfo.tm_wday = rtc_datetime.u32DayOfWeek;
     timeinfo.tm_hour = rtc_datetime.u32Hour;
+    if (rtc_datetime.u32TimeScale == RTC_CLOCK_12 && rtc_datetime.u32AmPm == RTC_PM) {
+        timeinfo.tm_hour += 12;
+    }
     timeinfo.tm_min  = rtc_datetime.u32Minute;
     timeinfo.tm_sec  = rtc_datetime.u32Second;
 
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c
index b0965477c70..382ea3e7e78 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c
@@ -656,33 +656,6 @@ int serial_irq_handler_asynch(serial_t *obj)
     return (obj->serial.event & (event_rx | event_tx));
 }
 
-int serial_allow_powerdown(void)
-{
-    uint32_t modinit_mask = uart_modinit_mask;
-    while (modinit_mask) {
-        int uart_idx = nu_ctz(modinit_mask);
-        const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx;
-        if (modinit->modname != NC) {
-            UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
-            // Disallow entering power-down mode if Tx FIFO has data to flush
-            if (! UART_IS_TX_EMPTY((uart_base))) {
-                return 0;
-            }
-            // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going
-            if (uart_base->INTEN & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
-                return 0;
-            }
-            // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going
-            if (uart_base->INTEN & UART_INTEN_RXPDMAEN_Msk) {
-                return 0;
-            }
-        }
-        modinit_mask &= ~(1 << uart_idx);
-    }
-    
-    return 1;
-}
-
 static void uart0_vec_async(void)
 {
     uart_irq_async(uart0_var.obj);
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/sleep.c b/targets/TARGET_NUVOTON/TARGET_M451/sleep.c
index ab1b9daa37d..c2bb24eb7ef 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/sleep.c
+++ b/targets/TARGET_NUVOTON/TARGET_M451/sleep.c
@@ -15,8 +15,6 @@
  */
 
 #include "sleep_api.h"
-#include "serial_api.h"
-#include "lp_ticker_api.h"
 
 #if DEVICE_SLEEP
 
@@ -25,77 +23,24 @@
 #include "objects.h"
 #include "PeripheralPins.h"
 
-static void mbed_enter_sleep(struct sleep_s *obj);
-static void mbed_exit_sleep(struct sleep_s *obj);
-
-int serial_allow_powerdown(void);
-int spi_allow_powerdown(void);
-int i2c_allow_powerdown(void);
-int pwmout_allow_powerdown(void);
-
 /**
- * Enter Idle mode.
+ * Enter idle mode, in which just CPU is halted.
  */
 void hal_sleep(void)
 {
-    struct sleep_s sleep_obj;
-    sleep_obj.powerdown = 0;
-    mbed_enter_sleep(&sleep_obj);
-    mbed_exit_sleep(&sleep_obj);
+    SYS_UnlockReg();
+    CLK_Idle();
+    SYS_LockReg();
 }
 
 /**
- * Enter Power-down mode while no peripheral is active; otherwise, enter Idle mode.
+ * Enter power-down mode, in which HXT/HIRC are halted.
  */
 void hal_deepsleep(void)
 {
-    struct sleep_s sleep_obj;
-    sleep_obj.powerdown = 1;
-    mbed_enter_sleep(&sleep_obj);
-    mbed_exit_sleep(&sleep_obj);
-}
-
-static void mbed_enter_sleep(struct sleep_s *obj)
-{
-    // Check if serial allows entering power-down mode
-    if (obj->powerdown) {
-        obj->powerdown = serial_allow_powerdown();
-    }
-    // Check if spi allows entering power-down mode
-    if (obj->powerdown) {
-        obj->powerdown = spi_allow_powerdown();
-    }
-    // Check if i2c allows entering power-down mode
-    if (obj->powerdown) {
-        obj->powerdown = i2c_allow_powerdown();
-    }
-    // Check if pwmout allows entering power-down mode
-    if (obj->powerdown) {
-        obj->powerdown = pwmout_allow_powerdown();
-    }
-    // TODO: Check if other peripherals allow entering power-down mode
-  
-    if (obj->powerdown) {   // Power-down mode (HIRC/HXT disabled, LIRC/LXT enabled)
-        SYS_UnlockReg();
-        CLK_PowerDown();
-        SYS_LockReg();
-    }
-    else {  // CPU halt mode (HIRC/HXT enabled, LIRC/LXT enabled)
-        SYS_UnlockReg();
-        CLK_Idle();
-        SYS_LockReg();
-    }
-    __NOP();
-    __NOP();
-    __NOP();
-    __NOP();
-}
-
-static void mbed_exit_sleep(struct sleep_s *obj)
-{
-    // TODO: TO BE CONTINUED
-    
-    (void)obj;
+    SYS_UnlockReg();
+    CLK_PowerDown();
+    SYS_LockReg();
 }
 
 #endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c b/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c
index 5616bd60cc6..5d035ccf994 100644
--- a/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c
@@ -470,25 +470,6 @@ uint8_t spi_active(spi_t *obj)
     return (spi_base->CTL & SPI_CTL_SPIEN_Msk);
 }
 
-int spi_allow_powerdown(void)
-{
-    uint32_t modinit_mask = spi_modinit_mask;
-    while (modinit_mask) {
-        int spi_idx = nu_ctz(modinit_mask);
-        const struct nu_modinit_s *modinit = spi_modinit_tab + spi_idx;
-        if (modinit->modname != NC) {
-            SPI_T *spi_base = (SPI_T *) NU_MODBASE(modinit->modname);
-            // Disallow entering power-down mode if SPI transfer is enabled.
-            if (spi_base->CTL & SPI_CTL_SPIEN_Msk) {
-                return 0;
-            }
-        }
-        modinit_mask &= ~(1 << spi_idx);
-    }
-    
-    return 1;
-}
-
 static int spi_writeable(spi_t * obj)
 {
     // Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive
diff --git a/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/objects.h b/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/objects.h
index fef01cfdafd..e3d24534d81 100644
--- a/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/objects.h
+++ b/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/objects.h
@@ -118,10 +118,6 @@ struct pwmout_s {
     uint32_t pulsewidth_us;
 };
 
-struct sleep_s {
-    int powerdown;
-};
-
 struct trng_s {
     uint8_t dummy;
 };
diff --git a/targets/TARGET_NUVOTON/TARGET_M480/device/M480.h b/targets/TARGET_NUVOTON/TARGET_M480/device/M480.h
index 070104eb74d..d3e5669df71 100644
--- a/targets/TARGET_NUVOTON/TARGET_M480/device/M480.h
+++ b/targets/TARGET_NUVOTON/TARGET_M480/device/M480.h
@@ -35908,8 +35908,12 @@ typedef volatile unsigned long  vu32;       ///< Define 32-bit unsigned volatile
 #define NULL           (0)      ///< NULL pointer
 #endif
 
+#ifndef TRUE
 #define TRUE           (1UL)      ///< Boolean true, define to use in API parameters or return value
+#endif
+#ifndef FALSE
 #define FALSE          (0UL)      ///< Boolean false, define to use in API parameters or return value
+#endif
 
 #define ENABLE         (1UL)      ///< Enable, define to use in API parameters
 #define DISABLE        (0UL)      ///< Disable, define to use in API parameters
diff --git a/targets/TARGET_NUVOTON/TARGET_M480/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_M480/i2c_api.c
index 2313d4f9283..bf8e92a87c0 100644
--- a/targets/TARGET_NUVOTON/TARGET_M480/i2c_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_M480/i2c_api.c
@@ -330,25 +330,6 @@ static int i2c_set_int(i2c_t *obj, int inten)
     return inten_back;
 }
 
-int i2c_allow_powerdown(void)
-{
-    uint32_t modinit_mask = i2c_modinit_mask;
-    while (modinit_mask) {
-        int i2c_idx = nu_ctz(modinit_mask);
-        const struct nu_modinit_s *modinit = i2c_modinit_tab + i2c_idx;
-        struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
-        if (var->obj) {
-            // Disallow entering power-down mode if I2C transfer is enabled.
-            if (i2c_active(var->obj)) {
-                return 0;
-            }
-        }
-        modinit_mask &= ~(1 << i2c_idx);
-    }
-
-    return 1;
-}
-
 static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata)
 {
     if (! buf || ! length) {
diff --git a/targets/TARGET_NUVOTON/TARGET_M480/pwmout_api.c b/targets/TARGET_NUVOTON/TARGET_M480/pwmout_api.c
index 93bfe68116c..12d49872563 100644
--- a/targets/TARGET_NUVOTON/TARGET_M480/pwmout_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_M480/pwmout_api.c
@@ -167,26 +167,6 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us)
     pwmout_config(obj, 1);
 }
 
-int pwmout_allow_powerdown(void)
-{
-    uint32_t modinit_mask = pwm_modinit_mask;
-    while (modinit_mask) {
-        int pwm_idx = nu_ctz(modinit_mask);
-        const struct nu_modinit_s *modinit = pwm_modinit_tab + pwm_idx;
-        if (modinit->modname != NC) {
-            EPWM_T *pwm_base = (EPWM_T *) NU_MODBASE(modinit->modname);
-            uint32_t chn = NU_MODSUBINDEX(modinit->modname);
-            // Disallow entering power-down mode if PWM counter is enabled.
-            if ((pwm_base->CNTEN & (1 << chn)) && pwm_base->CMPDAT[chn]) {
-                return 0;
-            }
-        }
-        modinit_mask &= ~(1 << pwm_idx);
-    }
-
-    return 1;
-}
-
 static void pwmout_config(pwmout_t* obj, int start)
 {
     EPWM_T *pwm_base = (EPWM_T *) NU_MODBASE(obj->pwm);
diff --git a/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c
index 5047ccad033..7535c3a72fa 100644
--- a/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c
@@ -22,6 +22,7 @@
 #include "mbed_error.h"
 #include "nu_modutil.h"
 #include "nu_miscutil.h"
+#include "mbed_mktime.h"
 
 #define YEAR0       1900
 //#define EPOCH_YR    1970
@@ -88,11 +89,14 @@ time_t rtc_read(void)
     timeinfo.tm_mday = rtc_datetime.u32Day;
     timeinfo.tm_wday = rtc_datetime.u32DayOfWeek;
     timeinfo.tm_hour = rtc_datetime.u32Hour;
+    if (rtc_datetime.u32TimeScale == RTC_CLOCK_12 && rtc_datetime.u32AmPm == RTC_PM) {
+        timeinfo.tm_hour += 12;
+    }
     timeinfo.tm_min  = rtc_datetime.u32Minute;
     timeinfo.tm_sec  = rtc_datetime.u32Second;
 
     // Convert to timestamp
-    time_t t = mktime(&timeinfo);
+    time_t t = _rtc_mktime(&timeinfo);
 
     return t;
 }
@@ -104,18 +108,21 @@ void rtc_write(time_t t)
     }
 
     // Convert timestamp to struct tm
-    struct tm *timeinfo = localtime(&t);
+    struct tm timeinfo;
+    if (_rtc_localtime(t, &timeinfo) == false) {
+        return;
+    }
 
     S_RTC_TIME_DATA_T rtc_datetime;
 
     // Convert S_RTC_TIME_DATA_T to struct tm
-    rtc_datetime.u32Year        = timeinfo->tm_year + YEAR0;
-    rtc_datetime.u32Month       = timeinfo->tm_mon + 1;
-    rtc_datetime.u32Day         = timeinfo->tm_mday;
-    rtc_datetime.u32DayOfWeek   = timeinfo->tm_wday;
-    rtc_datetime.u32Hour        = timeinfo->tm_hour;
-    rtc_datetime.u32Minute      = timeinfo->tm_min;
-    rtc_datetime.u32Second      = timeinfo->tm_sec;
+    rtc_datetime.u32Year        = timeinfo.tm_year + YEAR0;
+    rtc_datetime.u32Month       = timeinfo.tm_mon + 1;
+    rtc_datetime.u32Day         = timeinfo.tm_mday;
+    rtc_datetime.u32DayOfWeek   = timeinfo.tm_wday;
+    rtc_datetime.u32Hour        = timeinfo.tm_hour;
+    rtc_datetime.u32Minute      = timeinfo.tm_min;
+    rtc_datetime.u32Second      = timeinfo.tm_sec;
     rtc_datetime.u32TimeScale   = RTC_CLOCK_24;
 
     // NOTE: Timing issue with write to RTC registers. This delay is empirical, not rational.
diff --git a/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c
index e45867c118c..25695156a39 100644
--- a/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c
@@ -710,33 +710,6 @@ int serial_irq_handler_asynch(serial_t *obj)
     return (obj->serial.event & (event_rx | event_tx));
 }
 
-int serial_allow_powerdown(void)
-{
-    uint32_t modinit_mask = uart_modinit_mask;
-    while (modinit_mask) {
-        int uart_idx = nu_ctz(modinit_mask);
-        const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx;
-        if (modinit->modname != NC) {
-            UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
-            // Disallow entering power-down mode if Tx FIFO has data to flush
-            if (! UART_IS_TX_EMPTY((uart_base))) {
-                return 0;
-            }
-            // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going
-            if (uart_base->INTEN & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
-                return 0;
-            }
-            // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going
-            if (uart_base->INTEN & UART_INTEN_RXPDMAEN_Msk) {
-                return 0;
-            }
-        }
-        modinit_mask &= ~(1 << uart_idx);
-    }
-
-    return 1;
-}
-
 static void uart0_vec_async(void)
 {
     uart_irq_async(uart0_var.obj);
diff --git a/targets/TARGET_NUVOTON/TARGET_M480/sleep.c b/targets/TARGET_NUVOTON/TARGET_M480/sleep.c
index a6fde61172b..c2bb24eb7ef 100644
--- a/targets/TARGET_NUVOTON/TARGET_M480/sleep.c
+++ b/targets/TARGET_NUVOTON/TARGET_M480/sleep.c
@@ -15,8 +15,6 @@
  */
 
 #include "sleep_api.h"
-#include "serial_api.h"
-#include "lp_ticker_api.h"
 
 #if DEVICE_SLEEP
 
@@ -25,74 +23,24 @@
 #include "objects.h"
 #include "PeripheralPins.h"
 
-static void mbed_enter_sleep(struct sleep_s *obj);
-static void mbed_exit_sleep(struct sleep_s *obj);
-
-int serial_allow_powerdown(void);
-int spi_allow_powerdown(void);
-int i2c_allow_powerdown(void);
-int pwmout_allow_powerdown(void);
-
 /**
- * Enter Idle mode.
+ * Enter idle mode, in which just CPU is halted.
  */
 void hal_sleep(void)
 {
-    struct sleep_s sleep_obj;
-    sleep_obj.powerdown = 0;
-    mbed_enter_sleep(&sleep_obj);
-    mbed_exit_sleep(&sleep_obj);
+    SYS_UnlockReg();
+    CLK_Idle();
+    SYS_LockReg();
 }
 
 /**
- * Enter Power-down mode while no peripheral is active; otherwise, enter Idle mode.
+ * Enter power-down mode, in which HXT/HIRC are halted.
  */
 void hal_deepsleep(void)
 {
-    struct sleep_s sleep_obj;
-    sleep_obj.powerdown = 1;
-    mbed_enter_sleep(&sleep_obj);
-    mbed_exit_sleep(&sleep_obj);
-}
-
-static void mbed_enter_sleep(struct sleep_s *obj)
-{
-    // Check if serial allows entering power-down mode
-    if (obj->powerdown) {
-        obj->powerdown = serial_allow_powerdown();
-    }
-    // Check if spi allows entering power-down mode
-    if (obj->powerdown) {
-        obj->powerdown = spi_allow_powerdown();
-    }
-    // Check if i2c allows entering power-down mode
-    if (obj->powerdown) {
-        obj->powerdown = i2c_allow_powerdown();
-    }
-    // Check if pwmout allows entering power-down mode
-    if (obj->powerdown) {
-        obj->powerdown = pwmout_allow_powerdown();
-    }
-    // TODO: Check if other peripherals allow entering power-down mode
-
-    if (obj->powerdown) {   // Power-down mode (HIRC/HXT disabled, LIRC/LXT enabled)
-        SYS_UnlockReg();
-        CLK_PowerDown();
-        SYS_LockReg();
-    } else { // CPU halt mode (HIRC/HXT enabled, LIRC/LXT enabled)
-        SYS_UnlockReg();
-        CLK_Idle();
-        SYS_LockReg();
-    }
-    __NOP();
-    __NOP();
-    __NOP();
-    __NOP();
-}
-
-static void mbed_exit_sleep(struct sleep_s *obj)
-{
-    (void)obj;
+    SYS_UnlockReg();
+    CLK_PowerDown();
+    SYS_LockReg();
 }
 
 #endif
diff --git a/targets/TARGET_NUVOTON/TARGET_M480/spi_api.c b/targets/TARGET_NUVOTON/TARGET_M480/spi_api.c
index 88ae09d6ff8..79e6818d28a 100644
--- a/targets/TARGET_NUVOTON/TARGET_M480/spi_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_M480/spi_api.c
@@ -461,25 +461,6 @@ uint8_t spi_active(spi_t *obj)
     return (spi_base->CTL & SPI_CTL_SPIEN_Msk);
 }
 
-int spi_allow_powerdown(void)
-{
-    uint32_t modinit_mask = spi_modinit_mask;
-    while (modinit_mask) {
-        int spi_idx = nu_ctz(modinit_mask);
-        const struct nu_modinit_s *modinit = spi_modinit_tab + spi_idx;
-        if (modinit->modname != NC) {
-            SPI_T *spi_base = (SPI_T *) NU_MODBASE(modinit->modname);
-            // Disallow entering power-down mode if SPI transfer is enabled.
-            if (spi_base->CTL & SPI_CTL_SPIEN_Msk) {
-                return 0;
-            }
-        }
-        modinit_mask &= ~(1 << spi_idx);
-    }
-
-    return 1;
-}
-
 static int spi_writeable(spi_t * obj)
 {
     // Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive
diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PinNames.h b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PinNames.h
index acd1297e01d..57661d2639e 100644
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PinNames.h
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PinNames.h
@@ -118,8 +118,8 @@ typedef enum {
     LED_GREEN = LED1,
     LED_YELLOW = LED2,
     // Button naming
-    SW2 = PE_5,
-    SW3 = PE_6,
+    SW1 = PE_5,
+    SW2 = PE_6,
     
 } PinName;
 
diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/objects.h b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/objects.h
index 8ec51b38e86..12476fd7c14 100644
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/objects.h
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/objects.h
@@ -110,9 +110,6 @@ struct pwmout_s {
     uint32_t pulsewidth_us;
 };
 
-struct sleep_s {
-    int powerdown;
-};
 #ifdef __cplusplus
 }
 #endif
diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/device/Nano100Series.h b/targets/TARGET_NUVOTON/TARGET_NANO100/device/Nano100Series.h
index c6655323a64..6a6520e57cd 100644
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/device/Nano100Series.h
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/Nano100Series.h
@@ -11831,8 +11831,12 @@ typedef volatile unsigned long  vu32;       ///< Define 32-bit unsigned volatile
 #define NULL           (0)      ///< NULL pointer
 #endif
 
+#ifndef TRUE
 #define TRUE           (1)      ///< Boolean true, define to use in API parameters or return value
+#endif
+#ifndef FALSE
 #define FALSE          (0)      ///< Boolean false, define to use in API parameters or return value
+#endif
 
 #define ENABLE         (1)      ///< Enable, define to use in API parameters
 #define DISABLE        (0)      ///< Disable, define to use in API parameters
diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_irq_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_irq_api.c
index 07d92ddd307..fb26ccc24fe 100644
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_irq_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_irq_api.c
@@ -49,23 +49,23 @@ static struct nu_gpio_irq_var gpio_irq_var_arr[] = {
 
 #define NU_MAX_PORT     (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
 
-#ifndef MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_ENABLE
-#define MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_ENABLE 0
+#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE
+#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE 0
 #endif
 
-#ifndef MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
-#define MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC
+#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
+#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC
 #endif
 static PinName gpio_irq_debounce_arr[] = {
-    MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
+    MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
 };
 
-#ifndef MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
-#define MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCLKSRC_IRC10K
+#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
+#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCLKSRC_IRC10K
 #endif
 
-#ifndef MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
-#define MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCLKSEL_16
+#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
+#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCLKSEL_16
 #endif
 
 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
@@ -90,12 +90,12 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
     //       There is no need to call gpio_set() redundantly.
     
     {
-#if MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_ENABLE
+#if MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE
         // Suppress compiler warning
         (void) gpio_irq_debounce_arr;
 
         // Configure de-bounce clock source and sampling cycle time
-        GPIO_SET_DEBOUNCE_TIME(MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
+        GPIO_SET_DEBOUNCE_TIME(MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
         GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
 #else
         // Enable de-bounce if the pin is in the de-bounce enable list
@@ -112,7 +112,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
             if (pin_index == pin_index_debunce &&
                 port_index == port_index_debounce) {
                 // Configure de-bounce clock source and sampling cycle time
-                GPIO_SET_DEBOUNCE_TIME(MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
+                GPIO_SET_DEBOUNCE_TIME(MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
                 GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
                 break;
             }
diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/i2c_api.c
index 375602b461e..3e146ee8b17 100644
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/i2c_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/i2c_api.c
@@ -358,25 +358,6 @@ static int i2c_set_int(i2c_t *obj, int inten)
     return inten_back;
 }
 
-int i2c_allow_powerdown(void)
-{
-    uint32_t modinit_mask = i2c_modinit_mask;
-    while (modinit_mask) {
-        int i2c_idx = nu_ctz(modinit_mask);
-        const struct nu_modinit_s *modinit = i2c_modinit_tab + i2c_idx;
-        struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
-        if (var->obj) {
-            // Disallow entering power-down mode if I2C transfer is enabled.
-            if (i2c_active(var->obj)) {
-                return 0;
-            }
-        }
-        modinit_mask &= ~(1 << i2c_idx);
-    }
-    
-    return 1;
-}
-
 static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata)
 {
     if (! buf || ! length) {
diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c
index 87b67b5ba87..7a9bf129b00 100644
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c
@@ -141,7 +141,7 @@ timestamp_t lp_ticker_read()
         while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
 
         // Add power-down compensation
-        return ((uint64_t) major_minor_clks * US_PER_SEC / TMR3_CLK_PER_SEC / US_PER_TICK);
+        return ((uint64_t) major_minor_clks * US_PER_SEC / TMR2_CLK_PER_SEC / US_PER_TICK);
     }
     while (0);
 }
@@ -222,6 +222,6 @@ static void lp_ticker_arm_cd(void)
     TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
     // Wait 2 cycles of engine clock to ensure previous CTL write action is finish
     wait_us(30 * 2);
-    timer3_base->CTL = ctl_timer3 | TIMER_CTL_TMR_EN_Msk;
+    timer3_base->CTL |= ctl_timer3 | TIMER_CTL_TMR_EN_Msk;
 }
 #endif
diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/mbed_lib.json b/targets/TARGET_NUVOTON/TARGET_NANO100/mbed_lib.json
deleted file mode 100644
index 1494a976ff2..00000000000
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/mbed_lib.json
+++ /dev/null
@@ -1,22 +0,0 @@
-{
-    "name": "NANO100",
-    "config": {
-        "gpio-irq-debounce-enable": {
-            "help": "Enable GPIO IRQ debounce",
-            "value": 0
-        },
-        "gpio-irq-debounce-enable-list": {
-            "help": "Comma separated pin list to enable GPIO IRQ debounce",
-            "value": "NC"
-        },
-        "gpio-irq-debounce-clock-source": {
-            "help": "Select GPIO IRQ debounce clock source: GPIO_DBCLKSRC_HCLK or GPIO_DBCLKSRC_IRC10K",
-            "value": "GPIO_DBCLKSRC_IRC10K"
-        },
-
-        "gpio-irq-debounce-sample-rate": {
-            "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCLKSEL_1, GPIO_DBCLKSEL_2, GPIO_DBCLKSEL_4, ..., or GPIO_DBCLKSEL_32768",
-            "value": "GPIO_DBCLKSEL_16"
-        }
-    }
-}
diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/pwmout_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/pwmout_api.c
index eb648492079..7eca1a1ab33 100644
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/pwmout_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/pwmout_api.c
@@ -176,26 +176,6 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us)
     pwmout_config(obj);
 }
 
-int pwmout_allow_powerdown(void)
-{
-    uint32_t modinit_mask = pwm_modinit_mask;
-    while (modinit_mask) {
-        int pwm_idx = nu_ctz(modinit_mask);
-        const struct nu_modinit_s *modinit = pwm_modinit_tab + pwm_idx;
-        if (modinit->modname != NC) {
-            PWM_T *pwm_base = (PWM_T *) NU_MODBASE(modinit->modname);
-            uint32_t chn = NU_MODSUBINDEX(modinit->modname);
-            // Disallow entering power-down mode if PWM counter is enabled.
-            if (pwm_base->OE & (1 << chn)) {
-                return 0;
-            }
-        }
-        modinit_mask &= ~(1 << pwm_idx);
-    }
-    
-    return 1;
-}
-
 static void pwmout_config(pwmout_t* obj)
 {
     PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/rtc_api.c
index c6836291377..a4a6bc0675a 100644
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/rtc_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/rtc_api.c
@@ -87,6 +87,9 @@ time_t rtc_read(void)
     timeinfo.tm_mday = rtc_datetime.u32Day;
     timeinfo.tm_wday = rtc_datetime.u32DayOfWeek;
     timeinfo.tm_hour = rtc_datetime.u32Hour;
+    if (rtc_datetime.u32TimeScale == RTC_CLOCK_12 && rtc_datetime.u32AmPm == RTC_PM) {
+        timeinfo.tm_hour += 12;
+    }
     timeinfo.tm_min  = rtc_datetime.u32Minute;
     timeinfo.tm_sec  = rtc_datetime.u32Second;
 
diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c
index 93f91467515..7810d009776 100644
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c
@@ -597,33 +597,6 @@ int serial_irq_handler_asynch(serial_t *obj)
     return (obj->serial.event & (event_rx | event_tx));
 }
 
-int serial_allow_powerdown(void)
-{
-    uint32_t modinit_mask = uart_modinit_mask;
-    while (modinit_mask) {
-        int uart_idx = nu_ctz(modinit_mask);
-        const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx;
-        if (modinit->modname != NC) {
-            UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
-            // Disallow entering power-down mode if Tx FIFO has data to flush
-            if (! UART_IS_TX_EMPTY((uart_base))) {
-                return 0;
-            }
-            // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going
-            if (uart_base->IER & (UART_IER_RDA_IE_Msk | UART_IER_RTO_IE_Msk)) {
-                return 0;
-            }
-            // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going
-            if (uart_base->CTL & UART_CTL_DMA_RX_EN_Msk) {
-                return 0;
-            }
-        }
-        modinit_mask &= ~(1 << uart_idx);
-    }
-    
-    return 1;
-}
-
 static void uart_irq_async(serial_t *obj)
 {
     if (serial_is_irq_en(obj, RxIrq)) {
diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/sleep.c b/targets/TARGET_NUVOTON/TARGET_NANO100/sleep.c
index ec5126ec20d..dd32dd41718 100644
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/sleep.c
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/sleep.c
@@ -15,8 +15,6 @@
  */
 
 #include "sleep_api.h"
-#include "serial_api.h"
-#include "lp_ticker_api.h"
 
 #if DEVICE_SLEEP
 
@@ -25,74 +23,24 @@
 #include "objects.h"
 #include "PeripheralPins.h"
 
-static void mbed_enter_sleep(struct sleep_s *obj);
-static void mbed_exit_sleep(struct sleep_s *obj);
-
-int serial_allow_powerdown(void);
-int spi_allow_powerdown(void);
-int i2c_allow_powerdown(void);
-int pwmout_allow_powerdown(void);
-
 /**
- * Enter Idle mode.
+ * Enter idle mode, in which just CPU is halted.
  */
 void hal_sleep(void)
 {
-    struct sleep_s sleep_obj;
-    sleep_obj.powerdown = 0;
-    mbed_enter_sleep(&sleep_obj);
-    mbed_exit_sleep(&sleep_obj);
+    SYS_UnlockReg();
+    CLK_Idle();
+    SYS_LockReg();
 }
 
 /**
- * Enter Power-down mode while no peripheral is active; otherwise, enter Idle mode.
+ * Enter power-down mode, in which HXT/HIRC are halted.
  */
 void hal_deepsleep(void)
 {
-    struct sleep_s sleep_obj;
-    sleep_obj.powerdown = 1;
-    mbed_enter_sleep(&sleep_obj);
-    mbed_exit_sleep(&sleep_obj);
-}
-
-static void mbed_enter_sleep(struct sleep_s *obj)
-{
-    // Check if serial allows entering power-down mode
-    if (obj->powerdown) {
-        obj->powerdown = serial_allow_powerdown();
-    }
-    // Check if spi allows entering power-down mode
-    if (obj->powerdown) {
-        obj->powerdown = spi_allow_powerdown();
-    }
-    // Check if i2c allows entering power-down mode
-    if (obj->powerdown) {
-        obj->powerdown = i2c_allow_powerdown();
-    }
-    // Check if pwmout allows entering power-down mode
-    if (obj->powerdown) {
-        obj->powerdown = pwmout_allow_powerdown();
-    }
-    // TODO: Check if other peripherals allow entering power-down mode
-
-    if (obj->powerdown) {   // Power-down mode (HIRC/HXT disabled, LIRC/LXT enabled)
-        SYS_UnlockReg();
-        CLK_PowerDown();
-        SYS_LockReg();
-    } else { // CPU halt mode (HIRC/HXT enabled, LIRC/LXT enabled)
-        SYS_UnlockReg();
-        CLK_Idle();
-        SYS_LockReg();
-    }
-    __NOP();
-    __NOP();
-    __NOP();
-    __NOP();
-}
-
-static void mbed_exit_sleep(struct sleep_s *obj)
-{
-    (void)obj;
+    SYS_UnlockReg();
+    CLK_PowerDown();
+    SYS_LockReg();
 }
 
 #endif
diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/spi_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/spi_api.c
index 86def36d767..0bc47ae67f3 100644
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/spi_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/spi_api.c
@@ -505,24 +505,6 @@ uint8_t spi_active(spi_t *obj)
     return SPI_IS_BUSY(spi_base);
 }
 
-int spi_allow_powerdown(void)
-{
-    uint32_t modinit_mask = spi_modinit_mask;
-    while (modinit_mask) {
-        int spi_idx = nu_ctz(modinit_mask);
-        const struct nu_modinit_s *modinit = spi_modinit_tab + spi_idx;
-        if (modinit->modname != NC) {
-            SPI_T *spi_base = (SPI_T *) NU_MODBASE(modinit->modname);
-            if (SPI_IS_BUSY(spi_base)) {
-                return 0;
-            }
-        }
-        modinit_mask &= ~(1 << spi_idx);
-    }
-    
-    return 1;
-}
-
 void SPI0_IRQHandler(void)
 {
     spi_irq(spi0_var.obj);
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/objects.h b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/objects.h
index 2e62f15efc7..da3db2d54b2 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/objects.h
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/objects.h
@@ -118,10 +118,6 @@ struct pwmout_s {
     uint32_t pulsewidth_us;
 };
 
-struct sleep_s {
-    int powerdown;
-};
-
 struct trng_s {
     uint8_t dummy;
 };
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h b/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h
index 664551ec71f..00af9638dea 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h
@@ -32511,8 +32511,12 @@ typedef volatile unsigned long  vu32;       ///< Define 32-bit unsigned volatile
 #define NULL           (0)      ///< NULL pointer
 #endif
 
+#ifndef TRUE
 #define TRUE           (1)      ///< Boolean true, define to use in API parameters or return value
+#endif
+#ifndef FALSE
 #define FALSE          (0)      ///< Boolean false, define to use in API parameters or return value
+#endif
 
 #define ENABLE         (1)      ///< Enable, define to use in API parameters
 #define DISABLE        (0)      ///< Disable, define to use in API parameters
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_rtc.h b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_rtc.h
index 9a87f8a6bb3..3d633b166d4 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_rtc.h
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_rtc.h
@@ -129,7 +129,7 @@ typedef struct {
  *            1 = This year is a leap year.
  * \hideinitializer 
  */
-#define RTC_IS_LEAP_YEAR    ((RTC->LEAPYEAR & (RTC_LEAPYEAR_LEAPYEAR_Msk))?1:0)
+#define RTC_IS_LEAP_YEAR()    ((RTC->LEAPYEAR & (RTC_LEAPYEAR_LEAPYEAR_Msk))?1:0)
 
 /**
  *  @brief    Clear alarm interrupt status.
@@ -139,7 +139,7 @@ typedef struct {
  *  @return   None
  * \hideinitializer 
  */
-#define RTC_CLEAR_ALARM_INT_FLAG    (RTC->INTSTS = RTC_INTSTS_ALMIF_Msk)
+#define RTC_CLEAR_ALARM_INT_FLAG()    (RTC->INTSTS = RTC_INTSTS_ALMIF_Msk)
 
 /**
  *  @brief    Clear tick interrupt status.
@@ -149,7 +149,7 @@ typedef struct {
  *  @return    None
  * \hideinitializer 
  */
-#define RTC_CLEAR_TICK_INT_FLAG    (RTC->INTSTS = RTC_INTSTS_TICKIF_Msk)
+#define RTC_CLEAR_TICK_INT_FLAG()    (RTC->INTSTS = RTC_INTSTS_TICKIF_Msk)
 
 /**
  *  @brief    Clear tamper detect pin status.
@@ -169,7 +169,7 @@ typedef struct {
  *  @return   Alarm interrupt status
  * \hideinitializer 
  */
-#define RTC_GET_ALARM_INT_FLAG    ((RTC->INTSTS & RTC_INTSTS_ALMIF_Msk) >> RTC_INTSTS_ALMIF_Pos)
+#define RTC_GET_ALARM_INT_FLAG()    ((RTC->INTSTS & RTC_INTSTS_ALMIF_Msk) >> RTC_INTSTS_ALMIF_Pos)
 
 /**
  *  @brief    Get alarm interrupt status.
@@ -179,7 +179,7 @@ typedef struct {
  *  @return   Alarm interrupt status
  * \hideinitializer 
  */
-#define RTC_GET_TICK_INT_FLAG    ((RTC->INTSTS & RTC_INTSTS_TICKIF_Msk) >> RTC_INTSTS_TICKIF_Pos)
+#define RTC_GET_TICK_INT_FLAG()    ((RTC->INTSTS & RTC_INTSTS_TICKIF_Msk) >> RTC_INTSTS_TICKIF_Pos)
 
 /**
  *  @brief    Get tamper detect pin status.
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/i2c_api.c
index 481f7d6bd05..450451d89f2 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/i2c_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/i2c_api.c
@@ -356,25 +356,6 @@ static int i2c_set_int(i2c_t *obj, int inten)
     return inten_back;
 }
 
-int i2c_allow_powerdown(void)
-{
-    uint32_t modinit_mask = i2c_modinit_mask;
-    while (modinit_mask) {
-        int i2c_idx = nu_ctz(modinit_mask);
-        const struct nu_modinit_s *modinit = i2c_modinit_tab + i2c_idx;
-        struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
-        if (var->obj) {
-            // Disallow entering power-down mode if I2C transfer is enabled.
-            if (i2c_active(var->obj)) {
-                return 0;
-            }
-        }
-        modinit_mask &= ~(1 << i2c_idx);
-    }
-    
-    return 1;
-}
-
 static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata)
 {
     if (! buf || ! length) {
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/pwmout_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/pwmout_api.c
index 90165697c63..bd2409ff8ce 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/pwmout_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/pwmout_api.c
@@ -195,26 +195,6 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us)
     pwmout_config(obj);
 }
 
-int pwmout_allow_powerdown(void)
-{
-    uint32_t modinit_mask = pwm_modinit_mask;
-    while (modinit_mask) {
-        int pwm_idx = nu_ctz(modinit_mask);
-        const struct nu_modinit_s *modinit = pwm_modinit_tab + pwm_idx;
-        if (modinit->modname != NC) {
-            PWM_T *pwm_base = (PWM_T *) NU_MODBASE(modinit->modname);
-            uint32_t chn = NU_MODSUBINDEX(modinit->modname);
-            // Disallow entering power-down mode if PWM counter is enabled.
-            if ((pwm_base->CNTEN & (1 << chn)) && pwm_base->CMPDAT[chn]) {
-                return 0;
-            }
-        }
-        modinit_mask &= ~(1 << pwm_idx);
-    }
-    
-    return 1;
-}
-
 static void pwmout_config(pwmout_t* obj)
 {
     PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c
index cf7dfbf2d2a..41ec6042d9d 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c
@@ -87,6 +87,9 @@ time_t rtc_read(void)
     timeinfo.tm_mday = rtc_datetime.u32Day;
     timeinfo.tm_wday = rtc_datetime.u32DayOfWeek;
     timeinfo.tm_hour = rtc_datetime.u32Hour;
+    if (rtc_datetime.u32TimeScale == RTC_CLOCK_12 && rtc_datetime.u32AmPm == RTC_PM) {
+        timeinfo.tm_hour += 12;
+    }
     timeinfo.tm_min  = rtc_datetime.u32Minute;
     timeinfo.tm_sec  = rtc_datetime.u32Second;
 
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c
index b3dd9737aaa..be8e304c4e9 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c
@@ -694,33 +694,6 @@ int serial_irq_handler_asynch(serial_t *obj)
     return (obj->serial.event & (event_rx | event_tx));
 }
 
-int serial_allow_powerdown(void)
-{
-    uint32_t modinit_mask = uart_modinit_mask;
-    while (modinit_mask) {
-        int uart_idx = nu_ctz(modinit_mask);
-        const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx;
-        if (modinit->modname != NC) {
-            UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
-            // Disallow entering power-down mode if Tx FIFO has data to flush
-            if (! UART_IS_TX_EMPTY((uart_base))) {
-                return 0;
-            }
-            // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going
-            if (uart_base->INTEN & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
-                return 0;
-            }
-            // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going
-            if (uart_base->INTEN & UART_INTEN_RXPDMAEN_Msk) {
-                return 0;
-            }
-        }
-        modinit_mask &= ~(1 << uart_idx);
-    }
-    
-    return 1;
-}
-
 static void uart0_vec_async(void)
 {
     uart_irq_async(uart0_var.obj);
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/sleep.c b/targets/TARGET_NUVOTON/TARGET_NUC472/sleep.c
index 87f53ab6f61..c2bb24eb7ef 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/sleep.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/sleep.c
@@ -15,8 +15,6 @@
  */
 
 #include "sleep_api.h"
-#include "serial_api.h"
-#include "lp_ticker_api.h"
 
 #if DEVICE_SLEEP
 
@@ -25,80 +23,24 @@
 #include "objects.h"
 #include "PeripheralPins.h"
 
-static void mbed_enter_sleep(struct sleep_s *obj);
-static void mbed_exit_sleep(struct sleep_s *obj);
-
-int serial_allow_powerdown(void);
-int spi_allow_powerdown(void);
-int i2c_allow_powerdown(void);
-int pwmout_allow_powerdown(void);
-
 /**
- * Enter Idle mode.
+ * Enter idle mode, in which just CPU is halted.
  */
 void hal_sleep(void)
 {
-    struct sleep_s sleep_obj;
-    sleep_obj.powerdown = 0;
-    mbed_enter_sleep(&sleep_obj);
-    mbed_exit_sleep(&sleep_obj);
+    SYS_UnlockReg();
+    CLK_Idle();
+    SYS_LockReg();
 }
 
 /**
- * Enter Power-down mode while no peripheral is active; otherwise, enter Idle mode.
+ * Enter power-down mode, in which HXT/HIRC are halted.
  */
 void hal_deepsleep(void)
 {
-    struct sleep_s sleep_obj;
-    sleep_obj.powerdown = 1;
-    mbed_enter_sleep(&sleep_obj);
-    mbed_exit_sleep(&sleep_obj);
-}
-
-static void mbed_enter_sleep(struct sleep_s *obj)
-{
-    // Check if serial allows entering power-down mode
-    if (obj->powerdown) {
-        obj->powerdown = serial_allow_powerdown();
-    }
-    // Check if spi allows entering power-down mode
-    if (obj->powerdown) {
-        obj->powerdown = spi_allow_powerdown();
-    }
-    // Check if i2c allows entering power-down mode
-    if (obj->powerdown) {
-        obj->powerdown = i2c_allow_powerdown();
-    }
-    // Check if pwmout allows entering power-down mode
-    if (obj->powerdown) {
-        obj->powerdown = pwmout_allow_powerdown();
-    }
-    // TODO: Check if other peripherals allow entering power-down mode
-    
-    if (obj->powerdown) {   // Power-down mode (HIRC/HXT disabled, LIRC/LXT enabled)
-        SYS_UnlockReg();
-        CLK_PowerDown();
-        SYS_LockReg();
-    }
-    else {  // CPU halt mode (HIRC/HXT enabled, LIRC/LXT enabled)
-        // NOTE: NUC472's CLK_Idle() will also disable HIRC/HXT.
-        SYS_UnlockReg();
-        SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
-        CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk;
-        __WFI();
-        SYS_LockReg();
-    }
-    __NOP();
-    __NOP();
-    __NOP();
-    __NOP();
-}
-
-static void mbed_exit_sleep(struct sleep_s *obj)
-{
-    // TODO: TO BE CONTINUED
-    
-    (void)obj;
+    SYS_UnlockReg();
+    CLK_PowerDown();
+    SYS_LockReg();
 }
 
 #endif
diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c
index 6b12a925f29..1ab0704fc26 100644
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c
@@ -469,25 +469,6 @@ uint8_t spi_active(spi_t *obj)
     return (spi_base->CTL & SPI_CTL_SPIEN_Msk);
 }
 
-int spi_allow_powerdown(void)
-{
-    uint32_t modinit_mask = spi_modinit_mask;
-    while (modinit_mask) {
-        int spi_idx = nu_ctz(modinit_mask);
-        const struct nu_modinit_s *modinit = spi_modinit_tab + spi_idx;
-        if (modinit->modname != NC) {
-            SPI_T *spi_base = (SPI_T *) NU_MODBASE(modinit->modname);
-            // Disallow entering power-down mode if SPI transfer is enabled.
-            if (spi_base->CTL & SPI_CTL_SPIEN_Msk) {
-                return 0;
-            }
-        }
-        modinit_mask &= ~(1 << spi_idx);
-    }
-    
-    return 1;
-}
-
 static int spi_writeable(spi_t * obj)
 {
     // Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive
diff --git a/targets/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/PinNames.h b/targets/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/PinNames.h
index 8ed4113f1f4..fa0b722f704 100644
--- a/targets/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/PinNames.h
+++ b/targets/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/PinNames.h
@@ -55,6 +55,32 @@ typedef enum {
     p18 = P0_26,
     p19 = P1_30,
     p20 = P1_31,
+#if defined(TARGET_LPC1769)
+    p21 = P0_2,
+    p22 = P0_3,
+    p23 = P0_21,
+    p24 = P0_22,
+    p25 = P0_27,
+    p26 = P0_28,
+    p27 = P2_13,
+
+    p38 = P0_4,
+    p39 = P0_5,
+    p40 = P0_10,
+    p41 = P0_11,
+    p42 = P2_0,
+    p43 = P2_1,
+    p44 = P2_2,
+    p45 = P2_3,
+    p46 = P2_4,
+    p47 = P2_5,
+    p48 = P2_6,
+    p49 = P2_7,
+    p50 = P2_8,
+    p51 = P2_10,
+    p52 = P2_11,
+    p53 = P2_12,
+#else
     p21 = P2_5,
     p22 = P2_4,
     p23 = P2_3,
@@ -65,6 +91,7 @@ typedef enum {
     p28 = P0_10,
     p29 = P0_5,
     p30 = P0_4,
+#endif
 
     // Other mbed Pin Names
 #ifdef MCB1700
@@ -72,6 +99,11 @@ typedef enum {
     LED2 = P1_29,
     LED3 = P1_31,
     LED4 = P2_2,
+#elif defined(TARGET_LPC1769)
+    LED1 = P0_22,
+    LED2 = P0_22,
+    LED3 = P0_22,
+    LED4 = P0_22,
 #else
     LED1 = P1_18,
     LED2 = P1_20,
@@ -113,8 +145,8 @@ typedef enum {
     I2C_SDA0 = NC,
     I2C_SCL1 = p10,
     I2C_SDA1 = p9,
-    I2C_SCL2 = p27, // pin used by application board
-    I2C_SDA2 = p28, // pin used by application board
+    I2C_SCL2 = P0_11, // pin used by application board
+    I2C_SDA2 = P0_10, // pin used by application board
     I2C_SCL = I2C_SCL2,
     I2C_SDA = I2C_SDA2,
 } PinName;
diff --git a/targets/TARGET_NXP/TARGET_LPC176X/device/CRP.c b/targets/TARGET_NXP/TARGET_LPC176X/device/CRP.c
new file mode 100644
index 00000000000..f2ae329670b
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_LPC176X/device/CRP.c
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *	 http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+ #include "mbed_toolchain.h"
+
+ /* Code Read Protection
+
+NONE	0xFFFFFFFF - No code protection.
+
+CRP1    0x12345678 - Write to RAM command can not access RAM below 0x10000200.
+                   - Read Memory command: disabled.
+                   - Copy RAM to Flash command: cannot write to Sector 0.
+                   - "Go" command: disabled.
+                   - Erase sector(s) command: can erase any individual sector except 
+                   	 sector 0 only, or can erase all sectors at once.
+                   - Compare command: disabled
+
+CRP2    0x87654321 - Write to RAM command: disabled.
+                   - Copy RAM to Flash: disabled.
+                   - Erase command: only allows erase of all sectors.
+
+CRP3    0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
+                     by pulling PIO0_1 LOW is disabled if a valid user code is
+                     present in flash sector 0.
+Caution: If CRP3 is selected, no future factory testing can be
+performed on the device.
+*/
+#if !defined(APPLICATION_ADDR) // Relocate CRP if there is a bootloader.
+    #define APPLICATION_ADDR 0
+#endif
+
+#define CRP_NONE	0xFFFFFFFF
+#define CRP_1		0x12345678 
+#define CRP_2		0x87654321
+#define CRP_3		0x43218765
+
+#ifndef CRP
+#define CRP CRP_NONE
+#endif
+
+MBED_SECTION(".CRPSection") MBED_USED const long CRP_Key = CRP;
diff --git a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_MICRO/LPC1768.sct b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_MICRO/LPC1768.sct
index 6af8037232f..44d51132a1d 100644
--- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_MICRO/LPC1768.sct
+++ b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_MICRO/LPC1768.sct
@@ -1,9 +1,24 @@
+#! armcc -E
 
-LR_IROM1 0x00000000 0x80000  {    ; load region size_region
-  ER_IROM1 0x00000000 0x80000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x00000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x80000
+#endif
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
+  ER_IROM0 MBED_APP_START 0x2FC  {  ; load address = execution address
+    *.o (RESET, +First)
+    .ANY (+RO)
+  }
+  ER_CRP (MBED_APP_START + 0x2FC) FIXED 4  {
+    *.o (.CRPSection)
+  }
+  ER_IROM1 (MBED_APP_START + (0x2FC + 4)) FIXED (MBED_APP_SIZE - (0x2FC + 4))  {
+    *(InRoot$$Sections)
+    .ANY (+RO)
   }
   ; 8_byte_aligned(49 vect * 4 bytes) =  8_byte_aligned(0xC4) = 0xC8
   ; 32KB (RAM size) - 0xC8 (NIVT) - 32 (topmost 32 bytes used by IAP functions) = 0x7F18
diff --git a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_MICRO/startup_LPC17xx.S b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_MICRO/startup_LPC17xx.S
index 9646f2f17c7..01b19858c3a 100644
--- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_MICRO/startup_LPC17xx.S
+++ b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_MICRO/startup_LPC17xx.S
@@ -99,12 +99,6 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
 
 
-                IF      :LNOT::DEF:NO_CRP
-                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
-CRP_Key         DCD     0xFFFFFFFF
-                ENDIF
-
-
                 AREA    |.text|, CODE, READONLY
 
 
diff --git a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_STD/LPC1768.sct b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_STD/LPC1768.sct
index 2e5afcd5e1e..f56aae73897 100644
--- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_STD/LPC1768.sct
+++ b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_STD/LPC1768.sct
@@ -1,9 +1,24 @@
+#! armcc -E
 
-LR_IROM1 0x00000000 0x80000  {    ; load region size_region
-  ER_IROM1 0x00000000 0x80000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x00000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x80000
+#endif
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
+  ER_IROM0 MBED_APP_START 0x2FC  {  ; load address = execution address
+    *.o (RESET, +First)
+    .ANY (+RO)
+  }
+  ER_CRP (MBED_APP_START + 0x2FC) FIXED 4  {
+    *.o (.CRPSection)
+  }
+  ER_IROM1 (MBED_APP_START + (0x2FC + 4)) FIXED (MBED_APP_SIZE - (0x2FC + 4))  {
+    *(InRoot$$Sections)
+    .ANY (+RO)
   }
   ; 8_byte_aligned(49 vect * 4 bytes) =  8_byte_aligned(0xC4) = 0xC8
   ; 32KB (RAM size) - 0xC8 (NIVT) - 32 (topmost 32 bytes used by IAP functions) = 0x7F18
diff --git a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_STD/startup_LPC17xx.S b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_STD/startup_LPC17xx.S
index 32e2abf7fbf..e844d2f9acb 100644
--- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_STD/startup_LPC17xx.S
+++ b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_STD/startup_LPC17xx.S
@@ -82,12 +82,6 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
 
 
-                IF      :LNOT::DEF:NO_CRP
-                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
-CRP_Key         DCD     0xFFFFFFFF
-                ENDIF
-
-
                 AREA    |.text|, CODE, READONLY
 
 
diff --git a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_ARM/LPC1768.ld b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_ARM/LPC1768.ld
index 8ab5bcaf22e..a4a05fcbfb9 100644
--- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_ARM/LPC1768.ld
+++ b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_ARM/LPC1768.ld
@@ -1,9 +1,15 @@
 /* Linker script for mbed LPC1768 */
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x00000000
+#endif
 
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 512K
+#endif
 /* Linker script to configure memory regions. */
 MEMORY
 {
-  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+  FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
   RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8 - 32)  /* topmost 32 bytes used by IAP functions */
 
   USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K
@@ -43,6 +49,10 @@ SECTIONS
     .text :
     {
         KEEP(*(.isr_vector))
+        /* Code Read Protect data */
+        . = 0x000002FC ;
+        KEEP(*(.CRPSection))
+        /* End of Code Read Protect */
         *(.text*)
 
         KEEP(*(.init))
@@ -65,6 +75,8 @@ SECTIONS
         *(.rodata*)
 
         KEEP(*(.eh_frame*))
+		
+		
     } > FLASH
 
     .ARM.extab : 
diff --git a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_IAR/LPC17xx.icf b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_IAR/LPC17xx.icf
index ae22e24652f..0cea4b47c71 100644
--- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_IAR/LPC17xx.icf
+++ b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_IAR/LPC17xx.icf
@@ -1,15 +1,17 @@
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x80000; }
 /*###ICF### Section handled by ICF editor, don't touch! ****/
 /*-Editor annotation file-*/
 /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
 /*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
 /*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__   = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__     = 0x0007FFFF;
+define symbol __ICFEDIT_region_ROM_start__   = MBED_APP_START;
+define symbol __ICFEDIT_region_ROM_end__     = MBED_APP_START + MBED_APP_SIZE - 1;
 define symbol __ICFEDIT_region_NVIC_start__   = 0x10000000;
 define symbol __ICFEDIT_region_NVIC_end__   = 0x100000C7;
 define symbol __ICFEDIT_region_RAM_start__   = 0x100000C8;
-define symbol __ICFEDIT_region_RAM_end__     = 0x10007FDF;
+define symbol __ICFEDIT_region_RAM_end__     = 0x10007FE0;
 
 /*-Sizes-*/
 /*Heap 1/4 of ram and stack 1/8*/
@@ -17,8 +19,8 @@ define symbol __ICFEDIT_size_cstack__   = 0x1000;
 define symbol __ICFEDIT_size_heap__     = 0x2000;
 /**** End of ICF editor section. ###ICF###*/
 
-define symbol __CRP_start__   = 0x000002FC;
-define symbol __CRP_end__     = 0x000002FF;
+define symbol __CRP_start__   = MBED_APP_START + 0x000002FC;
+define symbol __CRP_end__     = MBED_APP_START + 0x000002FF;
 
 define symbol __RAM1_start__  = 0x2007C000;
 define symbol __RAM1_end__    = 0x20083FFF;
@@ -41,5 +43,5 @@ place in ROM_region   { readonly };
 place in RAM_region   { readwrite,
                         block HEAP, block CSTACK };
 
-place in CRP_region  	{ section .crp };
+place in CRP_region  	{ section .CRPSection };
 place in RAM1_region	{ section .ethusbram };
diff --git a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_IAR/startup_LPC17xx.S b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_IAR/startup_LPC17xx.S
index 4ffb5331abf..52b1c39d4f8 100644
--- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_IAR/startup_LPC17xx.S
+++ b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_IAR/startup_LPC17xx.S
@@ -350,26 +350,4 @@ USBActivity_IRQHandler
 CANActivity_IRQHandler
         B CANActivity_IRQHandler
 
-#ifndef SRAM
-        SECTION .crp:CODE:ROOT(2)
-        DATA
-/* Code Read Protection
-CRP1    0x12345678 - Write to RAM command can not access RAM below 0x10000200.
-                   - Read Memory command: disabled.
-                   - Copy RAM to Flash command: cannot write to Sector 0.
-                   - "Go" command: disabled.
-                   - Erase sector(s) command: can erase any individual sector except 
-                   	 sector 0 only, or can erase all sectors at once.
-                   - Compare command: disabled
-CRP2    0x87654321 - Write to RAM command: disabled.
-                   - Copy RAM to Flash: disabled.
-                   - Erase command: only allows erase of all sectors.
-CRP3    0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
-                     by pulling PIO0_1 LOW is disabled if a valid user code is
-                     present in flash sector 0.
-Caution: If CRP3 is selected, no future factory testing can be
-performed on the device.
-*/
-	DCD	0xFFFFFFFF
-#endif
         END
diff --git a/targets/TARGET_NXP/TARGET_LPC176X/device/flash_api.c b/targets/TARGET_NXP/TARGET_LPC176X/device/flash_api.c
index 0b140350bf5..03adf3b674a 100644
--- a/targets/TARGET_NXP/TARGET_LPC176X/device/flash_api.c
+++ b/targets/TARGET_NXP/TARGET_LPC176X/device/flash_api.c
@@ -13,55 +13,169 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
+#if DEVICE_FLASH
+#include "mbed_critical.h"
 
 #include "flash_api.h"
-#include "platform/mbed_critical.h"
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include <stdlib.h>
+#include <string.h>
 
-// This file is automatically generated
+#define MEMMAP     (*((volatile unsigned long *) 0x400FC040))
 
-#if DEVICE_FLASH
+#define PLL0CON    (*((volatile unsigned long *) 0x400FC080))
+#define PLL0CFG    (*((volatile unsigned long *) 0x400FC084))
+#define PLL0STAT   (*((volatile unsigned long *) 0x400FC088))
+#define PLL0FEED   (*((volatile unsigned long *) 0x400FC08C))
+#define CCLKSEL    (*((volatile unsigned long *) 0x400FC104))
+#define CLKSRCSEL  (*((volatile unsigned long *) 0x400FC10C))
+
+#define STACK_SIZE 64 // Stack Size
+
+#define SET_VALID_CODE 1 // Set Valid User Code Signature
+/* IAP Call */
+typedef void (*IAP_Entry) (unsigned long *cmd, unsigned long *stat);
+#define IAP_Call ((IAP_Entry) 0x1FFF1FF1)
+
+typedef struct flash_s flash_t;
+unsigned long CCLK; // CCLK in kHz
+
+struct sIAP { // IAP Structure
+    unsigned long cmd;// Command
+    unsigned long par[4];// Parameters
+    unsigned long stat;// Status
+    unsigned long res[2];// Result
+}IAP;
+
+/*
+ * Get Sector Number
+ *    Parameter:      address:  Sector Address
+ *    Return Value:   Sector Number
+ */
+
+unsigned long GetSecNum (unsigned long address)
+{
+    unsigned long n;
+
+    n = address >> 12; // 4kB Sector
+    if (n >= 0x10) {
+        n = 0x0E + (n >> 3); // 32kB Sector
+    }
+
+    return (n); // Sector Number
+}
+int32_t flash_init(flash_t *obj)
+{
+    CCLK = SystemCoreClock / 1000; // CCLK value is in kHz, clk in Hz
+
+    MEMMAP = 0x01;// User Flash Mode
+
+    return (0);
+}
+
+int32_t flash_free(flash_t *obj)
+{
+    return 0;
+}
+
+int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+    unsigned long n;
+
+    n = GetSecNum(address); // Get Sector Number
+
+    core_util_critical_section_enter();
+    IAP.cmd = 50;// Prepare Sector for Erase
+    IAP.par[0] = n;// Start Sector
+    IAP.par[1] = n;// End Sector
+    IAP_Call (&IAP.cmd, &IAP.stat);// Call IAP Command
+    if (IAP.stat) {
+        return (1); // Command Failed
+    }
+
+    IAP.cmd = 52; // Erase Sector
+    IAP.par[0] = n;// Start Sector
+    IAP.par[1] = n;// End Sector
+    IAP.par[2] = CCLK;// CCLK in kHz
+    IAP_Call (&IAP.cmd, &IAP.stat);// Call IAP Command
+    core_util_critical_section_exit();
+    if (IAP.stat) {
+        return (1); // Command Failed
+    }
+
+    return (0); // Finished without Errors
+
+}
+
+int32_t flash_program_page(flash_t *obj, uint32_t address,
+        const uint8_t *data, uint32_t size)
+{
+    unsigned long n;
+    // always malloc outside critical section
+    uint8_t *alignedData = malloc(size);
+
+    n = GetSecNum(address); // Get Sector Number
+
+    core_util_critical_section_enter();
+    IAP.cmd = 50;// Prepare Sector for Write
+    IAP.par[0] = n;// Start Sector
+    IAP.par[1] = n;// End Sector
+    IAP_Call (&IAP.cmd, &IAP.stat);// Call IAP Command
+    if (IAP.stat) {
+        return (1); // Command Failed
+    }
+
+    IAP.cmd = 51; // Copy RAM to Flash
+    IAP.par[0] = address;// Destination Flash Address
+
+    if ((unsigned long)data%4==0) { // Word boundary
+        IAP.par[1] = (unsigned long)data;// Source RAM Address
+    } else {
+        memcpy(alignedData,data,size);
+        IAP.par[1] = (unsigned long)alignedData; // Source RAM Address
+    }
+
+    IAP.par[2] = 1024; // Fixed Page Size
+    IAP.par[3] = CCLK;// CCLK in kHz
+    IAP_Call (&IAP.cmd, &IAP.stat);// Call IAP Command
+    core_util_critical_section_exit();
+
+    if(alignedData !=0) { // We allocated our own memory
+        free(alignedData);
+    }
+
+    if (IAP.stat) {
+        return (1); // Command Failed
+    }
+    return (0); // Finished without Errors
+}
+
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
+{
+    if (address < flash_get_start_address(obj) || address >= flash_get_start_address(obj) +flash_get_size(obj)) {
+        return MBED_FLASH_INVALID_SIZE;
+    }
+    if(GetSecNum(address)>=0x10) {
+        return 0x8000;
+    } else {
+        return 0x1000;
+    }
+}
+
+uint32_t flash_get_page_size(const flash_t *obj)
+{
+    return 1024;
+}
+
+uint32_t flash_get_start_address(const flash_t *obj)
+{
+    return LPC_FLASH_BASE;
+}
 
-#include "flash_data.h"
-
-// This is a flash algo binary blob. It is PIC (position independent code) that should be stored in RAM
-static uint32_t FLASH_ALGO[] = {
-    0x28100b00, 0x210ed302, 0x00d0eb01, 0xf44f4770, 0xfbb1707a, 0x4933f0f0, 0x60084449, 0x20014932,
-    0x20006408, 0x20004770, 0xe92d4770, 0xf7ff41f0, 0x4d2effe7, 0x444d4604, 0xe9c52032, 0xf1050400,
-    0x4e2b0114, 0x4628460f, 0x47b060ac, 0xb9686968, 0xe9c52034, 0x48230400, 0x444860ac, 0x68004639,
-    0x462860e8, 0x696847b0, 0xd0002800, 0xe8bd2001, 0xe92d81f0, 0x461441f0, 0xd10e0006, 0x0100e9d4,
-    0xe9d44408, 0x44111202, 0x69214408, 0x69614408, 0x69a14408, 0x42404408, 0x463061e0, 0xffb0f7ff,
-    0x21324d12, 0x4f12444d, 0x1000e9c5, 0x0114f105, 0x468860a8, 0x47b84628, 0xb9806968, 0xe9c52033,
-    0xf44f0600, 0xe9c56080, 0x48064002, 0x44484641, 0x61286800, 0x47b84628, 0x28006968, 0x2001d0c7,
-    0x0000e7c5, 0x00000004, 0x400fc000, 0x00000008, 0x1fff1ff1, 0x00000000, 0x00000000, 0x00000000,
-    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-};
-
-static const flash_algo_t flash_algo_config = {
-    .init = 0xf,
-    .uninit = 0x27,
-    .erase_sector = 0x2b,
-    .program_page = 0x73,
-    .static_base = 0xf4,
-    .algo_blob = FLASH_ALGO
-};
-
-static const sector_info_t sectors_info[] = {
-    {0x0, 0x1000},
-    {0x10000, 0x8000},
-};
-
-static const flash_target_config_t flash_target_config = {
-    .page_size  = 0x400,
-    .flash_start = 0x0,
-    .flash_size = 0x80000,
-    .sectors = sectors_info,
-    .sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t)
-};
-
-void flash_set_target_config(flash_t *obj)
+uint32_t flash_get_size(const flash_t *obj)
 {
-    obj->flash_algo = &flash_algo_config;
-    obj->target_config = &flash_target_config;
+    return 0x80000;
 }
 
 #endif
diff --git a/targets/TARGET_NXP/TARGET_LPC176X/objects.h b/targets/TARGET_NXP/TARGET_LPC176X/objects.h
index ecbd354934b..331ccc9ceba 100644
--- a/targets/TARGET_NXP/TARGET_LPC176X/objects.h
+++ b/targets/TARGET_NXP/TARGET_LPC176X/objects.h
@@ -71,6 +71,10 @@ struct spi_s {
     LPC_SSP_TypeDef *spi;
 };
 
+struct flash_s {
+	/*  nothing to be stored for now */
+	uint32_t dummy;
+};
 #ifdef __cplusplus
 }
 #endif
diff --git a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c
index 54d97dbb0d2..7ea6885fbf2 100644
--- a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c
+++ b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c
@@ -52,25 +52,25 @@ const int ethernet_MTU_SIZE  = 0x300;
 
 #define ETHERNET_ADDR_SIZE 6
 
-PACKED struct RX_DESC_TypeDef {                        /* RX Descriptor struct              */
+MBED_PACKED(struct) RX_DESC_TypeDef {                        /* RX Descriptor struct              */
    unsigned int Packet;
    unsigned int Ctrl;
 };
 typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
 
-PACKED struct RX_STAT_TypeDef {                        /* RX Status struct                  */
+MBED_PACKED(struct) RX_STAT_TypeDef {                        /* RX Status struct                  */
    unsigned int Info;
    unsigned int HashCRC;
 };
 typedef struct RX_STAT_TypeDef RX_STAT_TypeDef;
 
-PACKED struct TX_DESC_TypeDef {                        /* TX Descriptor struct              */
+MBED_PACKED(struct) TX_DESC_TypeDef {                        /* TX Descriptor struct              */
    unsigned int Packet;
    unsigned int Ctrl;
 };
 typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
 
-PACKED struct TX_STAT_TypeDef {                        /* TX Status struct                  */
+MBED_PACKED(struct) TX_STAT_TypeDef {                        /* TX Status struct                  */
    unsigned int Info;
 };
 typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
@@ -436,9 +436,9 @@ int ethernet_init() {
   int regv, tout;
   char mac[ETHERNET_ADDR_SIZE];
   unsigned int clock = clockselect();
-  
+
   LPC_SC->PCONP |= 0x40000000;                       /* Power Up the EMAC controller. */
-  
+
   LPC_IOCON->P1_0  &= ~0x07;    /*  ENET I/O config */
   LPC_IOCON->P1_0  |= 0x01;     /* ENET_TXD0 */
   LPC_IOCON->P1_1  &= ~0x07;
@@ -459,7 +459,7 @@ int ethernet_init() {
   LPC_IOCON->P1_16 |= 0x01;     /* ENET_MDC */
   LPC_IOCON->P1_17 &= ~0x07;
   LPC_IOCON->P1_17 |= 0x01;     /* ENET_MDIO */
-  
+
    /* Reset all EMAC internal modules. */
   LPC_EMAC->MAC1    = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX |
                       MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
@@ -523,7 +523,7 @@ int ethernet_init() {
 
   LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;    /* Enable EMAC interrupts. */
   LPC_EMAC->IntClear  = 0xFFFF;                       /* Reset all interrupts */
-  
+
   LPC_EMAC->Command  |= (CR_RX_EN | CR_TX_EN);        /* Enable receive and transmit mode of MAC Ethernet core */
   LPC_EMAC->MAC1     |= MAC1_REC_EN;
 
@@ -548,9 +548,9 @@ int ethernet_init() {
 void ethernet_free() {
     LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE);
     LPC_EMAC->IntClear   =  0xFFFF;
-    
+
     LPC_SC->PCONP   &= ~0x40000000;       /* Power down the EMAC controller. */
-    
+
     LPC_IOCON->P1_0  &= ~0x07;    /*  ENET I/O config */
     LPC_IOCON->P1_1  &= ~0x07;
     LPC_IOCON->P1_4  &= ~0x07;
@@ -908,22 +908,22 @@ void ethernet_address(char *mac) {
 void ethernet_set_link(int speed, int duplex) {
     unsigned short phy_data;
     int tout;
-    
+
     if((speed < 0) || (speed > 1)) {
         phy_data = PHY_AUTO_NEG;
     } else {
         phy_data = (((unsigned short) speed << 13) |
                     ((unsigned short) duplex << 8));
     }
-    
+
     phy_write(PHY_REG_BMCR, phy_data);
-    
+
     for (tout = 100; tout; tout--) { __NOP(); }     /* A short delay */
-    
+
     switch(phy_id) {
         case DP83848C_ID:
             phy_data = phy_read(PHY_REG_STS);
-            
+
             if(phy_data & PHY_STS_DUPLEX) {
                 LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
                 LPC_EMAC->Command |= CR_FULL_DUP;
@@ -933,17 +933,17 @@ void ethernet_set_link(int speed, int duplex) {
                 LPC_EMAC->Command &= ~CR_FULL_DUP;
                 LPC_EMAC->IPGT = IPGT_HALF_DUP;
             }
-            
+
             if(phy_data & PHY_STS_SPEED) {
                 LPC_EMAC->SUPP &= ~SUPP_SPEED;
             } else {
                 LPC_EMAC->SUPP |= SUPP_SPEED;
             }
             break;
-        
+
         case LAN8720_ID:
             phy_data = phy_read(PHY_REG_SCSR);
-            
+
             if (phy_data & PHY_SCSR_DUPLEX) {
                 LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
                 LPC_EMAC->Command |= CR_FULL_DUP;
@@ -952,13 +952,13 @@ void ethernet_set_link(int speed, int duplex) {
                 LPC_EMAC->Command &= ~CR_FULL_DUP;
                 LPC_EMAC->IPGT = IPGT_HALF_DUP;
             }
-            
+
             if(phy_data & PHY_SCSR_100MBIT) {
                 LPC_EMAC->SUPP |= SUPP_SPEED;
             } else {
                 LPC_EMAC->SUPP &= ~SUPP_SPEED;
             }
-            
+
             break;
     }
 }
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/cmsis_nvic.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/cmsis_nvic.h
new file mode 100644
index 00000000000..584b9075a85
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/cmsis_nvic.h
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+extern uint32_t Image$$VECTOR_RAM$$Base[];
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
+#else
+extern uint32_t __VECTOR_RAM[];
+#endif
+
+/* Symbols defined by the linker script */
+#define NVIC_NUM_VECTORS        (16 + 40)         // CORE + MCU Peripherals
+#define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM)    // Vectors positioned at start of RAM
+
+#endif
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/libpower.a b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/libpower.a
deleted file mode 100644
index f5e2ab0bdb0..00000000000
Binary files a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/libpower.a and /dev/null differ
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/libpower.a b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/libpower.a
deleted file mode 100644
index f5f23f69e50..00000000000
Binary files a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/libpower.a and /dev/null differ
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralNames.h
new file mode 100644
index 00000000000..7efa1e5c20e
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralNames.h
@@ -0,0 +1,113 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    OSC32KCLK = 0,
+} RTCName;
+
+typedef enum {
+    UART_0 = Flexcomm0,
+    UART_2 = Flexcomm2,
+    UART_7 = Flexcomm7
+} UARTName;
+
+#define STDIO_UART_TX     USBTX
+#define STDIO_UART_RX     USBRX
+#define STDIO_UART        UART_0
+
+typedef enum {
+    I2C_7 = Flexcomm7,
+    I2C_2 = Flexcomm2
+} I2CName;
+
+#define TPM_SHIFT   8
+typedef enum {
+    PWM_1  = (0 << TPM_SHIFT) | (0),  // FTM0 CH0
+    PWM_2  = (0 << TPM_SHIFT) | (1),  // FTM0 CH1
+    PWM_3  = (0 << TPM_SHIFT) | (2),  // FTM0 CH2
+    PWM_4  = (0 << TPM_SHIFT) | (3),  // FTM0 CH3
+    PWM_5  = (0 << TPM_SHIFT) | (4),  // FTM0 CH4
+    PWM_6  = (0 << TPM_SHIFT) | (5),  // FTM0 CH5
+    PWM_7  = (0 << TPM_SHIFT) | (6),  // FTM0 CH6
+    PWM_8  = (0 << TPM_SHIFT) | (7),  // FTM0 CH7
+    PWM_9  = (1 << TPM_SHIFT) | (0),  // FTM1 CH0
+    PWM_10 = (1 << TPM_SHIFT) | (1),  // FTM1 CH1
+    PWM_11 = (1 << TPM_SHIFT) | (2),  // FTM1 CH2
+    PWM_12 = (1 << TPM_SHIFT) | (3),  // FTM1 CH3
+    PWM_13 = (1 << TPM_SHIFT) | (4),  // FTM1 CH4
+    PWM_14 = (1 << TPM_SHIFT) | (5),  // FTM1 CH5
+    PWM_15 = (1 << TPM_SHIFT) | (6),  // FTM1 CH6
+    PWM_16 = (1 << TPM_SHIFT) | (7),  // FTM1 CH7
+    PWM_17 = (2 << TPM_SHIFT) | (0),  // FTM2 CH0
+    PWM_18 = (2 << TPM_SHIFT) | (1),  // FTM2 CH1
+    PWM_19 = (2 << TPM_SHIFT) | (2),  // FTM2 CH2
+    PWM_20 = (2 << TPM_SHIFT) | (3),  // FTM2 CH3
+    PWM_21 = (2 << TPM_SHIFT) | (4),  // FTM2 CH4
+    PWM_22 = (2 << TPM_SHIFT) | (5),  // FTM2 CH5
+    PWM_23 = (2 << TPM_SHIFT) | (6),  // FTM2 CH6
+    PWM_24 = (2 << TPM_SHIFT) | (7),  // FTM2 CH7
+    PWM_25 = (3 << TPM_SHIFT) | (0),  // FTM3 CH0
+    PWM_26 = (3 << TPM_SHIFT) | (1),  // FTM3 CH1
+    PWM_27 = (3 << TPM_SHIFT) | (2),  // FTM3 CH2
+    PWM_28 = (3 << TPM_SHIFT) | (3),  // FTM3 CH3
+    PWM_29 = (3 << TPM_SHIFT) | (4),  // FTM3 CH4
+    PWM_30 = (3 << TPM_SHIFT) | (5),  // FTM3 CH5
+    PWM_31 = (3 << TPM_SHIFT) | (6),  // FTM3 CH6
+    PWM_32 = (3 << TPM_SHIFT) | (7),  // FTM3 CH7
+} PWMName;
+
+#define ADC_INSTANCE_SHIFT         8
+#define ADC_B_CHANNEL_SHIFT        5
+
+typedef enum {
+    ADC0_SE0  = 0,
+    ADC0_SE1  = 1,
+    ADC0_SE2  = 2,
+    ADC0_SE3  = 3,
+    ADC0_SE4  = 4,
+    ADC0_SE5  = 5,
+    ADC0_SE6  = 6,
+    ADC0_SE7  = 7,
+    ADC0_SE8  = 8,
+    ADC0_SE9  = 9,
+    ADC0_SE10 = 10,
+    ADC0_SE11 = 11,
+} ADCName;
+
+typedef enum {
+    CAN_1 = 1
+} CANName;
+
+typedef enum {
+    SPI_0 = Flexcomm0,
+    SPI_2 = Flexcomm2,
+    SPI_3 = Flexcomm3
+} SPIName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c
new file mode 100644
index 00000000000..bb555ca3b71
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c
@@ -0,0 +1,125 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PeripheralPins.h"
+
+/************RTC***************/
+const PinMap PinMap_RTC[] = {
+    {NC, OSC32KCLK, 0},
+};
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+    {P0_15,  ADC0_SE3,   0},
+    {P0_16,  ADC0_SE4,   0},
+    {P0_23,  ADC0_SE11,  0},
+    {P0_31,  ADC0_SE5,   0},
+    {P1_0,   ADC0_SE6,   0},
+    {P0_10,  ADC0_SE0,   0},
+    {NC   ,  NC      ,   0}
+};
+
+/************CAN***************/
+const PinMap PinMap_CAN_TD[] = {
+    {P0_1,  CAN_1,  1},
+    {NC  ,  NC   ,  0}
+};
+
+const PinMap PinMap_CAN_RD[] = {
+    {P0_0, CAN_1,  1},
+    {NC  , NC   ,  0}
+};
+
+
+/************DAC***************/
+const PinMap PinMap_DAC[] = {
+    {NC      , NC   , 0}
+};
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+    {P0_26, I2C_2, 1},
+    {P1_29, I2C_7, 1},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {P0_27, I2C_2, 1},
+    {P1_30, I2C_7, 1},
+    {NC   , NC   , 0}
+};
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+    {P0_30, UART_0, 1},
+    {P0_27, UART_2, 1},
+    {P1_30, UART_7, 1},
+    {NC   ,  NC   , 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {P0_29, UART_0, 1},
+    {P0_26, UART_2, 1},
+    {P1_29, UART_7, 1},
+    {NC   ,  NC   , 0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+    {NC   , NC    , 0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {NC   , NC    , 0}
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+    {P1_4,  SPI_0, 1},
+    {P1_23, SPI_2, 1},
+    {P0_6,  SPI_3, 1},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {P1_5,  SPI_0, 1},
+    {P1_24, SPI_2, 1},
+    {P0_8,  SPI_3, 1},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {P1_6,  SPI_0, 1},
+    {P1_25, SPI_2, 1},
+    {P0_9,  SPI_3, 1},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {P1_7,  SPI_0, 1},
+    {P0_7,  SPI_3, 1},
+    {NC  ,  NC   , 0}
+};
+
+/************PWM***************/
+const PinMap PinMap_PWM[] = {
+    {P0_17   , PWM_1,  4},
+    {P0_18   , PWM_2,  4},
+    {P0_19   , PWM_3,  4},
+    {P0_22   , PWM_4,  4},
+    {P0_28   , PWM_8,  4},
+    {P0_29   , PWM_9,  4},
+    {NC      , NC,     0}
+};
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h
new file mode 100644
index 00000000000..bc22e8e4bce
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h
@@ -0,0 +1,250 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  5
+
+typedef enum {
+    P0_0 = (0 << PORT_SHIFT | 0),
+    P0_1 = (0 << PORT_SHIFT | 1),
+    P0_2 = (0 << PORT_SHIFT | 2),
+    P0_3 = (0 << PORT_SHIFT | 3),
+    P0_4 = (0 << PORT_SHIFT | 4),
+    P0_5 = (0 << PORT_SHIFT | 5),
+    P0_6 = (0 << PORT_SHIFT | 6),
+    P0_7 = (0 << PORT_SHIFT | 7),
+    P0_8 = (0 << PORT_SHIFT | 8),
+    P0_9 = (0 << PORT_SHIFT | 9),
+    P0_10 = (0 << PORT_SHIFT | 10),
+    P0_11 = (0 << PORT_SHIFT | 11),
+    P0_12 = (0 << PORT_SHIFT | 12),
+    P0_13 = (0 << PORT_SHIFT | 13),
+    P0_14 = (0 << PORT_SHIFT | 14),
+    P0_15 = (0 << PORT_SHIFT | 15),
+    P0_16 = (0 << PORT_SHIFT | 16),
+    P0_17 = (0 << PORT_SHIFT | 17),
+    P0_18 = (0 << PORT_SHIFT | 18),
+    P0_19 = (0 << PORT_SHIFT | 19),
+    P0_20 = (0 << PORT_SHIFT | 20),
+    P0_21 = (0 << PORT_SHIFT | 21),
+    P0_22 = (0 << PORT_SHIFT | 22),
+    P0_23 = (0 << PORT_SHIFT | 23),
+    P0_24 = (0 << PORT_SHIFT | 24),
+    P0_25 = (0 << PORT_SHIFT | 25),
+    P0_26 = (0 << PORT_SHIFT | 26),
+    P0_27 = (0 << PORT_SHIFT | 27),
+    P0_28 = (0 << PORT_SHIFT | 28),
+    P0_29 = (0 << PORT_SHIFT | 29),
+    P0_30 = (0 << PORT_SHIFT | 30),
+    P0_31 = (0 << PORT_SHIFT | 31),
+
+    P1_0 = (1 << PORT_SHIFT | 0),
+    P1_1 = (1 << PORT_SHIFT | 1),
+    P1_2 = (1 << PORT_SHIFT | 2),
+    P1_3 = (1 << PORT_SHIFT | 3),
+    P1_4 = (1 << PORT_SHIFT | 4),
+    P1_5 = (1 << PORT_SHIFT | 5),
+    P1_6 = (1 << PORT_SHIFT | 6),
+    P1_7 = (1 << PORT_SHIFT | 7),
+    P1_8 = (1 << PORT_SHIFT | 8),
+    P1_9 = (1 << PORT_SHIFT | 9),
+    P1_10 = (1 << PORT_SHIFT | 10),
+    P1_11 = (1 << PORT_SHIFT | 11),
+    P1_12 = (1 << PORT_SHIFT | 12),
+    P1_13 = (1 << PORT_SHIFT | 13),
+    P1_14 = (1 << PORT_SHIFT | 14),
+    P1_15 = (1 << PORT_SHIFT | 15),
+    P1_16 = (1 << PORT_SHIFT | 16),
+    P1_17 = (1 << PORT_SHIFT | 17),
+    P1_18 = (1 << PORT_SHIFT | 18),
+    P1_19 = (1 << PORT_SHIFT | 19),
+    P1_20 = (1 << PORT_SHIFT | 20),
+    P1_21 = (1 << PORT_SHIFT | 21),
+    P1_22 = (1 << PORT_SHIFT | 22),
+    P1_23 = (1 << PORT_SHIFT | 23),
+    P1_24 = (1 << PORT_SHIFT | 24),
+    P1_25 = (1 << PORT_SHIFT | 25),
+    P1_26 = (1 << PORT_SHIFT | 26),
+    P1_27 = (1 << PORT_SHIFT | 27),
+    P1_28 = (1 << PORT_SHIFT | 28),
+    P1_29 = (1 << PORT_SHIFT | 29),
+    P1_30 = (1 << PORT_SHIFT | 30),
+    P1_31 = (1 << PORT_SHIFT | 31),
+
+    P2_0 = (2 <<  PORT_SHIFT | 0),
+    P2_1 = (2 <<  PORT_SHIFT | 1),
+    P2_2 = (2 <<  PORT_SHIFT | 2),
+    P2_3 = (2 <<  PORT_SHIFT | 3),
+    P2_4 = (2 <<  PORT_SHIFT | 4),
+    P2_5 = (2 <<  PORT_SHIFT | 5),
+    P2_6 = (2 <<  PORT_SHIFT | 6),
+    P2_7 = (2 <<  PORT_SHIFT | 7),
+    P2_8 = (2 <<  PORT_SHIFT | 8),
+    P2_9 = (2 <<  PORT_SHIFT | 9),
+    P2_10 = (2 <<  PORT_SHIFT | 10),
+    P2_11 = (2 <<  PORT_SHIFT | 11),
+    P2_12 = (2 <<  PORT_SHIFT | 12),
+    P2_13 = (2 <<  PORT_SHIFT | 13),
+    P2_14 = (2 <<  PORT_SHIFT | 14),
+    P2_15 = (2 <<  PORT_SHIFT | 15),
+    P2_16 = (2 <<  PORT_SHIFT | 16),
+    P2_17 = (2 <<  PORT_SHIFT | 17),
+    P2_18 = (2 <<  PORT_SHIFT | 18),
+    P2_19 = (2 <<  PORT_SHIFT | 19),
+    P2_20 = (2 <<  PORT_SHIFT | 20),
+    P2_21 = (2 <<  PORT_SHIFT | 21),
+    P2_22 = (2 <<  PORT_SHIFT | 22),
+    P2_23 = (2 <<  PORT_SHIFT | 23),
+    P2_24 = (2 <<  PORT_SHIFT | 24),
+    P2_25 = (2 <<  PORT_SHIFT | 25),
+    P2_26 = (2 <<  PORT_SHIFT | 26),
+    P2_27 = (2 <<  PORT_SHIFT | 27),
+    P2_28 = (2 <<  PORT_SHIFT | 28),
+    P2_29 = (2 <<  PORT_SHIFT | 29),
+    P2_30 = (2 <<  PORT_SHIFT | 30),
+    P2_31 = (2 <<  PORT_SHIFT | 31),
+
+    P3_0 = (3 <<  PORT_SHIFT | 0),
+    P3_1 = (3 <<  PORT_SHIFT | 1),
+    P3_2 = (3 <<  PORT_SHIFT | 2),
+    P3_3 = (3 <<  PORT_SHIFT | 3),
+    P3_4 = (3 <<  PORT_SHIFT | 4),
+    P3_5 = (3 <<  PORT_SHIFT | 5),
+    P3_6 = (3 <<  PORT_SHIFT | 6),
+    P3_7 = (3 <<  PORT_SHIFT | 7),
+    P3_8 = (3 <<  PORT_SHIFT | 8),
+    P3_9 = (3 <<  PORT_SHIFT | 9),
+    P3_10 = (3 <<  PORT_SHIFT | 10),
+    P3_11 = (3 <<  PORT_SHIFT | 11),
+    P3_12 = (3 <<  PORT_SHIFT | 12),
+    P3_13 = (3 <<  PORT_SHIFT | 13),
+    P3_14 = (3 <<  PORT_SHIFT | 14),
+    P3_15 = (3 <<  PORT_SHIFT | 15),
+    P3_16 = (3 <<  PORT_SHIFT | 16),
+    P3_17 = (3 <<  PORT_SHIFT | 17),
+    P3_18 = (3 <<  PORT_SHIFT | 18),
+    P3_19 = (3 <<  PORT_SHIFT | 19),
+    P3_20 = (3 <<  PORT_SHIFT | 20),
+    P3_21 = (3 <<  PORT_SHIFT | 21),
+    P3_22 = (3 <<  PORT_SHIFT | 22),
+    P3_23 = (3 <<  PORT_SHIFT | 23),
+    P3_24 = (3 <<  PORT_SHIFT | 24),
+    P3_25 = (3 <<  PORT_SHIFT | 25),
+    P3_26 = (3 <<  PORT_SHIFT | 26),
+    P3_27 = (3 <<  PORT_SHIFT | 27),
+    P3_28 = (3 <<  PORT_SHIFT | 28),
+    P3_29 = (3 <<  PORT_SHIFT | 29),
+    P3_30 = (3 <<  PORT_SHIFT | 30),
+    P3_31 = (3 <<  PORT_SHIFT | 31),
+
+    P4_0 = (4 <<  PORT_SHIFT | 0),
+    P4_1 = (4 <<  PORT_SHIFT | 1),
+    P4_2 = (4 <<  PORT_SHIFT | 2),
+    P4_3 = (4 <<  PORT_SHIFT | 3),
+    P4_4 = (4 <<  PORT_SHIFT | 4),
+    P4_5 = (4 <<  PORT_SHIFT | 5),
+    P4_6 = (4 <<  PORT_SHIFT | 6),
+    P4_7 = (4 <<  PORT_SHIFT | 7),
+    P4_8 = (4 <<  PORT_SHIFT | 8),
+    P4_9 = (4 <<  PORT_SHIFT | 9),
+    P4_10 = (4 <<  PORT_SHIFT | 10),
+    P4_11 = (4 <<  PORT_SHIFT | 11),
+    P4_12 = (4 <<  PORT_SHIFT | 12),
+    P4_13 = (4 <<  PORT_SHIFT | 13),
+    P4_14 = (4 <<  PORT_SHIFT | 14),
+    P4_15 = (4 <<  PORT_SHIFT | 15),
+    P4_16 = (4 <<  PORT_SHIFT | 16),
+
+
+
+    // mbed original LED naming
+    LED1 = P0_13,
+    LED2 = P1_27,
+    LED3 = P0_14,
+    LED4 = P1_28,
+
+
+    // USB Pins
+    USBTX = P0_30,
+    USBRX = P0_29,
+
+
+    A0 = P0_16,
+    A1 = P0_31,
+    A2 = P1_0,
+    A3 = P2_0,
+    A4 = P3_4,
+    A5 = P1_1,
+
+
+    p5  = P1_24,
+    p6  = P1_25,
+    p7  = P1_23,
+    p8  = P1_8,
+    p9  = P0_26,
+    p10 = P0_27,
+    p11 = P1_4,
+    p12 = P1_5,
+    p13 = P1_6,
+    p14 = P1_7,
+    p15 = P0_15,
+    p16 = P0_16,
+    p17 = P0_23,
+    p18 = P0_31,
+    p19 = P1_0,
+    p20 = P0_10,
+    p21 = P0_17,
+    p22 = P0_18,
+    p23 = P0_19,
+    p24 = P0_22,
+    p25 = P0_28,
+    p26 = P0_29,
+    p27 = P1_30,
+    p28 = P1_29,
+    p29 = P0_0,
+    p30 = P0_1,
+
+
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+
+typedef enum {
+    PullNone = 0,
+    PullDown = 1,
+    PullUp   = 2,
+    PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/clock_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.c
similarity index 99%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/clock_config.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.c
index fd94300ab2c..cea986a6c04 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/clock_config.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.c
@@ -45,11 +45,11 @@
 /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
 !!ClocksProfile
 product: Clocks v1.0
-processor: LPC54608J512
-package_id: LPC54608J512ET180
+processor: LPC54618J512
+package_id: LPC54618J512ET180
 mcu_data: ksdk2_0
 processor_version: 0.0.0
-board: LPCXpresso54608
+board: LPCXpresso54618
  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
 
 #include "fsl_power.h"
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/clock_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/clock_config.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/device.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/device.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/device.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/device.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/mbed_overrides.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PeripheralNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/PeripheralNames.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PeripheralNames.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/PeripheralNames.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PeripheralPins.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/PeripheralPins.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PeripheralPins.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/PeripheralPins.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PinNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/PinNames.h
similarity index 99%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PinNames.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/PinNames.h
index ccb3268eed0..66d9e7c17cf 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PinNames.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/PinNames.h
@@ -183,9 +183,9 @@ typedef enum {
     LED_RED   = P2_2,
 
     // mbed original LED naming
-    LED1 = LED_RED,
+    LED1 = P3_14,
     LED2 = P3_3,
-    LED3 = P3_14,
+    LED3 = LED_RED,
     LED4 = LED_RED,
 
     //Push buttons
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.c
new file mode 100644
index 00000000000..cea986a6c04
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.c
@@ -0,0 +1,248 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Setup voltage for the fastest of the clock outputs
+ *
+ * 3. Set up wait states of the flash.
+ *
+ * 4. Set up all dividers.
+ *
+ * 5. Set up all selectors to provide selected clocks.
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!ClocksProfile
+product: Clocks v1.0
+processor: LPC54618J512
+package_id: LPC54618J512ET180
+mcu_data: ksdk2_0
+processor_version: 0.0.0
+board: LPCXpresso54618
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockFRO12M ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: System_clock.outFreq, value: 12 MHz}
+settings:
+- {id: SYSCON.EMCCLKDIV.scale, value: '1', locked: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(
+        kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
+                                   being below the voltage for current speed */
+    CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
+    POWER_SetVoltageForFreq(
+        12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockFROHF48M ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockFROHF48M
+outputs:
+- {id: System_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF48M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(
+        kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
+                                   being below the voltage for current speed */
+    POWER_SetVoltageForFreq(
+        48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(48000000U); /*!< Set FLASH wait states for core */
+
+    CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockFROHF96M **********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
+sources:
+- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF96M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(
+        kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
+                                   being below the voltage for current speed */
+    POWER_SetVoltageForFreq(
+        96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
+
+    CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
+    /*!< Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockPLL180M **********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockPLL180M
+outputs:
+- {id: FRO12M_clock.outFreq, value: 12 MHz}
+- {id: FROHF_clock.outFreq, value: 48 MHz}
+- {id: SYSPLL_clock.outFreq, value: 180 MHz}
+- {id: System_clock.outFreq, value: 180 MHz}
+settings:
+- {id: SYSCON.M_MULT.scale, value: '30', locked: true}
+- {id: SYSCON.N_DIV.scale, value: '1', locked: true}
+- {id: SYSCON.PDEC.scale, value: '2', locked: true}
+- {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up}
+sources:
+- {id: SYSCON._clk_in.outFreq, value: 12 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL180M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(
+        kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
+                                   being below the voltage for current speed */
+    POWER_SetVoltageForFreq(
+        12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
+
+    /*!< Set up SYS PLL */
+    const pll_setup_t pllSetup = {
+        .pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U),
+        .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)),
+        .pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)),
+        .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
+        .pllRate = 180000000U,
+        .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP};
+    CLOCK_AttachClk(kEXT_CLK_to_SYS_PLL); /*!< Set sys pll clock source from external crystal */
+    CLOCK_SetPLLFreq(&pllSetup);          /*!< Configure PLL to the desired value */
+    POWER_SetVoltageForFreq(
+        180000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    CLOCK_SetFLASHAccessCyclesForFreq(180000000U); /*!< Set FLASH wait states for core */
+    CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK);         /*!< Switch System clock to SYS PLL 180MHz */
+
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BootClockPLL180M_CORE_CLOCK;
+}
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.h
new file mode 100644
index 00000000000..f9cdab4d95f
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         12000000U  /*!< Board xtal0 frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+#define BOARD_BootClockRUN BOARD_BootClockFROHF48M
+
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockFRO12M ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK   12000000U    /*!< Core clock frequency:12000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockFROHF48M ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK   48000000U    /*!< Core clock frequency:48000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF48M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockFROHF96M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK   96000000U    /*!< Core clock frequency:96000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockPLL180M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+#define BOARD_BootClockPLL180M_CORE_CLOCK   180000000U    /*!< Core clock frequency:180000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL180M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+#endif /* _CLOCK_CONFIG_H_ */
+
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/device.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/device.h
new file mode 100644
index 00000000000..de347c375d8
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/device.h
@@ -0,0 +1,39 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define NUMBER_OF_GPIO_INTS    8
+
+#define APP_EXCLUDE_FROM_DEEPSLEEP                                                                        \
+    (SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK |  SYSCON_PDRUNCFG_PDEN_SRAMX_MASK |                               \
+     SYSCON_PDRUNCFG_PDEN_SRAM0_MASK | SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK)
+
+/* Defines used by the sleep code */
+#define LPC_CLOCK_INTERNAL_IRC BOARD_BootClockFRO12M
+#define LPC_CLOCK_RUN          BOARD_BootClockFROHF48M
+
+#define DEVICE_ID_LENGTH       24
+
+
+
+
+
+#include "objects.h"
+
+#endif
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c
new file mode 100644
index 00000000000..b727924a6a7
--- /dev/null
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c
@@ -0,0 +1,121 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "clock_config.h"
+#include "fsl_emc.h"
+#include "fsl_power.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* The SDRAM timing. */
+#define SDRAM_REFRESHPERIOD_NS (64 * 1000000 / 4096) /* 4096 rows/ 64ms */
+#define SDRAM_TRP_NS (18u)
+#define SDRAM_TRAS_NS (42u)
+#define SDRAM_TSREX_NS (67u)
+#define SDRAM_TAPR_NS (18u)
+#define SDRAM_TWRDELT_NS (6u)
+#define SDRAM_TRC_NS (60u)
+#define SDRAM_RFC_NS (60u)
+#define SDRAM_XSR_NS (67u)
+#define SDRAM_RRD_NS (12u)
+#define SDRAM_MRD_NCLK (2u)
+#define SDRAM_RAS_NCLK (2u)
+#define SDRAM_MODEREG_VALUE (0x23u)
+#define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/
+
+// called before main
+void mbed_sdk_init()
+{
+    BOARD_BootClockFROHF48M();
+}
+
+// Change the NMI pin to an input. This allows NMI pin to
+//  be used as a low power mode wakeup.  The application will
+//  need to change the pin back to NMI_b or wakeup only occurs once!
+void NMI_Handler(void)
+{
+    //gpio_t gpio;
+    //gpio_init_in(&gpio, PTA4);
+}
+
+// Enable the RTC oscillator if available on the board
+void rtc_setup_oscillator(void)
+{
+    /* Enable the RTC 32K Oscillator */
+    SYSCON->RTCOSCCTRL |= SYSCON_RTCOSCCTRL_EN_MASK;
+}
+
+void ADC_ClockPower_Configuration(void)
+{
+    /* SYSCON power. */
+    POWER_DisablePD(kPDRUNCFG_PD_VDDA);    /* Power on VDDA. */
+    POWER_DisablePD(kPDRUNCFG_PD_ADC0);    /* Power on the ADC converter. */
+    POWER_DisablePD(kPDRUNCFG_PD_VD2_ANA); /* Power on the analog power supply. */
+    POWER_DisablePD(kPDRUNCFG_PD_VREFP);   /* Power on the reference voltage source. */
+    POWER_DisablePD(kPDRUNCFG_PD_TS);      /* Power on the temperature sensor. */
+
+    /* Enable the clock. */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
+
+    /* CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK); */
+    /* Sync clock source is not used. Using sync clock source and would be divided by 2.
+     * The divider would be set when configuring the converter.
+     */
+    CLOCK_EnableClock(kCLOCK_Adc0); /* SYSCON->AHBCLKCTRL[0] |= SYSCON_AHBCLKCTRL_ADC0_MASK; */
+}
+
+/* Initialize the external memory. */
+void BOARD_InitSDRAM(void)
+{
+    emc_basic_config_t basicConfig;
+    emc_dynamic_timing_config_t dynTiming;
+    emc_dynamic_chip_config_t dynChipConfig;
+
+    /* Basic configuration. */
+    basicConfig.endian = kEMC_LittleEndian;
+    basicConfig.fbClkSrc = kEMC_IntloopbackEmcclk;
+    /* EMC Clock = CPU FREQ/2 here can fit CPU freq from 12M ~ 180M.
+     * If you change the divide to 0 and EMC clock is larger than 100M
+     * please take refer to emc.dox to adjust EMC clock delay.
+     */
+    basicConfig.emcClkDiv = 1;
+    /* Dynamic memory timing configuration. */
+    dynTiming.readConfig = kEMC_Cmddelay;
+    dynTiming.refreshPeriod_Nanosec = SDRAM_REFRESHPERIOD_NS;
+    dynTiming.tRp_Ns = SDRAM_TRP_NS;
+    dynTiming.tRas_Ns = SDRAM_TRAS_NS;
+    dynTiming.tSrex_Ns = SDRAM_TSREX_NS;
+    dynTiming.tApr_Ns = SDRAM_TAPR_NS;
+    dynTiming.tWr_Ns = (1000000000 / CLOCK_GetFreq(kCLOCK_EMC) + SDRAM_TWRDELT_NS); /* one clk + 6ns */
+    dynTiming.tDal_Ns = dynTiming.tWr_Ns + dynTiming.tRp_Ns;
+    dynTiming.tRc_Ns = SDRAM_TRC_NS;
+    dynTiming.tRfc_Ns = SDRAM_RFC_NS;
+    dynTiming.tXsr_Ns = SDRAM_XSR_NS;
+    dynTiming.tRrd_Ns = SDRAM_RRD_NS;
+    dynTiming.tMrd_Nclk = SDRAM_MRD_NCLK;
+    /* Dynamic memory chip specific configuration: Chip 0 - MTL48LC8M16A2B4-6A */
+    dynChipConfig.chipIndex = 0;
+    dynChipConfig.dynamicDevice = kEMC_Sdram;
+    dynChipConfig.rAS_Nclk = SDRAM_RAS_NCLK;
+    dynChipConfig.sdramModeReg = SDRAM_MODEREG_VALUE;
+    dynChipConfig.sdramExtModeReg = 0; /* it has no use for normal sdram */
+    dynChipConfig.devAddrMap = SDRAM_DEV_MEMORYMAP;
+    /* EMC Basic configuration. */
+    EMC_Init(EMC, &basicConfig);
+    /* EMC Dynamc memory configuration. */
+    EMC_DynamicMemInit(EMC, &dynTiming, &dynChipConfig, 1);
+}
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/LPC54608.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54618.h
old mode 100644
new mode 100755
similarity index 99%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/LPC54608.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54618.h
index b0d51d03b8b..358d93ddb70
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/LPC54608.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54618.h
@@ -1,7 +1,7 @@
 /*
 ** ###################################################################
-**     Processors:          LPC54608J512BD208
-**                          LPC54608J512ET180
+**     Processors:          LPC54618J512BD208
+**                          LPC54618J512ET180
 **
 **     Compilers:           Keil ARM C/C++ Compiler
 **                          GNU C Compiler
@@ -13,7 +13,7 @@
 **     Build:               b170214
 **
 **     Abstract:
-**         CMSIS Peripheral Access Layer for LPC54608
+**         CMSIS Peripheral Access Layer for LPC54618
 **
 **     Copyright 1997-2016 Freescale Semiconductor, Inc.
 **     Copyright 2016-2017 NXP
@@ -56,16 +56,16 @@
 */
 
 /*!
- * @file LPC54608.h
+ * @file LPC54618.h
  * @version 1.1
  * @date 2016-11-25
- * @brief CMSIS Peripheral Access Layer for LPC54608
+ * @brief CMSIS Peripheral Access Layer for LPC54618
  *
- * CMSIS Peripheral Access Layer for LPC54608
+ * CMSIS Peripheral Access Layer for LPC54618
  */
 
-#ifndef _LPC54608_H_
-#define _LPC54608_H_                             /**< Symbol preventing repeated inclusion */
+#ifndef _LPC54618_H_
+#define _LPC54618_H_                             /**< Symbol preventing repeated inclusion */
 
 /** Memory map major version (memory maps with equal major version number are
  * compatible) */
@@ -181,7 +181,7 @@ typedef enum IRQn {
 #define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
 
 #include "core_cm4.h"                  /* Core Peripheral Access Layer */
-#include "system_LPC54608.h"           /* Device specific configuration file */
+#include "system_LPC54618.h"           /* Device specific configuration file */
 
 /*!
  * @}
@@ -713,7 +713,8 @@ typedef struct {
 
 /** CAN - Register Layout Typedef */
 typedef struct {
-       uint8_t RESERVED_0[16];
+       uint8_t RESERVED_0[12];
+  __IO uint32_t DBTP;                              /**< Data Bit Timing Prescaler Register, offset: 0xC */
   __IO uint32_t TEST;                              /**< Test Register, offset: 0x10 */
        uint8_t RESERVED_1[4];
   __IO uint32_t CCCR;                              /**< CC Control Register, offset: 0x18 */
@@ -779,6 +780,23 @@ typedef struct {
  * @{
  */
 
+/*! @name DBTP - Data Bit Timing Prescaler Register */
+#define CAN_DBTP_DSJW_MASK                       (0xFU)
+#define CAN_DBTP_DSJW_SHIFT                      (0U)
+#define CAN_DBTP_DSJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK)
+#define CAN_DBTP_DTSEG2_MASK                     (0xF0U)
+#define CAN_DBTP_DTSEG2_SHIFT                    (4U)
+#define CAN_DBTP_DTSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK)
+#define CAN_DBTP_DTSEG1_MASK                     (0x1F00U)
+#define CAN_DBTP_DTSEG1_SHIFT                    (8U)
+#define CAN_DBTP_DTSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK)
+#define CAN_DBTP_DBRP_MASK                       (0x1F0000U)
+#define CAN_DBTP_DBRP_SHIFT                      (16U)
+#define CAN_DBTP_DBRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK)
+#define CAN_DBTP_TDC_MASK                        (0x800000U)
+#define CAN_DBTP_TDC_SHIFT                       (23U)
+#define CAN_DBTP_TDC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK)
+
 /*! @name TEST - Test Register */
 #define CAN_TEST_LBCK_MASK                       (0x10U)
 #define CAN_TEST_LBCK_SHIFT                      (4U)
@@ -815,6 +833,12 @@ typedef struct {
 #define CAN_CCCR_TEST_MASK                       (0x80U)
 #define CAN_CCCR_TEST_SHIFT                      (7U)
 #define CAN_CCCR_TEST(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)
+#define CAN_CCCR_FDOE_MASK                       (0x100U)
+#define CAN_CCCR_FDOE_SHIFT                      (8U)
+#define CAN_CCCR_FDOE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK)
+#define CAN_CCCR_BRSE_MASK                       (0x200U)
+#define CAN_CCCR_BRSE_SHIFT                      (9U)
+#define CAN_CCCR_BRSE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK)
 #define CAN_CCCR_PXHD_MASK                       (0x1000U)
 #define CAN_CCCR_PXHD_SHIFT                      (12U)
 #define CAN_CCCR_PXHD(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)
@@ -824,6 +848,9 @@ typedef struct {
 #define CAN_CCCR_TXP_MASK                        (0x4000U)
 #define CAN_CCCR_TXP_SHIFT                       (14U)
 #define CAN_CCCR_TXP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)
+#define CAN_CCCR_NISO_MASK                       (0x8000U)
+#define CAN_CCCR_NISO_SHIFT                      (15U)
+#define CAN_CCCR_NISO(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK)
 
 /*! @name NBTP - Nominal Bit Timing and Prescaler Register */
 #define CAN_NBTP_NTSEG2_MASK                     (0x7FU)
@@ -898,6 +925,18 @@ typedef struct {
 #define CAN_PSR_BO_MASK                          (0x80U)
 #define CAN_PSR_BO_SHIFT                         (7U)
 #define CAN_PSR_BO(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)
+#define CAN_PSR_DLEC_MASK                        (0x700U)
+#define CAN_PSR_DLEC_SHIFT                       (8U)
+#define CAN_PSR_DLEC(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK)
+#define CAN_PSR_RESI_MASK                        (0x800U)
+#define CAN_PSR_RESI_SHIFT                       (11U)
+#define CAN_PSR_RESI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK)
+#define CAN_PSR_RBRS_MASK                        (0x1000U)
+#define CAN_PSR_RBRS_SHIFT                       (12U)
+#define CAN_PSR_RBRS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK)
+#define CAN_PSR_RFDF_MASK                        (0x2000U)
+#define CAN_PSR_RFDF_SHIFT                       (13U)
+#define CAN_PSR_RFDF(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK)
 #define CAN_PSR_PXE_MASK                         (0x4000U)
 #define CAN_PSR_PXE_SHIFT                        (14U)
 #define CAN_PSR_PXE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)
@@ -12367,5 +12406,5 @@ typedef struct {
  */ /* end of group SDK_Compatibility_Symbols */
 
 
-#endif  /* _LPC54608_H_ */
+#endif  /* _LPC54618_H_ */
 
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/LPC54608_features.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54618_features.h
old mode 100644
new mode 100755
similarity index 98%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/LPC54608_features.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54618_features.h
index 1bdb5d04e33..02e279d0787
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/LPC54608_features.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54618_features.h
@@ -46,8 +46,8 @@
 ** ###################################################################
 */
 
-#ifndef _LPC54608_FEATURES_H_
-#define _LPC54608_FEATURES_H_
+#ifndef _LPC54618_FEATURES_H_
+#define _LPC54618_FEATURES_H_
 
 /* SOC module features */
 
@@ -133,7 +133,7 @@
 /* CAN module features */
 
 /* @brief Support CANFD or not */
-#define FSL_FEATURE_CAN_SUPPORT_CANFD (0)
+#define FSL_FEATURE_CAN_SUPPORT_CANFD (1)
 
 /* DMA module features */
 
@@ -227,5 +227,5 @@
 /* @brief Base address of the USB dedicated RAM */
 #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
 
-#endif /* _LPC54608_FEATURES_H_ */
+#endif /* _LPC54618_FEATURES_H_ */
 
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/LPC54608J512.sct b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/LPC54618J512.sct
similarity index 97%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/LPC54608J512.sct
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/LPC54618J512.sct
index 348ada9c3cc..f6a981b2c3e 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/LPC54608J512.sct
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/LPC54618J512.sct
@@ -1,8 +1,8 @@
 #! armcc -E
 /*
 ** ###################################################################
-**     Processors:          LPC54608J512BD208
-**                          LPC54608J512ET180
+**     Processors:          LPC54618J512BD208
+**                          LPC54618J512ET180
 **
 **     Compiler:            Keil ARM C/C++ Compiler
 **     Reference manual:    LPC54S60x/LPC5460x User manual Rev.0.9  7 Nov 2016
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/libpower.ar b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/lib_power.ar
old mode 100644
new mode 100755
similarity index 86%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/libpower.ar
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/lib_power.ar
index 9e4944c5a4d..2cab4e5e686
Binary files a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/libpower.ar and b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/lib_power.ar differ
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/startup_LPC54608.S b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/startup_LPC54618.S
similarity index 99%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/startup_LPC54608.S
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/startup_LPC54618.S
index 7416e0e5449..6ebe3baf63a 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/startup_LPC54608.S
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/startup_LPC54618.S
@@ -1,7 +1,7 @@
 ;/*****************************************************************************
-; * @file:    startup_LPC54608.s
+; * @file:    startup_LPC54618.s
 ; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
-; *           LPC54608
+; *           LPC54618
 ; * @version: 1.1
 ; * @date:    2016-11-25
 ; *
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/LPC54608J512_flash.ld b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/LPC54618J512.ld
similarity index 76%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/LPC54608J512_flash.ld
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/LPC54618J512.ld
index 0391dfbd37d..47aaf977952 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/LPC54608J512_flash.ld
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/LPC54618J512.ld
@@ -1,61 +1,28 @@
 /*
 ** ###################################################################
-**     Processors:          LPC54608J512
+**     Processors:          LPC54618J512
 **
 **     Compiler:            GNU C Compiler
-**     Reference manual:    LPC54608 Series Reference Manual, Rev. 0 , 06/2017
+**     Reference manual:    LPC54618 Series Reference Manual, Rev. 0 , 06/2017
 **     Version:             rev. 1.0, 2017-6-06
 **     Build:               b161214
 **
 **     Abstract:
 **         Linker file for the GNU C Compiler
 **
-**     Copyright (c) 2016 Freescale Semiconductor, Inc.
-**     Copyright (c) 2016 - 2017 , NXP
-**     All rights reserved.
-**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
 **     Redistribution and use in source and binary forms, with or without modification,
 **     are permitted provided that the following conditions are met:
 **
-**     o Redistributions of source code must retain the above copyright notice, this list
+**     1. Redistributions of source code must retain the above copyright notice, this list
 **       of conditions and the following disclaimer.
 **
-**     o Redistributions in binary form must reproduce the above copyright notice, this
+**     2. Redistributions in binary form must reproduce the above copyright notice, this
 **       list of conditions and the following disclaimer in the documentation and/or
 **       other materials provided with the distribution.
 **
-**     o Neither the name of copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from this
-**       software without specific prior written permission.
-**
-**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-**     http:                 www.freescale.com
-**     mail:                 support@freescale.com
-**
-**     Copyright (c) 2016 NXP Semiconductors, Inc.
-**     All rights reserved.
-**
-**     Redistribution and use in source and binary forms, with or without modification,
-**     are permitted provided that the following conditions are met:
-**
-**     o Redistributions of source code must retain the above copyright notice, this list
-**       of conditions and the following disclaimer.
-**
-**     o Redistributions in binary form must reproduce the above copyright notice, this
-**       list of conditions and the following disclaimer in the documentation and/or
-**       other materials provided with the distribution.
-**
-**     o Neither the name of NXP Semiconductors, Inc. nor the names of its
+**     3. Neither the name of the copyright holder nor the names of its
 **       contributors may be used to endorse or promote products derived from this
 **       software without specific prior written permission.
 **
@@ -97,8 +64,6 @@ MEMORY
   m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00028000
   m_sramx               (RW)  : ORIGIN = 0x04000000, LENGTH = 0x00008000
   m_usb_sram            (RW)  : ORIGIN = 0x40100000, LENGTH = 0x00002000
-
-
 }
 
 /* Define output sections */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/libpower.a b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/libpower.a
new file mode 100755
index 00000000000..4503c056334
Binary files /dev/null and b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/libpower.a differ
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/startup_LPC54608.S b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/startup_LPC54618.S
similarity index 91%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/startup_LPC54608.S
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/startup_LPC54618.S
index 22667a8de17..b801b029220 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/startup_LPC54608.S
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/startup_LPC54618.S
@@ -1,54 +1,25 @@
 /* ---------------------------------------------------------------------------------------*/
-/*  @file:    startup_LPC54608.S                                                          */
+/*  @file:    startup_LPC54618.S                                                          */
 /*  @purpose: CMSIS Cortex-M4 Core Device Startup File                                    */
-/*            LPC54608                                                                    */
+/*            LPC54618                                                                    */
 /*  @version: 1.0                                                                         */
 /*  @date:    2017-6-6                                                                    */
 /*  @build:   b161214                                                                     */
 /* ---------------------------------------------------------------------------------------*/
 /*                                                                                        */
-/* Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc.                              */
-/* Copyright (c) 2016 - 2017 , NXP                                                        */
-/*                                                                                        */
-/* Redistribution and use in source and binary forms, with or without modification,       */
-/* are permitted provided that the following conditions are met:                          */
-/*                                                                                        */
-/* o Redistributions of source code must retain the above copyright notice, this list     */
-/*   of conditions and the following disclaimer.                                          */
-/*                                                                                        */
-/* o Redistributions in binary form must reproduce the above copyright notice, this       */
-/*   list of conditions and the following disclaimer in the documentation and/or          */
-/*   other materials provided with the distribution.                                      */
-/*                                                                                        */
-/* o Neither the name of copyright holder nor the names of its                            */
-/*   contributors may be used to endorse or promote products derived from this            */
-/*   software without specific prior written permission.                                  */
-/*                                                                                        */
-/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
-/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
-/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
-/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
-/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
-/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
-/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
-/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
-/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
-/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
-/*                                                                                        */
-/* Copyright (c) 2016 , NXP Semiconductors, Inc.                                          */
-/* All rights reserved.                                                                   */
-/*                                                                                        */
+/* Copyright 1997-2016 Freescale Semiconductor, Inc.                                      */
+/* Copyright 2016-2017 NXP                                                                */
 /* Redistribution and use in source and binary forms, with or without modification,       */
 /* are permitted provided that the following conditions are met:                          */
 /*                                                                                        */
-/* o Redistributions of source code must retain the above copyright notice, this list     */
+/* 1. Redistributions of source code must retain the above copyright notice, this list    */
 /*   of conditions and the following disclaimer.                                          */
 /*                                                                                        */
-/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/* 2. Redistributions in binary form must reproduce the above copyright notice, this      */
 /*   list of conditions and the following disclaimer in the documentation and/or          */
 /*   other materials provided with the distribution.                                      */
 /*                                                                                        */
-/* o Neither the name of NXP Semiconductors, Inc. nor the names of its                    */
+/* 3. Neither the name of the copyright holder nor the names of its                       */
 /*   contributors may be used to endorse or promote products derived from this            */
 /*   software without specific prior written permission.                                  */
 /*                                                                                        */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/LPC54608J512.icf b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/LPC54618J512.icf
similarity index 98%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/LPC54608J512.icf
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/LPC54618J512.icf
index 3e46c7e9baa..eb219474d99 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/LPC54608J512.icf
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/LPC54618J512.icf
@@ -1,7 +1,7 @@
 /*
 ** ###################################################################
-**     Processors:          LPC54608J512BD208
-**                          LPC54608J512ET180
+**     Processors:          LPC54618J512BD208
+**                          LPC54618J512ET180
 **
 **     Compiler:            IAR ANSI C/C++ Compiler for ARM
 **     Reference manual:    LPC54S60x/LPC5460x User manual Rev.0.9  7 Nov 2016
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/lib_power.a b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/lib_power.a
new file mode 100755
index 00000000000..755b29878d6
Binary files /dev/null and b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/lib_power.a differ
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/startup_LPC54608.S b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/startup_LPC54618.S
similarity index 99%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/startup_LPC54608.S
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/startup_LPC54618.S
index bc7e9e45502..442949881ae 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/startup_LPC54608.S
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/startup_LPC54618.S
@@ -1,7 +1,7 @@
 ;/*****************************************************************************
-; * @file:    startup_LPC54608.s
+; * @file:    startup_LPC54618.s
 ; * @purpose: CMSIS Cortex-M4 Core Device Startup File
-; *           LPC54608
+; *           LPC54618
 ; * @version: 1.1
 ; * @date:    2016-11-25
 ; *----------------------------------------------------------------------------
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/cmsis.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/cmsis.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/cmsis.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/cmsis.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/cmsis_nvic.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/cmsis_nvic.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/cmsis_nvic.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/cmsis_nvic.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/fsl_device_registers.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/fsl_device_registers.h
similarity index 93%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/fsl_device_registers.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/fsl_device_registers.h
index ac8dd79f0e3..aff433895d8 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/fsl_device_registers.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/fsl_device_registers.h
@@ -36,14 +36,14 @@
  *
  * The CPU macro should be declared in the project or makefile.
  */
-#if (defined(CPU_LPC54608J512BD208) || defined(CPU_LPC54608J512ET180))
+#if (defined(CPU_LPC54618J512BD208) || defined(CPU_LPC54618J512ET180))
 
-#define LPC54608_SERIES
+#define LPC54618_SERIES
 
 /* CMSIS-style register definitions */
-#include "LPC54608.h"
+#include "LPC54618.h"
 /* CPU specific feature definitions */
-#include "LPC54608_features.h"
+#include "LPC54618_features.h"
 
 #else
     #error "No valid CPU defined!"
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/system_LPC54608.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/system_LPC54618.c
old mode 100644
new mode 100755
similarity index 98%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/system_LPC54608.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/system_LPC54618.c
index b16179714ae..51e13ce43b1
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/system_LPC54608.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/system_LPC54618.c
@@ -1,7 +1,7 @@
 /*
 ** ###################################################################
-**     Processors:          LPC54608J512BD208
-**                          LPC54608J512ET180
+**     Processors:          LPC54618J512BD208
+**                          LPC54618J512ET180
 **
 **     Compilers:           Keil ARM C/C++ Compiler
 **                          GNU C Compiler
@@ -58,10 +58,10 @@
 */
 
 /*!
- * @file LPC54608
+ * @file LPC54618
  * @version 1.1
  * @date 2016-11-25
- * @brief Device specific configuration file for LPC54608 (implementation file)
+ * @brief Device specific configuration file for LPC54618 (implementation file)
  *
  * Provides a system configuration function and a global variable that contains
  * the system frequency. It configures the device and initializes the oscillator
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/system_LPC54608.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/system_LPC54618.h
old mode 100644
new mode 100755
similarity index 94%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/system_LPC54608.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/system_LPC54618.h
index 79194524e49..edcefbd0ed4
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/system_LPC54608.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/system_LPC54618.h
@@ -1,7 +1,7 @@
 /*
 ** ###################################################################
-**     Processors:          LPC54608J512BD208
-**                          LPC54608J512ET180
+**     Processors:          LPC54618J512BD208
+**                          LPC54618J512ET180
 **
 **     Compilers:           Keil ARM C/C++ Compiler
 **                          GNU C Compiler
@@ -58,18 +58,18 @@
 */
 
 /*!
- * @file LPC54608
+ * @file LPC54618
  * @version 1.1
  * @date 2016-11-25
- * @brief Device specific configuration file for LPC54608 (header file)
+ * @brief Device specific configuration file for LPC54618 (header file)
  *
  * Provides a system configuration function and a global variable that contains
  * the system frequency. It configures the device and initializes the oscillator
  * (PLL) that is part of the microcontroller device.
  */
 
-#ifndef _SYSTEM_LPC54608_H_
-#define _SYSTEM_LPC54608_H_                      /**< Symbol preventing repeated inclusion */
+#ifndef _SYSTEM_LPC54618_H_
+#define _SYSTEM_LPC54618_H_                      /**< Symbol preventing repeated inclusion */
 
 #ifdef __cplusplus
 extern "C" {
@@ -118,4 +118,4 @@ void SystemCoreClockUpdate (void);
 }
 #endif
 
-#endif  /* _SYSTEM_LPC54608_H_ */
+#endif  /* _SYSTEM_LPC54618_H_ */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_adc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_adc.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_adc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_adc.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_clock.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.c
similarity index 96%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_clock.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.c
index f239799c0da..90a32de9d36 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_clock.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.c
@@ -984,8 +984,13 @@ static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n)
     return m;
 }
 
-/* Set PLL output based on desired output rate */
-static pll_error_t CLOCK_GetPllConfig(
+/*
+ * Set PLL output based on desired output rate.
+ * In this function, the it calculates the PLL setting for output frequency from input clock
+ * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently.
+ * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function.
+ */
+static pll_error_t CLOCK_GetPllConfigInternal(
     uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup)
 {
     uint32_t nDivOutHz, fccoHz, multFccoDiv;
@@ -1098,6 +1103,64 @@ static pll_error_t CLOCK_GetPllConfig(
     return kStatus_PLL_Success;
 }
 
+#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
+/* Alloct the static buffer for cache. */
+pll_setup_t gPllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT];
+uint32_t gFinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};
+uint32_t gFoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};
+uint32_t gPllSetupCacheIdx = 0U;
+#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
+
+/*
+ * Calculate the PLL setting values from input clock freq to output freq.
+ */
+static pll_error_t CLOCK_GetPllConfig(
+    uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup)
+{
+    pll_error_t retErr;
+#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
+    uint32_t i;
+
+    for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++)
+    {
+        if ( (finHz == gFinHzCache[i]) && (foutHz == gFoutHzCache[i]) )
+        {
+            /* Hit the target in cache buffer. */
+            pSetup->pllctrl = gPllSetupCacheStruct[i].pllctrl;
+            pSetup->pllndec = gPllSetupCacheStruct[i].pllndec;
+            pSetup->pllpdec = gPllSetupCacheStruct[i].pllpdec;
+            pSetup->pllmdec = gPllSetupCacheStruct[i].pllmdec;
+            retErr = kStatus_PLL_Success;
+        }
+    }
+
+    if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
+    {
+        return retErr;
+    }
+#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
+
+    /* No cache or did not hit the cache. */
+    retErr = CLOCK_GetPllConfigInternal(finHz, foutHz, pSetup);
+
+#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)
+    if (kStatus_PLL_Success == retErr)
+    {
+        /* Cache the most recent calulation result into buffer. */
+        gFinHzCache[gPllSetupCacheIdx] = finHz;
+        gFoutHzCache[gPllSetupCacheIdx] = foutHz;
+    
+        gPllSetupCacheStruct[gPllSetupCacheIdx].pllctrl = pSetup->pllctrl;
+        gPllSetupCacheStruct[gPllSetupCacheIdx].pllndec = pSetup->pllndec;
+        gPllSetupCacheStruct[gPllSetupCacheIdx].pllpdec = pSetup->pllpdec;
+        gPllSetupCacheStruct[gPllSetupCacheIdx].pllmdec = pSetup->pllmdec;
+        /* Update the index for next available buffer. */
+        gPllSetupCacheIdx = (gPllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT;
+    }
+#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */
+
+    return retErr;
+}
 
 /* Update SYSTEM PLL rate variable */
 static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup)
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_clock.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.h
similarity index 99%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_clock.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.h
index 5093b03232d..a602dc9fba7 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_clock.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.h
@@ -59,6 +59,18 @@
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
 #endif
+
+/*!
+ * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
+ *
+ * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
+ * would cache the recent calulation and accelerate the execution to get the
+ * right settings.
+ */
+#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
+#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT  2U
+#endif
+
 /*! @brief Clock ip name array for ROM. */
 #define ADC_CLOCKS \
     {              \
@@ -656,7 +668,7 @@ typedef enum _clock_attach_id
     kSYS_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1),
     kUSB_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 2),
     kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),
-    kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),
+    kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 4),
     kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7),
 
     kMCLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0),
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_common.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_common.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_common.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_common.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_crc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_crc.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_crc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_crc.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_ctimer.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_ctimer.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_ctimer.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_ctimer.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dma.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dma.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic_dma.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic_dma.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_eeprom.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_eeprom.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_eeprom.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_eeprom.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_emc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_emc.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_emc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_emc.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_enet.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_enet.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_enet.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_enet.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flashiap.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flashiap.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flashiap.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flashiap.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flexcomm.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flexcomm.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flexcomm.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flexcomm.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmc.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmc.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmeas.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmeas.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmeas.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmeas.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gint.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gint.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gint.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gint.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gpio.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gpio.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gpio.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gpio.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c_dma.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c_dma.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.c
similarity index 99%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s_dma.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.c
index 3b69be4772e..6501b169611 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s_dma.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.c
@@ -575,7 +575,7 @@ void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, ui
     i2s_dma_handle_t *i2sHandle = privateHandle->handle;
     I2S_Type *base = privateHandle->base;
 
-    if (!transferDone || (i2sHandle->state == kI2S_DmaStateIdle))
+    if ((!transferDone) || (i2sHandle->state == kI2S_DmaStateIdle))
     {
         return;
     }
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s_dma.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_inputmux.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_inputmux.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_inputmux.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_inputmux.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_inputmux_connections.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux_connections.h
similarity index 99%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_inputmux_connections.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux_connections.h
index 20c210d41ca..1c8cf763439 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_inputmux_connections.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux_connections.h
@@ -1,6 +1,5 @@
 /*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright (c) 2016, NXP
+ * Copyright (c) 2013-2016, NXP Semiconductors.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_iocon.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_iocon.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_iocon.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_iocon.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_lcdc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_lcdc.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_lcdc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_lcdc.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mcan.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mcan.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mcan.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mcan.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mrt.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mrt.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mrt.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mrt.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_otp.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_otp.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_otp.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_otp.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_pint.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_pint.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_pint.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_pint.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_power.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_power.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_power.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.h
similarity index 95%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_power.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.h
index e36168283fe..ef1a5434bd2 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_power.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.h
@@ -230,15 +230,6 @@ void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd);
  */
 void POWER_SetVoltageForFreq(uint32_t freq);
 
-/*!
- * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
- *
- * @param freq  - The desired frequency at which the part would like to operate, 
- *                note that the voltage and flash wait states should be set before changing frequency
- * @return none
- */
-void POWER_SetVoltageForFreq(uint32_t freq);
-
 /*!
  * @brief Power Library API to return the library version.
  *
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_reset.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_reset.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_reset.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_reset.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rit.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rit.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rit.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rit.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rng.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rng.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rng.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rng.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rtc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rtc.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rtc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rtc.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sctimer.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sctimer.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sctimer.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sctimer.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sdif.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sdif.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sdif.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sdif.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi_dma.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi_dma.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi_dma.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi_dma.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart_dma.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart_dma.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_utick.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_utick.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_utick.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_utick.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_wwdt.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.c
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_wwdt.c
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.c
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_wwdt.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.h
similarity index 100%
rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_wwdt.h
rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.h
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/rtc_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/rtc_api.c
index f152a13f1a3..0fa0f3d0809 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/rtc_api.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/rtc_api.c
@@ -54,9 +54,6 @@ time_t rtc_read(void)
 
 void rtc_write(time_t t)
 {
-    if (t == 0) {
-        t = 1;
-    }
     RTC_StopTimer(RTC);
     RTC->COUNT = t;
     RTC_StartTimer(RTC);
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/spi_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/spi_api.c
index 75d906156ca..bdacb00b6df 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/spi_api.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/spi_api.c
@@ -68,7 +68,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
     if (slave) {
         /* Slave config */
         SPI_SlaveGetDefaultConfig(&slave_config);
-        slave_config.dataWidth = (uint32_t)bits - 1;
+        slave_config.dataWidth = (spi_data_width_t)(bits - 1);
         slave_config.polarity = (mode & 0x2) ? kSPI_ClockPolarityActiveLow : kSPI_ClockPolarityActiveHigh;
         slave_config.phase = (mode & 0x1) ? kSPI_ClockPhaseSecondEdge : kSPI_ClockPhaseFirstEdge;
 
@@ -76,7 +76,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
     } else {
         /* Master config */
         SPI_MasterGetDefaultConfig(&master_config);
-        master_config.dataWidth = (uint32_t)bits - 1;
+        master_config.dataWidth = (spi_data_width_t)(bits - 1);
         master_config.polarity = (mode & 0x2) ? kSPI_ClockPolarityActiveLow : kSPI_ClockPolarityActiveHigh;
         master_config.phase = (mode & 0x1) ? kSPI_ClockPhaseSecondEdge : kSPI_ClockPhaseFirstEdge;
         master_config.direction = kSPI_MsbFirst;
@@ -154,7 +154,7 @@ int spi_master_write(spi_t *obj, int value)
     return rx_data & 0xffff;
 }
 
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, 
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
                            char *rx_buffer, int rx_length, char write_fill) {
     int total = (tx_length > rx_length) ? tx_length : rx_length;
 
diff --git a/targets/TARGET_NXP/mbed_rtx.h b/targets/TARGET_NXP/mbed_rtx.h
index d2c4256b942..26e8c630a72 100644
--- a/targets/TARGET_NXP/mbed_rtx.h
+++ b/targets/TARGET_NXP/mbed_rtx.h
@@ -50,7 +50,7 @@
 #define INITIAL_SP              (0x02009000UL)
 #endif
 
-#elif defined(TARGET_LPC1768)
+#elif defined(TARGET_LPC1768) || defined(TARGET_LPC1769)
 
 #ifndef INITIAL_SP
 #define INITIAL_SP              (0x10008000UL)
@@ -86,7 +86,7 @@
 #define INITIAL_SP              (0x20010000UL)
 #endif
 
-#elif defined(TARGET_LPC54608)
+#elif defined(TARGET_LPC546XX)
 
 #ifndef INITIAL_SP
 #define INITIAL_SP              (0x20028000UL)
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h
index bcbafbe0002..2b5f3233438 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h
@@ -48,7 +48,6 @@
 #define I2C_SPEED_400K_AT_8MHZ     (uint8_t)0x03
 #define I2C_SPEED_400K_AT_16MHZ    (uint8_t)0x08
 
-
 /* I2C commands */
 #define I2C_CMD_NULL          0x00
 #define I2C_CMD_WDAT0         0x10
@@ -93,7 +92,10 @@
 #define I2C_API_STATUS_SUCCESS    0
 #define PAD_REG_ADRS_BYTE_SIZE    4
 
-#define SEND_COMMAND(cmd)  while(!I2C_FIFO_EMPTY); wait_us(1); obj->membase->CMD_REG = cmd;
+// The wait_us(0) command is needed so the I2C state machines have enough
+// time for data to settle across all clock domain crossings in their
+// synchronizers, both directions.
+#define SEND_COMMAND(cmd) wait_us(0); obj->membase->CMD_REG = cmd; wait_us(0);
 
 /** Init I2C device.
  * @details
@@ -158,4 +160,4 @@ extern int32_t fI2cReadB(i2c_t *d, char *buf, int len);
  */
 extern int32_t fI2cWriteB(i2c_t *d, const char *buf, int len);
 
-#endif /* I2C_H_ */
\ No newline at end of file
+#endif /* I2C_H_ */
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c
index cc57ed834d6..12845ed0695 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c
@@ -169,9 +169,7 @@ int i2c_byte_write(i2c_t *obj, int data)
         return Count;
     }
 
-    while(obj->membase->STATUS.WORD & I2C_STATUS_CMD_FIFO_OFL_BIT); /* Wait till command overflow ends */
-
-    if(obj->membase->STATUS.WORD & I2C_STATUS_BUS_ERR_BIT) {
+    if(I2C_BUS_ERR_CHECK) {
         /* Bus error means NAK received */
         return 0;
     } else {
@@ -180,4 +178,4 @@ int i2c_byte_write(i2c_t *obj, int data)
     }
 }
 
-#endif /* DEVICE_I2C */
\ No newline at end of file
+#endif /* DEVICE_I2C */
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c
index 1b3e5daf202..8ae4a9b9356 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c
@@ -65,7 +65,6 @@
 /* See i2c.h for details */
 void fI2cInit(i2c_t *obj,PinName sda,PinName scl)
 {
-    uint32_t clockDivisor;
     /* determine the I2C to use */
     I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
     I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
@@ -93,9 +92,7 @@ void fI2cInit(i2c_t *obj,PinName sda,PinName scl)
     obj->membase->CR.BITS.I2C_APB_CD_EN = True;
 
     /* set default baud rate at 100k */
-    clockDivisor = ((fClockGetPeriphClockfrequency() / 100000) >> 2) - 2;
-    obj->membase->CR.BITS.CD_VAL = (clockDivisor & I2C_CLOCKDIVEDER_VAL_MASK);
-    obj->membase->PRE_SCALE_REG = (clockDivisor & I2C_APB_CLK_DIVIDER_VAL_MASK) >> 5; /**< Zero pre-scale value not allowed */
+    fI2cFrequency(obj, 100000);
 
     /* Cross bar setting */
     pinmap_pinout(sda, PinMap_I2C_SDA);
@@ -110,8 +107,8 @@ void fI2cInit(i2c_t *obj,PinName sda,PinName scl)
     PadReg_t *padRegScl = (PadReg_t*)(PADREG_BASE + (scl * PAD_REG_ADRS_BYTE_SIZE));
 
     CLOCK_ENABLE(CLOCK_PAD);
-    padRegSda->PADIO0.BITS.POWER = 1; /* sda: Drive strength */
-    padRegScl->PADIO0.BITS.POWER = 1; /* scl: Drive strength */
+    padRegSda->PADIO0.BITS.POWER = 3; /* sda: Drive strength */
+    padRegScl->PADIO0.BITS.POWER = 3; /* scl: Drive strength */
     CLOCK_DISABLE(CLOCK_PAD);
 
     CLOCK_ENABLE(CLOCK_GPIO);
@@ -160,7 +157,10 @@ int32_t fI2cReadB(i2c_t *obj, char *buf, int len)
     int32_t read = 0;
 
     while (read < len) {
-        /* Send read command */
+
+        while(FIFO_OFL_CHECK); /* Wait till command overflow ends */
+
+    	/* Send read command */
         SEND_COMMAND(I2C_CMD_RDAT8);
         while(!RD_DATA_READY) {
             if (I2C_BUS_ERR_CHECK) {
@@ -170,8 +170,8 @@ int32_t fI2cReadB(i2c_t *obj, char *buf, int len)
         }
         buf[read++] = obj->membase->RD_FIFO_REG; /**< Reading 'read FIFO register' will clear status register */
 
-        if(!(read>=len)) {  /* No ACK will be generated for the last read, upper level I2C protocol should generate */
-            SEND_COMMAND(I2C_CMD_WDAT0); /* TODO based on requirement generate ACK or NACK Based on the requirement. */
+        if(!(read>=len)) {
+            SEND_COMMAND(I2C_CMD_WDAT0);
         } else {
             /* No ack */
             SEND_COMMAND(I2C_CMD_WDAT1);
@@ -179,7 +179,7 @@ int32_t fI2cReadB(i2c_t *obj, char *buf, int len)
 
         /* check for FIFO underflow */
         if(I2C_UFL_CHECK) {
-            return I2C_ERROR_NO_SLAVE; /* TODO No error available for this in i2c_api.h */
+            return I2C_EVENT_ERROR;
         }
         if(I2C_BUS_ERR_CHECK) {
             /* Bus error */
@@ -196,8 +196,8 @@ int32_t fI2cWriteB(i2c_t *obj, const char *buf, int len)
     int32_t write = 0;
 
     while (write < len) {
-        /* Send write command */
-        SEND_COMMAND(I2C_CMD_WDAT8);
+
+        while(FIFO_OFL_CHECK); /* Wait till command overflow ends */
 
         if(buf[write] == I2C_CMD_RDAT8) {
             /* SW work around to counter FSM issue. If the only command in the CMD FIFO is the WDAT8 command (data of 0x13)
@@ -205,35 +205,27 @@ int32_t fI2cWriteB(i2c_t *obj, const char *buf, int len)
             RDAT8 command by the data FSM; resulting in an I2C bus error (NACK instead of an ACK). */
             /* Send 0x13 bit wise */
             SEND_COMMAND(I2C_CMD_WDAT0);
-
             SEND_COMMAND(I2C_CMD_WDAT0);
-
             SEND_COMMAND(I2C_CMD_WDAT0);
-
             SEND_COMMAND(I2C_CMD_WDAT1);
-
             SEND_COMMAND(I2C_CMD_WDAT0);
-
             SEND_COMMAND(I2C_CMD_WDAT0);
-
             SEND_COMMAND(I2C_CMD_WDAT1);
-
             SEND_COMMAND(I2C_CMD_WDAT1);
+            write++;
         } else {
             /* Send data */
+            SEND_COMMAND(I2C_CMD_WDAT8);
             SEND_COMMAND(buf[write++]);
         }
-        SEND_COMMAND(I2C_CMD_VRFY_ACK); /* TODO Verify ACK based on requirement, Do we need? */
+        SEND_COMMAND(I2C_CMD_VRFY_ACK);
 
         if (I2C_BUS_ERR_CHECK) {
             /* Bus error */
             return I2C_ERROR_BUS_BUSY;
         }
-
-        while(FIFO_OFL_CHECK); /* Wait till command overflow ends */
     }
-
     return write;
 }
 
-#endif /* DEVICE_I2C */
\ No newline at end of file
+#endif /* DEVICE_I2C */
diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c
index 75fa1b398bf..e0b07b9cbce 100644
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c
@@ -130,7 +130,8 @@ uint32_t us_ticker_read()
 
 void us_ticker_fire_interrupt(void)
 {
-    NVIC_SetPendingIRQ(Tim0_IRQn);
+    us_ticker_target = 0;
+    NVIC_SetPendingIRQ(Tim1_IRQn);
 }
 
 /*******************************************************************************
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/can_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1H/can_api.c
index 6a727b84979..2b813fcf6ab 100644
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/can_api.c
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/can_api.c
@@ -637,17 +637,17 @@ int can_write(can_t *obj, CAN_Message msg, int cc) {
         __NOP();
     }
     
-    if (((msg.format == CANStandard) && (msg.id <= 0x07FF)) || ((msg.format == CANExtended) && (msg.id <= 0x03FFFF))) {
+    if (((msg.format == CANStandard) && (msg.id <= 0x07FF)) || ((msg.format == CANExtended) && (msg.id <= 0x1FFFFFFF))) {
         /* send/receive FIFO buffer isn't full */
         dmy_cfsts = CFSTS_TBL[obj->ch][CAN_SEND];
         if ((*dmy_cfsts & 0x02) != 0x02) {
-            /* set format, frame type and send/receive FIFO buffer ID(b10-0 or b28-11) */
+            /* set format, frame type and send/receive FIFO buffer ID(b10-0 or b28-0) */
             dmy_cfid = CFID_TBL[obj->ch][CAN_SEND];
             *dmy_cfid = ((msg.format << 31) | (msg.type << 30));
             if (msg.format == CANStandard) {
                 *dmy_cfid |= (msg.id & 0x07FF);
             } else {
-                *dmy_cfid |= ((msg.id & 0x03FFFF) << 11);
+                *dmy_cfid |= (msg.id & 0x1FFFFFFF);
             }
             /* set length */
             dmy_cfptr = CFPTR_TBL[obj->ch][CAN_SEND];
@@ -686,14 +686,14 @@ int can_read(can_t *obj, CAN_Message *msg, int handle) {
     /* send/receive FIFO buffer isn't empty */
     dmy_cfsts = CFSTS_TBL[obj->ch][CAN_RECV];
     while ((*dmy_cfsts & 0x01) != 0x01) {
-        /* get format, frame type and send/receive FIFO buffer ID(b10-0 or b28-11) */
+        /* get format, frame type and send/receive FIFO buffer ID(b10-0 or b28-0) */
         dmy_cfid = CFID_TBL[obj->ch][CAN_RECV];
         msg->format = (CANFormat)(*dmy_cfid >> 31);
-        msg->type = (CANType)(*dmy_cfid >> 30);
+        msg->type = (CANType)((*dmy_cfid >> 30) & 0x1);
         if (msg->format == CANStandard) {
             msg->id = (*dmy_cfid & 0x07FF);
         } else {
-            msg->id = ((*dmy_cfid >> 11) & 0x03FFFF);
+            msg->id = (*dmy_cfid & 0x1FFFFFFF);
         }
         /* get length */
         dmy_cfptr = CFPTR_TBL[obj->ch][CAN_RECV];
@@ -813,7 +813,7 @@ int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t
     int retval = 0;
     
     if ((format == CANStandard) || (format == CANExtended)) {
-        if (((format == CANStandard) && (id <= 0x07FF)) || ((format == CANExtended) && (id <= 0x03FFFF))) {
+        if (((format == CANStandard) && (id <= 0x07FF)) || ((format == CANExtended) && (id <= 0x1FFFFFFF))) {
             /* set Global Reset mode and Channel Reset mode */
             can_set_global_mode(GL_RESET);
             can_set_channel_mode(obj->ch, CH_RESET);
@@ -824,11 +824,11 @@ int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t
             /* set IDE format */
             *dmy_gaflid = (format << 31);
             if (format == CANExtended) {
-                /* set receive rule ID for bit28-11 */
-                *dmy_gaflid |= (id << 11);
+                /* set receive rule ID for bit28-0 */
+                *dmy_gaflid |= (id & 0x1FFFFFFF);
             } else {
                 /* set receive rule ID for bit10-0 */
-                *dmy_gaflid |= id;
+                *dmy_gaflid |= (id & 0x07FF);
             }
             /* set ID mask bit */
             *dmy_gaflm = (0xC0000000 | mask);
@@ -971,6 +971,7 @@ static void can_set_frequency(can_t *obj, int f) {
     uint8_t brp = 0;
     uint8_t tseg1 = 0;
     uint8_t tseg2 = 0;
+    uint8_t sjw = 0;
     
     /* set clkc */
     if (RZ_A1_IsClockMode0() == false) {
@@ -993,9 +994,10 @@ static void can_set_frequency(can_t *obj, int f) {
     /* calculate TSEG1 bit and TSEG2 bit */
     tseg1 = (tq - 1) * 0.666666667;
     tseg2 = (tq - 1) - tseg1;
+    sjw = (tseg2 > 4)? 4 : tseg2;
     /* set RSCAN0CmCFG register */
     dmy_cfg = CFG_MATCH[obj->ch];
-    *dmy_cfg = ((tseg2 - 1) << 20) | ((tseg1 - 1) << 16) | brp;
+    *dmy_cfg = ((sjw - 1) << 24) | ((tseg2 - 1) << 20) | ((tseg1 - 1) << 16) | brp;
 }
 
 static void can_set_global_mode(int mode) {
diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/can_api.c b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/can_api.c
index 7192cf1ce66..ea826157ca8 100644
--- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/can_api.c
+++ b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/can_api.c
@@ -654,17 +654,17 @@ int can_write(can_t *obj, CAN_Message msg, int cc) {
         __NOP();
     }
     
-    if (((msg.format == CANStandard) && (msg.id <= 0x07FF)) || ((msg.format == CANExtended) && (msg.id <= 0x03FFFF))) {
+    if (((msg.format == CANStandard) && (msg.id <= 0x07FF)) || ((msg.format == CANExtended) && (msg.id <= 0x1FFFFFFF))) {
         /* send/receive FIFO buffer isn't full */
         dmy_cfsts = CFSTS_TBL[obj->ch][CAN_SEND];
         if ((*dmy_cfsts & 0x02) != 0x02) {
-            /* set format, frame type and send/receive FIFO buffer ID(b10-0 or b28-11) */
+            /* set format, frame type and send/receive FIFO buffer ID(b10-0 or b28-0) */
             dmy_cfid = CFID_TBL[obj->ch][CAN_SEND];
             *dmy_cfid = ((msg.format << 31) | (msg.type << 30));
             if (msg.format == CANStandard) {
                 *dmy_cfid |= (msg.id & 0x07FF);
             } else {
-                *dmy_cfid |= ((msg.id & 0x03FFFF) << 11);
+                *dmy_cfid |= (msg.id & 0x1FFFFFFF);
             }
             /* set length */
             dmy_cfptr = CFPTR_TBL[obj->ch][CAN_SEND];
@@ -703,14 +703,14 @@ int can_read(can_t *obj, CAN_Message *msg, int handle) {
     /* send/receive FIFO buffer isn't empty */
     dmy_cfsts = CFSTS_TBL[obj->ch][CAN_RECV];
     while ((*dmy_cfsts & 0x01) != 0x01) {
-        /* get format, frame type and send/receive FIFO buffer ID(b10-0 or b28-11) */
+        /* get format, frame type and send/receive FIFO buffer ID(b10-0 or b28-0) */
         dmy_cfid = CFID_TBL[obj->ch][CAN_RECV];
         msg->format = (CANFormat)(*dmy_cfid >> 31);
-        msg->type = (CANType)(*dmy_cfid >> 30);
+        msg->type = (CANType)((*dmy_cfid >> 30) & 0x1);
         if (msg->format == CANStandard) {
             msg->id = (*dmy_cfid & 0x07FF);
         } else {
-            msg->id = ((*dmy_cfid >> 11) & 0x03FFFF);
+            msg->id = (*dmy_cfid & 0x1FFFFFFF);
         }
         /* get length */
         dmy_cfptr = CFPTR_TBL[obj->ch][CAN_RECV];
@@ -830,7 +830,7 @@ int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t
     int retval = 0;
     
     if ((format == CANStandard) || (format == CANExtended)) {
-        if (((format == CANStandard) && (id <= 0x07FF)) || ((format == CANExtended) && (id <= 0x03FFFF))) {
+        if (((format == CANStandard) && (id <= 0x07FF)) || ((format == CANExtended) && (id <= 0x1FFFFFFF))) {
             /* set Global Reset mode and Channel Reset mode */
             can_set_global_mode(GL_RESET);
             can_set_channel_mode(obj->ch, CH_RESET);
@@ -841,11 +841,11 @@ int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t
             /* set IDE format */
             *dmy_gaflid = (format << 31);
             if (format == CANExtended) {
-                /* set receive rule ID for bit28-11 */
-                *dmy_gaflid |= (id << 11);
+                /* set receive rule ID for bit28-0 */
+                *dmy_gaflid |= (id & 0x1FFFFFFF);
             } else {
                 /* set receive rule ID for bit10-0 */
-                *dmy_gaflid |= id;
+                *dmy_gaflid |= (id & 0x07FF);
             }
             /* set ID mask bit */
             *dmy_gaflm = (0xC0000000 | mask);
@@ -988,6 +988,7 @@ static void can_set_frequency(can_t *obj, int f) {
     uint8_t brp = 0;
     uint8_t tseg1 = 0;
     uint8_t tseg2 = 0;
+    uint8_t sjw = 0;
     
     /* set clkc */
     if (RZ_A1_IsClockMode0() == false) {
@@ -1010,9 +1011,10 @@ static void can_set_frequency(can_t *obj, int f) {
     /* calculate TSEG1 bit and TSEG2 bit */
     tseg1 = (tq - 1) * 0.666666667;
     tseg2 = (tq - 1) - tseg1;
+    sjw = (tseg2 > 4)? 4 : tseg2;
     /* set RSCAN0CmCFG register */
     dmy_cfg = CFG_MATCH[obj->ch];
-    *dmy_cfg = ((tseg2 - 1) << 20) | ((tseg1 - 1) << 16) | brp;
+    *dmy_cfg = ((sjw - 1) << 24) | ((tseg2 - 1) << 20) | ((tseg1 - 1) << 16) | brp;
 }
 
 static void can_set_global_mode(int mode) {
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp
index 273e3d1a695..4410b92f8d6 100644
--- a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp
@@ -28,7 +28,7 @@
 #include "osdep_service.h"
 
 typedef struct _wifi_scan_hdl {
-    void *scan_sema;
+    _sema scan_sema;
     nsapi_size_t ap_num;
     nsapi_size_t scan_num;
     WiFiAccessPoint *ap_details;
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_peripheral_mbed_arm.ar b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_peripheral_mbed_arm.ar
index 9ab2e81f22a..7aff54937f7 100644
Binary files a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_peripheral_mbed_arm.ar and b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_peripheral_mbed_arm.ar differ
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_wlan_mbed_arm.ar b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_wlan_mbed_arm.ar
index 41d9b5f3aa9..980575aa8b6 100644
Binary files a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_wlan_mbed_arm.ar and b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_wlan_mbed_arm.ar differ
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct
index e76cc189fe8..4cf7eea1a8d 100644
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct
@@ -19,24 +19,13 @@ LR_IRAM 0x10007000 (0x70000 - 0x7000) {
 
   ER_IRAM +0 FIXED {
     *rtl8195a_crypto.o (+RO)
-    * (i.mbedtls*)
+    *(i.mbedtls*)
     *libc.a (+RO)
-    
-	*rtx_*.o (+RO)
-    *Ticker.o (+RO)
-    *Timeout.o (+RO)
-	*rtx_timer.o (+RO)
-    *TimerEvent.o (+RO)
-    *mbed_ticker_api.o (+RO)
-    *mbed_critical.o (+RO)
-    *us_ticker.o (+RO)
-    
-    *lib_peripheral_mbed_arm.ar (+RO)
+    *rtx_*.o (+RO)
   }
 
   RW_IRAM1 +0 UNINIT FIXED {
     *rtl8195a_crypto.o(+RW)
-    ;*mbedtls*.o(+RW)
     *libc.a (+RW)
     *(.sdram.data*)
     *lib_peripheral_mbed_arm.ar (+RW)
@@ -44,7 +33,6 @@ LR_IRAM 0x10007000 (0x70000 - 0x7000) {
 
   RW_IRAM2 +0 UNINIT FIXED {
     *rtl8195a_crypto.o(+ZI, COMMON)
-    ;*mbedtls*.o(+ZI, COMMON)
     *libc.a (+ZI, COMMON)
     *(.bss.thread_stack_main)
     *lib_peripheral_mbed_arm.ar (+ZI, COMMON)
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a_startup.S b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a_startup.S
new file mode 100644
index 00000000000..c184bdff725
--- /dev/null
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a_startup.S
@@ -0,0 +1,31 @@
+;
+; Copyright (c) 2017 Realtek Semiconductor Corp.
+;
+; Licensed under the Apache License, Version 2.0 (the "License");
+; you may not use this file except in compliance with the License.
+; You may obtain a copy of the License at
+;
+;     http://www.apache.org/licenses/LICENSE-2.0
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an "AS IS" BASIS,
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+
+            PRESERVE8
+            THUMB
+
+            AREA    |i.PLAT_Start|, CODE, READONLY
+
+PLAT_Start  PROC
+
+            EXPORT  PLAT_Start
+    IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
+    IMPORT  PLAT_Init
+            LDR     SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
+            LDR     R0, =PLAT_Init
+            BX      R0
+            ENDP
+            ALIGN
+            END
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a
index 352cdf86f64..2f6ab3f0c9b 100644
Binary files a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a and b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a differ
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_wlan_mbed_gcc.a b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_wlan_mbed_gcc.a
index a7786cbbd5b..312525c6181 100644
Binary files a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_wlan_mbed_gcc.a and b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_wlan_mbed_gcc.a differ
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld
index 4c05ef96414..ed3661c6af7 100644
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld
@@ -70,15 +70,6 @@ SECTIONS
         *rtl8195a_crypto.o (.text* .rodata*)
         *mbedtls*.o (.text* .rodata*)
         *libc.a: (.text* .rodata*)
-        *Ticker.o (.text*)
-        *Timeout.o (.text*)
-        *TimerEvent.o (.text*)
-        *mbed_ticker_api.o (.text*)
-        *mbed_critical.o (.text*)
-        *us_ticker.o (.text*)
-        
-        *lib_peripheral_mbed_gcc.a: (.text*)
-        
     } > SRAM1
 
     .text.sram2 :
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a_startup.S b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a_startup.S
new file mode 100644
index 00000000000..219265a5083
--- /dev/null
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a_startup.S
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017 Realtek Semiconductor Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+    .syntax unified
+    .thumb
+
+    .global  __StackTop
+    .global  PLAT_Init
+
+    /* entry point of application image */
+    .section  .text.PLAT_Start
+    .weak  PLAT_Start
+    .type  PLAT_Start, %function
+PLAT_Start:
+    ldr   sp, =__StackTop
+    ldr   r0, =PLAT_Init
+    bx    r0
+    .size  PLAT_Start, .-PLAT_Start
+    .end
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_peripheral_mbed_iar.a b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_peripheral_mbed_iar.a
index 63c8d704d43..e906f7fd123 100644
Binary files a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_peripheral_mbed_iar.a and b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_peripheral_mbed_iar.a differ
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_wlan_mbed_iar.a b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_wlan_mbed_iar.a
index 138b31f6269..a19c10c6367 100644
Binary files a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_wlan_mbed_iar.a and b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_wlan_mbed_iar.a differ
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/librom.a b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/librom.a
deleted file mode 100644
index 4978f11c11e..00000000000
Binary files a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/librom.a and /dev/null differ
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a.icf b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a.icf
index 5244ef9a5c3..abf86b9e16f 100644
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a.icf
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a.icf
@@ -1,330 +1,212 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-//define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-
-//include "main.icf";
+/*
+ * Copyright (c) 2013-2017 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
 
 /*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__                  = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__                    = 0x000FFFFF;
-define symbol __ICFEDIT_region_TCM_start__                  = 0x1FFF0000;
-define symbol __ICFEDIT_region_TCM_end__                    = 0x1FFFFFFF;
-define symbol __ICFEDIT_region_ROM_USED_RAM_start__         = 0x10000000;
-define symbol __ICFEDIT_region_ROM_USED_RAM_end__           = 0x10005FFF;
-//define symbol __ICFEDIT_region_RECY_RAM_start__           = 0x10002090;
-//define symbol __ICFEDIT_region_RECY_RAM_end__             = 0x100037FF;
-if( !isdefinedsymbol( __ICFEDIT_region_BD_RAM_start__ ) ) {
-    define symbol __ICFEDIT_region_BD_RAM_start__           = 0x10007000;
-}
-if( !isdefinedsymbol( __ICFEDIT_region_BD_RAM_end__ ) ) {
-    define symbol __ICFEDIT_region_BD_RAM_end__             = 0x1006FFFF;
-}
-define symbol __ICFEDIT_region_SDRAM_RAM_start__            = 0x30000000;
-define symbol __ICFEDIT_region_SDRAM_RAM_end__              = 0x301FFFFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__   = 0x1000;
-define symbol __ICFEDIT_size_heap__     = 0x19000;
-/**** End of ICF editor section. ###ICF###*/
-
+define symbol __SRAM_start__  = 0x10007000;
+define symbol __SRAM_end__    = 0x1006FFFF;
+define symbol __DTCM_start__  = 0x1FFF0000;
+define symbol __DTCM_end__    = 0x1FFFFFFF;
+define symbol __DRAM_start__  = 0x30000000;
+define symbol __DRAM_end__    = 0x301FFFFF;
 
 define memory mem with size = 4G;
-define region ROM_region               = mem:[from __ICFEDIT_region_ROM_start__               to __ICFEDIT_region_ROM_end__];
-define region TCM_region               = mem:[from __ICFEDIT_region_TCM_start__               to __ICFEDIT_region_TCM_end__];
-define region ROM_USED_RAM_region   = mem:[from __ICFEDIT_region_ROM_USED_RAM_start__   to __ICFEDIT_region_ROM_USED_RAM_end__];
-//define region RECY_RAM_region       = mem:[from __ICFEDIT_region_RECY_RAM_start__       to __ICFEDIT_region_RECY_RAM_end__];
-define region BD_RAM_region           = mem:[from __ICFEDIT_region_BD_RAM_start__           to __ICFEDIT_region_BD_RAM_end__];
-define region SDRAM_RAM_region       = mem:[from __ICFEDIT_region_SDRAM_RAM_start__       to __ICFEDIT_region_SDRAM_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-//initialize by copy { readwrite };
-//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
-
-//do not initialize  { section * };
-
-//place at address mem:__ICFEDIT_intvec_start__ { readonly section .vectors_table };
-
-
-/*place in RAM_region   { readwrite, block CSTACK, block HEAP };*/
-//place in TCM_region   { readwrite };
-
-/****************************************
- * ROM Section config                   *
- ****************************************/
-keep { section .rom };
-place at start of ROM_region   { section .rom };
-
-/****************************************
- * BD RAM Section config                *
- ****************************************/
-keep { section .ram_dedecated_vector_table* };
-define block .vector_table with fixed order{section .ram_dedecated_vector_table*};
-
-keep { section .ram_user_define_irq_table* };
-define block .user_vector_table with fixed order{section .ram_user_define_irq_table*};
-
-keep { section .ram_user_define_data_table* };
-define block .user_data_table with fixed order{section .ram_user_define_data_table*};
-
-define block .rom.bss with fixed order{         section .hal.ram.bss* object hal_misc.o, 
-                                                section .hal.ram.bss* object hal_pinmux.o,
-                                                section .hal.ram.bss* object diag.o,
-                                                section .hal.ram.bss* object rtl8195a_ssi_rom.o,
-                                                section .hal.ram.bss* object rtl8195a_gpio.o,
-                                                section .hal.ram.bss*,
-                                                section .timer2_7_vector_table.data*, 
-                                                section .infra.ram.bss*,
-                                                section .mon.ram.bss*,
-                                                section .wlan_ram_map* object rom_wlan_ram_map.o,
-                                                section .wlan_ram_map*,
-                                                section .libc.ram.bss*,
-                                      };
-
-keep { section .start.ram.data* };
-define block .ram.start.table with fixed order{ section .start.ram.data* };
-
-keep { section .image1.validate.rodata* };
-keep { section .infra.ram.data* };
-keep { section .timer.ram.data* };
-keep { section .hal.ram.data* };
-define block .ram_image1.data with fixed order{ section .image1.validate.rodata*,
-                                                section .infra.ram.data*,
-                                                section .timer.ram.data*,
-                                                section .cutb.ram.data*,
-                                                section .hal.ram.data* object rom.o,    // for standard libaray __impure_data_ptr
-                                                section .cutc.ram.data*,
-                                                section .hal.ram.data*
-                                              };
-define block .ram_image1.bss with fixed order{     //section .hal.flash.data*,
-                                                section .hal.sdrc.data*
-                                                };
-
-define block .ram_image1.text with fixed order{ section .hal.ram.text*,
-                                                section .hal.sdrc.text*,
-                                                //section .text* object startup.o,
-                                                section .infra.ram.text*,
-                                                };
-
-define block IMAGE1 with fixed order { section LOADER };
-define block IMAGE1_DBG with fixed order { block .ram.start.table, block .ram_image1.data, block .ram_image1.bss, block .ram_image1.text };
-
-place at start of ROM_USED_RAM_region   {  
-                                            block .vector_table, 
-                                            block .user_vector_table,
-                                            block .user_data_table, 
-                                            block .rom.bss, 
-                                            block IMAGE1
-                                        };
-
-                                        
-keep { section .image2.ram.data* };
-define block .image2.start.table1 with fixed order{ section .image2.ram.data* };
-
-keep { section .image2.validate.rodata*, section .custom.validate.rodata* };
-define block .image2.start.table2 with fixed order{ section .image2.validate.rodata*, section .custom.validate.rodata* };
-
-define block SHT$$PREINIT_ARRAY { preinit_array };
-define block SHT$$INIT_ARRAY { init_array };
-define block CPP_INIT with alignment = 8, fixed order {        
-                                                block SHT$$PREINIT_ARRAY,
-                                                block SHT$$INIT_ARRAY 
-                                                };
-define block FPB_REMAP with alignment = 256,fixed order {
-                                                section .fpb.remap*
-                                                };
-
-define block MBEDTLS_TEXT with alignment = 8, fixed order{
-                                        section .text* object aes.o,
-                                        section .text* object aesni.o,
-                                        section .text* object arc4.o,
-                                        section .text* object asn1parse.o,
-                                        section .text* object asn1write.o,
-                                        section .text* object base64.o,
-                                        section .text* object bignum.o,
-                                        section .text* object blowfish.o,
-                                        section .text* object camellia.o,
-                                        section .text* object ccm.o,
-                                        section .text* object certs.o,
-                                        section .text* object cipher.o,
-                                        section .text* object cipher_wrap.o,
-                                        section .text* object cmac.o,
-                                        section .text* object ctr_drbg.o,
-                                        section .text* object debug.o,
-                                        section .text* object des.o,
-                                        section .text* object dhm.o,
-                                        section .text* object ecdh.o,
-                                        section .text* object ecdsa.o,
-                                        section .text* object ecjpake.o,
-                                        section .text* object ecp.o,
-                                        section .text* object ecp_curves.o,
-                                        section .text* object entropy.o,
-                                        section .text* object entropy_poll.o,
-                                        section .text* object error.o,
-                                        section .text* object gcm.o,
-                                        section .text* object havege.o,
-                                        section .text* object hmac_drbg.o,
-                                        section .text* object md.o,
-                                        section .text* object md2.o,
-                                        section .text* object md4.o,
-                                        section .text* object md5.o,
-                                        section .text* object md_wrap.o,
-                                        section .text* object memory_buffer_alloc.o,
-                                        section .text* object net_sockets.o,
-                                        section .text* object oid.o,
-                                        section .text* object padlock.o,
-                                        section .text* object pem.o,
-                                        section .text* object pk.o,
-                                        section .text* object pk_wrap.o,
-                                        section .text* object pkcs11.o,
-                                        section .text* object pkcs12.o,
-                                        section .text* object pkcs5.o,
-                                        section .text* object pkparse.o,
-                                        section .text* object pkwrite.o,
-                                        section .text* object platform.o,
-                                        section .text* object ripemd160.o,
-                                        section .text* object rsa.o,
-                                        section .text* object sha1.o,
-                                        section .text* object sha256.o,
-                                        section .text* object sha512.o,
-                                        section .text* object ssl_cache.o,
-                                        section .text* object ssl_ciphersuites.o,
-                                        section .text* object ssl_cli.o,
-                                        section .text* object ssl_cookie.o,
-                                        section .text* object ssl_srv.o,
-                                        section .text* object ssl_ticket.o,
-                                        section .text* object ssl_tls.o,
-                                        section .text* object threading.o,
-                                        section .text* object timing.o,
-                                        section .text* object version.o,
-                                        section .text* object version_features.o,
-                                        section .text* object x509.o,
-                                        section .text* object x509_create.o,
-                                        section .text* object x509_crl.o,
-                                        section .text* object x509_crt.o,
-                                        section .text* object x509_csr.o,
-                                        section .text* object x509write_crt.o,
-                                        section .text* object x509write_csr.o,
-                                        section .text* object xtea.o,
-                                       };
-
-define block .sram1.text with fixed order   {  
-                                                block MBEDTLS_TEXT,
-                                                section .text* object Ticker.o,
-                                                section .text* object Timeout.o,
-                                                section .text* object TimerEvent.o,
-                                                section .text* object mbed_ticker_api.o,
-                                                section .text* object mbed_critical.o,
-                                                section .text* object us_ticker.o,
-                                                
-                                                section .text* object lib_peripheral_mbed_iar.a,
-                                            };
-
-define block .sram2.text with fixed order   {
-                                                block .image2.start.table1,
-                                                block .image2.start.table2,
-                                                section .mon.ram.text*, 
-                                                section .hal.flash.text*,
-                                                section .hal.sdrc.text*,
-                                                section .hal.gpio.text*,
-                                                section .text*,
-                                                section .infra.ram.start*,
-                                                section .rodata*,
-                                            };
-
-define block .sram2.data with fixed order   {
-                                                //section .infra.ram.start*,
-                                                //section .rodata*,
-                                                //section .wlan.text,
-                                                //section .wps.text,
-                                                section CODE,
-                                                //section .otg.rom.text,
-                                                section Veneer object startup.o,
-                                                section __DLIB_PERTHREAD,
-                                                section .iar.dynexit*,
-                                                block CPP_INIT,
-                                                //section .mdns.text
-                                            };
-define block .ram.data with fixed order {
-                                            readwrite, readonly,
-                                            section .data*, 
-                                            section .wlan.data,
-                                            section .wps.data,
-                                            section DATA, 
-                                            section .ram.otg.data.a, 
-                                            section .iar.init_table,
-                                            //section .mdns.data,
-                                            //section .data* object lib_peripheral_mbed_iar.a,
-                                        };
-
-define block .ram.bss with fixed order  {
-                                            section .bss*,
-                                            section COMMON,
-                                            section .bdsram.data*,
-                                        };
-
-define block IMAGE2 with fixed order    {
-                                            block .sram1.text,
-                                            block .ram.data,
-                                            block .ram.bss
-                                        };
-
-define block .bf_data with fixed order{ section .bfsram.data* };
-define block .heap with fixed order{ section .heap* };
-define block .stack_dummy with fixed order { section .stack };
-place at start of BD_RAM_region {  
-                                    block IMAGE2,
-                                    //block IMAGE1_DBG,
-                                    //block .ram.bss,
-                                    //block .bf_data,
-                                };
-
-place at end of BD_RAM_region   { 
-                                     block .bf_data,
-                                     block HEAP,
-                                };
-                                  
-define block SDRAM with fixed order {
-                                        block .sram2.text,
-                                        block .sram2.data,  
-                                        section .sdram.text*, 
-                                        section .sdram.data*, 
-                                        section .mdns.text*, 
-                                        section .mdns.data*,
-                                        block FPB_REMAP
-                                    };
-define block SDRBSS with fixed order{ 
-                                        section .sdram.bss*                                
-                                    };
-
-place at start of SDRAM_RAM_region  {  
-                                        block SDRAM, 
-                                        block SDRBSS,
-                                        //block IMAGE1_DBG
-                                    };
-
-
-/* TCM placement */
-define overlay TCM_overlay { 
-                                section .tcm.heap,
-                                section .bss object lwip_mem.o,
-                                section .bss object lwip_memp.o,
-                                block .heap,
-                                block .stack_dummy
-                            };
-/* dummy code placement */
-define overlay TCM_overlay { block IMAGE1_DBG };
-place at start of TCM_region {     overlay TCM_overlay }; 
-place at end of TCM_region  {     block CSTACK}; 
-
-define exported symbol __rom_bss_start__ = 0x10000300;     // use in rom
-define exported symbol __rom_bss_end__ = 0x10000bc8;    // use in rom
-define exported symbol __ram_start_table_start__= 0x10000bc8;    // use in rom
-define exported symbol __image1_validate_code__= 0x10000bdc;    // needed by ram code
-define exported symbol _rtl_impure_ptr = 0x10001c60;        // for standard library
-
-define exported symbol __sdio_rom_bss_start__ = 0x1006D000;
-define exported symbol __sdio_rom_bss_end__ = 0x1006fa10;
+define region TCM_region = mem:[from __DTCM_start__ to __DTCM_end__];
+define region RAM_region = mem:[from __SRAM_start__ to __SRAM_end__] |
+                           mem:[from __DRAM_start__ to __DRAM_end__];
+
+define block CSTACK with alignment = 8, size = 0x1000  { };
+define block HEAP   with alignment = 8, size = 0x19000 { };
+
+do not initialize  { section .noinit };
+
+/**
+    IMAGE2
+**/
+keep {
+    section .image2.ram.data*,
+    section .image2.validate.rodata*,
+};
+
+define block .image2.table with fixed order {
+    section .image2.ram.data*,
+    section .image2.validate.rodata*,
+};
+
+define block FPB_REMAP with alignment = 256, fixed order {
+    section .fpb.remap*
+};
+
+define block .text.mbedtls {
+    readonly object aes.o,
+    readonly object aesni.o,
+    readonly object arc4.o,
+    readonly object asn1parse.o,
+    readonly object asn1write.o,
+    readonly object base64.o,
+    readonly object bignum.o,
+    readonly object blowfish.o,
+    readonly object camellia.o,
+    readonly object ccm.o,
+    readonly object certs.o,
+    readonly object cipher.o,
+    readonly object cipher_wrap.o,
+    readonly object cmac.o,
+    readonly object ctr_drbg.o,
+    readonly object debug.o,
+    readonly object des.o,
+    readonly object dhm.o,
+    readonly object ecdh.o,
+    readonly object ecdsa.o,
+    readonly object ecjpake.o,
+    readonly object ecp.o,
+    readonly object ecp_curves.o,
+    readonly object entropy.o,
+    readonly object entropy_poll.o,
+    readonly object error.o,
+    readonly object gcm.o,
+    readonly object havege.o,
+    readonly object hmac_drbg.o,
+    readonly object md.o,
+    readonly object md2.o,
+    readonly object md4.o,
+    readonly object md5.o,
+    readonly object md_wrap.o,
+    readonly object memory_buffer_alloc.o,
+    readonly object net_sockets.o,
+    readonly object oid.o,
+    readonly object padlock.o,
+    readonly object pem.o,
+    readonly object pk.o,
+    readonly object pk_wrap.o,
+    readonly object pkcs11.o,
+    readonly object pkcs12.o,
+    readonly object pkcs5.o,
+    readonly object pkparse.o,
+    readonly object pkwrite.o,
+    readonly object platform.o,
+    readonly object ripemd160.o,
+    readonly object rsa.o,
+    readonly object sha1.o,
+    readonly object sha256.o,
+    readonly object sha512.o,
+    readonly object ssl_cache.o,
+    readonly object ssl_ciphersuites.o,
+    readonly object ssl_cli.o,
+    readonly object ssl_cookie.o,
+    readonly object ssl_srv.o,
+    readonly object ssl_ticket.o,
+    readonly object ssl_tls.o,
+    readonly object threading.o,
+    readonly object timing.o,
+    readonly object version.o,
+    readonly object version_features.o,
+    readonly object x509.o,
+    readonly object x509_create.o,
+    readonly object x509_crl.o,
+    readonly object x509_crt.o,
+    readonly object x509_csr.o,
+    readonly object x509write_crt.o,
+    readonly object x509write_csr.o,
+    readonly object xtea.o,
+};
+
+define block .text.sram {
+    readonly object rtl8195a_crypto.o,
+    readonly object vector_table_M.o,
+    section .text.sram*,
+};
+
+define block .text.dram {
+    section .text.dram*,
+    section .text*,
+    section .rodata*,
+    section .sdram.text*,
+    section .mdns.text*,
+    section CODE,
+};
+
+define block .data.sram {
+    readwrite object rtl8195a_crypto.o,
+    readwrite object vector_table_M.o,
+    readwrite object lib_peripheral_mbed_iar.a,
+    section .data.os.*,
+    section .data.sram*,
+    section .wlan.data,
+    section .wps.data,
+    section .ram.otg.data.a,
+    section .bfsram.data*,
+};
+
+define block .data.dram {
+    section .data*,
+    section .data.dram*,
+    section .sdram.data*,
+    section .mdns.data*,
+    section .iar.init_table,
+    section .iar.dynexit*,
+    section DATA,
+    section __DLIB_PERTHREAD,
+};
+
+define block .data.dtcm {
+    section .data.dtcm*,
+};
+
+define block .bss.sram {
+    zeroinit object rtl8195a_crypto.o,
+    section .bss.os.*,
+    section .bss.sram*,
+    section .bdsram.data*,
+};
+
+define block .bss.dram {
+    zeroinit,
+    section .sdram.bss*,
+};
+
+define block .bss.dtcm {
+    zeroinit object lwip_mem.o,
+    zeroinit object lwip_memp.o,
+    section .bss.dtcm*,
+};
+
+place in TCM_region {
+    section .tcm.heap,
+    block .data.dtcm,
+    block .bss.dtcm,
+};
+
+place in RAM_region {
+    readonly,
+    block .text.sram,
+    block .text.mbedtls,
+    readwrite,
+    block .data.sram,
+    block .bss.sram,
+    block HEAP,
+    block CSTACK,
+    readonly,
+    block .image2.table,
+    block .text.dram,
+    readwrite,
+    block .data.dram,
+    block .bss.dram,
+    block FPB_REMAP,
+};
+
+include "rtl8195a_rom.h";
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a_rom.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a_rom.h
new file mode 100644
index 00000000000..d9a7b284d9d
--- /dev/null
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a_rom.h
@@ -0,0 +1,740 @@
+define exported symbol __vectors_table = 0x00000000;
+define exported symbol Reset_Handler = 0x00000101;
+define exported symbol NMI_Handler = 0x00000109;
+define exported symbol HardFault_Handler = 0x0000010d;
+define exported symbol MemManage_Handler = 0x00000121;
+define exported symbol BusFault_Handler = 0x00000125;
+define exported symbol UsageFault_Handler = 0x00000129;
+define exported symbol HalLogUartInit = 0x00000201;
+define exported symbol HalSerialPutcRtl8195a = 0x000002d9;
+define exported symbol HalSerialGetcRtl8195a = 0x00000309;
+define exported symbol HalSerialGetIsrEnRegRtl8195a = 0x00000329;
+define exported symbol HalSerialSetIrqEnRegRtl8195a = 0x00000335;
+define exported symbol HalCpuClkConfig = 0x00000341;
+define exported symbol HalGetCpuClk = 0x00000355;
+define exported symbol HalRomInfo = 0x0000039d;
+define exported symbol HalGetRomInfo = 0x000003b5;
+define exported symbol HalResetVsr = 0x000003c5;
+define exported symbol HalDelayUs = 0x00000899;
+define exported symbol HalNMIHandler = 0x000008e1;
+define exported symbol HalHardFaultHandler = 0x00000911;
+define exported symbol HalMemManageHandler = 0x00000c09;
+define exported symbol HalBusFaultHandler = 0x00000c39;
+define exported symbol HalUsageFaultHandler = 0x00000c69;
+define exported symbol HalUart0PinCtrlRtl8195A = 0x00000cfd;
+define exported symbol HalUart1PinCtrlRtl8195A = 0x00000dc9;
+define exported symbol HalUart2PinCtrlRtl8195A = 0x00000e9d;
+define exported symbol HalSPI0PinCtrlRtl8195A = 0x00000f75;
+define exported symbol HalSPI1PinCtrlRtl8195A = 0x00001015;
+define exported symbol HalSPI2PinCtrlRtl8195A = 0x000010e5;
+define exported symbol HalSPI0MCSPinCtrlRtl8195A = 0x000011b5;
+define exported symbol HalI2C0PinCtrlRtl8195A = 0x00001275;
+define exported symbol HalI2C1PinCtrlRtl8195A = 0x00001381;
+define exported symbol HalI2C2PinCtrlRtl8195A = 0x00001459;
+define exported symbol HalI2C3PinCtrlRtl8195A = 0x00001529;
+define exported symbol HalI2S0PinCtrlRtl8195A = 0x00001639;
+define exported symbol HalI2S1PinCtrlRtl8195A = 0x0000176d;
+define exported symbol HalPCM0PinCtrlRtl8195A = 0x00001845;
+define exported symbol HalPCM1PinCtrlRtl8195A = 0x00001949;
+define exported symbol HalSDIODPinCtrlRtl8195A = 0x00001a1d;
+define exported symbol HalSDIOHPinCtrlRtl8195A = 0x00001a6d;
+define exported symbol HalMIIPinCtrlRtl8195A = 0x00001ab9;
+define exported symbol HalWLLEDPinCtrlRtl8195A = 0x00001b51;
+define exported symbol HalWLANT0PinCtrlRtl8195A = 0x00001c0d;
+define exported symbol HalWLANT1PinCtrlRtl8195A = 0x00001c61;
+define exported symbol HalWLBTCOEXPinCtrlRtl8195A = 0x00001cb5;
+define exported symbol HalWLBTCMDPinCtrlRtl8195A = 0x00001d05;
+define exported symbol HalNFCPinCtrlRtl8195A = 0x00001d59;
+define exported symbol HalPWM0PinCtrlRtl8195A = 0x00001da9;
+define exported symbol HalPWM1PinCtrlRtl8195A = 0x00001ead;
+define exported symbol HalPWM2PinCtrlRtl8195A = 0x00001fb5;
+define exported symbol HalPWM3PinCtrlRtl8195A = 0x000020b1;
+define exported symbol HalETE0PinCtrlRtl8195A = 0x000021b9;
+define exported symbol HalETE1PinCtrlRtl8195A = 0x000022c1;
+define exported symbol HalETE2PinCtrlRtl8195A = 0x000023c9;
+define exported symbol HalETE3PinCtrlRtl8195A = 0x000024d1;
+define exported symbol HalEGTIMPinCtrlRtl8195A = 0x000025d9;
+define exported symbol HalSPIFlashPinCtrlRtl8195A = 0x00002679;
+define exported symbol HalSDRPinCtrlRtl8195A = 0x00002725;
+define exported symbol HalJTAGPinCtrlRtl8195A = 0x0000280d;
+define exported symbol HalTRACEPinCtrlRtl8195A = 0x00002861;
+define exported symbol HalLOGUartPinCtrlRtl8195A = 0x000028b9;
+define exported symbol HalLOGUartIRPinCtrlRtl8195A = 0x0000291d;
+define exported symbol HalSICPinCtrlRtl8195A = 0x00002981;
+define exported symbol HalEEPROMPinCtrlRtl8195A = 0x000029d9;
+define exported symbol HalDEBUGPinCtrlRtl8195A = 0x00002a31;
+define exported symbol HalPinCtrlRtl8195A = 0x00002b39;
+define exported symbol SpicRxCmdRtl8195A = 0x00002e5d;
+define exported symbol SpicWaitBusyDoneRtl8195A = 0x00002ea5;
+define exported symbol SpicGetFlashStatusRtl8195A = 0x00002eb5;
+define exported symbol SpicWaitWipDoneRtl8195A = 0x00002f55;
+define exported symbol SpicTxCmdRtl8195A = 0x00002f6d;
+define exported symbol SpicSetFlashStatusRtl8195A = 0x00002fc1;
+define exported symbol SpicCmpDataForCalibrationRtl8195A = 0x00003049;
+define exported symbol SpicLoadInitParaFromClockRtl8195A = 0x00003081;
+define exported symbol SpicInitRtl8195A = 0x000030e5;
+define exported symbol SpicEraseFlashRtl8195A = 0x000031bd;
+define exported symbol SpiFlashApp = 0x00003279;
+define exported symbol HalPeripheralIntrHandle = 0x000033b5;
+define exported symbol HalSysOnIntrHandle = 0x00003439;
+define exported symbol HalWdgIntrHandle = 0x00003485;
+define exported symbol HalTimer0IntrHandle = 0x000034d5;
+define exported symbol HalTimer1IntrHandle = 0x00003525;
+define exported symbol HalI2C3IntrHandle = 0x00003575;
+define exported symbol HalTimer2To7IntrHandle = 0x000035c5;
+define exported symbol HalSpi0IntrHandle = 0x00003615;
+define exported symbol HalGpioIntrHandle = 0x00003665;
+define exported symbol HalUart0IntrHandle = 0x000036b5;
+define exported symbol HalSpiFlashIntrHandle = 0x00003705;
+define exported symbol HalUsbOtgIntrHandle = 0x00003755;
+define exported symbol HalSdioHostIntrHandle = 0x000037a5;
+define exported symbol HalI2s0OrPcm0IntrHandle = 0x000037f5;
+define exported symbol HalI2s1OrPcm1IntrHandle = 0x00003845;
+define exported symbol HalWlDmaIntrHandle = 0x00003895;
+define exported symbol HalWlProtocolIntrHandle = 0x000038e5;
+define exported symbol HalCryptoIntrHandle = 0x00003935;
+define exported symbol HalGmacIntrHandle = 0x00003985;
+define exported symbol HalGdma0Ch0IntrHandle = 0x000039d5;
+define exported symbol HalGdma0Ch1IntrHandle = 0x00003a25;
+define exported symbol HalGdma0Ch2IntrHandle = 0x00003a75;
+define exported symbol HalGdma0Ch3IntrHandle = 0x00003ac5;
+define exported symbol HalGdma0Ch4IntrHandle = 0x00003b15;
+define exported symbol HalGdma0Ch5IntrHandle = 0x00003b65;
+define exported symbol HalGdma1Ch0IntrHandle = 0x00003bb5;
+define exported symbol HalGdma1Ch1IntrHandle = 0x00003c05;
+define exported symbol HalGdma1Ch2IntrHandle = 0x00003c55;
+define exported symbol HalGdma1Ch3IntrHandle = 0x00003ca5;
+define exported symbol HalGdma1Ch4IntrHandle = 0x00003cf5;
+define exported symbol HalGdma1Ch5IntrHandle = 0x00003d45;
+define exported symbol HalSdioDeviceIntrHandle = 0x00003d95;
+define exported symbol VectorTableInitRtl8195A = 0x00003de5;
+define exported symbol VectorTableInitForOSRtl8195A = 0x00004019;
+define exported symbol VectorIrqRegisterRtl8195A = 0x00004029;
+define exported symbol VectorIrqUnRegisterRtl8195A = 0x00004091;
+define exported symbol VectorIrqEnRtl8195A = 0x000040f1;
+define exported symbol VectorIrqDisRtl8195A = 0x0000418d;
+define exported symbol _UartRxDmaIrqHandle = 0x0000422d;
+define exported symbol HalRuartPutCRtl8195a = 0x00004281;
+define exported symbol HalRuartGetCRtl8195a = 0x0000429d;
+define exported symbol HalRuartRTSCtrlRtl8195a = 0x000042bd;
+define exported symbol HalRuartGetDebugValueRtl8195a = 0x000042e1;
+define exported symbol HalRuartGetIMRRtl8195a = 0x000043e1;
+define exported symbol HalRuartSetIMRRtl8195a = 0x0000442d;
+define exported symbol _UartIrqHandle = 0x00004465;
+define exported symbol HalRuartDmaInitRtl8195a = 0x00004681;
+define exported symbol HalRuartIntDisableRtl8195a = 0x00004845;
+define exported symbol HalRuartDeInitRtl8195a = 0x00004855;
+define exported symbol HalRuartIntEnableRtl8195a = 0x00004985;
+define exported symbol _UartTxDmaIrqHandle = 0x00004995;
+define exported symbol HalRuartRegIrqRtl8195a = 0x000049d1;
+define exported symbol HalRuartAdapterLoadDefRtl8195a = 0x00004a4d;
+define exported symbol HalRuartTxGdmaLoadDefRtl8195a = 0x00004add;
+define exported symbol HalRuartRxGdmaLoadDefRtl8195a = 0x00004bc9;
+define exported symbol RuartLock = 0x00004cc9;
+define exported symbol RuartUnLock = 0x00004ced;
+define exported symbol HalRuartIntSendRtl8195a = 0x00004d09;
+define exported symbol HalRuartDmaSendRtl8195a = 0x00004e35;
+define exported symbol HalRuartStopSendRtl8195a = 0x00004f89;
+define exported symbol HalRuartIntRecvRtl8195a = 0x0000504d;
+define exported symbol HalRuartDmaRecvRtl8195a = 0x000051ad;
+define exported symbol HalRuartStopRecvRtl8195a = 0x000052cd;
+define exported symbol RuartIsTimeout = 0x00005385;
+define exported symbol HalRuartSendRtl8195a = 0x000053b1;
+define exported symbol HalRuartRecvRtl8195a = 0x00005599;
+define exported symbol RuartResetRxFifoRtl8195a = 0x00005751;
+define exported symbol HalRuartResetRxFifoRtl8195a = 0x00005775;
+define exported symbol HalRuartInitRtl8195a = 0x00005829;
+define exported symbol HalGdmaOnOffRtl8195a = 0x00005df1;
+define exported symbol HalGdmaChIsrEnAndDisRtl8195a = 0x00005e0d;
+define exported symbol HalGdmaChEnRtl8195a = 0x00005e51;
+define exported symbol HalGdmaChDisRtl8195a = 0x00005e6d;
+define exported symbol HalGdamChInitRtl8195a = 0x00005e91;
+define exported symbol HalGdmaChSetingRtl8195a = 0x00005ebd;
+define exported symbol HalGdmaChBlockSetingRtl8195a = 0x000060dd;
+define exported symbol HalGdmaChIsrCleanRtl8195a = 0x00006419;
+define exported symbol HalGdmaChCleanAutoSrcRtl8195a = 0x000064a1;
+define exported symbol HalGdmaChCleanAutoDstRtl8195a = 0x00006501;
+define exported symbol HalEFUSEPowerSwitch8195AROM = 0x00006561;
+define exported symbol HALEFUSEOneByteReadROM = 0x000065f9;
+define exported symbol HALEFUSEOneByteWriteROM = 0x00006699;
+define exported symbol __rtl_memcmpb_v1_00 = 0x0000681d;
+define exported symbol __rtl_random_v1_00 = 0x00006861;
+define exported symbol __rtl_align_to_be32_v1_00 = 0x00006881;
+define exported symbol __rtl_memsetw_v1_00 = 0x00006899;
+define exported symbol __rtl_memsetb_v1_00 = 0x000068ad;
+define exported symbol __rtl_memcpyw_v1_00 = 0x000068bd;
+define exported symbol __rtl_memcpyb_v1_00 = 0x000068dd;
+define exported symbol __rtl_memDump_v1_00 = 0x000068f5;
+define exported symbol __rtl_AES_set_encrypt_key = 0x00006901;
+define exported symbol __rtl_cryptoEngine_AES_set_decrypt_key = 0x00006c11;
+define exported symbol __rtl_cryptoEngine_set_security_mode_v1_00 = 0x00006c95;
+define exported symbol __rtl_cryptoEngine_init_v1_00 = 0x00006ea9;
+define exported symbol __rtl_cryptoEngine_exit_v1_00 = 0x00007055;
+define exported symbol __rtl_cryptoEngine_reset_v1_00 = 0x000070b1;
+define exported symbol __rtl_cryptoEngine_v1_00 = 0x000070ed;
+define exported symbol __rtl_crypto_cipher_init_v1_00 = 0x00007c69;
+define exported symbol __rtl_crypto_cipher_encrypt_v1_00 = 0x00007c89;
+define exported symbol __rtl_crypto_cipher_decrypt_v1_00 = 0x00007cad;
+define exported symbol HalSsiPinmuxEnableRtl8195a = 0x00007cd5;
+define exported symbol HalSsiEnableRtl8195a = 0x00007e45;
+define exported symbol HalSsiDisableRtl8195a = 0x00007ef9;
+define exported symbol HalSsiLoadSettingRtl8195a = 0x00007fad;
+define exported symbol HalSsiSetInterruptMaskRtl8195a = 0x00008521;
+define exported symbol HalSsiGetInterruptMaskRtl8195a = 0x000085c9;
+define exported symbol HalSsiSetSclkPolarityRtl8195a = 0x0000863d;
+define exported symbol HalSsiSetSclkPhaseRtl8195a = 0x00008715;
+define exported symbol HalSsiWriteRtl8195a = 0x000087e9;
+define exported symbol HalSsiSetDeviceRoleRtl8195a = 0x00008861;
+define exported symbol HalSsiSetRxFifoThresholdLevelRtl8195a = 0x000088c9;
+define exported symbol HalSsiSetTxFifoThresholdLevelRtl8195a = 0x00008941;
+define exported symbol HalSsiReadRtl8195a = 0x000089b9;
+define exported symbol HalSsiGetRxFifoLevelRtl8195a = 0x00008a2d;
+define exported symbol HalSsiGetTxFifoLevelRtl8195a = 0x00008aa5;
+define exported symbol HalSsiGetStatusRtl8195a = 0x00008b1d;
+define exported symbol HalSsiWriteableRtl8195a = 0x00008b91;
+define exported symbol HalSsiReadableRtl8195a = 0x00008c09;
+define exported symbol HalSsiBusyRtl8195a = 0x00008c81;
+define exported symbol HalSsiReadInterruptRtl8195a = 0x00008cf9;
+define exported symbol HalSsiWriteInterruptRtl8195a = 0x00008efd;
+define exported symbol HalSsiSetSlaveEnableRegisterRtl8195a = 0x00009009;
+define exported symbol HalSsiGetInterruptStatusRtl8195a = 0x000090d9;
+define exported symbol HalSsiInterruptEnableRtl8195a = 0x0000914d;
+define exported symbol HalSsiInterruptDisableRtl8195a = 0x00009299;
+define exported symbol HalSsiGetRawInterruptStatusRtl8195a = 0x000093e9;
+define exported symbol HalSsiGetSlaveEnableRegisterRtl8195a = 0x0000945d;
+define exported symbol HalSsiInitRtl8195a = 0x000094d1;
+define exported symbol _SsiReadInterrupt = 0x00009ba5;
+define exported symbol _SsiWriteInterrupt = 0x00009db1;
+define exported symbol _SsiIrqHandle = 0x00009eb1;
+define exported symbol HalI2CWrite32 = 0x0000a061;
+define exported symbol HalI2CRead32 = 0x0000a09d;
+define exported symbol HalI2CDeInit8195a = 0x0000a0dd;
+define exported symbol HalI2CSendRtl8195a = 0x0000a1f1;
+define exported symbol HalI2CReceiveRtl8195a = 0x0000a25d;
+define exported symbol HalI2CEnableRtl8195a = 0x0000a271;
+define exported symbol HalI2CIntrCtrl8195a = 0x0000a389;
+define exported symbol HalI2CReadRegRtl8195a = 0x0000a3a1;
+define exported symbol HalI2CWriteRegRtl8195a = 0x0000a3b1;
+define exported symbol HalI2CSetCLKRtl8195a = 0x0000a3c5;
+define exported symbol HalI2CMassSendRtl8195a = 0x0000a6e9;
+define exported symbol HalI2CClrIntrRtl8195a = 0x0000a749;
+define exported symbol HalI2CClrAllIntrRtl8195a = 0x0000a761;
+define exported symbol HalI2CInit8195a = 0x0000a775;
+define exported symbol HalI2CDMACtrl8195a = 0x0000aa31;
+define exported symbol RtkI2CIoCtrl = 0x0000aa61;
+define exported symbol RtkI2CPowerCtrl = 0x0000aa65;
+define exported symbol HalI2COpInit = 0x0000aa69;
+define exported symbol I2CIsTimeout = 0x0000ac65;
+define exported symbol I2CTXGDMAISRHandle = 0x0000b435;
+define exported symbol I2CRXGDMAISRHandle = 0x0000b4c1;
+define exported symbol RtkI2CIrqInit = 0x0000b54d;
+define exported symbol RtkI2CIrqDeInit = 0x0000b611;
+define exported symbol RtkI2CPinMuxInit = 0x0000b675;
+define exported symbol RtkI2CPinMuxDeInit = 0x0000b7c9;
+define exported symbol RtkI2CDMAInit = 0x0000b955;
+define exported symbol RtkI2CInit = 0x0000bc95;
+define exported symbol RtkI2CDMADeInit = 0x0000bdad;
+define exported symbol RtkI2CDeInit = 0x0000be4d;
+define exported symbol RtkI2CSendUserAddr = 0x0000bee5;
+define exported symbol RtkI2CSend = 0x0000c07d;
+define exported symbol RtkI2CLoadDefault = 0x0000ce51;
+define exported symbol RtkSalI2COpInit = 0x0000cf21;
+define exported symbol HalI2SWrite32 = 0x0000cf65;
+define exported symbol HalI2SRead32 = 0x0000cf85;
+define exported symbol HalI2SDeInitRtl8195a = 0x0000cfa9;
+define exported symbol HalI2STxRtl8195a = 0x0000cfc9;
+define exported symbol HalI2SRxRtl8195a = 0x0000d011;
+define exported symbol HalI2SEnableRtl8195a = 0x0000d05d;
+define exported symbol HalI2SIntrCtrlRtl8195a = 0x0000d0b1;
+define exported symbol HalI2SReadRegRtl8195a = 0x0000d0d1;
+define exported symbol HalI2SClrIntrRtl8195a = 0x0000d0dd;
+define exported symbol HalI2SClrAllIntrRtl8195a = 0x0000d0fd;
+define exported symbol HalI2SInitRtl8195a = 0x0000d11d;
+define exported symbol GPIO_GetIPPinName_8195a = 0x0000d2e5;
+define exported symbol GPIO_GetChipPinName_8195a = 0x0000d331;
+define exported symbol GPIO_PullCtrl_8195a = 0x0000d39d;
+define exported symbol GPIO_FuncOn_8195a = 0x0000d421;
+define exported symbol GPIO_FuncOff_8195a = 0x0000d481;
+define exported symbol GPIO_Int_Mask_8195a = 0x0000d4e9;
+define exported symbol GPIO_Int_SetType_8195a = 0x0000d511;
+define exported symbol HAL_GPIO_IrqHandler_8195a = 0x0000d5fd;
+define exported symbol HAL_GPIO_MbedIrqHandler_8195a = 0x0000d645;
+define exported symbol HAL_GPIO_UserIrqHandler_8195a = 0x0000d6a1;
+define exported symbol HAL_GPIO_IntCtrl_8195a = 0x0000d6cd;
+define exported symbol HAL_GPIO_Init_8195a = 0x0000d805;
+define exported symbol HAL_GPIO_DeInit_8195a = 0x0000dac1;
+define exported symbol HAL_GPIO_ReadPin_8195a = 0x0000dbd1;
+define exported symbol HAL_GPIO_WritePin_8195a = 0x0000dc91;
+define exported symbol HAL_GPIO_RegIrq_8195a = 0x0000ddad;
+define exported symbol HAL_GPIO_UnRegIrq_8195a = 0x0000ddf5;
+define exported symbol HAL_GPIO_UserRegIrq_8195a = 0x0000de15;
+define exported symbol HAL_GPIO_UserUnRegIrq_8195a = 0x0000def9;
+define exported symbol HAL_GPIO_MaskIrq_8195a = 0x0000dfc1;
+define exported symbol HAL_GPIO_UnMaskIrq_8195a = 0x0000e061;
+define exported symbol HAL_GPIO_IntDebounce_8195a = 0x0000e101;
+define exported symbol HAL_GPIO_GetIPPinName_8195a = 0x0000e1c1;
+define exported symbol HAL_GPIO_PullCtrl_8195a = 0x0000e1c9;
+define exported symbol DumpForOneBytes = 0x0000e259;
+define exported symbol CmdRomHelp = 0x0000e419;
+define exported symbol CmdWriteWord = 0x0000e491;
+define exported symbol CmdDumpHelfWord = 0x0000e505;
+define exported symbol CmdDumpWord = 0x0000e5f1;
+define exported symbol CmdDumpByte = 0x0000e6f5;
+define exported symbol CmdSpiFlashTool = 0x0000e751;
+define exported symbol GetRomCmdNum = 0x0000e7a9;
+define exported symbol CmdWriteByte = 0x0000e7ad;
+define exported symbol Isspace = 0x0000e7ed;
+define exported symbol Strtoul = 0x0000e801;
+define exported symbol ArrayInitialize = 0x0000e8b1;
+define exported symbol GetArgc = 0x0000e8c9;
+define exported symbol GetArgv = 0x0000e8f9;
+define exported symbol UartLogCmdExecute = 0x0000e95d;
+define exported symbol UartLogShowBackSpace = 0x0000e9fd;
+define exported symbol UartLogRecallOldCmd = 0x0000ea39;
+define exported symbol UartLogHistoryCmd = 0x0000ea71;
+define exported symbol UartLogCmdChk = 0x0000eadd;
+define exported symbol UartLogIrqHandle = 0x0000ebf5;
+define exported symbol RtlConsolInit = 0x0000ecc5;
+define exported symbol RtlConsolTaskRom = 0x0000ed49;
+define exported symbol RtlExitConsol = 0x0000ed79;
+define exported symbol RtlConsolRom = 0x0000edcd;
+define exported symbol HalTimerOpInit = 0x0000ee0d;
+define exported symbol HalTimerIrq2To7Handle = 0x0000ee59;
+define exported symbol HalGetTimerIdRtl8195a = 0x0000ef09;
+define exported symbol HalTimerInitRtl8195a = 0x0000ef3d;
+define exported symbol HalTimerDisRtl8195a = 0x0000f069;
+define exported symbol HalTimerEnRtl8195a = 0x0000f089;
+define exported symbol HalTimerReadCountRtl8195a = 0x0000f0a9;
+define exported symbol HalTimerIrqClearRtl8195a = 0x0000f0bd;
+define exported symbol HalTimerDumpRegRtl8195a = 0x0000f0d1;
+define exported symbol VSprintf = 0x0000f129;
+define exported symbol DiagPrintf = 0x0000f39d;
+define exported symbol DiagSPrintf = 0x0000f3b9;
+define exported symbol DiagSnPrintf = 0x0000f3d1;
+define exported symbol prvDiagPrintf = 0x0000f3ed;
+define exported symbol prvDiagSPrintf = 0x0000f40d;
+define exported symbol _memcmp = 0x0000f429;
+define exported symbol __memcmp = 0x0000f429;
+define exported symbol _memcpy = 0x0000f465;
+define exported symbol __memcpy = 0x0000f465;
+define exported symbol _memset = 0x0000f511;
+define exported symbol __memset = 0x0000f511;
+define exported symbol Rand = 0x0000f585;
+define exported symbol _strncpy = 0x0000f60d;
+define exported symbol __strncpy = 0x0000f60d;
+define exported symbol _strcpy = 0x0000f629;
+define exported symbol __strcpy = 0x0000f629;
+define exported symbol prvStrCpy = 0x0000f639;
+define exported symbol _strlen = 0x0000f651;
+define exported symbol __strlen = 0x0000f651;
+define exported symbol _strnlen = 0x0000f669;
+define exported symbol __strnlen = 0x0000f669;
+define exported symbol prvStrLen = 0x0000f699;
+define exported symbol _strcmp = 0x0000f6b1;
+define exported symbol __strcmp = 0x0000f6b1;
+define exported symbol _strncmp = 0x0000f6d1;
+define exported symbol __strncmp = 0x0000f6d1;
+define exported symbol prvStrCmp = 0x0000f719;
+define exported symbol StrUpr = 0x0000f749;
+define exported symbol prvAtoi = 0x0000f769;
+define exported symbol prvStrStr = 0x0000f7bd;
+define exported symbol _strsep = 0x0000f7d5;
+define exported symbol __strsep = 0x0000f7d5;
+define exported symbol skip_spaces = 0x0000f815;
+define exported symbol skip_atoi = 0x0000f831;
+define exported symbol _parse_integer_fixup_radix = 0x0000f869;
+define exported symbol _parse_integer = 0x0000f8bd;
+define exported symbol __strtoull = 0x0000f915;
+define exported symbol __strtoll = 0x0000f945;
+define exported symbol __strtoul = 0x0000f965;
+define exported symbol __strtol = 0x0000f96d;
+define exported symbol simple_strtoull = 0x0000f915;
+define exported symbol simple_strtoll = 0x0000f945;
+define exported symbol simple_strtoul = 0x0000f965;
+define exported symbol simple_strtol = 0x0000f96d;
+define exported symbol __vsscanf = 0x0000f985;
+define exported symbol __sscanf = 0x0000ff71;
+define exported symbol div_u64 = 0x0000ff91;
+define exported symbol div_s64 = 0x0000ff99;
+define exported symbol div_u64_rem = 0x0000ffa1;
+define exported symbol div_s64_rem = 0x0000ffb1;
+define exported symbol __strpbrk = 0x0000ffc1;
+define exported symbol __strchr = 0x0000ffed;
+define exported symbol aes_set_key = 0x00010005;
+define exported symbol aes_encrypt = 0x000103d1;
+define exported symbol aes_decrypt = 0x000114a5;
+define exported symbol AES_WRAP = 0x000125c9;
+define exported symbol AES_UnWRAP = 0x00012701;
+define exported symbol crc32_get = 0x00012861;
+define exported symbol arc4_byte = 0x00012895;
+define exported symbol rt_arc4_init = 0x000128bd;
+define exported symbol rt_arc4_crypt = 0x00012901;
+define exported symbol rt_md5_init = 0x000131c1;
+define exported symbol rt_md5_append = 0x000131f5;
+define exported symbol rt_md5_final = 0x0001327d;
+define exported symbol rt_md5_hmac = 0x000132d5;
+define exported symbol rtw_get_bit_value_from_ieee_value = 0x00013449;
+define exported symbol rtw_is_cckrates_included = 0x00013475;
+define exported symbol rtw_is_cckratesonly_included = 0x000134b5;
+define exported symbol rtw_check_network_type = 0x000134dd;
+define exported symbol rtw_set_fixed_ie = 0x0001350d;
+define exported symbol rtw_set_ie = 0x0001352d;
+define exported symbol rtw_get_ie = 0x0001355d;
+define exported symbol rtw_set_supported_rate = 0x00013591;
+define exported symbol rtw_get_rateset_len = 0x00013611;
+define exported symbol rtw_get_wpa_ie = 0x0001362d;
+define exported symbol rtw_get_wpa2_ie = 0x000136c9;
+define exported symbol rtw_get_wpa_cipher_suite = 0x00013701;
+define exported symbol rtw_get_wpa2_cipher_suite = 0x00013769;
+define exported symbol rtw_parse_wpa_ie = 0x000137d1;
+define exported symbol rtw_parse_wpa2_ie = 0x000138ad;
+define exported symbol rtw_get_sec_ie = 0x00013965;
+define exported symbol rtw_get_wps_ie = 0x00013a15;
+define exported symbol rtw_get_wps_attr = 0x00013a99;
+define exported symbol rtw_get_wps_attr_content = 0x00013b49;
+define exported symbol rtw_ieee802_11_parse_elems = 0x00013b91;
+define exported symbol str_2char2num = 0x00013d9d;
+define exported symbol key_2char2num = 0x00013db9;
+define exported symbol convert_ip_addr = 0x00013dd1;
+define exported symbol rom_psk_PasswordHash = 0x00013e9d;
+define exported symbol rom_psk_CalcGTK = 0x00013ed5;
+define exported symbol rom_psk_CalcPTK = 0x00013f69;
+define exported symbol wep_80211_encrypt = 0x00014295;
+define exported symbol wep_80211_decrypt = 0x000142f5;
+define exported symbol tkip_micappendbyte = 0x00014389;
+define exported symbol rtw_secmicsetkey = 0x000143d9;
+define exported symbol rtw_secmicappend = 0x00014419;
+define exported symbol rtw_secgetmic = 0x00014435;
+define exported symbol rtw_seccalctkipmic = 0x0001449d;
+define exported symbol tkip_phase1 = 0x000145a5;
+define exported symbol tkip_phase2 = 0x00014725;
+define exported symbol tkip_80211_encrypt = 0x00014941;
+define exported symbol tkip_80211_decrypt = 0x000149d5;
+define exported symbol aes1_encrypt = 0x00014a8d;
+define exported symbol aesccmp_construct_mic_iv = 0x00014c65;
+define exported symbol aesccmp_construct_mic_header1 = 0x00014ccd;
+define exported symbol aesccmp_construct_mic_header2 = 0x00014d21;
+define exported symbol aesccmp_construct_ctr_preload = 0x00014db5;
+define exported symbol aes_80211_encrypt = 0x00014e29;
+define exported symbol aes_80211_decrypt = 0x000151ad;
+define exported symbol _sha1_process_message_block = 0x000155b9;
+define exported symbol _sha1_pad_message = 0x00015749;
+define exported symbol rt_sha1_init = 0x000157e5;
+define exported symbol rt_sha1_update = 0x00015831;
+define exported symbol rt_sha1_finish = 0x000158a9;
+define exported symbol rt_hmac_sha1 = 0x00015909;
+define exported symbol rom_aes_128_cbc_encrypt = 0x00015a65;
+define exported symbol rom_aes_128_cbc_decrypt = 0x00015ae1;
+define exported symbol rom_rijndaelKeySetupEnc = 0x00015b5d;
+define exported symbol rom_aes_decrypt_init = 0x00015c39;
+define exported symbol rom_aes_internal_decrypt = 0x00015d15;
+define exported symbol rom_aes_decrypt_deinit = 0x00016071;
+define exported symbol rom_aes_encrypt_init = 0x00016085;
+define exported symbol rom_aes_internal_encrypt = 0x0001609d;
+define exported symbol rom_aes_encrypt_deinit = 0x00016451;
+define exported symbol bignum_init = 0x00017b35;
+define exported symbol bignum_deinit = 0x00017b61;
+define exported symbol bignum_get_unsigned_bin_len = 0x00017b81;
+define exported symbol bignum_get_unsigned_bin = 0x00017b85;
+define exported symbol bignum_set_unsigned_bin = 0x00017c21;
+define exported symbol bignum_cmp = 0x00017cd1;
+define exported symbol bignum_cmp_d = 0x00017cd5;
+define exported symbol bignum_add = 0x00017cfd;
+define exported symbol bignum_sub = 0x00017d0d;
+define exported symbol bignum_mul = 0x00017d1d;
+define exported symbol bignum_exptmod = 0x00017d2d;
+define exported symbol WPS_realloc = 0x00017d51;
+define exported symbol os_zalloc = 0x00017d99;
+define exported symbol rom_hmac_sha256_vector = 0x00017dc1;
+define exported symbol rom_hmac_sha256 = 0x00017ebd;
+define exported symbol rom_sha256_vector = 0x00018009;
+define exported symbol phy_CalculateBitShift = 0x00018221;
+define exported symbol PHY_SetBBReg_8195A = 0x00018239;
+define exported symbol PHY_QueryBBReg_8195A = 0x00018279;
+define exported symbol ROM_odm_QueryRxPwrPercentage = 0x0001829d;
+define exported symbol ROM_odm_EVMdbToPercentage = 0x000182bd;
+define exported symbol ROM_odm_SignalScaleMapping_8195A = 0x000182e5;
+define exported symbol ROM_odm_FalseAlarmCounterStatistics = 0x000183cd;
+define exported symbol ROM_odm_SetEDCCAThreshold = 0x00018721;
+define exported symbol ROM_odm_SetTRxMux = 0x00018749;
+define exported symbol ROM_odm_SetCrystalCap = 0x00018771;
+define exported symbol ROM_odm_GetDefaultCrytaltalCap = 0x000187d5;
+define exported symbol ROM_ODM_CfoTrackingReset = 0x000187e9;
+define exported symbol ROM_odm_CfoTrackingFlow = 0x00018811;
+define exported symbol curve25519_donna = 0x0001965d;
+define exported symbol aes_test_alignment_detection = 0x0001a391;
+define exported symbol aes_mode_reset = 0x0001a3ed;
+define exported symbol aes_ecb_encrypt = 0x0001a3f9;
+define exported symbol aes_ecb_decrypt = 0x0001a431;
+define exported symbol aes_cbc_encrypt = 0x0001a469;
+define exported symbol aes_cbc_decrypt = 0x0001a579;
+define exported symbol aes_cfb_encrypt = 0x0001a701;
+define exported symbol aes_cfb_decrypt = 0x0001a9e5;
+define exported symbol aes_ofb_crypt = 0x0001acc9;
+define exported symbol aes_ctr_crypt = 0x0001af7d;
+define exported symbol aes_encrypt_key128 = 0x0001b289;
+define exported symbol aes_encrypt_key192 = 0x0001b2a5;
+define exported symbol aes_encrypt_key256 = 0x0001b2c1;
+define exported symbol aes_encrypt_key = 0x0001b2e1;
+define exported symbol aes_decrypt_key128 = 0x0001b351;
+define exported symbol aes_decrypt_key192 = 0x0001b36d;
+define exported symbol aes_decrypt_key256 = 0x0001b389;
+define exported symbol aes_decrypt_key = 0x0001b3a9;
+define exported symbol aes_init = 0x0001b419;
+define exported symbol CRYPTO_chacha_20 = 0x0001b41d;
+define exported symbol CRYPTO_poly1305_init = 0x0001bc25;
+define exported symbol CRYPTO_poly1305_update = 0x0001bd09;
+define exported symbol CRYPTO_poly1305_finish = 0x0001bd8d;
+define exported symbol rom_sha512_starts = 0x0001ceb5;
+define exported symbol rom_sha512_update = 0x0001d009;
+define exported symbol rom_sha512_finish = 0x0001d011;
+define exported symbol rom_sha512 = 0x0001d261;
+define exported symbol rom_sha512_hmac_starts = 0x0001d299;
+define exported symbol rom_sha512_hmac_update = 0x0001d35d;
+define exported symbol rom_sha512_hmac_finish = 0x0001d365;
+define exported symbol rom_sha512_hmac_reset = 0x0001d3b5;
+define exported symbol rom_sha512_hmac = 0x0001d3d1;
+define exported symbol rom_sha512_hkdf = 0x0001d40d;
+define exported symbol rom_ed25519_gen_keypair = 0x0001d501;
+define exported symbol rom_ed25519_gen_signature = 0x0001d505;
+define exported symbol rom_ed25519_verify_signature = 0x0001d51d;
+define exported symbol rom_ed25519_crypto_sign_seed_keypair = 0x0001d521;
+define exported symbol rom_ed25519_crypto_sign_detached = 0x0001d579;
+define exported symbol rom_ed25519_crypto_sign_verify_detached = 0x0001d655;
+define exported symbol rom_ed25519_ge_double_scalarmult_vartime = 0x0001f86d;
+define exported symbol rom_ed25519_ge_frombytes_negate_vartime = 0x0001fc35;
+define exported symbol rom_ed25519_ge_p3_tobytes = 0x000207d5;
+define exported symbol rom_ed25519_ge_scalarmult_base = 0x00020821;
+define exported symbol rom_ed25519_ge_tobytes = 0x000209e1;
+define exported symbol rom_ed25519_sc_muladd = 0x00020a2d;
+define exported symbol rom_ed25519_sc_reduce = 0x0002603d;
+define exported symbol __rtl_memchr_v1_00 = 0x00028a4d;
+define exported symbol __rtl_memcmp_v1_00 = 0x00028ae1;
+define exported symbol __rtl_memcpy_v1_00 = 0x00028b49;
+define exported symbol __rtl_memmove_v1_00 = 0x00028bed;
+define exported symbol __rtl_memset_v1_00 = 0x00028cb5;
+define exported symbol __rtl_strcat_v1_00 = 0x00028d49;
+define exported symbol __rtl_strchr_v1_00 = 0x00028d91;
+define exported symbol __rtl_strcmp_v1_00 = 0x00028e55;
+define exported symbol __rtl_strcpy_v1_00 = 0x00028ec9;
+define exported symbol __rtl_strlen_v1_00 = 0x00028f15;
+define exported symbol __rtl_strncat_v1_00 = 0x00028f69;
+define exported symbol __rtl_strncmp_v1_00 = 0x00028fc5;
+define exported symbol __rtl_strncpy_v1_00 = 0x0002907d;
+define exported symbol __rtl_strstr_v1_00 = 0x000293cd;
+define exported symbol __rtl_strsep_v1_00 = 0x0002960d;
+define exported symbol __rtl_strtok_v1_00 = 0x00029619;
+define exported symbol __rtl__strtok_r_v1_00 = 0x0002962d;
+define exported symbol __rtl_strtok_r_v1_00 = 0x00029691;
+define exported symbol __rtl_close_v1_00 = 0x00029699;
+define exported symbol __rtl_fstat_v1_00 = 0x000296ad;
+define exported symbol __rtl_isatty_v1_00 = 0x000296c1;
+define exported symbol __rtl_lseek_v1_00 = 0x000296d5;
+define exported symbol __rtl_open_v1_00 = 0x000296e9;
+define exported symbol __rtl_read_v1_00 = 0x000296fd;
+define exported symbol __rtl_write_v1_00 = 0x00029711;
+define exported symbol __rtl_sbrk_v1_00 = 0x00029725;
+define exported symbol __rtl_ltoa_v1_00 = 0x000297bd;
+define exported symbol __rtl_ultoa_v1_00 = 0x00029855;
+define exported symbol __rtl_dtoi_v1_00 = 0x000298c5;
+define exported symbol __rtl_dtoi64_v1_00 = 0x00029945;
+define exported symbol __rtl_dtoui_v1_00 = 0x000299dd;
+define exported symbol __rtl_ftol_v1_00 = 0x000299e5;
+define exported symbol __rtl_itof_v1_00 = 0x00029a51;
+define exported symbol __rtl_itod_v1_00 = 0x00029ae9;
+define exported symbol __rtl_i64tod_v1_00 = 0x00029b79;
+define exported symbol __rtl_uitod_v1_00 = 0x00029c55;
+define exported symbol __rtl_ftod_v1_00 = 0x00029d2d;
+define exported symbol __rtl_dtof_v1_00 = 0x00029de9;
+define exported symbol __rtl_uitof_v1_00 = 0x00029e89;
+define exported symbol __rtl_fadd_v1_00 = 0x00029f65;
+define exported symbol __rtl_fsub_v1_00 = 0x0002a261;
+define exported symbol __rtl_fmul_v1_00 = 0x0002a559;
+define exported symbol __rtl_fdiv_v1_00 = 0x0002a695;
+define exported symbol __rtl_dadd_v1_00 = 0x0002a825;
+define exported symbol __rtl_dsub_v1_00 = 0x0002aed9;
+define exported symbol __rtl_dmul_v1_00 = 0x0002b555;
+define exported symbol __rtl_ddiv_v1_00 = 0x0002b8ad;
+define exported symbol __rtl_dcmpeq_v1_00 = 0x0002be4d;
+define exported symbol __rtl_dcmplt_v1_00 = 0x0002bebd;
+define exported symbol __rtl_dcmpgt_v1_00 = 0x0002bf51;
+define exported symbol __rtl_dcmple_v1_00 = 0x0002c049;
+define exported symbol __rtl_fcmplt_v1_00 = 0x0002c139;
+define exported symbol __rtl_fcmpgt_v1_00 = 0x0002c195;
+define exported symbol __rtl_cos_f32_v1_00 = 0x0002c229;
+define exported symbol __rtl_sin_f32_v1_00 = 0x0002c435;
+define exported symbol __rtl_fabs_v1_00 = 0x0002c639;
+define exported symbol __rtl_fabsf_v1_00 = 0x0002c641;
+define exported symbol __rtl_dtoa_r_v1_00 = 0x0002c77d;
+define exported symbol __rom_mallocr_init_v1_00 = 0x0002d7d1;
+define exported symbol __rtl_free_r_v1_00 = 0x0002d841;
+define exported symbol __rtl_malloc_r_v1_00 = 0x0002da31;
+define exported symbol __rtl_realloc_r_v1_00 = 0x0002df55;
+define exported symbol __rtl_memalign_r_v1_00 = 0x0002e331;
+define exported symbol __rtl_valloc_r_v1_00 = 0x0002e421;
+define exported symbol __rtl_pvalloc_r_v1_00 = 0x0002e42d;
+define exported symbol __rtl_calloc_r_v1_00 = 0x0002e441;
+define exported symbol __rtl_cfree_r_v1_00 = 0x0002e4a9;
+define exported symbol __rtl_Balloc_v1_00 = 0x0002e515;
+define exported symbol __rtl_Bfree_v1_00 = 0x0002e571;
+define exported symbol __rtl_i2b_v1_00 = 0x0002e585;
+define exported symbol __rtl_multadd_v1_00 = 0x0002e599;
+define exported symbol __rtl_mult_v1_00 = 0x0002e629;
+define exported symbol __rtl_pow5mult_v1_00 = 0x0002e769;
+define exported symbol __rtl_hi0bits_v1_00 = 0x0002e809;
+define exported symbol __rtl_d2b_v1_00 = 0x0002e845;
+define exported symbol __rtl_lshift_v1_00 = 0x0002e901;
+define exported symbol __rtl_cmp_v1_00 = 0x0002e9bd;
+define exported symbol __rtl_diff_v1_00 = 0x0002ea01;
+define exported symbol __rtl_sread_v1_00 = 0x0002eae9;
+define exported symbol __rtl_seofread_v1_00 = 0x0002eb39;
+define exported symbol __rtl_swrite_v1_00 = 0x0002eb3d;
+define exported symbol __rtl_sseek_v1_00 = 0x0002ebc1;
+define exported symbol __rtl_sclose_v1_00 = 0x0002ec11;
+define exported symbol __rtl_sbrk_r_v1_00 = 0x0002ec41;
+define exported symbol __rtl_fflush_r_v1_00 = 0x0002ef8d;
+define exported symbol __rtl_vfprintf_r_v1_00 = 0x0002f661;
+define exported symbol __rtl_fpclassifyd = 0x00030c15;
+define exported symbol CpkClkTbl = 0x00030c68;
+define exported symbol ROM_IMG1_VALID_PATTEN = 0x00030c80;
+define exported symbol SpicCalibrationPattern = 0x00030c88;
+define exported symbol SpicInitCPUCLK = 0x00030c98;
+define exported symbol BAUDRATE = 0x00030ca8;
+define exported symbol OVSR = 0x00030d1c;
+define exported symbol DIV = 0x00030d90;
+define exported symbol OVSR_ADJ = 0x00030e04;
+define exported symbol __AES_rcon = 0x00030e78;
+define exported symbol __AES_Te4 = 0x00030ea0;
+define exported symbol I2CDmaChNo = 0x000312a0;
+define exported symbol _GPIO_PinMap_Chip2IP_8195a = 0x000312b4;
+define exported symbol _GPIO_PinMap_PullCtrl_8195a = 0x0003136c;
+define exported symbol _GPIO_SWPORT_DDR_TBL = 0x00031594;
+define exported symbol _GPIO_EXT_PORT_TBL = 0x00031598;
+define exported symbol _GPIO_SWPORT_DR_TBL = 0x0003159c;
+define exported symbol UartLogRomCmdTable = 0x000316a0;
+define exported symbol _HalRuartOp = 0x00031700;
+define exported symbol _HalGdmaOp = 0x00031760;
+define exported symbol RTW_WPA_OUI_TYPE = 0x0003540c;
+define exported symbol WPA_CIPHER_SUITE_NONE = 0x00035410;
+define exported symbol WPA_CIPHER_SUITE_WEP40 = 0x00035414;
+define exported symbol WPA_CIPHER_SUITE_TKIP = 0x00035418;
+define exported symbol WPA_CIPHER_SUITE_CCMP = 0x0003541c;
+define exported symbol WPA_CIPHER_SUITE_WEP104 = 0x00035420;
+define exported symbol RSN_CIPHER_SUITE_NONE = 0x00035424;
+define exported symbol RSN_CIPHER_SUITE_WEP40 = 0x00035428;
+define exported symbol RSN_CIPHER_SUITE_TKIP = 0x0003542c;
+define exported symbol RSN_CIPHER_SUITE_CCMP = 0x00035430;
+define exported symbol RSN_CIPHER_SUITE_WEP104 = 0x00035434;
+define exported symbol RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x00035444;
+define exported symbol RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x00035448;
+define exported symbol RSN_VERSION_BSD = 0x0003544c;
+define exported symbol rom_wps_Te0 = 0x00035988;
+define exported symbol rom_wps_rcons = 0x00035d88;
+define exported symbol rom_wps_Td4s = 0x00035d94;
+define exported symbol rom_wps_Td0 = 0x00035e94;
+define exported symbol __rom_b_cut_end__ = 0x0004467c;
+define exported symbol __rom_c_cut_text_start__ = 0x0004467c;
+define exported symbol HalInitPlatformLogUartV02 = 0x0004467d;
+define exported symbol HalReInitPlatformLogUartV02 = 0x0004471d;
+define exported symbol HalInitPlatformTimerV02 = 0x00044755;
+define exported symbol HalShowBuildInfoV02 = 0x000447cd;
+define exported symbol SpicReleaseDeepPowerDownFlashRtl8195A = 0x00044831;
+define exported symbol HalSpiInitV02 = 0x0004488d;
+define exported symbol HalBootFlowV02 = 0x00044a29;
+define exported symbol HalInitialROMCodeGlobalVarV02 = 0x00044ae5;
+define exported symbol HalResetVsrV02 = 0x00044b41;
+define exported symbol HalI2CSendRtl8195aV02 = 0x00044ce1;
+define exported symbol HalI2CSetCLKRtl8195aV02 = 0x00044d59;
+define exported symbol RtkI2CSendV02 = 0x0004508d;
+define exported symbol RtkI2CReceiveV02 = 0x000459a1;
+define exported symbol HalI2COpInitV02 = 0x000461ed;
+define exported symbol I2CISRHandleV02 = 0x000463e9;
+define exported symbol RtkSalI2COpInitV02 = 0x00046be1;
+define exported symbol SpicLoadInitParaFromClockRtl8195AV02 = 0x00046c25;
+define exported symbol SpiFlashAppV02 = 0x00046c85;
+define exported symbol SpicInitRtl8195AV02 = 0x00046dc5;
+define exported symbol SpicEraseFlashRtl8195AV02 = 0x00046ea1;
+define exported symbol HalTimerIrq2To7HandleV02 = 0x00046f5d;
+define exported symbol HalTimerIrqRegisterRtl8195aV02 = 0x00046fe1;
+define exported symbol HalTimerInitRtl8195aV02 = 0x0004706d;
+define exported symbol HalTimerReadCountRtl8195aV02 = 0x000471b5;
+define exported symbol HalTimerReLoadRtl8195aV02 = 0x000471d1;
+define exported symbol HalTimerIrqUnRegisterRtl8195aV02 = 0x0004722d;
+define exported symbol HalTimerDeInitRtl8195aV02 = 0x000472c1;
+define exported symbol HalTimerOpInitV02 = 0x000472f9;
+define exported symbol GPIO_LockV02 = 0x00047345;
+define exported symbol GPIO_UnLockV02 = 0x00047379;
+define exported symbol GPIO_Int_Clear_8195aV02 = 0x000473a5;
+define exported symbol HAL_GPIO_IntCtrl_8195aV02 = 0x000473b5;
+define exported symbol FindElementIndexV02 = 0x00047541;
+define exported symbol HalRuartInitRtl8195aV02 = 0x0004756d;
+define exported symbol DramInit_rom = 0x00047619;
+define exported symbol ChangeRandSeed_rom = 0x00047979;
+define exported symbol Sdr_Rand2_rom = 0x00047985;
+define exported symbol MemTest_rom = 0x000479dd;
+define exported symbol SdrCalibration_rom = 0x00047a45;
+define exported symbol SdrControllerInit_rom = 0x00047d99;
+define exported symbol SDIO_EnterCritical = 0x00047e39;
+define exported symbol SDIO_ExitCritical = 0x00047e85;
+define exported symbol SDIO_IRQ_Handler_Rom = 0x00047ec5;
+define exported symbol SDIO_Interrupt_Init_Rom = 0x00047f31;
+define exported symbol SDIO_Device_Init_Rom = 0x00047f81;
+define exported symbol SDIO_Interrupt_DeInit_Rom = 0x00048215;
+define exported symbol SDIO_Device_DeInit_Rom = 0x00048255;
+define exported symbol SDIO_Enable_Interrupt_Rom = 0x00048281;
+define exported symbol SDIO_Disable_Interrupt_Rom = 0x000482a1;
+define exported symbol SDIO_Clear_ISR_Rom = 0x000482c1;
+define exported symbol SDIO_Alloc_Rx_Pkt_Rom = 0x000482d9;
+define exported symbol SDIO_Free_Rx_Pkt_Rom = 0x00048331;
+define exported symbol SDIO_Recycle_Rx_BD_Rom = 0x00048355;
+define exported symbol SDIO_RX_IRQ_Handler_BH_Rom = 0x000484f1;
+define exported symbol SDIO_RxTask_Rom = 0x0004851d;
+define exported symbol SDIO_Process_H2C_IOMsg_Rom = 0x0004856d;
+define exported symbol SDIO_Send_C2H_IOMsg_Rom = 0x0004859d;
+define exported symbol SDIO_Process_RPWM_Rom = 0x000485b5;
+define exported symbol SDIO_Reset_Cmd_Rom = 0x000485e9;
+define exported symbol SDIO_Rx_Data_Transaction_Rom = 0x00048611;
+define exported symbol SDIO_Send_C2H_PktMsg_Rom = 0x00048829;
+define exported symbol SDIO_Register_Tx_Callback_Rom = 0x000488f5;
+define exported symbol SDIO_ReadMem_Rom = 0x000488fd;
+define exported symbol SDIO_WriteMem_Rom = 0x000489a9;
+define exported symbol SDIO_SetMem_Rom = 0x00048a69;
+define exported symbol SDIO_TX_Pkt_Handle_Rom = 0x00048b29;
+define exported symbol SDIO_TX_FIFO_DataReady_Rom = 0x00048c69;
+define exported symbol SDIO_IRQ_Handler_BH_Rom = 0x00048d95;
+define exported symbol SDIO_TxTask_Rom = 0x00048e9d;
+define exported symbol SDIO_TaskUp_Rom = 0x00048eed;
+define exported symbol SDIO_Boot_Up = 0x00048f55;
+define exported symbol __rom_c_cut_text_end__ = 0x00049070;
+define exported symbol __rom_c_cut_rodata_start__ = 0x00049070;
+define exported symbol BAUDRATE_v02 = 0x00049070;
+define exported symbol OVSR_v02 = 0x000490fc;
+define exported symbol DIV_v02 = 0x00049188;
+define exported symbol OVSR_ADJ_v02 = 0x00049214;
+define exported symbol SdrDramInfo_rom = 0x000492a0;
+define exported symbol SdrDramTiming_rom = 0x000492b4;
+define exported symbol NewVectorTable = 0x10000000;
+define exported symbol UserIrqFunTable = 0x10000100;
+define exported symbol UserIrqDataTable = 0x10000200;
+define exported symbol __rom_bss_start__ = 0x10000300;
+define exported symbol CfgSysDebugWarn = 0x10000300;
+define exported symbol CfgSysDebugInfo = 0x10000304;
+define exported symbol CfgSysDebugErr = 0x10000308;
+define exported symbol ConfigDebugWarn = 0x1000030c;
+define exported symbol ConfigDebugInfo = 0x10000310;
+define exported symbol ConfigDebugErr = 0x10000314;
+define exported symbol HalTimerOp = 0x10000318;
+define exported symbol GPIOState = 0x10000334;
+define exported symbol gTimerRecord = 0x1000034c;
+define exported symbol SSI_DBG_CONFIG = 0x10000350;
+define exported symbol _pHAL_Gpio_Adapter = 0x10000354;
+define exported symbol Timer2To7VectorTable = 0x10000358;
+define exported symbol rom_wlan_ram_map = 0x100006d4;
+define exported symbol ROMInfo = 0x10000720;
+define exported symbol rom_libgloss_ram_map = 0x10000760;
+define exported symbol __rtl_errno = 0x10000bc4;
+define exported symbol __rom_bss_end__ = 0x10000bc8;
+define exported symbol __ram_table_start__ = 0x10000bc8;
+define exported symbol _rtl_impure_ptr = 0x10001c60;
+define exported symbol FalseAlmCnt = 0x100006d4;
+define exported symbol DM_CfoTrack = 0x1000072c;
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a_startup.S b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a_startup.S
new file mode 100644
index 00000000000..4e00f35c3db
--- /dev/null
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a_startup.S
@@ -0,0 +1,31 @@
+;
+; Copyright (c) 2017 Realtek Semiconductor Corp.
+;
+; Licensed under the Apache License, Version 2.0 (the "License");
+; you may not use this file except in compliance with the License.
+; You may obtain a copy of the License at
+;
+;     http://www.apache.org/licenses/LICENSE-2.0
+;
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an "AS IS" BASIS,
+; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
+
+    MODULE  ?cstartup
+
+    SECTION .text:CODE:NOROOT:REORDER(2)
+    EXTERN  CSTACK$$Limit
+    EXTERN  PLAT_Init
+
+    ; Default image 2 entry
+    THUMB
+    PUBWEAK PLAT_Start
+
+PLAT_Start
+    LDR     SP, =CSTACK$$Limit
+    LDR     R0, =PLAT_Init
+    BX      R0
+
+    END
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_compiler.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_compiler.h
index 52e74b491fd..3d0dee3dcb5 100644
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_compiler.h
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_compiler.h
@@ -29,6 +29,12 @@
 #define __romcall
 #define __longcall
 
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+
+#ifndef __longcall
+#define __longcall
+#endif
+
 #elif defined(__CC_ARM)
 
 #ifndef __longcall
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c
index 50ea18db163..1882a7c7472 100644
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c
@@ -29,7 +29,6 @@
 #if defined(__CC_ARM) || \
     (defined (__ARMCC_VERSION) && __ARMCC_VERSION >= 6010050)
 
-extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
 extern uint8_t Image$$RW_IRAM2$$ZI$$Base[];
 extern uint8_t Image$$RW_IRAM2$$ZI$$Limit[];
 extern uint8_t Image$$TCM_OVERLAY$$ZI$$Base[];
@@ -42,27 +41,32 @@ extern uint8_t Image$$RW_DRAM2$$ZI$$Limit[];
 #define __bss_dtcm_end__   Image$$TCM_OVERLAY$$ZI$$Limit
 #define __bss_dram_start__ Image$$RW_DRAM2$$ZI$$Base
 #define __bss_dram_end__   Image$$RW_DRAM2$$ZI$$Limit
-#define __stackp           Image$$ARM_LIB_STACK$$ZI$$Limit
 
 #elif defined (__ICCARM__)
 
-#pragma section=".ram.bss"
+#pragma section=".bss.sram"
+#pragma section=".bss.dtcm"
+#pragma section=".bss.dram"
 
-extern uint32_t CSTACK$$Limit;
-uint8_t *__bss_start__;
-uint8_t *__bss_end__;
+uint8_t *__bss_sram_start__;
+uint8_t *__bss_sram_end__;
+uint8_t *__bss_dtcm_start__;
+uint8_t *__bss_dtcm_end__;
+uint8_t *__bss_dram_start__;
+uint8_t *__bss_dram_end__;
 
 void __iar_data_init_app(void)
 {
-    __bss_start__ = (uint8_t *)__section_begin(".ram.bss");
-    __bss_end__   = (uint8_t *)__section_end(".ram.bss");
+    __bss_sram_start__ = (uint8_t *)__section_begin(".bss.sram");
+    __bss_sram_end__   = (uint8_t *)__section_end(".bss.sram");
+    __bss_dtcm_start__ = (uint8_t *)__section_begin(".bss.dtcm");
+    __bss_dtcm_end__   = (uint8_t *)__section_end(".bss.dtcm");
+    __bss_dram_start__ = (uint8_t *)__section_begin(".bss.dram");
+    __bss_dram_end__   = (uint8_t *)__section_end(".bss.dram");
 }
-#define __stackp           CSTACK$$Limit
 
 #else
 
-extern uint32_t __StackTop;
-extern uint32_t __StackLimit;
 extern uint8_t __bss_sram_start__[];
 extern uint8_t __bss_sram_end__[];
 extern uint8_t __bss_dtcm_start__[];
@@ -70,7 +74,6 @@ extern uint8_t __bss_dtcm_end__[];
 extern uint8_t __bss_dram_start__[];
 extern uint8_t __bss_dram_end__[];
 
-#define __stackp           __StackTop
 #endif
 
 extern VECTOR_Func NewVectorTable[];
@@ -175,30 +178,23 @@ void TRAP_HardFaultHandler_Patch(void)
 
 extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n);
 // Image2 Entry Function
-void PLAT_Start(void)
+void PLAT_Init(void)
 {
     uint32_t val;
 
-#if defined (__ICCARM__)
-    __iar_data_init_app();
+    // Overwrite vector table
+    NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler;
+#if defined ( __ICCARM__ )
+    NewVectorTable[3] = (VECTOR_Func) TRAP_HardFaultHandler_Patch;
 #endif
 
     // Clear RAM BSS
 #if defined (__ICCARM__)
-    __rtl_memset_v1_00((void *)__bss_start__, 0, __bss_end__ - __bss_start__);
-#else
+    __iar_data_init_app();
+#endif
     __rtl_memset_v1_00((void *)__bss_sram_start__, 0, __bss_sram_end__ - __bss_sram_start__);
     __rtl_memset_v1_00((void *)__bss_dtcm_start__, 0, __bss_dtcm_end__ - __bss_dtcm_start__);
     __rtl_memset_v1_00((void *)__bss_dram_start__, 0, __bss_dram_end__ - __bss_dram_start__);
-#endif
-
-    // Set MSP
-    __set_MSP((uint32_t)&__stackp - 0x100);
-    // Overwrite vector table
-    NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler;
-#if defined ( __ICCARM__ )
-    NewVectorTable[3] = (VECTOR_Func) TRAP_HardFaultHandler_Patch;
-#endif
 
     extern HAL_TIMER_OP_EXT HalTimerOpExt;
     __rtl_memset_v1_00((void *)&HalTimerOpExt, 0, sizeof(HalTimerOpExt));
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_rom.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_rom.h
deleted file mode 100644
index 8b55a13e17c..00000000000
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_rom.h
+++ /dev/null
@@ -1,748 +0,0 @@
-/*
- * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-SECTIONS
-{
-    __vectors_table = 0x0;
-    Reset_Handler = 0x101;
-    NMI_Handler = 0x109;
-    HardFault_Handler = 0x10d;
-    MemManage_Handler = 0x121;
-    BusFault_Handler = 0x125;
-    UsageFault_Handler = 0x129;
-    HalLogUartInit = 0x201;
-    HalSerialPutcRtl8195a = 0x2d9;
-    HalSerialGetcRtl8195a = 0x309;
-    HalSerialGetIsrEnRegRtl8195a = 0x329;
-    HalSerialSetIrqEnRegRtl8195a = 0x335;
-    HalCpuClkConfig = 0x341;
-    HalGetCpuClk = 0x355;
-    HalRomInfo = 0x39d;
-    HalGetRomInfo = 0x3b5;
-    HalResetVsr = 0x3c5;
-    HalDelayUs = 0x899;
-    HalNMIHandler = 0x8e1;
-    HalHardFaultHandler = 0x911;
-    HalMemManageHandler = 0xc09;
-    HalBusFaultHandler = 0xc39;
-    HalUsageFaultHandler = 0xc69;
-    HalUart0PinCtrlRtl8195A = 0xcfd;
-    HalUart1PinCtrlRtl8195A = 0xdc9;
-    HalUart2PinCtrlRtl8195A = 0xe9d;
-    HalSPI0PinCtrlRtl8195A = 0xf75;
-    HalSPI1PinCtrlRtl8195A = 0x1015;
-    HalSPI2PinCtrlRtl8195A = 0x10e5;
-    HalSPI0MCSPinCtrlRtl8195A = 0x11b5;
-    HalI2C0PinCtrlRtl8195A = 0x1275;
-    HalI2C1PinCtrlRtl8195A = 0x1381;
-    HalI2C2PinCtrlRtl8195A = 0x1459;
-    HalI2C3PinCtrlRtl8195A = 0x1529;
-    HalI2S0PinCtrlRtl8195A = 0x1639;
-    HalI2S1PinCtrlRtl8195A = 0x176d;
-    HalPCM0PinCtrlRtl8195A = 0x1845;
-    HalPCM1PinCtrlRtl8195A = 0x1949;
-    HalSDIODPinCtrlRtl8195A = 0x1a1d;
-    HalSDIOHPinCtrlRtl8195A = 0x1a6d;
-    HalMIIPinCtrlRtl8195A = 0x1ab9;
-    HalWLLEDPinCtrlRtl8195A = 0x1b51;
-    HalWLANT0PinCtrlRtl8195A = 0x1c0d;
-    HalWLANT1PinCtrlRtl8195A = 0x1c61;
-    HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5;
-    HalWLBTCMDPinCtrlRtl8195A = 0x1d05;
-    HalNFCPinCtrlRtl8195A = 0x1d59;
-    HalPWM0PinCtrlRtl8195A = 0x1da9;
-    HalPWM1PinCtrlRtl8195A = 0x1ead;
-    HalPWM2PinCtrlRtl8195A = 0x1fb5;
-    HalPWM3PinCtrlRtl8195A = 0x20b1;
-    HalETE0PinCtrlRtl8195A = 0x21b9;
-    HalETE1PinCtrlRtl8195A = 0x22c1;
-    HalETE2PinCtrlRtl8195A = 0x23c9;
-    HalETE3PinCtrlRtl8195A = 0x24d1;
-    HalEGTIMPinCtrlRtl8195A = 0x25d9;
-    HalSPIFlashPinCtrlRtl8195A = 0x2679;
-    HalSDRPinCtrlRtl8195A = 0x2725;
-    HalJTAGPinCtrlRtl8195A = 0x280d;
-    HalTRACEPinCtrlRtl8195A = 0x2861;
-    HalLOGUartPinCtrlRtl8195A = 0x28b9;
-    HalLOGUartIRPinCtrlRtl8195A = 0x291d;
-    HalSICPinCtrlRtl8195A = 0x2981;
-    HalEEPROMPinCtrlRtl8195A = 0x29d9;
-    HalDEBUGPinCtrlRtl8195A = 0x2a31;
-    HalPinCtrlRtl8195A = 0x2b39;
-    SpicRxCmdRtl8195A = 0x2e5d;
-    SpicWaitBusyDoneRtl8195A = 0x2ea5;
-    SpicGetFlashStatusRtl8195A = 0x2eb5;
-    SpicWaitWipDoneRtl8195A = 0x2f55;
-    SpicTxCmdRtl8195A = 0x2f6d;
-    SpicSetFlashStatusRtl8195A = 0x2fc1;
-    SpicCmpDataForCalibrationRtl8195A = 0x3049;
-    SpicLoadInitParaFromClockRtl8195A = 0x3081;
-    SpicInitRtl8195A = 0x30e5;
-    SpicEraseFlashRtl8195A = 0x31bd;
-    SpiFlashApp = 0x3279;
-    HalPeripheralIntrHandle = 0x33b5;
-    HalSysOnIntrHandle = 0x3439;
-    HalWdgIntrHandle = 0x3485;
-    HalTimer0IntrHandle = 0x34d5;
-    HalTimer1IntrHandle = 0x3525;
-    HalI2C3IntrHandle = 0x3575;
-    HalTimer2To7IntrHandle = 0x35c5;
-    HalSpi0IntrHandle = 0x3615;
-    HalGpioIntrHandle = 0x3665;
-    HalUart0IntrHandle = 0x36b5;
-    HalSpiFlashIntrHandle = 0x3705;
-    HalUsbOtgIntrHandle = 0x3755;
-    HalSdioHostIntrHandle = 0x37a5;
-    HalI2s0OrPcm0IntrHandle = 0x37f5;
-    HalI2s1OrPcm1IntrHandle = 0x3845;
-    HalWlDmaIntrHandle = 0x3895;
-    HalWlProtocolIntrHandle = 0x38e5;
-    HalCryptoIntrHandle = 0x3935;
-    HalGmacIntrHandle = 0x3985;
-    HalGdma0Ch0IntrHandle = 0x39d5;
-    HalGdma0Ch1IntrHandle = 0x3a25;
-    HalGdma0Ch2IntrHandle = 0x3a75;
-    HalGdma0Ch3IntrHandle = 0x3ac5;
-    HalGdma0Ch4IntrHandle = 0x3b15;
-    HalGdma0Ch5IntrHandle = 0x3b65;
-    HalGdma1Ch0IntrHandle = 0x3bb5;
-    HalGdma1Ch1IntrHandle = 0x3c05;
-    HalGdma1Ch2IntrHandle = 0x3c55;
-    HalGdma1Ch3IntrHandle = 0x3ca5;
-    HalGdma1Ch4IntrHandle = 0x3cf5;
-    HalGdma1Ch5IntrHandle = 0x3d45;
-    HalSdioDeviceIntrHandle = 0x3d95;
-    VectorTableInitRtl8195A = 0x3de5;
-    VectorTableInitForOSRtl8195A = 0x4019;
-    VectorIrqRegisterRtl8195A = 0x4029;
-    VectorIrqUnRegisterRtl8195A = 0x4091;
-    VectorIrqEnRtl8195A = 0x40f1;
-    VectorIrqDisRtl8195A = 0x418d;
-    _UartRxDmaIrqHandle = 0x422d;
-    HalRuartPutCRtl8195a = 0x4281;
-    HalRuartGetCRtl8195a = 0x429d;
-    HalRuartRTSCtrlRtl8195a = 0x42bd;
-    HalRuartGetDebugValueRtl8195a = 0x42e1;
-    HalRuartGetIMRRtl8195a = 0x43e1;
-    HalRuartSetIMRRtl8195a = 0x442d;
-    _UartIrqHandle = 0x4465;
-    HalRuartDmaInitRtl8195a = 0x4681;
-    HalRuartIntDisableRtl8195a = 0x4845;
-    HalRuartDeInitRtl8195a = 0x4855;
-    HalRuartIntEnableRtl8195a = 0x4985;
-    _UartTxDmaIrqHandle = 0x4995;
-    HalRuartRegIrqRtl8195a = 0x49d1;
-    HalRuartAdapterLoadDefRtl8195a = 0x4a4d;
-    HalRuartTxGdmaLoadDefRtl8195a = 0x4add;
-    HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9;
-    RuartLock = 0x4cc9;
-    RuartUnLock = 0x4ced;
-    HalRuartIntSendRtl8195a = 0x4d09;
-    HalRuartDmaSendRtl8195a = 0x4e35;
-    HalRuartStopSendRtl8195a = 0x4f89;
-    HalRuartIntRecvRtl8195a = 0x504d;
-    HalRuartDmaRecvRtl8195a = 0x51ad;
-    HalRuartStopRecvRtl8195a = 0x52cd;
-    RuartIsTimeout = 0x5385;
-    HalRuartSendRtl8195a = 0x53b1;
-    HalRuartRecvRtl8195a = 0x5599;
-    RuartResetRxFifoRtl8195a = 0x5751;
-    HalRuartResetRxFifoRtl8195a = 0x5775;
-    HalRuartInitRtl8195a = 0x5829;
-    HalGdmaOnOffRtl8195a = 0x5df1;
-    HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d;
-    HalGdmaChEnRtl8195a = 0x5e51;
-    HalGdmaChDisRtl8195a = 0x5e6d;
-    HalGdamChInitRtl8195a = 0x5e91;
-    HalGdmaChSetingRtl8195a = 0x5ebd;
-    HalGdmaChIsrCleanRtl8195a = 0x6419;
-    HalGdmaChCleanAutoSrcRtl8195a = 0x64a1;
-    HalGdmaChCleanAutoDstRtl8195a = 0x6501;
-    HalEFUSEPowerSwitch8195AROM = 0x6561;
-    HALEFUSEOneByteReadROM = 0x65f9;
-    HALEFUSEOneByteWriteROM = 0x6699;
-    __rtl_memcmpb_v1_00 = 0x681d;
-    __rtl_random_v1_00 = 0x6861;
-    __rtl_align_to_be32_v1_00 = 0x6881;
-    __rtl_memsetw_v1_00 = 0x6899;
-    __rtl_memsetb_v1_00 = 0x68ad;
-    __rtl_memcpyw_v1_00 = 0x68bd;
-    __rtl_memcpyb_v1_00 = 0x68dd;
-    __rtl_memDump_v1_00 = 0x68f5;
-    __rtl_AES_set_encrypt_key = 0x6901;
-    __rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11;
-    __rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95;
-    __rtl_cryptoEngine_init_v1_00 = 0x6ea9;
-    __rtl_cryptoEngine_exit_v1_00 = 0x7055;
-    __rtl_cryptoEngine_reset_v1_00 = 0x70b1;
-    __rtl_cryptoEngine_v1_00 = 0x70ed;
-    __rtl_crypto_cipher_init_v1_00 = 0x7c69;
-    __rtl_crypto_cipher_encrypt_v1_00 = 0x7c89;
-    __rtl_crypto_cipher_decrypt_v1_00 = 0x7cad;
-    HalSsiPinmuxEnableRtl8195a = 0x7cd5;
-    HalSsiEnableRtl8195a = 0x7e45;
-    HalSsiDisableRtl8195a = 0x7ef9;
-    HalSsiLoadSettingRtl8195a = 0x7fad;
-    HalSsiSetInterruptMaskRtl8195a = 0x8521;
-    HalSsiGetInterruptMaskRtl8195a = 0x85c9;
-    HalSsiSetSclkPolarityRtl8195a = 0x863d;
-    HalSsiSetSclkPhaseRtl8195a = 0x8715;
-    HalSsiWriteRtl8195a = 0x87e9;
-    HalSsiSetDeviceRoleRtl8195a = 0x8861;
-    HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9;
-    HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941;
-    HalSsiReadRtl8195a = 0x89b9;
-    HalSsiGetRxFifoLevelRtl8195a = 0x8a2d;
-    HalSsiGetTxFifoLevelRtl8195a = 0x8aa5;
-    HalSsiGetStatusRtl8195a = 0x8b1d;
-    HalSsiWriteableRtl8195a = 0x8b91;
-    HalSsiReadableRtl8195a = 0x8c09;
-    HalSsiBusyRtl8195a = 0x8c81;
-    HalSsiReadInterruptRtl8195a = 0x8cf9;
-    HalSsiWriteInterruptRtl8195a = 0x8efd;
-    HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009;
-    HalSsiGetInterruptStatusRtl8195a = 0x90d9;
-    HalSsiInterruptEnableRtl8195a = 0x914d;
-    HalSsiInterruptDisableRtl8195a = 0x9299;
-    HalSsiGetRawInterruptStatusRtl8195a = 0x93e9;
-    HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d;
-    HalSsiInitRtl8195a = 0x94d1;
-    _SsiReadInterrupt = 0x9ba5;
-    _SsiWriteInterrupt = 0x9db1;
-    _SsiIrqHandle = 0x9eb1;
-    HalI2CWrite32 = 0xa061;
-    HalI2CRead32 = 0xa09d;
-    HalI2CDeInit8195a = 0xa0dd;
-    HalI2CSendRtl8195a = 0xa1f1;
-    HalI2CReceiveRtl8195a = 0xa25d;
-    HalI2CEnableRtl8195a = 0xa271;
-    HalI2CIntrCtrl8195a = 0xa389;
-    HalI2CReadRegRtl8195a = 0xa3a1;
-    HalI2CWriteRegRtl8195a = 0xa3b1;
-    HalI2CSetCLKRtl8195a = 0xa3c5;
-    HalI2CMassSendRtl8195a = 0xa6e9;
-    HalI2CClrIntrRtl8195a = 0xa749;
-    HalI2CClrAllIntrRtl8195a = 0xa761;
-    HalI2CInit8195a = 0xa775;
-    HalI2CDMACtrl8195a = 0xaa31;
-    RtkI2CIoCtrl = 0xaa61;
-    RtkI2CPowerCtrl = 0xaa65;
-    HalI2COpInit = 0xaa69;
-    I2CIsTimeout = 0xac65;
-    I2CTXGDMAISRHandle = 0xb435;
-    I2CRXGDMAISRHandle = 0xb4c1;
-    RtkI2CIrqInit = 0xb54d;
-    RtkI2CIrqDeInit = 0xb611;
-    RtkI2CPinMuxInit = 0xb675;
-    RtkI2CPinMuxDeInit = 0xb7c9;
-    RtkI2CDMAInit = 0xb955;
-    RtkI2CInit = 0xbc95;
-    RtkI2CDMADeInit = 0xbdad;
-    RtkI2CDeInit = 0xbe4d;
-    RtkI2CSendUserAddr = 0xbee5;
-    RtkI2CSend = 0xc07d;
-    RtkI2CLoadDefault = 0xce51;
-    RtkSalI2COpInit = 0xcf21;
-    HalI2SWrite32 = 0xcf65;
-    HalI2SRead32 = 0xcf85;
-    HalI2SDeInitRtl8195a = 0xcfa9;
-    HalI2STxRtl8195a = 0xcfc9;
-    HalI2SRxRtl8195a = 0xd011;
-    HalI2SEnableRtl8195a = 0xd05d;
-    HalI2SIntrCtrlRtl8195a = 0xd0b1;
-    HalI2SReadRegRtl8195a = 0xd0d1;
-    HalI2SClrIntrRtl8195a = 0xd0dd;
-    HalI2SClrAllIntrRtl8195a = 0xd0fd;
-    HalI2SInitRtl8195a = 0xd11d;
-    GPIO_GetIPPinName_8195a = 0xd2e5;
-    GPIO_GetChipPinName_8195a = 0xd331;
-    GPIO_PullCtrl_8195a = 0xd39d;
-    GPIO_FuncOn_8195a = 0xd421;
-    GPIO_FuncOff_8195a = 0xd481;
-    GPIO_Int_Mask_8195a = 0xd4e9;
-    GPIO_Int_SetType_8195a = 0xd511;
-    HAL_GPIO_IrqHandler_8195a = 0xd5fd;
-    HAL_GPIO_MbedIrqHandler_8195a = 0xd645;
-    HAL_GPIO_UserIrqHandler_8195a = 0xd6a1;
-    HAL_GPIO_IntCtrl_8195a = 0xd6cd;
-    HAL_GPIO_Init_8195a = 0xd805;
-    HAL_GPIO_DeInit_8195a = 0xdac1;
-    HAL_GPIO_ReadPin_8195a = 0xdbd1;
-    HAL_GPIO_WritePin_8195a = 0xdc91;
-    HAL_GPIO_RegIrq_8195a = 0xddad;
-    HAL_GPIO_UnRegIrq_8195a = 0xddf5;
-    HAL_GPIO_UserRegIrq_8195a = 0xde15;
-    HAL_GPIO_UserUnRegIrq_8195a = 0xdef9;
-    HAL_GPIO_MaskIrq_8195a = 0xdfc1;
-    HAL_GPIO_UnMaskIrq_8195a = 0xe061;
-    HAL_GPIO_IntDebounce_8195a = 0xe101;
-    HAL_GPIO_GetIPPinName_8195a = 0xe1c1;
-    HAL_GPIO_PullCtrl_8195a = 0xe1c9;
-    DumpForOneBytes = 0xe259;
-    CmdRomHelp = 0xe419;
-    CmdWriteWord = 0xe491;
-    CmdDumpHelfWord = 0xe505;
-    CmdDumpWord = 0xe5f1;
-    CmdDumpByte = 0xe6f5;
-    CmdSpiFlashTool = 0xe751;
-    GetRomCmdNum = 0xe7a9;
-    CmdWriteByte = 0xe7ad;
-    Isspace = 0xe7ed;
-    Strtoul = 0xe801;
-    ArrayInitialize = 0xe8b1;
-    GetArgc = 0xe8c9;
-    GetArgv = 0xe8f9;
-    UartLogCmdExecute = 0xe95d;
-    UartLogShowBackSpace = 0xe9fd;
-    UartLogRecallOldCmd = 0xea39;
-    UartLogHistoryCmd = 0xea71;
-    UartLogCmdChk = 0xeadd;
-    UartLogIrqHandle = 0xebf5;
-    RtlConsolInit = 0xecc5;
-    RtlConsolTaskRom = 0xed49;
-    RtlExitConsol = 0xed79;
-    RtlConsolRom = 0xedcd;
-    HalTimerOpInit = 0xee0d;
-    HalTimerIrq2To7Handle = 0xee59;
-    HalGetTimerIdRtl8195a = 0xef09;
-    HalTimerInitRtl8195a = 0xef3d;
-    HalTimerDisRtl8195a = 0xf069;
-    HalTimerEnRtl8195a = 0xf089;
-    HalTimerReadCountRtl8195a = 0xf0a9;
-    HalTimerIrqClearRtl8195a = 0xf0bd;
-    HalTimerDumpRegRtl8195a = 0xf0d1;
-    VSprintf = 0xf129;
-    DiagPrintf = 0xf39d;
-    DiagSPrintf = 0xf3b9;
-    DiagSnPrintf = 0xf3d1;
-    prvDiagPrintf = 0xf3ed;
-    prvDiagSPrintf = 0xf40d;
-    _memcmp = 0xf429;
-    _memcpy = 0xf465;
-    _memset = 0xf511;
-    Rand = 0xf585;
-    _strncpy = 0xf60d;
-    _strcpy = 0xf629;
-    prvStrCpy = 0xf639;
-    _strlen = 0xf651;
-    _strnlen = 0xf669;
-    prvStrLen = 0xf699;
-    _strcmp = 0xf6b1;
-    _strncmp = 0xf6d1;
-    prvStrCmp = 0xf719;
-    StrUpr = 0xf749;
-    prvAtoi = 0xf769;
-    prvStrStr = 0xf7bd;
-    _strsep = 0xf7d5;
-    skip_spaces = 0xf815;
-    skip_atoi = 0xf831;
-    _parse_integer_fixup_radix = 0xf869;
-    _parse_integer = 0xf8bd;
-    simple_strtoull = 0xf915;
-    simple_strtoll = 0xf945;
-    simple_strtoul = 0xf965;
-    simple_strtol = 0xf96d;
-    _vsscanf = 0xf985;
-    _sscanf = 0xff71;
-    div_u64 = 0xff91;
-    div_s64 = 0xff99;
-    div_u64_rem = 0xffa1;
-    div_s64_rem = 0xffb1;
-    _strpbrk = 0xffc1;
-    _strchr = 0xffed;
-    aes_set_key = 0x10005;
-    aes_encrypt = 0x103d1;
-    aes_decrypt = 0x114a5;
-    AES_WRAP = 0x125c9;
-    AES_UnWRAP = 0x12701;
-    crc32_get = 0x12861;
-    arc4_byte = 0x12895;
-    rt_arc4_init = 0x128bd;
-    rt_arc4_crypt = 0x12901;
-    rt_md5_init = 0x131c1;
-    rt_md5_append = 0x131f5;
-    rt_md5_final = 0x1327d;
-    rt_md5_hmac = 0x132d5;
-    rtw_get_bit_value_from_ieee_value = 0x13449;
-    rtw_is_cckrates_included = 0x13475;
-    rtw_is_cckratesonly_included = 0x134b5;
-    rtw_check_network_type = 0x134dd;
-    rtw_set_fixed_ie = 0x1350d;
-    rtw_set_ie = 0x1352d;
-    rtw_get_ie = 0x1355d;
-    rtw_set_supported_rate = 0x13591;
-    rtw_get_rateset_len = 0x13611;
-    rtw_get_wpa_ie = 0x1362d;
-    rtw_get_wpa2_ie = 0x136c9;
-    rtw_get_wpa_cipher_suite = 0x13701;
-    rtw_get_wpa2_cipher_suite = 0x13769;
-    rtw_parse_wpa_ie = 0x137d1;
-    rtw_parse_wpa2_ie = 0x138ad;
-    rtw_get_sec_ie = 0x13965;
-    rtw_get_wps_ie = 0x13a15;
-    rtw_get_wps_attr = 0x13a99;
-    rtw_get_wps_attr_content = 0x13b49;
-    rtw_ieee802_11_parse_elems = 0x13b91;
-    str_2char2num = 0x13d9d;
-    key_2char2num = 0x13db9;
-    convert_ip_addr = 0x13dd1;
-    rom_psk_PasswordHash = 0x13e9d;
-    rom_psk_CalcGTK = 0x13ed5;
-    rom_psk_CalcPTK = 0x13f69;
-    wep_80211_encrypt = 0x14295;
-    wep_80211_decrypt = 0x142f5;
-    tkip_micappendbyte = 0x14389;
-    rtw_secmicsetkey = 0x143d9;
-    rtw_secmicappend = 0x14419;
-    rtw_secgetmic = 0x14435;
-    rtw_seccalctkipmic = 0x1449d;
-    tkip_phase1 = 0x145a5;
-    tkip_phase2 = 0x14725;
-    tkip_80211_encrypt = 0x14941;
-    tkip_80211_decrypt = 0x149d5;
-    aes1_encrypt = 0x14a8d;
-    aesccmp_construct_mic_iv = 0x14c65;
-    aesccmp_construct_mic_header1 = 0x14ccd;
-    aesccmp_construct_mic_header2 = 0x14d21;
-    aesccmp_construct_ctr_preload = 0x14db5;
-    aes_80211_encrypt = 0x14e29;
-    aes_80211_decrypt = 0x151ad;
-    _sha1_process_message_block = 0x155b9;
-    _sha1_pad_message = 0x15749;
-    rt_sha1_init = 0x157e5;
-    rt_sha1_update = 0x15831;
-    rt_sha1_finish = 0x158a9;
-    rt_hmac_sha1 = 0x15909;
-    rom_aes_128_cbc_encrypt = 0x15a65;
-    rom_aes_128_cbc_decrypt = 0x15ae1;
-    rom_rijndaelKeySetupEnc = 0x15b5d;
-    rom_aes_decrypt_init = 0x15c39;
-    rom_aes_internal_decrypt = 0x15d15;
-    rom_aes_decrypt_deinit = 0x16071;
-    rom_aes_encrypt_init = 0x16085;
-    rom_aes_internal_encrypt = 0x1609d;
-    rom_aes_encrypt_deinit = 0x16451;
-    bignum_init = 0x17b35;
-    bignum_deinit = 0x17b61;
-    bignum_get_unsigned_bin_len = 0x17b81;
-    bignum_get_unsigned_bin = 0x17b85;
-    bignum_set_unsigned_bin = 0x17c21;
-    bignum_cmp = 0x17cd1;
-    bignum_cmp_d = 0x17cd5;
-    bignum_add = 0x17cfd;
-    bignum_sub = 0x17d0d;
-    bignum_mul = 0x17d1d;
-    bignum_exptmod = 0x17d2d;
-    WPS_realloc = 0x17d51;
-    os_zalloc = 0x17d99;
-    rom_hmac_sha256_vector = 0x17dc1;
-    rom_hmac_sha256 = 0x17ebd;
-    rom_sha256_vector = 0x18009;
-    phy_CalculateBitShift = 0x18221;
-    PHY_SetBBReg_8195A = 0x18239;
-    PHY_QueryBBReg_8195A = 0x18279;
-    ROM_odm_QueryRxPwrPercentage = 0x1829d;
-    ROM_odm_EVMdbToPercentage = 0x182bd;
-    ROM_odm_SignalScaleMapping_8195A = 0x182e5;
-    ROM_odm_FalseAlarmCounterStatistics = 0x183cd;
-    ROM_odm_SetEDCCAThreshold = 0x18721;
-    ROM_odm_SetTRxMux = 0x18749;
-    ROM_odm_SetCrystalCap = 0x18771;
-    ROM_odm_GetDefaultCrytaltalCap = 0x187d5;
-    ROM_ODM_CfoTrackingReset = 0x187e9;
-    ROM_odm_CfoTrackingFlow = 0x18811;
-    curve25519_donna = 0x1965d;
-    aes_test_alignment_detection = 0x1a391;
-    aes_mode_reset = 0x1a3ed;
-    aes_ecb_encrypt = 0x1a3f9;
-    aes_ecb_decrypt = 0x1a431;
-    aes_cbc_encrypt = 0x1a469;
-    aes_cbc_decrypt = 0x1a579;
-    aes_cfb_encrypt = 0x1a701;
-    aes_cfb_decrypt = 0x1a9e5;
-    aes_ofb_crypt = 0x1acc9;
-    aes_ctr_crypt = 0x1af7d;
-    aes_encrypt_key128 = 0x1b289;
-    aes_encrypt_key192 = 0x1b2a5;
-    aes_encrypt_key256 = 0x1b2c1;
-    aes_encrypt_key = 0x1b2e1;
-    aes_decrypt_key128 = 0x1b351;
-    aes_decrypt_key192 = 0x1b36d;
-    aes_decrypt_key256 = 0x1b389;
-    aes_decrypt_key = 0x1b3a9;
-    aes_init = 0x1b419;
-    CRYPTO_chacha_20 = 0x1b41d;
-    CRYPTO_poly1305_init = 0x1bc25;
-    CRYPTO_poly1305_update = 0x1bd09;
-    CRYPTO_poly1305_finish = 0x1bd8d;
-    rom_sha512_starts = 0x1ceb5;
-    rom_sha512_update = 0x1d009;
-    rom_sha512_finish = 0x1d011;
-    rom_sha512 = 0x1d261;
-    rom_sha512_hmac_starts = 0x1d299;
-    rom_sha512_hmac_update = 0x1d35d;
-    rom_sha512_hmac_finish = 0x1d365;
-    rom_sha512_hmac_reset = 0x1d3b5;
-    rom_sha512_hmac = 0x1d3d1;
-    rom_sha512_hkdf = 0x1d40d;
-    rom_ed25519_gen_keypair = 0x1d501;
-    rom_ed25519_gen_signature = 0x1d505;
-    rom_ed25519_verify_signature = 0x1d51d;
-    rom_ed25519_crypto_sign_seed_keypair = 0x1d521;
-    rom_ed25519_crypto_sign_detached = 0x1d579;
-    rom_ed25519_crypto_sign_verify_detached = 0x1d655;
-    rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d;
-    rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35;
-    rom_ed25519_ge_p3_tobytes = 0x207d5;
-    rom_ed25519_ge_scalarmult_base = 0x20821;
-    rom_ed25519_ge_tobytes = 0x209e1;
-    rom_ed25519_sc_muladd = 0x20a2d;
-    rom_ed25519_sc_reduce = 0x2603d;
-    __rtl_memchr_v1_00 = 0x28a4d;
-    __rtl_memcmp_v1_00 = 0x28ae1;
-    __rtl_memcpy_v1_00 = 0x28b49;
-    __rtl_memmove_v1_00 = 0x28bed;
-    __rtl_memset_v1_00 = 0x28cb5;
-    __rtl_strcat_v1_00 = 0x28d49;
-    __rtl_strchr_v1_00 = 0x28d91;
-    __rtl_strcmp_v1_00 = 0x28e55;
-    __rtl_strcpy_v1_00 = 0x28ec9;
-    __rtl_strlen_v1_00 = 0x28f15;
-    __rtl_strncat_v1_00 = 0x28f69;
-    __rtl_strncmp_v1_00 = 0x28fc5;
-    __rtl_strncpy_v1_00 = 0x2907d;
-    __rtl_strstr_v1_00 = 0x293cd;
-    __rtl_strsep_v1_00 = 0x2960d;
-    __rtl_strtok_v1_00 = 0x29619;
-    __rtl__strtok_r_v1_00 = 0x2962d;
-    __rtl_strtok_r_v1_00 = 0x29691;
-    __rtl_close_v1_00 = 0x29699;
-    __rtl_fstat_v1_00 = 0x296ad;
-    __rtl_isatty_v1_00 = 0x296c1;
-    __rtl_lseek_v1_00 = 0x296d5;
-    __rtl_open_v1_00 = 0x296e9;
-    __rtl_read_v1_00 = 0x296fd;
-    __rtl_write_v1_00 = 0x29711;
-    __rtl_sbrk_v1_00 = 0x29725;
-    __rtl_ltoa_v1_00 = 0x297bd;
-    __rtl_ultoa_v1_00 = 0x29855;
-    __rtl_dtoi_v1_00 = 0x298c5;
-    __rtl_dtoi64_v1_00 = 0x29945;
-    __rtl_dtoui_v1_00 = 0x299dd;
-    __rtl_ftol_v1_00 = 0x299e5;
-    __rtl_itof_v1_00 = 0x29a51;
-    __rtl_itod_v1_00 = 0x29ae9;
-    __rtl_i64tod_v1_00 = 0x29b79;
-    __rtl_uitod_v1_00 = 0x29c55;
-    __rtl_ftod_v1_00 = 0x29d2d;
-    __rtl_dtof_v1_00 = 0x29de9;
-    __rtl_uitof_v1_00 = 0x29e89;
-    __rtl_fadd_v1_00 = 0x29f65;
-    __rtl_fsub_v1_00 = 0x2a261;
-    __rtl_fmul_v1_00 = 0x2a559;
-    __rtl_fdiv_v1_00 = 0x2a695;
-    __rtl_dadd_v1_00 = 0x2a825;
-    __rtl_dsub_v1_00 = 0x2aed9;
-    __rtl_dmul_v1_00 = 0x2b555;
-    __rtl_ddiv_v1_00 = 0x2b8ad;
-    __rtl_dcmpeq_v1_00 = 0x2be4d;
-    __rtl_dcmplt_v1_00 = 0x2bebd;
-    __rtl_dcmpgt_v1_00 = 0x2bf51;
-    __rtl_dcmple_v1_00 = 0x2c049;
-    __rtl_fcmplt_v1_00 = 0x2c139;
-    __rtl_fcmpgt_v1_00 = 0x2c195;
-    __rtl_cos_f32_v1_00 = 0x2c229;
-    __rtl_sin_f32_v1_00 = 0x2c435;
-    __rtl_fabs_v1_00 = 0x2c639;
-    __rtl_fabsf_v1_00 = 0x2c641;
-    __rtl_dtoa_r_v1_00 = 0x2c77d;
-    __rom_mallocr_init_v1_00 = 0x2d7d1;
-    __rtl_free_r_v1_00 = 0x2d841;
-    __rtl_malloc_r_v1_00 = 0x2da31;
-    __rtl_realloc_r_v1_00 = 0x2df55;
-    __rtl_memalign_r_v1_00 = 0x2e331;
-    __rtl_valloc_r_v1_00 = 0x2e421;
-    __rtl_pvalloc_r_v1_00 = 0x2e42d;
-    __rtl_calloc_r_v1_00 = 0x2e441;
-    __rtl_cfree_r_v1_00 = 0x2e4a9;
-    __rtl_Balloc_v1_00 = 0x2e515;
-    __rtl_Bfree_v1_00 = 0x2e571;
-    __rtl_i2b_v1_00 = 0x2e585;
-    __rtl_multadd_v1_00 = 0x2e599;
-    __rtl_mult_v1_00 = 0x2e629;
-    __rtl_pow5mult_v1_00 = 0x2e769;
-    __rtl_hi0bits_v1_00 = 0x2e809;
-    __rtl_d2b_v1_00 = 0x2e845;
-    __rtl_lshift_v1_00 = 0x2e901;
-    __rtl_cmp_v1_00 = 0x2e9bd;
-    __rtl_diff_v1_00 = 0x2ea01;
-    __rtl_sread_v1_00 = 0x2eae9;
-    __rtl_seofread_v1_00 = 0x2eb39;
-    __rtl_swrite_v1_00 = 0x2eb3d;
-    __rtl_sseek_v1_00 = 0x2ebc1;
-    __rtl_sclose_v1_00 = 0x2ec11;
-    __rtl_sbrk_r_v1_00 = 0x2ec41;
-    __rtl_fflush_r_v1_00 = 0x2ef8d;
-    __rtl_vfprintf_r_v1_00 = 0x2f661;
-    __rtl_fpclassifyd = 0x30c15;
-    CpkClkTbl = 0x30c68;
-    ROM_IMG1_VALID_PATTEN = 0x30c80;
-    SpicCalibrationPattern = 0x30c88;
-    SpicInitCPUCLK = 0x30c98;
-    BAUDRATE = 0x30ca8;
-    OVSR = 0x30d1c;
-    DIV = 0x30d90;
-    OVSR_ADJ = 0x30e04;
-    __AES_rcon = 0x30e78;
-    __AES_Te4 = 0x30ea0;
-    I2CDmaChNo = 0x312a0;
-    _GPIO_PinMap_Chip2IP_8195a = 0x312b4;
-    _GPIO_PinMap_PullCtrl_8195a = 0x3136c;
-    _GPIO_SWPORT_DDR_TBL = 0x31594;
-    _GPIO_EXT_PORT_TBL = 0x31598;
-    _GPIO_SWPORT_DR_TBL = 0x3159c;
-    UartLogRomCmdTable = 0x316a0;
-    _HalRuartOp = 0x31700;
-    _HalGdmaOp = 0x31760;
-    RTW_WPA_OUI_TYPE = 0x3540c;
-    WPA_CIPHER_SUITE_NONE = 0x35410;
-    WPA_CIPHER_SUITE_WEP40 = 0x35414;
-    WPA_CIPHER_SUITE_TKIP = 0x35418;
-    WPA_CIPHER_SUITE_CCMP = 0x3541c;
-    WPA_CIPHER_SUITE_WEP104 = 0x35420;
-    RSN_CIPHER_SUITE_NONE = 0x35424;
-    RSN_CIPHER_SUITE_WEP40 = 0x35428;
-    RSN_CIPHER_SUITE_TKIP = 0x3542c;
-    RSN_CIPHER_SUITE_CCMP = 0x35430;
-    RSN_CIPHER_SUITE_WEP104 = 0x35434;
-    RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444;
-    RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448;
-    RSN_VERSION_BSD = 0x3544c;
-    rom_wps_Te0 = 0x35988;
-    rom_wps_rcons = 0x35d88;
-    rom_wps_Td4s = 0x35d94;
-    rom_wps_Td0 = 0x35e94;
-    __rom_b_cut_end__ = 0x4467c;
-    __rom_c_cut_text_start__ = 0x4467c;
-    HalInitPlatformLogUartV02 = 0x4467d;
-    HalReInitPlatformLogUartV02 = 0x4471d;
-    HalInitPlatformTimerV02 = 0x44755;
-    HalShowBuildInfoV02 = 0x447cd;
-    SpicReleaseDeepPowerDownFlashRtl8195A = 0x44831;
-    HalSpiInitV02 = 0x4488d;
-    HalBootFlowV02 = 0x44a29;
-    HalInitialROMCodeGlobalVarV02 = 0x44ae5;
-    HalResetVsrV02 = 0x44b41;
-    HalI2CSendRtl8195aV02 = 0x44ce1;
-    HalI2CSetCLKRtl8195aV02 = 0x44d59;
-    RtkI2CSendV02 = 0x4508d;
-    RtkI2CReceiveV02 = 0x459a1;
-    HalI2COpInitV02 = 0x461ed;
-    I2CISRHandleV02 = 0x463e9;
-    RtkSalI2COpInitV02 = 0x46be1;
-    SpicLoadInitParaFromClockRtl8195AV02 = 0x46c25;
-    SpiFlashAppV02 = 0x46c85;
-    SpicInitRtl8195AV02 = 0x46dc5;
-    SpicEraseFlashRtl8195AV02 = 0x46ea1;
-    HalTimerIrq2To7HandleV02 = 0x46f5d;
-    HalTimerIrqRegisterRtl8195aV02 = 0x46fe1;
-    HalTimerInitRtl8195aV02 = 0x4706d;
-    HalTimerReadCountRtl8195aV02 = 0x471b5;
-    HalTimerReLoadRtl8195aV02 = 0x471d1;
-    HalTimerIrqUnRegisterRtl8195aV02 = 0x4722d;
-    HalTimerDeInitRtl8195aV02 = 0x472c1;
-    HalTimerOpInitV02 = 0x472f9;
-    GPIO_LockV02 = 0x47345;
-    GPIO_UnLockV02 = 0x47379;
-    GPIO_Int_Clear_8195aV02 = 0x473a5;
-    HAL_GPIO_IntCtrl_8195aV02 = 0x473b5;
-    FindElementIndexV02 = 0x47541;
-    HalRuartInitRtl8195aV02 = 0x4756d;
-    DramInit_rom = 0x47619;
-    ChangeRandSeed_rom = 0x47979;
-    Sdr_Rand2_rom = 0x47985;
-    MemTest_rom = 0x479dd;
-    SdrCalibration_rom = 0x47a45;
-    SdrControllerInit_rom = 0x47d99;
-    SDIO_EnterCritical = 0x47e39;
-    SDIO_ExitCritical = 0x47e85;
-    SDIO_IRQ_Handler_Rom = 0x47ec5;
-    SDIO_Interrupt_Init_Rom = 0x47f31;
-    SDIO_Device_Init_Rom = 0x47f81;
-    SDIO_Interrupt_DeInit_Rom = 0x48215;
-    SDIO_Device_DeInit_Rom = 0x48255;
-    SDIO_Enable_Interrupt_Rom = 0x48281;
-    SDIO_Disable_Interrupt_Rom = 0x482a1;
-    SDIO_Clear_ISR_Rom = 0x482c1;
-    SDIO_Alloc_Rx_Pkt_Rom = 0x482d9;
-    SDIO_Free_Rx_Pkt_Rom = 0x48331;
-    SDIO_Recycle_Rx_BD_Rom = 0x48355;
-    SDIO_RX_IRQ_Handler_BH_Rom = 0x484f1;
-    SDIO_RxTask_Rom = 0x4851d;
-    SDIO_Process_H2C_IOMsg_Rom = 0x4856d;
-    SDIO_Send_C2H_IOMsg_Rom = 0x4859d;
-    SDIO_Process_RPWM_Rom = 0x485b5;
-    SDIO_Reset_Cmd_Rom = 0x485e9;
-    SDIO_Rx_Data_Transaction_Rom = 0x48611;
-    SDIO_Send_C2H_PktMsg_Rom = 0x48829;
-    SDIO_Register_Tx_Callback_Rom = 0x488f5;
-    SDIO_ReadMem_Rom = 0x488fd;
-    SDIO_WriteMem_Rom = 0x489a9;
-    SDIO_SetMem_Rom = 0x48a69;
-    SDIO_TX_Pkt_Handle_Rom = 0x48b29;
-    SDIO_TX_FIFO_DataReady_Rom = 0x48c69;
-    SDIO_IRQ_Handler_BH_Rom = 0x48d95;
-    SDIO_TxTask_Rom = 0x48e9d;
-    SDIO_TaskUp_Rom = 0x48eed;
-    SDIO_Boot_Up = 0x48f55;
-    __rom_c_cut_text_end__ = 0x49070;
-    __rom_c_cut_rodata_start__ = 0x49070;
-    BAUDRATE_v02 = 0x49070;
-    OVSR_v02 = 0x490fc;
-    DIV_v02 = 0x49188;
-    OVSR_ADJ_v02 = 0x49214;
-    SdrDramInfo_rom = 0x492a0;
-    SdrDramTiming_rom = 0x492b4;
-    SdrDramModeReg_rom = 0x492e8;
-    SdrDramDev_rom = 0x49304;
-    __rom_c_cut_rodata_end__ = 0x49314;
-    NewVectorTable = 0x10000000;
-    UserhandlerTable = 0x10000100;
-    UserIrqDataTable = 0x10000200;
-    __rom_bss_start__ = 0x10000300;
-    CfgSysDebugWarn = 0x10000300;
-    CfgSysDebugInfo = 0x10000304;
-    CfgSysDebugErr = 0x10000308;
-    ConfigDebugWarn = 0x1000030c;
-    ConfigDebugInfo = 0x10000310;
-    ConfigDebugErr = 0x10000314;
-    HalTimerOp = 0x10000318;
-    GPIOState = 0x10000334;
-    gTimerRecord = 0x1000034c;
-    SSI_DBG_CONFIG = 0x10000350;
-    _pHAL_Gpio_Adapter = 0x10000354;
-    Timer2To7VectorTable = 0x10000358;
-    pUartLogCtl = 0x10000384;
-    UartLogBuf = 0x10000388;
-    UartLogCtl = 0x10000408;
-    UartLogHistoryBuf = 0x10000430;
-    ArgvArray = 0x100006ac;
-    rom_wlan_ram_map = 0x100006d4;
-    FalseAlmCnt = 0x100006e0;
-    ROMInfo = 0x10000720;
-    DM_CfoTrack = 0x10000738;
-    rom_libgloss_ram_map = 0x10000760;
-    __rtl_errno = 0x10000bc4;
-}
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_timer.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_timer.h
index caf8223d118..42d5c62e0c1 100644
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_timer.h
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_timer.h
@@ -94,6 +94,11 @@ HalTimerReadCountRtl8195a_Patch(
     IN  u32 TimerId
 );
 
+VOID 
+HalTimerSync(
+    IN u32 TimerId
+);
+
 VOID
 HalTimerIrqEnRtl8195a(
     IN  u32 TimerId
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.h b/targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.h
index 6ad5c799dac..b2d287bf619 100644
--- a/targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.h
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.h
@@ -24,7 +24,7 @@ extern "C" {
 #endif
 
 #define FLASH_PAGE_SIZE 256
-#define FLASH_SIZE        0x100000
+#define FLASH_SIZE        0x200000
 #define FLASH_OFS_START   0x0
 #define FLASH_OFS_END     (FLASH_OFS_START + FLASH_SIZE)
 
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c
index 890a8ad5600..5b6215a78e7 100644
--- a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c
@@ -19,28 +19,11 @@
 #include "mbed_wait_api.h"
 
 #include "rtl8195a.h"
+#include "ota_api.h"
 #include "flash_ext.h"
 
-#define FLASH_TOP           0x200000
-#define FLASH_SECTOR_SIZE   0x1000
-#define FLASH_SECTOR_MASK   ~(FLASH_SECTOR_SIZE - 1)
-#define OTA_REGION1         0x0b000
-#define OTA_REGION2         0xc0000
-#define TAG_OFS             0xc
-#define VER_OFS             0x10
-
-#define TAG_DOWNLOAD        0x81950001
-#define TAG_VERIFIED        0x81950003
-
 static flash_t flash_obj;
 
-typedef struct imginfo_s {
-    uint32_t base;
-    uint32_t tag;
-    uint64_t ver;
-} imginfo_t;
-
-
 void OTA_GetImageInfo(imginfo_t *info)
 {
     uint32_t ver_hi, ver_lo;
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h
index 2b978a32368..8fe91694cee 100644
--- a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h
@@ -1,10 +1,30 @@
 #ifndef MBED_OTA_API_H
 #define MBED_OTA_API_H
 
+#define FLASH_TOP           0x200000
+#define FLASH_SECTOR_SIZE   0x1000
+#define FLASH_SECTOR_MASK   ~(FLASH_SECTOR_SIZE - 1)
+#define OTA_REGION1         0x0b000
+#define OTA_REGION2         0xc0000
+#define TAG_OFS             0xc
+#define VER_OFS             0x10
+
+#define TAG_DOWNLOAD        0x81950001
+#define TAG_VERIFIED        0x81950003
+
+typedef struct imginfo_s {
+    uint32_t base;
+    uint32_t tag;
+    uint64_t ver;
+} imginfo_t;
+
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
+extern void OTA_GetImageInfo(imginfo_t *info);
+extern uint32_t OTA_GetBase(void);
+
 extern uint32_t OTA_UpdateImage(uint32_t offset, uint32_t len, uint8_t *data);
 extern uint32_t OTA_ReadImage(uint32_t offset, uint32_t len, uint8_t *data);
 extern uint32_t OTA_MarkUpdateDone(void);
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/rtw_emac.cpp b/targets/TARGET_Realtek/TARGET_AMEBA/rtw_emac.cpp
index 280ebcb157c..9f9a3fff43e 100644
--- a/targets/TARGET_Realtek/TARGET_AMEBA/rtw_emac.cpp
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/rtw_emac.cpp
@@ -218,10 +218,7 @@ emac_interface_t *wlan_emac_init_interface()
 
     if (_emac == NULL) {
         _emac = (emac_interface_t*) malloc(sizeof(emac_interface_t));
-    	if (_emac == NULL) {//new emac_interface_t fail
-        	printf("emac initialization failed\r\n");
-		return NULL;
-    	}
+        MBED_ASSERT(_emac);
         _emac->hw = NULL;
         memcpy((void*)&_emac->ops, &wlan_emac_interface, sizeof(wlan_emac_interface));
     }
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/rtx2/rtx2_service.c b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/rtx2/rtx2_service.c
index 9876be86e83..f3d91ac100e 100644
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/rtx2/rtx2_service.c
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/rtx2/rtx2_service.c
@@ -548,7 +548,7 @@ _func_exit_;
 
 static u32 _rtx2_get_current_time(void)
 {
-	return osKernelGetTickCount();
+	return osKernelGetSysTimerCount();
 }
 
 static u32 _rtx2_systime_to_ms(u32 systime)
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_adc.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_adc.h
index 93b08da5da7..819454c28f8 100644
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_adc.h
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_adc.h
@@ -45,8 +45,7 @@ enum _ADC_DBG_LVL_ {
 typedef uint32_t ADC_DBG_LVL;
 typedef uint32_t * PADC_DBG_LVL;
 
-#ifdef CONFIG_DEBUG_LOG
-#ifdef CONFIG_DEBUG_LOG_ADC_HAL
+#if defined (CONFIG_DEBUG_LOG) && defined (CONFIG_DEBUG_LOG_ADC_HAL)
 
     #define DBG_8195A_ADC(...)  do{ \
         _DbgDump("\r"ADC_PREFIX __VA_ARGS__);\
@@ -64,7 +63,6 @@ typedef uint32_t * PADC_DBG_LVL;
     #define DBG_8195A_ADC(...)
     #define DBG_8195A_ADC_LVL(...)
 #endif
-#endif
 
 
 //================ ADC HAL Related Enumeration ==================
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_timer.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_timer.h
index 3e0b6cce154..b716cbaae32 100644
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_timer.h
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_timer.h
@@ -53,9 +53,10 @@ typedef struct _HAL_TIMER_OP_ {
 }HAL_TIMER_OP, *PHAL_TIMER_OP;
 
 typedef struct _HAL_TIMER_OP_EXT_ {
-	PHAL_TIMER_OP phal_timer_op_rom;
-	VOID (*HalTimerIrqEn)(u32 TimerId);
-	VOID (*HalTimerReLoad)(u32 TimerId, u32 LoadUs);
+    PHAL_TIMER_OP phal_timer_op_rom;
+    VOID (*HalTimerIrqEn)(u32 TimerId);
+    VOID (*HalTimerReLoad)(u32 TimerId, u32 LoadUs);
+    VOID (*HalTimerSync)(u32 TimerId);
 }HAL_TIMER_OP_EXT, *PHAL_TIMER_OP_EXT;
 
 #ifdef CONFIG_TIMER_MODULE
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/common/bsp/basic_types.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/common/bsp/basic_types.h
index da881fcabc1..bdadd0e0bdb 100644
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/common/bsp/basic_types.h
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/common/bsp/basic_types.h
@@ -206,6 +206,23 @@ typedef	    __kernel_ssize_t	SSIZE_T;
 
 #define _LONG_CALL_ROM_     _LONG_CALL_
 
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define SECTION(_name) __attribute__ ((__section__(_name)))
+#define ALIGNMTO(_bound) __attribute__ ((aligned (_bound)))
+#define _PACKED_       __attribute__ ((packed))
+#ifdef CONFIG_RELEASE_BUILD_LIBRARIES
+#define _LONG_CALL_
+#define _LONG_CALL_ROM_
+#ifdef E_CUT_ROM_DOMAIN
+#undef _LONG_CALL_ROM_
+#define _LONG_CALL_ROM_
+#endif
+#else
+#define _LONG_CALL_
+#define _LONG_CALL_ROM_     _LONG_CALL_
+#endif
+#define _WEAK           __attribute__ ((weak))
+
 #else
 #define SECTION(_name) __attribute__ ((__section__(_name)))
 #define ALIGNMTO(_bound) __attribute__ ((aligned (_bound)))
diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c b/targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c
index 4969b5f84b5..91d7f40027c 100644
--- a/targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c
@@ -19,9 +19,20 @@
 #include "us_ticker_api.h"
 #include "PeripheralNames.h"
 
-#define TICK_READ_FROM_CPU  0   // 1: read tick from CPU, 0: read tick from G-Timer
-#define SYS_TIM_ID      1   // the G-Timer ID for System
-#define APP_TIM_ID      6   // the G-Timer ID for Application
+#define SYS_TIM_ID          1   // the G-Timer ID for System
+#define APP_TIM_ID          2   // the G-Timer ID for Application
+
+/*
+ * For RTL8195AM, clock source is 32k
+ *
+ *   us per tick: 30.5
+ *   tick per ms: 32.7
+ *   tick per us: 0.032
+ *   tick per sec: 32768
+ *
+ * Define the following macros to convert between TICK and US.
+ */
+#define TICK_TO_US(x)       (uint64_t)(((x)/2) * 61 + ((x)%2) * TIMER_TICK_US)
 
 static int us_ticker_inited = 0;
 static TIMER_ADAPTER TimerAdapter;
@@ -29,19 +40,25 @@ static TIMER_ADAPTER TimerAdapter;
 extern HAL_TIMER_OP HalTimerOp;
 extern HAL_TIMER_OP_EXT HalTimerOpExt;
 
-VOID _us_ticker_irq_handler(IN  VOID *Data)
+VOID _us_ticker_irq_handler(void *Data)
 {
     us_ticker_irq_handler();
 }
 
-void us_ticker_init(void) 
+void us_ticker_init(void)
 {
-    
-    if (us_ticker_inited) return;
+    if (us_ticker_inited) {
+        return;
+    }
+
     us_ticker_inited = 1;
-    
 
-    // Initial a G-Timer
+    // Reload and restart sys-timer
+    HalTimerOp.HalTimerDis(SYS_TIM_ID);
+    HalTimerOpExt.HalTimerReLoad(SYS_TIM_ID, 0xFFFFFFFFUL);
+    HalTimerOp.HalTimerEn(SYS_TIM_ID);
+
+    // Initial a app-timer
     TimerAdapter.IrqDis = 0;    // Enable Irq @ initial
     TimerAdapter.IrqHandle.IrqFun = (IRQ_FUN) _us_ticker_irq_handler;
     TimerAdapter.IrqHandle.IrqNum = TIMER2_7_IRQ;
@@ -52,63 +69,53 @@ void us_ticker_init(void)
     TimerAdapter.TimerLoadValueUs = 0xFFFFFFFF;
     TimerAdapter.TimerMode = USER_DEFINED;
 
-    HalTimerOp.HalTimerInit((VOID*) &TimerAdapter);
-
-    DBG_TIMER_INFO("%s: Timer_Id=%d\n", __FUNCTION__, APP_TIM_ID);
+    HalTimerOp.HalTimerInit((void *) &TimerAdapter);
 }
 
-uint32_t us_ticker_read() 
+uint32_t us_ticker_read(void)
 {
     uint32_t tick_cnt;
-    uint32_t ticks_125ms;
-    uint32_t ticks_remain;
-    uint64_t us_tick;
 
-    tick_cnt = HalTimerOp.HalTimerReadCount(SYS_TIM_ID);
-    tick_cnt = 0xffffffff - tick_cnt;   // it's a down counter
-    ticks_125ms = tick_cnt/(GTIMER_CLK_HZ/8);  //use 125ms as a intermediate unit; 
-    ticks_remain = tick_cnt - (ticks_125ms*(GTIMER_CLK_HZ/8));  //calculate the remainder
-    us_tick = ticks_125ms * 125000;  //change unit to us, 125ms is 125000 us
-    us_tick += (ticks_remain * 1000000)/GTIMER_CLK_HZ;  //also use us as unit
+    if (!us_ticker_inited) {
+        us_ticker_init();
+    }
 
-    return ((uint32_t)us_tick);  //return ticker value in micro-seconds (us)
+    tick_cnt = HalTimerOp.HalTimerReadCount(SYS_TIM_ID);
+    return (uint32_t)TICK_TO_US(0xFFFFFFFFUL - tick_cnt);
 }
 
-void us_ticker_set_interrupt(timestamp_t timestamp) 
+void us_ticker_set_interrupt(timestamp_t timestamp)
 {
-    uint32_t cur_time_us;
-    uint32_t time_dif;
+    uint32_t time_cur;
 
-    HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId);
-    cur_time_us = us_ticker_read();
-    if ((uint32_t)timestamp > cur_time_us) {
-        time_dif = (uint32_t)timestamp - cur_time_us;
+    time_cur = us_ticker_read();
+    if (timestamp > time_cur + TIMER_TICK_US) {
+        TimerAdapter.TimerLoadValueUs = timestamp - time_cur;
     } else {
-        HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, 0xffffffff);
-        HalTimerOpExt.HalTimerIrqEn((u32)TimerAdapter.TimerId);
-        HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId);
-        NVIC_SetPendingIRQ(TIMER2_7_IRQ);
-        return;
-    }    
+        TimerAdapter.TimerLoadValueUs = TIMER_TICK_US;
+    }
 
-    TimerAdapter.TimerLoadValueUs = time_dif;
-    HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, time_dif / TIMER_TICK_US);
-    HalTimerOpExt.HalTimerIrqEn((u32)TimerAdapter.TimerId);
+    HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId);
+    HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, TimerAdapter.TimerLoadValueUs);
+    HalTimerOpExt.HalTimerSync(SYS_TIM_ID);
     HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId);
-
 }
 
 void us_ticker_fire_interrupt(void)
 {
-    NVIC_SetPendingIRQ(TIMER2_7_IRQ);
+    TimerAdapter.TimerLoadValueUs = TIMER_TICK_US;
+
+    HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId);
+    HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, TimerAdapter.TimerLoadValueUs);
+    HalTimerOpExt.HalTimerSync(SYS_TIM_ID);
+    HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId);
 }
 
-void us_ticker_disable_interrupt(void) 
+void us_ticker_disable_interrupt(void)
 {
     HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId);
 }
 
-void us_ticker_clear_interrupt(void) 
+void us_ticker_clear_interrupt(void)
 {
-    HalTimerOp.HalTimerIrqClear((u32)TimerAdapter.TimerId);
 }
diff --git a/targets/TARGET_Realtek/mbed_rtx.h b/targets/TARGET_Realtek/mbed_rtx.h
index cbf7b73fbc1..1da2503cd2c 100644
--- a/targets/TARGET_Realtek/mbed_rtx.h
+++ b/targets/TARGET_Realtek/mbed_rtx.h
@@ -20,7 +20,7 @@
 
 #include "rtl8195a.h"
 
-#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) || (__ARMCC_VERSION >= 6010050))
+#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
     extern uint32_t             Image$$ARM_LIB_STACK$$ZI$$Base[];
     extern uint32_t             Image$$ARM_LIB_STACK$$ZI$$Length[];
     #define ISR_STACK_START     (unsigned char *)(Image$$ARM_LIB_STACK$$ZI$$Base)
@@ -33,22 +33,11 @@
     #define INITIAL_SP          (__StackTop)
 #endif
 
-
-#if defined(__CC_ARM) || defined(__GNUC__)
+#if defined(__GNUC__)
 #ifndef ISR_STACK_SIZE
 #define ISR_STACK_SIZE          (0x1000)
 #endif
 #endif
 
-#ifndef OS_TASKCNT
-#define OS_TASKCNT              14
-#endif
-#ifndef OS_MAINSTKSIZE
-#define OS_MAINSTKSIZE          256
-#endif
-#ifndef OS_CLOCK
-#define OS_CLOCK                PLATFORM_CLK
-#endif
-
 #endif
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h
index 2c662d8d403..3f0c4e35f60 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h
@@ -47,6 +47,7 @@
 #define TIM_MST_UP_IRQ  TIM1_BRK_UP_TRG_COM_IRQn
 #define TIM_MST_OC_IRQ  TIM1_CC_IRQn
 #define TIM_MST_RCC     __TIM1_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM1()
 
 #define TIM_MST_RESET_ON   __TIM1_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM1_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h
index 2c662d8d403..3f0c4e35f60 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h
@@ -47,6 +47,7 @@
 #define TIM_MST_UP_IRQ  TIM1_BRK_UP_TRG_COM_IRQn
 #define TIM_MST_OC_IRQ  TIM1_CC_IRQn
 #define TIM_MST_RCC     __TIM1_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM1()
 
 #define TIM_MST_RESET_ON   __TIM1_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM1_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h
index 760f6b9c748..e8d74550477 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h
@@ -46,6 +46,7 @@ extern "C" {
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralPins.c
index 79eaa6c91e2..3ef6261bf95 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralPins.c
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralPins.c
@@ -1,6 +1,6 @@
 /* mbed Microcontroller Library
- '*******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -30,33 +30,42 @@
 
 #include "PeripheralPins.h"
 
-// =====
-// Note: Commented lines are alternative possibilities which are not used per default.
-//       If you change them, you will have also to modify the corresponding xxx_api.c file
-//       for pwmout, analogin, analogout, ...
-// =====
+//==============================================================================
+// Notes
+//
+// - The pins mentionned Px_y_ALTz are alternative possibilities which use other
+//   HW peripheral instances. You can use them the same way as any other "normal"
+//   pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+//   pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+//   the comment "Connected to xxx". The pin function may not work properly in this
+//   case. These pins may not be displayed on the board pinout image on mbed.org.
+//   Please read the board reference manual and schematic for more information.
+//
+//==============================================================================
 
 //*** ADC ***
 
 const PinMap PinMap_ADC[] = {
-    {PA_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0
-    {PA_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1
-//  {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 - Connected to STDIO_UART_TX
-    {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3
-    {PA_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4
-    {PA_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5
-    {PA_6,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC_IN6
-    {PA_7,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC_IN7
-    {PB_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC_IN8
-    {PB_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC_IN9
-    {NC,   NC,    0}
+    {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0
+    {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1
+//  {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 - Connected to STDIO_UART_TX
+    {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3
+    {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4
+    {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5
+    {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC_IN6
+    {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC_IN7
+    {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC_IN8
+    {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC_IN9
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC_IN16
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC_IN17
     {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC_IN18
-    {NC,   NC,    0}
+    {NC, NC, 0}
 };
 
 //*** I2C ***
@@ -66,48 +75,46 @@ const PinMap PinMap_I2C_SDA[] = {
     {PA_12, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C1)},
     {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
     {PF_0,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
-    {NC,    NC,    0}
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_I2C_SCL[] = {
     {PA_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
     {PA_11, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C1)},
     {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
-    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
     {PF_1,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
-    {NC,    NC,    0}
+    {NC, NC, 0}
 };
 
 //*** PWM ***
 
-// TIM2 cannot be used because already used by the us_ticker
+// TIM2 (PWM_2) cannot be used because already used by the us_ticker
 const PinMap PinMap_PWM[] = {
-//  {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2,  2, 0)},  // TIM2_CH2
-//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2,  3, 0)},  // TIM2_CH3 - Connected to STDIO_UART_TX
-//  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2,  4, 0)},  // TIM2_CH4
-    {PA_4,  PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1
-    {PA_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3,  1, 0)},  // TIM3_CH1
-//  {PA_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1
-    {PA_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3,  2, 0)},  // TIM3_CH2
-//  {PA_7,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1,  1, 1)},  // TIM1_CH1N
-//  {PA_7,  PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1
-//  {PA_7,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1
-    {PA_8,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1,  1, 0)},  // TIM1_CH1
-    {PA_9,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1,  2, 0)},  // TIM1_CH2
-    {PA_10, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1,  3, 0)},  // TIM1_CH3
-    {PA_11, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1,  4, 0)},  // TIM1_CH4
-    {PB_0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3,  3, 0)},  // TIM3_CH3
-//  {PB_0,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1,  2, 1)},  // TIM1_CH2N
-//  {PB_1,  PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1
-    {PB_1,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3,  4, 0)},  // TIM3_CH4
-//  {PB_1,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1,  3, 1)},  // TIM1_CH3N
-//  {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2,  2, 0)},  // TIM2_CH2
-    {PB_4,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3,  1, 0)},  // TIM3_CH1
-    {PB_5,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3,  2, 0)},  // TIM3_CH2
-    {PB_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N
-    {PB_7,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N
-//  {PB_8,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1
-    {NC,    NC,    0}
+//  {PA_1,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2,  2, 0)}, // TIM2_CH2
+//  {PA_2,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2,  3, 0)}, // TIM2_CH3 - Connected to STDIO_UART_TX
+//  {PA_3,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2,  4, 0)}, // TIM2_CH4
+    {PA_4,      PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1
+    {PA_6,      PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3,  1, 0)}, // TIM3_CH1
+    {PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1
+    {PA_7,      PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3,  2, 0)}, // TIM3_CH2
+    {PA_7_ALT0, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1,  1, 1)}, // TIM1_CH1N
+    {PA_7_ALT1, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1
+    {PA_7_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1
+    {PA_8,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1,  1, 0)}, // TIM1_CH1
+    {PA_9,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1,  2, 0)}, // TIM1_CH2
+    {PA_10,     PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1,  3, 0)}, // TIM1_CH3
+    {PA_11,     PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1,  4, 0)}, // TIM1_CH4
+    {PB_0,      PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3,  3, 0)}, // TIM3_CH3
+    {PB_0_ALT0, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1,  2, 1)}, // TIM1_CH2N
+    {PB_1,      PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3,  4, 0)}, // TIM3_CH4
+    {PB_1_ALT0, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1,  3, 1)}, // TIM1_CH3N
+    {PB_1_ALT1, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1
+//  {PB_3,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2,  2, 0)}, // TIM2_CH2 - Connected to LED
+    {PB_4,      PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3,  1, 0)}, // TIM3_CH1
+    {PB_5,      PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3,  2, 0)}, // TIM3_CH2
+    {PB_6,      PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N
+    {PB_7,      PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N
+    {NC, NC, 0}
 };
 
 //*** SERIAL ***
@@ -115,9 +122,9 @@ const PinMap PinMap_PWM[] = {
 const PinMap PinMap_UART_TX[] = {
     {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_TX
     {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
-//  {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // SWCLK
+//  {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to SWCLK
     {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
-    {NC,    NC,     0}
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_UART_RX[] = {
@@ -125,54 +132,55 @@ const PinMap PinMap_UART_RX[] = {
     {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
     {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_RX
     {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
-    {NC,    NC,     0}
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_UART_RTS[] = {
     {PA_1,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
     {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
-    {NC,    NC,     0}
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_UART_CTS[] = {
     {PA_0,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)},
     {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)},
-    {NC,    NC,     0}
+    {NC, NC, 0}
 };
 
 //*** SPI ***
 
 const PinMap PinMap_SPI_MOSI[] = {
-    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
-    {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
-    {NC,    NC,    0}
+    {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+    {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_SPI_MISO[] = {
-    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
-    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
-    {NC,    NC,    0}
+    {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+    {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_SPI_SCLK[] = {
-    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
-    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
-    {NC,    NC,    0}
+    {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
+    {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, // Connected to LED
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_SPI_SSEL[] = {
     {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)},
 //  {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, // Connected to STDIO_UART_RX
-    {NC,    NC,    0}
+    {NC, NC, 0}
 };
 
+//*** CAN ***
+
 const PinMap PinMap_CAN_RD[] = {
-//  {PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_CAN)},
     {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_CAN)},
-    {NC,    NC,    0}
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_CAN_TD[] = {
     {PA_12,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_CAN)},
-    {NC,    NC,    0}
+    {NC, NC, 0}
 };
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h
index 14d009eef16..a148910e590 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h
@@ -37,6 +37,13 @@
 extern "C" {
 #endif
 
+typedef enum {
+    ALT0  = 0x100,
+    ALT1  = 0x200,
+    ALT2  = 0x300,
+    ALT3  = 0x400
+} ALTx;
+
 typedef enum {
     PA_0  = 0x00,
     PA_1  = 0x01,
@@ -45,7 +52,11 @@ typedef enum {
     PA_4  = 0x04,
     PA_5  = 0x05,
     PA_6  = 0x06,
+    PA_6_ALT0 = PA_6|ALT0,
     PA_7  = 0x07,
+    PA_7_ALT0 = PA_7|ALT0,
+    PA_7_ALT1 = PA_7|ALT1,
+    PA_7_ALT2 = PA_7|ALT2,
     PA_8  = 0x08,
     PA_9  = 0x09,
     PA_10 = 0x0A,
@@ -56,7 +67,10 @@ typedef enum {
     PA_15 = 0x0F,
 
     PB_0  = 0x10,
+    PB_0_ALT0 = PB_0|ALT0,
     PB_1  = 0x11,
+    PB_1_ALT0 = PB_1|ALT0,
+    PB_1_ALT1 = PB_1|ALT1,
     PB_3  = 0x13,
     PB_4  = 0x14,
     PB_5  = 0x15,
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h
index 34e8fead9a7..0caa0508c08 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h
@@ -46,6 +46,7 @@ extern "C" {
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/objects.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/objects.h
index 8022de0cb78..d0f3565f66d 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 #include "common_objects.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h
index 2c662d8d403..3f0c4e35f60 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h
@@ -47,6 +47,7 @@
 #define TIM_MST_UP_IRQ  TIM1_BRK_UP_TRG_COM_IRQn
 #define TIM_MST_OC_IRQ  TIM1_CC_IRQn
 #define TIM_MST_RCC     __TIM1_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM1()
 
 #define TIM_MST_RESET_ON   __TIM1_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM1_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h
index 082b22cebba..42c96c85c60 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/objects.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/objects.h
index 8022de0cb78..d0f3565f66d 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 #include "common_objects.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h
index 082b22cebba..42c96c85c60 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/objects.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/objects.h
index 8022de0cb78..d0f3565f66d 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 #include "common_objects.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F0/analogout_device.c b/targets/TARGET_STM/TARGET_STM32F0/analogout_device.c
index c8891f85d8a..da73e70b309 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/analogout_device.c
+++ b/targets/TARGET_STM/TARGET_STM32F0/analogout_device.c
@@ -36,7 +36,7 @@
 #include "PeripheralPins.h"
 
 void analogout_init(dac_t *obj, PinName pin) {
-    DAC_ChannelConfTypeDef sConfig;
+    DAC_ChannelConfTypeDef sConfig = {0};
 
     // Get the peripheral name from the pin and assign it to the object
     obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
@@ -71,6 +71,8 @@ void analogout_init(dac_t *obj, PinName pin) {
 
     // Configure DAC
     obj->handle.Instance = (DAC_TypeDef *)(obj->dac);
+    obj->handle.State = HAL_DAC_STATE_RESET;
+
     if (HAL_DAC_Init(&obj->handle) != HAL_OK ) {
         error("HAL_DAC_Init failed");
     }
diff --git a/targets/TARGET_STM/TARGET_STM32F0/can_device.h b/targets/TARGET_STM/TARGET_STM32F0/can_device.h
index cff47d6a4c6..c1fa6fab6ae 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/can_device.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/can_device.h
@@ -17,7 +17,7 @@
 #define MBED_CAN_DEVICE_H
 
 #include "cmsis.h"
-#include "stm32f0xx_hal.h"
+#include "stm32f0xx.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -25,7 +25,7 @@ extern "C" {
 
 #ifdef DEVICE_CAN
 
-#define CAN_NUM    1 // Number of CAN peripherals present in the STM32 serie
+#define CAN_NUM 1 // Number of CAN peripherals present in the STM32 serie
 
 #define CAN1_IRQ_RX_IRQN        CEC_CAN_IRQn
 #define CAN1_IRQ_RX_VECT        CAN_IRQHandler
diff --git a/targets/TARGET_STM/TARGET_STM32F0/common_objects.h b/targets/TARGET_STM/TARGET_STM32F0/common_objects.h
index 3d11acebd0a..c6ebc7bd02c 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/common_objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F0/common_objects.h
@@ -128,6 +128,14 @@ struct dac_s {
 };
 #endif
 
+#if DEVICE_CAN
+struct can_s {
+    CAN_HandleTypeDef CanHandle;
+    int index;
+    int hz;
+};
+#endif
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c
index 600642db789..36023d28e75 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c
+++ b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c
@@ -478,9 +478,7 @@ void serial_clear(serial_t *obj)
 void serial_break_set(serial_t *obj)
 {
     struct serial_s *obj_s = SERIAL_S(obj);
-    UART_HandleTypeDef *huart = &uart_handlers[obj_s->index];
-
-    //HAL_LIN_SendBreak(huart);
+    UART_HandleTypeDef *huart __attribute__((unused)) = &uart_handlers[obj_s->index];
 }
 
 #if DEVICE_SERIAL_ASYNCH
@@ -798,9 +796,9 @@ int serial_irq_handler_asynch(serial_t *obj)
     HAL_UART_IRQHandler(huart);
     
     // Abort if an error occurs
-    if (return_event & SERIAL_EVENT_RX_PARITY_ERROR ||
-            return_event & SERIAL_EVENT_RX_FRAMING_ERROR ||
-            return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
+    if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) ||
+        (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
+        (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
         return return_event;
     }
     
@@ -874,8 +872,7 @@ void serial_rx_abort_asynch(serial_t *obj)
     
     // clear flags
     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF | UART_CLEAR_FEF | UART_CLEAR_OREF);
-    volatile uint32_t tmpval = huart->Instance->RDR; // Clear RXNE flag
-    UNUSED(tmpval);
+    volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear RXNE flag
     
     // reset states
     huart->RxXferCount = 0;
diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/hal_tick.h
index 91fd0c3789e..ac309396258 100644
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM4
 #define TIM_MST_IRQ  TIM4_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM4_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM4()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM4_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM4_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h
index 24fa9d1f175..5ddc595468a 100644
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 #include "common_objects.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/hal_tick.h
index 91fd0c3789e..ac309396258 100644
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM4
 #define TIM_MST_IRQ  TIM4_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM4_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM4()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM4_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM4_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/hal_tick.h
index 91fd0c3789e..ac309396258 100644
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM4
 #define TIM_MST_IRQ  TIM4_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM4_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM4()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM4_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM4_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h
index 24fa9d1f175..5ddc595468a 100644
--- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 #include "common_objects.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F1/can_device.h b/targets/TARGET_STM/TARGET_STM32F1/can_device.h
index 3792d0743e9..3a8438faed5 100644
--- a/targets/TARGET_STM/TARGET_STM32F1/can_device.h
+++ b/targets/TARGET_STM/TARGET_STM32F1/can_device.h
@@ -17,7 +17,7 @@
 #define MBED_CAN_DEVICE_H
 
 #include "cmsis.h"
-#include "stm32f1xx_hal.h"
+#include "stm32f1xx.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -25,7 +25,7 @@ extern "C" {
 
 #ifdef DEVICE_CAN
 
-#define CAN_NUM    1 // Number of CAN peripherals present in the STM32 serie
+#define CAN_NUM 1 // Number of CAN peripherals present in the STM32 serie
 
 #define CAN1_IRQ_RX_IRQN        CAN1_RX0_IRQn
 #define CAN1_IRQ_RX_VECT        CAN1_RX0_IRQHandler
diff --git a/targets/TARGET_STM/TARGET_STM32F1/common_objects.h b/targets/TARGET_STM/TARGET_STM32F1/common_objects.h
index 12487fcf0b6..3bd078970cb 100644
--- a/targets/TARGET_STM/TARGET_STM32F1/common_objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F1/common_objects.h
@@ -116,6 +116,14 @@ struct analogin_s {
     uint8_t channel;
 };
 
+#if DEVICE_CAN
+struct can_s {
+    CAN_HandleTypeDef CanHandle;
+    int index;
+    int hz;
+};
+#endif
+
 #include "gpio_object.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.c
index bec0085ea28..106f15e691b 100644
--- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.c
+++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.c
@@ -500,7 +500,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
   */
 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
-  uint16_t* tmp;
   uint32_t tickstart = 0U;
   
   if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
@@ -530,8 +529,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
       {
         return HAL_TIMEOUT;
       }
-      tmp = (uint16_t*) pData;
-      *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF);
+      *pData = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF);
       pData +=1U;
     }
 
diff --git a/targets/TARGET_STM/TARGET_STM32F1/serial_device.c b/targets/TARGET_STM/TARGET_STM32F1/serial_device.c
index d427407f6d1..8c9cf38f214 100644
--- a/targets/TARGET_STM/TARGET_STM32F1/serial_device.c
+++ b/targets/TARGET_STM/TARGET_STM32F1/serial_device.c
@@ -172,7 +172,7 @@ static void uart_irq(int id)
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
             if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET) {
-                volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag
+                volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear ORE flag
             }
         }
     }
@@ -542,13 +542,13 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
 
 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
     if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
-        volatile uint32_t tmpval = huart->Instance->DR; // Clear PE flag
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag
     } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
-        volatile uint32_t tmpval = huart->Instance->DR; // Clear FE flag
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear FE flag
     } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_NE) != RESET) {
-        volatile uint32_t tmpval = huart->Instance->DR; // Clear NE flag
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear NE flag
     } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
-        volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear ORE flag
     }
 }
 
@@ -599,9 +599,9 @@ int serial_irq_handler_asynch(serial_t *obj)
     HAL_UART_IRQHandler(huart);
     
     // Abort if an error occurs
-    if (return_event & SERIAL_EVENT_RX_PARITY_ERROR ||
-            return_event & SERIAL_EVENT_RX_FRAMING_ERROR ||
-            return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
+    if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) ||
+        (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
+        (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
         return return_event;
     }
     
@@ -675,7 +675,7 @@ void serial_rx_abort_asynch(serial_t *obj)
     
     // clear flags
     __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
-    volatile uint32_t tmpval = huart->Instance->DR; // Clear errors flag
+    volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear errors flag
     
     // reset states
     huart->RxXferCount = 0;
diff --git a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/hal_tick.h
index cc5b124ad1d..94a71d0eef6 100644
--- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/hal_tick.h
@@ -46,6 +46,7 @@ extern "C" {
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F2/analogout_device.c b/targets/TARGET_STM/TARGET_STM32F2/analogout_device.c
index 584034fc85f..3976d5b0840 100644
--- a/targets/TARGET_STM/TARGET_STM32F2/analogout_device.c
+++ b/targets/TARGET_STM/TARGET_STM32F2/analogout_device.c
@@ -1,5 +1,5 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2016, STMicroelectronics
+ * Copyright (c) 2017, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -25,6 +25,7 @@
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
+#include "mbed_assert.h"
 #include "analogout_api.h"
 
 #if DEVICE_ANALOGOUT
@@ -32,19 +33,20 @@
 #include "cmsis.h"
 #include "pinmap.h"
 #include "mbed_error.h"
-#include "stm32f2xx_hal.h"
 #include "PeripheralPins.h"
 
 void analogout_init(dac_t *obj, PinName pin)
 {
-    DAC_ChannelConfTypeDef sConfig;
+    DAC_ChannelConfTypeDef sConfig = {0};
 
-    // Get the peripheral name (DAC_1, ...) from the pin and assign it to the object
+    // Get the peripheral name from the pin and assign it to the object
     obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
-    // Get the functions (dac channel) from the pin and assign it to the object
+    MBED_ASSERT(obj->dac != (DACName)NC);
+
+    // Get the pin function and assign the used channel to the object
     uint32_t function = pinmap_function(pin, PinMap_DAC);
     MBED_ASSERT(function != (uint32_t)NC);
-    // Save the channel for the write and read functions
+
     switch (STM_PIN_CHANNEL(function)) {
         case 1:
             obj->channel = DAC_CHANNEL_1;
@@ -59,18 +61,19 @@ void analogout_init(dac_t *obj, PinName pin)
             break;
     }
 
-    if (obj->dac == (DACName)NC) {
-        error("DAC pin mapping failed");
-    }
-
     // Configure GPIO
     pinmap_pinout(pin, PinMap_DAC);
 
-    __GPIOA_CLK_ENABLE();
+    // Save the pin for future use
+    obj->pin = pin;
+
+    // Enable DAC clock
+    __HAL_RCC_DAC_CLK_ENABLE();
 
-    __DAC_CLK_ENABLE();
+    // Configure DAC
+    obj->handle.Instance = (DAC_TypeDef *)(obj->dac);
+    obj->handle.State = HAL_DAC_STATE_RESET;
 
-    obj->handle.Instance = DAC;
     if (HAL_DAC_Init(&obj->handle) != HAL_OK ) {
         error("HAL_DAC_Init failed");
     }
@@ -87,8 +90,13 @@ void analogout_init(dac_t *obj, PinName pin)
 
 void analogout_free(dac_t *obj)
 {
-}
-
+    // Reset DAC and disable clock
+    __HAL_RCC_DAC_FORCE_RESET();
+    __HAL_RCC_DAC_RELEASE_RESET();
+    __HAL_RCC_DAC_CLK_DISABLE();
 
+    // Configure GPIO
+    pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+}
 
 #endif // DEVICE_ANALOGOUT
diff --git a/targets/TARGET_STM/TARGET_STM32F2/can_device.h b/targets/TARGET_STM/TARGET_STM32F2/can_device.h
index 97a54210a06..cb95b44ea83 100644
--- a/targets/TARGET_STM/TARGET_STM32F2/can_device.h
+++ b/targets/TARGET_STM/TARGET_STM32F2/can_device.h
@@ -17,7 +17,7 @@
 #define MBED_CAN_DEVICE_H
 
 #include "cmsis.h"
-#include "stm32f2xx_hal.h"
+#include "stm32f2xx.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -25,7 +25,7 @@ extern "C" {
 
 #ifdef DEVICE_CAN
 
-#define CAN_NUM 2 // Number of CAN peripherals present in the STM32 serie (1 or 2)
+#define CAN_NUM 2 // Number of CAN peripherals present in the STM32 serie
 
 #define CAN1_IRQ_RX_IRQN        CAN1_RX0_IRQn
 #define CAN1_IRQ_RX_VECT        CAN1_RX0_IRQHandler
diff --git a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_smartcard.c
index e76577faa30..b04749ff634 100644
--- a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_smartcard.c
+++ b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_smartcard.c
@@ -496,7 +496,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
   */
 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
-  uint16_t* tmp;
   uint32_t tickstart = 0U;
   
   if(hsc->RxState == HAL_SMARTCARD_STATE_READY) 
@@ -526,8 +525,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
       {
         return HAL_TIMEOUT;
       }
-      tmp = (uint16_t*) pData;
-      *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF);
+      *pData = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF);
       pData +=1U;
     }
 
diff --git a/targets/TARGET_STM/TARGET_STM32F2/objects.h b/targets/TARGET_STM/TARGET_STM32F2/objects.h
index c2489cb8511..a961a63a448 100644
--- a/targets/TARGET_STM/TARGET_STM32F2/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F2/objects.h
@@ -62,7 +62,8 @@ struct analogin_s {
 
 struct dac_s {
     DACName dac;
-    uint8_t channel;
+    PinName pin;
+    uint32_t channel;
     DAC_HandleTypeDef handle;
 };
 
@@ -136,10 +137,13 @@ struct pwmout_s {
     uint8_t inverted;
 };
 
+#ifdef DEVICE_CAN
 struct can_s {
-    CANName can;
+    CAN_HandleTypeDef CanHandle;
     int index;
+    int hz;
 };
+#endif
 
 #define GPIO_IP_WITHOUT_BRR
 #include "gpio_object.h"
diff --git a/targets/TARGET_STM/TARGET_STM32F2/serial_device.c b/targets/TARGET_STM/TARGET_STM32F2/serial_device.c
index c1d16826937..7f238971756 100644
--- a/targets/TARGET_STM/TARGET_STM32F2/serial_device.c
+++ b/targets/TARGET_STM/TARGET_STM32F2/serial_device.c
@@ -259,7 +259,7 @@ static void uart_irq(int id)
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
             if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
-                volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag
+                volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear ORE flag
             }
         }
     }
@@ -720,13 +720,13 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
 
 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
     if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
-        volatile uint32_t tmpval = huart->Instance->DR; // Clear PE flag
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag
     } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
-        volatile uint32_t tmpval = huart->Instance->DR; // Clear FE flag
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear FE flag
     } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_NE) != RESET) {
-        volatile uint32_t tmpval = huart->Instance->DR; // Clear NE flag
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear NE flag
     } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
-        volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear ORE flag
     }
 }
 
@@ -777,9 +777,9 @@ int serial_irq_handler_asynch(serial_t *obj)
     HAL_UART_IRQHandler(huart);
     
     // Abort if an error occurs
-    if (return_event & SERIAL_EVENT_RX_PARITY_ERROR ||
-            return_event & SERIAL_EVENT_RX_FRAMING_ERROR ||
-            return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
+    if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) ||
+        (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
+        (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
         return return_event;
     }
     
@@ -853,7 +853,7 @@ void serial_rx_abort_asynch(serial_t *obj)
     
     // clear flags
     __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
-    volatile uint32_t tmpval = huart->Instance->DR; // Clear error flags
+    volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear error flags
     
     // reset states
     huart->RxXferCount = 0;
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/hal_tick.h
index 8ff2fb0ace0..8bd5f6b136e 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/objects.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/objects.h
index 8022de0cb78..d0f3565f66d 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 #include "common_objects.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralPins.c
index 7f6fa41ee5b..1478979209a 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralPins.c
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralPins.c
@@ -1,6 +1,6 @@
 /* mbed Microcontroller Library
  *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
+ * Copyright (c) 2017, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -30,28 +30,35 @@
 
 #include "PeripheralPins.h"
 
-// =====
-// Note: Commented lines are alternative possibilities which are not used per default.
-//       If you change them, you will have also to modify the corresponding xxx_api.c file
-//       for pwmout, analogin, analogout, ...
-// =====
+//==============================================================================
+// Notes
+//
+// - The pins mentionned Px_y_ALTz are alternative possibilities which use other
+//   HW peripheral instances. You can use them the same way as any other "normal"
+//   pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+//   pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+//   the comment "Connected to xxx". The pin function may not work properly in this
+//   case. These pins may not be displayed on the board pinout image on mbed.org.
+//   Please read the board reference manual and schematic for more information.
+//
+//==============================================================================
 
 //*** ADC ***
 
 const PinMap PinMap_ADC[] = {
-    {PA_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 - ARDUINO A0
-    {PA_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 - ARDUINO A1
-    {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
-    {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 - ARDUINO A2
-    {PA_4,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 - ARDUINO A3
-    {PA_5,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 - ARDUINO A4
-    {PA_6,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 - ARDUINO A5
-    {PA_7,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 - ARDUINO A7
-	
+    {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 - ARDUINO A0
+    {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 - ARDUINO A1
+//  {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 - Connected to STDIO_UART_TX
+    {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 - ARDUINO A2
+    {PA_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 - ARDUINO A3
+    {PA_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 - ARDUINO A4
+    {PA_6, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 - ARDUINO A5
+    {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 - ARDUINO A7
     {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 - ARDUINO D3
     {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 - ARDUINO D6
-
-    {NC,    NC,    0}
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_ADC_Internal[] = {
@@ -60,8 +67,7 @@ const PinMap PinMap_ADC_Internal[] = {
     {ADC_VREF2,   ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_IN18
     {ADC_VBAT,    ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17
     {ADC_VOPAMP2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC2_IN17
-
-    {NC,    NC,    0}
+    {NC, NC, 0}
 };
 
 //*** DAC ***
@@ -70,136 +76,135 @@ const PinMap PinMap_DAC[] = {
     {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 - ARDUINO A3
     {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 - ARDUINO A4
     {PA_6, DAC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC2_OUT1 - ARDUINO A5
-    {NC,   NC,    0}
+    {NC, NC, 0}
 };
 
 //*** I2C ***
 
 const PinMap PinMap_I2C_SDA[] = {
-    {PA_14,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PA_14, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
     {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {NC,    NC,    0}
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_I2C_SCL[] = {
-    {PA_15,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+//  {PA_15, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to STDIO_UART_RX
     {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {NC,    NC,    0}
+    {NC, NC, 0}
 };
 
 //*** PWM ***
 
-// TIM2 cannot be used because already used by the us_ticker
+// TIM2 (PWM_2) cannot be used because already used by the us_ticker
 const PinMap PinMap_PWM[] = {
-//  {PA_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
-//  {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2
-    {PA_1,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 1)}, // TIM15_CH1N
-//  {PA_2,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},   // TIM2_CH3
-    {PA_2,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 0)}, // TIM15_CH1
-//  {PA_3,  PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)},   // TIM2_CH4
-    {PA_3,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 2, 0)}, // TIM15_CH2
-    {PA_4,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
-//  {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
-    {PA_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1
-//  {PA_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
-    {PA_7,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1
-//  {PA_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
-//  {PA_7,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)},  // TIM1_CH1N
-    {PA_8,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 0)},  // TIM1_CH1
-    {PA_9,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 0)},  // TIM1_CH2
-//  {PA_9,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 3, 0)}, // TIM2_CH3
-    {PA_10, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 0)},  // TIM1_CH3
-//  {PA_10, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 4, 0)}, // TIM2_CH4
-    {PA_11, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 4, 0)}, // TIM1_CH4
-//  {PA_11, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)},  // TIM1_CH1N
-    {PA_12, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1
-//  {PA_12, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)},  // TIM1_CH2N
-    {PA_13, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N
-//  {PA_15, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
-
-//  {PB_0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
-    {PB_0,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)},  // TIM1_CH2N
-//  {PB_1,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
-    {PB_1,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)},  // TIM1_CH3N
-//  {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2
-    {PB_4,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1
-//  {PB_4,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
-//  {PB_5,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
-    {PB_5,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)},// TIM17_CH1
-    {PB_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - ARDUINO
-    {PB_7,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N
-//  {PB_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM3, 4, 0)}, // TIM3_CH4
-
-    {PF_0,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)},  // TIM1_CH3N
-
-    {NC,    NC,     0}
+//  {PA_0,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+//  {PA_1,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2
+    {PA_1,       PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 1)}, // TIM15_CH1N
+//  {PA_2,       PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},   // TIM2_CH3 - Connected to STDIO_UART_TX
+//  {PA_2,       PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 0)}, // TIM15_CH1 - Connected to STDIO_UART_TX
+//  {PA_3,       PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)},   // TIM2_CH4
+    {PA_3,       PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 2, 0)}, // TIM15_CH2
+    {PA_4,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+//  {PA_5,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+    {PA_6,       PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1
+    {PA_6_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+    {PA_7,       PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1
+    {PA_7_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+    {PA_7_ALT1,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)},  // TIM1_CH1N
+    {PA_8,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 0)},  // TIM1_CH1
+    {PA_9,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 0)},  // TIM1_CH2
+//  {PA_9,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 3, 0)}, // TIM2_CH3
+    {PA_10,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 0)},  // TIM1_CH3
+//  {PA_10,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 4, 0)}, // TIM2_CH4
+    {PA_11,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 4, 0)}, // TIM1_CH4
+    {PA_11_ALT0, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)},  // TIM1_CH1N
+    {PA_12,      PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1
+    {PA_12_ALT0, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)},  // TIM1_CH2N
+    {PA_13,      PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N
+//  {PA_15,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1 - Connected to STDIO_UART_RX
+    {PB_0,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)},  // TIM1_CH2N
+    {PB_0_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
+    {PB_1,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)},  // TIM1_CH3N
+    {PB_1_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
+//  {PB_3,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2 - Connected to LED
+    {PB_4,       PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1
+    {PB_4_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+    {PB_5,       PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)},// TIM17_CH1
+    {PB_5_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+    {PB_6,       PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - ARDUINO
+    {PB_7,       PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N
+    {PB_7_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM3, 4, 0)}, // TIM3_CH4
+    {PF_0,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)},  // TIM1_CH3N
+    {NC, NC, 0}
 };
 
 //*** SERIAL ***
 
 const PinMap PinMap_UART_TX[] = {
-    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX
     {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
-    {PB_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PB_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to LED
     {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {NC,    NC,     0}
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_UART_RX[] = {
     {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
     {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX
     {PB_4,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
     {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {NC,    NC,     0}
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_UART_RTS[] = {
     {PA_1,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
     {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {NC,    NC,    0}
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_UART_CTS[] = {
     {PA_0,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
     {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PA_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-    {NC,    NC,    0}
+    {NC, NC, 0}
 };
 
 //*** SPI ***
 
 const PinMap PinMap_SPI_MOSI[] = {
-    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {NC,    NC,    0}
+    {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_SPI_MISO[] = {
-    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {NC,    NC,    0}
+    {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_SPI_SCLK[] = {
-    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // Warning: LED1 is connected on this pin
-    {NC,    NC,    0}
+    {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // Connected to LED
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_SPI_SSEL[] = {
     {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {NC,    NC,    0}
+//  {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // Connected to STDIO_UART_RX
+    {NC, NC, 0}
 };
 
+//*** CAN ***
+
 const PinMap PinMap_CAN_RD[] = {
     {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)},
-    {NC,    NC,    0}
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_CAN_TD[] = {
-    {PA_12,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)},
-    {NC,    NC,    0}
+    {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)},
+    {NC, NC, 0}
 };
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h
index c46b324dfc6..65b8674ddf7 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h
@@ -37,6 +37,13 @@
 extern "C" {
 #endif
 
+typedef enum {
+    ALT0  = 0x100,
+    ALT1  = 0x200,
+    ALT2  = 0x300,
+    ALT3  = 0x400
+} ALTx;
+
 typedef enum {
     PA_0  = 0x00,
     PA_1  = 0x01,
@@ -45,23 +52,33 @@ typedef enum {
     PA_4  = 0x04,
     PA_5  = 0x05,
     PA_6  = 0x06,
+    PA_6_ALT0 = PA_6|ALT0,
     PA_7  = 0x07,
+    PA_7_ALT0 = PA_7|ALT0,
+    PA_7_ALT1 = PA_7|ALT1,
     PA_8  = 0x08,
     PA_9  = 0x09,
     PA_10 = 0x0A,
     PA_11 = 0x0B,
+    PA_11_ALT0 = PA_11|ALT0,
     PA_12 = 0x0C,
+    PA_12_ALT0 = PA_12|ALT0,
     PA_13 = 0x0D,
     PA_14 = 0x0E,
     PA_15 = 0x0F,
 
     PB_0  = 0x10,
+    PB_0_ALT0 = PB_0|ALT0,
     PB_1  = 0x11,
+    PB_1_ALT0 = PB_1|ALT0,
     PB_3  = 0x13,
     PB_4  = 0x14,
+    PB_4_ALT0 = PB_4|ALT0,
     PB_5  = 0x15,
+    PB_5_ALT0 = PB_5|ALT0,
     PB_6  = 0x16,
     PB_7  = 0x17,
+    PB_7_ALT0 = PB_7|ALT0,
 
     PF_0  = 0x50,
     PF_1  = 0x51,
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/hal_tick.h
index 8ff2fb0ace0..8bd5f6b136e 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/objects.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/objects.h
index 8022de0cb78..d0f3565f66d 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 #include "common_objects.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/hal_tick.h
index 8ff2fb0ace0..8bd5f6b136e 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/objects.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/objects.h
index 8022de0cb78..d0f3565f66d 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 #include "common_objects.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/hal_tick.h
index 8ff2fb0ace0..8bd5f6b136e 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/objects.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/objects.h
index 8022de0cb78..d0f3565f66d 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 #include "common_objects.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/hal_tick.h
index 8ff2fb0ace0..8bd5f6b136e 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/objects.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/objects.h
index 90b0f732c14..d0f3565f66d 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/objects.h
@@ -54,13 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-#if defined (DEVICE_CAN)
-struct can_s {
-    CANName can;
-    int index;
-};
-#endif
-
 #include "common_objects.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F3/analogout_device.c b/targets/TARGET_STM/TARGET_STM32F3/analogout_device.c
index 6bc7da1e5b0..4b17b6e5f2f 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/analogout_device.c
+++ b/targets/TARGET_STM/TARGET_STM32F3/analogout_device.c
@@ -40,7 +40,7 @@ static int pa4_used = 0;
 static int pa5_used = 0;
 
 void analogout_init(dac_t *obj, PinName pin) {
-    DAC_ChannelConfTypeDef sConfig;
+    DAC_ChannelConfTypeDef sConfig = {0};
 
     // Get the peripheral name from the pin and assign it to the object
     obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
@@ -83,6 +83,8 @@ void analogout_init(dac_t *obj, PinName pin) {
 
     // Configure DAC
     obj->handle.Instance = (DAC_TypeDef *)(obj->dac);
+    obj->handle.State = HAL_DAC_STATE_RESET;
+
     if (HAL_DAC_Init(&obj->handle) != HAL_OK ) {
         error("HAL_DAC_Init failed");
     }
diff --git a/targets/TARGET_STM/TARGET_STM32F3/can_device.h b/targets/TARGET_STM/TARGET_STM32F3/can_device.h
index 1d777682008..121999c6811 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/can_device.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/can_device.h
@@ -17,7 +17,7 @@
 #define MBED_CAN_DEVICE_H
 
 #include "cmsis.h"
-#include "stm32f3xx_hal.h"
+#include "stm32f3xx.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -25,7 +25,7 @@ extern "C" {
 
 #ifdef DEVICE_CAN
 
-#define CAN_NUM    1 // Number of CAN peripherals present in the STM32 serie
+#define CAN_NUM 1 // Number of CAN peripherals present in the STM32 serie
 
 #define CAN1_IRQ_RX_IRQN        CAN_RX0_IRQn
 #define CAN1_IRQ_RX_VECT        CAN_RX0_IRQHandler
diff --git a/targets/TARGET_STM/TARGET_STM32F3/common_objects.h b/targets/TARGET_STM/TARGET_STM32F3/common_objects.h
index 8db726ed146..ba731890ce5 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/common_objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F3/common_objects.h
@@ -124,6 +124,14 @@ struct analogin_s {
     uint8_t channel;
 };
 
+#if DEVICE_CAN
+struct can_s {
+    CAN_HandleTypeDef CanHandle;
+    int index;
+    int hz;
+};
+#endif
+
 #include "gpio_object.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F3/serial_device.c b/targets/TARGET_STM/TARGET_STM32F3/serial_device.c
index be5660a0863..b1f2de8ca06 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/serial_device.c
+++ b/targets/TARGET_STM/TARGET_STM32F3/serial_device.c
@@ -697,9 +697,9 @@ int serial_irq_handler_asynch(serial_t *obj)
     HAL_UART_IRQHandler(huart);
     
     // Abort if an error occurs
-    if (return_event & SERIAL_EVENT_RX_PARITY_ERROR ||
-            return_event & SERIAL_EVENT_RX_FRAMING_ERROR ||
-            return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
+    if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) ||
+        (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
+        (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
         return return_event;
     }
     
@@ -773,8 +773,7 @@ void serial_rx_abort_asynch(serial_t *obj)
     
     // clear flags
     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF | UART_CLEAR_FEF | UART_CLEAR_OREF);
-    volatile uint32_t tmpval = huart->Instance->RDR; // Clear RXNE flag
-    UNUSED(tmpval);
+    volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear RXNE flag
     
     // reset states
     huart->RxXferCount = 0;
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/hal_tick.h
index 19d9584eee3..cedecee5453 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c
index e80ad41e0fb..eee454211db 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c
@@ -35,6 +35,7 @@
 **/
 
 #include "stm32f4xx.h"
+#include "mbed_debug.h"
 
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */
@@ -240,8 +241,6 @@ uint8_t SetSysClock_PLL_HSI(void)
 /******************************************************************************/
 void HardFault_Handler(void)
 {
-#if !defined(NDEBUG) || NDEBUG == 0
-    printf("Hard Fault\n");
-#endif
+    debug("Hard Fault\n");
     NVIC_SystemReset();
 }
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/hal_tick.h
index 19d9584eee3..cedecee5453 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/hal_tick.h
index 19d9584eee3..cedecee5453 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c
index cf1e3832b3d..f24a80bfdaf 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c
@@ -35,7 +35,7 @@
 **/
 
 #include "stm32f4xx.h"
-
+#include "mbed_debug.h"
 
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */
@@ -243,8 +243,6 @@ uint8_t SetSysClock_PLL_HSI(void)
 /******************************************************************************/
 void HardFault_Handler(void)
 {
-#if !defined(NDEBUG) || NDEBUG == 0
-    printf("Hard Fault\n");
-#endif
+    debug("Hard Fault\n");
     NVIC_SystemReset();
 }
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/hal_tick.h
index 19d9584eee3..cedecee5453 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/hal_tick.h
index 19d9584eee3..cedecee5453 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/hal_tick.h
index 19d9584eee3..cedecee5453 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/hal_tick.h
index 19d9584eee3..cedecee5453 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf
index f702047a09c..46363c1caf5 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf
@@ -10,7 +10,7 @@ define symbol __region_ROM_end__   = MBED_APP_START + MBED_APP_SIZE;
 define symbol __NVIC_start__          = 0x20000000;
 define symbol __NVIC_end__            = 0x200001C7; /* Aligned on 8 bytes */
 define symbol __region_RAM_start__    = 0x200001C8;
-define symbol __region_RAM_end__      = 0x2001FFFF;
+define symbol __region_RAM_end__      = 0x2003FFFF;
 
 /* Memory regions */
 define memory mem with size = 4G;
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/hal_tick.h
index 19d9584eee3..cedecee5453 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/objects.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/objects.h
index 9ab04158e02..565319422ca 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/objects.h
@@ -40,11 +40,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 struct trng_s {
     RNG_HandleTypeDef handle;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/hal_tick.h
index e428968d4a6..5627990658b 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/objects.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/objects.h
index ceee07a5945..9b3aa0b3f9a 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/objects.h
@@ -40,11 +40,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 struct trng_s {
     RNG_HandleTypeDef handle;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/hal_tick.h
index d5ede91000a..02aa6028c22 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/objects.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/objects.h
index a7e928ec3a8..ece5f1679fa 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 struct trng_s {
     RNG_HandleTypeDef handle;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/hal_tick.h
index d5ede91000a..02aa6028c22 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/objects.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/objects.h
index e1b80b20e45..d2474f4e521 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/objects.h
@@ -59,11 +59,6 @@ struct trng_s {
 };
 
 #include "common_objects.h"
-struct can_s {
-    CANName can;
-    int index;
-};
-
 #include "gpio_object.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h
similarity index 97%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PeripheralNames.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h
index fb1cdab06b6..fcd76d01523 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PeripheralNames.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h
@@ -57,9 +57,8 @@ typedef enum {
     UART_8 = (int)UART8_BASE
 } UARTName;
 
-#define STDIO_UART_TX  PA_9
-#define STDIO_UART_RX  PA_10
-#define STDIO_UART     UART_1
+#define STDIO_UART_TX  USBTX
+#define STDIO_UART_RX  USBRX
 
 typedef enum {
     SPI_1 = (int)SPI1_BASE,
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralPins.c
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PeripheralPins.c
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralPins.c
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h
similarity index 61%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h
index 08373f49235..ea26b948073 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h
@@ -57,7 +57,7 @@ typedef enum {
     PD_4  = 0x34, PD_5  = 0x35, PD_6  = 0x36, PD_7  = 0x37,
     PD_8  = 0x38, PD_9  = 0x39, PD_10 = 0x3A, PD_11 = 0x3B,
     PD_12 = 0x3C, PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F,
-    
+
     PE_0  = 0x40, PE_1  = 0x41, PE_2  = 0x42, PE_3  = 0x43,
     PE_4  = 0x44, PE_5  = 0x45, PE_6  = 0x46, PE_7  = 0x47,
     PE_8  = 0x48, PE_9  = 0x49, PE_10 = 0x4A, PE_11 = 0x4B,
@@ -80,100 +80,90 @@ typedef enum {
 
     // Module Pins
     // A
-    P_A5    = PC_2,   // UART-DTR
-    P_A6    = PF_2,   // Switch-0
-    P_A7    = PE_0,   // Red, Mode
-    P_A8    = PB_6,   // Green, Switch-1
-    P_A9    = PB_8,   // Blue
-    P_A10   = PA_11,  // UART-CTS
-    P_A11   = PA_9,   // UART-TXD
-    P_A12   = PA_12,  // UART-RTS
-    P_A13   = PA_10,  // UART-RXD
-    P_A14   = PD_9,   // GPIO-0
-    P_A15   = PD_8,   // GPIO-1
-    P_A16   = PD_11,  // GPIO-2
-    P_A17   = PD_12,  // GPIO-3
-    P_A18   = PA_3,   // UART-DSR
+    P_A5       = PC_2,   // UART-DTR
+    P_A6       = PF_2,   // Switch-0
+    P_A7       = PE_0,   // Red, Mode
+    P_A8       = PB_6,   // Green, Switch-1
+    P_A9       = PB_8,   // Blue
+    P_A10      = PA_11,  // UART-CTS
+    P_A11      = PA_9,   // UART-TXD
+    P_A12      = PA_12,  // UART-RTS
+    P_A13      = PA_10,  // UART-RXD
+    P_A14      = PD_9,   // GPIO-0
+    P_A15      = PD_8,   // GPIO-1
+    P_A16      = PD_11,  // GPIO-2
+    P_A17      = PD_12,  // GPIO-3
+    P_A18      = PA_3,   // UART-DSR
     // B
     // C
-    P_C5    = PG_4,   // SPI-IRQ
-    P_C6    = PE_13,  // SPI-MISO
-    P_C8    = PE_12,  // Res
-    P_C10   = PE_14,  // SPI-MOSI
-    P_C11   = PE_11,  // SPI-CS0
-    P_C12   = PE_9,   // Res
-    P_C13   = PF_6,   // GPIO-4
-    P_C14   = PC_1,   // RMII-MDC
-    P_C15   = PA_2,   // RMII-MDIO
-    P_C16   = PF_7,   // GPIO-7
-    P_C17   = PF_1,   // I2C-SCL
-    P_C18   = PF_0,   // I2C-SDA
+    P_C5       = PG_4,   // SPI-IRQ
+    P_C6       = PE_13,  // SPI-MISO
+    P_C8       = PE_12,  // Res
+    P_C10      = PE_14,  // SPI-MOSI
+    P_C11      = PE_11,  // SPI-CS0
+    P_C12      = PE_9,   // Res
+    P_C13      = PF_6,   // GPIO-4
+    P_C14      = PC_1,   // RMII-MDC
+    P_C15      = PA_2,   // RMII-MDIO
+    P_C16      = PF_7,   // GPIO-7
+    P_C17      = PF_1,   // I2C-SCL
+    P_C18      = PF_0,   // I2C-SDA
 	  // D
-    P_D1    = PB_12,  // RMII-TXD0
-    P_D2    = PB_13,  // RMII-TXD1
-    P_D3    = PB_11,  // RMII-TXEN
-    P_D4    = PA_7,   // RMII-CRSDV
-    P_D5    = PC_4,   // RMII-RXD0
-    P_D6    = PC_5,   // RMII-RXD1
-    P_D8    = PA_1,   // RMII-REFCLK
+    P_D1       = PB_12,  // RMII-TXD0
+    P_D2       = PB_13,  // RMII-TXD1
+    P_D3       = PB_11,  // RMII-TXEN
+    P_D4       = PA_7,   // RMII-CRSDV
+    P_D5       = PC_4,   // RMII-RXD0
+    P_D6       = PC_5,   // RMII-RXD1
+    P_D8       = PA_1,   // RMII-REFCLK
     // TP
-    P_TP5   = PB_4,   // NTRST
-    P_TP7   = PA_13,  // TMS  SWDIO
-    P_TP8   = PA_15,  // TDI
-    P_TP9   = PA_14,  // TCK  SWCLK
-    P_TP10  = PB_3,   // TDO 
-    //P_TP11,         // BOOT0 		
-
-    // Board Pins
-    // A0-A5
-    A0      = PF_6,  // AI4
-    A1      = PA_3,  // AI3
-    A2      = PC_2,  // AI12
-    A3      = PF_7,  // LPOCLK, not AI
-    A4      = PG_4,  // not AI
-    A5      = PE_0,  // not AI
-    // D0-D15
-    D0      = PD_9,   // UART3-RX
-    D1      = PD_8,   // UART3-TX
-    D2      = PA_10,  // UART1-RX
-    D3      = PA_11,  // CAN1-RX
-    D4      = PA_12,  // CAN1-TX
-    D5      = PB_8,
-    D6      = PD_11,  // UART3-CTS
-    D7      = PD_12,  // UART3-RTS
-    D8      = PA_9,   // UART1-TX
-    D9      = PE_9,   // SDCard-CS
-    D10     = PE_11,  // SSEL
-    D11     = PE_14,  // MOSI
-    D12     = PE_13,  // MISO
-    D13     = PE_12,  // SCK
-    D14     = PF_0,   // SDA
-    D15     = PF_1,   // SCL
-    // Internal
-    LED1    = PE_0,   // Red / Mode
-    LED2    = PB_6,   // Green / Switch-1
-    LED3    = PB_8,   // Blue
-    LED4    = D10,
-    SW0     = PF_2,   // Switch-0
-    SW1     = PB_6,   // Green / Switch-1
+    P_TP5      = PB_4,   // NTRST
+    P_TP7      = PA_13,  // TMS  SWDIO
+    P_TP8      = PA_15,  // TDI
+    P_TP9      = PA_14,  // TCK  SWCLK
+    P_TP10     = PB_3,   // TDO
+    //P_TP11,         // BOOT0
 
-    LED_RED   = LED1,
-    LED_GREEN = LED2,
-    LED_BLUE  = LED3,
+    // Internal
+    LED1       = PD_9,
+    LED2       = PA_12,
+    LED3       = PD_8,
+    LED4       = PA_11,
+    LED5       = PC_2,
+    LED6       = PA_3,
+    LED7       = PF_6,
+    LED_RED    = PE_0,
+    LED_GREEN  = PB_6,
+    LED_BLUE   = PB_8,
+    SW1        = PF_2,
+    SW2        = PG_4,
 
     // Standardized button names
-    BUTTON1 = SW0,
-    BUTTON2 = SW1,
-
-    // ST-Link
-    USBRX   = PA_10,
-    USBTX   = PA_9,
-    SWDIO   = PA_15, 
-    SWCLK   = PA_14, 
-    NTRST   = PB_4,  
+    BUTTON1    = SW1,
+    BUTTON2    = SW2,
+    
+    I2C_SDA    = PF_0,
+    I2C_SCL    = PF_1,
+    SPI0_MOSI  = PE_14,
+    SPI0_MISO  = PE_13,
+    SPI0_SCK   = PE_12,
+    SPI0_CS    = PE_11,
+    SPI1_CS    = PE_9,
+    
+    SPI_MOSI   = SPI0_MOSI,
+    SPI_MISO   = SPI0_MISO,
+    SPI_SCK    = SPI0_SCK,
+    SPI_CS     = SPI0_CS,
+
+    // DAPLink
+    USBRX      = MBED_CONF_TARGET_USB_RX,
+    USBTX      = MBED_CONF_TARGET_USB_TX,
+    SWDIO      = PA_15,
+    SWCLK      = PA_14,
+    NTRST      = PB_4,
 
     // Not connected
-    NC = (int)0xFFFFFFFF
+    NC    = (int)0xFFFFFFFF
 } PinName;
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h
new file mode 100644
index 00000000000..e6b09b75023
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h
@@ -0,0 +1,196 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PA_0  = 0x00, PA_1  = 0x01, PA_2  = 0x02, PA_3  = 0x03,
+    PA_4  = 0x04, PA_5  = 0x05, PA_6  = 0x06, PA_7  = 0x07,
+    PA_8  = 0x08, PA_9  = 0x09, PA_10 = 0x0A, PA_11 = 0x0B,
+    PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F,
+
+    PB_0  = 0x10, PB_1  = 0x11, PB_2  = 0x12, PB_3  = 0x13,
+    PB_4  = 0x14, PB_5  = 0x15, PB_6  = 0x16, PB_7  = 0x17,
+    PB_8  = 0x18, PB_9  = 0x19, PB_10 = 0x1A, PB_11 = 0x1B,
+    PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F,
+
+    PC_0  = 0x20, PC_1  = 0x21, PC_2  = 0x22, PC_3  = 0x23,
+    PC_4  = 0x24, PC_5  = 0x25, PC_6  = 0x26, PC_7  = 0x27,
+    PC_8  = 0x28, PC_9  = 0x29, PC_10 = 0x2A, PC_11 = 0x2B,
+    PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, PC_15 = 0x2F,
+
+    PD_0  = 0x30, PD_1  = 0x31, PD_2  = 0x32, PD_3  = 0x33,
+    PD_4  = 0x34, PD_5  = 0x35, PD_6  = 0x36, PD_7  = 0x37,
+    PD_8  = 0x38, PD_9  = 0x39, PD_10 = 0x3A, PD_11 = 0x3B,
+    PD_12 = 0x3C, PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F,
+
+    PE_0  = 0x40, PE_1  = 0x41, PE_2  = 0x42, PE_3  = 0x43,
+    PE_4  = 0x44, PE_5  = 0x45, PE_6  = 0x46, PE_7  = 0x47,
+    PE_8  = 0x48, PE_9  = 0x49, PE_10 = 0x4A, PE_11 = 0x4B,
+    PE_12 = 0x4C, PE_13 = 0x4D, PE_14 = 0x4E, PE_15 = 0x4F,
+
+    PF_0  = 0x50, PF_1  = 0x51, PF_2  = 0x52, PF_3  = 0x53,
+    PF_4  = 0x54, PF_5  = 0x55, PF_6  = 0x56, PF_7  = 0x57,
+    PF_8  = 0x58, PF_9  = 0x59, PF_10 = 0x5A, PF_11 = 0x5B,
+    PF_12 = 0x5C, PF_13 = 0x5D, PF_14 = 0x5E, PF_15 = 0x5F,
+
+    PG_0  = 0x60, PG_1  = 0x61, PG_2  = 0x62, PG_3  = 0x63,
+    PG_4  = 0x64, PG_5  = 0x65, PG_6  = 0x66, PG_7  = 0x67,
+    PG_8  = 0x68, PG_9  = 0x69, PG_10 = 0x6A, PG_11 = 0x6B,
+    PG_12 = 0x6C, PG_13 = 0x6D, PG_14 = 0x6E, PG_15 = 0x6F,
+
+    PH_0  = 0x70, PH_1  = 0x71, PH_2  = 0x72, PH_3  = 0x73,
+    PH_4  = 0x74, PH_5  = 0x75, PH_6  = 0x76, PH_7  = 0x77,
+    PH_8  = 0x78, PH_9  = 0x79, PH_10 = 0x7A, PH_11 = 0x7B,
+    PH_12 = 0x7C, PH_13 = 0x7D, PH_14 = 0x7E, PH_15 = 0x7F,
+
+    // Module Pins
+    // A
+    P_A5       = PC_2,   // UART-DTR
+    P_A6       = PF_2,   // Switch-0
+    P_A7       = PE_0,   // Red, Mode
+    P_A8       = PB_6,   // Green, Switch-1
+    P_A9       = PB_8,   // Blue
+    P_A10      = PA_11,  // UART-CTS
+    P_A11      = PA_9,   // UART-TXD
+    P_A12      = PA_12,  // UART-RTS
+    P_A13      = PA_10,  // UART-RXD
+    P_A14      = PD_9,   // GPIO-0
+    P_A15      = PD_8,   // GPIO-1
+    P_A16      = PD_11,  // GPIO-2
+    P_A17      = PD_12,  // GPIO-3
+    P_A18      = PA_3,   // UART-DSR
+    // B
+    // C
+    P_C5       = PG_4,   // SPI-IRQ
+    P_C6       = PE_13,  // SPI-MISO
+    P_C8       = PE_12,  // Res
+    P_C10      = PE_14,  // SPI-MOSI
+    P_C11      = PE_11,  // SPI-CS0
+    P_C12      = PE_9,   // Res
+    P_C13      = PF_6,   // GPIO-4
+    P_C14      = PC_1,   // RMII-MDC
+    P_C15      = PA_2,   // RMII-MDIO
+    P_C16      = PF_7,   // GPIO-7
+    P_C17      = PF_1,   // I2C-SCL
+    P_C18      = PF_0,   // I2C-SDA
+	  // D
+    P_D1       = PB_12,  // RMII-TXD0
+    P_D2       = PB_13,  // RMII-TXD1
+    P_D3       = PB_11,  // RMII-TXEN
+    P_D4       = PA_7,   // RMII-CRSDV
+    P_D5       = PC_4,   // RMII-RXD0
+    P_D6       = PC_5,   // RMII-RXD1
+    P_D8       = PA_1,   // RMII-REFCLK
+    // TP
+    P_TP5      = PB_4,   // NTRST
+    P_TP7      = PA_13,  // TMS  SWDIO
+    P_TP8      = PA_15,  // TDI
+    P_TP9      = PA_14,  // TCK  SWCLK
+    P_TP10     = PB_3,   // TDO
+    //P_TP11,         // BOOT0
+
+    // Board Pins
+    // A0-A5
+    A0         = PF_6,  // AI4
+    A1         = PA_3,  // AI3
+    A2         = PC_2,  // AI12
+    A3         = PF_7,  // LPOCLK, not AI
+    A4         = PG_4,  // not AI
+    A5         = PE_0,  // not AI
+    // D0-D15
+    D0         = PD_9,   // UART3-RX
+    D1         = PD_8,   // UART3-TX
+    D2         = PA_10,  // UART1-RX
+    D3         = PA_11,  // CAN1-RX
+    D4         = PA_12,  // CAN1-TX
+    D5         = PB_8,
+    D6         = PD_11,  // UART3-CTS
+    D7         = PD_12,  // UART3-RTS
+    D8         = PA_9,   // UART1-TX
+    D9         = PE_9,   // SDCard-CS
+    D10        = PE_11,  // SSEL
+    D11        = PE_14,  // MOSI
+    D12        = PE_13,  // MISO
+    D13        = PE_12,  // SCK
+    D14        = PF_0,   // SDA
+    D15        = PF_1,   // SCL
+    // Internal
+    LED1       = PE_0,   // Red / Mode
+    LED2       = PB_6,   // Green / Switch-1
+    LED3       = PB_8,   // Blue
+    LED4       = D10,
+    LED_RED    = LED1,
+    LED_GREEN  = LED2,
+    LED_BLUE   = LED3,
+    SW0        = PF_2,   // Switch-0
+    SW1        = PB_6,   // Green / Switch-1
+    
+    I2C_SCL     = D15,
+    I2C_SDA     = D14,
+    SPI0_MOSI    = D11,
+    SPI0_MISO    = D12,
+    SPI0_SCK     = D13,
+    SPI0_CS      = D10,
+    SPI1_CS      = D9,
+    
+    SPI_MOSI   = SPI0_MOSI,
+    SPI_MISO   = SPI0_MISO,
+    SPI_SCK    = SPI0_SCK,
+    SPI_CS     = SPI0_CS,
+
+
+    // Standardized button names
+    BUTTON1    = SW0,
+    BUTTON2    = SW1,
+
+    // ST-Link
+    USBRX      = MBED_CONF_TARGET_USB_RX,
+    USBTX      = MBED_CONF_TARGET_USB_TX,
+    SWDIO      = PA_15,
+    SWCLK      = PA_14,
+    NTRST      = PB_4,
+
+    // Not connected
+    NC    = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/LICENSE b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/LICENSE
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/LICENSE
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/LICENSE
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/LICENSE-permissive-binary-license-1.0.txt b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/LICENSE-permissive-binary-license-1.0.txt
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diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar
new file mode 100644
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diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a
similarity index 69%
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rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a
index d87214a9242..1589afc3c35 100644
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diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h
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diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/bt_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/bt_types.h
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diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_assert.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_assert.h
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diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_conn_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_conn_man.h
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diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_man.h
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diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_pan.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_pan.h
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diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h
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rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial.h
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diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial_le.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial_le.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial_le.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_serial_le.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_utils.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_utils.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_utils.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_utils.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_cert_utils.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_cert_utils.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_cert_utils.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_cert_utils.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_comdefs.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_comdefs.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_comdefs.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_comdefs.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/wifi_emac/wifi_emac_api.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.h
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/wifi_emac/wifi_emac_api.h
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/system_clock.c
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/system_clock.c
rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/system_clock.c
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar
deleted file mode 100644
index 4273207630a..00000000000
Binary files a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar and /dev/null differ
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a
deleted file mode 100644
index 389522c320c..00000000000
Binary files a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a and /dev/null differ
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/hal_tick.h
index 19d9584eee3..cedecee5453 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/objects.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/objects.h
index a7e928ec3a8..ece5f1679fa 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 struct trng_s {
     RNG_HandleTypeDef handle;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c
index 48acec0abe1..4c2293602a8 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c
@@ -37,13 +37,6 @@
 #include "stm32f4xx.h"
 #include "mbed_assert.h"
 
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
-                                   This value must be a multiple of 0x200. */
-
-
 // clock source is selected with CLOCK_SOURCE in json config
 #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
 #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
@@ -97,13 +90,6 @@ void SystemInit(void)
     SystemInit_ExtMemCtl();
 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
 
-    /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
 }
 
 
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_GCC_ARM/STM32F446XE.ld b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_GCC_ARM/STM32F446XE.ld
index 5453f9629e6..e8fea5d8b20 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_GCC_ARM/STM32F446XE.ld
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_GCC_ARM/STM32F446XE.ld
@@ -1,7 +1,15 @@
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x08000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 512K
+#endif
+
 /* Linker script to configure memory regions. */
 MEMORY
-{ 
-  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
+{
+  FLASH (rx)   : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
   RAM (rwx)  : ORIGIN = 0x200001C4, LENGTH = 128k - 0x1C4
 }
 
@@ -9,7 +17,7 @@ MEMORY
  * with other linker script that defines memory regions FLASH and RAM.
  * It references following symbols, which must be defined in code:
  *   Reset_Handler : Entry of reset handler
- * 
+ *
  * It defines following symbols, which code can use without definition:
  *   __exidx_start
  *   __exidx_end
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/hal_tick.h
index 35154709357..dede60361a7 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/objects.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/objects.h
index a2e2ad0f34f..16467b7c876 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 #include "common_objects.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/hal_tick.h
index 90f6a00776c..7f7c8cb4f7a 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/objects.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/objects.h
index 0de614ff89a..bea7fef5477 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 struct trng_s {
     RNG_HandleTypeDef handle;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32F4/analogout_device.c b/targets/TARGET_STM/TARGET_STM32F4/analogout_device.c
index 802fad6bbb1..da07ad678bc 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/analogout_device.c
+++ b/targets/TARGET_STM/TARGET_STM32F4/analogout_device.c
@@ -36,7 +36,7 @@
 #include "PeripheralPins.h"
 
 void analogout_init(dac_t *obj, PinName pin) {
-    DAC_ChannelConfTypeDef sConfig;
+    DAC_ChannelConfTypeDef sConfig = {0};
 
     // Get the peripheral name (DAC_1, ...) from the pin and assign it to the object
     obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
@@ -71,6 +71,8 @@ void analogout_init(dac_t *obj, PinName pin) {
     __HAL_RCC_DAC_CLK_ENABLE();
 
     obj->handle.Instance = DAC;
+    obj->handle.State = HAL_DAC_STATE_RESET;
+
     if (HAL_DAC_Init(&obj->handle) != HAL_OK ) {
         error("HAL_DAC_Init failed");
     }
diff --git a/targets/TARGET_STM/TARGET_STM32F4/can_device.h b/targets/TARGET_STM/TARGET_STM32F4/can_device.h
index ffc85b663c2..16377c24c9f 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/can_device.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/can_device.h
@@ -17,7 +17,7 @@
 #define MBED_CAN_DEVICE_H
 
 #include "cmsis.h"
-#include "stm32f4xx_hal.h"
+#include "stm32f4xx.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -25,7 +25,26 @@ extern "C" {
 
 #ifdef DEVICE_CAN
 
-#define CAN_NUM 2 // Number of CAN peripherals present in the STM32 serie (1 or 2)
+#if defined(CAN3_BASE) && defined(CAN_3)
+
+#define CAN_NUM 3 // Number of CAN peripherals present in the STM32 serie
+
+#define CAN3_IRQ_RX_IRQN        CAN3_RX0_IRQn
+#define CAN3_IRQ_RX_VECT        CAN3_RX0_IRQHandler
+#define CAN3_IRQ_TX_IRQN        CAN3_TX_IRQn
+#define CAN3_IRQ_TX_VECT        CAN3_TX_IRQHandler
+#define CAN3_IRQ_ERROR_IRQN     CAN3_SCE_IRQn
+#define CAN3_IRQ_ERROR_VECT     CAN3_SCE_IRQHandler
+#define CAN3_IRQ_PASSIVE_IRQN   CAN3_SCE_IRQn
+#define CAN3_IRQ_PASSIVE_VECT   CAN3_SCE_IRQHandler
+#define CAN3_IRQ_BUS_IRQN       CAN3_SCE_IRQn
+#define CAN3_IRQ_BUS_VECT       CAN3_SCE_IRQHandler
+
+#else
+
+#define CAN_NUM 2 // Number of CAN peripherals present in the STM32 serie
+
+#endif
 
 #define CAN1_IRQ_RX_IRQN        CAN1_RX0_IRQn
 #define CAN1_IRQ_RX_VECT        CAN1_RX0_IRQHandler
diff --git a/targets/TARGET_STM/TARGET_STM32F4/common_objects.h b/targets/TARGET_STM/TARGET_STM32F4/common_objects.h
index d5d8a6c1849..3f39a9ce53b 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/common_objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F4/common_objects.h
@@ -133,6 +133,14 @@ struct dac_s {
 };
 #endif
 
+#if DEVICE_CAN
+struct can_s {
+    CAN_HandleTypeDef CanHandle;
+    int index;
+    int hz;
+};
+#endif
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_msp_template.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_msp_template.c
deleted file mode 100644
index 5f5a6ca1760..00000000000
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_msp_template.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_msp_template.c
-  * @author  MCD Application Team
-  * @version V1.4.1
-  * @date    09-October-2015
-  * @brief   This file contains the HAL System and Peripheral (PPP) MSP initialization
-  *          and de-initialization functions.
-  *          It should be copied to the application folder and renamed into 'stm32f4xx_hal_msp.c'.           
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup HAL_MSP HAL MSP
-  * @brief HAL MSP module.
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HAL_MSP_Private_Functions HAL MSP Private Functions
-  * @{
-  */
-
-/**
-  * @brief  Initializes the Global MSP.
-  * @note   This function is called from HAL_Init() function to perform system
-  *         level initialization (GPIOs, clock, DMA, interrupt).
-  * @retval None
-  */
-void HAL_MspInit(void)
-{
-
-}
-
-/**
-  * @brief  DeInitializes the Global MSP.
-  * @note   This functiona is called from HAL_DeInit() function to perform system
-  *         level de-initialization (GPIOs, clock, DMA, interrupt).
-  * @retval None
-  */
-void HAL_MspDeInit(void)
-{
-
-}
-
-/**
-  * @brief  Initializes the PPP MSP.
-  * @note   This functiona is called from HAL_PPP_Init() function to perform 
-  *         peripheral(PPP) system level initialization (GPIOs, clock, DMA, interrupt)
-  * @retval None
-  */
-void HAL_PPP_MspInit(void)
-{
-
-}
-
-/**
-  * @brief  DeInitializes the PPP MSP.
-  * @note   This functiona is called from HAL_PPP_DeInit() function to perform 
-  *         peripheral(PPP) system level de-initialization (GPIOs, clock, DMA, interrupt)
-  * @retval None
-  */
-void HAL_PPP_MspDeInit(void)
-{
-
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.c
index 5acd5c89bc5..e08f974c4ca 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.c
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.c
@@ -497,7 +497,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *
   */
 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
-  uint16_t* tmp;
   uint32_t tickstart = 0U;
   
   if(hsc->RxState == HAL_SMARTCARD_STATE_READY) 
@@ -527,8 +526,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p
       {
         return HAL_TIMEOUT;
       }
-      tmp = (uint16_t*) pData;
-      *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF);
+      *pData = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF);
       pData +=1U;
     }
 
diff --git a/targets/TARGET_STM/TARGET_STM32F4/flash_api.c b/targets/TARGET_STM/TARGET_STM32F4/flash_api.c
index 5e8f4a49108..5ba7fb9e495 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/flash_api.c
+++ b/targets/TARGET_STM/TARGET_STM32F4/flash_api.c
@@ -40,6 +40,16 @@ static uint32_t GetSector(uint32_t Address);
 static uint32_t GetSectorSize(uint32_t Sector);
 
 int32_t flash_init(flash_t *obj)
+{
+    return 0;
+}
+
+int32_t flash_free(flash_t *obj)
+{
+    return 0;
+}
+
+static int32_t flash_unlock(void)
 {
     /* Allow Access to Flash control registers and user Falsh */
     if (HAL_FLASH_Unlock()) {
@@ -48,9 +58,10 @@ int32_t flash_init(flash_t *obj)
         return 0;
     }
 }
-int32_t flash_free(flash_t *obj)
+
+static int32_t flash_lock(void)
 {
-    /* Disable the Flash option control register access (recommended to protect 
+    /* Disable the Flash option control register access (recommended to protect
     the option Bytes against possible unwanted operations) */
     if (HAL_FLASH_Lock()) {
         return -1;
@@ -58,18 +69,23 @@ int32_t flash_free(flash_t *obj)
         return 0;
     }
 }
+
 int32_t flash_erase_sector(flash_t *obj, uint32_t address)
 {
     /*Variable used for Erase procedure*/
     static FLASH_EraseInitTypeDef EraseInitStruct;
     uint32_t FirstSector;
     uint32_t SectorError = 0;
- 
+    int32_t status = 0;
+
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
+        return -1;
+    }
 
+    if (flash_unlock() != HAL_OK) {
         return -1;
     }
-   
+
     /* Get the 1st sector to erase */
     FirstSector = GetSector(address);
 
@@ -79,19 +95,26 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address)
     EraseInitStruct.Sector = FirstSector;
     EraseInitStruct.NbSectors = 1;
     if(HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK){
-        return -1;
-    } else {
-        return 0;
+        status = -1;
     }
+
+    flash_lock();
+
+    return status;
 }
 
 int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
 {
+    int32_t status = 0;
 
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
         return -1;
     }
 
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
   /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
      you have to make sure that these data are rewritten before they are accessed during code
      execution. If this cannot be done safely, it is recommended to flush the caches by setting the
@@ -105,21 +128,23 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
     __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
     __HAL_FLASH_DATA_CACHE_ENABLE();
 
-    while (size > 0) {
+    while ((size > 0) && (status == 0)) {
         if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, address, (uint64_t)*data) != HAL_OK) {
-            return -1;
+            status = -1;
         } else {
             size--;
             address++;
             data++;
         }
     }
-    return 0;
+
+    flash_lock();
+
+    return status;
 }
 
 uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
 {
-    
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
         return MBED_FLASH_INVALID_SIZE;
     }
@@ -139,7 +164,7 @@ uint32_t flash_get_start_address(const flash_t *obj)
 }
 uint32_t flash_get_size(const flash_t *obj)
 {
-    return FLASH_SIZE;    
+    return FLASH_SIZE;
 }
 
 /**
@@ -149,13 +174,15 @@ uint32_t flash_get_size(const flash_t *obj)
   */
 static uint32_t GetSector(uint32_t address)
 {
-    uint32_t sector = 0; 
+    uint32_t sector = 0;
     uint32_t tmp = address - ADDR_FLASH_SECTOR_0;
     /* This function supports 1Mb and 2Mb flash sizes */
 #if defined(ADDR_FLASH_SECTOR_16)
     if (address & 0x100000) { // handle 2nd bank
+        /*  Sector will be at least 12 */
         sector = FLASH_SECTOR_12;
-        tmp = address - ADDR_FLASH_SECTOR_12;
+        tmp -= 0x100000;
+        address -= 0x100000;
     }
 #endif
     if (address < ADDR_FLASH_SECTOR_4) { // 16k sectorsize
@@ -163,14 +190,14 @@ static uint32_t GetSector(uint32_t address)
     }
 #if defined(ADDR_FLASH_SECTOR_5)
     else if (address < ADDR_FLASH_SECTOR_5) { //64k sector size
-        sector += FLASH_SECTOR_4; 
+        sector += FLASH_SECTOR_4;
     } else {
         sector += 4 + (tmp >>17);
     }
 #else
     // In case ADDR_FLASH_SECTOR_5 is not defined, sector 4 is the last one.
     else { //64k sector size
-        sector += FLASH_SECTOR_4; 
+        sector += FLASH_SECTOR_4;
     }
 #endif
     return sector;
@@ -199,7 +226,7 @@ if((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_
         sectorsize = 64 * 1024;
     } else {
         sectorsize = 128 * 1024;
-    }  
+    }
     return sectorsize;
 }
 
diff --git a/targets/TARGET_STM/TARGET_STM32F4/serial_device.c b/targets/TARGET_STM/TARGET_STM32F4/serial_device.c
index 0cf5d9be77e..02a3811ccd4 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/serial_device.c
+++ b/targets/TARGET_STM/TARGET_STM32F4/serial_device.c
@@ -286,7 +286,7 @@ static void uart_irq(int id)
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
             if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) {
-                volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag
+                volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear ORE flag
             }
         }
     }
@@ -782,13 +782,13 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
 
 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
     if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
-        volatile uint32_t tmpval = huart->Instance->DR; // Clear PE flag
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag
     } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
-        volatile uint32_t tmpval = huart->Instance->DR; // Clear FE flag
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear FE flag
     } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_NE) != RESET) {
-        volatile uint32_t tmpval = huart->Instance->DR; // Clear NE flag
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear NE flag
     } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
-        volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear ORE flag
     }
 }
 
@@ -839,9 +839,9 @@ int serial_irq_handler_asynch(serial_t *obj)
     HAL_UART_IRQHandler(huart);
     
     // Abort if an error occurs
-    if (return_event & SERIAL_EVENT_RX_PARITY_ERROR ||
-            return_event & SERIAL_EVENT_RX_FRAMING_ERROR ||
-            return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
+    if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) ||
+        (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
+        (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
         return return_event;
     }
     
@@ -915,7 +915,7 @@ void serial_rx_abort_asynch(serial_t *obj)
     
     // clear flags
     __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
-    volatile uint32_t tmpval = huart->Instance->DR; // Clear errors flag
+    volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear errors flag
     
     // reset states
     huart->RxXferCount = 0;
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/hal_tick.h
index fa8cc979639..e67b911185d 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/objects.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/objects.h
index 52b8e159eba..28946911189 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 struct trng_s {
     RNG_HandleTypeDef handle;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/hal_tick.h
index fa8cc979639..e67b911185d 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/objects.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/objects.h
index 52b8e159eba..28946911189 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 struct trng_s {
     RNG_HandleTypeDef handle;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/hal_tick.h
index fa8cc979639..e67b911185d 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/objects.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/objects.h
index 52b8e159eba..28946911189 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 struct trng_s {
     RNG_HandleTypeDef handle;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/hal_tick.h
index fa8cc979639..e67b911185d 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/objects.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/objects.h
index 52b8e159eba..28946911189 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 struct trng_s {
     RNG_HandleTypeDef handle;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32F7/analogout_device.c b/targets/TARGET_STM/TARGET_STM32F7/analogout_device.c
index 8003d35a51c..d817d3d2808 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/analogout_device.c
+++ b/targets/TARGET_STM/TARGET_STM32F7/analogout_device.c
@@ -36,7 +36,7 @@
 #include "PeripheralPins.h"
 
 void analogout_init(dac_t *obj, PinName pin) {
-    DAC_ChannelConfTypeDef sConfig;
+    DAC_ChannelConfTypeDef sConfig = {0};
 
     // Get the peripheral name (DAC_1, ...) from the pin and assign it to the object
     obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
@@ -71,6 +71,8 @@ void analogout_init(dac_t *obj, PinName pin) {
     __DAC_CLK_ENABLE();
 
     obj->handle.Instance = DAC;
+    obj->handle.State = HAL_DAC_STATE_RESET;
+
     if (HAL_DAC_Init(&obj->handle) != HAL_OK ) {
         error("HAL_DAC_Init failed");
     }
diff --git a/targets/TARGET_STM/TARGET_STM32F7/can_device.h b/targets/TARGET_STM/TARGET_STM32F7/can_device.h
index 7f4f6bf253f..0581da55843 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/can_device.h
+++ b/targets/TARGET_STM/TARGET_STM32F7/can_device.h
@@ -17,7 +17,7 @@
 #define MBED_CAN_DEVICE_H
 
 #include "cmsis.h"
-#include "stm32f7xx_hal.h"
+#include "stm32f7xx.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -25,7 +25,26 @@ extern "C" {
 
 #ifdef DEVICE_CAN
 
-#define CAN_NUM 2 // Number of CAN peripherals present in the STM32 serie (1 or 2)
+#if defined(CAN3_BASE) && defined(CAN_3)
+
+#define CAN_NUM 3 // Number of CAN peripherals present in the STM32 serie
+
+#define CAN3_IRQ_RX_IRQN        CAN3_RX0_IRQn
+#define CAN3_IRQ_RX_VECT        CAN3_RX0_IRQHandler
+#define CAN3_IRQ_TX_IRQN        CAN3_TX_IRQn
+#define CAN3_IRQ_TX_VECT        CAN3_TX_IRQHandler
+#define CAN3_IRQ_ERROR_IRQN     CAN3_SCE_IRQn
+#define CAN3_IRQ_ERROR_VECT     CAN3_SCE_IRQHandler
+#define CAN3_IRQ_PASSIVE_IRQN   CAN3_SCE_IRQn
+#define CAN3_IRQ_PASSIVE_VECT   CAN3_SCE_IRQHandler
+#define CAN3_IRQ_BUS_IRQN       CAN3_SCE_IRQn
+#define CAN3_IRQ_BUS_VECT       CAN3_SCE_IRQHandler
+
+#else
+
+#define CAN_NUM 2 // Number of CAN peripherals present in the STM32 serie
+
+#endif
 
 #define CAN1_IRQ_RX_IRQN        CAN1_RX0_IRQn
 #define CAN1_IRQ_RX_VECT        CAN1_RX0_IRQHandler
diff --git a/targets/TARGET_STM/TARGET_STM32F7/common_objects.h b/targets/TARGET_STM/TARGET_STM32F7/common_objects.h
index ee81970f049..b3f02642c78 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/common_objects.h
+++ b/targets/TARGET_STM/TARGET_STM32F7/common_objects.h
@@ -132,6 +132,14 @@ struct flash_s {
     uint32_t dummy;
 };
 
+#if DEVICE_CAN
+struct can_s {
+    CAN_HandleTypeDef CanHandle;
+    int index;
+    int hz;
+};
+#endif
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.c
index 323c8aae5f8..14cd418e9ff 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.c
@@ -1063,33 +1063,54 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
   
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
 
-    /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
+  /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
   if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
   {
-    /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+    tickstart = HAL_GetTick();
+
+    /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
     {
       if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
       {
         /* Enable the write protection for RTC registers */
         __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-      
-        /* Process Unlocked */ 
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+        /* Process Unlocked */
         __HAL_UNLOCK(hrtc);
-      
+
         return HAL_TIMEOUT;
       }  
     }
   }
-  
+  /* Disable the Wake-Up timer */
+  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+
+  /* Clear flag Wake-Up */
+  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+
+  tickstart = HAL_GetTick();
+
+  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+    {
+      /* Enable the write protection for RTC registers */
+      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+      hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hrtc);
+
+      return HAL_TIMEOUT;
+    }
+  }
+
   /* Configure the Wakeup Timer counter */
   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
 
@@ -1098,15 +1119,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
 
   /* Configure the clock source */
   hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-  
+
   /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
-  
-  EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;
-  
-  /* Clear RTC Wake Up timer Flag */
-  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-  
+
+  __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
+
   /* Configure the Interrupt in the RTC_CR register */
   __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
   
diff --git a/targets/TARGET_STM/TARGET_STM32F7/flash_api.c b/targets/TARGET_STM/TARGET_STM32F7/flash_api.c
index 9fe41a5f491..a02c132fcd6 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/flash_api.c
+++ b/targets/TARGET_STM/TARGET_STM32F7/flash_api.c
@@ -38,14 +38,24 @@ static uint32_t GetSectorSize(uint32_t Sector);
 
 int32_t flash_init(flash_t *obj)
 {
-    /* Allow Access to Flash control registers and user Flash */
+    return 0;
+}
+int32_t flash_free(flash_t *obj)
+{
+    return 0;
+}
+
+static int32_t flash_unlock(void)
+{
+    /* Allow Access to Flash control registers and user Falsh */
     if (HAL_FLASH_Unlock()) {
         return -1;
     } else {
         return 0;
     }
 }
-int32_t flash_free(flash_t *obj)
+
+static int32_t flash_lock(void)
 {
     /* Disable the Flash option control register access (recommended to protect
     the option Bytes against possible unwanted operations) */
@@ -55,6 +65,7 @@ int32_t flash_free(flash_t *obj)
         return 0;
     }
 }
+
 int32_t flash_erase_sector(flash_t *obj, uint32_t address)
 {
     /* Variable used for Erase procedure */
@@ -62,11 +73,16 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address)
     FLASH_OBProgramInitTypeDef OBInit;
     uint32_t SectorId;
     uint32_t SectorError = 0;
+    int32_t status = 0;
 
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
         return -1;
     }
 
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
   /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
      you have to make sure that these data are rewritten before they are accessed during code
      execution. If this cannot be done safely, it is recommended to flush the caches by setting the
@@ -102,19 +118,27 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address)
     EraseInitStruct.NbSectors = 1;
 
     if(HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK){
-        return -1;
-    } else {
-        return 0;
+        status = -1;
     }
+
+    flash_lock();
+
+    return status;
 }
 
 int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
         uint32_t size)
 {
+    int32_t status = 0;
+
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
         return -1;
     }
 
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
   /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache,
      you have to make sure that these data are rewritten before they are accessed during code
      execution. If this cannot be done safely, it is recommended to flush the caches by setting the
@@ -123,17 +147,20 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
     __HAL_FLASH_ART_RESET();
     __HAL_FLASH_ART_ENABLE();
 
-    while (size > 0) {
+    while ((size > 0) && (status == 0)) {
         if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE,
                     address, (uint64_t)*data) != HAL_OK) {
-            return -1;
+            status = -1;
         } else {
             size--;
             address++;
             data++;
         }
     }
-    return 0;
+
+    flash_lock();
+
+    return status;
 }
 
 uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
diff --git a/targets/TARGET_STM/TARGET_STM32F7/serial_device.c b/targets/TARGET_STM/TARGET_STM32F7/serial_device.c
index 34f4fc7bbe1..a4bece18154 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/serial_device.c
+++ b/targets/TARGET_STM/TARGET_STM32F7/serial_device.c
@@ -763,9 +763,9 @@ int serial_irq_handler_asynch(serial_t *obj)
     HAL_UART_IRQHandler(huart);
     
     // Abort if an error occurs
-    if (return_event & SERIAL_EVENT_RX_PARITY_ERROR ||
-            return_event & SERIAL_EVENT_RX_FRAMING_ERROR ||
-            return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
+    if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) ||
+        (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
+        (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
         return return_event;
     }
     
@@ -838,7 +838,7 @@ void serial_rx_abort_asynch(serial_t *obj)
     __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
     
     // clear flags
-    volatile uint32_t tmpval = huart->Instance->RDR; // Clear RXNE
+    volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear RXNE
     __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
     __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
     __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/hal_tick.h
index 966ce876ae6..80a92081d32 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM21
 #define TIM_MST_IRQ  TIM21_IRQn
 #define TIM_MST_RCC  __TIM21_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM21()
 
 #define TIM_MST_RESET_ON   __TIM21_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM21_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/system_clock.c
index afe7ff433a5..f8bd4e85480 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/system_clock.c
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/system_clock.c
@@ -41,6 +41,9 @@
 #define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board - not provided by default)
 #define USE_PLL_HSI          0x2  // Use HSI internal clock
 
+// Uncomment to output the MCO on PA8 for debugging
+//#define DEBUG_MCO
+
 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
@@ -118,10 +121,6 @@ void SetSysClock(void)
             }
         }
     }
-
-    /* Output clock on MCO1 pin(PA8) for debugging purpose */
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
 }
 
 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
@@ -130,9 +129,10 @@ void SetSysClock(void)
 /******************************************************************************/
 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
 {
-    RCC_ClkInitTypeDef RCC_ClkInitStruct;
-    RCC_OscInitTypeDef RCC_OscInitStruct;
-    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+    RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
 
     /* Used to gain time after DeepSleep in case HSI is used */
     if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
@@ -144,11 +144,12 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
        regarding system frequency refer to product datasheet. */
     __PWR_CLK_ENABLE();
     __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+    __HAL_RCC_PWR_CLK_DISABLE();
 
     /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_HSI48;
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
     if (bypass == 0) {
-        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
+        RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* 8 MHz xtal on OSC_IN/OSC_OUT */
     } else {
         RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
     }
@@ -163,6 +164,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
         return 0; // FAIL
     }
 
+    /* Select HSI48 as USB clock source */
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+    
     /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
     RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
     RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
@@ -173,17 +181,30 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
         return 0; // FAIL
     }
 
-    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
-    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
-    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
-        return 0; // FAIL
-    }
+    /* Configure the clock recovery system (CRS) ********************************/
+    /* Enable CRS Clock */
+    __HAL_RCC_CRS_CLK_ENABLE();
+    /* Default Synchro Signal division factor (not divided) */
+    RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+    /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+    RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+    /* HSI48 is synchronized with USB SOF at 1KHz rate */
+    RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
+    RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+    /* Set the TRIM[5:0] to the default value */
+    RCC_CRSInitStruct.HSI48CalibrationValue = 0x20;
+    /* Start automatic synchronization */
+    HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
 
-    /* Output clock on MCO1 pin(PA8) for debugging purpose */
-    //if (bypass == 0)
-    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-    //else
-    //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+#ifdef DEBUG_MCO
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+    if (bypass == 0) { // Xtal used
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_2); // 16 MHz
+    }
+    else { // External clock used
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_4); // 8 MHz
+    }
+#endif
 
     return 1; // OK
 }
@@ -252,8 +273,10 @@ uint8_t SetSysClock_PLL_HSI(void)
     /* Start automatic synchronization */
     HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
 
-    /* Output clock on MCO1 pin(PA8) for debugging purpose */
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#ifdef DEBUG_MCO
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 32 MHz (not precise due to HSI not calibrated)
+#endif
 
     return 1; // OK
 }
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PeripheralPins.c
index 47cb630d20e..18df1cdc09c 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PeripheralPins.c
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PeripheralPins.c
@@ -1,6 +1,6 @@
 /* mbed Microcontroller Library
  *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
+ * Copyright (c) 2017, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -30,118 +30,126 @@
 
 #include "PeripheralPins.h"
 
-// =====
-// Note: Commented lines are alternative possibilities which are not used per default.
-//       If you change them, you will have also to modify the corresponding xxx_api.c file
-//       for pwmout, analogin, analogout, ...
-// =====
+//==============================================================================
+// Notes
+//
+// - The pins mentionned Px_y_ALTz are alternative possibilities which use other
+//   HW peripheral instances. You can use them the same way as any other "normal"
+//   pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+//   pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+//   the comment "Connected to xxx". The pin function may not work properly in this
+//   case. These pins may not be displayed on the board pinout image on mbed.org.
+//   Please read the board reference manual and schematic for more information.
+//
+//==============================================================================
 
 //*** ADC ***
 
 const PinMap PinMap_ADC[] = {
-    {PA_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0
-    {PA_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1
-    {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2
-    {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3
-    {PA_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4
-    {PA_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5
-    {PA_6,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC_IN6
-    {PA_7,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC_IN7
-    {PB_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC_IN8
-    {PB_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC_IN9
-    {NC,   NC,    0}
+    {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0
+    {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1
+//  {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 - Connected to STDIO_UART_TX
+    {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3
+    {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4
+    {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5
+    {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC_IN6
+    {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC_IN7
+    {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC_IN8
+    {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC_IN9
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_ADC_Internal[] = {
     {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
     {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
-    {NC,   NC,    0}
+    {NC, NC, 0}
 };
 
 //*** DAC ***
 
 const PinMap PinMap_DAC[] = {
-    {NC,   NC,    0}
+    {NC, NC, 0}
 };
 
-
 //*** I2C ***
 
 const PinMap PinMap_I2C_SDA[] = {
     {PA_10, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
     {PA_13, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C1)},
     {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
-    {NC,    NC,    0}
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_I2C_SCL[] = {
-    {PA_4,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C1)},
-    {PA_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
-    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
-    {NC,    NC,    0}
+    {PA_4, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C1)},
+    {PA_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
+    {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
+    {NC, NC, 0}
 };
 
 //*** PWM ***
 
-// TIM21 cannot be used because already used by the us_ticker
+// TIM21 (PWM_21) cannot be used because already used by the us_ticker
 const PinMap PinMap_PWM[] = {
-    {PA_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2,  1, 0)},  // TIM2_CH1
-    {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2,  2, 0)},  // TIM2_CH2
-//  {PA_2,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)},  // TIM21_CH1
-//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2,  3, 0)},  // TIM2_CH3 - used by STDIO TX
-//  {PA_3,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 2, 0)},  // TIM21_CH2
-    {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2,  4, 0)},  // TIM2_CH4
-    {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2,  1, 0)},  // TIM2_CH1
-    {PA_8,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2,  1, 0)},  // TIM2_CH1
-//  {PA_9,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM21, 2, 0)},  // TIM21_CH2
-//  {PA_10, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)},  // TIM21_CH1
-    {PA_10, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2,  3, 0)},  // TIM2_CH3
-//  {PA_11, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM21, 2, 0)},  // TIM21_CH2
-//  {PA_15, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2,  1, 0)},  // TIM2_CH1 - used by STDIO RX
-//  {PB_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2,  2, 0)},  // TIM2_CH2
-    {PB_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2,  3, 0)},  // TIM2_CH3
-    {PB_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2,  4, 0)},  // TIM2_CH4
-    {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2,  2, 0)},  // TIM2_CH2
-//  {PB_5,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM21, 1, 0)},  // TIM21_CH1
-    {PB_6,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2,  3, 0)},  // TIM2_CH3
-    {PB_7,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2,  4, 0)},  // TIM2_CH4
-    {NC,    NC,    0}
+    {PA_0,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2,  1, 0)}, // TIM2_CH1
+    {PA_1,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2,  2, 0)}, // TIM2_CH2
+//  {PA_2,      PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1 - Connected to STDIO_UART_TX
+//  {PA_2,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2,  3, 0)}, // TIM2_CH3 - Connected to STDIO_UART_TX
+//  {PA_3,      PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 2, 0)}, // TIM21_CH2
+    {PA_3,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2,  4, 0)}, // TIM2_CH4
+    {PA_5,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2,  1, 0)}, // TIM2_CH1
+    {PA_8,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2,  1, 0)}, // TIM2_CH1
+//  {PA_9,      PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM21, 2, 0)}, // TIM21_CH2
+//  {PA_10,     PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1
+    {PA_10,     PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2,  3, 0)}, // TIM2_CH3
+//  {PA_11,     PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM21, 2, 0)}, // TIM21_CH2
+//  {PA_15,     PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2,  1, 0)}, // TIM2_CH1 - Connected to STDIO_UART_RX
+    {PB_0,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2,  3, 0)}, // TIM2_CH3
+    {PB_0_ALT0, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2,  2, 0)}, // TIM2_CH2
+    {PB_1,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2,  4, 0)}, // TIM2_CH4
+    {PB_3,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2,  2, 0)}, // TIM2_CH2 - Connected to LED
+//  {PB_5,      PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM21, 1, 0)}, // TIM21_CH1
+    {PB_6,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2,  3, 0)}, // TIM2_CH3
+    {PB_7,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2,  4, 0)}, // TIM2_CH4
+    {NC, NC, 0}
 };
 
 //*** SERIAL ***
 
 const PinMap PinMap_UART_TX[] = {
-    {PA_1,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
-//  {PA_2,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
-    {PA_2,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PA_4,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
-    {PA_9,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-//  {PA_14, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
-    {PA_14, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-//  {PB_6,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
-    {PB_6,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)},
-    {NC,    NC,    0}
+    {PA_1,       LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
+    {PA_2,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to STDIO_UART_TX
+    {PA_2_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_TX (Warning: no LPUART_1 on STDIO_UART_RX = PA_15)
+    {PA_4,       LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
+    {PA_9,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PA_14,      UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PA_14_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
+    {PB_6,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)},
+    {PB_6_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_UART_RX[] = {
-//  {PA_0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
-    {PA_0,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)},
-//  {PA_3,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
-    {PA_3,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PA_10, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PA_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
-    {PA_15, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-//  {PB_7,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
-    {PB_7,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)},
-    {NC,    NC,    0}
+    {PA_0,      UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)},
+    {PA_0_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
+    {PA_3,      UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PA_3_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
+    {PA_10,     UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PA_13,     LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
+    {PA_15,     UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to STDIO_UART_RX
+    {PB_7,      UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)},
+    {PB_7_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_UART_RTS[] = {
     {PA_1,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PA_12, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
     {PB_0,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
     {PB_1,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
-    {PA_12, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {NC,    NC,       0}
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_UART_CTS[] = {
@@ -149,7 +157,7 @@ const PinMap PinMap_UART_CTS[] = {
     {PA_6,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
     {PA_7,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
     {PA_11, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {NC,    NC,       0}
+    {NC, NC, 0}
 };
 
 //*** SPI ***
@@ -159,7 +167,7 @@ const PinMap PinMap_SPI_MOSI[] = {
     {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
     {PB_1,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_SPI1)},
     {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {NC,    NC,    0}
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_SPI_MISO[] = {
@@ -168,18 +176,18 @@ const PinMap PinMap_SPI_MISO[] = {
     {PA_14, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
     {PB_0,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_SPI1)},
     {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {NC,    NC,    0}
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_SPI_SCLK[] = {
     {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
     {PA_13, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {NC,    NC,    0}
+    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // Connected to LED
+    {NC, NC, 0}
 };
 
 const PinMap PinMap_SPI_SSEL[] = {
     {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-//  {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, - used by STDIO RX
-    {NC,    NC,    0}
+//  {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // Connected to STDIO_UART_RX
+    {NC, NC, 0}
 };
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h
index adcd8901a8e..ca509321045 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h
@@ -33,15 +33,25 @@
 #include "cmsis.h"
 #include "PinNamesTypes.h"
 
+typedef enum {
+    ALT0  = 0x100,
+    ALT1  = 0x200,
+    ALT2  = 0x300,
+    ALT3  = 0x400
+} ALTx;
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 typedef enum {
     PA_0  = 0x00,
+    PA_0_ALT0 = PA_0|ALT0,
     PA_1  = 0x01,
     PA_2  = 0x02,
+    PA_2_ALT0 = PA_2|ALT0,
     PA_3  = 0x03,
+    PA_3_ALT0 = PA_3|ALT0,
     PA_4  = 0x04,
     PA_5  = 0x05,
     PA_6  = 0x06,
@@ -53,16 +63,20 @@ typedef enum {
     PA_12 = 0x0C,
     PA_13 = 0x0D,
     PA_14 = 0x0E,
+    PA_14_ALT0 = PA_14|ALT0,
     PA_15 = 0x0F,
 
     PB_0  = 0x10,
+    PB_0_ALT0 = PB_0|ALT0,
     PB_1  = 0x11,
     PB_2  = 0x12,
     PB_3  = 0x13,
     PB_4  = 0x14,
     PB_5  = 0x15,
     PB_6  = 0x16,
+    PB_6_ALT0 = PB_6|ALT0,
     PB_7  = 0x17,
+    PB_7_ALT0 = PB_7|ALT0,
 
     PC_14 = 0x2E,
     PC_15 = 0x2F,
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/hal_tick.h
index 7724b546fb4..4f43c6e22eb 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM21
 #define TIM_MST_IRQ  TIM21_IRQn
 #define TIM_MST_RCC  __TIM21_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM21()
 
 #define TIM_MST_RESET_ON   __TIM21_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM21_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PeripheralPins.c
index d8ffa050c8d..79f19e7239a 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PeripheralPins.c
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PeripheralPins.c
@@ -1,6 +1,6 @@
 /* mbed Microcontroller Library
  *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
+ * Copyright (c) 2017, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -30,18 +30,27 @@
 
 #include "PeripheralPins.h"
 
-// =====
-// Note: Commented lines are alternative possibilities which are not used per default.
-//       If you change them, you will have also to modify the corresponding xxx_api.c file
-//       for pwmout, analogin, analogout, ...
-// =====
+//==============================================================================
+// Notes
+//
+// - The pins mentionned Px_y_ALTz are alternative possibilities which use other
+//   HW peripheral instances. You can use them the same way as any other "normal"
+//   pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+//   pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+//   the comment "Connected to xxx". The pin function may not work properly in this
+//   case. These pins may not be displayed on the board pinout image on mbed.org.
+//   Please read the board reference manual and schematic for more information.
+//
+//==============================================================================
 
 //*** ADC ***
 
 const PinMap PinMap_ADC[] = {
     {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
     {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
-    {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+//  {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 - Connected to STDIO_UART_TX
     {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
     {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
     {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
@@ -84,8 +93,8 @@ const PinMap PinMap_I2C_SCL[] = {
 const PinMap PinMap_PWM[] = {
     {PA_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)},  // TIM2_CH1
     {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)},  // TIM2_CH2
-//  {PA_2,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1
-//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},  // TIM2_CH3 - used by STDIO TX
+//  {PA_2,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1 - Connected to STDIO_UART_TX
+//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},  // TIM2_CH3 - Connected to STDIO_UART_TX
 //  {PA_3,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 2, 0)}, // TIM21_CH2
     {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)},  // TIM2_CH4
     {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)},  // TIM2_CH1
@@ -95,10 +104,10 @@ const PinMap PinMap_PWM[] = {
     {PA_9,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 1, 0)}, // TIM22_CH1
     {PA_10, PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 2, 0)}, // TIM22_CH2
 //  {PA_11, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM21, 2, 0)}, // TIM21_CH2
-//  {PA_15, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)},  // TIM2_CH1 - used by STDIO RX
+//  {PA_15, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)},  // TIM2_CH1 - Connected to STDIO_UART_RX
     {PB_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 3, 0)},  // TIM2_CH3
     {PB_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 4, 0)},  // TIM2_CH4
-    {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)},  // TIM2_CH2 - used also to drive the LED
+    {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)},  // TIM2_CH2 - Connected to LED
     {PB_4,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 1, 0)}, // TIM22_CH1
     {PB_5,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 2, 0)}, // TIM22_CH2
 //  {PB_6,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM21, 1, 0)}, // TIM21_CH1
@@ -108,23 +117,23 @@ const PinMap PinMap_PWM[] = {
 //*** SERIAL ***
 
 const PinMap PinMap_UART_TX[] = {
-    {PA_2,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PA_9,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PA_14, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Warning: this pin is used by SWCLK
-    {PB_6,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)},
-//  {PA_2,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
-//  {PA_14, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
-    {NC,    NC,       0}
+    {PA_2,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to STDIO_UART_TX
+    {PA_2_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_TX
+    {PA_9,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PA_14,      UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to SWCLK
+    {PA_14_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},  // Connected to SWCLK
+    {PB_6,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)},
+    {NC,         NC,       0}
 };
 
 const PinMap PinMap_UART_RX[] = {
-    {PA_3,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PA_10, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PA_15, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PB_7,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)},
-//  {PA_3,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
-//  {PA_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
-    {NC,    NC,      0}
+    {PA_3,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PA_3_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
+    {PA_10,      UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PA_15,      UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to STDIO_UART_RX
+    {PB_7,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)},
+    {PA_13,      LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to SWDIO
+    {NC,         NC,      0}
 };
 
 const PinMap PinMap_UART_RTS[] = {
@@ -163,12 +172,12 @@ const PinMap PinMap_SPI_MISO[] = {
 
 const PinMap PinMap_SPI_SCLK[] = {
     {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // used also to drive the LED
+    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // Connected to LED
     {NC,    NC,    0}
 };
 
 const PinMap PinMap_SPI_SSEL[] = {
     {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-//  {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // used by STDIO RX
+//  {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // Connected to STDIO_UART_RX
     {NC,    NC,    0}
 };
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h
index adcd8901a8e..8302724210b 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h
@@ -37,11 +37,20 @@
 extern "C" {
 #endif
 
+typedef enum {
+    ALT0  = 0x100,
+    ALT1  = 0x200,
+    ALT2  = 0x300,
+    ALT3  = 0x400
+} ALTx;
+
 typedef enum {
     PA_0  = 0x00,
     PA_1  = 0x01,
     PA_2  = 0x02,
+    PA_2_ALT0 = PA_2|ALT0,
     PA_3  = 0x03,
+    PA_3_ALT0 = PA_3|ALT0,
     PA_4  = 0x04,
     PA_5  = 0x05,
     PA_6  = 0x06,
@@ -53,6 +62,7 @@ typedef enum {
     PA_12 = 0x0C,
     PA_13 = 0x0D,
     PA_14 = 0x0E,
+    PA_14_ALT0 = PA_14|ALT0,
     PA_15 = 0x0F,
 
     PB_0  = 0x10,
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/hal_tick.h
index 7724b546fb4..4f43c6e22eb 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM21
 #define TIM_MST_IRQ  TIM21_IRQn
 #define TIM_MST_RCC  __TIM21_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM21()
 
 #define TIM_MST_RESET_ON   __TIM21_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM21_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/hal_tick.h
index 7724b546fb4..4f43c6e22eb 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM21
 #define TIM_MST_IRQ  TIM21_IRQn
 #define TIM_MST_RCC  __TIM21_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM21()
 
 #define TIM_MST_RESET_ON   __TIM21_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM21_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/hal_tick.h
index 7724b546fb4..4f43c6e22eb 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM21
 #define TIM_MST_IRQ  TIM21_IRQn
 #define TIM_MST_RCC  __TIM21_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM21()
 
 #define TIM_MST_RESET_ON   __TIM21_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM21_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L0/analogout_device.c b/targets/TARGET_STM/TARGET_STM32L0/analogout_device.c
index dbf8f9cab12..499008b73a8 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/analogout_device.c
+++ b/targets/TARGET_STM/TARGET_STM32L0/analogout_device.c
@@ -40,7 +40,7 @@ static int channel1_used = 0;
 static int channel2_used = 0;
 
 void analogout_init(dac_t *obj, PinName pin) {
-    DAC_ChannelConfTypeDef sConfig;
+    DAC_ChannelConfTypeDef sConfig = {0};
 
     // Get the peripheral name from the pin and assign it to the object
     obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
@@ -74,6 +74,8 @@ void analogout_init(dac_t *obj, PinName pin) {
 
     // Configure DAC
     obj->handle.Instance = DAC;
+    obj->handle.State = HAL_DAC_STATE_RESET;
+
     if (HAL_DAC_Init(&obj->handle) != HAL_OK ) {
         error("HAL_DAC_Init failed");
     }
diff --git a/targets/TARGET_STM/TARGET_STM32L0/flash_api.c b/targets/TARGET_STM/TARGET_STM32L0/flash_api.c
index c4e5b4063c8..bd4a411cb02 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/flash_api.c
+++ b/targets/TARGET_STM/TARGET_STM32L0/flash_api.c
@@ -26,30 +26,50 @@
 
 int32_t flash_init(flash_t *obj)
 {
-    /* Unlock the Flash to enable the flash control register access *************/
-    HAL_FLASH_Unlock();
     return 0;
 }
 
 int32_t flash_free(flash_t *obj)
 {
-    /* Lock the Flash to disable the flash control register access (recommended
-     * to protect the FLASH memory against possible unwanted operation) *********/
-    HAL_FLASH_Lock();
     return 0;
 }
 
+static int32_t flash_unlock(void)
+{
+    /* Allow Access to Flash control registers and user Falsh */
+    if (HAL_FLASH_Unlock()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+static int32_t flash_lock(void)
+{
+    /* Disable the Flash option control register access (recommended to protect
+    the option Bytes against possible unwanted operations) */
+    if (HAL_FLASH_Lock()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
 int32_t flash_erase_sector(flash_t *obj, uint32_t address)
 {
-    uint32_t FirstPage = 0;
     uint32_t PAGEError = 0;
     FLASH_EraseInitTypeDef EraseInitStruct;
+    int32_t status = 0;
 
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
 
         return -1;
     }
 
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
     /* Clear OPTVERR bit set on virgin samples */
     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
 
@@ -65,16 +85,20 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address)
      DCRST and ICRST bits in the FLASH_CR register. */
 
     if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) {
-        return -1;
-    } else {
-        return 0;
+        status = -1;
     }
+
+    flash_lock();
+
+    return status;
+
 }
 
 int32_t flash_program_page(flash_t *obj, uint32_t address,
         const uint8_t *data, uint32_t size)
 {
     uint32_t StartAddress = 0;
+    int32_t status = 0;
 
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
         return -1;
@@ -85,6 +109,10 @@ int32_t flash_program_page(flash_t *obj, uint32_t address,
         return -1;
     }
 
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
     /* Program the user Flash area word by word */
     StartAddress = address;
 
@@ -92,7 +120,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address,
      *  parameters doesn't ensure  */
     if ((uint32_t) data % 4 != 0) {
         volatile uint32_t data32;
-        while (address < (StartAddress + size)) {
+        while ((address < (StartAddress + size)) && (status == 0)) {
             for (uint8_t i =0; i < 4; i++) {
                 *(((uint8_t *) &data32) + i) = *(data + i);
             }
@@ -101,21 +129,23 @@ int32_t flash_program_page(flash_t *obj, uint32_t address,
                 address = address + 4;
                 data = data + 4;
             } else {
-                return -1;
+                status = -1;
             }
         }
     } else { /*  case where data is aligned, so let's avoid any copy */
-        while (address < (StartAddress + size)) {
+        while ((address < (StartAddress + size)) && (status == 0)) {
             if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) {
                 address = address + 4;
                 data = data + 4;
             } else {
-                return -1;
+                status = -1;
             }
         }
     }
 
-    return 0;
+    flash_lock();
+
+    return status;
 }
 
 uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) {
diff --git a/targets/TARGET_STM/TARGET_STM32L0/serial_device.c b/targets/TARGET_STM/TARGET_STM32L0/serial_device.c
index cef163dd9c6..74107fd42fb 100644
--- a/targets/TARGET_STM/TARGET_STM32L0/serial_device.c
+++ b/targets/TARGET_STM/TARGET_STM32L0/serial_device.c
@@ -673,9 +673,9 @@ int serial_irq_handler_asynch(serial_t *obj)
     HAL_UART_IRQHandler(huart);
     
     // Abort if an error occurs
-    if (return_event & SERIAL_EVENT_RX_PARITY_ERROR ||
-            return_event & SERIAL_EVENT_RX_FRAMING_ERROR ||
-            return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
+    if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) ||
+        (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
+        (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
         return return_event;
     }
     
@@ -749,7 +749,7 @@ void serial_rx_abort_asynch(serial_t *obj)
     
     // clear flags
     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF | UART_CLEAR_FEF | UART_CLEAR_OREF);
-    volatile uint32_t tmpval = huart->Instance->RDR; // Clear RXNE flag
+    volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear RXNE flag
     
     // reset states
     huart->RxXferCount = 0;
diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/hal_tick.h
index 408bc75d4fe..f38bbe0fca0 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/hal_tick.h
index 408bc75d4fe..f38bbe0fca0 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/hal_tick.h
index dc2245e8f8a..15cb9f2c4e8 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PinNames.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PinNames.h
index 7060d7da3ca..4bf3b2f4464 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PinNames.h
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/PinNames.h
@@ -170,6 +170,22 @@ typedef enum {
     SE_IO           = PB_10,
     SE_CLK          = PB_11,
 
+#ifdef TARGET_FF1705_L151CC
+    // Arduino Headers
+    A0  = PA_0,
+    A1  = PB_0,
+    D0  = PA_10,
+    D1  = PA_9,
+    D2  = PA_11,
+    D3  = PA_12,
+    D10 = PB_12,
+    D11 = PB_15,
+    D12 = PB_14,
+    D13 = PB_13,
+    D14 = I2C_SDA,
+    D15 = I2C_SCL,
+#endif
+
     // Not connected
     NC = (int)0xFFFFFFFF
 } PinName;
diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/hal_tick.h
index dc2245e8f8a..15cb9f2c4e8 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c
index 2cb8919f9ac..e5f39de4f74 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c
@@ -37,6 +37,7 @@
 
 #include "stm32l1xx.h"
 #include "stdio.h"
+#include "mbed_debug.h"
 
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */
@@ -253,9 +254,7 @@ uint8_t SetSysClock_PLL_HSI(void)
 /******************************************************************************/
 void HardFault_Handler(void)
 {
-#if !defined(NDEBUG) || NDEBUG == 0
-    printf("Hard Fault\n");
-#endif
+    debug("Hard Fault\n");
     NVIC_SystemReset();
 }
 
diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_low_power.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_low_power.c
index cec303bd953..437a576ecb1 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_low_power.c
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_low_power.c
@@ -30,12 +30,7 @@
 
 #include "xdot_low_power.h"
 #include "stdio.h"
-
-#if defined(NDEBUG) && NDEBUG == 1
-#define xdot_lp_debug(...) do {} while(0)
-#else
-#define xdot_lp_debug(...) printf(__VA_ARGS__)
-#endif
+#include "mbed_debug.h"
 
 static uint32_t portA[6];
 static uint32_t portB[6];
@@ -236,7 +231,7 @@ void xdot_enter_stop_mode() {
     HSERCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL4;
     HSERCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV3;
     if (HAL_RCC_OscConfig(&HSERCC_OscInitStruct) != HAL_OK) {
-        xdot_lp_debug("OSC initialization failed - initiating soft reset\r\n");
+        debug("OSC initialization failed - initiating soft reset\r\n");
         NVIC_SystemReset();
     }
 
@@ -247,7 +242,7 @@ void xdot_enter_stop_mode() {
     RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
     RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
-        xdot_lp_debug("PLL initialization failed - initiating soft reset\r\n");
+        debug("PLL initialization failed - initiating soft reset\r\n");
         NVIC_SystemReset();
     }
 
@@ -260,7 +255,7 @@ void xdot_enter_stop_mode() {
         HSIRCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
         HAL_StatusTypeDef ret = HAL_RCC_OscConfig(&HSIRCC_OscInitStruct);
         if ( ret != HAL_OK ) {
-            xdot_lp_debug("HSI initialization failed - ADC will not function properly\r\n");
+            debug("HSI initialization failed - ADC will not function properly\r\n");
         }
     }
 
diff --git a/targets/TARGET_STM/TARGET_STM32L1/analogout_device.c b/targets/TARGET_STM/TARGET_STM32L1/analogout_device.c
index 7dd2cb7eac5..2220b7d592e 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/analogout_device.c
+++ b/targets/TARGET_STM/TARGET_STM32L1/analogout_device.c
@@ -40,7 +40,7 @@ static int pa4_used = 0;
 static int pa5_used = 0;
 
 void analogout_init(dac_t *obj, PinName pin) {
-    DAC_ChannelConfTypeDef sConfig;
+    DAC_ChannelConfTypeDef sConfig = {0};
 
     // Get the peripheral name (DAC_1, ...) from the pin and assign it to the object
     obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
@@ -68,6 +68,8 @@ void analogout_init(dac_t *obj, PinName pin) {
     obj->pin = pin;
 
     obj->handle.Instance = DAC;
+    obj->handle.State = HAL_DAC_STATE_RESET;
+
     if (HAL_DAC_Init(&obj->handle) != HAL_OK ) {
         error("HAL_DAC_Init failed");
     }
diff --git a/targets/TARGET_STM/TARGET_STM32L1/flash_api.c b/targets/TARGET_STM/TARGET_STM32L1/flash_api.c
index 1044830eeb0..5e6932071f0 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/flash_api.c
+++ b/targets/TARGET_STM/TARGET_STM32L1/flash_api.c
@@ -26,30 +26,50 @@
 
 int32_t flash_init(flash_t *obj)
 {
-    /* Unlock the Flash to enable the flash control register access *************/
-    HAL_FLASH_Unlock();
     return 0;
 }
 
 int32_t flash_free(flash_t *obj)
 {
-    /* Lock the Flash to disable the flash control register access (recommended
-     * to protect the FLASH memory against possible unwanted operation) *********/
-    HAL_FLASH_Lock();
     return 0;
 }
 
+static int32_t flash_unlock(void)
+{
+    /* Allow Access to Flash control registers and user Falsh */
+    if (HAL_FLASH_Unlock()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+static int32_t flash_lock(void)
+{
+    /* Disable the Flash option control register access (recommended to protect
+    the option Bytes against possible unwanted operations) */
+    if (HAL_FLASH_Lock()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
 int32_t flash_erase_sector(flash_t *obj, uint32_t address)
 {
-    uint32_t FirstPage = 0;
     uint32_t PAGEError = 0;
     FLASH_EraseInitTypeDef EraseInitStruct;
+    int32_t status = 0;
 
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
 
         return -1;
     }
 
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR | FLASH_FLAG_EOP | FLASH_FLAG_PGAERR | FLASH_FLAG_WRPERR);
     /* MBED HAL erases 1 sector at a time */
     /* Fill EraseInit structure*/
@@ -63,16 +83,20 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address)
      DCRST and ICRST bits in the FLASH_CR register. */
 
     if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) {
-        return -1;
-    } else {
-        return 0;
+        status = -1;
     }
+
+    flash_lock();
+
+    return status;
+
 }
 
 int32_t flash_program_page(flash_t *obj, uint32_t address,
         const uint8_t *data, uint32_t size)
 {
     uint32_t StartAddress = 0;
+    int32_t status = 0;
 
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
         return -1;
@@ -83,6 +107,10 @@ int32_t flash_program_page(flash_t *obj, uint32_t address,
         return -1;
     }
 
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
     /* Program the user Flash area word by word */
     StartAddress = address;
 
@@ -90,7 +118,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address,
      *  parameters doesn't ensure  */
     if ((uint32_t) data % 4 != 0) {
         volatile uint32_t data32;
-        while (address < (StartAddress + size)) {
+        while (address < (StartAddress + size) && (status == 0)) {
             for (uint8_t i =0; i < 4; i++) {
                 *(((uint8_t *) &data32) + i) = *(data + i);
             }
@@ -99,21 +127,23 @@ int32_t flash_program_page(flash_t *obj, uint32_t address,
                 address = address + 4;
                 data = data + 4;
             } else {
-                return -1;
+                status = -1;
             }
         }
     } else { /*  case where data is aligned, so let's avoid any copy */
-        while (address < (StartAddress + size)) {
+        while ((address < (StartAddress + size)) && (status == 0)) {
             if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, *((uint32_t*) data)) == HAL_OK) {
                 address = address + 4;
                 data = data + 4;
             } else {
-                return -1;
+                status = -1;
             }
         }
     }
 
-    return 0;
+    flash_lock();
+
+    return status;
 }
 
 uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) 
diff --git a/targets/TARGET_STM/TARGET_STM32L1/serial_device.c b/targets/TARGET_STM/TARGET_STM32L1/serial_device.c
index 3859270e225..bcf53156b05 100755
--- a/targets/TARGET_STM/TARGET_STM32L1/serial_device.c
+++ b/targets/TARGET_STM/TARGET_STM32L1/serial_device.c
@@ -203,7 +203,7 @@ static void uart_irq(int id)
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
             if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET) {
-                volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag
+                volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear ORE flag
             }
         }
     }
@@ -607,13 +607,13 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
 
 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
     if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
-        volatile uint32_t tmpval = huart->Instance->DR; // Clear PE flag
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag
     } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
-        volatile uint32_t tmpval = huart->Instance->DR; // Clear FE flag
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear FE flag
     } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_NE) != RESET) {
-        volatile uint32_t tmpval = huart->Instance->DR; // Clear NE flag
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear NE flag
     } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
-        volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear ORE flag
     }
 }
 
@@ -664,9 +664,9 @@ int serial_irq_handler_asynch(serial_t *obj)
     HAL_UART_IRQHandler(huart);
     
     // Abort if an error occurs
-    if (return_event & SERIAL_EVENT_RX_PARITY_ERROR ||
-            return_event & SERIAL_EVENT_RX_FRAMING_ERROR ||
-            return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
+    if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) ||
+        (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
+        (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
         return return_event;
     }
     
@@ -740,7 +740,7 @@ void serial_rx_abort_asynch(serial_t *obj)
     
     // clear flags
     __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
-    volatile uint32_t tmpval = huart->Instance->DR; // Clear errors flag
+    volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear errors flag
     
     // reset states
     huart->RxXferCount = 0;
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.c
index 279491f6acc..4713a839d7e 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.c
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.c
@@ -1,6 +1,6 @@
 /* mbed Microcontroller Library
  *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
+ * Copyright (c) 2017, STMicroelectronics
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -30,18 +30,27 @@
 
 #include "PeripheralPins.h"
 
-// =====
-// Note: Commented lines are alternative possibilities which are not used per default.
-//       If you change them, you will have also to modify the corresponding xxx_api.c file
-//       for pwmout, analogin, analogout, ...
-// =====
+//==============================================================================
+// Notes
+//
+// - The pins mentionned Px_y_ALTz are alternative possibilities which use other
+//   HW peripheral instances. You can use them the same way as any other "normal"
+//   pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+//   pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+//   the comment "Connected to xxx". The pin function may not work properly in this
+//   case. These pins may not be displayed on the board pinout image on mbed.org.
+//   Please read the board reference manual and schematic for more information.
+//
+//==============================================================================
 
 //*** ADC ***
 
 const PinMap PinMap_ADC[] = {
     {PA_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
     {PA_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
-//  {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 - used by STDIO_UART_TX
+//  {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 - Connected to STDIO_UART_TX
     {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
     {PA_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
     {PA_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
@@ -85,13 +94,13 @@ const PinMap PinMap_I2C_SCL[] = {
 
 //*** PWM ***
 
-// TIM2 cannot be used because already used by the us_ticker
+// TIM2 (PWM_2) cannot be used because already used by the us_ticker
 const PinMap PinMap_PWM[] = {
 //  {PA_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
     {PA_1,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},  // TIM15_CH1N
 //  {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2
-//  {PA_2,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},  // TIM15_CH1 - used by STDIO_UART_TX
-//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3
+//  {PA_2,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},  // TIM15_CH1 - Connected to STDIO_UART_TX
+//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3 - Connected to STDIO_UART_TX
     {PA_3,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},  // TIM15_CH2
 //  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4
 //  {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
@@ -103,7 +112,7 @@ const PinMap PinMap_PWM[] = {
     {PA_11, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)},  // TIM1_CH4
     {PB_0,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)},  // TIM1_CH2N
     {PB_1,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},  // TIM1_CH3N
-//  {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2
+//  {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2 - Connected to LED
     {PB_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)},  // TIM16_CH1N
     {NC,    NC,    0}
 };
@@ -111,27 +120,27 @@ const PinMap PinMap_PWM[] = {
 //*** SERIAL ***
 
 const PinMap PinMap_UART_TX[] = {
-//  {PA_2,  LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
-    {PA_2,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
-    {PA_9,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {PB_6,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {NC,    NC,    0}
+    {PA_2,      UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX
+    {PA_2_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX
+    {PA_9,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_6,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {NC,        NC,       0}
 };
 
 const PinMap PinMap_UART_RX[] = {
-//  {PA_3,  LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
-    {PA_3,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
-    {PA_10, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {PA_15, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)},
-    {PB_7,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {NC,    NC,    0}
+    {PA_3,      UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_3_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PA_10,     UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PA_15,     UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, // Connected to STDIO_UART_RX
+    {PB_7,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {NC,        NC,       0}
 };
 
 const PinMap PinMap_UART_RTS[] = {
     {PA_1,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
     {PA_12, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PB_1,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
-    {PB_3,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_3,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LED
     {NC,    NC,    0}
 };
 
@@ -146,34 +155,34 @@ const PinMap PinMap_UART_CTS[] = {
 //*** SPI ***
 
 const PinMap PinMap_SPI_MOSI[] = {
-    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-//  {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PB_5,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {NC,    NC,    0}
+    {PA_7,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_12,     SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_5,      SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_5_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {NC,        NC,    0}
 };
 
 const PinMap PinMap_SPI_MISO[] = {
-    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-//  {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PB_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {NC,    NC,    0}
+    {PA_6,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_11,     SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_4,      SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_4_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {NC,        NC,    0}
 };
 
 const PinMap PinMap_SPI_SCLK[] = {
-    {PA_1,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-//  {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PB_3,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {NC,    NC,    0}
+    {PA_1,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_5,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_3,      SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // Connected to LED
+    {PB_3_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // Connected to LED
+    {NC,        NC,    0}
 };
 
 const PinMap PinMap_SPI_SSEL[] = {
-//  {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PA_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {PB_0,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {NC,    NC,    0}
+    {PA_4,      SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PA_4_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_0,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {NC,        NC,    0}
 };
 
 //*** CAN ***
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h
index 8f7e2673cad..f0f0f79cac6 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h
@@ -33,6 +33,13 @@
 #include "cmsis.h"
 #include "PinNamesTypes.h"
 
+typedef enum {
+    ALT0  = 0x100,
+    ALT1  = 0x200,
+    ALT2  = 0x300,
+    ALT3  = 0x400
+} ALTx;
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -41,8 +48,11 @@ typedef enum {
   PA_0  = 0x00,
   PA_1  = 0x01,
   PA_2  = 0x02,
+  PA_2_ALT0 = PA_2|ALT0,
   PA_3  = 0x03,
+  PA_3_ALT0 = PA_3|ALT0,
   PA_4  = 0x04,
+  PA_4_ALT0 = PA_4|ALT0,
   PA_5  = 0x05,
   PA_6  = 0x06,
   PA_7  = 0x07,
@@ -59,8 +69,11 @@ typedef enum {
   PB_1  = 0x11,
   PB_2  = 0x12,
   PB_3  = 0x13,
+  PB_3_ALT0 = PB_3|ALT0,
   PB_4  = 0x14,
+  PB_4_ALT0 = PB_4|ALT0,
   PB_5  = 0x15,
+  PB_5_ALT0 = PB_5|ALT0,
   PB_6  = 0x16,
   PB_7  = 0x17,
 
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l432xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l432xx.S
index 6362f5298d2..1b396032559 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l432xx.S
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l432xx.S
@@ -42,13 +42,13 @@
                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
                 EXPORT  __initial_sp
 
-__initial_sp    EQU     0x2000C000 ; Top of RAM, L4-ECC-SRAM2 retained in standby
+__initial_sp    EQU     0x20010000 ; Top of RAM
 
 ; <h> Heap Configuration
 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 
-Heap_Size       EQU     0x0BA00 ; 46KB (48KB, -2*1KB for main thread and scheduler)
+Heap_Size       EQU     0x0F800 ; 62KB (64KB, -2*1KB for main thread and scheduler)
 
                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
                 EXPORT  __heap_base
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/stm32l432xx.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/stm32l432xx.sct
index 184888d9125..9da54cc7c7e 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/stm32l432xx.sct
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/stm32l432xx.sct
@@ -36,12 +36,8 @@ LR_IROM1 0x08000000 0x40000  {    ; load region size_region
    .ANY (+RO)
   }
 
-  RW_IRAM1 0x20000000 0x0000C000  { ; RW data 48k L4-SRAM1
-   .ANY (+RW +ZI)
-  }
-
   ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
-  RW_IRAM2 (0x10000000+0x188) (0x04000-0x188)  {  ; RW data 16k L4-ECC-SRAM2 retained in standby
+  RW_IRAM1 (0x20000000+0x188) (0x00010000-0x188)  {
   .ANY (+RW +ZI)
   }
 
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/startup_stm32l432xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/startup_stm32l432xx.S
index 7a5810e6acf..a2f127a5395 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/startup_stm32l432xx.S
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/startup_stm32l432xx.S
@@ -39,7 +39,7 @@
 ;*
 ;*******************************************************************************
 
-__initial_sp    EQU     0x2000C000 ; Top of RAM, L4-ECC-SRAM2 retained in standby
+__initial_sp    EQU     0x20010000 ; Top of RAM
 
                 PRESERVE8
                 THUMB
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/stm32l432xx.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/stm32l432xx.sct
index cdb1c3c84c2..9da54cc7c7e 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/stm32l432xx.sct
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/stm32l432xx.sct
@@ -36,13 +36,9 @@ LR_IROM1 0x08000000 0x40000  {    ; load region size_region
    .ANY (+RO)
   }
 
-  RW_IRAM1 0x20000000 0x0000C000  { ; RW data 48k L4-SRAM1
-  .ANY (+RW +ZI)
-  }
-
   ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
-  RW_IRAM2 (0x10000000+0x188) (0x04000-0x188)  {  ; RW data 16k L4-ECC-SRAM2 retained in standby
-   .ANY (+RW +ZI)
+  RW_IRAM1 (0x20000000+0x188) (0x00010000-0x188)  {
+  .ANY (+RW +ZI)
   }
 
 }
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld
index b8f52e70e8e..04dcddcecea 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld
@@ -2,8 +2,7 @@
 MEMORY
 {
   FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
-  SRAM2 (rwx)  : ORIGIN = 0x10000188, LENGTH = 16k - 0x188
-  SRAM1 (rwx)  : ORIGIN = 0x20000000, LENGTH = 48k
+  SRAM1 (rwx)  : ORIGIN = 0x20000188, LENGTH = 64k - 0x188
 }
 
 /* Linker script to place sections and symbol values. Should be used together
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf
index 03920410070..9c478c51e2e 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf
@@ -5,20 +5,16 @@ define symbol __region_ROM_end__   = 0x0803FFFF;
 
 /* [RAM = 48kb + 16kb = 0xC000] */
 /* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */
-define symbol __NVIC_start__          = 0x10000000;
-define symbol __NVIC_end__            = 0x10000187; /* Aligned on 8 bytes (392 = 49 x 8) */
-define symbol __region_SRAM2_start__  = 0x10000188;
-define symbol __region_SRAM2_end__    = 0x10003FFF;
-define symbol __region_SRAM1_start__  = 0x20000000;
-define symbol __region_SRAM1_end__    = 0x2000BFFF;
+define symbol __NVIC_start__          = 0x20000000;
+define symbol __NVIC_end__            = 0x20000187; /* Aligned on 8 bytes (392 = 49 x 8) */
+define symbol __region_SRAM1_start__  = 0x20000188;
+define symbol __region_SRAM1_end__    = 0x2000FFFF;
 
 /* Memory regions */
 define memory mem with size = 4G;
 define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
-define region SRAM2_region = mem:[from __region_SRAM2_start__ to __region_SRAM2_end__];
 define region SRAM1_region = mem:[from __region_SRAM1_start__ to __region_SRAM1_end__];
 
-/* Stack 1/8 and Heap 1/4 of RAM */
 define symbol __size_cstack__ = 0x2000;
 define symbol __size_heap__   = 0x4000;
 define block CSTACK    with alignment = 8, size = __size_cstack__   { };
@@ -32,4 +28,3 @@ place at address mem:__intvec_start__ { readonly section .intvec };
 
 place in ROM_region   { readonly };
 place in SRAM1_region   { readwrite, block STACKHEAP };
-place in SRAM2_region { };
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h
index abb7956a000..49f64adf45c 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/cmsis_nvic.h
@@ -35,6 +35,6 @@
 // MCU Peripherals: 82 vectors = 328 bytes from 0x40 to 0x187
 // Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
 #define NVIC_NUM_VECTORS        98
-#define NVIC_RAM_VECTOR_ADDRESS 0x10000000    // Vectors positioned at start of SRAM2
+#define NVIC_RAM_VECTOR_ADDRESS SRAM1_BASE    // Vectors positioned at start of SRAM1
 
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h
index bdcb1570c38..934e8ed9d23 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h
index a7e928ec3a8..ece5f1679fa 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 struct trng_s {
     RNG_HandleTypeDef handle;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/hal_tick.h
index 315a9bf43fc..11cd6c10df8 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/objects.h
index a0dee029b45..e68c4eb6194 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 struct trng_s {
     RNG_HandleTypeDef handle;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralNames.h
new file mode 100644
index 00000000000..d260c726cb9
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralNames.h
@@ -0,0 +1,94 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE,
+    ADC_2 = (int)ADC2_BASE,
+    ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+    DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+    UART_1 = (int)USART1_BASE,
+    UART_2 = (int)USART2_BASE,
+    UART_3 = (int)USART3_BASE,
+    UART_4 = (int)UART4_BASE,
+    UART_5 = (int)UART5_BASE,
+    LPUART_1 = (int)LPUART1_BASE
+} UARTName;
+
+#define STDIO_UART_TX  PC_12
+#define STDIO_UART_RX  PD_2
+#define STDIO_UART     UART_5
+
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_2 = (int)SPI2_BASE,
+    SPI_3 = (int)SPI3_BASE
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+    I2C_2 = (int)I2C2_BASE,
+    I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+    PWM_1  = (int)TIM1_BASE,
+    PWM_2  = (int)TIM2_BASE,
+    PWM_3  = (int)TIM3_BASE,
+    PWM_4  = (int)TIM4_BASE,
+    PWM_5  = (int)TIM5_BASE,
+    PWM_8  = (int)TIM8_BASE,
+    PWM_15 = (int)TIM15_BASE,
+    PWM_16 = (int)TIM16_BASE,
+    PWM_17 = (int)TIM17_BASE
+} PWMName;
+
+typedef enum {
+    CAN_1 = (int)CAN1_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralPins.c
new file mode 100644
index 00000000000..b2cf6b0af1f
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralPins.c
@@ -0,0 +1,269 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+//       If you change them, you will have also to modify the corresponding xxx_api.c file
+//       for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+    {PA_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  5, 0)}, // IN5 - ARDUINO A0
+    {PA_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  6, 0)}, // IN6 - ARDUINO A1
+//  {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  7, 0)}, // IN7 // PA_2 is used as SERIAL_TX
+//  {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  8, 0)}, // IN8 // PA_3 is used as SERIAL_RX
+    {PA_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  9, 0)}, // IN9 - ARDUINO A2
+    {PA_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // IN10
+    {PA_6,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // IN11
+    {PA_7,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // IN12
+    {PB_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // IN15 - ARDUINO A3
+    {PB_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // IN16
+    {PC_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  1, 0)}, // IN1 - ARDUINO A5
+    {PC_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  2, 0)}, // IN2 - ARDUINO A4
+    {PC_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  3, 0)}, // IN3
+    {PC_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  4, 0)}, // IN4
+    {PC_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // IN13
+    {PC_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // IN14
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,  0, 0)},
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+    {NC,    NC,    0}
+};
+
+//*** DAC ***
+
+const PinMap PinMap_DAC[] = {
+    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // OUT1
+    {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // OUT2 (Warning: LED1 is also on this pin)
+    {NC,   NC,    0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PC_1,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PC_0,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {NC,    NC,    0}
+};
+
+//*** PWM ***
+
+// Warning: TIM5 cannot be used because already used by the us_ticker.
+const PinMap PinMap_PWM[] = {
+    {PA_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+//  {PA_0,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)},  // TIM5_CH1 (used by us_ticker)
+    {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2
+//  {PA_1,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)},  // TIM5_CH2 (used by us_ticker)
+//  {PA_1,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},// TIM15_CH1N
+//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3 // PA_2 is used as SERIAL_TX
+//  {PA_2,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)},  // TIM5_CH3 (used by us_ticker)
+//  {PA_2,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},// TIM15_CH1
+//  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4 // PA_3 is used as SERIAL_RX
+//  {PA_3,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)},  // TIM5_CH4 (used by us_ticker)
+//  {PA_3,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},// TIM15_CH2
+    {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+//  {PA_5,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)},  // TIM8_CH1N
+    {PA_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+//  {PA_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},// TIM16_CH1
+    {PA_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2 - ARDUINO D11
+//  {PA_7,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)},  // TIM1_CH1N
+//  {PA_7,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)},  // TIM8_CH1N
+//  {PA_7,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},// TIM17_CH1
+    {PA_8,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)},  // TIM1_CH1
+    {PA_9,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)},  // TIM1_CH2
+    {PA_10, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)},  // TIM1_CH3
+    {PA_11, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)},  // TIM1_CH4
+    {PA_15, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+    {PB_0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
+//  {PB_0,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)},  // TIM1_CH2N
+//  {PB_0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)},  // TIM8_CH2N
+    {PB_1,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
+//  {PB_1,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},  // TIM1_CH3N
+//  {PB_1,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)},  // TIM8_CH3N
+    {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2 - ARDUINO D3
+    {PB_4,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1 - ARDUINO D5
+    {PB_5,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+    {PB_6,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)},  // TIM4_CH1 - ARDUINO D10
+//  {PB_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)},// TIM16_CH1N
+    {PB_7,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)},  // TIM4_CH2
+//  {PB_7,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)},// TIM17_CH1N
+    {PB_8,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)},  // TIM4_CH3
+//  {PB_6,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},// TIM16_CH1
+    {PB_9,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)},  // TIM4_CH4
+//  {PB_9,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},// TIM17_CH1
+    {PB_10, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3 - ARDUINO D6
+    {PB_11, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4
+    {PB_13, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)},  // TIM1_CH1N
+//  {PB_13, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},// TIM15_CH1N
+    {PB_14, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)},  // TIM1_CH2N
+//  {PB_14, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},// TIM15_CH1
+//  {PB_14, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)},  // TIM8_CH2N
+    {PB_15, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},  // TIM1_CH3N
+//  {PB_15, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},// TIM15_CH2
+//  {PB_15, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)},  // TIM8_CH3N
+    {PC_6,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)},  // TIM8_CH1
+//  {PC_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+    {PC_7,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)},  // TIM8_CH2 - ARDUINO D9
+//  {PC_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+    {PC_8,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)},  // TIM8_CH3
+//  {PC_8,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
+    {PC_9,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)},  // TIM8_CH4
+//  {PC_9,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
+    {NC,    NC,     0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+    {PA_0,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_TX
+    {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_1,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_4,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+//  {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {PA_1,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_RX
+    {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_5,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+//  {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PD_2,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {PA_1,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+//  {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+//  {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // MEMs
+//  {PC_8,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)},
+//  {PD_4,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+//  {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4
+    {NC,    NC,     0}
+};
+ 
+const PinMap PinMap_UART_CTS[] = {
+    {PA_0,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+//  {PB_0,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+//  {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+//  {PC_9,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, 
+//  {PD_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+//  {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4
+    {NC,    NC,     0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D11
+    {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_3,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PG_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D12
+    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_2,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PG_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D13
+    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PG_9,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+//  {PA_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+//  {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_9,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PG_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_CAN_RD[] = {
+    {PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_CAN_TD[] = {
+    {PB_9 ,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PA_12,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {NC,    NC,    0}
+};
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PinNames.h
new file mode 100644
index 00000000000..7a919852018
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PinNames.h
@@ -0,0 +1,168 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PA_0  = 0x00,
+    PA_1  = 0x01,
+    PA_2  = 0x02,
+    PA_3  = 0x03,
+    PA_4  = 0x04,
+    PA_5  = 0x05,
+    PA_6  = 0x06,
+    PA_7  = 0x07,
+    PA_8  = 0x08,
+    PA_9  = 0x09,
+    PA_10 = 0x0A,
+    PA_11 = 0x0B,
+    PA_12 = 0x0C,
+    PA_13 = 0x0D,
+    PA_14 = 0x0E,
+    PA_15 = 0x0F,
+
+    PB_0  = 0x10,
+    PB_1  = 0x11,
+    PB_2  = 0x12,
+    PB_3  = 0x13,
+    PB_4  = 0x14,
+    PB_5  = 0x15,
+    PB_6  = 0x16,
+    PB_7  = 0x17,
+    PB_8  = 0x18,
+    PB_9  = 0x19,
+    PB_10 = 0x1A,
+    PB_11 = 0x1B,
+    PB_12 = 0x1C,
+    PB_13 = 0x1D,
+    PB_14 = 0x1E,
+    PB_15 = 0x1F,
+
+    PC_0  = 0x20,
+    PC_1  = 0x21,
+    PC_2  = 0x22,
+    PC_3  = 0x23,
+    PC_4  = 0x24,
+    PC_5  = 0x25,
+    PC_6  = 0x26,
+    PC_7  = 0x27,
+    PC_8  = 0x28,
+    PC_9  = 0x29,
+    PC_10 = 0x2A,
+    PC_11 = 0x2B,
+    PC_12 = 0x2C,
+    PC_13 = 0x2D,
+    PC_14 = 0x2E,
+    PC_15 = 0x2F,
+
+    PD_2  = 0x32,
+
+    PG_9  = 0x69,
+    PG_10 = 0x6A,
+    PG_11 = 0x6B,
+    PG_12 = 0x6C,
+
+    PH_0  = 0x70,
+    PH_1  = 0x71,
+
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
+    // Arduino connector namings
+    A0          = PA_0,
+    A1          = PA_1,
+    A2          = PA_4,
+    A3          = PB_0,
+    A4          = PC_1,
+    A5          = PC_0,
+    D0          = PA_3,
+    D1          = PA_2,
+    D2          = PA_10,
+    D3          = PB_3,
+    D4          = PB_5,
+    D5          = PB_4,
+    D6          = PB_10,
+    D7          = PA_8,
+    D8          = PA_9,
+    D9          = PC_7,
+    D10         = PB_6,
+    D11         = PA_7,
+    D12         = PA_6,
+    D13         = PA_5,
+    D14         = PB_9,
+    D15         = PB_8,
+
+    // Generic signals namings
+    LED1        = PG_12,
+    LED2        = PG_12,
+    LED3        = PG_12,
+    LED4        = PG_12,
+    USER_BUTTON = PC_13,
+    // Standardized button names
+    BUTTON1 = USER_BUTTON,
+    SERIAL_TX   = PC_12,
+    SERIAL_RX   = PD_2,
+    USBTX       = PC_12,
+    USBRX       = PD_2,
+    I2C_SCL     = PC_0,
+    I2C_SDA     = PC_1,
+    SPI_MOSI    = PG_11,
+    SPI_MISO    = PG_10,
+    SPI_SCK     = PG_9,
+    SPI_CS      = PG_12,
+    PWM_OUT     = PB_3,
+
+    //USB pins
+    USB_OTG_FS_SOF = PA_8,
+    USB_OTG_FS_VBUS = PA_9,
+    USB_OTG_FS_ID = PA_10,
+    USB_OTG_FS_DM = PA_11,
+    USB_OTG_FS_DP = PA_12,
+    USB_OTG_FS_NOE_ALT = PA_13,
+    USB_OTG_FS_NOE = PC_9,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c
new file mode 100644
index 00000000000..ee5ac4b40cb
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c
@@ -0,0 +1,361 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *                     | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)         | 80
+  * AHBCLK (MHz)        | 80
+  * APB1CLK (MHz)       | 80
+  * APB2CLK (MHz)       | 80
+  * USB capable         | YES
+  *-----------------------------------------------------------------------------
+**/
+
+#include "stm32l4xx.h"
+#include "nvic_addr.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI      0x2 // Use HSI internal clock
+#define USE_PLL_MSI      0x1 // Use MSI internal clock
+
+#define DEBUG_MCO        (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+uint8_t SetSysClock_PLL_MSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set MSION bit */
+    RCC->CR |= RCC_CR_MSION;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON , HSION, and PLLON bits */
+    RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x00001000;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIER = 0x00000000;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI()==0)
+#endif
+            {
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+                /* 4- If fail start with MSI clock */
+                if (SetSysClock_PLL_MSI() == 0)
+#endif
+                {
+                    while(1) {
+                        MBED_ASSERT(1);
+                    }
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Used to gain time after DeepSleep in case HSI is used
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+    }
+    RCC_OscInitStruct.HSIState              = RCC_HSI_OFF;
+    RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE; // 8 MHz
+    RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
+    RCC_OscInitStruct.PLL.PLLN              = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ              = 2;
+    RCC_OscInitStruct.PLL.PLLR              = 2; // PLL clock = 80 MHz (160 MHz / 2)
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz or 48 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 2
+    if (bypass == 0)
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    else
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSI oscillator and activate PLL with HSI as source
+    RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI; // 16 MHz
+    RCC_OscInitStruct.PLL.PLLM             = 2; // VCO input clock = 8 MHz (16 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLN             = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ             = 2;
+    RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 3
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+/******************************************************************************/
+/*            PLL (clocked by MSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_MSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+    // Enable LSE Oscillator to automatically calibrate the MSI clock
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+        RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+    }
+
+    HAL_RCCEx_DisableLSECSS();
+    /* Enable MSI Oscillator and activate PLL with MSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.MSIState             = RCC_MSI_ON;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_OFF;
+
+    RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_11; /* 48 MHz */
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
+    RCC_OscInitStruct.PLL.PLLM            = 6;    /* 8 MHz */
+    RCC_OscInitStruct.PLL.PLLN            = 40;   /* 320 MHz */
+    RCC_OscInitStruct.PLL.PLLP            = 7;    /* 45 MHz */
+    RCC_OscInitStruct.PLL.PLLQ            = 4;    /* 80 MHz */
+    RCC_OscInitStruct.PLL.PLLR            = 4;    /* 80 MHz */
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+    /* Enable MSI Auto-calibration through LSE */
+    HAL_RCCEx_EnableMSIPLLMode();
+    /* Select MSI output as USB clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         /* 80 MHz */
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 4
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/hal_tick.h
index 173f8e7cb9b..6c533d19975 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/objects.h
index a7e928ec3a8..ece5f1679fa 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 struct trng_s {
     RNG_HandleTypeDef handle;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/hal_tick.h
index 173f8e7cb9b..6c533d19975 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/hal_tick.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/objects.h
index a7e928ec3a8..ece5f1679fa 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/objects.h
@@ -54,11 +54,6 @@ struct port_s {
     __IO uint32_t *reg_out;
 };
 
-struct can_s {
-    CANName can;
-    int index;
-};
-
 struct trng_s {
     RNG_HandleTypeDef handle;
 };
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralNames.h
new file mode 100644
index 00000000000..c87dfc103ee
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralNames.h
@@ -0,0 +1,96 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE,
+    ADC_2 = (int)ADC2_BASE,
+    ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+    DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+    UART_1 = (int)USART1_BASE,
+    UART_2 = (int)USART2_BASE,
+    UART_3 = (int)USART3_BASE,
+    UART_4 = (int)UART4_BASE,
+    UART_5 = (int)UART5_BASE,
+    LPUART_1 = (int)LPUART1_BASE
+} UARTName;
+
+#define STDIO_UART_TX  SERIAL_TX
+#define STDIO_UART_RX  SERIAL_RX
+#define STDIO_UART     LPUART_1
+
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_2 = (int)SPI2_BASE,
+    SPI_3 = (int)SPI3_BASE
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+    I2C_2 = (int)I2C2_BASE,
+    I2C_3 = (int)I2C3_BASE,
+    I2C_4 = (int)I2C4_BASE
+} I2CName;
+
+typedef enum {
+    PWM_1  = (int)TIM1_BASE,
+    PWM_2  = (int)TIM2_BASE,
+    PWM_3  = (int)TIM3_BASE,
+    PWM_4  = (int)TIM4_BASE,
+    PWM_5  = (int)TIM5_BASE,
+    PWM_8  = (int)TIM8_BASE,
+    PWM_15 = (int)TIM15_BASE,
+    PWM_16 = (int)TIM16_BASE,
+    PWM_17 = (int)TIM17_BASE
+} PWMName;
+
+typedef enum {
+    CAN_1 = (int)CAN1_BASE,
+    CAN_2 = (int)CAN2_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c
new file mode 100644
index 00000000000..890c0e7842d
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c
@@ -0,0 +1,406 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentionned Px_y_ALTz are alternative possibilities which use other
+//   HW peripheral instances. You can use them the same way as any other "normal"
+//   pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+//   pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+//   the comment "Connected to xxx". The pin function may not work properly in this
+//   case. These pins may not be displayed on the board pinout image on mbed.org.
+//   Please read the board reference manual and schematic for more information.
+//
+//==============================================================================
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+    {PA_0,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+    {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5
+    {PA_1,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+    {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6
+    {PA_2,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+    {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7
+    {PA_3,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+    {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8
+    {PA_4,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+    {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9
+    {PA_5,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+    {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10
+    {PA_6,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+    {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11
+    {PA_7,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+    {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12
+    {PB_0,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 
+    {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 
+    {PB_1,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16
+    {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16
+    {PC_0,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+    {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1
+    {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1
+    {PC_1,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+    {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2
+    {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2
+    {PC_2,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+    {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3
+    {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3
+    {PC_3,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+    {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4
+    {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4
+    {PC_4,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+    {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13
+    {PC_5,      ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+    {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14
+    {PF_3,      ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6
+    {PF_4,      ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7
+    {PF_5,      ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8
+    {PF_6,      ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9
+    {PF_7,      ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10
+    {PF_8,      ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11
+    {PF_9,      ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12
+    {PF_10,     ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13
+    {NC,   NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,  0, 0)},
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+    {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+    {NC,    NC,    0}
+};
+
+//*** DAC ***
+
+const PinMap PinMap_DAC[] = {
+    {PA_4,  DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1
+    {PA_5,  DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2
+    {NC,   NC,    0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+    {PB_4,       I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {PB_7,       I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to LED2
+    {PB_7_ALT0,  I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, // Connected to LED2
+    {PB_9,       I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_11,      I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PB_11_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)},
+    {PB_14,      I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to LED3
+    {PC_1,       I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {PC_1_ALT0,  I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C4)},
+    {PC_9,       I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C3)},
+    {PD_13,      I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+    {PF_0,       I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PF_15,      I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+    {PG_8,       I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to STDIO_UART_RX
+    {PG_13,      I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {PA_7,       I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {PB_6,       I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_6_ALT0,  I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)},
+    {PB_8,       I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_10,      I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PB_10_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)},
+    {PB_13,      I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PC_0,       I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {PC_0_ALT0,  I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C4)},
+    {PD_12,      I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+    {PF_1,       I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PF_14,      I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+    {PG_7,       I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to STDIO_UART_TX
+    {PG_14,      I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {NC,    NC,    0}
+};
+
+//*** PWM ***
+// Warning: Pins using PWM_5 cannot be used as TIMER5 is already used by the us_ticker.
+
+const PinMap PinMap_PWM[] = {
+    {PA_0,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+//  {PA_0_ALT0,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)},  // TIM5_CH1
+    {PA_1,       PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},  // TIM15_CH1N
+    {PA_1_ALT0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2
+//  {PA_1_ALT1,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)},  // TIM5_CH2
+    {PA_2,       PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},  // TIM15_CH1
+    {PA_2_ALT0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3
+//  {PA_2_ALT1,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)},  // TIM5_CH3
+    {PA_3,       PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},  // TIM15_CH2
+    {PA_3_ALT0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4
+//  {PA_3_ALT1,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)},  // TIM5_CH4
+    {PA_5,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+    {PA_5_ALT0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)},  // TIM8_CH1N
+    {PA_6,       PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},  // TIM16_CH1
+    {PA_6_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+    {PA_7,       PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},  // TIM17_CH1
+    {PA_7_ALT0,  PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)},  // TIM1_CH1N
+    {PA_7_ALT1,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+    {PA_7_ALT2,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)},  // TIM8_CH1N
+    {PA_8,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)},  // TIM1_CH1
+    {PA_9,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)},  // TIM1_CH2
+    {PA_10,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)},  // TIM1_CH3
+    {PA_11,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)},  // TIM1_CH4
+    {PA_15,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
+    {PB_0,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)},  // TIM1_CH2N 
+    {PB_0_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3 
+    {PB_0_ALT1,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)},  // TIM8_CH2N 
+    {PB_1,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},  // TIM1_CH3N
+    {PB_1_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
+    {PB_1_ALT1,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)},  // TIM8_CH3N
+    {PB_3,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2
+    {PB_4,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+    {PB_5,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+    {PB_6,       PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)},  // TIM16_CH1N
+    {PB_6_ALT0,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)},  // TIM4_CH1
+    {PB_7,       PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)},  // TIM17_CH1N Connected to LED2
+    {PB_7_ALT0,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)},  // TIM4_CH2 Connected to LED2
+    {PB_8,       PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},  // TIM16_CH1 - ARDUINO D15
+    {PB_8_ALT0,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)},  // TIM4_CH3
+    {PB_9,       PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},  // TIM17_CH1 - ARDUINO D14
+    {PB_9_ALT0,  PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)},  // TIM4_CH4
+    {PB_10,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3
+    {PB_11,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4
+    {PB_13,      PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},  // TIM15_CH1N
+    {PB_13_ALT0, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)},  // TIM1_CH1N
+    {PB_14,      PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},  // TIM15_CH1 Connected to LED3
+    {PB_14_ALT0, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)},  // TIM1_CH2N Connected to LED3
+    {PB_14_ALT1, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)},  // TIM8_CH2N Connected to LED3
+    {PB_15,      PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},  // TIM15_CH2
+    {PB_15_ALT0, PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},  // TIM1_CH3N
+    {PB_15_ALT1, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)},  // TIM8_CH3N
+    {PC_6,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+    {PC_6_ALT0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)},  // TIM8_CH1
+    {PC_7,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2 Connected to LED1
+    {PC_7_ALT0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)},  // TIM8_CH2 Connected to LED1
+    {PC_8,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
+    {PC_8_ALT0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)},  // TIM8_CH3
+    {PC_9,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
+    {PC_9_ALT0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)},  // TIM8_CH4
+    {PD_12,      PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)},  // TIM4_CH1
+    {PD_13,      PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)},  // TIM4_CH2
+    {PD_14,      PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)},  // TIM4_CH3 - ARDUINO D10
+    {PD_15,      PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)},  // TIM4_CH4
+    {PE_0,       PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},  // TIM16_CH1
+    {PE_1,       PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},  // TIM17_CH1
+    {PE_3,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
+    {PE_4,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
+    {PE_5,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
+    {PE_6,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
+    {PE_8,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)},  // TIM1_CH1N
+    {PE_9,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)},  // TIM1_CH1 - ARDUINO D14
+    {PE_10,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)},  // TIM1_CH2N
+    {PE_11,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)},  // TIM1_CH2
+    {PE_12,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)},  // TIM1_CH3N
+    {PE_13,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)},  // TIM1_CH3 - ARDUINO D3
+    {PE_14,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)},  // TIM1_CH4
+//  {PF_6,       PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)},  // TIM5_CH1
+//  {PF_7,       PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)},  // TIM5_CH2
+//  {PF_8,       PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)},  // TIM5_CH3
+    {PF_9,       PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},  // TIM15_CH1
+//  {PF_9_ALT0,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)},  // TIM5_CH4
+    {PF_10,      PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},  // TIM15_CH2
+    {PG_9,       PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},  // TIM15_CH1N
+    {PG_10,      PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},  // TIM15_CH1
+    {PG_11,      PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},  // TIM15_CH2
+    {NC,    NC,    0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+    {PA_0,       UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PA_2,       LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PA_2_ALT0,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_9,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_6,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_10,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_11,      LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_1,       LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // ARDUINO A3
+    {PC_4,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // ARDUINO A4
+    {PC_10,      UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PC_10_ALT0, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_12,      UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {PD_5,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PD_8,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // ARDUINO D1
+    {PG_7,       LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX
+    {PG_9,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {PA_1,       UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PA_3,       LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // ARDUINO A0
+    {PA_3_ALT0,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // ARDUINO A0
+    {PA_10,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PA_15,      UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)},
+    {PB_7,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LED2
+    {PB_10,      LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_11,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_0,       LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // ARDUINO A1
+    {PC_5,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // ARDUINO A5
+    {PC_11,      UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PC_11_ALT0, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PD_2,       UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {PD_6,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PD_9,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PG_8,       LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_RX
+    {PG_10,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    {PA_1,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_12,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PA_15,      UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PA_15_ALT0, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_1,       LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_1_ALT0,  UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_3,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_4,       UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {PB_12,      LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_14,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LED3
+    {PD_2,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PD_4,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PD_12,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PG_6,       LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PG_12,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_UART_CTS[] = {
+    {PA_0,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_6,       LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // ARDUINO D12
+    {PA_6_ALT0,  UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // ARDUINO D12
+    {PA_11,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_4,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_5,       UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {PB_7,       UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to LED2
+    {PB_13,      LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_13_ALT0, UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PD_3,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PD_11,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PG_5,       LPUART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PG_11,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {NC,    NC,    0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {PA_7,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D11
+    {PA_12,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_5,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, 
+    {PB_5_ALT0,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_15,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, 
+    {PC_1,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, // ARDUINO A3
+    {PC_3,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // ARDUINO A2
+    {PC_12,      SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PD_4,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PE_15,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PG_4,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PG_11,      SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {PA_6,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D12
+    {PA_11,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_4,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_4_ALT0,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_14,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // Connected to LED3
+    {PC_2,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_11,      SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PD_3,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PE_14,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PG_3,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PG_10,      SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+    {PA_1,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_5,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D13
+    {PA_9,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)},
+    {PB_3,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_3_ALT0,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_10,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_13,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_10,      SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PD_1,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PD_3,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)},
+    {PE_13,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PG_2,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PG_9,       SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_4_ALT0,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PA_15,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},	
+    {PB_0,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, 
+    {PB_9,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // ARDUINO D14
+    {PB_12,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PD_0,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PE_12,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PG_5,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PG_12,      SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {NC,    NC,    0}
+};
+
+//*** CAN ***
+
+const PinMap PinMap_CAN_RD[] = {
+    {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PB_5,  CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_CAN2)},
+    {PB_8,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // ARDUINO D15
+    {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_CAN2)},
+    {PD_0,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_CAN_TD[] = {
+    {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PB_6,  CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN2)},
+    {PB_9,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // ARDUINO D14
+    {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_CAN2)},
+    {PD_1,  CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {NC,    NC,    0}
+};
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h
new file mode 100644
index 00000000000..e51ea37f501
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h
@@ -0,0 +1,286 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ALT0  = 0x100,
+    ALT1  = 0x200,
+    ALT2  = 0x300,
+    ALT3  = 0x400
+} ALTx;
+
+typedef enum {
+    PA_0  = 0x00,
+    PA_0_ALT0 = PA_0|ALT0,
+    PA_1  = 0x01,
+    PA_1_ALT0 = PA_1|ALT0,
+    PA_1_ALT1 = PA_1|ALT1,
+    PA_2  = 0x02,
+    PA_2_ALT0 = PA_2|ALT0,
+    PA_2_ALT1 = PA_2|ALT1,
+    PA_3  = 0x03,
+    PA_3_ALT0 = PA_3|ALT0,
+    PA_3_ALT1 = PA_3|ALT1,
+    PA_4  = 0x04,
+    PA_4_ALT0 = PA_4|ALT0,
+    PA_5  = 0x05,
+    PA_5_ALT0 = PA_5|ALT0,
+    PA_6  = 0x06,
+    PA_6_ALT0 = PA_6|ALT0,
+    PA_7  = 0x07,
+    PA_7_ALT0 = PA_7|ALT0,
+    PA_7_ALT1 = PA_7|ALT1,
+    PA_7_ALT2 = PA_7|ALT2,
+    PA_8  = 0x08,
+    PA_9  = 0x09,
+    PA_10 = 0x0A,
+    PA_11 = 0x0B,
+    PA_12 = 0x0C,
+    PA_13 = 0x0D,
+    PA_14 = 0x0E,
+    PA_15 = 0x0F,
+    PA_15_ALT0 = PA_15|ALT0,
+
+    PB_0  = 0x10,
+    PB_0_ALT0 = PB_0|ALT0,
+    PB_0_ALT1 = PB_0|ALT1,
+    PB_1  = 0x11,
+    PB_1_ALT0 = PB_1|ALT0,
+    PB_1_ALT1 = PB_1|ALT1,
+    PB_2  = 0x12,
+    PB_3  = 0x13,
+    PB_3_ALT0 = PB_3|ALT0,
+    PB_4  = 0x14,
+    PB_4_ALT0 = PB_4|ALT0,
+    PB_5  = 0x15,
+    PB_5_ALT0 = PB_5|ALT0,
+    PB_6  = 0x16,
+    PB_6_ALT0 = PB_6|ALT0,
+    PB_7  = 0x17,
+    PB_7_ALT0 = PB_7|ALT0,
+    PB_8  = 0x18,
+    PB_8_ALT0 = PB_8|ALT0,
+    PB_9  = 0x19,
+    PB_9_ALT0 = PB_9|ALT0,
+    PB_10 = 0x1A,
+    PB_10_ALT0 = PB_10|ALT0,
+    PB_11 = 0x1B,
+    PB_11_ALT0 = PB_11|ALT0,
+    PB_12 = 0x1C,
+    PB_13 = 0x1D,
+    PB_13_ALT0 = PB_13|ALT0,
+    PB_14 = 0x1E,
+    PB_14_ALT0 = PB_14|ALT0,
+    PB_14_ALT1 = PB_14|ALT1,
+    PB_15 = 0x1F,
+    PB_15_ALT0 = PB_15|ALT0,
+    PB_15_ALT1 = PB_15|ALT1,
+
+    PC_0  = 0x20,
+    PC_0_ALT0 = PC_0|ALT0,
+    PC_0_ALT1 = PC_0|ALT1,
+    PC_1  = 0x21,
+    PC_1_ALT0 = PC_1|ALT0,
+    PC_1_ALT1 = PC_1|ALT1,
+    PC_2  = 0x22,
+    PC_2_ALT0 = PC_2|ALT0,
+    PC_2_ALT1 = PC_2|ALT1,
+    PC_3  = 0x23,
+    PC_3_ALT0 = PC_3|ALT0,
+    PC_3_ALT1 = PC_3|ALT1,
+    PC_4  = 0x24,
+    PC_4_ALT0 = PC_4|ALT0,
+    PC_5  = 0x25,
+    PC_5_ALT0 = PC_5|ALT0,
+    PC_6  = 0x26,
+    PC_6_ALT0 = PC_6|ALT0,
+    PC_7  = 0x27,
+    PC_7_ALT0 = PC_7|ALT0,
+    PC_8  = 0x28,
+    PC_8_ALT0 = PC_8|ALT0,
+    PC_9  = 0x29,
+    PC_9_ALT0 = PC_9|ALT0,
+    PC_10 = 0x2A,
+    PC_10_ALT0 = PC_10|ALT0,
+    PC_11 = 0x2B,
+    PC_11_ALT0 = PC_11|ALT0,
+    PC_12 = 0x2C,
+    PC_13 = 0x2D,
+    PC_14 = 0x2E,
+    PC_15 = 0x2F,
+
+    PD_0  = 0x30,
+    PD_1  = 0x31,
+    PD_2  = 0x32,
+    PD_3  = 0x33,
+    PD_4  = 0x34,
+    PD_5  = 0x35,
+    PD_6  = 0x36,
+    PD_7  = 0x37,
+    PD_8  = 0x38,
+    PD_9  = 0x39,
+    PD_10 = 0x3A,
+    PD_11 = 0x3B,
+    PD_12 = 0x3C,
+    PD_13 = 0x3D,
+    PD_14 = 0x3E,
+    PD_15 = 0x3F,
+
+    PE_0  = 0x40,
+    PE_1  = 0x41,
+    PE_2  = 0x42,
+    PE_3  = 0x43,
+    PE_4  = 0x44,
+    PE_5  = 0x45,
+    PE_6  = 0x46,
+    PE_7  = 0x47,
+    PE_8  = 0x48,
+    PE_9  = 0x49,
+    PE_10 = 0x4A,
+    PE_11 = 0x4B,
+    PE_12 = 0x4C,
+    PE_13 = 0x4D,
+    PE_14 = 0x4E,
+    PE_15 = 0x4F,
+
+    PF_0  = 0x50,
+    PF_1  = 0x51,
+    PF_2  = 0x52,
+    PF_3  = 0x53,
+    PF_4  = 0x54,
+    PF_5  = 0x55,
+    PF_6  = 0x56,
+    PF_7  = 0x57,
+    PF_8  = 0x58,
+    PF_9  = 0x59,
+    PF_9_ALT0 = PF_9|ALT0,
+    PF_10 = 0x5A,
+    PF_11 = 0x5B,
+    PF_12 = 0x5C,
+    PF_13 = 0x5D,
+    PF_14 = 0x5E,
+    PF_15 = 0x5F,
+
+    PG_0  = 0x60,
+    PG_1  = 0x61,
+    PG_2  = 0x62,
+    PG_3  = 0x63,
+    PG_4  = 0x64,
+    PG_5  = 0x65,
+    PG_6  = 0x66,
+    PG_7  = 0x67,
+    PG_8  = 0x68,
+    PG_9  = 0x69,
+    PG_10 = 0x6A,
+    PG_11 = 0x6B,
+    PG_12 = 0x6C,
+    PG_13 = 0x6D,
+    PG_14 = 0x6E,
+    PG_15 = 0x6F,
+
+    PH_0  = 0x70,
+    PH_1  = 0x71,
+
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
+    // Arduino J3 connector namings
+    A0          = PA_3,
+    A1          = PC_0,
+    A2          = PC_3,
+    A3          = PC_1,
+    A4          = PC_4, 
+    A5          = PC_5, 
+    D0          = PD_9,
+    D1          = PD_8,
+    D2          = PF_15,
+    D3          = PE_13,
+    D4          = PF_14,
+    D5          = PE_11,
+    D6          = PE_9,
+    D7          = PF_13,
+    D8          = PF_12,
+    D9          = PD_15,
+    D10         = PD_14,
+    D11         = PA_7,
+    D12         = PA_6,
+    D13         = PA_5,
+    D14         = PB_9,
+    D15         = PB_8,
+
+    // Generic signals namings
+    LED1        = PC_7,
+    LED2        = PB_7,
+    LED3        = PB_14,
+    LED4        = LED1,
+    USER_BUTTON = PC_13,
+
+    // Standardized button names
+    BUTTON1 = USER_BUTTON,
+    SERIAL_TX   = PG_7, // Virtual Com Port 
+    SERIAL_RX   = PG_8, // Virtual Com Port
+    USBTX       = PG_7, // Virtual Com Port
+    USBRX       = PG_8, // Virtual Com Port
+    I2C_SCL     = D15, 
+    I2C_SDA     = D14,
+    SPI_MOSI    = D11,
+    SPI_MISO    = D12,
+    SPI_SCK     = D13,
+    SPI_CS      = D10,
+    PWM_OUT     = D9,
+
+    USB_OTG_FS_SOF = PA_8,
+    USB_OTG_FS_VBUS = PA_9,
+    USB_OTG_FS_ID = PA_10,
+    USB_OTG_FS_DM = PA_11,
+    USB_OTG_FS_DP = PA_12,
+    USB_OTG_FS_NOE_ALT = PA_13,
+    USB_OTG_FS_SOF_ALT = PA_14,
+    USB_OTG_FS_NOE = PC_9,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c
new file mode 100644
index 00000000000..e8d5be0049b
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c
@@ -0,0 +1,382 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *                     | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)         | 80
+  * AHBCLK (MHz)        | 80
+  * APB1CLK (MHz)       | 80
+  * APB2CLK (MHz)       | 80
+  * USB capable         | YES
+  *-----------------------------------------------------------------------------
+**/
+
+#include "stm32l4xx.h"
+#include "nvic_addr.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI      0x2 // Use HSI internal clock
+#define USE_PLL_MSI      0x1 // Use MSI internal clock
+
+#define DEBUG_MCO        (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+uint8_t SetSysClock_PLL_MSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set MSION bit */
+    RCC->CR |= RCC_CR_MSION;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON , HSION, and PLLON bits */
+    RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x00001000;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIER = 0x00000000;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI()==0)
+#endif
+            {
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+                /* 4- If fail start with MSI clock */
+                if (SetSysClock_PLL_MSI() == 0)
+#endif
+                {
+                    while(1) {
+                        MBED_ASSERT(1);
+                    }
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Used to gain time after DeepSleep in case HSI is used
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+    }
+    RCC_OscInitStruct.HSIState              = RCC_HSI_OFF;
+    RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE; // 8 MHz
+    RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
+    RCC_OscInitStruct.PLL.PLLN              = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ              = 2;
+    RCC_OscInitStruct.PLL.PLLR              = 2; // PLL clock = 80 MHz (160 MHz / 2)
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    /* Select HSI as clock source for LPUART1 */
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+    RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 2
+    if (bypass == 0)
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    else
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSI oscillator and activate PLL with HSI as source
+    RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI; // 16 MHz
+    RCC_OscInitStruct.PLL.PLLM             = 2; // VCO input clock = 8 MHz (16 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLN             = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ             = 2;
+    RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    /* Select HSI as clock source for LPUART1 */
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+    RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 3
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+/******************************************************************************/
+/*            PLL (clocked by MSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_MSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+    // Enable LSE Oscillator to automatically calibrate the MSI clock
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+        RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+    }
+
+    HAL_RCCEx_DisableLSECSS();
+    /* Enable MSI Oscillator and activate PLL with MSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.MSIState             = RCC_MSI_ON;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_OFF;
+    RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_11; /* 48 MHz */
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
+    RCC_OscInitStruct.PLL.PLLM            = 6;    /* 8 MHz */
+    RCC_OscInitStruct.PLL.PLLN            = 40;   /* 320 MHz */
+    RCC_OscInitStruct.PLL.PLLP            = 7;    /* 45 MHz */
+    RCC_OscInitStruct.PLL.PLLQ            = 4;    /* 80 MHz */
+    RCC_OscInitStruct.PLL.PLLR            = 4;    /* 80 MHz */
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+    /* Enable MSI Auto-calibration through LSE */
+    HAL_RCCEx_EnableMSIPLLMode();
+    /* Select MSI output as USB clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         /* 80 MHz */
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select LSE as clock source for LPUART1 */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+    PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 4
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l496xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l496xx.S
new file mode 100644
index 00000000000..ec2258b0d9b
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l496xx.S
@@ -0,0 +1,434 @@
+;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;* File Name          : startup_stm32l496xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.7.0
+;* Date               : 17-February-2017
+;* Description        : STM32L496xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+
+__initial_sp    EQU     0x20050000 ; Top of RAM
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x17800 ; 94KB (96KB, -2*1KB for main thread and scheduler)
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     ADC3_IRQHandler                   ; ADC3 global  Interrupt
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                 ; LP UART1 interrupt
+                DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+                DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     LCD_IRQHandler                    ; LCD global interrupt
+                DCD     0                                 ; Reserved 
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     CRS_IRQHandler                    ; CRS error
+                DCD     I2C4_EV_IRQHandler                ; I2C4 event
+                DCD     I2C4_ER_IRQHandler                ; I2C4 error
+                DCD     DCMI_IRQHandler                   ; DCMI global interrupt
+                DCD     CAN2_TX_IRQHandler                ; CAN2 TX
+                DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0
+                DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1
+                DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE
+                DCD     DMA2D_IRQHandler                  ; DMA2D global interrupt                    
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_2_IRQHandler                 [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     TIM3_IRQHandler                   [WEAK]
+        EXPORT     TIM4_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     DFSDM1_FLT3_IRQHandler                 [WEAK]
+        EXPORT     TIM8_BRK_IRQHandler               [WEAK]
+        EXPORT     TIM8_UP_IRQHandler                [WEAK]
+        EXPORT     TIM8_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM8_CC_IRQHandler                [WEAK]
+        EXPORT     ADC3_IRQHandler                   [WEAK]
+        EXPORT     FMC_IRQHandler                    [WEAK]
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]
+        EXPORT     TIM5_IRQHandler                   [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     UART4_IRQHandler                  [WEAK]
+        EXPORT     UART5_IRQHandler                  [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     DFSDM1_FLT0_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT1_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT2_IRQHandler            [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     OTG_FS_IRQHandler                 [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     QUADSPI_IRQHandler                [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SAI2_IRQHandler                   [WEAK]
+        EXPORT     SWPMI1_IRQHandler                 [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     LCD_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+        EXPORT     CRS_IRQHandler                    [WEAK]
+        EXPORT     I2C4_EV_IRQHandler                [WEAK]
+        EXPORT     I2C4_ER_IRQHandler                [WEAK]
+        EXPORT     DCMI_IRQHandler                   [WEAK]
+        EXPORT     CAN2_TX_IRQHandler                [WEAK]
+        EXPORT     CAN2_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN2_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN2_SCE_IRQHandler               [WEAK]
+        EXPORT     DMA2D_IRQHandler                  [WEAK]                  
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM1_FLT3_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC3_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+QUADSPI_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+SWPMI1_IRQHandler
+TSC_IRQHandler
+LCD_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler     
+CRS_IRQHandler     
+I2C4_EV_IRQHandler 
+I2C4_ER_IRQHandler 
+DCMI_IRQHandler    
+CAN2_TX_IRQHandler 
+CAN2_RX0_IRQHandler
+CAN2_RX1_IRQHandler
+CAN2_SCE_IRQHandler
+DMA2D_IRQHandler   
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_MICRO/stm32l496xx.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_MICRO/stm32l496xx.sct
new file mode 100644
index 00000000000..b7d0a9fccdc
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_MICRO/stm32l496xx.sct
@@ -0,0 +1,44 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; 1MB FLASH (0x100000) + 320KB SRAM (0xxxxx)
+LR_IROM1 0x08000000 0x100000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x100000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x1AC) (0x00500000-0x1AC)  { ; RW data 320k L4-SRAM1
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_STD/startup_stm32l496xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_STD/startup_stm32l496xx.S
new file mode 100644
index 00000000000..b233de792f3
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_STD/startup_stm32l496xx.S
@@ -0,0 +1,417 @@
+;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
+;* File Name          : startup_stm32l496xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.7.0
+;* Date               : 17-February-2017
+;* Description        : STM32L496xx Ultra Low Power devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+
+__initial_sp    EQU     0x20050000 ; Top of RAM
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+                DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+                DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+                DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+                DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+                DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     ADC3_IRQHandler                   ; ADC3 global  Interrupt
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+                DCD     COMP_IRQHandler                   ; COMP Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+                DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+                DCD     LPUART1_IRQHandler                 ; LP UART1 interrupt
+                DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+                DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+                DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface 1 global interrupt
+                DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+                DCD     LCD_IRQHandler                    ; LCD global interrupt
+                DCD     0                                 ; Reserved 
+                DCD     RNG_IRQHandler                    ; RNG global interrupt
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     CRS_IRQHandler                    ; CRS error
+                DCD     I2C4_EV_IRQHandler                ; I2C4 event
+                DCD     I2C4_ER_IRQHandler                ; I2C4 error
+                DCD     DCMI_IRQHandler                   ; DCMI global interrupt
+                DCD     CAN2_TX_IRQHandler                ; CAN2 TX
+                DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0
+                DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1
+                DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE
+                DCD     DMA2D_IRQHandler                  ; DMA2D global interrupt                    
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+        EXPORT     WWDG_IRQHandler                   [WEAK]
+        EXPORT     PVD_PVM_IRQHandler                [WEAK]
+        EXPORT     TAMP_STAMP_IRQHandler             [WEAK]
+        EXPORT     RTC_WKUP_IRQHandler               [WEAK]
+        EXPORT     FLASH_IRQHandler                  [WEAK]
+        EXPORT     RCC_IRQHandler                    [WEAK]
+        EXPORT     EXTI0_IRQHandler                  [WEAK]
+        EXPORT     EXTI1_IRQHandler                  [WEAK]
+        EXPORT     EXTI2_IRQHandler                  [WEAK]
+        EXPORT     EXTI3_IRQHandler                  [WEAK]
+        EXPORT     EXTI4_IRQHandler                  [WEAK]
+        EXPORT     DMA1_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel5_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA1_Channel7_IRQHandler          [WEAK]
+        EXPORT     ADC1_2_IRQHandler                 [WEAK]
+        EXPORT     CAN1_TX_IRQHandler                [WEAK]
+        EXPORT     CAN1_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN1_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN1_SCE_IRQHandler               [WEAK]
+        EXPORT     EXTI9_5_IRQHandler                [WEAK]
+        EXPORT     TIM1_BRK_TIM15_IRQHandler         [WEAK]
+        EXPORT     TIM1_UP_TIM16_IRQHandler          [WEAK]
+        EXPORT     TIM1_TRG_COM_TIM17_IRQHandler     [WEAK]
+        EXPORT     TIM1_CC_IRQHandler                [WEAK]
+        EXPORT     TIM2_IRQHandler                   [WEAK]
+        EXPORT     TIM3_IRQHandler                   [WEAK]
+        EXPORT     TIM4_IRQHandler                   [WEAK]
+        EXPORT     I2C1_EV_IRQHandler                [WEAK]
+        EXPORT     I2C1_ER_IRQHandler                [WEAK]
+        EXPORT     I2C2_EV_IRQHandler                [WEAK]
+        EXPORT     I2C2_ER_IRQHandler                [WEAK]
+        EXPORT     SPI1_IRQHandler                   [WEAK]
+        EXPORT     SPI2_IRQHandler                   [WEAK]
+        EXPORT     USART1_IRQHandler                 [WEAK]
+        EXPORT     USART2_IRQHandler                 [WEAK]
+        EXPORT     USART3_IRQHandler                 [WEAK]
+        EXPORT     EXTI15_10_IRQHandler              [WEAK]
+        EXPORT     RTC_Alarm_IRQHandler              [WEAK]
+        EXPORT     DFSDM1_FLT3_IRQHandler                 [WEAK]
+        EXPORT     TIM8_BRK_IRQHandler               [WEAK]
+        EXPORT     TIM8_UP_IRQHandler                [WEAK]
+        EXPORT     TIM8_TRG_COM_IRQHandler           [WEAK]
+        EXPORT     TIM8_CC_IRQHandler                [WEAK]
+        EXPORT     ADC3_IRQHandler                   [WEAK]
+        EXPORT     FMC_IRQHandler                    [WEAK]
+        EXPORT     SDMMC1_IRQHandler                 [WEAK]
+        EXPORT     TIM5_IRQHandler                   [WEAK]
+        EXPORT     SPI3_IRQHandler                   [WEAK]
+        EXPORT     UART4_IRQHandler                  [WEAK]
+        EXPORT     UART5_IRQHandler                  [WEAK]
+        EXPORT     TIM6_DAC_IRQHandler               [WEAK]
+        EXPORT     TIM7_IRQHandler                   [WEAK]
+        EXPORT     DMA2_Channel1_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel2_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel3_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel4_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel5_IRQHandler          [WEAK]
+        EXPORT     DFSDM1_FLT0_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT1_IRQHandler            [WEAK]
+        EXPORT     DFSDM1_FLT2_IRQHandler            [WEAK]
+        EXPORT     COMP_IRQHandler                   [WEAK]
+        EXPORT     LPTIM1_IRQHandler                 [WEAK]
+        EXPORT     LPTIM2_IRQHandler                 [WEAK]
+        EXPORT     OTG_FS_IRQHandler                 [WEAK]
+        EXPORT     DMA2_Channel6_IRQHandler          [WEAK]
+        EXPORT     DMA2_Channel7_IRQHandler          [WEAK]
+        EXPORT     LPUART1_IRQHandler                [WEAK]
+        EXPORT     QUADSPI_IRQHandler                [WEAK]
+        EXPORT     I2C3_EV_IRQHandler                [WEAK]
+        EXPORT     I2C3_ER_IRQHandler                [WEAK]
+        EXPORT     SAI1_IRQHandler                   [WEAK]
+        EXPORT     SAI2_IRQHandler                   [WEAK]
+        EXPORT     SWPMI1_IRQHandler                 [WEAK]
+        EXPORT     TSC_IRQHandler                    [WEAK]
+        EXPORT     LCD_IRQHandler                    [WEAK]
+        EXPORT     RNG_IRQHandler                    [WEAK]
+        EXPORT     FPU_IRQHandler                    [WEAK]
+        EXPORT     CRS_IRQHandler                    [WEAK]
+        EXPORT     I2C4_EV_IRQHandler                [WEAK]
+        EXPORT     I2C4_ER_IRQHandler                [WEAK]
+        EXPORT     DCMI_IRQHandler                   [WEAK]
+        EXPORT     CAN2_TX_IRQHandler                [WEAK]
+        EXPORT     CAN2_RX0_IRQHandler               [WEAK]
+        EXPORT     CAN2_RX1_IRQHandler               [WEAK]
+        EXPORT     CAN2_SCE_IRQHandler               [WEAK]
+        EXPORT     DMA2D_IRQHandler                  [WEAK]                  
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM15_IRQHandler
+TIM1_UP_TIM16_IRQHandler
+TIM1_TRG_COM_TIM17_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM1_FLT3_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC3_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+COMP_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+LPUART1_IRQHandler
+QUADSPI_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SAI1_IRQHandler
+SAI2_IRQHandler
+SWPMI1_IRQHandler
+TSC_IRQHandler
+LCD_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler     
+CRS_IRQHandler     
+I2C4_EV_IRQHandler 
+I2C4_ER_IRQHandler 
+DCMI_IRQHandler    
+CAN2_TX_IRQHandler 
+CAN2_RX0_IRQHandler
+CAN2_RX1_IRQHandler
+CAN2_SCE_IRQHandler
+DMA2D_IRQHandler   
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_STD/stm32l496xx.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_STD/stm32l496xx.sct
new file mode 100644
index 00000000000..b7d0a9fccdc
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_STD/stm32l496xx.sct
@@ -0,0 +1,44 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; 1MB FLASH (0x100000) + 320KB SRAM (0xxxxx)
+LR_IROM1 0x08000000 0x100000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x100000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x1AC) (0x00500000-0x1AC)  { ; RW data 320k L4-SRAM1
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_GCC_ARM/STM32L496XX.ld b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_GCC_ARM/STM32L496XX.ld
new file mode 100644
index 00000000000..628e11f0cf4
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_GCC_ARM/STM32L496XX.ld
@@ -0,0 +1,153 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{ 
+  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+  SRAM1 (rwx)  : ORIGIN = 0x200001AC, LENGTH = 320k - 0x1AC
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+    _sidata = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        _sdata = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+        _edata = .;
+
+    } > SRAM1
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        _sbss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+        _ebss = .;
+    } > SRAM1
+
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > SRAM1
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > SRAM1
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l496xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l496xx.S
new file mode 100644
index 00000000000..1e5ac5b16f4
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l496xx.S
@@ -0,0 +1,549 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l496xx.s
+  * @author    MCD Application Team
+  * @version   V1.1.1
+  * @date      29-April-2016
+  * @brief     STM32L496xx devices vector table GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Configure the clock system  
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+	.cpu cortex-m4
+	.fpu softvfp
+	.thumb
+
+.global	g_pfnVectors
+.global	Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word	_sidata
+/* start address for the .data section. defined in linker script */
+.word	_sdata
+/* end address for the .data section. defined in linker script */
+.word	_edata
+
+.equ  BootRAM,        0xF1E0F85F
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section	.text.Reset_Handler
+	.weak	Reset_Handler
+	.type	Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack    /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs	r1, #0
+  b	LoopCopyDataInit
+
+CopyDataInit:
+	ldr	r3, =_sidata
+	ldr	r3, [r3, r1]
+	str	r3, [r0, r1]
+	adds	r1, r1, #4
+
+LoopCopyDataInit:
+	ldr	r0, =_sdata
+	ldr	r3, =_edata
+	adds	r2, r0, r1
+	cmp	r2, r3
+	bcc	CopyDataInit
+
+/* Call the clock system intitialization function.*/
+    bl  SystemInit
+/* Call static constructors */
+  //bl __libc_init_array
+/* Call the application's entry point.*/
+  //bl  main
+  // Calling the crt0 'cold-start' entry point. There __libc_init_array is called
+  // and when existing hardware_init_hook() and software_init_hook() before 
+  // starting main(). software_init_hook() is available and has to be called due 
+  // to initializsation when using rtos.
+  bl _start
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section	.text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+	b	Infinite_Loop
+	.size	Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ 	.section	.isr_vector,"a",%progbits
+	.type	g_pfnVectors, %object
+	.size	g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+	.word	_estack
+	.word	Reset_Handler
+	.word	NMI_Handler
+	.word	HardFault_Handler
+	.word	MemManage_Handler
+	.word	BusFault_Handler
+	.word	UsageFault_Handler
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	SVC_Handler
+	.word	DebugMon_Handler
+	.word	0
+	.word	PendSV_Handler
+	.word	SysTick_Handler
+	.word	WWDG_IRQHandler
+	.word	PVD_PVM_IRQHandler
+	.word	TAMP_STAMP_IRQHandler
+	.word	RTC_WKUP_IRQHandler
+	.word	FLASH_IRQHandler
+	.word	RCC_IRQHandler
+	.word	EXTI0_IRQHandler
+	.word	EXTI1_IRQHandler
+	.word	EXTI2_IRQHandler
+	.word	EXTI3_IRQHandler
+	.word	EXTI4_IRQHandler
+	.word	DMA1_Channel1_IRQHandler
+	.word	DMA1_Channel2_IRQHandler
+	.word	DMA1_Channel3_IRQHandler
+	.word	DMA1_Channel4_IRQHandler
+	.word	DMA1_Channel5_IRQHandler
+	.word	DMA1_Channel6_IRQHandler
+	.word	DMA1_Channel7_IRQHandler
+	.word	ADC1_2_IRQHandler
+	.word	CAN1_TX_IRQHandler
+	.word	CAN1_RX0_IRQHandler
+	.word	CAN1_RX1_IRQHandler
+	.word	CAN1_SCE_IRQHandler
+	.word	EXTI9_5_IRQHandler
+	.word	TIM1_BRK_TIM15_IRQHandler
+	.word	TIM1_UP_TIM16_IRQHandler
+	.word	TIM1_TRG_COM_TIM17_IRQHandler
+	.word	TIM1_CC_IRQHandler
+	.word	TIM2_IRQHandler
+	.word	TIM3_IRQHandler
+	.word	TIM4_IRQHandler
+	.word	I2C1_EV_IRQHandler
+	.word	I2C1_ER_IRQHandler
+	.word	I2C2_EV_IRQHandler
+	.word	I2C2_ER_IRQHandler
+	.word	SPI1_IRQHandler
+	.word	SPI2_IRQHandler
+	.word	USART1_IRQHandler
+	.word	USART2_IRQHandler
+	.word	USART3_IRQHandler
+	.word	EXTI15_10_IRQHandler
+	.word	RTC_Alarm_IRQHandler
+	.word	DFSDM1_FLT3_IRQHandler
+	.word	TIM8_BRK_IRQHandler
+	.word	TIM8_UP_IRQHandler
+	.word	TIM8_TRG_COM_IRQHandler
+	.word	TIM8_CC_IRQHandler
+	.word	ADC3_IRQHandler
+	.word	FMC_IRQHandler
+	.word	SDMMC1_IRQHandler
+	.word	TIM5_IRQHandler
+	.word	SPI3_IRQHandler
+	.word	UART4_IRQHandler
+	.word	UART5_IRQHandler
+	.word	TIM6_DAC_IRQHandler
+	.word	TIM7_IRQHandler
+	.word	DMA2_Channel1_IRQHandler
+	.word	DMA2_Channel2_IRQHandler
+	.word	DMA2_Channel3_IRQHandler
+	.word	DMA2_Channel4_IRQHandler
+	.word	DMA2_Channel5_IRQHandler
+	.word	DFSDM1_FLT0_IRQHandler
+	.word	DFSDM1_FLT1_IRQHandler
+	.word	DFSDM1_FLT2_IRQHandler
+	.word	COMP_IRQHandler
+	.word	LPTIM1_IRQHandler
+	.word	LPTIM2_IRQHandler
+	.word	OTG_FS_IRQHandler
+	.word	DMA2_Channel6_IRQHandler
+	.word	DMA2_Channel7_IRQHandler
+	.word	LPUART1_IRQHandler
+	.word	QUADSPI_IRQHandler
+	.word	I2C3_EV_IRQHandler
+	.word	I2C3_ER_IRQHandler
+	.word	SAI1_IRQHandler
+	.word	SAI2_IRQHandler
+	.word	SWPMI1_IRQHandler
+	.word	TSC_IRQHandler
+	.word	LCD_IRQHandler
+	.word 0
+	.word	RNG_IRQHandler
+	.word	FPU_IRQHandler
+	.word	CRS_IRQHandler
+	.word	I2C4_EV_IRQHandler
+	.word	I2C4_ER_IRQHandler
+	.word	DCMI_IRQHandler
+	.word	CAN2_TX_IRQHandler
+	.word	CAN2_RX0_IRQHandler
+	.word	CAN2_RX1_IRQHandler
+	.word	CAN2_SCE_IRQHandler
+	.word	DMA2D_IRQHandler
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+  .weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+  .weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+  .weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_PVM_IRQHandler
+	.thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+	.weak	TAMP_STAMP_IRQHandler
+	.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+	.weak	RTC_WKUP_IRQHandler
+	.thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_IRQHandler
+	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel2_IRQHandler
+	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel3_IRQHandler
+	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_IRQHandler
+	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel5_IRQHandler
+	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel6_IRQHandler
+	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel7_IRQHandler
+	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	ADC1_2_IRQHandler
+	.thumb_set ADC1_2_IRQHandler,Default_Handler
+
+	.weak	CAN1_TX_IRQHandler
+	.thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX0_IRQHandler
+	.thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+	.weak	CAN1_RX1_IRQHandler
+	.thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+	.weak	CAN1_SCE_IRQHandler
+	.thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+	.weak	EXTI9_5_IRQHandler
+	.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_TIM15_IRQHandler
+	.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_TIM16_IRQHandler
+	.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_TIM17_IRQHandler
+	.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM3_IRQHandler
+	.thumb_set TIM3_IRQHandler,Default_Handler
+
+	.weak	TIM4_IRQHandler
+	.thumb_set TIM4_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	USART3_IRQHandler
+	.thumb_set USART3_IRQHandler,Default_Handler
+
+	.weak	EXTI15_10_IRQHandler
+	.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+	.weak	RTC_Alarm_IRQHandler
+	.thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+	.weak	DFSDM1_FLT3_IRQHandler
+	.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+	.weak	TIM8_BRK_IRQHandler
+	.thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM8_UP_IRQHandler
+	.thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+	.weak	TIM8_TRG_COM_IRQHandler
+	.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM8_CC_IRQHandler
+	.thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+	.weak	ADC3_IRQHandler
+	.thumb_set ADC3_IRQHandler,Default_Handler
+
+	.weak	FMC_IRQHandler
+	.thumb_set FMC_IRQHandler,Default_Handler
+
+	.weak	SDMMC1_IRQHandler
+	.thumb_set SDMMC1_IRQHandler,Default_Handler
+
+	.weak	TIM5_IRQHandler
+	.thumb_set TIM5_IRQHandler,Default_Handler
+
+	.weak	SPI3_IRQHandler
+	.thumb_set SPI3_IRQHandler,Default_Handler
+
+	.weak	UART4_IRQHandler
+	.thumb_set UART4_IRQHandler,Default_Handler
+
+	.weak	UART5_IRQHandler
+	.thumb_set UART5_IRQHandler,Default_Handler
+
+	.weak	TIM6_DAC_IRQHandler
+	.thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+	.weak	TIM7_IRQHandler
+	.thumb_set TIM7_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel1_IRQHandler
+	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel2_IRQHandler
+	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel3_IRQHandler
+	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel4_IRQHandler
+	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel5_IRQHandler
+	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	DFSDM1_FLT0_IRQHandler
+	.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler	
+	
+	.weak	DFSDM1_FLT1_IRQHandler
+	.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler	
+	
+	.weak	DFSDM1_FLT2_IRQHandler
+	.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler	
+	
+	.weak	COMP_IRQHandler
+	.thumb_set COMP_IRQHandler,Default_Handler
+	
+	.weak	LPTIM1_IRQHandler
+	.thumb_set LPTIM1_IRQHandler,Default_Handler
+	
+	.weak	LPTIM2_IRQHandler
+	.thumb_set LPTIM2_IRQHandler,Default_Handler	
+	
+	.weak	OTG_FS_IRQHandler
+	.thumb_set OTG_FS_IRQHandler,Default_Handler	
+	
+	.weak	DMA2_Channel6_IRQHandler
+	.thumb_set DMA2_Channel6_IRQHandler,Default_Handler	
+	
+	.weak	DMA2_Channel7_IRQHandler
+	.thumb_set DMA2_Channel7_IRQHandler,Default_Handler	
+	
+	.weak	LPUART1_IRQHandler
+	.thumb_set LPUART1_IRQHandler,Default_Handler	
+	
+	.weak	QUADSPI_IRQHandler
+	.thumb_set QUADSPI_IRQHandler,Default_Handler	
+	
+	.weak	I2C3_EV_IRQHandler
+	.thumb_set I2C3_EV_IRQHandler,Default_Handler	
+	
+	.weak	I2C3_ER_IRQHandler
+	.thumb_set I2C3_ER_IRQHandler,Default_Handler	
+	
+	.weak	SAI1_IRQHandler
+	.thumb_set SAI1_IRQHandler,Default_Handler
+	
+	.weak	SAI2_IRQHandler
+	.thumb_set SAI2_IRQHandler,Default_Handler
+	
+	.weak	SWPMI1_IRQHandler
+	.thumb_set SWPMI1_IRQHandler,Default_Handler
+	
+	.weak	TSC_IRQHandler
+	.thumb_set TSC_IRQHandler,Default_Handler
+	
+	.weak	LCD_IRQHandler
+	.thumb_set LCD_IRQHandler,Default_Handler
+	
+	.weak	RNG_IRQHandler
+	.thumb_set RNG_IRQHandler,Default_Handler
+	
+	.weak	FPU_IRQHandler
+	.thumb_set FPU_IRQHandler,Default_Handler
+
+		.weak	CRS_IRQHandler
+	.thumb_set CRS_IRQHandler,Default_Handler
+
+	.weak	I2C4_EV_IRQHandler
+	.thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+	.weak	I2C4_ER_IRQHandler
+	.thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+	.weak	DCMI_IRQHandler
+	.thumb_set DCMI_IRQHandler,Default_Handler
+
+	.weak	CAN2_TX_IRQHandler
+	.thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+	.weak	CAN2_RX0_IRQHandler
+	.thumb_set CAN2_RX0_IRQHandler,Default_Handler
+
+	.weak	CAN2_RX1_IRQHandler
+	.thumb_set CAN2_RX1_IRQHandler,Default_Handler
+
+	.weak	CAN2_SCE_IRQHandler
+	.thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+	.weak	DMA2D_IRQHandler
+	.thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_IAR/startup_stm32l496xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_IAR/startup_stm32l496xx.S
new file mode 100644
index 00000000000..71698fcbb1f
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_IAR/startup_stm32l496xx.S
@@ -0,0 +1,691 @@
+;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
+;* File Name          : startup_stm32l496xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.7.0
+;* Date               : 17-February-2017
+;* Description        : STM32L496xx Ultra Low Power Devices vector
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7
+        DCD     ADC1_2_IRQHandler                 ; ADC1, ADC2
+        DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_TIM15_IRQHandler         ; TIM1 Break and TIM15
+        DCD     TIM1_UP_TIM16_IRQHandler          ; TIM1 Update and TIM16
+        DCD     TIM1_TRG_COM_TIM17_IRQHandler     ; TIM1 Trigger and Commutation and TIM17
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     TIM3_IRQHandler                   ; TIM3
+        DCD     TIM4_IRQHandler                   ; TIM4
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+        DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM1 Filter 3 global Interrupt
+        DCD     TIM8_BRK_IRQHandler               ; TIM8 Break Interrupt
+        DCD     TIM8_UP_IRQHandler                ; TIM8 Update Interrupt
+        DCD     TIM8_TRG_COM_IRQHandler           ; TIM8 Trigger and Commutation Interrupt
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+        DCD     ADC3_IRQHandler                   ; ADC3 global  Interrupt
+        DCD     FMC_IRQHandler                    ; FMC
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1
+        DCD     TIM5_IRQHandler                   ; TIM5
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     UART4_IRQHandler                  ; UART4
+        DCD     UART5_IRQHandler                  ; UART5
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1
+        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2
+        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3
+        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4
+        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global Interrupt
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global Interrupt
+        DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM1 Filter 2 global Interrupt
+        DCD     COMP_IRQHandler                   ; COMP Interrupt
+        DCD     LPTIM1_IRQHandler                 ; LP TIM1 interrupt
+        DCD     LPTIM2_IRQHandler                 ; LP TIM2 interrupt
+        DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6
+        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7
+        DCD     LPUART1_IRQHandler                ; LP UART 1 interrupt
+        DCD     QUADSPI_IRQHandler                ; Quad SPI global interrupt
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     SAI1_IRQHandler                   ; Serial Audio Interface 1 global interrupt
+        DCD     SAI2_IRQHandler                   ; Serial Audio Interface 2 global interrupt
+        DCD     SWPMI1_IRQHandler                 ; Serial Wire Interface global interrupt
+        DCD     TSC_IRQHandler                    ; Touch Sense Controller global interrupt
+        DCD     LCD_IRQHandler                    ; LCD global interrupt
+        DCD     0                                 ; Reserved        
+        DCD     RNG_IRQHandler                    ; RNG global interrupt
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     CRS_IRQHandler                    ; CRS error
+        DCD     I2C4_EV_IRQHandler                ; I2C4 event
+        DCD     I2C4_ER_IRQHandler                ; I2C4 error
+        DCD     DCMI_IRQHandler                   ; DCMI global interrupt
+        DCD     CAN2_TX_IRQHandler                ; CAN2 TX
+        DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0
+        DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1
+        DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE
+        DCD     DMA2D_IRQHandler                  ; DMA2D global interrupt       
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+
+        PUBWEAK ADC1_2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+        B ADC1_2_IRQHandler
+
+        PUBWEAK CAN1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_TX_IRQHandler
+        B CAN1_TX_IRQHandler
+
+        PUBWEAK CAN1_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX0_IRQHandler
+        B CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_SCE_IRQHandler
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_TIM15_IRQHandler
+        B TIM1_BRK_TIM15_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_TIM16_IRQHandler
+        B TIM1_UP_TIM16_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_TIM17_IRQHandler
+        B TIM1_TRG_COM_TIM17_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK DFSDM1_FLT3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+        B DFSDM1_FLT3_IRQHandler
+
+        PUBWEAK TIM8_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_IRQHandler
+        B TIM8_BRK_IRQHandler
+
+        PUBWEAK TIM8_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_IRQHandler
+        B TIM8_UP_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+        B TIM8_TRG_COM_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK ADC3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+        B ADC3_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel1_IRQHandler
+        B DMA2_Channel1_IRQHandler
+
+        PUBWEAK DMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel2_IRQHandler
+        B DMA2_Channel2_IRQHandler
+
+        PUBWEAK DMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel3_IRQHandler
+        B DMA2_Channel3_IRQHandler
+
+        PUBWEAK DMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel4_IRQHandler
+        B DMA2_Channel4_IRQHandler
+
+        PUBWEAK DMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel5_IRQHandler
+        B DMA2_Channel5_IRQHandler
+
+        PUBWEAK DFSDM1_FLT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+        B DFSDM1_FLT0_IRQHandler
+
+        PUBWEAK DFSDM1_FLT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+        B DFSDM1_FLT1_IRQHandler
+
+        PUBWEAK DFSDM1_FLT2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+        B DFSDM1_FLT2_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK OTG_FS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+        B OTG_FS_IRQHandler
+
+        PUBWEAK DMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel6_IRQHandler
+        B DMA2_Channel6_IRQHandler
+
+        PUBWEAK DMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Channel7_IRQHandler
+        B DMA2_Channel7_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK QUADSPI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+        B QUADSPI_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+       PUBWEAK SAI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+        PUBWEAK SWPMI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+        B SWPMI1_IRQHandler
+
+       PUBWEAK TSC_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+TSC_IRQHandler
+       B TSC_IRQHandler
+
+       PUBWEAK LCD_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+LCD_IRQHandler
+       B LCD_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+        
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler        
+        
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+        B I2C4_EV_IRQHandler
+
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+        B I2C4_ER_IRQHandler 
+        
+        PUBWEAK DCMI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_IRQHandler
+        B DCMI_IRQHandler                 
+        
+        PUBWEAK CAN2_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN2_TX_IRQHandler
+        B CAN2_TX_IRQHandler
+
+        PUBWEAK CAN2_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN2_RX0_IRQHandler
+        B CAN2_RX0_IRQHandler
+
+        PUBWEAK CAN2_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN2_RX1_IRQHandler
+        B CAN2_RX1_IRQHandler
+
+        PUBWEAK CAN2_SCE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN2_SCE_IRQHandler
+        B CAN2_SCE_IRQHandler
+        
+        PUBWEAK DMA2D_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+        B DMA2D_IRQHandler                  
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_IAR/stm32l496xx.icf b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_IAR/stm32l496xx.icf
new file mode 100644
index 00000000000..87437eaabbe
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_IAR/stm32l496xx.icf
@@ -0,0 +1,32 @@
+/* [ROM = 1024kb = 0x100000] */
+define symbol __intvec_start__     = 0x08000000;
+define symbol __region_ROM_start__ = 0x08000000;
+define symbol __region_ROM_end__   = 0x08000000 + 0x100000 - 1;
+
+/* [RAM = 0x50000] */
+/* Vector table dynamic copy: Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM */
+define symbol __NVIC_start__          = 0x20000000;
+define symbol __NVIC_end__            = 0x200001AC - 1;
+define symbol __region_SRAM1_start__  = 0x200001AC; /* Aligned on 8 bytes (428 = 53 x 8) */
+define symbol __region_SRAM1_end__    = 0x2004FFFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region SRAM1_region = mem:[from __region_SRAM1_start__ to __region_SRAM1_end__];
+
+/* Stack 1/8 and Heap 1/4 of RAM */
+define symbol __size_cstack__ = 0x8000;
+define symbol __size_heap__   = 0xa000;
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in SRAM1_region   { readwrite, block STACKHEAP };
+
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/cmsis.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/cmsis.h
new file mode 100644
index 00000000000..41a1233f3b7
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/cmsis.h
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32l4xx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/cmsis_nvic.h
new file mode 100644
index 00000000000..ad22074ad6e
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/cmsis_nvic.h
@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 91 vectors = 364 bytes from 0x40 to 0x1AB
+// Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM
+#define NVIC_NUM_VECTORS        107
+#define NVIC_RAM_VECTOR_ADDRESS 0X20000000 // Vectors positioned at start of SRAM
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/hal_tick.h
new file mode 100644
index 00000000000..173f8e7cb9b
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/hal_tick.h
@@ -0,0 +1,65 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.h
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32l4xx.h"
+#include "stm32l4xx_ll_tim.h"
+#include "cmsis_nvic.h"
+   
+#define TIM_MST      TIM5
+#define TIM_MST_IRQ  TIM5_IRQn
+#define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+
+#define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
+
+#define TIM_MST_16BIT  0 // 1=16-bit timer, 0=32-bit timer
+
+#define TIM_MST_PCLK  1 // Select the peripheral clock number (1 or 2)
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l496xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l496xx.h
new file mode 100644
index 00000000000..cf136503df9
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l496xx.h
@@ -0,0 +1,19771 @@
+/**
+  ******************************************************************************
+  * @file    stm32l496xx.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    17-February-2017
+  * @brief   CMSIS STM32L496xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral�s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32l496xx
+  * @{
+  */
+
+#ifndef __STM32L496xx_H
+#define __STM32L496xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+   */
+#define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */
+#define __MPU_PRESENT             1       /*!< STM32L4XX provides an MPU                     */
+#define __NVIC_PRIO_BITS          4       /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1       /*!< FPU present                                   */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32L4XX Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum
+{
+/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_PVM_IRQn                = 1,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts    */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                   */
+  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                   */
+  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                   */
+  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                   */
+  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                   */
+  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                   */
+  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                                   */
+  ADC1_2_IRQn                 = 18,     /*!< ADC1, ADC2 SAR global Interrupts                                  */
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break interrupt and TIM15 global interrupt                   */
+  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                  */
+  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  DFSDM1_FLT3_IRQn            = 42,     /*!< DFSDM1 Filter 3 global Interrupt                                  */
+  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                              */
+  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                             */
+  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt                            */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  ADC3_IRQn                   = 47,     /*!< ADC3 global  Interrupt                                            */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */
+  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */
+  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */
+  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */
+  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */
+  DFSDM1_FLT0_IRQn            = 61,     /*!< DFSDM1 Filter 0 global Interrupt                                  */
+  DFSDM1_FLT1_IRQn            = 62,     /*!< DFSDM1 Filter 1 global Interrupt                                  */
+  DFSDM1_FLT2_IRQn            = 63,     /*!< DFSDM1 Filter 2 global Interrupt                                  */
+  COMP_IRQn                   = 64,     /*!< COMP1 and COMP2 Interrupts                                        */
+  LPTIM1_IRQn                 = 65,     /*!< LP TIM1 interrupt                                                 */
+  LPTIM2_IRQn                 = 66,     /*!< LP TIM2 interrupt                                                 */
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
+  DMA2_Channel6_IRQn          = 68,     /*!< DMA2 Channel 6 global interrupt                                   */
+  DMA2_Channel7_IRQn          = 69,     /*!< DMA2 Channel 7 global interrupt                                   */
+  LPUART1_IRQn                = 70,     /*!< LP UART1 interrupt                                                */
+  QUADSPI_IRQn                = 71,     /*!< Quad SPI global interrupt                                         */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  SAI1_IRQn                   = 74,     /*!< Serial Audio Interface 1 global interrupt                         */
+  SAI2_IRQn                   = 75,     /*!< Serial Audio Interface 2 global interrupt                         */
+  SWPMI1_IRQn                 = 76,     /*!< Serial Wire Interface 1 global interrupt                          */
+  TSC_IRQn                    = 77,     /*!< Touch Sense Controller global interrupt                           */
+  LCD_IRQn                    = 78,     /*!< LCD global interrupt                                              */
+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
+  CRS_IRQn                    = 82,     /*!< CRS global interrupt                                              */
+  I2C4_EV_IRQn                = 83,     /*!< I2C4 Event interrupt                                              */
+  I2C4_ER_IRQn                = 84,     /*!< I2C4 Error interrupt                                              */
+  DCMI_IRQn                   = 85,     /*!< DCMI global interrupt                                             */
+  CAN2_TX_IRQn                = 86,     /*!< CAN2 TX interrupt                                                 */
+  CAN2_RX0_IRQn               = 87,     /*!< CAN2 RX0 interrupt                                                */
+  CAN2_RX1_IRQn               = 88,     /*!< CAN2 RX1 interrupt                                                */
+  CAN2_SCE_IRQn               = 89,     /*!< CAN2 SCE interrupt                                                */
+  DMA2D_IRQn                  = 90      /*!< DMA2D global interrupt                                            */                                             
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
+#include "system_stm32l4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
+  __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
+  __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
+  __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
+  __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
+  __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
+  __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
+       uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
+  __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
+  __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
+  __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
+       uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
+  __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
+  __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
+  __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
+  __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
+  __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
+       uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
+       uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
+  __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
+       uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
+  __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
+  __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
+  __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
+  __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
+       uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
+  __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
+  __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
+  __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
+  __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
+       uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
+  __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 1 configuration register,  Address offset: 0xA0 */
+  __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
+       uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
+       uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
+  __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
+  __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;          /*!< ADC common status register,                    Address offset: ADC1 base address + 0x300 */
+  uint32_t      RESERVED;     /*!< Reserved,                                      Address offset: ADC1 base address + 0x304 */
+  __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */
+  __IO uint32_t CDR;          /*!< ADC common group regular data register         Address offset: ADC1 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+/** 
+  * @brief DCMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register,                         Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+  * @brief Controller Area Network TxMailBox
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+  * @brief Controller Area Network FIFOMailBox
+  */
+
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+  * @brief Controller Area Network FilterRegister
+  */
+
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+  * @brief Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+
+/**
+  * @brief Comparator
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
+  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+  * @brief Clock Recovery System
+  */
+typedef struct 
+{
+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */
+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */
+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */
+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
+  __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
+  __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
+  __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
+  __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
+  __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
+  __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
+} DAC_TypeDef;
+
+/**
+  * @brief DFSDM module registers
+  */
+typedef struct
+{
+  __IO uint32_t FLTCR1;      /*!< DFSDM control register1,                          Address offset: 0x100 */
+  __IO uint32_t FLTCR2;      /*!< DFSDM control register2,                          Address offset: 0x104 */
+  __IO uint32_t FLTISR;      /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
+  __IO uint32_t FLTICR;      /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
+  __IO uint32_t FLTJCHGR;    /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
+  __IO uint32_t FLTFCR;      /*!< DFSDM filter control register,                    Address offset: 0x114 */
+  __IO uint32_t FLTJDATAR;   /*!< DFSDM data register for injected group,           Address offset: 0x118 */
+  __IO uint32_t FLTRDATAR;   /*!< DFSDM data register for regular group,            Address offset: 0x11C */
+  __IO uint32_t FLTAWHTR;    /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
+  __IO uint32_t FLTAWLTR;    /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
+  __IO uint32_t FLTAWSR;     /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
+  __IO uint32_t FLTAWCFR;    /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
+  __IO uint32_t FLTEXMAX;    /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
+  __IO uint32_t FLTEXMIN;    /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
+  __IO uint32_t FLTCNVTIMR;  /*!< DFSDM conversion timer,                           Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+  * @brief DFSDM channel configuration registers
+  */
+typedef struct
+{
+  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
+  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
+  __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and
+                                  short circuit detector register,                  Address offset: 0x08 */
+  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
+  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */
+  __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */
+  __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
+  __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
+  __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
+} DBGMCU_TypeDef;
+
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
+  __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
+  __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
+  __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
+  __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSELR;       /*!< DMA channel selection register              */
+} DMA_Request_TypeDef;
+
+/* Legacy define */
+#define DMA_request_TypeDef  DMA_Request_TypeDef
+
+
+/** 
+  * @brief DMA2D Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */
+  __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */
+  __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */
+  __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */
+  __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */
+  __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */
+  uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */
+  uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */
+  __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */
+  __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */
+  __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */
+  __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */
+  __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */
+  __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */
+} EXTI_TypeDef;
+
+
+/**
+  * @brief Firewall
+  */
+
+typedef struct
+{
+  __IO uint32_t CSSA;        /*!< Code Segment Start Address register,              Address offset: 0x00 */
+  __IO uint32_t CSL;         /*!< Code Segment Length register,                      Address offset: 0x04 */
+  __IO uint32_t NVDSSA;      /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
+  __IO uint32_t NVDSL;       /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
+  __IO uint32_t VDSSA ;      /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
+  __IO uint32_t VDSL ;       /*!< Volatile data Segment Length register,             Address offset: 0x14 */
+  uint32_t      RESERVED1;   /*!< Reserved1,                                         Address offset: 0x18 */
+  uint32_t      RESERVED2;   /*!< Reserved2,                                         Address offset: 0x1C */
+  __IO uint32_t CR ;         /*!< Configuration  register,                           Address offset: 0x20 */
+} FIREWALL_TypeDef;
+
+
+/**
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */
+  __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */
+  __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */
+  __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */
+  __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */
+  __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */
+  __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */
+  __IO uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */
+  __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */
+  __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
+  __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */
+  __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */
+  __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */
+       uint32_t RESERVED2[4];     /*!< Reserved2,                                Address offset: 0x34 */
+  __IO uint32_t PCROP2SR;         /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
+  __IO uint32_t PCROP2ER;         /*!< FLASH bank2 PCROP end address register,   Address offset: 0x48 */
+  __IO uint32_t WRP2AR;           /*!< FLASH bank2 WRP area A address register,  Address offset: 0x4C */
+  __IO uint32_t WRP2BR;           /*!< FLASH bank2 WRP area B address register,  Address offset: 0x50 */
+} FLASH_TypeDef;
+
+
+/**
+  * @brief Flexible Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];     /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank1E
+  */
+
+typedef struct
+{
+  __IO uint32_t BWTR[7];     /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank3
+  */
+
+typedef struct
+{
+  __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
+  __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
+  __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
+  __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
+  __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
+  __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+  __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
+
+} GPIO_TypeDef;
+
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+  * @brief LCD
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< LCD control register,              Address offset: 0x00 */
+  __IO uint32_t FCR;         /*!< LCD frame control register,        Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< LCD status register,               Address offset: 0x08 */
+  __IO uint32_t CLR;         /*!< LCD clear register,                Address offset: 0x0C */
+  uint32_t RESERVED;         /*!< Reserved,                          Address offset: 0x10 */
+  __IO uint32_t RAM[16];     /*!< LCD display memory,           Address offset: 0x14-0x50 */
+} LCD_TypeDef;
+
+/**
+  * @brief LPTIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
+  __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
+  __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
+  __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
+  __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
+  __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
+  __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
+  __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
+  __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
+} LPTIM_TypeDef;
+
+/**
+  * @brief Operational Amplifier (OPAMP)
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< OPAMP control/status register,                     Address offset: 0x00 */
+  __IO uint32_t OTR;         /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
+  __IO uint32_t LPOTR;       /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
+} OPAMP_Common_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
+  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x04 */
+  __IO uint32_t CR3;   /*!< PWR power control register 3,        Address offset: 0x08 */
+  __IO uint32_t CR4;   /*!< PWR power control register 4,        Address offset: 0x0C */
+  __IO uint32_t SR1;   /*!< PWR power status register 1,         Address offset: 0x10 */
+  __IO uint32_t SR2;   /*!< PWR power status register 2,         Address offset: 0x14 */
+  __IO uint32_t SCR;   /*!< PWR power status reset register,     Address offset: 0x18 */
+  uint32_t RESERVED;   /*!< Reserved,                            Address offset: 0x1C */
+  __IO uint32_t PUCRA; /*!< Pull_up control register of portA,   Address offset: 0x20 */
+  __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
+  __IO uint32_t PUCRB; /*!< Pull_up control register of portB,   Address offset: 0x28 */
+  __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
+  __IO uint32_t PUCRC; /*!< Pull_up control register of portC,   Address offset: 0x30 */
+  __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
+  __IO uint32_t PUCRD; /*!< Pull_up control register of portD,   Address offset: 0x38 */
+  __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
+  __IO uint32_t PUCRE; /*!< Pull_up control register of portE,   Address offset: 0x40 */
+  __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
+  __IO uint32_t PUCRF; /*!< Pull_up control register of portF,   Address offset: 0x48 */
+  __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
+  __IO uint32_t PUCRG; /*!< Pull_up control register of portG,   Address offset: 0x50 */
+  __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
+  __IO uint32_t PUCRH; /*!< Pull_up control register of portH,   Address offset: 0x58 */
+  __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
+  __IO uint32_t PUCRI; /*!< Pull_up control register of portI,   Address offset: 0x60 */
+  __IO uint32_t PDCRI; /*!< Pull_Down control register of portI, Address offset: 0x64 */
+} PWR_TypeDef;
+
+
+/**
+  * @brief QUAD Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< QUADSPI Control register,                           Address offset: 0x00 */
+  __IO uint32_t DCR;         /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< QUADSPI Status register,                            Address offset: 0x08 */
+  __IO uint32_t FCR;         /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
+  __IO uint32_t DLR;         /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
+  __IO uint32_t CCR;         /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
+  __IO uint32_t AR;          /*!< QUADSPI Address register,                           Address offset: 0x18 */
+  __IO uint32_t ABR;         /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
+  __IO uint32_t DR;          /*!< QUADSPI Data register,                              Address offset: 0x20 */
+  __IO uint32_t PSMKR;       /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
+  __IO uint32_t PSMAR;       /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
+  __IO uint32_t PIR;         /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
+  __IO uint32_t LPTR;        /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */
+  __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */
+  __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */
+  __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */
+  __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register,                                     Address offset: 0x10 */
+  __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register,                                     Address offset: 0x14 */
+  __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */
+  __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */
+  __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */
+  uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x24 */
+  __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */
+  __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */
+  __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */
+  uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x34 */
+  __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */
+  __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */
+  __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x44 */
+  __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */
+  __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */
+  __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */
+  uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x54 */
+  __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */
+  __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */
+  __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */
+  uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x64 */
+  __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */
+  __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */
+  __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
+  uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x74 */
+  __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
+  __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
+  __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
+  uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x84 */
+  __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */
+  uint32_t      RESERVED7;   /*!< Reserved,                                                                Address offset: 0x8C */
+  __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */
+  __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */
+  __IO uint32_t CRRCR;       /*!< RCC clock recovery RC register,                                          Address offset: 0x98 */
+  __IO uint32_t CCIPR2;      /*!< RCC peripherals independent clock configuration register 2,              Address offset: 0x9C */
+} RCC_TypeDef;
+
+/**
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;         /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+       uint32_t reserved;    /*!< Reserved  */
+  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAMPCR;      /*!< RTC tamper configuration register,                         Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  __IO uint32_t OR;          /*!< RTC option register,                                       Address offset: 0x4C */
+  __IO uint32_t BKP0R;       /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;       /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;       /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;       /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;       /*!< RTC backup register 4,                                     Address offset: 0x60 */
+  __IO uint32_t BKP5R;       /*!< RTC backup register 5,                                     Address offset: 0x64 */
+  __IO uint32_t BKP6R;       /*!< RTC backup register 6,                                     Address offset: 0x68 */
+  __IO uint32_t BKP7R;       /*!< RTC backup register 7,                                     Address offset: 0x6C */
+  __IO uint32_t BKP8R;       /*!< RTC backup register 8,                                     Address offset: 0x70 */
+  __IO uint32_t BKP9R;       /*!< RTC backup register 9,                                     Address offset: 0x74 */
+  __IO uint32_t BKP10R;      /*!< RTC backup register 10,                                    Address offset: 0x78 */
+  __IO uint32_t BKP11R;      /*!< RTC backup register 11,                                    Address offset: 0x7C */
+  __IO uint32_t BKP12R;      /*!< RTC backup register 12,                                    Address offset: 0x80 */
+  __IO uint32_t BKP13R;      /*!< RTC backup register 13,                                    Address offset: 0x84 */
+  __IO uint32_t BKP14R;      /*!< RTC backup register 14,                                    Address offset: 0x88 */
+  __IO uint32_t BKP15R;      /*!< RTC backup register 15,                                    Address offset: 0x8C */
+  __IO uint32_t BKP16R;      /*!< RTC backup register 16,                                    Address offset: 0x90 */
+  __IO uint32_t BKP17R;      /*!< RTC backup register 17,                                    Address offset: 0x94 */
+  __IO uint32_t BKP18R;      /*!< RTC backup register 18,                                    Address offset: 0x98 */
+  __IO uint32_t BKP19R;      /*!< RTC backup register 19,                                    Address offset: 0x9C */
+  __IO uint32_t BKP20R;      /*!< RTC backup register 20,                                    Address offset: 0xA0 */
+  __IO uint32_t BKP21R;      /*!< RTC backup register 21,                                    Address offset: 0xA4 */
+  __IO uint32_t BKP22R;      /*!< RTC backup register 22,                                    Address offset: 0xA8 */
+  __IO uint32_t BKP23R;      /*!< RTC backup register 23,                                    Address offset: 0xAC */
+  __IO uint32_t BKP24R;      /*!< RTC backup register 24,                                    Address offset: 0xB0 */
+  __IO uint32_t BKP25R;      /*!< RTC backup register 25,                                    Address offset: 0xB4 */
+  __IO uint32_t BKP26R;      /*!< RTC backup register 26,                                    Address offset: 0xB8 */
+  __IO uint32_t BKP27R;      /*!< RTC backup register 27,                                    Address offset: 0xBC */
+  __IO uint32_t BKP28R;      /*!< RTC backup register 28,                                    Address offset: 0xC0 */
+  __IO uint32_t BKP29R;      /*!< RTC backup register 29,                                    Address offset: 0xC4 */
+  __IO uint32_t BKP30R;      /*!< RTC backup register 30,                                    Address offset: 0xC8 */
+  __IO uint32_t BKP31R;      /*!< RTC backup register 31,                                    Address offset: 0xCC */
+} RTC_TypeDef;
+
+
+/**
+  * @brief Serial Audio Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t GCR;         /*!< SAI global configuration register,        Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+
+/**
+  * @brief Secure digital input/output Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,    Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
+  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */
+  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */
+} SDMMC_TypeDef;
+
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */
+  __IO uint32_t DR;          /*!< SPI data register,                                  Address offset: 0x0C */
+  __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
+  __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
+  __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
+  uint32_t  RESERVED1;       /*!< Reserved,                                            Address offset: 0x1C */
+  uint32_t  RESERVED2;       /*!< Reserved,                                            Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/**
+  * @brief Single Wire Protocol Master Interface SPWMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */
+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */
+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */
+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */
+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */
+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */
+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */
+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */
+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */
+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */
+} SWPMI_TypeDef;
+
+
+/**
+  * @brief System configuration controller
+  */
+
+typedef struct
+{
+  __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                   Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+  __IO uint32_t SCSR;        /*!< SYSCFG SRAM2 control and status register,          Address offset: 0x18      */
+  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                   Address offset: 0x1C      */
+  __IO uint32_t SWPR;        /*!< SYSCFG SRAM2 write protection register,            Address offset: 0x20      */
+  __IO uint32_t SKR;         /*!< SYSCFG SRAM2 key register,                         Address offset: 0x24      */
+  __IO uint32_t SWPR2;       /*!< SYSCFG SRAM2 write protection register 2,          Address offset: 0x28      */
+} SYSCFG_TypeDef;
+
+
+/**
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
+  __IO uint32_t OR1;         /*!< TIM option register 1,                    Address offset: 0x50 */
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
+  __IO uint32_t OR2;         /*!< TIM option register 2,                    Address offset: 0x60 */
+  __IO uint32_t OR3;         /*!< TIM option register 3,                    Address offset: 0x64 */
+} TIM_TypeDef;
+
+
+/**
+  * @brief Touch Sensing Controller (TSC)
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */
+  __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */
+  __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */
+  __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */
+  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
+  uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */
+  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
+  uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */
+  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
+  uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */
+  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */
+  uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */
+  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */
+  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */
+  __IO uint16_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  uint16_t  RESERVED2;       /*!< Reserved, 0x12                                                 */
+  __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint16_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */
+  uint16_t  RESERVED3;       /*!< Reserved, 0x1A                                                 */
+  __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint16_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */
+  uint16_t  RESERVED4;       /*!< Reserved, 0x26                                                 */
+  __IO uint16_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */
+  uint16_t  RESERVED5;       /*!< Reserved, 0x2A                                                 */
+} USART_TypeDef;
+
+/**
+  * @brief VREFBUF
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+/**
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+  * @brief RNG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/** 
+  * @brief USB_OTG_Core_register
+  */
+typedef struct
+{
+  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register          000h*/
+  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register                   004h*/
+  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register              008h*/
+  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register              00Ch*/
+  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                          010h*/
+  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                      014h*/
+  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register                 018h*/
+  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register                  01Ch*/
+  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register            020h*/
+  __IO uint32_t GRXFSIZ;              /* Receive FIFO Size Register                      024h*/
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register     028h*/
+  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg           02Ch*/
+  uint32_t Reserved30[2];             /* Reserved                                        030h*/
+  __IO uint32_t GCCFG;                /* General Purpose IO Register                     038h*/
+  __IO uint32_t CID;                  /* User ID Register                                03Ch*/
+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                 040h*/
+  __IO uint32_t GHWCFG1;              /* User HW config1                                 044h*/
+  __IO uint32_t GHWCFG2;              /* User HW config2                                 048h*/
+  __IO uint32_t GHWCFG3;              /* User HW config3                                 04Ch*/
+  uint32_t  Reserved6;                /* Reserved                                        050h*/ 
+  __IO uint32_t GLPMCFG;              /* LPM Register                                    054h*/
+  __IO uint32_t GPWRDN;               /* Power Down Register                             058h*/
+  __IO uint32_t GDFIFOCFG;            /* DFIFO Software Config Register                  05Ch*/
+   __IO uint32_t GADPCTL;             /* ADP Timer, Control and Status Register          60Ch*/
+    uint32_t  Reserved43[39];         /* Reserved                                        058h-0FFh*/
+  __IO uint32_t HPTXFSIZ;             /* Host Periodic Tx FIFO Size Reg                  100h*/
+  __IO uint32_t DIEPTXF[0x0F];        /* dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+/** 
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DCFG;        /* dev Configuration Register   800h*/
+  __IO uint32_t DCTL;        /* dev Control Register         804h*/
+  __IO uint32_t DSTS;        /* dev Status Register (RO)     808h*/
+  uint32_t Reserved0C;       /* Reserved                     80Ch*/
+  __IO uint32_t DIEPMSK;     /* dev IN Endpoint Mask         810h*/
+  __IO uint32_t DOEPMSK;     /* dev OUT Endpoint Mask        814h*/
+  __IO uint32_t DAINT;       /* dev All Endpoints Itr Reg    818h*/
+  __IO uint32_t DAINTMSK;    /* dev All Endpoints Itr Mask   81Ch*/
+  uint32_t  Reserved20;      /* Reserved                     820h*/
+  uint32_t Reserved9;        /* Reserved                     824h*/
+  __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/
+  __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/
+  __IO uint32_t DTHRCTL;     /* dev thr                      830h*/
+  __IO uint32_t DIEPEMPMSK;  /* dev empty msk             834h*/
+  __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/
+  __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/  
+  uint32_t Reserved40;       /* dedicated EP mask           840h*/
+  __IO uint32_t DINEP1MSK;   /* dedicated EP mask           844h*/
+  uint32_t  Reserved44[15];  /* Reserved                 844-87Ch*/
+  __IO uint32_t DOUTEP1MSK;  /* dedicated EP msk            884h*/   
+} USB_OTG_DeviceTypeDef;
+
+/** 
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct 
+{
+  __IO uint32_t DIEPCTL;     /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+  uint32_t Reserved04;       /* Reserved                       900h + (ep_num * 20h) + 04h*/
+  __IO uint32_t DIEPINT;     /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/
+  uint32_t Reserved0C;       /* Reserved                       900h + (ep_num * 20h) + 0Ch*/
+  __IO uint32_t DIEPTSIZ;    /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/
+  __IO uint32_t DIEPDMA;     /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/
+  __IO uint32_t DTXFSTS;     /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+  uint32_t Reserved18;       /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+} USB_OTG_INEndpointTypeDef;
+
+/** 
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DOEPCTL;     /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
+  uint32_t Reserved04;       /* Reserved                      B00h + (ep_num * 20h) + 04h*/
+  __IO uint32_t DOEPINT;     /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
+  uint32_t Reserved0C;       /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
+  __IO uint32_t DOEPTSIZ;    /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
+  __IO uint32_t DOEPDMA;     /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
+  uint32_t Reserved18[2];    /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+} USB_OTG_OUTEndpointTypeDef;
+
+/** 
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct 
+{
+  __IO uint32_t HCFG;        /* Host Configuration Register    400h*/
+  __IO uint32_t HFIR;        /* Host Frame Interval Register   404h*/
+  __IO uint32_t HFNUM;       /* Host Frame Nbr/Frame Remaining 408h*/
+  uint32_t Reserved40C;      /* Reserved                       40Ch*/
+  __IO uint32_t HPTXSTS;     /* Host Periodic Tx FIFO/ Queue Status 410h*/
+  __IO uint32_t HAINT;       /* Host All Channels Interrupt Register 414h*/
+  __IO uint32_t HAINTMSK;    /* Host All Channels Interrupt Mask 418h*/
+} USB_OTG_HostTypeDef;
+
+/** 
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;
+  __IO uint32_t HCSPLT;
+  __IO uint32_t HCINT;
+  __IO uint32_t HCINTMSK;
+  __IO uint32_t HCTSIZ;
+  __IO uint32_t HCDMA;
+  uint32_t Reserved[2];
+} USB_OTG_HostChannelTypeDef;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
+#define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(up to 256 KB) base address */
+#define SRAM2_BASE            ((uint32_t)0x10000000U) /*!< SRAM2(64 KB) base address */
+#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address */
+#define FMC_BASE              ((uint32_t)0x60000000U) /*!< FMC base address */
+#define QSPI_BASE             ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */
+
+#define FMC_R_BASE            ((uint32_t)0xA0000000U) /*!< FMC  control registers base address */
+#define QSPI_R_BASE           ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
+#define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
+#define SRAM2_BB_BASE         ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
+
+/* Legacy defines */
+#define SRAM_BASE             SRAM1_BASE
+#define SRAM_BB_BASE          SRAM1_BB_BASE
+
+#define SRAM1_SIZE_MAX        ((uint32_t)0x00040000U) /*!< maximum SRAM1 size (up to 256 KBytes) */
+#define SRAM2_SIZE            ((uint32_t)0x00010000U) /*!< SRAM2 size (64 KBytes) */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE        PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000U)
+
+#define FMC_BANK1             FMC_BASE
+#define FMC_BANK1_1           FMC_BANK1
+#define FMC_BANK1_2           (FMC_BANK1 + 0x04000000U)
+#define FMC_BANK1_3           (FMC_BANK1 + 0x08000000U)
+#define FMC_BANK1_4           (FMC_BANK1 + 0x0C000000U)
+#define FMC_BANK3             (FMC_BASE  + 0x20000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
+#define LCD_BASE              (APB1PERIPH_BASE + 0x2400U)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
+#define CRS_BASE              (APB1PERIPH_BASE + 0x6000U)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
+#define I2C4_BASE             (APB1PERIPH_BASE + 0x8400U)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
+#define DAC1_BASE             (APB1PERIPH_BASE + 0x7400U)
+#define OPAMP_BASE            (APB1PERIPH_BASE + 0x7800U)
+#define OPAMP1_BASE           (APB1PERIPH_BASE + 0x7800U)
+#define OPAMP2_BASE           (APB1PERIPH_BASE + 0x7810U)
+#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00U)
+#define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000U)
+#define SWPMI1_BASE           (APB1PERIPH_BASE + 0x8800U)
+#define LPTIM2_BASE           (APB1PERIPH_BASE + 0x9400U)
+
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000U)
+#define VREFBUF_BASE          (APB2PERIPH_BASE + 0x0030U)
+#define COMP1_BASE            (APB2PERIPH_BASE + 0x0200U)
+#define COMP2_BASE            (APB2PERIPH_BASE + 0x0204U)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400U)
+#define FIREWALL_BASE         (APB2PERIPH_BASE + 0x1C00U)
+#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2800U)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400U)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800U)
+#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000U)
+#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400U)
+#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800U)
+#define SAI1_BASE             (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024)
+#define SAI2_BASE             (APB2PERIPH_BASE + 0x5800U)
+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004)
+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024)
+#define DFSDM1_BASE           (APB2PERIPH_BASE + 0x6000U)
+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00)
+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20)
+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40)
+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60)
+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80)
+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0)
+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0)
+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0)
+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100)
+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180)
+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200)
+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE             (AHB1PERIPH_BASE)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400U)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x1000U)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000U)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
+#define TSC_BASE              (AHB1PERIPH_BASE + 0x4000U)
+#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)
+
+
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008U)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CU)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030U)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044U)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058U)
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CU)
+#define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080U)
+#define DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8U)
+
+
+#define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008U)
+#define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CU)
+#define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030U)
+#define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044U)
+#define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058U)
+#define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CU)
+#define DMA2_Channel7_BASE    (DMA2_BASE + 0x0080U)
+#define DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8U)
+
+
+/*!< AHB2 peripherals */
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE            (AHB2PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE            (AHB2PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE            (AHB2PERIPH_BASE + 0x2000U)
+
+#define USBOTG_BASE           (AHB2PERIPH_BASE + 0x08000000U)
+
+#define ADC1_BASE             (AHB2PERIPH_BASE + 0x08040000U)
+#define ADC2_BASE             (AHB2PERIPH_BASE + 0x08040100U)
+#define ADC3_BASE             (AHB2PERIPH_BASE + 0x08040200U)
+#define ADC123_COMMON_BASE    (AHB2PERIPH_BASE + 0x08040300U)
+
+#define DCMI_BASE             (AHB2PERIPH_BASE + 0x08050000U)
+
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800U)
+
+
+/*!< FMC Banks registers base  address */
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           ((uint32_t)0xE0042000U)
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE               ((uint32_t)0x50000000U)
+
+#define USB_OTG_GLOBAL_BASE                  ((uint32_t)0x00000000U)
+#define USB_OTG_DEVICE_BASE                  ((uint32_t)0x00000800U)
+#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t)0x00000900U)
+#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t)0x00000B00U)
+#define USB_OTG_EP_REG_SIZE                  ((uint32_t)0x00000020U)
+#define USB_OTG_HOST_BASE                    ((uint32_t)0x00000400U)
+#define USB_OTG_HOST_PORT_BASE               ((uint32_t)0x00000440U)
+#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t)0x00000500U)
+#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t)0x00000020U)
+#define USB_OTG_PCGCCTL_BASE                 ((uint32_t)0x00000E00U)
+#define USB_OTG_FIFO_BASE                    ((uint32_t)0x00001000U)
+#define USB_OTG_FIFO_SIZE                    ((uint32_t)0x00001000U)
+
+
+#define PACKAGE_BASE          ((uint32_t)0x1FFF7500U)        /*!< Package data register base address     */
+#define UID_BASE              ((uint32_t)0x1FFF7590U)        /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE        ((uint32_t)0x1FFF75E0U)        /*!< Flash size data register base address  */
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define LCD                 ((LCD_TypeDef *) LCD_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define CRS                 ((CRS_TypeDef *) CRS_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC1_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)
+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)
+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
+/* Aliases to keep compatibility after DFSDM renaming */
+#define DFSDM_Channel0      DFSDM1_Channel0
+#define DFSDM_Channel1      DFSDM1_Channel1
+#define DFSDM_Channel2      DFSDM1_Channel2
+#define DFSDM_Channel3      DFSDM1_Channel3
+#define DFSDM_Channel4      DFSDM1_Channel4
+#define DFSDM_Channel5      DFSDM1_Channel5
+#define DFSDM_Channel6      DFSDM1_Channel6
+#define DFSDM_Channel7      DFSDM1_Channel7
+#define DFSDM_Filter0       DFSDM1_Filter0
+#define DFSDM_Filter1       DFSDM1_Filter1
+#define DFSDM_Filter2       DFSDM1_Filter2
+#define DFSDM_Filter3       DFSDM1_Filter3
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
+#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+
+
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
+#define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
+#define DMA2_CSELR          ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
+
+
+#define FMC_Bank1_R         ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E_R        ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank3_R         ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+
+#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
+
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+ */
+#define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
+
+/********************  Bit definition for ADC_ISR register  *******************/
+#define ADC_ISR_ADRDY_Pos              (0U)                                    
+#define ADC_ISR_ADRDY_Msk              (0x1U << ADC_ISR_ADRDY_Pos)             /*!< 0x00000001 */
+#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
+#define ADC_ISR_EOSMP_Pos              (1U)                                    
+#define ADC_ISR_EOSMP_Msk              (0x1U << ADC_ISR_EOSMP_Pos)             /*!< 0x00000002 */
+#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
+#define ADC_ISR_EOC_Pos                (2U)                                    
+#define ADC_ISR_EOC_Msk                (0x1U << ADC_ISR_EOC_Pos)               /*!< 0x00000004 */
+#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
+#define ADC_ISR_EOS_Pos                (3U)                                    
+#define ADC_ISR_EOS_Msk                (0x1U << ADC_ISR_EOS_Pos)               /*!< 0x00000008 */
+#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
+#define ADC_ISR_OVR_Pos                (4U)                                    
+#define ADC_ISR_OVR_Msk                (0x1U << ADC_ISR_OVR_Pos)               /*!< 0x00000010 */
+#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
+#define ADC_ISR_JEOC_Pos               (5U)                                    
+#define ADC_ISR_JEOC_Msk               (0x1U << ADC_ISR_JEOC_Pos)              /*!< 0x00000020 */
+#define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
+#define ADC_ISR_JEOS_Pos               (6U)                                    
+#define ADC_ISR_JEOS_Msk               (0x1U << ADC_ISR_JEOS_Pos)              /*!< 0x00000040 */
+#define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
+#define ADC_ISR_AWD1_Pos               (7U)                                    
+#define ADC_ISR_AWD1_Msk               (0x1U << ADC_ISR_AWD1_Pos)              /*!< 0x00000080 */
+#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos               (8U)                                    
+#define ADC_ISR_AWD2_Msk               (0x1U << ADC_ISR_AWD2_Pos)              /*!< 0x00000100 */
+#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos               (9U)                                    
+#define ADC_ISR_AWD3_Msk               (0x1U << ADC_ISR_AWD3_Pos)              /*!< 0x00000200 */
+#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos              (10U)                                   
+#define ADC_ISR_JQOVF_Msk              (0x1U << ADC_ISR_JQOVF_Pos)             /*!< 0x00000400 */
+#define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
+
+/********************  Bit definition for ADC_IER register  *******************/
+#define ADC_IER_ADRDYIE_Pos            (0U)                                    
+#define ADC_IER_ADRDYIE_Msk            (0x1U << ADC_IER_ADRDYIE_Pos)           /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
+#define ADC_IER_EOSMPIE_Pos            (1U)                                    
+#define ADC_IER_EOSMPIE_Msk            (0x1U << ADC_IER_EOSMPIE_Pos)           /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
+#define ADC_IER_EOCIE_Pos              (2U)                                    
+#define ADC_IER_EOCIE_Msk              (0x1U << ADC_IER_EOCIE_Pos)             /*!< 0x00000004 */
+#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
+#define ADC_IER_EOSIE_Pos              (3U)                                    
+#define ADC_IER_EOSIE_Msk              (0x1U << ADC_IER_EOSIE_Pos)             /*!< 0x00000008 */
+#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_IER_OVRIE_Pos              (4U)                                    
+#define ADC_IER_OVRIE_Msk              (0x1U << ADC_IER_OVRIE_Pos)             /*!< 0x00000010 */
+#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
+#define ADC_IER_JEOCIE_Pos             (5U)                                    
+#define ADC_IER_JEOCIE_Msk             (0x1U << ADC_IER_JEOCIE_Pos)            /*!< 0x00000020 */
+#define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
+#define ADC_IER_JEOSIE_Pos             (6U)                                    
+#define ADC_IER_JEOSIE_Msk             (0x1U << ADC_IER_JEOSIE_Pos)            /*!< 0x00000040 */
+#define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_IER_AWD1IE_Pos             (7U)                                    
+#define ADC_IER_AWD1IE_Msk             (0x1U << ADC_IER_AWD1IE_Pos)            /*!< 0x00000080 */
+#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
+#define ADC_IER_AWD2IE_Pos             (8U)                                    
+#define ADC_IER_AWD2IE_Msk             (0x1U << ADC_IER_AWD2IE_Pos)            /*!< 0x00000100 */
+#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
+#define ADC_IER_AWD3IE_Pos             (9U)                                    
+#define ADC_IER_AWD3IE_Msk             (0x1U << ADC_IER_AWD3IE_Pos)            /*!< 0x00000200 */
+#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
+#define ADC_IER_JQOVFIE_Pos            (10U)                                   
+#define ADC_IER_JQOVFIE_Msk            (0x1U << ADC_IER_JQOVFIE_Pos)           /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
+
+/* Legacy defines */
+#define ADC_IER_ADRDY           (ADC_IER_ADRDYIE)
+#define ADC_IER_EOSMP           (ADC_IER_EOSMPIE)
+#define ADC_IER_EOC             (ADC_IER_EOCIE)
+#define ADC_IER_EOS             (ADC_IER_EOSIE)
+#define ADC_IER_OVR             (ADC_IER_OVRIE)
+#define ADC_IER_JEOC            (ADC_IER_JEOCIE)
+#define ADC_IER_JEOS            (ADC_IER_JEOSIE)
+#define ADC_IER_AWD1            (ADC_IER_AWD1IE)
+#define ADC_IER_AWD2            (ADC_IER_AWD2IE)
+#define ADC_IER_AWD3            (ADC_IER_AWD3IE)
+#define ADC_IER_JQOVF           (ADC_IER_JQOVFIE)
+
+/********************  Bit definition for ADC_CR register  ********************/
+#define ADC_CR_ADEN_Pos                (0U)                                    
+#define ADC_CR_ADEN_Msk                (0x1U << ADC_CR_ADEN_Pos)               /*!< 0x00000001 */
+#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
+#define ADC_CR_ADDIS_Pos               (1U)                                    
+#define ADC_CR_ADDIS_Msk               (0x1U << ADC_CR_ADDIS_Pos)              /*!< 0x00000002 */
+#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
+#define ADC_CR_ADSTART_Pos             (2U)                                    
+#define ADC_CR_ADSTART_Msk             (0x1U << ADC_CR_ADSTART_Pos)            /*!< 0x00000004 */
+#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
+#define ADC_CR_JADSTART_Pos            (3U)                                    
+#define ADC_CR_JADSTART_Msk            (0x1U << ADC_CR_JADSTART_Pos)           /*!< 0x00000008 */
+#define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
+#define ADC_CR_ADSTP_Pos               (4U)                                    
+#define ADC_CR_ADSTP_Msk               (0x1U << ADC_CR_ADSTP_Pos)              /*!< 0x00000010 */
+#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
+#define ADC_CR_JADSTP_Pos              (5U)                                    
+#define ADC_CR_JADSTP_Msk              (0x1U << ADC_CR_JADSTP_Pos)             /*!< 0x00000020 */
+#define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
+#define ADC_CR_ADVREGEN_Pos            (28U)                                   
+#define ADC_CR_ADVREGEN_Msk            (0x1U << ADC_CR_ADVREGEN_Pos)           /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
+#define ADC_CR_DEEPPWD_Pos             (29U)                                   
+#define ADC_CR_DEEPPWD_Msk             (0x1U << ADC_CR_DEEPPWD_Pos)            /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
+#define ADC_CR_ADCALDIF_Pos            (30U)                                   
+#define ADC_CR_ADCALDIF_Msk            (0x1U << ADC_CR_ADCALDIF_Pos)           /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
+#define ADC_CR_ADCAL_Pos               (31U)                                   
+#define ADC_CR_ADCAL_Msk               (0x1U << ADC_CR_ADCAL_Pos)              /*!< 0x80000000 */
+#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
+
+/********************  Bit definition for ADC_CFGR register  ******************/
+#define ADC_CFGR_DMAEN_Pos             (0U)                                    
+#define ADC_CFGR_DMAEN_Msk             (0x1U << ADC_CFGR_DMAEN_Pos)            /*!< 0x00000001 */
+#define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */
+#define ADC_CFGR_DMACFG_Pos            (1U)                                    
+#define ADC_CFGR_DMACFG_Msk            (0x1U << ADC_CFGR_DMACFG_Pos)           /*!< 0x00000002 */
+#define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */
+
+#define ADC_CFGR_DFSDMCFG_Pos          (2U)                                    
+#define ADC_CFGR_DFSDMCFG_Msk          (0x1U << ADC_CFGR_DFSDMCFG_Pos)         /*!< 0x00000004 */
+#define ADC_CFGR_DFSDMCFG              ADC_CFGR_DFSDMCFG_Msk                   /*!< ADC DFSDM mode configuration */
+
+#define ADC_CFGR_RES_Pos               (3U)                                    
+#define ADC_CFGR_RES_Msk               (0x3U << ADC_CFGR_RES_Pos)              /*!< 0x00000018 */
+#define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
+#define ADC_CFGR_RES_0                 (0x1U << ADC_CFGR_RES_Pos)              /*!< 0x00000008 */
+#define ADC_CFGR_RES_1                 (0x2U << ADC_CFGR_RES_Pos)              /*!< 0x00000010 */
+
+#define ADC_CFGR_ALIGN_Pos             (5U)                                    
+#define ADC_CFGR_ALIGN_Msk             (0x1U << ADC_CFGR_ALIGN_Pos)            /*!< 0x00000020 */
+#define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignement */
+
+#define ADC_CFGR_EXTSEL_Pos            (6U)                                    
+#define ADC_CFGR_EXTSEL_Msk            (0xFU << ADC_CFGR_EXTSEL_Pos)           /*!< 0x000003C0 */
+#define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
+#define ADC_CFGR_EXTSEL_0              (0x1U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000040 */
+#define ADC_CFGR_EXTSEL_1              (0x2U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000080 */
+#define ADC_CFGR_EXTSEL_2              (0x4U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000100 */
+#define ADC_CFGR_EXTSEL_3              (0x8U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000200 */
+
+#define ADC_CFGR_EXTEN_Pos             (10U)                                   
+#define ADC_CFGR_EXTEN_Msk             (0x3U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000C00 */
+#define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
+#define ADC_CFGR_EXTEN_0               (0x1U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000400 */
+#define ADC_CFGR_EXTEN_1               (0x2U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000800 */
+
+#define ADC_CFGR_OVRMOD_Pos            (12U)                                   
+#define ADC_CFGR_OVRMOD_Msk            (0x1U << ADC_CFGR_OVRMOD_Pos)           /*!< 0x00001000 */
+#define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
+#define ADC_CFGR_CONT_Pos              (13U)                                   
+#define ADC_CFGR_CONT_Msk              (0x1U << ADC_CFGR_CONT_Pos)             /*!< 0x00002000 */
+#define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
+#define ADC_CFGR_AUTDLY_Pos            (14U)                                   
+#define ADC_CFGR_AUTDLY_Msk            (0x1U << ADC_CFGR_AUTDLY_Pos)           /*!< 0x00004000 */
+#define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
+
+#define ADC_CFGR_DISCEN_Pos            (16U)                                   
+#define ADC_CFGR_DISCEN_Msk            (0x1U << ADC_CFGR_DISCEN_Pos)           /*!< 0x00010000 */
+#define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
+
+#define ADC_CFGR_DISCNUM_Pos           (17U)                                   
+#define ADC_CFGR_DISCNUM_Msk           (0x7U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x000E0000 */
+#define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CFGR_DISCNUM_0             (0x1U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00020000 */
+#define ADC_CFGR_DISCNUM_1             (0x2U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00040000 */
+#define ADC_CFGR_DISCNUM_2             (0x4U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00080000 */
+
+#define ADC_CFGR_JDISCEN_Pos           (20U)                                   
+#define ADC_CFGR_JDISCEN_Msk           (0x1U << ADC_CFGR_JDISCEN_Pos)          /*!< 0x00100000 */
+#define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */
+#define ADC_CFGR_JQM_Pos               (21U)                                   
+#define ADC_CFGR_JQM_Msk               (0x1U << ADC_CFGR_JQM_Pos)              /*!< 0x00200000 */
+#define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
+#define ADC_CFGR_AWD1SGL_Pos           (22U)                                   
+#define ADC_CFGR_AWD1SGL_Msk           (0x1U << ADC_CFGR_AWD1SGL_Pos)          /*!< 0x00400000 */
+#define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CFGR_AWD1EN_Pos            (23U)                                   
+#define ADC_CFGR_AWD1EN_Msk            (0x1U << ADC_CFGR_AWD1EN_Pos)           /*!< 0x00800000 */
+#define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+#define ADC_CFGR_JAWD1EN_Pos           (24U)                                   
+#define ADC_CFGR_JAWD1EN_Msk           (0x1U << ADC_CFGR_JAWD1EN_Pos)          /*!< 0x01000000 */
+#define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CFGR_JAUTO_Pos             (25U)                                   
+#define ADC_CFGR_JAUTO_Msk             (0x1U << ADC_CFGR_JAUTO_Pos)            /*!< 0x02000000 */
+#define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
+
+#define ADC_CFGR_AWD1CH_Pos            (26U)                                   
+#define ADC_CFGR_AWD1CH_Msk            (0x1FU << ADC_CFGR_AWD1CH_Pos)          /*!< 0x7C000000 */
+#define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CFGR_AWD1CH_0              (0x01U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x04000000 */
+#define ADC_CFGR_AWD1CH_1              (0x02U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x08000000 */
+#define ADC_CFGR_AWD1CH_2              (0x04U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x10000000 */
+#define ADC_CFGR_AWD1CH_3              (0x08U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x20000000 */
+#define ADC_CFGR_AWD1CH_4              (0x10U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x40000000 */
+
+#define ADC_CFGR_JQDIS_Pos             (31U)                                   
+#define ADC_CFGR_JQDIS_Msk             (0x1U << ADC_CFGR_JQDIS_Pos)            /*!< 0x80000000 */
+#define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */
+
+/********************  Bit definition for ADC_CFGR2 register  *****************/
+#define ADC_CFGR2_ROVSE_Pos            (0U)                                    
+#define ADC_CFGR2_ROVSE_Msk            (0x1U << ADC_CFGR2_ROVSE_Pos)           /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
+#define ADC_CFGR2_JOVSE_Pos            (1U)                                    
+#define ADC_CFGR2_JOVSE_Msk            (0x1U << ADC_CFGR2_JOVSE_Pos)           /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
+
+#define ADC_CFGR2_OVSR_Pos             (2U)                                    
+#define ADC_CFGR2_OVSR_Msk             (0x7U << ADC_CFGR2_OVSR_Pos)            /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
+#define ADC_CFGR2_OVSR_0               (0x1U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1               (0x2U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2               (0x4U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000010 */
+
+#define ADC_CFGR2_OVSS_Pos             (5U)                                    
+#define ADC_CFGR2_OVSS_Msk             (0xFU << ADC_CFGR2_OVSS_Pos)            /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
+#define ADC_CFGR2_OVSS_0               (0x1U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1               (0x2U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2               (0x4U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3               (0x8U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos            (9U)                                    
+#define ADC_CFGR2_TROVS_Msk            (0x1U << ADC_CFGR2_TROVS_Pos)           /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
+#define ADC_CFGR2_ROVSM_Pos            (10U)                                   
+#define ADC_CFGR2_ROVSM_Msk            (0x1U << ADC_CFGR2_ROVSM_Pos)           /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
+
+/********************  Bit definition for ADC_SMPR1 register  *****************/
+#define ADC_SMPR1_SMP0_Pos             (0U)                                    
+#define ADC_SMPR1_SMP0_Msk             (0x7U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
+#define ADC_SMPR1_SMP0_0               (0x1U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1               (0x2U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2               (0x4U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos             (3U)                                    
+#define ADC_SMPR1_SMP1_Msk             (0x7U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
+#define ADC_SMPR1_SMP1_0               (0x1U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1               (0x2U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2               (0x4U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos             (6U)                                    
+#define ADC_SMPR1_SMP2_Msk             (0x7U << ADC_SMPR1_SMP2_Pos)            /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
+#define ADC_SMPR1_SMP2_0               (0x1U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1               (0x2U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2               (0x4U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos             (9U)                                    
+#define ADC_SMPR1_SMP3_Msk             (0x7U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
+#define ADC_SMPR1_SMP3_0               (0x1U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1               (0x2U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2               (0x4U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos             (12U)                                   
+#define ADC_SMPR1_SMP4_Msk             (0x7U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
+#define ADC_SMPR1_SMP4_0               (0x1U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1               (0x2U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2               (0x4U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos             (15U)                                   
+#define ADC_SMPR1_SMP5_Msk             (0x7U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
+#define ADC_SMPR1_SMP5_0               (0x1U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1               (0x2U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2               (0x4U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos             (18U)                                   
+#define ADC_SMPR1_SMP6_Msk             (0x7U << ADC_SMPR1_SMP6_Pos)            /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
+#define ADC_SMPR1_SMP6_0               (0x1U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1               (0x2U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2               (0x4U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos             (21U)                                   
+#define ADC_SMPR1_SMP7_Msk             (0x7U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
+#define ADC_SMPR1_SMP7_0               (0x1U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1               (0x2U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2               (0x4U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos             (24U)                                   
+#define ADC_SMPR1_SMP8_Msk             (0x7U << ADC_SMPR1_SMP8_Pos)            /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
+#define ADC_SMPR1_SMP8_0               (0x1U << ADC_SMPR1_SMP8_Pos)            /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1               (0x2U << ADC_SMPR1_SMP8_Pos)            /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2               (0x4U << ADC_SMPR1_SMP8_Pos)            /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos             (27U)                                   
+#define ADC_SMPR1_SMP9_Msk             (0x7U << ADC_SMPR1_SMP9_Pos)            /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
+#define ADC_SMPR1_SMP9_0               (0x1U << ADC_SMPR1_SMP9_Pos)            /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1               (0x2U << ADC_SMPR1_SMP9_Pos)            /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2               (0x4U << ADC_SMPR1_SMP9_Pos)            /*!< 0x20000000 */
+
+#define ADC_SMPR1_SMPPLUS_Pos          (31U)                                   
+#define ADC_SMPR1_SMPPLUS_Msk          (0x1U << ADC_SMPR1_SMPPLUS_Pos)         /*!< 0x80000000 */
+#define ADC_SMPR1_SMPPLUS              ADC_SMPR1_SMPPLUS_Msk                   /*!< ADC channels sampling time additional setting */
+
+/********************  Bit definition for ADC_SMPR2 register  *****************/
+#define ADC_SMPR2_SMP10_Pos            (0U)                                    
+#define ADC_SMPR2_SMP10_Msk            (0x7U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
+#define ADC_SMPR2_SMP10_0              (0x1U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1              (0x2U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2              (0x4U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos            (3U)                                    
+#define ADC_SMPR2_SMP11_Msk            (0x7U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
+#define ADC_SMPR2_SMP11_0              (0x1U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1              (0x2U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2              (0x4U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos            (6U)                                    
+#define ADC_SMPR2_SMP12_Msk            (0x7U << ADC_SMPR2_SMP12_Pos)           /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
+#define ADC_SMPR2_SMP12_0              (0x1U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1              (0x2U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2              (0x4U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos            (9U)                                    
+#define ADC_SMPR2_SMP13_Msk            (0x7U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
+#define ADC_SMPR2_SMP13_0              (0x1U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1              (0x2U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2              (0x4U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos            (12U)                                   
+#define ADC_SMPR2_SMP14_Msk            (0x7U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
+#define ADC_SMPR2_SMP14_0              (0x1U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1              (0x2U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2              (0x4U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos            (15U)                                   
+#define ADC_SMPR2_SMP15_Msk            (0x7U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
+#define ADC_SMPR2_SMP15_0              (0x1U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1              (0x2U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2              (0x4U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos            (18U)                                   
+#define ADC_SMPR2_SMP16_Msk            (0x7U << ADC_SMPR2_SMP16_Pos)           /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
+#define ADC_SMPR2_SMP16_0              (0x1U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1              (0x2U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2              (0x4U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos            (21U)                                   
+#define ADC_SMPR2_SMP17_Msk            (0x7U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
+#define ADC_SMPR2_SMP17_0              (0x1U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1              (0x2U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2              (0x4U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos            (24U)                                   
+#define ADC_SMPR2_SMP18_Msk            (0x7U << ADC_SMPR2_SMP18_Pos)           /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
+#define ADC_SMPR2_SMP18_0              (0x1U << ADC_SMPR2_SMP18_Pos)           /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1              (0x2U << ADC_SMPR2_SMP18_Pos)           /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2              (0x4U << ADC_SMPR2_SMP18_Pos)           /*!< 0x04000000 */
+
+/********************  Bit definition for ADC_TR1 register  *******************/
+#define ADC_TR1_LT1_Pos                (0U)                                    
+#define ADC_TR1_LT1_Msk                (0xFFFU << ADC_TR1_LT1_Pos)             /*!< 0x00000FFF */
+#define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
+#define ADC_TR1_LT1_0                  (0x001U << ADC_TR1_LT1_Pos)             /*!< 0x00000001 */
+#define ADC_TR1_LT1_1                  (0x002U << ADC_TR1_LT1_Pos)             /*!< 0x00000002 */
+#define ADC_TR1_LT1_2                  (0x004U << ADC_TR1_LT1_Pos)             /*!< 0x00000004 */
+#define ADC_TR1_LT1_3                  (0x008U << ADC_TR1_LT1_Pos)             /*!< 0x00000008 */
+#define ADC_TR1_LT1_4                  (0x010U << ADC_TR1_LT1_Pos)             /*!< 0x00000010 */
+#define ADC_TR1_LT1_5                  (0x020U << ADC_TR1_LT1_Pos)             /*!< 0x00000020 */
+#define ADC_TR1_LT1_6                  (0x040U << ADC_TR1_LT1_Pos)             /*!< 0x00000040 */
+#define ADC_TR1_LT1_7                  (0x080U << ADC_TR1_LT1_Pos)             /*!< 0x00000080 */
+#define ADC_TR1_LT1_8                  (0x100U << ADC_TR1_LT1_Pos)             /*!< 0x00000100 */
+#define ADC_TR1_LT1_9                  (0x200U << ADC_TR1_LT1_Pos)             /*!< 0x00000200 */
+#define ADC_TR1_LT1_10                 (0x400U << ADC_TR1_LT1_Pos)             /*!< 0x00000400 */
+#define ADC_TR1_LT1_11                 (0x800U << ADC_TR1_LT1_Pos)             /*!< 0x00000800 */
+
+#define ADC_TR1_HT1_Pos                (16U)                                   
+#define ADC_TR1_HT1_Msk                (0xFFFU << ADC_TR1_HT1_Pos)             /*!< 0x0FFF0000 */
+#define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */
+#define ADC_TR1_HT1_0                  (0x001U << ADC_TR1_HT1_Pos)             /*!< 0x00010000 */
+#define ADC_TR1_HT1_1                  (0x002U << ADC_TR1_HT1_Pos)             /*!< 0x00020000 */
+#define ADC_TR1_HT1_2                  (0x004U << ADC_TR1_HT1_Pos)             /*!< 0x00040000 */
+#define ADC_TR1_HT1_3                  (0x008U << ADC_TR1_HT1_Pos)             /*!< 0x00080000 */
+#define ADC_TR1_HT1_4                  (0x010U << ADC_TR1_HT1_Pos)             /*!< 0x00100000 */
+#define ADC_TR1_HT1_5                  (0x020U << ADC_TR1_HT1_Pos)             /*!< 0x00200000 */
+#define ADC_TR1_HT1_6                  (0x040U << ADC_TR1_HT1_Pos)             /*!< 0x00400000 */
+#define ADC_TR1_HT1_7                  (0x080U << ADC_TR1_HT1_Pos)             /*!< 0x00800000 */
+#define ADC_TR1_HT1_8                  (0x100U << ADC_TR1_HT1_Pos)             /*!< 0x01000000 */
+#define ADC_TR1_HT1_9                  (0x200U << ADC_TR1_HT1_Pos)             /*!< 0x02000000 */
+#define ADC_TR1_HT1_10                 (0x400U << ADC_TR1_HT1_Pos)             /*!< 0x04000000 */
+#define ADC_TR1_HT1_11                 (0x800U << ADC_TR1_HT1_Pos)             /*!< 0x08000000 */
+
+/********************  Bit definition for ADC_TR2 register  *******************/
+#define ADC_TR2_LT2_Pos                (0U)                                    
+#define ADC_TR2_LT2_Msk                (0xFFU << ADC_TR2_LT2_Pos)              /*!< 0x000000FF */
+#define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
+#define ADC_TR2_LT2_0                  (0x01U << ADC_TR2_LT2_Pos)              /*!< 0x00000001 */
+#define ADC_TR2_LT2_1                  (0x02U << ADC_TR2_LT2_Pos)              /*!< 0x00000002 */
+#define ADC_TR2_LT2_2                  (0x04U << ADC_TR2_LT2_Pos)              /*!< 0x00000004 */
+#define ADC_TR2_LT2_3                  (0x08U << ADC_TR2_LT2_Pos)              /*!< 0x00000008 */
+#define ADC_TR2_LT2_4                  (0x10U << ADC_TR2_LT2_Pos)              /*!< 0x00000010 */
+#define ADC_TR2_LT2_5                  (0x20U << ADC_TR2_LT2_Pos)              /*!< 0x00000020 */
+#define ADC_TR2_LT2_6                  (0x40U << ADC_TR2_LT2_Pos)              /*!< 0x00000040 */
+#define ADC_TR2_LT2_7                  (0x80U << ADC_TR2_LT2_Pos)              /*!< 0x00000080 */
+
+#define ADC_TR2_HT2_Pos                (16U)                                   
+#define ADC_TR2_HT2_Msk                (0xFFU << ADC_TR2_HT2_Pos)              /*!< 0x00FF0000 */
+#define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
+#define ADC_TR2_HT2_0                  (0x01U << ADC_TR2_HT2_Pos)              /*!< 0x00010000 */
+#define ADC_TR2_HT2_1                  (0x02U << ADC_TR2_HT2_Pos)              /*!< 0x00020000 */
+#define ADC_TR2_HT2_2                  (0x04U << ADC_TR2_HT2_Pos)              /*!< 0x00040000 */
+#define ADC_TR2_HT2_3                  (0x08U << ADC_TR2_HT2_Pos)              /*!< 0x00080000 */
+#define ADC_TR2_HT2_4                  (0x10U << ADC_TR2_HT2_Pos)              /*!< 0x00100000 */
+#define ADC_TR2_HT2_5                  (0x20U << ADC_TR2_HT2_Pos)              /*!< 0x00200000 */
+#define ADC_TR2_HT2_6                  (0x40U << ADC_TR2_HT2_Pos)              /*!< 0x00400000 */
+#define ADC_TR2_HT2_7                  (0x80U << ADC_TR2_HT2_Pos)              /*!< 0x00800000 */
+
+/********************  Bit definition for ADC_TR3 register  *******************/
+#define ADC_TR3_LT3_Pos                (0U)                                    
+#define ADC_TR3_LT3_Msk                (0xFFU << ADC_TR3_LT3_Pos)              /*!< 0x000000FF */
+#define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
+#define ADC_TR3_LT3_0                  (0x01U << ADC_TR3_LT3_Pos)              /*!< 0x00000001 */
+#define ADC_TR3_LT3_1                  (0x02U << ADC_TR3_LT3_Pos)              /*!< 0x00000002 */
+#define ADC_TR3_LT3_2                  (0x04U << ADC_TR3_LT3_Pos)              /*!< 0x00000004 */
+#define ADC_TR3_LT3_3                  (0x08U << ADC_TR3_LT3_Pos)              /*!< 0x00000008 */
+#define ADC_TR3_LT3_4                  (0x10U << ADC_TR3_LT3_Pos)              /*!< 0x00000010 */
+#define ADC_TR3_LT3_5                  (0x20U << ADC_TR3_LT3_Pos)              /*!< 0x00000020 */
+#define ADC_TR3_LT3_6                  (0x40U << ADC_TR3_LT3_Pos)              /*!< 0x00000040 */
+#define ADC_TR3_LT3_7                  (0x80U << ADC_TR3_LT3_Pos)              /*!< 0x00000080 */
+
+#define ADC_TR3_HT3_Pos                (16U)                                   
+#define ADC_TR3_HT3_Msk                (0xFFU << ADC_TR3_HT3_Pos)              /*!< 0x00FF0000 */
+#define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
+#define ADC_TR3_HT3_0                  (0x01U << ADC_TR3_HT3_Pos)              /*!< 0x00010000 */
+#define ADC_TR3_HT3_1                  (0x02U << ADC_TR3_HT3_Pos)              /*!< 0x00020000 */
+#define ADC_TR3_HT3_2                  (0x04U << ADC_TR3_HT3_Pos)              /*!< 0x00040000 */
+#define ADC_TR3_HT3_3                  (0x08U << ADC_TR3_HT3_Pos)              /*!< 0x00080000 */
+#define ADC_TR3_HT3_4                  (0x10U << ADC_TR3_HT3_Pos)              /*!< 0x00100000 */
+#define ADC_TR3_HT3_5                  (0x20U << ADC_TR3_HT3_Pos)              /*!< 0x00200000 */
+#define ADC_TR3_HT3_6                  (0x40U << ADC_TR3_HT3_Pos)              /*!< 0x00400000 */
+#define ADC_TR3_HT3_7                  (0x80U << ADC_TR3_HT3_Pos)              /*!< 0x00800000 */
+
+/********************  Bit definition for ADC_SQR1 register  ******************/
+#define ADC_SQR1_L_Pos                 (0U)                                    
+#define ADC_SQR1_L_Msk                 (0xFU << ADC_SQR1_L_Pos)                /*!< 0x0000000F */
+#define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0                   (0x1U << ADC_SQR1_L_Pos)                /*!< 0x00000001 */
+#define ADC_SQR1_L_1                   (0x2U << ADC_SQR1_L_Pos)                /*!< 0x00000002 */
+#define ADC_SQR1_L_2                   (0x4U << ADC_SQR1_L_Pos)                /*!< 0x00000004 */
+#define ADC_SQR1_L_3                   (0x8U << ADC_SQR1_L_Pos)                /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos               (6U)                                    
+#define ADC_SQR1_SQ1_Msk               (0x1FU << ADC_SQR1_SQ1_Pos)             /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR1_SQ1_0                 (0x01U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1                 (0x02U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2                 (0x04U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3                 (0x08U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4                 (0x10U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos               (12U)                                   
+#define ADC_SQR1_SQ2_Msk               (0x1FU << ADC_SQR1_SQ2_Pos)             /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR1_SQ2_0                 (0x01U << ADC_SQR1_SQ2_Pos)             /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1                 (0x02U << ADC_SQR1_SQ2_Pos)             /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2                 (0x04U << ADC_SQR1_SQ2_Pos)             /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3                 (0x08U << ADC_SQR1_SQ2_Pos)             /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4                 (0x10U << ADC_SQR1_SQ2_Pos)             /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos               (18U)                                   
+#define ADC_SQR1_SQ3_Msk               (0x1FU << ADC_SQR1_SQ3_Pos)             /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR1_SQ3_0                 (0x01U << ADC_SQR1_SQ3_Pos)             /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1                 (0x02U << ADC_SQR1_SQ3_Pos)             /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2                 (0x04U << ADC_SQR1_SQ3_Pos)             /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3                 (0x08U << ADC_SQR1_SQ3_Pos)             /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4                 (0x10U << ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos               (24U)                                   
+#define ADC_SQR1_SQ4_Msk               (0x1FU << ADC_SQR1_SQ4_Pos)             /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR1_SQ4_0                 (0x01U << ADC_SQR1_SQ4_Pos)             /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1                 (0x02U << ADC_SQR1_SQ4_Pos)             /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2                 (0x04U << ADC_SQR1_SQ4_Pos)             /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3                 (0x08U << ADC_SQR1_SQ4_Pos)             /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4                 (0x10U << ADC_SQR1_SQ4_Pos)             /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR2 register  ******************/
+#define ADC_SQR2_SQ5_Pos               (0U)                                    
+#define ADC_SQR2_SQ5_Msk               (0x1FU << ADC_SQR2_SQ5_Pos)             /*!< 0x0000001F */
+#define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR2_SQ5_0                 (0x01U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1                 (0x02U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2                 (0x04U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3                 (0x08U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4                 (0x10U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos               (6U)                                    
+#define ADC_SQR2_SQ6_Msk               (0x1FU << ADC_SQR2_SQ6_Pos)             /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR2_SQ6_0                 (0x01U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1                 (0x02U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2                 (0x04U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3                 (0x08U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4                 (0x10U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos               (12U)                                   
+#define ADC_SQR2_SQ7_Msk               (0x1FU << ADC_SQR2_SQ7_Pos)             /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0                 (0x01U << ADC_SQR2_SQ7_Pos)             /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1                 (0x02U << ADC_SQR2_SQ7_Pos)             /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2                 (0x04U << ADC_SQR2_SQ7_Pos)             /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3                 (0x08U << ADC_SQR2_SQ7_Pos)             /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4                 (0x10U << ADC_SQR2_SQ7_Pos)             /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos               (18U)                                   
+#define ADC_SQR2_SQ8_Msk               (0x1FU << ADC_SQR2_SQ8_Pos)             /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0                 (0x01U << ADC_SQR2_SQ8_Pos)             /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1                 (0x02U << ADC_SQR2_SQ8_Pos)             /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2                 (0x04U << ADC_SQR2_SQ8_Pos)             /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3                 (0x08U << ADC_SQR2_SQ8_Pos)             /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4                 (0x10U << ADC_SQR2_SQ8_Pos)             /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos               (24U)                                   
+#define ADC_SQR2_SQ9_Msk               (0x1FU << ADC_SQR2_SQ9_Pos)             /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0                 (0x01U << ADC_SQR2_SQ9_Pos)             /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1                 (0x02U << ADC_SQR2_SQ9_Pos)             /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2                 (0x04U << ADC_SQR2_SQ9_Pos)             /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3                 (0x08U << ADC_SQR2_SQ9_Pos)             /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4                 (0x10U << ADC_SQR2_SQ9_Pos)             /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR3 register  ******************/
+#define ADC_SQR3_SQ10_Pos              (0U)                                    
+#define ADC_SQR3_SQ10_Msk              (0x1FU << ADC_SQR3_SQ10_Pos)            /*!< 0x0000001F */
+#define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR3_SQ10_0                (0x01U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1                (0x02U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2                (0x04U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3                (0x08U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4                (0x10U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos              (6U)                                    
+#define ADC_SQR3_SQ11_Msk              (0x1FU << ADC_SQR3_SQ11_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
+#define ADC_SQR3_SQ11_0                (0x01U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1                (0x02U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2                (0x04U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3                (0x08U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4                (0x10U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos              (12U)                                   
+#define ADC_SQR3_SQ12_Msk              (0x1FU << ADC_SQR3_SQ12_Pos)            /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR3_SQ12_0                (0x01U << ADC_SQR3_SQ12_Pos)            /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1                (0x02U << ADC_SQR3_SQ12_Pos)            /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2                (0x04U << ADC_SQR3_SQ12_Pos)            /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3                (0x08U << ADC_SQR3_SQ12_Pos)            /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4                (0x10U << ADC_SQR3_SQ12_Pos)            /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos              (18U)                                   
+#define ADC_SQR3_SQ13_Msk              (0x1FU << ADC_SQR3_SQ13_Pos)            /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR3_SQ13_0                (0x01U << ADC_SQR3_SQ13_Pos)            /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1                (0x02U << ADC_SQR3_SQ13_Pos)            /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2                (0x04U << ADC_SQR3_SQ13_Pos)            /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3                (0x08U << ADC_SQR3_SQ13_Pos)            /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4                (0x10U << ADC_SQR3_SQ13_Pos)            /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos              (24U)                                   
+#define ADC_SQR3_SQ14_Msk              (0x1FU << ADC_SQR3_SQ14_Pos)            /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR3_SQ14_0                (0x01U << ADC_SQR3_SQ14_Pos)            /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1                (0x02U << ADC_SQR3_SQ14_Pos)            /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2                (0x04U << ADC_SQR3_SQ14_Pos)            /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3                (0x08U << ADC_SQR3_SQ14_Pos)            /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4                (0x10U << ADC_SQR3_SQ14_Pos)            /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR4 register  ******************/
+#define ADC_SQR4_SQ15_Pos              (0U)                                    
+#define ADC_SQR4_SQ15_Msk              (0x1FU << ADC_SQR4_SQ15_Pos)            /*!< 0x0000001F */
+#define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR4_SQ15_0                (0x01U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1                (0x02U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2                (0x04U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3                (0x08U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4                (0x10U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos              (6U)                                    
+#define ADC_SQR4_SQ16_Msk              (0x1FU << ADC_SQR4_SQ16_Pos)            /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR4_SQ16_0                (0x01U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1                (0x02U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2                (0x04U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3                (0x08U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4                (0x10U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000400 */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_RDATA_Pos               (0U)                                    
+#define ADC_DR_RDATA_Msk               (0xFFFFU << ADC_DR_RDATA_Pos)           /*!< 0x0000FFFF */
+#define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
+#define ADC_DR_RDATA_0                 (0x0001U << ADC_DR_RDATA_Pos)           /*!< 0x00000001 */
+#define ADC_DR_RDATA_1                 (0x0002U << ADC_DR_RDATA_Pos)           /*!< 0x00000002 */
+#define ADC_DR_RDATA_2                 (0x0004U << ADC_DR_RDATA_Pos)           /*!< 0x00000004 */
+#define ADC_DR_RDATA_3                 (0x0008U << ADC_DR_RDATA_Pos)           /*!< 0x00000008 */
+#define ADC_DR_RDATA_4                 (0x0010U << ADC_DR_RDATA_Pos)           /*!< 0x00000010 */
+#define ADC_DR_RDATA_5                 (0x0020U << ADC_DR_RDATA_Pos)           /*!< 0x00000020 */
+#define ADC_DR_RDATA_6                 (0x0040U << ADC_DR_RDATA_Pos)           /*!< 0x00000040 */
+#define ADC_DR_RDATA_7                 (0x0080U << ADC_DR_RDATA_Pos)           /*!< 0x00000080 */
+#define ADC_DR_RDATA_8                 (0x0100U << ADC_DR_RDATA_Pos)           /*!< 0x00000100 */
+#define ADC_DR_RDATA_9                 (0x0200U << ADC_DR_RDATA_Pos)           /*!< 0x00000200 */
+#define ADC_DR_RDATA_10                (0x0400U << ADC_DR_RDATA_Pos)           /*!< 0x00000400 */
+#define ADC_DR_RDATA_11                (0x0800U << ADC_DR_RDATA_Pos)           /*!< 0x00000800 */
+#define ADC_DR_RDATA_12                (0x1000U << ADC_DR_RDATA_Pos)           /*!< 0x00001000 */
+#define ADC_DR_RDATA_13                (0x2000U << ADC_DR_RDATA_Pos)           /*!< 0x00002000 */
+#define ADC_DR_RDATA_14                (0x4000U << ADC_DR_RDATA_Pos)           /*!< 0x00004000 */
+#define ADC_DR_RDATA_15                (0x8000U << ADC_DR_RDATA_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JSQR register  ******************/
+#define ADC_JSQR_JL_Pos                (0U)                                    
+#define ADC_JSQR_JL_Msk                (0x3U << ADC_JSQR_JL_Pos)               /*!< 0x00000003 */
+#define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0                  (0x1U << ADC_JSQR_JL_Pos)               /*!< 0x00000001 */
+#define ADC_JSQR_JL_1                  (0x2U << ADC_JSQR_JL_Pos)               /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos           (2U)                                    
+#define ADC_JSQR_JEXTSEL_Msk           (0xFU << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x0000003C */
+#define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
+#define ADC_JSQR_JEXTSEL_0             (0x1U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1             (0x2U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2             (0x4U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3             (0x8U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000020 */
+
+#define ADC_JSQR_JEXTEN_Pos            (6U)                                    
+#define ADC_JSQR_JEXTEN_Msk            (0x3U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x000000C0 */
+#define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
+#define ADC_JSQR_JEXTEN_0              (0x1U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000040 */
+#define ADC_JSQR_JEXTEN_1              (0x2U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000080 */
+
+#define ADC_JSQR_JSQ1_Pos              (8U)                                    
+#define ADC_JSQR_JSQ1_Msk              (0x1FU << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001F00 */
+#define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0                (0x01U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000100 */
+#define ADC_JSQR_JSQ1_1                (0x02U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_2                (0x04U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_3                (0x08U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_4                (0x10U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001000 */
+
+#define ADC_JSQR_JSQ2_Pos              (14U)                                   
+#define ADC_JSQR_JSQ2_Msk              (0x1FU << ADC_JSQR_JSQ2_Pos)            /*!< 0x0007C000 */
+#define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0                (0x01U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00004000 */
+#define ADC_JSQR_JSQ2_1                (0x02U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_2                (0x04U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_3                (0x08U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_4                (0x10U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00040000 */
+
+#define ADC_JSQR_JSQ3_Pos              (20U)                                   
+#define ADC_JSQR_JSQ3_Msk              (0x1FU << ADC_JSQR_JSQ3_Pos)            /*!< 0x01F00000 */
+#define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0                (0x01U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00100000 */
+#define ADC_JSQR_JSQ3_1                (0x02U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_2                (0x04U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_3                (0x08U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_4                (0x10U << ADC_JSQR_JSQ3_Pos)            /*!< 0x01000000 */
+
+#define ADC_JSQR_JSQ4_Pos              (26U)                                   
+#define ADC_JSQR_JSQ4_Msk              (0x1FU << ADC_JSQR_JSQ4_Pos)            /*!< 0x7C000000 */
+#define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0                (0x01U << ADC_JSQR_JSQ4_Pos)            /*!< 0x04000000 */
+#define ADC_JSQR_JSQ4_1                (0x02U << ADC_JSQR_JSQ4_Pos)            /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_2                (0x04U << ADC_JSQR_JSQ4_Pos)            /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_3                (0x08U << ADC_JSQR_JSQ4_Pos)            /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_4                (0x10U << ADC_JSQR_JSQ4_Pos)            /*!< 0x40000000 */
+
+/********************  Bit definition for ADC_OFR1 register  ******************/
+#define ADC_OFR1_OFFSET1_Pos           (0U)                                    
+#define ADC_OFR1_OFFSET1_Msk           (0xFFFU << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
+#define ADC_OFR1_OFFSET1_0             (0x001U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET1_1             (0x002U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET1_2             (0x004U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET1_3             (0x008U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET1_4             (0x010U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET1_5             (0x020U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET1_6             (0x040U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET1_7             (0x080U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET1_8             (0x100U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET1_9             (0x200U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET1_10            (0x400U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET1_11            (0x800U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR1_OFFSET1_CH_Pos        (26U)                                   
+#define ADC_OFR1_OFFSET1_CH_Msk        (0x1FU << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
+#define ADC_OFR1_OFFSET1_CH_0          (0x01U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1          (0x02U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2          (0x04U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3          (0x08U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4          (0x10U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR1_OFFSET1_EN_Pos        (31U)                                   
+#define ADC_OFR1_OFFSET1_EN_Msk        (0x1U << ADC_OFR1_OFFSET1_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
+
+/********************  Bit definition for ADC_OFR2 register  ******************/
+#define ADC_OFR2_OFFSET2_Pos           (0U)                                    
+#define ADC_OFR2_OFFSET2_Msk           (0xFFFU << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
+#define ADC_OFR2_OFFSET2_0             (0x001U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET2_1             (0x002U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET2_2             (0x004U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET2_3             (0x008U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET2_4             (0x010U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET2_5             (0x020U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET2_6             (0x040U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET2_7             (0x080U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET2_8             (0x100U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET2_9             (0x200U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET2_10            (0x400U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET2_11            (0x800U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR2_OFFSET2_CH_Pos        (26U)                                   
+#define ADC_OFR2_OFFSET2_CH_Msk        (0x1FU << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
+#define ADC_OFR2_OFFSET2_CH_0          (0x01U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1          (0x02U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2          (0x04U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3          (0x08U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4          (0x10U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR2_OFFSET2_EN_Pos        (31U)                                   
+#define ADC_OFR2_OFFSET2_EN_Msk        (0x1U << ADC_OFR2_OFFSET2_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
+
+/********************  Bit definition for ADC_OFR3 register  ******************/
+#define ADC_OFR3_OFFSET3_Pos           (0U)                                    
+#define ADC_OFR3_OFFSET3_Msk           (0xFFFU << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
+#define ADC_OFR3_OFFSET3_0             (0x001U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET3_1             (0x002U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET3_2             (0x004U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET3_3             (0x008U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET3_4             (0x010U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET3_5             (0x020U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET3_6             (0x040U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET3_7             (0x080U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET3_8             (0x100U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET3_9             (0x200U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET3_10            (0x400U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET3_11            (0x800U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR3_OFFSET3_CH_Pos        (26U)                                   
+#define ADC_OFR3_OFFSET3_CH_Msk        (0x1FU << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
+#define ADC_OFR3_OFFSET3_CH_0          (0x01U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1          (0x02U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2          (0x04U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3          (0x08U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4          (0x10U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR3_OFFSET3_EN_Pos        (31U)                                   
+#define ADC_OFR3_OFFSET3_EN_Msk        (0x1U << ADC_OFR3_OFFSET3_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
+
+/********************  Bit definition for ADC_OFR4 register  ******************/
+#define ADC_OFR4_OFFSET4_Pos           (0U)                                    
+#define ADC_OFR4_OFFSET4_Msk           (0xFFFU << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000FFF */
+#define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
+#define ADC_OFR4_OFFSET4_0             (0x001U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET4_1             (0x002U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET4_2             (0x004U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET4_3             (0x008U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET4_4             (0x010U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET4_5             (0x020U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET4_6             (0x040U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET4_7             (0x080U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET4_8             (0x100U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET4_9             (0x200U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET4_10            (0x400U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET4_11            (0x800U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000800 */
+
+#define ADC_OFR4_OFFSET4_CH_Pos        (26U)                                   
+#define ADC_OFR4_OFFSET4_CH_Msk        (0x1FU << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
+#define ADC_OFR4_OFFSET4_CH_0          (0x01U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1          (0x02U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2          (0x04U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3          (0x08U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4          (0x10U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x40000000 */
+
+#define ADC_OFR4_OFFSET4_EN_Pos        (31U)                                   
+#define ADC_OFR4_OFFSET4_EN_Msk        (0x1U << ADC_OFR4_OFFSET4_EN_Pos)       /*!< 0x80000000 */
+#define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
+
+/********************  Bit definition for ADC_JDR1 register  ******************/
+#define ADC_JDR1_JDATA_Pos             (0U)                                    
+#define ADC_JDR1_JDATA_Msk             (0xFFFFU << ADC_JDR1_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
+#define ADC_JDR1_JDATA_0               (0x0001U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1               (0x0002U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2               (0x0004U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3               (0x0008U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4               (0x0010U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5               (0x0020U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6               (0x0040U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7               (0x0080U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8               (0x0100U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9               (0x0200U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10              (0x0400U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11              (0x0800U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12              (0x1000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13              (0x2000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14              (0x4000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15              (0x8000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR2 register  ******************/
+#define ADC_JDR2_JDATA_Pos             (0U)                                    
+#define ADC_JDR2_JDATA_Msk             (0xFFFFU << ADC_JDR2_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
+#define ADC_JDR2_JDATA_0               (0x0001U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1               (0x0002U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2               (0x0004U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3               (0x0008U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4               (0x0010U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5               (0x0020U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6               (0x0040U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7               (0x0080U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8               (0x0100U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9               (0x0200U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10              (0x0400U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11              (0x0800U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12              (0x1000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13              (0x2000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14              (0x4000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15              (0x8000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR3 register  ******************/
+#define ADC_JDR3_JDATA_Pos             (0U)                                    
+#define ADC_JDR3_JDATA_Msk             (0xFFFFU << ADC_JDR3_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
+#define ADC_JDR3_JDATA_0               (0x0001U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1               (0x0002U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2               (0x0004U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3               (0x0008U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4               (0x0010U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5               (0x0020U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6               (0x0040U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7               (0x0080U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8               (0x0100U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9               (0x0200U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10              (0x0400U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11              (0x0800U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12              (0x1000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13              (0x2000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14              (0x4000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15              (0x8000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_JDR4 register  ******************/
+#define ADC_JDR4_JDATA_Pos             (0U)                                    
+#define ADC_JDR4_JDATA_Msk             (0xFFFFU << ADC_JDR4_JDATA_Pos)         /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
+#define ADC_JDR4_JDATA_0               (0x0001U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1               (0x0002U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2               (0x0004U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3               (0x0008U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4               (0x0010U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5               (0x0020U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6               (0x0040U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7               (0x0080U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8               (0x0100U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9               (0x0200U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10              (0x0400U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11              (0x0800U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12              (0x1000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13              (0x2000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14              (0x4000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15              (0x8000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00008000 */
+
+/********************  Bit definition for ADC_AWD2CR register  ****************/
+#define ADC_AWD2CR_AWD2CH_Pos          (0U)                                    
+#define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x0007FFFF */
+#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
+#define ADC_AWD2CR_AWD2CH_0            (0x00001U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1            (0x00002U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2            (0x00004U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3            (0x00008U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4            (0x00010U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5            (0x00020U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6            (0x00040U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7            (0x00080U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8            (0x00100U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9            (0x00200U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10           (0x00400U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11           (0x00800U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12           (0x01000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13           (0x02000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14           (0x04000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15           (0x08000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16           (0x10000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17           (0x20000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18           (0x40000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_AWD3CR register  ****************/
+#define ADC_AWD3CR_AWD3CH_Pos          (0U)                                    
+#define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x0007FFFF */
+#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
+#define ADC_AWD3CR_AWD3CH_0            (0x00001U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1            (0x00002U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2            (0x00004U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3            (0x00008U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4            (0x00010U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5            (0x00020U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6            (0x00040U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7            (0x00080U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8            (0x00100U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9            (0x00200U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10           (0x00400U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11           (0x00800U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12           (0x01000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13           (0x02000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14           (0x04000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15           (0x08000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16           (0x10000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17           (0x20000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18           (0x40000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_DIFSEL register  ****************/
+#define ADC_DIFSEL_DIFSEL_Pos          (0U)                                    
+#define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x0007FFFF */
+#define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
+#define ADC_DIFSEL_DIFSEL_0            (0x00001U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1            (0x00002U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2            (0x00004U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3            (0x00008U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4            (0x00010U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5            (0x00020U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6            (0x00040U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7            (0x00080U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8            (0x00100U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9            (0x00200U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10           (0x00400U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11           (0x00800U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12           (0x01000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13           (0x02000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14           (0x04000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15           (0x08000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16           (0x10000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17           (0x20000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18           (0x40000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00040000 */
+
+/********************  Bit definition for ADC_CALFACT register  ***************/
+#define ADC_CALFACT_CALFACT_S_Pos      (0U)                                    
+#define ADC_CALFACT_CALFACT_S_Msk      (0x7FU << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0        (0x01U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1        (0x02U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2        (0x04U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3        (0x08U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4        (0x10U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5        (0x20U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6        (0x40U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000040 */
+
+#define ADC_CALFACT_CALFACT_D_Pos      (16U)                                   
+#define ADC_CALFACT_CALFACT_D_Msk      (0x7FU << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x007F0000 */
+#define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
+#define ADC_CALFACT_CALFACT_D_0        (0x01U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1        (0x02U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2        (0x04U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3        (0x08U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4        (0x10U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5        (0x20U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6        (0x40U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00400000 */
+
+/*************************  ADC Common registers  *****************************/
+/********************  Bit definition for ADC_CSR register  *******************/
+#define ADC_CSR_ADRDY_MST_Pos          (0U)                                    
+#define ADC_CSR_ADRDY_MST_Msk          (0x1U << ADC_CSR_ADRDY_MST_Pos)         /*!< 0x00000001 */
+#define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
+#define ADC_CSR_EOSMP_MST_Pos          (1U)                                    
+#define ADC_CSR_EOSMP_MST_Msk          (0x1U << ADC_CSR_EOSMP_MST_Pos)         /*!< 0x00000002 */
+#define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
+#define ADC_CSR_EOC_MST_Pos            (2U)                                    
+#define ADC_CSR_EOC_MST_Msk            (0x1U << ADC_CSR_EOC_MST_Pos)           /*!< 0x00000004 */
+#define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_MST_Pos            (3U)                                    
+#define ADC_CSR_EOS_MST_Msk            (0x1U << ADC_CSR_EOS_MST_Pos)           /*!< 0x00000008 */
+#define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_MST_Pos            (4U)                                    
+#define ADC_CSR_OVR_MST_Msk            (0x1U << ADC_CSR_OVR_MST_Pos)           /*!< 0x00000010 */
+#define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
+#define ADC_CSR_JEOC_MST_Pos           (5U)                                    
+#define ADC_CSR_JEOC_MST_Msk           (0x1U << ADC_CSR_JEOC_MST_Pos)          /*!< 0x00000020 */
+#define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_MST_Pos           (6U)                                    
+#define ADC_CSR_JEOS_MST_Msk           (0x1U << ADC_CSR_JEOS_MST_Pos)          /*!< 0x00000040 */
+#define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_MST_Pos           (7U)                                    
+#define ADC_CSR_AWD1_MST_Msk           (0x1U << ADC_CSR_AWD1_MST_Pos)          /*!< 0x00000080 */
+#define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
+#define ADC_CSR_AWD2_MST_Pos           (8U)                                    
+#define ADC_CSR_AWD2_MST_Msk           (0x1U << ADC_CSR_AWD2_MST_Pos)          /*!< 0x00000100 */
+#define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
+#define ADC_CSR_AWD3_MST_Pos           (9U)                                    
+#define ADC_CSR_AWD3_MST_Msk           (0x1U << ADC_CSR_AWD3_MST_Pos)          /*!< 0x00000200 */
+#define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
+#define ADC_CSR_JQOVF_MST_Pos          (10U)                                   
+#define ADC_CSR_JQOVF_MST_Msk          (0x1U << ADC_CSR_JQOVF_MST_Pos)         /*!< 0x00000400 */
+#define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */
+
+#define ADC_CSR_ADRDY_SLV_Pos          (16U)                                   
+#define ADC_CSR_ADRDY_SLV_Msk          (0x1U << ADC_CSR_ADRDY_SLV_Pos)         /*!< 0x00010000 */
+#define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
+#define ADC_CSR_EOSMP_SLV_Pos          (17U)                                   
+#define ADC_CSR_EOSMP_SLV_Msk          (0x1U << ADC_CSR_EOSMP_SLV_Pos)         /*!< 0x00020000 */
+#define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
+#define ADC_CSR_EOC_SLV_Pos            (18U)                                   
+#define ADC_CSR_EOC_SLV_Msk            (0x1U << ADC_CSR_EOC_SLV_Pos)           /*!< 0x00040000 */
+#define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
+#define ADC_CSR_EOS_SLV_Pos            (19U)                                   
+#define ADC_CSR_EOS_SLV_Msk            (0x1U << ADC_CSR_EOS_SLV_Pos)           /*!< 0x00080000 */
+#define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
+#define ADC_CSR_OVR_SLV_Pos            (20U)                                   
+#define ADC_CSR_OVR_SLV_Msk            (0x1U << ADC_CSR_OVR_SLV_Pos)           /*!< 0x00100000 */
+#define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
+#define ADC_CSR_JEOC_SLV_Pos           (21U)                                   
+#define ADC_CSR_JEOC_SLV_Msk           (0x1U << ADC_CSR_JEOC_SLV_Pos)          /*!< 0x00200000 */
+#define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
+#define ADC_CSR_JEOS_SLV_Pos           (22U)                                   
+#define ADC_CSR_JEOS_SLV_Msk           (0x1U << ADC_CSR_JEOS_SLV_Pos)          /*!< 0x00400000 */
+#define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
+#define ADC_CSR_AWD1_SLV_Pos           (23U)                                   
+#define ADC_CSR_AWD1_SLV_Msk           (0x1U << ADC_CSR_AWD1_SLV_Pos)          /*!< 0x00800000 */
+#define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
+#define ADC_CSR_AWD2_SLV_Pos           (24U)                                   
+#define ADC_CSR_AWD2_SLV_Msk           (0x1U << ADC_CSR_AWD2_SLV_Pos)          /*!< 0x01000000 */
+#define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
+#define ADC_CSR_AWD3_SLV_Pos           (25U)                                   
+#define ADC_CSR_AWD3_SLV_Msk           (0x1U << ADC_CSR_AWD3_SLV_Pos)          /*!< 0x02000000 */
+#define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
+#define ADC_CSR_JQOVF_SLV_Pos          (26U)                                   
+#define ADC_CSR_JQOVF_SLV_Msk          (0x1U << ADC_CSR_JQOVF_SLV_Pos)         /*!< 0x04000000 */
+#define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */
+
+/********************  Bit definition for ADC_CCR register  *******************/
+#define ADC_CCR_DUAL_Pos               (0U)                                    
+#define ADC_CCR_DUAL_Msk               (0x1FU << ADC_CCR_DUAL_Pos)             /*!< 0x0000001F */
+#define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
+#define ADC_CCR_DUAL_0                 (0x01U << ADC_CCR_DUAL_Pos)             /*!< 0x00000001 */
+#define ADC_CCR_DUAL_1                 (0x02U << ADC_CCR_DUAL_Pos)             /*!< 0x00000002 */
+#define ADC_CCR_DUAL_2                 (0x04U << ADC_CCR_DUAL_Pos)             /*!< 0x00000004 */
+#define ADC_CCR_DUAL_3                 (0x08U << ADC_CCR_DUAL_Pos)             /*!< 0x00000008 */
+#define ADC_CCR_DUAL_4                 (0x10U << ADC_CCR_DUAL_Pos)             /*!< 0x00000010 */
+
+#define ADC_CCR_DELAY_Pos              (8U)                                    
+#define ADC_CCR_DELAY_Msk              (0xFU << ADC_CCR_DELAY_Pos)             /*!< 0x00000F00 */
+#define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0                (0x1U << ADC_CCR_DELAY_Pos)             /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1                (0x2U << ADC_CCR_DELAY_Pos)             /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2                (0x4U << ADC_CCR_DELAY_Pos)             /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3                (0x8U << ADC_CCR_DELAY_Pos)             /*!< 0x00000800 */
+
+#define ADC_CCR_DMACFG_Pos             (13U)                                   
+#define ADC_CCR_DMACFG_Msk             (0x1U << ADC_CCR_DMACFG_Pos)            /*!< 0x00002000 */
+#define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */
+
+#define ADC_CCR_MDMA_Pos               (14U)                                   
+#define ADC_CCR_MDMA_Msk               (0x3U << ADC_CCR_MDMA_Pos)              /*!< 0x0000C000 */
+#define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */
+#define ADC_CCR_MDMA_0                 (0x1U << ADC_CCR_MDMA_Pos)              /*!< 0x00004000 */
+#define ADC_CCR_MDMA_1                 (0x2U << ADC_CCR_MDMA_Pos)              /*!< 0x00008000 */
+
+#define ADC_CCR_CKMODE_Pos             (16U)                                   
+#define ADC_CCR_CKMODE_Msk             (0x3U << ADC_CCR_CKMODE_Pos)            /*!< 0x00030000 */
+#define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
+#define ADC_CCR_CKMODE_0               (0x1U << ADC_CCR_CKMODE_Pos)            /*!< 0x00010000 */
+#define ADC_CCR_CKMODE_1               (0x2U << ADC_CCR_CKMODE_Pos)            /*!< 0x00020000 */
+
+#define ADC_CCR_PRESC_Pos              (18U)                                   
+#define ADC_CCR_PRESC_Msk              (0xFU << ADC_CCR_PRESC_Pos)             /*!< 0x003C0000 */
+#define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
+#define ADC_CCR_PRESC_0                (0x1U << ADC_CCR_PRESC_Pos)             /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1                (0x2U << ADC_CCR_PRESC_Pos)             /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2                (0x4U << ADC_CCR_PRESC_Pos)             /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3                (0x8U << ADC_CCR_PRESC_Pos)             /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos             (22U)                                   
+#define ADC_CCR_VREFEN_Msk             (0x1U << ADC_CCR_VREFEN_Pos)            /*!< 0x00400000 */
+#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
+#define ADC_CCR_TSEN_Pos               (23U)                                   
+#define ADC_CCR_TSEN_Msk               (0x1U << ADC_CCR_TSEN_Pos)              /*!< 0x00800000 */
+#define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos             (24U)                                   
+#define ADC_CCR_VBATEN_Msk             (0x1U << ADC_CCR_VBATEN_Pos)            /*!< 0x01000000 */
+#define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
+
+/********************  Bit definition for ADC_CDR register  *******************/
+#define ADC_CDR_RDATA_MST_Pos          (0U)                                    
+#define ADC_CDR_RDATA_MST_Msk          (0xFFFFU << ADC_CDR_RDATA_MST_Pos)      /*!< 0x0000FFFF */
+#define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
+#define ADC_CDR_RDATA_MST_0            (0x0001U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000001 */
+#define ADC_CDR_RDATA_MST_1            (0x0002U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000002 */
+#define ADC_CDR_RDATA_MST_2            (0x0004U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000004 */
+#define ADC_CDR_RDATA_MST_3            (0x0008U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000008 */
+#define ADC_CDR_RDATA_MST_4            (0x0010U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000010 */
+#define ADC_CDR_RDATA_MST_5            (0x0020U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000020 */
+#define ADC_CDR_RDATA_MST_6            (0x0040U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000040 */
+#define ADC_CDR_RDATA_MST_7            (0x0080U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000080 */
+#define ADC_CDR_RDATA_MST_8            (0x0100U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000100 */
+#define ADC_CDR_RDATA_MST_9            (0x0200U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000200 */
+#define ADC_CDR_RDATA_MST_10           (0x0400U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000400 */
+#define ADC_CDR_RDATA_MST_11           (0x0800U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000800 */
+#define ADC_CDR_RDATA_MST_12           (0x1000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00001000 */
+#define ADC_CDR_RDATA_MST_13           (0x2000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00002000 */
+#define ADC_CDR_RDATA_MST_14           (0x4000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00004000 */
+#define ADC_CDR_RDATA_MST_15           (0x8000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00008000 */
+
+#define ADC_CDR_RDATA_SLV_Pos          (16U)                                   
+#define ADC_CDR_RDATA_SLV_Msk          (0xFFFFU << ADC_CDR_RDATA_SLV_Pos)      /*!< 0xFFFF0000 */
+#define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
+#define ADC_CDR_RDATA_SLV_0            (0x0001U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00010000 */
+#define ADC_CDR_RDATA_SLV_1            (0x0002U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00020000 */
+#define ADC_CDR_RDATA_SLV_2            (0x0004U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00040000 */
+#define ADC_CDR_RDATA_SLV_3            (0x0008U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00080000 */
+#define ADC_CDR_RDATA_SLV_4            (0x0010U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00100000 */
+#define ADC_CDR_RDATA_SLV_5            (0x0020U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00200000 */
+#define ADC_CDR_RDATA_SLV_6            (0x0040U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00400000 */
+#define ADC_CDR_RDATA_SLV_7            (0x0080U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00800000 */
+#define ADC_CDR_RDATA_SLV_8            (0x0100U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x01000000 */
+#define ADC_CDR_RDATA_SLV_9            (0x0200U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x02000000 */
+#define ADC_CDR_RDATA_SLV_10           (0x0400U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x04000000 */
+#define ADC_CDR_RDATA_SLV_11           (0x0800U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x08000000 */
+#define ADC_CDR_RDATA_SLV_12           (0x1000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x10000000 */
+#define ADC_CDR_RDATA_SLV_13           (0x2000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x20000000 */
+#define ADC_CDR_RDATA_SLV_14           (0x4000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x40000000 */
+#define ADC_CDR_RDATA_SLV_15           (0x8000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x80000000 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define CAN_MCR_INRQ_Pos       (0U)                                            
+#define CAN_MCR_INRQ_Msk       (0x1U << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
+#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos      (1U)                                            
+#define CAN_MCR_SLEEP_Msk      (0x1U << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
+#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos       (2U)                                            
+#define CAN_MCR_TXFP_Msk       (0x1U << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
+#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos       (3U)                                            
+#define CAN_MCR_RFLM_Msk       (0x1U << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
+#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos       (4U)                                            
+#define CAN_MCR_NART_Msk       (0x1U << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
+#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos       (5U)                                            
+#define CAN_MCR_AWUM_Msk       (0x1U << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
+#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos       (6U)                                            
+#define CAN_MCR_ABOM_Msk       (0x1U << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
+#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos       (7U)                                            
+#define CAN_MCR_TTCM_Msk       (0x1U << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
+#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos      (15U)                                           
+#define CAN_MCR_RESET_Msk      (0x1U << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
+#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
+
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define CAN_MSR_INAK_Pos       (0U)                                            
+#define CAN_MSR_INAK_Msk       (0x1U << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
+#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos       (1U)                                            
+#define CAN_MSR_SLAK_Msk       (0x1U << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
+#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos       (2U)                                            
+#define CAN_MSR_ERRI_Msk       (0x1U << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
+#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos       (3U)                                            
+#define CAN_MSR_WKUI_Msk       (0x1U << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
+#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos      (4U)                                            
+#define CAN_MSR_SLAKI_Msk      (0x1U << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
+#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos        (8U)                                            
+#define CAN_MSR_TXM_Msk        (0x1U << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
+#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos        (9U)                                            
+#define CAN_MSR_RXM_Msk        (0x1U << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
+#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos       (10U)                                           
+#define CAN_MSR_SAMP_Msk       (0x1U << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
+#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos         (11U)                                           
+#define CAN_MSR_RX_Msk         (0x1U << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
+#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define CAN_TSR_RQCP0_Pos      (0U)                                            
+#define CAN_TSR_RQCP0_Msk      (0x1U << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
+#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos      (1U)                                            
+#define CAN_TSR_TXOK0_Msk      (0x1U << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
+#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos      (2U)                                            
+#define CAN_TSR_ALST0_Msk      (0x1U << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
+#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos      (3U)                                            
+#define CAN_TSR_TERR0_Msk      (0x1U << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
+#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos      (7U)                                            
+#define CAN_TSR_ABRQ0_Msk      (0x1U << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos      (8U)                                            
+#define CAN_TSR_RQCP1_Msk      (0x1U << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
+#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos      (9U)                                            
+#define CAN_TSR_TXOK1_Msk      (0x1U << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
+#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos      (10U)                                           
+#define CAN_TSR_ALST1_Msk      (0x1U << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
+#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos      (11U)                                           
+#define CAN_TSR_TERR1_Msk      (0x1U << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
+#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos      (15U)                                           
+#define CAN_TSR_ABRQ1_Msk      (0x1U << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos      (16U)                                           
+#define CAN_TSR_RQCP2_Msk      (0x1U << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
+#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos      (17U)                                           
+#define CAN_TSR_TXOK2_Msk      (0x1U << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
+#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos      (18U)                                           
+#define CAN_TSR_ALST2_Msk      (0x1U << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
+#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos      (19U)                                           
+#define CAN_TSR_TERR2_Msk      (0x1U << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
+#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos      (23U)                                           
+#define CAN_TSR_ABRQ2_Msk      (0x1U << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos       (24U)                                           
+#define CAN_TSR_CODE_Msk       (0x3U << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
+#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos        (26U)                                           
+#define CAN_TSR_TME_Msk        (0x7U << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
+#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos       (26U)                                           
+#define CAN_TSR_TME0_Msk       (0x1U << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
+#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos       (27U)                                           
+#define CAN_TSR_TME1_Msk       (0x1U << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
+#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos       (28U)                                           
+#define CAN_TSR_TME2_Msk       (0x1U << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
+#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos        (29U)                                           
+#define CAN_TSR_LOW_Msk        (0x7U << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
+#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos       (29U)                                           
+#define CAN_TSR_LOW0_Msk       (0x1U << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
+#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos       (30U)                                           
+#define CAN_TSR_LOW1_Msk       (0x1U << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
+#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos       (31U)                                           
+#define CAN_TSR_LOW2_Msk       (0x1U << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
+#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define CAN_RF0R_FMP0_Pos      (0U)                                            
+#define CAN_RF0R_FMP0_Msk      (0x3U << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
+#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos     (3U)                                            
+#define CAN_RF0R_FULL0_Msk     (0x1U << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
+#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos     (4U)                                            
+#define CAN_RF0R_FOVR0_Msk     (0x1U << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos     (5U)                                            
+#define CAN_RF0R_RFOM0_Msk     (0x1U << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define CAN_RF1R_FMP1_Pos      (0U)                                            
+#define CAN_RF1R_FMP1_Msk      (0x3U << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
+#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos     (3U)                                            
+#define CAN_RF1R_FULL1_Msk     (0x1U << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
+#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos     (4U)                                            
+#define CAN_RF1R_FOVR1_Msk     (0x1U << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos     (5U)                                            
+#define CAN_RF1R_RFOM1_Msk     (0x1U << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define CAN_IER_TMEIE_Pos      (0U)                                            
+#define CAN_IER_TMEIE_Msk      (0x1U << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
+#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos     (1U)                                            
+#define CAN_IER_FMPIE0_Msk     (0x1U << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
+#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos      (2U)                                            
+#define CAN_IER_FFIE0_Msk      (0x1U << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
+#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos     (3U)                                            
+#define CAN_IER_FOVIE0_Msk     (0x1U << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
+#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos     (4U)                                            
+#define CAN_IER_FMPIE1_Msk     (0x1U << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
+#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos      (5U)                                            
+#define CAN_IER_FFIE1_Msk      (0x1U << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
+#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos     (6U)                                            
+#define CAN_IER_FOVIE1_Msk     (0x1U << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
+#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos      (8U)                                            
+#define CAN_IER_EWGIE_Msk      (0x1U << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
+#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos      (9U)                                            
+#define CAN_IER_EPVIE_Msk      (0x1U << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
+#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos      (10U)                                           
+#define CAN_IER_BOFIE_Msk      (0x1U << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
+#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos      (11U)                                           
+#define CAN_IER_LECIE_Msk      (0x1U << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
+#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos      (15U)                                           
+#define CAN_IER_ERRIE_Msk      (0x1U << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
+#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos      (16U)                                           
+#define CAN_IER_WKUIE_Msk      (0x1U << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
+#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos      (17U)                                           
+#define CAN_IER_SLKIE_Msk      (0x1U << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
+#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define CAN_ESR_EWGF_Pos       (0U)                                            
+#define CAN_ESR_EWGF_Msk       (0x1U << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
+#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos       (1U)                                            
+#define CAN_ESR_EPVF_Msk       (0x1U << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
+#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos       (2U)                                            
+#define CAN_ESR_BOFF_Msk       (0x1U << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
+#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos        (4U)                                            
+#define CAN_ESR_LEC_Msk        (0x7U << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
+#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0          (0x1U << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
+#define CAN_ESR_LEC_1          (0x2U << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
+#define CAN_ESR_LEC_2          (0x4U << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos        (16U)                                           
+#define CAN_ESR_TEC_Msk        (0xFFU << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
+#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos        (24U)                                           
+#define CAN_ESR_REC_Msk        (0xFFU << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
+#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define CAN_BTR_BRP_Pos        (0U)                                            
+#define CAN_BTR_BRP_Msk        (0x3FFU << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
+#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos        (16U)                                           
+#define CAN_BTR_TS1_Msk        (0xFU << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
+#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0          (0x1U << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
+#define CAN_BTR_TS1_1          (0x2U << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
+#define CAN_BTR_TS1_2          (0x4U << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
+#define CAN_BTR_TS1_3          (0x8U << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos        (20U)                                           
+#define CAN_BTR_TS2_Msk        (0x7U << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
+#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0          (0x1U << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
+#define CAN_BTR_TS2_1          (0x2U << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
+#define CAN_BTR_TS2_2          (0x4U << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos        (24U)                                           
+#define CAN_BTR_SJW_Msk        (0x3U << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
+#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0          (0x1U << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
+#define CAN_BTR_SJW_1          (0x2U << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos       (30U)                                           
+#define CAN_BTR_LBKM_Msk       (0x1U << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
+#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos       (31U)                                           
+#define CAN_BTR_SILM_Msk       (0x1U << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
+#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define CAN_TI0R_TXRQ_Pos      (0U)                                            
+#define CAN_TI0R_TXRQ_Msk      (0x1U << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos       (1U)                                            
+#define CAN_TI0R_RTR_Msk       (0x1U << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos       (2U)                                            
+#define CAN_TI0R_IDE_Msk       (0x1U << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos      (3U)                                            
+#define CAN_TI0R_EXID_Msk      (0x3FFFFU << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos      (21U)                                           
+#define CAN_TI0R_STID_Msk      (0x7FFU << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define CAN_TDT0R_DLC_Pos      (0U)                                            
+#define CAN_TDT0R_DLC_Msk      (0xFU << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos      (8U)                                            
+#define CAN_TDT0R_TGT_Msk      (0x1U << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos     (16U)                                           
+#define CAN_TDT0R_TIME_Msk     (0xFFFFU << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define CAN_TDL0R_DATA0_Pos    (0U)                                            
+#define CAN_TDL0R_DATA0_Msk    (0xFFU << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos    (8U)                                            
+#define CAN_TDL0R_DATA1_Msk    (0xFFU << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos    (16U)                                           
+#define CAN_TDL0R_DATA2_Msk    (0xFFU << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos    (24U)                                           
+#define CAN_TDL0R_DATA3_Msk    (0xFFU << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define CAN_TDH0R_DATA4_Pos    (0U)                                            
+#define CAN_TDH0R_DATA4_Msk    (0xFFU << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos    (8U)                                            
+#define CAN_TDH0R_DATA5_Msk    (0xFFU << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos    (16U)                                           
+#define CAN_TDH0R_DATA6_Msk    (0xFFU << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos    (24U)                                           
+#define CAN_TDH0R_DATA7_Msk    (0xFFU << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define CAN_TI1R_TXRQ_Pos      (0U)                                            
+#define CAN_TI1R_TXRQ_Msk      (0x1U << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos       (1U)                                            
+#define CAN_TI1R_RTR_Msk       (0x1U << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos       (2U)                                            
+#define CAN_TI1R_IDE_Msk       (0x1U << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos      (3U)                                            
+#define CAN_TI1R_EXID_Msk      (0x3FFFFU << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos      (21U)                                           
+#define CAN_TI1R_STID_Msk      (0x7FFU << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define CAN_TDT1R_DLC_Pos      (0U)                                            
+#define CAN_TDT1R_DLC_Msk      (0xFU << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos      (8U)                                            
+#define CAN_TDT1R_TGT_Msk      (0x1U << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos     (16U)                                           
+#define CAN_TDT1R_TIME_Msk     (0xFFFFU << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define CAN_TDL1R_DATA0_Pos    (0U)                                            
+#define CAN_TDL1R_DATA0_Msk    (0xFFU << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos    (8U)                                            
+#define CAN_TDL1R_DATA1_Msk    (0xFFU << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos    (16U)                                           
+#define CAN_TDL1R_DATA2_Msk    (0xFFU << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos    (24U)                                           
+#define CAN_TDL1R_DATA3_Msk    (0xFFU << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define CAN_TDH1R_DATA4_Pos    (0U)                                            
+#define CAN_TDH1R_DATA4_Msk    (0xFFU << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos    (8U)                                            
+#define CAN_TDH1R_DATA5_Msk    (0xFFU << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos    (16U)                                           
+#define CAN_TDH1R_DATA6_Msk    (0xFFU << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos    (24U)                                           
+#define CAN_TDH1R_DATA7_Msk    (0xFFU << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define CAN_TI2R_TXRQ_Pos      (0U)                                            
+#define CAN_TI2R_TXRQ_Msk      (0x1U << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos       (1U)                                            
+#define CAN_TI2R_RTR_Msk       (0x1U << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos       (2U)                                            
+#define CAN_TI2R_IDE_Msk       (0x1U << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos      (3U)                                            
+#define CAN_TI2R_EXID_Msk      (0x3FFFFU << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos      (21U)                                           
+#define CAN_TI2R_STID_Msk      (0x7FFU << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/
+#define CAN_TDT2R_DLC_Pos      (0U)                                            
+#define CAN_TDT2R_DLC_Msk      (0xFU << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos      (8U)                                            
+#define CAN_TDT2R_TGT_Msk      (0x1U << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos     (16U)                                           
+#define CAN_TDT2R_TIME_Msk     (0xFFFFU << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define CAN_TDL2R_DATA0_Pos    (0U)                                            
+#define CAN_TDL2R_DATA0_Msk    (0xFFU << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos    (8U)                                            
+#define CAN_TDL2R_DATA1_Msk    (0xFFU << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos    (16U)                                           
+#define CAN_TDL2R_DATA2_Msk    (0xFFU << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos    (24U)                                           
+#define CAN_TDL2R_DATA3_Msk    (0xFFU << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define CAN_TDH2R_DATA4_Pos    (0U)                                            
+#define CAN_TDH2R_DATA4_Msk    (0xFFU << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos    (8U)                                            
+#define CAN_TDH2R_DATA5_Msk    (0xFFU << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos    (16U)                                           
+#define CAN_TDH2R_DATA6_Msk    (0xFFU << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos    (24U)                                           
+#define CAN_TDH2R_DATA7_Msk    (0xFFU << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define CAN_RI0R_RTR_Pos       (1U)                                            
+#define CAN_RI0R_RTR_Msk       (0x1U << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos       (2U)                                            
+#define CAN_RI0R_IDE_Msk       (0x1U << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos      (3U)                                            
+#define CAN_RI0R_EXID_Msk      (0x3FFFFU << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos      (21U)                                           
+#define CAN_RI0R_STID_Msk      (0x7FFU << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define CAN_RDT0R_DLC_Pos      (0U)                                            
+#define CAN_RDT0R_DLC_Msk      (0xFU << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos      (8U)                                            
+#define CAN_RDT0R_FMI_Msk      (0xFFU << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos     (16U)                                           
+#define CAN_RDT0R_TIME_Msk     (0xFFFFU << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define CAN_RDL0R_DATA0_Pos    (0U)                                            
+#define CAN_RDL0R_DATA0_Msk    (0xFFU << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos    (8U)                                            
+#define CAN_RDL0R_DATA1_Msk    (0xFFU << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos    (16U)                                           
+#define CAN_RDL0R_DATA2_Msk    (0xFFU << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos    (24U)                                           
+#define CAN_RDL0R_DATA3_Msk    (0xFFU << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define CAN_RDH0R_DATA4_Pos    (0U)                                            
+#define CAN_RDH0R_DATA4_Msk    (0xFFU << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos    (8U)                                            
+#define CAN_RDH0R_DATA5_Msk    (0xFFU << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos    (16U)                                           
+#define CAN_RDH0R_DATA6_Msk    (0xFFU << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos    (24U)                                           
+#define CAN_RDH0R_DATA7_Msk    (0xFFU << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define CAN_RI1R_RTR_Pos       (1U)                                            
+#define CAN_RI1R_RTR_Msk       (0x1U << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos       (2U)                                            
+#define CAN_RI1R_IDE_Msk       (0x1U << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos      (3U)                                            
+#define CAN_RI1R_EXID_Msk      (0x3FFFFU << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos      (21U)                                           
+#define CAN_RI1R_STID_Msk      (0x7FFU << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define CAN_RDT1R_DLC_Pos      (0U)                                            
+#define CAN_RDT1R_DLC_Msk      (0xFU << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos      (8U)                                            
+#define CAN_RDT1R_FMI_Msk      (0xFFU << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos     (16U)                                           
+#define CAN_RDT1R_TIME_Msk     (0xFFFFU << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define CAN_RDL1R_DATA0_Pos    (0U)                                            
+#define CAN_RDL1R_DATA0_Msk    (0xFFU << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos    (8U)                                            
+#define CAN_RDL1R_DATA1_Msk    (0xFFU << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos    (16U)                                           
+#define CAN_RDL1R_DATA2_Msk    (0xFFU << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos    (24U)                                           
+#define CAN_RDL1R_DATA3_Msk    (0xFFU << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define CAN_RDH1R_DATA4_Pos    (0U)                                            
+#define CAN_RDH1R_DATA4_Msk    (0xFFU << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos    (8U)                                            
+#define CAN_RDH1R_DATA5_Msk    (0xFFU << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos    (16U)                                           
+#define CAN_RDH1R_DATA6_Msk    (0xFFU << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos    (24U)                                           
+#define CAN_RDH1R_DATA7_Msk    (0xFFU << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define CAN_FMR_FINIT_Pos      (0U)                                            
+#define CAN_FMR_FINIT_Msk      (0x1U << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
+#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB_Pos     (8U)                                            
+#define CAN_FMR_CAN2SB_Msk     (0x3FU << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */
+#define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank  */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define CAN_FM1R_FBM_Pos       (0U)                                            
+#define CAN_FM1R_FBM_Msk       (0x3FFFU << CAN_FM1R_FBM_Pos)                   /*!< 0x00003FFF */
+#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos      (0U)                                            
+#define CAN_FM1R_FBM0_Msk      (0x1U << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
+#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos      (1U)                                            
+#define CAN_FM1R_FBM1_Msk      (0x1U << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
+#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos      (2U)                                            
+#define CAN_FM1R_FBM2_Msk      (0x1U << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
+#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos      (3U)                                            
+#define CAN_FM1R_FBM3_Msk      (0x1U << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
+#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos      (4U)                                            
+#define CAN_FM1R_FBM4_Msk      (0x1U << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
+#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos      (5U)                                            
+#define CAN_FM1R_FBM5_Msk      (0x1U << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
+#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos      (6U)                                            
+#define CAN_FM1R_FBM6_Msk      (0x1U << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
+#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos      (7U)                                            
+#define CAN_FM1R_FBM7_Msk      (0x1U << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
+#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos      (8U)                                            
+#define CAN_FM1R_FBM8_Msk      (0x1U << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
+#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos      (9U)                                            
+#define CAN_FM1R_FBM9_Msk      (0x1U << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
+#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos     (10U)                                           
+#define CAN_FM1R_FBM10_Msk     (0x1U << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
+#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos     (11U)                                           
+#define CAN_FM1R_FBM11_Msk     (0x1U << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
+#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos     (12U)                                           
+#define CAN_FM1R_FBM12_Msk     (0x1U << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
+#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos     (13U)                                           
+#define CAN_FM1R_FBM13_Msk     (0x1U << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
+#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define CAN_FS1R_FSC_Pos       (0U)                                            
+#define CAN_FS1R_FSC_Msk       (0x3FFFU << CAN_FS1R_FSC_Pos)                   /*!< 0x00003FFF */
+#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos      (0U)                                            
+#define CAN_FS1R_FSC0_Msk      (0x1U << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
+#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos      (1U)                                            
+#define CAN_FS1R_FSC1_Msk      (0x1U << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
+#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos      (2U)                                            
+#define CAN_FS1R_FSC2_Msk      (0x1U << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
+#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos      (3U)                                            
+#define CAN_FS1R_FSC3_Msk      (0x1U << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
+#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos      (4U)                                            
+#define CAN_FS1R_FSC4_Msk      (0x1U << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
+#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos      (5U)                                            
+#define CAN_FS1R_FSC5_Msk      (0x1U << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
+#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos      (6U)                                            
+#define CAN_FS1R_FSC6_Msk      (0x1U << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
+#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos      (7U)                                            
+#define CAN_FS1R_FSC7_Msk      (0x1U << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
+#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos      (8U)                                            
+#define CAN_FS1R_FSC8_Msk      (0x1U << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
+#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos      (9U)                                            
+#define CAN_FS1R_FSC9_Msk      (0x1U << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
+#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos     (10U)                                           
+#define CAN_FS1R_FSC10_Msk     (0x1U << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
+#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos     (11U)                                           
+#define CAN_FS1R_FSC11_Msk     (0x1U << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
+#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos     (12U)                                           
+#define CAN_FS1R_FSC12_Msk     (0x1U << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
+#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos     (13U)                                           
+#define CAN_FS1R_FSC13_Msk     (0x1U << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
+#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define CAN_FFA1R_FFA_Pos      (0U)                                            
+#define CAN_FFA1R_FFA_Msk      (0x3FFFU << CAN_FFA1R_FFA_Pos)                  /*!< 0x00003FFF */
+#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos     (0U)                                            
+#define CAN_FFA1R_FFA0_Msk     (0x1U << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1_Pos     (1U)                                            
+#define CAN_FFA1R_FFA1_Msk     (0x1U << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2_Pos     (2U)                                            
+#define CAN_FFA1R_FFA2_Msk     (0x1U << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3_Pos     (3U)                                            
+#define CAN_FFA1R_FFA3_Msk     (0x1U << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4_Pos     (4U)                                            
+#define CAN_FFA1R_FFA4_Msk     (0x1U << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5_Pos     (5U)                                            
+#define CAN_FFA1R_FFA5_Msk     (0x1U << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6_Pos     (6U)                                            
+#define CAN_FFA1R_FFA6_Msk     (0x1U << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7_Pos     (7U)                                            
+#define CAN_FFA1R_FFA7_Msk     (0x1U << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8_Pos     (8U)                                            
+#define CAN_FFA1R_FFA8_Msk     (0x1U << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9_Pos     (9U)                                            
+#define CAN_FFA1R_FFA9_Msk     (0x1U << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10_Pos    (10U)                                           
+#define CAN_FFA1R_FFA10_Msk    (0x1U << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11_Pos    (11U)                                           
+#define CAN_FFA1R_FFA11_Msk    (0x1U << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12_Pos    (12U)                                           
+#define CAN_FFA1R_FFA12_Msk    (0x1U << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13_Pos    (13U)                                           
+#define CAN_FFA1R_FFA13_Msk    (0x1U << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define CAN_FA1R_FACT_Pos      (0U)                                            
+#define CAN_FA1R_FACT_Msk      (0x3FFFU << CAN_FA1R_FACT_Pos)                  /*!< 0x00003FFF */
+#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos     (0U)                                            
+#define CAN_FA1R_FACT0_Msk     (0x1U << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
+#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1_Pos     (1U)                                            
+#define CAN_FA1R_FACT1_Msk     (0x1U << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
+#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2_Pos     (2U)                                            
+#define CAN_FA1R_FACT2_Msk     (0x1U << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
+#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3_Pos     (3U)                                            
+#define CAN_FA1R_FACT3_Msk     (0x1U << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
+#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4_Pos     (4U)                                            
+#define CAN_FA1R_FACT4_Msk     (0x1U << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
+#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5_Pos     (5U)                                            
+#define CAN_FA1R_FACT5_Msk     (0x1U << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
+#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6_Pos     (6U)                                            
+#define CAN_FA1R_FACT6_Msk     (0x1U << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
+#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7_Pos     (7U)                                            
+#define CAN_FA1R_FACT7_Msk     (0x1U << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
+#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8_Pos     (8U)                                            
+#define CAN_FA1R_FACT8_Msk     (0x1U << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
+#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9_Pos     (9U)                                            
+#define CAN_FA1R_FACT9_Msk     (0x1U << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
+#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10_Pos    (10U)                                           
+#define CAN_FA1R_FACT10_Msk    (0x1U << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
+#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11_Pos    (11U)                                           
+#define CAN_FA1R_FACT11_Msk    (0x1U << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
+#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12_Pos    (12U)                                           
+#define CAN_FA1R_FACT12_Msk    (0x1U << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
+#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13_Pos    (13U)                                           
+#define CAN_FA1R_FACT13_Msk    (0x1U << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
+#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define CAN_F0R1_FB0_Pos       (0U)                                            
+#define CAN_F0R1_FB0_Msk       (0x1U << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos       (1U)                                            
+#define CAN_F0R1_FB1_Msk       (0x1U << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos       (2U)                                            
+#define CAN_F0R1_FB2_Msk       (0x1U << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos       (3U)                                            
+#define CAN_F0R1_FB3_Msk       (0x1U << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos       (4U)                                            
+#define CAN_F0R1_FB4_Msk       (0x1U << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos       (5U)                                            
+#define CAN_F0R1_FB5_Msk       (0x1U << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos       (6U)                                            
+#define CAN_F0R1_FB6_Msk       (0x1U << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos       (7U)                                            
+#define CAN_F0R1_FB7_Msk       (0x1U << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos       (8U)                                            
+#define CAN_F0R1_FB8_Msk       (0x1U << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos       (9U)                                            
+#define CAN_F0R1_FB9_Msk       (0x1U << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos      (10U)                                           
+#define CAN_F0R1_FB10_Msk      (0x1U << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos      (11U)                                           
+#define CAN_F0R1_FB11_Msk      (0x1U << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos      (12U)                                           
+#define CAN_F0R1_FB12_Msk      (0x1U << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos      (13U)                                           
+#define CAN_F0R1_FB13_Msk      (0x1U << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos      (14U)                                           
+#define CAN_F0R1_FB14_Msk      (0x1U << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos      (15U)                                           
+#define CAN_F0R1_FB15_Msk      (0x1U << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos      (16U)                                           
+#define CAN_F0R1_FB16_Msk      (0x1U << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos      (17U)                                           
+#define CAN_F0R1_FB17_Msk      (0x1U << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos      (18U)                                           
+#define CAN_F0R1_FB18_Msk      (0x1U << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos      (19U)                                           
+#define CAN_F0R1_FB19_Msk      (0x1U << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos      (20U)                                           
+#define CAN_F0R1_FB20_Msk      (0x1U << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos      (21U)                                           
+#define CAN_F0R1_FB21_Msk      (0x1U << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos      (22U)                                           
+#define CAN_F0R1_FB22_Msk      (0x1U << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos      (23U)                                           
+#define CAN_F0R1_FB23_Msk      (0x1U << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos      (24U)                                           
+#define CAN_F0R1_FB24_Msk      (0x1U << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos      (25U)                                           
+#define CAN_F0R1_FB25_Msk      (0x1U << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos      (26U)                                           
+#define CAN_F0R1_FB26_Msk      (0x1U << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos      (27U)                                           
+#define CAN_F0R1_FB27_Msk      (0x1U << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos      (28U)                                           
+#define CAN_F0R1_FB28_Msk      (0x1U << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos      (29U)                                           
+#define CAN_F0R1_FB29_Msk      (0x1U << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos      (30U)                                           
+#define CAN_F0R1_FB30_Msk      (0x1U << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos      (31U)                                           
+#define CAN_F0R1_FB31_Msk      (0x1U << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define CAN_F1R1_FB0_Pos       (0U)                                            
+#define CAN_F1R1_FB0_Msk       (0x1U << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos       (1U)                                            
+#define CAN_F1R1_FB1_Msk       (0x1U << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos       (2U)                                            
+#define CAN_F1R1_FB2_Msk       (0x1U << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos       (3U)                                            
+#define CAN_F1R1_FB3_Msk       (0x1U << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos       (4U)                                            
+#define CAN_F1R1_FB4_Msk       (0x1U << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos       (5U)                                            
+#define CAN_F1R1_FB5_Msk       (0x1U << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos       (6U)                                            
+#define CAN_F1R1_FB6_Msk       (0x1U << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos       (7U)                                            
+#define CAN_F1R1_FB7_Msk       (0x1U << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos       (8U)                                            
+#define CAN_F1R1_FB8_Msk       (0x1U << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos       (9U)                                            
+#define CAN_F1R1_FB9_Msk       (0x1U << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos      (10U)                                           
+#define CAN_F1R1_FB10_Msk      (0x1U << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos      (11U)                                           
+#define CAN_F1R1_FB11_Msk      (0x1U << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos      (12U)                                           
+#define CAN_F1R1_FB12_Msk      (0x1U << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos      (13U)                                           
+#define CAN_F1R1_FB13_Msk      (0x1U << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos      (14U)                                           
+#define CAN_F1R1_FB14_Msk      (0x1U << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos      (15U)                                           
+#define CAN_F1R1_FB15_Msk      (0x1U << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos      (16U)                                           
+#define CAN_F1R1_FB16_Msk      (0x1U << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos      (17U)                                           
+#define CAN_F1R1_FB17_Msk      (0x1U << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos      (18U)                                           
+#define CAN_F1R1_FB18_Msk      (0x1U << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos      (19U)                                           
+#define CAN_F1R1_FB19_Msk      (0x1U << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos      (20U)                                           
+#define CAN_F1R1_FB20_Msk      (0x1U << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos      (21U)                                           
+#define CAN_F1R1_FB21_Msk      (0x1U << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos      (22U)                                           
+#define CAN_F1R1_FB22_Msk      (0x1U << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos      (23U)                                           
+#define CAN_F1R1_FB23_Msk      (0x1U << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos      (24U)                                           
+#define CAN_F1R1_FB24_Msk      (0x1U << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos      (25U)                                           
+#define CAN_F1R1_FB25_Msk      (0x1U << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos      (26U)                                           
+#define CAN_F1R1_FB26_Msk      (0x1U << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos      (27U)                                           
+#define CAN_F1R1_FB27_Msk      (0x1U << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos      (28U)                                           
+#define CAN_F1R1_FB28_Msk      (0x1U << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos      (29U)                                           
+#define CAN_F1R1_FB29_Msk      (0x1U << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos      (30U)                                           
+#define CAN_F1R1_FB30_Msk      (0x1U << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos      (31U)                                           
+#define CAN_F1R1_FB31_Msk      (0x1U << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define CAN_F2R1_FB0_Pos       (0U)                                            
+#define CAN_F2R1_FB0_Msk       (0x1U << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos       (1U)                                            
+#define CAN_F2R1_FB1_Msk       (0x1U << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos       (2U)                                            
+#define CAN_F2R1_FB2_Msk       (0x1U << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos       (3U)                                            
+#define CAN_F2R1_FB3_Msk       (0x1U << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos       (4U)                                            
+#define CAN_F2R1_FB4_Msk       (0x1U << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos       (5U)                                            
+#define CAN_F2R1_FB5_Msk       (0x1U << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos       (6U)                                            
+#define CAN_F2R1_FB6_Msk       (0x1U << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos       (7U)                                            
+#define CAN_F2R1_FB7_Msk       (0x1U << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos       (8U)                                            
+#define CAN_F2R1_FB8_Msk       (0x1U << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos       (9U)                                            
+#define CAN_F2R1_FB9_Msk       (0x1U << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos      (10U)                                           
+#define CAN_F2R1_FB10_Msk      (0x1U << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos      (11U)                                           
+#define CAN_F2R1_FB11_Msk      (0x1U << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos      (12U)                                           
+#define CAN_F2R1_FB12_Msk      (0x1U << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos      (13U)                                           
+#define CAN_F2R1_FB13_Msk      (0x1U << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos      (14U)                                           
+#define CAN_F2R1_FB14_Msk      (0x1U << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos      (15U)                                           
+#define CAN_F2R1_FB15_Msk      (0x1U << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos      (16U)                                           
+#define CAN_F2R1_FB16_Msk      (0x1U << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos      (17U)                                           
+#define CAN_F2R1_FB17_Msk      (0x1U << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos      (18U)                                           
+#define CAN_F2R1_FB18_Msk      (0x1U << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos      (19U)                                           
+#define CAN_F2R1_FB19_Msk      (0x1U << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos      (20U)                                           
+#define CAN_F2R1_FB20_Msk      (0x1U << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos      (21U)                                           
+#define CAN_F2R1_FB21_Msk      (0x1U << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos      (22U)                                           
+#define CAN_F2R1_FB22_Msk      (0x1U << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos      (23U)                                           
+#define CAN_F2R1_FB23_Msk      (0x1U << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos      (24U)                                           
+#define CAN_F2R1_FB24_Msk      (0x1U << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos      (25U)                                           
+#define CAN_F2R1_FB25_Msk      (0x1U << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos      (26U)                                           
+#define CAN_F2R1_FB26_Msk      (0x1U << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos      (27U)                                           
+#define CAN_F2R1_FB27_Msk      (0x1U << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos      (28U)                                           
+#define CAN_F2R1_FB28_Msk      (0x1U << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos      (29U)                                           
+#define CAN_F2R1_FB29_Msk      (0x1U << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos      (30U)                                           
+#define CAN_F2R1_FB30_Msk      (0x1U << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos      (31U)                                           
+#define CAN_F2R1_FB31_Msk      (0x1U << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define CAN_F3R1_FB0_Pos       (0U)                                            
+#define CAN_F3R1_FB0_Msk       (0x1U << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos       (1U)                                            
+#define CAN_F3R1_FB1_Msk       (0x1U << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos       (2U)                                            
+#define CAN_F3R1_FB2_Msk       (0x1U << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos       (3U)                                            
+#define CAN_F3R1_FB3_Msk       (0x1U << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos       (4U)                                            
+#define CAN_F3R1_FB4_Msk       (0x1U << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos       (5U)                                            
+#define CAN_F3R1_FB5_Msk       (0x1U << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos       (6U)                                            
+#define CAN_F3R1_FB6_Msk       (0x1U << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos       (7U)                                            
+#define CAN_F3R1_FB7_Msk       (0x1U << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos       (8U)                                            
+#define CAN_F3R1_FB8_Msk       (0x1U << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos       (9U)                                            
+#define CAN_F3R1_FB9_Msk       (0x1U << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos      (10U)                                           
+#define CAN_F3R1_FB10_Msk      (0x1U << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos      (11U)                                           
+#define CAN_F3R1_FB11_Msk      (0x1U << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos      (12U)                                           
+#define CAN_F3R1_FB12_Msk      (0x1U << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos      (13U)                                           
+#define CAN_F3R1_FB13_Msk      (0x1U << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos      (14U)                                           
+#define CAN_F3R1_FB14_Msk      (0x1U << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos      (15U)                                           
+#define CAN_F3R1_FB15_Msk      (0x1U << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos      (16U)                                           
+#define CAN_F3R1_FB16_Msk      (0x1U << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos      (17U)                                           
+#define CAN_F3R1_FB17_Msk      (0x1U << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos      (18U)                                           
+#define CAN_F3R1_FB18_Msk      (0x1U << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos      (19U)                                           
+#define CAN_F3R1_FB19_Msk      (0x1U << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos      (20U)                                           
+#define CAN_F3R1_FB20_Msk      (0x1U << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos      (21U)                                           
+#define CAN_F3R1_FB21_Msk      (0x1U << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos      (22U)                                           
+#define CAN_F3R1_FB22_Msk      (0x1U << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos      (23U)                                           
+#define CAN_F3R1_FB23_Msk      (0x1U << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos      (24U)                                           
+#define CAN_F3R1_FB24_Msk      (0x1U << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos      (25U)                                           
+#define CAN_F3R1_FB25_Msk      (0x1U << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos      (26U)                                           
+#define CAN_F3R1_FB26_Msk      (0x1U << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos      (27U)                                           
+#define CAN_F3R1_FB27_Msk      (0x1U << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos      (28U)                                           
+#define CAN_F3R1_FB28_Msk      (0x1U << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos      (29U)                                           
+#define CAN_F3R1_FB29_Msk      (0x1U << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos      (30U)                                           
+#define CAN_F3R1_FB30_Msk      (0x1U << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos      (31U)                                           
+#define CAN_F3R1_FB31_Msk      (0x1U << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define CAN_F4R1_FB0_Pos       (0U)                                            
+#define CAN_F4R1_FB0_Msk       (0x1U << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos       (1U)                                            
+#define CAN_F4R1_FB1_Msk       (0x1U << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos       (2U)                                            
+#define CAN_F4R1_FB2_Msk       (0x1U << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos       (3U)                                            
+#define CAN_F4R1_FB3_Msk       (0x1U << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos       (4U)                                            
+#define CAN_F4R1_FB4_Msk       (0x1U << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos       (5U)                                            
+#define CAN_F4R1_FB5_Msk       (0x1U << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos       (6U)                                            
+#define CAN_F4R1_FB6_Msk       (0x1U << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos       (7U)                                            
+#define CAN_F4R1_FB7_Msk       (0x1U << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos       (8U)                                            
+#define CAN_F4R1_FB8_Msk       (0x1U << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos       (9U)                                            
+#define CAN_F4R1_FB9_Msk       (0x1U << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos      (10U)                                           
+#define CAN_F4R1_FB10_Msk      (0x1U << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos      (11U)                                           
+#define CAN_F4R1_FB11_Msk      (0x1U << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos      (12U)                                           
+#define CAN_F4R1_FB12_Msk      (0x1U << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos      (13U)                                           
+#define CAN_F4R1_FB13_Msk      (0x1U << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos      (14U)                                           
+#define CAN_F4R1_FB14_Msk      (0x1U << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos      (15U)                                           
+#define CAN_F4R1_FB15_Msk      (0x1U << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos      (16U)                                           
+#define CAN_F4R1_FB16_Msk      (0x1U << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos      (17U)                                           
+#define CAN_F4R1_FB17_Msk      (0x1U << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos      (18U)                                           
+#define CAN_F4R1_FB18_Msk      (0x1U << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos      (19U)                                           
+#define CAN_F4R1_FB19_Msk      (0x1U << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos      (20U)                                           
+#define CAN_F4R1_FB20_Msk      (0x1U << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos      (21U)                                           
+#define CAN_F4R1_FB21_Msk      (0x1U << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos      (22U)                                           
+#define CAN_F4R1_FB22_Msk      (0x1U << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos      (23U)                                           
+#define CAN_F4R1_FB23_Msk      (0x1U << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos      (24U)                                           
+#define CAN_F4R1_FB24_Msk      (0x1U << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos      (25U)                                           
+#define CAN_F4R1_FB25_Msk      (0x1U << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos      (26U)                                           
+#define CAN_F4R1_FB26_Msk      (0x1U << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos      (27U)                                           
+#define CAN_F4R1_FB27_Msk      (0x1U << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos      (28U)                                           
+#define CAN_F4R1_FB28_Msk      (0x1U << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos      (29U)                                           
+#define CAN_F4R1_FB29_Msk      (0x1U << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos      (30U)                                           
+#define CAN_F4R1_FB30_Msk      (0x1U << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos      (31U)                                           
+#define CAN_F4R1_FB31_Msk      (0x1U << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define CAN_F5R1_FB0_Pos       (0U)                                            
+#define CAN_F5R1_FB0_Msk       (0x1U << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos       (1U)                                            
+#define CAN_F5R1_FB1_Msk       (0x1U << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos       (2U)                                            
+#define CAN_F5R1_FB2_Msk       (0x1U << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos       (3U)                                            
+#define CAN_F5R1_FB3_Msk       (0x1U << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos       (4U)                                            
+#define CAN_F5R1_FB4_Msk       (0x1U << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos       (5U)                                            
+#define CAN_F5R1_FB5_Msk       (0x1U << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos       (6U)                                            
+#define CAN_F5R1_FB6_Msk       (0x1U << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos       (7U)                                            
+#define CAN_F5R1_FB7_Msk       (0x1U << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos       (8U)                                            
+#define CAN_F5R1_FB8_Msk       (0x1U << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos       (9U)                                            
+#define CAN_F5R1_FB9_Msk       (0x1U << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos      (10U)                                           
+#define CAN_F5R1_FB10_Msk      (0x1U << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos      (11U)                                           
+#define CAN_F5R1_FB11_Msk      (0x1U << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos      (12U)                                           
+#define CAN_F5R1_FB12_Msk      (0x1U << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos      (13U)                                           
+#define CAN_F5R1_FB13_Msk      (0x1U << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos      (14U)                                           
+#define CAN_F5R1_FB14_Msk      (0x1U << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos      (15U)                                           
+#define CAN_F5R1_FB15_Msk      (0x1U << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos      (16U)                                           
+#define CAN_F5R1_FB16_Msk      (0x1U << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos      (17U)                                           
+#define CAN_F5R1_FB17_Msk      (0x1U << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos      (18U)                                           
+#define CAN_F5R1_FB18_Msk      (0x1U << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos      (19U)                                           
+#define CAN_F5R1_FB19_Msk      (0x1U << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos      (20U)                                           
+#define CAN_F5R1_FB20_Msk      (0x1U << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos      (21U)                                           
+#define CAN_F5R1_FB21_Msk      (0x1U << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos      (22U)                                           
+#define CAN_F5R1_FB22_Msk      (0x1U << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos      (23U)                                           
+#define CAN_F5R1_FB23_Msk      (0x1U << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos      (24U)                                           
+#define CAN_F5R1_FB24_Msk      (0x1U << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos      (25U)                                           
+#define CAN_F5R1_FB25_Msk      (0x1U << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos      (26U)                                           
+#define CAN_F5R1_FB26_Msk      (0x1U << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos      (27U)                                           
+#define CAN_F5R1_FB27_Msk      (0x1U << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos      (28U)                                           
+#define CAN_F5R1_FB28_Msk      (0x1U << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos      (29U)                                           
+#define CAN_F5R1_FB29_Msk      (0x1U << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos      (30U)                                           
+#define CAN_F5R1_FB30_Msk      (0x1U << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos      (31U)                                           
+#define CAN_F5R1_FB31_Msk      (0x1U << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define CAN_F6R1_FB0_Pos       (0U)                                            
+#define CAN_F6R1_FB0_Msk       (0x1U << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos       (1U)                                            
+#define CAN_F6R1_FB1_Msk       (0x1U << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos       (2U)                                            
+#define CAN_F6R1_FB2_Msk       (0x1U << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos       (3U)                                            
+#define CAN_F6R1_FB3_Msk       (0x1U << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos       (4U)                                            
+#define CAN_F6R1_FB4_Msk       (0x1U << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos       (5U)                                            
+#define CAN_F6R1_FB5_Msk       (0x1U << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos       (6U)                                            
+#define CAN_F6R1_FB6_Msk       (0x1U << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos       (7U)                                            
+#define CAN_F6R1_FB7_Msk       (0x1U << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos       (8U)                                            
+#define CAN_F6R1_FB8_Msk       (0x1U << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos       (9U)                                            
+#define CAN_F6R1_FB9_Msk       (0x1U << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos      (10U)                                           
+#define CAN_F6R1_FB10_Msk      (0x1U << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos      (11U)                                           
+#define CAN_F6R1_FB11_Msk      (0x1U << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos      (12U)                                           
+#define CAN_F6R1_FB12_Msk      (0x1U << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos      (13U)                                           
+#define CAN_F6R1_FB13_Msk      (0x1U << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos      (14U)                                           
+#define CAN_F6R1_FB14_Msk      (0x1U << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos      (15U)                                           
+#define CAN_F6R1_FB15_Msk      (0x1U << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos      (16U)                                           
+#define CAN_F6R1_FB16_Msk      (0x1U << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos      (17U)                                           
+#define CAN_F6R1_FB17_Msk      (0x1U << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos      (18U)                                           
+#define CAN_F6R1_FB18_Msk      (0x1U << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos      (19U)                                           
+#define CAN_F6R1_FB19_Msk      (0x1U << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos      (20U)                                           
+#define CAN_F6R1_FB20_Msk      (0x1U << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos      (21U)                                           
+#define CAN_F6R1_FB21_Msk      (0x1U << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos      (22U)                                           
+#define CAN_F6R1_FB22_Msk      (0x1U << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos      (23U)                                           
+#define CAN_F6R1_FB23_Msk      (0x1U << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos      (24U)                                           
+#define CAN_F6R1_FB24_Msk      (0x1U << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos      (25U)                                           
+#define CAN_F6R1_FB25_Msk      (0x1U << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos      (26U)                                           
+#define CAN_F6R1_FB26_Msk      (0x1U << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos      (27U)                                           
+#define CAN_F6R1_FB27_Msk      (0x1U << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos      (28U)                                           
+#define CAN_F6R1_FB28_Msk      (0x1U << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos      (29U)                                           
+#define CAN_F6R1_FB29_Msk      (0x1U << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos      (30U)                                           
+#define CAN_F6R1_FB30_Msk      (0x1U << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos      (31U)                                           
+#define CAN_F6R1_FB31_Msk      (0x1U << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define CAN_F7R1_FB0_Pos       (0U)                                            
+#define CAN_F7R1_FB0_Msk       (0x1U << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos       (1U)                                            
+#define CAN_F7R1_FB1_Msk       (0x1U << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos       (2U)                                            
+#define CAN_F7R1_FB2_Msk       (0x1U << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos       (3U)                                            
+#define CAN_F7R1_FB3_Msk       (0x1U << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos       (4U)                                            
+#define CAN_F7R1_FB4_Msk       (0x1U << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos       (5U)                                            
+#define CAN_F7R1_FB5_Msk       (0x1U << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos       (6U)                                            
+#define CAN_F7R1_FB6_Msk       (0x1U << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos       (7U)                                            
+#define CAN_F7R1_FB7_Msk       (0x1U << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos       (8U)                                            
+#define CAN_F7R1_FB8_Msk       (0x1U << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos       (9U)                                            
+#define CAN_F7R1_FB9_Msk       (0x1U << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos      (10U)                                           
+#define CAN_F7R1_FB10_Msk      (0x1U << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos      (11U)                                           
+#define CAN_F7R1_FB11_Msk      (0x1U << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos      (12U)                                           
+#define CAN_F7R1_FB12_Msk      (0x1U << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos      (13U)                                           
+#define CAN_F7R1_FB13_Msk      (0x1U << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos      (14U)                                           
+#define CAN_F7R1_FB14_Msk      (0x1U << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos      (15U)                                           
+#define CAN_F7R1_FB15_Msk      (0x1U << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos      (16U)                                           
+#define CAN_F7R1_FB16_Msk      (0x1U << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos      (17U)                                           
+#define CAN_F7R1_FB17_Msk      (0x1U << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos      (18U)                                           
+#define CAN_F7R1_FB18_Msk      (0x1U << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos      (19U)                                           
+#define CAN_F7R1_FB19_Msk      (0x1U << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos      (20U)                                           
+#define CAN_F7R1_FB20_Msk      (0x1U << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos      (21U)                                           
+#define CAN_F7R1_FB21_Msk      (0x1U << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos      (22U)                                           
+#define CAN_F7R1_FB22_Msk      (0x1U << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos      (23U)                                           
+#define CAN_F7R1_FB23_Msk      (0x1U << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos      (24U)                                           
+#define CAN_F7R1_FB24_Msk      (0x1U << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos      (25U)                                           
+#define CAN_F7R1_FB25_Msk      (0x1U << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos      (26U)                                           
+#define CAN_F7R1_FB26_Msk      (0x1U << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos      (27U)                                           
+#define CAN_F7R1_FB27_Msk      (0x1U << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos      (28U)                                           
+#define CAN_F7R1_FB28_Msk      (0x1U << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos      (29U)                                           
+#define CAN_F7R1_FB29_Msk      (0x1U << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos      (30U)                                           
+#define CAN_F7R1_FB30_Msk      (0x1U << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos      (31U)                                           
+#define CAN_F7R1_FB31_Msk      (0x1U << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define CAN_F8R1_FB0_Pos       (0U)                                            
+#define CAN_F8R1_FB0_Msk       (0x1U << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos       (1U)                                            
+#define CAN_F8R1_FB1_Msk       (0x1U << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos       (2U)                                            
+#define CAN_F8R1_FB2_Msk       (0x1U << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos       (3U)                                            
+#define CAN_F8R1_FB3_Msk       (0x1U << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos       (4U)                                            
+#define CAN_F8R1_FB4_Msk       (0x1U << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos       (5U)                                            
+#define CAN_F8R1_FB5_Msk       (0x1U << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos       (6U)                                            
+#define CAN_F8R1_FB6_Msk       (0x1U << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos       (7U)                                            
+#define CAN_F8R1_FB7_Msk       (0x1U << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos       (8U)                                            
+#define CAN_F8R1_FB8_Msk       (0x1U << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos       (9U)                                            
+#define CAN_F8R1_FB9_Msk       (0x1U << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos      (10U)                                           
+#define CAN_F8R1_FB10_Msk      (0x1U << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos      (11U)                                           
+#define CAN_F8R1_FB11_Msk      (0x1U << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos      (12U)                                           
+#define CAN_F8R1_FB12_Msk      (0x1U << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos      (13U)                                           
+#define CAN_F8R1_FB13_Msk      (0x1U << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos      (14U)                                           
+#define CAN_F8R1_FB14_Msk      (0x1U << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos      (15U)                                           
+#define CAN_F8R1_FB15_Msk      (0x1U << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos      (16U)                                           
+#define CAN_F8R1_FB16_Msk      (0x1U << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos      (17U)                                           
+#define CAN_F8R1_FB17_Msk      (0x1U << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos      (18U)                                           
+#define CAN_F8R1_FB18_Msk      (0x1U << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos      (19U)                                           
+#define CAN_F8R1_FB19_Msk      (0x1U << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos      (20U)                                           
+#define CAN_F8R1_FB20_Msk      (0x1U << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos      (21U)                                           
+#define CAN_F8R1_FB21_Msk      (0x1U << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos      (22U)                                           
+#define CAN_F8R1_FB22_Msk      (0x1U << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos      (23U)                                           
+#define CAN_F8R1_FB23_Msk      (0x1U << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos      (24U)                                           
+#define CAN_F8R1_FB24_Msk      (0x1U << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos      (25U)                                           
+#define CAN_F8R1_FB25_Msk      (0x1U << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos      (26U)                                           
+#define CAN_F8R1_FB26_Msk      (0x1U << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos      (27U)                                           
+#define CAN_F8R1_FB27_Msk      (0x1U << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos      (28U)                                           
+#define CAN_F8R1_FB28_Msk      (0x1U << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos      (29U)                                           
+#define CAN_F8R1_FB29_Msk      (0x1U << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos      (30U)                                           
+#define CAN_F8R1_FB30_Msk      (0x1U << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos      (31U)                                           
+#define CAN_F8R1_FB31_Msk      (0x1U << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define CAN_F9R1_FB0_Pos       (0U)                                            
+#define CAN_F9R1_FB0_Msk       (0x1U << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos       (1U)                                            
+#define CAN_F9R1_FB1_Msk       (0x1U << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos       (2U)                                            
+#define CAN_F9R1_FB2_Msk       (0x1U << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos       (3U)                                            
+#define CAN_F9R1_FB3_Msk       (0x1U << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos       (4U)                                            
+#define CAN_F9R1_FB4_Msk       (0x1U << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos       (5U)                                            
+#define CAN_F9R1_FB5_Msk       (0x1U << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos       (6U)                                            
+#define CAN_F9R1_FB6_Msk       (0x1U << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos       (7U)                                            
+#define CAN_F9R1_FB7_Msk       (0x1U << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos       (8U)                                            
+#define CAN_F9R1_FB8_Msk       (0x1U << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos       (9U)                                            
+#define CAN_F9R1_FB9_Msk       (0x1U << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos      (10U)                                           
+#define CAN_F9R1_FB10_Msk      (0x1U << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos      (11U)                                           
+#define CAN_F9R1_FB11_Msk      (0x1U << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos      (12U)                                           
+#define CAN_F9R1_FB12_Msk      (0x1U << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos      (13U)                                           
+#define CAN_F9R1_FB13_Msk      (0x1U << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos      (14U)                                           
+#define CAN_F9R1_FB14_Msk      (0x1U << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos      (15U)                                           
+#define CAN_F9R1_FB15_Msk      (0x1U << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos      (16U)                                           
+#define CAN_F9R1_FB16_Msk      (0x1U << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos      (17U)                                           
+#define CAN_F9R1_FB17_Msk      (0x1U << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos      (18U)                                           
+#define CAN_F9R1_FB18_Msk      (0x1U << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos      (19U)                                           
+#define CAN_F9R1_FB19_Msk      (0x1U << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos      (20U)                                           
+#define CAN_F9R1_FB20_Msk      (0x1U << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos      (21U)                                           
+#define CAN_F9R1_FB21_Msk      (0x1U << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos      (22U)                                           
+#define CAN_F9R1_FB22_Msk      (0x1U << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos      (23U)                                           
+#define CAN_F9R1_FB23_Msk      (0x1U << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos      (24U)                                           
+#define CAN_F9R1_FB24_Msk      (0x1U << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos      (25U)                                           
+#define CAN_F9R1_FB25_Msk      (0x1U << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos      (26U)                                           
+#define CAN_F9R1_FB26_Msk      (0x1U << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos      (27U)                                           
+#define CAN_F9R1_FB27_Msk      (0x1U << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos      (28U)                                           
+#define CAN_F9R1_FB28_Msk      (0x1U << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos      (29U)                                           
+#define CAN_F9R1_FB29_Msk      (0x1U << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos      (30U)                                           
+#define CAN_F9R1_FB30_Msk      (0x1U << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos      (31U)                                           
+#define CAN_F9R1_FB31_Msk      (0x1U << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define CAN_F10R1_FB0_Pos      (0U)                                            
+#define CAN_F10R1_FB0_Msk      (0x1U << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos      (1U)                                            
+#define CAN_F10R1_FB1_Msk      (0x1U << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos      (2U)                                            
+#define CAN_F10R1_FB2_Msk      (0x1U << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos      (3U)                                            
+#define CAN_F10R1_FB3_Msk      (0x1U << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos      (4U)                                            
+#define CAN_F10R1_FB4_Msk      (0x1U << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos      (5U)                                            
+#define CAN_F10R1_FB5_Msk      (0x1U << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos      (6U)                                            
+#define CAN_F10R1_FB6_Msk      (0x1U << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos      (7U)                                            
+#define CAN_F10R1_FB7_Msk      (0x1U << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos      (8U)                                            
+#define CAN_F10R1_FB8_Msk      (0x1U << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos      (9U)                                            
+#define CAN_F10R1_FB9_Msk      (0x1U << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos     (10U)                                           
+#define CAN_F10R1_FB10_Msk     (0x1U << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos     (11U)                                           
+#define CAN_F10R1_FB11_Msk     (0x1U << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos     (12U)                                           
+#define CAN_F10R1_FB12_Msk     (0x1U << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos     (13U)                                           
+#define CAN_F10R1_FB13_Msk     (0x1U << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos     (14U)                                           
+#define CAN_F10R1_FB14_Msk     (0x1U << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos     (15U)                                           
+#define CAN_F10R1_FB15_Msk     (0x1U << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos     (16U)                                           
+#define CAN_F10R1_FB16_Msk     (0x1U << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos     (17U)                                           
+#define CAN_F10R1_FB17_Msk     (0x1U << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos     (18U)                                           
+#define CAN_F10R1_FB18_Msk     (0x1U << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos     (19U)                                           
+#define CAN_F10R1_FB19_Msk     (0x1U << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos     (20U)                                           
+#define CAN_F10R1_FB20_Msk     (0x1U << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos     (21U)                                           
+#define CAN_F10R1_FB21_Msk     (0x1U << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos     (22U)                                           
+#define CAN_F10R1_FB22_Msk     (0x1U << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos     (23U)                                           
+#define CAN_F10R1_FB23_Msk     (0x1U << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos     (24U)                                           
+#define CAN_F10R1_FB24_Msk     (0x1U << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos     (25U)                                           
+#define CAN_F10R1_FB25_Msk     (0x1U << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos     (26U)                                           
+#define CAN_F10R1_FB26_Msk     (0x1U << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos     (27U)                                           
+#define CAN_F10R1_FB27_Msk     (0x1U << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos     (28U)                                           
+#define CAN_F10R1_FB28_Msk     (0x1U << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos     (29U)                                           
+#define CAN_F10R1_FB29_Msk     (0x1U << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos     (30U)                                           
+#define CAN_F10R1_FB30_Msk     (0x1U << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos     (31U)                                           
+#define CAN_F10R1_FB31_Msk     (0x1U << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define CAN_F11R1_FB0_Pos      (0U)                                            
+#define CAN_F11R1_FB0_Msk      (0x1U << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos      (1U)                                            
+#define CAN_F11R1_FB1_Msk      (0x1U << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos      (2U)                                            
+#define CAN_F11R1_FB2_Msk      (0x1U << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos      (3U)                                            
+#define CAN_F11R1_FB3_Msk      (0x1U << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos      (4U)                                            
+#define CAN_F11R1_FB4_Msk      (0x1U << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos      (5U)                                            
+#define CAN_F11R1_FB5_Msk      (0x1U << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos      (6U)                                            
+#define CAN_F11R1_FB6_Msk      (0x1U << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos      (7U)                                            
+#define CAN_F11R1_FB7_Msk      (0x1U << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos      (8U)                                            
+#define CAN_F11R1_FB8_Msk      (0x1U << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos      (9U)                                            
+#define CAN_F11R1_FB9_Msk      (0x1U << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos     (10U)                                           
+#define CAN_F11R1_FB10_Msk     (0x1U << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos     (11U)                                           
+#define CAN_F11R1_FB11_Msk     (0x1U << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos     (12U)                                           
+#define CAN_F11R1_FB12_Msk     (0x1U << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos     (13U)                                           
+#define CAN_F11R1_FB13_Msk     (0x1U << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos     (14U)                                           
+#define CAN_F11R1_FB14_Msk     (0x1U << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos     (15U)                                           
+#define CAN_F11R1_FB15_Msk     (0x1U << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos     (16U)                                           
+#define CAN_F11R1_FB16_Msk     (0x1U << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos     (17U)                                           
+#define CAN_F11R1_FB17_Msk     (0x1U << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos     (18U)                                           
+#define CAN_F11R1_FB18_Msk     (0x1U << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos     (19U)                                           
+#define CAN_F11R1_FB19_Msk     (0x1U << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos     (20U)                                           
+#define CAN_F11R1_FB20_Msk     (0x1U << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos     (21U)                                           
+#define CAN_F11R1_FB21_Msk     (0x1U << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos     (22U)                                           
+#define CAN_F11R1_FB22_Msk     (0x1U << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos     (23U)                                           
+#define CAN_F11R1_FB23_Msk     (0x1U << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos     (24U)                                           
+#define CAN_F11R1_FB24_Msk     (0x1U << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos     (25U)                                           
+#define CAN_F11R1_FB25_Msk     (0x1U << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos     (26U)                                           
+#define CAN_F11R1_FB26_Msk     (0x1U << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos     (27U)                                           
+#define CAN_F11R1_FB27_Msk     (0x1U << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos     (28U)                                           
+#define CAN_F11R1_FB28_Msk     (0x1U << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos     (29U)                                           
+#define CAN_F11R1_FB29_Msk     (0x1U << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos     (30U)                                           
+#define CAN_F11R1_FB30_Msk     (0x1U << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos     (31U)                                           
+#define CAN_F11R1_FB31_Msk     (0x1U << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define CAN_F12R1_FB0_Pos      (0U)                                            
+#define CAN_F12R1_FB0_Msk      (0x1U << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos      (1U)                                            
+#define CAN_F12R1_FB1_Msk      (0x1U << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos      (2U)                                            
+#define CAN_F12R1_FB2_Msk      (0x1U << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos      (3U)                                            
+#define CAN_F12R1_FB3_Msk      (0x1U << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos      (4U)                                            
+#define CAN_F12R1_FB4_Msk      (0x1U << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos      (5U)                                            
+#define CAN_F12R1_FB5_Msk      (0x1U << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos      (6U)                                            
+#define CAN_F12R1_FB6_Msk      (0x1U << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos      (7U)                                            
+#define CAN_F12R1_FB7_Msk      (0x1U << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos      (8U)                                            
+#define CAN_F12R1_FB8_Msk      (0x1U << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos      (9U)                                            
+#define CAN_F12R1_FB9_Msk      (0x1U << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos     (10U)                                           
+#define CAN_F12R1_FB10_Msk     (0x1U << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos     (11U)                                           
+#define CAN_F12R1_FB11_Msk     (0x1U << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos     (12U)                                           
+#define CAN_F12R1_FB12_Msk     (0x1U << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos     (13U)                                           
+#define CAN_F12R1_FB13_Msk     (0x1U << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos     (14U)                                           
+#define CAN_F12R1_FB14_Msk     (0x1U << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos     (15U)                                           
+#define CAN_F12R1_FB15_Msk     (0x1U << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos     (16U)                                           
+#define CAN_F12R1_FB16_Msk     (0x1U << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos     (17U)                                           
+#define CAN_F12R1_FB17_Msk     (0x1U << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos     (18U)                                           
+#define CAN_F12R1_FB18_Msk     (0x1U << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos     (19U)                                           
+#define CAN_F12R1_FB19_Msk     (0x1U << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos     (20U)                                           
+#define CAN_F12R1_FB20_Msk     (0x1U << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos     (21U)                                           
+#define CAN_F12R1_FB21_Msk     (0x1U << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos     (22U)                                           
+#define CAN_F12R1_FB22_Msk     (0x1U << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos     (23U)                                           
+#define CAN_F12R1_FB23_Msk     (0x1U << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos     (24U)                                           
+#define CAN_F12R1_FB24_Msk     (0x1U << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos     (25U)                                           
+#define CAN_F12R1_FB25_Msk     (0x1U << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos     (26U)                                           
+#define CAN_F12R1_FB26_Msk     (0x1U << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos     (27U)                                           
+#define CAN_F12R1_FB27_Msk     (0x1U << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos     (28U)                                           
+#define CAN_F12R1_FB28_Msk     (0x1U << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos     (29U)                                           
+#define CAN_F12R1_FB29_Msk     (0x1U << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos     (30U)                                           
+#define CAN_F12R1_FB30_Msk     (0x1U << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos     (31U)                                           
+#define CAN_F12R1_FB31_Msk     (0x1U << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define CAN_F13R1_FB0_Pos      (0U)                                            
+#define CAN_F13R1_FB0_Msk      (0x1U << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos      (1U)                                            
+#define CAN_F13R1_FB1_Msk      (0x1U << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos      (2U)                                            
+#define CAN_F13R1_FB2_Msk      (0x1U << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos      (3U)                                            
+#define CAN_F13R1_FB3_Msk      (0x1U << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos      (4U)                                            
+#define CAN_F13R1_FB4_Msk      (0x1U << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos      (5U)                                            
+#define CAN_F13R1_FB5_Msk      (0x1U << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos      (6U)                                            
+#define CAN_F13R1_FB6_Msk      (0x1U << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos      (7U)                                            
+#define CAN_F13R1_FB7_Msk      (0x1U << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos      (8U)                                            
+#define CAN_F13R1_FB8_Msk      (0x1U << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos      (9U)                                            
+#define CAN_F13R1_FB9_Msk      (0x1U << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos     (10U)                                           
+#define CAN_F13R1_FB10_Msk     (0x1U << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos     (11U)                                           
+#define CAN_F13R1_FB11_Msk     (0x1U << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos     (12U)                                           
+#define CAN_F13R1_FB12_Msk     (0x1U << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos     (13U)                                           
+#define CAN_F13R1_FB13_Msk     (0x1U << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos     (14U)                                           
+#define CAN_F13R1_FB14_Msk     (0x1U << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos     (15U)                                           
+#define CAN_F13R1_FB15_Msk     (0x1U << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos     (16U)                                           
+#define CAN_F13R1_FB16_Msk     (0x1U << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos     (17U)                                           
+#define CAN_F13R1_FB17_Msk     (0x1U << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos     (18U)                                           
+#define CAN_F13R1_FB18_Msk     (0x1U << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos     (19U)                                           
+#define CAN_F13R1_FB19_Msk     (0x1U << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos     (20U)                                           
+#define CAN_F13R1_FB20_Msk     (0x1U << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos     (21U)                                           
+#define CAN_F13R1_FB21_Msk     (0x1U << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos     (22U)                                           
+#define CAN_F13R1_FB22_Msk     (0x1U << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos     (23U)                                           
+#define CAN_F13R1_FB23_Msk     (0x1U << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos     (24U)                                           
+#define CAN_F13R1_FB24_Msk     (0x1U << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos     (25U)                                           
+#define CAN_F13R1_FB25_Msk     (0x1U << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos     (26U)                                           
+#define CAN_F13R1_FB26_Msk     (0x1U << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos     (27U)                                           
+#define CAN_F13R1_FB27_Msk     (0x1U << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos     (28U)                                           
+#define CAN_F13R1_FB28_Msk     (0x1U << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos     (29U)                                           
+#define CAN_F13R1_FB29_Msk     (0x1U << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos     (30U)                                           
+#define CAN_F13R1_FB30_Msk     (0x1U << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos     (31U)                                           
+#define CAN_F13R1_FB31_Msk     (0x1U << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define CAN_F0R2_FB0_Pos       (0U)                                            
+#define CAN_F0R2_FB0_Msk       (0x1U << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos       (1U)                                            
+#define CAN_F0R2_FB1_Msk       (0x1U << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos       (2U)                                            
+#define CAN_F0R2_FB2_Msk       (0x1U << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos       (3U)                                            
+#define CAN_F0R2_FB3_Msk       (0x1U << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos       (4U)                                            
+#define CAN_F0R2_FB4_Msk       (0x1U << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos       (5U)                                            
+#define CAN_F0R2_FB5_Msk       (0x1U << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos       (6U)                                            
+#define CAN_F0R2_FB6_Msk       (0x1U << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos       (7U)                                            
+#define CAN_F0R2_FB7_Msk       (0x1U << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos       (8U)                                            
+#define CAN_F0R2_FB8_Msk       (0x1U << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos       (9U)                                            
+#define CAN_F0R2_FB9_Msk       (0x1U << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos      (10U)                                           
+#define CAN_F0R2_FB10_Msk      (0x1U << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos      (11U)                                           
+#define CAN_F0R2_FB11_Msk      (0x1U << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos      (12U)                                           
+#define CAN_F0R2_FB12_Msk      (0x1U << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos      (13U)                                           
+#define CAN_F0R2_FB13_Msk      (0x1U << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos      (14U)                                           
+#define CAN_F0R2_FB14_Msk      (0x1U << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos      (15U)                                           
+#define CAN_F0R2_FB15_Msk      (0x1U << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos      (16U)                                           
+#define CAN_F0R2_FB16_Msk      (0x1U << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos      (17U)                                           
+#define CAN_F0R2_FB17_Msk      (0x1U << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos      (18U)                                           
+#define CAN_F0R2_FB18_Msk      (0x1U << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos      (19U)                                           
+#define CAN_F0R2_FB19_Msk      (0x1U << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos      (20U)                                           
+#define CAN_F0R2_FB20_Msk      (0x1U << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos      (21U)                                           
+#define CAN_F0R2_FB21_Msk      (0x1U << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos      (22U)                                           
+#define CAN_F0R2_FB22_Msk      (0x1U << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos      (23U)                                           
+#define CAN_F0R2_FB23_Msk      (0x1U << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos      (24U)                                           
+#define CAN_F0R2_FB24_Msk      (0x1U << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos      (25U)                                           
+#define CAN_F0R2_FB25_Msk      (0x1U << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos      (26U)                                           
+#define CAN_F0R2_FB26_Msk      (0x1U << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos      (27U)                                           
+#define CAN_F0R2_FB27_Msk      (0x1U << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos      (28U)                                           
+#define CAN_F0R2_FB28_Msk      (0x1U << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos      (29U)                                           
+#define CAN_F0R2_FB29_Msk      (0x1U << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos      (30U)                                           
+#define CAN_F0R2_FB30_Msk      (0x1U << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos      (31U)                                           
+#define CAN_F0R2_FB31_Msk      (0x1U << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define CAN_F1R2_FB0_Pos       (0U)                                            
+#define CAN_F1R2_FB0_Msk       (0x1U << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos       (1U)                                            
+#define CAN_F1R2_FB1_Msk       (0x1U << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos       (2U)                                            
+#define CAN_F1R2_FB2_Msk       (0x1U << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos       (3U)                                            
+#define CAN_F1R2_FB3_Msk       (0x1U << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos       (4U)                                            
+#define CAN_F1R2_FB4_Msk       (0x1U << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos       (5U)                                            
+#define CAN_F1R2_FB5_Msk       (0x1U << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos       (6U)                                            
+#define CAN_F1R2_FB6_Msk       (0x1U << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos       (7U)                                            
+#define CAN_F1R2_FB7_Msk       (0x1U << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos       (8U)                                            
+#define CAN_F1R2_FB8_Msk       (0x1U << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos       (9U)                                            
+#define CAN_F1R2_FB9_Msk       (0x1U << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos      (10U)                                           
+#define CAN_F1R2_FB10_Msk      (0x1U << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos      (11U)                                           
+#define CAN_F1R2_FB11_Msk      (0x1U << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos      (12U)                                           
+#define CAN_F1R2_FB12_Msk      (0x1U << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos      (13U)                                           
+#define CAN_F1R2_FB13_Msk      (0x1U << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos      (14U)                                           
+#define CAN_F1R2_FB14_Msk      (0x1U << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos      (15U)                                           
+#define CAN_F1R2_FB15_Msk      (0x1U << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos      (16U)                                           
+#define CAN_F1R2_FB16_Msk      (0x1U << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos      (17U)                                           
+#define CAN_F1R2_FB17_Msk      (0x1U << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos      (18U)                                           
+#define CAN_F1R2_FB18_Msk      (0x1U << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos      (19U)                                           
+#define CAN_F1R2_FB19_Msk      (0x1U << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos      (20U)                                           
+#define CAN_F1R2_FB20_Msk      (0x1U << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos      (21U)                                           
+#define CAN_F1R2_FB21_Msk      (0x1U << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos      (22U)                                           
+#define CAN_F1R2_FB22_Msk      (0x1U << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos      (23U)                                           
+#define CAN_F1R2_FB23_Msk      (0x1U << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos      (24U)                                           
+#define CAN_F1R2_FB24_Msk      (0x1U << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos      (25U)                                           
+#define CAN_F1R2_FB25_Msk      (0x1U << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos      (26U)                                           
+#define CAN_F1R2_FB26_Msk      (0x1U << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos      (27U)                                           
+#define CAN_F1R2_FB27_Msk      (0x1U << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos      (28U)                                           
+#define CAN_F1R2_FB28_Msk      (0x1U << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos      (29U)                                           
+#define CAN_F1R2_FB29_Msk      (0x1U << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos      (30U)                                           
+#define CAN_F1R2_FB30_Msk      (0x1U << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos      (31U)                                           
+#define CAN_F1R2_FB31_Msk      (0x1U << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define CAN_F2R2_FB0_Pos       (0U)                                            
+#define CAN_F2R2_FB0_Msk       (0x1U << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos       (1U)                                            
+#define CAN_F2R2_FB1_Msk       (0x1U << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos       (2U)                                            
+#define CAN_F2R2_FB2_Msk       (0x1U << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos       (3U)                                            
+#define CAN_F2R2_FB3_Msk       (0x1U << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos       (4U)                                            
+#define CAN_F2R2_FB4_Msk       (0x1U << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos       (5U)                                            
+#define CAN_F2R2_FB5_Msk       (0x1U << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos       (6U)                                            
+#define CAN_F2R2_FB6_Msk       (0x1U << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos       (7U)                                            
+#define CAN_F2R2_FB7_Msk       (0x1U << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos       (8U)                                            
+#define CAN_F2R2_FB8_Msk       (0x1U << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos       (9U)                                            
+#define CAN_F2R2_FB9_Msk       (0x1U << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos      (10U)                                           
+#define CAN_F2R2_FB10_Msk      (0x1U << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos      (11U)                                           
+#define CAN_F2R2_FB11_Msk      (0x1U << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos      (12U)                                           
+#define CAN_F2R2_FB12_Msk      (0x1U << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos      (13U)                                           
+#define CAN_F2R2_FB13_Msk      (0x1U << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos      (14U)                                           
+#define CAN_F2R2_FB14_Msk      (0x1U << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos      (15U)                                           
+#define CAN_F2R2_FB15_Msk      (0x1U << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos      (16U)                                           
+#define CAN_F2R2_FB16_Msk      (0x1U << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos      (17U)                                           
+#define CAN_F2R2_FB17_Msk      (0x1U << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos      (18U)                                           
+#define CAN_F2R2_FB18_Msk      (0x1U << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos      (19U)                                           
+#define CAN_F2R2_FB19_Msk      (0x1U << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos      (20U)                                           
+#define CAN_F2R2_FB20_Msk      (0x1U << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos      (21U)                                           
+#define CAN_F2R2_FB21_Msk      (0x1U << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos      (22U)                                           
+#define CAN_F2R2_FB22_Msk      (0x1U << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos      (23U)                                           
+#define CAN_F2R2_FB23_Msk      (0x1U << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos      (24U)                                           
+#define CAN_F2R2_FB24_Msk      (0x1U << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos      (25U)                                           
+#define CAN_F2R2_FB25_Msk      (0x1U << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos      (26U)                                           
+#define CAN_F2R2_FB26_Msk      (0x1U << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos      (27U)                                           
+#define CAN_F2R2_FB27_Msk      (0x1U << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos      (28U)                                           
+#define CAN_F2R2_FB28_Msk      (0x1U << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos      (29U)                                           
+#define CAN_F2R2_FB29_Msk      (0x1U << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos      (30U)                                           
+#define CAN_F2R2_FB30_Msk      (0x1U << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos      (31U)                                           
+#define CAN_F2R2_FB31_Msk      (0x1U << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define CAN_F3R2_FB0_Pos       (0U)                                            
+#define CAN_F3R2_FB0_Msk       (0x1U << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos       (1U)                                            
+#define CAN_F3R2_FB1_Msk       (0x1U << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos       (2U)                                            
+#define CAN_F3R2_FB2_Msk       (0x1U << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos       (3U)                                            
+#define CAN_F3R2_FB3_Msk       (0x1U << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos       (4U)                                            
+#define CAN_F3R2_FB4_Msk       (0x1U << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos       (5U)                                            
+#define CAN_F3R2_FB5_Msk       (0x1U << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos       (6U)                                            
+#define CAN_F3R2_FB6_Msk       (0x1U << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos       (7U)                                            
+#define CAN_F3R2_FB7_Msk       (0x1U << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos       (8U)                                            
+#define CAN_F3R2_FB8_Msk       (0x1U << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos       (9U)                                            
+#define CAN_F3R2_FB9_Msk       (0x1U << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos      (10U)                                           
+#define CAN_F3R2_FB10_Msk      (0x1U << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos      (11U)                                           
+#define CAN_F3R2_FB11_Msk      (0x1U << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos      (12U)                                           
+#define CAN_F3R2_FB12_Msk      (0x1U << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos      (13U)                                           
+#define CAN_F3R2_FB13_Msk      (0x1U << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos      (14U)                                           
+#define CAN_F3R2_FB14_Msk      (0x1U << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos      (15U)                                           
+#define CAN_F3R2_FB15_Msk      (0x1U << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos      (16U)                                           
+#define CAN_F3R2_FB16_Msk      (0x1U << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos      (17U)                                           
+#define CAN_F3R2_FB17_Msk      (0x1U << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos      (18U)                                           
+#define CAN_F3R2_FB18_Msk      (0x1U << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos      (19U)                                           
+#define CAN_F3R2_FB19_Msk      (0x1U << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos      (20U)                                           
+#define CAN_F3R2_FB20_Msk      (0x1U << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos      (21U)                                           
+#define CAN_F3R2_FB21_Msk      (0x1U << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos      (22U)                                           
+#define CAN_F3R2_FB22_Msk      (0x1U << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos      (23U)                                           
+#define CAN_F3R2_FB23_Msk      (0x1U << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos      (24U)                                           
+#define CAN_F3R2_FB24_Msk      (0x1U << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos      (25U)                                           
+#define CAN_F3R2_FB25_Msk      (0x1U << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos      (26U)                                           
+#define CAN_F3R2_FB26_Msk      (0x1U << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos      (27U)                                           
+#define CAN_F3R2_FB27_Msk      (0x1U << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos      (28U)                                           
+#define CAN_F3R2_FB28_Msk      (0x1U << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos      (29U)                                           
+#define CAN_F3R2_FB29_Msk      (0x1U << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos      (30U)                                           
+#define CAN_F3R2_FB30_Msk      (0x1U << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos      (31U)                                           
+#define CAN_F3R2_FB31_Msk      (0x1U << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define CAN_F4R2_FB0_Pos       (0U)                                            
+#define CAN_F4R2_FB0_Msk       (0x1U << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos       (1U)                                            
+#define CAN_F4R2_FB1_Msk       (0x1U << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos       (2U)                                            
+#define CAN_F4R2_FB2_Msk       (0x1U << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos       (3U)                                            
+#define CAN_F4R2_FB3_Msk       (0x1U << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos       (4U)                                            
+#define CAN_F4R2_FB4_Msk       (0x1U << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos       (5U)                                            
+#define CAN_F4R2_FB5_Msk       (0x1U << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos       (6U)                                            
+#define CAN_F4R2_FB6_Msk       (0x1U << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos       (7U)                                            
+#define CAN_F4R2_FB7_Msk       (0x1U << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos       (8U)                                            
+#define CAN_F4R2_FB8_Msk       (0x1U << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos       (9U)                                            
+#define CAN_F4R2_FB9_Msk       (0x1U << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos      (10U)                                           
+#define CAN_F4R2_FB10_Msk      (0x1U << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos      (11U)                                           
+#define CAN_F4R2_FB11_Msk      (0x1U << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos      (12U)                                           
+#define CAN_F4R2_FB12_Msk      (0x1U << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos      (13U)                                           
+#define CAN_F4R2_FB13_Msk      (0x1U << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos      (14U)                                           
+#define CAN_F4R2_FB14_Msk      (0x1U << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos      (15U)                                           
+#define CAN_F4R2_FB15_Msk      (0x1U << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos      (16U)                                           
+#define CAN_F4R2_FB16_Msk      (0x1U << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos      (17U)                                           
+#define CAN_F4R2_FB17_Msk      (0x1U << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos      (18U)                                           
+#define CAN_F4R2_FB18_Msk      (0x1U << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos      (19U)                                           
+#define CAN_F4R2_FB19_Msk      (0x1U << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos      (20U)                                           
+#define CAN_F4R2_FB20_Msk      (0x1U << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos      (21U)                                           
+#define CAN_F4R2_FB21_Msk      (0x1U << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos      (22U)                                           
+#define CAN_F4R2_FB22_Msk      (0x1U << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos      (23U)                                           
+#define CAN_F4R2_FB23_Msk      (0x1U << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos      (24U)                                           
+#define CAN_F4R2_FB24_Msk      (0x1U << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos      (25U)                                           
+#define CAN_F4R2_FB25_Msk      (0x1U << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos      (26U)                                           
+#define CAN_F4R2_FB26_Msk      (0x1U << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos      (27U)                                           
+#define CAN_F4R2_FB27_Msk      (0x1U << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos      (28U)                                           
+#define CAN_F4R2_FB28_Msk      (0x1U << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos      (29U)                                           
+#define CAN_F4R2_FB29_Msk      (0x1U << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos      (30U)                                           
+#define CAN_F4R2_FB30_Msk      (0x1U << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos      (31U)                                           
+#define CAN_F4R2_FB31_Msk      (0x1U << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define CAN_F5R2_FB0_Pos       (0U)                                            
+#define CAN_F5R2_FB0_Msk       (0x1U << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos       (1U)                                            
+#define CAN_F5R2_FB1_Msk       (0x1U << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos       (2U)                                            
+#define CAN_F5R2_FB2_Msk       (0x1U << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos       (3U)                                            
+#define CAN_F5R2_FB3_Msk       (0x1U << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos       (4U)                                            
+#define CAN_F5R2_FB4_Msk       (0x1U << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos       (5U)                                            
+#define CAN_F5R2_FB5_Msk       (0x1U << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos       (6U)                                            
+#define CAN_F5R2_FB6_Msk       (0x1U << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos       (7U)                                            
+#define CAN_F5R2_FB7_Msk       (0x1U << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos       (8U)                                            
+#define CAN_F5R2_FB8_Msk       (0x1U << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos       (9U)                                            
+#define CAN_F5R2_FB9_Msk       (0x1U << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos      (10U)                                           
+#define CAN_F5R2_FB10_Msk      (0x1U << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos      (11U)                                           
+#define CAN_F5R2_FB11_Msk      (0x1U << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos      (12U)                                           
+#define CAN_F5R2_FB12_Msk      (0x1U << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos      (13U)                                           
+#define CAN_F5R2_FB13_Msk      (0x1U << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos      (14U)                                           
+#define CAN_F5R2_FB14_Msk      (0x1U << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos      (15U)                                           
+#define CAN_F5R2_FB15_Msk      (0x1U << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos      (16U)                                           
+#define CAN_F5R2_FB16_Msk      (0x1U << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos      (17U)                                           
+#define CAN_F5R2_FB17_Msk      (0x1U << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos      (18U)                                           
+#define CAN_F5R2_FB18_Msk      (0x1U << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos      (19U)                                           
+#define CAN_F5R2_FB19_Msk      (0x1U << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos      (20U)                                           
+#define CAN_F5R2_FB20_Msk      (0x1U << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos      (21U)                                           
+#define CAN_F5R2_FB21_Msk      (0x1U << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos      (22U)                                           
+#define CAN_F5R2_FB22_Msk      (0x1U << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos      (23U)                                           
+#define CAN_F5R2_FB23_Msk      (0x1U << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos      (24U)                                           
+#define CAN_F5R2_FB24_Msk      (0x1U << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos      (25U)                                           
+#define CAN_F5R2_FB25_Msk      (0x1U << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos      (26U)                                           
+#define CAN_F5R2_FB26_Msk      (0x1U << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos      (27U)                                           
+#define CAN_F5R2_FB27_Msk      (0x1U << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos      (28U)                                           
+#define CAN_F5R2_FB28_Msk      (0x1U << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos      (29U)                                           
+#define CAN_F5R2_FB29_Msk      (0x1U << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos      (30U)                                           
+#define CAN_F5R2_FB30_Msk      (0x1U << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos      (31U)                                           
+#define CAN_F5R2_FB31_Msk      (0x1U << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define CAN_F6R2_FB0_Pos       (0U)                                            
+#define CAN_F6R2_FB0_Msk       (0x1U << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos       (1U)                                            
+#define CAN_F6R2_FB1_Msk       (0x1U << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos       (2U)                                            
+#define CAN_F6R2_FB2_Msk       (0x1U << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos       (3U)                                            
+#define CAN_F6R2_FB3_Msk       (0x1U << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos       (4U)                                            
+#define CAN_F6R2_FB4_Msk       (0x1U << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos       (5U)                                            
+#define CAN_F6R2_FB5_Msk       (0x1U << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos       (6U)                                            
+#define CAN_F6R2_FB6_Msk       (0x1U << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos       (7U)                                            
+#define CAN_F6R2_FB7_Msk       (0x1U << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos       (8U)                                            
+#define CAN_F6R2_FB8_Msk       (0x1U << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos       (9U)                                            
+#define CAN_F6R2_FB9_Msk       (0x1U << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos      (10U)                                           
+#define CAN_F6R2_FB10_Msk      (0x1U << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos      (11U)                                           
+#define CAN_F6R2_FB11_Msk      (0x1U << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos      (12U)                                           
+#define CAN_F6R2_FB12_Msk      (0x1U << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos      (13U)                                           
+#define CAN_F6R2_FB13_Msk      (0x1U << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos      (14U)                                           
+#define CAN_F6R2_FB14_Msk      (0x1U << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos      (15U)                                           
+#define CAN_F6R2_FB15_Msk      (0x1U << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos      (16U)                                           
+#define CAN_F6R2_FB16_Msk      (0x1U << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos      (17U)                                           
+#define CAN_F6R2_FB17_Msk      (0x1U << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos      (18U)                                           
+#define CAN_F6R2_FB18_Msk      (0x1U << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos      (19U)                                           
+#define CAN_F6R2_FB19_Msk      (0x1U << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos      (20U)                                           
+#define CAN_F6R2_FB20_Msk      (0x1U << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos      (21U)                                           
+#define CAN_F6R2_FB21_Msk      (0x1U << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos      (22U)                                           
+#define CAN_F6R2_FB22_Msk      (0x1U << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos      (23U)                                           
+#define CAN_F6R2_FB23_Msk      (0x1U << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos      (24U)                                           
+#define CAN_F6R2_FB24_Msk      (0x1U << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos      (25U)                                           
+#define CAN_F6R2_FB25_Msk      (0x1U << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos      (26U)                                           
+#define CAN_F6R2_FB26_Msk      (0x1U << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos      (27U)                                           
+#define CAN_F6R2_FB27_Msk      (0x1U << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos      (28U)                                           
+#define CAN_F6R2_FB28_Msk      (0x1U << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos      (29U)                                           
+#define CAN_F6R2_FB29_Msk      (0x1U << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos      (30U)                                           
+#define CAN_F6R2_FB30_Msk      (0x1U << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos      (31U)                                           
+#define CAN_F6R2_FB31_Msk      (0x1U << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define CAN_F7R2_FB0_Pos       (0U)                                            
+#define CAN_F7R2_FB0_Msk       (0x1U << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos       (1U)                                            
+#define CAN_F7R2_FB1_Msk       (0x1U << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos       (2U)                                            
+#define CAN_F7R2_FB2_Msk       (0x1U << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos       (3U)                                            
+#define CAN_F7R2_FB3_Msk       (0x1U << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos       (4U)                                            
+#define CAN_F7R2_FB4_Msk       (0x1U << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos       (5U)                                            
+#define CAN_F7R2_FB5_Msk       (0x1U << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos       (6U)                                            
+#define CAN_F7R2_FB6_Msk       (0x1U << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos       (7U)                                            
+#define CAN_F7R2_FB7_Msk       (0x1U << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos       (8U)                                            
+#define CAN_F7R2_FB8_Msk       (0x1U << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos       (9U)                                            
+#define CAN_F7R2_FB9_Msk       (0x1U << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos      (10U)                                           
+#define CAN_F7R2_FB10_Msk      (0x1U << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos      (11U)                                           
+#define CAN_F7R2_FB11_Msk      (0x1U << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos      (12U)                                           
+#define CAN_F7R2_FB12_Msk      (0x1U << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos      (13U)                                           
+#define CAN_F7R2_FB13_Msk      (0x1U << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos      (14U)                                           
+#define CAN_F7R2_FB14_Msk      (0x1U << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos      (15U)                                           
+#define CAN_F7R2_FB15_Msk      (0x1U << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos      (16U)                                           
+#define CAN_F7R2_FB16_Msk      (0x1U << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos      (17U)                                           
+#define CAN_F7R2_FB17_Msk      (0x1U << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos      (18U)                                           
+#define CAN_F7R2_FB18_Msk      (0x1U << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos      (19U)                                           
+#define CAN_F7R2_FB19_Msk      (0x1U << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos      (20U)                                           
+#define CAN_F7R2_FB20_Msk      (0x1U << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos      (21U)                                           
+#define CAN_F7R2_FB21_Msk      (0x1U << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos      (22U)                                           
+#define CAN_F7R2_FB22_Msk      (0x1U << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos      (23U)                                           
+#define CAN_F7R2_FB23_Msk      (0x1U << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos      (24U)                                           
+#define CAN_F7R2_FB24_Msk      (0x1U << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos      (25U)                                           
+#define CAN_F7R2_FB25_Msk      (0x1U << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos      (26U)                                           
+#define CAN_F7R2_FB26_Msk      (0x1U << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos      (27U)                                           
+#define CAN_F7R2_FB27_Msk      (0x1U << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos      (28U)                                           
+#define CAN_F7R2_FB28_Msk      (0x1U << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos      (29U)                                           
+#define CAN_F7R2_FB29_Msk      (0x1U << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos      (30U)                                           
+#define CAN_F7R2_FB30_Msk      (0x1U << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos      (31U)                                           
+#define CAN_F7R2_FB31_Msk      (0x1U << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define CAN_F8R2_FB0_Pos       (0U)                                            
+#define CAN_F8R2_FB0_Msk       (0x1U << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos       (1U)                                            
+#define CAN_F8R2_FB1_Msk       (0x1U << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos       (2U)                                            
+#define CAN_F8R2_FB2_Msk       (0x1U << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos       (3U)                                            
+#define CAN_F8R2_FB3_Msk       (0x1U << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos       (4U)                                            
+#define CAN_F8R2_FB4_Msk       (0x1U << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos       (5U)                                            
+#define CAN_F8R2_FB5_Msk       (0x1U << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos       (6U)                                            
+#define CAN_F8R2_FB6_Msk       (0x1U << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos       (7U)                                            
+#define CAN_F8R2_FB7_Msk       (0x1U << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos       (8U)                                            
+#define CAN_F8R2_FB8_Msk       (0x1U << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos       (9U)                                            
+#define CAN_F8R2_FB9_Msk       (0x1U << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos      (10U)                                           
+#define CAN_F8R2_FB10_Msk      (0x1U << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos      (11U)                                           
+#define CAN_F8R2_FB11_Msk      (0x1U << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos      (12U)                                           
+#define CAN_F8R2_FB12_Msk      (0x1U << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos      (13U)                                           
+#define CAN_F8R2_FB13_Msk      (0x1U << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos      (14U)                                           
+#define CAN_F8R2_FB14_Msk      (0x1U << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos      (15U)                                           
+#define CAN_F8R2_FB15_Msk      (0x1U << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos      (16U)                                           
+#define CAN_F8R2_FB16_Msk      (0x1U << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos      (17U)                                           
+#define CAN_F8R2_FB17_Msk      (0x1U << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos      (18U)                                           
+#define CAN_F8R2_FB18_Msk      (0x1U << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos      (19U)                                           
+#define CAN_F8R2_FB19_Msk      (0x1U << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos      (20U)                                           
+#define CAN_F8R2_FB20_Msk      (0x1U << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos      (21U)                                           
+#define CAN_F8R2_FB21_Msk      (0x1U << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos      (22U)                                           
+#define CAN_F8R2_FB22_Msk      (0x1U << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos      (23U)                                           
+#define CAN_F8R2_FB23_Msk      (0x1U << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos      (24U)                                           
+#define CAN_F8R2_FB24_Msk      (0x1U << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos      (25U)                                           
+#define CAN_F8R2_FB25_Msk      (0x1U << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos      (26U)                                           
+#define CAN_F8R2_FB26_Msk      (0x1U << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos      (27U)                                           
+#define CAN_F8R2_FB27_Msk      (0x1U << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos      (28U)                                           
+#define CAN_F8R2_FB28_Msk      (0x1U << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos      (29U)                                           
+#define CAN_F8R2_FB29_Msk      (0x1U << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos      (30U)                                           
+#define CAN_F8R2_FB30_Msk      (0x1U << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos      (31U)                                           
+#define CAN_F8R2_FB31_Msk      (0x1U << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define CAN_F9R2_FB0_Pos       (0U)                                            
+#define CAN_F9R2_FB0_Msk       (0x1U << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos       (1U)                                            
+#define CAN_F9R2_FB1_Msk       (0x1U << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos       (2U)                                            
+#define CAN_F9R2_FB2_Msk       (0x1U << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos       (3U)                                            
+#define CAN_F9R2_FB3_Msk       (0x1U << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos       (4U)                                            
+#define CAN_F9R2_FB4_Msk       (0x1U << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos       (5U)                                            
+#define CAN_F9R2_FB5_Msk       (0x1U << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos       (6U)                                            
+#define CAN_F9R2_FB6_Msk       (0x1U << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos       (7U)                                            
+#define CAN_F9R2_FB7_Msk       (0x1U << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos       (8U)                                            
+#define CAN_F9R2_FB8_Msk       (0x1U << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos       (9U)                                            
+#define CAN_F9R2_FB9_Msk       (0x1U << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos      (10U)                                           
+#define CAN_F9R2_FB10_Msk      (0x1U << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos      (11U)                                           
+#define CAN_F9R2_FB11_Msk      (0x1U << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos      (12U)                                           
+#define CAN_F9R2_FB12_Msk      (0x1U << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos      (13U)                                           
+#define CAN_F9R2_FB13_Msk      (0x1U << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos      (14U)                                           
+#define CAN_F9R2_FB14_Msk      (0x1U << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos      (15U)                                           
+#define CAN_F9R2_FB15_Msk      (0x1U << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos      (16U)                                           
+#define CAN_F9R2_FB16_Msk      (0x1U << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos      (17U)                                           
+#define CAN_F9R2_FB17_Msk      (0x1U << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos      (18U)                                           
+#define CAN_F9R2_FB18_Msk      (0x1U << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos      (19U)                                           
+#define CAN_F9R2_FB19_Msk      (0x1U << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos      (20U)                                           
+#define CAN_F9R2_FB20_Msk      (0x1U << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos      (21U)                                           
+#define CAN_F9R2_FB21_Msk      (0x1U << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos      (22U)                                           
+#define CAN_F9R2_FB22_Msk      (0x1U << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos      (23U)                                           
+#define CAN_F9R2_FB23_Msk      (0x1U << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos      (24U)                                           
+#define CAN_F9R2_FB24_Msk      (0x1U << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos      (25U)                                           
+#define CAN_F9R2_FB25_Msk      (0x1U << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos      (26U)                                           
+#define CAN_F9R2_FB26_Msk      (0x1U << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos      (27U)                                           
+#define CAN_F9R2_FB27_Msk      (0x1U << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos      (28U)                                           
+#define CAN_F9R2_FB28_Msk      (0x1U << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos      (29U)                                           
+#define CAN_F9R2_FB29_Msk      (0x1U << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos      (30U)                                           
+#define CAN_F9R2_FB30_Msk      (0x1U << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos      (31U)                                           
+#define CAN_F9R2_FB31_Msk      (0x1U << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define CAN_F10R2_FB0_Pos      (0U)                                            
+#define CAN_F10R2_FB0_Msk      (0x1U << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos      (1U)                                            
+#define CAN_F10R2_FB1_Msk      (0x1U << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos      (2U)                                            
+#define CAN_F10R2_FB2_Msk      (0x1U << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos      (3U)                                            
+#define CAN_F10R2_FB3_Msk      (0x1U << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos      (4U)                                            
+#define CAN_F10R2_FB4_Msk      (0x1U << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos      (5U)                                            
+#define CAN_F10R2_FB5_Msk      (0x1U << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos      (6U)                                            
+#define CAN_F10R2_FB6_Msk      (0x1U << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos      (7U)                                            
+#define CAN_F10R2_FB7_Msk      (0x1U << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos      (8U)                                            
+#define CAN_F10R2_FB8_Msk      (0x1U << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos      (9U)                                            
+#define CAN_F10R2_FB9_Msk      (0x1U << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos     (10U)                                           
+#define CAN_F10R2_FB10_Msk     (0x1U << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos     (11U)                                           
+#define CAN_F10R2_FB11_Msk     (0x1U << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos     (12U)                                           
+#define CAN_F10R2_FB12_Msk     (0x1U << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos     (13U)                                           
+#define CAN_F10R2_FB13_Msk     (0x1U << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos     (14U)                                           
+#define CAN_F10R2_FB14_Msk     (0x1U << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos     (15U)                                           
+#define CAN_F10R2_FB15_Msk     (0x1U << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos     (16U)                                           
+#define CAN_F10R2_FB16_Msk     (0x1U << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos     (17U)                                           
+#define CAN_F10R2_FB17_Msk     (0x1U << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos     (18U)                                           
+#define CAN_F10R2_FB18_Msk     (0x1U << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos     (19U)                                           
+#define CAN_F10R2_FB19_Msk     (0x1U << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos     (20U)                                           
+#define CAN_F10R2_FB20_Msk     (0x1U << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos     (21U)                                           
+#define CAN_F10R2_FB21_Msk     (0x1U << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos     (22U)                                           
+#define CAN_F10R2_FB22_Msk     (0x1U << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos     (23U)                                           
+#define CAN_F10R2_FB23_Msk     (0x1U << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos     (24U)                                           
+#define CAN_F10R2_FB24_Msk     (0x1U << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos     (25U)                                           
+#define CAN_F10R2_FB25_Msk     (0x1U << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos     (26U)                                           
+#define CAN_F10R2_FB26_Msk     (0x1U << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos     (27U)                                           
+#define CAN_F10R2_FB27_Msk     (0x1U << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos     (28U)                                           
+#define CAN_F10R2_FB28_Msk     (0x1U << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos     (29U)                                           
+#define CAN_F10R2_FB29_Msk     (0x1U << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos     (30U)                                           
+#define CAN_F10R2_FB30_Msk     (0x1U << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos     (31U)                                           
+#define CAN_F10R2_FB31_Msk     (0x1U << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define CAN_F11R2_FB0_Pos      (0U)                                            
+#define CAN_F11R2_FB0_Msk      (0x1U << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos      (1U)                                            
+#define CAN_F11R2_FB1_Msk      (0x1U << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos      (2U)                                            
+#define CAN_F11R2_FB2_Msk      (0x1U << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos      (3U)                                            
+#define CAN_F11R2_FB3_Msk      (0x1U << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos      (4U)                                            
+#define CAN_F11R2_FB4_Msk      (0x1U << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos      (5U)                                            
+#define CAN_F11R2_FB5_Msk      (0x1U << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos      (6U)                                            
+#define CAN_F11R2_FB6_Msk      (0x1U << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos      (7U)                                            
+#define CAN_F11R2_FB7_Msk      (0x1U << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos      (8U)                                            
+#define CAN_F11R2_FB8_Msk      (0x1U << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos      (9U)                                            
+#define CAN_F11R2_FB9_Msk      (0x1U << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos     (10U)                                           
+#define CAN_F11R2_FB10_Msk     (0x1U << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos     (11U)                                           
+#define CAN_F11R2_FB11_Msk     (0x1U << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos     (12U)                                           
+#define CAN_F11R2_FB12_Msk     (0x1U << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos     (13U)                                           
+#define CAN_F11R2_FB13_Msk     (0x1U << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos     (14U)                                           
+#define CAN_F11R2_FB14_Msk     (0x1U << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos     (15U)                                           
+#define CAN_F11R2_FB15_Msk     (0x1U << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos     (16U)                                           
+#define CAN_F11R2_FB16_Msk     (0x1U << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos     (17U)                                           
+#define CAN_F11R2_FB17_Msk     (0x1U << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos     (18U)                                           
+#define CAN_F11R2_FB18_Msk     (0x1U << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos     (19U)                                           
+#define CAN_F11R2_FB19_Msk     (0x1U << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos     (20U)                                           
+#define CAN_F11R2_FB20_Msk     (0x1U << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos     (21U)                                           
+#define CAN_F11R2_FB21_Msk     (0x1U << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos     (22U)                                           
+#define CAN_F11R2_FB22_Msk     (0x1U << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos     (23U)                                           
+#define CAN_F11R2_FB23_Msk     (0x1U << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos     (24U)                                           
+#define CAN_F11R2_FB24_Msk     (0x1U << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos     (25U)                                           
+#define CAN_F11R2_FB25_Msk     (0x1U << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos     (26U)                                           
+#define CAN_F11R2_FB26_Msk     (0x1U << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos     (27U)                                           
+#define CAN_F11R2_FB27_Msk     (0x1U << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos     (28U)                                           
+#define CAN_F11R2_FB28_Msk     (0x1U << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos     (29U)                                           
+#define CAN_F11R2_FB29_Msk     (0x1U << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos     (30U)                                           
+#define CAN_F11R2_FB30_Msk     (0x1U << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos     (31U)                                           
+#define CAN_F11R2_FB31_Msk     (0x1U << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define CAN_F12R2_FB0_Pos      (0U)                                            
+#define CAN_F12R2_FB0_Msk      (0x1U << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos      (1U)                                            
+#define CAN_F12R2_FB1_Msk      (0x1U << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos      (2U)                                            
+#define CAN_F12R2_FB2_Msk      (0x1U << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos      (3U)                                            
+#define CAN_F12R2_FB3_Msk      (0x1U << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos      (4U)                                            
+#define CAN_F12R2_FB4_Msk      (0x1U << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos      (5U)                                            
+#define CAN_F12R2_FB5_Msk      (0x1U << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos      (6U)                                            
+#define CAN_F12R2_FB6_Msk      (0x1U << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos      (7U)                                            
+#define CAN_F12R2_FB7_Msk      (0x1U << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos      (8U)                                            
+#define CAN_F12R2_FB8_Msk      (0x1U << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos      (9U)                                            
+#define CAN_F12R2_FB9_Msk      (0x1U << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos     (10U)                                           
+#define CAN_F12R2_FB10_Msk     (0x1U << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos     (11U)                                           
+#define CAN_F12R2_FB11_Msk     (0x1U << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos     (12U)                                           
+#define CAN_F12R2_FB12_Msk     (0x1U << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos     (13U)                                           
+#define CAN_F12R2_FB13_Msk     (0x1U << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos     (14U)                                           
+#define CAN_F12R2_FB14_Msk     (0x1U << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos     (15U)                                           
+#define CAN_F12R2_FB15_Msk     (0x1U << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos     (16U)                                           
+#define CAN_F12R2_FB16_Msk     (0x1U << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos     (17U)                                           
+#define CAN_F12R2_FB17_Msk     (0x1U << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos     (18U)                                           
+#define CAN_F12R2_FB18_Msk     (0x1U << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos     (19U)                                           
+#define CAN_F12R2_FB19_Msk     (0x1U << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos     (20U)                                           
+#define CAN_F12R2_FB20_Msk     (0x1U << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos     (21U)                                           
+#define CAN_F12R2_FB21_Msk     (0x1U << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos     (22U)                                           
+#define CAN_F12R2_FB22_Msk     (0x1U << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos     (23U)                                           
+#define CAN_F12R2_FB23_Msk     (0x1U << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos     (24U)                                           
+#define CAN_F12R2_FB24_Msk     (0x1U << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos     (25U)                                           
+#define CAN_F12R2_FB25_Msk     (0x1U << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos     (26U)                                           
+#define CAN_F12R2_FB26_Msk     (0x1U << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos     (27U)                                           
+#define CAN_F12R2_FB27_Msk     (0x1U << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos     (28U)                                           
+#define CAN_F12R2_FB28_Msk     (0x1U << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos     (29U)                                           
+#define CAN_F12R2_FB29_Msk     (0x1U << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos     (30U)                                           
+#define CAN_F12R2_FB30_Msk     (0x1U << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos     (31U)                                           
+#define CAN_F12R2_FB31_Msk     (0x1U << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define CAN_F13R2_FB0_Pos      (0U)                                            
+#define CAN_F13R2_FB0_Msk      (0x1U << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos      (1U)                                            
+#define CAN_F13R2_FB1_Msk      (0x1U << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos      (2U)                                            
+#define CAN_F13R2_FB2_Msk      (0x1U << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos      (3U)                                            
+#define CAN_F13R2_FB3_Msk      (0x1U << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos      (4U)                                            
+#define CAN_F13R2_FB4_Msk      (0x1U << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos      (5U)                                            
+#define CAN_F13R2_FB5_Msk      (0x1U << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos      (6U)                                            
+#define CAN_F13R2_FB6_Msk      (0x1U << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos      (7U)                                            
+#define CAN_F13R2_FB7_Msk      (0x1U << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos      (8U)                                            
+#define CAN_F13R2_FB8_Msk      (0x1U << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos      (9U)                                            
+#define CAN_F13R2_FB9_Msk      (0x1U << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos     (10U)                                           
+#define CAN_F13R2_FB10_Msk     (0x1U << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos     (11U)                                           
+#define CAN_F13R2_FB11_Msk     (0x1U << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos     (12U)                                           
+#define CAN_F13R2_FB12_Msk     (0x1U << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos     (13U)                                           
+#define CAN_F13R2_FB13_Msk     (0x1U << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos     (14U)                                           
+#define CAN_F13R2_FB14_Msk     (0x1U << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos     (15U)                                           
+#define CAN_F13R2_FB15_Msk     (0x1U << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos     (16U)                                           
+#define CAN_F13R2_FB16_Msk     (0x1U << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos     (17U)                                           
+#define CAN_F13R2_FB17_Msk     (0x1U << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos     (18U)                                           
+#define CAN_F13R2_FB18_Msk     (0x1U << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos     (19U)                                           
+#define CAN_F13R2_FB19_Msk     (0x1U << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos     (20U)                                           
+#define CAN_F13R2_FB20_Msk     (0x1U << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos     (21U)                                           
+#define CAN_F13R2_FB21_Msk     (0x1U << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos     (22U)                                           
+#define CAN_F13R2_FB22_Msk     (0x1U << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos     (23U)                                           
+#define CAN_F13R2_FB23_Msk     (0x1U << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos     (24U)                                           
+#define CAN_F13R2_FB24_Msk     (0x1U << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos     (25U)                                           
+#define CAN_F13R2_FB25_Msk     (0x1U << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos     (26U)                                           
+#define CAN_F13R2_FB26_Msk     (0x1U << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos     (27U)                                           
+#define CAN_F13R2_FB27_Msk     (0x1U << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos     (28U)                                           
+#define CAN_F13R2_FB28_Msk     (0x1U << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos     (29U)                                           
+#define CAN_F13R2_FB29_Msk     (0x1U << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos     (30U)                                           
+#define CAN_F13R2_FB30_Msk     (0x1U << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos     (31U)                                           
+#define CAN_F13R2_FB31_Msk     (0x1U << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos            (0U)                                          
+#define CRC_DR_DR_Msk            (0xFFFFFFFFU << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos          (0U)                                          
+#define CRC_IDR_IDR_Msk          (0xFFU << CRC_IDR_IDR_Pos)                    /*!< 0x000000FF */
+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos         (0U)                                          
+#define CRC_CR_RESET_Msk         (0x1U << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos      (3U)                                          
+#define CRC_CR_POLYSIZE_Msk      (0x3U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0        (0x1U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1        (0x2U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos        (5U)                                          
+#define CRC_CR_REV_IN_Msk        (0x3U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0          (0x1U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1          (0x2U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos       (7U)                                          
+#define CRC_CR_REV_OUT_Msk       (0x1U << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define CRC_INIT_INIT_Pos        (0U)                                          
+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFU << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define CRC_POL_POL_Pos          (0U)                                          
+#define CRC_POL_POL_Msk          (0xFFFFFFFFU << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRS Clock Recovery System                         */
+/******************************************************************************/
+
+/*******************  Bit definition for CRS_CR register  *********************/
+#define CRS_CR_SYNCOKIE_Pos       (0U)                                         
+#define CRS_CR_SYNCOKIE_Msk       (0x1U << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE_Pos     (1U)                                         
+#define CRS_CR_SYNCWARNIE_Msk     (0x1U << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
+#define CRS_CR_ERRIE_Pos          (2U)                                         
+#define CRS_CR_ERRIE_Msk          (0x1U << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */
+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
+#define CRS_CR_ESYNCIE_Pos        (3U)                                         
+#define CRS_CR_ESYNCIE_Msk        (0x1U << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
+#define CRS_CR_CEN_Pos            (5U)                                         
+#define CRS_CR_CEN_Msk            (0x1U << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */
+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN_Pos     (6U)                                         
+#define CRS_CR_AUTOTRIMEN_Msk     (0x1U << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
+#define CRS_CR_SWSYNC_Pos         (7U)                                         
+#define CRS_CR_SWSYNC_Msk         (0x1U << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */
+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
+#define CRS_CR_TRIM_Pos           (8U)                                         
+#define CRS_CR_TRIM_Msk           (0x3FU << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */
+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
+
+/*******************  Bit definition for CRS_CFGR register  *********************/
+#define CRS_CFGR_RELOAD_Pos       (0U)                                         
+#define CRS_CFGR_RELOAD_Msk       (0xFFFFU << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
+#define CRS_CFGR_FELIM_Pos        (16U)                                        
+#define CRS_CFGR_FELIM_Msk        (0xFFU << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV_Pos      (24U)                                        
+#define CRS_CFGR_SYNCDIV_Msk      (0x7U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
+#define CRS_CFGR_SYNCDIV_0        (0x1U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1        (0x2U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2        (0x4U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
+
+#define CRS_CFGR_SYNCSRC_Pos      (28U)                                        
+#define CRS_CFGR_SYNCSRC_Msk      (0x3U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0        (0x1U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1        (0x2U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
+
+#define CRS_CFGR_SYNCPOL_Pos      (31U)                                        
+#define CRS_CFGR_SYNCPOL_Msk      (0x1U << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
+  
+/*******************  Bit definition for CRS_ISR register  *********************/
+#define CRS_ISR_SYNCOKF_Pos       (0U)                                         
+#define CRS_ISR_SYNCOKF_Msk       (0x1U << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF_Pos     (1U)                                         
+#define CRS_ISR_SYNCWARNF_Msk     (0x1U << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
+#define CRS_ISR_ERRF_Pos          (2U)                                         
+#define CRS_ISR_ERRF_Msk          (0x1U << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */
+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
+#define CRS_ISR_ESYNCF_Pos        (3U)                                         
+#define CRS_ISR_ESYNCF_Msk        (0x1U << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
+#define CRS_ISR_SYNCERR_Pos       (8U)                                         
+#define CRS_ISR_SYNCERR_Msk       (0x1U << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
+#define CRS_ISR_SYNCMISS_Pos      (9U)                                         
+#define CRS_ISR_SYNCMISS_Msk      (0x1U << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
+#define CRS_ISR_TRIMOVF_Pos       (10U)                                        
+#define CRS_ISR_TRIMOVF_Msk       (0x1U << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos         (15U)                                        
+#define CRS_ISR_FEDIR_Msk         (0x1U << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */
+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
+#define CRS_ISR_FECAP_Pos         (16U)                                        
+#define CRS_ISR_FECAP_Msk         (0xFFFFU << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
+
+/*******************  Bit definition for CRS_ICR register  *********************/
+#define CRS_ICR_SYNCOKC_Pos       (0U)                                         
+#define CRS_ICR_SYNCOKC_Msk       (0x1U << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC_Pos     (1U)                                         
+#define CRS_ICR_SYNCWARNC_Msk     (0x1U << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
+#define CRS_ICR_ERRC_Pos          (2U)                                         
+#define CRS_ICR_ERRC_Msk          (0x1U << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */
+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
+#define CRS_ICR_ESYNCC_Pos        (3U)                                         
+#define CRS_ICR_ESYNCC_Msk        (0x1U << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+ */
+#define DAC_CHANNEL2_SUPPORT                           /*!< DAC feature available only on specific devices: DAC channel 2 available */
+
+/********************  Bit definition for DAC_CR register  ********************/
+#define DAC_CR_EN1_Pos              (0U)                                       
+#define DAC_CR_EN1_Msk              (0x1U << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
+#define DAC_CR_TEN1_Pos             (2U)                                       
+#define DAC_CR_TEN1_Msk             (0x1U << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos            (3U)                                       
+#define DAC_CR_TSEL1_Msk            (0x7U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0              (0x1U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1              (0x2U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2              (0x4U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos            (6U)                                       
+#define DAC_CR_WAVE1_Msk            (0x3U << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0              (0x1U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1              (0x2U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos            (8U)                                       
+#define DAC_CR_MAMP1_Msk            (0xFU << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0              (0x1U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1              (0x2U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2              (0x4U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3              (0x8U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos           (12U)                                      
+#define DAC_CR_DMAEN1_Msk           (0x1U << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos        (13U)                                      
+#define DAC_CR_DMAUDRIE1_Msk        (0x1U << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN1_Pos             (14U)                                      
+#define DAC_CR_CEN1_Msk             (0x1U << DAC_CR_CEN1_Pos)                  /*!< 0x00004000 */
+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
+
+#define DAC_CR_EN2_Pos              (16U)                                      
+#define DAC_CR_EN2_Msk              (0x1U << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
+#define DAC_CR_TEN2_Pos             (18U)                                      
+#define DAC_CR_TEN2_Msk             (0x1U << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos            (19U)                                      
+#define DAC_CR_TSEL2_Msk            (0x7U << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0              (0x1U << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1              (0x2U << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2              (0x4U << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos            (22U)                                      
+#define DAC_CR_WAVE2_Msk            (0x3U << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0              (0x1U << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1              (0x2U << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos            (24U)                                      
+#define DAC_CR_MAMP2_Msk            (0xFU << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0              (0x1U << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1              (0x2U << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2              (0x4U << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3              (0x8U << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos           (28U)                                      
+#define DAC_CR_DMAEN2_Msk           (0x1U << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos        (29U)                                      
+#define DAC_CR_DMAUDRIE2_Msk        (0x1U << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN2_Pos             (30U)                                      
+#define DAC_CR_CEN2_Msk             (0x1U << DAC_CR_CEN2_Pos)                  /*!< 0x40000000 */
+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)                                       
+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)                                       
+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1U << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)                                       
+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)                                       
+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)                                       
+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFU << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)                                      
+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)                                      
+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFU << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)                                       
+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFU << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR_Pos       (0U)                                       
+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFU << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DOR2_DACC2DOR_Pos       (0U)                                       
+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFU << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_DMAUDR1_Pos          (13U)                                      
+#define DAC_SR_DMAUDR1_Msk          (0x1U << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_CAL_FLAG1_Pos        (14U)                                      
+#define DAC_SR_CAL_FLAG1_Msk        (0x1U << DAC_SR_CAL_FLAG1_Pos)             /*!< 0x00004000 */
+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
+#define DAC_SR_BWST1_Pos            (15U)                                      
+#define DAC_SR_BWST1_Msk            (0x1U << DAC_SR_BWST1_Pos)                 /*!< 0x00008000 */
+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
+
+#define DAC_SR_DMAUDR2_Pos          (29U)                                      
+#define DAC_SR_DMAUDR2_Msk          (0x1U << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
+#define DAC_SR_CAL_FLAG2_Pos        (30U)                                      
+#define DAC_SR_CAL_FLAG2_Msk        (0x1U << DAC_SR_CAL_FLAG2_Pos)             /*!< 0x40000000 */
+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
+#define DAC_SR_BWST2_Pos            (31U)                                      
+#define DAC_SR_BWST2_Msk            (0x1U << DAC_SR_BWST2_Pos)                 /*!< 0x80000000 */
+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
+
+/*******************  Bit definition for DAC_CCR register  ********************/
+#define DAC_CCR_OTRIM1_Pos          (0U)                                       
+#define DAC_CCR_OTRIM1_Msk          (0x1FU << DAC_CCR_OTRIM1_Pos)              /*!< 0x0000001F */
+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
+#define DAC_CCR_OTRIM2_Pos          (16U)                                      
+#define DAC_CCR_OTRIM2_Msk          (0x1FU << DAC_CCR_OTRIM2_Pos)              /*!< 0x001F0000 */
+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
+
+/*******************  Bit definition for DAC_MCR register  *******************/
+#define DAC_MCR_MODE1_Pos           (0U)                                       
+#define DAC_MCR_MODE1_Msk           (0x7U << DAC_MCR_MODE1_Pos)                /*!< 0x00000007 */
+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
+#define DAC_MCR_MODE1_0             (0x1U << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */
+#define DAC_MCR_MODE1_1             (0x2U << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */
+#define DAC_MCR_MODE1_2             (0x4U << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */
+
+#define DAC_MCR_MODE2_Pos           (16U)                                      
+#define DAC_MCR_MODE2_Msk           (0x7U << DAC_MCR_MODE2_Pos)                /*!< 0x00070000 */
+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
+#define DAC_MCR_MODE2_0             (0x1U << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */
+#define DAC_MCR_MODE2_1             (0x2U << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */
+#define DAC_MCR_MODE2_2             (0x4U << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */
+
+/******************  Bit definition for DAC_SHSR1 register  ******************/
+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)                                       
+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos)         /*!< 0x000003FF */
+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
+
+/******************  Bit definition for DAC_SHSR2 register  ******************/
+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)                                       
+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos)         /*!< 0x000003FF */
+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
+
+/******************  Bit definition for DAC_SHHR register  ******************/
+#define DAC_SHHR_THOLD1_Pos         (0U)                                       
+#define DAC_SHHR_THOLD1_Msk         (0x3FFU << DAC_SHHR_THOLD1_Pos)            /*!< 0x000003FF */
+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
+#define DAC_SHHR_THOLD2_Pos         (16U)                                      
+#define DAC_SHHR_THOLD2_Msk         (0x3FFU << DAC_SHHR_THOLD2_Pos)            /*!< 0x03FF0000 */
+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
+
+/******************  Bit definition for DAC_SHRR register  ******************/
+#define DAC_SHRR_TREFRESH1_Pos      (0U)                                       
+#define DAC_SHRR_TREFRESH1_Msk      (0xFFU << DAC_SHRR_TREFRESH1_Pos)          /*!< 0x000000FF */
+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
+#define DAC_SHRR_TREFRESH2_Pos      (16U)                                      
+#define DAC_SHRR_TREFRESH2_Msk      (0xFFU << DAC_SHRR_TREFRESH2_Pos)          /*!< 0x00FF0000 */
+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    DCMI                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DCMI_CR register  ******************/
+#define DCMI_CR_CAPTURE_Pos           (0U)                                     
+#define DCMI_CR_CAPTURE_Msk           (0x1U << DCMI_CR_CAPTURE_Pos)            /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE               DCMI_CR_CAPTURE_Msk                      /*!< DCMI Capture enable */
+#define DCMI_CR_CM_Pos                (1U)                                     
+#define DCMI_CR_CM_Msk                (0x1U << DCMI_CR_CM_Pos)                 /*!< 0x00000002 */
+#define DCMI_CR_CM                    DCMI_CR_CM_Msk                           /*!< DCMI Capture mode */
+#define DCMI_CR_CROP_Pos              (2U)                                     
+#define DCMI_CR_CROP_Msk              (0x1U << DCMI_CR_CROP_Pos)               /*!< 0x00000004 */
+#define DCMI_CR_CROP                  DCMI_CR_CROP_Msk                         /*!< DCMI Crop feature */
+#define DCMI_CR_JPEG_Pos              (3U)                                     
+#define DCMI_CR_JPEG_Msk              (0x1U << DCMI_CR_JPEG_Pos)               /*!< 0x00000008 */
+#define DCMI_CR_JPEG                  DCMI_CR_JPEG_Msk                         /*!< DCMI JPEG format */
+#define DCMI_CR_ESS_Pos               (4U)                                     
+#define DCMI_CR_ESS_Msk               (0x1U << DCMI_CR_ESS_Pos)                /*!< 0x00000010 */
+#define DCMI_CR_ESS                   DCMI_CR_ESS_Msk                          /*!< DCMI Embedded synchronization select */
+#define DCMI_CR_PCKPOL_Pos            (5U)                                     
+#define DCMI_CR_PCKPOL_Msk            (0x1U << DCMI_CR_PCKPOL_Pos)             /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL                DCMI_CR_PCKPOL_Msk                       /*!< DCMI Pixel clock polarity */
+#define DCMI_CR_HSPOL_Pos             (6U)                                     
+#define DCMI_CR_HSPOL_Msk             (0x1U << DCMI_CR_HSPOL_Pos)              /*!< 0x00000040 */
+#define DCMI_CR_HSPOL                 DCMI_CR_HSPOL_Msk                        /*!< DCMI Horizontal synchronization polarity */
+#define DCMI_CR_VSPOL_Pos             (7U)                                     
+#define DCMI_CR_VSPOL_Msk             (0x1U << DCMI_CR_VSPOL_Pos)              /*!< 0x00000080 */
+#define DCMI_CR_VSPOL                 DCMI_CR_VSPOL_Msk                        /*!< DCMI Vertical synchronization polarity */
+#define DCMI_CR_FCRC_Pos              (8U)                                     
+#define DCMI_CR_FCRC_Msk              (0x3U << DCMI_CR_FCRC_Pos)               /*!< 0x00000300 */
+#define DCMI_CR_FCRC                  DCMI_CR_FCRC_Msk                         /*!< DCMI Frame capture rate control FCRC[1:0] */
+#define DCMI_CR_FCRC_0                (0x1U << DCMI_CR_FCRC_Pos)               /*!< 0x00000100 */
+#define DCMI_CR_FCRC_1                (0x2U << DCMI_CR_FCRC_Pos)               /*!< 0x00000200 */
+#define DCMI_CR_EDM_Pos               (10U)                                    
+#define DCMI_CR_EDM_Msk               (0x3U << DCMI_CR_EDM_Pos)                /*!< 0x00000C00 */
+#define DCMI_CR_EDM                   DCMI_CR_EDM_Msk                          /*!< DCMI Extended data mode EDM[1:0] */
+#define DCMI_CR_EDM_0                 (0x1U << DCMI_CR_EDM_Pos)                /*!< 0x00000400 */
+#define DCMI_CR_EDM_1                 (0x2U << DCMI_CR_EDM_Pos)                /*!< 0x00000800 */
+#define DCMI_CR_ENABLE_Pos            (14U)                                    
+#define DCMI_CR_ENABLE_Msk            (0x1U << DCMI_CR_ENABLE_Pos)             /*!< 0x00004000 */
+#define DCMI_CR_ENABLE                DCMI_CR_ENABLE_Msk                       /*!< DCMI DCMI enable */
+#define DCMI_CR_BSM_Pos               (16U)                                    
+#define DCMI_CR_BSM_Msk               (0x3U << DCMI_CR_BSM_Pos)                /*!< 0x00030000 */
+#define DCMI_CR_BSM                   DCMI_CR_BSM_Msk                          /*!< DCMI Byte Select mode BSM[1:0] */
+#define DCMI_CR_BSM_0                 (0x1U << DCMI_CR_BSM_Pos)                /*!< 0x00010000 */
+#define DCMI_CR_BSM_1                 (0x2U << DCMI_CR_BSM_Pos)                /*!< 0x00020000 */
+#define DCMI_CR_OEBS_Pos              (18U)                                    
+#define DCMI_CR_OEBS_Msk              (0x1U << DCMI_CR_OEBS_Pos)               /*!< 0x00040000 */
+#define DCMI_CR_OEBS                  DCMI_CR_OEBS_Msk                         /*!< DCMI Odd/Even Byte Select (Byte Select Start) */
+#define DCMI_CR_LSM_Pos               (19U)                                    
+#define DCMI_CR_LSM_Msk               (0x1U << DCMI_CR_LSM_Pos)                /*!< 0x00080000 */
+#define DCMI_CR_LSM                   DCMI_CR_LSM_Msk                          /*!< DCMI Line Select mode */
+#define DCMI_CR_OELS_Pos              (20U)                                    
+#define DCMI_CR_OELS_Msk              (0x1U << DCMI_CR_OELS_Pos)               /*!< 0x00100000 */
+#define DCMI_CR_OELS                  DCMI_CR_OELS_Msk                         /*!< DCMI Odd/Even Line Select (Line Select Start) */
+
+/********************  Bits definition for DCMI_SR register  ******************/
+#define DCMI_SR_HSYNC_Pos             (0U)                                     
+#define DCMI_SR_HSYNC_Msk             (0x1U << DCMI_SR_HSYNC_Pos)              /*!< 0x00000001 */
+#define DCMI_SR_HSYNC                 DCMI_SR_HSYNC_Msk                        
+#define DCMI_SR_VSYNC_Pos             (1U)                                     
+#define DCMI_SR_VSYNC_Msk             (0x1U << DCMI_SR_VSYNC_Pos)              /*!< 0x00000002 */
+#define DCMI_SR_VSYNC                 DCMI_SR_VSYNC_Msk                        
+#define DCMI_SR_FNE_Pos               (2U)                                     
+#define DCMI_SR_FNE_Msk               (0x1U << DCMI_SR_FNE_Pos)                /*!< 0x00000004 */
+#define DCMI_SR_FNE                   DCMI_SR_FNE_Msk                          /*!< DCMI FIFO not empty */  
+
+/********************  Bits definition for DCMI_RISR register  ****************/
+#define DCMI_RIS_FRAME_RIS_Pos        (0U)                                     
+#define DCMI_RIS_FRAME_RIS_Msk        (0x1U << DCMI_RIS_FRAME_RIS_Pos)         /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS            DCMI_RIS_FRAME_RIS_Msk                   /*!< DCMI Capture complete raw interrupt status */               
+#define DCMI_RIS_OVR_RIS_Pos          (1U)                                     
+#define DCMI_RIS_OVR_RIS_Msk          (0x1U << DCMI_RIS_OVR_RIS_Pos)           /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS              DCMI_RIS_OVR_RIS_Msk                     /*!< DCMI Overrun raw interrupt status */                  
+#define DCMI_RIS_ERR_RIS_Pos          (2U)                                     
+#define DCMI_RIS_ERR_RIS_Msk          (0x1U << DCMI_RIS_ERR_RIS_Pos)           /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS              DCMI_RIS_ERR_RIS_Msk                     /*!< DCMI Synchronization error raw interrupt status */                  
+#define DCMI_RIS_VSYNC_RIS_Pos        (3U)                                     
+#define DCMI_RIS_VSYNC_RIS_Msk        (0x1U << DCMI_RIS_VSYNC_RIS_Pos)         /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS            DCMI_RIS_VSYNC_RIS_Msk                   /*!< DCMI VSYNC raw interrupt status */
+#define DCMI_RIS_LINE_RIS_Pos         (4U)                                     
+#define DCMI_RIS_LINE_RIS_Msk         (0x1U << DCMI_RIS_LINE_RIS_Pos)          /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS             DCMI_RIS_LINE_RIS_Msk                    /*!< DCMI Line raw interrupt status */                        
+
+/********************  Bits definition for DCMI_IER register  *****************/
+#define DCMI_IER_FRAME_IE_Pos         (0U)                                     
+#define DCMI_IER_FRAME_IE_Msk         (0x1U << DCMI_IER_FRAME_IE_Pos)          /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE             DCMI_IER_FRAME_IE_Msk                    /*!< DCMI Capture complete interrupt enable */     
+#define DCMI_IER_OVR_IE_Pos           (1U)                                     
+#define DCMI_IER_OVR_IE_Msk           (0x1U << DCMI_IER_OVR_IE_Pos)            /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE               DCMI_IER_OVR_IE_Msk                      /*!< DCMI Overrun interrupt enable */              
+#define DCMI_IER_ERR_IE_Pos           (2U)                                     
+#define DCMI_IER_ERR_IE_Msk           (0x1U << DCMI_IER_ERR_IE_Pos)            /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE               DCMI_IER_ERR_IE_Msk                      /*!< DCMI Synchronization error interrupt enable */
+#define DCMI_IER_VSYNC_IE_Pos         (3U)                                     
+#define DCMI_IER_VSYNC_IE_Msk         (0x1U << DCMI_IER_VSYNC_IE_Pos)          /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE             DCMI_IER_VSYNC_IE_Msk                    /*!< DCMI VSYNC interrupt enable */                
+#define DCMI_IER_LINE_IE_Pos          (4U)                                     
+#define DCMI_IER_LINE_IE_Msk          (0x1U << DCMI_IER_LINE_IE_Pos)           /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE              DCMI_IER_LINE_IE_Msk                     /*!< DCMI Line interrupt enable */
+#define DCMI_IER_INT_IE_Pos           (0U)                                     
+#define DCMI_IER_INT_IE_Msk           (0x1FU << DCMI_IER_INT_IE_Pos)           /*!< 0x0000001F */
+#define DCMI_IER_INT_IE               DCMI_IER_INT_IE_Msk                      
+
+/********************  Bits definition for DCMI_MIS register  *****************/
+#define DCMI_MIS_FRAME_MIS_Pos        (0U)                                     
+#define DCMI_MIS_FRAME_MIS_Msk        (0x1U << DCMI_MIS_FRAME_MIS_Pos)         /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS            DCMI_MIS_FRAME_MIS_Msk                   /*!< DCMI Capture complete masked interrupt status */      
+#define DCMI_MIS_OVR_MIS_Pos          (1U)                                     
+#define DCMI_MIS_OVR_MIS_Msk          (0x1U << DCMI_MIS_OVR_MIS_Pos)           /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS              DCMI_MIS_OVR_MIS_Msk                     /*!< DCMI Overrun masked interrupt status */               
+#define DCMI_MIS_ERR_MIS_Pos          (2U)                                     
+#define DCMI_MIS_ERR_MIS_Msk          (0x1U << DCMI_MIS_ERR_MIS_Pos)           /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS              DCMI_MIS_ERR_MIS_Msk                     /*!< DCMI Synchronization error masked interrupt status */ 
+#define DCMI_MIS_VSYNC_MIS_Pos        (3U)                                     
+#define DCMI_MIS_VSYNC_MIS_Msk        (0x1U << DCMI_MIS_VSYNC_MIS_Pos)         /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS            DCMI_MIS_VSYNC_MIS_Msk                   /*!< DCMI VSYNC masked interrupt status */                 
+#define DCMI_MIS_LINE_MIS_Pos         (4U)                                     
+#define DCMI_MIS_LINE_MIS_Msk         (0x1U << DCMI_MIS_LINE_MIS_Pos)          /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS             DCMI_MIS_LINE_MIS_Msk                    /*!< DCMI Line masked interrupt status */                   
+
+/********************  Bits definition for DCMI_ICR register  *****************/
+#define DCMI_ICR_FRAME_ISC_Pos        (0U)                                     
+#define DCMI_ICR_FRAME_ISC_Msk        (0x1U << DCMI_ICR_FRAME_ISC_Pos)         /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC            DCMI_ICR_FRAME_ISC_Msk                   /*!< DCMI Capture complete interrupt status clear */      
+#define DCMI_ICR_OVR_ISC_Pos          (1U)                                     
+#define DCMI_ICR_OVR_ISC_Msk          (0x1U << DCMI_ICR_OVR_ISC_Pos)           /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC              DCMI_ICR_OVR_ISC_Msk                     /*!< DCMI Overrun interrupt status clear */               
+#define DCMI_ICR_ERR_ISC_Pos          (2U)                                     
+#define DCMI_ICR_ERR_ISC_Msk          (0x1U << DCMI_ICR_ERR_ISC_Pos)           /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC              DCMI_ICR_ERR_ISC_Msk                     /*!< DCMI Synchronization error interrupt status clear */ 
+#define DCMI_ICR_VSYNC_ISC_Pos        (3U)                                     
+#define DCMI_ICR_VSYNC_ISC_Msk        (0x1U << DCMI_ICR_VSYNC_ISC_Pos)         /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC            DCMI_ICR_VSYNC_ISC_Msk                   /*!< DCMI Vertical synch interrupt status clear */                 
+#define DCMI_ICR_LINE_ISC_Pos         (4U)                                     
+#define DCMI_ICR_LINE_ISC_Msk         (0x1U << DCMI_ICR_LINE_ISC_Pos)          /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC             DCMI_ICR_LINE_ISC_Msk                    /*!< DCMI line interrupt status clear */                  
+
+/********************  Bits definition for DCMI_ESCR register  ****************/
+#define DCMI_ESCR_FSC_Pos             (0U)                                     
+#define DCMI_ESCR_FSC_Msk             (0xFFU << DCMI_ESCR_FSC_Pos)             /*!< 0x000000FF */
+#define DCMI_ESCR_FSC                 DCMI_ESCR_FSC_Msk                        /*!< DCMI Frame start delimiter code FSC[7:0] */
+#define DCMI_ESCR_FSC_0               (0x01U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000001 */
+#define DCMI_ESCR_FSC_1               (0x02U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000002 */
+#define DCMI_ESCR_FSC_2               (0x04U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000004 */
+#define DCMI_ESCR_FSC_3               (0x08U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000008 */
+#define DCMI_ESCR_FSC_4               (0x10U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000010 */
+#define DCMI_ESCR_FSC_5               (0x20U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000020 */
+#define DCMI_ESCR_FSC_6               (0x40U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000040 */
+#define DCMI_ESCR_FSC_7               (0x80U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000080 */
+#define DCMI_ESCR_LSC_Pos             (8U)                                     
+#define DCMI_ESCR_LSC_Msk             (0xFFU << DCMI_ESCR_LSC_Pos)             /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC                 DCMI_ESCR_LSC_Msk                        /*!< DCMI Line start delimiter code LSC[7:0] */
+#define DCMI_ESCR_LSC_0               (0x01U << DCMI_ESCR_LSC_Pos)             /*!< 0x00000100 */
+#define DCMI_ESCR_LSC_1               (0x02U << DCMI_ESCR_LSC_Pos)             /*!< 0x00000200 */
+#define DCMI_ESCR_LSC_2               (0x04U << DCMI_ESCR_LSC_Pos)             /*!< 0x00000400 */
+#define DCMI_ESCR_LSC_3               (0x08U << DCMI_ESCR_LSC_Pos)             /*!< 0x00000800 */
+#define DCMI_ESCR_LSC_4               (0x10U << DCMI_ESCR_LSC_Pos)             /*!< 0x00001000 */
+#define DCMI_ESCR_LSC_5               (0x20U << DCMI_ESCR_LSC_Pos)             /*!< 0x00002000 */
+#define DCMI_ESCR_LSC_6               (0x40U << DCMI_ESCR_LSC_Pos)             /*!< 0x00004000 */
+#define DCMI_ESCR_LSC_7               (0x80U << DCMI_ESCR_LSC_Pos)             /*!< 0x00008000 */
+#define DCMI_ESCR_LEC_Pos             (16U)                                    
+#define DCMI_ESCR_LEC_Msk             (0xFFU << DCMI_ESCR_LEC_Pos)             /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC                 DCMI_ESCR_LEC_Msk                        /*!< DCMI Line end delimiter code LEC[7:0] */
+#define DCMI_ESCR_LEC_0               (0x01U << DCMI_ESCR_LEC_Pos)             /*!< 0x00010000 */
+#define DCMI_ESCR_LEC_1               (0x02U << DCMI_ESCR_LEC_Pos)             /*!< 0x00020000 */
+#define DCMI_ESCR_LEC_2               (0x04U << DCMI_ESCR_LEC_Pos)             /*!< 0x00040000 */
+#define DCMI_ESCR_LEC_3               (0x08U << DCMI_ESCR_LEC_Pos)             /*!< 0x00080000 */
+#define DCMI_ESCR_LEC_4               (0x10U << DCMI_ESCR_LEC_Pos)             /*!< 0x00100000 */
+#define DCMI_ESCR_LEC_5               (0x20U << DCMI_ESCR_LEC_Pos)             /*!< 0x00200000 */
+#define DCMI_ESCR_LEC_6               (0x40U << DCMI_ESCR_LEC_Pos)             /*!< 0x00400000 */
+#define DCMI_ESCR_LEC_7               (0x80U << DCMI_ESCR_LEC_Pos)             /*!< 0x00800000 */
+#define DCMI_ESCR_FEC_Pos             (24U)                                    
+#define DCMI_ESCR_FEC_Msk             (0xFFU << DCMI_ESCR_FEC_Pos)             /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC                 DCMI_ESCR_FEC_Msk                        /*!< DCMI Frame end delimiter code FEC[7:0] */
+#define DCMI_ESCR_FEC_0               (0x01U << DCMI_ESCR_FEC_Pos)             /*!< 0x01000000 */
+#define DCMI_ESCR_FEC_1               (0x02U << DCMI_ESCR_FEC_Pos)             /*!< 0x02000000 */
+#define DCMI_ESCR_FEC_2               (0x04U << DCMI_ESCR_FEC_Pos)             /*!< 0x04000000 */
+#define DCMI_ESCR_FEC_3               (0x08U << DCMI_ESCR_FEC_Pos)             /*!< 0x08000000 */
+#define DCMI_ESCR_FEC_4               (0x10U << DCMI_ESCR_FEC_Pos)             /*!< 0x10000000 */
+#define DCMI_ESCR_FEC_5               (0x20U << DCMI_ESCR_FEC_Pos)             /*!< 0x20000000 */
+#define DCMI_ESCR_FEC_6               (0x40U << DCMI_ESCR_FEC_Pos)             /*!< 0x40000000 */
+#define DCMI_ESCR_FEC_7               (0x80U << DCMI_ESCR_FEC_Pos)             /*!< 0x80000000 */
+
+/********************  Bits definition for DCMI_ESUR register  ****************/
+#define DCMI_ESUR_FSU_Pos             (0U)                                     
+#define DCMI_ESUR_FSU_Msk             (0xFFU << DCMI_ESUR_FSU_Pos)             /*!< 0x000000FF */
+#define DCMI_ESUR_FSU                 DCMI_ESUR_FSU_Msk                        /*!< DCMI Frame start delimiter unmask FSU[7:0] */
+#define DCMI_ESUR_FSU_0               (0x01U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000001 */
+#define DCMI_ESUR_FSU_1               (0x02U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000002 */
+#define DCMI_ESUR_FSU_2               (0x04U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000004 */
+#define DCMI_ESUR_FSU_3               (0x08U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000008 */
+#define DCMI_ESUR_FSU_4               (0x10U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000010 */
+#define DCMI_ESUR_FSU_5               (0x20U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000020 */
+#define DCMI_ESUR_FSU_6               (0x40U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000040 */
+#define DCMI_ESUR_FSU_7               (0x80U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000080 */
+#define DCMI_ESUR_LSU_Pos             (8U)                                     
+#define DCMI_ESUR_LSU_Msk             (0xFFU << DCMI_ESUR_LSU_Pos)             /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU                 DCMI_ESUR_LSU_Msk                        /*!< DCMI Line start delimiter unmask LSU[7:0] */
+#define DCMI_ESUR_LSU_0               (0x01U << DCMI_ESUR_LSU_Pos)             /*!< 0x00000100 */
+#define DCMI_ESUR_LSU_1               (0x02U << DCMI_ESUR_LSU_Pos)             /*!< 0x00000200 */
+#define DCMI_ESUR_LSU_2               (0x04U << DCMI_ESUR_LSU_Pos)             /*!< 0x00000400 */
+#define DCMI_ESUR_LSU_3               (0x08U << DCMI_ESUR_LSU_Pos)             /*!< 0x00000800 */
+#define DCMI_ESUR_LSU_4               (0x10U << DCMI_ESUR_LSU_Pos)             /*!< 0x00001000 */
+#define DCMI_ESUR_LSU_5               (0x20U << DCMI_ESUR_LSU_Pos)             /*!< 0x00002000 */
+#define DCMI_ESUR_LSU_6               (0x40U << DCMI_ESUR_LSU_Pos)             /*!< 0x00004000 */
+#define DCMI_ESUR_LSU_7               (0x80U << DCMI_ESUR_LSU_Pos)             /*!< 0x00008000 */
+#define DCMI_ESUR_LEU_Pos             (16U)                                    
+#define DCMI_ESUR_LEU_Msk             (0xFFU << DCMI_ESUR_LEU_Pos)             /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU                 DCMI_ESUR_LEU_Msk                        /*!< DCMI Line end delimiter unmask LEU[7:0] */  
+#define DCMI_ESUR_LEU_0               (0x01U << DCMI_ESUR_LEU_Pos)             /*!< 0x00010000 */
+#define DCMI_ESUR_LEU_1               (0x02U << DCMI_ESUR_LEU_Pos)             /*!< 0x00020000 */
+#define DCMI_ESUR_LEU_2               (0x04U << DCMI_ESUR_LEU_Pos)             /*!< 0x00040000 */
+#define DCMI_ESUR_LEU_3               (0x08U << DCMI_ESUR_LEU_Pos)             /*!< 0x00080000 */
+#define DCMI_ESUR_LEU_4               (0x10U << DCMI_ESUR_LEU_Pos)             /*!< 0x00100000 */
+#define DCMI_ESUR_LEU_5               (0x20U << DCMI_ESUR_LEU_Pos)             /*!< 0x00200000 */
+#define DCMI_ESUR_LEU_6               (0x40U << DCMI_ESUR_LEU_Pos)             /*!< 0x00400000 */
+#define DCMI_ESUR_LEU_7               (0x80U << DCMI_ESUR_LEU_Pos)             /*!< 0x00800000 */
+#define DCMI_ESUR_FEU_Pos             (24U)                                    
+#define DCMI_ESUR_FEU_Msk             (0xFFU << DCMI_ESUR_FEU_Pos)             /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU                 DCMI_ESUR_FEU_Msk                        /*!< DCMI Frame end delimiter unmask FEU[7:0] */ 
+#define DCMI_ESUR_FEU_0               (0x01U << DCMI_ESUR_FEU_Pos)             /*!< 0x01000000 */
+#define DCMI_ESUR_FEU_1               (0x02U << DCMI_ESUR_FEU_Pos)             /*!< 0x02000000 */
+#define DCMI_ESUR_FEU_2               (0x04U << DCMI_ESUR_FEU_Pos)             /*!< 0x04000000 */
+#define DCMI_ESUR_FEU_3               (0x08U << DCMI_ESUR_FEU_Pos)             /*!< 0x08000000 */
+#define DCMI_ESUR_FEU_4               (0x10U << DCMI_ESUR_FEU_Pos)             /*!< 0x10000000 */
+#define DCMI_ESUR_FEU_5               (0x20U << DCMI_ESUR_FEU_Pos)             /*!< 0x20000000 */
+#define DCMI_ESUR_FEU_6               (0x40U << DCMI_ESUR_FEU_Pos)             /*!< 0x40000000 */
+#define DCMI_ESUR_FEU_7               (0x80U << DCMI_ESUR_FEU_Pos)             /*!< 0x80000000 */
+
+/********************  Bits definition for DCMI_CWSTRT register  **************/
+#define DCMI_CWSTRT_HOFFCNT_Pos       (0U)                                     
+#define DCMI_CWSTRT_HOFFCNT_Msk       (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT           DCMI_CWSTRT_HOFFCNT_Msk                  /*!< DCMI Horizontal offset count HOFFCNT[13:0] */  
+#define DCMI_CWSTRT_HOFFCNT_0         (0x0001U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000001 */
+#define DCMI_CWSTRT_HOFFCNT_1         (0x0002U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000002 */
+#define DCMI_CWSTRT_HOFFCNT_2         (0x0004U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000004 */
+#define DCMI_CWSTRT_HOFFCNT_3         (0x0008U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000008 */
+#define DCMI_CWSTRT_HOFFCNT_4         (0x0010U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000010 */
+#define DCMI_CWSTRT_HOFFCNT_5         (0x0020U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000020 */
+#define DCMI_CWSTRT_HOFFCNT_6         (0x0040U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000040 */
+#define DCMI_CWSTRT_HOFFCNT_7         (0x0080U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000080 */
+#define DCMI_CWSTRT_HOFFCNT_8         (0x0100U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000100 */
+#define DCMI_CWSTRT_HOFFCNT_9         (0x0200U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000200 */
+#define DCMI_CWSTRT_HOFFCNT_10        (0x0400U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000400 */
+#define DCMI_CWSTRT_HOFFCNT_11        (0x0800U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000800 */
+#define DCMI_CWSTRT_HOFFCNT_12        (0x1000U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00001000 */
+#define DCMI_CWSTRT_HOFFCNT_13        (0x2000U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00002000 */
+#define DCMI_CWSTRT_VST_Pos           (16U)                                    
+#define DCMI_CWSTRT_VST_Msk           (0x1FFFU << DCMI_CWSTRT_VST_Pos)         /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST               DCMI_CWSTRT_VST_Msk                      /*!< DCMI Vertical start line count VST[12:0] */
+#define DCMI_CWSTRT_VST_0             (0x0001U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00010000 */
+#define DCMI_CWSTRT_VST_1             (0x0002U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00020000 */
+#define DCMI_CWSTRT_VST_2             (0x0004U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00040000 */
+#define DCMI_CWSTRT_VST_3             (0x0008U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00080000 */
+#define DCMI_CWSTRT_VST_4             (0x0010U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00100000 */
+#define DCMI_CWSTRT_VST_5             (0x0020U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00200000 */
+#define DCMI_CWSTRT_VST_6             (0x0040U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00400000 */
+#define DCMI_CWSTRT_VST_7             (0x0080U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00800000 */
+#define DCMI_CWSTRT_VST_8             (0x0100U << DCMI_CWSTRT_VST_Pos)         /*!< 0x01000000 */
+#define DCMI_CWSTRT_VST_9             (0x0200U << DCMI_CWSTRT_VST_Pos)         /*!< 0x02000000 */
+#define DCMI_CWSTRT_VST_10            (0x0400U << DCMI_CWSTRT_VST_Pos)         /*!< 0x04000000 */
+#define DCMI_CWSTRT_VST_11            (0x0800U << DCMI_CWSTRT_VST_Pos)         /*!< 0x08000000 */
+#define DCMI_CWSTRT_VST_12            (0x1000U << DCMI_CWSTRT_VST_Pos)         /*!< 0x10000000 */
+                                                                         
+/********************  Bits definition for DCMI_CWSIZE register  **************/
+#define DCMI_CWSIZE_CAPCNT_Pos        (0U)                                     
+#define DCMI_CWSIZE_CAPCNT_Msk        (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT            DCMI_CWSIZE_CAPCNT_Msk                   /*!< DCMI Capture count CAPCNT[13:0] */
+#define DCMI_CWSIZE_CAPCNT_0          (0x0001U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000001 */
+#define DCMI_CWSIZE_CAPCNT_1          (0x0002U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000002 */
+#define DCMI_CWSIZE_CAPCNT_2          (0x0004U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000004 */
+#define DCMI_CWSIZE_CAPCNT_3          (0x0008U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000008 */
+#define DCMI_CWSIZE_CAPCNT_4          (0x0010U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000010 */
+#define DCMI_CWSIZE_CAPCNT_5          (0x0020U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000020 */
+#define DCMI_CWSIZE_CAPCNT_6          (0x0040U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000040 */
+#define DCMI_CWSIZE_CAPCNT_7          (0x0080U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000080 */
+#define DCMI_CWSIZE_CAPCNT_8          (0x0100U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000100 */
+#define DCMI_CWSIZE_CAPCNT_9          (0x0200U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000200 */
+#define DCMI_CWSIZE_CAPCNT_10         (0x0400U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000400 */
+#define DCMI_CWSIZE_CAPCNT_11         (0x0800U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000800 */
+#define DCMI_CWSIZE_CAPCNT_12         (0x1000U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00001000 */
+#define DCMI_CWSIZE_CAPCNT_13         (0x2000U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00002000 */
+#define DCMI_CWSIZE_VLINE_Pos         (16U)                                    
+#define DCMI_CWSIZE_VLINE_Msk         (0x3FFFU << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE             DCMI_CWSIZE_VLINE_Msk                    /*!< DCMI Vertical line count VLINE[13:0] */  
+#define DCMI_CWSIZE_VLINE_0           (0x0001U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00010000 */
+#define DCMI_CWSIZE_VLINE_1           (0x0002U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00020000 */
+#define DCMI_CWSIZE_VLINE_2           (0x0004U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00040000 */
+#define DCMI_CWSIZE_VLINE_3           (0x0008U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00080000 */
+#define DCMI_CWSIZE_VLINE_4           (0x0010U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00100000 */
+#define DCMI_CWSIZE_VLINE_5           (0x0020U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00200000 */
+#define DCMI_CWSIZE_VLINE_6           (0x0040U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00400000 */
+#define DCMI_CWSIZE_VLINE_7           (0x0080U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00800000 */
+#define DCMI_CWSIZE_VLINE_8           (0x0100U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x01000000 */
+#define DCMI_CWSIZE_VLINE_9           (0x0200U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x02000000 */
+#define DCMI_CWSIZE_VLINE_10          (0x0400U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x04000000 */
+#define DCMI_CWSIZE_VLINE_11          (0x0800U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x08000000 */
+#define DCMI_CWSIZE_VLINE_12          (0x1000U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x10000000 */
+#define DCMI_CWSIZE_VLINE_13          (0x2000U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x20000000 */
+
+/********************  Bits definition for DCMI_DR register  **************/
+#define DCMI_DR_BYTE0_Pos             (0U)                                     
+#define DCMI_DR_BYTE0_Msk             (0xFFU << DCMI_DR_BYTE0_Pos)             /*!< 0x000000FF */
+#define DCMI_DR_BYTE0                 DCMI_DR_BYTE0_Msk                        /*!< DCMI Data byte 0 Byte0[7:0] */
+#define DCMI_DR_BYTE0_0               (0x01U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000001 */
+#define DCMI_DR_BYTE0_1               (0x02U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000002 */
+#define DCMI_DR_BYTE0_2               (0x04U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000004 */
+#define DCMI_DR_BYTE0_3               (0x08U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000008 */
+#define DCMI_DR_BYTE0_4               (0x10U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000010 */
+#define DCMI_DR_BYTE0_5               (0x20U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000020 */
+#define DCMI_DR_BYTE0_6               (0x40U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000040 */
+#define DCMI_DR_BYTE0_7               (0x80U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000080 */
+#define DCMI_DR_BYTE1_Pos             (8U)                                     
+#define DCMI_DR_BYTE1_Msk             (0xFFU << DCMI_DR_BYTE1_Pos)             /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1                 DCMI_DR_BYTE1_Msk                        /*!< DCMI Data byte 1 Byte1[7:0] */
+#define DCMI_DR_BYTE1_0               (0x01U << DCMI_DR_BYTE1_Pos)             /*!< 0x00000100 */
+#define DCMI_DR_BYTE1_1               (0x02U << DCMI_DR_BYTE1_Pos)             /*!< 0x00000200 */
+#define DCMI_DR_BYTE1_2               (0x04U << DCMI_DR_BYTE1_Pos)             /*!< 0x00000400 */
+#define DCMI_DR_BYTE1_3               (0x08U << DCMI_DR_BYTE1_Pos)             /*!< 0x00000800 */
+#define DCMI_DR_BYTE1_4               (0x10U << DCMI_DR_BYTE1_Pos)             /*!< 0x00001000 */
+#define DCMI_DR_BYTE1_5               (0x20U << DCMI_DR_BYTE1_Pos)             /*!< 0x00002000 */
+#define DCMI_DR_BYTE1_6               (0x40U << DCMI_DR_BYTE1_Pos)             /*!< 0x00004000 */
+#define DCMI_DR_BYTE1_7               (0x80U << DCMI_DR_BYTE1_Pos)             /*!< 0x00008000 */
+#define DCMI_DR_BYTE2_Pos             (16U)                                    
+#define DCMI_DR_BYTE2_Msk             (0xFFU << DCMI_DR_BYTE2_Pos)             /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2                 DCMI_DR_BYTE2_Msk                        /*!< DCMI Data byte 2 Byte2[7:0] */
+#define DCMI_DR_BYTE2_0               (0x01U << DCMI_DR_BYTE2_Pos)             /*!< 0x00010000 */
+#define DCMI_DR_BYTE2_1               (0x02U << DCMI_DR_BYTE2_Pos)             /*!< 0x00020000 */
+#define DCMI_DR_BYTE2_2               (0x04U << DCMI_DR_BYTE2_Pos)             /*!< 0x00040000 */
+#define DCMI_DR_BYTE2_3               (0x08U << DCMI_DR_BYTE2_Pos)             /*!< 0x00080000 */
+#define DCMI_DR_BYTE2_4               (0x10U << DCMI_DR_BYTE2_Pos)             /*!< 0x00100000 */
+#define DCMI_DR_BYTE2_5               (0x20U << DCMI_DR_BYTE2_Pos)             /*!< 0x00200000 */
+#define DCMI_DR_BYTE2_6               (0x40U << DCMI_DR_BYTE2_Pos)             /*!< 0x00400000 */
+#define DCMI_DR_BYTE2_7               (0x80U << DCMI_DR_BYTE2_Pos)             /*!< 0x00800000 */
+#define DCMI_DR_BYTE3_Pos             (24U)                                    
+#define DCMI_DR_BYTE3_Msk             (0xFFU << DCMI_DR_BYTE3_Pos)             /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3                 DCMI_DR_BYTE3_Msk                        /*!< DCMI Data byte 3 Byte3[7:0] */
+#define DCMI_DR_BYTE3_0               (0x01U << DCMI_DR_BYTE3_Pos)             /*!< 0x01000000 */
+#define DCMI_DR_BYTE3_1               (0x02U << DCMI_DR_BYTE3_Pos)             /*!< 0x02000000 */
+#define DCMI_DR_BYTE3_2               (0x04U << DCMI_DR_BYTE3_Pos)             /*!< 0x04000000 */
+#define DCMI_DR_BYTE3_3               (0x08U << DCMI_DR_BYTE3_Pos)             /*!< 0x08000000 */
+#define DCMI_DR_BYTE3_4               (0x10U << DCMI_DR_BYTE3_Pos)             /*!< 0x10000000 */
+#define DCMI_DR_BYTE3_5               (0x20U << DCMI_DR_BYTE3_Pos)             /*!< 0x20000000 */
+#define DCMI_DR_BYTE3_6               (0x40U << DCMI_DR_BYTE3_Pos)             /*!< 0x40000000 */
+#define DCMI_DR_BYTE3_7               (0x80U << DCMI_DR_BYTE3_Pos)             /*!< 0x80000000 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital Filter for Sigma Delta Modulators                  */
+/*                                                                            */
+/******************************************************************************/
+
+/****************   DFSDM channel configuration registers  ********************/
+
+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)                                  
+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos)    /*!< 0x80000000 */
+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */
+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)                                  
+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos)   /*!< 0x40000000 */
+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */
+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)                                  
+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos)  /*!< 0x00FF0000 */
+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */
+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)                                  
+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x0000C000 */
+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */
+#define DFSDM_CHCFGR1_DATPACK_1         (0x2U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */
+#define DFSDM_CHCFGR1_DATPACK_0         (0x1U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */
+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)                                  
+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00003000 */
+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define DFSDM_CHCFGR1_DATMPX_1          (0x2U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */
+#define DFSDM_CHCFGR1_DATMPX_0          (0x1U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */
+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)                                   
+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos)    /*!< 0x00000100 */
+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */
+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)                                   
+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1U << DFSDM_CHCFGR1_CHEN_Pos)       /*!< 0x00000080 */
+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */
+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)                                   
+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1U << DFSDM_CHCFGR1_CKABEN_Pos)     /*!< 0x00000040 */
+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */
+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)                                   
+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1U << DFSDM_CHCFGR1_SCDEN_Pos)      /*!< 0x00000020 */
+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)                                   
+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x0000000C */
+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */
+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */
+#define DFSDM_CHCFGR1_SITP_Pos          (0U)                                   
+#define DFSDM_CHCFGR1_SITP_Msk          (0x3U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000003 */
+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */
+#define DFSDM_CHCFGR1_SITP_1            (0x2U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */
+#define DFSDM_CHCFGR1_SITP_0            (0x1U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */
+
+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)                                   
+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)                                   
+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos)     /*!< 0x000000F8 */
+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/****************  Bit definition for DFSDM_CHAWSCDR register *****************/
+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)                                  
+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00C00000 */
+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */
+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */
+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)                                  
+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos)   /*!< 0x001F0000 */
+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)                                  
+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos)     /*!< 0x0000F000 */
+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)                                   
+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos)     /*!< 0x000000FF */
+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/****************  Bit definition for DFSDM_CHWDATR register *******************/
+#define DFSDM_CHWDATR_WDATA_Pos         (0U)                                   
+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos)   /*!< 0x0000FFFF */
+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */
+
+/****************  Bit definition for DFSDM_CHDATINR register *****************/
+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)                                   
+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)                                  
+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */
+
+/************************   DFSDM module registers  ****************************/
+
+/*****************  Bit definition for DFSDM_FLTCR1 register *******************/
+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)                                  
+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1U << DFSDM_FLTCR1_AWFSEL_Pos)      /*!< 0x40000000 */
+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */
+#define DFSDM_FLTCR1_FAST_Pos           (29U)                                  
+#define DFSDM_FLTCR1_FAST_Msk           (0x1U << DFSDM_FLTCR1_FAST_Pos)        /*!< 0x20000000 */
+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */
+#define DFSDM_FLTCR1_RCH_Pos            (24U)                                  
+#define DFSDM_FLTCR1_RCH_Msk            (0x7U << DFSDM_FLTCR1_RCH_Pos)         /*!< 0x07000000 */
+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */
+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)                                  
+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1U << DFSDM_FLTCR1_RDMAEN_Pos)      /*!< 0x00200000 */
+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */
+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)                                  
+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1U << DFSDM_FLTCR1_RSYNC_Pos)       /*!< 0x00080000 */
+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */
+#define DFSDM_FLTCR1_RCONT_Pos          (18U)                                  
+#define DFSDM_FLTCR1_RCONT_Msk          (0x1U << DFSDM_FLTCR1_RCONT_Pos)       /*!< 0x00040000 */
+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */
+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)                                  
+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1U << DFSDM_FLTCR1_RSWSTART_Pos)    /*!< 0x00020000 */
+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */
+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)                                  
+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00006000 */
+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define DFSDM_FLTCR1_JEXTEN_1           (0x2U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */
+#define DFSDM_FLTCR1_JEXTEN_0           (0x1U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */
+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)                                   
+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x7U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000700 */
+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
+#define DFSDM_FLTCR1_JEXTSEL_2          (0x4U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000400 */
+#define DFSDM_FLTCR1_JEXTSEL_1          (0x2U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000200 */
+#define DFSDM_FLTCR1_JEXTSEL_0          (0x1U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000100 */
+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)                                   
+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1U << DFSDM_FLTCR1_JDMAEN_Pos)      /*!< 0x00000020 */
+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */
+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)                                   
+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1U << DFSDM_FLTCR1_JSCAN_Pos)       /*!< 0x00000010 */
+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)                                   
+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1U << DFSDM_FLTCR1_JSYNC_Pos)       /*!< 0x00000008 */
+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)                                   
+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1U << DFSDM_FLTCR1_JSWSTART_Pos)    /*!< 0x00000002 */
+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */
+#define DFSDM_FLTCR1_DFEN_Pos           (0U)                                   
+#define DFSDM_FLTCR1_DFEN_Msk           (0x1U << DFSDM_FLTCR1_DFEN_Pos)        /*!< 0x00000001 */
+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */
+
+/*****************  Bit definition for DFSDM_FLTCR2 register *******************/
+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)                                  
+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFU << DFSDM_FLTCR2_AWDCH_Pos)      /*!< 0x00FF0000 */
+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define DFSDM_FLTCR2_EXCH_Pos           (8U)                                   
+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFU << DFSDM_FLTCR2_EXCH_Pos)       /*!< 0x0000FF00 */
+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */
+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)                                   
+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1U << DFSDM_FLTCR2_CKABIE_Pos)      /*!< 0x00000040 */
+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */
+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)                                   
+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1U << DFSDM_FLTCR2_SCDIE_Pos)       /*!< 0x00000020 */
+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */
+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)                                   
+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1U << DFSDM_FLTCR2_AWDIE_Pos)       /*!< 0x00000010 */
+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */
+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)                                   
+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1U << DFSDM_FLTCR2_ROVRIE_Pos)      /*!< 0x00000008 */
+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */
+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)                                   
+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1U << DFSDM_FLTCR2_JOVRIE_Pos)      /*!< 0x00000004 */
+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */
+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)                                   
+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1U << DFSDM_FLTCR2_REOCIE_Pos)      /*!< 0x00000002 */
+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */
+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)                                   
+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1U << DFSDM_FLTCR2_JEOCIE_Pos)      /*!< 0x00000001 */
+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */
+
+/*****************  Bit definition for DFSDM_FLTISR register *******************/
+#define DFSDM_FLTISR_SCDF_Pos           (24U)                                  
+#define DFSDM_FLTISR_SCDF_Msk           (0xFFU << DFSDM_FLTISR_SCDF_Pos)       /*!< 0xFF000000 */
+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */
+#define DFSDM_FLTISR_CKABF_Pos          (16U)                                  
+#define DFSDM_FLTISR_CKABF_Msk          (0xFFU << DFSDM_FLTISR_CKABF_Pos)      /*!< 0x00FF0000 */
+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */
+#define DFSDM_FLTISR_RCIP_Pos           (14U)                                  
+#define DFSDM_FLTISR_RCIP_Msk           (0x1U << DFSDM_FLTISR_RCIP_Pos)        /*!< 0x00004000 */
+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */
+#define DFSDM_FLTISR_JCIP_Pos           (13U)                                  
+#define DFSDM_FLTISR_JCIP_Msk           (0x1U << DFSDM_FLTISR_JCIP_Pos)        /*!< 0x00002000 */
+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */
+#define DFSDM_FLTISR_AWDF_Pos           (4U)                                   
+#define DFSDM_FLTISR_AWDF_Msk           (0x1U << DFSDM_FLTISR_AWDF_Pos)        /*!< 0x00000010 */
+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */
+#define DFSDM_FLTISR_ROVRF_Pos          (3U)                                   
+#define DFSDM_FLTISR_ROVRF_Msk          (0x1U << DFSDM_FLTISR_ROVRF_Pos)       /*!< 0x00000008 */
+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */
+#define DFSDM_FLTISR_JOVRF_Pos          (2U)                                   
+#define DFSDM_FLTISR_JOVRF_Msk          (0x1U << DFSDM_FLTISR_JOVRF_Pos)       /*!< 0x00000004 */
+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */
+#define DFSDM_FLTISR_REOCF_Pos          (1U)                                   
+#define DFSDM_FLTISR_REOCF_Msk          (0x1U << DFSDM_FLTISR_REOCF_Pos)       /*!< 0x00000002 */
+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */
+#define DFSDM_FLTISR_JEOCF_Pos          (0U)                                   
+#define DFSDM_FLTISR_JEOCF_Msk          (0x1U << DFSDM_FLTISR_JEOCF_Pos)       /*!< 0x00000001 */
+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */
+
+/*****************  Bit definition for DFSDM_FLTICR register *******************/
+#define DFSDM_FLTICR_CLRSCSDF_Pos       (24U)                                  
+#define DFSDM_FLTICR_CLRSCSDF_Msk       (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos)   /*!< 0xFF000000 */
+#define DFSDM_FLTICR_CLRSCSDF           DFSDM_FLTICR_CLRSCSDF_Msk              /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)                                  
+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos)   /*!< 0x00FF0000 */
+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)                                   
+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1U << DFSDM_FLTICR_CLRROVRF_Pos)    /*!< 0x00000008 */
+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */
+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)                                   
+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos)    /*!< 0x00000004 */
+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */
+
+/****************  Bit definition for DFSDM_FLTJCHGR register ******************/
+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)                                   
+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos)     /*!< 0x000000FF */
+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */
+
+/*****************  Bit definition for DFSDM_FLTFCR register *******************/
+#define DFSDM_FLTFCR_FORD_Pos           (29U)                                  
+#define DFSDM_FLTFCR_FORD_Msk           (0x7U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0xE0000000 */
+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */
+#define DFSDM_FLTFCR_FORD_2             (0x4U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */
+#define DFSDM_FLTFCR_FORD_1             (0x2U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */
+#define DFSDM_FLTFCR_FORD_0             (0x1U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */
+#define DFSDM_FLTFCR_FOSR_Pos           (16U)                                  
+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFU << DFSDM_FLTFCR_FOSR_Pos)      /*!< 0x03FF0000 */
+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define DFSDM_FLTFCR_IOSR_Pos           (0U)                                   
+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFU << DFSDM_FLTFCR_IOSR_Pos)       /*!< 0x000000FF */
+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/***************  Bit definition for DFSDM_FLTJDATAR register *****************/
+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)                                   
+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */
+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)                                   
+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos)  /*!< 0x00000007 */
+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/***************  Bit definition for DFSDM_FLTRDATAR register *****************/
+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)                                   
+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */
+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)                                   
+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1U << DFSDM_FLTRDATAR_RPEND_Pos)    /*!< 0x00000010 */
+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */
+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)                                   
+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos)  /*!< 0x00000007 */
+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/***************  Bit definition for DFSDM_FLTAWHTR register ******************/
+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)                                   
+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */
+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)                                   
+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos)     /*!< 0x0000000F */
+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/***************  Bit definition for DFSDM_FLTAWLTR register ******************/
+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)                                   
+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWLT[23:0] Analog watchdog low threshold */
+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)                                   
+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos)     /*!< 0x0000000F */
+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/***************  Bit definition for DFSDM_FLTAWSR register *******************/
+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)                                   
+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos)     /*!< 0x0000FF00 */
+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)                                   
+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos)     /*!< 0x000000FF */
+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+/***************  Bit definition for DFSDM_FLTAWCFR register ******************/
+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)                                   
+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)                                   
+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/***************  Bit definition for DFSDM_FLTEXMAX register ******************/
+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)                                   
+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */
+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)                                   
+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos)   /*!< 0x00000007 */
+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/***************  Bit definition for DFSDM_FLTEXMIN register ******************/
+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)                                   
+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */
+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)                                   
+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos)   /*!< 0x00000007 */
+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/***************  Bit definition for DFSDM_FLTCNVTIMR register ****************/
+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)                                   
+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define DMA_ISR_GIF1_Pos       (0U)                                            
+#define DMA_ISR_GIF1_Msk       (0x1U << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
+#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos      (1U)                                            
+#define DMA_ISR_TCIF1_Msk      (0x1U << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
+#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos      (2U)                                            
+#define DMA_ISR_HTIF1_Msk      (0x1U << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
+#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos      (3U)                                            
+#define DMA_ISR_TEIF1_Msk      (0x1U << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
+#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos       (4U)                                            
+#define DMA_ISR_GIF2_Msk       (0x1U << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
+#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos      (5U)                                            
+#define DMA_ISR_TCIF2_Msk      (0x1U << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
+#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos      (6U)                                            
+#define DMA_ISR_HTIF2_Msk      (0x1U << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
+#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos      (7U)                                            
+#define DMA_ISR_TEIF2_Msk      (0x1U << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
+#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos       (8U)                                            
+#define DMA_ISR_GIF3_Msk       (0x1U << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
+#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos      (9U)                                            
+#define DMA_ISR_TCIF3_Msk      (0x1U << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
+#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos      (10U)                                           
+#define DMA_ISR_HTIF3_Msk      (0x1U << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
+#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos      (11U)                                           
+#define DMA_ISR_TEIF3_Msk      (0x1U << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
+#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos       (12U)                                           
+#define DMA_ISR_GIF4_Msk       (0x1U << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
+#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos      (13U)                                           
+#define DMA_ISR_TCIF4_Msk      (0x1U << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
+#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos      (14U)                                           
+#define DMA_ISR_HTIF4_Msk      (0x1U << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
+#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos      (15U)                                           
+#define DMA_ISR_TEIF4_Msk      (0x1U << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
+#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos       (16U)                                           
+#define DMA_ISR_GIF5_Msk       (0x1U << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
+#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos      (17U)                                           
+#define DMA_ISR_TCIF5_Msk      (0x1U << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
+#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos      (18U)                                           
+#define DMA_ISR_HTIF5_Msk      (0x1U << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
+#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos      (19U)                                           
+#define DMA_ISR_TEIF5_Msk      (0x1U << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
+#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos       (20U)                                           
+#define DMA_ISR_GIF6_Msk       (0x1U << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
+#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos      (21U)                                           
+#define DMA_ISR_TCIF6_Msk      (0x1U << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
+#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos      (22U)                                           
+#define DMA_ISR_HTIF6_Msk      (0x1U << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
+#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos      (23U)                                           
+#define DMA_ISR_TEIF6_Msk      (0x1U << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
+#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos       (24U)                                           
+#define DMA_ISR_GIF7_Msk       (0x1U << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
+#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos      (25U)                                           
+#define DMA_ISR_TCIF7_Msk      (0x1U << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
+#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos      (26U)                                           
+#define DMA_ISR_HTIF7_Msk      (0x1U << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
+#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos      (27U)                                           
+#define DMA_ISR_TEIF7_Msk      (0x1U << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
+#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define DMA_IFCR_CGIF1_Pos     (0U)                                            
+#define DMA_IFCR_CGIF1_Msk     (0x1U << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */
+#define DMA_IFCR_CTCIF1_Pos    (1U)                                            
+#define DMA_IFCR_CTCIF1_Msk    (0x1U << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos    (2U)                                            
+#define DMA_IFCR_CHTIF1_Msk    (0x1U << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos    (3U)                                            
+#define DMA_IFCR_CTEIF1_Msk    (0x1U << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos     (4U)                                            
+#define DMA_IFCR_CGIF2_Msk     (0x1U << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos    (5U)                                            
+#define DMA_IFCR_CTCIF2_Msk    (0x1U << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos    (6U)                                            
+#define DMA_IFCR_CHTIF2_Msk    (0x1U << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos    (7U)                                            
+#define DMA_IFCR_CTEIF2_Msk    (0x1U << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos     (8U)                                            
+#define DMA_IFCR_CGIF3_Msk     (0x1U << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos    (9U)                                            
+#define DMA_IFCR_CTCIF3_Msk    (0x1U << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos    (10U)                                           
+#define DMA_IFCR_CHTIF3_Msk    (0x1U << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos    (11U)                                           
+#define DMA_IFCR_CTEIF3_Msk    (0x1U << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos     (12U)                                           
+#define DMA_IFCR_CGIF4_Msk     (0x1U << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos    (13U)                                           
+#define DMA_IFCR_CTCIF4_Msk    (0x1U << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos    (14U)                                           
+#define DMA_IFCR_CHTIF4_Msk    (0x1U << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos    (15U)                                           
+#define DMA_IFCR_CTEIF4_Msk    (0x1U << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos     (16U)                                           
+#define DMA_IFCR_CGIF5_Msk     (0x1U << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos    (17U)                                           
+#define DMA_IFCR_CTCIF5_Msk    (0x1U << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos    (18U)                                           
+#define DMA_IFCR_CHTIF5_Msk    (0x1U << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos    (19U)                                           
+#define DMA_IFCR_CTEIF5_Msk    (0x1U << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos     (20U)                                           
+#define DMA_IFCR_CGIF6_Msk     (0x1U << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos    (21U)                                           
+#define DMA_IFCR_CTCIF6_Msk    (0x1U << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos    (22U)                                           
+#define DMA_IFCR_CHTIF6_Msk    (0x1U << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos    (23U)                                           
+#define DMA_IFCR_CTEIF6_Msk    (0x1U << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos     (24U)                                           
+#define DMA_IFCR_CGIF7_Msk     (0x1U << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos    (25U)                                           
+#define DMA_IFCR_CTCIF7_Msk    (0x1U << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos    (26U)                                           
+#define DMA_IFCR_CHTIF7_Msk    (0x1U << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos    (27U)                                           
+#define DMA_IFCR_CTEIF7_Msk    (0x1U << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define DMA_CCR_EN_Pos         (0U)                                            
+#define DMA_CCR_EN_Msk         (0x1U << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
+#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
+#define DMA_CCR_TCIE_Pos       (1U)                                            
+#define DMA_CCR_TCIE_Msk       (0x1U << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
+#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
+#define DMA_CCR_HTIE_Pos       (2U)                                            
+#define DMA_CCR_HTIE_Msk       (0x1U << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
+#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
+#define DMA_CCR_TEIE_Pos       (3U)                                            
+#define DMA_CCR_TEIE_Msk       (0x1U << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
+#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
+#define DMA_CCR_DIR_Pos        (4U)                                            
+#define DMA_CCR_DIR_Msk        (0x1U << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
+#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
+#define DMA_CCR_CIRC_Pos       (5U)                                            
+#define DMA_CCR_CIRC_Msk       (0x1U << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
+#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
+#define DMA_CCR_PINC_Pos       (6U)                                            
+#define DMA_CCR_PINC_Msk       (0x1U << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
+#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
+#define DMA_CCR_MINC_Pos       (7U)                                            
+#define DMA_CCR_MINC_Msk       (0x1U << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
+#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
+
+#define DMA_CCR_PSIZE_Pos      (8U)                                            
+#define DMA_CCR_PSIZE_Msk      (0x3U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
+#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define DMA_CCR_PSIZE_0        (0x1U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1        (0x2U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos      (10U)                                           
+#define DMA_CCR_MSIZE_Msk      (0x3U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
+#define DMA_CCR_MSIZE_0        (0x1U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1        (0x2U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos         (12U)                                           
+#define DMA_CCR_PL_Msk         (0x3U << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
+#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0           (0x1U << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
+#define DMA_CCR_PL_1           (0x2U << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos    (14U)                                           
+#define DMA_CCR_MEM2MEM_Msk    (0x1U << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define DMA_CNDTR_NDT_Pos      (0U)                                            
+#define DMA_CNDTR_NDT_Msk      (0xFFFFU << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define DMA_CPAR_PA_Pos        (0U)                                            
+#define DMA_CPAR_PA_Msk        (0xFFFFFFFFU << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define DMA_CMAR_MA_Pos        (0U)                                            
+#define DMA_CMAR_MA_Msk        (0xFFFFFFFFU << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
+
+
+/*******************  Bit definition for DMA_CSELR register  *******************/
+#define DMA_CSELR_C1S_Pos      (0U)                                            
+#define DMA_CSELR_C1S_Msk      (0xFU << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
+#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos      (4U)                                            
+#define DMA_CSELR_C2S_Msk      (0xFU << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
+#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos      (8U)                                            
+#define DMA_CSELR_C3S_Msk      (0xFU << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
+#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos      (12U)                                           
+#define DMA_CSELR_C4S_Msk      (0xFU << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
+#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos      (16U)                                           
+#define DMA_CSELR_C5S_Msk      (0xFU << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
+#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos      (20U)                                           
+#define DMA_CSELR_C6S_Msk      (0xFU << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
+#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos      (24U)                                           
+#define DMA_CSELR_C7S_Msk      (0xFU << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
+#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         AHB Master DMA2D Controller (DMA2D)                */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DMA2D_CR register  ******************/
+
+#define DMA2D_CR_START_Pos         (0U)                                        
+#define DMA2D_CR_START_Msk         (0x1U << DMA2D_CR_START_Pos)                /*!< 0x00000001 */
+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer */
+#define DMA2D_CR_SUSP_Pos          (1U)                                        
+#define DMA2D_CR_SUSP_Msk          (0x1U << DMA2D_CR_SUSP_Pos)                 /*!< 0x00000002 */
+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer */
+#define DMA2D_CR_ABORT_Pos         (2U)                                        
+#define DMA2D_CR_ABORT_Msk         (0x1U << DMA2D_CR_ABORT_Pos)                /*!< 0x00000004 */
+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer */
+#define DMA2D_CR_TEIE_Pos          (8U)                                        
+#define DMA2D_CR_TEIE_Msk          (0x1U << DMA2D_CR_TEIE_Pos)                 /*!< 0x00000100 */
+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE_Pos          (9U)                                        
+#define DMA2D_CR_TCIE_Msk          (0x1U << DMA2D_CR_TCIE_Pos)                 /*!< 0x00000200 */
+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE_Pos          (10U)                                       
+#define DMA2D_CR_TWIE_Msk          (0x1U << DMA2D_CR_TWIE_Pos)                 /*!< 0x00000400 */
+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE_Pos         (11U)                                       
+#define DMA2D_CR_CAEIE_Msk         (0x1U << DMA2D_CR_CAEIE_Pos)                /*!< 0x00000800 */
+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE_Pos         (12U)                                       
+#define DMA2D_CR_CTCIE_Msk         (0x1U << DMA2D_CR_CTCIE_Pos)                /*!< 0x00001000 */
+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE_Pos          (13U)                                       
+#define DMA2D_CR_CEIE_Msk          (0x1U << DMA2D_CR_CEIE_Pos)                 /*!< 0x00002000 */
+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE_Pos          (16U)                                       
+#define DMA2D_CR_MODE_Msk          (0x3U << DMA2D_CR_MODE_Pos)                 /*!< 0x00030000 */
+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[1:0] */
+#define DMA2D_CR_MODE_0            (0x1U << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */
+#define DMA2D_CR_MODE_1            (0x2U << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */
+
+/********************  Bit definition for DMA2D_ISR register  *****************/
+
+#define DMA2D_ISR_TEIF_Pos         (0U)                                        
+#define DMA2D_ISR_TEIF_Msk         (0x1U << DMA2D_ISR_TEIF_Pos)                /*!< 0x00000001 */
+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF_Pos         (1U)                                        
+#define DMA2D_ISR_TCIF_Msk         (0x1U << DMA2D_ISR_TCIF_Pos)                /*!< 0x00000002 */
+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF_Pos         (2U)                                        
+#define DMA2D_ISR_TWIF_Msk         (0x1U << DMA2D_ISR_TWIF_Pos)                /*!< 0x00000004 */
+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF_Pos        (3U)                                        
+#define DMA2D_ISR_CAEIF_Msk        (0x1U << DMA2D_ISR_CAEIF_Pos)               /*!< 0x00000008 */
+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF_Pos        (4U)                                        
+#define DMA2D_ISR_CTCIF_Msk        (0x1U << DMA2D_ISR_CTCIF_Pos)               /*!< 0x00000010 */
+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF_Pos         (5U)                                        
+#define DMA2D_ISR_CEIF_Msk         (0x1U << DMA2D_ISR_CEIF_Pos)                /*!< 0x00000020 */
+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag */
+
+/********************  Bit definition for DMA2D_IFCR register  ****************/
+
+#define DMA2D_IFCR_CTEIF_Pos       (0U)                                        
+#define DMA2D_IFCR_CTEIF_Msk       (0x1U << DMA2D_IFCR_CTEIF_Pos)              /*!< 0x00000001 */
+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag */
+#define DMA2D_IFCR_CTCIF_Pos       (1U)                                        
+#define DMA2D_IFCR_CTCIF_Msk       (0x1U << DMA2D_IFCR_CTCIF_Pos)              /*!< 0x00000002 */
+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CTWIF_Pos       (2U)                                        
+#define DMA2D_IFCR_CTWIF_Msk       (0x1U << DMA2D_IFCR_CTWIF_Pos)              /*!< 0x00000004 */
+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag */
+#define DMA2D_IFCR_CAECIF_Pos      (3U)                                        
+#define DMA2D_IFCR_CAECIF_Msk      (0x1U << DMA2D_IFCR_CAECIF_Pos)             /*!< 0x00000008 */
+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag */
+#define DMA2D_IFCR_CCTCIF_Pos      (4U)                                        
+#define DMA2D_IFCR_CCTCIF_Msk      (0x1U << DMA2D_IFCR_CCTCIF_Pos)             /*!< 0x00000010 */
+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF_Pos       (5U)                                        
+#define DMA2D_IFCR_CCEIF_Msk       (0x1U << DMA2D_IFCR_CCEIF_Pos)              /*!< 0x00000020 */
+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag */
+
+/********************  Bit definition for DMA2D_FGMAR register  ***************/
+
+#define DMA2D_FGMAR_MA_Pos         (0U)                                        
+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos)         /*!< 0xFFFFFFFF */
+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_FGOR register  ****************/
+
+#define DMA2D_FGOR_LO_Pos          (0U)                                        
+#define DMA2D_FGOR_LO_Msk          (0x3FFFU << DMA2D_FGOR_LO_Pos)              /*!< 0x00003FFF */
+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_BGMAR register  ***************/
+
+#define DMA2D_BGMAR_MA_Pos         (0U)                                        
+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos)         /*!< 0xFFFFFFFF */
+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGOR register  ****************/
+
+#define DMA2D_BGOR_LO_Pos          (0U)                                        
+#define DMA2D_BGOR_LO_Msk          (0x3FFFU << DMA2D_BGOR_LO_Pos)              /*!< 0x00003FFF */
+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_FGPFCCR register  *************/
+
+#define DMA2D_FGPFCCR_CM_Pos       (0U)                                        
+#define DMA2D_FGPFCCR_CM_Msk       (0xFU << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x0000000F */
+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0         (0x1U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_FGPFCCR_CM_1         (0x2U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_FGPFCCR_CM_2         (0x4U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_FGPFCCR_CM_3         (0x8U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */
+#define DMA2D_FGPFCCR_CCM_Pos      (4U)                                        
+#define DMA2D_FGPFCCR_CCM_Msk      (0x1U << DMA2D_FGPFCCR_CCM_Pos)             /*!< 0x00000010 */
+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START_Pos    (5U)                                        
+#define DMA2D_FGPFCCR_START_Msk    (0x1U << DMA2D_FGPFCCR_START_Pos)           /*!< 0x00000020 */
+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_FGPFCCR_CS_Pos       (8U)                                        
+#define DMA2D_FGPFCCR_CS_Msk       (0xFFU << DMA2D_FGPFCCR_CS_Pos)             /*!< 0x0000FF00 */
+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM_Pos       (16U)                                       
+#define DMA2D_FGPFCCR_AM_Msk       (0x3U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00030000 */
+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0         (0x1U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */
+#define DMA2D_FGPFCCR_AM_1         (0x2U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */
+#define DMA2D_FGPFCCR_AI_Pos       (20U)                                       
+#define DMA2D_FGPFCCR_AI_Msk       (0x1U << DMA2D_FGPFCCR_AI_Pos)              /*!< 0x00100000 */
+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Alpha Inverted */
+#define DMA2D_FGPFCCR_RBS_Pos      (21U)                                       
+#define DMA2D_FGPFCCR_RBS_Msk      (0x1U << DMA2D_FGPFCCR_RBS_Pos)             /*!< 0x00200000 */
+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Red Blue Swap */
+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)                                       
+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */
+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_FGCOLR register  **************/
+
+#define DMA2D_FGCOLR_BLUE_Pos      (0U)                                        
+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFU << DMA2D_FGCOLR_BLUE_Pos)            /*!< 0x000000FF */
+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN_Pos     (8U)                                        
+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFU << DMA2D_FGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */
+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Green Value */
+#define DMA2D_FGCOLR_RED_Pos       (16U)                                       
+#define DMA2D_FGCOLR_RED_Msk       (0xFFU << DMA2D_FGCOLR_RED_Pos)             /*!< 0x00FF0000 */
+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Red Value */   
+
+/********************  Bit definition for DMA2D_BGPFCCR register  *************/
+
+#define DMA2D_BGPFCCR_CM_Pos       (0U)                                        
+#define DMA2D_BGPFCCR_CM_Msk       (0xFU << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x0000000F */
+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0         (0x1U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_BGPFCCR_CM_1         (0x2U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_BGPFCCR_CM_2         (0x4U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_BGPFCCR_CM_3         (0x8U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */
+#define DMA2D_BGPFCCR_CCM_Pos      (4U)                                        
+#define DMA2D_BGPFCCR_CCM_Msk      (0x1U << DMA2D_BGPFCCR_CCM_Pos)             /*!< 0x00000010 */
+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START_Pos    (5U)                                        
+#define DMA2D_BGPFCCR_START_Msk    (0x1U << DMA2D_BGPFCCR_START_Pos)           /*!< 0x00000020 */
+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_BGPFCCR_CS_Pos       (8U)                                        
+#define DMA2D_BGPFCCR_CS_Msk       (0xFFU << DMA2D_BGPFCCR_CS_Pos)             /*!< 0x0000FF00 */
+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM_Pos       (16U)                                       
+#define DMA2D_BGPFCCR_AM_Msk       (0x3U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00030000 */
+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0         (0x1U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */
+#define DMA2D_BGPFCCR_AM_1         (0x2U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */
+#define DMA2D_BGPFCCR_AI_Pos       (20U)                                       
+#define DMA2D_BGPFCCR_AI_Msk       (0x1U << DMA2D_BGPFCCR_AI_Pos)              /*!< 0x00100000 */
+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< Alpha Inverted */
+#define DMA2D_BGPFCCR_RBS_Pos      (21U)                                       
+#define DMA2D_BGPFCCR_RBS_Msk      (0x1U << DMA2D_BGPFCCR_RBS_Pos)             /*!< 0x00200000 */
+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Red Blue Swap */
+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)                                       
+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */
+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_BGCOLR register  **************/
+
+#define DMA2D_BGCOLR_BLUE_Pos      (0U)                                        
+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFU << DMA2D_BGCOLR_BLUE_Pos)            /*!< 0x000000FF */
+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN_Pos     (8U)                                        
+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFU << DMA2D_BGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */
+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Green Value */
+#define DMA2D_BGCOLR_RED_Pos       (16U)                                       
+#define DMA2D_BGCOLR_RED_Msk       (0xFFU << DMA2D_BGCOLR_RED_Pos)             /*!< 0x00FF0000 */
+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Red Value */
+
+/********************  Bit definition for DMA2D_FGCMAR register  **************/
+
+#define DMA2D_FGCMAR_MA_Pos        (0U)                                        
+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGCMAR register  **************/
+
+#define DMA2D_BGCMAR_MA_Pos        (0U)                                        
+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OPFCCR register  **************/
+
+#define DMA2D_OPFCCR_CM_Pos        (0U)                                        
+#define DMA2D_OPFCCR_CM_Msk        (0x7U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000007 */
+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0          (0x1U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000001 */
+#define DMA2D_OPFCCR_CM_1          (0x2U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000002 */
+#define DMA2D_OPFCCR_CM_2          (0x4U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000004 */
+#define DMA2D_OPFCCR_AI_Pos        (20U)                                       
+#define DMA2D_OPFCCR_AI_Msk        (0x1U << DMA2D_OPFCCR_AI_Pos)               /*!< 0x00100000 */
+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Alpha Inverted */
+#define DMA2D_OPFCCR_RBS_Pos       (21U)                                       
+#define DMA2D_OPFCCR_RBS_Msk       (0x1U << DMA2D_OPFCCR_RBS_Pos)              /*!< 0x00200000 */
+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Red Blue Swap */
+
+/********************  Bit definition for DMA2D_OCOLR register  ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1         (0x000000FFU)                               /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_1        (0x0000FF00U)                               /*!< Green Value  */
+#define DMA2D_OCOLR_RED_1          (0x00FF0000U)                               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1        (0xFF000000U)                               /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2         (0x0000001FU)                               /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_2        (0x000007E0U)                               /*!< Green Value  */
+#define DMA2D_OCOLR_RED_2          (0x0000F800U)                               /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3         (0x0000001FU)                               /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_3        (0x000003E0U)                               /*!< Green Value  */
+#define DMA2D_OCOLR_RED_3          (0x00007C00U)                               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3        (0x00008000U)                               /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4         (0x0000000FU)                               /*!< Blue Value */
+#define DMA2D_OCOLR_GREEN_4        (0x000000F0U)                               /*!< Green Value  */
+#define DMA2D_OCOLR_RED_4          (0x00000F00U)                               /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4        (0x0000F000U)                               /*!< Alpha Channel Value */
+
+/********************  Bit definition for DMA2D_OMAR register  ****************/
+
+#define DMA2D_OMAR_MA_Pos          (0U)                                        
+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos)          /*!< 0xFFFFFFFF */
+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OOR register  *****************/
+
+#define DMA2D_OOR_LO_Pos           (0U)                                        
+#define DMA2D_OOR_LO_Msk           (0x3FFFU << DMA2D_OOR_LO_Pos)               /*!< 0x00003FFF */
+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_NLR register  *****************/
+
+#define DMA2D_NLR_NL_Pos           (0U)                                        
+#define DMA2D_NLR_NL_Msk           (0xFFFFU << DMA2D_NLR_NL_Pos)               /*!< 0x0000FFFF */
+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
+#define DMA2D_NLR_PL_Pos           (16U)                                       
+#define DMA2D_NLR_PL_Msk           (0x3FFFU << DMA2D_NLR_PL_Pos)               /*!< 0x3FFF0000 */
+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */
+
+/********************  Bit definition for DMA2D_LWR register  *****************/
+
+#define DMA2D_LWR_LW_Pos           (0U)                                        
+#define DMA2D_LWR_LW_Msk           (0xFFFFU << DMA2D_LWR_LW_Pos)               /*!< 0x0000FFFF */
+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */
+
+/********************  Bit definition for DMA2D_AMTCR register  ***************/
+
+#define DMA2D_AMTCR_EN_Pos         (0U)                                        
+#define DMA2D_AMTCR_EN_Msk         (0x1U << DMA2D_AMTCR_EN_Pos)                /*!< 0x00000001 */
+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
+#define DMA2D_AMTCR_DT_Pos         (8U)                                        
+#define DMA2D_AMTCR_DT_Msk         (0xFFU << DMA2D_AMTCR_DT_Pos)               /*!< 0x0000FF00 */
+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
+
+
+/********************  Bit definition for DMA2D_FGCLUT register  **************/
+                                                                     
+/********************  Bit definition for DMA2D_BGCLUT register  **************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR1 register  ******************/
+#define EXTI_IMR1_IM0_Pos        (0U)                                          
+#define EXTI_IMR1_IM0_Msk        (0x1U << EXTI_IMR1_IM0_Pos)                   /*!< 0x00000001 */
+#define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos        (1U)                                          
+#define EXTI_IMR1_IM1_Msk        (0x1U << EXTI_IMR1_IM1_Pos)                   /*!< 0x00000002 */
+#define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos        (2U)                                          
+#define EXTI_IMR1_IM2_Msk        (0x1U << EXTI_IMR1_IM2_Pos)                   /*!< 0x00000004 */
+#define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos        (3U)                                          
+#define EXTI_IMR1_IM3_Msk        (0x1U << EXTI_IMR1_IM3_Pos)                   /*!< 0x00000008 */
+#define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos        (4U)                                          
+#define EXTI_IMR1_IM4_Msk        (0x1U << EXTI_IMR1_IM4_Pos)                   /*!< 0x00000010 */
+#define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos        (5U)                                          
+#define EXTI_IMR1_IM5_Msk        (0x1U << EXTI_IMR1_IM5_Pos)                   /*!< 0x00000020 */
+#define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos        (6U)                                          
+#define EXTI_IMR1_IM6_Msk        (0x1U << EXTI_IMR1_IM6_Pos)                   /*!< 0x00000040 */
+#define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos        (7U)                                          
+#define EXTI_IMR1_IM7_Msk        (0x1U << EXTI_IMR1_IM7_Pos)                   /*!< 0x00000080 */
+#define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos        (8U)                                          
+#define EXTI_IMR1_IM8_Msk        (0x1U << EXTI_IMR1_IM8_Pos)                   /*!< 0x00000100 */
+#define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos        (9U)                                          
+#define EXTI_IMR1_IM9_Msk        (0x1U << EXTI_IMR1_IM9_Pos)                   /*!< 0x00000200 */
+#define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos       (10U)                                         
+#define EXTI_IMR1_IM10_Msk       (0x1U << EXTI_IMR1_IM10_Pos)                  /*!< 0x00000400 */
+#define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos       (11U)                                         
+#define EXTI_IMR1_IM11_Msk       (0x1U << EXTI_IMR1_IM11_Pos)                  /*!< 0x00000800 */
+#define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos       (12U)                                         
+#define EXTI_IMR1_IM12_Msk       (0x1U << EXTI_IMR1_IM12_Pos)                  /*!< 0x00001000 */
+#define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos       (13U)                                         
+#define EXTI_IMR1_IM13_Msk       (0x1U << EXTI_IMR1_IM13_Pos)                  /*!< 0x00002000 */
+#define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos       (14U)                                         
+#define EXTI_IMR1_IM14_Msk       (0x1U << EXTI_IMR1_IM14_Pos)                  /*!< 0x00004000 */
+#define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos       (15U)                                         
+#define EXTI_IMR1_IM15_Msk       (0x1U << EXTI_IMR1_IM15_Pos)                  /*!< 0x00008000 */
+#define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM16_Pos       (16U)                                         
+#define EXTI_IMR1_IM16_Msk       (0x1U << EXTI_IMR1_IM16_Pos)                  /*!< 0x00010000 */
+#define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR1_IM17_Pos       (17U)                                         
+#define EXTI_IMR1_IM17_Msk       (0x1U << EXTI_IMR1_IM17_Pos)                  /*!< 0x00020000 */
+#define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos       (18U)                                         
+#define EXTI_IMR1_IM18_Msk       (0x1U << EXTI_IMR1_IM18_Pos)                  /*!< 0x00040000 */
+#define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos       (19U)                                         
+#define EXTI_IMR1_IM19_Msk       (0x1U << EXTI_IMR1_IM19_Pos)                  /*!< 0x00080000 */
+#define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos       (20U)                                         
+#define EXTI_IMR1_IM20_Msk       (0x1U << EXTI_IMR1_IM20_Pos)                  /*!< 0x00100000 */
+#define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos       (21U)                                         
+#define EXTI_IMR1_IM21_Msk       (0x1U << EXTI_IMR1_IM21_Pos)                  /*!< 0x00200000 */
+#define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos       (22U)                                         
+#define EXTI_IMR1_IM22_Msk       (0x1U << EXTI_IMR1_IM22_Pos)                  /*!< 0x00400000 */
+#define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos       (23U)                                         
+#define EXTI_IMR1_IM23_Msk       (0x1U << EXTI_IMR1_IM23_Pos)                  /*!< 0x00800000 */
+#define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos       (24U)                                         
+#define EXTI_IMR1_IM24_Msk       (0x1U << EXTI_IMR1_IM24_Pos)                  /*!< 0x01000000 */
+#define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos       (25U)                                         
+#define EXTI_IMR1_IM25_Msk       (0x1U << EXTI_IMR1_IM25_Pos)                  /*!< 0x02000000 */
+#define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos       (26U)                                         
+#define EXTI_IMR1_IM26_Msk       (0x1U << EXTI_IMR1_IM26_Pos)                  /*!< 0x04000000 */
+#define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos       (27U)                                         
+#define EXTI_IMR1_IM27_Msk       (0x1U << EXTI_IMR1_IM27_Pos)                  /*!< 0x08000000 */
+#define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos       (28U)                                         
+#define EXTI_IMR1_IM28_Msk       (0x1U << EXTI_IMR1_IM28_Pos)                  /*!< 0x10000000 */
+#define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM29_Pos       (29U)                                         
+#define EXTI_IMR1_IM29_Msk       (0x1U << EXTI_IMR1_IM29_Pos)                  /*!< 0x20000000 */
+#define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR1_IM30_Pos       (30U)                                         
+#define EXTI_IMR1_IM30_Msk       (0x1U << EXTI_IMR1_IM30_Pos)                  /*!< 0x40000000 */
+#define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR1_IM31_Pos       (31U)                                         
+#define EXTI_IMR1_IM31_Msk       (0x1U << EXTI_IMR1_IM31_Pos)                  /*!< 0x80000000 */
+#define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< Interrupt Mask on line 31 */
+#define EXTI_IMR1_IM_Pos         (0U)                                          
+#define EXTI_IMR1_IM_Msk         (0xFFFFFFFFU << EXTI_IMR1_IM_Pos)             /*!< 0xFFFFFFFF */
+#define EXTI_IMR1_IM             EXTI_IMR1_IM_Msk                              /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR1 register  ******************/
+#define EXTI_EMR1_EM0_Pos        (0U)                                          
+#define EXTI_EMR1_EM0_Msk        (0x1U << EXTI_EMR1_EM0_Pos)                   /*!< 0x00000001 */
+#define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos        (1U)                                          
+#define EXTI_EMR1_EM1_Msk        (0x1U << EXTI_EMR1_EM1_Pos)                   /*!< 0x00000002 */
+#define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos        (2U)                                          
+#define EXTI_EMR1_EM2_Msk        (0x1U << EXTI_EMR1_EM2_Pos)                   /*!< 0x00000004 */
+#define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos        (3U)                                          
+#define EXTI_EMR1_EM3_Msk        (0x1U << EXTI_EMR1_EM3_Pos)                   /*!< 0x00000008 */
+#define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos        (4U)                                          
+#define EXTI_EMR1_EM4_Msk        (0x1U << EXTI_EMR1_EM4_Pos)                   /*!< 0x00000010 */
+#define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos        (5U)                                          
+#define EXTI_EMR1_EM5_Msk        (0x1U << EXTI_EMR1_EM5_Pos)                   /*!< 0x00000020 */
+#define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos        (6U)                                          
+#define EXTI_EMR1_EM6_Msk        (0x1U << EXTI_EMR1_EM6_Pos)                   /*!< 0x00000040 */
+#define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos        (7U)                                          
+#define EXTI_EMR1_EM7_Msk        (0x1U << EXTI_EMR1_EM7_Pos)                   /*!< 0x00000080 */
+#define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos        (8U)                                          
+#define EXTI_EMR1_EM8_Msk        (0x1U << EXTI_EMR1_EM8_Pos)                   /*!< 0x00000100 */
+#define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos        (9U)                                          
+#define EXTI_EMR1_EM9_Msk        (0x1U << EXTI_EMR1_EM9_Pos)                   /*!< 0x00000200 */
+#define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos       (10U)                                         
+#define EXTI_EMR1_EM10_Msk       (0x1U << EXTI_EMR1_EM10_Pos)                  /*!< 0x00000400 */
+#define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos       (11U)                                         
+#define EXTI_EMR1_EM11_Msk       (0x1U << EXTI_EMR1_EM11_Pos)                  /*!< 0x00000800 */
+#define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos       (12U)                                         
+#define EXTI_EMR1_EM12_Msk       (0x1U << EXTI_EMR1_EM12_Pos)                  /*!< 0x00001000 */
+#define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos       (13U)                                         
+#define EXTI_EMR1_EM13_Msk       (0x1U << EXTI_EMR1_EM13_Pos)                  /*!< 0x00002000 */
+#define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos       (14U)                                         
+#define EXTI_EMR1_EM14_Msk       (0x1U << EXTI_EMR1_EM14_Pos)                  /*!< 0x00004000 */
+#define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos       (15U)                                         
+#define EXTI_EMR1_EM15_Msk       (0x1U << EXTI_EMR1_EM15_Pos)                  /*!< 0x00008000 */
+#define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM16_Pos       (16U)                                         
+#define EXTI_EMR1_EM16_Msk       (0x1U << EXTI_EMR1_EM16_Pos)                  /*!< 0x00010000 */
+#define EXTI_EMR1_EM16           EXTI_EMR1_EM16_Msk                            /*!< Event Mask on line 16 */
+#define EXTI_EMR1_EM17_Pos       (17U)                                         
+#define EXTI_EMR1_EM17_Msk       (0x1U << EXTI_EMR1_EM17_Pos)                  /*!< 0x00020000 */
+#define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos       (18U)                                         
+#define EXTI_EMR1_EM18_Msk       (0x1U << EXTI_EMR1_EM18_Pos)                  /*!< 0x00040000 */
+#define EXTI_EMR1_EM18           EXTI_EMR1_EM18_Msk                            /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM19_Pos       (19U)                                         
+#define EXTI_EMR1_EM19_Msk       (0x1U << EXTI_EMR1_EM19_Pos)                  /*!< 0x00080000 */
+#define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< Event Mask on line 19 */
+#define EXTI_EMR1_EM20_Pos       (20U)                                         
+#define EXTI_EMR1_EM20_Msk       (0x1U << EXTI_EMR1_EM20_Pos)                  /*!< 0x00100000 */
+#define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos       (21U)                                         
+#define EXTI_EMR1_EM21_Msk       (0x1U << EXTI_EMR1_EM21_Pos)                  /*!< 0x00200000 */
+#define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos       (22U)                                         
+#define EXTI_EMR1_EM22_Msk       (0x1U << EXTI_EMR1_EM22_Pos)                  /*!< 0x00400000 */
+#define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos       (23U)                                         
+#define EXTI_EMR1_EM23_Msk       (0x1U << EXTI_EMR1_EM23_Pos)                  /*!< 0x00800000 */
+#define EXTI_EMR1_EM23           EXTI_EMR1_EM23_Msk                            /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos       (24U)                                         
+#define EXTI_EMR1_EM24_Msk       (0x1U << EXTI_EMR1_EM24_Pos)                  /*!< 0x01000000 */
+#define EXTI_EMR1_EM24           EXTI_EMR1_EM24_Msk                            /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos       (25U)                                         
+#define EXTI_EMR1_EM25_Msk       (0x1U << EXTI_EMR1_EM25_Pos)                  /*!< 0x02000000 */
+#define EXTI_EMR1_EM25           EXTI_EMR1_EM25_Msk                            /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos       (26U)                                         
+#define EXTI_EMR1_EM26_Msk       (0x1U << EXTI_EMR1_EM26_Pos)                  /*!< 0x04000000 */
+#define EXTI_EMR1_EM26           EXTI_EMR1_EM26_Msk                            /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos       (27U)                                         
+#define EXTI_EMR1_EM27_Msk       (0x1U << EXTI_EMR1_EM27_Pos)                  /*!< 0x08000000 */
+#define EXTI_EMR1_EM27           EXTI_EMR1_EM27_Msk                            /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos       (28U)                                         
+#define EXTI_EMR1_EM28_Msk       (0x1U << EXTI_EMR1_EM28_Pos)                  /*!< 0x10000000 */
+#define EXTI_EMR1_EM28           EXTI_EMR1_EM28_Msk                            /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM29_Pos       (29U)                                         
+#define EXTI_EMR1_EM29_Msk       (0x1U << EXTI_EMR1_EM29_Pos)                  /*!< 0x20000000 */
+#define EXTI_EMR1_EM29           EXTI_EMR1_EM29_Msk                            /*!< Event Mask on line 29 */
+#define EXTI_EMR1_EM30_Pos       (30U)                                         
+#define EXTI_EMR1_EM30_Msk       (0x1U << EXTI_EMR1_EM30_Pos)                  /*!< 0x40000000 */
+#define EXTI_EMR1_EM30           EXTI_EMR1_EM30_Msk                            /*!< Event Mask on line 30 */
+#define EXTI_EMR1_EM31_Pos       (31U)                                         
+#define EXTI_EMR1_EM31_Msk       (0x1U << EXTI_EMR1_EM31_Pos)                  /*!< 0x80000000 */
+#define EXTI_EMR1_EM31           EXTI_EMR1_EM31_Msk                            /*!< Event Mask on line 31 */
+
+/******************  Bit definition for EXTI_RTSR1 register  ******************/
+#define EXTI_RTSR1_RT0_Pos       (0U)                                          
+#define EXTI_RTSR1_RT0_Msk       (0x1U << EXTI_RTSR1_RT0_Pos)                  /*!< 0x00000001 */
+#define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR1_RT1_Pos       (1U)                                          
+#define EXTI_RTSR1_RT1_Msk       (0x1U << EXTI_RTSR1_RT1_Pos)                  /*!< 0x00000002 */
+#define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR1_RT2_Pos       (2U)                                          
+#define EXTI_RTSR1_RT2_Msk       (0x1U << EXTI_RTSR1_RT2_Pos)                  /*!< 0x00000004 */
+#define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR1_RT3_Pos       (3U)                                          
+#define EXTI_RTSR1_RT3_Msk       (0x1U << EXTI_RTSR1_RT3_Pos)                  /*!< 0x00000008 */
+#define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR1_RT4_Pos       (4U)                                          
+#define EXTI_RTSR1_RT4_Msk       (0x1U << EXTI_RTSR1_RT4_Pos)                  /*!< 0x00000010 */
+#define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR1_RT5_Pos       (5U)                                          
+#define EXTI_RTSR1_RT5_Msk       (0x1U << EXTI_RTSR1_RT5_Pos)                  /*!< 0x00000020 */
+#define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR1_RT6_Pos       (6U)                                          
+#define EXTI_RTSR1_RT6_Msk       (0x1U << EXTI_RTSR1_RT6_Pos)                  /*!< 0x00000040 */
+#define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR1_RT7_Pos       (7U)                                          
+#define EXTI_RTSR1_RT7_Msk       (0x1U << EXTI_RTSR1_RT7_Pos)                  /*!< 0x00000080 */
+#define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR1_RT8_Pos       (8U)                                          
+#define EXTI_RTSR1_RT8_Msk       (0x1U << EXTI_RTSR1_RT8_Pos)                  /*!< 0x00000100 */
+#define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR1_RT9_Pos       (9U)                                          
+#define EXTI_RTSR1_RT9_Msk       (0x1U << EXTI_RTSR1_RT9_Pos)                  /*!< 0x00000200 */
+#define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR1_RT10_Pos      (10U)                                         
+#define EXTI_RTSR1_RT10_Msk      (0x1U << EXTI_RTSR1_RT10_Pos)                 /*!< 0x00000400 */
+#define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR1_RT11_Pos      (11U)                                         
+#define EXTI_RTSR1_RT11_Msk      (0x1U << EXTI_RTSR1_RT11_Pos)                 /*!< 0x00000800 */
+#define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR1_RT12_Pos      (12U)                                         
+#define EXTI_RTSR1_RT12_Msk      (0x1U << EXTI_RTSR1_RT12_Pos)                 /*!< 0x00001000 */
+#define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR1_RT13_Pos      (13U)                                         
+#define EXTI_RTSR1_RT13_Msk      (0x1U << EXTI_RTSR1_RT13_Pos)                 /*!< 0x00002000 */
+#define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR1_RT14_Pos      (14U)                                         
+#define EXTI_RTSR1_RT14_Msk      (0x1U << EXTI_RTSR1_RT14_Pos)                 /*!< 0x00004000 */
+#define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR1_RT15_Pos      (15U)                                         
+#define EXTI_RTSR1_RT15_Msk      (0x1U << EXTI_RTSR1_RT15_Pos)                 /*!< 0x00008000 */
+#define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR1_RT16_Pos      (16U)                                         
+#define EXTI_RTSR1_RT16_Msk      (0x1U << EXTI_RTSR1_RT16_Pos)                 /*!< 0x00010000 */
+#define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR1_RT18_Pos      (18U)                                         
+#define EXTI_RTSR1_RT18_Msk      (0x1U << EXTI_RTSR1_RT18_Pos)                 /*!< 0x00040000 */
+#define EXTI_RTSR1_RT18          EXTI_RTSR1_RT18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR1_RT19_Pos      (19U)                                         
+#define EXTI_RTSR1_RT19_Msk      (0x1U << EXTI_RTSR1_RT19_Pos)                 /*!< 0x00080000 */
+#define EXTI_RTSR1_RT19          EXTI_RTSR1_RT19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR1_RT20_Pos      (20U)                                         
+#define EXTI_RTSR1_RT20_Msk      (0x1U << EXTI_RTSR1_RT20_Pos)                 /*!< 0x00100000 */
+#define EXTI_RTSR1_RT20          EXTI_RTSR1_RT20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR1_RT21_Pos      (21U)                                         
+#define EXTI_RTSR1_RT21_Msk      (0x1U << EXTI_RTSR1_RT21_Pos)                 /*!< 0x00200000 */
+#define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR1_RT22_Pos      (22U)                                         
+#define EXTI_RTSR1_RT22_Msk      (0x1U << EXTI_RTSR1_RT22_Pos)                 /*!< 0x00400000 */
+#define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_FTSR1 register  ******************/
+#define EXTI_FTSR1_FT0_Pos       (0U)                                          
+#define EXTI_FTSR1_FT0_Msk       (0x1U << EXTI_FTSR1_FT0_Pos)                  /*!< 0x00000001 */
+#define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR1_FT1_Pos       (1U)                                          
+#define EXTI_FTSR1_FT1_Msk       (0x1U << EXTI_FTSR1_FT1_Pos)                  /*!< 0x00000002 */
+#define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR1_FT2_Pos       (2U)                                          
+#define EXTI_FTSR1_FT2_Msk       (0x1U << EXTI_FTSR1_FT2_Pos)                  /*!< 0x00000004 */
+#define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR1_FT3_Pos       (3U)                                          
+#define EXTI_FTSR1_FT3_Msk       (0x1U << EXTI_FTSR1_FT3_Pos)                  /*!< 0x00000008 */
+#define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR1_FT4_Pos       (4U)                                          
+#define EXTI_FTSR1_FT4_Msk       (0x1U << EXTI_FTSR1_FT4_Pos)                  /*!< 0x00000010 */
+#define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR1_FT5_Pos       (5U)                                          
+#define EXTI_FTSR1_FT5_Msk       (0x1U << EXTI_FTSR1_FT5_Pos)                  /*!< 0x00000020 */
+#define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR1_FT6_Pos       (6U)                                          
+#define EXTI_FTSR1_FT6_Msk       (0x1U << EXTI_FTSR1_FT6_Pos)                  /*!< 0x00000040 */
+#define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR1_FT7_Pos       (7U)                                          
+#define EXTI_FTSR1_FT7_Msk       (0x1U << EXTI_FTSR1_FT7_Pos)                  /*!< 0x00000080 */
+#define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR1_FT8_Pos       (8U)                                          
+#define EXTI_FTSR1_FT8_Msk       (0x1U << EXTI_FTSR1_FT8_Pos)                  /*!< 0x00000100 */
+#define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR1_FT9_Pos       (9U)                                          
+#define EXTI_FTSR1_FT9_Msk       (0x1U << EXTI_FTSR1_FT9_Pos)                  /*!< 0x00000200 */
+#define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR1_FT10_Pos      (10U)                                         
+#define EXTI_FTSR1_FT10_Msk      (0x1U << EXTI_FTSR1_FT10_Pos)                 /*!< 0x00000400 */
+#define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR1_FT11_Pos      (11U)                                         
+#define EXTI_FTSR1_FT11_Msk      (0x1U << EXTI_FTSR1_FT11_Pos)                 /*!< 0x00000800 */
+#define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR1_FT12_Pos      (12U)                                         
+#define EXTI_FTSR1_FT12_Msk      (0x1U << EXTI_FTSR1_FT12_Pos)                 /*!< 0x00001000 */
+#define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR1_FT13_Pos      (13U)                                         
+#define EXTI_FTSR1_FT13_Msk      (0x1U << EXTI_FTSR1_FT13_Pos)                 /*!< 0x00002000 */
+#define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR1_FT14_Pos      (14U)                                         
+#define EXTI_FTSR1_FT14_Msk      (0x1U << EXTI_FTSR1_FT14_Pos)                 /*!< 0x00004000 */
+#define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR1_FT15_Pos      (15U)                                         
+#define EXTI_FTSR1_FT15_Msk      (0x1U << EXTI_FTSR1_FT15_Pos)                 /*!< 0x00008000 */
+#define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR1_FT16_Pos      (16U)                                         
+#define EXTI_FTSR1_FT16_Msk      (0x1U << EXTI_FTSR1_FT16_Pos)                 /*!< 0x00010000 */
+#define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR1_FT18_Pos      (18U)                                         
+#define EXTI_FTSR1_FT18_Msk      (0x1U << EXTI_FTSR1_FT18_Pos)                 /*!< 0x00040000 */
+#define EXTI_FTSR1_FT18          EXTI_FTSR1_FT18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR1_FT19_Pos      (19U)                                         
+#define EXTI_FTSR1_FT19_Msk      (0x1U << EXTI_FTSR1_FT19_Pos)                 /*!< 0x00080000 */
+#define EXTI_FTSR1_FT19          EXTI_FTSR1_FT19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR1_FT20_Pos      (20U)                                         
+#define EXTI_FTSR1_FT20_Msk      (0x1U << EXTI_FTSR1_FT20_Pos)                 /*!< 0x00100000 */
+#define EXTI_FTSR1_FT20          EXTI_FTSR1_FT20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR1_FT21_Pos      (21U)                                         
+#define EXTI_FTSR1_FT21_Msk      (0x1U << EXTI_FTSR1_FT21_Pos)                 /*!< 0x00200000 */
+#define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR1_FT22_Pos      (22U)                                         
+#define EXTI_FTSR1_FT22_Msk      (0x1U << EXTI_FTSR1_FT22_Pos)                 /*!< 0x00400000 */
+#define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_SWIER1 register  *****************/
+#define EXTI_SWIER1_SWI0_Pos     (0U)                                          
+#define EXTI_SWIER1_SWI0_Msk     (0x1U << EXTI_SWIER1_SWI0_Pos)                /*!< 0x00000001 */
+#define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWI1_Pos     (1U)                                          
+#define EXTI_SWIER1_SWI1_Msk     (0x1U << EXTI_SWIER1_SWI1_Pos)                /*!< 0x00000002 */
+#define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWI2_Pos     (2U)                                          
+#define EXTI_SWIER1_SWI2_Msk     (0x1U << EXTI_SWIER1_SWI2_Pos)                /*!< 0x00000004 */
+#define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWI3_Pos     (3U)                                          
+#define EXTI_SWIER1_SWI3_Msk     (0x1U << EXTI_SWIER1_SWI3_Pos)                /*!< 0x00000008 */
+#define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWI4_Pos     (4U)                                          
+#define EXTI_SWIER1_SWI4_Msk     (0x1U << EXTI_SWIER1_SWI4_Pos)                /*!< 0x00000010 */
+#define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWI5_Pos     (5U)                                          
+#define EXTI_SWIER1_SWI5_Msk     (0x1U << EXTI_SWIER1_SWI5_Pos)                /*!< 0x00000020 */
+#define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWI6_Pos     (6U)                                          
+#define EXTI_SWIER1_SWI6_Msk     (0x1U << EXTI_SWIER1_SWI6_Pos)                /*!< 0x00000040 */
+#define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWI7_Pos     (7U)                                          
+#define EXTI_SWIER1_SWI7_Msk     (0x1U << EXTI_SWIER1_SWI7_Pos)                /*!< 0x00000080 */
+#define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWI8_Pos     (8U)                                          
+#define EXTI_SWIER1_SWI8_Msk     (0x1U << EXTI_SWIER1_SWI8_Pos)                /*!< 0x00000100 */
+#define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWI9_Pos     (9U)                                          
+#define EXTI_SWIER1_SWI9_Msk     (0x1U << EXTI_SWIER1_SWI9_Pos)                /*!< 0x00000200 */
+#define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWI10_Pos    (10U)                                         
+#define EXTI_SWIER1_SWI10_Msk    (0x1U << EXTI_SWIER1_SWI10_Pos)               /*!< 0x00000400 */
+#define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWI11_Pos    (11U)                                         
+#define EXTI_SWIER1_SWI11_Msk    (0x1U << EXTI_SWIER1_SWI11_Pos)               /*!< 0x00000800 */
+#define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWI12_Pos    (12U)                                         
+#define EXTI_SWIER1_SWI12_Msk    (0x1U << EXTI_SWIER1_SWI12_Pos)               /*!< 0x00001000 */
+#define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWI13_Pos    (13U)                                         
+#define EXTI_SWIER1_SWI13_Msk    (0x1U << EXTI_SWIER1_SWI13_Pos)               /*!< 0x00002000 */
+#define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWI14_Pos    (14U)                                         
+#define EXTI_SWIER1_SWI14_Msk    (0x1U << EXTI_SWIER1_SWI14_Pos)               /*!< 0x00004000 */
+#define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWI15_Pos    (15U)                                         
+#define EXTI_SWIER1_SWI15_Msk    (0x1U << EXTI_SWIER1_SWI15_Pos)               /*!< 0x00008000 */
+#define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWI16_Pos    (16U)                                         
+#define EXTI_SWIER1_SWI16_Msk    (0x1U << EXTI_SWIER1_SWI16_Pos)               /*!< 0x00010000 */
+#define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER1_SWI18_Pos    (18U)                                         
+#define EXTI_SWIER1_SWI18_Msk    (0x1U << EXTI_SWIER1_SWI18_Pos)               /*!< 0x00040000 */
+#define EXTI_SWIER1_SWI18        EXTI_SWIER1_SWI18_Msk                         /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER1_SWI19_Pos    (19U)                                         
+#define EXTI_SWIER1_SWI19_Msk    (0x1U << EXTI_SWIER1_SWI19_Pos)               /*!< 0x00080000 */
+#define EXTI_SWIER1_SWI19        EXTI_SWIER1_SWI19_Msk                         /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER1_SWI20_Pos    (20U)                                         
+#define EXTI_SWIER1_SWI20_Msk    (0x1U << EXTI_SWIER1_SWI20_Pos)               /*!< 0x00100000 */
+#define EXTI_SWIER1_SWI20        EXTI_SWIER1_SWI20_Msk                         /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWI21_Pos    (21U)                                         
+#define EXTI_SWIER1_SWI21_Msk    (0x1U << EXTI_SWIER1_SWI21_Pos)               /*!< 0x00200000 */
+#define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER1_SWI22_Pos    (22U)                                         
+#define EXTI_SWIER1_SWI22_Msk    (0x1U << EXTI_SWIER1_SWI22_Pos)               /*!< 0x00400000 */
+#define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */
+
+/*******************  Bit definition for EXTI_PR1 register  *******************/
+#define EXTI_PR1_PIF0_Pos        (0U)                                          
+#define EXTI_PR1_PIF0_Msk        (0x1U << EXTI_PR1_PIF0_Pos)                   /*!< 0x00000001 */
+#define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
+#define EXTI_PR1_PIF1_Pos        (1U)                                          
+#define EXTI_PR1_PIF1_Msk        (0x1U << EXTI_PR1_PIF1_Pos)                   /*!< 0x00000002 */
+#define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
+#define EXTI_PR1_PIF2_Pos        (2U)                                          
+#define EXTI_PR1_PIF2_Msk        (0x1U << EXTI_PR1_PIF2_Pos)                   /*!< 0x00000004 */
+#define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
+#define EXTI_PR1_PIF3_Pos        (3U)                                          
+#define EXTI_PR1_PIF3_Msk        (0x1U << EXTI_PR1_PIF3_Pos)                   /*!< 0x00000008 */
+#define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
+#define EXTI_PR1_PIF4_Pos        (4U)                                          
+#define EXTI_PR1_PIF4_Msk        (0x1U << EXTI_PR1_PIF4_Pos)                   /*!< 0x00000010 */
+#define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
+#define EXTI_PR1_PIF5_Pos        (5U)                                          
+#define EXTI_PR1_PIF5_Msk        (0x1U << EXTI_PR1_PIF5_Pos)                   /*!< 0x00000020 */
+#define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
+#define EXTI_PR1_PIF6_Pos        (6U)                                          
+#define EXTI_PR1_PIF6_Msk        (0x1U << EXTI_PR1_PIF6_Pos)                   /*!< 0x00000040 */
+#define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
+#define EXTI_PR1_PIF7_Pos        (7U)                                          
+#define EXTI_PR1_PIF7_Msk        (0x1U << EXTI_PR1_PIF7_Pos)                   /*!< 0x00000080 */
+#define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
+#define EXTI_PR1_PIF8_Pos        (8U)                                          
+#define EXTI_PR1_PIF8_Msk        (0x1U << EXTI_PR1_PIF8_Pos)                   /*!< 0x00000100 */
+#define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
+#define EXTI_PR1_PIF9_Pos        (9U)                                          
+#define EXTI_PR1_PIF9_Msk        (0x1U << EXTI_PR1_PIF9_Pos)                   /*!< 0x00000200 */
+#define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
+#define EXTI_PR1_PIF10_Pos       (10U)                                         
+#define EXTI_PR1_PIF10_Msk       (0x1U << EXTI_PR1_PIF10_Pos)                  /*!< 0x00000400 */
+#define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
+#define EXTI_PR1_PIF11_Pos       (11U)                                         
+#define EXTI_PR1_PIF11_Msk       (0x1U << EXTI_PR1_PIF11_Pos)                  /*!< 0x00000800 */
+#define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
+#define EXTI_PR1_PIF12_Pos       (12U)                                         
+#define EXTI_PR1_PIF12_Msk       (0x1U << EXTI_PR1_PIF12_Pos)                  /*!< 0x00001000 */
+#define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
+#define EXTI_PR1_PIF13_Pos       (13U)                                         
+#define EXTI_PR1_PIF13_Msk       (0x1U << EXTI_PR1_PIF13_Pos)                  /*!< 0x00002000 */
+#define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
+#define EXTI_PR1_PIF14_Pos       (14U)                                         
+#define EXTI_PR1_PIF14_Msk       (0x1U << EXTI_PR1_PIF14_Pos)                  /*!< 0x00004000 */
+#define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
+#define EXTI_PR1_PIF15_Pos       (15U)                                         
+#define EXTI_PR1_PIF15_Msk       (0x1U << EXTI_PR1_PIF15_Pos)                  /*!< 0x00008000 */
+#define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
+#define EXTI_PR1_PIF16_Pos       (16U)                                         
+#define EXTI_PR1_PIF16_Msk       (0x1U << EXTI_PR1_PIF16_Pos)                  /*!< 0x00010000 */
+#define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
+#define EXTI_PR1_PIF18_Pos       (18U)                                         
+#define EXTI_PR1_PIF18_Msk       (0x1U << EXTI_PR1_PIF18_Pos)                  /*!< 0x00040000 */
+#define EXTI_PR1_PIF18           EXTI_PR1_PIF18_Msk                            /*!< Pending bit for line 18 */
+#define EXTI_PR1_PIF19_Pos       (19U)                                         
+#define EXTI_PR1_PIF19_Msk       (0x1U << EXTI_PR1_PIF19_Pos)                  /*!< 0x00080000 */
+#define EXTI_PR1_PIF19           EXTI_PR1_PIF19_Msk                            /*!< Pending bit for line 19 */
+#define EXTI_PR1_PIF20_Pos       (20U)                                         
+#define EXTI_PR1_PIF20_Msk       (0x1U << EXTI_PR1_PIF20_Pos)                  /*!< 0x00100000 */
+#define EXTI_PR1_PIF20           EXTI_PR1_PIF20_Msk                            /*!< Pending bit for line 20 */
+#define EXTI_PR1_PIF21_Pos       (21U)                                         
+#define EXTI_PR1_PIF21_Msk       (0x1U << EXTI_PR1_PIF21_Pos)                  /*!< 0x00200000 */
+#define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */
+#define EXTI_PR1_PIF22_Pos       (22U)                                         
+#define EXTI_PR1_PIF22_Msk       (0x1U << EXTI_PR1_PIF22_Pos)                  /*!< 0x00400000 */
+#define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */
+
+/*******************  Bit definition for EXTI_IMR2 register  ******************/
+#define EXTI_IMR2_IM32_Pos       (0U)                                          
+#define EXTI_IMR2_IM32_Msk       (0x1U << EXTI_IMR2_IM32_Pos)                  /*!< 0x00000001 */
+#define EXTI_IMR2_IM32           EXTI_IMR2_IM32_Msk                            /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_IM33_Pos       (1U)                                          
+#define EXTI_IMR2_IM33_Msk       (0x1U << EXTI_IMR2_IM33_Pos)                  /*!< 0x00000002 */
+#define EXTI_IMR2_IM33           EXTI_IMR2_IM33_Msk                            /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_IM34_Pos       (2U)                                          
+#define EXTI_IMR2_IM34_Msk       (0x1U << EXTI_IMR2_IM34_Pos)                  /*!< 0x00000004 */
+#define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_IM35_Pos       (3U)                                          
+#define EXTI_IMR2_IM35_Msk       (0x1U << EXTI_IMR2_IM35_Pos)                  /*!< 0x00000008 */
+#define EXTI_IMR2_IM35           EXTI_IMR2_IM35_Msk                            /*!< Interrupt Mask on line 35 */
+#define EXTI_IMR2_IM36_Pos       (4U)                                          
+#define EXTI_IMR2_IM36_Msk       (0x1U << EXTI_IMR2_IM36_Pos)                  /*!< 0x00000010 */
+#define EXTI_IMR2_IM36           EXTI_IMR2_IM36_Msk                            /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos       (5U)                                          
+#define EXTI_IMR2_IM37_Msk       (0x1U << EXTI_IMR2_IM37_Pos)                  /*!< 0x00000020 */
+#define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos       (6U)                                          
+#define EXTI_IMR2_IM38_Msk       (0x1U << EXTI_IMR2_IM38_Pos)                  /*!< 0x00000040 */
+#define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM39_Pos       (7U)                                          
+#define EXTI_IMR2_IM39_Msk       (0x1U << EXTI_IMR2_IM39_Pos)                  /*!< 0x00000080 */
+#define EXTI_IMR2_IM39           EXTI_IMR2_IM39_Msk                            /*!< Interrupt Mask on line 39 */
+#define EXTI_IMR2_IM40_Pos       (8U)                                          
+#define EXTI_IMR2_IM40_Msk       (0x1U << EXTI_IMR2_IM40_Pos)                  /*!< 0x00000100 */
+#define EXTI_IMR2_IM40           EXTI_IMR2_IM40_Msk                            /*!< Interrupt Mask on line 40 */
+#define EXTI_IMR2_IM_Pos         (0U)                                          
+#define EXTI_IMR2_IM_Msk         (0x1FFU << EXTI_IMR2_IM_Pos)                  /*!< 0x000001FF */
+#define EXTI_IMR2_IM             EXTI_IMR2_IM_Msk                              /*!< Interrupt Mask all        */
+
+/*******************  Bit definition for EXTI_EMR2 register  ******************/
+#define EXTI_EMR2_EM32_Pos       (0U)                                          
+#define EXTI_EMR2_EM32_Msk       (0x1U << EXTI_EMR2_EM32_Pos)                  /*!< 0x00000001 */
+#define EXTI_EMR2_EM32           EXTI_EMR2_EM32_Msk                            /*!< Event Mask on line 32 */
+#define EXTI_EMR2_EM33_Pos       (1U)                                          
+#define EXTI_EMR2_EM33_Msk       (0x1U << EXTI_EMR2_EM33_Pos)                  /*!< 0x00000002 */
+#define EXTI_EMR2_EM33           EXTI_EMR2_EM33_Msk                            /*!< Event Mask on line 33 */
+#define EXTI_EMR2_EM34_Pos       (2U)                                          
+#define EXTI_EMR2_EM34_Msk       (0x1U << EXTI_EMR2_EM34_Pos)                  /*!< 0x00000004 */
+#define EXTI_EMR2_EM34           EXTI_EMR2_EM34_Msk                            /*!< Event Mask on line 34 */
+#define EXTI_EMR2_EM35_Pos       (3U)                                          
+#define EXTI_EMR2_EM35_Msk       (0x1U << EXTI_EMR2_EM35_Pos)                  /*!< 0x00000008 */
+#define EXTI_EMR2_EM35           EXTI_EMR2_EM35_Msk                            /*!< Event Mask on line 35 */
+#define EXTI_EMR2_EM36_Pos       (4U)                                          
+#define EXTI_EMR2_EM36_Msk       (0x1U << EXTI_EMR2_EM36_Pos)                  /*!< 0x00000010 */
+#define EXTI_EMR2_EM36           EXTI_EMR2_EM36_Msk                            /*!< Event Mask on line 36 */
+#define EXTI_EMR2_EM37_Pos       (5U)                                          
+#define EXTI_EMR2_EM37_Msk       (0x1U << EXTI_EMR2_EM37_Pos)                  /*!< 0x00000020 */
+#define EXTI_EMR2_EM37           EXTI_EMR2_EM37_Msk                            /*!< Event Mask on line 37 */
+#define EXTI_EMR2_EM38_Pos       (6U)                                          
+#define EXTI_EMR2_EM38_Msk       (0x1U << EXTI_EMR2_EM38_Pos)                  /*!< 0x00000040 */
+#define EXTI_EMR2_EM38           EXTI_EMR2_EM38_Msk                            /*!< Event Mask on line 38 */
+#define EXTI_EMR2_EM39_Pos       (7U)                                          
+#define EXTI_EMR2_EM39_Msk       (0x1U << EXTI_EMR2_EM39_Pos)                  /*!< 0x00000080 */
+#define EXTI_EMR2_EM39           EXTI_EMR2_EM39_Msk                            /*!< Event Mask on line 39 */
+#define EXTI_EMR2_IM40_Pos       (8U)                                          
+#define EXTI_EMR2_IM40_Msk       (0x1U << EXTI_EMR2_IM40_Pos)                  /*!< 0x00000100 */
+#define EXTI_EMR2_IM40           EXTI_EMR2_IM40_Msk                            /*!< Event Mask on line 40 */
+
+/******************  Bit definition for EXTI_RTSR2 register  ******************/
+#define EXTI_RTSR2_RT35_Pos      (3U)                                          
+#define EXTI_RTSR2_RT35_Msk      (0x1U << EXTI_RTSR2_RT35_Pos)                 /*!< 0x00000008 */
+#define EXTI_RTSR2_RT35          EXTI_RTSR2_RT35_Msk                           /*!< Rising trigger event configuration bit of line 35 */
+#define EXTI_RTSR2_RT36_Pos      (4U)                                          
+#define EXTI_RTSR2_RT36_Msk      (0x1U << EXTI_RTSR2_RT36_Pos)                 /*!< 0x00000010 */
+#define EXTI_RTSR2_RT36          EXTI_RTSR2_RT36_Msk                           /*!< Rising trigger event configuration bit of line 36 */
+#define EXTI_RTSR2_RT37_Pos      (5U)                                          
+#define EXTI_RTSR2_RT37_Msk      (0x1U << EXTI_RTSR2_RT37_Pos)                 /*!< 0x00000020 */
+#define EXTI_RTSR2_RT37          EXTI_RTSR2_RT37_Msk                           /*!< Rising trigger event configuration bit of line 37 */
+#define EXTI_RTSR2_RT38_Pos      (6U)                                          
+#define EXTI_RTSR2_RT38_Msk      (0x1U << EXTI_RTSR2_RT38_Pos)                 /*!< 0x00000040 */
+#define EXTI_RTSR2_RT38          EXTI_RTSR2_RT38_Msk                           /*!< Rising trigger event configuration bit of line 38 */
+
+/******************  Bit definition for EXTI_FTSR2 register  ******************/
+#define EXTI_FTSR2_FT35_Pos      (3U)                                          
+#define EXTI_FTSR2_FT35_Msk      (0x1U << EXTI_FTSR2_FT35_Pos)                 /*!< 0x00000008 */
+#define EXTI_FTSR2_FT35          EXTI_FTSR2_FT35_Msk                           /*!< Falling trigger event configuration bit of line 35 */
+#define EXTI_FTSR2_FT36_Pos      (4U)                                          
+#define EXTI_FTSR2_FT36_Msk      (0x1U << EXTI_FTSR2_FT36_Pos)                 /*!< 0x00000010 */
+#define EXTI_FTSR2_FT36          EXTI_FTSR2_FT36_Msk                           /*!< Falling trigger event configuration bit of line 36 */
+#define EXTI_FTSR2_FT37_Pos      (5U)                                          
+#define EXTI_FTSR2_FT37_Msk      (0x1U << EXTI_FTSR2_FT37_Pos)                 /*!< 0x00000020 */
+#define EXTI_FTSR2_FT37          EXTI_FTSR2_FT37_Msk                           /*!< Falling trigger event configuration bit of line 37 */
+#define EXTI_FTSR2_FT38_Pos      (6U)                                          
+#define EXTI_FTSR2_FT38_Msk      (0x1U << EXTI_FTSR2_FT38_Pos)                 /*!< 0x00000040 */
+#define EXTI_FTSR2_FT38          EXTI_FTSR2_FT38_Msk                           /*!< Falling trigger event configuration bit of line 38 */
+
+/******************  Bit definition for EXTI_SWIER2 register  *****************/
+#define EXTI_SWIER2_SWI35_Pos    (3U)                                          
+#define EXTI_SWIER2_SWI35_Msk    (0x1U << EXTI_SWIER2_SWI35_Pos)               /*!< 0x00000008 */
+#define EXTI_SWIER2_SWI35        EXTI_SWIER2_SWI35_Msk                         /*!< Software Interrupt on line 35 */
+#define EXTI_SWIER2_SWI36_Pos    (4U)                                          
+#define EXTI_SWIER2_SWI36_Msk    (0x1U << EXTI_SWIER2_SWI36_Pos)               /*!< 0x00000010 */
+#define EXTI_SWIER2_SWI36        EXTI_SWIER2_SWI36_Msk                         /*!< Software Interrupt on line 36 */
+#define EXTI_SWIER2_SWI37_Pos    (5U)                                          
+#define EXTI_SWIER2_SWI37_Msk    (0x1U << EXTI_SWIER2_SWI37_Pos)               /*!< 0x00000020 */
+#define EXTI_SWIER2_SWI37        EXTI_SWIER2_SWI37_Msk                         /*!< Software Interrupt on line 37 */
+#define EXTI_SWIER2_SWI38_Pos    (6U)                                          
+#define EXTI_SWIER2_SWI38_Msk    (0x1U << EXTI_SWIER2_SWI38_Pos)               /*!< 0x00000040 */
+#define EXTI_SWIER2_SWI38        EXTI_SWIER2_SWI38_Msk                         /*!< Software Interrupt on line 38 */
+
+/*******************  Bit definition for EXTI_PR2 register  *******************/
+#define EXTI_PR2_PIF35_Pos       (3U)                                          
+#define EXTI_PR2_PIF35_Msk       (0x1U << EXTI_PR2_PIF35_Pos)                  /*!< 0x00000008 */
+#define EXTI_PR2_PIF35           EXTI_PR2_PIF35_Msk                            /*!< Pending bit for line 35 */
+#define EXTI_PR2_PIF36_Pos       (4U)                                          
+#define EXTI_PR2_PIF36_Msk       (0x1U << EXTI_PR2_PIF36_Pos)                  /*!< 0x00000010 */
+#define EXTI_PR2_PIF36           EXTI_PR2_PIF36_Msk                            /*!< Pending bit for line 36 */
+#define EXTI_PR2_PIF37_Pos       (5U)                                          
+#define EXTI_PR2_PIF37_Msk       (0x1U << EXTI_PR2_PIF37_Pos)                  /*!< 0x00000020 */
+#define EXTI_PR2_PIF37           EXTI_PR2_PIF37_Msk                            /*!< Pending bit for line 37 */
+#define EXTI_PR2_PIF38_Pos       (6U)                                          
+#define EXTI_PR2_PIF38_Msk       (0x1U << EXTI_PR2_PIF38_Pos)                  /*!< 0x00000040 */
+#define EXTI_PR2_PIF38           EXTI_PR2_PIF38_Msk                            /*!< Pending bit for line 38 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for FLASH_ACR register  *****************/
+#define FLASH_ACR_LATENCY_Pos             (0U)                                 
+#define FLASH_ACR_LATENCY_Msk             (0x7U << FLASH_ACR_LATENCY_Pos)      /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk                
+#define FLASH_ACR_LATENCY_0WS             (0x00000000U)
+#define FLASH_ACR_LATENCY_1WS             (0x00000001U)
+#define FLASH_ACR_LATENCY_2WS             (0x00000002U)
+#define FLASH_ACR_LATENCY_3WS             (0x00000003U)
+#define FLASH_ACR_LATENCY_4WS             (0x00000004U)
+#define FLASH_ACR_PRFTEN_Pos              (8U)                                 
+#define FLASH_ACR_PRFTEN_Msk              (0x1U << FLASH_ACR_PRFTEN_Pos)       /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN                  FLASH_ACR_PRFTEN_Msk                 
+#define FLASH_ACR_ICEN_Pos                (9U)                                 
+#define FLASH_ACR_ICEN_Msk                (0x1U << FLASH_ACR_ICEN_Pos)         /*!< 0x00000200 */
+#define FLASH_ACR_ICEN                    FLASH_ACR_ICEN_Msk                   
+#define FLASH_ACR_DCEN_Pos                (10U)                                
+#define FLASH_ACR_DCEN_Msk                (0x1U << FLASH_ACR_DCEN_Pos)         /*!< 0x00000400 */
+#define FLASH_ACR_DCEN                    FLASH_ACR_DCEN_Msk                   
+#define FLASH_ACR_ICRST_Pos               (11U)                                
+#define FLASH_ACR_ICRST_Msk               (0x1U << FLASH_ACR_ICRST_Pos)        /*!< 0x00000800 */
+#define FLASH_ACR_ICRST                   FLASH_ACR_ICRST_Msk                  
+#define FLASH_ACR_DCRST_Pos               (12U)                                
+#define FLASH_ACR_DCRST_Msk               (0x1U << FLASH_ACR_DCRST_Pos)        /*!< 0x00001000 */
+#define FLASH_ACR_DCRST                   FLASH_ACR_DCRST_Msk                  
+#define FLASH_ACR_RUN_PD_Pos              (13U)                                
+#define FLASH_ACR_RUN_PD_Msk              (0x1U << FLASH_ACR_RUN_PD_Pos)       /*!< 0x00002000 */
+#define FLASH_ACR_RUN_PD                  FLASH_ACR_RUN_PD_Msk                 /*!< Flash power down mode during run */
+#define FLASH_ACR_SLEEP_PD_Pos            (14U)                                
+#define FLASH_ACR_SLEEP_PD_Msk            (0x1U << FLASH_ACR_SLEEP_PD_Pos)     /*!< 0x00004000 */
+#define FLASH_ACR_SLEEP_PD                FLASH_ACR_SLEEP_PD_Msk               /*!< Flash power down mode during sleep */
+
+/*******************  Bits definition for FLASH_SR register  ******************/
+#define FLASH_SR_EOP_Pos                  (0U)                                 
+#define FLASH_SR_EOP_Msk                  (0x1U << FLASH_SR_EOP_Pos)           /*!< 0x00000001 */
+#define FLASH_SR_EOP                      FLASH_SR_EOP_Msk                     
+#define FLASH_SR_OPERR_Pos                (1U)                                 
+#define FLASH_SR_OPERR_Msk                (0x1U << FLASH_SR_OPERR_Pos)         /*!< 0x00000002 */
+#define FLASH_SR_OPERR                    FLASH_SR_OPERR_Msk                   
+#define FLASH_SR_PROGERR_Pos              (3U)                                 
+#define FLASH_SR_PROGERR_Msk              (0x1U << FLASH_SR_PROGERR_Pos)       /*!< 0x00000008 */
+#define FLASH_SR_PROGERR                  FLASH_SR_PROGERR_Msk                 
+#define FLASH_SR_WRPERR_Pos               (4U)                                 
+#define FLASH_SR_WRPERR_Msk               (0x1U << FLASH_SR_WRPERR_Pos)        /*!< 0x00000010 */
+#define FLASH_SR_WRPERR                   FLASH_SR_WRPERR_Msk                  
+#define FLASH_SR_PGAERR_Pos               (5U)                                 
+#define FLASH_SR_PGAERR_Msk               (0x1U << FLASH_SR_PGAERR_Pos)        /*!< 0x00000020 */
+#define FLASH_SR_PGAERR                   FLASH_SR_PGAERR_Msk                  
+#define FLASH_SR_SIZERR_Pos               (6U)                                 
+#define FLASH_SR_SIZERR_Msk               (0x1U << FLASH_SR_SIZERR_Pos)        /*!< 0x00000040 */
+#define FLASH_SR_SIZERR                   FLASH_SR_SIZERR_Msk                  
+#define FLASH_SR_PGSERR_Pos               (7U)                                 
+#define FLASH_SR_PGSERR_Msk               (0x1U << FLASH_SR_PGSERR_Pos)        /*!< 0x00000080 */
+#define FLASH_SR_PGSERR                   FLASH_SR_PGSERR_Msk                  
+#define FLASH_SR_MISERR_Pos               (8U)                                 
+#define FLASH_SR_MISERR_Msk               (0x1U << FLASH_SR_MISERR_Pos)        /*!< 0x00000100 */
+#define FLASH_SR_MISERR                   FLASH_SR_MISERR_Msk                  
+#define FLASH_SR_FASTERR_Pos              (9U)                                 
+#define FLASH_SR_FASTERR_Msk              (0x1U << FLASH_SR_FASTERR_Pos)       /*!< 0x00000200 */
+#define FLASH_SR_FASTERR                  FLASH_SR_FASTERR_Msk                 
+#define FLASH_SR_RDERR_Pos                (14U)                                
+#define FLASH_SR_RDERR_Msk                (0x1U << FLASH_SR_RDERR_Pos)         /*!< 0x00004000 */
+#define FLASH_SR_RDERR                    FLASH_SR_RDERR_Msk                   
+#define FLASH_SR_OPTVERR_Pos              (15U)                                
+#define FLASH_SR_OPTVERR_Msk              (0x1U << FLASH_SR_OPTVERR_Pos)       /*!< 0x00008000 */
+#define FLASH_SR_OPTVERR                  FLASH_SR_OPTVERR_Msk                 
+#define FLASH_SR_BSY_Pos                  (16U)                                
+#define FLASH_SR_BSY_Msk                  (0x1U << FLASH_SR_BSY_Pos)           /*!< 0x00010000 */
+#define FLASH_SR_BSY                      FLASH_SR_BSY_Msk                     
+#define FLASH_SR_PEMPTY_Pos               (17U)                                
+#define FLASH_SR_PEMPTY_Msk               (0x1U << FLASH_SR_PEMPTY_Pos)        /*!< 0x00020000 */
+#define FLASH_SR_PEMPTY                   FLASH_SR_PEMPTY_Msk                  
+
+/*******************  Bits definition for FLASH_CR register  ******************/
+#define FLASH_CR_PG_Pos                   (0U)                                 
+#define FLASH_CR_PG_Msk                   (0x1U << FLASH_CR_PG_Pos)            /*!< 0x00000001 */
+#define FLASH_CR_PG                       FLASH_CR_PG_Msk                      
+#define FLASH_CR_PER_Pos                  (1U)                                 
+#define FLASH_CR_PER_Msk                  (0x1U << FLASH_CR_PER_Pos)           /*!< 0x00000002 */
+#define FLASH_CR_PER                      FLASH_CR_PER_Msk                     
+#define FLASH_CR_MER1_Pos                 (2U)                                 
+#define FLASH_CR_MER1_Msk                 (0x1U << FLASH_CR_MER1_Pos)          /*!< 0x00000004 */
+#define FLASH_CR_MER1                     FLASH_CR_MER1_Msk                    
+#define FLASH_CR_PNB_Pos                  (3U)                                 
+#define FLASH_CR_PNB_Msk                  (0xFFU << FLASH_CR_PNB_Pos)          /*!< 0x000007F8 */
+#define FLASH_CR_PNB                      FLASH_CR_PNB_Msk                     
+#define FLASH_CR_BKER_Pos                 (11U)                                
+#define FLASH_CR_BKER_Msk                 (0x1U << FLASH_CR_BKER_Pos)          /*!< 0x00000800 */
+#define FLASH_CR_BKER                     FLASH_CR_BKER_Msk                    
+#define FLASH_CR_MER2_Pos                 (15U)                                
+#define FLASH_CR_MER2_Msk                 (0x1U << FLASH_CR_MER2_Pos)          /*!< 0x00008000 */
+#define FLASH_CR_MER2                     FLASH_CR_MER2_Msk                    
+#define FLASH_CR_STRT_Pos                 (16U)                                
+#define FLASH_CR_STRT_Msk                 (0x1U << FLASH_CR_STRT_Pos)          /*!< 0x00010000 */
+#define FLASH_CR_STRT                     FLASH_CR_STRT_Msk                    
+#define FLASH_CR_OPTSTRT_Pos              (17U)                                
+#define FLASH_CR_OPTSTRT_Msk              (0x1U << FLASH_CR_OPTSTRT_Pos)       /*!< 0x00020000 */
+#define FLASH_CR_OPTSTRT                  FLASH_CR_OPTSTRT_Msk                 
+#define FLASH_CR_FSTPG_Pos                (18U)                                
+#define FLASH_CR_FSTPG_Msk                (0x1U << FLASH_CR_FSTPG_Pos)         /*!< 0x00040000 */
+#define FLASH_CR_FSTPG                    FLASH_CR_FSTPG_Msk                   
+#define FLASH_CR_EOPIE_Pos                (24U)                                
+#define FLASH_CR_EOPIE_Msk                (0x1U << FLASH_CR_EOPIE_Pos)         /*!< 0x01000000 */
+#define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk                   
+#define FLASH_CR_ERRIE_Pos                (25U)                                
+#define FLASH_CR_ERRIE_Msk                (0x1U << FLASH_CR_ERRIE_Pos)         /*!< 0x02000000 */
+#define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk                   
+#define FLASH_CR_RDERRIE_Pos              (26U)                                
+#define FLASH_CR_RDERRIE_Msk              (0x1U << FLASH_CR_RDERRIE_Pos)       /*!< 0x04000000 */
+#define FLASH_CR_RDERRIE                  FLASH_CR_RDERRIE_Msk                 
+#define FLASH_CR_OBL_LAUNCH_Pos           (27U)                                
+#define FLASH_CR_OBL_LAUNCH_Msk           (0x1U << FLASH_CR_OBL_LAUNCH_Pos)    /*!< 0x08000000 */
+#define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk              
+#define FLASH_CR_OPTLOCK_Pos              (30U)                                
+#define FLASH_CR_OPTLOCK_Msk              (0x1U << FLASH_CR_OPTLOCK_Pos)       /*!< 0x40000000 */
+#define FLASH_CR_OPTLOCK                  FLASH_CR_OPTLOCK_Msk                 
+#define FLASH_CR_LOCK_Pos                 (31U)                                
+#define FLASH_CR_LOCK_Msk                 (0x1U << FLASH_CR_LOCK_Pos)          /*!< 0x80000000 */
+#define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk                    
+
+/*******************  Bits definition for FLASH_ECCR register  ***************/
+#define FLASH_ECCR_ADDR_ECC_Pos           (0U)                                 
+#define FLASH_ECCR_ADDR_ECC_Msk           (0x7FFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
+#define FLASH_ECCR_ADDR_ECC               FLASH_ECCR_ADDR_ECC_Msk              
+#define FLASH_ECCR_BK_ECC_Pos             (19U)                                
+#define FLASH_ECCR_BK_ECC_Msk             (0x1U << FLASH_ECCR_BK_ECC_Pos)      /*!< 0x00080000 */
+#define FLASH_ECCR_BK_ECC                 FLASH_ECCR_BK_ECC_Msk                
+#define FLASH_ECCR_SYSF_ECC_Pos           (20U)                                
+#define FLASH_ECCR_SYSF_ECC_Msk           (0x1U << FLASH_ECCR_SYSF_ECC_Pos)    /*!< 0x00100000 */
+#define FLASH_ECCR_SYSF_ECC               FLASH_ECCR_SYSF_ECC_Msk              
+#define FLASH_ECCR_ECCIE_Pos              (24U)                                
+#define FLASH_ECCR_ECCIE_Msk              (0x1U << FLASH_ECCR_ECCIE_Pos)       /*!< 0x01000000 */
+#define FLASH_ECCR_ECCIE                  FLASH_ECCR_ECCIE_Msk                 
+#define FLASH_ECCR_ECCC_Pos               (30U)                                
+#define FLASH_ECCR_ECCC_Msk               (0x1U << FLASH_ECCR_ECCC_Pos)        /*!< 0x40000000 */
+#define FLASH_ECCR_ECCC                   FLASH_ECCR_ECCC_Msk                  
+#define FLASH_ECCR_ECCD_Pos               (31U)                                
+#define FLASH_ECCR_ECCD_Msk               (0x1U << FLASH_ECCR_ECCD_Pos)        /*!< 0x80000000 */
+#define FLASH_ECCR_ECCD                   FLASH_ECCR_ECCD_Msk                  
+
+/*******************  Bits definition for FLASH_OPTR register  ***************/
+#define FLASH_OPTR_RDP_Pos                (0U)                                 
+#define FLASH_OPTR_RDP_Msk                (0xFFU << FLASH_OPTR_RDP_Pos)        /*!< 0x000000FF */
+#define FLASH_OPTR_RDP                    FLASH_OPTR_RDP_Msk                   
+#define FLASH_OPTR_BOR_LEV_Pos            (8U)                                 
+#define FLASH_OPTR_BOR_LEV_Msk            (0x7U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000700 */
+#define FLASH_OPTR_BOR_LEV                FLASH_OPTR_BOR_LEV_Msk               
+#define FLASH_OPTR_BOR_LEV_0              (0x0U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000000 */
+#define FLASH_OPTR_BOR_LEV_1              (0x1U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000100 */
+#define FLASH_OPTR_BOR_LEV_2              (0x2U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000200 */
+#define FLASH_OPTR_BOR_LEV_3              (0x3U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000300 */
+#define FLASH_OPTR_BOR_LEV_4              (0x4U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000400 */
+#define FLASH_OPTR_nRST_STOP_Pos          (12U)                                
+#define FLASH_OPTR_nRST_STOP_Msk          (0x1U << FLASH_OPTR_nRST_STOP_Pos)   /*!< 0x00001000 */
+#define FLASH_OPTR_nRST_STOP              FLASH_OPTR_nRST_STOP_Msk             
+#define FLASH_OPTR_nRST_STDBY_Pos         (13U)                                
+#define FLASH_OPTR_nRST_STDBY_Msk         (0x1U << FLASH_OPTR_nRST_STDBY_Pos)  /*!< 0x00002000 */
+#define FLASH_OPTR_nRST_STDBY             FLASH_OPTR_nRST_STDBY_Msk            
+#define FLASH_OPTR_nRST_SHDW_Pos          (14U)                                
+#define FLASH_OPTR_nRST_SHDW_Msk          (0x1U << FLASH_OPTR_nRST_SHDW_Pos)   /*!< 0x00004000 */
+#define FLASH_OPTR_nRST_SHDW              FLASH_OPTR_nRST_SHDW_Msk             
+#define FLASH_OPTR_IWDG_SW_Pos            (16U)                                
+#define FLASH_OPTR_IWDG_SW_Msk            (0x1U << FLASH_OPTR_IWDG_SW_Pos)     /*!< 0x00010000 */
+#define FLASH_OPTR_IWDG_SW                FLASH_OPTR_IWDG_SW_Msk               
+#define FLASH_OPTR_IWDG_STOP_Pos          (17U)                                
+#define FLASH_OPTR_IWDG_STOP_Msk          (0x1U << FLASH_OPTR_IWDG_STOP_Pos)   /*!< 0x00020000 */
+#define FLASH_OPTR_IWDG_STOP              FLASH_OPTR_IWDG_STOP_Msk             
+#define FLASH_OPTR_IWDG_STDBY_Pos         (18U)                                
+#define FLASH_OPTR_IWDG_STDBY_Msk         (0x1U << FLASH_OPTR_IWDG_STDBY_Pos)  /*!< 0x00040000 */
+#define FLASH_OPTR_IWDG_STDBY             FLASH_OPTR_IWDG_STDBY_Msk            
+#define FLASH_OPTR_WWDG_SW_Pos            (19U)                                
+#define FLASH_OPTR_WWDG_SW_Msk            (0x1U << FLASH_OPTR_WWDG_SW_Pos)     /*!< 0x00080000 */
+#define FLASH_OPTR_WWDG_SW                FLASH_OPTR_WWDG_SW_Msk               
+#define FLASH_OPTR_BFB2_Pos               (20U)                                
+#define FLASH_OPTR_BFB2_Msk               (0x1U << FLASH_OPTR_BFB2_Pos)        /*!< 0x00100000 */
+#define FLASH_OPTR_BFB2                   FLASH_OPTR_BFB2_Msk                  
+#define FLASH_OPTR_DUALBANK_Pos           (21U)                                
+#define FLASH_OPTR_DUALBANK_Msk           (0x1U << FLASH_OPTR_DUALBANK_Pos)    /*!< 0x00200000 */
+#define FLASH_OPTR_DUALBANK               FLASH_OPTR_DUALBANK_Msk              
+#define FLASH_OPTR_nBOOT1_Pos             (23U)                                
+#define FLASH_OPTR_nBOOT1_Msk             (0x1U << FLASH_OPTR_nBOOT1_Pos)      /*!< 0x00800000 */
+#define FLASH_OPTR_nBOOT1                 FLASH_OPTR_nBOOT1_Msk                
+#define FLASH_OPTR_SRAM2_PE_Pos           (24U)                                
+#define FLASH_OPTR_SRAM2_PE_Msk           (0x1U << FLASH_OPTR_SRAM2_PE_Pos)    /*!< 0x01000000 */
+#define FLASH_OPTR_SRAM2_PE               FLASH_OPTR_SRAM2_PE_Msk              
+#define FLASH_OPTR_SRAM2_RST_Pos          (25U)                                
+#define FLASH_OPTR_SRAM2_RST_Msk          (0x1U << FLASH_OPTR_SRAM2_RST_Pos)   /*!< 0x02000000 */
+#define FLASH_OPTR_SRAM2_RST              FLASH_OPTR_SRAM2_RST_Msk             
+#define FLASH_OPTR_nSWBOOT0_Pos           (26U)                                
+#define FLASH_OPTR_nSWBOOT0_Msk           (0x1U << FLASH_OPTR_nSWBOOT0_Pos)    /*!< 0x04000000 */
+#define FLASH_OPTR_nSWBOOT0               FLASH_OPTR_nSWBOOT0_Msk              
+#define FLASH_OPTR_nBOOT0_Pos             (27U)                                
+#define FLASH_OPTR_nBOOT0_Msk             (0x1U << FLASH_OPTR_nBOOT0_Pos)      /*!< 0x08000000 */
+#define FLASH_OPTR_nBOOT0                 FLASH_OPTR_nBOOT0_Msk                
+
+/******************  Bits definition for FLASH_PCROP1SR register  **********/
+#define FLASH_PCROP1SR_PCROP1_STRT_Pos    (0U)                                 
+#define FLASH_PCROP1SR_PCROP1_STRT_Msk    (0xFFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP1SR_PCROP1_STRT        FLASH_PCROP1SR_PCROP1_STRT_Msk       
+
+/******************  Bits definition for FLASH_PCROP1ER register  ***********/
+#define FLASH_PCROP1ER_PCROP1_END_Pos     (0U)                                 
+#define FLASH_PCROP1ER_PCROP1_END_Msk     (0xFFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP1ER_PCROP1_END         FLASH_PCROP1ER_PCROP1_END_Msk        
+#define FLASH_PCROP1ER_PCROP_RDP_Pos      (31U)                                
+#define FLASH_PCROP1ER_PCROP_RDP_Msk      (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
+#define FLASH_PCROP1ER_PCROP_RDP          FLASH_PCROP1ER_PCROP_RDP_Msk         
+
+/******************  Bits definition for FLASH_WRP1AR register  ***************/
+#define FLASH_WRP1AR_WRP1A_STRT_Pos       (0U)                                 
+#define FLASH_WRP1AR_WRP1A_STRT_Msk       (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP1AR_WRP1A_STRT           FLASH_WRP1AR_WRP1A_STRT_Msk          
+#define FLASH_WRP1AR_WRP1A_END_Pos        (16U)                                
+#define FLASH_WRP1AR_WRP1A_END_Msk        (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1AR_WRP1A_END            FLASH_WRP1AR_WRP1A_END_Msk           
+
+/******************  Bits definition for FLASH_WRPB1R register  ***************/
+#define FLASH_WRP1BR_WRP1B_STRT_Pos       (0U)                                 
+#define FLASH_WRP1BR_WRP1B_STRT_Msk       (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP1BR_WRP1B_STRT           FLASH_WRP1BR_WRP1B_STRT_Msk          
+#define FLASH_WRP1BR_WRP1B_END_Pos        (16U)                                
+#define FLASH_WRP1BR_WRP1B_END_Msk        (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP1BR_WRP1B_END            FLASH_WRP1BR_WRP1B_END_Msk           
+
+/******************  Bits definition for FLASH_PCROP2SR register  **********/
+#define FLASH_PCROP2SR_PCROP2_STRT_Pos    (0U)                                 
+#define FLASH_PCROP2SR_PCROP2_STRT_Msk    (0xFFFFU << FLASH_PCROP2SR_PCROP2_STRT_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP2SR_PCROP2_STRT        FLASH_PCROP2SR_PCROP2_STRT_Msk       
+
+/******************  Bits definition for FLASH_PCROP2ER register  ***********/
+#define FLASH_PCROP2ER_PCROP2_END_Pos     (0U)                                 
+#define FLASH_PCROP2ER_PCROP2_END_Msk     (0xFFFFU << FLASH_PCROP2ER_PCROP2_END_Pos) /*!< 0x0000FFFF */
+#define FLASH_PCROP2ER_PCROP2_END         FLASH_PCROP2ER_PCROP2_END_Msk        
+
+/******************  Bits definition for FLASH_WRP2AR register  ***************/
+#define FLASH_WRP2AR_WRP2A_STRT_Pos       (0U)                                 
+#define FLASH_WRP2AR_WRP2A_STRT_Msk       (0xFFU << FLASH_WRP2AR_WRP2A_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2AR_WRP2A_STRT           FLASH_WRP2AR_WRP2A_STRT_Msk          
+#define FLASH_WRP2AR_WRP2A_END_Pos        (16U)                                
+#define FLASH_WRP2AR_WRP2A_END_Msk        (0xFFU << FLASH_WRP2AR_WRP2A_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP2AR_WRP2A_END            FLASH_WRP2AR_WRP2A_END_Msk           
+
+/******************  Bits definition for FLASH_WRP2BR register  ***************/
+#define FLASH_WRP2BR_WRP2B_STRT_Pos       (0U)                                 
+#define FLASH_WRP2BR_WRP2B_STRT_Msk       (0xFFU << FLASH_WRP2BR_WRP2B_STRT_Pos) /*!< 0x000000FF */
+#define FLASH_WRP2BR_WRP2B_STRT           FLASH_WRP2BR_WRP2B_STRT_Msk          
+#define FLASH_WRP2BR_WRP2B_END_Pos        (16U)                                
+#define FLASH_WRP2BR_WRP2B_END_Msk        (0xFFU << FLASH_WRP2BR_WRP2B_END_Pos) /*!< 0x00FF0000 */
+#define FLASH_WRP2BR_WRP2B_END            FLASH_WRP2BR_WRP2B_END_Msk           
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCR1 register  *******************/
+#define FMC_BCR1_CCLKEN_Pos        (20U)                                       
+#define FMC_BCR1_CCLKEN_Msk        (0x1U << FMC_BCR1_CCLKEN_Pos)               /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */
+#define FMC_BCR1_WFDIS_Pos         (21U)                                       
+#define FMC_BCR1_WFDIS_Msk         (0x1U << FMC_BCR1_WFDIS_Pos)                /*!< 0x00200000 */
+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */
+
+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/
+#define FMC_BCRx_MBKEN_Pos         (0U)                                        
+#define FMC_BCRx_MBKEN_Msk         (0x1U << FMC_BCRx_MBKEN_Pos)                /*!< 0x00000001 */
+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */
+#define FMC_BCRx_MUXEN_Pos         (1U)                                        
+#define FMC_BCRx_MUXEN_Msk         (0x1U << FMC_BCRx_MUXEN_Pos)                /*!< 0x00000002 */
+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCRx_MTYP_Pos          (2U)                                        
+#define FMC_BCRx_MTYP_Msk          (0x3U << FMC_BCRx_MTYP_Pos)                 /*!< 0x0000000C */
+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCRx_MTYP_0            (0x1U << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */
+#define FMC_BCRx_MTYP_1            (0x2U << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */
+
+#define FMC_BCRx_MWID_Pos          (4U)                                        
+#define FMC_BCRx_MWID_Msk          (0x3U << FMC_BCRx_MWID_Pos)                 /*!< 0x00000030 */
+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCRx_MWID_0            (0x1U << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */
+#define FMC_BCRx_MWID_1            (0x2U << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */
+
+#define FMC_BCRx_FACCEN_Pos        (6U)                                        
+#define FMC_BCRx_FACCEN_Msk        (0x1U << FMC_BCRx_FACCEN_Pos)               /*!< 0x00000040 */
+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */
+#define FMC_BCRx_BURSTEN_Pos       (8U)                                        
+#define FMC_BCRx_BURSTEN_Msk       (0x1U << FMC_BCRx_BURSTEN_Pos)              /*!< 0x00000100 */
+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */
+#define FMC_BCRx_WAITPOL_Pos       (9U)                                        
+#define FMC_BCRx_WAITPOL_Msk       (0x1U << FMC_BCRx_WAITPOL_Pos)              /*!< 0x00000200 */
+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
+#define FMC_BCRx_WAITCFG_Pos       (11U)                                       
+#define FMC_BCRx_WAITCFG_Msk       (0x1U << FMC_BCRx_WAITCFG_Pos)              /*!< 0x00000800 */
+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */
+#define FMC_BCRx_WREN_Pos          (12U)                                       
+#define FMC_BCRx_WREN_Msk          (0x1U << FMC_BCRx_WREN_Pos)                 /*!< 0x00001000 */
+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */
+#define FMC_BCRx_WAITEN_Pos        (13U)                                       
+#define FMC_BCRx_WAITEN_Msk        (0x1U << FMC_BCRx_WAITEN_Pos)               /*!< 0x00002000 */
+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */
+#define FMC_BCRx_EXTMOD_Pos        (14U)                                       
+#define FMC_BCRx_EXTMOD_Msk        (0x1U << FMC_BCRx_EXTMOD_Pos)               /*!< 0x00004000 */
+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */
+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)                                       
+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1U << FMC_BCRx_ASYNCWAIT_Pos)            /*!< 0x00008000 */
+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
+
+#define FMC_BCRx_CPSIZE_Pos        (16U)                                       
+#define FMC_BCRx_CPSIZE_Msk        (0x7U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00070000 */
+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<CRAM page size             */
+#define FMC_BCRx_CPSIZE_0          (0x1U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */
+#define FMC_BCRx_CPSIZE_1          (0x2U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */
+#define FMC_BCRx_CPSIZE_2          (0x4U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */
+
+#define FMC_BCRx_CBURSTRW_Pos      (19U)                                       
+#define FMC_BCRx_CBURSTRW_Msk      (0x1U << FMC_BCRx_CBURSTRW_Pos)             /*!< 0x00080000 */
+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/
+#define FMC_BTRx_ADDSET_Pos        (0U)                                        
+#define FMC_BTRx_ADDSET_Msk        (0xFU << FMC_BTRx_ADDSET_Pos)               /*!< 0x0000000F */
+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTRx_ADDSET_0          (0x1U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */
+#define FMC_BTRx_ADDSET_1          (0x2U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */
+#define FMC_BTRx_ADDSET_2          (0x4U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */
+#define FMC_BTRx_ADDSET_3          (0x8U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */
+
+#define FMC_BTRx_ADDHLD_Pos        (4U)                                        
+#define FMC_BTRx_ADDHLD_Msk        (0xFU << FMC_BTRx_ADDHLD_Pos)               /*!< 0x000000F0 */
+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define FMC_BTRx_ADDHLD_0          (0x1U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */
+#define FMC_BTRx_ADDHLD_1          (0x2U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */
+#define FMC_BTRx_ADDHLD_2          (0x4U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */
+#define FMC_BTRx_ADDHLD_3          (0x8U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */
+
+#define FMC_BTRx_DATAST_Pos        (8U)                                        
+#define FMC_BTRx_DATAST_Msk        (0xFFU << FMC_BTRx_DATAST_Pos)              /*!< 0x0000FF00 */
+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTRx_DATAST_0          (0x01U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */
+#define FMC_BTRx_DATAST_1          (0x02U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */
+#define FMC_BTRx_DATAST_2          (0x04U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */
+#define FMC_BTRx_DATAST_3          (0x08U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */
+#define FMC_BTRx_DATAST_4          (0x10U << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */
+#define FMC_BTRx_DATAST_5          (0x20U << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */
+#define FMC_BTRx_DATAST_6          (0x40U << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */
+#define FMC_BTRx_DATAST_7          (0x80U << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */
+
+#define FMC_BTRx_BUSTURN_Pos       (16U)                                       
+#define FMC_BTRx_BUSTURN_Msk       (0xFU << FMC_BTRx_BUSTURN_Pos)              /*!< 0x000F0000 */
+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTRx_BUSTURN_0         (0x1U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */
+#define FMC_BTRx_BUSTURN_1         (0x2U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */
+#define FMC_BTRx_BUSTURN_2         (0x4U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */
+#define FMC_BTRx_BUSTURN_3         (0x8U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */
+
+#define FMC_BTRx_CLKDIV_Pos        (20U)                                       
+#define FMC_BTRx_CLKDIV_Msk        (0xFU << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00F00000 */
+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTRx_CLKDIV_0          (0x1U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */
+#define FMC_BTRx_CLKDIV_1          (0x2U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */
+#define FMC_BTRx_CLKDIV_2          (0x4U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */
+#define FMC_BTRx_CLKDIV_3          (0x8U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */
+
+#define FMC_BTRx_DATLAT_Pos        (24U)                                       
+#define FMC_BTRx_DATLAT_Msk        (0xFU << FMC_BTRx_DATLAT_Pos)               /*!< 0x0F000000 */
+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLAT[3:0] bits (Data latency) */
+#define FMC_BTRx_DATLAT_0          (0x1U << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */
+#define FMC_BTRx_DATLAT_1          (0x2U << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */
+#define FMC_BTRx_DATLAT_2          (0x4U << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */
+#define FMC_BTRx_DATLAT_3          (0x8U << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */
+
+#define FMC_BTRx_ACCMOD_Pos        (28U)                                       
+#define FMC_BTRx_ACCMOD_Msk        (0x3U << FMC_BTRx_ACCMOD_Pos)               /*!< 0x30000000 */
+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTRx_ACCMOD_0          (0x1U << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */
+#define FMC_BTRx_ACCMOD_1          (0x2U << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
+#define FMC_BWTRx_ADDSET_Pos       (0U)                                        
+#define FMC_BWTRx_ADDSET_Msk       (0xFU << FMC_BWTRx_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTRx_ADDSET_0         (0x1U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BWTRx_ADDSET_1         (0x2U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BWTRx_ADDSET_2         (0x4U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BWTRx_ADDSET_3         (0x8U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BWTRx_ADDHLD_Pos       (4U)                                        
+#define FMC_BWTRx_ADDHLD_Msk       (0xFU << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTRx_ADDHLD_0         (0x1U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BWTRx_ADDHLD_1         (0x2U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BWTRx_ADDHLD_2         (0x4U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BWTRx_ADDHLD_3         (0x8U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BWTRx_DATAST_Pos       (8U)                                        
+#define FMC_BWTRx_DATAST_Msk       (0xFFU << FMC_BWTRx_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTRx_DATAST_0         (0x01U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BWTRx_DATAST_1         (0x02U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BWTRx_DATAST_2         (0x04U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BWTRx_DATAST_3         (0x08U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BWTRx_DATAST_4         (0x10U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BWTRx_DATAST_5         (0x20U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BWTRx_DATAST_6         (0x40U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BWTRx_DATAST_7         (0x80U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BWTRx_BUSTURN_Pos      (16U)                                       
+#define FMC_BWTRx_BUSTURN_Msk      (0xFU << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BWTRx_BUSTURN_0        (0x1U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BWTRx_BUSTURN_1        (0x2U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BWTRx_BUSTURN_2        (0x4U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BWTRx_BUSTURN_3        (0x8U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BWTRx_ACCMOD_Pos       (28U)                                       
+#define FMC_BWTRx_ACCMOD_Msk       (0x3U << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTRx_ACCMOD_0         (0x1U << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BWTRx_ACCMOD_1         (0x2U << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_PCR register  ********************/
+#define FMC_PCR_PWAITEN_Pos        (1U)                                        
+#define FMC_PCR_PWAITEN_Msk        (0x1U << FMC_PCR_PWAITEN_Pos)               /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */
+#define FMC_PCR_PBKEN_Pos          (2U)                                        
+#define FMC_PCR_PBKEN_Msk          (0x1U << FMC_PCR_PBKEN_Pos)                 /*!< 0x00000004 */
+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */
+#define FMC_PCR_PTYP_Pos           (3U)                                        
+#define FMC_PCR_PTYP_Msk           (0x1U << FMC_PCR_PTYP_Pos)                  /*!< 0x00000008 */
+#define FMC_PCR_PTYP               FMC_PCR_PTYP_Msk                            /*!<Memory type                               */
+
+#define FMC_PCR_PWID_Pos           (4U)                                        
+#define FMC_PCR_PWID_Msk           (0x3U << FMC_PCR_PWID_Pos)                  /*!< 0x00000030 */
+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0             (0x1U << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */
+#define FMC_PCR_PWID_1             (0x2U << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */
+
+#define FMC_PCR_ECCEN_Pos          (6U)                                        
+#define FMC_PCR_ECCEN_Msk          (0x1U << FMC_PCR_ECCEN_Pos)                 /*!< 0x00000040 */
+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */
+
+#define FMC_PCR_TCLR_Pos           (9U)                                        
+#define FMC_PCR_TCLR_Msk           (0xFU << FMC_PCR_TCLR_Pos)                  /*!< 0x00001E00 */
+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define FMC_PCR_TCLR_0             (0x1U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1             (0x2U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2             (0x4U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3             (0x8U << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */
+
+#define FMC_PCR_TAR_Pos            (13U)                                       
+#define FMC_PCR_TAR_Msk            (0xFU << FMC_PCR_TAR_Pos)                   /*!< 0x0001E000 */
+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define FMC_PCR_TAR_0              (0x1U << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */
+#define FMC_PCR_TAR_1              (0x2U << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */
+#define FMC_PCR_TAR_2              (0x4U << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */
+#define FMC_PCR_TAR_3              (0x8U << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */
+
+#define FMC_PCR_ECCPS_Pos          (17U)                                       
+#define FMC_PCR_ECCPS_Msk          (0x7U << FMC_PCR_ECCPS_Pos)                 /*!< 0x000E0000 */
+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */
+#define FMC_PCR_ECCPS_0            (0x1U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */
+#define FMC_PCR_ECCPS_1            (0x2U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */
+#define FMC_PCR_ECCPS_2            (0x4U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */
+
+/*******************  Bit definition for FMC_SR register  ********************/
+#define FMC_SR_IRS_Pos             (0U)                                        
+#define FMC_SR_IRS_Msk             (0x1U << FMC_SR_IRS_Pos)                    /*!< 0x00000001 */
+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */
+#define FMC_SR_ILS_Pos             (1U)                                        
+#define FMC_SR_ILS_Msk             (0x1U << FMC_SR_ILS_Pos)                    /*!< 0x00000002 */
+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */
+#define FMC_SR_IFS_Pos             (2U)                                        
+#define FMC_SR_IFS_Msk             (0x1U << FMC_SR_IFS_Pos)                    /*!< 0x00000004 */
+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */
+#define FMC_SR_IREN_Pos            (3U)                                        
+#define FMC_SR_IREN_Msk            (0x1U << FMC_SR_IREN_Pos)                   /*!< 0x00000008 */
+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */
+#define FMC_SR_ILEN_Pos            (4U)                                        
+#define FMC_SR_ILEN_Msk            (0x1U << FMC_SR_ILEN_Pos)                   /*!< 0x00000010 */
+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */
+#define FMC_SR_IFEN_Pos            (5U)                                        
+#define FMC_SR_IFEN_Msk            (0x1U << FMC_SR_IFEN_Pos)                   /*!< 0x00000020 */
+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT_Pos           (6U)                                        
+#define FMC_SR_FEMPT_Msk           (0x1U << FMC_SR_FEMPT_Pos)                  /*!< 0x00000040 */
+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */
+
+/******************  Bit definition for FMC_PMEM register  ******************/
+#define FMC_PMEM_MEMSET_Pos        (0U)                                        
+#define FMC_PMEM_MEMSET_Msk        (0xFFU << FMC_PMEM_MEMSET_Pos)              /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET            FMC_PMEM_MEMSET_Msk                         /*!<MEMSET[7:0] bits (Common memory setup time) */
+#define FMC_PMEM_MEMSET_0          (0x01U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET_1          (0x02U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET_2          (0x04U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET_3          (0x08U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET_4          (0x10U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET_5          (0x20U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET_6          (0x40U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET_7          (0x80U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000080 */
+
+#define FMC_PMEM_MEMWAIT_Pos       (8U)                                        
+#define FMC_PMEM_MEMWAIT_Msk       (0xFFU << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT           FMC_PMEM_MEMWAIT_Msk                        /*!<MEMWAIT[7:0] bits (Common memory wait time) */
+#define FMC_PMEM_MEMWAIT_0         (0x01U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT_1         (0x02U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT_2         (0x04U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT_3         (0x08U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT_4         (0x10U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT_5         (0x20U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT_6         (0x40U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT_7         (0x80U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00008000 */
+
+#define FMC_PMEM_MEMHOLD_Pos       (16U)                                       
+#define FMC_PMEM_MEMHOLD_Msk       (0xFFU << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD           FMC_PMEM_MEMHOLD_Msk                        /*!<MEMHOLD[7:0] bits (Common memory hold time) */
+#define FMC_PMEM_MEMHOLD_0         (0x01U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD_1         (0x02U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD_2         (0x04U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD_3         (0x08U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD_4         (0x10U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD_5         (0x20U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD_6         (0x40U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD_7         (0x80U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00800000 */
+
+#define FMC_PMEM_MEMHIZ_Pos        (24U)                                       
+#define FMC_PMEM_MEMHIZ_Msk        (0xFFU << FMC_PMEM_MEMHIZ_Pos)              /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ            FMC_PMEM_MEMHIZ_Msk                         /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
+#define FMC_PMEM_MEMHIZ_0          (0x01U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ_1          (0x02U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ_2          (0x04U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ_3          (0x08U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ_4          (0x10U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ_5          (0x20U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ_6          (0x40U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ_7          (0x80U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT register  *******************/
+#define FMC_PATT_ATTSET_Pos        (0U)                                        
+#define FMC_PATT_ATTSET_Msk        (0xFFU << FMC_PATT_ATTSET_Pos)              /*!< 0x000000FF */
+#define FMC_PATT_ATTSET            FMC_PATT_ATTSET_Msk                         /*!<ATTSET[7:0] bits (Attribute memory setup time) */
+#define FMC_PATT_ATTSET_0          (0x01U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000001 */
+#define FMC_PATT_ATTSET_1          (0x02U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000002 */
+#define FMC_PATT_ATTSET_2          (0x04U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000004 */
+#define FMC_PATT_ATTSET_3          (0x08U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000008 */
+#define FMC_PATT_ATTSET_4          (0x10U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000010 */
+#define FMC_PATT_ATTSET_5          (0x20U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000020 */
+#define FMC_PATT_ATTSET_6          (0x40U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000040 */
+#define FMC_PATT_ATTSET_7          (0x80U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000080 */
+
+#define FMC_PATT_ATTWAIT_Pos       (8U)                                        
+#define FMC_PATT_ATTWAIT_Msk       (0xFFU << FMC_PATT_ATTWAIT_Pos)             /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT           FMC_PATT_ATTWAIT_Msk                        /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
+#define FMC_PATT_ATTWAIT_0         (0x01U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT_1         (0x02U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT_2         (0x04U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT_3         (0x08U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT_4         (0x10U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT_5         (0x20U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT_6         (0x40U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT_7         (0x80U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00008000 */
+
+#define FMC_PATT_ATTHOLD_Pos       (16U)                                       
+#define FMC_PATT_ATTHOLD_Msk       (0xFFU << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD           FMC_PATT_ATTHOLD_Msk                        /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
+#define FMC_PATT_ATTHOLD_0         (0x01U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD_1         (0x02U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD_2         (0x04U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD_3         (0x08U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD_4         (0x10U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD_5         (0x20U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD_6         (0x40U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD_7         (0x80U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00800000 */
+
+#define FMC_PATT_ATTHIZ_Pos        (24U)                                       
+#define FMC_PATT_ATTHIZ_Msk        (0xFFU << FMC_PATT_ATTHIZ_Pos)              /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ            FMC_PATT_ATTHIZ_Msk                         /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
+#define FMC_PATT_ATTHIZ_0          (0x01U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ_1          (0x02U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ_2          (0x04U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ_3          (0x08U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ_4          (0x10U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ_5          (0x20U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ_6          (0x40U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ_7          (0x80U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_ECCR register  *******************/
+#define FMC_ECCR_ECC_Pos           (0U)                                        
+#define FMC_ECCR_ECC_Msk           (0xFFFFFFFFU << FMC_ECCR_ECC_Pos)           /*!< 0xFFFFFFFF */
+#define FMC_ECCR_ECC               FMC_ECCR_ECC_Msk                            /*!<ECC result */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODE0_Pos           (0U)                                    
+#define GPIO_MODER_MODE0_Msk           (0x3U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000003 */
+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk                    
+#define GPIO_MODER_MODE0_0             (0x1U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1             (0x2U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos           (2U)                                    
+#define GPIO_MODER_MODE1_Msk           (0x3U << GPIO_MODER_MODE1_Pos)          /*!< 0x0000000C */
+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk                    
+#define GPIO_MODER_MODE1_0             (0x1U << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1             (0x2U << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos           (4U)                                    
+#define GPIO_MODER_MODE2_Msk           (0x3U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000030 */
+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk                    
+#define GPIO_MODER_MODE2_0             (0x1U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1             (0x2U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos           (6U)                                    
+#define GPIO_MODER_MODE3_Msk           (0x3U << GPIO_MODER_MODE3_Pos)          /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk                    
+#define GPIO_MODER_MODE3_0             (0x1U << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1             (0x2U << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos           (8U)                                    
+#define GPIO_MODER_MODE4_Msk           (0x3U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000300 */
+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk                    
+#define GPIO_MODER_MODE4_0             (0x1U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1             (0x2U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos           (10U)                                   
+#define GPIO_MODER_MODE5_Msk           (0x3U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk                    
+#define GPIO_MODER_MODE5_0             (0x1U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1             (0x2U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos           (12U)                                   
+#define GPIO_MODER_MODE6_Msk           (0x3U << GPIO_MODER_MODE6_Pos)          /*!< 0x00003000 */
+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk                    
+#define GPIO_MODER_MODE6_0             (0x1U << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1             (0x2U << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos           (14U)                                   
+#define GPIO_MODER_MODE7_Msk           (0x3U << GPIO_MODER_MODE7_Pos)          /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk                    
+#define GPIO_MODER_MODE7_0             (0x1U << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1             (0x2U << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos           (16U)                                   
+#define GPIO_MODER_MODE8_Msk           (0x3U << GPIO_MODER_MODE8_Pos)          /*!< 0x00030000 */
+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk                    
+#define GPIO_MODER_MODE8_0             (0x1U << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1             (0x2U << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos           (18U)                                   
+#define GPIO_MODER_MODE9_Msk           (0x3U << GPIO_MODER_MODE9_Pos)          /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk                    
+#define GPIO_MODER_MODE9_0             (0x1U << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1             (0x2U << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos          (20U)                                   
+#define GPIO_MODER_MODE10_Msk          (0x3U << GPIO_MODER_MODE10_Pos)         /*!< 0x00300000 */
+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk                   
+#define GPIO_MODER_MODE10_0            (0x1U << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1            (0x2U << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos          (22U)                                   
+#define GPIO_MODER_MODE11_Msk          (0x3U << GPIO_MODER_MODE11_Pos)         /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk                   
+#define GPIO_MODER_MODE11_0            (0x1U << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1            (0x2U << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos          (24U)                                   
+#define GPIO_MODER_MODE12_Msk          (0x3U << GPIO_MODER_MODE12_Pos)         /*!< 0x03000000 */
+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk                   
+#define GPIO_MODER_MODE12_0            (0x1U << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1            (0x2U << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos          (26U)                                   
+#define GPIO_MODER_MODE13_Msk          (0x3U << GPIO_MODER_MODE13_Pos)         /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk                   
+#define GPIO_MODER_MODE13_0            (0x1U << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1            (0x2U << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos          (28U)                                   
+#define GPIO_MODER_MODE14_Msk          (0x3U << GPIO_MODER_MODE14_Pos)         /*!< 0x30000000 */
+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk                   
+#define GPIO_MODER_MODE14_0            (0x1U << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1            (0x2U << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos          (30U)                                   
+#define GPIO_MODER_MODE15_Msk          (0x3U << GPIO_MODER_MODE15_Pos)         /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk                   
+#define GPIO_MODER_MODE15_0            (0x1U << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1            (0x2U << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0                   GPIO_MODER_MODE0
+#define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0
+#define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1
+#define GPIO_MODER_MODER1                   GPIO_MODER_MODE1
+#define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0
+#define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1
+#define GPIO_MODER_MODER2                   GPIO_MODER_MODE2
+#define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0
+#define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1
+#define GPIO_MODER_MODER3                   GPIO_MODER_MODE3
+#define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0
+#define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1
+#define GPIO_MODER_MODER4                   GPIO_MODER_MODE4
+#define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0
+#define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1
+#define GPIO_MODER_MODER5                   GPIO_MODER_MODE5
+#define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0
+#define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1
+#define GPIO_MODER_MODER6                   GPIO_MODER_MODE6
+#define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0
+#define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1
+#define GPIO_MODER_MODER7                   GPIO_MODER_MODE7
+#define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0
+#define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1
+#define GPIO_MODER_MODER8                   GPIO_MODER_MODE8
+#define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0
+#define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1
+#define GPIO_MODER_MODER9                   GPIO_MODER_MODE9
+#define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0
+#define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1
+#define GPIO_MODER_MODER10                  GPIO_MODER_MODE10
+#define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0
+#define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1
+#define GPIO_MODER_MODER11                  GPIO_MODER_MODE11
+#define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0
+#define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1
+#define GPIO_MODER_MODER12                  GPIO_MODER_MODE12
+#define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0
+#define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1
+#define GPIO_MODER_MODER13                  GPIO_MODER_MODE13
+#define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0
+#define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1
+#define GPIO_MODER_MODER14                  GPIO_MODER_MODE14
+#define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0
+#define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1
+#define GPIO_MODER_MODER15                  GPIO_MODER_MODE15
+#define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0
+#define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos            (0U)                                    
+#define GPIO_OTYPER_OT0_Msk            (0x1U << GPIO_OTYPER_OT0_Pos)           /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk                     
+#define GPIO_OTYPER_OT1_Pos            (1U)                                    
+#define GPIO_OTYPER_OT1_Msk            (0x1U << GPIO_OTYPER_OT1_Pos)           /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk                     
+#define GPIO_OTYPER_OT2_Pos            (2U)                                    
+#define GPIO_OTYPER_OT2_Msk            (0x1U << GPIO_OTYPER_OT2_Pos)           /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk                     
+#define GPIO_OTYPER_OT3_Pos            (3U)                                    
+#define GPIO_OTYPER_OT3_Msk            (0x1U << GPIO_OTYPER_OT3_Pos)           /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk                     
+#define GPIO_OTYPER_OT4_Pos            (4U)                                    
+#define GPIO_OTYPER_OT4_Msk            (0x1U << GPIO_OTYPER_OT4_Pos)           /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk                     
+#define GPIO_OTYPER_OT5_Pos            (5U)                                    
+#define GPIO_OTYPER_OT5_Msk            (0x1U << GPIO_OTYPER_OT5_Pos)           /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk                     
+#define GPIO_OTYPER_OT6_Pos            (6U)                                    
+#define GPIO_OTYPER_OT6_Msk            (0x1U << GPIO_OTYPER_OT6_Pos)           /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk                     
+#define GPIO_OTYPER_OT7_Pos            (7U)                                    
+#define GPIO_OTYPER_OT7_Msk            (0x1U << GPIO_OTYPER_OT7_Pos)           /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk                     
+#define GPIO_OTYPER_OT8_Pos            (8U)                                    
+#define GPIO_OTYPER_OT8_Msk            (0x1U << GPIO_OTYPER_OT8_Pos)           /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk                     
+#define GPIO_OTYPER_OT9_Pos            (9U)                                    
+#define GPIO_OTYPER_OT9_Msk            (0x1U << GPIO_OTYPER_OT9_Pos)           /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk                     
+#define GPIO_OTYPER_OT10_Pos           (10U)                                   
+#define GPIO_OTYPER_OT10_Msk           (0x1U << GPIO_OTYPER_OT10_Pos)          /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk                    
+#define GPIO_OTYPER_OT11_Pos           (11U)                                   
+#define GPIO_OTYPER_OT11_Msk           (0x1U << GPIO_OTYPER_OT11_Pos)          /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk                    
+#define GPIO_OTYPER_OT12_Pos           (12U)                                   
+#define GPIO_OTYPER_OT12_Msk           (0x1U << GPIO_OTYPER_OT12_Pos)          /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk                    
+#define GPIO_OTYPER_OT13_Pos           (13U)                                   
+#define GPIO_OTYPER_OT13_Msk           (0x1U << GPIO_OTYPER_OT13_Pos)          /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk                    
+#define GPIO_OTYPER_OT14_Pos           (14U)                                   
+#define GPIO_OTYPER_OT14_Msk           (0x1U << GPIO_OTYPER_OT14_Pos)          /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk                    
+#define GPIO_OTYPER_OT15_Pos           (15U)                                   
+#define GPIO_OTYPER_OT15_Msk           (0x1U << GPIO_OTYPER_OT15_Pos)          /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk                    
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)                                    
+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk                
+#define GPIO_OSPEEDR_OSPEED0_0         (0x1U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1         (0x2U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)                                    
+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk                
+#define GPIO_OSPEEDR_OSPEED1_0         (0x1U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1         (0x2U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)                                    
+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk                
+#define GPIO_OSPEEDR_OSPEED2_0         (0x1U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1         (0x2U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)                                    
+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk                
+#define GPIO_OSPEEDR_OSPEED3_0         (0x1U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1         (0x2U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)                                    
+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk                
+#define GPIO_OSPEEDR_OSPEED4_0         (0x1U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1         (0x2U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)                                   
+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk                
+#define GPIO_OSPEEDR_OSPEED5_0         (0x1U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1         (0x2U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)                                   
+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk                
+#define GPIO_OSPEEDR_OSPEED6_0         (0x1U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1         (0x2U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)                                   
+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk                
+#define GPIO_OSPEEDR_OSPEED7_0         (0x1U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1         (0x2U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)                                   
+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk                
+#define GPIO_OSPEEDR_OSPEED8_0         (0x1U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1         (0x2U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)                                   
+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk                
+#define GPIO_OSPEEDR_OSPEED9_0         (0x1U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1         (0x2U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)                                   
+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk               
+#define GPIO_OSPEEDR_OSPEED10_0        (0x1U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1        (0x2U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)                                   
+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk               
+#define GPIO_OSPEEDR_OSPEED11_0        (0x1U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1        (0x2U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)                                   
+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk               
+#define GPIO_OSPEEDR_OSPEED12_0        (0x1U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1        (0x2U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)                                   
+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk               
+#define GPIO_OSPEEDR_OSPEED13_0        (0x1U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1        (0x2U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)                                   
+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk               
+#define GPIO_OSPEEDR_OSPEED14_0        (0x1U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1        (0x2U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)                                   
+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk               
+#define GPIO_OSPEEDR_OSPEED15_0        (0x1U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1        (0x2U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos           (0U)                                    
+#define GPIO_PUPDR_PUPD0_Msk           (0x3U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk                    
+#define GPIO_PUPDR_PUPD0_0             (0x1U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1             (0x2U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos           (2U)                                    
+#define GPIO_PUPDR_PUPD1_Msk           (0x3U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk                    
+#define GPIO_PUPDR_PUPD1_0             (0x1U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1             (0x2U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos           (4U)                                    
+#define GPIO_PUPDR_PUPD2_Msk           (0x3U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk                    
+#define GPIO_PUPDR_PUPD2_0             (0x1U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1             (0x2U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos           (6U)                                    
+#define GPIO_PUPDR_PUPD3_Msk           (0x3U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk                    
+#define GPIO_PUPDR_PUPD3_0             (0x1U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1             (0x2U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos           (8U)                                    
+#define GPIO_PUPDR_PUPD4_Msk           (0x3U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk                    
+#define GPIO_PUPDR_PUPD4_0             (0x1U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1             (0x2U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos           (10U)                                   
+#define GPIO_PUPDR_PUPD5_Msk           (0x3U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk                    
+#define GPIO_PUPDR_PUPD5_0             (0x1U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1             (0x2U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos           (12U)                                   
+#define GPIO_PUPDR_PUPD6_Msk           (0x3U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk                    
+#define GPIO_PUPDR_PUPD6_0             (0x1U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1             (0x2U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos           (14U)                                   
+#define GPIO_PUPDR_PUPD7_Msk           (0x3U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk                    
+#define GPIO_PUPDR_PUPD7_0             (0x1U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1             (0x2U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos           (16U)                                   
+#define GPIO_PUPDR_PUPD8_Msk           (0x3U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk                    
+#define GPIO_PUPDR_PUPD8_0             (0x1U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1             (0x2U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos           (18U)                                   
+#define GPIO_PUPDR_PUPD9_Msk           (0x3U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk                    
+#define GPIO_PUPDR_PUPD9_0             (0x1U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1             (0x2U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos          (20U)                                   
+#define GPIO_PUPDR_PUPD10_Msk          (0x3U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk                   
+#define GPIO_PUPDR_PUPD10_0            (0x1U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1            (0x2U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos          (22U)                                   
+#define GPIO_PUPDR_PUPD11_Msk          (0x3U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk                   
+#define GPIO_PUPDR_PUPD11_0            (0x1U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1            (0x2U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos          (24U)                                   
+#define GPIO_PUPDR_PUPD12_Msk          (0x3U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk                   
+#define GPIO_PUPDR_PUPD12_0            (0x1U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1            (0x2U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos          (26U)                                   
+#define GPIO_PUPDR_PUPD13_Msk          (0x3U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk                   
+#define GPIO_PUPDR_PUPD13_0            (0x1U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1            (0x2U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos          (28U)                                   
+#define GPIO_PUPDR_PUPD14_Msk          (0x3U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk                   
+#define GPIO_PUPDR_PUPD14_0            (0x1U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1            (0x2U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos          (30U)                                   
+#define GPIO_PUPDR_PUPD15_Msk          (0x3U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk                   
+#define GPIO_PUPDR_PUPD15_0            (0x1U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1            (0x2U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos               (0U)                                    
+#define GPIO_IDR_ID0_Msk               (0x1U << GPIO_IDR_ID0_Pos)              /*!< 0x00000001 */
+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk                        
+#define GPIO_IDR_ID1_Pos               (1U)                                    
+#define GPIO_IDR_ID1_Msk               (0x1U << GPIO_IDR_ID1_Pos)              /*!< 0x00000002 */
+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk                        
+#define GPIO_IDR_ID2_Pos               (2U)                                    
+#define GPIO_IDR_ID2_Msk               (0x1U << GPIO_IDR_ID2_Pos)              /*!< 0x00000004 */
+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk                        
+#define GPIO_IDR_ID3_Pos               (3U)                                    
+#define GPIO_IDR_ID3_Msk               (0x1U << GPIO_IDR_ID3_Pos)              /*!< 0x00000008 */
+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk                        
+#define GPIO_IDR_ID4_Pos               (4U)                                    
+#define GPIO_IDR_ID4_Msk               (0x1U << GPIO_IDR_ID4_Pos)              /*!< 0x00000010 */
+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk                        
+#define GPIO_IDR_ID5_Pos               (5U)                                    
+#define GPIO_IDR_ID5_Msk               (0x1U << GPIO_IDR_ID5_Pos)              /*!< 0x00000020 */
+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk                        
+#define GPIO_IDR_ID6_Pos               (6U)                                    
+#define GPIO_IDR_ID6_Msk               (0x1U << GPIO_IDR_ID6_Pos)              /*!< 0x00000040 */
+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk                        
+#define GPIO_IDR_ID7_Pos               (7U)                                    
+#define GPIO_IDR_ID7_Msk               (0x1U << GPIO_IDR_ID7_Pos)              /*!< 0x00000080 */
+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk                        
+#define GPIO_IDR_ID8_Pos               (8U)                                    
+#define GPIO_IDR_ID8_Msk               (0x1U << GPIO_IDR_ID8_Pos)              /*!< 0x00000100 */
+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk                        
+#define GPIO_IDR_ID9_Pos               (9U)                                    
+#define GPIO_IDR_ID9_Msk               (0x1U << GPIO_IDR_ID9_Pos)              /*!< 0x00000200 */
+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk                        
+#define GPIO_IDR_ID10_Pos              (10U)                                   
+#define GPIO_IDR_ID10_Msk              (0x1U << GPIO_IDR_ID10_Pos)             /*!< 0x00000400 */
+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk                       
+#define GPIO_IDR_ID11_Pos              (11U)                                   
+#define GPIO_IDR_ID11_Msk              (0x1U << GPIO_IDR_ID11_Pos)             /*!< 0x00000800 */
+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk                       
+#define GPIO_IDR_ID12_Pos              (12U)                                   
+#define GPIO_IDR_ID12_Msk              (0x1U << GPIO_IDR_ID12_Pos)             /*!< 0x00001000 */
+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk                       
+#define GPIO_IDR_ID13_Pos              (13U)                                   
+#define GPIO_IDR_ID13_Msk              (0x1U << GPIO_IDR_ID13_Pos)             /*!< 0x00002000 */
+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk                       
+#define GPIO_IDR_ID14_Pos              (14U)                                   
+#define GPIO_IDR_ID14_Msk              (0x1U << GPIO_IDR_ID14_Pos)             /*!< 0x00004000 */
+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk                       
+#define GPIO_IDR_ID15_Pos              (15U)                                   
+#define GPIO_IDR_ID15_Msk              (0x1U << GPIO_IDR_ID15_Pos)             /*!< 0x00008000 */
+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk                       
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0                      GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1                      GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2                      GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3                      GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4                      GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5                      GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6                      GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7                      GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8                      GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9                      GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10                     GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11                     GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12                     GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13                     GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14                     GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15                     GPIO_IDR_ID15
+
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0
+#define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1
+#define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2
+#define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3
+#define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4
+#define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5
+#define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6
+#define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7
+#define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8
+#define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9
+#define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10
+#define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11
+#define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12
+#define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13
+#define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14
+#define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos               (0U)                                    
+#define GPIO_ODR_OD0_Msk               (0x1U << GPIO_ODR_OD0_Pos)              /*!< 0x00000001 */
+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk                        
+#define GPIO_ODR_OD1_Pos               (1U)                                    
+#define GPIO_ODR_OD1_Msk               (0x1U << GPIO_ODR_OD1_Pos)              /*!< 0x00000002 */
+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk                        
+#define GPIO_ODR_OD2_Pos               (2U)                                    
+#define GPIO_ODR_OD2_Msk               (0x1U << GPIO_ODR_OD2_Pos)              /*!< 0x00000004 */
+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk                        
+#define GPIO_ODR_OD3_Pos               (3U)                                    
+#define GPIO_ODR_OD3_Msk               (0x1U << GPIO_ODR_OD3_Pos)              /*!< 0x00000008 */
+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk                        
+#define GPIO_ODR_OD4_Pos               (4U)                                    
+#define GPIO_ODR_OD4_Msk               (0x1U << GPIO_ODR_OD4_Pos)              /*!< 0x00000010 */
+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk                        
+#define GPIO_ODR_OD5_Pos               (5U)                                    
+#define GPIO_ODR_OD5_Msk               (0x1U << GPIO_ODR_OD5_Pos)              /*!< 0x00000020 */
+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk                        
+#define GPIO_ODR_OD6_Pos               (6U)                                    
+#define GPIO_ODR_OD6_Msk               (0x1U << GPIO_ODR_OD6_Pos)              /*!< 0x00000040 */
+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk                        
+#define GPIO_ODR_OD7_Pos               (7U)                                    
+#define GPIO_ODR_OD7_Msk               (0x1U << GPIO_ODR_OD7_Pos)              /*!< 0x00000080 */
+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk                        
+#define GPIO_ODR_OD8_Pos               (8U)                                    
+#define GPIO_ODR_OD8_Msk               (0x1U << GPIO_ODR_OD8_Pos)              /*!< 0x00000100 */
+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk                        
+#define GPIO_ODR_OD9_Pos               (9U)                                    
+#define GPIO_ODR_OD9_Msk               (0x1U << GPIO_ODR_OD9_Pos)              /*!< 0x00000200 */
+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk                        
+#define GPIO_ODR_OD10_Pos              (10U)                                   
+#define GPIO_ODR_OD10_Msk              (0x1U << GPIO_ODR_OD10_Pos)             /*!< 0x00000400 */
+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk                       
+#define GPIO_ODR_OD11_Pos              (11U)                                   
+#define GPIO_ODR_OD11_Msk              (0x1U << GPIO_ODR_OD11_Pos)             /*!< 0x00000800 */
+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk                       
+#define GPIO_ODR_OD12_Pos              (12U)                                   
+#define GPIO_ODR_OD12_Msk              (0x1U << GPIO_ODR_OD12_Pos)             /*!< 0x00001000 */
+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk                       
+#define GPIO_ODR_OD13_Pos              (13U)                                   
+#define GPIO_ODR_OD13_Msk              (0x1U << GPIO_ODR_OD13_Pos)             /*!< 0x00002000 */
+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk                       
+#define GPIO_ODR_OD14_Pos              (14U)                                   
+#define GPIO_ODR_OD14_Msk              (0x1U << GPIO_ODR_OD14_Pos)             /*!< 0x00004000 */
+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk                       
+#define GPIO_ODR_OD15_Pos              (15U)                                   
+#define GPIO_ODR_OD15_Msk              (0x1U << GPIO_ODR_OD15_Pos)             /*!< 0x00008000 */
+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk                       
+
+/* Legacy defines */
+#define GPIO_ODR_ODR_0                      GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1                      GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2                      GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3                      GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4                      GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5                      GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6                      GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7                      GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8                      GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9                      GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10                     GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11                     GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12                     GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13                     GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14                     GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15                     GPIO_ODR_OD15
+
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0
+#define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1
+#define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2
+#define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3
+#define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4
+#define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5
+#define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6
+#define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7
+#define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8
+#define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9
+#define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10
+#define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11
+#define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12
+#define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13
+#define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14
+#define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos              (0U)                                    
+#define GPIO_BSRR_BS0_Msk              (0x1U << GPIO_BSRR_BS0_Pos)             /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk                       
+#define GPIO_BSRR_BS1_Pos              (1U)                                    
+#define GPIO_BSRR_BS1_Msk              (0x1U << GPIO_BSRR_BS1_Pos)             /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk                       
+#define GPIO_BSRR_BS2_Pos              (2U)                                    
+#define GPIO_BSRR_BS2_Msk              (0x1U << GPIO_BSRR_BS2_Pos)             /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk                       
+#define GPIO_BSRR_BS3_Pos              (3U)                                    
+#define GPIO_BSRR_BS3_Msk              (0x1U << GPIO_BSRR_BS3_Pos)             /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk                       
+#define GPIO_BSRR_BS4_Pos              (4U)                                    
+#define GPIO_BSRR_BS4_Msk              (0x1U << GPIO_BSRR_BS4_Pos)             /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk                       
+#define GPIO_BSRR_BS5_Pos              (5U)                                    
+#define GPIO_BSRR_BS5_Msk              (0x1U << GPIO_BSRR_BS5_Pos)             /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk                       
+#define GPIO_BSRR_BS6_Pos              (6U)                                    
+#define GPIO_BSRR_BS6_Msk              (0x1U << GPIO_BSRR_BS6_Pos)             /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk                       
+#define GPIO_BSRR_BS7_Pos              (7U)                                    
+#define GPIO_BSRR_BS7_Msk              (0x1U << GPIO_BSRR_BS7_Pos)             /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk                       
+#define GPIO_BSRR_BS8_Pos              (8U)                                    
+#define GPIO_BSRR_BS8_Msk              (0x1U << GPIO_BSRR_BS8_Pos)             /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk                       
+#define GPIO_BSRR_BS9_Pos              (9U)                                    
+#define GPIO_BSRR_BS9_Msk              (0x1U << GPIO_BSRR_BS9_Pos)             /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk                       
+#define GPIO_BSRR_BS10_Pos             (10U)                                   
+#define GPIO_BSRR_BS10_Msk             (0x1U << GPIO_BSRR_BS10_Pos)            /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk                      
+#define GPIO_BSRR_BS11_Pos             (11U)                                   
+#define GPIO_BSRR_BS11_Msk             (0x1U << GPIO_BSRR_BS11_Pos)            /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk                      
+#define GPIO_BSRR_BS12_Pos             (12U)                                   
+#define GPIO_BSRR_BS12_Msk             (0x1U << GPIO_BSRR_BS12_Pos)            /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk                      
+#define GPIO_BSRR_BS13_Pos             (13U)                                   
+#define GPIO_BSRR_BS13_Msk             (0x1U << GPIO_BSRR_BS13_Pos)            /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk                      
+#define GPIO_BSRR_BS14_Pos             (14U)                                   
+#define GPIO_BSRR_BS14_Msk             (0x1U << GPIO_BSRR_BS14_Pos)            /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk                      
+#define GPIO_BSRR_BS15_Pos             (15U)                                   
+#define GPIO_BSRR_BS15_Msk             (0x1U << GPIO_BSRR_BS15_Pos)            /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk                      
+#define GPIO_BSRR_BR0_Pos              (16U)                                   
+#define GPIO_BSRR_BR0_Msk              (0x1U << GPIO_BSRR_BR0_Pos)             /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk                       
+#define GPIO_BSRR_BR1_Pos              (17U)                                   
+#define GPIO_BSRR_BR1_Msk              (0x1U << GPIO_BSRR_BR1_Pos)             /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk                       
+#define GPIO_BSRR_BR2_Pos              (18U)                                   
+#define GPIO_BSRR_BR2_Msk              (0x1U << GPIO_BSRR_BR2_Pos)             /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk                       
+#define GPIO_BSRR_BR3_Pos              (19U)                                   
+#define GPIO_BSRR_BR3_Msk              (0x1U << GPIO_BSRR_BR3_Pos)             /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk                       
+#define GPIO_BSRR_BR4_Pos              (20U)                                   
+#define GPIO_BSRR_BR4_Msk              (0x1U << GPIO_BSRR_BR4_Pos)             /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk                       
+#define GPIO_BSRR_BR5_Pos              (21U)                                   
+#define GPIO_BSRR_BR5_Msk              (0x1U << GPIO_BSRR_BR5_Pos)             /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk                       
+#define GPIO_BSRR_BR6_Pos              (22U)                                   
+#define GPIO_BSRR_BR6_Msk              (0x1U << GPIO_BSRR_BR6_Pos)             /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk                       
+#define GPIO_BSRR_BR7_Pos              (23U)                                   
+#define GPIO_BSRR_BR7_Msk              (0x1U << GPIO_BSRR_BR7_Pos)             /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk                       
+#define GPIO_BSRR_BR8_Pos              (24U)                                   
+#define GPIO_BSRR_BR8_Msk              (0x1U << GPIO_BSRR_BR8_Pos)             /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk                       
+#define GPIO_BSRR_BR9_Pos              (25U)                                   
+#define GPIO_BSRR_BR9_Msk              (0x1U << GPIO_BSRR_BR9_Pos)             /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk                       
+#define GPIO_BSRR_BR10_Pos             (26U)                                   
+#define GPIO_BSRR_BR10_Msk             (0x1U << GPIO_BSRR_BR10_Pos)            /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk                      
+#define GPIO_BSRR_BR11_Pos             (27U)                                   
+#define GPIO_BSRR_BR11_Msk             (0x1U << GPIO_BSRR_BR11_Pos)            /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk                      
+#define GPIO_BSRR_BR12_Pos             (28U)                                   
+#define GPIO_BSRR_BR12_Msk             (0x1U << GPIO_BSRR_BR12_Pos)            /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk                      
+#define GPIO_BSRR_BR13_Pos             (29U)                                   
+#define GPIO_BSRR_BR13_Msk             (0x1U << GPIO_BSRR_BR13_Pos)            /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk                      
+#define GPIO_BSRR_BR14_Pos             (30U)                                   
+#define GPIO_BSRR_BR14_Msk             (0x1U << GPIO_BSRR_BR14_Pos)            /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk                      
+#define GPIO_BSRR_BR15_Pos             (31U)                                   
+#define GPIO_BSRR_BR15_Msk             (0x1U << GPIO_BSRR_BR15_Pos)            /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk                      
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos             (0U)                                    
+#define GPIO_LCKR_LCK0_Msk             (0x1U << GPIO_LCKR_LCK0_Pos)            /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk                      
+#define GPIO_LCKR_LCK1_Pos             (1U)                                    
+#define GPIO_LCKR_LCK1_Msk             (0x1U << GPIO_LCKR_LCK1_Pos)            /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk                      
+#define GPIO_LCKR_LCK2_Pos             (2U)                                    
+#define GPIO_LCKR_LCK2_Msk             (0x1U << GPIO_LCKR_LCK2_Pos)            /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk                      
+#define GPIO_LCKR_LCK3_Pos             (3U)                                    
+#define GPIO_LCKR_LCK3_Msk             (0x1U << GPIO_LCKR_LCK3_Pos)            /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk                      
+#define GPIO_LCKR_LCK4_Pos             (4U)                                    
+#define GPIO_LCKR_LCK4_Msk             (0x1U << GPIO_LCKR_LCK4_Pos)            /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk                      
+#define GPIO_LCKR_LCK5_Pos             (5U)                                    
+#define GPIO_LCKR_LCK5_Msk             (0x1U << GPIO_LCKR_LCK5_Pos)            /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk                      
+#define GPIO_LCKR_LCK6_Pos             (6U)                                    
+#define GPIO_LCKR_LCK6_Msk             (0x1U << GPIO_LCKR_LCK6_Pos)            /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk                      
+#define GPIO_LCKR_LCK7_Pos             (7U)                                    
+#define GPIO_LCKR_LCK7_Msk             (0x1U << GPIO_LCKR_LCK7_Pos)            /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk                      
+#define GPIO_LCKR_LCK8_Pos             (8U)                                    
+#define GPIO_LCKR_LCK8_Msk             (0x1U << GPIO_LCKR_LCK8_Pos)            /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk                      
+#define GPIO_LCKR_LCK9_Pos             (9U)                                    
+#define GPIO_LCKR_LCK9_Msk             (0x1U << GPIO_LCKR_LCK9_Pos)            /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk                      
+#define GPIO_LCKR_LCK10_Pos            (10U)                                   
+#define GPIO_LCKR_LCK10_Msk            (0x1U << GPIO_LCKR_LCK10_Pos)           /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk                     
+#define GPIO_LCKR_LCK11_Pos            (11U)                                   
+#define GPIO_LCKR_LCK11_Msk            (0x1U << GPIO_LCKR_LCK11_Pos)           /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk                     
+#define GPIO_LCKR_LCK12_Pos            (12U)                                   
+#define GPIO_LCKR_LCK12_Msk            (0x1U << GPIO_LCKR_LCK12_Pos)           /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk                     
+#define GPIO_LCKR_LCK13_Pos            (13U)                                   
+#define GPIO_LCKR_LCK13_Msk            (0x1U << GPIO_LCKR_LCK13_Pos)           /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk                     
+#define GPIO_LCKR_LCK14_Pos            (14U)                                   
+#define GPIO_LCKR_LCK14_Msk            (0x1U << GPIO_LCKR_LCK14_Pos)           /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk                     
+#define GPIO_LCKR_LCK15_Pos            (15U)                                   
+#define GPIO_LCKR_LCK15_Msk            (0x1U << GPIO_LCKR_LCK15_Pos)           /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk                     
+#define GPIO_LCKR_LCKK_Pos             (16U)                                   
+#define GPIO_LCKR_LCKK_Msk             (0x1U << GPIO_LCKR_LCKK_Pos)            /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk                      
+
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos           (0U)                                    
+#define GPIO_AFRL_AFSEL0_Msk           (0xFU << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk                    
+#define GPIO_AFRL_AFSEL0_0             (0x1U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1             (0x2U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2             (0x4U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3             (0x8U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos           (4U)                                    
+#define GPIO_AFRL_AFSEL1_Msk           (0xFU << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk                    
+#define GPIO_AFRL_AFSEL1_0             (0x1U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1             (0x2U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2             (0x4U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3             (0x8U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos           (8U)                                    
+#define GPIO_AFRL_AFSEL2_Msk           (0xFU << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk                    
+#define GPIO_AFRL_AFSEL2_0             (0x1U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1             (0x2U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2             (0x4U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3             (0x8U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos           (12U)                                   
+#define GPIO_AFRL_AFSEL3_Msk           (0xFU << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk                    
+#define GPIO_AFRL_AFSEL3_0             (0x1U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1             (0x2U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2             (0x4U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3             (0x8U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos           (16U)                                   
+#define GPIO_AFRL_AFSEL4_Msk           (0xFU << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk                    
+#define GPIO_AFRL_AFSEL4_0             (0x1U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1             (0x2U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2             (0x4U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3             (0x8U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos           (20U)                                   
+#define GPIO_AFRL_AFSEL5_Msk           (0xFU << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk                    
+#define GPIO_AFRL_AFSEL5_0             (0x1U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1             (0x2U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2             (0x4U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3             (0x8U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos           (24U)                                   
+#define GPIO_AFRL_AFSEL6_Msk           (0xFU << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk                    
+#define GPIO_AFRL_AFSEL6_0             (0x1U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1             (0x2U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2             (0x4U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3             (0x8U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos           (28U)                                   
+#define GPIO_AFRL_AFSEL7_Msk           (0xFU << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk                    
+#define GPIO_AFRL_AFSEL7_0             (0x1U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1             (0x2U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2             (0x4U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3             (0x8U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos           (0U)                                    
+#define GPIO_AFRH_AFSEL8_Msk           (0xFU << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk                    
+#define GPIO_AFRH_AFSEL8_0             (0x1U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1             (0x2U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2             (0x4U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3             (0x8U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos           (4U)                                    
+#define GPIO_AFRH_AFSEL9_Msk           (0xFU << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk                    
+#define GPIO_AFRH_AFSEL9_0             (0x1U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1             (0x2U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2             (0x4U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3             (0x8U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos          (8U)                                    
+#define GPIO_AFRH_AFSEL10_Msk          (0xFU << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk                   
+#define GPIO_AFRH_AFSEL10_0            (0x1U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1            (0x2U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2            (0x4U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3            (0x8U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos          (12U)                                   
+#define GPIO_AFRH_AFSEL11_Msk          (0xFU << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk                   
+#define GPIO_AFRH_AFSEL11_0            (0x1U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1            (0x2U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2            (0x4U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3            (0x8U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos          (16U)                                   
+#define GPIO_AFRH_AFSEL12_Msk          (0xFU << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk                   
+#define GPIO_AFRH_AFSEL12_0            (0x1U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1            (0x2U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2            (0x4U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3            (0x8U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos          (20U)                                   
+#define GPIO_AFRH_AFSEL13_Msk          (0xFU << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk                   
+#define GPIO_AFRH_AFSEL13_0            (0x1U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1            (0x2U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2            (0x4U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3            (0x8U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos          (24U)                                   
+#define GPIO_AFRH_AFSEL14_Msk          (0xFU << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk                   
+#define GPIO_AFRH_AFSEL14_0            (0x1U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1            (0x2U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2            (0x4U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3            (0x8U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos          (28U)                                   
+#define GPIO_AFRH_AFSEL15_Msk          (0xFU << GPIO_AFRH_AFSEL15_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk                   
+#define GPIO_AFRH_AFSEL15_0            (0x1U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1            (0x2U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2            (0x4U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3            (0x8U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
+
+/******************  Bits definition for GPIO_BRR register  ******************/
+#define GPIO_BRR_BR0_Pos               (0U)                                    
+#define GPIO_BRR_BR0_Msk               (0x1U << GPIO_BRR_BR0_Pos)              /*!< 0x00000001 */
+#define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk                        
+#define GPIO_BRR_BR1_Pos               (1U)                                    
+#define GPIO_BRR_BR1_Msk               (0x1U << GPIO_BRR_BR1_Pos)              /*!< 0x00000002 */
+#define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk                        
+#define GPIO_BRR_BR2_Pos               (2U)                                    
+#define GPIO_BRR_BR2_Msk               (0x1U << GPIO_BRR_BR2_Pos)              /*!< 0x00000004 */
+#define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk                        
+#define GPIO_BRR_BR3_Pos               (3U)                                    
+#define GPIO_BRR_BR3_Msk               (0x1U << GPIO_BRR_BR3_Pos)              /*!< 0x00000008 */
+#define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk                        
+#define GPIO_BRR_BR4_Pos               (4U)                                    
+#define GPIO_BRR_BR4_Msk               (0x1U << GPIO_BRR_BR4_Pos)              /*!< 0x00000010 */
+#define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk                        
+#define GPIO_BRR_BR5_Pos               (5U)                                    
+#define GPIO_BRR_BR5_Msk               (0x1U << GPIO_BRR_BR5_Pos)              /*!< 0x00000020 */
+#define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk                        
+#define GPIO_BRR_BR6_Pos               (6U)                                    
+#define GPIO_BRR_BR6_Msk               (0x1U << GPIO_BRR_BR6_Pos)              /*!< 0x00000040 */
+#define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk                        
+#define GPIO_BRR_BR7_Pos               (7U)                                    
+#define GPIO_BRR_BR7_Msk               (0x1U << GPIO_BRR_BR7_Pos)              /*!< 0x00000080 */
+#define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk                        
+#define GPIO_BRR_BR8_Pos               (8U)                                    
+#define GPIO_BRR_BR8_Msk               (0x1U << GPIO_BRR_BR8_Pos)              /*!< 0x00000100 */
+#define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk                        
+#define GPIO_BRR_BR9_Pos               (9U)                                    
+#define GPIO_BRR_BR9_Msk               (0x1U << GPIO_BRR_BR9_Pos)              /*!< 0x00000200 */
+#define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk                        
+#define GPIO_BRR_BR10_Pos              (10U)                                   
+#define GPIO_BRR_BR10_Msk              (0x1U << GPIO_BRR_BR10_Pos)             /*!< 0x00000400 */
+#define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk                       
+#define GPIO_BRR_BR11_Pos              (11U)                                   
+#define GPIO_BRR_BR11_Msk              (0x1U << GPIO_BRR_BR11_Pos)             /*!< 0x00000800 */
+#define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk                       
+#define GPIO_BRR_BR12_Pos              (12U)                                   
+#define GPIO_BRR_BR12_Msk              (0x1U << GPIO_BRR_BR12_Pos)             /*!< 0x00001000 */
+#define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk                       
+#define GPIO_BRR_BR13_Pos              (13U)                                   
+#define GPIO_BRR_BR13_Msk              (0x1U << GPIO_BRR_BR13_Pos)             /*!< 0x00002000 */
+#define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk                       
+#define GPIO_BRR_BR14_Pos              (14U)                                   
+#define GPIO_BRR_BR14_Msk              (0x1U << GPIO_BRR_BR14_Pos)             /*!< 0x00004000 */
+#define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk                       
+#define GPIO_BRR_BR15_Pos              (15U)                                   
+#define GPIO_BRR_BR15_Msk              (0x1U << GPIO_BRR_BR15_Pos)             /*!< 0x00008000 */
+#define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk                       
+
+/* Legacy defines */
+#define GPIO_BRR_BR_0                       GPIO_BRR_BR0
+#define GPIO_BRR_BR_1                       GPIO_BRR_BR1
+#define GPIO_BRR_BR_2                       GPIO_BRR_BR2
+#define GPIO_BRR_BR_3                       GPIO_BRR_BR3
+#define GPIO_BRR_BR_4                       GPIO_BRR_BR4
+#define GPIO_BRR_BR_5                       GPIO_BRR_BR5
+#define GPIO_BRR_BR_6                       GPIO_BRR_BR6
+#define GPIO_BRR_BR_7                       GPIO_BRR_BR7
+#define GPIO_BRR_BR_8                       GPIO_BRR_BR8
+#define GPIO_BRR_BR_9                       GPIO_BRR_BR9
+#define GPIO_BRR_BR_10                      GPIO_BRR_BR10
+#define GPIO_BRR_BR_11                      GPIO_BRR_BR11
+#define GPIO_BRR_BR_12                      GPIO_BRR_BR12
+#define GPIO_BRR_BR_13                      GPIO_BRR_BR13
+#define GPIO_BRR_BR_14                      GPIO_BRR_BR14
+#define GPIO_BRR_BR_15                      GPIO_BRR_BR15
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define I2C_CR1_PE_Pos               (0U)                                      
+#define I2C_CR1_PE_Msk               (0x1U << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */
+#define I2C_CR1_TXIE_Pos             (1U)                                      
+#define I2C_CR1_TXIE_Msk             (0x1U << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */
+#define I2C_CR1_RXIE_Pos             (2U)                                      
+#define I2C_CR1_RXIE_Msk             (0x1U << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */
+#define I2C_CR1_ADDRIE_Pos           (3U)                                      
+#define I2C_CR1_ADDRIE_Msk           (0x1U << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */
+#define I2C_CR1_NACKIE_Pos           (4U)                                      
+#define I2C_CR1_NACKIE_Msk           (0x1U << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */
+#define I2C_CR1_STOPIE_Pos           (5U)                                      
+#define I2C_CR1_STOPIE_Msk           (0x1U << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */
+#define I2C_CR1_TCIE_Pos             (6U)                                      
+#define I2C_CR1_TCIE_Msk             (0x1U << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */
+#define I2C_CR1_ERRIE_Pos            (7U)                                      
+#define I2C_CR1_ERRIE_Msk            (0x1U << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */
+#define I2C_CR1_DNF_Pos              (8U)                                      
+#define I2C_CR1_DNF_Msk              (0xFU << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */
+#define I2C_CR1_ANFOFF_Pos           (12U)                                     
+#define I2C_CR1_ANFOFF_Msk           (0x1U << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */
+#define I2C_CR1_SWRST_Pos            (13U)                                     
+#define I2C_CR1_SWRST_Msk            (0x1U << I2C_CR1_SWRST_Pos)               /*!< 0x00002000 */
+#define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset                      */
+#define I2C_CR1_TXDMAEN_Pos          (14U)                                     
+#define I2C_CR1_TXDMAEN_Msk          (0x1U << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */
+#define I2C_CR1_RXDMAEN_Pos          (15U)                                     
+#define I2C_CR1_RXDMAEN_Msk          (0x1U << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */
+#define I2C_CR1_SBC_Pos              (16U)                                     
+#define I2C_CR1_SBC_Msk              (0x1U << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */
+#define I2C_CR1_NOSTRETCH_Pos        (17U)                                     
+#define I2C_CR1_NOSTRETCH_Msk        (0x1U << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */
+#define I2C_CR1_WUPEN_Pos            (18U)                                     
+#define I2C_CR1_WUPEN_Msk            (0x1U << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable             */
+#define I2C_CR1_GCEN_Pos             (19U)                                     
+#define I2C_CR1_GCEN_Msk             (0x1U << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */
+#define I2C_CR1_SMBHEN_Pos           (20U)                                     
+#define I2C_CR1_SMBHEN_Msk           (0x1U << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */
+#define I2C_CR1_SMBDEN_Pos           (21U)                                     
+#define I2C_CR1_SMBDEN_Msk           (0x1U << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos          (22U)                                     
+#define I2C_CR1_ALERTEN_Msk          (0x1U << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */
+#define I2C_CR1_PECEN_Pos            (23U)                                     
+#define I2C_CR1_PECEN_Msk            (0x1U << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_SADD_Pos             (0U)                                      
+#define I2C_CR2_SADD_Msk             (0x3FFU << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */
+#define I2C_CR2_RD_WRN_Pos           (10U)                                     
+#define I2C_CR2_RD_WRN_Msk           (0x1U << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */
+#define I2C_CR2_ADD10_Pos            (11U)                                     
+#define I2C_CR2_ADD10_Msk            (0x1U << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */
+#define I2C_CR2_HEAD10R_Pos          (12U)                                     
+#define I2C_CR2_HEAD10R_Msk          (0x1U << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos            (13U)                                     
+#define I2C_CR2_START_Msk            (0x1U << I2C_CR2_START_Pos)               /*!< 0x00002000 */
+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */
+#define I2C_CR2_STOP_Pos             (14U)                                     
+#define I2C_CR2_STOP_Msk             (0x1U << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */
+#define I2C_CR2_NACK_Pos             (15U)                                     
+#define I2C_CR2_NACK_Msk             (0x1U << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */
+#define I2C_CR2_NBYTES_Pos           (16U)                                     
+#define I2C_CR2_NBYTES_Msk           (0xFFU << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */
+#define I2C_CR2_RELOAD_Pos           (24U)                                     
+#define I2C_CR2_RELOAD_Msk           (0x1U << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */
+#define I2C_CR2_AUTOEND_Pos          (25U)                                     
+#define I2C_CR2_AUTOEND_Msk          (0x1U << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */
+#define I2C_CR2_PECBYTE_Pos          (26U)                                     
+#define I2C_CR2_PECBYTE_Msk          (0x1U << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define I2C_OAR1_OA1_Pos             (0U)                                      
+#define I2C_OAR1_OA1_Msk             (0x3FFU << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */
+#define I2C_OAR1_OA1MODE_Pos         (10U)                                     
+#define I2C_OAR1_OA1MODE_Msk         (0x1U << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos           (15U)                                     
+#define I2C_OAR1_OA1EN_Msk           (0x1U << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define I2C_OAR2_OA2_Pos             (1U)                                      
+#define I2C_OAR2_OA2_Msk             (0x7FU << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
+#define I2C_OAR2_OA2MSK_Pos          (8U)                                      
+#define I2C_OAR2_OA2MSK_Msk          (0x7U << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
+#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
+#define I2C_OAR2_OA2MASK01_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK01_Msk       (0x1U << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
+#define I2C_OAR2_OA2MASK02_Pos       (9U)                                      
+#define I2C_OAR2_OA2MASK02_Msk       (0x1U << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK03_Msk       (0x3U << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos       (10U)                                     
+#define I2C_OAR2_OA2MASK04_Msk       (0x1U << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK05_Msk       (0x5U << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos       (9U)                                      
+#define I2C_OAR2_OA2MASK06_Msk       (0x3U << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
+#define I2C_OAR2_OA2MASK07_Pos       (8U)                                      
+#define I2C_OAR2_OA2MASK07_Msk       (0x7U << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
+#define I2C_OAR2_OA2EN_Pos           (15U)                                     
+#define I2C_OAR2_OA2EN_Msk           (0x1U << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos         (0U)                                      
+#define I2C_TIMINGR_SCLL_Msk         (0xFFU << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */
+#define I2C_TIMINGR_SCLH_Pos         (8U)                                      
+#define I2C_TIMINGR_SCLH_Msk         (0xFFU << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos       (16U)                                     
+#define I2C_TIMINGR_SDADEL_Msk       (0xFU << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */
+#define I2C_TIMINGR_SCLDEL_Pos       (20U)                                     
+#define I2C_TIMINGR_SCLDEL_Msk       (0xFU << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */
+#define I2C_TIMINGR_PRESC_Pos        (28U)                                     
+#define I2C_TIMINGR_PRESC_Msk        (0xFU << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)                                      
+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */
+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)                                     
+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1U << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)                                     
+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)                                     
+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */
+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)                                     
+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1U << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define I2C_ISR_TXE_Pos              (0U)                                      
+#define I2C_ISR_TXE_Msk              (0x1U << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */
+#define I2C_ISR_TXIS_Pos             (1U)                                      
+#define I2C_ISR_TXIS_Msk             (0x1U << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */
+#define I2C_ISR_RXNE_Pos             (2U)                                      
+#define I2C_ISR_RXNE_Msk             (0x1U << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos             (3U)                                      
+#define I2C_ISR_ADDR_Msk             (0x1U << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */
+#define I2C_ISR_NACKF_Pos            (4U)                                      
+#define I2C_ISR_NACKF_Msk            (0x1U << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */
+#define I2C_ISR_STOPF_Pos            (5U)                                      
+#define I2C_ISR_STOPF_Msk            (0x1U << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */
+#define I2C_ISR_TC_Pos               (6U)                                      
+#define I2C_ISR_TC_Msk               (0x1U << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos              (7U)                                      
+#define I2C_ISR_TCR_Msk              (0x1U << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */
+#define I2C_ISR_BERR_Pos             (8U)                                      
+#define I2C_ISR_BERR_Msk             (0x1U << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */
+#define I2C_ISR_ARLO_Pos             (9U)                                      
+#define I2C_ISR_ARLO_Msk             (0x1U << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */
+#define I2C_ISR_OVR_Pos              (10U)                                     
+#define I2C_ISR_OVR_Msk              (0x1U << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */
+#define I2C_ISR_PECERR_Pos           (11U)                                     
+#define I2C_ISR_PECERR_Msk           (0x1U << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */
+#define I2C_ISR_TIMEOUT_Pos          (12U)                                     
+#define I2C_ISR_TIMEOUT_Msk          (0x1U << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */
+#define I2C_ISR_ALERT_Pos            (13U)                                     
+#define I2C_ISR_ALERT_Msk            (0x1U << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */
+#define I2C_ISR_BUSY_Pos             (15U)                                     
+#define I2C_ISR_BUSY_Msk             (0x1U << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */
+#define I2C_ISR_DIR_Pos              (16U)                                     
+#define I2C_ISR_DIR_Msk              (0x1U << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos          (17U)                                     
+#define I2C_ISR_ADDCODE_Msk          (0x7FU << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define I2C_ICR_ADDRCF_Pos           (3U)                                      
+#define I2C_ICR_ADDRCF_Msk           (0x1U << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag  */
+#define I2C_ICR_NACKCF_Pos           (4U)                                      
+#define I2C_ICR_NACKCF_Msk           (0x1U << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag             */
+#define I2C_ICR_STOPCF_Pos           (5U)                                      
+#define I2C_ICR_STOPCF_Msk           (0x1U << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag   */
+#define I2C_ICR_BERRCF_Pos           (8U)                                      
+#define I2C_ICR_BERRCF_Msk           (0x1U << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag        */
+#define I2C_ICR_ARLOCF_Pos           (9U)                                      
+#define I2C_ICR_ARLOCF_Msk           (0x1U << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos            (10U)                                     
+#define I2C_ICR_OVRCF_Msk            (0x1U << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos            (11U)                                     
+#define I2C_ICR_PECCF_Msk            (0x1U << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag        */
+#define I2C_ICR_TIMOUTCF_Pos         (12U)                                     
+#define I2C_ICR_TIMOUTCF_Msk         (0x1U << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag          */
+#define I2C_ICR_ALERTCF_Pos          (13U)                                     
+#define I2C_ICR_ALERTCF_Msk          (0x1U << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag            */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define I2C_PECR_PEC_Pos             (0U)                                      
+#define I2C_PECR_PEC_Msk             (0xFFU << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define I2C_RXDR_RXDATA_Pos          (0U)                                      
+#define I2C_RXDR_RXDATA_Msk          (0xFFU << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define I2C_TXDR_TXDATA_Pos          (0U)                                      
+#define I2C_TXDR_TXDATA_Msk          (0xFFU << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos      (0U)                                              
+#define IWDG_KR_KEY_Msk      (0xFFFFU << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos       (0U)                                              
+#define IWDG_PR_PR_Msk       (0x7U << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
+#define IWDG_PR_PR_0         (0x1U << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
+#define IWDG_PR_PR_1         (0x2U << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
+#define IWDG_PR_PR_2         (0x4U << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos      (0U)                                              
+#define IWDG_RLR_RL_Msk      (0xFFFU << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos      (0U)                                              
+#define IWDG_SR_PVU_Msk      (0x1U << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos      (1U)                                              
+#define IWDG_SR_RVU_Msk      (0x1U << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos      (2U)                                              
+#define IWDG_SR_WVU_Msk      (0x1U << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_WINR_WIN_Pos    (0U)                                              
+#define IWDG_WINR_WIN_Msk    (0xFFFU << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                     Firewall                               */
+/*                                                                            */
+/******************************************************************************/
+
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register          */
+#define FW_CSSA_ADD_Pos      (8U)                                              
+#define FW_CSSA_ADD_Msk      (0xFFFFU << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
+#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */
+#define FW_CSL_LENG_Pos      (8U)                                              
+#define FW_CSL_LENG_Msk      (0x3FFFU << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
+#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */
+#define FW_NVDSSA_ADD_Pos    (8U)                                              
+#define FW_NVDSSA_ADD_Msk    (0xFFFFU << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
+#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG_Pos    (8U)                                              
+#define FW_NVDSL_LENG_Msk    (0x3FFFU << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
+#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD_Pos     (6U)                                              
+#define FW_VDSSA_ADD_Msk     (0x7FFU << FW_VDSSA_ADD_Pos)                      /*!< 0x0001FFC0 */
+#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG_Pos     (6U)                                              
+#define FW_VDSL_LENG_Msk     (0x7FFU << FW_VDSL_LENG_Pos)                      /*!< 0x0001FFC0 */
+#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */
+
+/**************************Bit definition for CR register *********************/
+#define FW_CR_FPA_Pos        (0U)                                              
+#define FW_CR_FPA_Msk        (0x1U << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
+#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/
+#define FW_CR_VDS_Pos        (1U)                                              
+#define FW_CR_VDS_Msk        (0x1U << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
+#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/
+#define FW_CR_VDE_Pos        (2U)                                              
+#define FW_CR_VDE_Msk        (0x1U << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
+#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR1 register  ********************/
+
+#define PWR_CR1_LPR_Pos              (14U)                                     
+#define PWR_CR1_LPR_Msk              (0x1U << PWR_CR1_LPR_Pos)                 /*!< 0x00004000 */
+#define PWR_CR1_LPR                  PWR_CR1_LPR_Msk                           /*!< Regulator low-power mode */
+#define PWR_CR1_VOS_Pos              (9U)                                      
+#define PWR_CR1_VOS_Msk              (0x3U << PWR_CR1_VOS_Pos)                 /*!< 0x00000600 */
+#define PWR_CR1_VOS                  PWR_CR1_VOS_Msk                           /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR1_VOS_0                (0x1U << PWR_CR1_VOS_Pos)                 /*!< 0x00000200 */
+#define PWR_CR1_VOS_1                (0x2U << PWR_CR1_VOS_Pos)                 /*!< 0x00000400 */
+#define PWR_CR1_DBP_Pos              (8U)                                      
+#define PWR_CR1_DBP_Msk              (0x1U << PWR_CR1_DBP_Pos)                 /*!< 0x00000100 */
+#define PWR_CR1_DBP                  PWR_CR1_DBP_Msk                           /*!< Disable Back-up domain Protection */
+#define PWR_CR1_LPMS_Pos             (0U)                                      
+#define PWR_CR1_LPMS_Msk             (0x7U << PWR_CR1_LPMS_Pos)                /*!< 0x00000007 */
+#define PWR_CR1_LPMS                 PWR_CR1_LPMS_Msk                          /*!< Low-power mode selection field */
+#define PWR_CR1_LPMS_STOP0           (0x00000000U)                             /*!< Stop 0 mode */
+#define PWR_CR1_LPMS_STOP1_Pos       (0U)                                      
+#define PWR_CR1_LPMS_STOP1_Msk       (0x1U << PWR_CR1_LPMS_STOP1_Pos)          /*!< 0x00000001 */
+#define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_Msk                    /*!< Stop 1 mode */
+#define PWR_CR1_LPMS_STOP2_Pos       (1U)                                      
+#define PWR_CR1_LPMS_STOP2_Msk       (0x1U << PWR_CR1_LPMS_STOP2_Pos)          /*!< 0x00000002 */
+#define PWR_CR1_LPMS_STOP2           PWR_CR1_LPMS_STOP2_Msk                    /*!< Stop 2 mode */
+#define PWR_CR1_LPMS_STANDBY_Pos     (0U)                                      
+#define PWR_CR1_LPMS_STANDBY_Msk     (0x3U << PWR_CR1_LPMS_STANDBY_Pos)        /*!< 0x00000003 */
+#define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_Msk                  /*!< Stand-by mode */
+#define PWR_CR1_LPMS_SHUTDOWN_Pos    (2U)                                      
+#define PWR_CR1_LPMS_SHUTDOWN_Msk    (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos)       /*!< 0x00000004 */
+#define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_Msk                 /*!< Shut-down mode */
+
+
+/********************  Bit definition for PWR_CR2 register  ********************/
+#define PWR_CR2_USV_Pos              (10U)                                     
+#define PWR_CR2_USV_Msk              (0x1U << PWR_CR2_USV_Pos)                 /*!< 0x00000400 */
+#define PWR_CR2_USV                  PWR_CR2_USV_Msk                           /*!< VDD USB Supply Valid */
+#define PWR_CR2_IOSV_Pos             (9U)                                      
+#define PWR_CR2_IOSV_Msk             (0x1U << PWR_CR2_IOSV_Pos)                /*!< 0x00000200 */
+#define PWR_CR2_IOSV                 PWR_CR2_IOSV_Msk                          /*!< VDD IO2 independent I/Os Supply Valid */
+/*!< PVME  Peripheral Voltage Monitor Enable */
+#define PWR_CR2_PVME_Pos             (4U)                                      
+#define PWR_CR2_PVME_Msk             (0xFU << PWR_CR2_PVME_Pos)                /*!< 0x000000F0 */
+#define PWR_CR2_PVME                 PWR_CR2_PVME_Msk                          /*!< PVM bits field */
+#define PWR_CR2_PVME4_Pos            (7U)                                      
+#define PWR_CR2_PVME4_Msk            (0x1U << PWR_CR2_PVME4_Pos)               /*!< 0x00000080 */
+#define PWR_CR2_PVME4                PWR_CR2_PVME4_Msk                         /*!< PVM 4 Enable */
+#define PWR_CR2_PVME3_Pos            (6U)                                      
+#define PWR_CR2_PVME3_Msk            (0x1U << PWR_CR2_PVME3_Pos)               /*!< 0x00000040 */
+#define PWR_CR2_PVME3                PWR_CR2_PVME3_Msk                         /*!< PVM 3 Enable */
+#define PWR_CR2_PVME2_Pos            (5U)                                      
+#define PWR_CR2_PVME2_Msk            (0x1U << PWR_CR2_PVME2_Pos)               /*!< 0x00000020 */
+#define PWR_CR2_PVME2                PWR_CR2_PVME2_Msk                         /*!< PVM 2 Enable */
+#define PWR_CR2_PVME1_Pos            (4U)                                      
+#define PWR_CR2_PVME1_Msk            (0x1U << PWR_CR2_PVME1_Pos)               /*!< 0x00000010 */
+#define PWR_CR2_PVME1                PWR_CR2_PVME1_Msk                         /*!< PVM 1 Enable */
+/*!< PVD level configuration */
+#define PWR_CR2_PLS_Pos              (1U)                                      
+#define PWR_CR2_PLS_Msk              (0x7U << PWR_CR2_PLS_Pos)                 /*!< 0x0000000E */
+#define PWR_CR2_PLS                  PWR_CR2_PLS_Msk                           /*!< PVD level selection */
+#define PWR_CR2_PLS_LEV0             (0x00000000U)                             /*!< PVD level 0 */
+#define PWR_CR2_PLS_LEV1_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV1_Msk         (0x1U << PWR_CR2_PLS_LEV1_Pos)            /*!< 0x00000002 */
+#define PWR_CR2_PLS_LEV1             PWR_CR2_PLS_LEV1_Msk                      /*!< PVD level 1 */
+#define PWR_CR2_PLS_LEV2_Pos         (2U)                                      
+#define PWR_CR2_PLS_LEV2_Msk         (0x1U << PWR_CR2_PLS_LEV2_Pos)            /*!< 0x00000004 */
+#define PWR_CR2_PLS_LEV2             PWR_CR2_PLS_LEV2_Msk                      /*!< PVD level 2 */
+#define PWR_CR2_PLS_LEV3_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV3_Msk         (0x3U << PWR_CR2_PLS_LEV3_Pos)            /*!< 0x00000006 */
+#define PWR_CR2_PLS_LEV3             PWR_CR2_PLS_LEV3_Msk                      /*!< PVD level 3 */
+#define PWR_CR2_PLS_LEV4_Pos         (3U)                                      
+#define PWR_CR2_PLS_LEV4_Msk         (0x1U << PWR_CR2_PLS_LEV4_Pos)            /*!< 0x00000008 */
+#define PWR_CR2_PLS_LEV4             PWR_CR2_PLS_LEV4_Msk                      /*!< PVD level 4 */
+#define PWR_CR2_PLS_LEV5_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV5_Msk         (0x5U << PWR_CR2_PLS_LEV5_Pos)            /*!< 0x0000000A */
+#define PWR_CR2_PLS_LEV5             PWR_CR2_PLS_LEV5_Msk                      /*!< PVD level 5 */
+#define PWR_CR2_PLS_LEV6_Pos         (2U)                                      
+#define PWR_CR2_PLS_LEV6_Msk         (0x3U << PWR_CR2_PLS_LEV6_Pos)            /*!< 0x0000000C */
+#define PWR_CR2_PLS_LEV6             PWR_CR2_PLS_LEV6_Msk                      /*!< PVD level 6 */
+#define PWR_CR2_PLS_LEV7_Pos         (1U)                                      
+#define PWR_CR2_PLS_LEV7_Msk         (0x7U << PWR_CR2_PLS_LEV7_Pos)            /*!< 0x0000000E */
+#define PWR_CR2_PLS_LEV7             PWR_CR2_PLS_LEV7_Msk                      /*!< PVD level 7 */
+#define PWR_CR2_PVDE_Pos             (0U)                                      
+#define PWR_CR2_PVDE_Msk             (0x1U << PWR_CR2_PVDE_Pos)                /*!< 0x00000001 */
+#define PWR_CR2_PVDE                 PWR_CR2_PVDE_Msk                          /*!< Power Voltage Detector Enable */
+
+/********************  Bit definition for PWR_CR3 register  ********************/
+#define PWR_CR3_EIWF_Pos             (15U)                                     
+#define PWR_CR3_EIWF_Msk             (0x1U << PWR_CR3_EIWF_Pos)                /*!< 0x00008000 */
+#define PWR_CR3_EIWF                 PWR_CR3_EIWF_Msk                          /*!< Enable Internal Wake-up line */
+#define PWR_CR3_APC_Pos              (10U)                                     
+#define PWR_CR3_APC_Msk              (0x1U << PWR_CR3_APC_Pos)                 /*!< 0x00000400 */
+#define PWR_CR3_APC                  PWR_CR3_APC_Msk                           /*!< Apply pull-up and pull-down configuration */
+#define PWR_CR3_RRS_Pos              (8U)                                      
+#define PWR_CR3_RRS_Msk              (0x1U << PWR_CR3_RRS_Pos)                 /*!< 0x00000100 */
+#define PWR_CR3_RRS                  PWR_CR3_RRS_Msk                           /*!< SRAM2 Retention in Stand-by mode */
+#define PWR_CR3_EWUP5_Pos            (4U)                                      
+#define PWR_CR3_EWUP5_Msk            (0x1U << PWR_CR3_EWUP5_Pos)               /*!< 0x00000010 */
+#define PWR_CR3_EWUP5                PWR_CR3_EWUP5_Msk                         /*!< Enable Wake-Up Pin 5 */
+#define PWR_CR3_EWUP4_Pos            (3U)                                      
+#define PWR_CR3_EWUP4_Msk            (0x1U << PWR_CR3_EWUP4_Pos)               /*!< 0x00000008 */
+#define PWR_CR3_EWUP4                PWR_CR3_EWUP4_Msk                         /*!< Enable Wake-Up Pin 4 */
+#define PWR_CR3_EWUP3_Pos            (2U)                                      
+#define PWR_CR3_EWUP3_Msk            (0x1U << PWR_CR3_EWUP3_Pos)               /*!< 0x00000004 */
+#define PWR_CR3_EWUP3                PWR_CR3_EWUP3_Msk                         /*!< Enable Wake-Up Pin 3 */
+#define PWR_CR3_EWUP2_Pos            (1U)                                      
+#define PWR_CR3_EWUP2_Msk            (0x1U << PWR_CR3_EWUP2_Pos)               /*!< 0x00000002 */
+#define PWR_CR3_EWUP2                PWR_CR3_EWUP2_Msk                         /*!< Enable Wake-Up Pin 2 */
+#define PWR_CR3_EWUP1_Pos            (0U)                                      
+#define PWR_CR3_EWUP1_Msk            (0x1U << PWR_CR3_EWUP1_Pos)               /*!< 0x00000001 */
+#define PWR_CR3_EWUP1                PWR_CR3_EWUP1_Msk                         /*!< Enable Wake-Up Pin 1 */
+#define PWR_CR3_EWUP_Pos             (0U)                                      
+#define PWR_CR3_EWUP_Msk             (0x1FU << PWR_CR3_EWUP_Pos)               /*!< 0x0000001F */
+#define PWR_CR3_EWUP                 PWR_CR3_EWUP_Msk                          /*!< Enable Wake-Up Pins  */
+
+/********************  Bit definition for PWR_CR4 register  ********************/
+#define PWR_CR4_VBRS_Pos             (9U)                                      
+#define PWR_CR4_VBRS_Msk             (0x1U << PWR_CR4_VBRS_Pos)                /*!< 0x00000200 */
+#define PWR_CR4_VBRS                 PWR_CR4_VBRS_Msk                          /*!< VBAT Battery charging Resistor Selection */
+#define PWR_CR4_VBE_Pos              (8U)                                      
+#define PWR_CR4_VBE_Msk              (0x1U << PWR_CR4_VBE_Pos)                 /*!< 0x00000100 */
+#define PWR_CR4_VBE                  PWR_CR4_VBE_Msk                           /*!< VBAT Battery charging Enable  */
+#define PWR_CR4_WP5_Pos              (4U)                                      
+#define PWR_CR4_WP5_Msk              (0x1U << PWR_CR4_WP5_Pos)                 /*!< 0x00000010 */
+#define PWR_CR4_WP5                  PWR_CR4_WP5_Msk                           /*!< Wake-Up Pin 5 polarity */
+#define PWR_CR4_WP4_Pos              (3U)                                      
+#define PWR_CR4_WP4_Msk              (0x1U << PWR_CR4_WP4_Pos)                 /*!< 0x00000008 */
+#define PWR_CR4_WP4                  PWR_CR4_WP4_Msk                           /*!< Wake-Up Pin 4 polarity */
+#define PWR_CR4_WP3_Pos              (2U)                                      
+#define PWR_CR4_WP3_Msk              (0x1U << PWR_CR4_WP3_Pos)                 /*!< 0x00000004 */
+#define PWR_CR4_WP3                  PWR_CR4_WP3_Msk                           /*!< Wake-Up Pin 3 polarity */
+#define PWR_CR4_WP2_Pos              (1U)                                      
+#define PWR_CR4_WP2_Msk              (0x1U << PWR_CR4_WP2_Pos)                 /*!< 0x00000002 */
+#define PWR_CR4_WP2                  PWR_CR4_WP2_Msk                           /*!< Wake-Up Pin 2 polarity */
+#define PWR_CR4_WP1_Pos              (0U)                                      
+#define PWR_CR4_WP1_Msk              (0x1U << PWR_CR4_WP1_Pos)                 /*!< 0x00000001 */
+#define PWR_CR4_WP1                  PWR_CR4_WP1_Msk                           /*!< Wake-Up Pin 1 polarity */
+
+/********************  Bit definition for PWR_SR1 register  ********************/
+#define PWR_SR1_WUFI_Pos             (15U)                                     
+#define PWR_SR1_WUFI_Msk             (0x1U << PWR_SR1_WUFI_Pos)                /*!< 0x00008000 */
+#define PWR_SR1_WUFI                 PWR_SR1_WUFI_Msk                          /*!< Wake-Up Flag Internal */
+#define PWR_SR1_SBF_Pos              (8U)                                      
+#define PWR_SR1_SBF_Msk              (0x1U << PWR_SR1_SBF_Pos)                 /*!< 0x00000100 */
+#define PWR_SR1_SBF                  PWR_SR1_SBF_Msk                           /*!< Stand-By Flag */
+#define PWR_SR1_WUF_Pos              (0U)                                      
+#define PWR_SR1_WUF_Msk              (0x1FU << PWR_SR1_WUF_Pos)                /*!< 0x0000001F */
+#define PWR_SR1_WUF                  PWR_SR1_WUF_Msk                           /*!< Wake-up Flags */
+#define PWR_SR1_WUF5_Pos             (4U)                                      
+#define PWR_SR1_WUF5_Msk             (0x1U << PWR_SR1_WUF5_Pos)                /*!< 0x00000010 */
+#define PWR_SR1_WUF5                 PWR_SR1_WUF5_Msk                          /*!< Wake-up Flag 5 */
+#define PWR_SR1_WUF4_Pos             (3U)                                      
+#define PWR_SR1_WUF4_Msk             (0x1U << PWR_SR1_WUF4_Pos)                /*!< 0x00000008 */
+#define PWR_SR1_WUF4                 PWR_SR1_WUF4_Msk                          /*!< Wake-up Flag 4 */
+#define PWR_SR1_WUF3_Pos             (2U)                                      
+#define PWR_SR1_WUF3_Msk             (0x1U << PWR_SR1_WUF3_Pos)                /*!< 0x00000004 */
+#define PWR_SR1_WUF3                 PWR_SR1_WUF3_Msk                          /*!< Wake-up Flag 3 */
+#define PWR_SR1_WUF2_Pos             (1U)                                      
+#define PWR_SR1_WUF2_Msk             (0x1U << PWR_SR1_WUF2_Pos)                /*!< 0x00000002 */
+#define PWR_SR1_WUF2                 PWR_SR1_WUF2_Msk                          /*!< Wake-up Flag 2 */
+#define PWR_SR1_WUF1_Pos             (0U)                                      
+#define PWR_SR1_WUF1_Msk             (0x1U << PWR_SR1_WUF1_Pos)                /*!< 0x00000001 */
+#define PWR_SR1_WUF1                 PWR_SR1_WUF1_Msk                          /*!< Wake-up Flag 1 */
+
+/********************  Bit definition for PWR_SR2 register  ********************/
+#define PWR_SR2_PVMO4_Pos            (15U)                                     
+#define PWR_SR2_PVMO4_Msk            (0x1U << PWR_SR2_PVMO4_Pos)               /*!< 0x00008000 */
+#define PWR_SR2_PVMO4                PWR_SR2_PVMO4_Msk                         /*!< Peripheral Voltage Monitoring Output 4 */
+#define PWR_SR2_PVMO3_Pos            (14U)                                     
+#define PWR_SR2_PVMO3_Msk            (0x1U << PWR_SR2_PVMO3_Pos)               /*!< 0x00004000 */
+#define PWR_SR2_PVMO3                PWR_SR2_PVMO3_Msk                         /*!< Peripheral Voltage Monitoring Output 3 */
+#define PWR_SR2_PVMO2_Pos            (13U)                                     
+#define PWR_SR2_PVMO2_Msk            (0x1U << PWR_SR2_PVMO2_Pos)               /*!< 0x00002000 */
+#define PWR_SR2_PVMO2                PWR_SR2_PVMO2_Msk                         /*!< Peripheral Voltage Monitoring Output 2 */
+#define PWR_SR2_PVMO1_Pos            (12U)                                     
+#define PWR_SR2_PVMO1_Msk            (0x1U << PWR_SR2_PVMO1_Pos)               /*!< 0x00001000 */
+#define PWR_SR2_PVMO1                PWR_SR2_PVMO1_Msk                         /*!< Peripheral Voltage Monitoring Output 1 */
+#define PWR_SR2_PVDO_Pos             (11U)                                     
+#define PWR_SR2_PVDO_Msk             (0x1U << PWR_SR2_PVDO_Pos)                /*!< 0x00000800 */
+#define PWR_SR2_PVDO                 PWR_SR2_PVDO_Msk                          /*!< Power Voltage Detector Output */
+#define PWR_SR2_VOSF_Pos             (10U)                                     
+#define PWR_SR2_VOSF_Msk             (0x1U << PWR_SR2_VOSF_Pos)                /*!< 0x00000400 */
+#define PWR_SR2_VOSF                 PWR_SR2_VOSF_Msk                          /*!< Voltage Scaling Flag */
+#define PWR_SR2_REGLPF_Pos           (9U)                                      
+#define PWR_SR2_REGLPF_Msk           (0x1U << PWR_SR2_REGLPF_Pos)              /*!< 0x00000200 */
+#define PWR_SR2_REGLPF               PWR_SR2_REGLPF_Msk                        /*!< Low-power Regulator Flag */
+#define PWR_SR2_REGLPS_Pos           (8U)                                      
+#define PWR_SR2_REGLPS_Msk           (0x1U << PWR_SR2_REGLPS_Pos)              /*!< 0x00000100 */
+#define PWR_SR2_REGLPS               PWR_SR2_REGLPS_Msk                        /*!< Low-power Regulator Started */
+
+/********************  Bit definition for PWR_SCR register  ********************/
+#define PWR_SCR_CSBF_Pos             (8U)                                      
+#define PWR_SCR_CSBF_Msk             (0x1U << PWR_SCR_CSBF_Pos)                /*!< 0x00000100 */
+#define PWR_SCR_CSBF                 PWR_SCR_CSBF_Msk                          /*!< Clear Stand-By Flag */
+#define PWR_SCR_CWUF_Pos             (0U)                                      
+#define PWR_SCR_CWUF_Msk             (0x1FU << PWR_SCR_CWUF_Pos)               /*!< 0x0000001F */
+#define PWR_SCR_CWUF                 PWR_SCR_CWUF_Msk                          /*!< Clear Wake-up Flags  */
+#define PWR_SCR_CWUF5_Pos            (4U)                                      
+#define PWR_SCR_CWUF5_Msk            (0x1U << PWR_SCR_CWUF5_Pos)               /*!< 0x00000010 */
+#define PWR_SCR_CWUF5                PWR_SCR_CWUF5_Msk                         /*!< Clear Wake-up Flag 5 */
+#define PWR_SCR_CWUF4_Pos            (3U)                                      
+#define PWR_SCR_CWUF4_Msk            (0x1U << PWR_SCR_CWUF4_Pos)               /*!< 0x00000008 */
+#define PWR_SCR_CWUF4                PWR_SCR_CWUF4_Msk                         /*!< Clear Wake-up Flag 4 */
+#define PWR_SCR_CWUF3_Pos            (2U)                                      
+#define PWR_SCR_CWUF3_Msk            (0x1U << PWR_SCR_CWUF3_Pos)               /*!< 0x00000004 */
+#define PWR_SCR_CWUF3                PWR_SCR_CWUF3_Msk                         /*!< Clear Wake-up Flag 3 */
+#define PWR_SCR_CWUF2_Pos            (1U)                                      
+#define PWR_SCR_CWUF2_Msk            (0x1U << PWR_SCR_CWUF2_Pos)               /*!< 0x00000002 */
+#define PWR_SCR_CWUF2                PWR_SCR_CWUF2_Msk                         /*!< Clear Wake-up Flag 2 */
+#define PWR_SCR_CWUF1_Pos            (0U)                                      
+#define PWR_SCR_CWUF1_Msk            (0x1U << PWR_SCR_CWUF1_Pos)               /*!< 0x00000001 */
+#define PWR_SCR_CWUF1                PWR_SCR_CWUF1_Msk                         /*!< Clear Wake-up Flag 1 */
+
+/********************  Bit definition for PWR_PUCRA register  ********************/
+#define PWR_PUCRA_PA15_Pos           (15U)                                     
+#define PWR_PUCRA_PA15_Msk           (0x1U << PWR_PUCRA_PA15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRA_PA15               PWR_PUCRA_PA15_Msk                        /*!< Port PA15 Pull-Up set */
+#define PWR_PUCRA_PA13_Pos           (13U)                                     
+#define PWR_PUCRA_PA13_Msk           (0x1U << PWR_PUCRA_PA13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRA_PA13               PWR_PUCRA_PA13_Msk                        /*!< Port PA13 Pull-Up set */
+#define PWR_PUCRA_PA12_Pos           (12U)                                     
+#define PWR_PUCRA_PA12_Msk           (0x1U << PWR_PUCRA_PA12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRA_PA12               PWR_PUCRA_PA12_Msk                        /*!< Port PA12 Pull-Up set */
+#define PWR_PUCRA_PA11_Pos           (11U)                                     
+#define PWR_PUCRA_PA11_Msk           (0x1U << PWR_PUCRA_PA11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRA_PA11               PWR_PUCRA_PA11_Msk                        /*!< Port PA11 Pull-Up set */
+#define PWR_PUCRA_PA10_Pos           (10U)                                     
+#define PWR_PUCRA_PA10_Msk           (0x1U << PWR_PUCRA_PA10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRA_PA10               PWR_PUCRA_PA10_Msk                        /*!< Port PA10 Pull-Up set */
+#define PWR_PUCRA_PA9_Pos            (9U)                                      
+#define PWR_PUCRA_PA9_Msk            (0x1U << PWR_PUCRA_PA9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRA_PA9                PWR_PUCRA_PA9_Msk                         /*!< Port PA9 Pull-Up set  */
+#define PWR_PUCRA_PA8_Pos            (8U)                                      
+#define PWR_PUCRA_PA8_Msk            (0x1U << PWR_PUCRA_PA8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRA_PA8                PWR_PUCRA_PA8_Msk                         /*!< Port PA8 Pull-Up set  */
+#define PWR_PUCRA_PA7_Pos            (7U)                                      
+#define PWR_PUCRA_PA7_Msk            (0x1U << PWR_PUCRA_PA7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRA_PA7                PWR_PUCRA_PA7_Msk                         /*!< Port PA7 Pull-Up set  */
+#define PWR_PUCRA_PA6_Pos            (6U)                                      
+#define PWR_PUCRA_PA6_Msk            (0x1U << PWR_PUCRA_PA6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRA_PA6                PWR_PUCRA_PA6_Msk                         /*!< Port PA6 Pull-Up set  */
+#define PWR_PUCRA_PA5_Pos            (5U)                                      
+#define PWR_PUCRA_PA5_Msk            (0x1U << PWR_PUCRA_PA5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRA_PA5                PWR_PUCRA_PA5_Msk                         /*!< Port PA5 Pull-Up set  */
+#define PWR_PUCRA_PA4_Pos            (4U)                                      
+#define PWR_PUCRA_PA4_Msk            (0x1U << PWR_PUCRA_PA4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRA_PA4                PWR_PUCRA_PA4_Msk                         /*!< Port PA4 Pull-Up set  */
+#define PWR_PUCRA_PA3_Pos            (3U)                                      
+#define PWR_PUCRA_PA3_Msk            (0x1U << PWR_PUCRA_PA3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRA_PA3                PWR_PUCRA_PA3_Msk                         /*!< Port PA3 Pull-Up set  */
+#define PWR_PUCRA_PA2_Pos            (2U)                                      
+#define PWR_PUCRA_PA2_Msk            (0x1U << PWR_PUCRA_PA2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRA_PA2                PWR_PUCRA_PA2_Msk                         /*!< Port PA2 Pull-Up set  */
+#define PWR_PUCRA_PA1_Pos            (1U)                                      
+#define PWR_PUCRA_PA1_Msk            (0x1U << PWR_PUCRA_PA1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRA_PA1                PWR_PUCRA_PA1_Msk                         /*!< Port PA1 Pull-Up set  */
+#define PWR_PUCRA_PA0_Pos            (0U)                                      
+#define PWR_PUCRA_PA0_Msk            (0x1U << PWR_PUCRA_PA0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRA_PA0                PWR_PUCRA_PA0_Msk                         /*!< Port PA0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRA register  ********************/
+#define PWR_PDCRA_PA14_Pos           (14U)                                     
+#define PWR_PDCRA_PA14_Msk           (0x1U << PWR_PDCRA_PA14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRA_PA14               PWR_PDCRA_PA14_Msk                        /*!< Port PA14 Pull-Down set */
+#define PWR_PDCRA_PA12_Pos           (12U)                                     
+#define PWR_PDCRA_PA12_Msk           (0x1U << PWR_PDCRA_PA12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRA_PA12               PWR_PDCRA_PA12_Msk                        /*!< Port PA12 Pull-Down set */
+#define PWR_PDCRA_PA11_Pos           (11U)                                     
+#define PWR_PDCRA_PA11_Msk           (0x1U << PWR_PDCRA_PA11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRA_PA11               PWR_PDCRA_PA11_Msk                        /*!< Port PA11 Pull-Down set */
+#define PWR_PDCRA_PA10_Pos           (10U)                                     
+#define PWR_PDCRA_PA10_Msk           (0x1U << PWR_PDCRA_PA10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRA_PA10               PWR_PDCRA_PA10_Msk                        /*!< Port PA10 Pull-Down set */
+#define PWR_PDCRA_PA9_Pos            (9U)                                      
+#define PWR_PDCRA_PA9_Msk            (0x1U << PWR_PDCRA_PA9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRA_PA9                PWR_PDCRA_PA9_Msk                         /*!< Port PA9 Pull-Down set  */
+#define PWR_PDCRA_PA8_Pos            (8U)                                      
+#define PWR_PDCRA_PA8_Msk            (0x1U << PWR_PDCRA_PA8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRA_PA8                PWR_PDCRA_PA8_Msk                         /*!< Port PA8 Pull-Down set  */
+#define PWR_PDCRA_PA7_Pos            (7U)                                      
+#define PWR_PDCRA_PA7_Msk            (0x1U << PWR_PDCRA_PA7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRA_PA7                PWR_PDCRA_PA7_Msk                         /*!< Port PA7 Pull-Down set  */
+#define PWR_PDCRA_PA6_Pos            (6U)                                      
+#define PWR_PDCRA_PA6_Msk            (0x1U << PWR_PDCRA_PA6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRA_PA6                PWR_PDCRA_PA6_Msk                         /*!< Port PA6 Pull-Down set  */
+#define PWR_PDCRA_PA5_Pos            (5U)                                      
+#define PWR_PDCRA_PA5_Msk            (0x1U << PWR_PDCRA_PA5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRA_PA5                PWR_PDCRA_PA5_Msk                         /*!< Port PA5 Pull-Down set  */
+#define PWR_PDCRA_PA4_Pos            (4U)                                      
+#define PWR_PDCRA_PA4_Msk            (0x1U << PWR_PDCRA_PA4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRA_PA4                PWR_PDCRA_PA4_Msk                         /*!< Port PA4 Pull-Down set  */
+#define PWR_PDCRA_PA3_Pos            (3U)                                      
+#define PWR_PDCRA_PA3_Msk            (0x1U << PWR_PDCRA_PA3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRA_PA3                PWR_PDCRA_PA3_Msk                         /*!< Port PA3 Pull-Down set  */
+#define PWR_PDCRA_PA2_Pos            (2U)                                      
+#define PWR_PDCRA_PA2_Msk            (0x1U << PWR_PDCRA_PA2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRA_PA2                PWR_PDCRA_PA2_Msk                         /*!< Port PA2 Pull-Down set  */
+#define PWR_PDCRA_PA1_Pos            (1U)                                      
+#define PWR_PDCRA_PA1_Msk            (0x1U << PWR_PDCRA_PA1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRA_PA1                PWR_PDCRA_PA1_Msk                         /*!< Port PA1 Pull-Down set  */
+#define PWR_PDCRA_PA0_Pos            (0U)                                      
+#define PWR_PDCRA_PA0_Msk            (0x1U << PWR_PDCRA_PA0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRA_PA0                PWR_PDCRA_PA0_Msk                         /*!< Port PA0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRB register  ********************/
+#define PWR_PUCRB_PB15_Pos           (15U)                                     
+#define PWR_PUCRB_PB15_Msk           (0x1U << PWR_PUCRB_PB15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRB_PB15               PWR_PUCRB_PB15_Msk                        /*!< Port PB15 Pull-Up set */
+#define PWR_PUCRB_PB14_Pos           (14U)                                     
+#define PWR_PUCRB_PB14_Msk           (0x1U << PWR_PUCRB_PB14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRB_PB14               PWR_PUCRB_PB14_Msk                        /*!< Port PB14 Pull-Up set */
+#define PWR_PUCRB_PB13_Pos           (13U)                                     
+#define PWR_PUCRB_PB13_Msk           (0x1U << PWR_PUCRB_PB13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRB_PB13               PWR_PUCRB_PB13_Msk                        /*!< Port PB13 Pull-Up set */
+#define PWR_PUCRB_PB12_Pos           (12U)                                     
+#define PWR_PUCRB_PB12_Msk           (0x1U << PWR_PUCRB_PB12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRB_PB12               PWR_PUCRB_PB12_Msk                        /*!< Port PB12 Pull-Up set */
+#define PWR_PUCRB_PB11_Pos           (11U)                                     
+#define PWR_PUCRB_PB11_Msk           (0x1U << PWR_PUCRB_PB11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRB_PB11               PWR_PUCRB_PB11_Msk                        /*!< Port PB11 Pull-Up set */
+#define PWR_PUCRB_PB10_Pos           (10U)                                     
+#define PWR_PUCRB_PB10_Msk           (0x1U << PWR_PUCRB_PB10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRB_PB10               PWR_PUCRB_PB10_Msk                        /*!< Port PB10 Pull-Up set */
+#define PWR_PUCRB_PB9_Pos            (9U)                                      
+#define PWR_PUCRB_PB9_Msk            (0x1U << PWR_PUCRB_PB9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRB_PB9                PWR_PUCRB_PB9_Msk                         /*!< Port PB9 Pull-Up set  */
+#define PWR_PUCRB_PB8_Pos            (8U)                                      
+#define PWR_PUCRB_PB8_Msk            (0x1U << PWR_PUCRB_PB8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRB_PB8                PWR_PUCRB_PB8_Msk                         /*!< Port PB8 Pull-Up set  */
+#define PWR_PUCRB_PB7_Pos            (7U)                                      
+#define PWR_PUCRB_PB7_Msk            (0x1U << PWR_PUCRB_PB7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRB_PB7                PWR_PUCRB_PB7_Msk                         /*!< Port PB7 Pull-Up set  */
+#define PWR_PUCRB_PB6_Pos            (6U)                                      
+#define PWR_PUCRB_PB6_Msk            (0x1U << PWR_PUCRB_PB6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRB_PB6                PWR_PUCRB_PB6_Msk                         /*!< Port PB6 Pull-Up set  */
+#define PWR_PUCRB_PB5_Pos            (5U)                                      
+#define PWR_PUCRB_PB5_Msk            (0x1U << PWR_PUCRB_PB5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRB_PB5                PWR_PUCRB_PB5_Msk                         /*!< Port PB5 Pull-Up set  */
+#define PWR_PUCRB_PB4_Pos            (4U)                                      
+#define PWR_PUCRB_PB4_Msk            (0x1U << PWR_PUCRB_PB4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRB_PB4                PWR_PUCRB_PB4_Msk                         /*!< Port PB4 Pull-Up set  */
+#define PWR_PUCRB_PB3_Pos            (3U)                                      
+#define PWR_PUCRB_PB3_Msk            (0x1U << PWR_PUCRB_PB3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRB_PB3                PWR_PUCRB_PB3_Msk                         /*!< Port PB3 Pull-Up set  */
+#define PWR_PUCRB_PB2_Pos            (2U)                                      
+#define PWR_PUCRB_PB2_Msk            (0x1U << PWR_PUCRB_PB2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRB_PB2                PWR_PUCRB_PB2_Msk                         /*!< Port PB2 Pull-Up set  */
+#define PWR_PUCRB_PB1_Pos            (1U)                                      
+#define PWR_PUCRB_PB1_Msk            (0x1U << PWR_PUCRB_PB1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRB_PB1                PWR_PUCRB_PB1_Msk                         /*!< Port PB1 Pull-Up set  */
+#define PWR_PUCRB_PB0_Pos            (0U)                                      
+#define PWR_PUCRB_PB0_Msk            (0x1U << PWR_PUCRB_PB0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRB_PB0                PWR_PUCRB_PB0_Msk                         /*!< Port PB0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRB register  ********************/
+#define PWR_PDCRB_PB15_Pos           (15U)                                     
+#define PWR_PDCRB_PB15_Msk           (0x1U << PWR_PDCRB_PB15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRB_PB15               PWR_PDCRB_PB15_Msk                        /*!< Port PB15 Pull-Down set */
+#define PWR_PDCRB_PB14_Pos           (14U)                                     
+#define PWR_PDCRB_PB14_Msk           (0x1U << PWR_PDCRB_PB14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRB_PB14               PWR_PDCRB_PB14_Msk                        /*!< Port PB14 Pull-Down set */
+#define PWR_PDCRB_PB13_Pos           (13U)                                     
+#define PWR_PDCRB_PB13_Msk           (0x1U << PWR_PDCRB_PB13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRB_PB13               PWR_PDCRB_PB13_Msk                        /*!< Port PB13 Pull-Down set */
+#define PWR_PDCRB_PB12_Pos           (12U)                                     
+#define PWR_PDCRB_PB12_Msk           (0x1U << PWR_PDCRB_PB12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRB_PB12               PWR_PDCRB_PB12_Msk                        /*!< Port PB12 Pull-Down set */
+#define PWR_PDCRB_PB11_Pos           (11U)                                     
+#define PWR_PDCRB_PB11_Msk           (0x1U << PWR_PDCRB_PB11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRB_PB11               PWR_PDCRB_PB11_Msk                        /*!< Port PB11 Pull-Down set */
+#define PWR_PDCRB_PB10_Pos           (10U)                                     
+#define PWR_PDCRB_PB10_Msk           (0x1U << PWR_PDCRB_PB10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRB_PB10               PWR_PDCRB_PB10_Msk                        /*!< Port PB10 Pull-Down set */
+#define PWR_PDCRB_PB9_Pos            (9U)                                      
+#define PWR_PDCRB_PB9_Msk            (0x1U << PWR_PDCRB_PB9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRB_PB9                PWR_PDCRB_PB9_Msk                         /*!< Port PB9 Pull-Down set  */
+#define PWR_PDCRB_PB8_Pos            (8U)                                      
+#define PWR_PDCRB_PB8_Msk            (0x1U << PWR_PDCRB_PB8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRB_PB8                PWR_PDCRB_PB8_Msk                         /*!< Port PB8 Pull-Down set  */
+#define PWR_PDCRB_PB7_Pos            (7U)                                      
+#define PWR_PDCRB_PB7_Msk            (0x1U << PWR_PDCRB_PB7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRB_PB7                PWR_PDCRB_PB7_Msk                         /*!< Port PB7 Pull-Down set  */
+#define PWR_PDCRB_PB6_Pos            (6U)                                      
+#define PWR_PDCRB_PB6_Msk            (0x1U << PWR_PDCRB_PB6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRB_PB6                PWR_PDCRB_PB6_Msk                         /*!< Port PB6 Pull-Down set  */
+#define PWR_PDCRB_PB5_Pos            (5U)                                      
+#define PWR_PDCRB_PB5_Msk            (0x1U << PWR_PDCRB_PB5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRB_PB5                PWR_PDCRB_PB5_Msk                         /*!< Port PB5 Pull-Down set  */
+#define PWR_PDCRB_PB3_Pos            (3U)                                      
+#define PWR_PDCRB_PB3_Msk            (0x1U << PWR_PDCRB_PB3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRB_PB3                PWR_PDCRB_PB3_Msk                         /*!< Port PB3 Pull-Down set  */
+#define PWR_PDCRB_PB2_Pos            (2U)                                      
+#define PWR_PDCRB_PB2_Msk            (0x1U << PWR_PDCRB_PB2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRB_PB2                PWR_PDCRB_PB2_Msk                         /*!< Port PB2 Pull-Down set  */
+#define PWR_PDCRB_PB1_Pos            (1U)                                      
+#define PWR_PDCRB_PB1_Msk            (0x1U << PWR_PDCRB_PB1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRB_PB1                PWR_PDCRB_PB1_Msk                         /*!< Port PB1 Pull-Down set  */
+#define PWR_PDCRB_PB0_Pos            (0U)                                      
+#define PWR_PDCRB_PB0_Msk            (0x1U << PWR_PDCRB_PB0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRB_PB0                PWR_PDCRB_PB0_Msk                         /*!< Port PB0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRC register  ********************/
+#define PWR_PUCRC_PC15_Pos           (15U)                                     
+#define PWR_PUCRC_PC15_Msk           (0x1U << PWR_PUCRC_PC15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRC_PC15               PWR_PUCRC_PC15_Msk                        /*!< Port PC15 Pull-Up set */
+#define PWR_PUCRC_PC14_Pos           (14U)                                     
+#define PWR_PUCRC_PC14_Msk           (0x1U << PWR_PUCRC_PC14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRC_PC14               PWR_PUCRC_PC14_Msk                        /*!< Port PC14 Pull-Up set */
+#define PWR_PUCRC_PC13_Pos           (13U)                                     
+#define PWR_PUCRC_PC13_Msk           (0x1U << PWR_PUCRC_PC13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRC_PC13               PWR_PUCRC_PC13_Msk                        /*!< Port PC13 Pull-Up set */
+#define PWR_PUCRC_PC12_Pos           (12U)                                     
+#define PWR_PUCRC_PC12_Msk           (0x1U << PWR_PUCRC_PC12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRC_PC12               PWR_PUCRC_PC12_Msk                        /*!< Port PC12 Pull-Up set */
+#define PWR_PUCRC_PC11_Pos           (11U)                                     
+#define PWR_PUCRC_PC11_Msk           (0x1U << PWR_PUCRC_PC11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRC_PC11               PWR_PUCRC_PC11_Msk                        /*!< Port PC11 Pull-Up set */
+#define PWR_PUCRC_PC10_Pos           (10U)                                     
+#define PWR_PUCRC_PC10_Msk           (0x1U << PWR_PUCRC_PC10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRC_PC10               PWR_PUCRC_PC10_Msk                        /*!< Port PC10 Pull-Up set */
+#define PWR_PUCRC_PC9_Pos            (9U)                                      
+#define PWR_PUCRC_PC9_Msk            (0x1U << PWR_PUCRC_PC9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRC_PC9                PWR_PUCRC_PC9_Msk                         /*!< Port PC9 Pull-Up set  */
+#define PWR_PUCRC_PC8_Pos            (8U)                                      
+#define PWR_PUCRC_PC8_Msk            (0x1U << PWR_PUCRC_PC8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRC_PC8                PWR_PUCRC_PC8_Msk                         /*!< Port PC8 Pull-Up set  */
+#define PWR_PUCRC_PC7_Pos            (7U)                                      
+#define PWR_PUCRC_PC7_Msk            (0x1U << PWR_PUCRC_PC7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRC_PC7                PWR_PUCRC_PC7_Msk                         /*!< Port PC7 Pull-Up set  */
+#define PWR_PUCRC_PC6_Pos            (6U)                                      
+#define PWR_PUCRC_PC6_Msk            (0x1U << PWR_PUCRC_PC6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRC_PC6                PWR_PUCRC_PC6_Msk                         /*!< Port PC6 Pull-Up set  */
+#define PWR_PUCRC_PC5_Pos            (5U)                                      
+#define PWR_PUCRC_PC5_Msk            (0x1U << PWR_PUCRC_PC5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRC_PC5                PWR_PUCRC_PC5_Msk                         /*!< Port PC5 Pull-Up set  */
+#define PWR_PUCRC_PC4_Pos            (4U)                                      
+#define PWR_PUCRC_PC4_Msk            (0x1U << PWR_PUCRC_PC4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRC_PC4                PWR_PUCRC_PC4_Msk                         /*!< Port PC4 Pull-Up set  */
+#define PWR_PUCRC_PC3_Pos            (3U)                                      
+#define PWR_PUCRC_PC3_Msk            (0x1U << PWR_PUCRC_PC3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRC_PC3                PWR_PUCRC_PC3_Msk                         /*!< Port PC3 Pull-Up set  */
+#define PWR_PUCRC_PC2_Pos            (2U)                                      
+#define PWR_PUCRC_PC2_Msk            (0x1U << PWR_PUCRC_PC2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRC_PC2                PWR_PUCRC_PC2_Msk                         /*!< Port PC2 Pull-Up set  */
+#define PWR_PUCRC_PC1_Pos            (1U)                                      
+#define PWR_PUCRC_PC1_Msk            (0x1U << PWR_PUCRC_PC1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRC_PC1                PWR_PUCRC_PC1_Msk                         /*!< Port PC1 Pull-Up set  */
+#define PWR_PUCRC_PC0_Pos            (0U)                                      
+#define PWR_PUCRC_PC0_Msk            (0x1U << PWR_PUCRC_PC0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRC_PC0                PWR_PUCRC_PC0_Msk                         /*!< Port PC0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRC register  ********************/
+#define PWR_PDCRC_PC15_Pos           (15U)                                     
+#define PWR_PDCRC_PC15_Msk           (0x1U << PWR_PDCRC_PC15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRC_PC15               PWR_PDCRC_PC15_Msk                        /*!< Port PC15 Pull-Down set */
+#define PWR_PDCRC_PC14_Pos           (14U)                                     
+#define PWR_PDCRC_PC14_Msk           (0x1U << PWR_PDCRC_PC14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRC_PC14               PWR_PDCRC_PC14_Msk                        /*!< Port PC14 Pull-Down set */
+#define PWR_PDCRC_PC13_Pos           (13U)                                     
+#define PWR_PDCRC_PC13_Msk           (0x1U << PWR_PDCRC_PC13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRC_PC13               PWR_PDCRC_PC13_Msk                        /*!< Port PC13 Pull-Down set */
+#define PWR_PDCRC_PC12_Pos           (12U)                                     
+#define PWR_PDCRC_PC12_Msk           (0x1U << PWR_PDCRC_PC12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRC_PC12               PWR_PDCRC_PC12_Msk                        /*!< Port PC12 Pull-Down set */
+#define PWR_PDCRC_PC11_Pos           (11U)                                     
+#define PWR_PDCRC_PC11_Msk           (0x1U << PWR_PDCRC_PC11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRC_PC11               PWR_PDCRC_PC11_Msk                        /*!< Port PC11 Pull-Down set */
+#define PWR_PDCRC_PC10_Pos           (10U)                                     
+#define PWR_PDCRC_PC10_Msk           (0x1U << PWR_PDCRC_PC10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRC_PC10               PWR_PDCRC_PC10_Msk                        /*!< Port PC10 Pull-Down set */
+#define PWR_PDCRC_PC9_Pos            (9U)                                      
+#define PWR_PDCRC_PC9_Msk            (0x1U << PWR_PDCRC_PC9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRC_PC9                PWR_PDCRC_PC9_Msk                         /*!< Port PC9 Pull-Down set  */
+#define PWR_PDCRC_PC8_Pos            (8U)                                      
+#define PWR_PDCRC_PC8_Msk            (0x1U << PWR_PDCRC_PC8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRC_PC8                PWR_PDCRC_PC8_Msk                         /*!< Port PC8 Pull-Down set  */
+#define PWR_PDCRC_PC7_Pos            (7U)                                      
+#define PWR_PDCRC_PC7_Msk            (0x1U << PWR_PDCRC_PC7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRC_PC7                PWR_PDCRC_PC7_Msk                         /*!< Port PC7 Pull-Down set  */
+#define PWR_PDCRC_PC6_Pos            (6U)                                      
+#define PWR_PDCRC_PC6_Msk            (0x1U << PWR_PDCRC_PC6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRC_PC6                PWR_PDCRC_PC6_Msk                         /*!< Port PC6 Pull-Down set  */
+#define PWR_PDCRC_PC5_Pos            (5U)                                      
+#define PWR_PDCRC_PC5_Msk            (0x1U << PWR_PDCRC_PC5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRC_PC5                PWR_PDCRC_PC5_Msk                         /*!< Port PC5 Pull-Down set  */
+#define PWR_PDCRC_PC4_Pos            (4U)                                      
+#define PWR_PDCRC_PC4_Msk            (0x1U << PWR_PDCRC_PC4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRC_PC4                PWR_PDCRC_PC4_Msk                         /*!< Port PC4 Pull-Down set  */
+#define PWR_PDCRC_PC3_Pos            (3U)                                      
+#define PWR_PDCRC_PC3_Msk            (0x1U << PWR_PDCRC_PC3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRC_PC3                PWR_PDCRC_PC3_Msk                         /*!< Port PC3 Pull-Down set  */
+#define PWR_PDCRC_PC2_Pos            (2U)                                      
+#define PWR_PDCRC_PC2_Msk            (0x1U << PWR_PDCRC_PC2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRC_PC2                PWR_PDCRC_PC2_Msk                         /*!< Port PC2 Pull-Down set  */
+#define PWR_PDCRC_PC1_Pos            (1U)                                      
+#define PWR_PDCRC_PC1_Msk            (0x1U << PWR_PDCRC_PC1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRC_PC1                PWR_PDCRC_PC1_Msk                         /*!< Port PC1 Pull-Down set  */
+#define PWR_PDCRC_PC0_Pos            (0U)                                      
+#define PWR_PDCRC_PC0_Msk            (0x1U << PWR_PDCRC_PC0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRC_PC0                PWR_PDCRC_PC0_Msk                         /*!< Port PC0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRD register  ********************/
+#define PWR_PUCRD_PD15_Pos           (15U)                                     
+#define PWR_PUCRD_PD15_Msk           (0x1U << PWR_PUCRD_PD15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRD_PD15               PWR_PUCRD_PD15_Msk                        /*!< Port PD15 Pull-Up set */
+#define PWR_PUCRD_PD14_Pos           (14U)                                     
+#define PWR_PUCRD_PD14_Msk           (0x1U << PWR_PUCRD_PD14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRD_PD14               PWR_PUCRD_PD14_Msk                        /*!< Port PD14 Pull-Up set */
+#define PWR_PUCRD_PD13_Pos           (13U)                                     
+#define PWR_PUCRD_PD13_Msk           (0x1U << PWR_PUCRD_PD13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRD_PD13               PWR_PUCRD_PD13_Msk                        /*!< Port PD13 Pull-Up set */
+#define PWR_PUCRD_PD12_Pos           (12U)                                     
+#define PWR_PUCRD_PD12_Msk           (0x1U << PWR_PUCRD_PD12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRD_PD12               PWR_PUCRD_PD12_Msk                        /*!< Port PD12 Pull-Up set */
+#define PWR_PUCRD_PD11_Pos           (11U)                                     
+#define PWR_PUCRD_PD11_Msk           (0x1U << PWR_PUCRD_PD11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRD_PD11               PWR_PUCRD_PD11_Msk                        /*!< Port PD11 Pull-Up set */
+#define PWR_PUCRD_PD10_Pos           (10U)                                     
+#define PWR_PUCRD_PD10_Msk           (0x1U << PWR_PUCRD_PD10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRD_PD10               PWR_PUCRD_PD10_Msk                        /*!< Port PD10 Pull-Up set */
+#define PWR_PUCRD_PD9_Pos            (9U)                                      
+#define PWR_PUCRD_PD9_Msk            (0x1U << PWR_PUCRD_PD9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRD_PD9                PWR_PUCRD_PD9_Msk                         /*!< Port PD9 Pull-Up set  */
+#define PWR_PUCRD_PD8_Pos            (8U)                                      
+#define PWR_PUCRD_PD8_Msk            (0x1U << PWR_PUCRD_PD8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRD_PD8                PWR_PUCRD_PD8_Msk                         /*!< Port PD8 Pull-Up set  */
+#define PWR_PUCRD_PD7_Pos            (7U)                                      
+#define PWR_PUCRD_PD7_Msk            (0x1U << PWR_PUCRD_PD7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRD_PD7                PWR_PUCRD_PD7_Msk                         /*!< Port PD7 Pull-Up set  */
+#define PWR_PUCRD_PD6_Pos            (6U)                                      
+#define PWR_PUCRD_PD6_Msk            (0x1U << PWR_PUCRD_PD6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRD_PD6                PWR_PUCRD_PD6_Msk                         /*!< Port PD6 Pull-Up set  */
+#define PWR_PUCRD_PD5_Pos            (5U)                                      
+#define PWR_PUCRD_PD5_Msk            (0x1U << PWR_PUCRD_PD5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRD_PD5                PWR_PUCRD_PD5_Msk                         /*!< Port PD5 Pull-Up set  */
+#define PWR_PUCRD_PD4_Pos            (4U)                                      
+#define PWR_PUCRD_PD4_Msk            (0x1U << PWR_PUCRD_PD4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRD_PD4                PWR_PUCRD_PD4_Msk                         /*!< Port PD4 Pull-Up set  */
+#define PWR_PUCRD_PD3_Pos            (3U)                                      
+#define PWR_PUCRD_PD3_Msk            (0x1U << PWR_PUCRD_PD3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRD_PD3                PWR_PUCRD_PD3_Msk                         /*!< Port PD3 Pull-Up set  */
+#define PWR_PUCRD_PD2_Pos            (2U)                                      
+#define PWR_PUCRD_PD2_Msk            (0x1U << PWR_PUCRD_PD2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRD_PD2                PWR_PUCRD_PD2_Msk                         /*!< Port PD2 Pull-Up set  */
+#define PWR_PUCRD_PD1_Pos            (1U)                                      
+#define PWR_PUCRD_PD1_Msk            (0x1U << PWR_PUCRD_PD1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRD_PD1                PWR_PUCRD_PD1_Msk                         /*!< Port PD1 Pull-Up set  */
+#define PWR_PUCRD_PD0_Pos            (0U)                                      
+#define PWR_PUCRD_PD0_Msk            (0x1U << PWR_PUCRD_PD0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRD_PD0                PWR_PUCRD_PD0_Msk                         /*!< Port PD0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRD register  ********************/
+#define PWR_PDCRD_PD15_Pos           (15U)                                     
+#define PWR_PDCRD_PD15_Msk           (0x1U << PWR_PDCRD_PD15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRD_PD15               PWR_PDCRD_PD15_Msk                        /*!< Port PD15 Pull-Down set */
+#define PWR_PDCRD_PD14_Pos           (14U)                                     
+#define PWR_PDCRD_PD14_Msk           (0x1U << PWR_PDCRD_PD14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRD_PD14               PWR_PDCRD_PD14_Msk                        /*!< Port PD14 Pull-Down set */
+#define PWR_PDCRD_PD13_Pos           (13U)                                     
+#define PWR_PDCRD_PD13_Msk           (0x1U << PWR_PDCRD_PD13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRD_PD13               PWR_PDCRD_PD13_Msk                        /*!< Port PD13 Pull-Down set */
+#define PWR_PDCRD_PD12_Pos           (12U)                                     
+#define PWR_PDCRD_PD12_Msk           (0x1U << PWR_PDCRD_PD12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRD_PD12               PWR_PDCRD_PD12_Msk                        /*!< Port PD12 Pull-Down set */
+#define PWR_PDCRD_PD11_Pos           (11U)                                     
+#define PWR_PDCRD_PD11_Msk           (0x1U << PWR_PDCRD_PD11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRD_PD11               PWR_PDCRD_PD11_Msk                        /*!< Port PD11 Pull-Down set */
+#define PWR_PDCRD_PD10_Pos           (10U)                                     
+#define PWR_PDCRD_PD10_Msk           (0x1U << PWR_PDCRD_PD10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRD_PD10               PWR_PDCRD_PD10_Msk                        /*!< Port PD10 Pull-Down set */
+#define PWR_PDCRD_PD9_Pos            (9U)                                      
+#define PWR_PDCRD_PD9_Msk            (0x1U << PWR_PDCRD_PD9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRD_PD9                PWR_PDCRD_PD9_Msk                         /*!< Port PD9 Pull-Down set  */
+#define PWR_PDCRD_PD8_Pos            (8U)                                      
+#define PWR_PDCRD_PD8_Msk            (0x1U << PWR_PDCRD_PD8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRD_PD8                PWR_PDCRD_PD8_Msk                         /*!< Port PD8 Pull-Down set  */
+#define PWR_PDCRD_PD7_Pos            (7U)                                      
+#define PWR_PDCRD_PD7_Msk            (0x1U << PWR_PDCRD_PD7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRD_PD7                PWR_PDCRD_PD7_Msk                         /*!< Port PD7 Pull-Down set  */
+#define PWR_PDCRD_PD6_Pos            (6U)                                      
+#define PWR_PDCRD_PD6_Msk            (0x1U << PWR_PDCRD_PD6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRD_PD6                PWR_PDCRD_PD6_Msk                         /*!< Port PD6 Pull-Down set  */
+#define PWR_PDCRD_PD5_Pos            (5U)                                      
+#define PWR_PDCRD_PD5_Msk            (0x1U << PWR_PDCRD_PD5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRD_PD5                PWR_PDCRD_PD5_Msk                         /*!< Port PD5 Pull-Down set  */
+#define PWR_PDCRD_PD4_Pos            (4U)                                      
+#define PWR_PDCRD_PD4_Msk            (0x1U << PWR_PDCRD_PD4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRD_PD4                PWR_PDCRD_PD4_Msk                         /*!< Port PD4 Pull-Down set  */
+#define PWR_PDCRD_PD3_Pos            (3U)                                      
+#define PWR_PDCRD_PD3_Msk            (0x1U << PWR_PDCRD_PD3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRD_PD3                PWR_PDCRD_PD3_Msk                         /*!< Port PD3 Pull-Down set  */
+#define PWR_PDCRD_PD2_Pos            (2U)                                      
+#define PWR_PDCRD_PD2_Msk            (0x1U << PWR_PDCRD_PD2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRD_PD2                PWR_PDCRD_PD2_Msk                         /*!< Port PD2 Pull-Down set  */
+#define PWR_PDCRD_PD1_Pos            (1U)                                      
+#define PWR_PDCRD_PD1_Msk            (0x1U << PWR_PDCRD_PD1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRD_PD1                PWR_PDCRD_PD1_Msk                         /*!< Port PD1 Pull-Down set  */
+#define PWR_PDCRD_PD0_Pos            (0U)                                      
+#define PWR_PDCRD_PD0_Msk            (0x1U << PWR_PDCRD_PD0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRD_PD0                PWR_PDCRD_PD0_Msk                         /*!< Port PD0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRE register  ********************/
+#define PWR_PUCRE_PE15_Pos           (15U)                                     
+#define PWR_PUCRE_PE15_Msk           (0x1U << PWR_PUCRE_PE15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRE_PE15               PWR_PUCRE_PE15_Msk                        /*!< Port PE15 Pull-Up set */
+#define PWR_PUCRE_PE14_Pos           (14U)                                     
+#define PWR_PUCRE_PE14_Msk           (0x1U << PWR_PUCRE_PE14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRE_PE14               PWR_PUCRE_PE14_Msk                        /*!< Port PE14 Pull-Up set */
+#define PWR_PUCRE_PE13_Pos           (13U)                                     
+#define PWR_PUCRE_PE13_Msk           (0x1U << PWR_PUCRE_PE13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRE_PE13               PWR_PUCRE_PE13_Msk                        /*!< Port PE13 Pull-Up set */
+#define PWR_PUCRE_PE12_Pos           (12U)                                     
+#define PWR_PUCRE_PE12_Msk           (0x1U << PWR_PUCRE_PE12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRE_PE12               PWR_PUCRE_PE12_Msk                        /*!< Port PE12 Pull-Up set */
+#define PWR_PUCRE_PE11_Pos           (11U)                                     
+#define PWR_PUCRE_PE11_Msk           (0x1U << PWR_PUCRE_PE11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRE_PE11               PWR_PUCRE_PE11_Msk                        /*!< Port PE11 Pull-Up set */
+#define PWR_PUCRE_PE10_Pos           (10U)                                     
+#define PWR_PUCRE_PE10_Msk           (0x1U << PWR_PUCRE_PE10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRE_PE10               PWR_PUCRE_PE10_Msk                        /*!< Port PE10 Pull-Up set */
+#define PWR_PUCRE_PE9_Pos            (9U)                                      
+#define PWR_PUCRE_PE9_Msk            (0x1U << PWR_PUCRE_PE9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRE_PE9                PWR_PUCRE_PE9_Msk                         /*!< Port PE9 Pull-Up set  */
+#define PWR_PUCRE_PE8_Pos            (8U)                                      
+#define PWR_PUCRE_PE8_Msk            (0x1U << PWR_PUCRE_PE8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRE_PE8                PWR_PUCRE_PE8_Msk                         /*!< Port PE8 Pull-Up set  */
+#define PWR_PUCRE_PE7_Pos            (7U)                                      
+#define PWR_PUCRE_PE7_Msk            (0x1U << PWR_PUCRE_PE7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRE_PE7                PWR_PUCRE_PE7_Msk                         /*!< Port PE7 Pull-Up set  */
+#define PWR_PUCRE_PE6_Pos            (6U)                                      
+#define PWR_PUCRE_PE6_Msk            (0x1U << PWR_PUCRE_PE6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRE_PE6                PWR_PUCRE_PE6_Msk                         /*!< Port PE6 Pull-Up set  */
+#define PWR_PUCRE_PE5_Pos            (5U)                                      
+#define PWR_PUCRE_PE5_Msk            (0x1U << PWR_PUCRE_PE5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRE_PE5                PWR_PUCRE_PE5_Msk                         /*!< Port PE5 Pull-Up set  */
+#define PWR_PUCRE_PE4_Pos            (4U)                                      
+#define PWR_PUCRE_PE4_Msk            (0x1U << PWR_PUCRE_PE4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRE_PE4                PWR_PUCRE_PE4_Msk                         /*!< Port PE4 Pull-Up set  */
+#define PWR_PUCRE_PE3_Pos            (3U)                                      
+#define PWR_PUCRE_PE3_Msk            (0x1U << PWR_PUCRE_PE3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRE_PE3                PWR_PUCRE_PE3_Msk                         /*!< Port PE3 Pull-Up set  */
+#define PWR_PUCRE_PE2_Pos            (2U)                                      
+#define PWR_PUCRE_PE2_Msk            (0x1U << PWR_PUCRE_PE2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRE_PE2                PWR_PUCRE_PE2_Msk                         /*!< Port PE2 Pull-Up set  */
+#define PWR_PUCRE_PE1_Pos            (1U)                                      
+#define PWR_PUCRE_PE1_Msk            (0x1U << PWR_PUCRE_PE1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRE_PE1                PWR_PUCRE_PE1_Msk                         /*!< Port PE1 Pull-Up set  */
+#define PWR_PUCRE_PE0_Pos            (0U)                                      
+#define PWR_PUCRE_PE0_Msk            (0x1U << PWR_PUCRE_PE0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRE_PE0                PWR_PUCRE_PE0_Msk                         /*!< Port PE0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRE register  ********************/
+#define PWR_PDCRE_PE15_Pos           (15U)                                     
+#define PWR_PDCRE_PE15_Msk           (0x1U << PWR_PDCRE_PE15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRE_PE15               PWR_PDCRE_PE15_Msk                        /*!< Port PE15 Pull-Down set */
+#define PWR_PDCRE_PE14_Pos           (14U)                                     
+#define PWR_PDCRE_PE14_Msk           (0x1U << PWR_PDCRE_PE14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRE_PE14               PWR_PDCRE_PE14_Msk                        /*!< Port PE14 Pull-Down set */
+#define PWR_PDCRE_PE13_Pos           (13U)                                     
+#define PWR_PDCRE_PE13_Msk           (0x1U << PWR_PDCRE_PE13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRE_PE13               PWR_PDCRE_PE13_Msk                        /*!< Port PE13 Pull-Down set */
+#define PWR_PDCRE_PE12_Pos           (12U)                                     
+#define PWR_PDCRE_PE12_Msk           (0x1U << PWR_PDCRE_PE12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRE_PE12               PWR_PDCRE_PE12_Msk                        /*!< Port PE12 Pull-Down set */
+#define PWR_PDCRE_PE11_Pos           (11U)                                     
+#define PWR_PDCRE_PE11_Msk           (0x1U << PWR_PDCRE_PE11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRE_PE11               PWR_PDCRE_PE11_Msk                        /*!< Port PE11 Pull-Down set */
+#define PWR_PDCRE_PE10_Pos           (10U)                                     
+#define PWR_PDCRE_PE10_Msk           (0x1U << PWR_PDCRE_PE10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRE_PE10               PWR_PDCRE_PE10_Msk                        /*!< Port PE10 Pull-Down set */
+#define PWR_PDCRE_PE9_Pos            (9U)                                      
+#define PWR_PDCRE_PE9_Msk            (0x1U << PWR_PDCRE_PE9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRE_PE9                PWR_PDCRE_PE9_Msk                         /*!< Port PE9 Pull-Down set  */
+#define PWR_PDCRE_PE8_Pos            (8U)                                      
+#define PWR_PDCRE_PE8_Msk            (0x1U << PWR_PDCRE_PE8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRE_PE8                PWR_PDCRE_PE8_Msk                         /*!< Port PE8 Pull-Down set  */
+#define PWR_PDCRE_PE7_Pos            (7U)                                      
+#define PWR_PDCRE_PE7_Msk            (0x1U << PWR_PDCRE_PE7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRE_PE7                PWR_PDCRE_PE7_Msk                         /*!< Port PE7 Pull-Down set  */
+#define PWR_PDCRE_PE6_Pos            (6U)                                      
+#define PWR_PDCRE_PE6_Msk            (0x1U << PWR_PDCRE_PE6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRE_PE6                PWR_PDCRE_PE6_Msk                         /*!< Port PE6 Pull-Down set  */
+#define PWR_PDCRE_PE5_Pos            (5U)                                      
+#define PWR_PDCRE_PE5_Msk            (0x1U << PWR_PDCRE_PE5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRE_PE5                PWR_PDCRE_PE5_Msk                         /*!< Port PE5 Pull-Down set  */
+#define PWR_PDCRE_PE4_Pos            (4U)                                      
+#define PWR_PDCRE_PE4_Msk            (0x1U << PWR_PDCRE_PE4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRE_PE4                PWR_PDCRE_PE4_Msk                         /*!< Port PE4 Pull-Down set  */
+#define PWR_PDCRE_PE3_Pos            (3U)                                      
+#define PWR_PDCRE_PE3_Msk            (0x1U << PWR_PDCRE_PE3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRE_PE3                PWR_PDCRE_PE3_Msk                         /*!< Port PE3 Pull-Down set  */
+#define PWR_PDCRE_PE2_Pos            (2U)                                      
+#define PWR_PDCRE_PE2_Msk            (0x1U << PWR_PDCRE_PE2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRE_PE2                PWR_PDCRE_PE2_Msk                         /*!< Port PE2 Pull-Down set  */
+#define PWR_PDCRE_PE1_Pos            (1U)                                      
+#define PWR_PDCRE_PE1_Msk            (0x1U << PWR_PDCRE_PE1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRE_PE1                PWR_PDCRE_PE1_Msk                         /*!< Port PE1 Pull-Down set  */
+#define PWR_PDCRE_PE0_Pos            (0U)                                      
+#define PWR_PDCRE_PE0_Msk            (0x1U << PWR_PDCRE_PE0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRE_PE0                PWR_PDCRE_PE0_Msk                         /*!< Port PE0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRF register  ********************/
+#define PWR_PUCRF_PF15_Pos           (15U)                                     
+#define PWR_PUCRF_PF15_Msk           (0x1U << PWR_PUCRF_PF15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRF_PF15               PWR_PUCRF_PF15_Msk                        /*!< Port PF15 Pull-Up set */
+#define PWR_PUCRF_PF14_Pos           (14U)                                     
+#define PWR_PUCRF_PF14_Msk           (0x1U << PWR_PUCRF_PF14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRF_PF14               PWR_PUCRF_PF14_Msk                        /*!< Port PF14 Pull-Up set */
+#define PWR_PUCRF_PF13_Pos           (13U)                                     
+#define PWR_PUCRF_PF13_Msk           (0x1U << PWR_PUCRF_PF13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRF_PF13               PWR_PUCRF_PF13_Msk                        /*!< Port PF13 Pull-Up set */
+#define PWR_PUCRF_PF12_Pos           (12U)                                     
+#define PWR_PUCRF_PF12_Msk           (0x1U << PWR_PUCRF_PF12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRF_PF12               PWR_PUCRF_PF12_Msk                        /*!< Port PF12 Pull-Up set */
+#define PWR_PUCRF_PF11_Pos           (11U)                                     
+#define PWR_PUCRF_PF11_Msk           (0x1U << PWR_PUCRF_PF11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRF_PF11               PWR_PUCRF_PF11_Msk                        /*!< Port PF11 Pull-Up set */
+#define PWR_PUCRF_PF10_Pos           (10U)                                     
+#define PWR_PUCRF_PF10_Msk           (0x1U << PWR_PUCRF_PF10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRF_PF10               PWR_PUCRF_PF10_Msk                        /*!< Port PF10 Pull-Up set */
+#define PWR_PUCRF_PF9_Pos            (9U)                                      
+#define PWR_PUCRF_PF9_Msk            (0x1U << PWR_PUCRF_PF9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRF_PF9                PWR_PUCRF_PF9_Msk                         /*!< Port PF9 Pull-Up set  */
+#define PWR_PUCRF_PF8_Pos            (8U)                                      
+#define PWR_PUCRF_PF8_Msk            (0x1U << PWR_PUCRF_PF8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRF_PF8                PWR_PUCRF_PF8_Msk                         /*!< Port PF8 Pull-Up set  */
+#define PWR_PUCRF_PF7_Pos            (7U)                                      
+#define PWR_PUCRF_PF7_Msk            (0x1U << PWR_PUCRF_PF7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRF_PF7                PWR_PUCRF_PF7_Msk                         /*!< Port PF7 Pull-Up set  */
+#define PWR_PUCRF_PF6_Pos            (6U)                                      
+#define PWR_PUCRF_PF6_Msk            (0x1U << PWR_PUCRF_PF6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRF_PF6                PWR_PUCRF_PF6_Msk                         /*!< Port PF6 Pull-Up set  */
+#define PWR_PUCRF_PF5_Pos            (5U)                                      
+#define PWR_PUCRF_PF5_Msk            (0x1U << PWR_PUCRF_PF5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRF_PF5                PWR_PUCRF_PF5_Msk                         /*!< Port PF5 Pull-Up set  */
+#define PWR_PUCRF_PF4_Pos            (4U)                                      
+#define PWR_PUCRF_PF4_Msk            (0x1U << PWR_PUCRF_PF4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRF_PF4                PWR_PUCRF_PF4_Msk                         /*!< Port PF4 Pull-Up set  */
+#define PWR_PUCRF_PF3_Pos            (3U)                                      
+#define PWR_PUCRF_PF3_Msk            (0x1U << PWR_PUCRF_PF3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRF_PF3                PWR_PUCRF_PF3_Msk                         /*!< Port PF3 Pull-Up set  */
+#define PWR_PUCRF_PF2_Pos            (2U)                                      
+#define PWR_PUCRF_PF2_Msk            (0x1U << PWR_PUCRF_PF2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRF_PF2                PWR_PUCRF_PF2_Msk                         /*!< Port PF2 Pull-Up set  */
+#define PWR_PUCRF_PF1_Pos            (1U)                                      
+#define PWR_PUCRF_PF1_Msk            (0x1U << PWR_PUCRF_PF1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRF_PF1                PWR_PUCRF_PF1_Msk                         /*!< Port PF1 Pull-Up set  */
+#define PWR_PUCRF_PF0_Pos            (0U)                                      
+#define PWR_PUCRF_PF0_Msk            (0x1U << PWR_PUCRF_PF0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRF_PF0                PWR_PUCRF_PF0_Msk                         /*!< Port PF0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRF register  ********************/
+#define PWR_PDCRF_PF15_Pos           (15U)                                     
+#define PWR_PDCRF_PF15_Msk           (0x1U << PWR_PDCRF_PF15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRF_PF15               PWR_PDCRF_PF15_Msk                        /*!< Port PF15 Pull-Down set */
+#define PWR_PDCRF_PF14_Pos           (14U)                                     
+#define PWR_PDCRF_PF14_Msk           (0x1U << PWR_PDCRF_PF14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRF_PF14               PWR_PDCRF_PF14_Msk                        /*!< Port PF14 Pull-Down set */
+#define PWR_PDCRF_PF13_Pos           (13U)                                     
+#define PWR_PDCRF_PF13_Msk           (0x1U << PWR_PDCRF_PF13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRF_PF13               PWR_PDCRF_PF13_Msk                        /*!< Port PF13 Pull-Down set */
+#define PWR_PDCRF_PF12_Pos           (12U)                                     
+#define PWR_PDCRF_PF12_Msk           (0x1U << PWR_PDCRF_PF12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRF_PF12               PWR_PDCRF_PF12_Msk                        /*!< Port PF12 Pull-Down set */
+#define PWR_PDCRF_PF11_Pos           (11U)                                     
+#define PWR_PDCRF_PF11_Msk           (0x1U << PWR_PDCRF_PF11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRF_PF11               PWR_PDCRF_PF11_Msk                        /*!< Port PF11 Pull-Down set */
+#define PWR_PDCRF_PF10_Pos           (10U)                                     
+#define PWR_PDCRF_PF10_Msk           (0x1U << PWR_PDCRF_PF10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRF_PF10               PWR_PDCRF_PF10_Msk                        /*!< Port PF10 Pull-Down set */
+#define PWR_PDCRF_PF9_Pos            (9U)                                      
+#define PWR_PDCRF_PF9_Msk            (0x1U << PWR_PDCRF_PF9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRF_PF9                PWR_PDCRF_PF9_Msk                         /*!< Port PF9 Pull-Down set  */
+#define PWR_PDCRF_PF8_Pos            (8U)                                      
+#define PWR_PDCRF_PF8_Msk            (0x1U << PWR_PDCRF_PF8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRF_PF8                PWR_PDCRF_PF8_Msk                         /*!< Port PF8 Pull-Down set  */
+#define PWR_PDCRF_PF7_Pos            (7U)                                      
+#define PWR_PDCRF_PF7_Msk            (0x1U << PWR_PDCRF_PF7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRF_PF7                PWR_PDCRF_PF7_Msk                         /*!< Port PF7 Pull-Down set  */
+#define PWR_PDCRF_PF6_Pos            (6U)                                      
+#define PWR_PDCRF_PF6_Msk            (0x1U << PWR_PDCRF_PF6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRF_PF6                PWR_PDCRF_PF6_Msk                         /*!< Port PF6 Pull-Down set  */
+#define PWR_PDCRF_PF5_Pos            (5U)                                      
+#define PWR_PDCRF_PF5_Msk            (0x1U << PWR_PDCRF_PF5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRF_PF5                PWR_PDCRF_PF5_Msk                         /*!< Port PF5 Pull-Down set  */
+#define PWR_PDCRF_PF4_Pos            (4U)                                      
+#define PWR_PDCRF_PF4_Msk            (0x1U << PWR_PDCRF_PF4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRF_PF4                PWR_PDCRF_PF4_Msk                         /*!< Port PF4 Pull-Down set  */
+#define PWR_PDCRF_PF3_Pos            (3U)                                      
+#define PWR_PDCRF_PF3_Msk            (0x1U << PWR_PDCRF_PF3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRF_PF3                PWR_PDCRF_PF3_Msk                         /*!< Port PF3 Pull-Down set  */
+#define PWR_PDCRF_PF2_Pos            (2U)                                      
+#define PWR_PDCRF_PF2_Msk            (0x1U << PWR_PDCRF_PF2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRF_PF2                PWR_PDCRF_PF2_Msk                         /*!< Port PF2 Pull-Down set  */
+#define PWR_PDCRF_PF1_Pos            (1U)                                      
+#define PWR_PDCRF_PF1_Msk            (0x1U << PWR_PDCRF_PF1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRF_PF1                PWR_PDCRF_PF1_Msk                         /*!< Port PF1 Pull-Down set  */
+#define PWR_PDCRF_PF0_Pos            (0U)                                      
+#define PWR_PDCRF_PF0_Msk            (0x1U << PWR_PDCRF_PF0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRF_PF0                PWR_PDCRF_PF0_Msk                         /*!< Port PF0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRG register  ********************/
+#define PWR_PUCRG_PG15_Pos           (15U)                                     
+#define PWR_PUCRG_PG15_Msk           (0x1U << PWR_PUCRG_PG15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRG_PG15               PWR_PUCRG_PG15_Msk                        /*!< Port PG15 Pull-Up set */
+#define PWR_PUCRG_PG14_Pos           (14U)                                     
+#define PWR_PUCRG_PG14_Msk           (0x1U << PWR_PUCRG_PG14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRG_PG14               PWR_PUCRG_PG14_Msk                        /*!< Port PG14 Pull-Up set */
+#define PWR_PUCRG_PG13_Pos           (13U)                                     
+#define PWR_PUCRG_PG13_Msk           (0x1U << PWR_PUCRG_PG13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRG_PG13               PWR_PUCRG_PG13_Msk                        /*!< Port PG13 Pull-Up set */
+#define PWR_PUCRG_PG12_Pos           (12U)                                     
+#define PWR_PUCRG_PG12_Msk           (0x1U << PWR_PUCRG_PG12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRG_PG12               PWR_PUCRG_PG12_Msk                        /*!< Port PG12 Pull-Up set */
+#define PWR_PUCRG_PG11_Pos           (11U)                                     
+#define PWR_PUCRG_PG11_Msk           (0x1U << PWR_PUCRG_PG11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRG_PG11               PWR_PUCRG_PG11_Msk                        /*!< Port PG11 Pull-Up set */
+#define PWR_PUCRG_PG10_Pos           (10U)                                     
+#define PWR_PUCRG_PG10_Msk           (0x1U << PWR_PUCRG_PG10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRG_PG10               PWR_PUCRG_PG10_Msk                        /*!< Port PG10 Pull-Up set */
+#define PWR_PUCRG_PG9_Pos            (9U)                                      
+#define PWR_PUCRG_PG9_Msk            (0x1U << PWR_PUCRG_PG9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRG_PG9                PWR_PUCRG_PG9_Msk                         /*!< Port PG9 Pull-Up set  */
+#define PWR_PUCRG_PG8_Pos            (8U)                                      
+#define PWR_PUCRG_PG8_Msk            (0x1U << PWR_PUCRG_PG8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRG_PG8                PWR_PUCRG_PG8_Msk                         /*!< Port PG8 Pull-Up set  */
+#define PWR_PUCRG_PG7_Pos            (7U)                                      
+#define PWR_PUCRG_PG7_Msk            (0x1U << PWR_PUCRG_PG7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRG_PG7                PWR_PUCRG_PG7_Msk                         /*!< Port PG7 Pull-Up set  */
+#define PWR_PUCRG_PG6_Pos            (6U)                                      
+#define PWR_PUCRG_PG6_Msk            (0x1U << PWR_PUCRG_PG6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRG_PG6                PWR_PUCRG_PG6_Msk                         /*!< Port PG6 Pull-Up set  */
+#define PWR_PUCRG_PG5_Pos            (5U)                                      
+#define PWR_PUCRG_PG5_Msk            (0x1U << PWR_PUCRG_PG5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRG_PG5                PWR_PUCRG_PG5_Msk                         /*!< Port PG5 Pull-Up set  */
+#define PWR_PUCRG_PG4_Pos            (4U)                                      
+#define PWR_PUCRG_PG4_Msk            (0x1U << PWR_PUCRG_PG4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRG_PG4                PWR_PUCRG_PG4_Msk                         /*!< Port PG4 Pull-Up set  */
+#define PWR_PUCRG_PG3_Pos            (3U)                                      
+#define PWR_PUCRG_PG3_Msk            (0x1U << PWR_PUCRG_PG3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRG_PG3                PWR_PUCRG_PG3_Msk                         /*!< Port PG3 Pull-Up set  */
+#define PWR_PUCRG_PG2_Pos            (2U)                                      
+#define PWR_PUCRG_PG2_Msk            (0x1U << PWR_PUCRG_PG2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRG_PG2                PWR_PUCRG_PG2_Msk                         /*!< Port PG2 Pull-Up set  */
+#define PWR_PUCRG_PG1_Pos            (1U)                                      
+#define PWR_PUCRG_PG1_Msk            (0x1U << PWR_PUCRG_PG1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRG_PG1                PWR_PUCRG_PG1_Msk                         /*!< Port PG1 Pull-Up set  */
+#define PWR_PUCRG_PG0_Pos            (0U)                                      
+#define PWR_PUCRG_PG0_Msk            (0x1U << PWR_PUCRG_PG0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRG_PG0                PWR_PUCRG_PG0_Msk                         /*!< Port PG0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRG register  ********************/
+#define PWR_PDCRG_PG15_Pos           (15U)                                     
+#define PWR_PDCRG_PG15_Msk           (0x1U << PWR_PDCRG_PG15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRG_PG15               PWR_PDCRG_PG15_Msk                        /*!< Port PG15 Pull-Down set */
+#define PWR_PDCRG_PG14_Pos           (14U)                                     
+#define PWR_PDCRG_PG14_Msk           (0x1U << PWR_PDCRG_PG14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRG_PG14               PWR_PDCRG_PG14_Msk                        /*!< Port PG14 Pull-Down set */
+#define PWR_PDCRG_PG13_Pos           (13U)                                     
+#define PWR_PDCRG_PG13_Msk           (0x1U << PWR_PDCRG_PG13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRG_PG13               PWR_PDCRG_PG13_Msk                        /*!< Port PG13 Pull-Down set */
+#define PWR_PDCRG_PG12_Pos           (12U)                                     
+#define PWR_PDCRG_PG12_Msk           (0x1U << PWR_PDCRG_PG12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRG_PG12               PWR_PDCRG_PG12_Msk                        /*!< Port PG12 Pull-Down set */
+#define PWR_PDCRG_PG11_Pos           (11U)                                     
+#define PWR_PDCRG_PG11_Msk           (0x1U << PWR_PDCRG_PG11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRG_PG11               PWR_PDCRG_PG11_Msk                        /*!< Port PG11 Pull-Down set */
+#define PWR_PDCRG_PG10_Pos           (10U)                                     
+#define PWR_PDCRG_PG10_Msk           (0x1U << PWR_PDCRG_PG10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRG_PG10               PWR_PDCRG_PG10_Msk                        /*!< Port PG10 Pull-Down set */
+#define PWR_PDCRG_PG9_Pos            (9U)                                      
+#define PWR_PDCRG_PG9_Msk            (0x1U << PWR_PDCRG_PG9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRG_PG9                PWR_PDCRG_PG9_Msk                         /*!< Port PG9 Pull-Down set  */
+#define PWR_PDCRG_PG8_Pos            (8U)                                      
+#define PWR_PDCRG_PG8_Msk            (0x1U << PWR_PDCRG_PG8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRG_PG8                PWR_PDCRG_PG8_Msk                         /*!< Port PG8 Pull-Down set  */
+#define PWR_PDCRG_PG7_Pos            (7U)                                      
+#define PWR_PDCRG_PG7_Msk            (0x1U << PWR_PDCRG_PG7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRG_PG7                PWR_PDCRG_PG7_Msk                         /*!< Port PG7 Pull-Down set  */
+#define PWR_PDCRG_PG6_Pos            (6U)                                      
+#define PWR_PDCRG_PG6_Msk            (0x1U << PWR_PDCRG_PG6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRG_PG6                PWR_PDCRG_PG6_Msk                         /*!< Port PG6 Pull-Down set  */
+#define PWR_PDCRG_PG5_Pos            (5U)                                      
+#define PWR_PDCRG_PG5_Msk            (0x1U << PWR_PDCRG_PG5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRG_PG5                PWR_PDCRG_PG5_Msk                         /*!< Port PG5 Pull-Down set  */
+#define PWR_PDCRG_PG4_Pos            (4U)                                      
+#define PWR_PDCRG_PG4_Msk            (0x1U << PWR_PDCRG_PG4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRG_PG4                PWR_PDCRG_PG4_Msk                         /*!< Port PG4 Pull-Down set  */
+#define PWR_PDCRG_PG3_Pos            (3U)                                      
+#define PWR_PDCRG_PG3_Msk            (0x1U << PWR_PDCRG_PG3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRG_PG3                PWR_PDCRG_PG3_Msk                         /*!< Port PG3 Pull-Down set  */
+#define PWR_PDCRG_PG2_Pos            (2U)                                      
+#define PWR_PDCRG_PG2_Msk            (0x1U << PWR_PDCRG_PG2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRG_PG2                PWR_PDCRG_PG2_Msk                         /*!< Port PG2 Pull-Down set  */
+#define PWR_PDCRG_PG1_Pos            (1U)                                      
+#define PWR_PDCRG_PG1_Msk            (0x1U << PWR_PDCRG_PG1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRG_PG1                PWR_PDCRG_PG1_Msk                         /*!< Port PG1 Pull-Down set  */
+#define PWR_PDCRG_PG0_Pos            (0U)                                      
+#define PWR_PDCRG_PG0_Msk            (0x1U << PWR_PDCRG_PG0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRG_PG0                PWR_PDCRG_PG0_Msk                         /*!< Port PG0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRH register  ********************/
+#define PWR_PUCRH_PH15_Pos           (15U)                                      
+#define PWR_PUCRH_PH15_Msk           (0x1U << PWR_PUCRH_PH15_Pos)              /*!< 0x00008000 */
+#define PWR_PUCRH_PH15               PWR_PUCRH_PH15_Msk                        /*!< Port PH15 Pull-Up set  */
+#define PWR_PUCRH_PH14_Pos           (14U)                                      
+#define PWR_PUCRH_PH14_Msk           (0x1U << PWR_PUCRH_PH14_Pos)              /*!< 0x00004000 */
+#define PWR_PUCRH_PH14               PWR_PUCRH_PH14_Msk                        /*!< Port PH14 Pull-Up set  */
+#define PWR_PUCRH_PH13_Pos           (13U)                                      
+#define PWR_PUCRH_PH13_Msk           (0x1U << PWR_PUCRH_PH13_Pos)              /*!< 0x00002000 */
+#define PWR_PUCRH_PH13               PWR_PUCRH_PH13_Msk                        /*!< Port PH13 Pull-Up set  */
+#define PWR_PUCRH_PH12_Pos           (12U)                                      
+#define PWR_PUCRH_PH12_Msk           (0x1U << PWR_PUCRH_PH12_Pos)              /*!< 0x00001000 */
+#define PWR_PUCRH_PH12               PWR_PUCRH_PH12_Msk                        /*!< Port PH12 Pull-Up set  */
+#define PWR_PUCRH_PH11_Pos           (11U)                                      
+#define PWR_PUCRH_PH11_Msk           (0x1U << PWR_PUCRH_PH11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRH_PH11               PWR_PUCRH_PH11_Msk                        /*!< Port PH11 Pull-Up set  */
+#define PWR_PUCRH_PH10_Pos           (10U)                                      
+#define PWR_PUCRH_PH10_Msk           (0x1U << PWR_PUCRH_PH10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRH_PH10               PWR_PUCRH_PH10_Msk                        /*!< Port PH10 Pull-Up set  */
+#define PWR_PUCRH_PH9_Pos            (9U)                                      
+#define PWR_PUCRH_PH9_Msk            (0x1U << PWR_PUCRH_PH9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRH_PH9                PWR_PUCRH_PH9_Msk                         /*!< Port PH9 Pull-Up set  */
+#define PWR_PUCRH_PH8_Pos            (8U)                                      
+#define PWR_PUCRH_PH8_Msk            (0x1U << PWR_PUCRH_PH8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRH_PH8                PWR_PUCRH_PH8_Msk                         /*!< Port PH8 Pull-Up set  */
+#define PWR_PUCRH_PH7_Pos            (7U)                                      
+#define PWR_PUCRH_PH7_Msk            (0x1U << PWR_PUCRH_PH7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRH_PH7                PWR_PUCRH_PH7_Msk                         /*!< Port PH7 Pull-Up set  */
+#define PWR_PUCRH_PH6_Pos            (6U)                                      
+#define PWR_PUCRH_PH6_Msk            (0x1U << PWR_PUCRH_PH6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRH_PH6                PWR_PUCRH_PH6_Msk                         /*!< Port PH6 Pull-Up set  */
+#define PWR_PUCRH_PH5_Pos            (5U)                                      
+#define PWR_PUCRH_PH5_Msk            (0x1U << PWR_PUCRH_PH5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRH_PH5                PWR_PUCRH_PH5_Msk                         /*!< Port PH5 Pull-Up set  */
+#define PWR_PUCRH_PH4_Pos            (4U)                                      
+#define PWR_PUCRH_PH4_Msk            (0x1U << PWR_PUCRH_PH4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRH_PH4                PWR_PUCRH_PH4_Msk                         /*!< Port PH4 Pull-Up set  */
+#define PWR_PUCRH_PH3_Pos            (3U)                                      
+#define PWR_PUCRH_PH3_Msk            (0x1U << PWR_PUCRH_PH3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRH_PH3                PWR_PUCRH_PH3_Msk                         /*!< Port PH3 Pull-Up set  */
+#define PWR_PUCRH_PH2_Pos            (2U)                                      
+#define PWR_PUCRH_PH2_Msk            (0x1U << PWR_PUCRH_PH2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRH_PH2                PWR_PUCRH_PH2_Msk                         /*!< Port PH2 Pull-Up set  */
+#define PWR_PUCRH_PH1_Pos            (1U)                                      
+#define PWR_PUCRH_PH1_Msk            (0x1U << PWR_PUCRH_PH1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRH_PH1                PWR_PUCRH_PH1_Msk                         /*!< Port PH1 Pull-Up set  */
+#define PWR_PUCRH_PH0_Pos            (0U)                                      
+#define PWR_PUCRH_PH0_Msk            (0x1U << PWR_PUCRH_PH0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRH_PH0                PWR_PUCRH_PH0_Msk                         /*!< Port PH0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRH register  ********************/
+#define PWR_PDCRH_PH15_Pos           (15U)                                      
+#define PWR_PDCRH_PH15_Msk           (0x1U << PWR_PDCRH_PH15_Pos)              /*!< 0x00008000 */
+#define PWR_PDCRH_PH15               PWR_PDCRH_PH15_Msk                        /*!< Port PH15 Pull-Down set  */
+#define PWR_PDCRH_PH14_Pos           (14U)                                      
+#define PWR_PDCRH_PH14_Msk           (0x1U << PWR_PDCRH_PH14_Pos)              /*!< 0x00004000 */
+#define PWR_PDCRH_PH14               PWR_PDCRH_PH14_Msk                        /*!< Port PH14 Pull-Down set  */
+#define PWR_PDCRH_PH13_Pos           (13U)                                      
+#define PWR_PDCRH_PH13_Msk           (0x1U << PWR_PDCRH_PH13_Pos)              /*!< 0x00002000 */
+#define PWR_PDCRH_PH13               PWR_PDCRH_PH13_Msk                        /*!< Port PH13 Pull-Down set  */
+#define PWR_PDCRH_PH12_Pos           (12U)                                      
+#define PWR_PDCRH_PH12_Msk           (0x1U << PWR_PDCRH_PH12_Pos)              /*!< 0x00001000 */
+#define PWR_PDCRH_PH12               PWR_PDCRH_PH12_Msk                        /*!< Port PH12 Pull-Down set  */
+#define PWR_PDCRH_PH11_Pos           (11U)                                      
+#define PWR_PDCRH_PH11_Msk           (0x1U << PWR_PDCRH_PH11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRH_PH11               PWR_PDCRH_PH11_Msk                        /*!< Port PH11 Pull-Down set  */
+#define PWR_PDCRH_PH10_Pos           (10U)                                      
+#define PWR_PDCRH_PH10_Msk           (0x1U << PWR_PDCRH_PH10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRH_PH10               PWR_PDCRH_PH10_Msk                        /*!< Port PH10 Pull-Down set  */
+#define PWR_PDCRH_PH9_Pos            (9U)                                      
+#define PWR_PDCRH_PH9_Msk            (0x1U << PWR_PDCRH_PH9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRH_PH9                PWR_PDCRH_PH9_Msk                         /*!< Port PH9 Pull-Down set  */
+#define PWR_PDCRH_PH8_Pos            (8U)                                      
+#define PWR_PDCRH_PH8_Msk            (0x1U << PWR_PDCRH_PH8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRH_PH8                PWR_PDCRH_PH8_Msk                         /*!< Port PH8 Pull-Down set  */
+#define PWR_PDCRH_PH7_Pos            (7U)                                      
+#define PWR_PDCRH_PH7_Msk            (0x1U << PWR_PDCRH_PH7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRH_PH7                PWR_PDCRH_PH7_Msk                         /*!< Port PH7 Pull-Down set  */
+#define PWR_PDCRH_PH6_Pos            (6U)                                      
+#define PWR_PDCRH_PH6_Msk            (0x1U << PWR_PDCRH_PH6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRH_PH6                PWR_PDCRH_PH6_Msk                         /*!< Port PH6 Pull-Down set  */
+#define PWR_PDCRH_PH5_Pos            (5U)                                      
+#define PWR_PDCRH_PH5_Msk            (0x1U << PWR_PDCRH_PH5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRH_PH5                PWR_PDCRH_PH5_Msk                         /*!< Port PH5 Pull-Down set  */
+#define PWR_PDCRH_PH4_Pos            (4U)                                      
+#define PWR_PDCRH_PH4_Msk            (0x1U << PWR_PDCRH_PH4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRH_PH4                PWR_PDCRH_PH4_Msk                         /*!< Port PH4 Pull-Down set  */
+#define PWR_PDCRH_PH3_Pos            (3U)                                      
+#define PWR_PDCRH_PH3_Msk            (0x1U << PWR_PDCRH_PH3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRH_PH3                PWR_PDCRH_PH3_Msk                         /*!< Port PH3 Pull-Down set  */
+#define PWR_PDCRH_PH2_Pos            (2U)                                      
+#define PWR_PDCRH_PH2_Msk            (0x1U << PWR_PDCRH_PH2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRH_PH2                PWR_PDCRH_PH2_Msk                         /*!< Port PH1 Pull-Down set  */
+#define PWR_PDCRH_PH1_Pos            (1U)                                      
+#define PWR_PDCRH_PH1_Msk            (0x1U << PWR_PDCRH_PH1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRH_PH1                PWR_PDCRH_PH1_Msk                         /*!< Port PH1 Pull-Down set  */
+#define PWR_PDCRH_PH0_Pos            (0U)                                      
+#define PWR_PDCRH_PH0_Msk            (0x1U << PWR_PDCRH_PH0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRH_PH0                PWR_PDCRH_PH0_Msk                         /*!< Port PH0 Pull-Down set  */
+
+/********************  Bit definition for PWR_PUCRI register  ********************/
+#define PWR_PUCRI_PI11_Pos           (11U)                                     
+#define PWR_PUCRI_PI11_Msk           (0x1U << PWR_PUCRI_PI11_Pos)              /*!< 0x00000800 */
+#define PWR_PUCRI_PI11               PWR_PUCRI_PI11_Msk                        /*!< Port PI11 Pull-Up set */
+#define PWR_PUCRI_PI10_Pos           (10U)                                     
+#define PWR_PUCRI_PI10_Msk           (0x1U << PWR_PUCRI_PI10_Pos)              /*!< 0x00000400 */
+#define PWR_PUCRI_PI10               PWR_PUCRI_PI10_Msk                        /*!< Port PI10 Pull-Up set */
+#define PWR_PUCRI_PI9_Pos            (9U)                                      
+#define PWR_PUCRI_PI9_Msk            (0x1U << PWR_PUCRI_PI9_Pos)               /*!< 0x00000200 */
+#define PWR_PUCRI_PI9                PWR_PUCRI_PI9_Msk                         /*!< Port PI9 Pull-Up set  */
+#define PWR_PUCRI_PI8_Pos            (8U)                                      
+#define PWR_PUCRI_PI8_Msk            (0x1U << PWR_PUCRI_PI8_Pos)               /*!< 0x00000100 */
+#define PWR_PUCRI_PI8                PWR_PUCRI_PI8_Msk                         /*!< Port PI8 Pull-Up set  */
+#define PWR_PUCRI_PI7_Pos            (7U)                                      
+#define PWR_PUCRI_PI7_Msk            (0x1U << PWR_PUCRI_PI7_Pos)               /*!< 0x00000080 */
+#define PWR_PUCRI_PI7                PWR_PUCRI_PI7_Msk                         /*!< Port PI7 Pull-Up set  */
+#define PWR_PUCRI_PI6_Pos            (6U)                                      
+#define PWR_PUCRI_PI6_Msk            (0x1U << PWR_PUCRI_PI6_Pos)               /*!< 0x00000040 */
+#define PWR_PUCRI_PI6                PWR_PUCRI_PI6_Msk                         /*!< Port PI6 Pull-Up set  */
+#define PWR_PUCRI_PI5_Pos            (5U)                                      
+#define PWR_PUCRI_PI5_Msk            (0x1U << PWR_PUCRI_PI5_Pos)               /*!< 0x00000020 */
+#define PWR_PUCRI_PI5                PWR_PUCRI_PI5_Msk                         /*!< Port PI5 Pull-Up set  */
+#define PWR_PUCRI_PI4_Pos            (4U)                                      
+#define PWR_PUCRI_PI4_Msk            (0x1U << PWR_PUCRI_PI4_Pos)               /*!< 0x00000010 */
+#define PWR_PUCRI_PI4                PWR_PUCRI_PI4_Msk                         /*!< Port PI4 Pull-Up set  */
+#define PWR_PUCRI_PI3_Pos            (3U)                                      
+#define PWR_PUCRI_PI3_Msk            (0x1U << PWR_PUCRI_PI3_Pos)               /*!< 0x00000008 */
+#define PWR_PUCRI_PI3                PWR_PUCRI_PI3_Msk                         /*!< Port PI3 Pull-Up set  */
+#define PWR_PUCRI_PI2_Pos            (2U)                                      
+#define PWR_PUCRI_PI2_Msk            (0x1U << PWR_PUCRI_PI2_Pos)               /*!< 0x00000004 */
+#define PWR_PUCRI_PI2                PWR_PUCRI_PI2_Msk                         /*!< Port PI2 Pull-Up set  */
+#define PWR_PUCRI_PI1_Pos            (1U)                                      
+#define PWR_PUCRI_PI1_Msk            (0x1U << PWR_PUCRI_PI1_Pos)               /*!< 0x00000002 */
+#define PWR_PUCRI_PI1                PWR_PUCRI_PI1_Msk                         /*!< Port PI1 Pull-Up set  */
+#define PWR_PUCRI_PI0_Pos            (0U)                                      
+#define PWR_PUCRI_PI0_Msk            (0x1U << PWR_PUCRI_PI0_Pos)               /*!< 0x00000001 */
+#define PWR_PUCRI_PI0                PWR_PUCRI_PI0_Msk                         /*!< Port PI0 Pull-Up set  */
+
+/********************  Bit definition for PWR_PDCRI register  ********************/
+#define PWR_PDCRI_PI11_Pos           (11U)                                     
+#define PWR_PDCRI_PI11_Msk           (0x1U << PWR_PDCRI_PI11_Pos)              /*!< 0x00000800 */
+#define PWR_PDCRI_PI11               PWR_PDCRI_PI11_Msk                        /*!< Port PI11 Pull-Down set */
+#define PWR_PDCRI_PI10_Pos           (10U)                                     
+#define PWR_PDCRI_PI10_Msk           (0x1U << PWR_PDCRI_PI10_Pos)              /*!< 0x00000400 */
+#define PWR_PDCRI_PI10               PWR_PDCRI_PI10_Msk                        /*!< Port PI10 Pull-Down set */
+#define PWR_PDCRI_PI9_Pos            (9U)                                      
+#define PWR_PDCRI_PI9_Msk            (0x1U << PWR_PDCRI_PI9_Pos)               /*!< 0x00000200 */
+#define PWR_PDCRI_PI9                PWR_PDCRI_PI9_Msk                         /*!< Port PI9 Pull-Down set  */
+#define PWR_PDCRI_PI8_Pos            (8U)                                      
+#define PWR_PDCRI_PI8_Msk            (0x1U << PWR_PDCRI_PI8_Pos)               /*!< 0x00000100 */
+#define PWR_PDCRI_PI8                PWR_PDCRI_PI8_Msk                         /*!< Port PI8 Pull-Down set  */
+#define PWR_PDCRI_PI7_Pos            (7U)                                      
+#define PWR_PDCRI_PI7_Msk            (0x1U << PWR_PDCRI_PI7_Pos)               /*!< 0x00000080 */
+#define PWR_PDCRI_PI7                PWR_PDCRI_PI7_Msk                         /*!< Port PI7 Pull-Down set  */
+#define PWR_PDCRI_PI6_Pos            (6U)                                      
+#define PWR_PDCRI_PI6_Msk            (0x1U << PWR_PDCRI_PI6_Pos)               /*!< 0x00000040 */
+#define PWR_PDCRI_PI6                PWR_PDCRI_PI6_Msk                         /*!< Port PI6 Pull-Down set  */
+#define PWR_PDCRI_PI5_Pos            (5U)                                      
+#define PWR_PDCRI_PI5_Msk            (0x1U << PWR_PDCRI_PI5_Pos)               /*!< 0x00000020 */
+#define PWR_PDCRI_PI5                PWR_PDCRI_PI5_Msk                         /*!< Port PI5 Pull-Down set  */
+#define PWR_PDCRI_PI4_Pos            (4U)                                      
+#define PWR_PDCRI_PI4_Msk            (0x1U << PWR_PDCRI_PI4_Pos)               /*!< 0x00000010 */
+#define PWR_PDCRI_PI4                PWR_PDCRI_PI4_Msk                         /*!< Port PI4 Pull-Down set  */
+#define PWR_PDCRI_PI3_Pos            (3U)                                      
+#define PWR_PDCRI_PI3_Msk            (0x1U << PWR_PDCRI_PI3_Pos)               /*!< 0x00000008 */
+#define PWR_PDCRI_PI3                PWR_PDCRI_PI3_Msk                         /*!< Port PI3 Pull-Down set  */
+#define PWR_PDCRI_PI2_Pos            (2U)                                      
+#define PWR_PDCRI_PI2_Msk            (0x1U << PWR_PDCRI_PI2_Pos)               /*!< 0x00000004 */
+#define PWR_PDCRI_PI2                PWR_PDCRI_PI2_Msk                         /*!< Port PI2 Pull-Down set  */
+#define PWR_PDCRI_PI1_Pos            (1U)                                      
+#define PWR_PDCRI_PI1_Msk            (0x1U << PWR_PDCRI_PI1_Pos)               /*!< 0x00000002 */
+#define PWR_PDCRI_PI1                PWR_PDCRI_PI1_Msk                         /*!< Port PI1 Pull-Down set  */
+#define PWR_PDCRI_PI0_Pos            (0U)                                      
+#define PWR_PDCRI_PI0_Msk            (0x1U << PWR_PDCRI_PI0_Pos)               /*!< 0x00000001 */
+#define PWR_PDCRI_PI0                PWR_PDCRI_PI0_Msk                         /*!< Port PI0 Pull-Down set  */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions  (not present on all devices in the STM32L4 serie)
+*/
+#define RCC_HSI48_SUPPORT
+#define RCC_PLLP_DIV_2_31_SUPPORT
+#define RCC_PLLSAI1P_DIV_2_31_SUPPORT
+#define RCC_PLLSAI2_SUPPORT
+#define RCC_PLLSAI2P_DIV_2_31_SUPPORT
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_MSION_Pos                     (0U)                              
+#define RCC_CR_MSION_Msk                     (0x1U << RCC_CR_MSION_Pos)        /*!< 0x00000001 */
+#define RCC_CR_MSION                         RCC_CR_MSION_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock enable */
+#define RCC_CR_MSIRDY_Pos                    (1U)                              
+#define RCC_CR_MSIRDY_Msk                    (0x1U << RCC_CR_MSIRDY_Pos)       /*!< 0x00000002 */
+#define RCC_CR_MSIRDY                        RCC_CR_MSIRDY_Msk                 /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
+#define RCC_CR_MSIPLLEN_Pos                  (2U)                              
+#define RCC_CR_MSIPLLEN_Msk                  (0x1U << RCC_CR_MSIPLLEN_Pos)     /*!< 0x00000004 */
+#define RCC_CR_MSIPLLEN                      RCC_CR_MSIPLLEN_Msk               /*!< Internal Multi Speed oscillator (MSI) PLL enable */
+#define RCC_CR_MSIRGSEL_Pos                  (3U)                              
+#define RCC_CR_MSIRGSEL_Msk                  (0x1U << RCC_CR_MSIRGSEL_Pos)     /*!< 0x00000008 */
+#define RCC_CR_MSIRGSEL                      RCC_CR_MSIRGSEL_Msk               /*!< Internal Multi Speed oscillator (MSI) range selection */
+
+/*!< MSIRANGE configuration : 12 frequency ranges available */
+#define RCC_CR_MSIRANGE_Pos                  (4U)                              
+#define RCC_CR_MSIRANGE_Msk                  (0xFU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000F0 */
+#define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */
+#define RCC_CR_MSIRANGE_0                    (0x0U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000000 */
+#define RCC_CR_MSIRANGE_1                    (0x1U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000010 */
+#define RCC_CR_MSIRANGE_2                    (0x2U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000020 */
+#define RCC_CR_MSIRANGE_3                    (0x3U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000030 */
+#define RCC_CR_MSIRANGE_4                    (0x4U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000040 */
+#define RCC_CR_MSIRANGE_5                    (0x5U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000050 */
+#define RCC_CR_MSIRANGE_6                    (0x6U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000060 */
+#define RCC_CR_MSIRANGE_7                    (0x7U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000070 */
+#define RCC_CR_MSIRANGE_8                    (0x8U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000080 */
+#define RCC_CR_MSIRANGE_9                    (0x9U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000090 */
+#define RCC_CR_MSIRANGE_10                   (0xAU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000A0 */
+#define RCC_CR_MSIRANGE_11                   (0xBU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000B0 */
+
+#define RCC_CR_HSION_Pos                     (8U)                              
+#define RCC_CR_HSION_Msk                     (0x1U << RCC_CR_HSION_Pos)        /*!< 0x00000100 */
+#define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
+#define RCC_CR_HSIKERON_Pos                  (9U)                              
+#define RCC_CR_HSIKERON_Msk                  (0x1U << RCC_CR_HSIKERON_Pos)     /*!< 0x00000200 */
+#define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos                    (10U)                             
+#define RCC_CR_HSIRDY_Msk                    (0x1U << RCC_CR_HSIRDY_Pos)       /*!< 0x00000400 */
+#define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
+#define RCC_CR_HSIASFS_Pos                   (11U)                             
+#define RCC_CR_HSIASFS_Msk                   (0x1U << RCC_CR_HSIASFS_Pos)      /*!< 0x00000800 */
+#define RCC_CR_HSIASFS                       RCC_CR_HSIASFS_Msk                /*!< HSI16 Automatic Start from Stop */
+
+#define RCC_CR_HSEON_Pos                     (16U)                             
+#define RCC_CR_HSEON_Msk                     (0x1U << RCC_CR_HSEON_Pos)        /*!< 0x00010000 */
+#define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
+#define RCC_CR_HSERDY_Pos                    (17U)                             
+#define RCC_CR_HSERDY_Msk                    (0x1U << RCC_CR_HSERDY_Pos)       /*!< 0x00020000 */
+#define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
+#define RCC_CR_HSEBYP_Pos                    (18U)                             
+#define RCC_CR_HSEBYP_Msk                    (0x1U << RCC_CR_HSEBYP_Pos)       /*!< 0x00040000 */
+#define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */
+#define RCC_CR_CSSON_Pos                     (19U)                             
+#define RCC_CR_CSSON_Msk                     (0x1U << RCC_CR_CSSON_Pos)        /*!< 0x00080000 */
+#define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
+
+#define RCC_CR_PLLON_Pos                     (24U)                             
+#define RCC_CR_PLLON_Msk                     (0x1U << RCC_CR_PLLON_Pos)        /*!< 0x01000000 */
+#define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
+#define RCC_CR_PLLRDY_Pos                    (25U)                             
+#define RCC_CR_PLLRDY_Msk                    (0x1U << RCC_CR_PLLRDY_Pos)       /*!< 0x02000000 */
+#define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
+#define RCC_CR_PLLSAI1ON_Pos                 (26U)                             
+#define RCC_CR_PLLSAI1ON_Msk                 (0x1U << RCC_CR_PLLSAI1ON_Pos)    /*!< 0x04000000 */
+#define RCC_CR_PLLSAI1ON                     RCC_CR_PLLSAI1ON_Msk              /*!< SAI1 PLL enable */
+#define RCC_CR_PLLSAI1RDY_Pos                (27U)                             
+#define RCC_CR_PLLSAI1RDY_Msk                (0x1U << RCC_CR_PLLSAI1RDY_Pos)   /*!< 0x08000000 */
+#define RCC_CR_PLLSAI1RDY                    RCC_CR_PLLSAI1RDY_Msk             /*!< SAI1 PLL ready */
+#define RCC_CR_PLLSAI2ON_Pos                 (28U)                             
+#define RCC_CR_PLLSAI2ON_Msk                 (0x1U << RCC_CR_PLLSAI2ON_Pos)    /*!< 0x10000000 */
+#define RCC_CR_PLLSAI2ON                     RCC_CR_PLLSAI2ON_Msk              /*!< SAI2 PLL enable */
+#define RCC_CR_PLLSAI2RDY_Pos                (29U)                             
+#define RCC_CR_PLLSAI2RDY_Msk                (0x1U << RCC_CR_PLLSAI2RDY_Pos)   /*!< 0x20000000 */
+#define RCC_CR_PLLSAI2RDY                    RCC_CR_PLLSAI2RDY_Msk             /*!< SAI2 PLL ready */
+
+/********************  Bit definition for RCC_ICSCR register  ***************/
+/*!< MSICAL configuration */
+#define RCC_ICSCR_MSICAL_Pos                 (0U)                              
+#define RCC_ICSCR_MSICAL_Msk                 (0xFFU << RCC_ICSCR_MSICAL_Pos)   /*!< 0x000000FF */
+#define RCC_ICSCR_MSICAL                     RCC_ICSCR_MSICAL_Msk              /*!< MSICAL[7:0] bits */
+#define RCC_ICSCR_MSICAL_0                   (0x01U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000001 */
+#define RCC_ICSCR_MSICAL_1                   (0x02U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000002 */
+#define RCC_ICSCR_MSICAL_2                   (0x04U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000004 */
+#define RCC_ICSCR_MSICAL_3                   (0x08U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000008 */
+#define RCC_ICSCR_MSICAL_4                   (0x10U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000010 */
+#define RCC_ICSCR_MSICAL_5                   (0x20U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000020 */
+#define RCC_ICSCR_MSICAL_6                   (0x40U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000040 */
+#define RCC_ICSCR_MSICAL_7                   (0x80U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000080 */
+
+/*!< MSITRIM configuration */
+#define RCC_ICSCR_MSITRIM_Pos                (8U)                              
+#define RCC_ICSCR_MSITRIM_Msk                (0xFFU << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x0000FF00 */
+#define RCC_ICSCR_MSITRIM                    RCC_ICSCR_MSITRIM_Msk             /*!< MSITRIM[7:0] bits */
+#define RCC_ICSCR_MSITRIM_0                  (0x01U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000100 */
+#define RCC_ICSCR_MSITRIM_1                  (0x02U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000200 */
+#define RCC_ICSCR_MSITRIM_2                  (0x04U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000400 */
+#define RCC_ICSCR_MSITRIM_3                  (0x08U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000800 */
+#define RCC_ICSCR_MSITRIM_4                  (0x10U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00001000 */
+#define RCC_ICSCR_MSITRIM_5                  (0x20U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00002000 */
+#define RCC_ICSCR_MSITRIM_6                  (0x40U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00004000 */
+#define RCC_ICSCR_MSITRIM_7                  (0x80U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00008000 */
+
+/*!< HSICAL configuration */
+#define RCC_ICSCR_HSICAL_Pos                 (16U)                             
+#define RCC_ICSCR_HSICAL_Msk                 (0xFFU << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00FF0000 */
+#define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
+#define RCC_ICSCR_HSICAL_0                   (0x01U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00010000 */
+#define RCC_ICSCR_HSICAL_1                   (0x02U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00020000 */
+#define RCC_ICSCR_HSICAL_2                   (0x04U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00040000 */
+#define RCC_ICSCR_HSICAL_3                   (0x08U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00080000 */
+#define RCC_ICSCR_HSICAL_4                   (0x10U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00100000 */
+#define RCC_ICSCR_HSICAL_5                   (0x20U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00200000 */
+#define RCC_ICSCR_HSICAL_6                   (0x40U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00400000 */
+#define RCC_ICSCR_HSICAL_7                   (0x80U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00800000 */
+
+/*!< HSITRIM configuration */
+#define RCC_ICSCR_HSITRIM_Pos                (24U)                             
+#define RCC_ICSCR_HSITRIM_Msk                (0x7FU << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x7F000000 */
+#define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[6:0] bits */
+#define RCC_ICSCR_HSITRIM_0                  (0x01U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x01000000 */
+#define RCC_ICSCR_HSITRIM_1                  (0x02U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x02000000 */
+#define RCC_ICSCR_HSITRIM_2                  (0x04U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x04000000 */
+#define RCC_ICSCR_HSITRIM_3                  (0x08U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x08000000 */
+#define RCC_ICSCR_HSITRIM_4                  (0x10U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x10000000 */
+#define RCC_ICSCR_HSITRIM_5                  (0x20U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x20000000 */
+#define RCC_ICSCR_HSITRIM_6                  (0x40U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x40000000 */
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos                      (0U)                              
+#define RCC_CFGR_SW_Msk                      (0x3U << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
+#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
+#define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI oscillator selection as system clock */
+#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI16 oscillator selection as system clock */
+#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE oscillator selection as system clock */
+#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selection as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos                     (2U)                              
+#define RCC_CFGR_SWS_Msk                     (0x3U << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
+#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI16 oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos                    (4U)                              
+#define RCC_CFGR_HPRE_Msk                    (0xFU << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0                      (0x1U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1                      (0x2U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos                   (8U)                              
+#define RCC_CFGR_PPRE1_Msk                   (0x7U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE1_0                     (0x1U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos                   (11U)                             
+#define RCC_CFGR_PPRE2_Msk                   (0x7U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0                     (0x1U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos                (15U)                             
+#define RCC_CFGR_STOPWUCK_Msk                (0x1U << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from stop and CSS backup clock selection */
+
+/*!< MCOSEL configuration */
+#define RCC_CFGR_MCOSEL_Pos                  (24U)                             
+#define RCC_CFGR_MCOSEL_Msk                  (0xFU << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [3:0] bits (Clock output selection) */
+#define RCC_CFGR_MCOSEL_0                    (0x1U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1                    (0x2U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2                    (0x4U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3                    (0x8U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOPRE_Pos                  (28U)                             
+#define RCC_CFGR_MCOPRE_Msk                  (0x7U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0                    (0x1U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1                    (0x2U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2                    (0x4U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
+ 
+#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
+ 
+/* Legacy aliases */
+#define RCC_CFGR_MCO_PRE                     RCC_CFGR_MCOPRE
+#define RCC_CFGR_MCO_PRE_1                   RCC_CFGR_MCOPRE_DIV1
+#define RCC_CFGR_MCO_PRE_2                   RCC_CFGR_MCOPRE_DIV2
+#define RCC_CFGR_MCO_PRE_4                   RCC_CFGR_MCOPRE_DIV4
+#define RCC_CFGR_MCO_PRE_8                   RCC_CFGR_MCOPRE_DIV8
+#define RCC_CFGR_MCO_PRE_16                  RCC_CFGR_MCOPRE_DIV16
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+#define RCC_PLLCFGR_PLLSRC_Pos               (0U)                              
+#define RCC_PLLCFGR_PLLSRC_Msk               (0x3U << RCC_PLLCFGR_PLLSRC_Pos)  /*!< 0x00000003 */
+#define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk            
+
+#define RCC_PLLCFGR_PLLSRC_MSI_Pos           (0U)                              
+#define RCC_PLLCFGR_PLLSRC_MSI_Msk           (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLSRC_MSI               RCC_PLLCFGR_PLLSRC_MSI_Msk        /*!< MSI oscillator source clock selected */
+#define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)                              
+#define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)                              
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
+#define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */
+
+#define RCC_PLLCFGR_PLLM_Pos                 (4U)                              
+#define RCC_PLLCFGR_PLLM_Msk                 (0x7U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000070 */
+#define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk              
+#define RCC_PLLCFGR_PLLM_0                   (0x1U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_1                   (0x2U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000020 */
+#define RCC_PLLCFGR_PLLM_2                   (0x4U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000040 */
+
+#define RCC_PLLCFGR_PLLN_Pos                 (8U)                              
+#define RCC_PLLCFGR_PLLN_Msk                 (0x7FU << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00007F00 */
+#define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk              
+#define RCC_PLLCFGR_PLLN_0                   (0x01U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_1                   (0x02U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_2                   (0x04U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_3                   (0x08U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_4                   (0x10U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_5                   (0x20U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_6                   (0x40U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLPEN_Pos               (16U)                             
+#define RCC_PLLCFGR_PLLPEN_Msk               (0x1U << RCC_PLLCFGR_PLLPEN_Pos)  /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk            
+#define RCC_PLLCFGR_PLLP_Pos                 (17U)                             
+#define RCC_PLLCFGR_PLLP_Msk                 (0x1U << RCC_PLLCFGR_PLLP_Pos)    /*!< 0x00020000 */
+#define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk              
+#define RCC_PLLCFGR_PLLQEN_Pos               (20U)                             
+#define RCC_PLLCFGR_PLLQEN_Msk               (0x1U << RCC_PLLCFGR_PLLQEN_Pos)  /*!< 0x00100000 */
+#define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk            
+
+#define RCC_PLLCFGR_PLLQ_Pos                 (21U)                             
+#define RCC_PLLCFGR_PLLQ_Msk                 (0x3U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00600000 */
+#define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk              
+#define RCC_PLLCFGR_PLLQ_0                   (0x1U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00200000 */
+#define RCC_PLLCFGR_PLLQ_1                   (0x2U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00400000 */
+
+#define RCC_PLLCFGR_PLLREN_Pos               (24U)                             
+#define RCC_PLLCFGR_PLLREN_Msk               (0x1U << RCC_PLLCFGR_PLLREN_Pos)  /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk            
+#define RCC_PLLCFGR_PLLR_Pos                 (25U)                             
+#define RCC_PLLCFGR_PLLR_Msk                 (0x3U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x06000000 */
+#define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk              
+#define RCC_PLLCFGR_PLLR_0                   (0x1U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLR_1                   (0x2U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x04000000 */
+
+#define RCC_PLLCFGR_PLLPDIV_Pos              (27U)                             
+#define RCC_PLLCFGR_PLLPDIV_Msk              (0x1FU << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0xF8000000 */
+#define RCC_PLLCFGR_PLLPDIV                  RCC_PLLCFGR_PLLPDIV_Msk           
+#define RCC_PLLCFGR_PLLPDIV_0                (0x01U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x08000000 */
+#define RCC_PLLCFGR_PLLPDIV_1                (0x02U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x10000000 */
+#define RCC_PLLCFGR_PLLPDIV_2                (0x04U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x20000000 */
+#define RCC_PLLCFGR_PLLPDIV_3                (0x08U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x40000000 */
+#define RCC_PLLCFGR_PLLPDIV_4                (0x10U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for RCC_PLLSAI1CFGR register  ************/
+#define RCC_PLLSAI1CFGR_PLLSAI1N_Pos         (8U)                              
+#define RCC_PLLSAI1CFGR_PLLSAI1N_Msk         (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N             RCC_PLLSAI1CFGR_PLLSAI1N_Msk      
+#define RCC_PLLSAI1CFGR_PLLSAI1N_0           (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_1           (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_2           (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_3           (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_4           (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_5           (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1N_6           (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos       (16U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PEN           RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk    
+#define RCC_PLLSAI1CFGR_PLLSAI1P_Pos         (17U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1P_Msk         (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1P             RCC_PLLSAI1CFGR_PLLSAI1P_Msk      
+
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos       (20U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1QEN           RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk    
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos         (21U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk         (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1Q             RCC_PLLSAI1CFGR_PLLSAI1Q_Msk      
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_0           (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1Q_1           (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos       (24U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1REN           RCC_PLLSAI1CFGR_PLLSAI1REN_Msk    
+#define RCC_PLLSAI1CFGR_PLLSAI1R_Pos         (25U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1R_Msk         (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1R             RCC_PLLSAI1CFGR_PLLSAI1R_Msk      
+#define RCC_PLLSAI1CFGR_PLLSAI1R_0           (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1R_1           (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
+
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos      (27U)                             
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk      (0x1FU << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0xF8000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV          RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk   
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_0        (0x01U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x08000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_1        (0x02U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x10000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_2        (0x04U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x20000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_3        (0x08U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x40000000 */
+#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_4        (0x10U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for RCC_PLLSAI2CFGR register  ************/
+#define RCC_PLLSAI2CFGR_PLLSAI2N_Pos         (8U)                              
+#define RCC_PLLSAI2CFGR_PLLSAI2N_Msk         (0x7FU << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00007F00 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N             RCC_PLLSAI2CFGR_PLLSAI2N_Msk      
+#define RCC_PLLSAI2CFGR_PLLSAI2N_0           (0x01U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_1           (0x02U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_2           (0x04U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_3           (0x08U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_4           (0x10U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_5           (0x20U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2N_6           (0x40U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos       (16U)                             
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk       (0x1U << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos) /*!< 0x00010000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2PEN           RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk    
+#define RCC_PLLSAI2CFGR_PLLSAI2P_Pos         (17U)                             
+#define RCC_PLLSAI2CFGR_PLLSAI2P_Msk         (0x1U << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) /*!< 0x00020000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2P             RCC_PLLSAI2CFGR_PLLSAI2P_Msk      
+
+#define RCC_PLLSAI2CFGR_PLLSAI2REN_Pos       (24U)                             
+#define RCC_PLLSAI2CFGR_PLLSAI2REN_Msk       (0x1U << RCC_PLLSAI2CFGR_PLLSAI2REN_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2REN           RCC_PLLSAI2CFGR_PLLSAI2REN_Msk    
+#define RCC_PLLSAI2CFGR_PLLSAI2R_Pos         (25U)                             
+#define RCC_PLLSAI2CFGR_PLLSAI2R_Msk         (0x3U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x06000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2R             RCC_PLLSAI2CFGR_PLLSAI2R_Msk      
+#define RCC_PLLSAI2CFGR_PLLSAI2R_0           (0x1U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2R_1           (0x2U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x04000000 */
+
+#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos      (27U)                             
+#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_Msk      (0x1FU << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0xF8000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2PDIV          RCC_PLLSAI2CFGR_PLLSAI2PDIV_Msk   
+#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_0        (0x01U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x08000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_1        (0x02U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x10000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_2        (0x04U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x20000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_3        (0x08U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x40000000 */
+#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_4        (0x10U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for RCC_CIER register  ******************/
+#define RCC_CIER_LSIRDYIE_Pos                (0U)                              
+#define RCC_CIER_LSIRDYIE_Msk                (0x1U << RCC_CIER_LSIRDYIE_Pos)   /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk             
+#define RCC_CIER_LSERDYIE_Pos                (1U)                              
+#define RCC_CIER_LSERDYIE_Msk                (0x1U << RCC_CIER_LSERDYIE_Pos)   /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk             
+#define RCC_CIER_MSIRDYIE_Pos                (2U)                              
+#define RCC_CIER_MSIRDYIE_Msk                (0x1U << RCC_CIER_MSIRDYIE_Pos)   /*!< 0x00000004 */
+#define RCC_CIER_MSIRDYIE                    RCC_CIER_MSIRDYIE_Msk             
+#define RCC_CIER_HSIRDYIE_Pos                (3U)                              
+#define RCC_CIER_HSIRDYIE_Msk                (0x1U << RCC_CIER_HSIRDYIE_Pos)   /*!< 0x00000008 */
+#define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk             
+#define RCC_CIER_HSERDYIE_Pos                (4U)                              
+#define RCC_CIER_HSERDYIE_Msk                (0x1U << RCC_CIER_HSERDYIE_Pos)   /*!< 0x00000010 */
+#define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk             
+#define RCC_CIER_PLLRDYIE_Pos                (5U)                              
+#define RCC_CIER_PLLRDYIE_Msk                (0x1U << RCC_CIER_PLLRDYIE_Pos)   /*!< 0x00000020 */
+#define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk             
+#define RCC_CIER_PLLSAI1RDYIE_Pos            (6U)                              
+#define RCC_CIER_PLLSAI1RDYIE_Msk            (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_PLLSAI1RDYIE                RCC_CIER_PLLSAI1RDYIE_Msk         
+#define RCC_CIER_PLLSAI2RDYIE_Pos            (7U)                              
+#define RCC_CIER_PLLSAI2RDYIE_Msk            (0x1U << RCC_CIER_PLLSAI2RDYIE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_PLLSAI2RDYIE                RCC_CIER_PLLSAI2RDYIE_Msk         
+#define RCC_CIER_LSECSSIE_Pos                (9U)                              
+#define RCC_CIER_LSECSSIE_Msk                (0x1U << RCC_CIER_LSECSSIE_Pos)   /*!< 0x00000200 */
+#define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk             
+#define RCC_CIER_HSI48RDYIE_Pos              (10U)                             
+#define RCC_CIER_HSI48RDYIE_Msk              (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000400 */
+#define RCC_CIER_HSI48RDYIE                  RCC_CIER_HSI48RDYIE_Msk           
+
+/********************  Bit definition for RCC_CIFR register  ******************/
+#define RCC_CIFR_LSIRDYF_Pos                 (0U)                              
+#define RCC_CIFR_LSIRDYF_Msk                 (0x1U << RCC_CIFR_LSIRDYF_Pos)    /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk              
+#define RCC_CIFR_LSERDYF_Pos                 (1U)                              
+#define RCC_CIFR_LSERDYF_Msk                 (0x1U << RCC_CIFR_LSERDYF_Pos)    /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk              
+#define RCC_CIFR_MSIRDYF_Pos                 (2U)                              
+#define RCC_CIFR_MSIRDYF_Msk                 (0x1U << RCC_CIFR_MSIRDYF_Pos)    /*!< 0x00000004 */
+#define RCC_CIFR_MSIRDYF                     RCC_CIFR_MSIRDYF_Msk              
+#define RCC_CIFR_HSIRDYF_Pos                 (3U)                              
+#define RCC_CIFR_HSIRDYF_Msk                 (0x1U << RCC_CIFR_HSIRDYF_Pos)    /*!< 0x00000008 */
+#define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk              
+#define RCC_CIFR_HSERDYF_Pos                 (4U)                              
+#define RCC_CIFR_HSERDYF_Msk                 (0x1U << RCC_CIFR_HSERDYF_Pos)    /*!< 0x00000010 */
+#define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk              
+#define RCC_CIFR_PLLRDYF_Pos                 (5U)                              
+#define RCC_CIFR_PLLRDYF_Msk                 (0x1U << RCC_CIFR_PLLRDYF_Pos)    /*!< 0x00000020 */
+#define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk              
+#define RCC_CIFR_PLLSAI1RDYF_Pos             (6U)                              
+#define RCC_CIFR_PLLSAI1RDYF_Msk             (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_PLLSAI1RDYF                 RCC_CIFR_PLLSAI1RDYF_Msk          
+#define RCC_CIFR_PLLSAI2RDYF_Pos             (7U)                              
+#define RCC_CIFR_PLLSAI2RDYF_Msk             (0x1U << RCC_CIFR_PLLSAI2RDYF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_PLLSAI2RDYF                 RCC_CIFR_PLLSAI2RDYF_Msk          
+#define RCC_CIFR_CSSF_Pos                    (8U)                              
+#define RCC_CIFR_CSSF_Msk                    (0x1U << RCC_CIFR_CSSF_Pos)       /*!< 0x00000100 */
+#define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk                 
+#define RCC_CIFR_LSECSSF_Pos                 (9U)                              
+#define RCC_CIFR_LSECSSF_Msk                 (0x1U << RCC_CIFR_LSECSSF_Pos)    /*!< 0x00000200 */
+#define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk              
+#define RCC_CIFR_HSI48RDYF_Pos               (10U)                             
+#define RCC_CIFR_HSI48RDYF_Msk               (0x1U << RCC_CIFR_HSI48RDYF_Pos)  /*!< 0x00000400 */
+#define RCC_CIFR_HSI48RDYF                   RCC_CIFR_HSI48RDYF_Msk            
+
+/********************  Bit definition for RCC_CICR register  ******************/
+#define RCC_CICR_LSIRDYC_Pos                 (0U)                              
+#define RCC_CICR_LSIRDYC_Msk                 (0x1U << RCC_CICR_LSIRDYC_Pos)    /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC                     RCC_CICR_LSIRDYC_Msk              
+#define RCC_CICR_LSERDYC_Pos                 (1U)                              
+#define RCC_CICR_LSERDYC_Msk                 (0x1U << RCC_CICR_LSERDYC_Pos)    /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC                     RCC_CICR_LSERDYC_Msk              
+#define RCC_CICR_MSIRDYC_Pos                 (2U)                              
+#define RCC_CICR_MSIRDYC_Msk                 (0x1U << RCC_CICR_MSIRDYC_Pos)    /*!< 0x00000004 */
+#define RCC_CICR_MSIRDYC                     RCC_CICR_MSIRDYC_Msk              
+#define RCC_CICR_HSIRDYC_Pos                 (3U)                              
+#define RCC_CICR_HSIRDYC_Msk                 (0x1U << RCC_CICR_HSIRDYC_Pos)    /*!< 0x00000008 */
+#define RCC_CICR_HSIRDYC                     RCC_CICR_HSIRDYC_Msk              
+#define RCC_CICR_HSERDYC_Pos                 (4U)                              
+#define RCC_CICR_HSERDYC_Msk                 (0x1U << RCC_CICR_HSERDYC_Pos)    /*!< 0x00000010 */
+#define RCC_CICR_HSERDYC                     RCC_CICR_HSERDYC_Msk              
+#define RCC_CICR_PLLRDYC_Pos                 (5U)                              
+#define RCC_CICR_PLLRDYC_Msk                 (0x1U << RCC_CICR_PLLRDYC_Pos)    /*!< 0x00000020 */
+#define RCC_CICR_PLLRDYC                     RCC_CICR_PLLRDYC_Msk              
+#define RCC_CICR_PLLSAI1RDYC_Pos             (6U)                              
+#define RCC_CICR_PLLSAI1RDYC_Msk             (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_PLLSAI1RDYC                 RCC_CICR_PLLSAI1RDYC_Msk          
+#define RCC_CICR_PLLSAI2RDYC_Pos             (7U)                              
+#define RCC_CICR_PLLSAI2RDYC_Msk             (0x1U << RCC_CICR_PLLSAI2RDYC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_PLLSAI2RDYC                 RCC_CICR_PLLSAI2RDYC_Msk          
+#define RCC_CICR_CSSC_Pos                    (8U)                              
+#define RCC_CICR_CSSC_Msk                    (0x1U << RCC_CICR_CSSC_Pos)       /*!< 0x00000100 */
+#define RCC_CICR_CSSC                        RCC_CICR_CSSC_Msk                 
+#define RCC_CICR_LSECSSC_Pos                 (9U)                              
+#define RCC_CICR_LSECSSC_Msk                 (0x1U << RCC_CICR_LSECSSC_Pos)    /*!< 0x00000200 */
+#define RCC_CICR_LSECSSC                     RCC_CICR_LSECSSC_Msk              
+#define RCC_CICR_HSI48RDYC_Pos               (10U)                             
+#define RCC_CICR_HSI48RDYC_Msk               (0x1U << RCC_CICR_HSI48RDYC_Pos)  /*!< 0x00000400 */
+#define RCC_CICR_HSI48RDYC                   RCC_CICR_HSI48RDYC_Msk            
+
+/********************  Bit definition for RCC_AHB1RSTR register  **************/
+#define RCC_AHB1RSTR_DMA1RST_Pos             (0U)                              
+#define RCC_AHB1RSTR_DMA1RST_Msk             (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk          
+#define RCC_AHB1RSTR_DMA2RST_Pos             (1U)                              
+#define RCC_AHB1RSTR_DMA2RST_Msk             (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk          
+#define RCC_AHB1RSTR_FLASHRST_Pos            (8U)                              
+#define RCC_AHB1RSTR_FLASHRST_Msk            (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB1RSTR_FLASHRST                RCC_AHB1RSTR_FLASHRST_Msk         
+#define RCC_AHB1RSTR_CRCRST_Pos              (12U)                             
+#define RCC_AHB1RSTR_CRCRST_Msk              (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk           
+#define RCC_AHB1RSTR_TSCRST_Pos              (16U)                             
+#define RCC_AHB1RSTR_TSCRST_Msk              (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
+#define RCC_AHB1RSTR_TSCRST                  RCC_AHB1RSTR_TSCRST_Msk           
+#define RCC_AHB1RSTR_DMA2DRST_Pos            (17U)                             
+#define RCC_AHB1RSTR_DMA2DRST_Msk            (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00020000 */
+#define RCC_AHB1RSTR_DMA2DRST                RCC_AHB1RSTR_DMA2DRST_Msk         
+
+/********************  Bit definition for RCC_AHB2RSTR register  **************/
+#define RCC_AHB2RSTR_GPIOARST_Pos            (0U)                              
+#define RCC_AHB2RSTR_GPIOARST_Msk            (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB2RSTR_GPIOARST                RCC_AHB2RSTR_GPIOARST_Msk         
+#define RCC_AHB2RSTR_GPIOBRST_Pos            (1U)                              
+#define RCC_AHB2RSTR_GPIOBRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB2RSTR_GPIOBRST                RCC_AHB2RSTR_GPIOBRST_Msk         
+#define RCC_AHB2RSTR_GPIOCRST_Pos            (2U)                              
+#define RCC_AHB2RSTR_GPIOCRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB2RSTR_GPIOCRST                RCC_AHB2RSTR_GPIOCRST_Msk         
+#define RCC_AHB2RSTR_GPIODRST_Pos            (3U)                              
+#define RCC_AHB2RSTR_GPIODRST_Msk            (0x1U << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB2RSTR_GPIODRST                RCC_AHB2RSTR_GPIODRST_Msk         
+#define RCC_AHB2RSTR_GPIOERST_Pos            (4U)                              
+#define RCC_AHB2RSTR_GPIOERST_Msk            (0x1U << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB2RSTR_GPIOERST                RCC_AHB2RSTR_GPIOERST_Msk         
+#define RCC_AHB2RSTR_GPIOFRST_Pos            (5U)                              
+#define RCC_AHB2RSTR_GPIOFRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB2RSTR_GPIOFRST                RCC_AHB2RSTR_GPIOFRST_Msk         
+#define RCC_AHB2RSTR_GPIOGRST_Pos            (6U)                              
+#define RCC_AHB2RSTR_GPIOGRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB2RSTR_GPIOGRST                RCC_AHB2RSTR_GPIOGRST_Msk         
+#define RCC_AHB2RSTR_GPIOHRST_Pos            (7U)                              
+#define RCC_AHB2RSTR_GPIOHRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_GPIOHRST                RCC_AHB2RSTR_GPIOHRST_Msk         
+#define RCC_AHB2RSTR_GPIOIRST_Pos            (8U)                              
+#define RCC_AHB2RSTR_GPIOIRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB2RSTR_GPIOIRST                RCC_AHB2RSTR_GPIOIRST_Msk         
+#define RCC_AHB2RSTR_OTGFSRST_Pos            (12U)                             
+#define RCC_AHB2RSTR_OTGFSRST_Msk            (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00001000 */
+#define RCC_AHB2RSTR_OTGFSRST                RCC_AHB2RSTR_OTGFSRST_Msk         
+#define RCC_AHB2RSTR_ADCRST_Pos              (13U)                             
+#define RCC_AHB2RSTR_ADCRST_Msk              (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
+#define RCC_AHB2RSTR_ADCRST                  RCC_AHB2RSTR_ADCRST_Msk           
+#define RCC_AHB2RSTR_DCMIRST_Pos             (14U)                             
+#define RCC_AHB2RSTR_DCMIRST_Msk             (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00004000 */
+#define RCC_AHB2RSTR_DCMIRST                 RCC_AHB2RSTR_DCMIRST_Msk          
+#define RCC_AHB2RSTR_RNGRST_Pos              (18U)                             
+#define RCC_AHB2RSTR_RNGRST_Msk              (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
+#define RCC_AHB2RSTR_RNGRST                  RCC_AHB2RSTR_RNGRST_Msk           
+
+/********************  Bit definition for RCC_AHB3RSTR register  **************/
+#define RCC_AHB3RSTR_FMCRST_Pos              (0U)                              
+#define RCC_AHB3RSTR_FMCRST_Msk              (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
+#define RCC_AHB3RSTR_FMCRST                  RCC_AHB3RSTR_FMCRST_Msk           
+#define RCC_AHB3RSTR_QSPIRST_Pos             (8U)                              
+#define RCC_AHB3RSTR_QSPIRST_Msk             (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB3RSTR_QSPIRST                 RCC_AHB3RSTR_QSPIRST_Msk          
+
+/********************  Bit definition for RCC_APB1RSTR1 register  **************/
+#define RCC_APB1RSTR1_TIM2RST_Pos            (0U)                              
+#define RCC_APB1RSTR1_TIM2RST_Msk            (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR1_TIM2RST                RCC_APB1RSTR1_TIM2RST_Msk         
+#define RCC_APB1RSTR1_TIM3RST_Pos            (1U)                              
+#define RCC_APB1RSTR1_TIM3RST_Msk            (0x1U << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR1_TIM3RST                RCC_APB1RSTR1_TIM3RST_Msk         
+#define RCC_APB1RSTR1_TIM4RST_Pos            (2U)                              
+#define RCC_APB1RSTR1_TIM4RST_Msk            (0x1U << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR1_TIM4RST                RCC_APB1RSTR1_TIM4RST_Msk         
+#define RCC_APB1RSTR1_TIM5RST_Pos            (3U)                              
+#define RCC_APB1RSTR1_TIM5RST_Msk            (0x1U << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1RSTR1_TIM5RST                RCC_APB1RSTR1_TIM5RST_Msk         
+#define RCC_APB1RSTR1_TIM6RST_Pos            (4U)                              
+#define RCC_APB1RSTR1_TIM6RST_Msk            (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR1_TIM6RST                RCC_APB1RSTR1_TIM6RST_Msk         
+#define RCC_APB1RSTR1_TIM7RST_Pos            (5U)                              
+#define RCC_APB1RSTR1_TIM7RST_Msk            (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR1_TIM7RST                RCC_APB1RSTR1_TIM7RST_Msk         
+#define RCC_APB1RSTR1_LCDRST_Pos             (9U)                              
+#define RCC_APB1RSTR1_LCDRST_Msk             (0x1U << RCC_APB1RSTR1_LCDRST_Pos) /*!< 0x00000200 */
+#define RCC_APB1RSTR1_LCDRST                 RCC_APB1RSTR1_LCDRST_Msk          
+#define RCC_APB1RSTR1_SPI2RST_Pos            (14U)                             
+#define RCC_APB1RSTR1_SPI2RST_Msk            (0x1U << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR1_SPI2RST                RCC_APB1RSTR1_SPI2RST_Msk         
+#define RCC_APB1RSTR1_SPI3RST_Pos            (15U)                             
+#define RCC_APB1RSTR1_SPI3RST_Msk            (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1RSTR1_SPI3RST                RCC_APB1RSTR1_SPI3RST_Msk         
+#define RCC_APB1RSTR1_USART2RST_Pos          (17U)                             
+#define RCC_APB1RSTR1_USART2RST_Msk          (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR1_USART2RST              RCC_APB1RSTR1_USART2RST_Msk       
+#define RCC_APB1RSTR1_USART3RST_Pos          (18U)                             
+#define RCC_APB1RSTR1_USART3RST_Msk          (0x1U << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR1_USART3RST              RCC_APB1RSTR1_USART3RST_Msk       
+#define RCC_APB1RSTR1_UART4RST_Pos           (19U)                             
+#define RCC_APB1RSTR1_UART4RST_Msk           (0x1U << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR1_UART4RST               RCC_APB1RSTR1_UART4RST_Msk        
+#define RCC_APB1RSTR1_UART5RST_Pos           (20U)                             
+#define RCC_APB1RSTR1_UART5RST_Msk           (0x1U << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR1_UART5RST               RCC_APB1RSTR1_UART5RST_Msk        
+#define RCC_APB1RSTR1_I2C1RST_Pos            (21U)                             
+#define RCC_APB1RSTR1_I2C1RST_Msk            (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR1_I2C1RST                RCC_APB1RSTR1_I2C1RST_Msk         
+#define RCC_APB1RSTR1_I2C2RST_Pos            (22U)                             
+#define RCC_APB1RSTR1_I2C2RST_Msk            (0x1U << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR1_I2C2RST                RCC_APB1RSTR1_I2C2RST_Msk         
+#define RCC_APB1RSTR1_I2C3RST_Pos            (23U)                             
+#define RCC_APB1RSTR1_I2C3RST_Msk            (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR1_I2C3RST                RCC_APB1RSTR1_I2C3RST_Msk         
+#define RCC_APB1RSTR1_CRSRST_Pos             (24U)                             
+#define RCC_APB1RSTR1_CRSRST_Msk             (0x1U << RCC_APB1RSTR1_CRSRST_Pos) /*!< 0x01000000 */
+#define RCC_APB1RSTR1_CRSRST                 RCC_APB1RSTR1_CRSRST_Msk          
+#define RCC_APB1RSTR1_CAN1RST_Pos            (25U)                             
+#define RCC_APB1RSTR1_CAN1RST_Msk            (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
+#define RCC_APB1RSTR1_CAN1RST                RCC_APB1RSTR1_CAN1RST_Msk         
+#define RCC_APB1RSTR1_CAN2RST_Pos            (26U)                             
+#define RCC_APB1RSTR1_CAN2RST_Msk            (0x1U << RCC_APB1RSTR1_CAN2RST_Pos) /*!< 0x04000000 */
+#define RCC_APB1RSTR1_CAN2RST                RCC_APB1RSTR1_CAN2RST_Msk         
+#define RCC_APB1RSTR1_PWRRST_Pos             (28U)                             
+#define RCC_APB1RSTR1_PWRRST_Msk             (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR1_PWRRST                 RCC_APB1RSTR1_PWRRST_Msk          
+#define RCC_APB1RSTR1_DAC1RST_Pos            (29U)                             
+#define RCC_APB1RSTR1_DAC1RST_Msk            (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR1_DAC1RST                RCC_APB1RSTR1_DAC1RST_Msk         
+#define RCC_APB1RSTR1_OPAMPRST_Pos           (30U)                             
+#define RCC_APB1RSTR1_OPAMPRST_Msk           (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR1_OPAMPRST               RCC_APB1RSTR1_OPAMPRST_Msk        
+#define RCC_APB1RSTR1_LPTIM1RST_Pos          (31U)                             
+#define RCC_APB1RSTR1_LPTIM1RST_Msk          (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR1_LPTIM1RST              RCC_APB1RSTR1_LPTIM1RST_Msk       
+
+/********************  Bit definition for RCC_APB1RSTR2 register  **************/
+#define RCC_APB1RSTR2_LPUART1RST_Pos         (0U)                              
+#define RCC_APB1RSTR2_LPUART1RST_Msk         (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR2_LPUART1RST             RCC_APB1RSTR2_LPUART1RST_Msk      
+#define RCC_APB1RSTR2_I2C4RST_Pos            (1U)                              
+#define RCC_APB1RSTR2_I2C4RST_Msk            (0x1U << RCC_APB1RSTR2_I2C4RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR2_I2C4RST                RCC_APB1RSTR2_I2C4RST_Msk         
+#define RCC_APB1RSTR2_SWPMI1RST_Pos          (2U)                              
+#define RCC_APB1RSTR2_SWPMI1RST_Msk          (0x1U << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR2_SWPMI1RST              RCC_APB1RSTR2_SWPMI1RST_Msk       
+#define RCC_APB1RSTR2_LPTIM2RST_Pos          (5U)                              
+#define RCC_APB1RSTR2_LPTIM2RST_Msk          (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR2_LPTIM2RST              RCC_APB1RSTR2_LPTIM2RST_Msk       
+
+/********************  Bit definition for RCC_APB2RSTR register  **************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos           (0U)                              
+#define RCC_APB2RSTR_SYSCFGRST_Msk           (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST               RCC_APB2RSTR_SYSCFGRST_Msk        
+#define RCC_APB2RSTR_SDMMC1RST_Pos           (10U)                             
+#define RCC_APB2RSTR_SDMMC1RST_Msk           (0x1U << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000400 */
+#define RCC_APB2RSTR_SDMMC1RST               RCC_APB2RSTR_SDMMC1RST_Msk        
+#define RCC_APB2RSTR_TIM1RST_Pos             (11U)                             
+#define RCC_APB2RSTR_TIM1RST_Msk             (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
+#define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk          
+#define RCC_APB2RSTR_SPI1RST_Pos             (12U)                             
+#define RCC_APB2RSTR_SPI1RST_Msk             (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk          
+#define RCC_APB2RSTR_TIM8RST_Pos             (13U)                             
+#define RCC_APB2RSTR_TIM8RST_Msk             (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_TIM8RST                 RCC_APB2RSTR_TIM8RST_Msk          
+#define RCC_APB2RSTR_USART1RST_Pos           (14U)                             
+#define RCC_APB2RSTR_USART1RST_Msk           (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk        
+#define RCC_APB2RSTR_TIM15RST_Pos            (16U)                             
+#define RCC_APB2RSTR_TIM15RST_Msk            (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST                RCC_APB2RSTR_TIM15RST_Msk         
+#define RCC_APB2RSTR_TIM16RST_Pos            (17U)                             
+#define RCC_APB2RSTR_TIM16RST_Msk            (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST                RCC_APB2RSTR_TIM16RST_Msk         
+#define RCC_APB2RSTR_TIM17RST_Pos            (18U)                             
+#define RCC_APB2RSTR_TIM17RST_Msk            (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST                RCC_APB2RSTR_TIM17RST_Msk         
+#define RCC_APB2RSTR_SAI1RST_Pos             (21U)                             
+#define RCC_APB2RSTR_SAI1RST_Msk             (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB2RSTR_SAI1RST                 RCC_APB2RSTR_SAI1RST_Msk          
+#define RCC_APB2RSTR_SAI2RST_Pos             (22U)                             
+#define RCC_APB2RSTR_SAI2RST_Msk             (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI2RST                 RCC_APB2RSTR_SAI2RST_Msk          
+#define RCC_APB2RSTR_DFSDM1RST_Pos           (24U)                             
+#define RCC_APB2RSTR_DFSDM1RST_Msk           (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
+#define RCC_APB2RSTR_DFSDM1RST               RCC_APB2RSTR_DFSDM1RST_Msk        
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define RCC_AHB1ENR_DMA1EN_Pos               (0U)                              
+#define RCC_AHB1ENR_DMA1EN_Msk               (0x1U << RCC_AHB1ENR_DMA1EN_Pos)  /*!< 0x00000001 */
+#define RCC_AHB1ENR_DMA1EN                   RCC_AHB1ENR_DMA1EN_Msk            
+#define RCC_AHB1ENR_DMA2EN_Pos               (1U)                              
+#define RCC_AHB1ENR_DMA2EN_Msk               (0x1U << RCC_AHB1ENR_DMA2EN_Pos)  /*!< 0x00000002 */
+#define RCC_AHB1ENR_DMA2EN                   RCC_AHB1ENR_DMA2EN_Msk            
+#define RCC_AHB1ENR_FLASHEN_Pos              (8U)                              
+#define RCC_AHB1ENR_FLASHEN_Msk              (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1ENR_FLASHEN                  RCC_AHB1ENR_FLASHEN_Msk           
+#define RCC_AHB1ENR_CRCEN_Pos                (12U)                             
+#define RCC_AHB1ENR_CRCEN_Msk                (0x1U << RCC_AHB1ENR_CRCEN_Pos)   /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN                    RCC_AHB1ENR_CRCEN_Msk             
+#define RCC_AHB1ENR_TSCEN_Pos                (16U)                             
+#define RCC_AHB1ENR_TSCEN_Msk                (0x1U << RCC_AHB1ENR_TSCEN_Pos)   /*!< 0x00010000 */
+#define RCC_AHB1ENR_TSCEN                    RCC_AHB1ENR_TSCEN_Msk             
+#define RCC_AHB1ENR_DMA2DEN_Pos              (17U)                             
+#define RCC_AHB1ENR_DMA2DEN_Msk              (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1ENR_DMA2DEN                  RCC_AHB1ENR_DMA2DEN_Msk           
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define RCC_AHB2ENR_GPIOAEN_Pos              (0U)                              
+#define RCC_AHB2ENR_GPIOAEN_Msk              (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2ENR_GPIOAEN                  RCC_AHB2ENR_GPIOAEN_Msk           
+#define RCC_AHB2ENR_GPIOBEN_Pos              (1U)                              
+#define RCC_AHB2ENR_GPIOBEN_Msk              (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB2ENR_GPIOBEN                  RCC_AHB2ENR_GPIOBEN_Msk           
+#define RCC_AHB2ENR_GPIOCEN_Pos              (2U)                              
+#define RCC_AHB2ENR_GPIOCEN_Msk              (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB2ENR_GPIOCEN                  RCC_AHB2ENR_GPIOCEN_Msk           
+#define RCC_AHB2ENR_GPIODEN_Pos              (3U)                              
+#define RCC_AHB2ENR_GPIODEN_Msk              (0x1U << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB2ENR_GPIODEN                  RCC_AHB2ENR_GPIODEN_Msk           
+#define RCC_AHB2ENR_GPIOEEN_Pos              (4U)                              
+#define RCC_AHB2ENR_GPIOEEN_Msk              (0x1U << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2ENR_GPIOEEN                  RCC_AHB2ENR_GPIOEEN_Msk           
+#define RCC_AHB2ENR_GPIOFEN_Pos              (5U)                              
+#define RCC_AHB2ENR_GPIOFEN_Msk              (0x1U << RCC_AHB2ENR_GPIOFEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB2ENR_GPIOFEN                  RCC_AHB2ENR_GPIOFEN_Msk           
+#define RCC_AHB2ENR_GPIOGEN_Pos              (6U)                              
+#define RCC_AHB2ENR_GPIOGEN_Msk              (0x1U << RCC_AHB2ENR_GPIOGEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2ENR_GPIOGEN                  RCC_AHB2ENR_GPIOGEN_Msk           
+#define RCC_AHB2ENR_GPIOHEN_Pos              (7U)                              
+#define RCC_AHB2ENR_GPIOHEN_Msk              (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2ENR_GPIOHEN                  RCC_AHB2ENR_GPIOHEN_Msk           
+#define RCC_AHB2ENR_GPIOIEN_Pos              (8U)                              
+#define RCC_AHB2ENR_GPIOIEN_Msk              (0x1U << RCC_AHB2ENR_GPIOIEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB2ENR_GPIOIEN                  RCC_AHB2ENR_GPIOIEN_Msk           
+#define RCC_AHB2ENR_OTGFSEN_Pos              (12U)                             
+#define RCC_AHB2ENR_OTGFSEN_Msk              (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB2ENR_OTGFSEN                  RCC_AHB2ENR_OTGFSEN_Msk           
+#define RCC_AHB2ENR_ADCEN_Pos                (13U)                             
+#define RCC_AHB2ENR_ADCEN_Msk                (0x1U << RCC_AHB2ENR_ADCEN_Pos)   /*!< 0x00002000 */
+#define RCC_AHB2ENR_ADCEN                    RCC_AHB2ENR_ADCEN_Msk             
+#define RCC_AHB2ENR_DCMIEN_Pos               (14U)                             
+#define RCC_AHB2ENR_DCMIEN_Msk               (0x1U << RCC_AHB2ENR_DCMIEN_Pos)  /*!< 0x00004000 */
+#define RCC_AHB2ENR_DCMIEN                   RCC_AHB2ENR_DCMIEN_Msk            
+#define RCC_AHB2ENR_RNGEN_Pos                (18U)                             
+#define RCC_AHB2ENR_RNGEN_Msk                (0x1U << RCC_AHB2ENR_RNGEN_Pos)   /*!< 0x00040000 */
+#define RCC_AHB2ENR_RNGEN                    RCC_AHB2ENR_RNGEN_Msk             
+
+/********************  Bit definition for RCC_AHB3ENR register  ***************/
+#define RCC_AHB3ENR_FMCEN_Pos                (0U)                              
+#define RCC_AHB3ENR_FMCEN_Msk                (0x1U << RCC_AHB3ENR_FMCEN_Pos)   /*!< 0x00000001 */
+#define RCC_AHB3ENR_FMCEN                    RCC_AHB3ENR_FMCEN_Msk             
+#define RCC_AHB3ENR_QSPIEN_Pos               (8U)                              
+#define RCC_AHB3ENR_QSPIEN_Msk               (0x1U << RCC_AHB3ENR_QSPIEN_Pos)  /*!< 0x00000100 */
+#define RCC_AHB3ENR_QSPIEN                   RCC_AHB3ENR_QSPIEN_Msk            
+
+/********************  Bit definition for RCC_APB1ENR1 register  ***************/
+#define RCC_APB1ENR1_TIM2EN_Pos              (0U)                              
+#define RCC_APB1ENR1_TIM2EN_Msk              (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR1_TIM2EN                  RCC_APB1ENR1_TIM2EN_Msk           
+#define RCC_APB1ENR1_TIM3EN_Pos              (1U)                              
+#define RCC_APB1ENR1_TIM3EN_Msk              (0x1U << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR1_TIM3EN                  RCC_APB1ENR1_TIM3EN_Msk           
+#define RCC_APB1ENR1_TIM4EN_Pos              (2U)                              
+#define RCC_APB1ENR1_TIM4EN_Msk              (0x1U << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR1_TIM4EN                  RCC_APB1ENR1_TIM4EN_Msk           
+#define RCC_APB1ENR1_TIM5EN_Pos              (3U)                              
+#define RCC_APB1ENR1_TIM5EN_Msk              (0x1U << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1ENR1_TIM5EN                  RCC_APB1ENR1_TIM5EN_Msk           
+#define RCC_APB1ENR1_TIM6EN_Pos              (4U)                              
+#define RCC_APB1ENR1_TIM6EN_Msk              (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR1_TIM6EN                  RCC_APB1ENR1_TIM6EN_Msk           
+#define RCC_APB1ENR1_TIM7EN_Pos              (5U)                              
+#define RCC_APB1ENR1_TIM7EN_Msk              (0x1U << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR1_TIM7EN                  RCC_APB1ENR1_TIM7EN_Msk           
+#define RCC_APB1ENR1_LCDEN_Pos               (9U)                              
+#define RCC_APB1ENR1_LCDEN_Msk               (0x1U << RCC_APB1ENR1_LCDEN_Pos)  /*!< 0x00000200 */
+#define RCC_APB1ENR1_LCDEN                   RCC_APB1ENR1_LCDEN_Msk            
+#define RCC_APB1ENR1_RTCAPBEN_Pos            (10U)                             
+#define RCC_APB1ENR1_RTCAPBEN_Msk            (0x1U << RCC_APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */
+#define RCC_APB1ENR1_RTCAPBEN                RCC_APB1ENR1_RTCAPBEN_Msk         
+#define RCC_APB1ENR1_WWDGEN_Pos              (11U)                             
+#define RCC_APB1ENR1_WWDGEN_Msk              (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR1_WWDGEN                  RCC_APB1ENR1_WWDGEN_Msk           
+#define RCC_APB1ENR1_SPI2EN_Pos              (14U)                             
+#define RCC_APB1ENR1_SPI2EN_Msk              (0x1U << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR1_SPI2EN                  RCC_APB1ENR1_SPI2EN_Msk           
+#define RCC_APB1ENR1_SPI3EN_Pos              (15U)                             
+#define RCC_APB1ENR1_SPI3EN_Msk              (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1ENR1_SPI3EN                  RCC_APB1ENR1_SPI3EN_Msk           
+#define RCC_APB1ENR1_USART2EN_Pos            (17U)                             
+#define RCC_APB1ENR1_USART2EN_Msk            (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR1_USART2EN                RCC_APB1ENR1_USART2EN_Msk         
+#define RCC_APB1ENR1_USART3EN_Pos            (18U)                             
+#define RCC_APB1ENR1_USART3EN_Msk            (0x1U << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR1_USART3EN                RCC_APB1ENR1_USART3EN_Msk         
+#define RCC_APB1ENR1_UART4EN_Pos             (19U)                             
+#define RCC_APB1ENR1_UART4EN_Msk             (0x1U << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR1_UART4EN                 RCC_APB1ENR1_UART4EN_Msk          
+#define RCC_APB1ENR1_UART5EN_Pos             (20U)                             
+#define RCC_APB1ENR1_UART5EN_Msk             (0x1U << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR1_UART5EN                 RCC_APB1ENR1_UART5EN_Msk          
+#define RCC_APB1ENR1_I2C1EN_Pos              (21U)                             
+#define RCC_APB1ENR1_I2C1EN_Msk              (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR1_I2C1EN                  RCC_APB1ENR1_I2C1EN_Msk           
+#define RCC_APB1ENR1_I2C2EN_Pos              (22U)                             
+#define RCC_APB1ENR1_I2C2EN_Msk              (0x1U << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR1_I2C2EN                  RCC_APB1ENR1_I2C2EN_Msk           
+#define RCC_APB1ENR1_I2C3EN_Pos              (23U)                             
+#define RCC_APB1ENR1_I2C3EN_Msk              (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR1_I2C3EN                  RCC_APB1ENR1_I2C3EN_Msk           
+#define RCC_APB1ENR1_CRSEN_Pos               (24U)                             
+#define RCC_APB1ENR1_CRSEN_Msk               (0x1U << RCC_APB1ENR1_CRSEN_Pos)  /*!< 0x01000000 */
+#define RCC_APB1ENR1_CRSEN                   RCC_APB1ENR1_CRSEN_Msk            
+#define RCC_APB1ENR1_CAN1EN_Pos              (25U)                             
+#define RCC_APB1ENR1_CAN1EN_Msk              (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */
+#define RCC_APB1ENR1_CAN1EN                  RCC_APB1ENR1_CAN1EN_Msk           
+#define RCC_APB1ENR1_CAN2EN_Pos              (26U)                             
+#define RCC_APB1ENR1_CAN2EN_Msk              (0x1U << RCC_APB1ENR1_CAN2EN_Pos) /*!< 0x04000000 */
+#define RCC_APB1ENR1_CAN2EN                  RCC_APB1ENR1_CAN2EN_Msk           
+#define RCC_APB1ENR1_PWREN_Pos               (28U)                             
+#define RCC_APB1ENR1_PWREN_Msk               (0x1U << RCC_APB1ENR1_PWREN_Pos)  /*!< 0x10000000 */
+#define RCC_APB1ENR1_PWREN                   RCC_APB1ENR1_PWREN_Msk            
+#define RCC_APB1ENR1_DAC1EN_Pos              (29U)                             
+#define RCC_APB1ENR1_DAC1EN_Msk              (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR1_DAC1EN                  RCC_APB1ENR1_DAC1EN_Msk           
+#define RCC_APB1ENR1_OPAMPEN_Pos             (30U)                             
+#define RCC_APB1ENR1_OPAMPEN_Msk             (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENR1_OPAMPEN                 RCC_APB1ENR1_OPAMPEN_Msk          
+#define RCC_APB1ENR1_LPTIM1EN_Pos            (31U)                             
+#define RCC_APB1ENR1_LPTIM1EN_Msk            (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR1_LPTIM1EN                RCC_APB1ENR1_LPTIM1EN_Msk         
+
+/********************  Bit definition for RCC_APB1RSTR2 register  **************/
+#define RCC_APB1ENR2_LPUART1EN_Pos           (0U)                              
+#define RCC_APB1ENR2_LPUART1EN_Msk           (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR2_LPUART1EN               RCC_APB1ENR2_LPUART1EN_Msk        
+#define RCC_APB1ENR2_I2C4EN_Pos              (1U)                              
+#define RCC_APB1ENR2_I2C4EN_Msk              (0x1U << RCC_APB1ENR2_I2C4EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR2_I2C4EN                  RCC_APB1ENR2_I2C4EN_Msk           
+#define RCC_APB1ENR2_SWPMI1EN_Pos            (2U)                              
+#define RCC_APB1ENR2_SWPMI1EN_Msk            (0x1U << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1ENR2_SWPMI1EN                RCC_APB1ENR2_SWPMI1EN_Msk         
+#define RCC_APB1ENR2_LPTIM2EN_Pos            (5U)                              
+#define RCC_APB1ENR2_LPTIM2EN_Msk            (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR2_LPTIM2EN                RCC_APB1ENR2_LPTIM2EN_Msk         
+
+/********************  Bit definition for RCC_APB2ENR register  ***************/
+#define RCC_APB2ENR_SYSCFGEN_Pos             (0U)                              
+#define RCC_APB2ENR_SYSCFGEN_Msk             (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN                 RCC_APB2ENR_SYSCFGEN_Msk          
+#define RCC_APB2ENR_FWEN_Pos                 (7U)                              
+#define RCC_APB2ENR_FWEN_Msk                 (0x1U << RCC_APB2ENR_FWEN_Pos)    /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN                     RCC_APB2ENR_FWEN_Msk              
+#define RCC_APB2ENR_SDMMC1EN_Pos             (10U)                             
+#define RCC_APB2ENR_SDMMC1EN_Msk             (0x1U << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000400 */
+#define RCC_APB2ENR_SDMMC1EN                 RCC_APB2ENR_SDMMC1EN_Msk          
+#define RCC_APB2ENR_TIM1EN_Pos               (11U)                             
+#define RCC_APB2ENR_TIM1EN_Msk               (0x1U << RCC_APB2ENR_TIM1EN_Pos)  /*!< 0x00000800 */
+#define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk            
+#define RCC_APB2ENR_SPI1EN_Pos               (12U)                             
+#define RCC_APB2ENR_SPI1EN_Msk               (0x1U << RCC_APB2ENR_SPI1EN_Pos)  /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk            
+#define RCC_APB2ENR_TIM8EN_Pos               (13U)                             
+#define RCC_APB2ENR_TIM8EN_Msk               (0x1U << RCC_APB2ENR_TIM8EN_Pos)  /*!< 0x00002000 */
+#define RCC_APB2ENR_TIM8EN                   RCC_APB2ENR_TIM8EN_Msk            
+#define RCC_APB2ENR_USART1EN_Pos             (14U)                             
+#define RCC_APB2ENR_USART1EN_Msk             (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk          
+#define RCC_APB2ENR_TIM15EN_Pos              (16U)                             
+#define RCC_APB2ENR_TIM15EN_Msk              (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN                  RCC_APB2ENR_TIM15EN_Msk           
+#define RCC_APB2ENR_TIM16EN_Pos              (17U)                             
+#define RCC_APB2ENR_TIM16EN_Msk              (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN                  RCC_APB2ENR_TIM16EN_Msk           
+#define RCC_APB2ENR_TIM17EN_Pos              (18U)                             
+#define RCC_APB2ENR_TIM17EN_Msk              (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN                  RCC_APB2ENR_TIM17EN_Msk           
+#define RCC_APB2ENR_SAI1EN_Pos               (21U)                             
+#define RCC_APB2ENR_SAI1EN_Msk               (0x1U << RCC_APB2ENR_SAI1EN_Pos)  /*!< 0x00200000 */
+#define RCC_APB2ENR_SAI1EN                   RCC_APB2ENR_SAI1EN_Msk            
+#define RCC_APB2ENR_SAI2EN_Pos               (22U)                             
+#define RCC_APB2ENR_SAI2EN_Msk               (0x1U << RCC_APB2ENR_SAI2EN_Pos)  /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI2EN                   RCC_APB2ENR_SAI2EN_Msk            
+#define RCC_APB2ENR_DFSDM1EN_Pos             (24U)                             
+#define RCC_APB2ENR_DFSDM1EN_Msk             (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
+#define RCC_APB2ENR_DFSDM1EN                 RCC_APB2ENR_DFSDM1EN_Msk          
+
+/********************  Bit definition for RCC_AHB1SMENR register  ***************/
+#define RCC_AHB1SMENR_DMA1SMEN_Pos           (0U)                              
+#define RCC_AHB1SMENR_DMA1SMEN_Msk           (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1SMENR_DMA1SMEN               RCC_AHB1SMENR_DMA1SMEN_Msk        
+#define RCC_AHB1SMENR_DMA2SMEN_Pos           (1U)                              
+#define RCC_AHB1SMENR_DMA2SMEN_Msk           (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1SMENR_DMA2SMEN               RCC_AHB1SMENR_DMA2SMEN_Msk        
+#define RCC_AHB1SMENR_FLASHSMEN_Pos          (8U)                              
+#define RCC_AHB1SMENR_FLASHSMEN_Msk          (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1SMENR_FLASHSMEN              RCC_AHB1SMENR_FLASHSMEN_Msk       
+#define RCC_AHB1SMENR_SRAM1SMEN_Pos          (9U)                              
+#define RCC_AHB1SMENR_SRAM1SMEN_Msk          (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB1SMENR_SRAM1SMEN              RCC_AHB1SMENR_SRAM1SMEN_Msk       
+#define RCC_AHB1SMENR_CRCSMEN_Pos            (12U)                             
+#define RCC_AHB1SMENR_CRCSMEN_Msk            (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1SMENR_CRCSMEN                RCC_AHB1SMENR_CRCSMEN_Msk         
+#define RCC_AHB1SMENR_TSCSMEN_Pos            (16U)                             
+#define RCC_AHB1SMENR_TSCSMEN_Msk            (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1SMENR_TSCSMEN                RCC_AHB1SMENR_TSCSMEN_Msk         
+#define RCC_AHB1SMENR_DMA2DSMEN_Pos          (17U)                             
+#define RCC_AHB1SMENR_DMA2DSMEN_Msk          (0x1U << RCC_AHB1SMENR_DMA2DSMEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1SMENR_DMA2DSMEN              RCC_AHB1SMENR_DMA2DSMEN_Msk       
+
+/********************  Bit definition for RCC_AHB2SMENR register  *************/
+#define RCC_AHB2SMENR_GPIOASMEN_Pos          (0U)                              
+#define RCC_AHB2SMENR_GPIOASMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2SMENR_GPIOASMEN              RCC_AHB2SMENR_GPIOASMEN_Msk       
+#define RCC_AHB2SMENR_GPIOBSMEN_Pos          (1U)                              
+#define RCC_AHB2SMENR_GPIOBSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB2SMENR_GPIOBSMEN              RCC_AHB2SMENR_GPIOBSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOCSMEN_Pos          (2U)                              
+#define RCC_AHB2SMENR_GPIOCSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB2SMENR_GPIOCSMEN              RCC_AHB2SMENR_GPIOCSMEN_Msk       
+#define RCC_AHB2SMENR_GPIODSMEN_Pos          (3U)                              
+#define RCC_AHB2SMENR_GPIODSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB2SMENR_GPIODSMEN              RCC_AHB2SMENR_GPIODSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOESMEN_Pos          (4U)                              
+#define RCC_AHB2SMENR_GPIOESMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2SMENR_GPIOESMEN              RCC_AHB2SMENR_GPIOESMEN_Msk       
+#define RCC_AHB2SMENR_GPIOFSMEN_Pos          (5U)                              
+#define RCC_AHB2SMENR_GPIOFSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB2SMENR_GPIOFSMEN              RCC_AHB2SMENR_GPIOFSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOGSMEN_Pos          (6U)                              
+#define RCC_AHB2SMENR_GPIOGSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOGSMEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2SMENR_GPIOGSMEN              RCC_AHB2SMENR_GPIOGSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOHSMEN_Pos          (7U)                              
+#define RCC_AHB2SMENR_GPIOHSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2SMENR_GPIOHSMEN              RCC_AHB2SMENR_GPIOHSMEN_Msk       
+#define RCC_AHB2SMENR_GPIOISMEN_Pos          (8U)                              
+#define RCC_AHB2SMENR_GPIOISMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOISMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB2SMENR_GPIOISMEN              RCC_AHB2SMENR_GPIOISMEN_Msk       
+#define RCC_AHB2SMENR_SRAM2SMEN_Pos          (9U)                              
+#define RCC_AHB2SMENR_SRAM2SMEN_Msk          (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB2SMENR_SRAM2SMEN              RCC_AHB2SMENR_SRAM2SMEN_Msk       
+#define RCC_AHB2SMENR_OTGFSSMEN_Pos          (12U)                             
+#define RCC_AHB2SMENR_OTGFSSMEN_Msk          (0x1U << RCC_AHB2SMENR_OTGFSSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB2SMENR_OTGFSSMEN              RCC_AHB2SMENR_OTGFSSMEN_Msk       
+#define RCC_AHB2SMENR_ADCSMEN_Pos            (13U)                             
+#define RCC_AHB2SMENR_ADCSMEN_Msk            (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
+#define RCC_AHB2SMENR_ADCSMEN                RCC_AHB2SMENR_ADCSMEN_Msk         
+#define RCC_AHB2SMENR_DCMISMEN_Pos           (14U)                             
+#define RCC_AHB2SMENR_DCMISMEN_Msk           (0x1U << RCC_AHB2SMENR_DCMISMEN_Pos) /*!< 0x00004000 */
+#define RCC_AHB2SMENR_DCMISMEN               RCC_AHB2SMENR_DCMISMEN_Msk        
+#define RCC_AHB2SMENR_RNGSMEN_Pos            (18U)                             
+#define RCC_AHB2SMENR_RNGSMEN_Msk            (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB2SMENR_RNGSMEN                RCC_AHB2SMENR_RNGSMEN_Msk         
+
+/********************  Bit definition for RCC_AHB3SMENR register  *************/
+#define RCC_AHB3SMENR_FMCSMEN_Pos            (0U)                              
+#define RCC_AHB3SMENR_FMCSMEN_Msk            (0x1U << RCC_AHB3SMENR_FMCSMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3SMENR_FMCSMEN                RCC_AHB3SMENR_FMCSMEN_Msk         
+#define RCC_AHB3SMENR_QSPISMEN_Pos           (8U)                              
+#define RCC_AHB3SMENR_QSPISMEN_Msk           (0x1U << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB3SMENR_QSPISMEN               RCC_AHB3SMENR_QSPISMEN_Msk        
+
+/********************  Bit definition for RCC_APB1SMENR1 register  *************/
+#define RCC_APB1SMENR1_TIM2SMEN_Pos          (0U)                              
+#define RCC_APB1SMENR1_TIM2SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR1_TIM2SMEN              RCC_APB1SMENR1_TIM2SMEN_Msk       
+#define RCC_APB1SMENR1_TIM3SMEN_Pos          (1U)                              
+#define RCC_APB1SMENR1_TIM3SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1SMENR1_TIM3SMEN              RCC_APB1SMENR1_TIM3SMEN_Msk       
+#define RCC_APB1SMENR1_TIM4SMEN_Pos          (2U)                              
+#define RCC_APB1SMENR1_TIM4SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM4SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1SMENR1_TIM4SMEN              RCC_APB1SMENR1_TIM4SMEN_Msk       
+#define RCC_APB1SMENR1_TIM5SMEN_Pos          (3U)                              
+#define RCC_APB1SMENR1_TIM5SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM5SMEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1SMENR1_TIM5SMEN              RCC_APB1SMENR1_TIM5SMEN_Msk       
+#define RCC_APB1SMENR1_TIM6SMEN_Pos          (4U)                              
+#define RCC_APB1SMENR1_TIM6SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1SMENR1_TIM6SMEN              RCC_APB1SMENR1_TIM6SMEN_Msk       
+#define RCC_APB1SMENR1_TIM7SMEN_Pos          (5U)                              
+#define RCC_APB1SMENR1_TIM7SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR1_TIM7SMEN              RCC_APB1SMENR1_TIM7SMEN_Msk       
+#define RCC_APB1SMENR1_LCDSMEN_Pos           (9U)                              
+#define RCC_APB1SMENR1_LCDSMEN_Msk           (0x1U << RCC_APB1SMENR1_LCDSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB1SMENR1_LCDSMEN               RCC_APB1SMENR1_LCDSMEN_Msk        
+#define RCC_APB1SMENR1_RTCAPBSMEN_Pos        (10U)                             
+#define RCC_APB1SMENR1_RTCAPBSMEN_Msk        (0x1U << RCC_APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
+#define RCC_APB1SMENR1_RTCAPBSMEN            RCC_APB1SMENR1_RTCAPBSMEN_Msk     
+#define RCC_APB1SMENR1_WWDGSMEN_Pos          (11U)                             
+#define RCC_APB1SMENR1_WWDGSMEN_Msk          (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR1_WWDGSMEN              RCC_APB1SMENR1_WWDGSMEN_Msk       
+#define RCC_APB1SMENR1_SPI2SMEN_Pos          (14U)                             
+#define RCC_APB1SMENR1_SPI2SMEN_Msk          (0x1U << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1SMENR1_SPI2SMEN              RCC_APB1SMENR1_SPI2SMEN_Msk       
+#define RCC_APB1SMENR1_SPI3SMEN_Pos          (15U)                             
+#define RCC_APB1SMENR1_SPI3SMEN_Msk          (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1SMENR1_SPI3SMEN              RCC_APB1SMENR1_SPI3SMEN_Msk       
+#define RCC_APB1SMENR1_USART2SMEN_Pos        (17U)                             
+#define RCC_APB1SMENR1_USART2SMEN_Msk        (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR1_USART2SMEN            RCC_APB1SMENR1_USART2SMEN_Msk     
+#define RCC_APB1SMENR1_USART3SMEN_Pos        (18U)                             
+#define RCC_APB1SMENR1_USART3SMEN_Msk        (0x1U << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR1_USART3SMEN            RCC_APB1SMENR1_USART3SMEN_Msk     
+#define RCC_APB1SMENR1_UART4SMEN_Pos         (19U)                             
+#define RCC_APB1SMENR1_UART4SMEN_Msk         (0x1U << RCC_APB1SMENR1_UART4SMEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1SMENR1_UART4SMEN             RCC_APB1SMENR1_UART4SMEN_Msk      
+#define RCC_APB1SMENR1_UART5SMEN_Pos         (20U)                             
+#define RCC_APB1SMENR1_UART5SMEN_Msk         (0x1U << RCC_APB1SMENR1_UART5SMEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1SMENR1_UART5SMEN             RCC_APB1SMENR1_UART5SMEN_Msk      
+#define RCC_APB1SMENR1_I2C1SMEN_Pos          (21U)                             
+#define RCC_APB1SMENR1_I2C1SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR1_I2C1SMEN              RCC_APB1SMENR1_I2C1SMEN_Msk       
+#define RCC_APB1SMENR1_I2C2SMEN_Pos          (22U)                             
+#define RCC_APB1SMENR1_I2C2SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1SMENR1_I2C2SMEN              RCC_APB1SMENR1_I2C2SMEN_Msk       
+#define RCC_APB1SMENR1_I2C3SMEN_Pos          (23U)                             
+#define RCC_APB1SMENR1_I2C3SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1SMENR1_I2C3SMEN              RCC_APB1SMENR1_I2C3SMEN_Msk       
+#define RCC_APB1SMENR1_CRSSMEN_Pos           (24U)                             
+#define RCC_APB1SMENR1_CRSSMEN_Msk           (0x1U << RCC_APB1SMENR1_CRSSMEN_Pos) /*!< 0x01000000 */
+#define RCC_APB1SMENR1_CRSSMEN               RCC_APB1SMENR1_CRSSMEN_Msk        
+#define RCC_APB1SMENR1_CAN1SMEN_Pos          (25U)                             
+#define RCC_APB1SMENR1_CAN1SMEN_Msk          (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1SMENR1_CAN1SMEN              RCC_APB1SMENR1_CAN1SMEN_Msk       
+#define RCC_APB1SMENR1_CAN2SMEN_Pos          (26U)                             
+#define RCC_APB1SMENR1_CAN2SMEN_Msk          (0x1U << RCC_APB1SMENR1_CAN2SMEN_Pos) /*!< 0x04000000 */
+#define RCC_APB1SMENR1_CAN2SMEN              RCC_APB1SMENR1_CAN2SMEN_Msk       
+#define RCC_APB1SMENR1_PWRSMEN_Pos           (28U)                             
+#define RCC_APB1SMENR1_PWRSMEN_Msk           (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR1_PWRSMEN               RCC_APB1SMENR1_PWRSMEN_Msk        
+#define RCC_APB1SMENR1_DAC1SMEN_Pos          (29U)                             
+#define RCC_APB1SMENR1_DAC1SMEN_Msk          (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1SMENR1_DAC1SMEN              RCC_APB1SMENR1_DAC1SMEN_Msk       
+#define RCC_APB1SMENR1_OPAMPSMEN_Pos         (30U)                             
+#define RCC_APB1SMENR1_OPAMPSMEN_Msk         (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1SMENR1_OPAMPSMEN             RCC_APB1SMENR1_OPAMPSMEN_Msk      
+#define RCC_APB1SMENR1_LPTIM1SMEN_Pos        (31U)                             
+#define RCC_APB1SMENR1_LPTIM1SMEN_Msk        (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR1_LPTIM1SMEN            RCC_APB1SMENR1_LPTIM1SMEN_Msk     
+
+/********************  Bit definition for RCC_APB1SMENR2 register  *************/
+#define RCC_APB1SMENR2_LPUART1SMEN_Pos       (0U)                              
+#define RCC_APB1SMENR2_LPUART1SMEN_Msk       (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR2_LPUART1SMEN           RCC_APB1SMENR2_LPUART1SMEN_Msk    
+#define RCC_APB1SMENR2_I2C4SMEN_Pos          (1U)                              
+#define RCC_APB1SMENR2_I2C4SMEN_Msk          (0x1U << RCC_APB1SMENR2_I2C4SMEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1SMENR2_I2C4SMEN              RCC_APB1SMENR2_I2C4SMEN_Msk       
+#define RCC_APB1SMENR2_SWPMI1SMEN_Pos        (2U)                              
+#define RCC_APB1SMENR2_SWPMI1SMEN_Msk        (0x1U << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1SMENR2_SWPMI1SMEN            RCC_APB1SMENR2_SWPMI1SMEN_Msk     
+#define RCC_APB1SMENR2_LPTIM2SMEN_Pos        (5U)                              
+#define RCC_APB1SMENR2_LPTIM2SMEN_Msk        (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR2_LPTIM2SMEN            RCC_APB1SMENR2_LPTIM2SMEN_Msk     
+
+/********************  Bit definition for RCC_APB2SMENR register  *************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos         (0U)                              
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk         (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN             RCC_APB2SMENR_SYSCFGSMEN_Msk      
+#define RCC_APB2SMENR_SDMMC1SMEN_Pos         (10U)                             
+#define RCC_APB2SMENR_SDMMC1SMEN_Msk         (0x1U << RCC_APB2SMENR_SDMMC1SMEN_Pos) /*!< 0x00000400 */
+#define RCC_APB2SMENR_SDMMC1SMEN             RCC_APB2SMENR_SDMMC1SMEN_Msk      
+#define RCC_APB2SMENR_TIM1SMEN_Pos           (11U)                             
+#define RCC_APB2SMENR_TIM1SMEN_Msk           (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2SMENR_TIM1SMEN               RCC_APB2SMENR_TIM1SMEN_Msk        
+#define RCC_APB2SMENR_SPI1SMEN_Pos           (12U)                             
+#define RCC_APB2SMENR_SPI1SMEN_Msk           (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN               RCC_APB2SMENR_SPI1SMEN_Msk        
+#define RCC_APB2SMENR_TIM8SMEN_Pos           (13U)                             
+#define RCC_APB2SMENR_TIM8SMEN_Msk           (0x1U << RCC_APB2SMENR_TIM8SMEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2SMENR_TIM8SMEN               RCC_APB2SMENR_TIM8SMEN_Msk        
+#define RCC_APB2SMENR_USART1SMEN_Pos         (14U)                             
+#define RCC_APB2SMENR_USART1SMEN_Msk         (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN             RCC_APB2SMENR_USART1SMEN_Msk      
+#define RCC_APB2SMENR_TIM15SMEN_Pos          (16U)                             
+#define RCC_APB2SMENR_TIM15SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2SMENR_TIM15SMEN              RCC_APB2SMENR_TIM15SMEN_Msk       
+#define RCC_APB2SMENR_TIM16SMEN_Pos          (17U)                             
+#define RCC_APB2SMENR_TIM16SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2SMENR_TIM16SMEN              RCC_APB2SMENR_TIM16SMEN_Msk       
+#define RCC_APB2SMENR_TIM17SMEN_Pos          (18U)                             
+#define RCC_APB2SMENR_TIM17SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2SMENR_TIM17SMEN              RCC_APB2SMENR_TIM17SMEN_Msk       
+#define RCC_APB2SMENR_SAI1SMEN_Pos           (21U)                             
+#define RCC_APB2SMENR_SAI1SMEN_Msk           (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB2SMENR_SAI1SMEN               RCC_APB2SMENR_SAI1SMEN_Msk        
+#define RCC_APB2SMENR_SAI2SMEN_Pos           (22U)                             
+#define RCC_APB2SMENR_SAI2SMEN_Msk           (0x1U << RCC_APB2SMENR_SAI2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_SAI2SMEN               RCC_APB2SMENR_SAI2SMEN_Msk        
+#define RCC_APB2SMENR_DFSDM1SMEN_Pos         (24U)                             
+#define RCC_APB2SMENR_DFSDM1SMEN_Msk         (0x1U << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */
+#define RCC_APB2SMENR_DFSDM1SMEN             RCC_APB2SMENR_DFSDM1SMEN_Msk      
+
+/********************  Bit definition for RCC_CCIPR register  ******************/
+#define RCC_CCIPR_USART1SEL_Pos              (0U)                              
+#define RCC_CCIPR_USART1SEL_Msk              (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
+#define RCC_CCIPR_USART1SEL                  RCC_CCIPR_USART1SEL_Msk           
+#define RCC_CCIPR_USART1SEL_0                (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR_USART1SEL_1                (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
+
+#define RCC_CCIPR_USART2SEL_Pos              (2U)                              
+#define RCC_CCIPR_USART2SEL_Msk              (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL                  RCC_CCIPR_USART2SEL_Msk           
+#define RCC_CCIPR_USART2SEL_0                (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1                (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+#define RCC_CCIPR_USART3SEL_Pos              (4U)                              
+#define RCC_CCIPR_USART3SEL_Msk              (0x3U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */
+#define RCC_CCIPR_USART3SEL                  RCC_CCIPR_USART3SEL_Msk           
+#define RCC_CCIPR_USART3SEL_0                (0x1U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */
+#define RCC_CCIPR_USART3SEL_1                (0x2U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */
+
+#define RCC_CCIPR_UART4SEL_Pos               (6U)                              
+#define RCC_CCIPR_UART4SEL_Msk               (0x3U << RCC_CCIPR_UART4SEL_Pos)  /*!< 0x000000C0 */
+#define RCC_CCIPR_UART4SEL                   RCC_CCIPR_UART4SEL_Msk            
+#define RCC_CCIPR_UART4SEL_0                 (0x1U << RCC_CCIPR_UART4SEL_Pos)  /*!< 0x00000040 */
+#define RCC_CCIPR_UART4SEL_1                 (0x2U << RCC_CCIPR_UART4SEL_Pos)  /*!< 0x00000080 */
+
+#define RCC_CCIPR_UART5SEL_Pos               (8U)                              
+#define RCC_CCIPR_UART5SEL_Msk               (0x3U << RCC_CCIPR_UART5SEL_Pos)  /*!< 0x00000300 */
+#define RCC_CCIPR_UART5SEL                   RCC_CCIPR_UART5SEL_Msk            
+#define RCC_CCIPR_UART5SEL_0                 (0x1U << RCC_CCIPR_UART5SEL_Pos)  /*!< 0x00000100 */
+#define RCC_CCIPR_UART5SEL_1                 (0x2U << RCC_CCIPR_UART5SEL_Pos)  /*!< 0x00000200 */
+
+#define RCC_CCIPR_LPUART1SEL_Pos             (10U)                             
+#define RCC_CCIPR_LPUART1SEL_Msk             (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL                 RCC_CCIPR_LPUART1SEL_Msk          
+#define RCC_CCIPR_LPUART1SEL_0               (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
+#define RCC_CCIPR_LPUART1SEL_1               (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
+
+#define RCC_CCIPR_I2C1SEL_Pos                (12U)                             
+#define RCC_CCIPR_I2C1SEL_Msk                (0x3U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL                    RCC_CCIPR_I2C1SEL_Msk             
+#define RCC_CCIPR_I2C1SEL_0                  (0x1U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1                  (0x2U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00002000 */
+
+#define RCC_CCIPR_I2C2SEL_Pos                (14U)                             
+#define RCC_CCIPR_I2C2SEL_Msk                (0x3U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x0000C000 */
+#define RCC_CCIPR_I2C2SEL                    RCC_CCIPR_I2C2SEL_Msk             
+#define RCC_CCIPR_I2C2SEL_0                  (0x1U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00004000 */
+#define RCC_CCIPR_I2C2SEL_1                  (0x2U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00008000 */
+
+#define RCC_CCIPR_I2C3SEL_Pos                (16U)                             
+#define RCC_CCIPR_I2C3SEL_Msk                (0x3U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00030000 */
+#define RCC_CCIPR_I2C3SEL                    RCC_CCIPR_I2C3SEL_Msk             
+#define RCC_CCIPR_I2C3SEL_0                  (0x1U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00010000 */
+#define RCC_CCIPR_I2C3SEL_1                  (0x2U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00020000 */
+
+#define RCC_CCIPR_LPTIM1SEL_Pos              (18U)                             
+#define RCC_CCIPR_LPTIM1SEL_Msk              (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL                  RCC_CCIPR_LPTIM1SEL_Msk           
+#define RCC_CCIPR_LPTIM1SEL_0                (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1                (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+#define RCC_CCIPR_LPTIM2SEL_Pos              (20U)                             
+#define RCC_CCIPR_LPTIM2SEL_Msk              (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
+#define RCC_CCIPR_LPTIM2SEL                  RCC_CCIPR_LPTIM2SEL_Msk           
+#define RCC_CCIPR_LPTIM2SEL_0                (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
+#define RCC_CCIPR_LPTIM2SEL_1                (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
+
+#define RCC_CCIPR_SAI1SEL_Pos                (22U)                             
+#define RCC_CCIPR_SAI1SEL_Msk                (0x3U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00C00000 */
+#define RCC_CCIPR_SAI1SEL                    RCC_CCIPR_SAI1SEL_Msk             
+#define RCC_CCIPR_SAI1SEL_0                  (0x1U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00400000 */
+#define RCC_CCIPR_SAI1SEL_1                  (0x2U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00800000 */
+
+#define RCC_CCIPR_SAI2SEL_Pos                (24U)                             
+#define RCC_CCIPR_SAI2SEL_Msk                (0x3U << RCC_CCIPR_SAI2SEL_Pos)   /*!< 0x03000000 */
+#define RCC_CCIPR_SAI2SEL                    RCC_CCIPR_SAI2SEL_Msk             
+#define RCC_CCIPR_SAI2SEL_0                  (0x1U << RCC_CCIPR_SAI2SEL_Pos)   /*!< 0x01000000 */
+#define RCC_CCIPR_SAI2SEL_1                  (0x2U << RCC_CCIPR_SAI2SEL_Pos)   /*!< 0x02000000 */
+
+#define RCC_CCIPR_CLK48SEL_Pos               (26U)                             
+#define RCC_CCIPR_CLK48SEL_Msk               (0x3U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x0C000000 */
+#define RCC_CCIPR_CLK48SEL                   RCC_CCIPR_CLK48SEL_Msk            
+#define RCC_CCIPR_CLK48SEL_0                 (0x1U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x04000000 */
+#define RCC_CCIPR_CLK48SEL_1                 (0x2U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x08000000 */
+
+#define RCC_CCIPR_ADCSEL_Pos                 (28U)                             
+#define RCC_CCIPR_ADCSEL_Msk                 (0x3U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x30000000 */
+#define RCC_CCIPR_ADCSEL                     RCC_CCIPR_ADCSEL_Msk              
+#define RCC_CCIPR_ADCSEL_0                   (0x1U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x10000000 */
+#define RCC_CCIPR_ADCSEL_1                   (0x2U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x20000000 */
+
+#define RCC_CCIPR_SWPMI1SEL_Pos              (30U)                             
+#define RCC_CCIPR_SWPMI1SEL_Msk              (0x1U << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */
+#define RCC_CCIPR_SWPMI1SEL                  RCC_CCIPR_SWPMI1SEL_Msk           
+
+#define RCC_CCIPR_DFSDM1SEL_Pos              (31U)                             
+#define RCC_CCIPR_DFSDM1SEL_Msk              (0x1U << RCC_CCIPR_DFSDM1SEL_Pos) /*!< 0x80000000 */
+#define RCC_CCIPR_DFSDM1SEL                  RCC_CCIPR_DFSDM1SEL_Msk           
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define RCC_BDCR_LSEON_Pos                   (0U)                              
+#define RCC_BDCR_LSEON_Msk                   (0x1U << RCC_BDCR_LSEON_Pos)      /*!< 0x00000001 */
+#define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk                
+#define RCC_BDCR_LSERDY_Pos                  (1U)                              
+#define RCC_BDCR_LSERDY_Msk                  (0x1U << RCC_BDCR_LSERDY_Pos)     /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk               
+#define RCC_BDCR_LSEBYP_Pos                  (2U)                              
+#define RCC_BDCR_LSEBYP_Msk                  (0x1U << RCC_BDCR_LSEBYP_Pos)     /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk               
+
+#define RCC_BDCR_LSEDRV_Pos                  (3U)                              
+#define RCC_BDCR_LSEDRV_Msk                  (0x3U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000018 */
+#define RCC_BDCR_LSEDRV                      RCC_BDCR_LSEDRV_Msk               
+#define RCC_BDCR_LSEDRV_0                    (0x1U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000008 */
+#define RCC_BDCR_LSEDRV_1                    (0x2U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000010 */
+
+#define RCC_BDCR_LSECSSON_Pos                (5U)                              
+#define RCC_BDCR_LSECSSON_Msk                (0x1U << RCC_BDCR_LSECSSON_Pos)   /*!< 0x00000020 */
+#define RCC_BDCR_LSECSSON                    RCC_BDCR_LSECSSON_Msk             
+#define RCC_BDCR_LSECSSD_Pos                 (6U)                              
+#define RCC_BDCR_LSECSSD_Msk                 (0x1U << RCC_BDCR_LSECSSD_Pos)    /*!< 0x00000040 */
+#define RCC_BDCR_LSECSSD                     RCC_BDCR_LSECSSD_Msk              
+
+#define RCC_BDCR_RTCSEL_Pos                  (8U)                              
+#define RCC_BDCR_RTCSEL_Msk                  (0x3U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk               
+#define RCC_BDCR_RTCSEL_0                    (0x1U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos                   (15U)                             
+#define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk                
+#define RCC_BDCR_BDRST_Pos                   (16U)                             
+#define RCC_BDCR_BDRST_Msk                   (0x1U << RCC_BDCR_BDRST_Pos)      /*!< 0x00010000 */
+#define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk                
+#define RCC_BDCR_LSCOEN_Pos                  (24U)                             
+#define RCC_BDCR_LSCOEN_Msk                  (0x1U << RCC_BDCR_LSCOEN_Pos)     /*!< 0x01000000 */
+#define RCC_BDCR_LSCOEN                      RCC_BDCR_LSCOEN_Msk               
+#define RCC_BDCR_LSCOSEL_Pos                 (25U)                             
+#define RCC_BDCR_LSCOSEL_Msk                 (0x1U << RCC_BDCR_LSCOSEL_Pos)    /*!< 0x02000000 */
+#define RCC_BDCR_LSCOSEL                     RCC_BDCR_LSCOSEL_Msk              
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define RCC_CSR_LSION_Pos                    (0U)                              
+#define RCC_CSR_LSION_Msk                    (0x1U << RCC_CSR_LSION_Pos)       /*!< 0x00000001 */
+#define RCC_CSR_LSION                        RCC_CSR_LSION_Msk                 
+#define RCC_CSR_LSIRDY_Pos                   (1U)                              
+#define RCC_CSR_LSIRDY_Msk                   (0x1U << RCC_CSR_LSIRDY_Pos)      /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk                
+
+#define RCC_CSR_MSISRANGE_Pos                (8U)                              
+#define RCC_CSR_MSISRANGE_Msk                (0xFU << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000F00 */
+#define RCC_CSR_MSISRANGE                    RCC_CSR_MSISRANGE_Msk             
+#define RCC_CSR_MSISRANGE_1                  (0x4U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000400 */
+#define RCC_CSR_MSISRANGE_2                  (0x5U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000500 */
+#define RCC_CSR_MSISRANGE_4                  (0x6U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000600 */
+#define RCC_CSR_MSISRANGE_8                  (0x7U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000700 */
+
+#define RCC_CSR_RMVF_Pos                     (23U)                             
+#define RCC_CSR_RMVF_Msk                     (0x1U << RCC_CSR_RMVF_Pos)        /*!< 0x00800000 */
+#define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk                  
+#define RCC_CSR_FWRSTF_Pos                   (24U)                             
+#define RCC_CSR_FWRSTF_Msk                   (0x1U << RCC_CSR_FWRSTF_Pos)      /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF                       RCC_CSR_FWRSTF_Msk                
+#define RCC_CSR_OBLRSTF_Pos                  (25U)                             
+#define RCC_CSR_OBLRSTF_Msk                  (0x1U << RCC_CSR_OBLRSTF_Pos)     /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF                      RCC_CSR_OBLRSTF_Msk               
+#define RCC_CSR_PINRSTF_Pos                  (26U)                             
+#define RCC_CSR_PINRSTF_Msk                  (0x1U << RCC_CSR_PINRSTF_Pos)     /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk               
+#define RCC_CSR_BORRSTF_Pos                  (27U)                             
+#define RCC_CSR_BORRSTF_Msk                  (0x1U << RCC_CSR_BORRSTF_Pos)     /*!< 0x08000000 */
+#define RCC_CSR_BORRSTF                      RCC_CSR_BORRSTF_Msk               
+#define RCC_CSR_SFTRSTF_Pos                  (28U)                             
+#define RCC_CSR_SFTRSTF_Msk                  (0x1U << RCC_CSR_SFTRSTF_Pos)     /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk               
+#define RCC_CSR_IWDGRSTF_Pos                 (29U)                             
+#define RCC_CSR_IWDGRSTF_Msk                 (0x1U << RCC_CSR_IWDGRSTF_Pos)    /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk              
+#define RCC_CSR_WWDGRSTF_Pos                 (30U)                             
+#define RCC_CSR_WWDGRSTF_Msk                 (0x1U << RCC_CSR_WWDGRSTF_Pos)    /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk              
+#define RCC_CSR_LPWRRSTF_Pos                 (31U)                             
+#define RCC_CSR_LPWRRSTF_Msk                 (0x1U << RCC_CSR_LPWRRSTF_Pos)    /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk              
+
+/********************  Bit definition for RCC_CRRCR register  *****************/
+#define RCC_CRRCR_HSI48ON_Pos                (0U)                              
+#define RCC_CRRCR_HSI48ON_Msk                (0x1U << RCC_CRRCR_HSI48ON_Pos)   /*!< 0x00000001 */
+#define RCC_CRRCR_HSI48ON                    RCC_CRRCR_HSI48ON_Msk             
+#define RCC_CRRCR_HSI48RDY_Pos               (1U)                              
+#define RCC_CRRCR_HSI48RDY_Msk               (0x1U << RCC_CRRCR_HSI48RDY_Pos)  /*!< 0x00000002 */
+#define RCC_CRRCR_HSI48RDY                   RCC_CRRCR_HSI48RDY_Msk            
+
+/*!< HSI48CAL configuration */
+#define RCC_CRRCR_HSI48CAL_Pos               (7U)                             
+#define RCC_CRRCR_HSI48CAL_Msk               (0x1FFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF80 */
+#define RCC_CRRCR_HSI48CAL                   RCC_CRRCR_HSI48CAL_Msk             /*!< HSI48CAL[8:0] bits */
+#define RCC_CRRCR_HSI48CAL_0                 (0x001U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
+#define RCC_CRRCR_HSI48CAL_1                 (0x002U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
+#define RCC_CRRCR_HSI48CAL_2                 (0x004U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
+#define RCC_CRRCR_HSI48CAL_3                 (0x008U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000400 */
+#define RCC_CRRCR_HSI48CAL_4                 (0x010U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000800 */
+#define RCC_CRRCR_HSI48CAL_5                 (0x020U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00001000 */
+#define RCC_CRRCR_HSI48CAL_6                 (0x040U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00002000 */
+#define RCC_CRRCR_HSI48CAL_7                 (0x080U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00004000 */
+#define RCC_CRRCR_HSI48CAL_8                 (0x100U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00008000 */
+
+/********************  Bit definition for RCC_CCIPR2 register  ******************/
+#define RCC_CCIPR2_I2C4SEL_Pos               (0U)                              
+#define RCC_CCIPR2_I2C4SEL_Msk               (0x3U << RCC_CCIPR2_I2C4SEL_Pos)  /*!< 0x00000003 */
+#define RCC_CCIPR2_I2C4SEL                   RCC_CCIPR2_I2C4SEL_Msk            
+#define RCC_CCIPR2_I2C4SEL_0                 (0x1U << RCC_CCIPR2_I2C4SEL_Pos)  /*!< 0x00000001 */
+#define RCC_CCIPR2_I2C4SEL_1                 (0x2U << RCC_CCIPR2_I2C4SEL_Pos)  /*!< 0x00000002 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos    (2U)                                               
+#define RNG_CR_RNGEN_Msk    (0x1U << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
+#define RNG_CR_IE_Pos       (3U)                                               
+#define RNG_CR_IE_Msk       (0x1U << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
+#define RNG_CR_IE           RNG_CR_IE_Msk                                      
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos     (0U)                                               
+#define RNG_SR_DRDY_Msk     (0x1U << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
+#define RNG_SR_CECS_Pos     (1U)                                               
+#define RNG_SR_CECS_Msk     (0x1U << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
+#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
+#define RNG_SR_SECS_Pos     (2U)                                               
+#define RNG_SR_SECS_Msk     (0x1U << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
+#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
+#define RNG_SR_CEIS_Pos     (5U)                                               
+#define RNG_SR_CEIS_Msk     (0x1U << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
+#define RNG_SR_SEIS_Pos     (6U)                                               
+#define RNG_SR_SEIS_Msk     (0x1U << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_TAMPER3_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM_Pos                  (22U)                                   
+#define RTC_TR_PM_Msk                  (0x1U << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
+#define RTC_TR_PM                      RTC_TR_PM_Msk                           
+#define RTC_TR_HT_Pos                  (20U)                                   
+#define RTC_TR_HT_Msk                  (0x3U << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
+#define RTC_TR_HT                      RTC_TR_HT_Msk                           
+#define RTC_TR_HT_0                    (0x1U << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
+#define RTC_TR_HT_1                    (0x2U << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
+#define RTC_TR_HU_Pos                  (16U)                                   
+#define RTC_TR_HU_Msk                  (0xFU << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
+#define RTC_TR_HU                      RTC_TR_HU_Msk                           
+#define RTC_TR_HU_0                    (0x1U << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
+#define RTC_TR_HU_1                    (0x2U << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
+#define RTC_TR_HU_2                    (0x4U << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
+#define RTC_TR_HU_3                    (0x8U << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos                 (12U)                                   
+#define RTC_TR_MNT_Msk                 (0x7U << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
+#define RTC_TR_MNT                     RTC_TR_MNT_Msk                          
+#define RTC_TR_MNT_0                   (0x1U << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
+#define RTC_TR_MNT_1                   (0x2U << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
+#define RTC_TR_MNT_2                   (0x4U << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos                 (8U)                                    
+#define RTC_TR_MNU_Msk                 (0xFU << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
+#define RTC_TR_MNU                     RTC_TR_MNU_Msk                          
+#define RTC_TR_MNU_0                   (0x1U << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
+#define RTC_TR_MNU_1                   (0x2U << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
+#define RTC_TR_MNU_2                   (0x4U << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
+#define RTC_TR_MNU_3                   (0x8U << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
+#define RTC_TR_ST_Pos                  (4U)                                    
+#define RTC_TR_ST_Msk                  (0x7U << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
+#define RTC_TR_ST                      RTC_TR_ST_Msk                           
+#define RTC_TR_ST_0                    (0x1U << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
+#define RTC_TR_ST_1                    (0x2U << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
+#define RTC_TR_ST_2                    (0x4U << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
+#define RTC_TR_SU_Pos                  (0U)                                    
+#define RTC_TR_SU_Msk                  (0xFU << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
+#define RTC_TR_SU                      RTC_TR_SU_Msk                           
+#define RTC_TR_SU_0                    (0x1U << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
+#define RTC_TR_SU_1                    (0x2U << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
+#define RTC_TR_SU_2                    (0x4U << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
+#define RTC_TR_SU_3                    (0x8U << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT_Pos                  (20U)                                   
+#define RTC_DR_YT_Msk                  (0xFU << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
+#define RTC_DR_YT                      RTC_DR_YT_Msk                           
+#define RTC_DR_YT_0                    (0x1U << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
+#define RTC_DR_YT_1                    (0x2U << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
+#define RTC_DR_YT_2                    (0x4U << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
+#define RTC_DR_YT_3                    (0x8U << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
+#define RTC_DR_YU_Pos                  (16U)                                   
+#define RTC_DR_YU_Msk                  (0xFU << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
+#define RTC_DR_YU                      RTC_DR_YU_Msk                           
+#define RTC_DR_YU_0                    (0x1U << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
+#define RTC_DR_YU_1                    (0x2U << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
+#define RTC_DR_YU_2                    (0x4U << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
+#define RTC_DR_YU_3                    (0x8U << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos                 (13U)                                   
+#define RTC_DR_WDU_Msk                 (0x7U << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
+#define RTC_DR_WDU                     RTC_DR_WDU_Msk                          
+#define RTC_DR_WDU_0                   (0x1U << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
+#define RTC_DR_WDU_1                   (0x2U << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
+#define RTC_DR_WDU_2                   (0x4U << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
+#define RTC_DR_MT_Pos                  (12U)                                   
+#define RTC_DR_MT_Msk                  (0x1U << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
+#define RTC_DR_MT                      RTC_DR_MT_Msk                           
+#define RTC_DR_MU_Pos                  (8U)                                    
+#define RTC_DR_MU_Msk                  (0xFU << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
+#define RTC_DR_MU                      RTC_DR_MU_Msk                           
+#define RTC_DR_MU_0                    (0x1U << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
+#define RTC_DR_MU_1                    (0x2U << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
+#define RTC_DR_MU_2                    (0x4U << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
+#define RTC_DR_MU_3                    (0x8U << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
+#define RTC_DR_DT_Pos                  (4U)                                    
+#define RTC_DR_DT_Msk                  (0x3U << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
+#define RTC_DR_DT                      RTC_DR_DT_Msk                           
+#define RTC_DR_DT_0                    (0x1U << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
+#define RTC_DR_DT_1                    (0x2U << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
+#define RTC_DR_DU_Pos                  (0U)                                    
+#define RTC_DR_DU_Msk                  (0xFU << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
+#define RTC_DR_DU                      RTC_DR_DU_Msk                           
+#define RTC_DR_DU_0                    (0x1U << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
+#define RTC_DR_DU_1                    (0x2U << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
+#define RTC_DR_DU_2                    (0x4U << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
+#define RTC_DR_DU_3                    (0x8U << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_ITSE_Pos                (24U)                                   
+#define RTC_CR_ITSE_Msk                (0x1U << RTC_CR_ITSE_Pos)               /*!< 0x01000000 */
+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk                         
+#define RTC_CR_COE_Pos                 (23U)                                   
+#define RTC_CR_COE_Msk                 (0x1U << RTC_CR_COE_Pos)                /*!< 0x00800000 */
+#define RTC_CR_COE                     RTC_CR_COE_Msk                          
+#define RTC_CR_OSEL_Pos                (21U)                                   
+#define RTC_CR_OSEL_Msk                (0x3U << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         
+#define RTC_CR_OSEL_0                  (0x1U << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                  (0x2U << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
+#define RTC_CR_POL_Pos                 (20U)                                   
+#define RTC_CR_POL_Msk                 (0x1U << RTC_CR_POL_Pos)                /*!< 0x00100000 */
+#define RTC_CR_POL                     RTC_CR_POL_Msk                          
+#define RTC_CR_COSEL_Pos               (19U)                                   
+#define RTC_CR_COSEL_Msk               (0x1U << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        
+#define RTC_CR_BKP_Pos                 (18U)                                   
+#define RTC_CR_BKP_Msk                 (0x1U << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
+#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          
+#define RTC_CR_SUB1H_Pos               (17U)                                   
+#define RTC_CR_SUB1H_Msk               (0x1U << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        
+#define RTC_CR_ADD1H_Pos               (16U)                                   
+#define RTC_CR_ADD1H_Msk               (0x1U << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        
+#define RTC_CR_TSIE_Pos                (15U)                                   
+#define RTC_CR_TSIE_Msk                (0x1U << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         
+#define RTC_CR_WUTIE_Pos               (14U)                                   
+#define RTC_CR_WUTIE_Msk               (0x1U << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        
+#define RTC_CR_ALRBIE_Pos              (13U)                                   
+#define RTC_CR_ALRBIE_Msk              (0x1U << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       
+#define RTC_CR_ALRAIE_Pos              (12U)                                   
+#define RTC_CR_ALRAIE_Msk              (0x1U << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       
+#define RTC_CR_TSE_Pos                 (11U)                                   
+#define RTC_CR_TSE_Msk                 (0x1U << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
+#define RTC_CR_TSE                     RTC_CR_TSE_Msk                          
+#define RTC_CR_WUTE_Pos                (10U)                                   
+#define RTC_CR_WUTE_Msk                (0x1U << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         
+#define RTC_CR_ALRBE_Pos               (9U)                                    
+#define RTC_CR_ALRBE_Msk               (0x1U << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        
+#define RTC_CR_ALRAE_Pos               (8U)                                    
+#define RTC_CR_ALRAE_Msk               (0x1U << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        
+#define RTC_CR_FMT_Pos                 (6U)                                    
+#define RTC_CR_FMT_Msk                 (0x1U << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
+#define RTC_CR_FMT                     RTC_CR_FMT_Msk                          
+#define RTC_CR_BYPSHAD_Pos             (5U)                                    
+#define RTC_CR_BYPSHAD_Msk             (0x1U << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      
+#define RTC_CR_REFCKON_Pos             (4U)                                    
+#define RTC_CR_REFCKON_Msk             (0x1U << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      
+#define RTC_CR_TSEDGE_Pos              (3U)                                    
+#define RTC_CR_TSEDGE_Msk              (0x1U << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       
+#define RTC_CR_WUCKSEL_Pos             (0U)                                    
+#define RTC_CR_WUCKSEL_Msk             (0x7U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      
+#define RTC_CR_WUCKSEL_0               (0x1U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1               (0x2U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2               (0x4U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK_Pos                 RTC_CR_BKP_Pos
+#define RTC_CR_BCK_Msk                 RTC_CR_BKP_Msk
+#define RTC_CR_BCK                     RTC_CR_BKP
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_ITSF_Pos               (17U)                                   
+#define RTC_ISR_ITSF_Msk               (0x1U << RTC_ISR_ITSF_Pos)              /*!< 0x00020000 */
+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk                        
+#define RTC_ISR_RECALPF_Pos            (16U)                                   
+#define RTC_ISR_RECALPF_Msk            (0x1U << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     
+#define RTC_ISR_TAMP3F_Pos             (15U)                                   
+#define RTC_ISR_TAMP3F_Msk             (0x1U << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk                      
+#define RTC_ISR_TAMP2F_Pos             (14U)                                   
+#define RTC_ISR_TAMP2F_Msk             (0x1U << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      
+#define RTC_ISR_TAMP1F_Pos             (13U)                                   
+#define RTC_ISR_TAMP1F_Msk             (0x1U << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      
+#define RTC_ISR_TSOVF_Pos              (12U)                                   
+#define RTC_ISR_TSOVF_Msk              (0x1U << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       
+#define RTC_ISR_TSF_Pos                (11U)                                   
+#define RTC_ISR_TSF_Msk                (0x1U << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         
+#define RTC_ISR_WUTF_Pos               (10U)                                   
+#define RTC_ISR_WUTF_Msk               (0x1U << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        
+#define RTC_ISR_ALRBF_Pos              (9U)                                    
+#define RTC_ISR_ALRBF_Msk              (0x1U << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       
+#define RTC_ISR_ALRAF_Pos              (8U)                                    
+#define RTC_ISR_ALRAF_Msk              (0x1U << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       
+#define RTC_ISR_INIT_Pos               (7U)                                    
+#define RTC_ISR_INIT_Msk               (0x1U << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        
+#define RTC_ISR_INITF_Pos              (6U)                                    
+#define RTC_ISR_INITF_Msk              (0x1U << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       
+#define RTC_ISR_RSF_Pos                (5U)                                    
+#define RTC_ISR_RSF_Msk                (0x1U << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         
+#define RTC_ISR_INITS_Pos              (4U)                                    
+#define RTC_ISR_INITS_Msk              (0x1U << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       
+#define RTC_ISR_SHPF_Pos               (3U)                                    
+#define RTC_ISR_SHPF_Msk               (0x1U << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        
+#define RTC_ISR_WUTWF_Pos              (2U)                                    
+#define RTC_ISR_WUTWF_Msk              (0x1U << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       
+#define RTC_ISR_ALRBWF_Pos             (1U)                                    
+#define RTC_ISR_ALRBWF_Msk             (0x1U << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      
+#define RTC_ISR_ALRAWF_Pos             (0U)                                    
+#define RTC_ISR_ALRAWF_Msk             (0x1U << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A_Pos          (16U)                                   
+#define RTC_PRER_PREDIV_A_Msk          (0x7FU << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   
+#define RTC_PRER_PREDIV_S_Pos          (0U)                                    
+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFU << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos               (0U)                                    
+#define RTC_WUTR_WUT_Msk               (0xFFFFU << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk                        
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4_Pos            (31U)                                   
+#define RTC_ALRMAR_MSK4_Msk            (0x1U << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     
+#define RTC_ALRMAR_WDSEL_Pos           (30U)                                   
+#define RTC_ALRMAR_WDSEL_Msk           (0x1U << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    
+#define RTC_ALRMAR_DT_Pos              (28U)                                   
+#define RTC_ALRMAR_DT_Msk              (0x3U << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       
+#define RTC_ALRMAR_DT_0                (0x1U << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1                (0x2U << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos              (24U)                                   
+#define RTC_ALRMAR_DU_Msk              (0xFU << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       
+#define RTC_ALRMAR_DU_0                (0x1U << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1                (0x2U << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2                (0x4U << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3                (0x8U << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos            (23U)                                   
+#define RTC_ALRMAR_MSK3_Msk            (0x1U << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     
+#define RTC_ALRMAR_PM_Pos              (22U)                                   
+#define RTC_ALRMAR_PM_Msk              (0x1U << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       
+#define RTC_ALRMAR_HT_Pos              (20U)                                   
+#define RTC_ALRMAR_HT_Msk              (0x3U << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       
+#define RTC_ALRMAR_HT_0                (0x1U << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1                (0x2U << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos              (16U)                                   
+#define RTC_ALRMAR_HU_Msk              (0xFU << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       
+#define RTC_ALRMAR_HU_0                (0x1U << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1                (0x2U << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2                (0x4U << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3                (0x8U << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos            (15U)                                   
+#define RTC_ALRMAR_MSK2_Msk            (0x1U << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     
+#define RTC_ALRMAR_MNT_Pos             (12U)                                   
+#define RTC_ALRMAR_MNT_Msk             (0x7U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      
+#define RTC_ALRMAR_MNT_0               (0x1U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1               (0x2U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2               (0x4U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos             (8U)                                    
+#define RTC_ALRMAR_MNU_Msk             (0xFU << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      
+#define RTC_ALRMAR_MNU_0               (0x1U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1               (0x2U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2               (0x4U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3               (0x8U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos            (7U)                                    
+#define RTC_ALRMAR_MSK1_Msk            (0x1U << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     
+#define RTC_ALRMAR_ST_Pos              (4U)                                    
+#define RTC_ALRMAR_ST_Msk              (0x7U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       
+#define RTC_ALRMAR_ST_0                (0x1U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1                (0x2U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2                (0x4U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos              (0U)                                    
+#define RTC_ALRMAR_SU_Msk              (0xFU << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       
+#define RTC_ALRMAR_SU_0                (0x1U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1                (0x2U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2                (0x4U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3                (0x8U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4_Pos            (31U)                                   
+#define RTC_ALRMBR_MSK4_Msk            (0x1U << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     
+#define RTC_ALRMBR_WDSEL_Pos           (30U)                                   
+#define RTC_ALRMBR_WDSEL_Msk           (0x1U << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    
+#define RTC_ALRMBR_DT_Pos              (28U)                                   
+#define RTC_ALRMBR_DT_Msk              (0x3U << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       
+#define RTC_ALRMBR_DT_0                (0x1U << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1                (0x2U << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos              (24U)                                   
+#define RTC_ALRMBR_DU_Msk              (0xFU << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       
+#define RTC_ALRMBR_DU_0                (0x1U << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1                (0x2U << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2                (0x4U << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3                (0x8U << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos            (23U)                                   
+#define RTC_ALRMBR_MSK3_Msk            (0x1U << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     
+#define RTC_ALRMBR_PM_Pos              (22U)                                   
+#define RTC_ALRMBR_PM_Msk              (0x1U << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       
+#define RTC_ALRMBR_HT_Pos              (20U)                                   
+#define RTC_ALRMBR_HT_Msk              (0x3U << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       
+#define RTC_ALRMBR_HT_0                (0x1U << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1                (0x2U << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos              (16U)                                   
+#define RTC_ALRMBR_HU_Msk              (0xFU << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       
+#define RTC_ALRMBR_HU_0                (0x1U << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1                (0x2U << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2                (0x4U << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3                (0x8U << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos            (15U)                                   
+#define RTC_ALRMBR_MSK2_Msk            (0x1U << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     
+#define RTC_ALRMBR_MNT_Pos             (12U)                                   
+#define RTC_ALRMBR_MNT_Msk             (0x7U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      
+#define RTC_ALRMBR_MNT_0               (0x1U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1               (0x2U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2               (0x4U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos             (8U)                                    
+#define RTC_ALRMBR_MNU_Msk             (0xFU << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      
+#define RTC_ALRMBR_MNU_0               (0x1U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1               (0x2U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2               (0x4U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3               (0x8U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos            (7U)                                    
+#define RTC_ALRMBR_MSK1_Msk            (0x1U << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     
+#define RTC_ALRMBR_ST_Pos              (4U)                                    
+#define RTC_ALRMBR_ST_Msk              (0x7U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       
+#define RTC_ALRMBR_ST_0                (0x1U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1                (0x2U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2                (0x4U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos              (0U)                                    
+#define RTC_ALRMBR_SU_Msk              (0xFU << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       
+#define RTC_ALRMBR_SU_0                (0x1U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1                (0x2U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2                (0x4U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3                (0x8U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos                (0U)                                    
+#define RTC_WPR_KEY_Msk                (0xFFU << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                 (0U)                                    
+#define RTC_SSR_SS_Msk                 (0xFFFFU << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
+#define RTC_SSR_SS                     RTC_SSR_SS_Msk                          
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos           (0U)                                    
+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    
+#define RTC_SHIFTR_ADD1S_Pos           (31U)                                   
+#define RTC_SHIFTR_ADD1S_Msk           (0x1U << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM_Pos                (22U)                                   
+#define RTC_TSTR_PM_Msk                (0x1U << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         
+#define RTC_TSTR_HT_Pos                (20U)                                   
+#define RTC_TSTR_HT_Msk                (0x3U << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         
+#define RTC_TSTR_HT_0                  (0x1U << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                  (0x2U << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos                (16U)                                   
+#define RTC_TSTR_HU_Msk                (0xFU << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         
+#define RTC_TSTR_HU_0                  (0x1U << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                  (0x2U << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                  (0x4U << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                  (0x8U << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos               (12U)                                   
+#define RTC_TSTR_MNT_Msk               (0x7U << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        
+#define RTC_TSTR_MNT_0                 (0x1U << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                 (0x2U << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                 (0x4U << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos               (8U)                                    
+#define RTC_TSTR_MNU_Msk               (0xFU << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        
+#define RTC_TSTR_MNU_0                 (0x1U << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                 (0x2U << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                 (0x4U << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                 (0x8U << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos                (4U)                                    
+#define RTC_TSTR_ST_Msk                (0x7U << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         
+#define RTC_TSTR_ST_0                  (0x1U << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                  (0x2U << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                  (0x4U << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos                (0U)                                    
+#define RTC_TSTR_SU_Msk                (0xFU << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         
+#define RTC_TSTR_SU_0                  (0x1U << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                  (0x2U << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                  (0x4U << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                  (0x8U << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU_Pos               (13U)                                   
+#define RTC_TSDR_WDU_Msk               (0x7U << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        
+#define RTC_TSDR_WDU_0                 (0x1U << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                 (0x2U << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                 (0x4U << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos                (12U)                                   
+#define RTC_TSDR_MT_Msk                (0x1U << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         
+#define RTC_TSDR_MU_Pos                (8U)                                    
+#define RTC_TSDR_MU_Msk                (0xFU << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         
+#define RTC_TSDR_MU_0                  (0x1U << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                  (0x2U << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                  (0x4U << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                  (0x8U << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos                (4U)                                    
+#define RTC_TSDR_DT_Msk                (0x3U << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         
+#define RTC_TSDR_DT_0                  (0x1U << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                  (0x2U << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos                (0U)                                    
+#define RTC_TSDR_DU_Msk                (0xFU << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         
+#define RTC_TSDR_DU_0                  (0x1U << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                  (0x2U << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                  (0x4U << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                  (0x8U << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos               (0U)                                    
+#define RTC_TSSSR_SS_Msk               (0xFFFFU << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk                        
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP_Pos              (15U)                                   
+#define RTC_CALR_CALP_Msk              (0x1U << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       
+#define RTC_CALR_CALW8_Pos             (14U)                                   
+#define RTC_CALR_CALW8_Msk             (0x1U << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      
+#define RTC_CALR_CALW16_Pos            (13U)                                   
+#define RTC_CALR_CALW16_Msk            (0x1U << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     
+#define RTC_CALR_CALM_Pos              (0U)                                    
+#define RTC_CALR_CALM_Msk              (0x1FFU << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       
+#define RTC_CALR_CALM_0                (0x001U << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
+#define RTC_CALR_CALM_1                (0x002U << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
+#define RTC_CALR_CALM_2                (0x004U << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
+#define RTC_CALR_CALM_3                (0x008U << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
+#define RTC_CALR_CALM_4                (0x010U << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
+#define RTC_CALR_CALM_5                (0x020U << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
+#define RTC_CALR_CALM_6                (0x040U << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
+#define RTC_CALR_CALM_7                (0x080U << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
+#define RTC_CALR_CALM_8                (0x100U << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
+
+/********************  Bits definition for RTC_TAMPCR register  ***************/
+#define RTC_TAMPCR_TAMP3MF_Pos         (24U)                                   
+#define RTC_TAMPCR_TAMP3MF_Msk         (0x1U << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk                  
+#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)                                   
+#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk             
+#define RTC_TAMPCR_TAMP3IE_Pos         (22U)                                   
+#define RTC_TAMPCR_TAMP3IE_Msk         (0x1U << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk                  
+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)                                   
+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1U << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  
+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)                                   
+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             
+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)                                   
+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1U << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  
+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)                                   
+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1U << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  
+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)                                   
+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             
+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)                                   
+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1U << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  
+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)                                   
+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                
+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)                                   
+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 
+#define RTC_TAMPCR_TAMPPRCH_0          (0x1U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1          (0x2U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)                                   
+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  
+#define RTC_TAMPCR_TAMPFLT_0           (0x1U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1           (0x2U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)                                    
+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 
+#define RTC_TAMPCR_TAMPFREQ_0          (0x1U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1          (0x2U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2          (0x4U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos          (7U)                                    
+#define RTC_TAMPCR_TAMPTS_Msk          (0x1U << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   
+#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)                                    
+#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1U << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk                 
+#define RTC_TAMPCR_TAMP3E_Pos          (5U)                                    
+#define RTC_TAMPCR_TAMP3E_Msk          (0x1U << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk                   
+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)                                    
+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1U << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 
+#define RTC_TAMPCR_TAMP2E_Pos          (3U)                                    
+#define RTC_TAMPCR_TAMP2E_Msk          (0x1U << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   
+#define RTC_TAMPCR_TAMPIE_Pos          (2U)                                    
+#define RTC_TAMPCR_TAMPIE_Msk          (0x1U << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   
+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)                                    
+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1U << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 
+#define RTC_TAMPCR_TAMP1E_Pos          (0U)                                    
+#define RTC_TAMPCR_TAMP1E_Msk          (0x1U << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS_Pos        (24U)                                   
+#define RTC_ALRMASSR_MASKSS_Msk        (0xFU << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk                 
+#define RTC_ALRMASSR_MASKSS_0          (0x1U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1          (0x2U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2          (0x4U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3          (0x8U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos            (0U)                                    
+#define RTC_ALRMASSR_SS_Msk            (0x7FFFU << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk                     
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)                                   
+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFU << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk                 
+#define RTC_ALRMBSSR_MASKSS_0          (0x1U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1          (0x2U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2          (0x4U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3          (0x8U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos            (0U)                                    
+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFU << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk                     
+
+/********************  Bits definition for RTC_0R register  *******************/
+#define RTC_OR_OUT_RMP_Pos             (1U)                                    
+#define RTC_OR_OUT_RMP_Msk             (0x1U << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      
+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)                                    
+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1U << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 
+
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R_Pos                  (0U)                                    
+#define RTC_BKP0R_Msk                  (0xFFFFFFFFU << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP0R                      RTC_BKP0R_Msk                           
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R_Pos                  (0U)                                    
+#define RTC_BKP1R_Msk                  (0xFFFFFFFFU << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP1R                      RTC_BKP1R_Msk                           
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R_Pos                  (0U)                                    
+#define RTC_BKP2R_Msk                  (0xFFFFFFFFU << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP2R                      RTC_BKP2R_Msk                           
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R_Pos                  (0U)                                    
+#define RTC_BKP3R_Msk                  (0xFFFFFFFFU << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP3R                      RTC_BKP3R_Msk                           
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R_Pos                  (0U)                                    
+#define RTC_BKP4R_Msk                  (0xFFFFFFFFU << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP4R                      RTC_BKP4R_Msk                           
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R_Pos                  (0U)                                    
+#define RTC_BKP5R_Msk                  (0xFFFFFFFFU << RTC_BKP5R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP5R                      RTC_BKP5R_Msk                           
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R_Pos                  (0U)                                    
+#define RTC_BKP6R_Msk                  (0xFFFFFFFFU << RTC_BKP6R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP6R                      RTC_BKP6R_Msk                           
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R_Pos                  (0U)                                    
+#define RTC_BKP7R_Msk                  (0xFFFFFFFFU << RTC_BKP7R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP7R                      RTC_BKP7R_Msk                           
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R_Pos                  (0U)                                    
+#define RTC_BKP8R_Msk                  (0xFFFFFFFFU << RTC_BKP8R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP8R                      RTC_BKP8R_Msk                           
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R_Pos                  (0U)                                    
+#define RTC_BKP9R_Msk                  (0xFFFFFFFFU << RTC_BKP9R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP9R                      RTC_BKP9R_Msk                           
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R_Pos                 (0U)                                    
+#define RTC_BKP10R_Msk                 (0xFFFFFFFFU << RTC_BKP10R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP10R                     RTC_BKP10R_Msk                          
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R_Pos                 (0U)                                    
+#define RTC_BKP11R_Msk                 (0xFFFFFFFFU << RTC_BKP11R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP11R                     RTC_BKP11R_Msk                          
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R_Pos                 (0U)                                    
+#define RTC_BKP12R_Msk                 (0xFFFFFFFFU << RTC_BKP12R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP12R                     RTC_BKP12R_Msk                          
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R_Pos                 (0U)                                    
+#define RTC_BKP13R_Msk                 (0xFFFFFFFFU << RTC_BKP13R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP13R                     RTC_BKP13R_Msk                          
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R_Pos                 (0U)                                    
+#define RTC_BKP14R_Msk                 (0xFFFFFFFFU << RTC_BKP14R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP14R                     RTC_BKP14R_Msk                          
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R_Pos                 (0U)                                    
+#define RTC_BKP15R_Msk                 (0xFFFFFFFFU << RTC_BKP15R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP15R                     RTC_BKP15R_Msk                          
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R_Pos                 (0U)                                    
+#define RTC_BKP16R_Msk                 (0xFFFFFFFFU << RTC_BKP16R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP16R                     RTC_BKP16R_Msk                          
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R_Pos                 (0U)                                    
+#define RTC_BKP17R_Msk                 (0xFFFFFFFFU << RTC_BKP17R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP17R                     RTC_BKP17R_Msk                          
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R_Pos                 (0U)                                    
+#define RTC_BKP18R_Msk                 (0xFFFFFFFFU << RTC_BKP18R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP18R                     RTC_BKP18R_Msk                          
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R_Pos                 (0U)                                    
+#define RTC_BKP19R_Msk                 (0xFFFFFFFFU << RTC_BKP19R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP19R                     RTC_BKP19R_Msk                          
+
+/********************  Bits definition for RTC_BKP20R register  ***************/
+#define RTC_BKP20R_Pos                 (0U)                                    
+#define RTC_BKP20R_Msk                 (0xFFFFFFFFU << RTC_BKP20R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP20R                     RTC_BKP20R_Msk                          
+
+/********************  Bits definition for RTC_BKP21R register  ***************/
+#define RTC_BKP21R_Pos                 (0U)                                    
+#define RTC_BKP21R_Msk                 (0xFFFFFFFFU << RTC_BKP21R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP21R                     RTC_BKP21R_Msk                          
+
+/********************  Bits definition for RTC_BKP22R register  ***************/
+#define RTC_BKP22R_Pos                 (0U)                                    
+#define RTC_BKP22R_Msk                 (0xFFFFFFFFU << RTC_BKP22R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP22R                     RTC_BKP22R_Msk                          
+
+/********************  Bits definition for RTC_BKP23R register  ***************/
+#define RTC_BKP23R_Pos                 (0U)                                    
+#define RTC_BKP23R_Msk                 (0xFFFFFFFFU << RTC_BKP23R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP23R                     RTC_BKP23R_Msk                          
+
+/********************  Bits definition for RTC_BKP24R register  ***************/
+#define RTC_BKP24R_Pos                 (0U)                                    
+#define RTC_BKP24R_Msk                 (0xFFFFFFFFU << RTC_BKP24R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP24R                     RTC_BKP24R_Msk                          
+
+/********************  Bits definition for RTC_BKP25R register  ***************/
+#define RTC_BKP25R_Pos                 (0U)                                    
+#define RTC_BKP25R_Msk                 (0xFFFFFFFFU << RTC_BKP25R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP25R                     RTC_BKP25R_Msk                          
+
+/********************  Bits definition for RTC_BKP26R register  ***************/
+#define RTC_BKP26R_Pos                 (0U)                                    
+#define RTC_BKP26R_Msk                 (0xFFFFFFFFU << RTC_BKP26R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP26R                     RTC_BKP26R_Msk                          
+
+/********************  Bits definition for RTC_BKP27R register  ***************/
+#define RTC_BKP27R_Pos                 (0U)                                    
+#define RTC_BKP27R_Msk                 (0xFFFFFFFFU << RTC_BKP27R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP27R                     RTC_BKP27R_Msk                          
+
+/********************  Bits definition for RTC_BKP28R register  ***************/
+#define RTC_BKP28R_Pos                 (0U)                                    
+#define RTC_BKP28R_Msk                 (0xFFFFFFFFU << RTC_BKP28R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP28R                     RTC_BKP28R_Msk                          
+
+/********************  Bits definition for RTC_BKP29R register  ***************/
+#define RTC_BKP29R_Pos                 (0U)                                    
+#define RTC_BKP29R_Msk                 (0xFFFFFFFFU << RTC_BKP29R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP29R                     RTC_BKP29R_Msk                          
+
+/********************  Bits definition for RTC_BKP30R register  ***************/
+#define RTC_BKP30R_Pos                 (0U)                                    
+#define RTC_BKP30R_Msk                 (0xFFFFFFFFU << RTC_BKP30R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP30R                     RTC_BKP30R_Msk                          
+
+/********************  Bits definition for RTC_BKP31R register  ***************/
+#define RTC_BKP31R_Pos                 (0U)                                    
+#define RTC_BKP31R_Msk                 (0xFFFFFFFFU << RTC_BKP31R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP31R                     RTC_BKP31R_Msk                          
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER                       32U
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SAI_GCR register  *******************/
+#define SAI_GCR_SYNCIN_Pos         (0U)                                        
+#define SAI_GCR_SYNCIN_Msk         (0x3U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define SAI_GCR_SYNCIN_0           (0x1U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1           (0x2U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos        (4U)                                        
+#define SAI_GCR_SYNCOUT_Msk        (0x3U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0          (0x1U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1          (0x2U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define SAI_xCR1_MODE_Pos          (0U)                                        
+#define SAI_xCR1_MODE_Msk          (0x3U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */
+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define SAI_xCR1_MODE_0            (0x1U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1            (0x2U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos        (2U)                                        
+#define SAI_xCR1_PRTCFG_Msk        (0x3U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define SAI_xCR1_PRTCFG_0          (0x1U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1          (0x2U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos            (5U)                                        
+#define SAI_xCR1_DS_Msk            (0x7U << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */
+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0              (0x1U << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
+#define SAI_xCR1_DS_1              (0x2U << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
+#define SAI_xCR1_DS_2              (0x4U << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos      (8U)                                        
+#define SAI_xCR1_LSBFIRST_Msk      (0x1U << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
+#define SAI_xCR1_CKSTR_Pos         (9U)                                        
+#define SAI_xCR1_CKSTR_Msk         (0x1U << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
+
+#define SAI_xCR1_SYNCEN_Pos        (10U)                                       
+#define SAI_xCR1_SYNCEN_Msk        (0x3U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0          (0x1U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1          (0x2U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos          (12U)                                       
+#define SAI_xCR1_MONO_Msk          (0x1U << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */
+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
+#define SAI_xCR1_OUTDRIV_Pos       (13U)                                       
+#define SAI_xCR1_OUTDRIV_Msk       (0x1U << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
+#define SAI_xCR1_SAIEN_Pos         (16U)                                       
+#define SAI_xCR1_SAIEN_Msk         (0x1U << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
+#define SAI_xCR1_DMAEN_Pos         (17U)                                       
+#define SAI_xCR1_DMAEN_Msk         (0x1U << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
+#define SAI_xCR1_NODIV_Pos         (19U)                                       
+#define SAI_xCR1_NODIV_Msk         (0x1U << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */
+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
+
+#define SAI_xCR1_MCKDIV_Pos        (20U)                                       
+#define SAI_xCR1_MCKDIV_Msk        (0xFU << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */
+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */
+#define SAI_xCR1_MCKDIV_0          (0x00100000U)                               /*!<Bit 0  */
+#define SAI_xCR1_MCKDIV_1          (0x00200000U)                               /*!<Bit 1  */
+#define SAI_xCR1_MCKDIV_2          (0x00400000U)                               /*!<Bit 2  */
+#define SAI_xCR1_MCKDIV_3          (0x00800000U)                               /*!<Bit 3  */
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define SAI_xCR2_FTH_Pos           (0U)                                        
+#define SAI_xCR2_FTH_Msk           (0x7U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */
+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
+#define SAI_xCR2_FTH_0             (0x1U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1             (0x2U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2             (0x4U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos        (3U)                                        
+#define SAI_xCR2_FFLUSH_Msk        (0x1U << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
+#define SAI_xCR2_TRIS_Pos          (4U)                                        
+#define SAI_xCR2_TRIS_Msk          (0x1U << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */
+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos          (5U)                                        
+#define SAI_xCR2_MUTE_Msk          (0x1U << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */
+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
+#define SAI_xCR2_MUTEVAL_Pos       (6U)                                        
+#define SAI_xCR2_MUTEVAL_Msk       (0x1U << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
+
+
+#define SAI_xCR2_MUTECNT_Pos       (7U)                                        
+#define SAI_xCR2_MUTECNT_Msk       (0x3FU << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0         (0x01U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1         (0x02U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2         (0x04U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3         (0x08U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4         (0x10U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5         (0x20U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos           (13U)                                       
+#define SAI_xCR2_CPL_Msk           (0x1U << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */
+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!<CPL mode                    */
+#define SAI_xCR2_COMP_Pos          (14U)                                       
+#define SAI_xCR2_COMP_Msk          (0x3U << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */
+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0            (0x1U << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1            (0x2U << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
+
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define SAI_xFRCR_FRL_Pos          (0U)                                        
+#define SAI_xFRCR_FRL_Msk          (0xFFU << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */
+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */
+#define SAI_xFRCR_FRL_0            (0x01U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1            (0x02U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2            (0x04U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3            (0x08U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4            (0x10U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5            (0x20U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6            (0x40U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7            (0x80U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos        (8U)                                        
+#define SAI_xFRCR_FSALL_Msk        (0x7FU << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */
+#define SAI_xFRCR_FSALL_0          (0x01U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1          (0x02U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2          (0x04U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3          (0x08U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4          (0x10U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5          (0x20U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6          (0x40U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos        (16U)                                       
+#define SAI_xFRCR_FSDEF_Msk        (0x1U << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos        (17U)                                       
+#define SAI_xFRCR_FSPOL_Msk        (0x1U << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
+#define SAI_xFRCR_FSOFF_Pos        (18U)                                       
+#define SAI_xFRCR_FSOFF_Msk        (0x1U << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define SAI_xSLOTR_FBOFF_Pos       (0U)                                        
+#define SAI_xSLOTR_FBOFF_Msk       (0x1FU << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */
+#define SAI_xSLOTR_FBOFF_0         (0x01U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1         (0x02U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2         (0x04U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3         (0x08U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4         (0x10U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)                                        
+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
+#define SAI_xSLOTR_SLOTSZ_0        (0x1U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1        (0x2U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos      (8U)                                        
+#define SAI_xSLOTR_NBSLOT_Msk      (0xFU << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define SAI_xSLOTR_NBSLOT_0        (0x1U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1        (0x2U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2        (0x4U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3        (0x8U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos      (16U)                                       
+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define SAI_xIMR_OVRUDRIE_Pos      (0U)                                        
+#define SAI_xIMR_OVRUDRIE_Msk      (0x1U << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
+#define SAI_xIMR_MUTEDETIE_Pos     (1U)                                        
+#define SAI_xIMR_MUTEDETIE_Msk     (0x1U << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
+#define SAI_xIMR_WCKCFGIE_Pos      (2U)                                        
+#define SAI_xIMR_WCKCFGIE_Msk      (0x1U << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
+#define SAI_xIMR_FREQIE_Pos        (3U)                                        
+#define SAI_xIMR_FREQIE_Msk        (0x1U << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
+#define SAI_xIMR_CNRDYIE_Pos       (4U)                                        
+#define SAI_xIMR_CNRDYIE_Msk       (0x1U << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
+#define SAI_xIMR_AFSDETIE_Pos      (5U)                                        
+#define SAI_xIMR_AFSDETIE_Msk      (0x1U << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
+#define SAI_xIMR_LFSDETIE_Pos      (6U)                                        
+#define SAI_xIMR_LFSDETIE_Msk      (0x1U << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define SAI_xSR_OVRUDR_Pos         (0U)                                        
+#define SAI_xSR_OVRUDR_Msk         (0x1U << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
+#define SAI_xSR_MUTEDET_Pos        (1U)                                        
+#define SAI_xSR_MUTEDET_Msk        (0x1U << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
+#define SAI_xSR_WCKCFG_Pos         (2U)                                        
+#define SAI_xSR_WCKCFG_Msk         (0x1U << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
+#define SAI_xSR_FREQ_Pos           (3U)                                        
+#define SAI_xSR_FREQ_Msk           (0x1U << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */
+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
+#define SAI_xSR_CNRDY_Pos          (4U)                                        
+#define SAI_xSR_CNRDY_Msk          (0x1U << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */
+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
+#define SAI_xSR_AFSDET_Pos         (5U)                                        
+#define SAI_xSR_AFSDET_Msk         (0x1U << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */
+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
+#define SAI_xSR_LFSDET_Pos         (6U)                                        
+#define SAI_xSR_LFSDET_Msk         (0x1U << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */
+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
+
+#define SAI_xSR_FLVL_Pos           (16U)                                       
+#define SAI_xSR_FLVL_Msk           (0x7U << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */
+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define SAI_xSR_FLVL_0             (0x1U << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1             (0x2U << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2             (0x4U << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define SAI_xCLRFR_COVRUDR_Pos     (0U)                                        
+#define SAI_xCLRFR_COVRUDR_Msk     (0x1U << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)                                        
+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1U << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)                                        
+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1U << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
+#define SAI_xCLRFR_CFREQ_Pos       (3U)                                        
+#define SAI_xCLRFR_CFREQ_Msk       (0x1U << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
+#define SAI_xCLRFR_CCNRDY_Pos      (4U)                                        
+#define SAI_xCLRFR_CCNRDY_Msk      (0x1U << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
+#define SAI_xCLRFR_CAFSDET_Pos     (5U)                                        
+#define SAI_xCLRFR_CAFSDET_Msk     (0x1U << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
+#define SAI_xCLRFR_CLFSDET_Pos     (6U)                                        
+#define SAI_xCLRFR_CLFSDET_Msk     (0x1U << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  ******************/
+#define SAI_xDR_DATA_Pos           (0U)                                        
+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFU << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk                            
+
+/******************************************************************************/
+/*                                                                            */
+/*                          LCD Controller (LCD)                              */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for LCD_CR register  *********************/
+#define LCD_CR_LCDEN_Pos            (0U)                                       
+#define LCD_CR_LCDEN_Msk            (0x1U << LCD_CR_LCDEN_Pos)                 /*!< 0x00000001 */
+#define LCD_CR_LCDEN                LCD_CR_LCDEN_Msk                           /*!< LCD Enable Bit */
+#define LCD_CR_VSEL_Pos             (1U)                                       
+#define LCD_CR_VSEL_Msk             (0x1U << LCD_CR_VSEL_Pos)                  /*!< 0x00000002 */
+#define LCD_CR_VSEL                 LCD_CR_VSEL_Msk                            /*!< Voltage source selector Bit */
+
+#define LCD_CR_DUTY_Pos             (2U)                                       
+#define LCD_CR_DUTY_Msk             (0x7U << LCD_CR_DUTY_Pos)                  /*!< 0x0000001C */
+#define LCD_CR_DUTY                 LCD_CR_DUTY_Msk                            /*!< DUTY[2:0] bits (Duty selector) */
+#define LCD_CR_DUTY_0               (0x1U << LCD_CR_DUTY_Pos)                  /*!< 0x00000004 */
+#define LCD_CR_DUTY_1               (0x2U << LCD_CR_DUTY_Pos)                  /*!< 0x00000008 */
+#define LCD_CR_DUTY_2               (0x4U << LCD_CR_DUTY_Pos)                  /*!< 0x00000010 */
+
+#define LCD_CR_BIAS_Pos             (5U)                                       
+#define LCD_CR_BIAS_Msk             (0x3U << LCD_CR_BIAS_Pos)                  /*!< 0x00000060 */
+#define LCD_CR_BIAS                 LCD_CR_BIAS_Msk                            /*!< BIAS[1:0] bits (Bias selector) */
+#define LCD_CR_BIAS_0               (0x1U << LCD_CR_BIAS_Pos)                  /*!< 0x00000020 */
+#define LCD_CR_BIAS_1               (0x2U << LCD_CR_BIAS_Pos)                  /*!< 0x00000040 */
+
+#define LCD_CR_MUX_SEG_Pos          (7U)                                       
+#define LCD_CR_MUX_SEG_Msk          (0x1U << LCD_CR_MUX_SEG_Pos)               /*!< 0x00000080 */
+#define LCD_CR_MUX_SEG              LCD_CR_MUX_SEG_Msk                         /*!< Mux Segment Enable Bit */
+#define LCD_CR_BUFEN_Pos            (8U)                                       
+#define LCD_CR_BUFEN_Msk            (0x1U << LCD_CR_BUFEN_Pos)                 /*!< 0x00000100 */
+#define LCD_CR_BUFEN                LCD_CR_BUFEN_Msk                           /*!< Voltage output buffer enable */
+
+/*******************  Bit definition for LCD_FCR register  ********************/
+#define LCD_FCR_HD_Pos              (0U)                                       
+#define LCD_FCR_HD_Msk              (0x1U << LCD_FCR_HD_Pos)                   /*!< 0x00000001 */
+#define LCD_FCR_HD                  LCD_FCR_HD_Msk                             /*!< High Drive Enable Bit */
+#define LCD_FCR_SOFIE_Pos           (1U)                                       
+#define LCD_FCR_SOFIE_Msk           (0x1U << LCD_FCR_SOFIE_Pos)                /*!< 0x00000002 */
+#define LCD_FCR_SOFIE               LCD_FCR_SOFIE_Msk                          /*!< Start of Frame Interrupt Enable Bit */
+#define LCD_FCR_UDDIE_Pos           (3U)                                       
+#define LCD_FCR_UDDIE_Msk           (0x1U << LCD_FCR_UDDIE_Pos)                /*!< 0x00000008 */
+#define LCD_FCR_UDDIE               LCD_FCR_UDDIE_Msk                          /*!< Update Display Done Interrupt Enable Bit */
+
+#define LCD_FCR_PON_Pos             (4U)                                       
+#define LCD_FCR_PON_Msk             (0x7U << LCD_FCR_PON_Pos)                  /*!< 0x00000070 */
+#define LCD_FCR_PON                 LCD_FCR_PON_Msk                            /*!< PON[2:0] bits (Pulse ON Duration) */
+#define LCD_FCR_PON_0               (0x1U << LCD_FCR_PON_Pos)                  /*!< 0x00000010 */
+#define LCD_FCR_PON_1               (0x2U << LCD_FCR_PON_Pos)                  /*!< 0x00000020 */
+#define LCD_FCR_PON_2               (0x4U << LCD_FCR_PON_Pos)                  /*!< 0x00000040 */
+
+#define LCD_FCR_DEAD_Pos            (7U)                                       
+#define LCD_FCR_DEAD_Msk            (0x7U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000380 */
+#define LCD_FCR_DEAD                LCD_FCR_DEAD_Msk                           /*!< DEAD[2:0] bits (DEAD Time) */
+#define LCD_FCR_DEAD_0              (0x1U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000080 */
+#define LCD_FCR_DEAD_1              (0x2U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000100 */
+#define LCD_FCR_DEAD_2              (0x4U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000200 */
+
+#define LCD_FCR_CC_Pos              (10U)                                      
+#define LCD_FCR_CC_Msk              (0x7U << LCD_FCR_CC_Pos)                   /*!< 0x00001C00 */
+#define LCD_FCR_CC                  LCD_FCR_CC_Msk                             /*!< CC[2:0] bits (Contrast Control) */
+#define LCD_FCR_CC_0                (0x1U << LCD_FCR_CC_Pos)                   /*!< 0x00000400 */
+#define LCD_FCR_CC_1                (0x2U << LCD_FCR_CC_Pos)                   /*!< 0x00000800 */
+#define LCD_FCR_CC_2                (0x4U << LCD_FCR_CC_Pos)                   /*!< 0x00001000 */
+
+#define LCD_FCR_BLINKF_Pos          (13U)                                      
+#define LCD_FCR_BLINKF_Msk          (0x7U << LCD_FCR_BLINKF_Pos)               /*!< 0x0000E000 */
+#define LCD_FCR_BLINKF              LCD_FCR_BLINKF_Msk                         /*!< BLINKF[2:0] bits (Blink Frequency) */
+#define LCD_FCR_BLINKF_0            (0x1U << LCD_FCR_BLINKF_Pos)               /*!< 0x00002000 */
+#define LCD_FCR_BLINKF_1            (0x2U << LCD_FCR_BLINKF_Pos)               /*!< 0x00004000 */
+#define LCD_FCR_BLINKF_2            (0x4U << LCD_FCR_BLINKF_Pos)               /*!< 0x00008000 */
+
+#define LCD_FCR_BLINK_Pos           (16U)                                      
+#define LCD_FCR_BLINK_Msk           (0x3U << LCD_FCR_BLINK_Pos)                /*!< 0x00030000 */
+#define LCD_FCR_BLINK               LCD_FCR_BLINK_Msk                          /*!< BLINK[1:0] bits (Blink Enable) */
+#define LCD_FCR_BLINK_0             (0x1U << LCD_FCR_BLINK_Pos)                /*!< 0x00010000 */
+#define LCD_FCR_BLINK_1             (0x2U << LCD_FCR_BLINK_Pos)                /*!< 0x00020000 */
+
+#define LCD_FCR_DIV_Pos             (18U)                                      
+#define LCD_FCR_DIV_Msk             (0xFU << LCD_FCR_DIV_Pos)                  /*!< 0x003C0000 */
+#define LCD_FCR_DIV                 LCD_FCR_DIV_Msk                            /*!< DIV[3:0] bits (Divider) */
+#define LCD_FCR_PS_Pos              (22U)                                      
+#define LCD_FCR_PS_Msk              (0xFU << LCD_FCR_PS_Pos)                   /*!< 0x03C00000 */
+#define LCD_FCR_PS                  LCD_FCR_PS_Msk                             /*!< PS[3:0] bits (Prescaler) */
+
+/*******************  Bit definition for LCD_SR register  *********************/
+#define LCD_SR_ENS_Pos              (0U)                                       
+#define LCD_SR_ENS_Msk              (0x1U << LCD_SR_ENS_Pos)                   /*!< 0x00000001 */
+#define LCD_SR_ENS                  LCD_SR_ENS_Msk                             /*!< LCD Enabled Bit */
+#define LCD_SR_SOF_Pos              (1U)                                       
+#define LCD_SR_SOF_Msk              (0x1U << LCD_SR_SOF_Pos)                   /*!< 0x00000002 */
+#define LCD_SR_SOF                  LCD_SR_SOF_Msk                             /*!< Start Of Frame Flag Bit */
+#define LCD_SR_UDR_Pos              (2U)                                       
+#define LCD_SR_UDR_Msk              (0x1U << LCD_SR_UDR_Pos)                   /*!< 0x00000004 */
+#define LCD_SR_UDR                  LCD_SR_UDR_Msk                             /*!< Update Display Request Bit */
+#define LCD_SR_UDD_Pos              (3U)                                       
+#define LCD_SR_UDD_Msk              (0x1U << LCD_SR_UDD_Pos)                   /*!< 0x00000008 */
+#define LCD_SR_UDD                  LCD_SR_UDD_Msk                             /*!< Update Display Done Flag Bit */
+#define LCD_SR_RDY_Pos              (4U)                                       
+#define LCD_SR_RDY_Msk              (0x1U << LCD_SR_RDY_Pos)                   /*!< 0x00000010 */
+#define LCD_SR_RDY                  LCD_SR_RDY_Msk                             /*!< Ready Flag Bit */
+#define LCD_SR_FCRSR_Pos            (5U)                                       
+#define LCD_SR_FCRSR_Msk            (0x1U << LCD_SR_FCRSR_Pos)                 /*!< 0x00000020 */
+#define LCD_SR_FCRSR                LCD_SR_FCRSR_Msk                           /*!< LCD FCR Register Synchronization Flag Bit */
+
+/*******************  Bit definition for LCD_CLR register  ********************/
+#define LCD_CLR_SOFC_Pos            (1U)                                       
+#define LCD_CLR_SOFC_Msk            (0x1U << LCD_CLR_SOFC_Pos)                 /*!< 0x00000002 */
+#define LCD_CLR_SOFC                LCD_CLR_SOFC_Msk                           /*!< Start Of Frame Flag Clear Bit */
+#define LCD_CLR_UDDC_Pos            (3U)                                       
+#define LCD_CLR_UDDC_Msk            (0x1U << LCD_CLR_UDDC_Pos)                 /*!< 0x00000008 */
+#define LCD_CLR_UDDC                LCD_CLR_UDDC_Msk                           /*!< Update Display Done Flag Clear Bit */
+
+/*******************  Bit definition for LCD_RAM register  ********************/
+#define LCD_RAM_SEGMENT_DATA_Pos    (0U)                                       
+#define LCD_RAM_SEGMENT_DATA_Msk    (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos)  /*!< 0xFFFFFFFF */
+#define LCD_RAM_SEGMENT_DATA        LCD_RAM_SEGMENT_DATA_Msk                   /*!< Segment Data Bits */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           SDMMC Interface                                  */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDMMC_POWER register  ******************/
+#define SDMMC_POWER_PWRCTRL_Pos         (0U)                                   
+#define SDMMC_POWER_PWRCTRL_Msk         (0x3U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000003 */
+#define SDMMC_POWER_PWRCTRL             SDMMC_POWER_PWRCTRL_Msk                /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDMMC_POWER_PWRCTRL_0           (0x1U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000001 */
+#define SDMMC_POWER_PWRCTRL_1           (0x2U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000002 */
+
+/******************  Bit definition for SDMMC_CLKCR register  ******************/
+#define SDMMC_CLKCR_CLKDIV_Pos          (0U)                                   
+#define SDMMC_CLKCR_CLKDIV_Msk          (0xFFU << SDMMC_CLKCR_CLKDIV_Pos)      /*!< 0x000000FF */
+#define SDMMC_CLKCR_CLKDIV              SDMMC_CLKCR_CLKDIV_Msk                 /*!<Clock divide factor             */
+#define SDMMC_CLKCR_CLKEN_Pos           (8U)                                   
+#define SDMMC_CLKCR_CLKEN_Msk           (0x1U << SDMMC_CLKCR_CLKEN_Pos)        /*!< 0x00000100 */
+#define SDMMC_CLKCR_CLKEN               SDMMC_CLKCR_CLKEN_Msk                  /*!<Clock enable bit                */
+#define SDMMC_CLKCR_PWRSAV_Pos          (9U)                                   
+#define SDMMC_CLKCR_PWRSAV_Msk          (0x1U << SDMMC_CLKCR_PWRSAV_Pos)       /*!< 0x00000200 */
+#define SDMMC_CLKCR_PWRSAV              SDMMC_CLKCR_PWRSAV_Msk                 /*!<Power saving configuration bit  */
+#define SDMMC_CLKCR_BYPASS_Pos          (10U)                                  
+#define SDMMC_CLKCR_BYPASS_Msk          (0x1U << SDMMC_CLKCR_BYPASS_Pos)       /*!< 0x00000400 */
+#define SDMMC_CLKCR_BYPASS              SDMMC_CLKCR_BYPASS_Msk                 /*!<Clock divider bypass enable bit */
+
+#define SDMMC_CLKCR_WIDBUS_Pos          (11U)                                  
+#define SDMMC_CLKCR_WIDBUS_Msk          (0x3U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00001800 */
+#define SDMMC_CLKCR_WIDBUS              SDMMC_CLKCR_WIDBUS_Msk                 /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDMMC_CLKCR_WIDBUS_0            (0x1U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00000800 */
+#define SDMMC_CLKCR_WIDBUS_1            (0x2U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00001000 */
+
+#define SDMMC_CLKCR_NEGEDGE_Pos         (13U)                                  
+#define SDMMC_CLKCR_NEGEDGE_Msk         (0x1U << SDMMC_CLKCR_NEGEDGE_Pos)      /*!< 0x00002000 */
+#define SDMMC_CLKCR_NEGEDGE             SDMMC_CLKCR_NEGEDGE_Msk                /*!<SDMMC_CK dephasing selection bit */
+#define SDMMC_CLKCR_HWFC_EN_Pos         (14U)                                  
+#define SDMMC_CLKCR_HWFC_EN_Msk         (0x1U << SDMMC_CLKCR_HWFC_EN_Pos)      /*!< 0x00004000 */
+#define SDMMC_CLKCR_HWFC_EN             SDMMC_CLKCR_HWFC_EN_Msk                /*!<HW Flow Control enable          */
+
+/*******************  Bit definition for SDMMC_ARG register  *******************/
+#define SDMMC_ARG_CMDARG_Pos            (0U)                                   
+#define SDMMC_ARG_CMDARG_Msk            (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos)  /*!< 0xFFFFFFFF */
+#define SDMMC_ARG_CMDARG                SDMMC_ARG_CMDARG_Msk                   /*!<Command argument */
+
+/*******************  Bit definition for SDMMC_CMD register  *******************/
+#define SDMMC_CMD_CMDINDEX_Pos          (0U)                                   
+#define SDMMC_CMD_CMDINDEX_Msk          (0x3FU << SDMMC_CMD_CMDINDEX_Pos)      /*!< 0x0000003F */
+#define SDMMC_CMD_CMDINDEX              SDMMC_CMD_CMDINDEX_Msk                 /*!<Command Index                               */
+
+#define SDMMC_CMD_WAITRESP_Pos          (6U)                                   
+#define SDMMC_CMD_WAITRESP_Msk          (0x3U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x000000C0 */
+#define SDMMC_CMD_WAITRESP              SDMMC_CMD_WAITRESP_Msk                 /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDMMC_CMD_WAITRESP_0            (0x1U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000040 */
+#define SDMMC_CMD_WAITRESP_1            (0x2U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000080 */
+
+#define SDMMC_CMD_WAITINT_Pos           (8U)                                   
+#define SDMMC_CMD_WAITINT_Msk           (0x1U << SDMMC_CMD_WAITINT_Pos)        /*!< 0x00000100 */
+#define SDMMC_CMD_WAITINT               SDMMC_CMD_WAITINT_Msk                  /*!<CPSM Waits for Interrupt Request                               */
+#define SDMMC_CMD_WAITPEND_Pos          (9U)                                   
+#define SDMMC_CMD_WAITPEND_Msk          (0x1U << SDMMC_CMD_WAITPEND_Pos)       /*!< 0x00000200 */
+#define SDMMC_CMD_WAITPEND              SDMMC_CMD_WAITPEND_Msk                 /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDMMC_CMD_CPSMEN_Pos            (10U)                                  
+#define SDMMC_CMD_CPSMEN_Msk            (0x1U << SDMMC_CMD_CPSMEN_Pos)         /*!< 0x00000400 */
+#define SDMMC_CMD_CPSMEN                SDMMC_CMD_CPSMEN_Msk                   /*!<Command path state machine (CPSM) Enable bit                   */
+#define SDMMC_CMD_SDIOSUSPEND_Pos       (11U)                                  
+#define SDMMC_CMD_SDIOSUSPEND_Msk       (0x1U << SDMMC_CMD_SDIOSUSPEND_Pos)    /*!< 0x00000800 */
+#define SDMMC_CMD_SDIOSUSPEND           SDMMC_CMD_SDIOSUSPEND_Msk              /*!<SD I/O suspend command                                         */
+
+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
+#define SDMMC_RESPCMD_RESPCMD_Pos       (0U)                                   
+#define SDMMC_RESPCMD_RESPCMD_Msk       (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos)   /*!< 0x0000003F */
+#define SDMMC_RESPCMD_RESPCMD           SDMMC_RESPCMD_RESPCMD_Msk              /*!<Response command index */
+
+/******************  Bit definition for SDMMC_RESP1 register  ******************/
+#define SDMMC_RESP1_CARDSTATUS1_Pos     (0U)                                   
+#define SDMMC_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP1_CARDSTATUS1         SDMMC_RESP1_CARDSTATUS1_Msk            /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP2 register  ******************/
+#define SDMMC_RESP2_CARDSTATUS2_Pos     (0U)                                   
+#define SDMMC_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP2_CARDSTATUS2         SDMMC_RESP2_CARDSTATUS2_Msk            /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP3 register  ******************/
+#define SDMMC_RESP3_CARDSTATUS3_Pos     (0U)                                   
+#define SDMMC_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP3_CARDSTATUS3         SDMMC_RESP3_CARDSTATUS3_Msk            /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP4 register  ******************/
+#define SDMMC_RESP4_CARDSTATUS4_Pos     (0U)                                   
+#define SDMMC_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP4_CARDSTATUS4         SDMMC_RESP4_CARDSTATUS4_Msk            /*!<Card Status */
+
+/******************  Bit definition for SDMMC_DTIMER register  *****************/
+#define SDMMC_DTIMER_DATATIME_Pos       (0U)                                   
+#define SDMMC_DTIMER_DATATIME_Msk       (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_DTIMER_DATATIME           SDMMC_DTIMER_DATATIME_Msk              /*!<Data timeout period. */
+
+/******************  Bit definition for SDMMC_DLEN register  *******************/
+#define SDMMC_DLEN_DATALENGTH_Pos       (0U)                                   
+#define SDMMC_DLEN_DATALENGTH_Msk       (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DLEN_DATALENGTH           SDMMC_DLEN_DATALENGTH_Msk              /*!<Data length value    */
+
+/******************  Bit definition for SDMMC_DCTRL register  ******************/
+#define SDMMC_DCTRL_DTEN_Pos            (0U)                                   
+#define SDMMC_DCTRL_DTEN_Msk            (0x1U << SDMMC_DCTRL_DTEN_Pos)         /*!< 0x00000001 */
+#define SDMMC_DCTRL_DTEN                SDMMC_DCTRL_DTEN_Msk                   /*!<Data transfer enabled bit         */
+#define SDMMC_DCTRL_DTDIR_Pos           (1U)                                   
+#define SDMMC_DCTRL_DTDIR_Msk           (0x1U << SDMMC_DCTRL_DTDIR_Pos)        /*!< 0x00000002 */
+#define SDMMC_DCTRL_DTDIR               SDMMC_DCTRL_DTDIR_Msk                  /*!<Data transfer direction selection */
+#define SDMMC_DCTRL_DTMODE_Pos          (2U)                                   
+#define SDMMC_DCTRL_DTMODE_Msk          (0x1U << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000004 */
+#define SDMMC_DCTRL_DTMODE              SDMMC_DCTRL_DTMODE_Msk                 /*!<Data transfer mode selection      */
+#define SDMMC_DCTRL_DMAEN_Pos           (3U)                                   
+#define SDMMC_DCTRL_DMAEN_Msk           (0x1U << SDMMC_DCTRL_DMAEN_Pos)        /*!< 0x00000008 */
+#define SDMMC_DCTRL_DMAEN               SDMMC_DCTRL_DMAEN_Msk                  /*!<DMA enabled bit                   */
+
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos      (4U)                                   
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk      (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x000000F0 */
+#define SDMMC_DCTRL_DBLOCKSIZE          SDMMC_DCTRL_DBLOCKSIZE_Msk             /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDMMC_DCTRL_DBLOCKSIZE_0        (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000010 */
+#define SDMMC_DCTRL_DBLOCKSIZE_1        (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000020 */
+#define SDMMC_DCTRL_DBLOCKSIZE_2        (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000040 */
+#define SDMMC_DCTRL_DBLOCKSIZE_3        (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000080 */
+
+#define SDMMC_DCTRL_RWSTART_Pos         (8U)                                   
+#define SDMMC_DCTRL_RWSTART_Msk         (0x1U << SDMMC_DCTRL_RWSTART_Pos)      /*!< 0x00000100 */
+#define SDMMC_DCTRL_RWSTART             SDMMC_DCTRL_RWSTART_Msk                /*!<Read wait start         */
+#define SDMMC_DCTRL_RWSTOP_Pos          (9U)                                   
+#define SDMMC_DCTRL_RWSTOP_Msk          (0x1U << SDMMC_DCTRL_RWSTOP_Pos)       /*!< 0x00000200 */
+#define SDMMC_DCTRL_RWSTOP              SDMMC_DCTRL_RWSTOP_Msk                 /*!<Read wait stop          */
+#define SDMMC_DCTRL_RWMOD_Pos           (10U)                                  
+#define SDMMC_DCTRL_RWMOD_Msk           (0x1U << SDMMC_DCTRL_RWMOD_Pos)        /*!< 0x00000400 */
+#define SDMMC_DCTRL_RWMOD               SDMMC_DCTRL_RWMOD_Msk                  /*!<Read wait mode          */
+#define SDMMC_DCTRL_SDIOEN_Pos          (11U)                                  
+#define SDMMC_DCTRL_SDIOEN_Msk          (0x1U << SDMMC_DCTRL_SDIOEN_Pos)       /*!< 0x00000800 */
+#define SDMMC_DCTRL_SDIOEN              SDMMC_DCTRL_SDIOEN_Msk                 /*!<SD I/O enable functions */
+
+/******************  Bit definition for SDMMC_DCOUNT register  *****************/
+#define SDMMC_DCOUNT_DATACOUNT_Pos      (0U)                                   
+#define SDMMC_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DCOUNT_DATACOUNT          SDMMC_DCOUNT_DATACOUNT_Msk             /*!<Data count value */
+
+/******************  Bit definition for SDMMC_STA register  ********************/
+#define SDMMC_STA_CCRCFAIL_Pos          (0U)                                   
+#define SDMMC_STA_CCRCFAIL_Msk          (0x1U << SDMMC_STA_CCRCFAIL_Pos)       /*!< 0x00000001 */
+#define SDMMC_STA_CCRCFAIL              SDMMC_STA_CCRCFAIL_Msk                 /*!<Command response received (CRC check failed)  */
+#define SDMMC_STA_DCRCFAIL_Pos          (1U)                                   
+#define SDMMC_STA_DCRCFAIL_Msk          (0x1U << SDMMC_STA_DCRCFAIL_Pos)       /*!< 0x00000002 */
+#define SDMMC_STA_DCRCFAIL              SDMMC_STA_DCRCFAIL_Msk                 /*!<Data block sent/received (CRC check failed)   */
+#define SDMMC_STA_CTIMEOUT_Pos          (2U)                                   
+#define SDMMC_STA_CTIMEOUT_Msk          (0x1U << SDMMC_STA_CTIMEOUT_Pos)       /*!< 0x00000004 */
+#define SDMMC_STA_CTIMEOUT              SDMMC_STA_CTIMEOUT_Msk                 /*!<Command response timeout                      */
+#define SDMMC_STA_DTIMEOUT_Pos          (3U)                                   
+#define SDMMC_STA_DTIMEOUT_Msk          (0x1U << SDMMC_STA_DTIMEOUT_Pos)       /*!< 0x00000008 */
+#define SDMMC_STA_DTIMEOUT              SDMMC_STA_DTIMEOUT_Msk                 /*!<Data timeout                                  */
+#define SDMMC_STA_TXUNDERR_Pos          (4U)                                   
+#define SDMMC_STA_TXUNDERR_Msk          (0x1U << SDMMC_STA_TXUNDERR_Pos)       /*!< 0x00000010 */
+#define SDMMC_STA_TXUNDERR              SDMMC_STA_TXUNDERR_Msk                 /*!<Transmit FIFO underrun error                  */
+#define SDMMC_STA_RXOVERR_Pos           (5U)                                   
+#define SDMMC_STA_RXOVERR_Msk           (0x1U << SDMMC_STA_RXOVERR_Pos)        /*!< 0x00000020 */
+#define SDMMC_STA_RXOVERR               SDMMC_STA_RXOVERR_Msk                  /*!<Received FIFO overrun error                   */
+#define SDMMC_STA_CMDREND_Pos           (6U)                                   
+#define SDMMC_STA_CMDREND_Msk           (0x1U << SDMMC_STA_CMDREND_Pos)        /*!< 0x00000040 */
+#define SDMMC_STA_CMDREND               SDMMC_STA_CMDREND_Msk                  /*!<Command response received (CRC check passed)  */
+#define SDMMC_STA_CMDSENT_Pos           (7U)                                   
+#define SDMMC_STA_CMDSENT_Msk           (0x1U << SDMMC_STA_CMDSENT_Pos)        /*!< 0x00000080 */
+#define SDMMC_STA_CMDSENT               SDMMC_STA_CMDSENT_Msk                  /*!<Command sent (no response required)           */
+#define SDMMC_STA_DATAEND_Pos           (8U)                                   
+#define SDMMC_STA_DATAEND_Msk           (0x1U << SDMMC_STA_DATAEND_Pos)        /*!< 0x00000100 */
+#define SDMMC_STA_DATAEND               SDMMC_STA_DATAEND_Msk                  /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define SDMMC_STA_STBITERR_Pos          (9U)                                   
+#define SDMMC_STA_STBITERR_Msk          (0x1U << SDMMC_STA_STBITERR_Pos)       /*!< 0x00000200 */
+#define SDMMC_STA_STBITERR              SDMMC_STA_STBITERR_Msk                 /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDMMC_STA_DBCKEND_Pos           (10U)                                  
+#define SDMMC_STA_DBCKEND_Msk           (0x1U << SDMMC_STA_DBCKEND_Pos)        /*!< 0x00000400 */
+#define SDMMC_STA_DBCKEND               SDMMC_STA_DBCKEND_Msk                  /*!<Data block sent/received (CRC check passed)   */
+#define SDMMC_STA_CMDACT_Pos            (11U)                                  
+#define SDMMC_STA_CMDACT_Msk            (0x1U << SDMMC_STA_CMDACT_Pos)         /*!< 0x00000800 */
+#define SDMMC_STA_CMDACT                SDMMC_STA_CMDACT_Msk                   /*!<Command transfer in progress                  */
+#define SDMMC_STA_TXACT_Pos             (12U)                                  
+#define SDMMC_STA_TXACT_Msk             (0x1U << SDMMC_STA_TXACT_Pos)          /*!< 0x00001000 */
+#define SDMMC_STA_TXACT                 SDMMC_STA_TXACT_Msk                    /*!<Data transmit in progress                     */
+#define SDMMC_STA_RXACT_Pos             (13U)                                  
+#define SDMMC_STA_RXACT_Msk             (0x1U << SDMMC_STA_RXACT_Pos)          /*!< 0x00002000 */
+#define SDMMC_STA_RXACT                 SDMMC_STA_RXACT_Msk                    /*!<Data receive in progress                      */
+#define SDMMC_STA_TXFIFOHE_Pos          (14U)                                  
+#define SDMMC_STA_TXFIFOHE_Msk          (0x1U << SDMMC_STA_TXFIFOHE_Pos)       /*!< 0x00004000 */
+#define SDMMC_STA_TXFIFOHE              SDMMC_STA_TXFIFOHE_Msk                 /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDMMC_STA_RXFIFOHF_Pos          (15U)                                  
+#define SDMMC_STA_RXFIFOHF_Msk          (0x1U << SDMMC_STA_RXFIFOHF_Pos)       /*!< 0x00008000 */
+#define SDMMC_STA_RXFIFOHF              SDMMC_STA_RXFIFOHF_Msk                 /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDMMC_STA_TXFIFOF_Pos           (16U)                                  
+#define SDMMC_STA_TXFIFOF_Msk           (0x1U << SDMMC_STA_TXFIFOF_Pos)        /*!< 0x00010000 */
+#define SDMMC_STA_TXFIFOF               SDMMC_STA_TXFIFOF_Msk                  /*!<Transmit FIFO full                            */
+#define SDMMC_STA_RXFIFOF_Pos           (17U)                                  
+#define SDMMC_STA_RXFIFOF_Msk           (0x1U << SDMMC_STA_RXFIFOF_Pos)        /*!< 0x00020000 */
+#define SDMMC_STA_RXFIFOF               SDMMC_STA_RXFIFOF_Msk                  /*!<Receive FIFO full                             */
+#define SDMMC_STA_TXFIFOE_Pos           (18U)                                  
+#define SDMMC_STA_TXFIFOE_Msk           (0x1U << SDMMC_STA_TXFIFOE_Pos)        /*!< 0x00040000 */
+#define SDMMC_STA_TXFIFOE               SDMMC_STA_TXFIFOE_Msk                  /*!<Transmit FIFO empty                           */
+#define SDMMC_STA_RXFIFOE_Pos           (19U)                                  
+#define SDMMC_STA_RXFIFOE_Msk           (0x1U << SDMMC_STA_RXFIFOE_Pos)        /*!< 0x00080000 */
+#define SDMMC_STA_RXFIFOE               SDMMC_STA_RXFIFOE_Msk                  /*!<Receive FIFO empty                            */
+#define SDMMC_STA_TXDAVL_Pos            (20U)                                  
+#define SDMMC_STA_TXDAVL_Msk            (0x1U << SDMMC_STA_TXDAVL_Pos)         /*!< 0x00100000 */
+#define SDMMC_STA_TXDAVL                SDMMC_STA_TXDAVL_Msk                   /*!<Data available in transmit FIFO               */
+#define SDMMC_STA_RXDAVL_Pos            (21U)                                  
+#define SDMMC_STA_RXDAVL_Msk            (0x1U << SDMMC_STA_RXDAVL_Pos)         /*!< 0x00200000 */
+#define SDMMC_STA_RXDAVL                SDMMC_STA_RXDAVL_Msk                   /*!<Data available in receive FIFO                */
+#define SDMMC_STA_SDIOIT_Pos            (22U)                                  
+#define SDMMC_STA_SDIOIT_Msk            (0x1U << SDMMC_STA_SDIOIT_Pos)         /*!< 0x00400000 */
+#define SDMMC_STA_SDIOIT                SDMMC_STA_SDIOIT_Msk                   /*!<SDIO interrupt received                       */
+
+/*******************  Bit definition for SDMMC_ICR register  *******************/
+#define SDMMC_ICR_CCRCFAILC_Pos         (0U)                                   
+#define SDMMC_ICR_CCRCFAILC_Msk         (0x1U << SDMMC_ICR_CCRCFAILC_Pos)      /*!< 0x00000001 */
+#define SDMMC_ICR_CCRCFAILC             SDMMC_ICR_CCRCFAILC_Msk                /*!<CCRCFAIL flag clear bit */
+#define SDMMC_ICR_DCRCFAILC_Pos         (1U)                                   
+#define SDMMC_ICR_DCRCFAILC_Msk         (0x1U << SDMMC_ICR_DCRCFAILC_Pos)      /*!< 0x00000002 */
+#define SDMMC_ICR_DCRCFAILC             SDMMC_ICR_DCRCFAILC_Msk                /*!<DCRCFAIL flag clear bit */
+#define SDMMC_ICR_CTIMEOUTC_Pos         (2U)                                   
+#define SDMMC_ICR_CTIMEOUTC_Msk         (0x1U << SDMMC_ICR_CTIMEOUTC_Pos)      /*!< 0x00000004 */
+#define SDMMC_ICR_CTIMEOUTC             SDMMC_ICR_CTIMEOUTC_Msk                /*!<CTIMEOUT flag clear bit */
+#define SDMMC_ICR_DTIMEOUTC_Pos         (3U)                                   
+#define SDMMC_ICR_DTIMEOUTC_Msk         (0x1U << SDMMC_ICR_DTIMEOUTC_Pos)      /*!< 0x00000008 */
+#define SDMMC_ICR_DTIMEOUTC             SDMMC_ICR_DTIMEOUTC_Msk                /*!<DTIMEOUT flag clear bit */
+#define SDMMC_ICR_TXUNDERRC_Pos         (4U)                                   
+#define SDMMC_ICR_TXUNDERRC_Msk         (0x1U << SDMMC_ICR_TXUNDERRC_Pos)      /*!< 0x00000010 */
+#define SDMMC_ICR_TXUNDERRC             SDMMC_ICR_TXUNDERRC_Msk                /*!<TXUNDERR flag clear bit */
+#define SDMMC_ICR_RXOVERRC_Pos          (5U)                                   
+#define SDMMC_ICR_RXOVERRC_Msk          (0x1U << SDMMC_ICR_RXOVERRC_Pos)       /*!< 0x00000020 */
+#define SDMMC_ICR_RXOVERRC              SDMMC_ICR_RXOVERRC_Msk                 /*!<RXOVERR flag clear bit  */
+#define SDMMC_ICR_CMDRENDC_Pos          (6U)                                   
+#define SDMMC_ICR_CMDRENDC_Msk          (0x1U << SDMMC_ICR_CMDRENDC_Pos)       /*!< 0x00000040 */
+#define SDMMC_ICR_CMDRENDC              SDMMC_ICR_CMDRENDC_Msk                 /*!<CMDREND flag clear bit  */
+#define SDMMC_ICR_CMDSENTC_Pos          (7U)                                   
+#define SDMMC_ICR_CMDSENTC_Msk          (0x1U << SDMMC_ICR_CMDSENTC_Pos)       /*!< 0x00000080 */
+#define SDMMC_ICR_CMDSENTC              SDMMC_ICR_CMDSENTC_Msk                 /*!<CMDSENT flag clear bit  */
+#define SDMMC_ICR_DATAENDC_Pos          (8U)                                   
+#define SDMMC_ICR_DATAENDC_Msk          (0x1U << SDMMC_ICR_DATAENDC_Pos)       /*!< 0x00000100 */
+#define SDMMC_ICR_DATAENDC              SDMMC_ICR_DATAENDC_Msk                 /*!<DATAEND flag clear bit  */
+#define SDMMC_ICR_STBITERRC_Pos         (9U)                                   
+#define SDMMC_ICR_STBITERRC_Msk         (0x1U << SDMMC_ICR_STBITERRC_Pos)      /*!< 0x00000200 */
+#define SDMMC_ICR_STBITERRC             SDMMC_ICR_STBITERRC_Msk                /*!<STBITERR flag clear bit */
+#define SDMMC_ICR_DBCKENDC_Pos          (10U)                                  
+#define SDMMC_ICR_DBCKENDC_Msk          (0x1U << SDMMC_ICR_DBCKENDC_Pos)       /*!< 0x00000400 */
+#define SDMMC_ICR_DBCKENDC              SDMMC_ICR_DBCKENDC_Msk                 /*!<DBCKEND flag clear bit  */
+#define SDMMC_ICR_SDIOITC_Pos           (22U)                                  
+#define SDMMC_ICR_SDIOITC_Msk           (0x1U << SDMMC_ICR_SDIOITC_Pos)        /*!< 0x00400000 */
+#define SDMMC_ICR_SDIOITC               SDMMC_ICR_SDIOITC_Msk                  /*!<SDIOIT flag clear bit   */
+
+/******************  Bit definition for SDMMC_MASK register  *******************/
+#define SDMMC_MASK_CCRCFAILIE_Pos       (0U)                                   
+#define SDMMC_MASK_CCRCFAILIE_Msk       (0x1U << SDMMC_MASK_CCRCFAILIE_Pos)    /*!< 0x00000001 */
+#define SDMMC_MASK_CCRCFAILIE           SDMMC_MASK_CCRCFAILIE_Msk              /*!<Command CRC Fail Interrupt Enable          */
+#define SDMMC_MASK_DCRCFAILIE_Pos       (1U)                                   
+#define SDMMC_MASK_DCRCFAILIE_Msk       (0x1U << SDMMC_MASK_DCRCFAILIE_Pos)    /*!< 0x00000002 */
+#define SDMMC_MASK_DCRCFAILIE           SDMMC_MASK_DCRCFAILIE_Msk              /*!<Data CRC Fail Interrupt Enable             */
+#define SDMMC_MASK_CTIMEOUTIE_Pos       (2U)                                   
+#define SDMMC_MASK_CTIMEOUTIE_Msk       (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos)    /*!< 0x00000004 */
+#define SDMMC_MASK_CTIMEOUTIE           SDMMC_MASK_CTIMEOUTIE_Msk              /*!<Command TimeOut Interrupt Enable           */
+#define SDMMC_MASK_DTIMEOUTIE_Pos       (3U)                                   
+#define SDMMC_MASK_DTIMEOUTIE_Msk       (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos)    /*!< 0x00000008 */
+#define SDMMC_MASK_DTIMEOUTIE           SDMMC_MASK_DTIMEOUTIE_Msk              /*!<Data TimeOut Interrupt Enable              */
+#define SDMMC_MASK_TXUNDERRIE_Pos       (4U)                                   
+#define SDMMC_MASK_TXUNDERRIE_Msk       (0x1U << SDMMC_MASK_TXUNDERRIE_Pos)    /*!< 0x00000010 */
+#define SDMMC_MASK_TXUNDERRIE           SDMMC_MASK_TXUNDERRIE_Msk              /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define SDMMC_MASK_RXOVERRIE_Pos        (5U)                                   
+#define SDMMC_MASK_RXOVERRIE_Msk        (0x1U << SDMMC_MASK_RXOVERRIE_Pos)     /*!< 0x00000020 */
+#define SDMMC_MASK_RXOVERRIE            SDMMC_MASK_RXOVERRIE_Msk               /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define SDMMC_MASK_CMDRENDIE_Pos        (6U)                                   
+#define SDMMC_MASK_CMDRENDIE_Msk        (0x1U << SDMMC_MASK_CMDRENDIE_Pos)     /*!< 0x00000040 */
+#define SDMMC_MASK_CMDRENDIE            SDMMC_MASK_CMDRENDIE_Msk               /*!<Command Response Received Interrupt Enable */
+#define SDMMC_MASK_CMDSENTIE_Pos        (7U)                                   
+#define SDMMC_MASK_CMDSENTIE_Msk        (0x1U << SDMMC_MASK_CMDSENTIE_Pos)     /*!< 0x00000080 */
+#define SDMMC_MASK_CMDSENTIE            SDMMC_MASK_CMDSENTIE_Msk               /*!<Command Sent Interrupt Enable              */
+#define SDMMC_MASK_DATAENDIE_Pos        (8U)                                   
+#define SDMMC_MASK_DATAENDIE_Msk        (0x1U << SDMMC_MASK_DATAENDIE_Pos)     /*!< 0x00000100 */
+#define SDMMC_MASK_DATAENDIE            SDMMC_MASK_DATAENDIE_Msk               /*!<Data End Interrupt Enable                  */
+#define SDMMC_MASK_DBCKENDIE_Pos        (10U)                                  
+#define SDMMC_MASK_DBCKENDIE_Msk        (0x1U << SDMMC_MASK_DBCKENDIE_Pos)     /*!< 0x00000400 */
+#define SDMMC_MASK_DBCKENDIE            SDMMC_MASK_DBCKENDIE_Msk               /*!<Data Block End Interrupt Enable            */
+#define SDMMC_MASK_CMDACTIE_Pos         (11U)                                  
+#define SDMMC_MASK_CMDACTIE_Msk         (0x1U << SDMMC_MASK_CMDACTIE_Pos)      /*!< 0x00000800 */
+#define SDMMC_MASK_CMDACTIE             SDMMC_MASK_CMDACTIE_Msk                /*!<CCommand Acting Interrupt Enable           */
+#define SDMMC_MASK_TXACTIE_Pos          (12U)                                  
+#define SDMMC_MASK_TXACTIE_Msk          (0x1U << SDMMC_MASK_TXACTIE_Pos)       /*!< 0x00001000 */
+#define SDMMC_MASK_TXACTIE              SDMMC_MASK_TXACTIE_Msk                 /*!<Data Transmit Acting Interrupt Enable      */
+#define SDMMC_MASK_RXACTIE_Pos          (13U)                                  
+#define SDMMC_MASK_RXACTIE_Msk          (0x1U << SDMMC_MASK_RXACTIE_Pos)       /*!< 0x00002000 */
+#define SDMMC_MASK_RXACTIE              SDMMC_MASK_RXACTIE_Msk                 /*!<Data receive acting interrupt enabled      */
+#define SDMMC_MASK_TXFIFOHEIE_Pos       (14U)                                  
+#define SDMMC_MASK_TXFIFOHEIE_Msk       (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos)    /*!< 0x00004000 */
+#define SDMMC_MASK_TXFIFOHEIE           SDMMC_MASK_TXFIFOHEIE_Msk              /*!<Tx FIFO Half Empty interrupt Enable        */
+#define SDMMC_MASK_RXFIFOHFIE_Pos       (15U)                                  
+#define SDMMC_MASK_RXFIFOHFIE_Msk       (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos)    /*!< 0x00008000 */
+#define SDMMC_MASK_RXFIFOHFIE           SDMMC_MASK_RXFIFOHFIE_Msk              /*!<Rx FIFO Half Full interrupt Enable         */
+#define SDMMC_MASK_TXFIFOFIE_Pos        (16U)                                  
+#define SDMMC_MASK_TXFIFOFIE_Msk        (0x1U << SDMMC_MASK_TXFIFOFIE_Pos)     /*!< 0x00010000 */
+#define SDMMC_MASK_TXFIFOFIE            SDMMC_MASK_TXFIFOFIE_Msk               /*!<Tx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_RXFIFOFIE_Pos        (17U)                                  
+#define SDMMC_MASK_RXFIFOFIE_Msk        (0x1U << SDMMC_MASK_RXFIFOFIE_Pos)     /*!< 0x00020000 */
+#define SDMMC_MASK_RXFIFOFIE            SDMMC_MASK_RXFIFOFIE_Msk               /*!<Rx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_TXFIFOEIE_Pos        (18U)                                  
+#define SDMMC_MASK_TXFIFOEIE_Msk        (0x1U << SDMMC_MASK_TXFIFOEIE_Pos)     /*!< 0x00040000 */
+#define SDMMC_MASK_TXFIFOEIE            SDMMC_MASK_TXFIFOEIE_Msk               /*!<Tx FIFO Empty interrupt Enable             */
+#define SDMMC_MASK_RXFIFOEIE_Pos        (19U)                                  
+#define SDMMC_MASK_RXFIFOEIE_Msk        (0x1U << SDMMC_MASK_RXFIFOEIE_Pos)     /*!< 0x00080000 */
+#define SDMMC_MASK_RXFIFOEIE            SDMMC_MASK_RXFIFOEIE_Msk               /*!<Rx FIFO Empty interrupt Enable             */
+#define SDMMC_MASK_TXDAVLIE_Pos         (20U)                                  
+#define SDMMC_MASK_TXDAVLIE_Msk         (0x1U << SDMMC_MASK_TXDAVLIE_Pos)      /*!< 0x00100000 */
+#define SDMMC_MASK_TXDAVLIE             SDMMC_MASK_TXDAVLIE_Msk                /*!<Data available in Tx FIFO interrupt Enable */
+#define SDMMC_MASK_RXDAVLIE_Pos         (21U)                                  
+#define SDMMC_MASK_RXDAVLIE_Msk         (0x1U << SDMMC_MASK_RXDAVLIE_Pos)      /*!< 0x00200000 */
+#define SDMMC_MASK_RXDAVLIE             SDMMC_MASK_RXDAVLIE_Msk                /*!<Data available in Rx FIFO interrupt Enable */
+#define SDMMC_MASK_SDIOITIE_Pos         (22U)                                  
+#define SDMMC_MASK_SDIOITIE_Msk         (0x1U << SDMMC_MASK_SDIOITIE_Pos)      /*!< 0x00400000 */
+#define SDMMC_MASK_SDIOITIE             SDMMC_MASK_SDIOITIE_Msk                /*!<SDIO Mode Interrupt Received interrupt Enable */
+
+/*****************  Bit definition for SDMMC_FIFOCNT register  *****************/
+#define SDMMC_FIFOCNT_FIFOCOUNT_Pos     (0U)                                   
+#define SDMMC_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDMMC_FIFOCNT_FIFOCOUNT         SDMMC_FIFOCNT_FIFOCOUNT_Msk            /*!<Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDMMC_FIFO register  *******************/
+#define SDMMC_FIFO_FIFODATA_Pos         (0U)                                   
+#define SDMMC_FIFO_FIFODATA_Msk         (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_FIFO_FIFODATA             SDMMC_FIFO_FIFODATA_Msk                /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_CPHA_Pos         (0U)                                          
+#define SPI_CR1_CPHA_Msk         (0x1U << SPI_CR1_CPHA_Pos)                    /*!< 0x00000001 */
+#define SPI_CR1_CPHA             SPI_CR1_CPHA_Msk                              /*!<Clock Phase      */
+#define SPI_CR1_CPOL_Pos         (1U)                                          
+#define SPI_CR1_CPOL_Msk         (0x1U << SPI_CR1_CPOL_Pos)                    /*!< 0x00000002 */
+#define SPI_CR1_CPOL             SPI_CR1_CPOL_Msk                              /*!<Clock Polarity   */
+#define SPI_CR1_MSTR_Pos         (2U)                                          
+#define SPI_CR1_MSTR_Msk         (0x1U << SPI_CR1_MSTR_Pos)                    /*!< 0x00000004 */
+#define SPI_CR1_MSTR             SPI_CR1_MSTR_Msk                              /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos           (3U)                                          
+#define SPI_CR1_BR_Msk           (0x7U << SPI_CR1_BR_Pos)                      /*!< 0x00000038 */
+#define SPI_CR1_BR               SPI_CR1_BR_Msk                                /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0             (0x1U << SPI_CR1_BR_Pos)                      /*!< 0x00000008 */
+#define SPI_CR1_BR_1             (0x2U << SPI_CR1_BR_Pos)                      /*!< 0x00000010 */
+#define SPI_CR1_BR_2             (0x4U << SPI_CR1_BR_Pos)                      /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos          (6U)                                          
+#define SPI_CR1_SPE_Msk          (0x1U << SPI_CR1_SPE_Pos)                     /*!< 0x00000040 */
+#define SPI_CR1_SPE              SPI_CR1_SPE_Msk                               /*!<SPI Enable                          */
+#define SPI_CR1_LSBFIRST_Pos     (7U)                                          
+#define SPI_CR1_LSBFIRST_Msk     (0x1U << SPI_CR1_LSBFIRST_Pos)                /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST         SPI_CR1_LSBFIRST_Msk                          /*!<Frame Format                        */
+#define SPI_CR1_SSI_Pos          (8U)                                          
+#define SPI_CR1_SSI_Msk          (0x1U << SPI_CR1_SSI_Pos)                     /*!< 0x00000100 */
+#define SPI_CR1_SSI              SPI_CR1_SSI_Msk                               /*!<Internal slave select               */
+#define SPI_CR1_SSM_Pos          (9U)                                          
+#define SPI_CR1_SSM_Msk          (0x1U << SPI_CR1_SSM_Pos)                     /*!< 0x00000200 */
+#define SPI_CR1_SSM              SPI_CR1_SSM_Msk                               /*!<Software slave management           */
+#define SPI_CR1_RXONLY_Pos       (10U)                                         
+#define SPI_CR1_RXONLY_Msk       (0x1U << SPI_CR1_RXONLY_Pos)                  /*!< 0x00000400 */
+#define SPI_CR1_RXONLY           SPI_CR1_RXONLY_Msk                            /*!<Receive only                        */
+#define SPI_CR1_CRCL_Pos         (11U)                                         
+#define SPI_CR1_CRCL_Msk         (0x1U << SPI_CR1_CRCL_Pos)                    /*!< 0x00000800 */
+#define SPI_CR1_CRCL             SPI_CR1_CRCL_Msk                              /*!< CRC Length */
+#define SPI_CR1_CRCNEXT_Pos      (12U)                                         
+#define SPI_CR1_CRCNEXT_Msk      (0x1U << SPI_CR1_CRCNEXT_Pos)                 /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT          SPI_CR1_CRCNEXT_Msk                           /*!<Transmit CRC next                   */
+#define SPI_CR1_CRCEN_Pos        (13U)                                         
+#define SPI_CR1_CRCEN_Msk        (0x1U << SPI_CR1_CRCEN_Pos)                   /*!< 0x00002000 */
+#define SPI_CR1_CRCEN            SPI_CR1_CRCEN_Msk                             /*!<Hardware CRC calculation enable     */
+#define SPI_CR1_BIDIOE_Pos       (14U)                                         
+#define SPI_CR1_BIDIOE_Msk       (0x1U << SPI_CR1_BIDIOE_Pos)                  /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE           SPI_CR1_BIDIOE_Msk                            /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos     (15U)                                         
+#define SPI_CR1_BIDIMODE_Msk     (0x1U << SPI_CR1_BIDIMODE_Pos)                /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE         SPI_CR1_BIDIMODE_Msk                          /*!<Bidirectional data mode enable      */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_RXDMAEN_Pos      (0U)                                          
+#define SPI_CR2_RXDMAEN_Msk      (0x1U << SPI_CR2_RXDMAEN_Pos)                 /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN          SPI_CR2_RXDMAEN_Msk                           /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos      (1U)                                          
+#define SPI_CR2_TXDMAEN_Msk      (0x1U << SPI_CR2_TXDMAEN_Pos)                 /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN          SPI_CR2_TXDMAEN_Msk                           /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos         (2U)                                          
+#define SPI_CR2_SSOE_Msk         (0x1U << SPI_CR2_SSOE_Pos)                    /*!< 0x00000004 */
+#define SPI_CR2_SSOE             SPI_CR2_SSOE_Msk                              /*!< SS Output Enable */
+#define SPI_CR2_NSSP_Pos         (3U)                                          
+#define SPI_CR2_NSSP_Msk         (0x1U << SPI_CR2_NSSP_Pos)                    /*!< 0x00000008 */
+#define SPI_CR2_NSSP             SPI_CR2_NSSP_Msk                              /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF_Pos          (4U)                                          
+#define SPI_CR2_FRF_Msk          (0x1U << SPI_CR2_FRF_Pos)                     /*!< 0x00000010 */
+#define SPI_CR2_FRF              SPI_CR2_FRF_Msk                               /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos        (5U)                                          
+#define SPI_CR2_ERRIE_Msk        (0x1U << SPI_CR2_ERRIE_Pos)                   /*!< 0x00000020 */
+#define SPI_CR2_ERRIE            SPI_CR2_ERRIE_Msk                             /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos       (6U)                                          
+#define SPI_CR2_RXNEIE_Msk       (0x1U << SPI_CR2_RXNEIE_Pos)                  /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE           SPI_CR2_RXNEIE_Msk                            /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos        (7U)                                          
+#define SPI_CR2_TXEIE_Msk        (0x1U << SPI_CR2_TXEIE_Pos)                   /*!< 0x00000080 */
+#define SPI_CR2_TXEIE            SPI_CR2_TXEIE_Msk                             /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS_Pos           (8U)                                          
+#define SPI_CR2_DS_Msk           (0xFU << SPI_CR2_DS_Pos)                      /*!< 0x00000F00 */
+#define SPI_CR2_DS               SPI_CR2_DS_Msk                                /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0             (0x1U << SPI_CR2_DS_Pos)                      /*!< 0x00000100 */
+#define SPI_CR2_DS_1             (0x2U << SPI_CR2_DS_Pos)                      /*!< 0x00000200 */
+#define SPI_CR2_DS_2             (0x4U << SPI_CR2_DS_Pos)                      /*!< 0x00000400 */
+#define SPI_CR2_DS_3             (0x8U << SPI_CR2_DS_Pos)                      /*!< 0x00000800 */
+#define SPI_CR2_FRXTH_Pos        (12U)                                         
+#define SPI_CR2_FRXTH_Msk        (0x1U << SPI_CR2_FRXTH_Pos)                   /*!< 0x00001000 */
+#define SPI_CR2_FRXTH            SPI_CR2_FRXTH_Msk                             /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX_Pos       (13U)                                         
+#define SPI_CR2_LDMARX_Msk       (0x1U << SPI_CR2_LDMARX_Pos)                  /*!< 0x00002000 */
+#define SPI_CR2_LDMARX           SPI_CR2_LDMARX_Msk                            /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX_Pos       (14U)                                         
+#define SPI_CR2_LDMATX_Msk       (0x1U << SPI_CR2_LDMATX_Pos)                  /*!< 0x00004000 */
+#define SPI_CR2_LDMATX           SPI_CR2_LDMATX_Msk                            /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define SPI_SR_RXNE_Pos          (0U)                                          
+#define SPI_SR_RXNE_Msk          (0x1U << SPI_SR_RXNE_Pos)                     /*!< 0x00000001 */
+#define SPI_SR_RXNE              SPI_SR_RXNE_Msk                               /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos           (1U)                                          
+#define SPI_SR_TXE_Msk           (0x1U << SPI_SR_TXE_Pos)                      /*!< 0x00000002 */
+#define SPI_SR_TXE               SPI_SR_TXE_Msk                                /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos        (2U)                                          
+#define SPI_SR_CHSIDE_Msk        (0x1U << SPI_SR_CHSIDE_Pos)                   /*!< 0x00000004 */
+#define SPI_SR_CHSIDE            SPI_SR_CHSIDE_Msk                             /*!< Channel side */
+#define SPI_SR_UDR_Pos           (3U)                                          
+#define SPI_SR_UDR_Msk           (0x1U << SPI_SR_UDR_Pos)                      /*!< 0x00000008 */
+#define SPI_SR_UDR               SPI_SR_UDR_Msk                                /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos        (4U)                                          
+#define SPI_SR_CRCERR_Msk        (0x1U << SPI_SR_CRCERR_Pos)                   /*!< 0x00000010 */
+#define SPI_SR_CRCERR            SPI_SR_CRCERR_Msk                             /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos          (5U)                                          
+#define SPI_SR_MODF_Msk          (0x1U << SPI_SR_MODF_Pos)                     /*!< 0x00000020 */
+#define SPI_SR_MODF              SPI_SR_MODF_Msk                               /*!< Mode fault */
+#define SPI_SR_OVR_Pos           (6U)                                          
+#define SPI_SR_OVR_Msk           (0x1U << SPI_SR_OVR_Pos)                      /*!< 0x00000040 */
+#define SPI_SR_OVR               SPI_SR_OVR_Msk                                /*!< Overrun flag */
+#define SPI_SR_BSY_Pos           (7U)                                          
+#define SPI_SR_BSY_Msk           (0x1U << SPI_SR_BSY_Pos)                      /*!< 0x00000080 */
+#define SPI_SR_BSY               SPI_SR_BSY_Msk                                /*!< Busy flag */
+#define SPI_SR_FRE_Pos           (8U)                                          
+#define SPI_SR_FRE_Msk           (0x1U << SPI_SR_FRE_Pos)                      /*!< 0x00000100 */
+#define SPI_SR_FRE               SPI_SR_FRE_Msk                                /*!< TI frame format error */
+#define SPI_SR_FRLVL_Pos         (9U)                                          
+#define SPI_SR_FRLVL_Msk         (0x3U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000600 */
+#define SPI_SR_FRLVL             SPI_SR_FRLVL_Msk                              /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0           (0x1U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000200 */
+#define SPI_SR_FRLVL_1           (0x2U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000400 */
+#define SPI_SR_FTLVL_Pos         (11U)                                         
+#define SPI_SR_FTLVL_Msk         (0x3U << SPI_SR_FTLVL_Pos)                    /*!< 0x00001800 */
+#define SPI_SR_FTLVL             SPI_SR_FTLVL_Msk                              /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0           (0x1U << SPI_SR_FTLVL_Pos)                    /*!< 0x00000800 */
+#define SPI_SR_FTLVL_1           (0x2U << SPI_SR_FTLVL_Pos)                    /*!< 0x00001000 */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define SPI_DR_DR_Pos            (0U)                                          
+#define SPI_DR_DR_Msk            (0xFFFFU << SPI_DR_DR_Pos)                    /*!< 0x0000FFFF */
+#define SPI_DR_DR                SPI_DR_DR_Msk                                 /*!<Data Register           */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define SPI_CRCPR_CRCPOLY_Pos    (0U)                                          
+#define SPI_CRCPR_CRCPOLY_Msk    (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos)            /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY        SPI_CRCPR_CRCPOLY_Msk                         /*!<CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define SPI_RXCRCR_RXCRC_Pos     (0U)                                          
+#define SPI_RXCRCR_RXCRC_Msk     (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)             /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC         SPI_RXCRCR_RXCRC_Msk                          /*!<Rx CRC Register         */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define SPI_TXCRCR_TXCRC_Pos     (0U)                                          
+#define SPI_TXCRCR_TXCRC_Msk     (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)             /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC         SPI_TXCRCR_TXCRC_Msk                          /*!<Tx CRC Register         */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    QUADSPI                                 */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for QUADSPI_CR register  *******************/
+#define QUADSPI_CR_EN_Pos              (0U)                                    
+#define QUADSPI_CR_EN_Msk              (0x1U << QUADSPI_CR_EN_Pos)             /*!< 0x00000001 */
+#define QUADSPI_CR_EN                  QUADSPI_CR_EN_Msk                       /*!< Enable */
+#define QUADSPI_CR_ABORT_Pos           (1U)                                    
+#define QUADSPI_CR_ABORT_Msk           (0x1U << QUADSPI_CR_ABORT_Pos)          /*!< 0x00000002 */
+#define QUADSPI_CR_ABORT               QUADSPI_CR_ABORT_Msk                    /*!< Abort request */
+#define QUADSPI_CR_DMAEN_Pos           (2U)                                    
+#define QUADSPI_CR_DMAEN_Msk           (0x1U << QUADSPI_CR_DMAEN_Pos)          /*!< 0x00000004 */
+#define QUADSPI_CR_DMAEN               QUADSPI_CR_DMAEN_Msk                    /*!< DMA Enable */
+#define QUADSPI_CR_TCEN_Pos            (3U)                                    
+#define QUADSPI_CR_TCEN_Msk            (0x1U << QUADSPI_CR_TCEN_Pos)           /*!< 0x00000008 */
+#define QUADSPI_CR_TCEN                QUADSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT_Pos          (4U)                                    
+#define QUADSPI_CR_SSHIFT_Msk          (0x1U << QUADSPI_CR_SSHIFT_Pos)         /*!< 0x00000010 */
+#define QUADSPI_CR_SSHIFT              QUADSPI_CR_SSHIFT_Msk                   /*!< Sample Shift */
+#define QUADSPI_CR_DFM_Pos             (6U)                                    
+#define QUADSPI_CR_DFM_Msk             (0x1U << QUADSPI_CR_DFM_Pos)            /*!< 0x00000040 */
+#define QUADSPI_CR_DFM                 QUADSPI_CR_DFM_Msk                      /*!< Dual-flash mode */
+#define QUADSPI_CR_FSEL_Pos            (7U)                                    
+#define QUADSPI_CR_FSEL_Msk            (0x1U << QUADSPI_CR_FSEL_Pos)           /*!< 0x00000080 */
+#define QUADSPI_CR_FSEL                QUADSPI_CR_FSEL_Msk                     /*!< Flash memory selection */
+#define QUADSPI_CR_FTHRES_Pos          (8U)                                    
+#define QUADSPI_CR_FTHRES_Msk          (0xFU << QUADSPI_CR_FTHRES_Pos)         /*!< 0x00000F00 */
+#define QUADSPI_CR_FTHRES              QUADSPI_CR_FTHRES_Msk                   /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_TEIE_Pos            (16U)                                   
+#define QUADSPI_CR_TEIE_Msk            (0x1U << QUADSPI_CR_TEIE_Pos)           /*!< 0x00010000 */
+#define QUADSPI_CR_TEIE                QUADSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE_Pos            (17U)                                   
+#define QUADSPI_CR_TCIE_Msk            (0x1U << QUADSPI_CR_TCIE_Pos)           /*!< 0x00020000 */
+#define QUADSPI_CR_TCIE                QUADSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE_Pos            (18U)                                   
+#define QUADSPI_CR_FTIE_Msk            (0x1U << QUADSPI_CR_FTIE_Pos)           /*!< 0x00040000 */
+#define QUADSPI_CR_FTIE                QUADSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE_Pos            (19U)                                   
+#define QUADSPI_CR_SMIE_Msk            (0x1U << QUADSPI_CR_SMIE_Pos)           /*!< 0x00080000 */
+#define QUADSPI_CR_SMIE                QUADSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE_Pos            (20U)                                   
+#define QUADSPI_CR_TOIE_Msk            (0x1U << QUADSPI_CR_TOIE_Pos)           /*!< 0x00100000 */
+#define QUADSPI_CR_TOIE                QUADSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS_Pos            (22U)                                   
+#define QUADSPI_CR_APMS_Msk            (0x1U << QUADSPI_CR_APMS_Pos)           /*!< 0x00400000 */
+#define QUADSPI_CR_APMS                QUADSPI_CR_APMS_Msk                     /*!< Automatic Polling Mode Stop */
+#define QUADSPI_CR_PMM_Pos             (23U)                                   
+#define QUADSPI_CR_PMM_Msk             (0x1U << QUADSPI_CR_PMM_Pos)            /*!< 0x00800000 */
+#define QUADSPI_CR_PMM                 QUADSPI_CR_PMM_Msk                      /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER_Pos       (24U)                                   
+#define QUADSPI_CR_PRESCALER_Msk       (0xFFU << QUADSPI_CR_PRESCALER_Pos)     /*!< 0xFF000000 */
+#define QUADSPI_CR_PRESCALER           QUADSPI_CR_PRESCALER_Msk                /*!< PRESCALER[7:0] Clock prescaler */
+
+/*****************  Bit definition for QUADSPI_DCR register  ******************/
+#define QUADSPI_DCR_CKMODE_Pos         (0U)                                    
+#define QUADSPI_DCR_CKMODE_Msk         (0x1U << QUADSPI_DCR_CKMODE_Pos)        /*!< 0x00000001 */
+#define QUADSPI_DCR_CKMODE             QUADSPI_DCR_CKMODE_Msk                  /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT_Pos           (8U)                                    
+#define QUADSPI_DCR_CSHT_Msk           (0x7U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000700 */
+#define QUADSPI_DCR_CSHT               QUADSPI_DCR_CSHT_Msk                    /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0             (0x1U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000100 */
+#define QUADSPI_DCR_CSHT_1             (0x2U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000200 */
+#define QUADSPI_DCR_CSHT_2             (0x4U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000400 */
+#define QUADSPI_DCR_FSIZE_Pos          (16U)                                   
+#define QUADSPI_DCR_FSIZE_Msk          (0x1FU << QUADSPI_DCR_FSIZE_Pos)        /*!< 0x001F0000 */
+#define QUADSPI_DCR_FSIZE              QUADSPI_DCR_FSIZE_Msk                   /*!< FSIZE[4:0]: Flash Size */
+
+/******************  Bit definition for QUADSPI_SR register  *******************/
+#define QUADSPI_SR_TEF_Pos             (0U)                                    
+#define QUADSPI_SR_TEF_Msk             (0x1U << QUADSPI_SR_TEF_Pos)            /*!< 0x00000001 */
+#define QUADSPI_SR_TEF                 QUADSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF_Pos             (1U)                                    
+#define QUADSPI_SR_TCF_Msk             (0x1U << QUADSPI_SR_TCF_Pos)            /*!< 0x00000002 */
+#define QUADSPI_SR_TCF                 QUADSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF_Pos             (2U)                                    
+#define QUADSPI_SR_FTF_Msk             (0x1U << QUADSPI_SR_FTF_Pos)            /*!< 0x00000004 */
+#define QUADSPI_SR_FTF                 QUADSPI_SR_FTF_Msk                      /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF_Pos             (3U)                                    
+#define QUADSPI_SR_SMF_Msk             (0x1U << QUADSPI_SR_SMF_Pos)            /*!< 0x00000008 */
+#define QUADSPI_SR_SMF                 QUADSPI_SR_SMF_Msk                      /*!< Status Match Flag */
+#define QUADSPI_SR_TOF_Pos             (4U)                                    
+#define QUADSPI_SR_TOF_Msk             (0x1U << QUADSPI_SR_TOF_Pos)            /*!< 0x00000010 */
+#define QUADSPI_SR_TOF                 QUADSPI_SR_TOF_Msk                      /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY_Pos            (5U)                                    
+#define QUADSPI_SR_BUSY_Msk            (0x1U << QUADSPI_SR_BUSY_Pos)           /*!< 0x00000020 */
+#define QUADSPI_SR_BUSY                QUADSPI_SR_BUSY_Msk                     /*!< Busy */
+#define QUADSPI_SR_FLEVEL_Pos          (8U)                                    
+#define QUADSPI_SR_FLEVEL_Msk          (0x1FU << QUADSPI_SR_FLEVEL_Pos)        /*!< 0x00001F00 */
+#define QUADSPI_SR_FLEVEL              QUADSPI_SR_FLEVEL_Msk                   /*!< FIFO Threshlod Flag */
+
+/******************  Bit definition for QUADSPI_FCR register  ******************/
+#define QUADSPI_FCR_CTEF_Pos           (0U)                                    
+#define QUADSPI_FCR_CTEF_Msk           (0x1U << QUADSPI_FCR_CTEF_Pos)          /*!< 0x00000001 */
+#define QUADSPI_FCR_CTEF               QUADSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF_Pos           (1U)                                    
+#define QUADSPI_FCR_CTCF_Msk           (0x1U << QUADSPI_FCR_CTCF_Pos)          /*!< 0x00000002 */
+#define QUADSPI_FCR_CTCF               QUADSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF_Pos           (3U)                                    
+#define QUADSPI_FCR_CSMF_Msk           (0x1U << QUADSPI_FCR_CSMF_Pos)          /*!< 0x00000008 */
+#define QUADSPI_FCR_CSMF               QUADSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF_Pos           (4U)                                    
+#define QUADSPI_FCR_CTOF_Msk           (0x1U << QUADSPI_FCR_CTOF_Pos)          /*!< 0x00000010 */
+#define QUADSPI_FCR_CTOF               QUADSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */
+
+/******************  Bit definition for QUADSPI_DLR register  ******************/
+#define QUADSPI_DLR_DL_Pos             (0U)                                    
+#define QUADSPI_DLR_DL_Msk             (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos)     /*!< 0xFFFFFFFF */
+#define QUADSPI_DLR_DL                 QUADSPI_DLR_DL_Msk                      /*!< DL[31:0]: Data Length */
+
+/******************  Bit definition for QUADSPI_CCR register  ******************/
+#define QUADSPI_CCR_INSTRUCTION_Pos    (0U)                                    
+#define QUADSPI_CCR_INSTRUCTION_Msk    (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos)  /*!< 0x000000FF */
+#define QUADSPI_CCR_INSTRUCTION        QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_IMODE_Pos          (8U)                                    
+#define QUADSPI_CCR_IMODE_Msk          (0x3U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000300 */
+#define QUADSPI_CCR_IMODE              QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0            (0x1U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000100 */
+#define QUADSPI_CCR_IMODE_1            (0x2U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000200 */
+#define QUADSPI_CCR_ADMODE_Pos         (10U)                                   
+#define QUADSPI_CCR_ADMODE_Msk         (0x3U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000C00 */
+#define QUADSPI_CCR_ADMODE             QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0           (0x1U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000400 */
+#define QUADSPI_CCR_ADMODE_1           (0x2U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000800 */
+#define QUADSPI_CCR_ADSIZE_Pos         (12U)                                   
+#define QUADSPI_CCR_ADSIZE_Msk         (0x3U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00003000 */
+#define QUADSPI_CCR_ADSIZE             QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0           (0x1U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00001000 */
+#define QUADSPI_CCR_ADSIZE_1           (0x2U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00002000 */
+#define QUADSPI_CCR_ABMODE_Pos         (14U)                                   
+#define QUADSPI_CCR_ABMODE_Msk         (0x3U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x0000C000 */
+#define QUADSPI_CCR_ABMODE             QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0           (0x1U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x00004000 */
+#define QUADSPI_CCR_ABMODE_1           (0x2U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x00008000 */
+#define QUADSPI_CCR_ABSIZE_Pos         (16U)                                   
+#define QUADSPI_CCR_ABSIZE_Msk         (0x3U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00030000 */
+#define QUADSPI_CCR_ABSIZE             QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0           (0x1U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00010000 */
+#define QUADSPI_CCR_ABSIZE_1           (0x2U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00020000 */
+#define QUADSPI_CCR_DCYC_Pos           (18U)                                   
+#define QUADSPI_CCR_DCYC_Msk           (0x1FU << QUADSPI_CCR_DCYC_Pos)         /*!< 0x007C0000 */
+#define QUADSPI_CCR_DCYC               QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DMODE_Pos          (24U)                                   
+#define QUADSPI_CCR_DMODE_Msk          (0x3U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x03000000 */
+#define QUADSPI_CCR_DMODE              QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0            (0x1U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x01000000 */
+#define QUADSPI_CCR_DMODE_1            (0x2U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x02000000 */
+#define QUADSPI_CCR_FMODE_Pos          (26U)                                   
+#define QUADSPI_CCR_FMODE_Msk          (0x3U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x0C000000 */
+#define QUADSPI_CCR_FMODE              QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0            (0x1U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x04000000 */
+#define QUADSPI_CCR_FMODE_1            (0x2U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x08000000 */
+#define QUADSPI_CCR_SIOO_Pos           (28U)                                   
+#define QUADSPI_CCR_SIOO_Msk           (0x1U << QUADSPI_CCR_SIOO_Pos)          /*!< 0x10000000 */
+#define QUADSPI_CCR_SIOO               QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC_Pos           (30U)                                   
+#define QUADSPI_CCR_DHHC_Msk           (0x1U << QUADSPI_CCR_DHHC_Pos)          /*!< 0x40000000 */
+#define QUADSPI_CCR_DHHC               QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold */
+#define QUADSPI_CCR_DDRM_Pos           (31U)                                   
+#define QUADSPI_CCR_DDRM_Msk           (0x1U << QUADSPI_CCR_DDRM_Pos)          /*!< 0x80000000 */
+#define QUADSPI_CCR_DDRM               QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */
+
+/******************  Bit definition for QUADSPI_AR register  *******************/
+#define QUADSPI_AR_ADDRESS_Pos         (0U)                                    
+#define QUADSPI_AR_ADDRESS_Msk         (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_AR_ADDRESS             QUADSPI_AR_ADDRESS_Msk                  /*!< ADDRESS[31:0]: Address */
+
+/******************  Bit definition for QUADSPI_ABR register  ******************/
+#define QUADSPI_ABR_ALTERNATE_Pos      (0U)                                    
+#define QUADSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_ABR_ALTERNATE          QUADSPI_ABR_ALTERNATE_Msk               /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/******************  Bit definition for QUADSPI_DR register  *******************/
+#define QUADSPI_DR_DATA_Pos            (0U)                                    
+#define QUADSPI_DR_DATA_Msk            (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos)    /*!< 0xFFFFFFFF */
+#define QUADSPI_DR_DATA                QUADSPI_DR_DATA_Msk                     /*!< DATA[31:0]: Data */
+
+/******************  Bit definition for QUADSPI_PSMKR register  ****************/
+#define QUADSPI_PSMKR_MASK_Pos         (0U)                                    
+#define QUADSPI_PSMKR_MASK_Msk         (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMKR_MASK             QUADSPI_PSMKR_MASK_Msk                  /*!< MASK[31:0]: Status Mask */
+
+/******************  Bit definition for QUADSPI_PSMAR register  ****************/
+#define QUADSPI_PSMAR_MATCH_Pos        (0U)                                    
+#define QUADSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMAR_MATCH            QUADSPI_PSMAR_MATCH_Msk                 /*!< MATCH[31:0]: Status Match */
+
+/******************  Bit definition for QUADSPI_PIR register  *****************/
+#define QUADSPI_PIR_INTERVAL_Pos       (0U)                                    
+#define QUADSPI_PIR_INTERVAL_Msk       (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos)   /*!< 0x0000FFFF */
+#define QUADSPI_PIR_INTERVAL           QUADSPI_PIR_INTERVAL_Msk                /*!< INTERVAL[15:0]: Polling Interval */
+
+/******************  Bit definition for QUADSPI_LPTR register  *****************/
+#define QUADSPI_LPTR_TIMEOUT_Pos       (0U)                                    
+#define QUADSPI_LPTR_TIMEOUT_Msk       (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos)   /*!< 0x0000FFFF */
+#define QUADSPI_LPTR_TIMEOUT           QUADSPI_LPTR_TIMEOUT_Msk                /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_MEMRMP register  ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)                                   
+#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000007 */
+#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
+#define SYSCFG_MEMRMP_MEM_MODE_2        (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000004 */
+
+#define SYSCFG_MEMRMP_FB_MODE_Pos       (8U)                                   
+#define SYSCFG_MEMRMP_FB_MODE_Msk       (0x1U << SYSCFG_MEMRMP_FB_MODE_Pos)    /*!< 0x00000100 */
+#define SYSCFG_MEMRMP_FB_MODE           SYSCFG_MEMRMP_FB_MODE_Msk              /*!< Flash Bank mode selection */
+
+/******************  Bit definition for SYSCFG_CFGR1 register  ******************/
+#define SYSCFG_CFGR1_FWDIS_Pos          (0U)                                   
+#define SYSCFG_CFGR1_FWDIS_Msk          (0x1U << SYSCFG_CFGR1_FWDIS_Pos)       /*!< 0x00000001 */
+#define SYSCFG_CFGR1_FWDIS              SYSCFG_CFGR1_FWDIS_Msk                 /*!< FIREWALL access enable*/
+#define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)                                   
+#define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos)     /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk               /*!< I/O analog switch voltage booster enable */
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)                                  
+#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
+#define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk           /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)                                  
+#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
+#define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk           /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos    (18U)                                  
+#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
+#define SYSCFG_CFGR1_I2C_PB8_FMP        SYSCFG_CFGR1_I2C_PB8_FMP_Msk           /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos    (19U)                                  
+#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
+#define SYSCFG_CFGR1_I2C_PB9_FMP        SYSCFG_CFGR1_I2C_PB9_FMP_Msk           /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP_Pos       (20U)                                  
+#define SYSCFG_CFGR1_I2C1_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos)    /*!< 0x00100000 */
+#define SYSCFG_CFGR1_I2C1_FMP           SYSCFG_CFGR1_I2C1_FMP_Msk              /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR1_I2C2_FMP_Pos       (21U)                                  
+#define SYSCFG_CFGR1_I2C2_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos)    /*!< 0x00200000 */
+#define SYSCFG_CFGR1_I2C2_FMP           SYSCFG_CFGR1_I2C2_FMP_Msk              /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR1_I2C3_FMP_Pos       (22U)                                  
+#define SYSCFG_CFGR1_I2C3_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos)    /*!< 0x00400000 */
+#define SYSCFG_CFGR1_I2C3_FMP           SYSCFG_CFGR1_I2C3_FMP_Msk              /*!< I2C3 Fast mode plus */
+#define SYSCFG_CFGR1_I2C4_FMP_Pos       (23U)                                  
+#define SYSCFG_CFGR1_I2C4_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C4_FMP_Pos)    /*!< 0x00800000 */
+#define SYSCFG_CFGR1_I2C4_FMP           SYSCFG_CFGR1_I2C4_FMP_Msk              /*!< I2C4 Fast mode plus */
+#define SYSCFG_CFGR1_FPU_IE_0           (0x04000000U)                          /*!<  Invalid operation Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_1           (0x08000000U)                          /*!<  Divide-by-zero Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_2           (0x10000000U)                          /*!<  Underflow Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_3           (0x20000000U)                          /*!<  Overflow Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_4           (0x40000000U)                          /*!<  Input denormal Interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE_5           (0x80000000U)                          /*!<  Inexact Interrupt enable (interrupt disabled at reset) */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)                                   
+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFU << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)                                   
+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFU << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)                                   
+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFU << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)                                  
+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFU << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
+
+/**
+  * @brief   EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA             (0x00000000U)                      /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB             (0x00000001U)                      /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC             (0x00000002U)                      /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD             (0x00000003U)                      /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE             (0x00000004U)                      /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF             (0x00000005U)                      /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG             (0x00000006U)                      /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH             (0x00000007U)                      /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI             (0x00000008U)                      /*!<PI[0] pin */
+
+/**
+  * @brief   EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA             (0x00000000U)                      /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB             (0x00000010U)                      /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC             (0x00000020U)                      /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD             (0x00000030U)                      /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE             (0x00000040U)                      /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF             (0x00000050U)                      /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG             (0x00000060U)                      /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH             (0x00000070U)                      /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI             (0x00000080U)                      /*!<PI[1] pin */
+
+/**
+  * @brief   EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA             (0x00000000U)                      /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB             (0x00000100U)                      /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC             (0x00000200U)                      /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD             (0x00000300U)                      /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE             (0x00000400U)                      /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF             (0x00000500U)                      /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG             (0x00000600U)                      /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH             (0x00000700U)                      /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI             (0x00000800U)                      /*!<PI[2] pin */
+
+/**
+  * @brief   EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA             (0x00000000U)                      /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB             (0x00001000U)                      /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC             (0x00002000U)                      /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD             (0x00003000U)                      /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE             (0x00004000U)                      /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF             (0x00005000U)                      /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG             (0x00006000U)                      /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH             (0x00007000U)                      /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI             (0x00008000U)                      /*!<PI[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)                                   
+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFU << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)                                   
+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFU << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)                                   
+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFU << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)                                  
+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFU << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
+/**
+  * @brief   EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA             (0x00000000U)                      /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB             (0x00000001U)                      /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC             (0x00000002U)                      /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD             (0x00000003U)                      /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE             (0x00000004U)                      /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF             (0x00000005U)                      /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG             (0x00000006U)                      /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH             (0x00000007U)                      /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI             (0x00000008U)                      /*!<PI[4] pin */
+
+/**
+  * @brief   EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA             (0x00000000U)                      /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB             (0x00000010U)                      /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC             (0x00000020U)                      /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD             (0x00000030U)                      /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE             (0x00000040U)                      /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF             (0x00000050U)                      /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG             (0x00000060U)                      /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH             (0x00000070U)                      /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI             (0x00000080U)                      /*!<PI[5] pin */
+
+/**
+  * @brief   EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA             (0x00000000U)                      /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB             (0x00000100U)                      /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC             (0x00000200U)                      /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD             (0x00000300U)                      /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE             (0x00000400U)                      /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF             (0x00000500U)                      /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG             (0x00000600U)                      /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH             (0x00000700U)                      /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI             (0x00000800U)                      /*!<PI[6] pin */
+
+/**
+  * @brief   EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA             (0x00000000U)                      /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB             (0x00001000U)                      /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC             (0x00002000U)                      /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD             (0x00003000U)                      /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE             (0x00004000U)                      /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF             (0x00005000U)                      /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG             (0x00006000U)                      /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH             (0x00007000U)                      /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI             (0x00008000U)                      /*!<PI[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)                                   
+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFU << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)                                   
+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFU << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)                                   
+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFU << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)                                  
+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFU << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
+
+/**
+  * @brief   EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA             (0x00000000U)                      /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB             (0x00000001U)                      /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC             (0x00000002U)                      /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD             (0x00000003U)                      /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE             (0x00000004U)                      /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF             (0x00000005U)                      /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG             (0x00000006U)                      /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH             (0x00000007U)                      /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI             (0x00000008U)                      /*!<PI[8] pin */
+
+/**
+  * @brief   EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA             (0x00000000U)                      /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB             (0x00000010U)                      /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC             (0x00000020U)                      /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD             (0x00000030U)                      /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE             (0x00000040U)                      /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF             (0x00000050U)                      /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG             (0x00000060U)                      /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH             (0x00000070U)                      /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI             (0x00000080U)                      /*!<PI[9] pin */
+
+/**
+  * @brief   EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA            (0x00000000U)                      /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB            (0x00000100U)                      /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC            (0x00000200U)                      /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD            (0x00000300U)                      /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE            (0x00000400U)                      /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF            (0x00000500U)                      /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG            (0x00000600U)                      /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH            (0x00000700U)                      /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI            (0x00000800U)                      /*!<PI[10] pin */
+
+/**
+  * @brief   EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA            (0x00000000U)                      /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB            (0x00001000U)                      /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC            (0x00002000U)                      /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD            (0x00003000U)                      /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE            (0x00004000U)                      /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF            (0x00005000U)                      /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG            (0x00006000U)                      /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH            (0x00007000U)                      /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI            (0x00008000U)                      /*!<PI[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)                                   
+#define SYSCFG_EXTICR4_EXTI12_Msk       (0x7U << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x00000007 */
+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)                                   
+#define SYSCFG_EXTICR4_EXTI13_Msk       (0x7U << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x00000070 */
+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)                                   
+#define SYSCFG_EXTICR4_EXTI14_Msk       (0x7U << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000700 */
+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)                                  
+#define SYSCFG_EXTICR4_EXTI15_Msk       (0x7U << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x00007000 */
+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
+
+/**
+  * @brief   EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA            (0x00000000U)                      /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB            (0x00000001U)                      /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC            (0x00000002U)                      /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD            (0x00000003U)                      /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE            (0x00000004U)                      /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF            (0x00000005U)                      /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG            (0x00000006U)                      /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH            (0x00000007U)                      /*!<PH[12] pin */
+
+/**
+  * @brief   EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA            (0x00000000U)                      /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB            (0x00000010U)                      /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC            (0x00000020U)                      /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD            (0x00000030U)                      /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE            (0x00000040U)                      /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF            (0x00000050U)                      /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG            (0x00000060U)                      /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH            (0x00000070U)                      /*!<PH[13] pin */
+
+/**
+  * @brief   EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA            (0x00000000U)                      /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB            (0x00000100U)                      /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC            (0x00000200U)                      /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD            (0x00000300U)                      /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE            (0x00000400U)                      /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF            (0x00000500U)                      /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG            (0x00000600U)                      /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH            (0x00000700U)                      /*!<PH[14] pin */
+
+/**
+  * @brief   EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA            (0x00000000U)                      /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB            (0x00001000U)                      /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC            (0x00002000U)                      /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD            (0x00003000U)                      /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE            (0x00004000U)                      /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF            (0x00005000U)                      /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG            (0x00006000U)                      /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH            (0x00007000U)                      /*!<PH[15] pin */
+
+/******************  Bit definition for SYSCFG_SCSR register  ****************/
+#define SYSCFG_SCSR_SRAM2ER_Pos         (0U)                                   
+#define SYSCFG_SCSR_SRAM2ER_Msk         (0x1U << SYSCFG_SCSR_SRAM2ER_Pos)      /*!< 0x00000001 */
+#define SYSCFG_SCSR_SRAM2ER             SYSCFG_SCSR_SRAM2ER_Msk                /*!< SRAM2 Erase Request */
+#define SYSCFG_SCSR_SRAM2BSY_Pos        (1U)                                   
+#define SYSCFG_SCSR_SRAM2BSY_Msk        (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos)     /*!< 0x00000002 */
+#define SYSCFG_SCSR_SRAM2BSY            SYSCFG_SCSR_SRAM2BSY_Msk               /*!< SRAM2 Erase Ongoing */
+
+/******************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_CLL_Pos            (0U)                                   
+#define SYSCFG_CFGR2_CLL_Msk            (0x1U << SYSCFG_CFGR2_CLL_Pos)         /*!< 0x00000001 */
+#define SYSCFG_CFGR2_CLL                SYSCFG_CFGR2_CLL_Msk                   /*!< Core Lockup Lock */
+#define SYSCFG_CFGR2_SPL_Pos            (1U)                                   
+#define SYSCFG_CFGR2_SPL_Msk            (0x1U << SYSCFG_CFGR2_SPL_Pos)         /*!< 0x00000002 */
+#define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                   /*!< SRAM Parity Lock*/
+#define SYSCFG_CFGR2_PVDL_Pos           (2U)                                   
+#define SYSCFG_CFGR2_PVDL_Msk           (0x1U << SYSCFG_CFGR2_PVDL_Pos)        /*!< 0x00000004 */
+#define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                  /*!<  PVD Lock */
+#define SYSCFG_CFGR2_ECCL_Pos           (3U)                                   
+#define SYSCFG_CFGR2_ECCL_Msk           (0x1U << SYSCFG_CFGR2_ECCL_Pos)        /*!< 0x00000008 */
+#define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                  /*!< ECC Lock*/
+#define SYSCFG_CFGR2_SPF_Pos            (8U)                                   
+#define SYSCFG_CFGR2_SPF_Msk            (0x1U << SYSCFG_CFGR2_SPF_Pos)         /*!< 0x00000100 */
+#define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                   /*!< SRAM Parity Flag */
+
+/******************  Bit definition for SYSCFG_SWPR register  ****************/
+#define SYSCFG_SWPR_PAGE0_Pos           (0U)                                   
+#define SYSCFG_SWPR_PAGE0_Msk           (0x1U << SYSCFG_SWPR_PAGE0_Pos)        /*!< 0x00000001 */
+#define SYSCFG_SWPR_PAGE0               SYSCFG_SWPR_PAGE0_Msk                  /*!< SRAM2 Write protection page 0 */
+#define SYSCFG_SWPR_PAGE1_Pos           (1U)                                   
+#define SYSCFG_SWPR_PAGE1_Msk           (0x1U << SYSCFG_SWPR_PAGE1_Pos)        /*!< 0x00000002 */
+#define SYSCFG_SWPR_PAGE1               SYSCFG_SWPR_PAGE1_Msk                  /*!< SRAM2 Write protection page 1 */
+#define SYSCFG_SWPR_PAGE2_Pos           (2U)                                   
+#define SYSCFG_SWPR_PAGE2_Msk           (0x1U << SYSCFG_SWPR_PAGE2_Pos)        /*!< 0x00000004 */
+#define SYSCFG_SWPR_PAGE2               SYSCFG_SWPR_PAGE2_Msk                  /*!< SRAM2 Write protection page 2 */
+#define SYSCFG_SWPR_PAGE3_Pos           (3U)                                   
+#define SYSCFG_SWPR_PAGE3_Msk           (0x1U << SYSCFG_SWPR_PAGE3_Pos)        /*!< 0x00000008 */
+#define SYSCFG_SWPR_PAGE3               SYSCFG_SWPR_PAGE3_Msk                  /*!< SRAM2 Write protection page 3 */
+#define SYSCFG_SWPR_PAGE4_Pos           (4U)                                   
+#define SYSCFG_SWPR_PAGE4_Msk           (0x1U << SYSCFG_SWPR_PAGE4_Pos)        /*!< 0x00000010 */
+#define SYSCFG_SWPR_PAGE4               SYSCFG_SWPR_PAGE4_Msk                  /*!< SRAM2 Write protection page 4 */
+#define SYSCFG_SWPR_PAGE5_Pos           (5U)                                   
+#define SYSCFG_SWPR_PAGE5_Msk           (0x1U << SYSCFG_SWPR_PAGE5_Pos)        /*!< 0x00000020 */
+#define SYSCFG_SWPR_PAGE5               SYSCFG_SWPR_PAGE5_Msk                  /*!< SRAM2 Write protection page 5 */
+#define SYSCFG_SWPR_PAGE6_Pos           (6U)                                   
+#define SYSCFG_SWPR_PAGE6_Msk           (0x1U << SYSCFG_SWPR_PAGE6_Pos)        /*!< 0x00000040 */
+#define SYSCFG_SWPR_PAGE6               SYSCFG_SWPR_PAGE6_Msk                  /*!< SRAM2 Write protection page 6 */
+#define SYSCFG_SWPR_PAGE7_Pos           (7U)                                   
+#define SYSCFG_SWPR_PAGE7_Msk           (0x1U << SYSCFG_SWPR_PAGE7_Pos)        /*!< 0x00000080 */
+#define SYSCFG_SWPR_PAGE7               SYSCFG_SWPR_PAGE7_Msk                  /*!< SRAM2 Write protection page 7 */
+#define SYSCFG_SWPR_PAGE8_Pos           (8U)                                   
+#define SYSCFG_SWPR_PAGE8_Msk           (0x1U << SYSCFG_SWPR_PAGE8_Pos)        /*!< 0x00000100 */
+#define SYSCFG_SWPR_PAGE8               SYSCFG_SWPR_PAGE8_Msk                  /*!< SRAM2 Write protection page 8 */
+#define SYSCFG_SWPR_PAGE9_Pos           (9U)                                   
+#define SYSCFG_SWPR_PAGE9_Msk           (0x1U << SYSCFG_SWPR_PAGE9_Pos)        /*!< 0x00000200 */
+#define SYSCFG_SWPR_PAGE9               SYSCFG_SWPR_PAGE9_Msk                  /*!< SRAM2 Write protection page 9 */
+#define SYSCFG_SWPR_PAGE10_Pos          (10U)                                  
+#define SYSCFG_SWPR_PAGE10_Msk          (0x1U << SYSCFG_SWPR_PAGE10_Pos)       /*!< 0x00000400 */
+#define SYSCFG_SWPR_PAGE10              SYSCFG_SWPR_PAGE10_Msk                 /*!< SRAM2 Write protection page 10*/
+#define SYSCFG_SWPR_PAGE11_Pos          (11U)                                  
+#define SYSCFG_SWPR_PAGE11_Msk          (0x1U << SYSCFG_SWPR_PAGE11_Pos)       /*!< 0x00000800 */
+#define SYSCFG_SWPR_PAGE11              SYSCFG_SWPR_PAGE11_Msk                 /*!< SRAM2 Write protection page 11*/
+#define SYSCFG_SWPR_PAGE12_Pos          (12U)                                  
+#define SYSCFG_SWPR_PAGE12_Msk          (0x1U << SYSCFG_SWPR_PAGE12_Pos)       /*!< 0x00001000 */
+#define SYSCFG_SWPR_PAGE12              SYSCFG_SWPR_PAGE12_Msk                 /*!< SRAM2 Write protection page 12*/
+#define SYSCFG_SWPR_PAGE13_Pos          (13U)                                  
+#define SYSCFG_SWPR_PAGE13_Msk          (0x1U << SYSCFG_SWPR_PAGE13_Pos)       /*!< 0x00002000 */
+#define SYSCFG_SWPR_PAGE13              SYSCFG_SWPR_PAGE13_Msk                 /*!< SRAM2 Write protection page 13*/
+#define SYSCFG_SWPR_PAGE14_Pos          (14U)                                  
+#define SYSCFG_SWPR_PAGE14_Msk          (0x1U << SYSCFG_SWPR_PAGE14_Pos)       /*!< 0x00004000 */
+#define SYSCFG_SWPR_PAGE14              SYSCFG_SWPR_PAGE14_Msk                 /*!< SRAM2 Write protection page 14*/
+#define SYSCFG_SWPR_PAGE15_Pos          (15U)                                  
+#define SYSCFG_SWPR_PAGE15_Msk          (0x1U << SYSCFG_SWPR_PAGE15_Pos)       /*!< 0x00008000 */
+#define SYSCFG_SWPR_PAGE15              SYSCFG_SWPR_PAGE15_Msk                 /*!< SRAM2 Write protection page 15*/
+#define SYSCFG_SWPR_PAGE16_Pos          (16U)                                  
+#define SYSCFG_SWPR_PAGE16_Msk          (0x1U << SYSCFG_SWPR_PAGE16_Pos)       /*!< 0x00010000 */
+#define SYSCFG_SWPR_PAGE16              SYSCFG_SWPR_PAGE16_Msk                 /*!< SRAM2 Write protection page 16*/
+#define SYSCFG_SWPR_PAGE17_Pos          (17U)                                  
+#define SYSCFG_SWPR_PAGE17_Msk          (0x1U << SYSCFG_SWPR_PAGE17_Pos)       /*!< 0x00020000 */
+#define SYSCFG_SWPR_PAGE17              SYSCFG_SWPR_PAGE17_Msk                 /*!< SRAM2 Write protection page 17*/
+#define SYSCFG_SWPR_PAGE18_Pos          (18U)                                  
+#define SYSCFG_SWPR_PAGE18_Msk          (0x1U << SYSCFG_SWPR_PAGE18_Pos)       /*!< 0x00040000 */
+#define SYSCFG_SWPR_PAGE18              SYSCFG_SWPR_PAGE18_Msk                 /*!< SRAM2 Write protection page 18*/
+#define SYSCFG_SWPR_PAGE19_Pos          (19U)                                  
+#define SYSCFG_SWPR_PAGE19_Msk          (0x1U << SYSCFG_SWPR_PAGE19_Pos)       /*!< 0x00080000 */
+#define SYSCFG_SWPR_PAGE19              SYSCFG_SWPR_PAGE19_Msk                 /*!< SRAM2 Write protection page 19*/
+#define SYSCFG_SWPR_PAGE20_Pos          (20U)                                  
+#define SYSCFG_SWPR_PAGE20_Msk          (0x1U << SYSCFG_SWPR_PAGE20_Pos)       /*!< 0x00100000 */
+#define SYSCFG_SWPR_PAGE20              SYSCFG_SWPR_PAGE20_Msk                 /*!< SRAM2 Write protection page 20*/
+#define SYSCFG_SWPR_PAGE21_Pos          (21U)                                  
+#define SYSCFG_SWPR_PAGE21_Msk          (0x1U << SYSCFG_SWPR_PAGE21_Pos)       /*!< 0x00200000 */
+#define SYSCFG_SWPR_PAGE21              SYSCFG_SWPR_PAGE21_Msk                 /*!< SRAM2 Write protection page 21*/
+#define SYSCFG_SWPR_PAGE22_Pos          (22U)                                  
+#define SYSCFG_SWPR_PAGE22_Msk          (0x1U << SYSCFG_SWPR_PAGE22_Pos)       /*!< 0x00400000 */
+#define SYSCFG_SWPR_PAGE22              SYSCFG_SWPR_PAGE22_Msk                 /*!< SRAM2 Write protection page 22*/
+#define SYSCFG_SWPR_PAGE23_Pos          (23U)                                  
+#define SYSCFG_SWPR_PAGE23_Msk          (0x1U << SYSCFG_SWPR_PAGE23_Pos)       /*!< 0x00800000 */
+#define SYSCFG_SWPR_PAGE23              SYSCFG_SWPR_PAGE23_Msk                 /*!< SRAM2 Write protection page 23*/
+#define SYSCFG_SWPR_PAGE24_Pos          (24U)                                  
+#define SYSCFG_SWPR_PAGE24_Msk          (0x1U << SYSCFG_SWPR_PAGE24_Pos)       /*!< 0x01000000 */
+#define SYSCFG_SWPR_PAGE24              SYSCFG_SWPR_PAGE24_Msk                 /*!< SRAM2 Write protection page 24*/
+#define SYSCFG_SWPR_PAGE25_Pos          (25U)                                  
+#define SYSCFG_SWPR_PAGE25_Msk          (0x1U << SYSCFG_SWPR_PAGE25_Pos)       /*!< 0x02000000 */
+#define SYSCFG_SWPR_PAGE25              SYSCFG_SWPR_PAGE25_Msk                 /*!< SRAM2 Write protection page 25*/
+#define SYSCFG_SWPR_PAGE26_Pos          (26U)                                  
+#define SYSCFG_SWPR_PAGE26_Msk          (0x1U << SYSCFG_SWPR_PAGE26_Pos)       /*!< 0x04000000 */
+#define SYSCFG_SWPR_PAGE26              SYSCFG_SWPR_PAGE26_Msk                 /*!< SRAM2 Write protection page 26*/
+#define SYSCFG_SWPR_PAGE27_Pos          (27U)                                  
+#define SYSCFG_SWPR_PAGE27_Msk          (0x1U << SYSCFG_SWPR_PAGE27_Pos)       /*!< 0x08000000 */
+#define SYSCFG_SWPR_PAGE27              SYSCFG_SWPR_PAGE27_Msk                 /*!< SRAM2 Write protection page 27*/
+#define SYSCFG_SWPR_PAGE28_Pos          (28U)                                  
+#define SYSCFG_SWPR_PAGE28_Msk          (0x1U << SYSCFG_SWPR_PAGE28_Pos)       /*!< 0x10000000 */
+#define SYSCFG_SWPR_PAGE28              SYSCFG_SWPR_PAGE28_Msk                 /*!< SRAM2 Write protection page 28*/
+#define SYSCFG_SWPR_PAGE29_Pos          (29U)                                  
+#define SYSCFG_SWPR_PAGE29_Msk          (0x1U << SYSCFG_SWPR_PAGE29_Pos)       /*!< 0x20000000 */
+#define SYSCFG_SWPR_PAGE29              SYSCFG_SWPR_PAGE29_Msk                 /*!< SRAM2 Write protection page 29*/
+#define SYSCFG_SWPR_PAGE30_Pos          (30U)                                  
+#define SYSCFG_SWPR_PAGE30_Msk          (0x1U << SYSCFG_SWPR_PAGE30_Pos)       /*!< 0x40000000 */
+#define SYSCFG_SWPR_PAGE30              SYSCFG_SWPR_PAGE30_Msk                 /*!< SRAM2 Write protection page 30*/
+#define SYSCFG_SWPR_PAGE31_Pos          (31U)                                  
+#define SYSCFG_SWPR_PAGE31_Msk          (0x1U << SYSCFG_SWPR_PAGE31_Pos)       /*!< 0x80000000 */
+#define SYSCFG_SWPR_PAGE31              SYSCFG_SWPR_PAGE31_Msk                 /*!< SRAM2 Write protection page 31*/
+#define SYSCFG_SWPR2_PAGE32_Pos         (0U)                                   
+#define SYSCFG_SWPR2_PAGE32_Msk         (0x1U << SYSCFG_SWPR2_PAGE32_Pos)      /*!< 0x00000001 */
+#define SYSCFG_SWPR2_PAGE32             SYSCFG_SWPR2_PAGE32_Msk                /*!< SRAM2 Write protection page 32*/
+#define SYSCFG_SWPR2_PAGE33_Pos         (1U)                                   
+#define SYSCFG_SWPR2_PAGE33_Msk         (0x1U << SYSCFG_SWPR2_PAGE33_Pos)      /*!< 0x00000002 */
+#define SYSCFG_SWPR2_PAGE33             SYSCFG_SWPR2_PAGE33_Msk                /*!< SRAM2 Write protection page 33*/
+#define SYSCFG_SWPR2_PAGE34_Pos         (2U)                                   
+#define SYSCFG_SWPR2_PAGE34_Msk         (0x1U << SYSCFG_SWPR2_PAGE34_Pos)      /*!< 0x00000004 */
+#define SYSCFG_SWPR2_PAGE34             SYSCFG_SWPR2_PAGE34_Msk                /*!< SRAM2 Write protection page 34*/
+#define SYSCFG_SWPR2_PAGE35_Pos         (3U)                                   
+#define SYSCFG_SWPR2_PAGE35_Msk         (0x1U << SYSCFG_SWPR2_PAGE35_Pos)      /*!< 0x00000008 */
+#define SYSCFG_SWPR2_PAGE35             SYSCFG_SWPR2_PAGE35_Msk                /*!< SRAM2 Write protection page 35*/
+#define SYSCFG_SWPR2_PAGE36_Pos         (4U)                                   
+#define SYSCFG_SWPR2_PAGE36_Msk         (0x1U << SYSCFG_SWPR2_PAGE36_Pos)      /*!< 0x00000010 */
+#define SYSCFG_SWPR2_PAGE36             SYSCFG_SWPR2_PAGE36_Msk                /*!< SRAM2 Write protection page 36*/
+#define SYSCFG_SWPR2_PAGE37_Pos         (5U)                                   
+#define SYSCFG_SWPR2_PAGE37_Msk         (0x1U << SYSCFG_SWPR2_PAGE37_Pos)      /*!< 0x00000020 */
+#define SYSCFG_SWPR2_PAGE37             SYSCFG_SWPR2_PAGE37_Msk                /*!< SRAM2 Write protection page 37*/
+#define SYSCFG_SWPR2_PAGE38_Pos         (6U)                                   
+#define SYSCFG_SWPR2_PAGE38_Msk         (0x1U << SYSCFG_SWPR2_PAGE38_Pos)      /*!< 0x00000040 */
+#define SYSCFG_SWPR2_PAGE38             SYSCFG_SWPR2_PAGE38_Msk                /*!< SRAM2 Write protection page 38*/
+#define SYSCFG_SWPR2_PAGE39_Pos         (7U)                                   
+#define SYSCFG_SWPR2_PAGE39_Msk         (0x1U << SYSCFG_SWPR2_PAGE39_Pos)      /*!< 0x00000080 */
+#define SYSCFG_SWPR2_PAGE39             SYSCFG_SWPR2_PAGE39_Msk                /*!< SRAM2 Write protection page 39*/
+#define SYSCFG_SWPR2_PAGE40_Pos         (8U)                                   
+#define SYSCFG_SWPR2_PAGE40_Msk         (0x1U << SYSCFG_SWPR2_PAGE40_Pos)      /*!< 0x00000100 */
+#define SYSCFG_SWPR2_PAGE40             SYSCFG_SWPR2_PAGE40_Msk                /*!< SRAM2 Write protection page 40*/
+#define SYSCFG_SWPR2_PAGE41_Pos         (9U)                                   
+#define SYSCFG_SWPR2_PAGE41_Msk         (0x1U << SYSCFG_SWPR2_PAGE41_Pos)      /*!< 0x00000200 */
+#define SYSCFG_SWPR2_PAGE41             SYSCFG_SWPR2_PAGE41_Msk                /*!< SRAM2 Write protection page 41*/
+#define SYSCFG_SWPR2_PAGE42_Pos         (10U)                                  
+#define SYSCFG_SWPR2_PAGE42_Msk         (0x1U << SYSCFG_SWPR2_PAGE42_Pos)      /*!< 0x00000400 */
+#define SYSCFG_SWPR2_PAGE42             SYSCFG_SWPR2_PAGE42_Msk                /*!< SRAM2 Write protection page 42*/
+#define SYSCFG_SWPR2_PAGE43_Pos         (11U)                                  
+#define SYSCFG_SWPR2_PAGE43_Msk         (0x1U << SYSCFG_SWPR2_PAGE43_Pos)      /*!< 0x00000800 */
+#define SYSCFG_SWPR2_PAGE43             SYSCFG_SWPR2_PAGE43_Msk                /*!< SRAM2 Write protection page 43*/
+#define SYSCFG_SWPR2_PAGE44_Pos         (12U)                                  
+#define SYSCFG_SWPR2_PAGE44_Msk         (0x1U << SYSCFG_SWPR2_PAGE44_Pos)      /*!< 0x00001000 */
+#define SYSCFG_SWPR2_PAGE44             SYSCFG_SWPR2_PAGE44_Msk                /*!< SRAM2 Write protection page 44*/
+#define SYSCFG_SWPR2_PAGE45_Pos         (13U)                                  
+#define SYSCFG_SWPR2_PAGE45_Msk         (0x1U << SYSCFG_SWPR2_PAGE45_Pos)      /*!< 0x00002000 */
+#define SYSCFG_SWPR2_PAGE45             SYSCFG_SWPR2_PAGE45_Msk                /*!< SRAM2 Write protection page 45*/
+#define SYSCFG_SWPR2_PAGE46_Pos         (14U)                                  
+#define SYSCFG_SWPR2_PAGE46_Msk         (0x1U << SYSCFG_SWPR2_PAGE46_Pos)      /*!< 0x00004000 */
+#define SYSCFG_SWPR2_PAGE46             SYSCFG_SWPR2_PAGE46_Msk                /*!< SRAM2 Write protection page 46*/
+#define SYSCFG_SWPR2_PAGE47_Pos         (15U)                                  
+#define SYSCFG_SWPR2_PAGE47_Msk         (0x1U << SYSCFG_SWPR2_PAGE47_Pos)      /*!< 0x00008000 */
+#define SYSCFG_SWPR2_PAGE47             SYSCFG_SWPR2_PAGE47_Msk                /*!< SRAM2 Write protection page 47*/
+#define SYSCFG_SWPR2_PAGE48_Pos         (16U)                                  
+#define SYSCFG_SWPR2_PAGE48_Msk         (0x1U << SYSCFG_SWPR2_PAGE48_Pos)      /*!< 0x00010000 */
+#define SYSCFG_SWPR2_PAGE48             SYSCFG_SWPR2_PAGE48_Msk                /*!< SRAM2 Write protection page 48*/
+#define SYSCFG_SWPR2_PAGE49_Pos         (17U)                                  
+#define SYSCFG_SWPR2_PAGE49_Msk         (0x1U << SYSCFG_SWPR2_PAGE49_Pos)      /*!< 0x00020000 */
+#define SYSCFG_SWPR2_PAGE49             SYSCFG_SWPR2_PAGE49_Msk                /*!< SRAM2 Write protection page 49*/
+#define SYSCFG_SWPR2_PAGE50_Pos         (18U)                                  
+#define SYSCFG_SWPR2_PAGE50_Msk         (0x1U << SYSCFG_SWPR2_PAGE50_Pos)      /*!< 0x00040000 */
+#define SYSCFG_SWPR2_PAGE50             SYSCFG_SWPR2_PAGE50_Msk                /*!< SRAM2 Write protection page 50*/
+#define SYSCFG_SWPR2_PAGE51_Pos         (19U)                                  
+#define SYSCFG_SWPR2_PAGE51_Msk         (0x1U << SYSCFG_SWPR2_PAGE51_Pos)      /*!< 0x00080000 */
+#define SYSCFG_SWPR2_PAGE51             SYSCFG_SWPR2_PAGE51_Msk                /*!< SRAM2 Write protection page 51*/
+#define SYSCFG_SWPR2_PAGE52_Pos         (20U)                                  
+#define SYSCFG_SWPR2_PAGE52_Msk         (0x1U << SYSCFG_SWPR2_PAGE52_Pos)      /*!< 0x00100000 */
+#define SYSCFG_SWPR2_PAGE52             SYSCFG_SWPR2_PAGE52_Msk                /*!< SRAM2 Write protection page 52*/
+#define SYSCFG_SWPR2_PAGE53_Pos         (21U)                                  
+#define SYSCFG_SWPR2_PAGE53_Msk         (0x1U << SYSCFG_SWPR2_PAGE53_Pos)      /*!< 0x00200000 */
+#define SYSCFG_SWPR2_PAGE53             SYSCFG_SWPR2_PAGE53_Msk                /*!< SRAM2 Write protection page 53*/
+#define SYSCFG_SWPR2_PAGE54_Pos         (22U)                                  
+#define SYSCFG_SWPR2_PAGE54_Msk         (0x1U << SYSCFG_SWPR2_PAGE54_Pos)      /*!< 0x00400000 */
+#define SYSCFG_SWPR2_PAGE54             SYSCFG_SWPR2_PAGE54_Msk                /*!< SRAM2 Write protection page 54*/
+#define SYSCFG_SWPR2_PAGE55_Pos         (23U)                                  
+#define SYSCFG_SWPR2_PAGE55_Msk         (0x1U << SYSCFG_SWPR2_PAGE55_Pos)      /*!< 0x00800000 */
+#define SYSCFG_SWPR2_PAGE55             SYSCFG_SWPR2_PAGE55_Msk                /*!< SRAM2 Write protection page 55*/
+#define SYSCFG_SWPR2_PAGE56_Pos         (24U)                                  
+#define SYSCFG_SWPR2_PAGE56_Msk         (0x1U << SYSCFG_SWPR2_PAGE56_Pos)      /*!< 0x01000000 */
+#define SYSCFG_SWPR2_PAGE56             SYSCFG_SWPR2_PAGE56_Msk                /*!< SRAM2 Write protection page 56*/
+#define SYSCFG_SWPR2_PAGE57_Pos         (25U)                                  
+#define SYSCFG_SWPR2_PAGE57_Msk         (0x1U << SYSCFG_SWPR2_PAGE57_Pos)      /*!< 0x02000000 */
+#define SYSCFG_SWPR2_PAGE57             SYSCFG_SWPR2_PAGE57_Msk                /*!< SRAM2 Write protection page 57*/
+#define SYSCFG_SWPR2_PAGE58_Pos         (26U)                                  
+#define SYSCFG_SWPR2_PAGE58_Msk         (0x1U << SYSCFG_SWPR2_PAGE58_Pos)      /*!< 0x04000000 */
+#define SYSCFG_SWPR2_PAGE58             SYSCFG_SWPR2_PAGE58_Msk                /*!< SRAM2 Write protection page 58*/
+#define SYSCFG_SWPR2_PAGE59_Pos         (27U)                                  
+#define SYSCFG_SWPR2_PAGE59_Msk         (0x1U << SYSCFG_SWPR2_PAGE59_Pos)      /*!< 0x08000000 */
+#define SYSCFG_SWPR2_PAGE59             SYSCFG_SWPR2_PAGE59_Msk                /*!< SRAM2 Write protection page 59*/
+#define SYSCFG_SWPR2_PAGE60_Pos         (28U)                                  
+#define SYSCFG_SWPR2_PAGE60_Msk         (0x1U << SYSCFG_SWPR2_PAGE60_Pos)      /*!< 0x10000000 */
+#define SYSCFG_SWPR2_PAGE60             SYSCFG_SWPR2_PAGE60_Msk                /*!< SRAM2 Write protection page 60*/
+#define SYSCFG_SWPR2_PAGE61_Pos         (29U)                                  
+#define SYSCFG_SWPR2_PAGE61_Msk         (0x1U << SYSCFG_SWPR2_PAGE61_Pos)      /*!< 0x20000000 */
+#define SYSCFG_SWPR2_PAGE61             SYSCFG_SWPR2_PAGE61_Msk                /*!< SRAM2 Write protection page 61*/
+#define SYSCFG_SWPR2_PAGE62_Pos         (30U)                                  
+#define SYSCFG_SWPR2_PAGE62_Msk         (0x1U << SYSCFG_SWPR2_PAGE62_Pos)      /*!< 0x40000000 */
+#define SYSCFG_SWPR2_PAGE62             SYSCFG_SWPR2_PAGE62_Msk                /*!< SRAM2 Write protection page 62*/
+#define SYSCFG_SWPR2_PAGE63_Pos         (31U)                                  
+#define SYSCFG_SWPR2_PAGE63_Msk         (0x1U << SYSCFG_SWPR2_PAGE63_Pos)      /*!< 0x80000000 */
+#define SYSCFG_SWPR2_PAGE63             SYSCFG_SWPR2_PAGE63_Msk                /*!< SRAM2 Write protection page 63*/
+
+/******************  Bit definition for SYSCFG_SKR register  ****************/
+#define SYSCFG_SKR_KEY_Pos              (0U)                                   
+#define SYSCFG_SKR_KEY_Msk              (0xFFU << SYSCFG_SKR_KEY_Pos)          /*!< 0x000000FF */
+#define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                     /*!<  SRAM2 write protection key for software erase  */
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)                                         
+#define TIM_CR1_CEN_Msk           (0x1U << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos          (1U)                                         
+#define TIM_CR1_UDIS_Msk          (0x1U << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
+#define TIM_CR1_URS_Pos           (2U)                                         
+#define TIM_CR1_URS_Msk           (0x1U << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)                                         
+#define TIM_CR1_OPM_Msk           (0x1U << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos           (4U)                                         
+#define TIM_CR1_DIR_Msk           (0x1U << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
+
+#define TIM_CR1_CMS_Pos           (5U)                                         
+#define TIM_CR1_CMS_Msk           (0x3U << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos          (7U)                                         
+#define TIM_CR1_ARPE_Msk          (0x1U << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos           (8U)                                         
+#define TIM_CR1_CKD_Msk           (0x3U << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
+#define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
+
+#define TIM_CR1_UIFREMAP_Pos      (11U)                                        
+#define TIM_CR1_UIFREMAP_Msk      (0x1U << TIM_CR1_UIFREMAP_Pos)               /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)                                         
+#define TIM_CR2_CCPC_Msk          (0x1U << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos          (2U)                                         
+#define TIM_CR2_CCUS_Msk          (0x1U << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)                                         
+#define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos           (4U)                                         
+#define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
+#define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos          (7U)                                         
+#define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)                                         
+#define TIM_CR2_OIS1_Msk          (0x1U << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos         (9U)                                         
+#define TIM_CR2_OIS1N_Msk         (0x1U << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)                                        
+#define TIM_CR2_OIS2_Msk          (0x1U << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos         (11U)                                        
+#define TIM_CR2_OIS2N_Msk         (0x1U << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)                                        
+#define TIM_CR2_OIS3_Msk          (0x1U << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos         (13U)                                        
+#define TIM_CR2_OIS3N_Msk         (0x1U << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)                                        
+#define TIM_CR2_OIS4_Msk          (0x1U << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5_Pos          (16U)                                        
+#define TIM_CR2_OIS5_Msk          (0x1U << TIM_CR2_OIS5_Pos)                   /*!< 0x00010000 */
+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
+#define TIM_CR2_OIS6_Pos          (18U)                                        
+#define TIM_CR2_OIS6_Msk          (0x1U << TIM_CR2_OIS6_Pos)                   /*!< 0x00040000 */
+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
+
+#define TIM_CR2_MMS2_Pos          (20U)                                        
+#define TIM_CR2_MMS2_Msk          (0xFU << TIM_CR2_MMS2_Pos)                   /*!< 0x00F00000 */
+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0            (0x1U << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1            (0x2U << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2            (0x4U << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3            (0x8U << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)                                         
+#define TIM_SMCR_SMS_Msk          (0x10007U << TIM_SMCR_SMS_Pos)               /*!< 0x00010007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0            (0x00001U << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1            (0x00002U << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2            (0x00004U << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3            (0x10000U << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */
+
+#define TIM_SMCR_OCCS_Pos         (3U)                                         
+#define TIM_SMCR_OCCS_Msk         (0x1U << TIM_SMCR_OCCS_Pos)                  /*!< 0x00000008 */
+#define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos           (4U)                                         
+#define TIM_SMCR_TS_Msk           (0x7U << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0             (0x1U << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
+#define TIM_SMCR_TS_1             (0x2U << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
+#define TIM_SMCR_TS_2             (0x4U << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos          (7U)                                         
+#define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos          (8U)                                         
+#define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos         (12U)                                        
+#define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos          (14U)                                        
+#define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos          (15U)                                        
+#define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)                                         
+#define TIM_DIER_UIE_Msk          (0x1U << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)                                         
+#define TIM_DIER_CC1IE_Msk        (0x1U << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos        (2U)                                         
+#define TIM_DIER_CC2IE_Msk        (0x1U << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos        (3U)                                         
+#define TIM_DIER_CC3IE_Msk        (0x1U << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos        (4U)                                         
+#define TIM_DIER_CC4IE_Msk        (0x1U << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos        (5U)                                         
+#define TIM_DIER_COMIE_Msk        (0x1U << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos          (6U)                                         
+#define TIM_DIER_TIE_Msk          (0x1U << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos          (7U)                                         
+#define TIM_DIER_BIE_Msk          (0x1U << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos          (8U)                                         
+#define TIM_DIER_UDE_Msk          (0x1U << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos        (9U)                                         
+#define TIM_DIER_CC1DE_Msk        (0x1U << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)                                        
+#define TIM_DIER_CC2DE_Msk        (0x1U << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)                                        
+#define TIM_DIER_CC3DE_Msk        (0x1U << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)                                        
+#define TIM_DIER_CC4DE_Msk        (0x1U << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)                                        
+#define TIM_DIER_COMDE_Msk        (0x1U << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos          (14U)                                        
+#define TIM_DIER_TDE_Msk          (0x1U << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)                                         
+#define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos          (1U)                                         
+#define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos          (2U)                                         
+#define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos          (3U)                                         
+#define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos          (4U)                                         
+#define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos          (5U)                                         
+#define TIM_SR_COMIF_Msk          (0x1U << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos            (6U)                                         
+#define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos            (7U)                                         
+#define TIM_SR_BIF_Msk            (0x1U << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos           (8U)                                         
+#define TIM_SR_B2IF_Msk           (0x1U << TIM_SR_B2IF_Pos)                    /*!< 0x00000100 */
+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos          (9U)                                         
+#define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)                                        
+#define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)                                        
+#define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)                                        
+#define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_SBIF_Pos           (13U)                                        
+#define TIM_SR_SBIF_Msk           (0x1U << TIM_SR_SBIF_Pos)                    /*!< 0x00002000 */
+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
+#define TIM_SR_CC5IF_Pos          (16U)                                        
+#define TIM_SR_CC5IF_Msk          (0x1U << TIM_SR_CC5IF_Pos)                   /*!< 0x00010000 */
+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos          (17U)                                        
+#define TIM_SR_CC6IF_Msk          (0x1U << TIM_SR_CC6IF_Pos)                   /*!< 0x00020000 */
+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
+
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)                                         
+#define TIM_EGR_UG_Msk            (0x1U << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos          (1U)                                         
+#define TIM_EGR_CC1G_Msk          (0x1U << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos          (2U)                                         
+#define TIM_EGR_CC2G_Msk          (0x1U << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos          (3U)                                         
+#define TIM_EGR_CC3G_Msk          (0x1U << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos          (4U)                                         
+#define TIM_EGR_CC4G_Msk          (0x1U << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos          (5U)                                         
+#define TIM_EGR_COMG_Msk          (0x1U << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)                                         
+#define TIM_EGR_TG_Msk            (0x1U << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos            (7U)                                         
+#define TIM_EGR_BG_Msk            (0x1U << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
+#define TIM_EGR_B2G_Pos           (8U)                                         
+#define TIM_EGR_B2G_Msk           (0x1U << TIM_EGR_B2G_Pos)                    /*!< 0x00000100 */
+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
+
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)                                         
+#define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos       (2U)                                         
+#define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos       (3U)                                         
+#define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos        (4U)                                         
+#define TIM_CCMR1_OC1M_Msk        (0x1007U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0          (0x0001U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1          (0x0002U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2          (0x0004U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3          (0x1000U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR1_OC1CE_Pos       (7U)                                         
+#define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos        (8U)                                         
+#define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos       (10U)                                        
+#define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos       (11U)                                        
+#define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos        (12U)                                        
+#define TIM_CCMR1_OC2M_Msk        (0x1007U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0          (0x0001U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1          (0x0002U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2          (0x0004U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3          (0x1000U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR1_OC2CE_Pos       (15U)                                        
+#define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR1_IC1PSC_Pos      (2U)                                         
+#define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos        (4U)                                         
+#define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos      (10U)                                        
+#define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos        (12U)                                        
+#define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)                                         
+#define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos       (2U)                                         
+#define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos       (3U)                                         
+#define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos        (4U)                                         
+#define TIM_CCMR2_OC3M_Msk        (0x1007U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x0001U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1          (0x0002U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2          (0x0004U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3          (0x1000U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR2_OC3CE_Pos       (7U)                                         
+#define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos        (8U)                                         
+#define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos       (10U)                                        
+#define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos       (11U)                                        
+#define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos        (12U)                                        
+#define TIM_CCMR2_OC4M_Msk        (0x1007U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x0001U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1          (0x0002U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2          (0x0004U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3          (0x1000U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR2_OC4CE_Pos       (15U)                                        
+#define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+#define TIM_CCMR2_IC3PSC_Pos      (2U)                                         
+#define TIM_CCMR2_IC3PSC_Msk      (0x3U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos        (4U)                                         
+#define TIM_CCMR2_IC3F_Msk        (0xFU << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos      (10U)                                        
+#define TIM_CCMR2_IC4PSC_Msk      (0x3U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos        (12U)                                        
+#define TIM_CCMR2_IC4F_Msk        (0xFU << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define TIM_CCMR3_OC5FE_Pos       (2U)                                         
+#define TIM_CCMR3_OC5FE_Msk       (0x1U << TIM_CCMR3_OC5FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos       (3U)                                         
+#define TIM_CCMR3_OC5PE_Msk       (0x1U << TIM_CCMR3_OC5PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M_Pos        (4U)                                         
+#define TIM_CCMR3_OC5M_Msk        (0x1007U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0          (0x0001U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1          (0x0002U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2          (0x0004U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3          (0x1000U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR3_OC5CE_Pos       (7U)                                         
+#define TIM_CCMR3_OC5CE_Msk       (0x1U << TIM_CCMR3_OC5CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE_Pos       (10U)                                        
+#define TIM_CCMR3_OC6FE_Msk       (0x1U << TIM_CCMR3_OC6FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos       (11U)                                        
+#define TIM_CCMR3_OC6PE_Msk       (0x1U << TIM_CCMR3_OC6PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
+
+#define TIM_CCMR3_OC6M_Pos        (12U)                                        
+#define TIM_CCMR3_OC6M_Msk        (0x1007U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMR3_OC6M_0          (0x0001U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1          (0x0002U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2          (0x0004U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3          (0x1000U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR3_OC6CE_Pos       (15U)                                        
+#define TIM_CCMR3_OC6CE_Msk       (0x1U << TIM_CCMR3_OC6CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)                                         
+#define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos         (1U)                                         
+#define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos        (2U)                                         
+#define TIM_CCER_CC1NE_Msk        (0x1U << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos        (3U)                                         
+#define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)                                         
+#define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos         (5U)                                         
+#define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos        (6U)                                         
+#define TIM_CCER_CC2NE_Msk        (0x1U << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos        (7U)                                         
+#define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)                                         
+#define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos         (9U)                                         
+#define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos        (10U)                                        
+#define TIM_CCER_CC3NE_Msk        (0x1U << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos        (11U)                                        
+#define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)                                        
+#define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos         (13U)                                        
+#define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos        (15U)                                        
+#define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos         (16U)                                        
+#define TIM_CCER_CC5E_Msk         (0x1U << TIM_CCER_CC5E_Pos)                  /*!< 0x00010000 */
+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos         (17U)                                        
+#define TIM_CCER_CC5P_Msk         (0x1U << TIM_CCER_CC5P_Pos)                  /*!< 0x00020000 */
+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos         (20U)                                        
+#define TIM_CCER_CC6E_Msk         (0x1U << TIM_CCER_CC6E_Pos)                  /*!< 0x00100000 */
+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos         (21U)                                        
+#define TIM_CCER_CC6P_Msk         (0x1U << TIM_CCER_CC6P_Pos)                  /*!< 0x00200000 */
+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)                                         
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFU << TIM_CNT_CNT_Pos)             /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos        (31U)                                        
+#define TIM_CNT_UIFCPY_Msk        (0x1U << TIM_CNT_UIFCPY_Pos)                 /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)                                         
+#define TIM_PSC_PSC_Msk           (0xFFFFU << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)                                         
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFU << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)                                         
+#define TIM_RCR_REP_Msk           (0xFFFFU << TIM_RCR_REP_Pos)                 /*!< 0x0000FFFF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)                                         
+#define TIM_CCR1_CCR1_Msk         (0xFFFFU << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)                                         
+#define TIM_CCR2_CCR2_Msk         (0xFFFFU << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)                                         
+#define TIM_CCR3_CCR3_Msk         (0xFFFFU << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)                                         
+#define TIM_CCR4_CCR4_Msk         (0xFFFFU << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define TIM_CCR5_CCR5_Pos         (0U)                                         
+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos)           /*!< 0xFFFFFFFF */
+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos        (29U)                                        
+#define TIM_CCR5_GC5C1_Msk        (0x1U << TIM_CCR5_GC5C1_Pos)                 /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos        (30U)                                        
+#define TIM_CCR5_GC5C2_Msk        (0x1U << TIM_CCR5_GC5C2_Pos)                 /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos        (31U)                                        
+#define TIM_CCR5_GC5C3_Msk        (0x1U << TIM_CCR5_GC5C3_Pos)                 /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define TIM_CCR6_CCR6_Pos         (0U)                                         
+#define TIM_CCR6_CCR6_Msk         (0xFFFFU << TIM_CCR6_CCR6_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)                                         
+#define TIM_BDTR_DTG_Msk          (0xFFU << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos         (8U)                                         
+#define TIM_BDTR_LOCK_Msk         (0x3U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos         (10U)                                        
+#define TIM_BDTR_OSSI_Msk         (0x1U << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)                                        
+#define TIM_BDTR_OSSR_Msk         (0x1U << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)                                        
+#define TIM_BDTR_BKE_Msk          (0x1U << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
+#define TIM_BDTR_BKP_Pos          (13U)                                        
+#define TIM_BDTR_BKP_Msk          (0x1U << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
+#define TIM_BDTR_AOE_Pos          (14U)                                        
+#define TIM_BDTR_AOE_Msk          (0x1U << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)                                        
+#define TIM_BDTR_MOE_Msk          (0x1U << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+
+#define TIM_BDTR_BKF_Pos          (16U)                                        
+#define TIM_BDTR_BKF_Msk          (0xFU << TIM_BDTR_BKF_Pos)                   /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
+#define TIM_BDTR_BK2F_Pos         (20U)                                        
+#define TIM_BDTR_BK2F_Msk         (0xFU << TIM_BDTR_BK2F_Pos)                  /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
+
+#define TIM_BDTR_BK2E_Pos         (24U)                                        
+#define TIM_BDTR_BK2E_Msk         (0x1U << TIM_BDTR_BK2E_Pos)                  /*!< 0x01000000 */
+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
+#define TIM_BDTR_BK2P_Pos         (25U)                                        
+#define TIM_BDTR_BK2P_Msk         (0x1U << TIM_BDTR_BK2P_Pos)                  /*!< 0x02000000 */
+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)                                         
+#define TIM_DCR_DBA_Msk           (0x1FU << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
+#define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
+#define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
+#define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
+#define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos           (8U)                                         
+#define TIM_DCR_DBL_Msk           (0x1FU << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
+#define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
+#define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
+#define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
+#define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)                                         
+#define TIM_DMAR_DMAB_Msk         (0xFFFFU << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM1_OR1 register  *******************/
+#define TIM1_OR1_ETR_ADC1_RMP_Pos      (0U)                                    
+#define TIM1_OR1_ETR_ADC1_RMP_Msk      (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000003 */
+#define TIM1_OR1_ETR_ADC1_RMP          TIM1_OR1_ETR_ADC1_RMP_Msk               /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
+#define TIM1_OR1_ETR_ADC1_RMP_0        (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000001 */
+#define TIM1_OR1_ETR_ADC1_RMP_1        (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000002 */
+
+#define TIM1_OR1_ETR_ADC3_RMP_Pos      (2U)                                    
+#define TIM1_OR1_ETR_ADC3_RMP_Msk      (0x3U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x0000000C */
+#define TIM1_OR1_ETR_ADC3_RMP          TIM1_OR1_ETR_ADC3_RMP_Msk               /*!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) */
+#define TIM1_OR1_ETR_ADC3_RMP_0        (0x1U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000004 */
+#define TIM1_OR1_ETR_ADC3_RMP_1        (0x2U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000008 */
+
+#define TIM1_OR1_TI1_RMP_Pos           (4U)                                    
+#define TIM1_OR1_TI1_RMP_Msk           (0x1U << TIM1_OR1_TI1_RMP_Pos)          /*!< 0x00000010 */
+#define TIM1_OR1_TI1_RMP               TIM1_OR1_TI1_RMP_Msk                    /*!<TIM1 Input Capture 1 remap */
+
+/*******************  Bit definition for TIM1_OR2 register  *******************/
+#define TIM1_OR2_BKINE_Pos             (0U)                                    
+#define TIM1_OR2_BKINE_Msk             (0x1U << TIM1_OR2_BKINE_Pos)            /*!< 0x00000001 */
+#define TIM1_OR2_BKINE                 TIM1_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */
+#define TIM1_OR2_BKCMP1E_Pos           (1U)                                    
+#define TIM1_OR2_BKCMP1E_Msk           (0x1U << TIM1_OR2_BKCMP1E_Pos)          /*!< 0x00000002 */
+#define TIM1_OR2_BKCMP1E               TIM1_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
+#define TIM1_OR2_BKCMP2E_Pos           (2U)                                    
+#define TIM1_OR2_BKCMP2E_Msk           (0x1U << TIM1_OR2_BKCMP2E_Pos)          /*!< 0x00000004 */
+#define TIM1_OR2_BKCMP2E               TIM1_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
+#define TIM1_OR2_BKDF1BK0E_Pos         (8U)                                    
+#define TIM1_OR2_BKDF1BK0E_Msk         (0x1U << TIM1_OR2_BKDF1BK0E_Pos)        /*!< 0x00000100 */
+#define TIM1_OR2_BKDF1BK0E             TIM1_OR2_BKDF1BK0E_Msk                  /*!<BRK DFSDM1_BREAK[0] enable */
+#define TIM1_OR2_BKINP_Pos             (9U)                                    
+#define TIM1_OR2_BKINP_Msk             (0x1U << TIM1_OR2_BKINP_Pos)            /*!< 0x00000200 */
+#define TIM1_OR2_BKINP                 TIM1_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */
+#define TIM1_OR2_BKCMP1P_Pos           (10U)                                   
+#define TIM1_OR2_BKCMP1P_Msk           (0x1U << TIM1_OR2_BKCMP1P_Pos)          /*!< 0x00000400 */
+#define TIM1_OR2_BKCMP1P               TIM1_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
+#define TIM1_OR2_BKCMP2P_Pos           (11U)                                   
+#define TIM1_OR2_BKCMP2P_Msk           (0x1U << TIM1_OR2_BKCMP2P_Pos)          /*!< 0x00000800 */
+#define TIM1_OR2_BKCMP2P               TIM1_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
+
+#define TIM1_OR2_ETRSEL_Pos            (14U)                                   
+#define TIM1_OR2_ETRSEL_Msk            (0x7U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x0001C000 */
+#define TIM1_OR2_ETRSEL                TIM1_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
+#define TIM1_OR2_ETRSEL_0              (0x1U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00004000 */
+#define TIM1_OR2_ETRSEL_1              (0x2U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00008000 */
+#define TIM1_OR2_ETRSEL_2              (0x4U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM1_OR3 register  *******************/
+#define TIM1_OR3_BK2INE_Pos            (0U)                                    
+#define TIM1_OR3_BK2INE_Msk            (0x1U << TIM1_OR3_BK2INE_Pos)           /*!< 0x00000001 */
+#define TIM1_OR3_BK2INE                TIM1_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */
+#define TIM1_OR3_BK2CMP1E_Pos          (1U)                                    
+#define TIM1_OR3_BK2CMP1E_Msk          (0x1U << TIM1_OR3_BK2CMP1E_Pos)         /*!< 0x00000002 */
+#define TIM1_OR3_BK2CMP1E              TIM1_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
+#define TIM1_OR3_BK2CMP2E_Pos          (2U)                                    
+#define TIM1_OR3_BK2CMP2E_Msk          (0x1U << TIM1_OR3_BK2CMP2E_Pos)         /*!< 0x00000004 */
+#define TIM1_OR3_BK2CMP2E              TIM1_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
+#define TIM1_OR3_BK2DF1BK1E_Pos        (8U)                                    
+#define TIM1_OR3_BK2DF1BK1E_Msk        (0x1U << TIM1_OR3_BK2DF1BK1E_Pos)       /*!< 0x00000100 */
+#define TIM1_OR3_BK2DF1BK1E            TIM1_OR3_BK2DF1BK1E_Msk                 /*!<BRK2 DFSDM1_BREAK[1] enable */
+#define TIM1_OR3_BK2INP_Pos            (9U)                                    
+#define TIM1_OR3_BK2INP_Msk            (0x1U << TIM1_OR3_BK2INP_Pos)           /*!< 0x00000200 */
+#define TIM1_OR3_BK2INP                TIM1_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */
+#define TIM1_OR3_BK2CMP1P_Pos          (10U)                                   
+#define TIM1_OR3_BK2CMP1P_Msk          (0x1U << TIM1_OR3_BK2CMP1P_Pos)         /*!< 0x00000400 */
+#define TIM1_OR3_BK2CMP1P              TIM1_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
+#define TIM1_OR3_BK2CMP2P_Pos          (11U)                                   
+#define TIM1_OR3_BK2CMP2P_Msk          (0x1U << TIM1_OR3_BK2CMP2P_Pos)         /*!< 0x00000800 */
+#define TIM1_OR3_BK2CMP2P              TIM1_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM8_OR1 register  *******************/
+#define TIM8_OR1_ETR_ADC2_RMP_Pos      (0U)                                    
+#define TIM8_OR1_ETR_ADC2_RMP_Msk      (0x3U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000003 */
+#define TIM8_OR1_ETR_ADC2_RMP          TIM8_OR1_ETR_ADC2_RMP_Msk               /*!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) */
+#define TIM8_OR1_ETR_ADC2_RMP_0        (0x1U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000001 */
+#define TIM8_OR1_ETR_ADC2_RMP_1        (0x2U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000002 */
+
+#define TIM8_OR1_ETR_ADC3_RMP_Pos      (2U)                                    
+#define TIM8_OR1_ETR_ADC3_RMP_Msk      (0x3U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x0000000C */
+#define TIM8_OR1_ETR_ADC3_RMP          TIM8_OR1_ETR_ADC3_RMP_Msk               /*!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) */
+#define TIM8_OR1_ETR_ADC3_RMP_0        (0x1U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000004 */
+#define TIM8_OR1_ETR_ADC3_RMP_1        (0x2U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000008 */
+
+#define TIM8_OR1_TI1_RMP_Pos           (4U)                                    
+#define TIM8_OR1_TI1_RMP_Msk           (0x1U << TIM8_OR1_TI1_RMP_Pos)          /*!< 0x00000010 */
+#define TIM8_OR1_TI1_RMP               TIM8_OR1_TI1_RMP_Msk                    /*!<TIM8 Input Capture 1 remap */
+
+/*******************  Bit definition for TIM8_OR2 register  *******************/
+#define TIM8_OR2_BKINE_Pos             (0U)                                    
+#define TIM8_OR2_BKINE_Msk             (0x1U << TIM8_OR2_BKINE_Pos)            /*!< 0x00000001 */
+#define TIM8_OR2_BKINE                 TIM8_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */
+#define TIM8_OR2_BKCMP1E_Pos           (1U)                                    
+#define TIM8_OR2_BKCMP1E_Msk           (0x1U << TIM8_OR2_BKCMP1E_Pos)          /*!< 0x00000002 */
+#define TIM8_OR2_BKCMP1E               TIM8_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
+#define TIM8_OR2_BKCMP2E_Pos           (2U)                                    
+#define TIM8_OR2_BKCMP2E_Msk           (0x1U << TIM8_OR2_BKCMP2E_Pos)          /*!< 0x00000004 */
+#define TIM8_OR2_BKCMP2E               TIM8_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
+#define TIM8_OR2_BKDF1BK2E_Pos         (8U)                                    
+#define TIM8_OR2_BKDF1BK2E_Msk         (0x1U << TIM8_OR2_BKDF1BK2E_Pos)        /*!< 0x00000100 */
+#define TIM8_OR2_BKDF1BK2E             TIM8_OR2_BKDF1BK2E_Msk                  /*!<BRK DFSDM1_BREAK[2] enable */
+#define TIM8_OR2_BKINP_Pos             (9U)                                    
+#define TIM8_OR2_BKINP_Msk             (0x1U << TIM8_OR2_BKINP_Pos)            /*!< 0x00000200 */
+#define TIM8_OR2_BKINP                 TIM8_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */
+#define TIM8_OR2_BKCMP1P_Pos           (10U)                                   
+#define TIM8_OR2_BKCMP1P_Msk           (0x1U << TIM8_OR2_BKCMP1P_Pos)          /*!< 0x00000400 */
+#define TIM8_OR2_BKCMP1P               TIM8_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
+#define TIM8_OR2_BKCMP2P_Pos           (11U)                                   
+#define TIM8_OR2_BKCMP2P_Msk           (0x1U << TIM8_OR2_BKCMP2P_Pos)          /*!< 0x00000800 */
+#define TIM8_OR2_BKCMP2P               TIM8_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
+
+#define TIM8_OR2_ETRSEL_Pos            (14U)                                   
+#define TIM8_OR2_ETRSEL_Msk            (0x7U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x0001C000 */
+#define TIM8_OR2_ETRSEL                TIM8_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */
+#define TIM8_OR2_ETRSEL_0              (0x1U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00004000 */
+#define TIM8_OR2_ETRSEL_1              (0x2U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00008000 */
+#define TIM8_OR2_ETRSEL_2              (0x4U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM8_OR3 register  *******************/
+#define TIM8_OR3_BK2INE_Pos            (0U)                                    
+#define TIM8_OR3_BK2INE_Msk            (0x1U << TIM8_OR3_BK2INE_Pos)           /*!< 0x00000001 */
+#define TIM8_OR3_BK2INE                TIM8_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */
+#define TIM8_OR3_BK2CMP1E_Pos          (1U)                                    
+#define TIM8_OR3_BK2CMP1E_Msk          (0x1U << TIM8_OR3_BK2CMP1E_Pos)         /*!< 0x00000002 */
+#define TIM8_OR3_BK2CMP1E              TIM8_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
+#define TIM8_OR3_BK2CMP2E_Pos          (2U)                                    
+#define TIM8_OR3_BK2CMP2E_Msk          (0x1U << TIM8_OR3_BK2CMP2E_Pos)         /*!< 0x00000004 */
+#define TIM8_OR3_BK2CMP2E              TIM8_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
+#define TIM8_OR3_BK2DF1BK3E_Pos        (8U)                                    
+#define TIM8_OR3_BK2DF1BK3E_Msk        (0x1U << TIM8_OR3_BK2DF1BK3E_Pos)       /*!< 0x00000100 */
+#define TIM8_OR3_BK2DF1BK3E            TIM8_OR3_BK2DF1BK3E_Msk                 /*!<BRK2 DFSDM1_BREAK[3] enable */
+#define TIM8_OR3_BK2INP_Pos            (9U)                                    
+#define TIM8_OR3_BK2INP_Msk            (0x1U << TIM8_OR3_BK2INP_Pos)           /*!< 0x00000200 */
+#define TIM8_OR3_BK2INP                TIM8_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */
+#define TIM8_OR3_BK2CMP1P_Pos          (10U)                                   
+#define TIM8_OR3_BK2CMP1P_Msk          (0x1U << TIM8_OR3_BK2CMP1P_Pos)         /*!< 0x00000400 */
+#define TIM8_OR3_BK2CMP1P              TIM8_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
+#define TIM8_OR3_BK2CMP2P_Pos          (11U)                                   
+#define TIM8_OR3_BK2CMP2P_Msk          (0x1U << TIM8_OR3_BK2CMP2P_Pos)         /*!< 0x00000800 */
+#define TIM8_OR3_BK2CMP2P              TIM8_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM2_OR1 register  *******************/
+#define TIM2_OR1_ITR1_RMP_Pos     (0U)                                         
+#define TIM2_OR1_ITR1_RMP_Msk     (0x1U << TIM2_OR1_ITR1_RMP_Pos)              /*!< 0x00000001 */
+#define TIM2_OR1_ITR1_RMP         TIM2_OR1_ITR1_RMP_Msk                        /*!<TIM2 Internal trigger 1 remap */
+#define TIM2_OR1_ETR1_RMP_Pos     (1U)                                         
+#define TIM2_OR1_ETR1_RMP_Msk     (0x1U << TIM2_OR1_ETR1_RMP_Pos)              /*!< 0x00000002 */
+#define TIM2_OR1_ETR1_RMP         TIM2_OR1_ETR1_RMP_Msk                        /*!<TIM2 External trigger 1 remap */
+
+#define TIM2_OR1_TI4_RMP_Pos      (2U)                                         
+#define TIM2_OR1_TI4_RMP_Msk      (0x3U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x0000000C */
+#define TIM2_OR1_TI4_RMP          TIM2_OR1_TI4_RMP_Msk                         /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
+#define TIM2_OR1_TI4_RMP_0        (0x1U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x00000004 */
+#define TIM2_OR1_TI4_RMP_1        (0x2U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x00000008 */
+
+/*******************  Bit definition for TIM2_OR2 register  *******************/
+#define TIM2_OR2_ETRSEL_Pos       (14U)                                        
+#define TIM2_OR2_ETRSEL_Msk       (0x7U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x0001C000 */
+#define TIM2_OR2_ETRSEL           TIM2_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
+#define TIM2_OR2_ETRSEL_0         (0x1U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM2_OR2_ETRSEL_1         (0x2U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM2_OR2_ETRSEL_2         (0x4U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM3_OR1 register  *******************/
+#define TIM3_OR1_TI1_RMP_Pos      (0U)                                         
+#define TIM3_OR1_TI1_RMP_Msk      (0x3U << TIM3_OR1_TI1_RMP_Pos)               /*!< 0x00000003 */
+#define TIM3_OR1_TI1_RMP          TIM3_OR1_TI1_RMP_Msk                         /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */
+#define TIM3_OR1_TI1_RMP_0        (0x1U << TIM3_OR1_TI1_RMP_Pos)               /*!< 0x00000001 */
+#define TIM3_OR1_TI1_RMP_1        (0x2U << TIM3_OR1_TI1_RMP_Pos)               /*!< 0x00000002 */
+
+/*******************  Bit definition for TIM3_OR2 register  *******************/
+#define TIM3_OR2_ETRSEL_Pos       (14U)                                        
+#define TIM3_OR2_ETRSEL_Msk       (0x7U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x0001C000 */
+#define TIM3_OR2_ETRSEL           TIM3_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */
+#define TIM3_OR2_ETRSEL_0         (0x1U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM3_OR2_ETRSEL_1         (0x2U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM3_OR2_ETRSEL_2         (0x4U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x00010000 */
+
+/*******************  Bit definition for TIM15_OR1 register  ******************/
+#define TIM15_OR1_TI1_RMP_Pos           (0U)                                   
+#define TIM15_OR1_TI1_RMP_Msk           (0x1U << TIM15_OR1_TI1_RMP_Pos)        /*!< 0x00000001 */
+#define TIM15_OR1_TI1_RMP               TIM15_OR1_TI1_RMP_Msk                  /*!<TIM15 Input Capture 1 remap */
+
+#define TIM15_OR1_ENCODER_MODE_Pos      (1U)                                   
+#define TIM15_OR1_ENCODER_MODE_Msk      (0x3U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000006 */
+#define TIM15_OR1_ENCODER_MODE          TIM15_OR1_ENCODER_MODE_Msk             /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
+#define TIM15_OR1_ENCODER_MODE_0        (0x1U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000002 */
+#define TIM15_OR1_ENCODER_MODE_1        (0x2U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000004 */
+
+/*******************  Bit definition for TIM15_OR2 register  ******************/
+#define TIM15_OR2_BKINE_Pos             (0U)                                   
+#define TIM15_OR2_BKINE_Msk             (0x1U << TIM15_OR2_BKINE_Pos)          /*!< 0x00000001 */
+#define TIM15_OR2_BKINE                 TIM15_OR2_BKINE_Msk                    /*!<BRK BKIN input enable */
+#define TIM15_OR2_BKCMP1E_Pos           (1U)                                   
+#define TIM15_OR2_BKCMP1E_Msk           (0x1U << TIM15_OR2_BKCMP1E_Pos)        /*!< 0x00000002 */
+#define TIM15_OR2_BKCMP1E               TIM15_OR2_BKCMP1E_Msk                  /*!<BRK COMP1 enable */
+#define TIM15_OR2_BKCMP2E_Pos           (2U)                                   
+#define TIM15_OR2_BKCMP2E_Msk           (0x1U << TIM15_OR2_BKCMP2E_Pos)        /*!< 0x00000004 */
+#define TIM15_OR2_BKCMP2E               TIM15_OR2_BKCMP2E_Msk                  /*!<BRK COMP2 enable */
+#define TIM15_OR2_BKDF1BK0E_Pos         (8U)                                   
+#define TIM15_OR2_BKDF1BK0E_Msk         (0x1U << TIM15_OR2_BKDF1BK0E_Pos)      /*!< 0x00000100 */
+#define TIM15_OR2_BKDF1BK0E             TIM15_OR2_BKDF1BK0E_Msk                /*!<BRK DFSDM1_BREAK[0] enable */
+#define TIM15_OR2_BKINP_Pos             (9U)                                   
+#define TIM15_OR2_BKINP_Msk             (0x1U << TIM15_OR2_BKINP_Pos)          /*!< 0x00000200 */
+#define TIM15_OR2_BKINP                 TIM15_OR2_BKINP_Msk                    /*!<BRK BKIN input polarity */
+#define TIM15_OR2_BKCMP1P_Pos           (10U)                                  
+#define TIM15_OR2_BKCMP1P_Msk           (0x1U << TIM15_OR2_BKCMP1P_Pos)        /*!< 0x00000400 */
+#define TIM15_OR2_BKCMP1P               TIM15_OR2_BKCMP1P_Msk                  /*!<BRK COMP1 input polarity */
+#define TIM15_OR2_BKCMP2P_Pos           (11U)                                  
+#define TIM15_OR2_BKCMP2P_Msk           (0x1U << TIM15_OR2_BKCMP2P_Pos)        /*!< 0x00000800 */
+#define TIM15_OR2_BKCMP2P               TIM15_OR2_BKCMP2P_Msk                  /*!<BRK COMP2 input polarity */
+
+/*******************  Bit definition for TIM16_OR1 register  ******************/
+#define TIM16_OR1_TI1_RMP_Pos      (0U)                                        
+#define TIM16_OR1_TI1_RMP_Msk      (0x3U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000003 */
+#define TIM16_OR1_TI1_RMP          TIM16_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */
+#define TIM16_OR1_TI1_RMP_0        (0x1U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000001 */
+#define TIM16_OR1_TI1_RMP_1        (0x2U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000002 */
+
+/*******************  Bit definition for TIM16_OR2 register  ******************/
+#define TIM16_OR2_BKINE_Pos        (0U)                                        
+#define TIM16_OR2_BKINE_Msk        (0x1U << TIM16_OR2_BKINE_Pos)               /*!< 0x00000001 */
+#define TIM16_OR2_BKINE            TIM16_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */
+#define TIM16_OR2_BKCMP1E_Pos      (1U)                                        
+#define TIM16_OR2_BKCMP1E_Msk      (0x1U << TIM16_OR2_BKCMP1E_Pos)             /*!< 0x00000002 */
+#define TIM16_OR2_BKCMP1E          TIM16_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */
+#define TIM16_OR2_BKCMP2E_Pos      (2U)                                        
+#define TIM16_OR2_BKCMP2E_Msk      (0x1U << TIM16_OR2_BKCMP2E_Pos)             /*!< 0x00000004 */
+#define TIM16_OR2_BKCMP2E          TIM16_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */
+#define TIM16_OR2_BKDF1BK1E_Pos    (8U)                                        
+#define TIM16_OR2_BKDF1BK1E_Msk    (0x1U << TIM16_OR2_BKDF1BK1E_Pos)           /*!< 0x00000100 */
+#define TIM16_OR2_BKDF1BK1E        TIM16_OR2_BKDF1BK1E_Msk                     /*!<BRK DFSDM1_BREAK[1] enable */
+#define TIM16_OR2_BKINP_Pos        (9U)                                        
+#define TIM16_OR2_BKINP_Msk        (0x1U << TIM16_OR2_BKINP_Pos)               /*!< 0x00000200 */
+#define TIM16_OR2_BKINP            TIM16_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */
+#define TIM16_OR2_BKCMP1P_Pos      (10U)                                       
+#define TIM16_OR2_BKCMP1P_Msk      (0x1U << TIM16_OR2_BKCMP1P_Pos)             /*!< 0x00000400 */
+#define TIM16_OR2_BKCMP1P          TIM16_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */
+#define TIM16_OR2_BKCMP2P_Pos      (11U)                                       
+#define TIM16_OR2_BKCMP2P_Msk      (0x1U << TIM16_OR2_BKCMP2P_Pos)             /*!< 0x00000800 */
+#define TIM16_OR2_BKCMP2P          TIM16_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */
+
+/*******************  Bit definition for TIM17_OR1 register  ******************/
+#define TIM17_OR1_TI1_RMP_Pos      (0U)                                        
+#define TIM17_OR1_TI1_RMP_Msk      (0x3U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000003 */
+#define TIM17_OR1_TI1_RMP          TIM17_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */
+#define TIM17_OR1_TI1_RMP_0        (0x1U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000001 */
+#define TIM17_OR1_TI1_RMP_1        (0x2U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000002 */
+
+/*******************  Bit definition for TIM17_OR2 register  ******************/
+#define TIM17_OR2_BKINE_Pos        (0U)                                        
+#define TIM17_OR2_BKINE_Msk        (0x1U << TIM17_OR2_BKINE_Pos)               /*!< 0x00000001 */
+#define TIM17_OR2_BKINE            TIM17_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */
+#define TIM17_OR2_BKCMP1E_Pos      (1U)                                        
+#define TIM17_OR2_BKCMP1E_Msk      (0x1U << TIM17_OR2_BKCMP1E_Pos)             /*!< 0x00000002 */
+#define TIM17_OR2_BKCMP1E          TIM17_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */
+#define TIM17_OR2_BKCMP2E_Pos      (2U)                                        
+#define TIM17_OR2_BKCMP2E_Msk      (0x1U << TIM17_OR2_BKCMP2E_Pos)             /*!< 0x00000004 */
+#define TIM17_OR2_BKCMP2E          TIM17_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */
+#define TIM17_OR2_BKDF1BK2E_Pos    (8U)                                        
+#define TIM17_OR2_BKDF1BK2E_Msk    (0x1U << TIM17_OR2_BKDF1BK2E_Pos)           /*!< 0x00000100 */
+#define TIM17_OR2_BKDF1BK2E        TIM17_OR2_BKDF1BK2E_Msk                     /*!<BRK DFSDM1_BREAK[2] enable */
+#define TIM17_OR2_BKINP_Pos        (9U)                                        
+#define TIM17_OR2_BKINP_Msk        (0x1U << TIM17_OR2_BKINP_Pos)               /*!< 0x00000200 */
+#define TIM17_OR2_BKINP            TIM17_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */
+#define TIM17_OR2_BKCMP1P_Pos      (10U)                                       
+#define TIM17_OR2_BKCMP1P_Msk      (0x1U << TIM17_OR2_BKCMP1P_Pos)             /*!< 0x00000400 */
+#define TIM17_OR2_BKCMP1P          TIM17_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */
+#define TIM17_OR2_BKCMP2P_Pos      (11U)                                       
+#define TIM17_OR2_BKCMP2P_Msk      (0x1U << TIM17_OR2_BKCMP2P_Pos)             /*!< 0x00000800 */
+#define TIM17_OR2_BKCMP2P          TIM17_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTTIM)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define LPTIM_ISR_CMPM_Pos          (0U)                                       
+#define LPTIM_ISR_CMPM_Msk          (0x1U << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos          (1U)                                       
+#define LPTIM_ISR_ARRM_Msk          (0x1U << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos       (2U)                                       
+#define LPTIM_ISR_EXTTRIG_Msk       (0x1U << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos         (3U)                                       
+#define LPTIM_ISR_CMPOK_Msk         (0x1U << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos         (4U)                                       
+#define LPTIM_ISR_ARROK_Msk         (0x1U << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos            (5U)                                       
+#define LPTIM_ISR_UP_Msk            (0x1U << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos          (6U)                                       
+#define LPTIM_ISR_DOWN_Msk          (0x1U << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define LPTIM_ICR_CMPMCF_Pos        (0U)                                       
+#define LPTIM_ICR_CMPMCF_Msk        (0x1U << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos        (1U)                                       
+#define LPTIM_ICR_ARRMCF_Msk        (0x1U << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)                                       
+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1U << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos       (3U)                                       
+#define LPTIM_ICR_CMPOKCF_Msk       (0x1U << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos       (4U)                                       
+#define LPTIM_ICR_ARROKCF_Msk       (0x1U << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos          (5U)                                       
+#define LPTIM_ICR_UPCF_Msk          (0x1U << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos        (6U)                                       
+#define LPTIM_ICR_DOWNCF_Msk        (0x1U << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
+
+/******************  Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos        (0U)                                       
+#define LPTIM_IER_CMPMIE_Msk        (0x1U << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos        (1U)                                       
+#define LPTIM_IER_ARRMIE_Msk        (0x1U << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)                                       
+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1U << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos       (3U)                                       
+#define LPTIM_IER_CMPOKIE_Msk       (0x1U << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos       (4U)                                       
+#define LPTIM_IER_ARROKIE_Msk       (0x1U << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos          (5U)                                       
+#define LPTIM_IER_UPIE_Msk          (0x1U << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos        (6U)                                       
+#define LPTIM_IER_DOWNIE_Msk        (0x1U << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
+
+/******************  Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos        (0U)                                       
+#define LPTIM_CFGR_CKSEL_Msk        (0x1U << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos        (1U)                                       
+#define LPTIM_CFGR_CKPOL_Msk        (0x3U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0          (0x1U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1          (0x2U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos        (3U)                                       
+#define LPTIM_CFGR_CKFLT_Msk        (0x3U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0          (0x1U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1          (0x2U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos       (6U)                                       
+#define LPTIM_CFGR_TRGFLT_Msk       (0x3U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0         (0x1U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1         (0x2U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos        (9U)                                       
+#define LPTIM_CFGR_PRESC_Msk        (0x7U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0          (0x1U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1          (0x2U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2          (0x4U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)                                      
+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0        (0x1U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1        (0x2U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2        (0x4U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos       (17U)                                      
+#define LPTIM_CFGR_TRIGEN_Msk       (0x3U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0         (0x1U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1         (0x2U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos       (19U)                                      
+#define LPTIM_CFGR_TIMOUT_Msk       (0x1U << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos         (20U)                                      
+#define LPTIM_CFGR_WAVE_Msk         (0x1U << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos       (21U)                                      
+#define LPTIM_CFGR_WAVPOL_Msk       (0x1U << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos      (22U)                                      
+#define LPTIM_CFGR_PRELOAD_Msk      (0x1U << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)                                      
+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1U << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos          (24U)                                      
+#define LPTIM_CFGR_ENC_Msk          (0x1U << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define LPTIM_CR_ENABLE_Pos         (0U)                                       
+#define LPTIM_CR_ENABLE_Msk         (0x1U << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos        (1U)                                       
+#define LPTIM_CR_SNGSTRT_Msk        (0x1U << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos        (2U)                                       
+#define LPTIM_CR_CNTSTRT_Msk        (0x1U << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
+
+/******************  Bit definition for LPTIM_CMP register  *******************/
+#define LPTIM_CMP_CMP_Pos           (0U)                                       
+#define LPTIM_CMP_CMP_Msk           (0xFFFFU << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
+
+/******************  Bit definition for LPTIM_ARR register  *******************/
+#define LPTIM_ARR_ARR_Pos           (0U)                                       
+#define LPTIM_ARR_ARR_Msk           (0xFFFFU << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define LPTIM_CNT_CNT_Pos           (0U)                                       
+#define LPTIM_CNT_CNT_Msk           (0xFFFFU << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
+
+/******************  Bit definition for LPTIM_OR register  ********************/
+#define LPTIM_OR_OR_Pos             (0U)                                       
+#define LPTIM_OR_OR_Msk             (0x3U << LPTIM_OR_OR_Pos)                  /*!< 0x00000003 */
+#define LPTIM_OR_OR                 LPTIM_OR_OR_Msk                            /*!< OR[1:0] bits (Remap selection) */
+#define LPTIM_OR_OR_0               (0x1U << LPTIM_OR_OR_Pos)                  /*!< 0x00000001 */
+#define LPTIM_OR_OR_1               (0x2U << LPTIM_OR_OR_Pos)                  /*!< 0x00000002 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+/**********************  Bit definition for COMP_CSR register  ****************/
+#define COMP_CSR_EN_Pos            (0U)                                        
+#define COMP_CSR_EN_Msk            (0x1U << COMP_CSR_EN_Pos)                   /*!< 0x00000001 */
+#define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
+
+#define COMP_CSR_PWRMODE_Pos       (2U)                                        
+#define COMP_CSR_PWRMODE_Msk       (0x3U << COMP_CSR_PWRMODE_Pos)              /*!< 0x0000000C */
+#define COMP_CSR_PWRMODE           COMP_CSR_PWRMODE_Msk                        /*!< Comparator power mode */
+#define COMP_CSR_PWRMODE_0         (0x1U << COMP_CSR_PWRMODE_Pos)              /*!< 0x00000004 */
+#define COMP_CSR_PWRMODE_1         (0x2U << COMP_CSR_PWRMODE_Pos)              /*!< 0x00000008 */
+
+#define COMP_CSR_INMSEL_Pos        (4U)                                        
+#define COMP_CSR_INMSEL_Msk        (0x7U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000070 */
+#define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
+#define COMP_CSR_INMSEL_0          (0x1U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000010 */
+#define COMP_CSR_INMSEL_1          (0x2U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000020 */
+#define COMP_CSR_INMSEL_2          (0x4U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000040 */
+
+#define COMP_CSR_INPSEL_Pos        (7U)                                        
+#define COMP_CSR_INPSEL_Msk        (0x1U << COMP_CSR_INPSEL_Pos)               /*!< 0x00000080 */
+#define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
+#define COMP_CSR_INPSEL_0          (0x1U << COMP_CSR_INPSEL_Pos)               /*!< 0x00000080 */
+
+#define COMP_CSR_WINMODE_Pos       (9U)                                        
+#define COMP_CSR_WINMODE_Msk       (0x1U << COMP_CSR_WINMODE_Pos)              /*!< 0x00000200 */
+#define COMP_CSR_WINMODE           COMP_CSR_WINMODE_Msk                        /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
+
+#define COMP_CSR_POLARITY_Pos      (15U)                                       
+#define COMP_CSR_POLARITY_Msk      (0x1U << COMP_CSR_POLARITY_Pos)             /*!< 0x00008000 */
+#define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
+
+#define COMP_CSR_HYST_Pos          (16U)                                       
+#define COMP_CSR_HYST_Msk          (0x3U << COMP_CSR_HYST_Pos)                 /*!< 0x00030000 */
+#define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
+#define COMP_CSR_HYST_0            (0x1U << COMP_CSR_HYST_Pos)                 /*!< 0x00010000 */
+#define COMP_CSR_HYST_1            (0x2U << COMP_CSR_HYST_Pos)                 /*!< 0x00020000 */
+
+#define COMP_CSR_BLANKING_Pos      (18U)                                       
+#define COMP_CSR_BLANKING_Msk      (0x7U << COMP_CSR_BLANKING_Pos)             /*!< 0x001C0000 */
+#define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
+#define COMP_CSR_BLANKING_0        (0x1U << COMP_CSR_BLANKING_Pos)             /*!< 0x00040000 */
+#define COMP_CSR_BLANKING_1        (0x2U << COMP_CSR_BLANKING_Pos)             /*!< 0x00080000 */
+#define COMP_CSR_BLANKING_2        (0x4U << COMP_CSR_BLANKING_Pos)             /*!< 0x00100000 */
+
+#define COMP_CSR_BRGEN_Pos         (22U)                                       
+#define COMP_CSR_BRGEN_Msk         (0x1U << COMP_CSR_BRGEN_Pos)                /*!< 0x00400000 */
+#define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator voltage scaler enable */
+#define COMP_CSR_SCALEN_Pos        (23U)                                       
+#define COMP_CSR_SCALEN_Msk        (0x1U << COMP_CSR_SCALEN_Pos)               /*!< 0x00800000 */
+#define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator scaler bridge enable */
+
+#define COMP_CSR_VALUE_Pos         (30U)                                       
+#define COMP_CSR_VALUE_Msk         (0x1U << COMP_CSR_VALUE_Pos)                /*!< 0x40000000 */
+#define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
+
+#define COMP_CSR_LOCK_Pos          (31U)                                       
+#define COMP_CSR_LOCK_Msk          (0x1U << COMP_CSR_LOCK_Pos)                 /*!< 0x80000000 */
+#define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Operational Amplifier (OPAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/*********************  Bit definition for OPAMPx_CSR register  ***************/
+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)                                  
+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1U << OPAMP_CSR_OPAMPxEN_Pos)      /*!< 0x00000001 */
+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */
+#define OPAMP_CSR_OPALPM_Pos             (1U)                                  
+#define OPAMP_CSR_OPALPM_Msk             (0x1U << OPAMP_CSR_OPALPM_Pos)        /*!< 0x00000002 */
+#define OPAMP_CSR_OPALPM                 OPAMP_CSR_OPALPM_Msk                  /*!< Operational amplifier Low Power Mode */
+
+#define OPAMP_CSR_OPAMODE_Pos            (2U)                                  
+#define OPAMP_CSR_OPAMODE_Msk            (0x3U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x0000000C */
+#define OPAMP_CSR_OPAMODE                OPAMP_CSR_OPAMODE_Msk                 /*!< Operational amplifier PGA mode */
+#define OPAMP_CSR_OPAMODE_0              (0x1U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x00000004 */
+#define OPAMP_CSR_OPAMODE_1              (0x2U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x00000008 */
+
+#define OPAMP_CSR_PGGAIN_Pos             (4U)                                  
+#define OPAMP_CSR_PGGAIN_Msk             (0x3U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000030 */
+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */
+#define OPAMP_CSR_PGGAIN_0               (0x1U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000010 */
+#define OPAMP_CSR_PGGAIN_1               (0x2U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000020 */
+
+#define OPAMP_CSR_VMSEL_Pos              (8U)                                  
+#define OPAMP_CSR_VMSEL_Msk              (0x3U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000300 */
+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0                (0x1U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000100 */
+#define OPAMP_CSR_VMSEL_1                (0x2U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000200 */
+
+#define OPAMP_CSR_VPSEL_Pos              (10U)                                 
+#define OPAMP_CSR_VPSEL_Msk              (0x1U << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000400 */
+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */
+#define OPAMP_CSR_CALON_Pos              (12U)                                 
+#define OPAMP_CSR_CALON_Msk              (0x1U << OPAMP_CSR_CALON_Pos)         /*!< 0x00001000 */
+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */
+#define OPAMP_CSR_CALSEL_Pos             (13U)                                 
+#define OPAMP_CSR_CALSEL_Msk             (0x1U << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */
+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */
+#define OPAMP_CSR_USERTRIM_Pos           (14U)                                 
+#define OPAMP_CSR_USERTRIM_Msk           (0x1U << OPAMP_CSR_USERTRIM_Pos)      /*!< 0x00004000 */
+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */
+#define OPAMP_CSR_CALOUT_Pos             (15U)                                 
+#define OPAMP_CSR_CALOUT_Msk             (0x1U << OPAMP_CSR_CALOUT_Pos)        /*!< 0x00008000 */
+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier1 calibration output */
+
+/*********************  Bit definition for OPAMP1_CSR register  ***************/
+#define OPAMP1_CSR_OPAEN_Pos              (0U)                                 
+#define OPAMP1_CSR_OPAEN_Msk              (0x1U << OPAMP1_CSR_OPAEN_Pos)       /*!< 0x00000001 */
+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */
+#define OPAMP1_CSR_OPALPM_Pos             (1U)                                 
+#define OPAMP1_CSR_OPALPM_Msk             (0x1U << OPAMP1_CSR_OPALPM_Pos)      /*!< 0x00000002 */
+#define OPAMP1_CSR_OPALPM                 OPAMP1_CSR_OPALPM_Msk                /*!< Operational amplifier1 Low Power Mode */
+
+#define OPAMP1_CSR_OPAMODE_Pos            (2U)                                 
+#define OPAMP1_CSR_OPAMODE_Msk            (0x3U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x0000000C */
+#define OPAMP1_CSR_OPAMODE                OPAMP1_CSR_OPAMODE_Msk               /*!< Operational amplifier1 PGA mode */
+#define OPAMP1_CSR_OPAMODE_0              (0x1U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x00000004 */
+#define OPAMP1_CSR_OPAMODE_1              (0x2U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x00000008 */
+
+#define OPAMP1_CSR_PGAGAIN_Pos            (4U)                                 
+#define OPAMP1_CSR_PGAGAIN_Msk            (0x3U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000030 */
+#define OPAMP1_CSR_PGAGAIN                OPAMP1_CSR_PGAGAIN_Msk               /*!< Operational amplifier1 Programmable amplifier gain value */
+#define OPAMP1_CSR_PGAGAIN_0              (0x1U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000010 */
+#define OPAMP1_CSR_PGAGAIN_1              (0x2U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000020 */
+
+#define OPAMP1_CSR_VMSEL_Pos              (8U)                                 
+#define OPAMP1_CSR_VMSEL_Msk              (0x3U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000300 */
+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0                (0x1U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000100 */
+#define OPAMP1_CSR_VMSEL_1                (0x2U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000200 */
+
+#define OPAMP1_CSR_VPSEL_Pos              (10U)                                
+#define OPAMP1_CSR_VPSEL_Msk              (0x1U << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000400 */
+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP1_CSR_CALON_Pos              (12U)                                
+#define OPAMP1_CSR_CALON_Msk              (0x1U << OPAMP1_CSR_CALON_Pos)       /*!< 0x00001000 */
+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */
+#define OPAMP1_CSR_CALSEL_Pos             (13U)                                
+#define OPAMP1_CSR_CALSEL_Msk             (0x1U << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP1_CSR_USERTRIM_Pos           (14U)                                
+#define OPAMP1_CSR_USERTRIM_Msk           (0x1U << OPAMP1_CSR_USERTRIM_Pos)    /*!< 0x00004000 */
+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP1_CSR_CALOUT_Pos             (15U)                                
+#define OPAMP1_CSR_CALOUT_Msk             (0x1U << OPAMP1_CSR_CALOUT_Pos)      /*!< 0x00008000 */
+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */
+
+#define OPAMP1_CSR_OPARANGE_Pos           (31U)                                
+#define OPAMP1_CSR_OPARANGE_Msk           (0x1U << OPAMP1_CSR_OPARANGE_Pos)    /*!< 0x80000000 */
+#define OPAMP1_CSR_OPARANGE               OPAMP1_CSR_OPARANGE_Msk              /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
+
+/*********************  Bit definition for OPAMP2_CSR register  ***************/
+#define OPAMP2_CSR_OPAEN_Pos              (0U)                                 
+#define OPAMP2_CSR_OPAEN_Msk              (0x1U << OPAMP2_CSR_OPAEN_Pos)       /*!< 0x00000001 */
+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */
+#define OPAMP2_CSR_OPALPM_Pos             (1U)                                 
+#define OPAMP2_CSR_OPALPM_Msk             (0x1U << OPAMP2_CSR_OPALPM_Pos)      /*!< 0x00000002 */
+#define OPAMP2_CSR_OPALPM                 OPAMP2_CSR_OPALPM_Msk                /*!< Operational amplifier2 Low Power Mode */
+
+#define OPAMP2_CSR_OPAMODE_Pos            (2U)                                 
+#define OPAMP2_CSR_OPAMODE_Msk            (0x3U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x0000000C */
+#define OPAMP2_CSR_OPAMODE                OPAMP2_CSR_OPAMODE_Msk               /*!< Operational amplifier2 PGA mode */
+#define OPAMP2_CSR_OPAMODE_0              (0x1U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x00000004 */
+#define OPAMP2_CSR_OPAMODE_1              (0x2U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x00000008 */
+
+#define OPAMP2_CSR_PGAGAIN_Pos            (4U)                                 
+#define OPAMP2_CSR_PGAGAIN_Msk            (0x3U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000030 */
+#define OPAMP2_CSR_PGAGAIN                OPAMP2_CSR_PGAGAIN_Msk               /*!< Operational amplifier2 Programmable amplifier gain value */
+#define OPAMP2_CSR_PGAGAIN_0              (0x1U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000010 */
+#define OPAMP2_CSR_PGAGAIN_1              (0x2U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000020 */
+
+#define OPAMP2_CSR_VMSEL_Pos              (8U)                                 
+#define OPAMP2_CSR_VMSEL_Msk              (0x3U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000300 */
+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0                (0x1U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000100 */
+#define OPAMP2_CSR_VMSEL_1                (0x2U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000200 */
+
+#define OPAMP2_CSR_VPSEL_Pos              (10U)                                
+#define OPAMP2_CSR_VPSEL_Msk              (0x1U << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000400 */
+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP2_CSR_CALON_Pos              (12U)                                
+#define OPAMP2_CSR_CALON_Msk              (0x1U << OPAMP2_CSR_CALON_Pos)       /*!< 0x00001000 */
+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */
+#define OPAMP2_CSR_CALSEL_Pos             (13U)                                
+#define OPAMP2_CSR_CALSEL_Msk             (0x1U << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP2_CSR_USERTRIM_Pos           (14U)                                
+#define OPAMP2_CSR_USERTRIM_Msk           (0x1U << OPAMP2_CSR_USERTRIM_Pos)    /*!< 0x00004000 */
+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP2_CSR_CALOUT_Pos             (15U)                                
+#define OPAMP2_CSR_CALOUT_Msk             (0x1U << OPAMP2_CSR_CALOUT_Pos)      /*!< 0x00008000 */
+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */
+
+/*******************  Bit definition for OPAMP_OTR register  ******************/
+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)                                  
+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos)  /*!< 0x0000001F */
+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)                                  
+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos)  /*!< 0x00001F00 */
+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_OTR register  ******************/
+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)                                 
+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)                                 
+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_OTR register  ******************/
+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)                                 
+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)                                 
+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP_LPOTR register  ****************/
+#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos    (0U)                                  
+#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_LPOTR_TRIMLPOFFSETN        OPAMP_LPOTR_TRIMLPOFFSETN_Msk         /*!< Trim for NMOS differential pairs */
+#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos    (8U)                                  
+#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_LPOTR_TRIMLPOFFSETP        OPAMP_LPOTR_TRIMLPOFFSETP_Msk         /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_LPOTR register  ****************/
+#define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos    (0U)                                 
+#define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_LPOTR_TRIMLPOFFSETN        OPAMP1_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos    (8U)                                 
+#define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_LPOTR_TRIMLPOFFSETP        OPAMP1_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_LPOTR register  ****************/
+#define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos    (0U)                                 
+#define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_LPOTR_TRIMLPOFFSETN        OPAMP2_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos    (8U)                                 
+#define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_LPOTR_TRIMLPOFFSETP        OPAMP2_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Touch Sensing Controller (TSC)                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TSC_CR register  *********************/
+#define TSC_CR_TSCE_Pos          (0U)                                          
+#define TSC_CR_TSCE_Msk          (0x1U << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
+#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
+#define TSC_CR_START_Pos         (1U)                                          
+#define TSC_CR_START_Msk         (0x1U << TSC_CR_START_Pos)                    /*!< 0x00000002 */
+#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
+#define TSC_CR_AM_Pos            (2U)                                          
+#define TSC_CR_AM_Msk            (0x1U << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
+#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL_Pos       (3U)                                          
+#define TSC_CR_SYNCPOL_Msk       (0x1U << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
+#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF_Pos         (4U)                                          
+#define TSC_CR_IODEF_Msk         (0x1U << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
+#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
+
+#define TSC_CR_MCV_Pos           (5U)                                          
+#define TSC_CR_MCV_Msk           (0x7U << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
+#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0             (0x1U << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
+#define TSC_CR_MCV_1             (0x2U << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
+#define TSC_CR_MCV_2             (0x4U << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
+
+#define TSC_CR_PGPSC_Pos         (12U)                                         
+#define TSC_CR_PGPSC_Msk         (0x7U << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
+#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0           (0x1U << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
+#define TSC_CR_PGPSC_1           (0x2U << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
+#define TSC_CR_PGPSC_2           (0x4U << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
+
+#define TSC_CR_SSPSC_Pos         (15U)                                         
+#define TSC_CR_SSPSC_Msk         (0x1U << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
+#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE_Pos           (16U)                                         
+#define TSC_CR_SSE_Msk           (0x1U << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
+#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD_Pos           (17U)                                         
+#define TSC_CR_SSD_Msk           (0x7FU << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
+#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0             (0x01U << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
+#define TSC_CR_SSD_1             (0x02U << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
+#define TSC_CR_SSD_2             (0x04U << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
+#define TSC_CR_SSD_3             (0x08U << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
+#define TSC_CR_SSD_4             (0x10U << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
+#define TSC_CR_SSD_5             (0x20U << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
+#define TSC_CR_SSD_6             (0x40U << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
+
+#define TSC_CR_CTPL_Pos          (24U)                                         
+#define TSC_CR_CTPL_Msk          (0xFU << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
+#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0            (0x1U << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
+#define TSC_CR_CTPL_1            (0x2U << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
+#define TSC_CR_CTPL_2            (0x4U << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
+#define TSC_CR_CTPL_3            (0x8U << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
+
+#define TSC_CR_CTPH_Pos          (28U)                                         
+#define TSC_CR_CTPH_Msk          (0xFU << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
+#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0            (0x1U << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
+#define TSC_CR_CTPH_1            (0x2U << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
+#define TSC_CR_CTPH_2            (0x4U << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
+#define TSC_CR_CTPH_3            (0x8U << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
+
+/*******************  Bit definition for TSC_IER register  ********************/
+#define TSC_IER_EOAIE_Pos        (0U)                                          
+#define TSC_IER_EOAIE_Msk        (0x1U << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
+#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE_Pos        (1U)                                          
+#define TSC_IER_MCEIE_Msk        (0x1U << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
+#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
+
+/*******************  Bit definition for TSC_ICR register  ********************/
+#define TSC_ICR_EOAIC_Pos        (0U)                                          
+#define TSC_ICR_EOAIC_Msk        (0x1U << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
+#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC_Pos        (1U)                                          
+#define TSC_ICR_MCEIC_Msk        (0x1U << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
+#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
+
+/*******************  Bit definition for TSC_ISR register  ********************/
+#define TSC_ISR_EOAF_Pos         (0U)                                          
+#define TSC_ISR_EOAF_Msk         (0x1U << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
+#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
+#define TSC_ISR_MCEF_Pos         (1U)                                          
+#define TSC_ISR_MCEF_Msk         (0x1U << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
+#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
+
+/*******************  Bit definition for TSC_IOHCR register  ******************/
+#define TSC_IOHCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOHCR_G1_IO1_Msk     (0x1U << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOHCR_G1_IO2_Msk     (0x1U << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOHCR_G1_IO3_Msk     (0x1U << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOHCR_G1_IO4_Msk     (0x1U << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOHCR_G2_IO1_Msk     (0x1U << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOHCR_G2_IO2_Msk     (0x1U << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOHCR_G2_IO3_Msk     (0x1U << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOHCR_G2_IO4_Msk     (0x1U << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOHCR_G3_IO1_Msk     (0x1U << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOHCR_G3_IO2_Msk     (0x1U << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOHCR_G3_IO3_Msk     (0x1U << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOHCR_G3_IO4_Msk     (0x1U << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOHCR_G4_IO1_Msk     (0x1U << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOHCR_G4_IO2_Msk     (0x1U << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOHCR_G4_IO3_Msk     (0x1U << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOHCR_G4_IO4_Msk     (0x1U << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOHCR_G5_IO1_Msk     (0x1U << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOHCR_G5_IO2_Msk     (0x1U << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOHCR_G5_IO3_Msk     (0x1U << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOHCR_G5_IO4_Msk     (0x1U << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOHCR_G6_IO1_Msk     (0x1U << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOHCR_G6_IO2_Msk     (0x1U << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOHCR_G6_IO3_Msk     (0x1U << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOHCR_G6_IO4_Msk     (0x1U << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOHCR_G7_IO1_Msk     (0x1U << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOHCR_G7_IO2_Msk     (0x1U << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOHCR_G7_IO3_Msk     (0x1U << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOHCR_G7_IO4_Msk     (0x1U << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1_Pos     (28U)                                         
+#define TSC_IOHCR_G8_IO1_Msk     (0x1U << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
+#define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2_Pos     (29U)                                         
+#define TSC_IOHCR_G8_IO2_Msk     (0x1U << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
+#define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3_Pos     (30U)                                         
+#define TSC_IOHCR_G8_IO3_Msk     (0x1U << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
+#define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4_Pos     (31U)                                         
+#define TSC_IOHCR_G8_IO4_Msk     (0x1U << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
+#define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/*******************  Bit definition for TSC_IOASCR register  *****************/
+#define TSC_IOASCR_G1_IO1_Pos    (0U)                                          
+#define TSC_IOASCR_G1_IO1_Msk    (0x1U << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
+#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2_Pos    (1U)                                          
+#define TSC_IOASCR_G1_IO2_Msk    (0x1U << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
+#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3_Pos    (2U)                                          
+#define TSC_IOASCR_G1_IO3_Msk    (0x1U << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
+#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4_Pos    (3U)                                          
+#define TSC_IOASCR_G1_IO4_Msk    (0x1U << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
+#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1_Pos    (4U)                                          
+#define TSC_IOASCR_G2_IO1_Msk    (0x1U << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
+#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2_Pos    (5U)                                          
+#define TSC_IOASCR_G2_IO2_Msk    (0x1U << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
+#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3_Pos    (6U)                                          
+#define TSC_IOASCR_G2_IO3_Msk    (0x1U << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
+#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4_Pos    (7U)                                          
+#define TSC_IOASCR_G2_IO4_Msk    (0x1U << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
+#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1_Pos    (8U)                                          
+#define TSC_IOASCR_G3_IO1_Msk    (0x1U << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
+#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2_Pos    (9U)                                          
+#define TSC_IOASCR_G3_IO2_Msk    (0x1U << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
+#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3_Pos    (10U)                                         
+#define TSC_IOASCR_G3_IO3_Msk    (0x1U << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
+#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4_Pos    (11U)                                         
+#define TSC_IOASCR_G3_IO4_Msk    (0x1U << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
+#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1_Pos    (12U)                                         
+#define TSC_IOASCR_G4_IO1_Msk    (0x1U << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
+#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2_Pos    (13U)                                         
+#define TSC_IOASCR_G4_IO2_Msk    (0x1U << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
+#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3_Pos    (14U)                                         
+#define TSC_IOASCR_G4_IO3_Msk    (0x1U << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
+#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4_Pos    (15U)                                         
+#define TSC_IOASCR_G4_IO4_Msk    (0x1U << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
+#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1_Pos    (16U)                                         
+#define TSC_IOASCR_G5_IO1_Msk    (0x1U << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
+#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2_Pos    (17U)                                         
+#define TSC_IOASCR_G5_IO2_Msk    (0x1U << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
+#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3_Pos    (18U)                                         
+#define TSC_IOASCR_G5_IO3_Msk    (0x1U << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
+#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4_Pos    (19U)                                         
+#define TSC_IOASCR_G5_IO4_Msk    (0x1U << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
+#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1_Pos    (20U)                                         
+#define TSC_IOASCR_G6_IO1_Msk    (0x1U << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
+#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2_Pos    (21U)                                         
+#define TSC_IOASCR_G6_IO2_Msk    (0x1U << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
+#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3_Pos    (22U)                                         
+#define TSC_IOASCR_G6_IO3_Msk    (0x1U << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
+#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4_Pos    (23U)                                         
+#define TSC_IOASCR_G6_IO4_Msk    (0x1U << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
+#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1_Pos    (24U)                                         
+#define TSC_IOASCR_G7_IO1_Msk    (0x1U << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
+#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2_Pos    (25U)                                         
+#define TSC_IOASCR_G7_IO2_Msk    (0x1U << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
+#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3_Pos    (26U)                                         
+#define TSC_IOASCR_G7_IO3_Msk    (0x1U << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
+#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4_Pos    (27U)                                         
+#define TSC_IOASCR_G7_IO4_Msk    (0x1U << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
+#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1_Pos    (28U)                                         
+#define TSC_IOASCR_G8_IO1_Msk    (0x1U << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
+#define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2_Pos    (29U)                                         
+#define TSC_IOASCR_G8_IO2_Msk    (0x1U << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
+#define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3_Pos    (30U)                                         
+#define TSC_IOASCR_G8_IO3_Msk    (0x1U << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
+#define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4_Pos    (31U)                                         
+#define TSC_IOASCR_G8_IO4_Msk    (0x1U << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
+#define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
+
+/*******************  Bit definition for TSC_IOSCR register  ******************/
+#define TSC_IOSCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOSCR_G1_IO1_Msk     (0x1U << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOSCR_G1_IO2_Msk     (0x1U << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOSCR_G1_IO3_Msk     (0x1U << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOSCR_G1_IO4_Msk     (0x1U << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOSCR_G2_IO1_Msk     (0x1U << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOSCR_G2_IO2_Msk     (0x1U << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOSCR_G2_IO3_Msk     (0x1U << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOSCR_G2_IO4_Msk     (0x1U << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOSCR_G3_IO1_Msk     (0x1U << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOSCR_G3_IO2_Msk     (0x1U << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOSCR_G3_IO3_Msk     (0x1U << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOSCR_G3_IO4_Msk     (0x1U << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOSCR_G4_IO1_Msk     (0x1U << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOSCR_G4_IO2_Msk     (0x1U << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOSCR_G4_IO3_Msk     (0x1U << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOSCR_G4_IO4_Msk     (0x1U << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOSCR_G5_IO1_Msk     (0x1U << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOSCR_G5_IO2_Msk     (0x1U << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOSCR_G5_IO3_Msk     (0x1U << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOSCR_G5_IO4_Msk     (0x1U << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOSCR_G6_IO1_Msk     (0x1U << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOSCR_G6_IO2_Msk     (0x1U << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOSCR_G6_IO3_Msk     (0x1U << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOSCR_G6_IO4_Msk     (0x1U << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOSCR_G7_IO1_Msk     (0x1U << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOSCR_G7_IO2_Msk     (0x1U << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOSCR_G7_IO3_Msk     (0x1U << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOSCR_G7_IO4_Msk     (0x1U << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1_Pos     (28U)                                         
+#define TSC_IOSCR_G8_IO1_Msk     (0x1U << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
+#define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2_Pos     (29U)                                         
+#define TSC_IOSCR_G8_IO2_Msk     (0x1U << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
+#define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3_Pos     (30U)                                         
+#define TSC_IOSCR_G8_IO3_Msk     (0x1U << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
+#define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4_Pos     (31U)                                         
+#define TSC_IOSCR_G8_IO4_Msk     (0x1U << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
+#define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
+
+/*******************  Bit definition for TSC_IOCCR register  ******************/
+#define TSC_IOCCR_G1_IO1_Pos     (0U)                                          
+#define TSC_IOCCR_G1_IO1_Msk     (0x1U << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
+#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2_Pos     (1U)                                          
+#define TSC_IOCCR_G1_IO2_Msk     (0x1U << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
+#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3_Pos     (2U)                                          
+#define TSC_IOCCR_G1_IO3_Msk     (0x1U << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
+#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4_Pos     (3U)                                          
+#define TSC_IOCCR_G1_IO4_Msk     (0x1U << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
+#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1_Pos     (4U)                                          
+#define TSC_IOCCR_G2_IO1_Msk     (0x1U << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
+#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2_Pos     (5U)                                          
+#define TSC_IOCCR_G2_IO2_Msk     (0x1U << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
+#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3_Pos     (6U)                                          
+#define TSC_IOCCR_G2_IO3_Msk     (0x1U << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
+#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4_Pos     (7U)                                          
+#define TSC_IOCCR_G2_IO4_Msk     (0x1U << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
+#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1_Pos     (8U)                                          
+#define TSC_IOCCR_G3_IO1_Msk     (0x1U << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
+#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2_Pos     (9U)                                          
+#define TSC_IOCCR_G3_IO2_Msk     (0x1U << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
+#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3_Pos     (10U)                                         
+#define TSC_IOCCR_G3_IO3_Msk     (0x1U << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
+#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4_Pos     (11U)                                         
+#define TSC_IOCCR_G3_IO4_Msk     (0x1U << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
+#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1_Pos     (12U)                                         
+#define TSC_IOCCR_G4_IO1_Msk     (0x1U << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
+#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2_Pos     (13U)                                         
+#define TSC_IOCCR_G4_IO2_Msk     (0x1U << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
+#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3_Pos     (14U)                                         
+#define TSC_IOCCR_G4_IO3_Msk     (0x1U << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
+#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4_Pos     (15U)                                         
+#define TSC_IOCCR_G4_IO4_Msk     (0x1U << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
+#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1_Pos     (16U)                                         
+#define TSC_IOCCR_G5_IO1_Msk     (0x1U << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
+#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2_Pos     (17U)                                         
+#define TSC_IOCCR_G5_IO2_Msk     (0x1U << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
+#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3_Pos     (18U)                                         
+#define TSC_IOCCR_G5_IO3_Msk     (0x1U << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
+#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4_Pos     (19U)                                         
+#define TSC_IOCCR_G5_IO4_Msk     (0x1U << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
+#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1_Pos     (20U)                                         
+#define TSC_IOCCR_G6_IO1_Msk     (0x1U << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
+#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2_Pos     (21U)                                         
+#define TSC_IOCCR_G6_IO2_Msk     (0x1U << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
+#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3_Pos     (22U)                                         
+#define TSC_IOCCR_G6_IO3_Msk     (0x1U << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
+#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4_Pos     (23U)                                         
+#define TSC_IOCCR_G6_IO4_Msk     (0x1U << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
+#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1_Pos     (24U)                                         
+#define TSC_IOCCR_G7_IO1_Msk     (0x1U << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
+#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2_Pos     (25U)                                         
+#define TSC_IOCCR_G7_IO2_Msk     (0x1U << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
+#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3_Pos     (26U)                                         
+#define TSC_IOCCR_G7_IO3_Msk     (0x1U << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
+#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4_Pos     (27U)                                         
+#define TSC_IOCCR_G7_IO4_Msk     (0x1U << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
+#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1_Pos     (28U)                                         
+#define TSC_IOCCR_G8_IO1_Msk     (0x1U << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
+#define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2_Pos     (29U)                                         
+#define TSC_IOCCR_G8_IO2_Msk     (0x1U << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
+#define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3_Pos     (30U)                                         
+#define TSC_IOCCR_G8_IO3_Msk     (0x1U << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
+#define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4_Pos     (31U)                                         
+#define TSC_IOCCR_G8_IO4_Msk     (0x1U << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
+#define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
+
+/*******************  Bit definition for TSC_IOGCSR register  *****************/
+#define TSC_IOGCSR_G1E_Pos       (0U)                                          
+#define TSC_IOGCSR_G1E_Msk       (0x1U << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
+#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E_Pos       (1U)                                          
+#define TSC_IOGCSR_G2E_Msk       (0x1U << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
+#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E_Pos       (2U)                                          
+#define TSC_IOGCSR_G3E_Msk       (0x1U << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
+#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E_Pos       (3U)                                          
+#define TSC_IOGCSR_G4E_Msk       (0x1U << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
+#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E_Pos       (4U)                                          
+#define TSC_IOGCSR_G5E_Msk       (0x1U << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
+#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E_Pos       (5U)                                          
+#define TSC_IOGCSR_G6E_Msk       (0x1U << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
+#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E_Pos       (6U)                                          
+#define TSC_IOGCSR_G7E_Msk       (0x1U << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
+#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E_Pos       (7U)                                          
+#define TSC_IOGCSR_G8E_Msk       (0x1U << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
+#define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S_Pos       (16U)                                         
+#define TSC_IOGCSR_G1S_Msk       (0x1U << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
+#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S_Pos       (17U)                                         
+#define TSC_IOGCSR_G2S_Msk       (0x1U << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
+#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S_Pos       (18U)                                         
+#define TSC_IOGCSR_G3S_Msk       (0x1U << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
+#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S_Pos       (19U)                                         
+#define TSC_IOGCSR_G4S_Msk       (0x1U << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
+#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S_Pos       (20U)                                         
+#define TSC_IOGCSR_G5S_Msk       (0x1U << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
+#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S_Pos       (21U)                                         
+#define TSC_IOGCSR_G6S_Msk       (0x1U << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
+#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S_Pos       (22U)                                         
+#define TSC_IOGCSR_G7S_Msk       (0x1U << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
+#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S_Pos       (23U)                                         
+#define TSC_IOGCSR_G8S_Msk       (0x1U << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
+#define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
+
+/*******************  Bit definition for TSC_IOGXCR register  *****************/
+#define TSC_IOGXCR_CNT_Pos       (0U)                                          
+#define TSC_IOGXCR_CNT_Msk       (0x3FFFU << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
+#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+*/
+#define USART_TCBGT_SUPPORT
+
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_UE_Pos              (0U)                                     
+#define USART_CR1_UE_Msk              (0x1U << USART_CR1_UE_Pos)               /*!< 0x00000001 */
+#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
+#define USART_CR1_UESM_Pos            (1U)                                     
+#define USART_CR1_UESM_Msk            (0x1U << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
+#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos              (2U)                                     
+#define USART_CR1_RE_Msk              (0x1U << USART_CR1_RE_Pos)               /*!< 0x00000004 */
+#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
+#define USART_CR1_TE_Pos              (3U)                                     
+#define USART_CR1_TE_Msk              (0x1U << USART_CR1_TE_Pos)               /*!< 0x00000008 */
+#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos          (4U)                                     
+#define USART_CR1_IDLEIE_Msk          (0x1U << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
+#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos          (5U)                                     
+#define USART_CR1_RXNEIE_Msk          (0x1U << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
+#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos            (6U)                                     
+#define USART_CR1_TCIE_Msk            (0x1U << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
+#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos           (7U)                                     
+#define USART_CR1_TXEIE_Msk           (0x1U << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
+#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos            (8U)                                     
+#define USART_CR1_PEIE_Msk            (0x1U << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
+#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos              (9U)                                     
+#define USART_CR1_PS_Msk              (0x1U << USART_CR1_PS_Pos)               /*!< 0x00000200 */
+#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
+#define USART_CR1_PCE_Pos             (10U)                                    
+#define USART_CR1_PCE_Msk             (0x1U << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
+#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos            (11U)                                    
+#define USART_CR1_WAKE_Msk            (0x1U << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
+#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos               (12U)                                    
+#define USART_CR1_M_Msk               (0x10001U << USART_CR1_M_Pos)            /*!< 0x10001000 */
+#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
+#define USART_CR1_M0_Pos              (12U)                                    
+#define USART_CR1_M0_Msk              (0x1U << USART_CR1_M0_Pos)               /*!< 0x00001000 */
+#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos             (13U)                                    
+#define USART_CR1_MME_Msk             (0x1U << USART_CR1_MME_Pos)              /*!< 0x00002000 */
+#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos            (14U)                                    
+#define USART_CR1_CMIE_Msk            (0x1U << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
+#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos           (15U)                                    
+#define USART_CR1_OVER8_Msk           (0x1U << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
+#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos            (16U)                                    
+#define USART_CR1_DEDT_Msk            (0x1FU << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
+#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0              (0x01U << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
+#define USART_CR1_DEDT_1              (0x02U << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
+#define USART_CR1_DEDT_2              (0x04U << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
+#define USART_CR1_DEDT_3              (0x08U << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
+#define USART_CR1_DEDT_4              (0x10U << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos            (21U)                                    
+#define USART_CR1_DEAT_Msk            (0x1FU << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
+#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0              (0x01U << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
+#define USART_CR1_DEAT_1              (0x02U << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
+#define USART_CR1_DEAT_2              (0x04U << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
+#define USART_CR1_DEAT_3              (0x08U << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
+#define USART_CR1_DEAT_4              (0x10U << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos           (26U)                                    
+#define USART_CR1_RTOIE_Msk           (0x1U << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
+#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos           (27U)                                    
+#define USART_CR1_EOBIE_Msk           (0x1U << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
+#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos              (28U)                                    
+#define USART_CR1_M1_Msk              (0x1U << USART_CR1_M1_Pos)               /*!< 0x10000000 */
+#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_ADDM7_Pos           (4U)                                     
+#define USART_CR2_ADDM7_Msk           (0x1U << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
+#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos            (5U)                                     
+#define USART_CR2_LBDL_Msk            (0x1U << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
+#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos           (6U)                                     
+#define USART_CR2_LBDIE_Msk           (0x1U << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
+#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos            (8U)                                     
+#define USART_CR2_LBCL_Msk            (0x1U << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
+#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos            (9U)                                     
+#define USART_CR2_CPHA_Msk            (0x1U << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
+#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos            (10U)                                    
+#define USART_CR2_CPOL_Msk            (0x1U << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
+#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos           (11U)                                    
+#define USART_CR2_CLKEN_Msk           (0x1U << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
+#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
+#define USART_CR2_STOP_Pos            (12U)                                    
+#define USART_CR2_STOP_Msk            (0x3U << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
+#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0              (0x1U << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
+#define USART_CR2_STOP_1              (0x2U << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos           (14U)                                    
+#define USART_CR2_LINEN_Msk           (0x1U << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
+#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos            (15U)                                    
+#define USART_CR2_SWAP_Msk            (0x1U << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
+#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos           (16U)                                    
+#define USART_CR2_RXINV_Msk           (0x1U << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
+#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos           (17U)                                    
+#define USART_CR2_TXINV_Msk           (0x1U << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
+#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos         (18U)                                    
+#define USART_CR2_DATAINV_Msk         (0x1U << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
+#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos        (19U)                                    
+#define USART_CR2_MSBFIRST_Msk        (0x1U << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos           (20U)                                    
+#define USART_CR2_ABREN_Msk           (0x1U << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
+#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos         (21U)                                    
+#define USART_CR2_ABRMODE_Msk         (0x3U << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
+#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0           (0x1U << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1           (0x2U << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos           (23U)                                    
+#define USART_CR2_RTOEN_Msk           (0x1U << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
+#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos             (24U)                                    
+#define USART_CR2_ADD_Msk             (0xFFU << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
+#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos             (0U)                                     
+#define USART_CR3_EIE_Msk             (0x1U << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
+#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos            (1U)                                     
+#define USART_CR3_IREN_Msk            (0x1U << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
+#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos            (2U)                                     
+#define USART_CR3_IRLP_Msk            (0x1U << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
+#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos           (3U)                                     
+#define USART_CR3_HDSEL_Msk           (0x1U << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
+#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos            (4U)                                     
+#define USART_CR3_NACK_Msk            (0x1U << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
+#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos            (5U)                                     
+#define USART_CR3_SCEN_Msk            (0x1U << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
+#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos            (6U)                                     
+#define USART_CR3_DMAR_Msk            (0x1U << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
+#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos            (7U)                                     
+#define USART_CR3_DMAT_Msk            (0x1U << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
+#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos            (8U)                                     
+#define USART_CR3_RTSE_Msk            (0x1U << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
+#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos            (9U)                                     
+#define USART_CR3_CTSE_Msk            (0x1U << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
+#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos           (10U)                                    
+#define USART_CR3_CTSIE_Msk           (0x1U << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
+#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos          (11U)                                    
+#define USART_CR3_ONEBIT_Msk          (0x1U << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
+#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos          (12U)                                    
+#define USART_CR3_OVRDIS_Msk          (0x1U << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
+#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos            (13U)                                    
+#define USART_CR3_DDRE_Msk            (0x1U << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
+#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos             (14U)                                    
+#define USART_CR3_DEM_Msk             (0x1U << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
+#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos             (15U)                                    
+#define USART_CR3_DEP_Msk             (0x1U << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
+#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos         (17U)                                    
+#define USART_CR3_SCARCNT_Msk         (0x7U << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0           (0x1U << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1           (0x2U << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2           (0x4U << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos             (20U)                                    
+#define USART_CR3_WUS_Msk             (0x3U << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
+#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0               (0x1U << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
+#define USART_CR3_WUS_1               (0x2U << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos           (22U)                                    
+#define USART_CR3_WUFIE_Msk           (0x1U << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
+#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
+#define USART_CR3_TCBGTIE_Pos         (24U)                                    
+#define USART_CR3_TCBGTIE_Msk         (0x1U << USART_CR3_TCBGTIE_Pos)          /*!< 0x01000000 */
+#define USART_CR3_TCBGTIE             USART_CR3_TCBGTIE_Msk                    /*!< Transmission Complete Before Guard Time Interrupt Enable */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_FRACTION_Pos    (0U)                                     
+#define USART_BRR_DIV_FRACTION_Msk    (0xFU << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos    (4U)                                     
+#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFU << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos            (0U)                                     
+#define USART_GTPR_PSC_Msk            (0xFFU << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
+#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos             (8U)                                     
+#define USART_GTPR_GT_Msk             (0xFFU << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
+#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define USART_RTOR_RTO_Pos            (0U)                                     
+#define USART_RTOR_RTO_Msk            (0xFFFFFFU << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos           (24U)                                    
+#define USART_RTOR_BLEN_Msk           (0xFFU << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
+#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define USART_RQR_ABRRQ_Pos           (0U)                                     
+#define USART_RQR_ABRRQ_Msk           (0x1U << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
+#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos           (1U)                                     
+#define USART_RQR_SBKRQ_Msk           (0x1U << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
+#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos            (2U)                                     
+#define USART_RQR_MMRQ_Msk            (0x1U << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
+#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos           (3U)                                     
+#define USART_RQR_RXFRQ_Msk           (0x1U << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
+#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos           (4U)                                     
+#define USART_RQR_TXFRQ_Msk           (0x1U << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
+#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define USART_ISR_PE_Pos              (0U)                                     
+#define USART_ISR_PE_Msk              (0x1U << USART_ISR_PE_Pos)               /*!< 0x00000001 */
+#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
+#define USART_ISR_FE_Pos              (1U)                                     
+#define USART_ISR_FE_Msk              (0x1U << USART_ISR_FE_Pos)               /*!< 0x00000002 */
+#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
+#define USART_ISR_NE_Pos              (2U)                                     
+#define USART_ISR_NE_Msk              (0x1U << USART_ISR_NE_Pos)               /*!< 0x00000004 */
+#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos             (3U)                                     
+#define USART_ISR_ORE_Msk             (0x1U << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
+#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos            (4U)                                     
+#define USART_ISR_IDLE_Msk            (0x1U << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
+#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos            (5U)                                     
+#define USART_ISR_RXNE_Msk            (0x1U << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
+#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos              (6U)                                     
+#define USART_ISR_TC_Msk              (0x1U << USART_ISR_TC_Pos)               /*!< 0x00000040 */
+#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos             (7U)                                     
+#define USART_ISR_TXE_Msk             (0x1U << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
+#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos            (8U)                                     
+#define USART_ISR_LBDF_Msk            (0x1U << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
+#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos           (9U)                                     
+#define USART_ISR_CTSIF_Msk           (0x1U << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
+#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos             (10U)                                    
+#define USART_ISR_CTS_Msk             (0x1U << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
+#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
+#define USART_ISR_RTOF_Pos            (11U)                                    
+#define USART_ISR_RTOF_Msk            (0x1U << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
+#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos            (12U)                                    
+#define USART_ISR_EOBF_Msk            (0x1U << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
+#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos            (14U)                                    
+#define USART_ISR_ABRE_Msk            (0x1U << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
+#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos            (15U)                                    
+#define USART_ISR_ABRF_Msk            (0x1U << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
+#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos            (16U)                                    
+#define USART_ISR_BUSY_Msk            (0x1U << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
+#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
+#define USART_ISR_CMF_Pos             (17U)                                    
+#define USART_ISR_CMF_Msk             (0x1U << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
+#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos            (18U)                                    
+#define USART_ISR_SBKF_Msk            (0x1U << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
+#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos             (19U)                                    
+#define USART_ISR_RWU_Msk             (0x1U << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
+#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos             (20U)                                    
+#define USART_ISR_WUF_Msk             (0x1U << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
+#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos           (21U)                                    
+#define USART_ISR_TEACK_Msk           (0x1U << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
+#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos           (22U)                                    
+#define USART_ISR_REACK_Msk           (0x1U << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
+#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_TCBGT_Pos           (25U)                                    
+#define USART_ISR_TCBGT_Msk           (0x1U << USART_ISR_TCBGT_Pos)            /*!< 0x02000000 */
+#define USART_ISR_TCBGT               USART_ISR_TCBGT_Msk                      /*!< Transmission Complete Before Guard Time Completion Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define USART_ICR_PECF_Pos            (0U)                                     
+#define USART_ICR_PECF_Msk            (0x1U << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
+#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos            (1U)                                     
+#define USART_ICR_FECF_Msk            (0x1U << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
+#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos             (2U)                                     
+#define USART_ICR_NCF_Msk             (0x1U << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
+#define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos           (3U)                                     
+#define USART_ICR_ORECF_Msk           (0x1U << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
+#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos          (4U)                                     
+#define USART_ICR_IDLECF_Msk          (0x1U << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
+#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos            (6U)                                     
+#define USART_ICR_TCCF_Msk            (0x1U << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
+#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
+#define USART_ICR_TCBGTCF_Pos         (7U)                                     
+#define USART_ICR_TCBGTCF_Msk         (0x1U << USART_ICR_TCBGTCF_Pos)          /*!< 0x00000080 */
+#define USART_ICR_TCBGTCF             USART_ICR_TCBGTCF_Msk                    /*!< Transmission Complete Before Guard Time Clear Flag */
+#define USART_ICR_LBDCF_Pos           (8U)                                     
+#define USART_ICR_LBDCF_Msk           (0x1U << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
+#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos           (9U)                                     
+#define USART_ICR_CTSCF_Msk           (0x1U << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
+#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos           (11U)                                    
+#define USART_ICR_RTOCF_Msk           (0x1U << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
+#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos           (12U)                                    
+#define USART_ICR_EOBCF_Msk           (0x1U << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
+#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos            (17U)                                    
+#define USART_ICR_CMCF_Msk            (0x1U << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
+#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos            (20U)                                    
+#define USART_ICR_WUCF_Msk            (0x1U << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
+#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define USART_RDR_RDR_Pos             (0U)                                     
+#define USART_RDR_RDR_Msk             (0x1FFU << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
+#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define USART_TDR_TDR_Pos             (0U)                                     
+#define USART_TDR_TDR_Msk             (0x1FFU << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
+#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*           Single Wire Protocol Master Interface (SWPMI)                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for SWPMI_CR register   ********************/
+#define SWPMI_CR_RXDMA_Pos       (0U)                                          
+#define SWPMI_CR_RXDMA_Msk       (0x1U << SWPMI_CR_RXDMA_Pos)                  /*!< 0x00000001 */
+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */
+#define SWPMI_CR_TXDMA_Pos       (1U)                                          
+#define SWPMI_CR_TXDMA_Msk       (0x1U << SWPMI_CR_TXDMA_Pos)                  /*!< 0x00000002 */
+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */
+#define SWPMI_CR_RXMODE_Pos      (2U)                                          
+#define SWPMI_CR_RXMODE_Msk      (0x1U << SWPMI_CR_RXMODE_Pos)                 /*!< 0x00000004 */
+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */
+#define SWPMI_CR_TXMODE_Pos      (3U)                                          
+#define SWPMI_CR_TXMODE_Msk      (0x1U << SWPMI_CR_TXMODE_Pos)                 /*!< 0x00000008 */
+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */
+#define SWPMI_CR_LPBK_Pos        (4U)                                          
+#define SWPMI_CR_LPBK_Msk        (0x1U << SWPMI_CR_LPBK_Pos)                   /*!< 0x00000010 */
+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */
+#define SWPMI_CR_SWPACT_Pos      (5U)                                          
+#define SWPMI_CR_SWPACT_Msk      (0x1U << SWPMI_CR_SWPACT_Pos)                 /*!< 0x00000020 */
+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */
+#define SWPMI_CR_DEACT_Pos       (10U)                                         
+#define SWPMI_CR_DEACT_Msk       (0x1U << SWPMI_CR_DEACT_Pos)                  /*!< 0x00000400 */
+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */
+
+/*******************  Bit definition for SWPMI_BRR register  ********************/
+#define SWPMI_BRR_BR_Pos         (0U)                                          
+#define SWPMI_BRR_BR_Msk         (0x3FU << SWPMI_BRR_BR_Pos)                   /*!< 0x0000003F */
+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[5:0] bits (Bitrate prescaler) */
+
+/*******************  Bit definition for SWPMI_ISR register  ********************/
+#define SWPMI_ISR_RXBFF_Pos      (0U)                                          
+#define SWPMI_ISR_RXBFF_Msk      (0x1U << SWPMI_ISR_RXBFF_Pos)                 /*!< 0x00000001 */
+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */
+#define SWPMI_ISR_TXBEF_Pos      (1U)                                          
+#define SWPMI_ISR_TXBEF_Msk      (0x1U << SWPMI_ISR_TXBEF_Pos)                 /*!< 0x00000002 */
+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */
+#define SWPMI_ISR_RXBERF_Pos     (2U)                                          
+#define SWPMI_ISR_RXBERF_Msk     (0x1U << SWPMI_ISR_RXBERF_Pos)                /*!< 0x00000004 */
+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */
+#define SWPMI_ISR_RXOVRF_Pos     (3U)                                          
+#define SWPMI_ISR_RXOVRF_Msk     (0x1U << SWPMI_ISR_RXOVRF_Pos)                /*!< 0x00000008 */
+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */
+#define SWPMI_ISR_TXUNRF_Pos     (4U)                                          
+#define SWPMI_ISR_TXUNRF_Msk     (0x1U << SWPMI_ISR_TXUNRF_Pos)                /*!< 0x00000010 */
+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */
+#define SWPMI_ISR_RXNE_Pos       (5U)                                          
+#define SWPMI_ISR_RXNE_Msk       (0x1U << SWPMI_ISR_RXNE_Pos)                  /*!< 0x00000020 */
+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */
+#define SWPMI_ISR_TXE_Pos        (6U)                                          
+#define SWPMI_ISR_TXE_Msk        (0x1U << SWPMI_ISR_TXE_Pos)                   /*!< 0x00000040 */
+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */
+#define SWPMI_ISR_TCF_Pos        (7U)                                          
+#define SWPMI_ISR_TCF_Msk        (0x1U << SWPMI_ISR_TCF_Pos)                   /*!< 0x00000080 */
+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */
+#define SWPMI_ISR_SRF_Pos        (8U)                                          
+#define SWPMI_ISR_SRF_Msk        (0x1U << SWPMI_ISR_SRF_Pos)                   /*!< 0x00000100 */
+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */
+#define SWPMI_ISR_SUSP_Pos       (9U)                                          
+#define SWPMI_ISR_SUSP_Msk       (0x1U << SWPMI_ISR_SUSP_Pos)                  /*!< 0x00000200 */
+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */
+#define SWPMI_ISR_DEACTF_Pos     (10U)                                         
+#define SWPMI_ISR_DEACTF_Msk     (0x1U << SWPMI_ISR_DEACTF_Pos)                /*!< 0x00000400 */
+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */
+
+/*******************  Bit definition for SWPMI_ICR register  ********************/
+#define SWPMI_ICR_CRXBFF_Pos     (0U)                                          
+#define SWPMI_ICR_CRXBFF_Msk     (0x1U << SWPMI_ICR_CRXBFF_Pos)                /*!< 0x00000001 */
+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */
+#define SWPMI_ICR_CTXBEF_Pos     (1U)                                          
+#define SWPMI_ICR_CTXBEF_Msk     (0x1U << SWPMI_ICR_CTXBEF_Pos)                /*!< 0x00000002 */
+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */
+#define SWPMI_ICR_CRXBERF_Pos    (2U)                                          
+#define SWPMI_ICR_CRXBERF_Msk    (0x1U << SWPMI_ICR_CRXBERF_Pos)               /*!< 0x00000004 */
+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */
+#define SWPMI_ICR_CRXOVRF_Pos    (3U)                                          
+#define SWPMI_ICR_CRXOVRF_Msk    (0x1U << SWPMI_ICR_CRXOVRF_Pos)               /*!< 0x00000008 */
+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */
+#define SWPMI_ICR_CTXUNRF_Pos    (4U)                                          
+#define SWPMI_ICR_CTXUNRF_Msk    (0x1U << SWPMI_ICR_CTXUNRF_Pos)               /*!< 0x00000010 */
+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */
+#define SWPMI_ICR_CTCF_Pos       (7U)                                          
+#define SWPMI_ICR_CTCF_Msk       (0x1U << SWPMI_ICR_CTCF_Pos)                  /*!< 0x00000080 */
+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */
+#define SWPMI_ICR_CSRF_Pos       (8U)                                          
+#define SWPMI_ICR_CSRF_Msk       (0x1U << SWPMI_ICR_CSRF_Pos)                  /*!< 0x00000100 */
+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */
+
+/*******************  Bit definition for SWPMI_IER register  ********************/
+#define SWPMI_IER_SRIE_Pos       (8U)                                          
+#define SWPMI_IER_SRIE_Msk       (0x1U << SWPMI_IER_SRIE_Pos)                  /*!< 0x00000100 */
+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */
+#define SWPMI_IER_TCIE_Pos       (7U)                                          
+#define SWPMI_IER_TCIE_Msk       (0x1U << SWPMI_IER_TCIE_Pos)                  /*!< 0x00000080 */
+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */
+#define SWPMI_IER_TIE_Pos        (6U)                                          
+#define SWPMI_IER_TIE_Msk        (0x1U << SWPMI_IER_TIE_Pos)                   /*!< 0x00000040 */
+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */
+#define SWPMI_IER_RIE_Pos        (5U)                                          
+#define SWPMI_IER_RIE_Msk        (0x1U << SWPMI_IER_RIE_Pos)                   /*!< 0x00000020 */
+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */
+#define SWPMI_IER_TXUNRIE_Pos    (4U)                                          
+#define SWPMI_IER_TXUNRIE_Msk    (0x1U << SWPMI_IER_TXUNRIE_Pos)               /*!< 0x00000010 */
+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */
+#define SWPMI_IER_RXOVRIE_Pos    (3U)                                          
+#define SWPMI_IER_RXOVRIE_Msk    (0x1U << SWPMI_IER_RXOVRIE_Pos)               /*!< 0x00000008 */
+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */
+#define SWPMI_IER_RXBERIE_Pos    (2U)                                          
+#define SWPMI_IER_RXBERIE_Msk    (0x1U << SWPMI_IER_RXBERIE_Pos)               /*!< 0x00000004 */
+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */
+#define SWPMI_IER_TXBEIE_Pos     (1U)                                          
+#define SWPMI_IER_TXBEIE_Msk     (0x1U << SWPMI_IER_TXBEIE_Pos)                /*!< 0x00000002 */
+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */
+#define SWPMI_IER_RXBFIE_Pos     (0U)                                          
+#define SWPMI_IER_RXBFIE_Msk     (0x1U << SWPMI_IER_RXBFIE_Pos)                /*!< 0x00000001 */
+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */
+
+/*******************  Bit definition for SWPMI_RFL register  ********************/
+#define SWPMI_RFL_RFL_Pos        (0U)                                          
+#define SWPMI_RFL_RFL_Msk        (0x1FU << SWPMI_RFL_RFL_Pos)                  /*!< 0x0000001F */
+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
+#define SWPMI_RFL_RFL_0_1_Pos    (0U)                                          
+#define SWPMI_RFL_RFL_0_1_Msk    (0x3U << SWPMI_RFL_RFL_0_1_Pos)               /*!< 0x00000003 */
+#define SWPMI_RFL_RFL_0_1        SWPMI_RFL_RFL_0_1_Msk                         /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+
+/*******************  Bit definition for SWPMI_TDR register  ********************/
+#define SWPMI_TDR_TD_Pos         (0U)                                          
+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFU << SWPMI_TDR_TD_Pos)             /*!< 0xFFFFFFFF */
+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */
+
+/*******************  Bit definition for SWPMI_RDR register  ********************/
+#define SWPMI_RDR_RD_Pos         (0U)                                          
+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFU << SWPMI_RDR_RD_Pos)             /*!< 0xFFFFFFFF */
+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Receive Data Register          */
+
+/*******************  Bit definition for SWPMI_OR register  ********************/
+#define SWPMI_OR_TBYP_Pos        (0U)                                          
+#define SWPMI_OR_TBYP_Msk        (0x1U << SWPMI_OR_TBYP_Pos)                   /*!< 0x00000001 */
+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */
+#define SWPMI_OR_CLASS_Pos       (1U)                                          
+#define SWPMI_OR_CLASS_Msk       (0x1U << SWPMI_OR_CLASS_Pos)                  /*!< 0x00000002 */
+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP Voltage Class selection */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 VREFBUF                                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for VREFBUF_CSR register  ****************/
+#define VREFBUF_CSR_ENVR_Pos    (0U)                                           
+#define VREFBUF_CSR_ENVR_Msk    (0x1U << VREFBUF_CSR_ENVR_Pos)                 /*!< 0x00000001 */
+#define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */
+#define VREFBUF_CSR_HIZ_Pos     (1U)                                           
+#define VREFBUF_CSR_HIZ_Msk     (0x1U << VREFBUF_CSR_HIZ_Pos)                  /*!< 0x00000002 */
+#define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */
+#define VREFBUF_CSR_VRS_Pos     (2U)                                           
+#define VREFBUF_CSR_VRS_Msk     (0x1U << VREFBUF_CSR_VRS_Pos)                  /*!< 0x00000004 */
+#define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<Voltage reference scale         */
+#define VREFBUF_CSR_VRR_Pos     (3U)                                           
+#define VREFBUF_CSR_VRR_Msk     (0x1U << VREFBUF_CSR_VRR_Pos)                  /*!< 0x00000008 */
+#define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference buffer ready  */
+
+/*******************  Bit definition for VREFBUF_CCR register  ******************/
+#define VREFBUF_CCR_TRIM_Pos    (0U)                                           
+#define VREFBUF_CCR_TRIM_Msk    (0x3FU << VREFBUF_CCR_TRIM_Pos)                /*!< 0x0000003F */
+#define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos           (0U)                                           
+#define WWDG_CR_T_Msk           (0x7FU << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
+#define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
+#define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
+#define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
+#define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
+#define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
+#define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
+
+#define WWDG_CR_WDGA_Pos        (7U)                                           
+#define WWDG_CR_WDGA_Msk        (0x1U << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos          (0U)                                           
+#define WWDG_CFR_W_Msk          (0x7FU << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
+#define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
+#define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
+#define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
+#define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
+#define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
+#define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
+
+#define WWDG_CFR_WDGTB_Pos      (7U)                                           
+#define WWDG_CFR_WDGTB_Msk      (0x3U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
+
+#define WWDG_CFR_EWI_Pos        (9U)                                           
+#define WWDG_CFR_EWI_Msk        (0x1U << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos        (0U)                                           
+#define WWDG_SR_EWIF_Msk        (0x1U << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)                            
+#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        
+#define DBGMCU_IDCODE_REV_ID_Pos               (16U)                           
+#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)                            
+#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         
+#define DBGMCU_CR_DBG_STOP_Pos                 (1U)                            
+#define DBGMCU_CR_DBG_STOP_Msk                 (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          
+#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)                            
+#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       
+#define DBGMCU_CR_TRACE_IOEN_Pos               (5U)                            
+#define DBGMCU_CR_TRACE_IOEN_Msk               (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk        
+
+#define DBGMCU_CR_TRACE_MODE_Pos               (6U)                            
+#define DBGMCU_CR_TRACE_MODE_Msk               (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE                   DBGMCU_CR_TRACE_MODE_Msk        
+#define DBGMCU_CR_TRACE_MODE_0                 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1                 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos      (0U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP          DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos      (1U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP          DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos      (2U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP          DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos      (3U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1FZR1_DBG_TIM5_STOP          DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos      (4U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP          DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos      (5U)                            
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP          DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos       (10U)                           
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk       (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1FZR1_DBG_RTC_STOP           DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos      (11U)                           
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP          DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos      (12U)                           
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP          DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos      (21U)                           
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP          DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos      (22U)                           
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP          DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos      (23U)                           
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP          DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos       (25U)                           
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk       (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1FZR1_DBG_CAN_STOP           DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_CAN2_STOP_Pos      (26U)                           
+#define DBGMCU_APB1FZR1_DBG_CAN2_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
+#define DBGMCU_APB1FZR1_DBG_CAN2_STOP          DBGMCU_APB1FZR1_DBG_CAN2_STOP_Msk 
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos    (31U)                           
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk    (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP        DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk 
+
+/********************  Bit definition for DBGMCU_APB1FZR2 register  **********/
+#define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos      (1U)                            
+#define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk      (0x1U << DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1FZR2_DBG_I2C4_STOP          DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk 
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos    (5U)                            
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk    (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP        DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk 
+
+/********************  Bit definition for DBGMCU_APB2FZ register  ************/
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos        (11U)                           
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk        (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB2FZ_DBG_TIM1_STOP            DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk 
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos        (13U)                           
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk        (0x1U << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */
+#define DBGMCU_APB2FZ_DBG_TIM8_STOP            DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk 
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos       (16U)                           
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2FZ_DBG_TIM15_STOP           DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk 
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos       (17U)                           
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2FZ_DBG_TIM16_STOP           DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk 
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos       (18U)                           
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2FZ_DBG_TIM17_STOP           DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk 
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)                          
+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)                          
+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)                          
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)                          
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)                          
+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)                          
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)                          
+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)                          
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)                         
+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!<  B-session valid*/
+
+/********************  Bit definition for USB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)                          
+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)                          
+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
+
+/********************  Bit definition for USB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                    (0U)                          
+#define USB_OTG_DCFG_DSPD_Msk                    (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                      (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                      (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)                          
+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
+#define USB_OTG_DCFG_DAD_Pos                     (4U)                          
+#define USB_OTG_DCFG_DAD_Msk                     (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                       (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                       (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                       (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                       (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                       (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                       (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                       (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)                         
+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                     (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                     (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)                         
+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for USB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)                          
+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)                          
+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)                          
+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
+
+/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)                          
+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)                          
+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)                          
+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)                         
+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)                         
+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)                         
+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done */
+
+/********************  Bit definition for USB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)                          
+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                    (1U)                          
+#define USB_OTG_DCTL_SDIS_Msk                    (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)                          
+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)                          
+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos                    (4U)                          
+#define USB_OTG_DCTL_TCTL_Msk                    (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                      (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                      (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                      (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)                          
+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)                          
+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)                          
+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)                         
+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)                         
+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+
+/********************  Bit definition for USB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)                          
+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
+
+/********************  Bit definition for USB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)                          
+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)                         
+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
+
+/********************  Bit definition for USB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)                          
+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)                          
+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                    (3U)                          
+#define USB_OTG_DSTS_EERR_Msk                    (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)                          
+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
+
+/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)                          
+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)                          
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)                          
+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)                          
+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)                          
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)                          
+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)                          
+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)                          
+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)                          
+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)                         
+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)                         
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)                         
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)                         
+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)                         
+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)                         
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)                         
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)                         
+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)                         
+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)                         
+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)                         
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)                         
+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)                         
+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)                         
+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet */
+
+/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)                          
+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)                          
+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)                          
+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)                          
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)                          
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)                          
+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)                         
+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)                         
+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
+
+/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)                          
+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)                          
+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)                          
+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)                          
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)                          
+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)                          
+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)                          
+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)                          
+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)                          
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)                         
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)                         
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for USB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                  (0U)                          
+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
+
+/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)                          
+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)                          
+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)                          
+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)                          
+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)                          
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)                          
+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)                          
+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask */
+
+/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)                          
+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)                          
+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)                          
+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)                          
+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)                          
+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)                          
+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)                          
+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)                          
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)                         
+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)                         
+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)                         
+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)                         
+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)                         
+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)                         
+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)                         
+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)                         
+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)                         
+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)                         
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)                         
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)                         
+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)                         
+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)                         
+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)                         
+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)                         
+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)                         
+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)                         
+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)                         
+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt */
+
+/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
+
+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)                          
+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)                          
+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)                          
+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)                          
+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)                          
+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)                          
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)                          
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)                         
+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)                         
+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)                         
+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)                         
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)                         
+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)                         
+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)                         
+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)                         
+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)                         
+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)                         
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)                         
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)                         
+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)                         
+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)                         
+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)                         
+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)                         
+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)                         
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)                         
+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)                         
+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)                         
+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask */
+
+/********************  Bit definition for USB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)                          
+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)                         
+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)                          
+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)                          
+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)                          
+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)                         
+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)                         
+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)                          
+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)                         
+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM_Pos                        (0U)                          
+#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)                          
+#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */                                                                             
+#define USB_OTG_DPID_Pos                         (15U)                         
+#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+#define USB_OTG_PKTSTS_Pos                       (17U)                         
+#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+#define USB_OTG_EPNUM_Pos                        (0U)                          
+#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_FRMNUM_Pos                       (21U)                         
+#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM_Pos                        (0U)                          
+#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)                          
+#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */                                                                         
+#define USB_OTG_DPID_Pos                         (15U)                         
+#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+#define USB_OTG_PKTSTS_Pos                       (17U)                         
+#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+#define USB_OTG_EPNUM_Pos                        (0U)                          
+#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_FRMNUM_Pos                       (21U)                         
+#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+
+/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)                          
+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)                          
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                      (0U)                          
+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                       (16U)                         
+#define USB_OTG_NPTXFD_Msk                       (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos                       (0U)                          
+#define USB_OTG_TX0FSA_Msk                       (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos                        (16U)                         
+#define USB_OTG_TX0FD_Msk                        (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)                          
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)                          
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)                         
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)                         
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DTHRCTL register  ***************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)                          
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)                          
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)                          
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)                         
+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)                         
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)                         
+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
+
+/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ***************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)                          
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)                          
+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)                         
+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition for USB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)                          
+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */
+#define USB_OTG_GCCFG_PDET_Pos                   (1U)                          
+#define USB_OTG_GCCFG_PDET_Msk                   (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */
+#define USB_OTG_GCCFG_SDET_Pos                   (2U)                          
+#define USB_OTG_GCCFG_SDET_Msk                   (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */
+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)                          
+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */
+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)                         
+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)                         
+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */
+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)                         
+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/
+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)                         
+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/
+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)                         
+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)                         
+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */
+
+/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
+#define USB_OTG_GPWRDN_DISABLEVBUS_Pos           (6U)                          
+#define USB_OTG_GPWRDN_DISABLEVBUS_Msk           (0x1U << USB_OTG_GPWRDN_DISABLEVBUS_Pos) /*!< 0x00000040 */
+#define USB_OTG_GPWRDN_DISABLEVBUS               USB_OTG_GPWRDN_DISABLEVBUS_Msk /*!< Power down */
+
+/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)                          
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)                         
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition for USB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)                          
+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
+
+
+/********************  Bit definition for USB_OTG_GHWCFG3 register  ********************/
+#define USB_OTG_GHWCFG3_LPMMode_Pos              (14U)                         
+#define USB_OTG_GHWCFG3_LPMMode_Msk              (0x1U << USB_OTG_GHWCFG3_LPMMode_Pos) /*!< 0x00004000 */
+#define USB_OTG_GHWCFG3_LPMMode                  USB_OTG_GHWCFG3_LPMMode_Msk   /* LPM mode specified for Mode of Operation */ 
+
+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)                         
+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /* Enable best effort service latency */ 
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)                         
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ 
+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)                         
+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /* Send LPM transaction */ 
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)                         
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /* LPM retry count */ 
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)                         
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /* LPMCHIDX: */ 
+#define USB_OTG_GLPMCFG_L1ResumeOK_Pos           (16U)                         
+#define USB_OTG_GLPMCFG_L1ResumeOK_Msk           (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1ResumeOK               USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ 
+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)                         
+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /* Port sleep status */ 
+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)                         
+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /* LPM response */ 
+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)                         
+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /* L1 deep sleep enable */ 
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)                          
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /* BESL threshold */ 
+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)                          
+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /* L1 shallow sleep enable */ 
+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)                          
+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /* bRemoteWake value received with last ACKed LPM Token */ 
+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)                          
+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /* BESL value received with last ACKed LPM Token  */
+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)                          
+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /* LPM Token acknowledge enable*/
+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)                          
+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /* LPM support enable  */
+
+
+/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)                          
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)                          
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)                          
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)                          
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)                          
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)                          
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)                          
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)                         
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)                          
+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos                   (1U)                          
+#define USB_OTG_HPRT_PCDET_Msk                   (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos                    (2U)                          
+#define USB_OTG_HPRT_PENA_Msk                    (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)                          
+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                    (4U)                          
+#define USB_OTG_HPRT_POCA_Msk                    (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)                          
+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos                    (6U)                          
+#define USB_OTG_HPRT_PRES_Msk                    (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)                          
+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos                    (8U)                          
+#define USB_OTG_HPRT_PRST_Msk                    (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)                         
+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                     (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                     (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                    (12U)                         
+#define USB_OTG_HPRT_PPWR_Msk                    (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)                         
+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                     (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                     (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                     (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                     (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                    (17U)                         
+#define USB_OTG_HPRT_PSPD_Msk                    (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                      (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                      (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)                          
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)                          
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)                          
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)                          
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)                          
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)                          
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)                          
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)                         
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)                         
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)                         
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)                          
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)                         
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)                          
+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)                         
+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)                         
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)                         
+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */
+                                                                             
+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)                         
+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)                         
+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */
+                                                                             
+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)                         
+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)                         
+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)                         
+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)                         
+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)                         
+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)                         
+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)                          
+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
+                                                                              
+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)                         
+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)                         
+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)                         
+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
+                                                                              
+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)                         
+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+                                                                              
+#define USB_OTG_HCCHAR_MC_Pos                    (20U)                         
+#define USB_OTG_HCCHAR_MC_Msk                    (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                      (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                      (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+                                                                              
+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)                         
+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                     (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                     (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                     (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                     (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                     (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                     (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                     (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)                         
+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)                         
+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)                         
+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
+
+/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)                          
+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+                                                                               
+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)                          
+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+                                                                               
+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)                         
+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)                         
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)                         
+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
+
+/********************  Bit definition for USB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                   (0U)                          
+#define USB_OTG_HCINT_XFRC_Msk                   (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                    (1U)                          
+#define USB_OTG_HCINT_CHH_Msk                    (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)                          
+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                  (3U)                          
+#define USB_OTG_HCINT_STALL_Msk                  (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                    (4U)                          
+#define USB_OTG_HCINT_NAK_Msk                    (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                    (5U)                          
+#define USB_OTG_HCINT_ACK_Msk                    (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                   (6U)                          
+#define USB_OTG_HCINT_NYET_Msk                   (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                  (7U)                          
+#define USB_OTG_HCINT_TXERR_Msk                  (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                  (8U)                          
+#define USB_OTG_HCINT_BBERR_Msk                  (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)                          
+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                  (10U)                         
+#define USB_OTG_HCINT_DTERR_Msk                  (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
+
+/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)                          
+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)                          
+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)                          
+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)                          
+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)                          
+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)                          
+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)                          
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)                          
+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)                         
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)                         
+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)                         
+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
+
+/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)                          
+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)                          
+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)                          
+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)                          
+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)                          
+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)                          
+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)                          
+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)                          
+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)                          
+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)                          
+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)                         
+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)                          
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)                         
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)                         
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
+/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)                          
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)                         
+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)                         
+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)                         
+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                    (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)                          
+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)                          
+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)                          
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space avail */
+
+/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)                          
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)                         
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)                          
+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)                         
+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)                         
+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)                         
+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)                         
+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)                         
+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)                         
+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)                         
+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)                         
+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)                         
+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)                         
+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)                          
+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)                          
+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)                          
+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)                          
+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)                          
+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)                         
+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
+
+/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)                          
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)                         
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)                         
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)                          
+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)                          
+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)                          
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+                                       ((INSTANCE) == ADC2) || \
+                                       ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
+
+/******************************** CAN Instances ******************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+                                       ((INSTANCE) == CAN2))
+
+/******************************** COMP Instances ******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+                                        ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+                                                ((INSTANCE) == DFSDM1_Filter1) || \
+                                                ((INSTANCE) == DFSDM1_Filter2) || \
+                                                ((INSTANCE) == DFSDM1_Filter3))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+                                                 ((INSTANCE) == DFSDM1_Channel1) || \
+                                                 ((INSTANCE) == DFSDM1_Channel2) || \
+                                                 ((INSTANCE) == DFSDM1_Channel3) || \
+                                                 ((INSTANCE) == DFSDM1_Channel4) || \
+                                                 ((INSTANCE) == DFSDM1_Channel5) || \
+                                                 ((INSTANCE) == DFSDM1_Channel6) || \
+                                                 ((INSTANCE) == DFSDM1_Channel7))
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+                                       ((INSTANCE) == DMA1_Channel2) || \
+                                       ((INSTANCE) == DMA1_Channel3) || \
+                                       ((INSTANCE) == DMA1_Channel4) || \
+                                       ((INSTANCE) == DMA1_Channel5) || \
+                                       ((INSTANCE) == DMA1_Channel6) || \
+                                       ((INSTANCE) == DMA1_Channel7) || \
+                                       ((INSTANCE) == DMA2_Channel1) || \
+                                       ((INSTANCE) == DMA2_Channel2) || \
+                                       ((INSTANCE) == DMA2_Channel3) || \
+                                       ((INSTANCE) == DMA2_Channel4) || \
+                                       ((INSTANCE) == DMA2_Channel5) || \
+                                       ((INSTANCE) == DMA2_Channel6) || \
+                                       ((INSTANCE) == DMA2_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOF) || \
+                                        ((INSTANCE) == GPIOG) || \
+                                        ((INSTANCE) == GPIOH) || \
+                                        ((INSTANCE) == GPIOI))
+
+/******************************* GPIO AF Instances ****************************/
+/* On L4, all GPIO Bank support AF */
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+/* On L4, all GPIO Bank support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2) || \
+                                       ((INSTANCE) == I2C3) || \
+                                       ((INSTANCE) == I2C4))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/******************************* LCD Instances ********************************/
+#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
+
+/******************************* HCD Instances *******************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
+                                         ((INSTANCE) == OPAMP2))
+
+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
+
+/******************************* PCD Instances *******************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+
+/******************************* QSPI Instances *******************************/
+#define IS_QSPI_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == QUADSPI)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+/******************************** SAI Instances *******************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
+                                       ((INSTANCE) == SAI1_Block_B) || \
+                                       ((INSTANCE) == SAI2_Block_A) || \
+                                       ((INSTANCE) == SAI2_Block_B))
+
+/****************************** SDMMC Instances *******************************/
+#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                         ((INSTANCE) == I2C2) || \
+                                         ((INSTANCE) == I2C3) || \
+                                         ((INSTANCE) == I2C4))
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                       ((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3))
+
+/******************************** SWPMI Instances *****************************/
+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
+                                         ((INSTANCE) == LPTIM2))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM6)   || \
+                                         ((INSTANCE) == TIM7)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
+                                               ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM8)    || \
+                                            ((INSTANCE) == TIM15)   || \
+                                            ((INSTANCE) == TIM16)   || \
+                                            ((INSTANCE) == TIM17))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                               ((INSTANCE) == TIM8)   || \
+                                               ((INSTANCE) == TIM15)  || \
+                                               ((INSTANCE) == TIM16)  || \
+                                               ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM8))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM6)   || \
+                                            ((INSTANCE) == TIM7)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM2) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM3) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM4) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM5) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+     ||                                        \
+     (((INSTANCE) == TIM8) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM15) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+     ||                                        \
+     (((INSTANCE) == TIM16) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+     ||                                        \
+     (((INSTANCE) == TIM17) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((((INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM8) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM15) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM16) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM17) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
+                                                    ((INSTANCE) == TIM2)    || \
+                                                    ((INSTANCE) == TIM3)    || \
+                                                    ((INSTANCE) == TIM4)    || \
+                                                    ((INSTANCE) == TIM5)    || \
+                                                    ((INSTANCE) == TIM8)    || \
+                                                    ((INSTANCE) == TIM15)   || \
+                                                    ((INSTANCE) == TIM16)   || \
+                                                    ((INSTANCE) == TIM17))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                     ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                     ((INSTANCE) == TIM8)   || \
+                                                     ((INSTANCE) == TIM15)  || \
+                                                     ((INSTANCE) == TIM16)  || \
+                                                     ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                                      ((INSTANCE) == TIM2)  || \
+                                                      ((INSTANCE) == TIM3)  || \
+                                                      ((INSTANCE) == TIM4)  || \
+                                                      ((INSTANCE) == TIM5)  || \
+                                                      ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                         ((INSTANCE) == TIM2)   || \
+                                                         ((INSTANCE) == TIM3)   || \
+                                                         ((INSTANCE) == TIM4)   || \
+                                                         ((INSTANCE) == TIM5))
+
+/**************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM5)  || \
+                                            ((INSTANCE) == TIM8))
+
+/************* TIM Instances : supporting ETR source selection ***************/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                             ((INSTANCE) == TIM2)  || \
+                                             ((INSTANCE) == TIM3)  || \
+                                             ((INSTANCE) == TIM8))
+      
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM5)  || \
+                                            ((INSTANCE) == TIM6)  || \
+                                            ((INSTANCE) == TIM7)  || \
+                                            ((INSTANCE) == TIM8)  || \
+                                            ((INSTANCE) == TIM15))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM5)  || \
+                                            ((INSTANCE) == TIM8)  || \
+                                            ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
+                                                       ((INSTANCE) == TIM2) || \
+                                                       ((INSTANCE) == TIM3) || \
+                                                       ((INSTANCE) == TIM4) || \
+                                                       ((INSTANCE) == TIM5) || \
+                                                       ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM8)  || \
+                                            ((INSTANCE) == TIM15) || \
+                                            ((INSTANCE) == TIM16) || \
+                                            ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                                       ((INSTANCE) == TIM8)  || \
+                                                       ((INSTANCE) == TIM15) || \
+                                                       ((INSTANCE) == TIM16) || \
+                                                       ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : Advanced timer instances *******************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
+                                                  ((INSTANCE) == TIM8))
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2) || \
+                                     ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5))
+
+/****************** UART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                            ((INSTANCE) == USART2) || \
+                                                            ((INSTANCE) == USART3) || \
+                                                            ((INSTANCE) == UART4)  || \
+                                                            ((INSTANCE) == UART5))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
+                                                      ((INSTANCE) == USART2) || \
+                                                      ((INSTANCE) == USART3) || \
+                                                      ((INSTANCE) == UART4)  || \
+                                                      ((INSTANCE) == UART5)  || \
+                                                      ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                 ((INSTANCE) == USART2) || \
+                                                 ((INSTANCE) == USART3) || \
+                                                 ((INSTANCE) == UART4)  || \
+                                                 ((INSTANCE) == UART5)  || \
+                                                 ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == USART3) || \
+                                           ((INSTANCE) == UART4)  || \
+                                           ((INSTANCE) == UART5)  || \
+                                           ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                          ((INSTANCE) == USART2) || \
+                                          ((INSTANCE) == USART3) || \
+                                          ((INSTANCE) == UART4)  || \
+                                          ((INSTANCE) == UART5))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                      ((INSTANCE) == USART2) || \
+                                                      ((INSTANCE) == USART3) || \
+                                                      ((INSTANCE) == UART4)  || \
+                                                      ((INSTANCE) == UART5)  || \
+                                                      ((INSTANCE) == LPUART1))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5))
+
+/********************* USART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
+
+/**
+  * @}
+  */
+
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32L4xx device product       */
+/*  lines, the aliases defined below are put in place to overcome the         */
+/*  differences in the interrupt handlers and IRQn definitions.               */
+/*  No need to update developed interrupt code when moving across             */ 
+/*  product lines within the same STM32L4 Family                              */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_IRQn                      ADC1_2_IRQn
+#define TIM1_TRG_COM_IRQn              TIM1_TRG_COM_TIM17_IRQn
+#define TIM8_IRQn                      TIM8_UP_IRQn
+#define HASH_RNG_IRQn                  RNG_IRQn
+#define HASH_CRS_IRQn                  CRS_IRQn
+#define DFSDM0_IRQn                    DFSDM1_FLT0_IRQn
+#define DFSDM1_IRQn                    DFSDM1_FLT1_IRQn
+#define DFSDM2_IRQn                    DFSDM1_FLT2_IRQn
+#define DFSDM3_IRQn                    DFSDM1_FLT3_IRQn
+
+/* Aliases for __IRQHandler */
+#define ADC1_IRQHandler                ADC1_2_IRQHandler
+#define TIM1_TRG_COM_IRQHandler        TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM8_IRQHandler                TIM8_UP_IRQHandler
+#define HASH_RNG_IRQHandler            RNG_IRQHandler
+#define HASH_CRS_IRQHandler            CRS_IRQHandler
+#define DFSDM0_IRQHandler              DFSDM1_FLT0_IRQHandler
+#define DFSDM1_IRQHandler              DFSDM1_FLT1_IRQHandler
+#define DFSDM2_IRQHandler              DFSDM1_FLT2_IRQHandler
+#define DFSDM3_IRQHandler              DFSDM1_FLT3_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L496xx_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l4xx.h
new file mode 100644
index 00000000000..879a1781866
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l4xx.h
@@ -0,0 +1,248 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx.h
+  * @author  MCD Application Team
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS STM32L4xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32L4xx device used in the target application
+  *              - To use or not the peripheral's drivers in application code(i.e.
+  *                code will be based on direct access to peripheral’s registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l4xx
+  * @{
+  */
+
+#ifndef __STM32L4xx_H
+#define __STM32L4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32L4)
+#define STM32L4
+#endif /* STM32L4 */
+
+/* Uncomment the line below according to the target STM32L4 device used in your
+   application
+  */
+
+#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
+    !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \
+    !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \
+    !defined (STM32L496xx) && !defined (STM32L4A6xx)
+  /* #define STM32L431xx */   /*!< STM32L431xx Devices */
+  /* #define STM32L432xx */   /*!< STM32L432xx Devices */
+  /* #define STM32L433xx */   /*!< STM32L433xx Devices */
+  /* #define STM32L442xx */   /*!< STM32L442xx Devices */
+  /* #define STM32L443xx */   /*!< STM32L443xx Devices */
+  /* #define STM32L451xx */   /*!< STM32L451xx Devices */
+  /* #define STM32L452xx */   /*!< STM32L452xx Devices */
+  /* #define STM32L462xx */   /*!< STM32L462xx Devices */
+  /* #define STM32L471xx */   /*!< STM32L471xx Devices */
+  /* #define STM32L475xx */   /*!< STM32L475xx Devices */
+  /* #define STM32L476xx */   /*!< STM32L476xx Devices */
+  /* #define STM32L485xx */   /*!< STM32L485xx Devices */
+  /* #define STM32L486xx */   /*!< STM32L486xx Devices */
+ #define STM32L496xx          /*!< STM32L496xx Devices */
+  /* #define STM32L4A6xx */   /*!< STM32L4A6xx Devices */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  #define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V1.3.1
+  */
+#define __STM32L4_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32L4_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
+#define __STM32L4_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32L4_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32L4_CMSIS_VERSION        ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
+                                       |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
+                                       |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\
+                                       |(__STM32L4_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32L431xx)
+  #include "stm32l431xx.h"
+#elif defined(STM32L432xx)
+  #include "stm32l432xx.h"
+#elif defined(STM32L433xx)
+  #include "stm32l433xx.h"
+#elif defined(STM32L442xx)
+  #include "stm32l442xx.h"
+#elif defined(STM32L443xx)
+  #include "stm32l443xx.h"
+#elif defined(STM32L451xx)
+  #include "stm32l451xx.h"
+#elif defined(STM32L452xx)
+  #include "stm32l452xx.h"
+#elif defined(STM32L462xx)
+  #include "stm32l462xx.h"
+#elif defined(STM32L471xx)
+  #include "stm32l471xx.h"
+#elif defined(STM32L475xx)
+  #include "stm32l475xx.h"
+#elif defined(STM32L476xx)
+  #include "stm32l476xx.h"
+#elif defined(STM32L485xx)
+  #include "stm32l485xx.h"
+#elif defined(STM32L486xx)
+  #include "stm32l486xx.h"
+#elif defined(STM32L496xx)
+  #include "stm32l496xx.h"
+#elif defined(STM32L4A6xx)
+  #include "stm32l4a6xx.h"
+#elif defined(STM32L4R5xx)
+  #include "stm32l4r5xx.h"
+#elif defined(STM32L4R9xx)
+  #include "stm32l4r9xx.h"
+#elif defined(STM32L4S5xx)
+  #include "stm32l4s5xx.h"
+#elif defined(STM32L4S9xx)
+  #include "stm32l4s9xx.h"
+#else
+ #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  ERROR = 0,
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32l4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L4xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_msp_template.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/system_stm32l4xx.h
similarity index 51%
rename from targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_msp_template.c
rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/system_stm32l4xx.h
index 833c42059ca..b2b77363aee 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_msp_template.c
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/system_stm32l4xx.h
@@ -1,16 +1,14 @@
 /**
   ******************************************************************************
-  * @file    stm32l4xx_hal_msp_template.c
+  * @file    system_stm32l4xx.h
   * @author  MCD Application Team
-  * @version V1.5.1
-  * @date    31-May-2016
-  * @brief   HAL MSP module.
-  *          This file template is located in the HAL folder and should be copied 
-  *          to the user folder.
+  * @version V1.3.1
+  * @date    21-April-2017
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -34,90 +32,96 @@
   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l4xx_hal.h"
+  ******************************************************************************
+  */
 
-/** @addtogroup STM32L4xx_HAL_Driver
+/** @addtogroup CMSIS
   * @{
   */
 
-/** @defgroup HAL_MSP HAL MSP module driver
-  * @brief HAL MSP module.
+/** @addtogroup stm32l4xx_system
   * @{
   */
 
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32L4XX_H
+#define __SYSTEM_STM32L4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
 
-/** @defgroup HAL_MSP_Private_Functions
+/** @addtogroup STM32L4xx_System_Includes
   * @{
   */
 
 /**
-  * @brief  Initialize the Global MSP.
-  * @param  None
-  * @retval None
-  */
-void HAL_MspInit(void)
-{
-  /* NOTE : This function is generated automatically by STM32CubeMX and eventually  
-            modified by the user
-   */ 
-}
+  * @}
+  */
 
-/**
-  * @brief  DeInitialize the Global MSP.
-  * @param  None  
-  * @retval None
-  */
-void HAL_MspDeInit(void)
-{
-  /* NOTE : This function is generated automatically by STM32CubeMX and eventually  
-            modified by the user
-   */
-}
+
+/** @addtogroup STM32L4xx_System_Exported_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;            /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */
+extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
+extern const uint32_t MSIRangeTable[12];    /*!< MSI ranges table values     */
 
 /**
-  * @brief  Initialize the PPP MSP.
-  * @param  None
-  * @retval None
-  */
-void HAL_PPP_MspInit(void)
-{
-  /* NOTE : This function is generated automatically by STM32CubeMX and eventually  
-            modified by the user
-   */ 
-}
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Exported_Constants
+  * @{
+  */
 
 /**
-  * @brief  DeInitialize the PPP MSP.
-  * @param  None  
-  * @retval None
-  */
-void HAL_PPP_MspDeInit(void)
-{
-  /* NOTE : This function is generated automatically by STM32CubeMX and eventually  
-            modified by the user
-   */
-}
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Exported_Macros
+  * @{
+  */
 
 /**
   * @}
   */
 
+/** @addtogroup STM32L4xx_System_Exported_Functions
+  * @{
+  */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
 /**
   * @}
   */
 
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32L4XX_H */
+
 /**
   * @}
   */
 
+/**
+  * @}
+  */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/objects.h
new file mode 100644
index 00000000000..ece5f1679fa
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/objects.h
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    IRQn_Type irq_n;
+    uint32_t irq_index;
+    uint32_t event;
+    PinName pin;
+};
+
+struct port_s {
+    PortName port;
+    uint32_t mask;
+    PinDirection direction;
+    __IO uint32_t *reg_in;
+    __IO uint32_t *reg_out;
+};
+
+struct trng_s {
+    RNG_HandleTypeDef handle;
+};
+
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32L4/analogout_device.c b/targets/TARGET_STM/TARGET_STM32L4/analogout_device.c
index bd5bafbd92b..92386ab594b 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/analogout_device.c
+++ b/targets/TARGET_STM/TARGET_STM32L4/analogout_device.c
@@ -75,6 +75,8 @@ void analogout_init(dac_t *obj, PinName pin) {
 
     // Configure DAC
     obj->handle.Instance = DAC;
+    obj->handle.State = HAL_DAC_STATE_RESET;
+
     if (HAL_DAC_Init(&obj->handle) != HAL_OK ) {
         error("HAL_DAC_Init failed");
     }
diff --git a/targets/TARGET_STM/TARGET_STM32L4/can_device.h b/targets/TARGET_STM/TARGET_STM32L4/can_device.h
index 3cb1c1b6c17..997a1b1087d 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/can_device.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/can_device.h
@@ -17,7 +17,7 @@
 #define MBED_CAN_DEVICE_H
 
 #include "cmsis.h"
-#include "stm32l4xx_hal.h"
+#include "stm32l4xx.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -25,7 +25,7 @@ extern "C" {
 
 #ifdef DEVICE_CAN
 
-#define CAN_NUM    1 // Number of CAN peripherals present in the STM32 serie
+#define CAN_NUM 1 // Number of CAN peripherals present in the STM32 serie
 
 #define CAN1_IRQ_RX_IRQN        CAN1_RX0_IRQn
 #define CAN1_IRQ_RX_VECT        CAN1_RX0_IRQHandler
diff --git a/targets/TARGET_STM/TARGET_STM32L4/common_objects.h b/targets/TARGET_STM/TARGET_STM32L4/common_objects.h
index e9e10f30696..9ee16729eab 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/common_objects.h
+++ b/targets/TARGET_STM/TARGET_STM32L4/common_objects.h
@@ -135,6 +135,14 @@ struct dac_s {
 }
 #endif
 
+#if DEVICE_CAN
+struct can_s {
+    CAN_HandleTypeDef CanHandle;
+    int index;
+    int hz;
+};
+#endif
+
 /* STM32L4 HAL doesn't provide this API called in rtc_api.c */
 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__)
 
diff --git a/targets/TARGET_STM/TARGET_STM32L4/flash_api.c b/targets/TARGET_STM/TARGET_STM32L4/flash_api.c
index 178d9b35955..4904e933178 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/flash_api.c
+++ b/targets/TARGET_STM/TARGET_STM32L4/flash_api.c
@@ -80,8 +80,6 @@ static uint32_t GetBank(uint32_t Addr)
  */
 int32_t flash_init(flash_t *obj)
 {
-    /* Unlock the Flash to enable the flash control register access *************/
-    HAL_FLASH_Unlock();
     return 0;
 }
 
@@ -92,12 +90,30 @@ int32_t flash_init(flash_t *obj)
  */
 int32_t flash_free(flash_t *obj)
 {
-    /* Lock the Flash to disable the flash control register access (recommended
-     * to protect the FLASH memory against possible unwanted operation) *********/
-    HAL_FLASH_Lock();
     return 0;
 }
 
+static int32_t flash_unlock(void)
+{
+    /* Allow Access to Flash control registers and user Falsh */
+    if (HAL_FLASH_Unlock()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
+static int32_t flash_lock(void)
+{
+    /* Disable the Flash option control register access (recommended to protect
+    the option Bytes against possible unwanted operations) */
+    if (HAL_FLASH_Lock()) {
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
 /** Erase one sector starting at defined address
  *
  * The address should be at sector boundary. This function does not do any check for address alignments
@@ -110,12 +126,17 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address)
     uint32_t FirstPage = 0, BankNumber = 0;
     uint32_t PAGEError = 0;
     FLASH_EraseInitTypeDef EraseInitStruct;
+    int32_t status = 0;
 
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
 
         return -1;
     }
 
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
       /* Clear OPTVERR bit set on virgin samples */
     __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
     /* Get the 1st page to erase */
@@ -135,10 +156,12 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address)
      DCRST and ICRST bits in the FLASH_CR register. */
 
     if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK) {
-        return -1;
-    } else {
-        return 0;
+        status = -1;
     }
+
+    flash_lock();
+
+    return status;
 }
 
 /** Program one page starting at defined address
@@ -156,6 +179,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address,
         const uint8_t *data, uint32_t size)
 {
     uint32_t StartAddress = 0;
+    int32_t status = 0;
 
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
         return -1;
@@ -166,6 +190,10 @@ int32_t flash_program_page(flash_t *obj, uint32_t address,
         return -1;
     }
 
+    if (flash_unlock() != HAL_OK) {
+        return -1;
+    }
+
     /* Program the user Flash area word by word */
     StartAddress = address;
 
@@ -173,34 +201,39 @@ int32_t flash_program_page(flash_t *obj, uint32_t address,
      *  parameters doesn't ensure  */
     if ((uint32_t) data % 4 != 0) {
         volatile uint64_t data64;
-        while (address < (StartAddress + size)) {
+        while ((address < (StartAddress + size)) && (status == 0)) {
             for (uint8_t i =0; i < 8; i++) {
                 *(((uint8_t *) &data64) + i) = *(data + i);
             }
 
-            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, address, data64) == HAL_OK) {
+            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, address, data64)
+                    == HAL_OK) {
                 address = address + 8;
                 data = data + 8;
             } else {
-                return -1;
+                status = -1;
             }
         }
     } else { /*  case where data is aligned, so let's avoid any copy */
-        while (address < (StartAddress + size)) {
-            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, address, *((uint64_t*) data)) == HAL_OK) {
+        while ((address < (StartAddress + size)) && (status == 0)) {
+            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, address,
+                        *((uint64_t*) data))
+                    == HAL_OK) {
                 address = address + 8;
                 data = data + 8;
             } else {
-                return -1;
+                status = -1;
             }
         }
     }
 
-    return 0;
+    flash_lock();
+
+    return status;
 }
 
 /** Get sector size
- * 
+ *
  * @param obj The flash object
  * @param address The sector starting address
  * @return The size of a sector
diff --git a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c
index cb3354530af..9e33644a7df 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c
+++ b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c
@@ -230,7 +230,7 @@ static void uart_irq(int id)
         }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
             if (__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) {
-                volatile uint32_t tmpval = huart->Instance->RDR; // Clear ORE flag
+                volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear ORE flag
             }
         }
     }
@@ -659,13 +659,13 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
 
 void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
     if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) {
-        volatile uint32_t tmpval = huart->Instance->RDR; // Clear PE flag
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear PE flag
     } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) {
-        volatile uint32_t tmpval = huart->Instance->RDR; // Clear FE flag
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear FE flag
     } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_NE) != RESET) {
-        volatile uint32_t tmpval = huart->Instance->RDR; // Clear NE flag
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear NE flag
     } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) {
-        volatile uint32_t tmpval = huart->Instance->RDR; // Clear ORE flag
+        volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear ORE flag
     }
 }
 
@@ -716,9 +716,9 @@ int serial_irq_handler_asynch(serial_t *obj)
     HAL_UART_IRQHandler(huart);
     
     // Abort if an error occurs
-    if (return_event & SERIAL_EVENT_RX_PARITY_ERROR ||
-            return_event & SERIAL_EVENT_RX_FRAMING_ERROR ||
-            return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
+    if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) ||
+        (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) ||
+        (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) {
         return return_event;
     }
     
@@ -792,7 +792,7 @@ void serial_rx_abort_asynch(serial_t *obj)
     
     // clear flags
     __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE);
-    volatile uint32_t tmpval = huart->Instance->RDR; // Clear errors flag
+    volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear errors flag
     
     // reset states
     huart->RxXferCount = 0;
diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c
index cd3c9b88889..bd2d7342472 100644
--- a/targets/TARGET_STM/can_api.c
+++ b/targets/TARGET_STM/can_api.c
@@ -25,10 +25,21 @@
 #include <math.h>
 #include <string.h>
 
-static CAN_HandleTypeDef CanHandle;
 static uint32_t can_irq_ids[CAN_NUM] = {0};
 static can_irq_handler irq_handler;
 
+static void can_registers_init(can_t *obj)
+{
+    if (HAL_CAN_Init(&obj->CanHandle) != HAL_OK) {
+        error("Cannot initialize CAN");
+    }
+
+    // Set initial CAN frequency to specified frequency
+    if (can_frequency(obj, obj->hz) != 1) {
+        error("Can frequency could not be set\n");
+    }
+}
+
 void can_init(can_t *obj, PinName rd, PinName td)
 {
     can_init_freq(obj, rd, td, 100000);
@@ -38,20 +49,26 @@ void can_init_freq (can_t *obj, PinName rd, PinName td, int hz)
 {
     CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
     CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
+    CANName can = (CANName)pinmap_merge(can_rd, can_td);
 
-    obj->can = (CANName)pinmap_merge(can_rd, can_td);
-    MBED_ASSERT((int)obj->can != NC);
+    MBED_ASSERT((int)can != NC);
 
-    if (obj->can == CAN_1) {
+    if (can == CAN_1) {
         __HAL_RCC_CAN1_CLK_ENABLE();
         obj->index = 0;
     }
-#if defined(CAN2_BASE) && (CAN_NUM == 2)
-    else if (obj->can == CAN_2) {
+#if defined(CAN2_BASE) && defined(CAN_2)
+    else if (can == CAN_2) {
         __HAL_RCC_CAN1_CLK_ENABLE(); // needed to set filters
         __HAL_RCC_CAN2_CLK_ENABLE();
         obj->index = 1;
     }
+#endif
+#if defined(CAN3_BASE) && defined(CAN_3)
+    else if (can == CAN_3) {
+        __HAL_RCC_CAN3_CLK_ENABLE();
+        obj->index = 2;
+    }
 #endif
     else {
         return;
@@ -67,33 +84,30 @@ void can_init_freq (can_t *obj, PinName rd, PinName td, int hz)
         pin_mode(td, PullUp);
     }
 
-    CanHandle.Instance = (CAN_TypeDef *)(obj->can);
+    /*  Use default values for rist init */
+    obj->CanHandle.Instance = (CAN_TypeDef *)can;
+    obj->CanHandle.Init.TTCM = DISABLE;
+    obj->CanHandle.Init.ABOM = DISABLE;
+    obj->CanHandle.Init.AWUM = DISABLE;
+    obj->CanHandle.Init.NART = DISABLE;
+    obj->CanHandle.Init.RFLM = DISABLE;
+    obj->CanHandle.Init.TXFP = DISABLE;
+    obj->CanHandle.Init.Mode = CAN_MODE_NORMAL;
+    obj->CanHandle.Init.SJW = CAN_SJW_1TQ;
+    obj->CanHandle.Init.BS1 = CAN_BS1_6TQ;
+    obj->CanHandle.Init.BS2 = CAN_BS2_8TQ;
+    obj->CanHandle.Init.Prescaler = 2;
 
-    CanHandle.Init.TTCM = DISABLE;
-    CanHandle.Init.ABOM = DISABLE;
-    CanHandle.Init.AWUM = DISABLE;
-    CanHandle.Init.NART = DISABLE;
-    CanHandle.Init.RFLM = DISABLE;
-    CanHandle.Init.TXFP = DISABLE;
-    CanHandle.Init.Mode = CAN_MODE_NORMAL;
-    CanHandle.Init.SJW = CAN_SJW_1TQ;
-    CanHandle.Init.BS1 = CAN_BS1_6TQ;
-    CanHandle.Init.BS2 = CAN_BS2_8TQ;
-    CanHandle.Init.Prescaler = 2;
+    /*  Store frequency to be restored in case of reset */
+    obj->hz = hz;
 
-    if (HAL_CAN_Init(&CanHandle) != HAL_OK) {
-        error("Cannot initialize CAN");
-    }
+    can_registers_init(obj);
 
-    // Set initial CAN frequency to specified frequency
-    if (can_frequency(obj, hz) != 1) {
-        error("Can frequency could not be set\n");
-    }
-
-    uint32_t filter_number = (obj->can == CAN_1) ? 0 : 14;
+    uint32_t filter_number = (can == CAN_1) ? 0 : 14;
     can_filter(obj, 0, 0, CANStandard, filter_number);
 }
 
+
 void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id)
 {
     irq_handler = handler;
@@ -102,7 +116,7 @@ void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id)
 
 void can_irq_free(can_t *obj)
 {
-    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+    CAN_TypeDef *can = obj->CanHandle.Instance;
 
     can->IER &= ~(CAN_IT_FMP0 | CAN_IT_FMP1 | CAN_IT_TME | \
                   CAN_IT_ERR | CAN_IT_EPV | CAN_IT_BOF);
@@ -111,19 +125,27 @@ void can_irq_free(can_t *obj)
 
 void can_free(can_t *obj)
 {
+    CANName can = (CANName) obj->CanHandle.Instance;
     // Reset CAN and disable clock
-    if (obj->can == CAN_1) {
+    if (can == CAN_1) {
         __HAL_RCC_CAN1_FORCE_RESET();
         __HAL_RCC_CAN1_RELEASE_RESET();
         __HAL_RCC_CAN1_CLK_DISABLE();
     }
-#if defined(CAN2_BASE) && (CAN_NUM == 2)
-    if (obj->can == CAN_2) {
+#if defined(CAN2_BASE) && defined(CAN_2)
+    if (can == CAN_2) {
         __HAL_RCC_CAN2_FORCE_RESET();
         __HAL_RCC_CAN2_RELEASE_RESET();
         __HAL_RCC_CAN2_CLK_DISABLE();
     }
 #endif
+#if defined(CAN3_BASE) && defined(CAN_3)
+    if (can == CAN_3) {
+        __HAL_RCC_CAN3_FORCE_RESET();
+        __HAL_RCC_CAN3_RELEASE_RESET();
+        __HAL_RCC_CAN3_CLK_DISABLE();
+    }
+#endif
 }
 
 // The following table is used to program bit_timing. It is an adjustment of the sample
@@ -196,7 +218,7 @@ int can_frequency(can_t *obj, int f)
 {
     int pclk = HAL_RCC_GetPCLK1Freq();
     int btr = can_speed(pclk, (unsigned int)f, 1);
-    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+    CAN_TypeDef *can = obj->CanHandle.Instance;
     uint32_t tickstart = 0;
     int status = 1;
 
@@ -211,7 +233,11 @@ int can_frequency(can_t *obj, int f)
             }
         }
         if (status != 0) {
-            can->BTR = btr;
+            /*  Do not erase all BTR registers (e.g. silent mode), only the
+             *  ones calculated in can_speed */
+            can->BTR &= ~(CAN_BTR_TS2 | CAN_BTR_TS1 | CAN_BTR_SJW | CAN_BTR_BRP);
+            can->BTR |= btr;
+
             can->MCR &= ~(uint32_t)CAN_MCR_INRQ;
             /* Get tick */
             tickstart = HAL_GetTick();
@@ -236,7 +262,7 @@ int can_frequency(can_t *obj, int f)
 int can_write(can_t *obj, CAN_Message msg, int cc)
 {
     uint32_t  transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
-    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+    CAN_TypeDef *can = obj->CanHandle.Instance;
 
     /* Select one empty transmit mailbox */
     if ((can->TSR & CAN_TSR_TME0) == CAN_TSR_TME0) {
@@ -279,7 +305,7 @@ int can_read(can_t *obj, CAN_Message *msg, int handle)
 {
     //handle is the FIFO number
 
-    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+    CAN_TypeDef *can = obj->CanHandle.Instance;
 
     // check FPM0 which holds the pending message count in FIFO 0
     // if no message is pending, return 0
@@ -324,46 +350,61 @@ int can_read(can_t *obj, CAN_Message *msg, int handle)
 
 void can_reset(can_t *obj)
 {
-    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+    CAN_TypeDef *can = obj->CanHandle.Instance;
+
+    /* Reset IP and delete errors */
     can->MCR |= CAN_MCR_RESET;
     can->ESR = 0x0;
+
+    /* restore registers state as saved in obj context */
+    can_registers_init(obj);
 }
 
 unsigned char can_rderror(can_t *obj)
 {
-    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+    CAN_TypeDef *can = obj->CanHandle.Instance;
     return (can->ESR >> 24) & 0xFF;
 }
 
 unsigned char can_tderror(can_t *obj)
 {
-    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+    CAN_TypeDef *can = obj->CanHandle.Instance;
     return (can->ESR >> 16) & 0xFF;
 }
 
 void can_monitor(can_t *obj, int silent)
 {
-    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
-
-    can->MCR |= CAN_MCR_INRQ ;
-    while ((can->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) {
-    }
-
-    if (silent) {
-        can->BTR |= ((uint32_t)1 << 31);
+    CanMode mode = MODE_NORMAL;
+    /*  Update current state w/ or w/o silent */
+    if(silent) {
+        switch (obj->CanHandle.Init.Mode) {
+            case CAN_MODE_LOOPBACK:
+            case CAN_MODE_SILENT_LOOPBACK:
+                mode = MODE_TEST_SILENT;
+                break;
+            default:
+                mode = MODE_SILENT;
+                break;
+        }
     } else {
-        can->BTR &= ~((uint32_t)1 << 31);
+        switch (obj->CanHandle.Init.Mode) {
+            case CAN_MODE_LOOPBACK:
+            case CAN_MODE_SILENT_LOOPBACK:
+                mode = MODE_TEST_LOCAL;
+                break;
+            default:
+                mode = MODE_NORMAL;
+                break;
+        }
     }
 
-    can->MCR &= ~(uint32_t)CAN_MCR_INRQ;
-    while ((can->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) {
-    }
+    can_mode(obj, mode);
 }
 
 int can_mode(can_t *obj, CanMode mode)
 {
     int success = 0;
-    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+    CAN_TypeDef *can = obj->CanHandle.Instance;
 
     can->MCR |= CAN_MCR_INRQ ;
     while ((can->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) {
@@ -371,21 +412,25 @@ int can_mode(can_t *obj, CanMode mode)
 
     switch (mode) {
         case MODE_NORMAL:
+            obj->CanHandle.Init.Mode = CAN_MODE_NORMAL;
             can->BTR &= ~(CAN_BTR_SILM | CAN_BTR_LBKM);
             success = 1;
             break;
         case MODE_SILENT:
+            obj->CanHandle.Init.Mode = CAN_MODE_SILENT;
             can->BTR |= CAN_BTR_SILM;
             can->BTR &= ~CAN_BTR_LBKM;
             success = 1;
             break;
         case MODE_TEST_GLOBAL:
         case MODE_TEST_LOCAL:
+            obj->CanHandle.Init.Mode = CAN_MODE_LOOPBACK;
             can->BTR |= CAN_BTR_LBKM;
             can->BTR &= ~CAN_BTR_SILM;
             success = 1;
             break;
         case MODE_TEST_SILENT:
+            obj->CanHandle.Init.Mode = CAN_MODE_SILENT_LOOPBACK;
             can->BTR |= (CAN_BTR_SILM | CAN_BTR_LBKM);
             success = 1;
             break;
@@ -407,7 +452,6 @@ int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t
 
     // filter for CANAny format cannot be configured for STM32
     if ((format == CANStandard) || (format == CANExtended)) {
-        CanHandle.Instance = (CAN_TypeDef *)(obj->can);
         CAN_FilterConfTypeDef  sFilterConfig;
         sFilterConfig.FilterNumber = handle;
         sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK;
@@ -429,7 +473,7 @@ int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t
         sFilterConfig.FilterActivation = ENABLE;
         sFilterConfig.BankNumber = 14 + handle;
 
-        HAL_CAN_ConfigFilter(&CanHandle, &sFilterConfig);
+        HAL_CAN_ConfigFilter(&obj->CanHandle, &sFilterConfig);
         retval = handle;
     }
     return retval;
@@ -438,6 +482,7 @@ int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t
 static void can_irq(CANName name, int id)
 {
     uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
+    CAN_HandleTypeDef CanHandle;
     CanHandle.Instance = (CAN_TypeDef *)name;
 
     if (__HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_TME)) {
@@ -517,7 +562,7 @@ void CAN1_SCE_IRQHandler(void)
 {
     can_irq(CAN_1, 0);
 }
-#if defined(CAN2_BASE) && (CAN_NUM == 2)
+#if defined(CAN2_BASE) && defined(CAN_2)
 void CAN2_RX0_IRQHandler(void)
 {
     can_irq(CAN_2, 1);
@@ -530,18 +575,31 @@ void CAN2_SCE_IRQHandler(void)
 {
     can_irq(CAN_2, 1);
 }
-#endif // defined(CAN2_BASE) && (CAN_NUM == 2)
+#endif
+#if defined(CAN3_BASE) && defined(CAN_3)
+void CAN3_RX0_IRQHandler(void)
+{
+    can_irq(CAN_3, 1);
+}
+void CAN3_TX_IRQHandler(void)
+{
+    can_irq(CAN_3, 1);
+}
+void CAN3_SCE_IRQHandler(void)
+{
+    can_irq(CAN_3, 1);
+}
+#endif
 #endif // else
 
 void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable)
 {
-
-    CAN_TypeDef *can = (CAN_TypeDef *)(obj->can);
+    CAN_TypeDef *can = obj->CanHandle.Instance;
     IRQn_Type irq_n = (IRQn_Type)0;
     uint32_t vector = 0;
     uint32_t ier;
 
-    if (obj->can == CAN_1) {
+    if ((CANName) can == CAN_1) {
         switch (type) {
             case IRQ_RX:
                 ier = CAN_IT_FMP0;
@@ -572,8 +630,8 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable)
                 return;
         }
     }
-#if defined(CAN2_BASE) && (CAN_NUM == 2)
-    else if (obj->can == CAN_2) {
+#if defined(CAN2_BASE) && defined(CAN_2)
+    else if ((CANName) can == CAN_2) {
         switch (type) {
             case IRQ_RX:
                 ier = CAN_IT_FMP0;
@@ -604,6 +662,39 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable)
                 return;
         }
     }
+#endif
+#if defined(CAN3_BASE) && defined(CAN_3)
+    else if ((CANName) can == CAN_3) {
+        switch (type) {
+            case IRQ_RX:
+                ier = CAN_IT_FMP0;
+                irq_n = CAN3_IRQ_RX_IRQN;
+                vector = (uint32_t)&CAN3_IRQ_RX_VECT;
+                break;
+            case IRQ_TX:
+                ier = CAN_IT_TME;
+                irq_n = CAN3_IRQ_TX_IRQN;
+                vector = (uint32_t)&CAN3_IRQ_TX_VECT;
+                break;
+            case IRQ_ERROR:
+                ier = CAN_IT_ERR;
+                irq_n = CAN3_IRQ_ERROR_IRQN;
+                vector = (uint32_t)&CAN3_IRQ_ERROR_VECT;
+                break;
+            case IRQ_PASSIVE:
+                ier = CAN_IT_EPV;
+                irq_n = CAN3_IRQ_PASSIVE_IRQN;
+                vector = (uint32_t)&CAN3_IRQ_PASSIVE_VECT;
+                break;
+            case IRQ_BUS:
+                ier = CAN_IT_BOF;
+                irq_n = CAN3_IRQ_BUS_IRQN;
+                vector = (uint32_t)&CAN3_IRQ_BUS_VECT;
+                break;
+            default:
+                return;
+        }
+    }
 #endif
     else {
         return;
diff --git a/targets/TARGET_STM/hal_tick_16b.c b/targets/TARGET_STM/hal_tick_16b.c
index 23263d5a958..f8e39f58a0d 100644
--- a/targets/TARGET_STM/hal_tick_16b.c
+++ b/targets/TARGET_STM/hal_tick_16b.c
@@ -148,12 +148,11 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
     // Enable timer
     HAL_TIM_Base_Start(&TimMasterHandle);
 
-#ifndef NDEBUG
-#ifdef TIM_MST_DBGMCU_FREEZE
     // Freeze timer on stop/breakpoint
+    // Define the FREEZE_TIMER_ON_DEBUG macro in mbed_app.json for example
+#if !defined(NDEBUG) && defined(FREEZE_TIMER_ON_DEBUG) && defined(TIM_MST_DBGMCU_FREEZE)
     TIM_MST_DBGMCU_FREEZE;
 #endif
-#endif
 
 #if DEBUG_TICK > 0
     __HAL_RCC_GPIOB_CLK_ENABLE();
diff --git a/targets/TARGET_STM/hal_tick_32b.c b/targets/TARGET_STM/hal_tick_32b.c
index 924df8b692e..7e84f34418e 100644
--- a/targets/TARGET_STM/hal_tick_32b.c
+++ b/targets/TARGET_STM/hal_tick_32b.c
@@ -118,12 +118,11 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
     __HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
     __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
 
-#ifndef NDEBUG
-#ifdef TIM_MST_DBGMCU_FREEZE
     // Freeze timer on stop/breakpoint
+    // Define the FREEZE_TIMER_ON_DEBUG macro in mbed_app.json for example
+#if !defined(NDEBUG) && defined(FREEZE_TIMER_ON_DEBUG) && defined(TIM_MST_DBGMCU_FREEZE)
     TIM_MST_DBGMCU_FREEZE;
 #endif
-#endif
 
 #if DEBUG_TICK > 0
     __HAL_RCC_GPIOB_CLK_ENABLE();
diff --git a/targets/TARGET_STM/i2c_api.c b/targets/TARGET_STM/i2c_api.c
index dd95931a462..5062d3c8970 100644
--- a/targets/TARGET_STM/i2c_api.c
+++ b/targets/TARGET_STM/i2c_api.c
@@ -743,8 +743,10 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
     int count = I2C_ERROR_BUS_BUSY, ret = 0;
     uint32_t timeout = 0;
 
-    if ((obj_s->XferOperation == I2C_FIRST_AND_LAST_FRAME) ||
-        (obj_s->XferOperation == I2C_LAST_FRAME)) {
+    // Trick to remove compiler warning "left and right operands are identical" in some cases
+    uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
+    uint32_t op2 = I2C_LAST_FRAME;
+    if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
         if (stop)
             obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
         else
@@ -795,8 +797,10 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
     int count = I2C_ERROR_BUS_BUSY, ret = 0;
     uint32_t timeout = 0;
 
-    if ((obj_s->XferOperation == I2C_FIRST_AND_LAST_FRAME) ||
-        (obj_s->XferOperation == I2C_LAST_FRAME)) {
+    // Trick to remove compiler warning "left and right operands are identical" in some cases
+    uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
+    uint32_t op2 = I2C_LAST_FRAME;
+    if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
         if (stop)
             obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
         else
@@ -1083,8 +1087,10 @@ void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx,
 
     /* Set operation step depending if stop sending required or not */
     if ((tx_length && !rx_length) || (!tx_length && rx_length)) {
-        if ((obj_s->XferOperation == I2C_FIRST_AND_LAST_FRAME) ||
-            (obj_s->XferOperation == I2C_LAST_FRAME)) {
+        // Trick to remove compiler warning "left and right operands are identical" in some cases
+        uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
+        uint32_t op2 = I2C_LAST_FRAME;
+        if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
             if (stop)
                 obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME;
             else
@@ -1106,8 +1112,10 @@ void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx,
     }
     else if (tx_length && rx_length) {
         /* Two steps operation, don't modify XferOperation, keep it for next step */
-        if ((obj_s->XferOperation == I2C_FIRST_AND_LAST_FRAME) ||
-            (obj_s->XferOperation == I2C_LAST_FRAME)) {
+        // Trick to remove compiler warning "left and right operands are identical" in some cases
+        uint32_t op1 = I2C_FIRST_AND_LAST_FRAME;
+        uint32_t op2 = I2C_LAST_FRAME;
+        if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) {
                 HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t*)tx, tx_length, I2C_FIRST_FRAME);
         } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) ||
             (obj_s->XferOperation == I2C_NEXT_FRAME)) {
diff --git a/targets/TARGET_STM/mbed_rtx.h b/targets/TARGET_STM/mbed_rtx.h
index 01cf38e44a8..5bdba667353 100644
--- a/targets/TARGET_STM/mbed_rtx.h
+++ b/targets/TARGET_STM/mbed_rtx.h
@@ -53,7 +53,7 @@
 #define INITIAL_SP              (0x2000A000UL)
 
 #elif defined(TARGET_STM32L432KC)
-#define INITIAL_SP              (0x2000C000UL)
+#define INITIAL_SP              (0x20010000UL)
 
 #elif (defined(TARGET_STM32F303RE) ||\
        defined(TARGET_STM32F303ZE) ||\
@@ -66,6 +66,7 @@
 #elif (defined(TARGET_STM32F401RE) ||\
        defined(TARGET_STM32L475VG) ||\
        defined(TARGET_STM32L476RG) ||\
+       defined(TARGET_STM32L476JG) ||\
        defined(TARGET_STM32L476VG) ||\
        defined(TARGET_STM32L486RG))
 #define INITIAL_SP              (0x20018000UL)
@@ -91,7 +92,8 @@
        defined(TARGET_STM32F469NI) ||\
        defined(TARGET_STM32F746NG) ||\
        defined(TARGET_STM32F746ZG) ||\
-       defined(TARGET_STM32F756ZG))
+       defined(TARGET_STM32F756ZG) ||\
+       defined(TARGET_STM32L496ZG))
 #define INITIAL_SP              (0x20050000UL)
 
 #elif (defined(TARGET_STM32F767ZI) ||\
diff --git a/targets/TARGET_STM/rtc_api.c b/targets/TARGET_STM/rtc_api.c
index c9e9341cf8d..23f7625012b 100644
--- a/targets/TARGET_STM/rtc_api.c
+++ b/targets/TARGET_STM/rtc_api.c
@@ -57,13 +57,14 @@ static void RTC_IRQHandler(void);
 
 void rtc_init(void)
 {
-    RCC_OscInitTypeDef RCC_OscInitStruct;
-    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
     // Enable access to Backup domain
     HAL_PWR_EnableBkUpAccess();
 
     RtcHandle.Instance = RTC;
+    RtcHandle.State = HAL_RTC_STATE_RESET;
 
 #if !RTC_LSI
     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
@@ -162,7 +163,7 @@ void rtc_free(void)
 #endif
 
     // Disable LSI and LSE clocks
-    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
     RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE;
     RCC_OscInitStruct.LSIState       = RCC_LSI_OFF;
@@ -217,8 +218,8 @@ It is then not a problem to not use shifts.
 
 time_t rtc_read(void)
 {
-    RTC_DateTypeDef dateStruct;
-    RTC_TimeTypeDef timeStruct;
+    RTC_DateTypeDef dateStruct = {0};
+    RTC_TimeTypeDef timeStruct = {0};
     struct tm timeinfo;
 
     RtcHandle.Instance = RTC;
@@ -247,8 +248,8 @@ time_t rtc_read(void)
 
 void rtc_write(time_t t)
 {
-    RTC_DateTypeDef dateStruct;
-    RTC_TimeTypeDef timeStruct;
+    RTC_DateTypeDef dateStruct = {0};
+    RTC_TimeTypeDef timeStruct = {0};
 
     RtcHandle.Instance = RTC;
 
@@ -295,13 +296,10 @@ int rtc_isenabled(void)
 
 static void RTC_IRQHandler(void)
 {
+    /*  Update HAL state */
     HAL_RTCEx_WakeUpTimerIRQHandler(&RtcHandle);
-}
-
-void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
-{
+    /* In case of registered handler, call it. */
     if (irq_handler) {
-        // Fire the user callback
         irq_handler();
     }
 }
diff --git a/targets/TARGET_STM/trng_api.c b/targets/TARGET_STM/trng_api.c
index f10bf69e06e..f77f2b31518 100644
--- a/targets/TARGET_STM/trng_api.c
+++ b/targets/TARGET_STM/trng_api.c
@@ -23,19 +23,20 @@
 #include <stdlib.h>
 #include "cmsis.h"
 #include "trng_api.h"
+#include "mbed_error.h"
+#include "mbed_critical.h"
 
-/** trng_get_byte
- *  @brief Get one byte of entropy from the RNG, assuming it is up and running.
- *  @param obj TRNG obj
- *  @param pointer to the hardware generated random byte.
- */
-static void trng_get_byte(trng_t *obj, unsigned char *byte )
-{
-    *byte = (unsigned char)HAL_RNG_GetRandomNumber(&obj->handle);
-}
+static uint8_t users = 0;
 
 void trng_init(trng_t *obj)
 {
+    uint32_t dummy;
+
+    /*  We're only supporting a single user of RNG */
+    if (core_util_atomic_incr_u8(&users, 1) > 1 ) {
+        error("Only 1 RNG instance supported\r\n");
+    }
+
 #if defined(TARGET_STM32L4)
     RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
 
@@ -50,11 +51,13 @@ void trng_init(trng_t *obj)
 
     /* Initialize RNG instance */
     obj->handle.Instance = RNG;
+    obj->handle.State = HAL_RNG_STATE_RESET;
+    obj->handle.Lock = HAL_UNLOCKED;
+
     HAL_RNG_Init(&obj->handle);
 
     /* first random number generated after setting the RNGEN bit should not be used */
-    HAL_RNG_GetRandomNumber(&obj->handle);
-
+    HAL_RNG_GenerateRandomNumber(&obj->handle, &dummy);
 }
 
 void trng_free(trng_t *obj)
@@ -63,23 +66,32 @@ void trng_free(trng_t *obj)
     HAL_RNG_DeInit(&obj->handle);
     /* RNG Peripheral clock disable - assume we're the only users of RNG  */
     __HAL_RCC_RNG_CLK_DISABLE();
+
+    users = 0;
 }
 
 int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
 {
-    int ret;
+    int ret = 0;
+    volatile uint8_t random[4];
+    *output_length = 0;
 
     /* Get Random byte */
-    for( uint32_t i = 0; i < length; i++ ){
-        trng_get_byte(obj, output + i );
+    while ((*output_length < length) && (ret ==0)) {
+        if ( HAL_RNG_GenerateRandomNumber(&obj->handle, (uint32_t *)random ) != HAL_OK) {
+                ret = -1;
+        } else {
+            for (uint8_t i =0; (i < 4) && (*output_length < length) ; i++) {
+                *output++ = random[i];
+                *output_length += 1;
+                random[i] = 0;
+            }
+        }
     }
 
-    *output_length = length;
     /* Just be extra sure that we didn't do it wrong */
     if( ( __HAL_RNG_GET_FLAG(&obj->handle, (RNG_FLAG_CECS | RNG_FLAG_SECS)) ) != 0 ) {
         ret = -1;
-    } else {
-        ret = 0;
     }
 
     return( ret );
diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/analogin_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/analogin_api.c
index c690cb499a1..0de7a2a8bf8 100644
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/analogin_api.c
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/analogin_api.c
@@ -99,8 +99,8 @@ uint16_t analogin_read_u16(analogin_t *obj)
 
 float analogin_read(analogin_t *obj)
 {
-    /* Convert from a uint16 to a float between 0 and 1 by division by 0xFFFF */
-    return analogin_read_u16(obj) / (float) 0xFFFF;
+    /* Convert from a uint16 to a float between 0 and 1 by division by 0xFFF0 */
+    return analogin_read_u16(obj) / (float) 0xFFF0;
 }
 
 #endif
diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c
index 514d7ba6b5f..f2c36fd4247 100644
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/us_ticker.c
@@ -213,6 +213,8 @@ void us_ticker_set_interrupt(timestamp_t timestamp)
 
 void us_ticker_fire_interrupt(void)
 {
+    ticker_int_cnt = 0;
+    TIMER_IntSet(US_TICKER_TIMER, TIMER_IF_CC0);
     NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQ);
 }
 
diff --git a/targets/targets.json b/targets/targets.json
old mode 100644
new mode 100755
index 452e29db014..fd8eb63bfc9
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -110,7 +110,7 @@
         "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
         "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
-	"default_lib": "small",
+        "default_lib": "small",
         "device_name": "LPC11U34FBD48/311"
     },
     "MICRONFCBOARD": {
@@ -238,10 +238,15 @@
         "extra_labels": ["NXP", "LPC176X", "MBED_LPC1768"],
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
         "detect_code": ["1010"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
         "release_versions": ["2", "5"],
         "features": ["LWIP"],
-        "device_name": "LPC1768"
+        "device_name": "LPC1768",
+        "bootloader_supported": true
+    },
+    "LPC1769": {
+        "inherits": ["LPC1768"],
+        "device_name": "LPC1769"
     },
     "ARCH_PRO": {
         "supported_form_factors": ["ARDUINO"],
@@ -250,16 +255,17 @@
         "extra_labels": ["NXP", "LPC176X"],
         "macros": ["TARGET_LPC1768"],
         "inherits": ["LPCTarget"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
         "release_versions": ["2", "5"],
         "features": ["LWIP"],
-        "device_name": "LPC1768"
+        "device_name": "LPC1768",
+        "bootloader_supported": true
     },
     "UBLOX_C027": {
         "supported_form_factors": ["ARDUINO"],
         "core": "Cortex-M3",
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
-        "extra_labels": ["NXP", "LPC176X", "FLASH_CMSIS_ALGO"],
+        "extra_labels": ["NXP", "LPC176X"],
         "config": {
             "modem_is_on_board": {
                 "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
@@ -277,13 +283,14 @@
         "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
         "release_versions": ["2", "5"],
         "features": ["LWIP"],
-        "device_name": "LPC1768"
+        "device_name": "LPC1768",
+        "bootloader_supported": true
     },
     "XBED_LPC1768": {
         "inherits": ["LPCTarget"],
         "core": "Cortex-M3",
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
-        "extra_labels": ["NXP", "LPC176X", "XBED_LPC1768", "FLASH_CMSIS_ALGO"],
+        "extra_labels": ["NXP", "LPC176X", "XBED_LPC1768"],
         "macros": ["TARGET_LPC1768"],
         "detect_code": ["1010"],
         "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
@@ -563,9 +570,10 @@
         "macros": ["CPU_MKW24D512VHA5", "FSL_RTOS_MBED"],
         "inherits": ["Target"],
         "detect_code": ["0250"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
-        "device_name": "MKW24D512xxx5"
+        "device_name": "MKW24D512xxx5",
+        "bootloader_supported": true
     },
     "KW41Z": {
         "supported_form_factors": ["ARDUINO"],
@@ -612,6 +620,28 @@
         "device_name": "MK64FN1M0xxx12",
         "bootloader_supported": true
     },
+    "EV_COG_AD4050LZ": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4F",
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "macros": ["__ADUCM4050__", "EV_COG_AD4050LZ"],
+        "extra_labels": ["Analog_Devices", "ADUCM4X50", "ADUCM4050", "EV_COG_AD4050LZ", "FLASH_CMSIS_ALGO"],
+        "device_has": ["SERIAL", "STDIO_MESSAGES", "TRNG", "SLEEP", "INTERRUPTIN", "RTC", "SPI", "I2C", "FLASH", "ANALOGIN"],
+        "device_name": "ADuCM4050",
+        "detect_code": ["0603"],
+        "release_versions": ["5"]
+    },
+    "EV_COG_AD3029LZ": {
+        "inherits": ["Target"],
+        "core": "Cortex-M3",
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "macros": ["__ADUCM3029__", "EV_COG_AD3029LZ"],
+        "extra_labels": ["Analog_Devices", "ADUCM302X", "ADUCM3029", "EV_COG_AD3029LZ", "FLASH_CMSIS_ALGO"],
+        "device_has": ["SERIAL", "STDIO_MESSAGES", "TRNG", "SLEEP", "INTERRUPTIN", "RTC", "SPI", "I2C", "FLASH", "ANALOGIN"],
+        "device_name": "ADuCM3029",
+        "detect_code": ["0602"],
+        "release_versions": ["5"]
+    },
     "MTS_GAMBIT": {
         "inherits": ["Target"],
         "core": "Cortex-M4F",
@@ -634,7 +664,8 @@
         "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
         "default_lib": "std",
         "release_versions": ["2", "5"],
-        "device_name": "MK64FN1M0xxx12"
+        "device_name": "MK64FN1M0xxx12",
+        "bootloader_supported": true
     },
     "K66F": {
         "supported_form_factors": ["ARDUINO"],
@@ -645,10 +676,11 @@
         "macros": ["CPU_MK66FN2M0VMD18", "FSL_RTOS_MBED"],
         "inherits": ["Target"],
         "detect_code": ["0311"],
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
         "features": ["LWIP"],
         "release_versions": ["2", "5"],
-        "device_name": "MK66FN2M0xxx18"
+        "device_name": "MK66FN2M0xxx18",
+        "bootloader_supported": true
     },
     "K82F": {
         "supported_form_factors": ["ARDUINO"],
@@ -689,18 +721,24 @@
         "release_versions": ["2", "5"],
         "device_name" : "LPC54114J256BD64"
     },
-    "LPC54608": {
+    "LPC546XX": {
         "supported_form_factors": ["ARDUINO"],
         "core": "Cortex-M4F",
         "supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
-        "extra_labels": ["NXP", "MCUXpresso_MCUS", "LPC54608", "LPCXpresso"],
+        "extra_labels": ["NXP", "MCUXpresso_MCUS", "LPCXpresso"],
         "is_disk_virtual": true,
-        "macros": ["CPU_LPC54608J512ET180", "FSL_RTOS_MBED"],
+        "macros": ["CPU_LPC54618J512ET180", "FSL_RTOS_MBED"],
         "inherits": ["Target"],
         "detect_code": ["1056"],
         "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
         "release_versions": ["2", "5"],
-        "device_name" : "LPC54608J512ET180"
+        "device_name" : "LPC54618J512ET180"
+    },
+    "FF_LPC546XX": {
+        "inherits": ["LPC546XX"],
+        "extra_labels_remove" : ["LPCXpresso"],
+        "supported_form_factors": [""],
+        "detect_code": ["8081"]
     },
     "NUCLEO_F030R8": {
         "inherits": ["FAMILY_STM32"],
@@ -710,7 +748,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -769,7 +807,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -787,7 +825,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -805,7 +843,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -823,7 +861,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC (SYSCLK=72 MHz) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI (SYSCLK=64 MHz)",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             },
             "clock_source_usb": {
@@ -850,7 +888,7 @@
             },
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -869,7 +907,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -906,7 +944,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -923,7 +961,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -940,7 +978,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -958,7 +996,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -976,7 +1014,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -994,7 +1032,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             },
             "clock_source_usb": {
@@ -1016,7 +1054,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1035,7 +1073,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1070,7 +1108,7 @@
             },
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             },
             "clock_source_usb": {
@@ -1100,7 +1138,7 @@
             },
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             },
             "clock_source_usb": {
@@ -1126,7 +1164,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1134,7 +1172,8 @@
         "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
         "release_versions": ["2", "5"],
-        "device_name": "STM32F446RE"
+        "device_name": "STM32F446RE",
+        "bootloader_supported": true
     },
     "NUCLEO_F446ZE": {
         "inherits": ["FAMILY_STM32"],
@@ -1144,7 +1183,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1176,7 +1215,7 @@
             },
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1200,7 +1239,7 @@
             },
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1224,7 +1263,7 @@
             },
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1246,7 +1285,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1283,7 +1322,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1301,7 +1340,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1318,7 +1357,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1363,6 +1402,24 @@
         "device_name": "STM32L476RG",
         "bootloader_supported": true
     },
+    "SILICA_SENSOR_NODE": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M4F",
+        "default_toolchain": "GCC_ARM",
+        "extra_labels_add": ["STM32L4", "STM32L476xG", "STM32L476JG"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+                "value": "USE_PLL_MSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0766"],
+        "macros_add": ["USBHOST_OTHER"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "release_versions": ["5"],
+        "device_name": "STM32L476JG"
+    },
     "NUCLEO_L486RG": {
         "inherits": ["FAMILY_STM32"],
         "supported_form_factors": ["ARDUINO", "MORPHO"],
@@ -1400,7 +1457,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1433,7 +1490,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1458,7 +1515,7 @@
         "extra_labels_add": ["STM32F4", "STM32F429", "STM32F429ZI", "STM32F429xI", "STM32F429xx"],
         "config": {
             "clock_source": {
-                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI",
                 "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             },
@@ -1480,12 +1537,13 @@
         "extra_labels_add": ["STM32F4", "STM32F469", "STM32F469NI", "STM32F469xI", "STM32F469xx"],
         "config": {
             "clock_source": {
-                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI",
                 "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
         "detect_code": ["0788"],
+        "macros_add": ["USB_STM_HAL"],
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32F469NI"
@@ -1498,7 +1556,7 @@
         "config": {
             "clock_source": {
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
-                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI",
+                "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
@@ -1515,13 +1573,13 @@
         "macros": ["RTC_LSI=1"],
         "config": {
             "clock_source": {
-                "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
                 "value": "USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
             }
         },
         "detect_code": ["0833"],
-        "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "TRNG"],
+        "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32L072CZ"
     },
@@ -1575,9 +1633,10 @@
         "supported_form_factors": ["ARDUINO"],
         "detect_code": ["0764"],
         "macros_add": ["USBHOST_OTHER"],
-        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
-        "device_name": "STM32L475VG"
+        "device_name": "STM32L475VG",
+        "bootloader_supported": true
     },
     "DISCO_L476VG": {
         "inherits": ["FAMILY_STM32"],
@@ -1662,6 +1721,11 @@
         "device_name": "STM32L151CC",
         "bootloader_supported": true
     },
+    "FF1705_L151CC": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["XDOT_L151CC"],
+        "detect_code": ["8080"]
+    },
     "MOTE_L152RC": {
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M3",
@@ -1683,19 +1747,56 @@
         "device_has_add": [],
         "device_name": "STM32F401VC"
     },
-    "UBLOX_EVK_ODIN_W2": {
+    "MODULE_UBLOX_ODIN_W2": {
         "inherits": ["FAMILY_STM32"],
-        "supported_form_factors": ["ARDUINO"],
         "core": "Cortex-M4F",
         "extra_labels_add": ["STM32F4", "STM32F439", "STM32F439ZI","STM32F439xx", "STM32F439xI"],
         "macros": ["MBEDTLS_CONFIG_HW_SUPPORT", "HSE_VALUE=24000000", "HSE_STARTUP_TIMEOUT=5000", "CB_INTERFACE_SDIO","CB_CHIP_WL18XX","SUPPORT_80211D_ALWAYS","WLAN_ENABLED","MBEDTLS_ARC4_C","MBEDTLS_DES_C","MBEDTLS_MD4_C","MBEDTLS_MD5_C","MBEDTLS_SHA1_C"],
         "device_has_add": ["CAN", "EMAC", "TRNG", "FLASH"],
         "device_has_remove": ["RTC", "SLEEP"],
         "features": ["LWIP"],
-        "release_versions": ["5"],
         "device_name": "STM32F439ZI",
         "bootloader_supported": true
     },
+    "UBLOX_EVK_ODIN_W2": {
+        "inherits": ["MODULE_UBLOX_ODIN_W2"],
+        "supported_form_factors": ["ARDUINO"],
+        "release_versions": ["5"],
+        "config": {
+            "usb_tx": {
+                "help": "Value: D8(default) or D1",
+                "value": "D8"
+            },
+            "usb_rx": {
+                "help": "Value: D2(default) or D0",
+                "value": "D2"
+            },
+            "stdio_uart": {
+                "help": "Value: UART_1(default) or UART_3",
+                "value": "UART_1",
+                "macro_name": "STDIO_UART"
+            }
+        }
+    },
+    "MBED_CONNECT_ODIN": {
+        "inherits": ["MODULE_UBLOX_ODIN_W2"],
+        "release_versions": ["5"],
+        "config": {
+            "usb_tx": {
+                "help": "Value: PA_9(default) or PD_8",
+                "value": "PA_9"
+            },
+            "usb_rx": {
+                "help": "Value: PA_10(default) or PD_9",
+                "value": "PA_10"
+            },
+            "stdio_uart": {
+                "help": "Value: UART_1(default) or UART_3",
+                "value": "UART_1",
+                "macro_name": "STDIO_UART"
+            }
+        }
+    },
     "UBLOX_C030": {
         "inherits": ["FAMILY_STM32"],
         "supported_form_factors": ["ARDUINO"],
@@ -1714,7 +1815,7 @@
                 "macro_name": "MODEM_ON_BOARD_UART"
             }
         },
-        "macros_add": ["RTC_LSI=1", "HSE_VALUE=12000000", "GNSSBAUD=9600"],
+        "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "RTC_LSI=1", "HSE_VALUE=12000000", "GNSSBAUD=9600"],
         "device_has_add": ["ANALOGOUT", "SERIAL_FC", "TRNG", "FLASH"],
         "features": ["LWIP"],
         "public": false,
@@ -1993,6 +2094,15 @@
         "extra_labels_add": ["RBLAB_BLENANO"],
         "macros_add": ["TARGET_RBLAB_BLENANO"]
     },
+    "RBLAB_BLENANO2": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF52"],
+        "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
+        "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "release_versions": ["2", "5"],
+        "overrides": {"uart_hwfc": 0},
+        "device_name": "nRF52832_xxAA"
+    },
     "NRF51822_Y5_MBUG": {
         "inherits": ["MCU_NRF51_16K"]
     },
@@ -2323,13 +2433,14 @@
     "EFM32": {
         "inherits": ["Target"],
         "extra_labels": ["Silicon_Labs", "EFM32"],
+        "macros": ["MBEDTLS_CONFIG_HW_SUPPORT"],
         "public": false
     },
     "EFM32GG990F1024": {
         "inherits": ["EFM32"],
         "extra_labels_add": ["EFM32GG", "1024K", "SL_AES"],
         "core": "Cortex-M3",
-        "macros": ["EFM32GG990F1024", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "macros_add": ["EFM32GG990F1024", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
         "release_versions": ["2", "5"],
         "device_name": "EFM32GG990F1024",
@@ -2383,7 +2494,7 @@
         "inherits": ["EFM32"],
         "extra_labels_add": ["EFM32LG", "256K", "SL_AES"],
         "core": "Cortex-M3",
-        "macros": ["EFM32LG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "macros_add": ["EFM32LG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
         "release_versions": ["2", "5"],
         "device_name": "EFM32LG990F256",
@@ -2437,7 +2548,7 @@
         "inherits": ["EFM32"],
         "extra_labels_add": ["EFM32WG", "256K", "SL_AES"],
         "core": "Cortex-M4F",
-        "macros": ["EFM32WG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "macros_add": ["EFM32WG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
         "release_versions": ["2", "5"],
         "device_name": "EFM32WG990F256",
@@ -2492,7 +2603,7 @@
         "extra_labels_add": ["EFM32ZG", "32K", "SL_AES"],
         "core": "Cortex-M0+",
         "default_toolchain": "uARM",
-        "macros": ["EFM32ZG222F32", "TRANSACTION_QUEUE_SIZE_SPI=0"],
+        "macros_add": ["EFM32ZG222F32", "TRANSACTION_QUEUE_SIZE_SPI=0"],
         "supported_toolchains": ["GCC_ARM", "uARM", "IAR"],
         "default_lib": "small",
         "release_versions": ["2"],
@@ -2546,7 +2657,7 @@
         "extra_labels_add": ["EFM32HG", "64K", "SL_AES"],
         "core": "Cortex-M0+",
         "default_toolchain": "uARM",
-        "macros": ["EFM32HG322F64", "TRANSACTION_QUEUE_SIZE_SPI=0"],
+        "macros_add": ["EFM32HG322F64", "TRANSACTION_QUEUE_SIZE_SPI=0"],
         "supported_toolchains": ["GCC_ARM", "uARM", "IAR"],
         "default_lib": "small",
         "release_versions": ["2"],
@@ -2599,7 +2710,7 @@
         "inherits": ["EFM32"],
         "extra_labels_add": ["EFM32PG", "256K", "SL_CRYPTO"],
         "core": "Cortex-M4F",
-        "macros": ["EFM32PG1B100F256GM32", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "macros_add": ["EFM32PG1B100F256GM32", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
         "release_versions": ["2", "5"],
         "device_name": "EFM32PG1B100F256GM32",
@@ -2652,7 +2763,7 @@
         "inherits": ["EFM32"],
         "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL", "SL_CRYPTO"],
         "core": "Cortex-M4F",
-        "macros": ["EFR32MG1P132F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "macros_add": ["EFR32MG1P132F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
         "release_versions": ["2", "5"],
         "device_name": "EFR32MG1P132F256GM48",
@@ -2663,7 +2774,7 @@
         "inherits": ["EFM32"],
         "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL", "SL_CRYPTO"],
         "core": "Cortex-M4F",
-        "macros": ["EFR32MG1P233F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "macros_add": ["EFR32MG1P233F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
         "release_versions": ["2", "5"],
         "public": false,
@@ -2753,7 +2864,7 @@
         "inherits": ["EFM32"],
         "extra_labels_add": ["EFM32PG12", "1024K", "SL_CRYPTO"],
         "core": "Cortex-M4F",
-        "macros": ["EFM32PG12B500F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "macros_add": ["EFM32PG12B500F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
         "release_versions": ["2", "5"],
         "public": false,
@@ -2801,17 +2912,17 @@
             }
         }
     },
-	"EFR32MG12P332F1024GL125": {
+    "EFR32MG12P332F1024GL125": {
         "inherits": ["EFM32"],
         "extra_labels_add": ["EFR32MG12", "1024K", "SL_RAIL", "SL_CRYPTO"],
         "core": "Cortex-M4F",
-        "macros": ["EFR32MG12P332F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
+        "macros_add": ["EFR32MG12P332F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
         "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
         "release_versions": ["2", "5"],
         "public": false,
         "bootloader_supported": true
     },
-	"TB_SENSE_12": {
+    "TB_SENSE_12": {
         "inherits": ["EFR32MG12P332F1024GL125"],
         "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG", "FLASH"],
         "forced_reset_timeout": 5,
@@ -3000,6 +3111,7 @@
         "inherits": ["Target"],
         "core": "Cortex-M4F",
         "macros": ["NRF52", "TARGET_NRF52832", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S132", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"", "MBED_TICKLESS"],
+        "device_has": ["STCLK_OFF_DURING_SLEEP"],
         "extra_labels": ["NORDIC", "MCU_NRF52", "MCU_NRF52832", "NRF5", "SDK11", "NRF52_COMMON"],
         "OUTPUT_EXT": "hex",
         "is_disk_virtual": true,
@@ -3037,14 +3149,14 @@
         "supported_form_factors": ["ARDUINO"],
         "inherits": ["MCU_NRF52"],
         "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
-        "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
         "release_versions": ["2", "5"],
         "device_name": "nRF52832_xxAA"
     },
     "UBLOX_EVA_NINA": {
         "inherits": ["MCU_NRF52"],
         "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
-        "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
         "release_versions": ["2", "5"],
         "overrides": {"uart_hwfc": 0},
         "device_name": "nRF52832_xxAA"
@@ -3053,7 +3165,7 @@
         "supported_form_factors": ["ARDUINO"],
         "inherits": ["MCU_NRF52"],
         "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
-        "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
         "release_versions": ["2", "5"],
         "device_name": "nRF52832_xxAA"
     },
@@ -3061,7 +3173,7 @@
         "supported_form_factors": ["ARDUINO"],
         "inherits": ["MCU_NRF52"],
         "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
-        "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
         "release_versions": ["2", "5"],
         "overrides": {"lf_clock_src": "NRF_LF_SRC_RC"},
         "config": {
@@ -3080,6 +3192,7 @@
         "inherits": ["Target"],
         "core": "Cortex-M4F",
         "macros": ["TARGET_NRF52840", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S140", "NRF_SD_BLE_API_VERSION=5", "NRF52840_XXAA", "NRF_DFU_SETTINGS_VERSION=1", "NRF_SD_BLE_API_VERSION=5", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "device_has": ["STCLK_OFF_DURING_SLEEP"],	    
         "extra_labels": ["NORDIC", "MCU_NRF52840", "NRF5", "SDK13", "NRF52_COMMON"],
         "OUTPUT_EXT": "hex",
         "is_disk_virtual": true,
@@ -3118,7 +3231,7 @@
         "supported_form_factors": ["ARDUINO"],
         "inherits": ["MCU_NRF52840"],
         "macros_add": ["BOARD_PCA10056", "CONFIG_GPIO_AS_PINRESET", "SWI_DISABLE0", "NRF52_ERRATA_20"],
-        "device_has": ["FLASH", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "TRNG"],
+        "device_has_add": ["FLASH", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "TRNG"],
         "release_versions": ["2", "5"],
         "device_name": "nRF52840_xxAA"
     },
@@ -3237,6 +3350,24 @@
         "extra_labels": ["NUVOTON", "NANO100", "NANO130KE3BN"],
         "is_disk_virtual": true,
         "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+        "config": {
+            "gpio-irq-debounce-enable": {
+                "help": "Enable GPIO IRQ debounce",
+                "value": 0
+            },
+            "gpio-irq-debounce-enable-list": {
+                "help": "Comma separated pin list to enable GPIO IRQ debounce",
+                "value": "NC"
+            },
+            "gpio-irq-debounce-clock-source": {
+                "help": "Select GPIO IRQ debounce clock source: GPIO_DBCLKSRC_HCLK or GPIO_DBCLKSRC_IRC10K",
+                "value": "GPIO_DBCLKSRC_IRC10K"
+            },
+            "gpio-irq-debounce-sample-rate": {
+                "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCLKSEL_1, GPIO_DBCLKSEL_2, GPIO_DBCLKSEL_4, ..., or GPIO_DBCLKSEL_32768",
+                "value": "GPIO_DBCLKSEL_16"
+            }
+        },
         "inherits": ["Target"],
         "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
         "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
@@ -3310,6 +3441,27 @@
         "release_versions": ["2"],
         "device_name": "nRF51822_xxAC"
     },
+    "NUCLEO_L496ZG": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO", "MORPHO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32L4", "STM32L496ZG", "STM32L496xG"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+                "value": "USE_PLL_MSI",
+                "macro_name": "CLOCK_SOURCE"
+            }
+        },
+        "detect_code": ["0823"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32L496ZG"
+    },
+    "NUCLEO_L496ZG_P": {
+        "inherits": ["NUCLEO_L496ZG"],
+        "detect_code": ["0828"]
+        },
     "VBLUNO52": {
         "supported_form_factors": ["ARDUINO"],
         "inherits": ["MCU_NRF52"],
diff --git a/tools/build_api.py b/tools/build_api.py
index 7a267a04059..790b1bcb65b 100644
--- a/tools/build_api.py
+++ b/tools/build_api.py
@@ -438,6 +438,18 @@ def scan_resources(src_paths, toolchain, dependencies_paths=None,
     # Set the toolchain's configuration data
     toolchain.set_config_data(toolchain.config.get_config_data())
 
+    if  (hasattr(toolchain.target, "release_versions") and
+            "5" not in toolchain.target.release_versions and
+            "rtos" in toolchain.config.lib_config_data):
+        if "Cortex-A" in toolchain.target.core:
+            raise NotSupportedException(
+                ("%s Will be supported in mbed OS 5.6. "
+                    "To use the %s, please checkout the mbed OS 5.4 release branch. "
+                    "See https://developer.mbed.org/platforms/Renesas-GR-PEACH/#important-notice "
+                    "for more information") % (toolchain.target.name, toolchain.target.name))
+        else:
+            raise NotSupportedException("Target does not support mbed OS 5")
+
     return resources
 
 def build_project(src_paths, build_path, target, toolchain_name,
@@ -519,17 +531,6 @@ def build_project(src_paths, build_path, target, toolchain_name,
     try:
         # Call unified scan_resources
         resources = scan_resources(src_paths, toolchain, inc_dirs=inc_dirs)
-        if  (hasattr(toolchain.target, "release_versions") and
-             "5" not in toolchain.target.release_versions and
-             "rtos" in toolchain.config.lib_config_data):
-            if "Cortex-A" in toolchain.target.core:
-                raise NotSupportedException(
-                    ("%s Will be supported in mbed OS 5.6. "
-                     "To use the %s, please checkout the mbed OS 5.4 release branch. "
-                     "See https://developer.mbed.org/platforms/Renesas-GR-PEACH/#important-notice "
-                     "for more information") % (toolchain.target.name, toolchain.target.name))
-            else:
-                raise NotSupportedException("Target does not support mbed OS 5")
 
         # Change linker script if specified
         if linker_script is not None:
diff --git a/tools/build_travis.py b/tools/build_travis.py
index 0982ee1a932..395dbd593a1 100644
--- a/tools/build_travis.py
+++ b/tools/build_travis.py
@@ -63,6 +63,7 @@
     { "target": "NUCLEO_F446ZE",     "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
     { "target": "NUCLEO_F746ZG",     "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
     { "target": "NUCLEO_F767ZI",     "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
+    { "target": "NUCLEO_L496ZG",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
 
     { "target": "MOTE_L152RC",     "toolchains": "GCC_ARM", "libs": ["dsp"] },
 
diff --git a/tools/detect_targets.py b/tools/detect_targets.py
index 5f32801db82..b9aa80df1ca 100644
--- a/tools/detect_targets.py
+++ b/tools/detect_targets.py
@@ -31,8 +31,13 @@
 # Imports related to mbed build api
 from tools.build_api import mcu_toolchain_matrix
 from tools.test_api import get_autodetected_MUTS_list
+from tools.test_api import get_module_avail
 from argparse import ArgumentParser
 
+try:
+    import mbed_lstools
+except:
+    pass
 
 def main():
     """Entry Point"""
@@ -75,15 +80,17 @@ def main():
         count = 0
         for mut in muts.values():
             if re.match(mcu_filter, mut['mcu']):
+                interface_version = get_interface_version(mut['disk'])
                 print ""
-                print "[mbed] Detected %s, port %s, mounted %s" % \
-                    (mut['mcu'], mut['port'], mut['disk'])
+                print "[mbed] Detected %s, port %s, mounted %s, interface version %s:" % \
+                        (mut['mcu'], mut['port'], mut['disk'], interface_version)
+                                    
                 print "[mbed] Supported toolchains for %s" % mut['mcu']
                 print mcu_toolchain_matrix(platform_filter=mut['mcu'])
                 count += 1
 
         if count == 0:
-            print "[mbed] No mbed targets where detected on your system."
+            print "[mbed] No mbed targets were detected on your system."
 
     except KeyboardInterrupt:
         print "\n[CTRL+c] exit"
@@ -92,6 +99,32 @@ def main():
         traceback.print_exc(file=sys.stdout)
         print "[ERROR] %s" % str(exc)
         sys.exit(1)
+        
+def get_interface_version(mount_point):
+    """ Function returns interface version from the target mounted on the specified mount point
+    
+        mount_point can be acquired via the following:
+            muts = get_autodetected_MUTS_list()
+            for mut in muts.values():
+                mount_point = mut['disk']
+                    
+        @param mount_point Name of disk where platform is connected to host machine.
+    """
+    if get_module_avail('mbed_lstools'):
+        try :
+            mbeds = mbed_lstools.create()
+            details_txt = mbeds.get_details_txt(mount_point)
+            
+            if 'Interface Version' in details_txt:
+                return details_txt['Interface Version']
+            
+            elif 'Version' in details_txt:
+                return details_txt['Version']
+            
+        except :
+            return 'unknown'
+        
+    return 'unknown'
 
 if __name__ == '__main__':
     main()
diff --git a/tools/export/__init__.py b/tools/export/__init__.py
index b56f790cbfe..501be59d151 100644
--- a/tools/export/__init__.py
+++ b/tools/export/__init__.py
@@ -310,6 +310,7 @@ def export_project(src_paths, export_path, target, ide, libraries_paths=None,
         extra_verbose=extra_verbose, config=config, build_profile=build_profile,
         app_config=app_config)
     # The first path will give the name to the library
+    toolchain.RESPONSE_FILES = False
     if name is None:
         name = basename(normpath(abspath(src_paths[0])))
 
diff --git a/tools/export/ds5_5/__init__.py b/tools/export/ds5_5/__init__.py
index 00acacf554d..377f4fe8628 100644
--- a/tools/export/ds5_5/__init__.py
+++ b/tools/export/ds5_5/__init__.py
@@ -29,6 +29,7 @@ class DS5_5(Exporter):
         'UBLOX_C027',
         'ARCH_PRO',
         'RZ_A1H',
+        'VK_RZ_A1H',
     ]
 
     USING_MICROLIB = [
diff --git a/tools/export/e2studio/.cproject.tmpl b/tools/export/e2studio/.cproject.tmpl
new file mode 100644
index 00000000000..d8732301d35
--- /dev/null
+++ b/tools/export/e2studio/.cproject.tmpl
@@ -0,0 +1,414 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+<!-- Generated by the GNU ARM Eclipse exporter from an mBed project. -->
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		{% for cfg_key in options %}
+		{% set opts = options[cfg_key] %}
+		<cconfiguration id="com.renesas.cdt.managedbuild.gnuarm.config.elf.{{opts['id']}}.{{opts['uid']['config']}}">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.renesas.cdt.managedbuild.gnuarm.config.elf.{{opts['id']}}.{{opts['uid']['config']}}" moduleId="org.eclipse.cdt.core.settings" name="{{opts['name']}}">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.{{opts['parent_id']}}" cleanCommand="${cross_rm} -rf" description="" id="com.renesas.cdt.managedbuild.gnuarm.config.elf.{{opts['id']}}.{{opts['uid']['config']}}" name="{{opts['name']}}" parent="com.renesas.cdt.managedbuild.gnuarm.config.elf.{{opts['parent_id']}}">
+					<folderInfo id="com.renesas.cdt.managedbuild.gnuarm.config.elf.{{opts['id']}}.{{opts['uid']['config']}}." name="/" resourcePath="">
+						<toolChain id="com.renesas.cdt.managedbuild.gnuarm.toolchain.elf.{{opts['id']}}.{{u.id}}" name="GCC ARM Embedded" superClass="com.renesas.cdt.managedbuild.gnuarm.toolchain.elf.{{opts['parent_id']}}">
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family.{{u.id}}" name="ARM family" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.{{opts['common']['arm.target.family']}}" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.architecture.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.architecture" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.arch.{{opts['common']['arm.target.arch']}}" valueType="enumerated"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.{{u.id}}" name="Instruction set" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.{{opts['common']['arm.target.instructionset']}}" valueType="enumerated"/>
+							{% if opts['common']['arm.target.thumbinterwork'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.thumbinterwork.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.thumbinterwork" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['arm.target.endianness'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.endianness.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.endianness" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.endianness.{{opts['common']['arm.target.endianness']}}" valueType="enumerated"/>
+							{% endif %}
+							{% if opts['common']['arm.target.fpu.abi'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.{{u.id}}" name="Float ABI" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.{{opts['common']['arm.target.fpu.abi']}}" valueType="enumerated"/>
+							{% endif %}
+							{% if opts['common']['arm.target.fpu.unit'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.{{u.id}}" name="FPU Type" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.{{opts['common']['arm.target.fpu.unit']}}" valueType="enumerated"/>
+							{% endif %}
+							{% if opts['common']['arm.target.unalignedaccess'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.unalignedaccess.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.unalignedaccess" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.unalignedaccess.{{opts['common']['arm.target.unalignedaccess']}}" valueType="enumerated"/>
+							{% endif %}
+
+							{% if opts['common']['optimization.level'] != '' %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.{{u.id}}" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.{{opts['common']['optimization.level']}}" valueType="enumerated"/>
+							{% endif %}
+							{% if opts['common']['optimization.messagelength'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.{{u.id}}" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.signedchar'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.{{u.id}}" name="'char' is signed (-fsigned-char)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.functionsections'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.{{u.id}}" name="Function sections (-ffunction-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.datasections'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections.{{u.id}}" name="Data sections (-fdata-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.nocommon'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nocommon.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nocommon" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.noinlinefunctions'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.noinlinefunctions.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.noinlinefunctions" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.freestanding'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.freestanding.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.freestanding" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.nobuiltin'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nobuiltin.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nobuiltin" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.spconstant'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.spconstant.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.spconstant" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.PIC'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.PIC.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.PIC" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.nomoveloopinvariants'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nomoveloopinvariants.{{u.id}}" name="Disable loop invariant move (-fno-move-loop-invariants)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.nomoveloopinvariants" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['optimization.other'] != '' %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.other.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.other" value="{{opts['common']['optimization.other']}}" valueType="string"/>
+							{% endif %}
+
+							{% if opts['common']['warnings.syntaxonly'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.syntaxonly.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.syntaxonly" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.pedantic'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.pedantic.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.pedantic" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.pedanticerrors'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.pedanticerrors.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.pedanticerrors" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.nowarn'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.nowarn.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.nowarn" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.unused'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.unused.{{u.id}}" name="Warn on various unused elements (-Wunused)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.unused" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.uninitialized'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.uninitialized.{{u.id}}" name="Warn on uninitialized variables (-Wuninitialised)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.uninitialized" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.allwarn'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.{{u.id}}" name="Enable all common warnings (-Wall)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.extrawarn'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.extrawarn.{{u.id}}" name="Enable extra warnings (-Wextra)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.extrawarn" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.missingdeclaration'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.missingdeclaration.{{u.id}}" name="Warn on undeclared global function (-Wmissing-declaration)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.missingdeclaration" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.conversion'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.conversion.{{u.id}}" name="Warn on implicit conversions (-Wconversion)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.conversion" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.pointerarith'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.pointerarith.{{u.id}}" name="Warn if pointer arithmetic (-Wpointer-arith)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.pointerarith" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.padded'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.padded.{{u.id}}" name="Warn if padding is included (-Wpadded)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.padded" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.shadow'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.shadow.{{u.id}}" name="Warn if shadowed variable (-Wshadow)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.shadow" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.logicalop'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.logicalop.{{u.id}}" name="Warn if suspicious logical ops (-Wlogical-op)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.logicalop" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.agreggatereturn'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.agreggatereturn.{{u.id}}" name="Warn if struct is returned (-Wagreggate-return)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.agreggatereturn" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.floatequal'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.floatequal.{{u.id}}" name="Warn if floats are compared as equal (-Wfloat-equal)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.floatequal" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['warnings.toerrors'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.toerrors.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.toerrors" value="true" valueType="boolean"/>
+							{% endif %}
+							
+							{% if opts['common']['warnings.other'] != '' %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.other.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.other" value="{{opts['common']['warnings.other']}}" valueType="string"/>
+							{% endif %}
+
+							{% if opts['common']['debugging.level'] != 'none' %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.{{u.id}}" name="Debug level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.{{opts['common']['debugging.level']}}" valueType="enumerated"/>
+							{% endif %}
+							{% if opts['common']['debugging.format'] != '' %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.{{u.id}}" name="Debug format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.{{opts['common']['debugging.format']}}"  valueType="enumerated"/>
+							{% endif %}
+							{% if opts['common']['debugging.prof'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.prof.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.prof" value="true" valueType="boolean"/>
+							{% endif %}
+							{% if opts['common']['debugging.gprof'] %}
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.gprof.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.gprof" value="true" valueType="boolean"/>
+							{% endif %}
+
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name" value="GNU Tools for ARM Embedded Processors" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix.{{u.id}}" name="Prefix" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix" value="arm-none-eabi-" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.c.{{u.id}}" name="C compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.c" value="gcc" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.{{u.id}}" name="C++ compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" value="g++" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar.{{u.id}}" name="Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar" value="ar" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy.{{u.id}}" name="Hex/Bin converter" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy" value="objcopy" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump.{{u.id}}" name="Listing generator" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump" value="objdump" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.size.{{u.id}}" name="Size command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.size" value="size" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.make.{{u.id}}" name="Build command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.make" value="make" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.{{u.id}}" name="Remove command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" value="rm" valueType="string"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash.{{u.id}}" name="Create flash image" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash" value="true" valueType="boolean"/>
+							<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.{{u.id}}" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" value="true" valueType="boolean"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform.{{u.id}}" isAbstract="false" osList="all" superClass="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform"/>
+							<builder buildPath="${workspace_loc:/{{name}}}/BUILD/{{opts['name']}}" cleanBuildTarget="mbedclean" id="ilg.gnuarmeclipse.managedbuild.cross.builder.{{u.id}}" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnuarmeclipse.managedbuild.cross.builder"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.{{u.id}}" name="Cross ARM GNU Assembler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler">
+								{% if opts['as']['usepreprocessor'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor.{{u.id}}" name="Use preprocessor" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['as']['nostdinc'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.nostdinc.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.nostdinc" value="true" valueType="boolean"/>
+								{% endif %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths.{{u.id}}" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths" valueType="includePath">
+									{% for path in opts['common']['include_paths'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs.{{u.id}}" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs" useByScannerDiscovery="true" valueType="definedSymbols">
+									{% for s in opts['as']['defines'] %}
+									<listOptionValue builtIn="false" value='{{s|replace("\"", "\\\"")|escape}}' />
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.files.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.files" useByScannerDiscovery="true" valueType="includeFiles">
+									{% for file in opts['common']['include_files'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{file}}&quot;"/>
+									{% endfor %}
+								</option>
+								{% if opts['as']['otherwarnings'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.otherwarnings.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.otherwarnings" value="{{opts['as']['otherwarnings']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['as']['verbose'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.verbose.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.verbose" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['as']['other'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.other.{{u.id}}" name="Other assembler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.other" value="{{opts['as']['other']}}" valueType="string"/>
+								{% endif %}
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.{{opts['uid']['tool_c_compiler']}}" name="Cross ARM C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler">
+								{% if opts['c']['nostdinc'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.nostdinc.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.nostdinc" value="true" valueType="boolean"/>
+								{% endif %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths.{{u.id}}" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
+									{% for path in opts['common']['include_paths'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.{{u.id}}" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" useByScannerDiscovery="true" valueType="definedSymbols">
+									{% for s in opts['c']['defines'] %}
+									<listOptionValue builtIn="false" value='{{s|replace("\"", "\\\"")|escape}}'/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.files.{{u.id}}" name="Include files (-include)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.files" useByScannerDiscovery="true" valueType="includeFiles">
+									{% for file in opts['common']['include_files'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{file}}&quot;"/>
+									{% endfor %}
+								</option>
+								{% if opts['c']['compiler.std'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std" value="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.std.{{opts['c']['compiler.std']}}" valueType="enumerated"/>
+								{% endif %}
+								{% if opts['c']['otheroptimizations'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.otheroptimizations.{{u.id}}" name="Other optimization flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.otheroptimizations" useByScannerDiscovery="true" value="{{opts['c']['otheroptimizations']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['c']['warnings.missingprototypes'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.warning.missingprototypes.{{u.id}}" name="Warn if a global function has no prototype (-Wmissing-prototypes)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.warning.missingprototypes" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['warnings.strictprototypes'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.warning.strictprototypes.{{u.id}}" name="Warn if a function has no arg type (-Wstrict-prototypes)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.warning.strictprototypes" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['warnings.badfunctioncast'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.warning.badfunctioncast.{{u.id}}" name="Warn if wrong cast  (-Wbad-function-cast)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.warning.badfunctioncast" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['otherwarnings'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.otherwarnings.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.otherwarnings" value="{{opts['c']['otherwarnings']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['c']['verbose'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.verbose.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.verbose" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['other'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other" value="{{opts['c']['other']}}" valueType="string"/>
+								{% endif %}
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.{{opts['uid']['tool_c_compiler_input']}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.{{opts['uid']['tool_cpp_compiler']}}" name="Cross ARM C++ Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler">
+								{% if opts['cpp']['nostdinc'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nostdinc.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nostdinc" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['nostdincpp'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nostdincpp.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nostdincpp" value="true" valueType="boolean"/>
+								{% endif %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths.{{u.id}}" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths" useByScannerDiscovery="false" valueType="includePath">
+									{% for path in opts['common']['include_paths'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs.{{u.id}}" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs" useByScannerDiscovery="true" valueType="definedSymbols">
+									{% for s in opts['cpp']['defines'] %}
+									<listOptionValue builtIn="false" value='{{s|replace("\"", "\\\"")|escape}}'/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.files.{{u.id}}" name="Include files (-include)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.files" useByScannerDiscovery="true" valueType="includeFiles">
+									{% for file in opts['common']['include_files'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{file}}&quot;"/>
+									{% endfor %}
+								</option>
+								{% if opts['cpp']['compiler.std'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std" value="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.std.{{opts['cpp']['compiler.std']}}" valueType="enumerated"/>
+								{% endif %}
+
+								{% if opts['cpp']['optimization.noexceptions'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions.{{u.id}}" name="Do not use exceptions (-fno-exceptions)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.noexceptions" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['optimization.nortti'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti.{{u.id}}" name="Do not use RTTI (-fno-rtti)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nortti" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['optimization.nousecxaatexit'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nousecxaatexit.{{u.id}}" name="Do not use _cxa_atexit() (-fno-use-cxa-atexit)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nousecxaatexit" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['optimization.nothreadsafestatics'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nothreadsafestatics.{{u.id}}" name="Do not use thread-safe statics (-fno-threadsafe-statics)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.nothreadsafestatics" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['otheroptimizations'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.otheroptimizations.{{u.id}}" name="Other optimization flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.otheroptimizations" useByScannerDiscovery="true" value="{{opts['cpp']['otheroptimizations']}}" valueType="string"/>
+								{% endif %}
+
+								{% if opts['cpp']['warnabi'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warnabi.{{u.id}}" name="Warn on ABI violations (-Wabi)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warnabi" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['warnings.ctordtorprivacy'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.ctordtorprivacy.{{u.id}}" name="Warn on class privacy (-Wctor-dtor-privacy)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.ctordtorprivacy" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['warnings.noexcept'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.noexcept.{{u.id}}" name="Warn on no-except expressions (-Wnoexcept)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.noexcept" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['warnings.nonvirtualdtor'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.nonvirtualdtor.{{u.id}}" name="Warn on virtual destructors (-Wnon-virtual-dtor)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.nonvirtualdtor" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['warnings.strictnullsentinel'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.strictnullsentinel.{{u.id}}" name="Warn on uncast NULL (-Wstrict-null-sentinel)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.strictnullsentinel" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['warnings.signpromo'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.signpromo.{{u.id}}" name="Warn on sign promotion (-Wsign-promo)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warning.signpromo" useByScannerDiscovery="true" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['warneffc'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warneffc.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.warneffc" value="true" valueType="boolean"/>
+								{% endif %}								
+								{% if opts['cpp']['otherwarnings'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.otherwarnings.{{u.id}}" name="Other warning flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.otherwarnings" useByScannerDiscovery="true" value="{{opts['cpp']['otherwarnings']}}" valueType="string"/>
+								{% endif %}
+
+								{% if opts['cpp']['verbose'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.verbose.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.verbose" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['other'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.other" value="{{opts['cpp']['other']}}" valueType="string"/>
+								{% endif %}
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.{{opts['uid']['tool_cpp_compiler_input']}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.{{u.id}}" name="Cross ARM C++ Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile.{{u.id}}" name="Script files (-T)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile" valueType="stringList">
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{opts['ld']['script']}}&quot;"/>
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.{{u.id}}" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" valueType="libPaths">
+									{% for path in opts['ld']['library_paths'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs" valueType="libs">
+									{% for lib in opts['ld']['user_libraries'] %}
+									<listOptionValue builtIn="false" value="{{lib}}"/>
+									{% endfor %}
+									{% for lib in opts['ld']['system_libraries'] %}
+									<listOptionValue builtIn="false" value="{{lib}}"/>
+									{% endfor %}
+								</option>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.otherobjs.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.otherobjs" valueType="userObjs">
+									{% for path in opts['ld']['object_files'] %}
+									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									{% endfor %}
+								</option>
+								{% if opts['ld']['gcsections'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections.{{u.id}}" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
+								{% endif %}
+
+								{% if opts['ld']['nostart'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostart.{{u.id}}" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostart" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['ld']['nodeflibs'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nodeflibs.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nodeflibs" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['ld']['nostdlibs'] %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostdlibs.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostdlibs" value="true" valueType="boolean"/>
+								{% endif %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.flags.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.flags" valueType="stringList">
+									{% for opt in opts['ld']['flags'] %}
+									<listOptionValue builtIn="false" value="{{opt}}"/>
+									{% endfor %}
+								</option>
+
+								{% if opts['ld']['other'] != '' %}
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.other" value="{{opts['ld']['other']}}" valueType="string"/>
+								{% endif %}
+								<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.{{u.id}}" name="Cross ARM GNU Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver"/>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.{{u.id}}" name="Cross ARM GNU Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.{{u.id}}" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.binary" valueType="enumerated"/>
+							</tool>
+
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.{{u.id}}" name="Cross ARM GNU Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.{{u.id}}" name="Display source (--source|-S)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.{{u.id}}" name="Display all headers (--all-headers|-x)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.{{u.id}}" name="Demangle names (--demangle|-C)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.{{u.id}}" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean"/>
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.{{u.id}}" name="Wide lines (--wide|-w)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.{{u.id}}" name="Cross ARM GNU Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
+								<option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.{{u.id}}" name="Size format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry excluding="{{opts['common']['excluded_folders']}}" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		{% endfor %}
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="{{name}}_emb.com.renesas.cdt.managedbuild.gnuarm.target.elf.{{u.id}}" name="Executable" projectType="com.renesas.cdt.managedbuild.gnuarm.target.elf"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		{% for cfg_key in options %}
+		{% set opts = options[cfg_key] %}	
+		<scannerConfigBuildInfo instanceId="com.renesas.cdt.managedbuild.gnuarm.config.elf.{{opts['id']}}.{{opts['uid']['config']}};com.renesas.cdt.managedbuild.gnuarm.config.elf.{{opts['id']}}.{{opts['uid']['config']}}.;com.renesas.cdt.managedbuild.gnuarm.tool.cpp.compiler.{{opts['uid']['tool_cpp_compiler']}};com.renesas.cdt.managedbuild.gnuarm.tool.cpp.compiler.input.{{opts['uid']['tool_cpp_compiler_input']}}">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		{% endfor %}
+		{% for cfg_key in options %}
+		{% set opts = options[cfg_key] %}	
+		<scannerConfigBuildInfo instanceId="com.renesas.cdt.managedbuild.gnuarm.config.elf.{{opts['id']}}.{{opts['uid']['config']}};com.renesas.cdt.managedbuild.gnuarm.config.elf.{{opts['id']}}.{{opts['uid']['config']}}.;com.renesas.cdt.managedbuild.gnuarm.tool.c.compiler.{{opts['uid']['tool_c_compiler']}};com.renesas.cdt.managedbuild.gnuarm.tool.c.compiler.input.{{opts['uid']['tool_c_compiler_input']}}">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		{% endfor %}
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="refreshScope"/>
+</cproject>
diff --git a/tools/export/e2studio/rz_a1h_gdbinit.tmpl b/tools/export/e2studio/.gdbinit.tmpl
similarity index 100%
rename from tools/export/e2studio/rz_a1h_gdbinit.tmpl
rename to tools/export/e2studio/.gdbinit.tmpl
diff --git a/tools/export/e2studio/__init__.py b/tools/export/e2studio/__init__.py
index 447dee58a8a..dbd0ff818da 100644
--- a/tools/export/e2studio/__init__.py
+++ b/tools/export/e2studio/__init__.py
@@ -14,35 +14,35 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
-from os.path import splitext, basename
+from tools.export.gnuarmeclipse import GNUARMEclipse
 
-from tools.export.exporters import Exporter, deprecated_exporter
-
-@deprecated_exporter
-class E2Studio(Exporter):
+class E2Studio(GNUARMEclipse):
     NAME = 'e2 studio'
     TOOLCHAIN = 'GCC_ARM'
 
     TARGETS = [
         'RZ_A1H',
+        'VK_RZ_A1H',
     ]
 
+    # override
     def generate(self):
-        libraries = []
-        for lib in self.resources.libraries:
-            l, _ = splitext(basename(lib))
-            libraries.append(l[3:])
-
-        ctx = {
-            'name': self.project_name,
-            'include_paths': self.resources.inc_dirs,
-            'linker_script': self.resources.linker_script,
+
+        jinja_ctx = self.collect_tmpl_vars()
             
-            'object_files': self.resources.objects,
-            'libraries': libraries,
-            'symbols': self.toolchain.get_symbols()
-        }
-        self.gen_file('e2studio/%s_project.tmpl' % self.target.lower(), ctx, '.project')
-        self.gen_file('e2studio/%s_cproject.tmpl' % self.target.lower(), ctx, '.cproject')
-        self.gen_file('e2studio/%s_gdbinit.tmpl' % self.target.lower(), ctx, '.gdbinit')
-        self.gen_file('e2studio/launch.tmpl', ctx, '%s OpenOCD.launch' % self.project_name)
+        print
+        print 'Create a e2 studio C++ managed project'
+        print 'Project name: {0}'.format(self.project_name)
+        print 'Target: {0}'.format(self.toolchain.target.name)
+        print 'Toolchain: {0}'.format(self.TOOLCHAIN)
+
+        self.gen_file('e2studio/.cproject.tmpl', jinja_ctx, '.cproject', trim_blocks=True, lstrip_blocks=True)
+        self.gen_file('e2studio/.gdbinit.tmpl', jinja_ctx, '.gdbinit')
+        self.gen_file('e2studio/launch.tmpl', jinja_ctx, '%s OpenOCD.launch' % self.project_name, trim_blocks=True, lstrip_blocks=True)
+
+        self.gen_file('gnuarmeclipse/.project.tmpl', jinja_ctx, '.project', trim_blocks=True, lstrip_blocks=True)
+        self.gen_file('gnuarmeclipse/mbedignore.tmpl', jinja_ctx, '.mbedignore')
+        self.gen_file('gnuarmeclipse/makefile.targets.tmpl', jinja_ctx, 'makefile.targets', trim_blocks=True, lstrip_blocks=True)
+
+        print
+        print 'Done. Import the project located at \'{0}\' in e2 studio.'.format(self.project_name)
diff --git a/tools/export/e2studio/rz_a1h_cproject.tmpl b/tools/export/e2studio/rz_a1h_cproject.tmpl
deleted file mode 100644
index d54ad2f337b..00000000000
--- a/tools/export/e2studio/rz_a1h_cproject.tmpl
+++ /dev/null
@@ -1,324 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
-	<storageModule moduleId="org.eclipse.cdt.core.settings">
-		<cconfiguration id="com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.637912026">
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diff --git a/tools/export/e2studio/rz_a1h_project.tmpl b/tools/export/e2studio/rz_a1h_project.tmpl
deleted file mode 100644
index 0bab8dd408e..00000000000
--- a/tools/export/e2studio/rz_a1h_project.tmpl
+++ /dev/null
@@ -1,27 +0,0 @@
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diff --git a/tools/export/e2studio/vk_rz_a1h_cproject.tmpl b/tools/export/e2studio/vk_rz_a1h_cproject.tmpl
deleted file mode 100644
index 85dcd994245..00000000000
--- a/tools/export/e2studio/vk_rz_a1h_cproject.tmpl
+++ /dev/null
@@ -1,318 +0,0 @@
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diff --git a/tools/export/e2studio/vk_rz_a1h_gdbinit.tmpl b/tools/export/e2studio/vk_rz_a1h_gdbinit.tmpl
deleted file mode 100644
index a59f78c10cd..00000000000
--- a/tools/export/e2studio/vk_rz_a1h_gdbinit.tmpl
+++ /dev/null
@@ -1,29 +0,0 @@
-define hook-step
-mon cortex_a maskisr on
-end
-
-define hook-stepi
-mon cortex_a maskisr on
-end
-
-define hook-next
-mon cortex_a maskisr on
-end
-
-define hook-nexti
-mon cortex_a maskisr on
-end
-
-define hook-finish
-mon cortex_a maskisr on
-end
-
-define hook-stop
-mon cortex_a maskisr off
-end
-
-define hook-kill
-mon reset init
-end
-
-set mem inaccessible-by-default off
\ No newline at end of file
diff --git a/tools/export/e2studio/vk_rz_a1h_project.tmpl b/tools/export/e2studio/vk_rz_a1h_project.tmpl
deleted file mode 100644
index 0bab8dd408e..00000000000
--- a/tools/export/e2studio/vk_rz_a1h_project.tmpl
+++ /dev/null
@@ -1,27 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
-	<name>{{name}}</name>
-	<comment>This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-e2studio</comment>
-	<projects>
-	</projects>
-	<buildSpec>
-		<buildCommand>
-			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
-			<triggers>clean,full,incremental,</triggers>
-			<arguments>
-			</arguments>
-		</buildCommand>
-		<buildCommand>
-			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
-			<triggers>full,incremental,</triggers>
-			<arguments>
-			</arguments>
-		</buildCommand>
-	</buildSpec>
-	<natures>
-		<nature>org.eclipse.cdt.core.cnature</nature>
-		<nature>org.eclipse.cdt.core.ccnature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
-	</natures>
-</projectDescription>
diff --git a/tools/export/gnuarmeclipse/__init__.py b/tools/export/gnuarmeclipse/__init__.py
index 3a6f480d735..5d4dcc8b7d9 100644
--- a/tools/export/gnuarmeclipse/__init__.py
+++ b/tools/export/gnuarmeclipse/__init__.py
@@ -126,19 +126,13 @@ def toolchain_flags(self, toolchain):
             flags['cxx_flags'] += header_options
         return flags
 
-    # override
-    def generate(self):
-        """
-        Generate the .project and .cproject files.
-        """
+    def validate_resources(self):
         if not self.resources.linker_script:
             raise NotSupportedException("No linker script found.")
 
-        print
-        print 'Create a GNU ARM Eclipse C++ managed project'
-        print 'Project name: {0}'.format(self.project_name)
-        print 'Target: {0}'.format(self.toolchain.target.name)
-        print 'Toolchain: {0}'.format(self.TOOLCHAIN)
+    def create_jinja_ctx(self):
+
+        self.validate_resources()
 
         self.resources.win_to_unix()
 
@@ -250,7 +244,7 @@ def generate(self):
             opts['ld']['system_libraries'] = self.system_libraries
             opts['ld']['script'] = join(id.capitalize(),
                                         "linker-script-%s.ld" % id)
-            opts['cpp_cmd'] = " ".join(toolchain.preproc)
+            opts['cpp_cmd'] = '"{}"'.format(toolchain.preproc[0]) + " " + " ".join(toolchain.preproc[1:])
 
             # Unique IDs used in multiple places.
             # Those used only once are implemented with {{u.id}}.
@@ -276,6 +270,20 @@ def generate(self):
             # will be called repeatedly, to generate multiple UIDs.
             'u': u,
         }
+        return jinja_ctx
+
+    # override
+    def generate(self):
+        """
+        Generate the .project and .cproject files.
+        """
+        jinja_ctx = self.create_jinja_ctx()
+
+        print
+        print 'Create a GNU ARM Eclipse C++ managed project'
+        print 'Project name: {0}'.format(self.project_name)
+        print 'Target: {0}'.format(self.toolchain.target.name)
+        print 'Toolchain: {0}'.format(self.TOOLCHAIN)
 
         self.gen_file('gnuarmeclipse/.project.tmpl', jinja_ctx,
                       '.project', trim_blocks=True, lstrip_blocks=True)
diff --git a/tools/export/iar/iar_definitions.json b/tools/export/iar/iar_definitions.json
index be9069d40a6..ac1861727e4 100644
--- a/tools/export/iar/iar_definitions.json
+++ b/tools/export/iar/iar_definitions.json
@@ -1,4 +1,7 @@
 {
+    "STM32L496ZG": {
+        "OGChipSelectEditMenu": "STM32L496ZG\tST STM32L496ZG"
+    },
     "STM32L476VG": {
         "OGChipSelectEditMenu": "STM32L476VG\tST STM32L476VG"
     },
@@ -23,6 +26,12 @@
     "STM32L476RG": {
         "OGChipSelectEditMenu": "STM32L476RG\tST STM32L476RG"
     },
+    "STM32L486RG": {
+        "OGChipSelectEditMenu": "STM32L486RG\tST STM32L486RG"
+    },
+    "STM32L476JG": {
+        "OGChipSelectEditMenu": "STM32L476JG\tST STM32L476JG"
+    },
     "STM32L011K4": {
         "OGChipSelectEditMenu": "STM32L011x4\tST STM32L011x4"
     },
@@ -68,8 +77,8 @@
     "LPC54114J256BD64": {
         "OGChipSelectEditMenu": "LPC54114J256_M4\tNXP LPC54114J256_M4"
     },
-    "LPC54608J512ET180": {
-        "OGChipSelectEditMenu": "LPC54608J512\tNXP LPC54608J512"
+    "LPC54618J512ET180": {
+        "OGChipSelectEditMenu": "LPC54618J512\tNXP LPC54618J512"
     },
     "STM32F072RB": {
         "OGChipSelectEditMenu": "STM32F072RB\tST STM32F072RB"
@@ -104,6 +113,9 @@
     "LPC1768": {
         "OGChipSelectEditMenu": "LPC1768\tNXP LPC1768"
     },
+    "LPC1769": {
+        "OGChipSelectEditMenu": "LPC1769\tNXP LPC1769"
+    },
     "STM32F446RE": {
         "OGChipSelectEditMenu": "STM32F446RE\tST STM32F446RE"
     },
@@ -228,5 +240,10 @@
         "CExtraOptionsCheck": 1,
         "CExtraOptions": "--drv_vector_table_base=0x0",
         "CMSISDAPJtagSpeedList": 10
+    },
+    "TMPM066FWUG":{
+        "OGChipSelectEditMenu": "TMPM066FWUG\tToshiba TMPM066FWUG",
+        "GFPUCoreSlave": 21,
+        "GBECoreSlave": 21
     }
 }
diff --git a/tools/export/makefile/Makefile.tmpl b/tools/export/makefile/Makefile.tmpl
index ed49fecd726..52a3d3d42bc 100644
--- a/tools/export/makefile/Makefile.tmpl
+++ b/tools/export/makefile/Makefile.tmpl
@@ -97,20 +97,26 @@ all: $(PROJECT).bin $(PROJECT)-combined.hex size
 all: $(PROJECT).bin $(PROJECT).hex size
 {% endif %}
 
-.asm.o:
-	+@$(call MAKEDIR,$(dir $@))
-	+@echo "Assemble: $(notdir $<)"
-	@$(AS) -c $(ASM_FLAGS) $(INCLUDE_PATHS) -o $@ $<
-
 .s.o:
 	+@$(call MAKEDIR,$(dir $@))
 	+@echo "Assemble: $(notdir $<)"
-	@$(AS) -c $(ASM_FLAGS) $(INCLUDE_PATHS) -o $@ $<
+  {% if needs_asm_preproc %}
+	@$(AS) -c $(ASM_FLAGS) -E -o $(@:.o=.E.s) $<
+	@$(AS) -c $(ASM_FLAGS) -o $@ $(@:.o=.E.s)
+  {% else %}
+	@$(AS) -c $(ASM_FLAGS) -o $@ $<
+  {% endif %}
+
 
 .S.o:
 	+@$(call MAKEDIR,$(dir $@))
 	+@echo "Assemble: $(notdir $<)"
-	@$(AS) -c $(ASM_FLAGS) $(INCLUDE_PATHS) -o $@ $<
+  {% if needs_asm_preproc %}
+	@$(AS) -c $(ASM_FLAGS) -E -o $(@:.o=.E.s) $<
+	@$(AS) -c $(ASM_FLAGS) -o $@ $(@:.o=.E.s)
+  {% else %}
+	@$(AS) -c $(ASM_FLAGS) -o $@ $<
+  {% endif %}
 
 .c.o:
 	+@$(call MAKEDIR,$(dir $@))
diff --git a/tools/export/makefile/__init__.py b/tools/export/makefile/__init__.py
index 247271aed39..cab92260f97 100644
--- a/tools/export/makefile/__init__.py
+++ b/tools/export/makefile/__init__.py
@@ -35,6 +35,8 @@ class Makefile(Exporter):
 
     MBED_CONFIG_HEADER_SUPPORTED = True
 
+    PREPROCESS_ASM = False
+
     POST_BINARY_WHITELIST = set([
         "MCU_NRF51Code.binary_hook",
         "TEENSY3_1Code.binary_hook",
@@ -96,6 +98,7 @@ def generate(self):
             'link_script_ext': self.toolchain.LINKER_EXT,
             'link_script_option': self.LINK_SCRIPT_OPTION,
             'user_library_flag': self.USER_LIBRARY_FLAG,
+            'needs_asm_preproc': self.PREPROCESS_ASM,
         }
 
         if hasattr(self.toolchain, "preproc"):
@@ -225,7 +228,7 @@ def prepare_sys_lib(libname):
 
     def generate(self):
         if self.resources.linker_script:
-            new_script = self.toolchain.make_real_scatter(
+            new_script = self.toolchain.correct_scatter_shebang(
                 self.resources.linker_script)
             if new_script is not self.resources.linker_script:
                 self.resources.linker_script = new_script
@@ -236,6 +239,7 @@ class Armc5(Arm):
     """ARM Compiler 5 (armcc) specific makefile target"""
     NAME = 'Make-ARMc5'
     TOOLCHAIN = "ARM"
+    PREPROCESS_ASM = True
 
 class Armc6(Arm):
     """ARM Compiler 6 (armclang) specific generic makefile target"""
diff --git a/tools/export/mcuxpresso/LPC54608_cproject.tmpl b/tools/export/mcuxpresso/LPC546XX_cproject.tmpl
similarity index 100%
rename from tools/export/mcuxpresso/LPC54608_cproject.tmpl
rename to tools/export/mcuxpresso/LPC546XX_cproject.tmpl
diff --git a/tools/export/sw4stm32/__init__.py b/tools/export/sw4stm32/__init__.py
index 8ed4fdcc578..9d55dae8fef 100644
--- a/tools/export/sw4stm32/__init__.py
+++ b/tools/export/sw4stm32/__init__.py
@@ -1,6 +1,6 @@
 """
 mbed SDK
-Copyright (c) 2011-2016 ARM Limited
+Copyright (c) 2011-2017 ARM Limited
 
 Licensed under the Apache License, Version 2.0 (the "License");
 you may not use this file except in compliance with the License.
@@ -14,109 +14,523 @@
 See the License for the specific language governing permissions and
 limitations under the License.
 """
+
 from os.path import splitext, basename, join
-from random import randint
 from tools.utils import mkdir
-from tools.export.exporters import Exporter
+from tools.export.gnuarmeclipse import GNUARMEclipse
+from tools.export.gnuarmeclipse import UID
+from tools.build_api import prepare_toolchain
+from sys import flags, platform
+
+# Global random number generator instance.
+u = UID()
 
 
-class Sw4STM32(Exporter):
+class Sw4STM32(GNUARMEclipse):
+    """
+    Sw4STM32 class
+    """
     NAME = 'Sw4STM32'
     TOOLCHAIN = 'GCC_ARM'
 
     BOARDS = {
-        'B96B_F446VE':             {'name': 'B96B-F446VE',           'mcuId': 'STM32F446VETx'},
-        'DISCO_F051R8':            {'name': 'STM32F0DISCOVERY',      'mcuId': 'STM32F051R8Tx'},
-        'DISCO_F303VC':            {'name': 'STM32F3DISCOVERY',      'mcuId': 'STM32F303VCTx'},
-        'DISCO_F334C8':            {'name': 'STM32F3348DISCOVERY',   'mcuId': 'STM32F334C8Tx'},
-        'DISCO_F401VC':            {'name': 'STM32F401C-DISCO',      'mcuId': 'STM32F401VCTx'},
-        'DISCO_F407VG':            {'name': 'STM32F4DISCOVERY',      'mcuId': 'STM32F407VGTx'},
-        'DISCO_F413ZH':            {'name': 'DISCO_F413',            'mcuId': 'STM32F413ZHTx'},
-        'DISCO_F429ZI':            {'name': 'STM32F429I-DISCO',      'mcuId': 'STM32F429ZITx'},
-        'DISCO_F469NI':            {'name': 'DISCO-F469NI',          'mcuId': 'STM32F469NIHx'},
-        'DISCO_F746NG':            {'name': 'STM32F746G-DISCO',      'mcuId': 'STM32F746NGHx'},
-        'DISCO_F769NI':            {'name': 'DISCO-F769NI',          'mcuId': 'STM32F769NIHx'},
-        'DISCO_L053C8':            {'name': 'STM32L0538DISCOVERY',   'mcuId': 'STM32L053C8Tx'},
-        'DISCO_L072CZ_LRWAN1':     {'name': 'DISCO-L072CZ-LRWAN1',   'mcuId': 'STM32L072CZTx'},
-        'DISCO_L475VG_IOT01A':     {'name': 'STM32L475G-DISCO',      'mcuId': 'STM32L475VGTx'},
-        'DISCO_L476VG':            {'name': 'STM32L476G-DISCO',      'mcuId': 'STM32L476VGTx'},
-        'NUCLEO_F030R8':           {'name': 'NUCLEO-F030R8',         'mcuId': 'STM32F030R8Tx'},
-        'NUCLEO_F031K6':           {'name': 'NUCLEO-F031K6',         'mcuId': 'STM32F031K6Tx'},
-        'NUCLEO_F042K6':           {'name': 'NUCLEO-F042K6',         'mcuId': 'STM32F042K6Tx'},
-        'NUCLEO_F070RB':           {'name': 'NUCLEO-F070RB',         'mcuId': 'STM32F070RBTx'},
-        'NUCLEO_F072RB':           {'name': 'NUCLEO-F072RB',         'mcuId': 'STM32F072RBTx'},
-        'NUCLEO_F091RC':           {'name': 'NUCLEO-F091RC',         'mcuId': 'STM32F091RCTx'},
-        'NUCLEO_F103RB':           {'name': 'NUCLEO-F103RB',         'mcuId': 'STM32F103RBTx'},
-        'NUCLEO_F207ZG':           {'name': 'NUCLEO-F207ZG',         'mcuId': 'STM32F207ZGTx'},
-        'NUCLEO_F302R8':           {'name': 'NUCLEO-F302R8',         'mcuId': 'STM32F302R8Tx'},
-        'NUCLEO_F303K8':           {'name': 'NUCLEO-F303K8',         'mcuId': 'STM32F303K8Tx'},
-        'NUCLEO_F303RE':           {'name': 'NUCLEO-F303RE',         'mcuId': 'STM32F303RETx'},
-        'NUCLEO_F303ZE':           {'name': 'NUCLEO-F303ZE',         'mcuId': 'STM32F303ZETx'},
-        'NUCLEO_F334R8':           {'name': 'NUCLEO-F334R8',         'mcuId': 'STM32F334R8Tx'},
-        'NUCLEO_F401RE':           {'name': 'NUCLEO-F401RE',         'mcuId': 'STM32F401RETx'},
-        'NUCLEO_F410RB':           {'name': 'NUCLEO-F410RB',         'mcuId': 'STM32F410RBTx'},
-        'NUCLEO_F411RE':           {'name': 'NUCLEO-F411RE',         'mcuId': 'STM32F411RETx'},
-        'NUCLEO_F429ZI':           {'name': 'NUCLEO-F429ZI',         'mcuId': 'STM32F429ZITx'},
-        'NUCLEO_F446RE':           {'name': 'NUCLEO-F446RE',         'mcuId': 'STM32F446RETx'},
-        'NUCLEO_F446ZE':           {'name': 'NUCLEO-F446ZE',         'mcuId': 'STM32F446ZETx'},
-        'NUCLEO_F746ZG':           {'name': 'NUCLEO-F746ZG',         'mcuId': 'STM32F746ZGTx'},
-        'NUCLEO_F767ZI':           {'name': 'NUCLEO-F767ZI',         'mcuId': 'STM32F767ZITx'},
-        'NUCLEO_L011K4':           {'name': 'NUCLEO-L011K4',         'mcuId': 'STM32L011K4Tx'},
-        'NUCLEO_L031K6':           {'name': 'NUCLEO-L031K6',         'mcuId': 'STM32L031K6Tx'},
-        'NUCLEO_L053R8':           {'name': 'NUCLEO-L053R8',         'mcuId': 'STM32L053R8Tx'},
-        'NUCLEO_L073RZ':           {'name': 'NUCLEO-L073RZ',         'mcuId': 'STM32L073RZTx'},
-        'NUCLEO_L152RE':           {'name': 'NUCLEO-L152RE',         'mcuId': 'STM32L152RETx'},
-        'NUCLEO_L432KC':           {'name': 'NUCLEO-L432KC',         'mcuId': 'STM32L432KCUx'},
-        'NUCLEO_L476RG':           {'name': 'NUCLEO-L476RG',         'mcuId': 'STM32L476RGTx'},
+        'B96B_F446VE':
+        {
+            'name': 'B96B-F446VE',
+            'mcuId': 'STM32F446VETx'
+        },
+        'DISCO_F051R8':
+        {
+            'name': 'STM32F0DISCOVERY',
+            'mcuId': 'STM32F051R8Tx'
+        },
+        'DISCO_F303VC':
+        {
+            'name': 'STM32F3DISCOVERY',
+            'mcuId': 'STM32F303VCTx'
+        },
+        'DISCO_F334C8':
+        {
+            'name': 'STM32F3348DISCOVERY',
+            'mcuId': 'STM32F334C8Tx'
+        },
+        'DISCO_F401VC':
+        {
+            'name': 'STM32F401C-DISCO',
+            'mcuId': 'STM32F401VCTx'
+        },
+        'DISCO_F407VG':
+        {
+            'name': 'STM32F4DISCOVERY',
+            'mcuId': 'STM32F407VGTx'
+        },
+        'DISCO_F413ZH':
+        {
+            'name': 'DISCO_F413',
+            'mcuId': 'STM32F413ZHTx'
+        },
+        'DISCO_F429ZI':
+        {
+            'name': 'STM32F429I-DISCO',
+            'mcuId': 'STM32F429ZITx'
+        },
+        'DISCO_F469NI':
+        {
+            'name': 'DISCO-F469NI',
+            'mcuId': 'STM32F469NIHx'
+        },
+        'DISCO_F746NG':
+        {
+            'name': 'STM32F746G-DISCO',
+            'mcuId': 'STM32F746NGHx'
+        },
+        'DISCO_F769NI':
+        {
+            'name': 'DISCO-F769NI',
+            'mcuId': 'STM32F769NIHx'
+        },
+        'DISCO_L053C8':
+        {
+            'name': 'STM32L0538DISCOVERY',
+            'mcuId': 'STM32L053C8Tx'
+        },
+        'DISCO_L072CZ_LRWAN1':
+        {
+            'name': 'DISCO-L072CZ-LRWAN1',
+            'mcuId': 'STM32L072CZTx'
+        },
+        'DISCO_L475VG_IOT01A':
+        {
+            'name': 'STM32L475G-DISCO',
+            'mcuId': 'STM32L475VGTx'
+        },
+        'DISCO_L476VG':
+        {
+            'name': 'STM32L476G-DISCO',
+            'mcuId': 'STM32L476VGTx'
+        },
+        'NUCLEO_F030R8':
+        {
+            'name': 'NUCLEO-F030R8',
+            'mcuId': 'STM32F030R8Tx'
+        },
+        'NUCLEO_F031K6':
+        {
+            'name': 'NUCLEO-F031K6',
+            'mcuId': 'STM32F031K6Tx'
+        },
+        'NUCLEO_F042K6':
+        {
+            'name': 'NUCLEO-F042K6',
+            'mcuId': 'STM32F042K6Tx'
+        },
+        'NUCLEO_F070RB':
+        {
+            'name': 'NUCLEO-F070RB',
+            'mcuId': 'STM32F070RBTx'
+        },
+        'NUCLEO_F072RB':
+        {
+            'name': 'NUCLEO-F072RB',
+            'mcuId': 'STM32F072RBTx'
+        },
+        'NUCLEO_F091RC':
+        {
+            'name': 'NUCLEO-F091RC',
+            'mcuId': 'STM32F091RCTx'
+        },
+        'NUCLEO_F103RB':
+        {
+            'name': 'NUCLEO-F103RB',
+            'mcuId': 'STM32F103RBTx'
+        },
+        'NUCLEO_F207ZG':
+        {
+            'name': 'NUCLEO-F207ZG',
+            'mcuId': 'STM32F207ZGTx'
+        },
+        'NUCLEO_F302R8':
+        {
+            'name': 'NUCLEO-F302R8',
+            'mcuId': 'STM32F302R8Tx'
+        },
+        'NUCLEO_F303K8':
+        {
+            'name': 'NUCLEO-F303K8',
+            'mcuId': 'STM32F303K8Tx'
+        },
+        'NUCLEO_F303RE':
+        {
+            'name': 'NUCLEO-F303RE',
+            'mcuId': 'STM32F303RETx'
+        },
+        'NUCLEO_F303ZE':
+        {
+            'name': 'NUCLEO-F303ZE',
+            'mcuId': 'STM32F303ZETx'
+        },
+        'NUCLEO_F334R8':
+        {
+            'name': 'NUCLEO-F334R8',
+            'mcuId': 'STM32F334R8Tx'
+        },
+        'NUCLEO_F401RE':
+        {
+            'name': 'NUCLEO-F401RE',
+            'mcuId': 'STM32F401RETx'
+        },
+        'NUCLEO_F410RB':
+        {
+            'name': 'NUCLEO-F410RB',
+            'mcuId': 'STM32F410RBTx'
+        },
+        'NUCLEO_F411RE':
+        {
+            'name': 'NUCLEO-F411RE',
+            'mcuId': 'STM32F411RETx'
+        },
+        'NUCLEO_F429ZI':
+        {
+            'name': 'NUCLEO-F429ZI',
+            'mcuId': 'STM32F429ZITx'
+        },
+        'NUCLEO_F446RE':
+        {
+            'name': 'NUCLEO-F446RE',
+            'mcuId': 'STM32F446RETx'
+        },
+        'NUCLEO_F446ZE':
+        {
+            'name': 'NUCLEO-F446ZE',
+            'mcuId': 'STM32F446ZETx'
+        },
+        'NUCLEO_F746ZG':
+        {
+            'name': 'NUCLEO-F746ZG',
+            'mcuId': 'STM32F746ZGTx'
+        },
+        'NUCLEO_F767ZI':
+        {
+            'name': 'NUCLEO-F767ZI',
+            'mcuId': 'STM32F767ZITx'
+        },
+        'NUCLEO_L011K4':
+        {
+            'name': 'NUCLEO-L011K4',
+            'mcuId': 'STM32L011K4Tx'
+        },
+        'NUCLEO_L031K6':
+        {
+            'name': 'NUCLEO-L031K6',
+            'mcuId': 'STM32L031K6Tx'
+        },
+        'NUCLEO_L053R8':
+        {
+            'name': 'NUCLEO-L053R8',
+            'mcuId': 'STM32L053R8Tx'
+        },
+        'NUCLEO_L073RZ':
+        {
+            'name': 'NUCLEO-L073RZ',
+            'mcuId': 'STM32L073RZTx'
+        },
+        'NUCLEO_L152RE':
+        {
+            'name': 'NUCLEO-L152RE',
+            'mcuId': 'STM32L152RETx'
+        },
+        'NUCLEO_L432KC':
+        {
+            'name': 'NUCLEO-L432KC',
+            'mcuId': 'STM32L432KCUx'
+        },
+        'NUCLEO_L476RG':
+        {
+            'name': 'NUCLEO-L476RG',
+            'mcuId': 'STM32L476RGTx'
+        },
+        'NUCLEO_L486RG':
+        {
+            'name': 'NUCLEO-L486RG',
+            'mcuId': 'STM32L486RGTx'
+        },
+        'NUCLEO_L496ZG':
+        {
+            'name': 'NUCLEO-L496ZG',
+            'mcuId': 'STM32L496ZGTx'
+        },        
+        'NUCLEO_L496ZG_P':
+        {
+            'name': 'NUCLEO-L496ZG',
+            'mcuId': 'STM32L496ZGTx'
+        },
     }
 
     TARGETS = BOARDS.keys()
 
-    def __gen_dir(self, dirname):
-        settings = join(self.export_dir, dirname)
+    def __gen_dir(self, dir_name):
+        """
+        Method that creates directory
+        """
+        settings = join(self.export_dir, dir_name)
         mkdir(settings)
 
-    def __generate_uid(self):
-        return "%0.9u" % randint(0, 999999999)
+    def get_fpu_hardware(self, fpu_unit):
+        """
+        Convert fpu unit name into hardware name.
+        """
+        hw = ''
+        fpus = {
+            'fpv4spd16': 'fpv4-sp-d16',
+            'fpv5d16': 'fpv5-d16',
+            'fpv5spd16': 'fpv5-sp-d16'
+        }
+        if fpu_unit in fpus:
+            hw = fpus[fpu_unit]
+        return hw
+
+    def process_sw_options(self, opts, flags_in):
+        """
+        Process System Workbench specific options.
+
+        System Workbench for STM32 has some compile options, which are not recognized by the GNUARMEclipse exporter.
+        Those are handled in this method.
+        """
+        opts['c']['preprocess'] = False
+        if '-E' in flags_in['c_flags']:
+            opts['c']['preprocess'] = True
+        opts['cpp']['preprocess'] = False
+        if '-E' in flags_in['cxx_flags']:
+            opts['cpp']['preprocess'] = True
+        opts['c']['slowflashdata'] = False
+        if '-mslow-flash-data' in flags_in['c_flags']:
+            opts['c']['slowflashdata'] = True
+        opts['cpp']['slowflashdata'] = False
+        if '-mslow-flash-data' in flags_in['cxx_flags']:
+            opts['cpp']['slowflashdata'] = True
+        if opts['common']['optimization.messagelength']:
+            opts['common']['optimization.other'] += ' -fmessage-length=0'
+        if opts['common']['optimization.signedchar']:
+            opts['common']['optimization.other'] += ' -fsigned-char'
+        if opts['common']['optimization.nocommon']:
+            opts['common']['optimization.other'] += ' -fno-common'
+        if opts['common']['optimization.noinlinefunctions']:
+            opts['common']['optimization.other'] += ' -fno-inline-functions'
+        if opts['common']['optimization.freestanding']:
+            opts['common']['optimization.other'] += ' -ffreestanding'
+        if opts['common']['optimization.nobuiltin']:
+            opts['common']['optimization.other'] += ' -fno-builtin'
+        if opts['common']['optimization.spconstant']:
+            opts['common']['optimization.other'] += ' -fsingle-precision-constant'
+        if opts['common']['optimization.nomoveloopinvariants']:
+            opts['common']['optimization.other'] += ' -fno-move-loop-invariants'
+        if opts['common']['warnings.unused']:
+            opts['common']['warnings.other'] += ' -Wunused'
+        if opts['common']['warnings.uninitialized']:
+            opts['common']['warnings.other'] += ' -Wuninitialized'
+        if opts['common']['warnings.missingdeclaration']:
+            opts['common']['warnings.other'] += ' -Wmissing-declarations'
+        if opts['common']['warnings.pointerarith']:
+            opts['common']['warnings.other'] += ' -Wpointer-arith'
+        if opts['common']['warnings.padded']:
+            opts['common']['warnings.other'] += ' -Wpadded'
+        if opts['common']['warnings.shadow']:
+            opts['common']['warnings.other'] += ' -Wshadow'
+        if opts['common']['warnings.logicalop']:
+            opts['common']['warnings.other'] += ' -Wlogical-op'
+        if opts['common']['warnings.agreggatereturn']:
+            opts['common']['warnings.other'] += ' -Waggregate-return'
+        if opts['common']['warnings.floatequal']:
+            opts['common']['warnings.other'] += ' -Wfloat-equal'
+        opts['ld']['strip'] = False
+        if '-s' in flags_in['ld_flags']:
+            opts['ld']['strip'] = True
+        opts['ld']['shared'] = False
+        if '-shared' in flags_in['ld_flags']:
+            opts['ld']['shared'] = True
+        opts['ld']['soname'] = ''
+        opts['ld']['implname'] = ''
+        opts['ld']['defname'] = ''
+        for item in flags_in['ld_flags']:
+            if item.startswith('-Wl,-soname='):
+                opts['ld']['soname'] = item[len('-Wl,-soname='):]
+            if item.startswith('-Wl,--out-implib='):
+                opts['ld']['implname'] = item[len('-Wl,--out-implib='):]
+            if item.startswith('-Wl,--output-def='):
+                opts['ld']['defname'] = item[len('-Wl,--output-def='):]
+        opts['common']['arm.target.fpu.hardware'] = self.get_fpu_hardware(
+            opts['common']['arm.target.fpu.unit'])
+        opts['common']['debugging.codecov'] = False
+        if '-fprofile-arcs' in flags_in['common_flags'] and '-ftest-coverage' in flags_in['common_flags']:
+            opts['common']['debugging.codecov'] = True
+        # Passing linker options to linker with '-Wl,'-prefix.
+        for index in range(len(opts['ld']['flags'])):
+            item = opts['ld']['flags'][index]
+            if not item.startswith('-Wl,'):
+                opts['ld']['flags'][index] = '-Wl,' + item
+        # Strange System Workbench feature: If first parameter in Other flags is a
+        # define (-D...), Other flags will be replaced by defines and other flags
+        # are completely ignored. Moving -D parameters to defines.
+        for compiler in ['c', 'cpp', 'as']:
+            tmpList = opts[compiler]['other'].split(' ')
+            otherList = []
+            for item in tmpList:
+                if item.startswith('-D'):
+                    opts[compiler]['defines'].append(str(item[2:]))
+                else:
+                    otherList.append(item)
+            opts[compiler]['other'] = ' '.join(otherList)
+        # Assembler options
+        for as_def in opts['as']['defines']:
+            if '=' in as_def:
+                opts['as']['other'] += ' --defsym ' + as_def
+            else:
+                opts['as']['other'] += ' --defsym ' + as_def + '=1'
 
     def generate(self):
-        fp_hardware = "no"
-        fp_abi = "soft"
-        core = self.toolchain.target.core
-        if core == "Cortex-M4F" or core == "Cortex-M7F":
-            fp_hardware = "fpv4-sp-d16"
-            fp_abi = "soft-fp"
-        elif core == "Cortex-M7FD":
-            fp_hardware = "fpv5-d16"
-            fp_abi = "soft-fp"
-            
+        """
+        Generate the .project and .cproject files.
+        """
+        options = {}
+
+        if not self.resources.linker_script:
+            raise NotSupportedException("No linker script found.")
+
+        print ('\nCreate a System Workbench for STM32 managed project')
+        print ('Project name: {0}'.format(self.project_name))
+        print ('Target:       {0}'.format(self.toolchain.target.name))
+        print ('Toolchain:    {0}'.format(self.TOOLCHAIN) + '\n')
+
+        self.resources.win_to_unix()
+
+        config_header = self.filter_dot(self.toolchain.get_config_header())
+
         libraries = []
         for lib in self.resources.libraries:
-            l, _ = splitext(basename(lib))
-            libraries.append(l[3:])
+            library, _ = splitext(basename(lib))
+            libraries.append(library[3:])
+
+        self.system_libraries = [
+            'stdc++', 'supc++', 'm', 'c', 'gcc', 'nosys'
+        ]
+
+        profiles = self.get_all_profiles()
+        self.as_defines = [s.replace('"', '&quot;')
+                           for s in self.toolchain.get_symbols(True)]
+        self.c_defines = [s.replace('"', '&quot;')
+                          for s in self.toolchain.get_symbols()]
+        self.cpp_defines = self.c_defines
+        print 'Symbols: {0}'.format(len(self.c_defines))
+
+        self.include_path = []
+        for s in self.resources.inc_dirs:
+            self.include_path.append("../" + self.filter_dot(s))
+        print ('Include folders: {0}'.format(len(self.include_path)))
+
+        self.compute_exclusions()
+
+        print ('Exclude folders: {0}'.format(len(self.excluded_folders)))
+
+        ld_script = self.filter_dot(self.resources.linker_script)
+        print ('Linker script:   {0}'.format(ld_script))
+
+        lib_dirs = [self.filter_dot(s) for s in self.resources.lib_dirs]
+
+        preproc_cmd = basename(self.toolchain.preproc[0]) + " " + " ".join(self.toolchain.preproc[1:])
+
+        for id in ['debug', 'release']:
+            opts = {}
+            opts['common'] = {}
+            opts['as'] = {}
+            opts['c'] = {}
+            opts['cpp'] = {}
+            opts['ld'] = {}
+
+            opts['id'] = id
+            opts['name'] = opts['id'].capitalize()
+
+            # TODO: Add prints to log or console in verbose mode.
+            #print ('\nBuild configuration: {0}'.format(opts['name']))
+
+            profile = profiles[id]
+
+            # A small hack, do not bother with src_path again,
+            # pass an empty string to avoid crashing.
+            src_paths = ['']
+            toolchain = prepare_toolchain(
+                src_paths, "", self.toolchain.target.name, self.TOOLCHAIN, build_profile=[profile])
+
+            # Hack to fill in build_dir
+            toolchain.build_dir = self.toolchain.build_dir
+
+            flags = self.toolchain_flags(toolchain)
+
+            # TODO: Add prints to log or console in verbose mode.
+            # print 'Common flags:', ' '.join(flags['common_flags'])
+            # print 'C++ flags:', ' '.join(flags['cxx_flags'])
+            # print 'C flags:', ' '.join(flags['c_flags'])
+            # print 'ASM flags:', ' '.join(flags['asm_flags'])
+            # print 'Linker flags:', ' '.join(flags['ld_flags'])
+
+            # Most GNU ARM Eclipse options have a parent,
+            # either debug or release.
+            if '-O0' in flags['common_flags'] or '-Og' in flags['common_flags']:
+                opts['parent_id'] = 'debug'
+            else:
+                opts['parent_id'] = 'release'
+
+            self.process_options(opts, flags)
+
+            opts['c']['defines'] = self.c_defines
+            opts['cpp']['defines'] = self.cpp_defines
+            opts['as']['defines'] = self.as_defines
+
+            self.process_sw_options(opts, flags)
+
+            opts['ld']['library_paths'] = [
+                self.filter_dot(s) for s in self.resources.lib_dirs]
+
+            opts['ld']['user_libraries'] = libraries
+            opts['ld']['system_libraries'] = self.system_libraries
+            opts['ld']['script'] = "linker-script-" + id + ".ld"
+
+            # Unique IDs used in multiple places.
+            uid = {}
+            uid['config'] = u.id
+            uid['tool_c_compiler'] = u.id
+            uid['tool_c_compiler_input'] = u.id
+            uid['tool_cpp_compiler'] = u.id
+            uid['tool_cpp_compiler_input'] = u.id
+
+            opts['uid'] = uid
+
+            options[id] = opts
 
         ctx = {
             'name': self.project_name,
-            'include_paths': self.resources.inc_dirs,
-            'linker_script': self.resources.linker_script,
-            'library_paths': self.resources.lib_dirs,
+            'platform': platform,
+            'include_paths': self.include_path,
+            'config_header': config_header,
+            'exclude_paths': '|'.join(self.excluded_folders),
+            'ld_script': ld_script,
+            'library_paths': lib_dirs,
             'object_files': self.resources.objects,
             'libraries': libraries,
-            'symbols': self.toolchain.get_symbols(),
             'board_name': self.BOARDS[self.target.upper()]['name'],
             'mcu_name': self.BOARDS[self.target.upper()]['mcuId'],
-            'debug_config_uid': self.__generate_uid(),
-            'debug_tool_compiler_uid': self.__generate_uid(),
-            'debug_tool_compiler_input_uid': self.__generate_uid(),
-            'release_config_uid': self.__generate_uid(),
-            'release_tool_compiler_uid': self.__generate_uid(),
-            'release_tool_compiler_input_uid': self.__generate_uid(),
-            'uid': self.__generate_uid(),
-            'floating_point_hardware': fp_hardware,
-            'floating_point_abi': fp_abi
+            'cpp_cmd': preproc_cmd,
+            'options': options,
+            # id property of 'u' will generate new random identifier every time
+            # when called.
+            'u': u
         }
 
         self.__gen_dir('.settings')
-        self.gen_file('sw4stm32/language_settings_commom.tmpl', ctx, '.settings/language.settings.xml')
+        self.gen_file('sw4stm32/language_settings_commom.tmpl',
+                      ctx, '.settings/language.settings.xml')
         self.gen_file('sw4stm32/project_common.tmpl', ctx, '.project')
         self.gen_file('sw4stm32/cproject_common.tmpl', ctx, '.cproject')
+        self.gen_file('sw4stm32/makefile.targets.tmpl', ctx,
+                      'makefile.targets', trim_blocks=True, lstrip_blocks=True)
+        self.gen_file('sw4stm32/launch.tmpl', ctx, self.project_name +
+                      ' ' + options['debug']['name'] + '.launch')
diff --git a/tools/export/sw4stm32/cproject_common.tmpl b/tools/export/sw4stm32/cproject_common.tmpl
index 94f1062f1f2..8453f73e060 100644
--- a/tools/export/sw4stm32/cproject_common.tmpl
+++ b/tools/export/sw4stm32/cproject_common.tmpl
@@ -1,8 +1,10 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
 	<storageModule moduleId="org.eclipse.cdt.core.settings">
-		<cconfiguration id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.{{debug_config_uid}}">
-			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.{{debug_config_uid}}" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+		{% for cfg_id in options %}
+		{% set opts = options[cfg_id] %}
+		<cconfiguration id="fr.ac6.managedbuild.config.gnu.cross.exe.{{cfg_id}}.{{opts['uid']['config']}}">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="fr.ac6.managedbuild.config.gnu.cross.exe.{{cfg_id}}.{{opts['uid']['config']}}" moduleId="org.eclipse.cdt.core.settings" name="{{opts['name']}}">
 				<externalSettings/>
 				<extensions>
 					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
@@ -14,201 +16,300 @@
 				</extensions>
 			</storageModule>
 			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.{{debug_config_uid}}" name="Debug" parent="fr.ac6.managedbuild.config.gnu.cross.exe.debug" postannouncebuildStep="Generating binary and Printing size information:" postbuildStep="arm-none-eabi-objcopy -O binary &quot;${BuildArtifactFileBaseName}.elf&quot; &quot;${BuildArtifactFileBaseName}.bin&quot; &amp;&amp; arm-none-eabi-size &quot;${BuildArtifactFileName}&quot;">
-					<folderInfo id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.{{debug_config_uid}}." name="/" resourcePath="">
-						<toolChain id="fr.ac6.managedbuild.toolchain.gnu.cross.exe.debug.{{uid}}" name="Ac6 STM32 MCU GCC" superClass="fr.ac6.managedbuild.toolchain.gnu.cross.exe.debug">
-							<option id="fr.ac6.managedbuild.option.gnu.cross.mcu.{{uid}}" name="Mcu" superClass="fr.ac6.managedbuild.option.gnu.cross.mcu" value="{{mcu_name}}" valueType="string"/>
-							<option id="fr.ac6.managedbuild.option.gnu.cross.board.{{uid}}" name="Board" superClass="fr.ac6.managedbuild.option.gnu.cross.board" value="{{board_name}}" valueType="string"/>
-							<option id="fr.ac6.managedbuild.option.gnu.cross.fpu.{{uid}}" name="Floating point hardware" superClass="fr.ac6.managedbuild.option.gnu.cross.fpu" value="fr.ac6.managedbuild.option.gnu.cross.fpu.{{floating_point_hardware}}" valueType="enumerated"/>
-							<option id="fr.ac6.managedbuild.option.gnu.cross.floatabi.{{uid}}" name="Floating-point ABI" superClass="fr.ac6.managedbuild.option.gnu.cross.floatabi" value="fr.ac6.managedbuild.option.gnu.cross.floatabi.{{floating_point_abi}}" valueType="enumerated"/>
-							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="fr.ac6.managedbuild.targetPlatform.gnu.cross.{{uid}}" isAbstract="false" osList="all" superClass="fr.ac6.managedbuild.targetPlatform.gnu.cross"/>
-							<builder buildPath="${workspace_loc:/{{name}}}/Debug" id="fr.ac6.managedbuild.builder.gnu.cross.{{uid}}" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="fr.ac6.managedbuild.builder.gnu.cross"/>
-							<tool id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.{{debug_tool_compiler_uid}}" name="MCU GCC Compiler" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler">
-								<option id="fr.ac6.managedbuild.gnu.c.compiler.option.optimization.level.{{uid}}" name="Optimization Level" superClass="fr.ac6.managedbuild.gnu.c.compiler.option.optimization.level" useByScannerDiscovery="false"/>
-								<option id="gnu.c.compiler.option.debugging.level.{{uid}}" name="Debug Level" superClass="gnu.c.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.max" valueType="enumerated"/>
-								<option id="gnu.c.compiler.option.include.paths.{{uid}}" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
+				<configuration artifactExtension="elf" artifactName="${ProjName}-{{cfg_id}}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.{{cfg_id}}" cleanCommand="rm -rf" description="" id="fr.ac6.managedbuild.config.gnu.cross.exe.{{cfg_id}}.{{opts['uid']['config']}}" name="{{opts['name']}}" parent="fr.ac6.managedbuild.config.gnu.cross.exe.{{cfg_id}}" postannouncebuildStep="Generating binary and Printing size information:" postbuildStep="arm-none-eabi-objcopy -O binary &quot;${BuildArtifactFileBaseName}.elf&quot; &quot;${ProjName}.bin&quot; &amp;&amp; arm-none-eabi-size -B &quot;${BuildArtifactFileName}&quot; &amp;&amp; make ldclean" preannouncebuildStep="Creating makefile.defs:" prebuildStep="echo &quot;export PREPROC_CMD = ${openstm32_compiler_path}/${compiler_prefix}cpp -E -P&quot; &gt; ${ProjDirPath}/makefile.defs">
+					<folderInfo id="fr.ac6.managedbuild.config.gnu.cross.exe.{{cfg_id}}.{{opts['uid']['config']}}." name="/" resourcePath="">
+						<toolChain id="fr.ac6.managedbuild.toolchain.gnu.cross.exe.{{cfg_id}}.{{u.id}}" name="Ac6 STM32 MCU GCC" superClass="fr.ac6.managedbuild.toolchain.gnu.cross.exe.{{cfg_id}}">
+							<option id="fr.ac6.managedbuild.option.gnu.cross.mcu.{{u.id}}" name="Mcu" superClass="fr.ac6.managedbuild.option.gnu.cross.mcu" value="{{mcu_name}}" valueType="string"/>
+							<option id="fr.ac6.managedbuild.option.gnu.cross.board.{{u.id}}" name="Board" superClass="fr.ac6.managedbuild.option.gnu.cross.board" value="{{board_name}}" valueType="string"/>
+							{% if opts['common']['arm.target.fpu.hardware'] %}
+							<option id="fr.ac6.managedbuild.option.gnu.cross.fpu.{{u.id}}" name="Floating point hardware" superClass="fr.ac6.managedbuild.option.gnu.cross.fpu" value="fr.ac6.managedbuild.option.gnu.cross.fpu.{{opts['common']['arm.target.fpu.hardware']}}" valueType="enumerated"/>
+							{% endif %}
+							{% if opts['common']['arm.target.fpu.abi'] %}
+							<option id="fr.ac6.managedbuild.option.gnu.cross.floatabi.{{u.id}}" name="Floating-point ABI" superClass="fr.ac6.managedbuild.option.gnu.cross.floatabi" value="fr.ac6.managedbuild.option.gnu.cross.floatabi.{{opts['common']['arm.target.fpu.abi']}}" valueType="enumerated"/>
+							{% endif %}
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="fr.ac6.managedbuild.targetPlatform.gnu.cross.{{u.id}}" isAbstract="false" osList="all" superClass="fr.ac6.managedbuild.targetPlatform.gnu.cross"/>
+							<builder buildPath="${workspace_loc:/{{name}}}/{{opts['name']}}" id="fr.ac6.managedbuild.builder.gnu.cross.{{u.id}}" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="fr.ac6.managedbuild.builder.gnu.cross"/>
+							<tool id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.{{opts['uid']['tool_c_compiler']}}" name="MCU GCC Compiler" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler">
+								{% if cfg_id == 'debug' %}
+								<option id="fr.ac6.managedbuild.gnu.c.compiler.option.optimization.level.{{u.id}}" name="Optimization Level" superClass="fr.ac6.managedbuild.gnu.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="fr.ac6.managedbuild.gnu.c.optimization.level.more" valueType="enumerated"/>
+								<option id="gnu.c.compiler.option.debugging.level.{{u.id}}" name="Debug Level" superClass="gnu.c.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.max" valueType="enumerated"/>
+								{% else %}
+								<option id="fr.ac6.managedbuild.gnu.c.compiler.option.optimization.level.{{u.id}}" name="Optimization Level" superClass="fr.ac6.managedbuild.gnu.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="fr.ac6.managedbuild.gnu.c.optimization.level.most" valueType="enumerated"/>
+								<option id="gnu.c.compiler.option.debugging.level.{{u.id}}" name="Debug Level" superClass="gnu.c.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.none" valueType="enumerated"/>
+								{% endif %}
+								<option id="gnu.c.compiler.option.include.paths.{{u.id}}" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
 									{% for path in include_paths %}
-									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;{{path}}&quot;"/>
 									{% endfor %}
 								</option>
-								<option id="gnu.c.compiler.option.preprocessor.def.symbols.{{uid}}" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" useByScannerDiscovery="false" valueType="definedSymbols">
-									{% for s in symbols %}
+								<option id="gnu.c.compiler.option.preprocessor.def.symbols.{{u.id}}" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" useByScannerDiscovery="false" valueType="definedSymbols">
+									{% for s in opts['c']['defines'] %}
 									<listOptionValue builtIn="false" value="{{s}}"/>
 									{% endfor %}
 								</option>
-								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c.{{release_tool_compiler_input_uid}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c"/>
-								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.s.{{uid}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.s"/>
+								{% if config_header %}
+								<option id="gnu.c.compiler.option.include.files.{{u.id}}" name="Include files (-include)" superClass="gnu.c.compiler.option.include.files" useByScannerDiscovery="false" valueType="includeFiles">
+									<listOptionValue builtIn="false" value="${ProjDirPath}/{{config_header}}"/>
+								</option>
+								{% endif %}
+								{% if 'compiler.std' in opts['c'] %}
+								{% if opts['c']['compiler.std'] == '-ansi' %}
+								<option id="gnu.c.compiler.option.misc.ansi.{{u.id}}" name="Support ANSI programs (-ansi)" superClass="gnu.c.compiler.option.misc.ansi" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% elif opts['c']['compiler.std'] %}
+								<option id="gnu.c.compiler.option.dialect.std.{{u.id}}" superClass="gnu.c.compiler.option.dialect.std" value="gnu.c.compiler.dialect.{{opts['c']['compiler.std']}}" valueType="enumerated"/>
+								<option id="gnu.c.compiler.option.dialect.std.{{u.id}}" name="Language standard" superClass="gnu.c.compiler.option.dialect.std" useByScannerDiscovery="true" value="gnu.c.compiler.dialect.c99" valueType="enumerated"/>
+								{% endif %}
+								{% endif %}
+								{% if opts['common']['warnings.pedantic'] %}
+								<option id="gnu.c.compiler.option.warnings.pedantic.{{u.id}}" name="Pedantic (-pedantic)" superClass="gnu.c.compiler.option.warnings.pedantic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['warnings.pedanticerrors'] %}
+								<option id="gnu.c.compiler.option.warnings.pedantic.error.{{u.id}}" name="Pedantic warnings as errors (-pedantic-errors)" superClass="gnu.c.compiler.option.warnings.pedantic.error" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['nostdinc'] %}
+								<option id="gnu.c.compiler.option.preprocessor.nostdinc.{{u.id}}" name="Do not search system directories (-nostdinc)" superClass="gnu.c.compiler.option.preprocessor.nostdinc" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['preprocess'] %}
+								<option id="gnu.c.compiler.option.preprocessor.preprocess.{{u.id}}" name="Preprocess only (-E)" superClass="gnu.c.compiler.option.preprocessor.preprocess" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}								
+								{% if opts['common']['warnings.syntaxonly'] %}
+								<option id="gnu.c.compiler.option.warnings.syntax.{{u.id}}" name="Check syntax only (-fsyntax-only)" superClass="gnu.c.compiler.option.warnings.syntax" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['warnings.nowarn'] %}
+								<option id="gnu.c.compiler.option.warnings.nowarn.{{u.id}}" name="Inhibit all warnings (-w)" superClass="gnu.c.compiler.option.warnings.nowarn" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['warnings.extrawarn'] %}
+								<option id="gnu.c.compiler.option.warnings.extrawarn.{{u.id}}" name="Extra warnings (-Wextra)" superClass="gnu.c.compiler.option.warnings.extrawarn" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['warnings.toerrors'] %}
+								<option id="gnu.c.compiler.option.warnings.toerrors.{{u.id}}" name="Warnings as errors (-Werror)" superClass="gnu.c.compiler.option.warnings.toerrors" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['warnings.conversion'] %}
+								<option id="gnu.c.compiler.option.warnings.wconversion.{{u.id}}" name="Implicit conversion warnings (-Wconversion)" superClass="gnu.c.compiler.option.warnings.wconversion" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['debugging.prof'] %}
+								<option id="gnu.c.compiler.option.debugging.prof.{{u.id}}" name="Generate prof information (-p)" superClass="gnu.c.compiler.option.debugging.prof" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['debugging.gprof'] %}
+								<option id="gnu.c.compiler.option.debugging.gprof.{{u.id}}" name="Generate gprof information (-pg)" superClass="gnu.c.compiler.option.debugging.gprof" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['debugging.codecov'] %}
+								<option id="gnu.c.compiler.option.debugging.codecov.{{u.id}}" superClass="gnu.c.compiler.option.debugging.codecov" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['verbose'] %}
+								<option id="gnu.c.compiler.option.misc.verbose.{{u.id}}" name="Verbose (-v)" superClass="gnu.c.compiler.option.misc.verbose" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['optimization.PIC'] %}
+								<option id="gnu.c.compiler.option.misc.pic.{{u.id}}" name="Position Independent Code (-fPIC)" superClass="gnu.c.compiler.option.misc.pic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['optimization.datasections'] %}
+								<option id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.fdata.{{u.id}}" name="Place the data in their own section (-fdata-sections)" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.fdata" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['optimization.functionsections'] %}
+								<option id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.ffunction.{{u.id}}" name="Place the function in their own section (-ffunction-sections)" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.ffunction" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['otheroptimizations'] != '' or opts['common']['optimization.other'] != '' %}
+								<option id="gnu.c.compiler.option.optimization.flags.{{u.id}}" superClass="gnu.c.compiler.option.optimization.flags" useByScannerDiscovery="false" value="{{opts['c']['otheroptimizations']}} {{opts['common']['optimization.other']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['c']['other'] != '' or opts['c']['otherwarnings'] != '' or opts['common']['warnings.other'] != '' %}
+								<option id="fr.ac6.managedbuid.gnu.c.compiler.option.misc.other.{{u.id}}" name="Other flags" superClass="fr.ac6.managedbuid.gnu.c.compiler.option.misc.other" useByScannerDiscovery="false" value="{{opts['c']['other']}} {{opts['c']['otherwarnings']}} {{opts['common']['warnings.other']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['c']['slowflashdata'] %}
+								<option id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.pcrop.{{u.id}}" name="No data reads in code memory (-mslow-flash-data) " superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.pcrop" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c.{{opts['uid']['tool_c_compiler_input']}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c"/>
+								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.s.{{u.id}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.s"/>
 							</tool>
-							<tool id="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.{{uid}}" name="MCU G++ Compiler" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler">
-								<option id="fr.ac6.managedbuild.gnu.cpp.compiler.option.optimization.level.{{uid}}" name="Optimization Level" superClass="fr.ac6.managedbuild.gnu.cpp.compiler.option.optimization.level" useByScannerDiscovery="false"/>
-								<option id="gnu.cpp.compiler.option.debugging.level.{{uid}}" name="Debug Level" superClass="gnu.cpp.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.debugging.level.max" valueType="enumerated"/>
-								<option id="gnu.cpp.compiler.option.include.paths.{{uid}}" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
+							<tool id="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.{{opts['uid']['tool_cpp_compiler']}}" name="MCU G++ Compiler" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler">
+								{% if cfg_id == 'debug' %}
+								<option id="fr.ac6.managedbuild.gnu.cpp.compiler.option.optimization.level.{{u.id}}" name="Optimization Level" superClass="fr.ac6.managedbuild.gnu.cpp.compiler.option.optimization.level" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.debugging.level.{{u.id}}" name="Debug Level" superClass="gnu.cpp.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.debugging.level.max" valueType="enumerated"/>
+								{% else %}
+								<option id="fr.ac6.managedbuild.gnu.cpp.compiler.option.optimization.level.{{u.id}}" name="Optimization Level" superClass="fr.ac6.managedbuild.gnu.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="fr.ac6.managedbuild.gnu.cpp.optimization.level.most" valueType="enumerated"/>
+								<option id="gnu.cpp.compiler.option.debugging.level.{{u.id}}" name="Debug Level" superClass="gnu.cpp.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.debugging.level.none" valueType="enumerated"/>
+								{% endif %}
+								<option id="gnu.cpp.compiler.option.include.paths.{{u.id}}" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
 									{% for path in include_paths %}
-									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;{{path}}&quot;"/>
 									{% endfor %}
 								</option>
-								<option id="gnu.cpp.compiler.option.dialect.std.{{uid}}" superClass="gnu.cpp.compiler.option.dialect.std" value="gnu.cpp.compiler.dialect.default" valueType="enumerated"/>
-								<option id="gnu.cpp.compiler.option.preprocessor.def{{uid}}" superClass="gnu.cpp.compiler.option.preprocessor.def" valueType="definedSymbols">
-								{% for s in symbols %}
+								<option id="gnu.cpp.compiler.option.preprocessor.def.{{u.id}}" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" valueType="definedSymbols">
+								{% for s in opts['cpp']['defines'] %}
 									<listOptionValue builtIn="false" value="{{s}}"/>
 								{% endfor %}
 								</option>
-								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.input.cpp.{{uid}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.input.cpp"/>
-								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.input.s.{{uid}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.input.s"/>
-							</tool>
-							<tool id="fr.ac6.managedbuild.tool.gnu.cross.c.linker.{{uid}}" name="MCU GCC Linker" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.linker">
-								<inputType id="cdt.managedbuild.tool.gnu.c.linker.input.{{uid}}" superClass="cdt.managedbuild.tool.gnu.c.linker.input">
-									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
-									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
-								</inputType>
+								{% if config_header %}
+								<option id="gnu.cpp.compiler.option.include.files.{{u.id}}" name="Include files (-include)" superClass="gnu.cpp.compiler.option.include.files" useByScannerDiscovery="false" valueType="includeFiles">
+									<listOptionValue builtIn="false" value="${ProjDirPath}/{{config_header}}"/>
+								</option>
+								{% endif %}
+								{% if 'compiler.std' in opts['cpp'] %}
+								{% if opts['cpp']['compiler.std'] %}
+								<option id="gnu.cpp.compiler.option.dialect.std.{{u.id}}" name="Language standard" superClass="gnu.cpp.compiler.option.dialect.std" useByScannerDiscovery="true" value="gnu.cpp.compiler.dialect.{{opts['c']['compiler.std']}}" valueType="enumerated"/>
+								{% endif %}
+								{% endif %}
+								{% if opts['common']['warnings.pedantic'] %}
+								<option id="gnu.cpp.compiler.option.warnings.pedantic.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.pedantic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['warnings.pedanticerrors'] %}
+								<option id="gnu.cpp.compiler.option.warnings.pedantic.error.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.pedantic.error" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['nostdinc'] %}
+								<option id="gnu.cpp.compiler.option.preprocessor.nostdinc.{{u.id}}" superClass="gnu.cpp.compiler.option.preprocessor.nostdinc" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['preprocess'] %}
+								<option id="gnu.cpp.compiler.option.preprocessor.preprocess.{{u.id}}" superClass="gnu.cpp.compiler.option.preprocessor.preprocess" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['warnings.syntaxonly'] %}
+								<option id="gnu.cpp.compiler.option.warnings.syntax.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.syntax" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['warnings.nowarn'] %}
+								<option id="gnu.cpp.compiler.option.warnings.nowarn.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.nowarn" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								<option id="gnu.cpp.compiler.option.warnings.allwarn.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.allwarn" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% if opts['common']['warnings.extrawarn'] %}
+								<option id="gnu.cpp.compiler.option.warnings.extrawarn.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.extrawarn" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['warnings.toerrors'] %}
+								<option id="gnu.cpp.compiler.option.warnings.toerrors.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.toerrors" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}							
+								{% if opts['common']['warnings.conversion'] %}
+								<option id="gnu.cpp.compiler.option.warnings.wconversion.{{u.id}}" superClass="gnu.cpp.compiler.option.warnings.wconversion" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['debugging.prof'] %}
+								<option id="gnu.cpp.compiler.option.debugging.prof.{{u.id}}" superClass="gnu.cpp.compiler.option.debugging.prof" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['debugging.gprof'] %}
+								<option id="gnu.cpp.compiler.option.debugging.gprof.{{u.id}}" superClass="gnu.cpp.compiler.option.debugging.gprof" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['debugging.codecov'] %}
+								<option id="gnu.cpp.compiler.option.debugging.codecov.{{u.id}}" superClass="gnu.cpp.compiler.option.debugging.codecov" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['c']['verbose'] %}
+								<option id="gnu.cpp.compiler.option.other.verbose.{{u.id}}" superClass="gnu.cpp.compiler.option.other.verbose" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['optimization.PIC'] %}
+								<option id="gnu.cpp.compiler.option.other.pic.{{u.id}}" superClass="gnu.cpp.compiler.option.other.pic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['optimization.datasections'] %}
+								<option id="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.fdata.{{u.id}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.fdata" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['optimization.functionsections'] %}
+								<option id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.ffunction.{{u.id}}" name="Place the function in their own section (-ffunction-sections)" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.ffunction" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['cpp']['otheroptimizations'] != '' or opts['common']['optimization.other'] != '' %}
+								<option id="gnu.cpp.compiler.option.optimization.flags.{{u.id}}" superClass="gnu.cpp.compiler.option.optimization.flags" useByScannerDiscovery="false" value="{{opts['cpp']['otheroptimizations']}} {{opts['common']['optimization.other']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['cpp']['other'] != '' or opts['cpp']['otherwarnings'] != '' or opts['common']['warnings.other'] != '' %}
+								<option id="fr.ac6.managedbuild.gnu.cpp.compiler.option.misc.other.{{u.id}}" name="Other flags" superClass="fr.ac6.managedbuild.gnu.cpp.compiler.option.misc.other" useByScannerDiscovery="false" value="{{opts['cpp']['other']}} {{opts['cpp']['otherwarnings']}} {{opts['common']['warnings.other']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['cpp']['slowflashdata'] %}
+								<option id="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.pcrop.{{u.id}}" name="No data reads in code memory (-mslow-flash-data) " superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.pcrop" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.input.cpp.{{opts['uid']['tool_cpp_compiler_input']}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.input.cpp"/>
+								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.input.s.{{u.id}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.input.s"/>
 							</tool>
-							<tool id="fr.ac6.managedbuild.tool.gnu.cross.cpp.linker.{{uid}}" name="MCU G++ Linker" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.linker">
-								<option id="fr.ac6.managedbuild.tool.gnu.cross.cpp.linker.script.{{uid}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.linker.script" value="${workspace_loc:/${ProjName}/{{linker_script}}}" valueType="string"/>
-								<option id="gnu.cpp.link.option.flags.{{uid}}" superClass="gnu.cpp.link.option.flags" value="--specs=nano.specs" valueType="string"/>
-								<option id="gnu.cpp.link.option.userobjs.{{uid}}" name="Other objects" superClass="gnu.cpp.link.option.userobjs" valueType="userObjs">
+							<tool id="fr.ac6.managedbuild.tool.gnu.cross.cpp.linker.{{u.id}}" name="MCU G++ Linker" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.linker">
+								<option id="fr.ac6.managedbuild.tool.gnu.cross.cpp.linker.script.{{u.id}}" name="Linker Script (-T)" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.linker.script" value="${ProjDirPath}/{{opts['name']}}/{{opts['ld']['script']}}" valueType="string"/>
+								{% if opts['ld']['flags'] != '' or opts['ld']['other'] != '' %}
+								<option id="gnu.cpp.link.option.flags.{{u.id}}" name="Linker flags" superClass="gnu.cpp.link.option.flags" value="{{ opts['ld']['flags']|join(' ') }} {{opts['ld']['other']}}" valueType="string"/>
+								{% endif %}
+								<option id="gnu.cpp.link.option.userobjs.{{u.id}}" name="Other objects" superClass="gnu.cpp.link.option.userobjs" valueType="userObjs">
 									{% for path in object_files %}
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
 									{% endfor %}
 								</option>
-								<option id="gnu.cpp.link.option.libs.{{uid}}" name="Libraries (-l)" superClass="gnu.cpp.link.option.libs" valueType="libs">
+								<option id="gnu.cpp.link.option.libs.{{u.id}}" name="Libraries (-l)" superClass="gnu.cpp.link.option.libs" valueType="libs">
 									{% for lib in libraries %}
 									<listOptionValue builtIn="false" value="{{lib}}"/>
 									{% endfor %}
 								</option>
-								<option id="gnu.cpp.link.option.paths.{{uid}}" superClass="gnu.cpp.link.option.paths" valueType="libPaths">
-									{% for path in library_paths %}
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
-									{% endfor %}
-								</option>
-								<inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.{{uid}}" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
+								{% if opts['ld']['nostart'] %}
+								<option id="gnu.cpp.link.option.nostart.{{u.id}}" name="Do not use standard start files (-nostartfiles)" superClass="gnu.cpp.link.option.nostart" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['ld']['nodeflibs'] %}
+								<option id="gnu.cpp.link.option.nodeflibs.{{u.id}}" superClass="gnu.cpp.link.option.nodeflibs" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['ld']['nostdlibs'] %}
+								<option id="gnu.cpp.link.option.nostdlibs.{{u.id}}" superClass="gnu.cpp.link.option.nostdlibs" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['ld']['strip'] %}
+								<option id="gnu.cpp.link.option.strip.{{u.id}}" superClass="gnu.cpp.link.option.strip" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['ld']['shared'] %}
+								<option id="gnu.cpp.link.option.shared.{{u.id}}" superClass="gnu.cpp.link.option.shared" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['ld']['soname'] != '' %}
+								<option id="gnu.cpp.link.option.soname.{{u.id}}" superClass="gnu.cpp.link.option.soname" useByScannerDiscovery="false" value="{{opts['ld']['soname']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['ld']['implname'] != '' %}
+								<option id="gnu.cpp.link.option.implname.{{u.id}}" superClass="gnu.cpp.link.option.implname" useByScannerDiscovery="false" value="{{opts['ld']['implname']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['ld']['defname'] != '' %}
+								<option id="gnu.cpp.link.option.defname.{{u.id}}" superClass="gnu.cpp.link.option.defname" useByScannerDiscovery="false" value="{{opts['ld']['defname']}}" valueType="string"/>
+								{% endif %}
+								{% if opts['common']['debugging.prof'] %}
+								<option id="gnu.cpp.link.option.debugging.prof.{{u.id}}" superClass="gnu.cpp.link.option.debugging.prof" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['debugging.gprof'] %}
+								<option id="gnu.cpp.link.option.debugging.gprof.{{u.id}}" superClass="gnu.cpp.link.option.debugging.gprof" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% if opts['common']['debugging.codecov'] %}
+								<option id="gnu.cpp.link.option.debugging.codecov.{{u.id}}" superClass="gnu.cpp.link.option.debugging.codecov" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								<inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.{{u.id}}" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
 									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
 									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
 								</inputType>
-							</tool>							<tool id="fr.ac6.managedbuild.tool.gnu.archiver.{{uid}}" name="MCU GCC Archiver" superClass="fr.ac6.managedbuild.tool.gnu.archiver"/>
-							<tool id="fr.ac6.managedbuild.tool.gnu.cross.assembler.{{uid}}" name="MCU GCC Assembler" superClass="fr.ac6.managedbuild.tool.gnu.cross.assembler">
-								<option id="gnu.both.asm.option.include.paths.{{uid}}" name="Include paths (-I)" superClass="gnu.both.asm.option.include.paths" valueType="includePath">
-								{% for path in include_paths %}
-								<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
-								{% endfor %}
-								</option>
-								<inputType id="cdt.managedbuild.tool.gnu.assembler.input.{{uid}}" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
-								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.assembler.input.{{uid}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.assembler.input"/>
-							</tool>
-						</toolChain>
-					</folderInfo>
-				</configuration>
-			</storageModule>
-			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
-		</cconfiguration>
-		<cconfiguration id="fr.ac6.managedbuild.config.gnu.cross.exe.release.{{release_config_uid}}">
-			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="fr.ac6.managedbuild.config.gnu.cross.exe.release.{{release_config_uid}}" moduleId="org.eclipse.cdt.core.settings" name="Release">
-				<externalSettings/>
-				<extensions>
-					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
-					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
-					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
-				</extensions>
-			</storageModule>
-			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="fr.ac6.managedbuild.config.gnu.cross.exe.release.{{release_config_uid}}" name="Release" parent="fr.ac6.managedbuild.config.gnu.cross.exe.release" postannouncebuildStep="Generating binary and Printing size information:" postbuildStep="arm-none-eabi-objcopy -O binary &quot;${BuildArtifactFileBaseName}.elf&quot; &quot;${BuildArtifactFileBaseName}.bin&quot; &amp;&amp; arm-none-eabi-size -B &quot;${BuildArtifactFileName}&quot;">
-					<folderInfo id="fr.ac6.managedbuild.config.gnu.cross.exe.release.{{release_config_uid}}." name="/" resourcePath="">
-						<toolChain id="fr.ac6.managedbuild.toolchain.gnu.cross.exe.release.{{uid}}" name="Ac6 STM32 MCU GCC" superClass="fr.ac6.managedbuild.toolchain.gnu.cross.exe.release">
-							<option id="fr.ac6.managedbuild.option.gnu.cross.mcu.{{uid}}" name="Mcu" superClass="fr.ac6.managedbuild.option.gnu.cross.mcu" value="{{mcu_name}}" valueType="string"/>
-							<option id="fr.ac6.managedbuild.option.gnu.cross.board.{{uid}}" name="Board" superClass="fr.ac6.managedbuild.option.gnu.cross.board" value="{{board_name}}" valueType="string"/>
-							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="fr.ac6.managedbuild.targetPlatform.gnu.cross.{{uid}}" isAbstract="false" osList="all" superClass="fr.ac6.managedbuild.targetPlatform.gnu.cross"/>
-							<builder buildPath="${workspace_loc:/{{name}}}/Release" id="fr.ac6.managedbuild.builder.gnu.cross.{{uid}}" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="fr.ac6.managedbuild.builder.gnu.cross"/>
-							<tool id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.{{release_tool_compiler_uid}}" name="MCU GCC Compiler" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler">
-								<option id="fr.ac6.managedbuild.gnu.c.compiler.option.optimization.level.{{uid}}" name="Optimization Level" superClass="fr.ac6.managedbuild.gnu.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="fr.ac6.managedbuild.gnu.c.optimization.level.most" valueType="enumerated"/>
-								<option id="gnu.c.compiler.option.debugging.level.{{uid}}" name="Debug Level" superClass="gnu.c.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.none" valueType="enumerated"/>
-								<option id="gnu.c.compiler.option.include.paths.{{uid}}" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
-								{% for path in include_paths %}
-									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
-								{% endfor %}}
-								</option>
-								<option id="gnu.c.compiler.option.preprocessor.def.symbols.{{uid}}" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" useByScannerDiscovery="false" valueType="definedSymbols">
-								{% for s in symbols %}
-									<listOptionValue builtIn="false" value="{{s}}"/>
-								{% endfor %}
-								</option>
-								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c.{{debug_tool_compiler_input_uid}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c"/>
-								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.s.{{uid}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.s"/>
-							</tool>
-							<tool id="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.{{uid}}" name="MCU G++ Compiler" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler">
-								<option id="fr.ac6.managedbuild.gnu.cpp.compiler.option.optimization.level.{{uid}}" name="Optimization Level" superClass="fr.ac6.managedbuild.gnu.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="fr.ac6.managedbuild.gnu.cpp.optimization.level.most" valueType="enumerated"/>
-								<option id="gnu.cpp.compiler.option.debugging.level.{{uid}}" name="Debug Level" superClass="gnu.cpp.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.debugging.level.none" valueType="enumerated"/>
-								<option id="gnu.cpp.compiler.option.include.paths.{{uid}}" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
-									{% for path in include_paths %}
-									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
-									{% endfor %}
-								</option>
-								<option id="gnu.cpp.compiler.option.preprocessor.def{{uid}}" superClass="gnu.cpp.compiler.option.preprocessor.def" valueType="definedSymbols">
-								{% for s in symbols %}
-									<listOptionValue builtIn="false" value="{{s}}"/>
-								{% endfor %}
-								</option>
-								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.input.cpp.{{uid}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.input.cpp"/>
-								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.input.s.{{uid}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.input.s"/>
-							</tool>
-							<tool id="fr.ac6.managedbuild.tool.gnu.cross.c.linker.{{uid}}" name="MCU GCC Linker" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.linker">
-								<inputType id="cdt.managedbuild.tool.gnu.c.linker.input.{{uid}}" superClass="cdt.managedbuild.tool.gnu.c.linker.input">
-									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
-									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
-								</inputType>
-							</tool>
-							<tool id="fr.ac6.managedbuild.tool.gnu.cross.cpp.linker.{{uid}}" name="MCU G++ Linker" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.linker">
-								<option id="fr.ac6.managedbuild.tool.gnu.cross.cpp.linker.script.{{uid}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.linker.script" value="${workspace_loc:/${ProjName}/{{linker_script}}}" valueType="string"/>
-								<option id="gnu.cpp.link.option.flags.{{uid}}" superClass="gnu.cpp.link.option.flags" value="--specs=nano.specs" valueType="string"/>
-								<option id="gnu.cpp.link.option.userobjs.{{uid}}" name="Other objects" superClass="gnu.cpp.link.option.userobjs" valueType="userObjs">
-									{% for path in object_files %}
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
-									{% endfor %}
-								</option>
-								<option id="gnu.cpp.link.option.libs.{{uid}}" name="Libraries (-l)" superClass="gnu.cpp.link.option.libs" valueType="libs">
-									{% for lib in libraries %}
-									<listOptionValue builtIn="false" value="{{lib}}"/>
-									{% endfor %}
-								</option>
-								<option id="gnu.cpp.link.option.paths.{{uid}}" superClass="gnu.cpp.link.option.paths" valueType="libPaths">
+								<option id="gnu.cpp.link.option.paths.{{u.id}}" name="Library search path (-L)" superClass="gnu.cpp.link.option.paths" valueType="libPaths">
 									{% for path in library_paths %}
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/{{path}}}&quot;"/>
 									{% endfor %}
 								</option>
-								<inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.{{uid}}" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
-									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
-									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
-								</inputType>
 							</tool>
-							<tool id="fr.ac6.managedbuild.tool.gnu.archiver.{{uid}}" name="MCU GCC Archiver" superClass="fr.ac6.managedbuild.tool.gnu.archiver"/>
-							<tool id="fr.ac6.managedbuild.tool.gnu.cross.assembler.{{uid}}" name="MCU GCC Assembler" superClass="fr.ac6.managedbuild.tool.gnu.cross.assembler">
-								<option id="gnu.both.asm.option.include.paths.{{uid}}" name="Include paths (-I)" superClass="gnu.both.asm.option.include.paths" valueType="includePath">
-								{% for path in include_paths %}
-									<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/{{path}}&quot;"/>
-								{% endfor %}
+							<tool id="fr.ac6.managedbuild.tool.gnu.archiver.{{u.id}}" name="MCU GCC Archiver" superClass="fr.ac6.managedbuild.tool.gnu.archiver"/>
+							<tool id="fr.ac6.managedbuild.tool.gnu.cross.assembler.{{u.id}}" name="MCU GCC Assembler" superClass="fr.ac6.managedbuild.tool.gnu.cross.assembler">
+								<option id="gnu.both.asm.option.include.paths.{{u.id}}" name="Include paths (-I)" superClass="gnu.both.asm.option.include.paths" valueType="includePath">
+									{% for path in include_paths %}
+									<listOptionValue builtIn="false" value="&quot;{{path}}&quot;"/>
+									{% endfor %}
 								</option>
-								<inputType id="cdt.managedbuild.tool.gnu.assembler.input.{{uid}}" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
-								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.assembler.input.{{uid}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.assembler.input"/>
+								{% if opts['as']['other'] != '' or opts['as']['otherwarnings'] != '' %}
+								<option id="gnu.both.asm.option.flags.{{u.id}}" superClass="gnu.both.asm.option.flags" useByScannerDiscovery="false" value="{{opts['as']['other']}} {{opts['as']['otherwarnings']}}" valueType="string"/>
+								{% endif %}
+								{% for item in opts['as']['otherwarnings'] %}
+								{% if item == '-W' %}
+								<option id="gnu.both.asm.option.warnings.nowarn.{{u.id}}" superClass="gnu.both.asm.option.warnings.nowarn" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								{% endif %}
+								{% endfor %}
+								<inputType id="cdt.managedbuild.tool.gnu.assembler.input.{{u.id}}" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+								<inputType id="fr.ac6.managedbuild.tool.gnu.cross.assembler.input.{{u.id}}" superClass="fr.ac6.managedbuild.tool.gnu.cross.assembler.input"/>
 							</tool>
 						</toolChain>
 					</folderInfo>
+					<sourceEntries>
+						<entry excluding="{{exclude_paths}}" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+					</sourceEntries>
 				</configuration>
 			</storageModule>
 			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
 		</cconfiguration>
+		{% endfor %}
 	</storageModule>
 	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-		<project id="{{name}}.fr.ac6.managedbuild.target.gnu.cross.exe.{{uid}}" name="Executable" projectType="fr.ac6.managedbuild.target.gnu.cross.exe"/>
+		<project id="{{name}}.fr.ac6.managedbuild.target.gnu.cross.exe.{{u.id}}" name="Executable" projectType="fr.ac6.managedbuild.target.gnu.cross.exe"/>
 	</storageModule>
 	<storageModule moduleId="scannerConfiguration">
 		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
-		<scannerConfigBuildInfo instanceId="fr.ac6.managedbuild.config.gnu.cross.exe.release.{{release_config_uid}};fr.ac6.managedbuild.config.gnu.cross.exe.release.{{release_config_uid}}.;fr.ac6.managedbuild.tool.gnu.cross.c.compiler.{{release_tool_compiler_uid}};fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c.{{debug_tool_compiler_input_uid}}">
+		{% for cfg_key in options %}
+		{% set opts = options[cfg_key] %}	
+		<scannerConfigBuildInfo instanceId="fr.ac6.managedbuild.config.gnu.cross.exe.{{opts['id']}}.{{opts['uid']['config']}};fr.ac6.managedbuild.config.gnu.cross.exe.{{opts['id']}}.{{opts['uid']['config']}}.;fr.ac6.managedbuild.tool.gnu.cross.c.compiler.{{opts['uid']['tool_c_compiler']}};fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c.{{opts['uid']['tool_c_compiler_input']}}">
 			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
 		</scannerConfigBuildInfo>
-		<scannerConfigBuildInfo instanceId="fr.ac6.managedbuild.config.gnu.cross.exe.debug.{{debug_config_uid}};fr.ac6.managedbuild.config.gnu.cross.exe.debug.{{debug_config_uid}}.;fr.ac6.managedbuild.tool.gnu.cross.c.compiler.{{debug_tool_compiler_uid}};fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c.{{release_tool_compiler_input_uid}}">
+		<scannerConfigBuildInfo instanceId="fr.ac6.managedbuild.config.gnu.cross.exe.{{opts['id']}}.{{opts['uid']['config']}};fr.ac6.managedbuild.config.gnu.cross.exe.{{opts['id']}}.{{opts['uid']['config']}}.;fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.{{opts['uid']['tool_cpp_compiler']}};fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.input.cpp.{{opts['uid']['tool_cpp_compiler_input']}}">
 			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
 		</scannerConfigBuildInfo>
+		{% endfor %}
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
 </cproject>
diff --git a/tools/export/sw4stm32/language_settings_commom.tmpl b/tools/export/sw4stm32/language_settings_commom.tmpl
index d138720fd22..99566a5c701 100644
--- a/tools/export/sw4stm32/language_settings_commom.tmpl
+++ b/tools/export/sw4stm32/language_settings_commom.tmpl
@@ -1,25 +1,18 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <project>
-	<configuration id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.{{debug_config_uid}}" name="Debug">
+	{% for cfg_id in options %}
+	{% set opts = options[cfg_id] %}
+	<configuration id="fr.ac6.managedbuild.config.gnu.cross.exe.{{cfg_id}}.{{opts['uid']['config']}}" name="{{opts['name']}}">
 		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" console="false" env-hash="1343080084626211886" id="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="Ac6 SW4 STM32 MCU Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
-				<language-scope id="org.eclipse.cdt.core.gcc"/>
-				<language-scope id="org.eclipse.cdt.core.g++"/>
-			</provider>
-		</extension>
-	</configuration>
-	<configuration id="fr.ac6.managedbuild.config.gnu.cross.exe.release.{{release_config_uid}}" name="Release">
-		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
-			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
-			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
-			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" console="false" env-hash="1343080084626211886" id="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="Ac6 SW4 STM32 MCU Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/>
+			<provider class="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" console="false" env-hash="-1025524915312781673" id="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="Ac6 SW4 STM32 MCU Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>
 		</extension>
 	</configuration>
+	{% endfor %}
 </project>
diff --git a/tools/export/sw4stm32/launch.tmpl b/tools/export/sw4stm32/launch.tmpl
new file mode 100644
index 00000000000..efba7bdab1c
--- /dev/null
+++ b/tools/export/sw4stm32/launch.tmpl
@@ -0,0 +1,63 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="fr.ac6.mcu.debug.config.launchConfigurationType">
+<stringAttribute key="DEBBUGER_BOARD_NAME" value="{{board_name}}"/>
+<stringAttribute key="DEBBUGER_MCU_NAME" value="{{mcu_name}}"/>
+<stringAttribute key="fr.ac6.mcu.ide.DBG_DEVICE" value="ST-Link"/>
+<stringAttribute key="fr.ac6.mcu.ide.DBG_DEVICE_SHAREABLE_ALLOWED" value="false"/>
+<stringAttribute key="fr.ac6.mcu.ide.DBG_INTERFACE" value="SWD"/>
+<stringAttribute key="fr.ac6.mcu.ide.DBG_INTERFACE_FREQUENCY" value="4000000.0"/>
+<stringAttribute key="fr.ac6.mcu.ide.DBG_LOW_POWER_MODE_ALLOWED" value="true"/>
+<stringAttribute key="fr.ac6.mcu.ide.DBG_RESET_MODE" value="connect_under_reset"/>
+<stringAttribute key="fr.ac6.mcu.ide.DBG_STOP_WATCHDOG_THEN_HALTED_ALLOWED" value="true"/>
+<booleanAttribute key="fr.ac6.mcu.ide.OPENOCD_GENERATOR_OPTION" value="false"/>
+<stringAttribute key="fr.ac6.mcu.ide.OPENOCD_NAME" value="&quot;${openstm32_openocd_path}{% if platform == 'win32' %}\{% else %}/{% endif %}openocd{% if platform == 'win32' %}.exe{% endif %}&quot;"/>
+<stringAttribute key="fr.ac6.mcu.ide.OPENOCD_OTHER_OPTIONS" value=""/>
+{% set cfg_id = 'debug' %}
+{% set opts = options[cfg_id] %}
+<stringAttribute key="fr.ac6.mcu.ide.OPENOCD_SCRIPT" value="{{opts['name']}}{% if platform == 'win32' %}\{% else %}/{% endif %}{{name}} {{opts['name']}}.cfg"/>
+<stringAttribute key="fr.ac6.mcu.ide.OPENOCD_SCRIPT_CHOICE" value="automated"/>
+<stringAttribute key="fr.ac6.mcu.ide.OPENOCD_SCRIPT_IS_LEGACY" value="false"/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="3"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="monitor reset halt"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${openstm32_compiler_path}{% if platform == 'win32' %}\{% else %}/{% endif %}arm-none-eabi-gdb"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="{{opts['name']}}{% if platform == 'win32' %}\{% else %}/{% endif %}{{name}}-{{cfg_id}}.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="{{name}}"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="fr.ac6.managedbuild.config.gnu.cross.exe.{{cfg_id}}.{{opts['uid']['config']}}"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/{{name}}"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
+<listEntry value="org.eclipse.debug.ui.launchGroup.{{cfg_id}}"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="fr.ac6.mcu.debug.launching.MCUGdbProcessFactory"/>
+</launchConfiguration>
diff --git a/tools/export/sw4stm32/makefile.targets.tmpl b/tools/export/sw4stm32/makefile.targets.tmpl
new file mode 100644
index 00000000000..da87905d02a
--- /dev/null
+++ b/tools/export/sw4stm32/makefile.targets.tmpl
@@ -0,0 +1,16 @@
+# DO NOT REMOVE! Generated by the SW4STM32 exporter from the mbed project.
+
+PREPROC_CMD ?= {{cpp_cmd}}
+
+ldclean:
+{% for config, opts in options.iteritems() %}
+	$(RM) {{opts['ld']['script']}}
+{% endfor %}
+
+{% for config, opts in options.iteritems() %}
+{{opts['ld']['script']}}: ../{{ld_script}}
+	$(PREPROC_CMD) {{opts.ld.other}} $< -o $@
+
+{{name}}-{{config}}.elf: {{opts['ld']['script']}}
+
+{% endfor %}
diff --git a/tools/export/uvision/__init__.py b/tools/export/uvision/__init__.py
index 12c3241207b..8382bae0f0f 100644
--- a/tools/export/uvision/__init__.py
+++ b/tools/export/uvision/__init__.py
@@ -167,8 +167,9 @@ def format_flags(self):
         """Format toolchain flags for Uvision"""
         flags = copy.deepcopy(self.flags)
         # to be preprocessed with armcc
-        asm_flag_string = '--cpreproc --cpreproc_opts=-D__ASSERT_MSG,' + \
-                          ",".join(flags['asm_flags'])
+        asm_flag_string = (
+            '--cpreproc --cpreproc_opts=-D__ASSERT_MSG,' +
+            ",".join(filter(lambda f: f.startswith("-D"), flags['asm_flags'])))
         flags['asm_flags'] = asm_flag_string
         # All non-asm flags are in one template field
         c_flags = list(set(flags['c_flags'] + flags['cxx_flags'] +flags['common_flags']))
diff --git a/tools/export/uvision/uvision.tmpl b/tools/export/uvision/uvision.tmpl
index f49c79659d4..49c708c3bb1 100644
--- a/tools/export/uvision/uvision.tmpl
+++ b/tools/export/uvision/uvision.tmpl
@@ -394,7 +394,7 @@
               <MiscControls>{{asm_flags}}</MiscControls>
               <Define></Define>
               <Undefine></Undefine>
-              <IncludePath></IncludePath>
+              <IncludePath>{{include_paths}}</IncludePath>
             </VariousControls>
           </Aads>
           <LDads>
diff --git a/tools/hooks.py b/tools/hooks.py
index 2693c6e6b68..ad1a32d90b7 100644
--- a/tools/hooks.py
+++ b/tools/hooks.py
@@ -65,7 +65,7 @@ def __init__(self, target, toolchain):
         _HOOKS.clear()
         self._cmdline_hooks = {}
         self.toolchain = toolchain
-        target.init_hooks(self, toolchain.__class__.__name__)
+        target.init_hooks(self, toolchain)
 
     # Hook various functions directly
     @staticmethod
diff --git a/tools/memap.py b/tools/memap.py
index e425afe102c..a2efd0e230d 100644
--- a/tools/memap.py
+++ b/tools/memap.py
@@ -20,6 +20,18 @@
     r'^\s+(.+)\s+(zero|const|ro code|inited|uninit)\s'
     r'+0x(\w{8})\s+0x(\w+)\s+(.+)\s.+$')
 
+RE_CMDLINE_FILE_IAR = re.compile(r'^#\s+(.+\.o)')
+RE_LIBRARY_IAR = re.compile(r'^(.+\.a)\:.+$')
+RE_OBJECT_LIBRARY_IAR = re.compile(r'^\s+(.+\.o)\s.*')
+
+RE_OBJECT_FILE_GCC = re.compile(r'^(.+\/.+\.o)$')
+RE_LIBRARY_OBJECT_GCC = re.compile(r'^.+\/lib(.+\.a)\((.+\.o)\)$')
+RE_STD_SECTION_GCC = re.compile(r'^\s+.*0x(\w{8,16})\s+0x(\w+)\s(.+)$')
+RE_FILL_SECTION_GCC = re.compile(r'^\s*\*fill\*\s+0x(\w{8,16})\s+0x(\w+).*$')
+
+RE_OBJECT_ARMCC = re.compile(r'(.+\.(l|ar))\((.+\.o)\)')
+
+
 class MemapParser(object):
     """An object that represents parsed results, parses the memory map files,
     and writes out different file types of memory results
@@ -59,31 +71,10 @@ def __init__(self):
 
         self.misc_flash_mem = 0
 
+        # Modules passed to the linker on the command line
+        # this is a dict because modules are looked up by their basename
+        self.cmd_modules = {}
 
-    def remove_unused_modules(self):
-        """ Removes modules/objects that were compiled but are not used
-        """
-
-        # Using keys to be able to remove entry
-        for i in self.modules.keys():
-            size = 0
-            for k in self.print_sections:
-                size += self.modules[i][k]
-            if size == 0:
-                del self.modules[i]
-
-    def module_init(self, object_name):
-        """ Initialize a module. Just adds the name of the module
-
-        Positional arguments:
-        object_name - name of the entry to add
-        """
-
-        if object_name not in self.modules:
-            temp_dic = dict()
-            for section_idx in self.all_sections:
-                temp_dic[section_idx] = 0
-            self.modules[object_name] = temp_dic
 
     def module_add(self, object_name, size, section):
         """ Adds a module / section to the list
@@ -94,28 +85,27 @@ def module_add(self, object_name, size, section):
         section - the section the module contributes to
         """
 
-        # Check if object is a sub-string of key
-        for module_path in self.modules:
+        if not object_name or not size or not section:
+            return
 
-            # this is required to differenciate: main.o vs xxxmain.o
-            module_split = os.path.basename(module_path)
-            obj_split = os.path.basename(object_name)
+        if object_name in self.modules:
+            self.modules[object_name].setdefault(section, 0)
+            self.modules[object_name][section] += size
+            return
 
-            if module_split == obj_split:
-                self.modules[module_path][section] += size
+        obj_split = os.sep + os.path.basename(object_name)
+        for module_path, contents in self.modules.items():
+            if module_path.endswith(obj_split) or module_path == object_name:
+                contents.setdefault(section, 0)
+                contents[section] += size
                 return
 
-        new_module = dict()
-        for section_idx in self.all_sections:
-            new_module[section_idx] = 0
-        new_module[section] = size
+        new_module = {section: size}
         self.modules[object_name] = new_module
 
     def module_replace(self, old_object, new_object):
         """ Replaces an object name with a new one
         """
-
-        # Check if object is a sub-string of key
         if old_object in self.modules:
             self.modules[new_object] = self.modules[old_object]
             del self.modules[old_object]
@@ -147,8 +137,7 @@ def parse_object_name_gcc(self, line):
         """
 
         line = line.replace('\\', '/')
-        RE_OBJECT_FILE = r'^.+\/(.+\.o)$'
-        test_re_mbed_os_name = re.match(RE_OBJECT_FILE, line)
+        test_re_mbed_os_name = re.match(RE_OBJECT_FILE_GCC, line)
 
         if test_re_mbed_os_name:
 
@@ -156,14 +145,12 @@ def parse_object_name_gcc(self, line):
 
             # corner case: certain objects are provided by the GCC toolchain
             if 'arm-none-eabi' in line:
-                object_name = '[lib]/misc/' + object_name
-
+                return '[lib]/misc/' + object_name
             return object_name
 
         else:
 
-            RE_LIBRARY_OBJECT_FILE = r'^.+\/(lib.+\.a)\((.+\.o)\)$'
-            test_re_obj_name = re.match(RE_LIBRARY_OBJECT_FILE, line)
+            test_re_obj_name = re.match(RE_LIBRARY_OBJECT_GCC, line)
 
             if test_re_obj_name:
                 object_name = test_re_obj_name.group(1) + '/' + \
@@ -172,7 +159,7 @@ def parse_object_name_gcc(self, line):
                 return '[lib]/' + object_name
 
             else:
-                print "Malformed input found when parsing GCC map: %s" % line
+                print "Unknown object name found in GCC map file: %s" % line
                 return '[misc]'
 
     def parse_section_gcc(self, line):
@@ -186,40 +173,20 @@ def parse_section_gcc(self, line):
         line - the line to parse a section from
         """
 
-        RE_STD_SECTION_GCC = re.compile(
-            r'^\s+.*0x(\w{8,16})\s+0x(\w+)\s(.+)$')
-
-        test_address_len_name = re.match(RE_STD_SECTION_GCC, line)
-
-        if test_address_len_name:
-
-            if int(test_address_len_name.group(2), 16) == 0: # size == 0
-                return ["", 0] # no valid entry
-            else:
-                o_name = self.parse_object_name_gcc(\
-                    test_address_len_name.group(3))
-                o_size = int(test_address_len_name.group(2), 16)
-
+        is_fill = re.match(RE_FILL_SECTION_GCC, line)
+        if is_fill:
+            o_name = '[fill]'
+            o_size = int(is_fill.group(2), 16)
+            return [o_name, o_size]
+
+        is_section = re.match(RE_STD_SECTION_GCC, line)
+        if is_section:
+            o_size = int(is_section.group(2), 16)
+            if o_size:
+                o_name = self.parse_object_name_gcc(is_section.group(3))
                 return [o_name, o_size]
 
-        else: # special corner case for *fill* sections
-            #  example
-            # *fill*         0x0000abe4        0x4
-
-            RE_FILL_SECTION_GCC = r'^\s+\*fill\*\s+0x(\w{8,16})\s+0x(\w+).*$'
-
-            test_address_len = re.match(RE_FILL_SECTION_GCC, line)
-
-            if test_address_len:
-                if int(test_address_len.group(2), 16) == 0: # size == 0
-                    return ["", 0] # no valid entry
-                else:
-                    o_name = '[fill]'
-                    o_size = int(test_address_len.group(2), 16)
-                    return [o_name, o_size]
-            else:
-                return ["", 0] # no valid entry
-
+        return ["", 0]
 
     def parse_map_file_gcc(self, file_desc):
         """ Main logic to decode gcc map files
@@ -231,30 +198,34 @@ def parse_map_file_gcc(self, file_desc):
         current_section = 'unknown'
 
         with file_desc as infile:
-
-            # Search area to parse
             for line in infile:
                 if line.startswith('Linker script and memory map'):
                     current_section = "unknown"
                     break
 
-            # Start decoding the map file
             for line in infile:
+                next_section = self.check_new_section_gcc(line)
 
-                change_section = self.check_new_section_gcc(line)
-
-                if change_section == "OUTPUT": # finish parsing file: exit
+                if next_section == "OUTPUT":
                     break
-                elif change_section != False:
-                    current_section = change_section
+                elif next_section:
+                    current_section = next_section
 
-                [object_name, object_size] = self.parse_section_gcc(line)
+                object_name, object_size = self.parse_section_gcc(line)
 
-                if object_size == 0 or object_name == "":
-                    pass
-                else:
-                    self.module_add(object_name, object_size,\
-                                        current_section)
+                self.module_add(object_name, object_size, current_section)
+
+        common_prefix = os.path.dirname(os.path.commonprefix([
+            o for o in self.modules.keys() if (o.endswith(".o") and not o.startswith("[lib]"))]))
+        new_modules = {}
+        for name, stats in self.modules.items():
+            if name.startswith("[lib]"):
+                new_modules[name] = stats
+            elif name.endswith(".o"):
+                new_modules[os.path.relpath(name, common_prefix)] = stats
+            else:
+                new_modules[name] = stats
+        self.modules = new_modules
 
     def parse_object_name_armcc(self, line):
         """ Parse object file
@@ -268,14 +239,9 @@ def parse_object_name_armcc(self, line):
             return line
 
         else:
-
-            RE_OBJECT_ARMCC = r'(.+\.l)\((.+\.o)\)'
-            test_re_obj_name = re.match(RE_OBJECT_ARMCC, line)
-
-            if test_re_obj_name:
-                object_name = test_re_obj_name.group(1) + '/' + \
-                              test_re_obj_name.group(2)
-
+            is_obj = re.match(RE_OBJECT_ARMCC, line)
+            if is_obj:
+                object_name = os.path.basename(is_obj.group(1)) + '/' + is_obj.group(3)
                 return '[lib]/' + object_name
             else:
                 print "Malformed input found when parsing ARMCC map: %s" % line
@@ -321,7 +287,7 @@ def parse_section_armcc(self, line):
         else:
             return ["", 0, ""]
 
-    def parse_object_name_iar(self, line):
+    def parse_object_name_iar(self, object_name):
         """ Parse object file
 
         Positional arguments:
@@ -329,10 +295,11 @@ def parse_object_name_iar(self, line):
         """
 
         # simple object (not library)
-        if line[-2] == '.' and line[-1] == 'o':
-            object_name = line
-            return object_name
-
+        if object_name.endswith(".o"):
+            try:
+                return self.cmd_modules[object_name]
+            except KeyError:
+                return object_name
         else:
             return '[misc]'
 
@@ -361,11 +328,11 @@ def parse_section_iar(self, line):
 
             size = int(test_re_iar.group(4), 16)
 
-            if test_re_iar.group(2) == 'const' or \
-               test_re_iar.group(2) == 'ro code':
+            if (test_re_iar.group(2) == 'const' or
+                test_re_iar.group(2) == 'ro code'):
                 section = '.text'
-            elif test_re_iar.group(2) == 'zero' or \
-            test_re_iar.group(2) == 'uninit':
+            elif (test_re_iar.group(2) == 'zero' or
+                  test_re_iar.group(2) == 'uninit'):
                 if test_re_iar.group(1)[0:4] == 'HEAP':
                     section = '.heap'
                 elif test_re_iar.group(1)[0:6] == 'CSTACK':
@@ -379,8 +346,7 @@ def parse_section_iar(self, line):
                 print "Malformed input found when parsing IAR map: %s" % line
 
             # lookup object in dictionary and return module name
-            temp = test_re_iar.group(5)
-            object_name = self.parse_object_name_iar(temp)
+            object_name = self.parse_object_name_iar(test_re_iar.group(5))
 
             return [object_name, size, section]
 
@@ -403,14 +369,20 @@ def parse_map_file_armcc(self, file_desc):
 
             # Start decoding the map file
             for line in infile:
+                self.module_add(*self.parse_section_armcc(line))
+
+        common_prefix = os.path.dirname(os.path.commonprefix([
+            o for o in self.modules.keys() if (o.endswith(".o") and o != "anon$$obj.o" and not o.startswith("[lib]"))]))
+        new_modules = {}
+        for name, stats in self.modules.items():
+            if name == "anon$$obj.o" or name.startswith("[lib]"):
+                new_modules[name] = stats
+            elif name.endswith(".o"):
+                new_modules[os.path.relpath(name, common_prefix)] = stats
+            else:
+                new_modules[name] = stats
+        self.modules = new_modules
 
-                [object_name, object_size, section] = \
-                                self.parse_section_armcc(line)
-
-                if object_size == 0 or object_name == "" or section == "":
-                    pass
-                else:
-                    self.module_add(object_name, object_size, section)
 
 
     def check_new_library_iar(self, line):
@@ -420,7 +392,6 @@ def check_new_library_iar(self, line):
 
         """
 
-        RE_LIBRARY_IAR = re.compile(r'^(.+\.a)\:.+$')
 
         test_address_line = re.match(RE_LIBRARY_IAR, line)
 
@@ -441,8 +412,6 @@ def check_new_object_lib_iar(self, line):
 
         """
 
-        RE_OBJECT_LIBRARY_IAR = re.compile(r'^\s+(.+\.o)\s.*')
-
         test_address_line = re.match(RE_OBJECT_LIBRARY_IAR, line)
 
         if test_address_line:
@@ -450,6 +419,25 @@ def check_new_object_lib_iar(self, line):
         else:
             return ""
 
+    def parse_iar_command_line(self, lines):
+        """Parse the files passed on the command line to the iar linker
+
+        Positional arguments:
+        lines -- an iterator over the lines within a file
+        """
+        for line in lines:
+            if line.startswith("*"):
+                break
+            is_cmdline_file = RE_CMDLINE_FILE_IAR.match(line)
+            if is_cmdline_file:
+                full_path = is_cmdline_file.group(1)
+                self.cmd_modules[os.path.basename(full_path)] = full_path
+
+        common_prefix = os.path.dirname(os.path.commonprefix(self.cmd_modules.values()))
+        self.cmd_modules = {s: os.path.relpath(f, common_prefix)
+                            for s, f in self.cmd_modules.items()}
+
+
     def parse_map_file_iar(self, file_desc):
         """ Main logic to decode IAR map files
 
@@ -457,106 +445,37 @@ def parse_map_file_iar(self, file_desc):
         file_desc - a file like object to parse as an IAR map file
         """
 
-        # first round, search for objects
         with file_desc as infile:
-            # Search area to parse
+            self.parse_iar_command_line(infile)
+
             for line in infile:
                 if line.startswith('  Section  '):
                     break
 
-            # Start decoding the map file
             for line in infile:
-
-                [name, size, section] = self.parse_section_iar(line)
-
-                if size == 0 or name == "" or section == "":
-                    pass
-                else:
-                    self.module_add(name, size, section)
+                self.module_add(*self.parse_section_iar(line))
 
                 if line.startswith('*** MODULE SUMMARY'): # finish section
                     break
 
-            # Start decoding the map file
             current_library = ""
             for line in infile:
 
                 library = self.check_new_library_iar(line)
 
-                if library != "":
+                if library:
                     current_library = library
 
                 object_name = self.check_new_object_lib_iar(line)
 
-                if object_name != "" and current_library != "":
+                if object_name and current_library:
                     temp = '[lib]' + '/'+ current_library + '/'+ object_name
                     self.module_replace(object_name, temp)
 
 
-    export_formats = ["json", "csv-ci", "table"]
-
-    def list_dir_obj(self, path):
-        """ Searches all objects in BUILD directory and creates list
-
-        Positional arguments:
-        path - the path to a map file
-        """
-
-        path = path.replace('\\', '/')
-
-        # check location of map file
-        RE_PATH_MAP_FILE = r'^(.+)\/.+\.map$'
-        test_re = re.match(RE_PATH_MAP_FILE, path)
-
-        if test_re:
-            search_path = test_re.group(1)
-        else:
-            print "Warning: this doesn't look like an mbed project"
-            return
-
-        # create empty disctionary
-        self.modules = dict()
-
-        # search for object files
-        for root, _, obj_files in os.walk(search_path):
-            for obj_file in obj_files:
-                if obj_file.endswith(".o"):
-
-                    txt = os.path.join(root, obj_file)
-
-                    txt = txt.replace('\\', '/')
-
-                    # add relative path + object to list
-                    self.module_init(txt[len(search_path)+1:])
-
-        # The code below is a special case for TESTS.
-        # mbed-os lives in a separate location and we need to explicitly search
-        # their object files skiping the TESTS folder (already scanned above)
-
-        # check location of mbed-os
-        RE_PATH_MAP_FILE = r'^(.+)\/mbed-os\/.*TESTS\/.+\.map$'
-        test_re = re.match(RE_PATH_MAP_FILE, path)
-
-        if test_re == None:
-            return
-
-        search_path = test_re.group(1)
-
-        # search for object files
-        for root, _, obj_files in os.walk(search_path):
-            for obj_file in obj_files:
-                if 'TESTS' not in root and obj_file.endswith(".o"):
-
-                    txt = os.path.join(root, obj_file)
-                    txt = txt.replace('\\', '/')
-
-                    # add relative path + object to list
-                    self.module_init(txt[len(search_path)+1:])
-
-
     def reduce_depth(self, depth):
         """
-        prints list of directories and objects. Examples:
+        populates the short_modules attribute with a truncated module list
 
         (1) depth = 1:
         main.o
@@ -568,43 +487,19 @@ def reduce_depth(self, depth):
         mbed-os/drivers
 
         """
-
-        # depth 0 or None shows all entries
         if depth == 0 or depth == None:
             self.short_modules = deepcopy(self.modules)
-            return
-
-        self.short_modules = dict()
-
-        # create reduced list
-        for line in self.modules:
-
-            data = line.split('/')
-            ndir = len(data)
-
-            temp = ''
-            count = 0
-
-            # iterate until the max depth level
-            max_level = min(depth, ndir)
-
-            # rebuild the path based on depth level
-            while count < max_level:
-                if count > 0:    # ignore '/' from first entry
-                    temp = temp + '/'
-
-                temp = temp + data[count]
-                count += 1
-
-            if temp not in self.short_modules:
-                temp_dic = dict()
-                for section_idx in self.all_sections:
-                    temp_dic[section_idx] = 0
-                self.short_modules[temp] = temp_dic
-
-            for section_idx in self.all_sections:
-                self.short_modules[temp][section_idx] += \
-                    self.modules[line][section_idx]
+        else:
+            self.short_modules = dict()
+            for module_name, v in self.modules.items():
+                split_name = module_name.split('/')
+                if split_name[0] == '':
+                    split_name = split_name[1:]
+                new_name = "/".join(split_name[:depth])
+                self.short_modules.setdefault(new_name, {})
+                for section_idx, value in v.items():
+                    self.short_modules[new_name].setdefault(section_idx, 0)
+                    self.short_modules[new_name][section_idx] += self.modules[module_name][section_idx]
 
 
     export_formats = ["json", "csv-ci", "table"]
@@ -728,12 +623,12 @@ def generate_table(self, file_desc):
     def compute_report(self):
         """ Generates summary of memory usage for main areas
         """
-
         for k in self.sections:
             self.subtotal[k] = 0
 
-        for i in sorted(self.short_modules):
+        for i in self.short_modules:
             for k in self.sections:
+                self.short_modules[i].setdefault(k, 0)
                 self.subtotal[k] += self.short_modules[i][k]
 
         self.mem_summary = {
@@ -746,7 +641,7 @@ def compute_report(self):
             self.mem_report.append({
                 "module":i,
                 "size":{
-                    k:self.short_modules[i][k] for k in self.print_sections
+                    k: self.short_modules[i][k] for k in self.print_sections
                 }
             })
 
@@ -765,10 +660,6 @@ def parse(self, mapfile, toolchain):
         result = True
         try:
             with open(mapfile, 'r') as file_input:
-
-                # Common to all toolchains: first search for objects in BUILD
-                self.list_dir_obj(os.path.abspath(mapfile))
-
                 if toolchain in ("ARM", "ARM_STD", "ARM_MICRO", "ARMC6"):
                     self.parse_map_file_armcc(file_input)
                 elif toolchain == "GCC_ARM" or toolchain == "GCC_CR":
@@ -778,8 +669,6 @@ def parse(self, mapfile, toolchain):
                 else:
                     result = False
 
-                self.remove_unused_modules()
-
         except IOError as error:
             print "I/O error({0}): {1}".format(error.errno, error.strerror)
             result = False
diff --git a/tools/profiles/debug.json b/tools/profiles/debug.json
index c3fa7a586c9..ad4fab345a7 100644
--- a/tools/profiles/debug.json
+++ b/tools/profiles/debug.json
@@ -19,7 +19,7 @@
         "common": ["-c", "--target=arm-arm-none-eabi", "-mthumb", "-g", "-O0",
                    "-Wno-armcc-pragma-push-pop", "-Wno-armcc-pragma-anon-unions",
                    "-DMULADDC_CANNOT_USE_R7", "-fdata-sections",
-                   "-fno-exceptions"],
+                   "-fno-exceptions", "-MMD"],
         "asm": [],
         "c": ["-D__ASSERT_MSG", "-std=gnu99"],
         "cxx": ["-fno-rtti", "-std=gnu++98"],
@@ -34,7 +34,7 @@
         "asm": [],
         "c": ["--md", "--no_depend_system_headers", "--c99", "-D__ASSERT_MSG"],
         "cxx": ["--cpp", "--no_rtti", "--no_vla"],
-        "ld": []
+        "ld": ["--show_full_path"]
     },
     "uARM": {
         "common": ["-c", "--gnu", "-Otime", "--split_sections",
diff --git a/tools/profiles/develop.json b/tools/profiles/develop.json
index f6db2a28aeb..6142485a5fa 100644
--- a/tools/profiles/develop.json
+++ b/tools/profiles/develop.json
@@ -18,7 +18,7 @@
         "common": ["-c", "--target=arm-arm-none-eabi", "-mthumb", "-Os",
                    "-Wno-armcc-pragma-push-pop", "-Wno-armcc-pragma-anon-unions",
                    "-DMULADDC_CANNOT_USE_R7", "-fdata-sections",
-                   "-fno-exceptions"],
+                   "-fno-exceptions", "-MMD"],
         "asm": [],
         "c": ["-D__ASSERT_MSG", "-std=gnu99"],
         "cxx": ["-fno-rtti", "-std=gnu++98"],
@@ -31,7 +31,7 @@
         "asm": [],
         "c": ["--md", "--no_depend_system_headers", "--c99", "-D__ASSERT_MSG"],
         "cxx": ["--cpp", "--no_rtti", "--no_vla"],
-        "ld": []
+        "ld": ["--show_full_path"]
     },
     "uARM": {
         "common": ["-c", "--gnu", "-Otime", "--split_sections",
diff --git a/tools/profiles/release.json b/tools/profiles/release.json
index 58cf5bd47e8..eedbce067f6 100644
--- a/tools/profiles/release.json
+++ b/tools/profiles/release.json
@@ -18,7 +18,7 @@
         "common": ["-c", "--target=arm-arm-none-eabi", "-mthumb", "-Oz",
                    "-Wno-armcc-pragma-push-pop", "-Wno-armcc-pragma-anon-unions",
                    "-DMULADDC_CANNOT_USE_R7", "-fdata-sections",
-                   "-fno-exceptions"],
+                   "-fno-exceptions", "-MMD"],
         "asm": [],
         "c": ["-D__ASSERT_MSG", "-std=gnu99"],
         "cxx": ["-fno-rtti", "-std=gnu++98"],
@@ -31,7 +31,7 @@
         "asm": [],
         "c": ["--md", "--no_depend_system_headers", "--c99", "-D__ASSERT_MSG"],
         "cxx": ["--cpp", "--no_rtti", "--no_vla"],
-        "ld": []
+        "ld": ["--show_full_path"]
     },
     "uARM": {
         "common": ["-c", "--gnu", "-Ospace", "--split_sections",
diff --git a/tools/project.py b/tools/project.py
index 05f5c0a7d0f..ff59f5b9d40 100644
--- a/tools/project.py
+++ b/tools/project.py
@@ -20,6 +20,7 @@
 from tools.utils import argparse_force_lowercase_type
 from tools.utils import argparse_force_uppercase_type
 from tools.utils import print_large_string
+from tools.utils import NotSupportedException
 from tools.options import extract_profile, list_profiles, extract_mcus
 
 def setup_project(ide, target, program=None, source_dir=None, build=None, export_path=None):
@@ -246,11 +247,13 @@ def main():
     profile = extract_profile(parser, options, toolchain_name, fallback="debug")
     if options.clean:
         rmtree(BUILD_DIR)
-    export(mcu, options.ide, build=options.build,
-           src=options.source_dir, macros=options.macros,
-           project_id=options.program, zip_proj=zip_proj,
-           build_profile=profile, app_config=options.app_config)
-
+    try:
+        export(mcu, options.ide, build=options.build,
+               src=options.source_dir, macros=options.macros,
+               project_id=options.program, zip_proj=zip_proj,
+               build_profile=profile, app_config=options.app_config)
+    except NotSupportedException as exc:
+        print "[ERROR] %s" % str(exc)
 
 if __name__ == "__main__":
     main()
diff --git a/tools/targets/REALTEK_RTL8195AM.py b/tools/targets/REALTEK_RTL8195AM.py
index 86eda42934f..be991645aef 100644
--- a/tools/targets/REALTEK_RTL8195AM.py
+++ b/tools/targets/REALTEK_RTL8195AM.py
@@ -9,6 +9,7 @@
 import shutil
 
 from tools.paths import TOOLS_BOOTLOADERS
+from tools.toolchains import TOOLCHAIN_PATHS
 from datetime import datetime
 
 # Constant Variables
@@ -122,7 +123,8 @@ def parse_load_segment_gcc(image_elf):
     #   LOAD           0x000034 0x10006000 0x10006000 0x026bc 0x026bc RW  0x8
     #   LOAD           0x0026f0 0x30000000 0x30000000 0x06338 0x06338 RWE 0x4
     segment_list = []
-    cmd = 'arm-none-eabi-readelf -l ' + image_elf
+    cmd = os.path.join(TOOLCHAIN_PATHS['GCC_ARM'], 'arm-none-eabi-readelf')
+    cmd = '"' + cmd + '"' + ' -l ' + image_elf
     for line in subprocess.check_output(cmd, shell=True, universal_newlines=True).split("\n"):
         if not line.startswith("  LOAD"):
             continue
@@ -153,7 +155,8 @@ def parse_load_segment_armcc(image_elf):
     (offset, addr, size) = (0, 0, 0)
     segment_list = []
     in_segment = False
-    cmd = 'fromelf --text -v --only=none ' + image_elf
+    cmd = os.path.join(TOOLCHAIN_PATHS['ARM'], 'bin', 'fromelf')
+    cmd = '"' + cmd + '"' + ' --text -v --only=none ' + image_elf
     for line in subprocess.check_output(cmd, shell=True, universal_newlines=True).split("\n"):
         if line == "":
             pass
@@ -201,7 +204,8 @@ def parse_load_segment_iar(image_elf):
 
     segment_list = []
     in_segment = False
-    cmd = 'ielfdumparm ' + image_elf
+    cmd = os.path.join(TOOLCHAIN_PATHS['IAR'], 'bin', 'ielfdumparm')
+    cmd = '"' + cmd + '"' + ' ' + image_elf
     for line in subprocess.check_output(cmd, shell=True, universal_newlines=True).split("\n"):
         if line.startswith("  SEGMENTS:"):
             in_segment = True
diff --git a/tools/targets/__init__.py b/tools/targets/__init__.py
index ee4e9bad4ad..fc4b221a283 100644
--- a/tools/targets/__init__.py
+++ b/tools/targets/__init__.py
@@ -22,6 +22,7 @@
 import inspect
 import sys
 from copy import copy
+from inspect import getmro
 from collections import namedtuple, Mapping
 from tools.targets.LPC import patch
 from tools.paths import TOOLS_BOOTLOADERS
@@ -310,10 +311,14 @@ def labels(self):
             labels.append("UVISOR_UNSUPPORTED")
         return labels
 
-    def init_hooks(self, hook, toolchain_name):
+    def init_hooks(self, hook, toolchain):
         """Initialize the post-build hooks for a toolchain. For now, this
         function only allows "post binary" hooks (hooks that are executed
         after the binary image is extracted from the executable file)
+
+        Positional Arguments:
+        hook - the hook object to add post-binary-hooks to
+        toolchain - the toolchain object for inspection
         """
 
         # If there's no hook, simply return
@@ -329,7 +334,7 @@ def init_hooks(self, hook, toolchain_name):
                 ("Invalid format for hook '%s' in target '%s'"
                  % (hook_data["function"], self.name)) +
                 " (must be 'class_name.function_name')")
-        class_name, function_name = temp[0], temp[1]
+        class_name, function_name = temp
         # "class_name" must refer to a class in this file, so check if the
         # class exists
         mdata = self.get_module_data()
@@ -349,10 +354,11 @@ def init_hooks(self, hook, toolchain_name):
                 ("required by '%s' " % hook_data["function"]) +
                 ("in target '%s' " % self.name) +
                 ("not found in class '%s'" %  class_name))
-        # Check if the hook specification also has target restrictions
-        toolchain_restrictions = hook_data.get("toolchains", [])
+        # Check if the hook specification also has toolchain restrictions
+        toolchain_restrictions = set(hook_data.get("toolchains", []))
+        toolchain_labels = set(c.__name__ for c in getmro(toolchain.__class__))
         if toolchain_restrictions and \
-           (toolchain_name not in toolchain_restrictions):
+           not toolchain_labels.intersection(toolchain_restrictions):
             return
         # Finally, hook the requested function
         hook.hook_add_binary("post", getattr(cls, function_name))
diff --git a/tools/targets/lint.py b/tools/targets/lint.py
index f83838d8b3e..0202d45a315 100644
--- a/tools/targets/lint.py
+++ b/tools/targets/lint.py
@@ -82,7 +82,7 @@ def check_inherits(dict):
                       "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT",
                       "PWMOUT", "RTC", "TRNG","SERIAL", "SERIAL_ASYNCH",
                       "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE",
-                      "STORAGE"]
+                      "STORAGE", "STCLK_OFF_DURING_SLEEP"]
 def check_device_has(dict):
     for name in dict.get("device_has", []):
         if name not in DEVICE_HAS_ALLOWED:
diff --git a/tools/test.py b/tools/test.py
index 91fad7ed50a..7b4f631b3f2 100644
--- a/tools/test.py
+++ b/tools/test.py
@@ -27,7 +27,8 @@
 sys.path.insert(0, ROOT)
 
 from tools.config import ConfigException
-from tools.test_api import test_path_to_name, find_tests, print_tests, build_tests, test_spec_from_test_builds
+from tools.test_api import test_path_to_name, find_tests, get_test_config, print_tests, build_tests, test_spec_from_test_builds
+import tools.test_configs as TestConfig
 from tools.options import get_default_options_parser, extract_profile, extract_mcus
 from tools.build_api import build_project, build_library
 from tools.build_api import print_build_memory_usage
@@ -84,6 +85,9 @@
         parser.add_argument("-n", "--names", dest="names", type=argparse_many(str),
                           default=None, help="Limit the tests to a comma separated list of names")
 
+        parser.add_argument("--test-config", dest="test_config", type=str,
+                          default=None, help="Test config for a module")
+
         parser.add_argument("--test-spec", dest="test_spec",
                           default=None, help="Destination path for a test spec file that can be used by the Greentea automated test tool")
 
@@ -133,10 +137,21 @@
                                "Currently set search path: %s"
                        % (toolchain, search_path))
 
+        # Assign config file. Precedence: test_config>app_config
+        # TODO: merge configs if both given
+        if options.test_config:
+            config = get_test_config(options.test_config, mcu)
+            if not config:
+                args_error(parser, "argument --test-config contains invalid path or identifier")
+        elif not options.app_config:
+            config = TestConfig.get_default_config(mcu)
+        else:
+            config = options.app_config
+
         # Find all tests in the relevant paths
         for path in all_paths:
             all_tests.update(find_tests(path, mcu, toolchain,
-                                        app_config=options.app_config))
+                                        app_config=config))
 
         # Filter tests by name if specified
         if options.names:
@@ -192,7 +207,7 @@
                               properties=build_properties, name="mbed-build",
                               macros=options.macros, verbose=options.verbose,
                               notify=notify, archive=False,
-                              app_config=options.app_config,
+                              app_config=config,
                               build_profile=profile)
 
                 library_build_success = True
@@ -220,7 +235,7 @@
                         notify=notify,
                         jobs=options.jobs,
                         continue_on_build_fail=options.continue_on_build_fail,
-                        app_config=options.app_config,
+                        app_config=config,
                         build_profile=profile,
                         stats_depth=options.stats_depth)
 
diff --git a/tools/test/build_api/build_api_test.py b/tools/test/build_api/build_api_test.py
index 5e6b1fc7983..9317e5a215c 100644
--- a/tools/test/build_api/build_api_test.py
+++ b/tools/test/build_api/build_api_test.py
@@ -20,10 +20,13 @@
 from mock import patch, MagicMock
 from tools.build_api import prepare_toolchain, build_project, build_library,\
     scan_resources
+from tools.toolchains import TOOLCHAINS
 
 """
 Tests for build_api.py
 """
+make_mock_target = namedtuple(
+    "Target", "init_hooks name features core supported_toolchains")
 
 class BuildApiTests(unittest.TestCase):
     """
@@ -82,9 +85,8 @@ def test_prepare_toolchain_app_config(self, mock_config_init):
         :return:
         """
         app_config = "app_config"
-        mock_target = namedtuple("Target",
-                                 "init_hooks name features core")(lambda _, __ : None,
-                                                                  "Junk", [], "Cortex-M3")
+        mock_target = make_mock_target(lambda _, __ : None,
+                                       "Junk", [], "Cortex-M3", TOOLCHAINS)
         mock_config_init.return_value = namedtuple(
             "Config", "target has_regions name")(mock_target, False, None)
 
@@ -102,9 +104,8 @@ def test_prepare_toolchain_no_app_config(self, mock_config_init):
         :param mock_config_init: mock of Config __init__
         :return:
         """
-        mock_target = namedtuple("Target",
-                                 "init_hooks name features core")(lambda _, __ : None,
-                                                                  "Junk", [], "Cortex-M3")
+        mock_target = make_mock_target(lambda _, __ : None,
+                                       "Junk", [], "Cortex-M3", TOOLCHAINS)
         mock_config_init.return_value = namedtuple(
             "Config", "target has_regions name")(mock_target, False, None)
 
diff --git a/tools/test/detect_targets_test.py b/tools/test/detect_targets_test.py
new file mode 100644
index 00000000000..be21a32956b
--- /dev/null
+++ b/tools/test/detect_targets_test.py
@@ -0,0 +1,160 @@
+"""
+mbed SDK
+Copyright (c) 2017 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import unittest
+from mock import patch
+from tools.detect_targets import get_interface_version
+
+
+class MbedLsToolsMock():
+    """
+    Mock of mbedls tools
+    """
+    
+    def __init__(self, test_type):
+        self.interface_test_type = test_type
+    
+    def get_details_txt(self, mount_point):
+        return self.details_txt_types[self.interface_test_type];
+    
+    # Static details.txt types.
+    details_txt_types = {    
+        'details_valid_interface_version' : {
+            'Unique ID': '0226000029164e45002f0012706e0006f301000097969900',
+            'HIF ID': '97969900',
+            'Auto Reset': '0',
+            'Automation allowed': '0',
+            'Daplink Mode': 'Interface',
+            'Interface Version': '0240',
+            'Git SHA': 'c765cbb590f57598756683254ca38b211693ae5e',
+            'Local Mods': '0',
+            'USB Interfaces': 'MSD, CDC, HID',
+            'Interface CRC': '0x26764ebf'
+        },
+        'details_valid_version' : {
+            'Version': '0226',
+            'Build':   'Aug 24 2015 17:06:30',
+            'Git Commit SHA': '27a236b9fe39c674a703c5c89655fbd26b8e27e1',
+            'Git Local mods': 'Yes'
+        }, 
+        'details_missing_interface_version' : {
+            'Unique ID': '0226000033514e450044500585d4001de981000097969900',
+            'HIC ID': '97969900',
+            'Auto Reset': '0',
+            'Automation allowed': '0',
+            'Overflow detection': '0',
+            'Daplink Mode': 'Interface',
+            'Git SHA': 'b403a07e3696cee1e116d44cbdd64446e056ce38',
+            'Local Mods': '0',
+            'USB Interfaces': 'MSD, CDC, HID',
+            'Interface CRC': '0x4d98bf7e',
+            'Remount count': '0'
+        },
+        'details_invalid_none' : None
+    }
+
+"""
+Tests for detect_targets.py
+"""
+
+class DetectTargetsTest(unittest.TestCase):
+    """
+    Test cases for Detect Target functionality
+    """
+
+    def setUp(self):
+        """
+        Called before each test case
+
+        :return:
+        """      
+        self.missing_mount_point = None
+        self.mount_point = "D:"
+
+    def tearDown(self):
+        """
+        Nothing to tear down.
+        Called after each test case
+
+        :return:
+        """
+        pass
+    
+    @patch("mbed_lstools.create", return_value=MbedLsToolsMock('details_valid_interface_version'))
+    def test_interface_version_valid(self, mbed_lstools_mock):
+        """
+        Test that checks function returns correctly when given a valid Interface Version
+        
+        :param mbed_lstools_mock: Mocks Mbed LS tools with MbedLsToolsMock
+        :return 
+        """
+
+        interface_version = get_interface_version(self.mount_point)
+        assert interface_version == '0240'
+        
+    @patch("mbed_lstools.create", return_value=MbedLsToolsMock('details_valid_version'))
+    def test_version_valid(self, mbed_lstools_mock):
+        """
+        Test that checks function returns correctly when given a valid Version
+        
+        :param mbed_lstools_mock: Mocks Mbed LS tools with MbedLsToolsMock
+        :return 
+        """
+
+        interface_version = get_interface_version(self.mount_point)
+        assert interface_version == '0226'
+        
+    @patch("mbed_lstools.create", return_value=MbedLsToolsMock('details_missing_interface_version'))
+    def test_interface_version_missing_interface_version(self, mbed_lstools_mock):
+        """
+        Test that checks function returns correctly when DETAILS.txt is present
+        but an interface version is not listed.
+        
+        :param mbed_lstools_mock: Mocks Mbed LS tools with MbedLsToolsMock
+        :return 
+        """
+
+        interface_version = get_interface_version(self.mount_point)
+        assert interface_version == 'unknown'
+        
+    @patch("mbed_lstools.create", return_value=MbedLsToolsMock('details_invalid_none'))
+    def test_version_none(self, mbed_lstools_mock):
+        """
+        Test that checks function returns correctly when a valid mount point is supplied
+        but DETAILS.txt is not present.
+        
+        :param mbed_lstools_mock: Mocks Mbed LS tools with MbedLsToolsMock
+        :return 
+        """
+        
+        interface_version = get_interface_version(self.mount_point)
+        assert interface_version == 'unknown'
+    
+    @patch("mbed_lstools.create", return_value=MbedLsToolsMock('details_invalid_none'))
+    def test_interface_version_missing_mount_point(self, mbed_lstools_mock):
+        """
+        Test that checks function returns correctly when no mount point is supplied.
+        
+        :param mbed_lstools_mock: Mocks Mbed LS tools with MbedLsToolsMock
+        :return 
+        """
+        
+        interface_version = get_interface_version(self.missing_mount_point)
+        assert interface_version == 'unknown'
+
+if __name__ == '__main__':
+    unittest.main()
diff --git a/tools/test/examples/examples.json b/tools/test/examples/examples.json
index 884dd8e22bb..23f17c1ff80 100644
--- a/tools/test/examples/examples.json
+++ b/tools/test/examples/examples.json
@@ -7,17 +7,17 @@
       },
       "via-branch" : {
         "help" : "-b cmd line option. Update dst branch, created from src branch",
-        "src-branch" : "mbed-os-5.5.0-rc1-oob",
-        "dst-branch" : "mbed-os-5.5.0-rc2-oob"    
+        "src-branch" : "mbed-os-5.6.0-oob2",
+        "dst-branch" : "mbed-os-5.6.0-oob2"    
       },
-      "tag" : "mbed-os-5.5.0-rc2"
+      "tag" : "mbed-os-5.6.2"
   },
   "examples": [
     {
       "name": "mbed-os-example-blinky",
       "github": "https://github.com/ARMmbed/mbed-os-example-blinky",
       "mbed": [
-          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-blinky"
+          "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-blinky"
       ],
       "test-repo-source": "github",
       "features" : [],
@@ -32,10 +32,10 @@
       "name": "mbed-os-example-tls",
       "github": "https://github.com/ARMmbed/mbed-os-example-tls",
       "mbed": [
-          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-tls-benchmark",
-          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-tls-tls-client",
-          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-tls-hashing",
-          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-tls-authcrypt"
+          "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-tls-benchmark",
+          "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-tls-tls-client",
+          "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-tls-hashing",
+          "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-tls-authcrypt"
       ],
       "test-repo-source": "mbed",
       "features" : [],
@@ -50,7 +50,7 @@
       "name": "mbed-os-example-mesh-minimal",
       "github":"https://github.com/ARMmbed/mbed-os-example-mesh-minimal",
       "mbed": [
-          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-mesh-minimal"
+          "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-mesh-minimal"
       ],
       "test-repo-source": "github",
       "features" : [],
@@ -68,16 +68,14 @@
       "name": "mbed-os-example-ble",
       "github":"https://github.com/ARMmbed/mbed-os-example-ble",
       "mbed": [
-          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-Beacon",
-          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-HeartRate",
-          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-Thermometer",
-          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-LEDBlinker",
-          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-LED",
-          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-GAPButton",
-          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-EddystoneService",
-          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-EddystoneObserver",
-          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-Button",
-          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-BatteryLevel"
+          "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-ble-Beacon",
+          "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-ble-HeartRate",
+          "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-ble-Thermometer",
+          "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-ble-LEDBlinker",
+          "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-ble-LED",
+          "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-ble-GAPButton",
+          "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-ble-Button",
+          "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-ble-BatteryLevel"
       ],
       "test-repo-source": "mbed",
       "features" : ["BLE"],
@@ -92,7 +90,7 @@
       "name": "mbed-os-example-client",
       "github":"https://github.com/ARMmbed/mbed-os-example-client",
       "mbed": [
-          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-client"
+          "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-client"
       ],
       "test-repo-source": "github",
       "features" : ["LWIP"],
@@ -174,7 +172,7 @@
       "name": "mbed-os-example-bootloader",
       "github":"https://github.com/ARMmbed/mbed-os-example-bootloader",
       "mbed": [
-          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-bootloader"
+          "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-bootloader"
       ],
       "test-repo-source": "github",
       "features" : [],
@@ -189,7 +187,7 @@
       "name": "mbed-os-example-fat-filesystem",
       "github":"https://github.com/ARMmbed/mbed-os-example-fat-filesystem",
       "mbed": [
-          "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-fat-filesystem"
+          "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-fat-filesystem"
       ],
       "test-repo-source": "github",
       "features" : [],
diff --git a/tools/test/examples/examples.py b/tools/test/examples/examples.py
index 4a6adcd6474..fcc3485baf2 100644
--- a/tools/test/examples/examples.py
+++ b/tools/test/examples/examples.py
@@ -54,6 +54,11 @@ def main():
                                 argparse_force_uppercase_type(
                                     official_target_names, "MCU")),
                             default=official_target_names)
+
+    compile_cmd.add_argument("--profile",
+                             help=("build profile file"),
+                             metavar="profile")
+
     export_cmd = subparsers.add_parser("export")
     export_cmd.set_defaults(fn=do_export),
     export_cmd.add_argument(
@@ -111,7 +116,7 @@ def do_deploy(_, config, examples):
 def do_compile(args, config, examples):
     """Do the compile step"""
     results = {}
-    results = lib.compile_repos(config, args.toolchains, args.mcu, examples)
+    results = lib.compile_repos(config, args.toolchains, args.mcu, args.profile, examples)
     
     lib.print_summary(results)
     failures = lib.get_num_failures(results)
diff --git a/tools/test/examples/examples_lib.py b/tools/test/examples/examples_lib.py
index 99aa11a5d42..5ff5de8444c 100644
--- a/tools/test/examples/examples_lib.py
+++ b/tools/test/examples/examples_lib.py
@@ -169,7 +169,7 @@ def source_repos(config, examples):
 
                 subprocess.call(["mbed-cli", "import", repo_info['repo']])
 
-def clone_repos(config, examples):
+def clone_repos(config, examples , retry = 3):
     """ Clones each of the repos associated with the specific examples name from the
         json config file. Note if there is already a clone of the repo then it will first
         be removed to ensure a clean, up to date cloning.
@@ -185,8 +185,11 @@ def clone_repos(config, examples):
                 if os.path.exists(name):
                     print("'%s' example directory already exists. Deleting..." % name)
                     rmtree(name)
-
-                subprocess.call([repo_info['type'], "clone", repo_info['repo']])
+                for i in range(0, retry):
+                    if subprocess.call([repo_info['type'], "clone", repo_info['repo']]) == 0:
+                        break
+                else:
+                    print("ERROR : unable to clone the repo {}".format(name))
 
 def deploy_repos(config, examples):
     """ If the example directory exists as provided by the json config file,
@@ -289,7 +292,7 @@ def status(message):
                         status("SUCCESS exporting")
                         status("Building")
                         try:
-                            if EXPORTERS[ide].build(example_project_name):
+                            if EXPORTERS[ide].build(example_project_name, cleanup=False):
                                 status("FAILURE building")
                                 build_failures.append(example_name)
                             else:
@@ -311,7 +314,7 @@ def status(message):
     return results
 
 
-def compile_repos(config, toolchains, targets, examples):
+def compile_repos(config, toolchains, targets, profile, examples):
     """Compiles combinations of example programs, targets and compile chains.
 
        The results are returned in a [key: value] dictionary format:
@@ -355,8 +358,14 @@ def compile_repos(config, toolchains, targets, examples):
                                                                 valid_choices(example['toolchains'], toolchains),
                                                                 example['features']):
                     print("Compiling %s for %s, %s" % (name, target, toolchain))
-                    proc = subprocess.Popen(["mbed-cli", "compile", "-t", toolchain,
-                                             "-m", target, "-v"])
+                    build_command = ["mbed-cli", "compile", "-t", toolchain, "-m", target, "-v"]
+
+                    if profile:
+                        build_command.append("--profile")
+                        build_command.append(profile)
+
+                    proc = subprocess.Popen(build_command)
+
                     proc.wait()
                     example_summary = "{} {} {}".format(name, target, toolchain)
                     if proc.returncode:
diff --git a/tools/test/examples/update.py b/tools/test/examples/update.py
index 64b6a66fc73..a385d6fbe15 100644
--- a/tools/test/examples/update.py
+++ b/tools/test/examples/update.py
@@ -36,22 +36,21 @@
 #
 # Command usage:
 #
-# update.py -c <config file> - T <github_token> -l <logging level> -f -b 
+# update.py -c <config file> - T <github_token> -f -b -s
 #
 # Where:
 # -c <config file> - Optional path to an examples file.
 #                    If not proved the default is 'examples.json'
 # -T <github_token> - GitHub token for secure access (required)
-# -l <logging level> - Optional Level for providing logging output. Can be one of,
-#                      CRITICAL, ERROR, WARNING, INFO, DEBUG
-#                      If not provided the default is 'INFO'
 # -f                 - Update forked repos. This will use the 'github-user' parameter in
 #                      the 'via-fork' section.
 # -b                 - Update branched repos. This will use the "src-branch" and 
 #                      "dst-branch" parameters in the 'via-branch' section. The destination
 #                      branch is created from the source branch (if it doesn't already exist).
+# -s               - Show the status of any pull requests with a tag matching that in the 
+#                    json config file
 # 
-# The options -f and -b are mutually exlusive. Only one can be specified.
+# The options -f, -b and -s are mutually exlusive. Only one can be specified.
 #
 #
 
@@ -75,16 +74,34 @@
 import examples_lib as lib
 from examples_lib import SUPPORTED_TOOLCHAINS
 
+userlog = logging.getLogger("Update")
+
+# Set logging level
+userlog.setLevel(logging.DEBUG)
+
+# Everything is output to the log file
+logfile = os.path.join(os.getcwd(), 'update.log')
+fh = logging.FileHandler(logfile)
+fh.setLevel(logging.DEBUG)
+
+# create console handler with a higher log level
+ch = logging.StreamHandler()
+ch.setLevel(logging.INFO)
+
+formatter = logging.Formatter('%(name)s: %(levelname)s - %(message)s')
+ch.setFormatter(formatter)
+fh.setFormatter(formatter)    
+
+# add the handlers to the logger
+userlog.addHandler(fh)
+userlog.addHandler(ch)
+
 def run_cmd(command, exit_on_failure=False):
-    """ Run a system command and return the result status
+    """ Run a system command returning a status result
     
-    Description:
+    This is just a wrapper for the run_cmd_with_output() function, but
+    only returns the status of the call.
     
-    Passes a command to the system and returns a True/False result, once the 
-    command has been executed, indicating success/failure. Commands are passed
-    as a list of tokens. 
-    E.g. The command 'git remote -v' would be passed in as ['git', 'remote', '-v']
-
     Args:
     command - system command as a list of tokens
     exit_on_failure - If True exit the program on failure (default = False)
@@ -92,49 +109,41 @@ def run_cmd(command, exit_on_failure=False):
     Returns:
     return_code - True/False indicating the success/failure of the command
     """
-    update_log.debug('[Exec] %s', ' '.join(command))
-    return_code = subprocess.call(command, shell=True)
-    
-    if return_code:
-        update_log.warning("Command '%s' failed with return code: %s", 
-                           ' '.join(command), return_code)
-        if exit_on_failure:
-            sys.exit(1)
-    
+    return_code, _ = run_cmd_with_output(command, exit_on_failure)       
     return return_code
 
 def run_cmd_with_output(command, exit_on_failure=False):
-    """ Run a system command and return the result status plus output  
+    """ Run a system command returning a status result and any command output
     
-    Description:
-        
     Passes a command to the system and returns a True/False result once the 
     command has been executed, indicating success/failure. If the command was 
     successful then the output from the command is returned to the caller.
-    Commands are passed as a list of tokens. 
-    E.g. The command 'git remote -v' would be passed in as ['git', 'remote', '-v']
+    Commands are passed as a string. 
+    E.g. The command 'git remote -v' would be passed in as "git remote -v"
 
     Args:
-    command - system command as a list of tokens
+    command - system command as a string
     exit_on_failure - If True exit the program on failure (default = False)
     
     Returns:
-    returncode - True/False indicating the success/failure of the command
+    return_code - True/False indicating the success/failure of the command
     output - The output of the command if it was successful, else empty string
     """
-    update_log.debug('[Exec] %s', ' '.join(command))
+    text = '[Exec] ' + command
+    userlog.debug(text)
     returncode = 0
     output = ""
     try:
         output = subprocess.check_output(command, shell=True)
     except subprocess.CalledProcessError as e:
-        update_log.warning("Command '%s' failed with return code: %s", 
-                           ' '.join(command), e.returncode)
+        text = "The command " + str(command) + "failed with return code: " + str(e.returncode)
+        userlog.warning(text)
         returncode = e.returncode
         if exit_on_failure:
             sys.exit(1)
     return returncode, output
 
+
 def rmtree_readonly(directory):
     """ Deletes a readonly directory tree.
         
@@ -198,7 +207,7 @@ def upgrade_single_example(example, tag, directory, ref):
         
         os.rename("mbed-os.lib", "mbed-os.lib_bak")
     else:
-        update_log.error("Failed to backup mbed-os.lib prior to updating.")
+        userlog.error("Failed to backup mbed-os.lib prior to updating.")
         return False
     
     # mbed-os.lib file contains one line with the following format
@@ -221,7 +230,7 @@ def upgrade_single_example(example, tag, directory, ref):
 
     if updated:
         # Setup and run the git add command
-        cmd = ['git', 'add', 'mbed-os.lib']
+        cmd = "git add mbed-os.lib"
         return_code = run_cmd(cmd)
 
     os.chdir(cwd)
@@ -242,12 +251,12 @@ def prepare_fork(arm_example):
     """
 
     logstr = "In: " + os.getcwd()
-    update_log.debug(logstr)
+    userlog.debug(logstr)
 
-    for cmd in [['git', 'remote', 'add', 'armmbed', arm_example],
-                ['git', 'fetch', 'armmbed'],
-                ['git', 'reset', '--hard', 'armmbed/master'],
-                ['git', 'push', '-f', 'origin']]:
+    for cmd in ["git remote add armmbed " + str(arm_example),
+                "git fetch armmbed",
+                "git reset --hard armmbed/master",
+                "git push -f origin"]:
         run_cmd(cmd, exit_on_failure=True)
 
 def prepare_branch(src, dst):
@@ -265,25 +274,34 @@ def prepare_branch(src, dst):
     
     """
 
-    update_log.debug("Preparing branch: %s", dst)
+    userlog.debug("Preparing branch: %s", dst)
 
     # Check if branch already exists or not.
-    cmd = ['git', 'branch']
+    # We can use the 'git branch -r' command. This returns all the remote branches for
+    # the current repo.
+    # The output consists of a list of lines of the form:
+    # origin/<branch>
+    # From these we need to extract just the branch names to a list and then check if 
+    # the specified dst exists in that list
+    branches = []
+    cmd = "git branch -r"
     _, output = run_cmd_with_output(cmd, exit_on_failure=True)
 
-    if not dst in output:
+    branches = [line.split('/')[1] for line in output.split('\n') if 'origin' in line and not '->' in line]
+  
+    if not dst in branches:
         
         # OOB branch does not exist thus create it, first ensuring we are on 
         # the src branch and then check it out
 
-        for cmd in [['git', 'checkout', src],
-                    ['git', 'checkout', '-b', dst],
-                    ['git', 'push', '-u', 'origin', dst]]:
+        for cmd in ["git checkout " + str(src),
+                    "git checkout -b " + str(dst),
+                    "git push -u origin " + str(dst)]:
 
             run_cmd(cmd, exit_on_failure=True)
 
     else: 
-        cmd = ['git', 'checkout', dst]
+        cmd = "git checkout " + str(dst)
         run_cmd(cmd, exit_on_failure=True)
    
 def upgrade_example(github, example, tag, ref, user, src, dst, template):
@@ -321,18 +339,18 @@ def upgrade_example(github, example, tag, ref, user, src, dst, template):
         user = 'ARMmbed'
                 
     ret = False
-    update_log.info("Updating example '%s'", example['name'])
-    update_log.debug("User: %s", user)
-    update_log.debug("Src branch: %s", (src or "None"))
-    update_log.debug("Dst branch: %s", (dst or "None"))
+    userlog.info("Updating example '%s'", example['name'])
+    userlog.debug("User: %s", user)
+    userlog.debug("Src branch: %s", (src or "None"))
+    userlog.debug("Dst branch: %s", (dst or "None"))
 
     cwd = os.getcwd()
 
     update_repo = "https://github.com/" + user + '/' + example['name'] 
-    update_log.debug("Update repository: %s", update_repo)
+    userlog.debug("Update repository: %s", update_repo)
 
     # Clone the example repo
-    clone_cmd = ['git', 'clone', update_repo]
+    clone_cmd = "git clone " +  str(update_repo)
     return_code = run_cmd(clone_cmd)
     
     if not return_code:
@@ -353,16 +371,13 @@ def upgrade_example(github, example, tag, ref, user, src, dst, template):
                 os.chdir(cwd)
                 return False
 
-        # Setup the default commit message
-        commit_message = 'Updating mbed-os to ' + tag 
-
         # Setup and run the commit command
-        commit_cmd = ['git', 'commit', '-m', commit_message]
+        commit_cmd = "git commit -m \"Updating mbed-os to " + tag + "\""
         return_code = run_cmd(commit_cmd)
         if not return_code:
 
             # Setup and run the push command
-            push_cmd = ['git', 'push', 'origin']
+            push_cmd = "git push origin"
             return_code = run_cmd(push_cmd)
             
             if not return_code:
@@ -370,13 +385,13 @@ def upgrade_example(github, example, tag, ref, user, src, dst, template):
                 if user != 'ARMmbed': 
                     
                     upstream_repo = 'ARMmbed/'+ example['name']
-                    update_log.debug("Upstream repository: %s", upstream_repo)
+                    userlog.debug("Upstream repository: %s", upstream_repo)
                     # Check access to mbed-os repo
                     try:
                         repo = github.get_repo(upstream_repo, False)
 
                     except:
-                        update_log.error("Upstream repo: %s, does not exist - skipping", upstream_repo)
+                        userlog.error("Upstream repo: %s, does not exist - skipping", upstream_repo)
                         return False
            
                     jinja_loader = FileSystemLoader(template)
@@ -391,15 +406,15 @@ def upgrade_example(github, example, tag, ref, user, src, dst, template):
                         ret = True
                     except GithubException as e:
                         # Default to False
-                         update_log.error("Pull request creation failed with error: %s", e)
+                         userlog.error("Pull request creation failed with error: %s", e)
                 else:
                     ret = True                    
             else:
-                update_log.error("Git push command failed.")
+                userlog.error("Git push command failed.")
         else:
-            update_log.error("Git commit command failed.")
+            userlog.error("Git commit command failed.")
     else:
-        update_log.error("Git clone %s failed", update_repo)
+        userlog.error("Git clone %s failed", update_repo)
 
     os.chdir(cwd)
     return ret
@@ -413,44 +428,73 @@ def create_work_directory(path):
     
     """
     if os.path.exists(path):
-        update_log.info("'%s' directory already exists. Deleting...", path)
+        userlog.info("'%s' directory already exists. Deleting...", path)
         rmtree_readonly(path)
     
     os.makedirs(path)
 
+def check_update_status(examples, github, tag):
+    """ Check the status of previously raised update pull requests
+    
+    Args:
+    examples - list of examples which should have had PRs raised against them. 
+    github - github rest API instance
+    tag - release tag used for the update
+    
+    """
+
+    for example in examples:
+
+        repo_name = ''.join(['ARMmbed/', example['name']])
+        try:
+            repo = github.get_repo(repo_name, False)
+
+        except Exception as exc:
+            text = "Cannot access: " + str(repo_name)
+            userlog.error(text)
+            userlog.exception(exc)
+            sys.exit(1)
+
+        # Create the full repository filter component
+        org_str = ''.join(['repo:ARMmbed/', example['name']])
+        filt = ' '.join([org_str, 'is:pr', tag])        
+        merged = False
+
+        issues = github.search_issues(query=(filt))
+        pr_list = [repo.get_pull(issue.number) for issue in issues]
+
+        # Should only be one matching PR but just in case, go through paginated list  
+        for pr in pr_list:
+            if pr.merged:
+                userlog.info("%s - '%s': MERGED", example['name'], pr.title)
+            elif pr.state == 'open':
+                userlog.info("%s - '%s': PENDING", example['name'], pr.title)
+            elif pr.state == 'closed':
+                userlog.info("%s - '%s': CLOSED NOT MERGED", example['name'], pr.title)
+            else:
+                userlog.error("%s: Cannot find a pull request for %s", example['name'], tag)
+
 if __name__ == '__main__':
 
     parser = argparse.ArgumentParser(description=__doc__,
                                      formatter_class=argparse.RawDescriptionHelpFormatter)
     parser.add_argument('-c', '--config_file', help="Path to the configuration file (default is 'examples.json')", default='examples.json')
     parser.add_argument('-T', '--github_token', help="GitHub token for secure access")
-    parser.add_argument('-l', '--log-level', 
-                        help="Level for providing logging output", 
-                        default='INFO')
     
     exclusive = parser.add_mutually_exclusive_group(required=True)
     exclusive.add_argument('-f', '--fork', help="Update a fork", action='store_true')
     exclusive.add_argument('-b', '--branch', help="Update a branch", action='store_true')
+    exclusive.add_argument('-s', '--status', help="Show examples update status", action='store_true')
     
     args = parser.parse_args()
 
-    default = getattr(logging, 'INFO')
-    level = getattr(logging, args.log_level.upper(), default)
-        
-    # Set logging level
-    logging.basicConfig(level=level)
-
-    update_log = logging.getLogger("Update")
-
     # Load the config file
     with open(os.path.join(os.path.dirname(__file__), args.config_file)) as config:
         if not config:
-            update_log.error("Failed to load config file '%s'", args.config_file)
+            userlog.error("Failed to load config file '%s'", args.config_file)
             sys.exit(1)
         json_data = json.load(config)
         
-    # Create working directory
-    create_work_directory('examples')
 
     github = Github(args.github_token)
     config = json_data['update-config']
@@ -460,6 +504,15 @@ def create_work_directory(path):
     src = "master"
     dst = None
 
+    if args.status:
+        
+        # This option should only be called after an update has been performed
+        check_update_status(json_data['examples'], github, tag)
+        exit(0)
+
+    # Create working directory
+    create_work_directory('examples')
+
     if args.fork:
         user = config['via-fork']['github-user']
     elif args.branch:
@@ -470,11 +523,11 @@ def create_work_directory(path):
         exit(1)    
 
     # Get the github sha corresponding to the specified mbed-os tag
-    cmd = ['git', 'rev-list', '-1', tag]
+    cmd = "git rev-list -1 " + tag
     return_code, ref = run_cmd_with_output(cmd) 
 
     if return_code:
-        update_log.error("Could not obtain SHA for tag: %s",  tag)
+        userlog.error("Could not obtain SHA for tag: %s",  tag)
         sys.exit(1)
 
     # Loop through the examples
@@ -499,11 +552,11 @@ def create_work_directory(path):
     os.chdir('../')
     
     # Finish the script and report the results
-    update_log.info("Finished updating examples")
+    userlog.info("Finished updating examples")
     if successes:
         for success in successes:
-            update_log.info(" SUCCEEDED: %s", success)
+            userlog.info(" SUCCEEDED: %s", success)
     
     if failures:
         for fail in failures:
-            update_log.info(" FAILED: %s", fail)
+            userlog.info(" FAILED: %s", fail)
diff --git a/tools/test/memap/arm.map b/tools/test/memap/arm.map
new file mode 100644
index 00000000000..0ecc1a5bdc0
--- /dev/null
+++ b/tools/test/memap/arm.map
@@ -0,0 +1,47 @@
+Component: ARM Compiler 5.06 update 5 (build 528) Tool: armlink [4d35e2]
+
+==============================================================================
+
+Memory Map of the image
+
+  Image Entry point : 0x0001b0c1
+
+  Load Region LR_IROM1 (Base: 0x0001b000, Size: 0x0000ed04, Max: 0x00025000, ABSOLUTE, COMPRESSED[0x0000e23c])
+
+    Execution Region ER_IROM1 (Base: 0x0001b000, Size: 0x0000e1c4, Max: 0x00025000, ABSOLUTE)
+
+    Base Addr    Size         Type   Attr      Idx    E Section Name        Object
+
+    0x0001b000   0x000000c0   Data   RO         7002    RESET               /common/path/startup/startup.o
+    0x0001b0c0   0x00000008   Code   RO         8820  * !!!main             /installed/libs/../lib/armlib/c_p.l(__main.o)
+    0x0001b26c   0x00000098   Code   RO         6076    .text               /common/path/irqs/irqs.o
+    0x000206a0   0x00000036   Code   RO           27    i._Z9time_funcPN4mbed5TimerEi  /common/path/main.o
+    0x200039b4   0x00000018   Data   RW         8092    .data               /common/path/data/data.o
+    0x20003af8   0x00000198   Zero   RW           57    .bss                /common/path/data/data.o
+
+==============================================================================
+
+Image component sizes
+
+
+      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   
+
+       344        368          0         24        408      36188   Object Totals
+         8          0          0          0          0       7596   Library Totals
+
+==============================================================================
+
+
+      Code (inc. data)   RO Data    RW Data    ZI Data      Debug   
+
+       352        376          0         24        408      17208   Grand Totals
+       352        376          0         24        408      17208   ELF Image Totals (compressed)
+       352        376          0         24          0          0   ROM Totals
+
+==============================================================================
+
+    Total RO  Size (Code + RO Data)                  352 (   0.35kB)
+    Total RW  Size (RW Data + ZI Data)               432 (   0.43kB)
+    Total ROM Size (Code + RO Data + RW Data)        376 (   0.37kB)
+
+==============================================================================
diff --git a/tools/test/memap/gcc.map b/tools/test/memap/gcc.map
new file mode 100644
index 00000000000..58ff289e973
--- /dev/null
+++ b/tools/test/memap/gcc.map
@@ -0,0 +1,25 @@
+Archive member included to satisfy reference by file (symbol)
+
+Linker script and memory map
+.text           0x000000000001b000    0x11a30
+ .Vectors       0x000000000001b000       0x98 /common/path/irqs/irqs.o
+                0x000000000001b168       0x36 /common/path/main.o
+                0x000000000001b168                count5(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int)
+                0x000000000001b200       0xc0 /common/path/startup/startup.o
+                0x000000000001b200                startup()
+                0x0000000000024020        0x8 /usr/lib/gcc/arm-none-eabi/7.1.0/../../../../arm-none-eabi/lib/armv6-m/libd16M_tlf.a(__main.o)
+
+.data           0x0000000020002ef8      0xac8 load address 0x000000000002ca38
+                0x0000000020002ef8                __data_start__ = .
+ *(vtable)
+ *(.data*)
+                0x0000000020002ef8       0x18 /common/path/data/data.o
+                0x0000000020002ef8                some_global_var
+
+.bss            0x0000000020003a80     0x2050 load address 0x000000000002d5c0
+                0x0000000020003a80                . = ALIGN (0x4)
+                0x0000000020003a80                __bss_start__ = .
+ *(.bss*)
+ .bss.completed.8574
+ .bss.counter   0x0000000020003c08      0x198 /common/path/data.o
+                0x0000000020003c08                some_zero_init_var
\ No newline at end of file
diff --git a/tools/test/memap/iar.map b/tools/test/memap/iar.map
new file mode 100644
index 00000000000..0fc3aae55d3
--- /dev/null
+++ b/tools/test/memap/iar.map
@@ -0,0 +1,86 @@
+###############################################################################
+#
+# IAR ELF Linker V7.80.1.28/LNX for ARM                   18/Sep/2017  14:26:09
+# Copyright 2007-2016 IAR Systems AB.
+#
+#    Output file  =  
+#        /common/path/project.elf
+#    Map file     =  
+#        /common/path/project.map
+#    Command line =  
+#        -f
+#        /common/path/.link_files.txt
+#        (-o
+#        --map=/common/path/project.map
+#        /common/path/project.elf
+#        /common/path/main.o
+#        /common/path/startup/startup.o
+#        /common/path/irqs/irqs.o
+#        /common/path/data/data.o
+#
+###############################################################################
+
+*******************************************************************************
+*** RUNTIME MODEL ATTRIBUTES
+***
+
+CppFlavor                     = *
+__CPP_Exceptions              = Disabled
+__CPP_Language                = C++
+__Heap_Handler                = DLMalloc
+__SystemLibrary               = DLib
+__dlib_dynamic_initialization = postponed
+__dlib_has_iterator_debugging = 0
+__dlib_jmp_buf_num_elements   = 8
+
+
+*******************************************************************************
+*** PLACEMENT SUMMARY
+***
+
+"A0":  place at 0x0001b000 { ro section .intvec };
+"P1":  place in [from 0x0001b0c0 to 0x0003ffff] { ro };
+"P2":  place in [from 0x20002ef8 to 0x20007fff] { rw, block HEAP, block CSTACK };
+do not initialize { section .noinit };
+initialize by copy { rw };
+ { section .intvec };
+
+  Section               Kind        Address    Size  Object
+  -------               ----        -------    ----  ------
+"A0":                                          0xc0
+  .intvec               ro code  0x0001b000    0xc0  startup.o [4]
+                               - 0x0001b0c0    0xc0
+
+"P1":                                         0x
+  .text                 ro code  0x0001c753    0x36  main.o [3]
+  .text                 ro code  0x0001cfff    0x98  irqs.o [5]
+  .text                 ro code  0x0001c778     0x8  __main.o [67]
+
+"P2", part 1 of 2:                             0x18
+  P2-1                           0x20002ef8    0x18  <Init block>
+    .data               inited   0x20002fa8    0x18  data.o [6]
+
+"P2", part 2 of 2:                            0x198
+  P2-2                           0x20005388   0x198  <Init block>
+    .bss                  zero   0x20002fa8   0x198  data.o [6]
+
+*******************************************************************************
+*** INIT TABLE
+***
+
+*******************************************************************************
+*** MODULE SUMMARY
+***
+
+d16M_tlf.a: [67]
+    __main.o                          8
+    ------------------------------------------------
+    Total:                            8
+
+    Linker created                             
+---------------------------------------------------
+    Grand Total:                      
+
+*******************************************************************************
+*** ENTRY LIST
+***
\ No newline at end of file
diff --git a/tools/test/memap/parse_test.py b/tools/test/memap/parse_test.py
new file mode 100644
index 00000000000..51eb9cae05a
--- /dev/null
+++ b/tools/test/memap/parse_test.py
@@ -0,0 +1,61 @@
+import sys
+from io import open
+from os.path import isfile, join, dirname
+import json
+
+import pytest
+
+from tools.memap import MemapParser
+from copy import deepcopy
+
+
+PARSED_ARM_DATA = {
+    "startup/startup.o": {".text": 0xc0},
+    "[lib]/c_p.l/__main.o": {".text": 8},
+    "irqs/irqs.o": {".text": 0x98},
+    "data/data.o": {".data": 0x18, ".bss": 0x198},
+    "main.o": {".text": 0x36},
+}
+
+def test_parse_armcc():
+    memap = MemapParser()
+    memap.parse_map_file_armcc(open(join(dirname(__file__), "arm.map")))
+    assert memap.modules == PARSED_ARM_DATA
+
+PARSED_IAR_GCC_DATA = {
+    "startup/startup.o": {".text": 0xc0},
+    "[lib]/d16M_tlf.a/__main.o": {".text": 8},
+    "irqs/irqs.o": {".text": 0x98},
+    "data/data.o": {".data": 0x18, ".bss": 0x198},
+    "main.o": {".text": 0x36},
+}
+
+def test_parse_iar():
+    memap = MemapParser()
+    memap.parse_map_file_iar(open(join(dirname(__file__), "iar.map")))
+    assert memap.modules == PARSED_IAR_GCC_DATA
+
+def test_parse_gcc():
+    memap = MemapParser()
+    memap.parse_map_file_gcc(open(join(dirname(__file__), "gcc.map")))
+    assert memap.modules == PARSED_IAR_GCC_DATA
+
+
+def test_add_empty_module():
+    memap = MemapParser()
+    old_modules = deepcopy(memap.modules)
+    memap.module_add("", 8, ".data")
+    assert(old_modules == memap.modules)
+    memap.module_add("main.o", 0, ".text")
+    assert(old_modules == memap.modules)
+    memap.module_add("main.o", 8, "")
+    assert(old_modules == memap.modules)
+
+def test_add_full_module():
+    memap = MemapParser()
+    old_modules = deepcopy(memap.modules)
+    memap.module_add("main.o", 8, ".data")
+    assert(old_modules != memap.modules)
+    assert("main.o" in memap.modules)
+    assert(".data" in memap.modules["main.o"])
+    assert(memap.modules["main.o"][".data"] == 8)
diff --git a/tools/test/toolchains/api_test.py b/tools/test/toolchains/api_test.py
index 81550593db2..d98b1cef1b2 100644
--- a/tools/test/toolchains/api_test.py
+++ b/tools/test/toolchains/api_test.py
@@ -12,7 +12,7 @@
 sys.path.insert(0, ROOT)
 
 from tools.toolchains import TOOLCHAIN_CLASSES, LEGACY_TOOLCHAIN_NAMES,\
-    Resources, TOOLCHAIN_PATHS
+    Resources, TOOLCHAIN_PATHS, mbedToolchain
 from tools.targets import TARGET_MAP
 
 def test_instantiation():
@@ -43,11 +43,15 @@ def test_toolchain_profile_c(profile, source_file):
             toolchain.inc_md5 = ""
             toolchain.build_dir = ""
             toolchain.config = MagicMock(app_config_location=None)
+            for parameter in profile['c'] + profile['common']:
+                assert any(parameter in cmd for cmd in toolchain.cc), \
+                    "Toolchain %s did not propagate arg %s" % (toolchain.name,
+                                                            parameter)
             compile_command = toolchain.compile_command(to_compile,
                                                         to_compile + ".o", [])
             for parameter in profile['c'] + profile['common']:
                 assert any(parameter in cmd for cmd in compile_command), \
-                    "Toolchain %s did not propigate arg %s" % (toolchain.name,
+                    "Toolchain %s did not propagate arg %s" % (toolchain.name,
                                                             parameter)
 
 @given(fixed_dictionaries({
@@ -69,11 +73,15 @@ def test_toolchain_profile_cpp(profile, source_file):
             toolchain.inc_md5 = ""
             toolchain.build_dir = ""
             toolchain.config = MagicMock(app_config_location=None)
+            for parameter in profile['cxx'] + profile['common']:
+                assert any(parameter in cmd for cmd in toolchain.cppc), \
+                    "Toolchain %s did not propagate arg %s" % (toolchain.name,
+                                                            parameter)
             compile_command = toolchain.compile_command(to_compile,
                                                         to_compile + ".o", [])
             for parameter in profile['cxx'] + profile['common']:
                 assert any(parameter in cmd for cmd in compile_command), \
-                    "Toolchain %s did not propigate arg %s" % (toolchain.name,
+                    "Toolchain %s did not propagate arg %s" % (toolchain.name,
                                                             parameter)
 
 @given(fixed_dictionaries({
@@ -94,14 +102,55 @@ def test_toolchain_profile_asm(profile, source_file):
             toolchain = tc_class(TARGET_MAP["K64F"], build_profile=profile)
             toolchain.inc_md5 = ""
             toolchain.build_dir = ""
+            for parameter in profile['asm']:
+                assert any(parameter in cmd for cmd in toolchain.asm), \
+                    "Toolchain %s did not propagate arg %s" % (toolchain.name,
+                                                               parameter)
             compile_command = toolchain.compile_command(to_compile,
                                                         to_compile + ".o", [])
             if not compile_command:
                 assert compile_command, to_compile
             for parameter in profile['asm']:
                 assert any(parameter in cmd for cmd in compile_command), \
-                    "Toolchain %s did not propigate arg %s" % (toolchain.name,
-                                                            parameter)
+                    "Toolchain %s did not propagate arg %s" % (toolchain.name,
+                                                               parameter)
+
+    for name, Class in  TOOLCHAIN_CLASSES.items():
+        CLS = Class(TARGET_MAP["K64F"])
+        assert name == CLS.name or name ==  LEGACY_TOOLCHAIN_NAMES[CLS.name]
+
+@given(fixed_dictionaries({
+    'common': lists(text()),
+    'c': lists(text()),
+    'cxx': lists(text()),
+    'asm': lists(text()),
+    'ld': lists(text(min_size=1))}),
+       lists(text(min_size=1, alphabet=ALPHABET), min_size=1))
+def test_toolchain_profile_ld(profile, source_file):
+    """Test that the appropriate profile parameters are passed to the
+    Linker"""
+    filename = deepcopy(source_file)
+    filename[-1] += ".o"
+    to_compile = os.path.join(*filename)
+    with patch('os.mkdir') as _mkdir,\
+         patch('tools.toolchains.mbedToolchain.default_cmd') as _dflt_cmd:
+        for _, tc_class in TOOLCHAIN_CLASSES.items():
+            toolchain = tc_class(TARGET_MAP["K64F"], build_profile=profile)
+            toolchain.RESPONSE_FILES = False
+            toolchain.inc_md5 = ""
+            toolchain.build_dir = ""
+            for parameter in profile['ld']:
+                assert any(parameter in cmd for cmd in toolchain.ld), \
+                    "Toolchain %s did not propagate arg %s" % (toolchain.name,
+                                                               parameter)
+            toolchain.link(to_compile + ".elf", [to_compile], [], [], None)
+            compile_cmd = _dflt_cmd.call_args_list
+            if not compile_cmd:
+                assert compile_cmd, to_compile
+            for parameter in profile['ld']:
+                assert any(parameter in cmd[0][0] for cmd in compile_cmd), \
+                    "Toolchain %s did not propagate arg %s" % (toolchain.name,
+                                                               parameter)
 
     for name, Class in  TOOLCHAIN_CLASSES.items():
         CLS = Class(TARGET_MAP["K64F"])
diff --git a/tools/test/toolchains/arm_support_test.py b/tools/test/toolchains/arm_support_test.py
new file mode 100644
index 00000000000..f26935a8f7d
--- /dev/null
+++ b/tools/test/toolchains/arm_support_test.py
@@ -0,0 +1,65 @@
+"""Tests for the arm toolchain supported checks"""
+import sys
+import os
+from string import printable
+from copy import deepcopy
+from mock import MagicMock, patch
+from hypothesis import given, settings
+from hypothesis.strategies import text, lists, sampled_from
+
+ROOT = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..",
+                                    ".."))
+sys.path.insert(0, ROOT)
+
+from tools.toolchains.arm import ARM_STD, ARM_MICRO, ARMC6
+from tools.utils import NotSupportedException
+
+ARMC5_CORES = ["Cortex-M0", "Cortex-M0+", "Cortex-M3", "Cortex-M4",
+               "Cortex-M4F", "Cortex-M7", "Cortex-M7F", "Cortex-M7FD"]
+ARMC6_CORES = ARMC5_CORES + ["Cortex-M23", "Cortex-M23-NS",
+                             "Cortex-M33", "CortexM33-NS"]
+
+CORE_SUF_ALPHA = ["MDFNS02347-+"]
+
+@given(lists(sampled_from(["ARM", "uARM", "GCC_ARM", "ARMC6", "IAR", "GARBAGE"])),
+       text(alphabet=CORE_SUF_ALPHA))
+def test_arm_std(supported_toolchains, core):
+    mock_target = MagicMock()
+    mock_target.core = "Cortex-" + core
+    mock_target.supported_toolchains = supported_toolchains
+    try:
+        ARM_STD(mock_target)
+        assert "ARM" in supported_toolchains
+        assert mock_target.core in ARMC5_CORES
+    except NotSupportedException:
+        assert "ARM" not in supported_toolchains or mock_target.core not in ARMC5_CORES
+
+
+@given(lists(sampled_from(["ARM", "uARM", "GCC_ARM", "ARMC6", "IAR", "GARBAGE"])),
+       text(alphabet=CORE_SUF_ALPHA))
+def test_arm_micro(supported_toolchains, core):
+    mock_target = MagicMock()
+    mock_target.core = "Cortex-" + core
+    mock_target.supported_toolchains = supported_toolchains
+    try:
+        ARM_MICRO(mock_target)
+        assert "ARM" in supported_toolchains or "uARM" in supported_toolchains
+        assert mock_target.core in ARMC5_CORES
+    except NotSupportedException:
+        assert ("ARM" not in supported_toolchains and "uARM" not in supported_toolchains)\
+            or mock_target.core not in ARMC5_CORES
+
+
+@given(lists(sampled_from(["ARM", "uARM", "GCC_ARM", "ARMC6", "IAR", "GARBAGE"])),
+       text(alphabet=CORE_SUF_ALPHA))
+def test_armc6(supported_toolchains, core):
+    mock_target = MagicMock()
+    mock_target.core = "Cortex-" + core
+    mock_target.supported_toolchains = supported_toolchains
+    try:
+        ARMC6(mock_target)
+        assert "ARM" in supported_toolchains or "ARMC6" in supported_toolchains
+        assert mock_target.core in ARMC6_CORES
+    except NotSupportedException:
+        assert ("ARM" not in supported_toolchains and "ARMC6" not in supported_toolchains)\
+            or mock_target.core not in ARMC6_CORES
diff --git a/tools/test_api.py b/tools/test_api.py
index 985c318e851..2e7d60a275f 100644
--- a/tools/test_api.py
+++ b/tools/test_api.py
@@ -50,6 +50,7 @@
 from tools.utils import construct_enum
 from tools.memap import MemapParser
 from tools.targets import TARGET_MAP
+import tools.test_configs as TestConfig
 from tools.test_db import BaseDBAccess
 from tools.build_api import build_project, build_mbed_libs, build_lib
 from tools.build_api import get_target_supported_toolchains
@@ -1643,11 +1644,10 @@ def detect_database_verbose(db_url):
 
 
 def get_module_avail(module_name):
-    """ This function returns True if module_name is already impored module
+    """ This function returns True if module_name is already imported module
     """
     return module_name in sys.modules.keys()
 
-
 def get_autodetected_MUTS_list(platform_name_filter=None):
     oldError = None
     if os.name == 'nt':
@@ -1999,6 +1999,19 @@ def test_path_to_name(path, base):
 
     return "-".join(name_parts).lower()
 
+def get_test_config(config_name, target_name):
+    """Finds the path to a test configuration file
+    config_name: path to a custom configuration file OR mbed OS interface "ethernet, wifi_odin, etc"
+    target_name: name of target to determing if mbed OS interface given is valid
+    returns path to config, will return None if no valid config is found
+    """
+    # If they passed in a full path
+    if exists(config_name):
+        # This is a module config
+        return config_name
+    # Otherwise find the path to configuration file based on mbed OS interface
+    return TestConfig.get_config_path(config_name, target_name)
+
 def find_tests(base_dir, target_name, toolchain_name, app_config=None):
     """ Finds all tests in a directory recursively
     base_dir: path to the directory to scan for tests (ex. 'path/to/project')
diff --git a/tools/test_configs/EthernetInterface.json b/tools/test_configs/EthernetInterface.json
new file mode 100644
index 00000000000..69bbac0b3a5
--- /dev/null
+++ b/tools/test_configs/EthernetInterface.json
@@ -0,0 +1,27 @@
+{
+    "config": {
+        "header-file": {
+            "help" : "String for including your driver header file",
+            "value" : "\"EthernetInterface.h\""
+        },
+        "object-construction" : {
+            "value" : "new EthernetInterface()"
+        },
+        "connect-statement" : {
+            "help" : "Must use 'net' variable name",
+            "value" : "((EthernetInterface *)net)->connect()"
+        },
+        "echo-server-addr" : {
+            "help" : "IP address of echo server",
+            "value" : "\"195.34.89.241\""
+        },
+        "echo-server-port" : {
+            "help" : "Port of echo server",
+            "value" : "7"
+        },
+        "tcp-echo-prefix" : {
+            "help" : "Some servers send a prefix before echoed message",
+            "value" : "\"u-blox AG TCP/UDP test service\\n\""
+        }
+    }
+}
diff --git a/tools/test_configs/OdinInterface.json b/tools/test_configs/OdinInterface.json
new file mode 100644
index 00000000000..3ebac83f0ef
--- /dev/null
+++ b/tools/test_configs/OdinInterface.json
@@ -0,0 +1,27 @@
+{
+    "config": {
+        "header-file": {
+            "help" : "String for including your driver header file",
+            "value" : "\"OdinWiFiInterface.h\""
+        },
+        "object-construction" : {
+            "value" : "new OdinWiFiInterface()"
+        },
+        "connect-statement" : {
+            "help" : "Must use 'net' variable name",
+            "value" : "((OdinWiFiInterface *)net)->connect(WIFI_SSID, WIFI_PASSWORD)"
+        },
+        "echo-server-addr" : {
+            "help" : "IP address of echo server",
+            "value" : "\"195.34.89.241\""
+        },
+        "echo-server-port" : {
+            "help" : "Port of echo server",
+            "value" : "7"
+        },
+        "tcp-echo-prefix" : {
+            "help" : "Some servers send a prefix before echoed message",
+            "value" : "\"u-blox AG TCP/UDP test service\\n\""
+        }
+    }
+}
diff --git a/tools/test_configs/Odin_EthernetInterface.json b/tools/test_configs/Odin_EthernetInterface.json
new file mode 100644
index 00000000000..24f48e212ca
--- /dev/null
+++ b/tools/test_configs/Odin_EthernetInterface.json
@@ -0,0 +1,32 @@
+{
+    "config": {
+        "header-file": {
+            "help" : "String for including your driver header file",
+            "value" : "\"EthernetInterface.h\""
+        },
+        "object-construction" : {
+            "value" : "new EthernetInterface()"
+        },
+        "connect-statement" : {
+            "help" : "Must use 'net' variable name",
+            "value" : "((EthernetInterface *)net)->connect()"
+        },
+        "echo-server-addr" : {
+            "help" : "IP address of echo server",
+            "value" : "\"195.34.89.241\""
+        },
+        "echo-server-port" : {
+            "help" : "Port of echo server",
+            "value" : "7"
+        },
+        "tcp-echo-prefix" : {
+            "help" : "Some servers send a prefix before echoed message",
+            "value" : "\"u-blox AG TCP/UDP test service\\n\""
+        }
+    },
+     "target_overrides": {
+         "UBLOX_EVK_ODIN_W2": {
+            "target.device_has_remove": ["EMAC"]
+        }
+    }
+}
diff --git a/tools/test_configs/RealtekInterface.json b/tools/test_configs/RealtekInterface.json
new file mode 100644
index 00000000000..ad4a9ef31b7
--- /dev/null
+++ b/tools/test_configs/RealtekInterface.json
@@ -0,0 +1,27 @@
+{
+    "config": {
+        "header-file": {
+            "help" : "String for including your driver header file",
+            "value" : "\"RTWInterface.h\""
+        },
+        "object-construction" : {
+            "value" : "new RTWInterface()"
+        },
+        "connect-statement" : {
+            "help" : "Must use 'net' variable name, replace WIFI_SSID, WIFI_PASSWORD, WIFI_SECURITY, WIFI_CHANNEL with your WiFi settings",
+            "value" : "((RTWInterface *)net)->connect(WIFI_SSID, WIFI_PASSWORD, WIFI_SECURITY, WIFI_CHANNEL)"
+        },
+        "echo-server-addr" : {
+            "help" : "IP address of echo server",
+            "value" : "\"195.34.89.241\""
+        },
+        "echo-server-port" : {
+            "help" : "Port of echo server",
+            "value" : "7"
+        },
+        "tcp-echo-prefix" : {
+            "help" : "Some servers send a prefix before echoed message",
+            "value" : "\"Realtek Ameba TCP/UDP test service\\n\""
+        }
+    }
+}
diff --git a/tools/test_configs/__init__.py b/tools/test_configs/__init__.py
new file mode 100644
index 00000000000..90666baf248
--- /dev/null
+++ b/tools/test_configs/__init__.py
@@ -0,0 +1,40 @@
+from os.path import dirname, abspath, join
+
+from tools.utils import json_file_to_dict
+from tools.targets import TARGET_MAP
+
+CONFIG_DIR = dirname(abspath(__file__))
+CONFIG_MAP = json_file_to_dict(join(CONFIG_DIR, "config_paths.json"))
+TARGET_CONFIGS = json_file_to_dict(join(CONFIG_DIR, "target_configs.json"))
+
+def get_valid_configs(target_name):
+    if target_name in TARGET_CONFIGS:
+        target_config = TARGET_CONFIGS[target_name]
+    elif (target_name in TARGET_MAP and 'LWIP' in TARGET_MAP[target_name].features):
+        target_config = { "default_test_configuration": "ETHERNET", "test_configurations": ["ETHERNET"] }
+    else:
+        return {}
+
+    config_dict = {}
+    for attr in CONFIG_MAP:
+        if attr in target_config['test_configurations']:
+            config_dict[attr] = CONFIG_MAP[attr]
+    return config_dict
+
+def get_config_path(conf_name, target_name):
+    configs = get_valid_configs(target_name)
+    if configs and conf_name.upper() in configs:
+        return join(CONFIG_DIR, configs[conf_name.upper()])
+    else:
+        return None
+
+def get_default_config(target_name):
+    if target_name in TARGET_CONFIGS:
+        config_name = TARGET_CONFIGS[target_name]['default_test_configuration']
+        if config_name == "NONE":
+            return None
+        return join(CONFIG_DIR, CONFIG_MAP[config_name])
+    elif (target_name in TARGET_MAP and 'LWIP' in TARGET_MAP[target_name].features):
+        return join(CONFIG_DIR, CONFIG_MAP["ETHERNET"])
+    else:
+        return None
diff --git a/tools/test_configs/config_paths.json b/tools/test_configs/config_paths.json
new file mode 100644
index 00000000000..098c9442c32
--- /dev/null
+++ b/tools/test_configs/config_paths.json
@@ -0,0 +1,6 @@
+{
+    "ETHERNET" : "EthernetInterface.json",
+    "ODIN_WIFI" : "OdinInterface.json",
+    "ODIN_ETHERNET" : "Odin_EthernetInterface.json",
+    "REALTEK_WIFI" : "RealtekInterface.json"	
+}
diff --git a/tools/test_configs/target_configs.json b/tools/test_configs/target_configs.json
new file mode 100644
index 00000000000..528889622a3
--- /dev/null
+++ b/tools/test_configs/target_configs.json
@@ -0,0 +1,10 @@
+{
+    "UBLOX_EVK_ODIN_W2": {
+        "default_test_configuration": "NONE",
+        "test_configurations": ["ODIN_WIFI", "ODIN_ETHERNET"]
+    },
+    "REALTEK_RTL8195AM": {
+        "default_test_configuration": "NONE",
+        "test_configurations": ["REALTEK_WIFI"]
+    }
+}
diff --git a/tools/toolchains/__init__.py b/tools/toolchains/__init__.py
index 0034d28dcac..0df502303f0 100644
--- a/tools/toolchains/__init__.py
+++ b/tools/toolchains/__init__.py
@@ -26,7 +26,6 @@
 from itertools import chain
 from inspect import getmro
 from copy import deepcopy
-from tools.config import Config
 from abc import ABCMeta, abstractmethod
 from distutils.spawn import find_executable
 
@@ -616,7 +615,8 @@ def add_ignore_patterns(self, root, base_path, patterns):
             self.ignore_patterns.extend(normcase(p) for p in patterns)
         else:
             self.ignore_patterns.extend(normcase(join(real_base, pat)) for pat in patterns)
-        self._ignore_regex = re.compile("|".join(fnmatch.translate(p) for p in self.ignore_patterns))
+        if self.ignore_patterns:
+            self._ignore_regex = re.compile("|".join(fnmatch.translate(p) for p in self.ignore_patterns))
 
     # Create a Resources object from the path pointed to by *path* by either traversing a
     # a directory structure, when *path* is a directory, or adding *path* to the resources,
@@ -1257,7 +1257,7 @@ def get_config_header(self):
         else:
             prev_data = None
         # Get the current configuration data
-        crt_data = Config.config_to_header(self.config_data) if self.config_data else None
+        crt_data = self.config.config_to_header(self.config_data) if self.config_data else None
         # "changed" indicates if a configuration change was detected
         changed = False
         if prev_data is not None: # a previous mbed_config.h exists
@@ -1553,7 +1553,7 @@ def redirect_symbol(source, sync, build_dir):
 
     # Return the list of macros geenrated by the build system
     def get_config_macros(self):
-        return Config.config_to_macros(self.config_data) if self.config_data else []
+        return self.config.config_to_macros(self.config_data) if self.config_data else []
 
     @property
     def report(self):
diff --git a/tools/toolchains/arm.py b/tools/toolchains/arm.py
index f1d954a8b26..4cc46aa0c2b 100644
--- a/tools/toolchains/arm.py
+++ b/tools/toolchains/arm.py
@@ -33,6 +33,8 @@ class ARM(mbedToolchain):
     INDEX_PATTERN  = re.compile('(?P<col>\s*)\^')
     DEP_PATTERN = re.compile('\S+:\s(?P<file>.+)\n')
     SHEBANG = "#! armcc -E"
+    SUPPORTED_CORES = ["Cortex-M0", "Cortex-M0+", "Cortex-M3", "Cortex-M4",
+                       "Cortex-M4F", "Cortex-M7", "Cortex-M7F", "Cortex-M7FD"]
 
     @staticmethod
     def check_executable():
@@ -48,6 +50,9 @@ def __init__(self, target, notify=None, macros=None,
                                build_dir=build_dir,
                                extra_verbose=extra_verbose,
                                build_profile=build_profile)
+        if target.core not in self.SUPPORTED_CORES:
+            raise NotSupportedException(
+                "this compiler does not support the core %s" % target.core)
 
         if target.core == "Cortex-M0+":
             cpu = "Cortex-M0"
@@ -71,7 +76,7 @@ def __init__(self, target, notify=None, macros=None,
         self.cc = [main_cc] + self.flags['common'] + self.flags['c']
         self.cppc = [main_cc] + self.flags['common'] + self.flags['c'] + self.flags['cxx']
 
-        self.ld = [join(ARM_BIN, "armlink")]
+        self.ld = [join(ARM_BIN, "armlink")] + self.flags['ld']
 
         self.ar = join(ARM_BIN, "armar")
         self.elf2bin = join(ARM_BIN, "fromelf")
@@ -262,22 +267,45 @@ def redirect_symbol(source, sync, build_dir):
 
 
 class ARM_STD(ARM):
-    pass
+    def __init__(self, target, notify=None, macros=None,
+                 silent=False, extra_verbose=False, build_profile=None,
+                 build_dir=None):
+        ARM.__init__(self, target, notify, macros, silent,
+                     build_dir=build_dir, extra_verbose=extra_verbose,
+                     build_profile=build_profile)
+        if "ARM" not in target.supported_toolchains:
+            raise NotSupportedException("ARM compiler support is required for ARM build")
+
 
 class ARM_MICRO(ARM):
     PATCHED_LIBRARY = False
+    def __init__(self, target, notify=None, macros=None,
+                 silent=False, extra_verbose=False, build_profile=None,
+                 build_dir=None):
+        ARM.__init__(self, target, notify, macros, silent,
+                     build_dir=build_dir, extra_verbose=extra_verbose,
+                     build_profile=build_profile)
+        if not set(("ARM", "uARM")).intersection(set(target.supported_toolchains)):
+            raise NotSupportedException("ARM/uARM compiler support is required for ARM build")
 
 class ARMC6(ARM_STD):
     SHEBANG = "#! armclang -E --target=arm-arm-none-eabi -x c"
+    SUPPORTED_CORES = ["Cortex-M0", "Cortex-M0+", "Cortex-M3", "Cortex-M4",
+                       "Cortex-M4F", "Cortex-M7", "Cortex-M7F", "Cortex-M7FD",
+                       "Cortex-M23", "Cortex-M23-NS", "Cortex-M33",
+                       "CortexM33-NS"]
     @staticmethod
     def check_executable():
         return mbedToolchain.generic_check_executable("ARMC6", "armclang", 1)
 
     def __init__(self, target, *args, **kwargs):
         mbedToolchain.__init__(self, target, *args, **kwargs)
+        if target.core not in self.SUPPORTED_CORES:
+            raise NotSupportedException(
+                "this compiler does not support the core %s" % target.core)
 
-        if "ARM" not in target.supported_toolchains:
-            raise NotSupportedException("ARM compiler support is required for ARMC6 support")
+        if not set(("ARM", "ARMC6")).intersection(set(target.supported_toolchains)):
+            raise NotSupportedException("ARM/ARMC6 compiler support is required for ARMC6 build")
 
         if target.core.lower().endswith("fd"):
             self.flags['common'].append("-mcpu=%s" % target.core.lower()[:-2])
@@ -285,6 +313,9 @@ def __init__(self, target, *args, **kwargs):
         elif target.core.lower().endswith("f"):
             self.flags['common'].append("-mcpu=%s" % target.core.lower()[:-1])
             self.flags['ld'].append("--cpu=%s" % target.core.lower()[:-1])
+        elif target.core.lower().endswith("ns"):
+            self.flags['common'].append("-mcpu=%s" % target.core.lower()[:-3])
+            self.flags['ld'].append("--cpu=%s" % target.core.lower()[:-3])
         else:
             self.flags['common'].append("-mcpu=%s" % target.core.lower())
             self.flags['ld'].append("--cpu=%s" % target.core.lower())
@@ -298,12 +329,21 @@ def __init__(self, target, *args, **kwargs):
         elif target.core == "Cortex-M7FD":
             self.flags['common'].append("-mfpu=fpv5-d16")
             self.flags['common'].append("-mfloat-abi=softfp")
+        elif target.core.startswith("Cortex-M23"):
+            self.flags['common'].append("-march=armv8-m.base")
+        elif target.core.startswith("Cortex-M33"):
+            self.flags['common'].append("-march=armv8-m.main")
+
+        if target.core == "Cortex-M23" or target.core == "Cortex-M33":
+            self.flags['common'].append("-mcmse")
 
         asm_cpu = {
             "Cortex-M0+": "Cortex-M0",
             "Cortex-M4F": "Cortex-M4.fp",
             "Cortex-M7F": "Cortex-M7.fp.sp",
-            "Cortex-M7FD": "Cortex-M7.fp.dp"}.get(target.core, target.core)
+            "Cortex-M7FD": "Cortex-M7.fp.dp",
+            "Cortex-M23-NS": "Cortex-M23",
+            "Cortex-M33-NS": "Cortex-M33" }.get(target.core, target.core)
 
         self.flags['asm'].append("--cpu=%s" % asm_cpu)
 
diff --git a/tools/toolchains/iar.py b/tools/toolchains/iar.py
index 5d460fc3392..a3e3bc71c86 100644
--- a/tools/toolchains/iar.py
+++ b/tools/toolchains/iar.py
@@ -84,7 +84,7 @@ def __init__(self, target, notify=None, macros=None,
         self.cc += self.flags["common"] + c_flags_cmd + self.flags["c"]
         self.cppc += self.flags["common"] + c_flags_cmd + cxx_flags_cmd + self.flags["cxx"]
         
-        self.ld   = [join(IAR_BIN, "ilinkarm")]
+        self.ld   = [join(IAR_BIN, "ilinkarm")] + self.flags['ld']
         self.ar = join(IAR_BIN, "iarchive")
         self.elf2bin = join(IAR_BIN, "ielftool")
 
@@ -186,7 +186,7 @@ def compile_cpp(self, source, object, includes):
     def link(self, output, objects, libraries, lib_dirs, mem_map):
         # Build linker command
         map_file = splitext(output)[0] + ".map"
-        cmd = self.ld + [ "-o", output, "--map=%s" % map_file] + objects + libraries + self.flags['ld']
+        cmd = self.ld + [ "-o", output, "--map=%s" % map_file] + objects + libraries
 
         if mem_map:
             cmd.extend(["--config", mem_map])